Manuel Caballero / AS3933

3D Low Frequency Wakeup Receiver

AS3933.h@4:10d482ca4eb1, 2018-03-13 (annotated)

Committer:
mcm
Date:
Tue Mar 13 15:08:21 2018 +0000
Revision:
4:10d482ca4eb1
Parent:
3:2de552c4ffbc 
The driver was completed and tested ( NUCLEO-L152RE ), it works as expected.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mcm 1:944583d4b1de 1 /**
mcm 1:944583d4b1de 2 * @brief AS3933.h
mcm 1:944583d4b1de 3 * @details 3D Low Frequency Wakeup Receiver.
mcm 1:944583d4b1de 4 * Header file.
mcm 1:944583d4b1de 5 *
mcm 1:944583d4b1de 6 *
mcm 1:944583d4b1de 7 * @return N/A
mcm 1:944583d4b1de 8 *
mcm 1:944583d4b1de 9 * @author Manuel Caballero
mcm 1:944583d4b1de 10 * @date 7/March/2018
mcm 1:944583d4b1de 11 * @version 7/March/2018 The ORIGIN
mcm 1:944583d4b1de 12 * @pre N/A.
mcm 1:944583d4b1de 13 * @warning N/A
mcm 4:10d482ca4eb1 14 * @pre This code belongs to Nimbus Centre ( http://www.nimbus.cit.ie ).
mcm 1:944583d4b1de 15 */
mcm 1:944583d4b1de 16 #ifndef AS3933_H
mcm 1:944583d4b1de 17 #define AS3933_H
mcm 1:944583d4b1de 18
mcm 1:944583d4b1de 19 #include "mbed.h"
mcm 1:944583d4b1de 20 /**
mcm 1:944583d4b1de 21 Example:
mcm 1:944583d4b1de 22
mcm 4:10d482ca4eb1 23 #include "mbed.h"
mcm 3:2de552c4ffbc 24 #include "AS3933.h"
mcm 3:2de552c4ffbc 25
mcm 4:10d482ca4eb1 26 AS3933 myAS3933 ( PB_5, PB_4, PB_3, PB_8, 1000000 ); // MOSI: PB_5 | MISO: PB_4 | SCLK: PB_3 | CS: PB_8 | FREQ: 1MHz;
mcm 3:2de552c4ffbc 27 Serial pc ( USBTX, USBRX );
mcm 3:2de552c4ffbc 28
mcm 4:10d482ca4eb1 29 DigitalOut myled ( LED1 );
mcm 4:10d482ca4eb1 30 InterruptIn myWAKEpin ( PA_8 );
mcm 4:10d482ca4eb1 31 DigitalIn myDATpin ( PC_7 );
mcm 4:10d482ca4eb1 32 DigitalIn myCLDpin ( PB_9 );
mcm 4:10d482ca4eb1 33
mcm 3:2de552c4ffbc 34
mcm 3:2de552c4ffbc 35 AS3933::AS3933_status_t aux;
mcm 3:2de552c4ffbc 36 AS3933::AS3933_data_t myAS3933Data;
mcm 3:2de552c4ffbc 37 uint32_t myState = 0;
mcm 3:2de552c4ffbc 38
mcm 3:2de552c4ffbc 39
mcm 4:10d482ca4eb1 40 void newData ( void )
mcm 3:2de552c4ffbc 41 {
mcm 3:2de552c4ffbc 42 myState = 1;
mcm 3:2de552c4ffbc 43 }
mcm 3:2de552c4ffbc 44
mcm 3:2de552c4ffbc 45
mcm 3:2de552c4ffbc 46 int main()
mcm 3:2de552c4ffbc 47 {
mcm 4:10d482ca4eb1 48 uint32_t myCounterData = 0;
mcm 4:10d482ca4eb1 49 uint32_t myCounterTimeout = 0;
mcm 4:10d482ca4eb1 50
mcm 4:10d482ca4eb1 51
mcm 3:2de552c4ffbc 52 pc.baud ( 115200 );
mcm 3:2de552c4ffbc 53
mcm 3:2de552c4ffbc 54 myled = 1;
mcm 3:2de552c4ffbc 55 wait(3);
mcm 3:2de552c4ffbc 56 myled = 0;
mcm 3:2de552c4ffbc 57
mcm 3:2de552c4ffbc 58
mcm 4:10d482ca4eb1 59 // AS3933 CONFIGURATION
mcm 3:2de552c4ffbc 60 // Clears the wake state of the chip
mcm 3:2de552c4ffbc 61 aux = myAS3933.AS3933_Send_DirectCommand ( AS3933::CLEAR_WAKE );
mcm 3:2de552c4ffbc 62
mcm 3:2de552c4ffbc 63 // Sets all register in the default mode
mcm 3:2de552c4ffbc 64 aux = myAS3933.AS3933_Send_DirectCommand ( AS3933::PRESET_DEFAULT );
mcm 3:2de552c4ffbc 65
mcm 3:2de552c4ffbc 66 // Update the wakeup pattern ( default value )
mcm 4:10d482ca4eb1 67 myAS3933Data.patt1b = AS3933::TS1_WAKEUP_PATTERN_PATT1B;
mcm 3:2de552c4ffbc 68 myAS3933Data.patt2b = AS3933::TS2_WAKEUP_PATTERN_PATT2B;
mcm 3:2de552c4ffbc 69
mcm 3:2de552c4ffbc 70 aux = myAS3933.AS3933_SetWakeUpPattern ( myAS3933Data );
mcm 3:2de552c4ffbc 71
mcm 4:10d482ca4eb1 72 // Configure All channels in Listening mode
mcm 4:10d482ca4eb1 73 aux = myAS3933.AS3933_SetLowPowerMode ( AS3933::AS3933_CH1_ON_CH2_ON_CH3_ON, AS3933::AS3933_STANDARD_LISTENING_MODE, ( AS3933::AS3933_r4_t_off_value_t )0 );
mcm 4:10d482ca4eb1 74
mcm 4:10d482ca4eb1 75 // Configure Crystal oscillator enabled without output signal displayed on CL_DAT pin
mcm 4:10d482ca4eb1 76 aux = myAS3933.AS3933_SetClockGenerator ( AS3933::EN_XTAL_ENABLED, AS3933::CLOCK_GEN_DIS_DISABLED );
mcm 4:10d482ca4eb1 77
mcm 4:10d482ca4eb1 78 // Configure Antenna dumper disabled
mcm 4:10d482ca4eb1 79 aux = myAS3933.AS3933_SetAntennaDamper ( AS3933::ATT_ON_DISABLED, ( AS3933::AS3933_r4_d_res_value_t )0 );
mcm 4:10d482ca4eb1 80
mcm 4:10d482ca4eb1 81 // Configure Envelop detector time constant = 4096 symbol rate
mcm 4:10d482ca4eb1 82 aux = myAS3933.AS3933_SetEnvelopDetector ( AS3933::FS_ENV_SYMBOL_RATE_4096 );
mcm 4:10d482ca4eb1 83
mcm 4:10d482ca4eb1 84 // Configure Data slicer. Threshold disabled, 2.3ms preamble length
mcm 4:10d482ca4eb1 85 aux = myAS3933.AS3933_SetDataSlicer ( AS3933::ABS_HY_DISABLED, AS3933::FS_SCL_PREAMBLE_LENGTH_2_3 );
mcm 4:10d482ca4eb1 86
mcm 4:10d482ca4eb1 87 // Configure Comparator Hysteresis. Both edges, 40mV
mcm 4:10d482ca4eb1 88 aux = myAS3933.AS3933_SetComparatorHysteresis ( AS3933::HY_POS_HYSTERESIS_BOTH_EDGES, AS3933::HY_20M_COMPARATOR_HYSTERESIS_40MV );
mcm 4:10d482ca4eb1 89
mcm 4:10d482ca4eb1 90 // Configure Gain reduction, No gain reduction at all
mcm 4:10d482ca4eb1 91 aux = myAS3933.AS3933_SetGainReduction ( AS3933::GR_GAIN_REDUCTION_NO_GAIN_REDUCTION );
mcm 4:10d482ca4eb1 92
mcm 4:10d482ca4eb1 93 // Configure Operating frequency range: 95-150 kHz
mcm 4:10d482ca4eb1 94 aux = myAS3933.AS3933_SetOperatingFrequencyRange ( AS3933::BAND_SEL_RANGE_95_150_KHZ );
mcm 4:10d482ca4eb1 95
mcm 4:10d482ca4eb1 96 // Configure Frequency detection tolerance: Tight
mcm 4:10d482ca4eb1 97 aux = myAS3933.AS3933_SetFrequencyDetectionTolerance ( AS3933::AS3933_TOLERANCE_TIGHT );
mcm 4:10d482ca4eb1 98
mcm 4:10d482ca4eb1 99 // Configure Sensitivity boost: Disabled
mcm 4:10d482ca4eb1 100 aux = myAS3933.AS3933_SetGainBoost ( AS3933::G_BOOST_DISABLED );
mcm 4:10d482ca4eb1 101
mcm 4:10d482ca4eb1 102 // Configure AGC: AGC acting only on the first carrier burst is disabled and AGC operating in both direction ( up-down )
mcm 4:10d482ca4eb1 103 aux = myAS3933.AS3933_SetAGC ( AS3933::AGC_TLIM_DISABLED, AS3933::AGC_UD_UP_DOWN_MODE );
mcm 4:10d482ca4eb1 104
mcm 4:10d482ca4eb1 105 // Configure Do mask data before wakeup
mcm 4:10d482ca4eb1 106 aux = myAS3933.AS3933_SetDataMask ( AS3933::DAT_MASK_ENABLED );
mcm 4:10d482ca4eb1 107
mcm 4:10d482ca4eb1 108 // Configure Clock Generator: Crystal oscillator enabled, do NOT clock signal on CL_DAT pin
mcm 4:10d482ca4eb1 109 aux = myAS3933.AS3933_SetClockGenerator ( AS3933::EN_XTAL_ENABLED, AS3933::CLOCK_GEN_DIS_DISABLED );
mcm 4:10d482ca4eb1 110
mcm 4:10d482ca4eb1 111 // Configure Correlator: Enabled, 16 bit pattern and Manchester decoder enabled
mcm 4:10d482ca4eb1 112 aux = myAS3933.AS3933_SetCorrelator ( AS3933::EN_WPAT_ENABLED, AS3933::PATT32_16_BITS, AS3933::T_HBIT_BIT_RATE_12, AS3933::EN_MANCH_ENABLED );
mcm 4:10d482ca4eb1 113
mcm 4:10d482ca4eb1 114 // Configure Automatic Timeout: 50ms
mcm 4:10d482ca4eb1 115 aux = myAS3933.AS3933_SetAutomaticTimeOut ( AS3933::T_OUT_50_MSEC );
mcm 4:10d482ca4eb1 116
mcm 4:10d482ca4eb1 117 // Configure Input capacitor bank: NO capacitance in any channels
mcm 4:10d482ca4eb1 118 aux = myAS3933.AS3933_SetParallelTuningCapacitance ( AS3933::AS3933_CHANNEL_LF1P, AS3933::AS3933_CAPACITANCE_ADDS_NONE );
mcm 4:10d482ca4eb1 119 aux = myAS3933.AS3933_SetParallelTuningCapacitance ( AS3933::AS3933_CHANNEL_LF2P, AS3933::AS3933_CAPACITANCE_ADDS_NONE );
mcm 4:10d482ca4eb1 120 aux = myAS3933.AS3933_SetParallelTuningCapacitance ( AS3933::AS3933_CHANNEL_LF3P, AS3933::AS3933_CAPACITANCE_ADDS_NONE );
mcm 4:10d482ca4eb1 121
mcm 4:10d482ca4eb1 122 // Configure Artificial wakeup: Disabled
mcm 4:10d482ca4eb1 123 aux = myAS3933.AS3933_SetArtificialWakeUp ( AS3933::T_AUTO_NO_ARTIFICIAL_WAKEUP );
mcm 4:10d482ca4eb1 124 // END AS3933 CONFIGURATION
mcm 4:10d482ca4eb1 125
mcm 4:10d482ca4eb1 126
mcm 4:10d482ca4eb1 127 // Read the wakeup pattern
mcm 4:10d482ca4eb1 128 aux = myAS3933.AS3933_GetWakeUpPattern ( &myAS3933Data );
mcm 4:10d482ca4eb1 129 pc.printf( "PATT1B: %x ( 0x96 ) | PATT2B: %x ( 0x69 )\r\n", myAS3933Data.patt1b, myAS3933Data.patt2b );
mcm 4:10d482ca4eb1 130
mcm 4:10d482ca4eb1 131
mcm 4:10d482ca4eb1 132 myWAKEpin.rise( &newData ); // attach the address of the 'newData' function to the rising edge
mcm 3:2de552c4ffbc 133
mcm 3:2de552c4ffbc 134 // Let the callbacks take care of everything
mcm 3:2de552c4ffbc 135 while(1) {
mcm 3:2de552c4ffbc 136 sleep();
mcm 3:2de552c4ffbc 137
mcm 3:2de552c4ffbc 138 myled = 1;
mcm 3:2de552c4ffbc 139
mcm 3:2de552c4ffbc 140 if ( myState == 1 ) {
mcm 4:10d482ca4eb1 141
mcm 4:10d482ca4eb1 142 // Get data ( 8-bits, Manchester ).
mcm 4:10d482ca4eb1 143 // NOTE: Make sure the transmitter is sending data otherwise a little delay will
mcm 4:10d482ca4eb1 144 // be introduced by myCounterTimeout.
mcm 4:10d482ca4eb1 145 //
mcm 4:10d482ca4eb1 146 myAS3933Data.data = 0;
mcm 4:10d482ca4eb1 147
mcm 4:10d482ca4eb1 148 for ( myCounterData = 0; myCounterData < 8; myCounterData++ ) {
mcm 4:10d482ca4eb1 149 // Wait until rising edges on CLD pin or Timeout
mcm 4:10d482ca4eb1 150 myCounterTimeout = 2323;
mcm 4:10d482ca4eb1 151 while ( ( myCLDpin == 0 ) && ( myCounterTimeout > 0 ) ) {
mcm 4:10d482ca4eb1 152 myCounterTimeout--;
mcm 4:10d482ca4eb1 153 }
mcm 4:10d482ca4eb1 154
mcm 4:10d482ca4eb1 155 // Process the data
mcm 4:10d482ca4eb1 156 myAS3933Data.data <<= 1;
mcm 4:10d482ca4eb1 157
mcm 4:10d482ca4eb1 158 if ( myDATpin == 1 ) {
mcm 4:10d482ca4eb1 159 myAS3933Data.data |= 1;
mcm 4:10d482ca4eb1 160 }
mcm 4:10d482ca4eb1 161
mcm 4:10d482ca4eb1 162 // Wait until CLD pin goes low again or Timeout
mcm 4:10d482ca4eb1 163 myCounterTimeout = 2323;
mcm 4:10d482ca4eb1 164 while ( ( myCLDpin == 1 ) && ( myCounterTimeout > 0 ) ) {
mcm 4:10d482ca4eb1 165 myCounterTimeout--;
mcm 4:10d482ca4eb1 166 }
mcm 4:10d482ca4eb1 167 }
mcm 4:10d482ca4eb1 168
mcm 4:10d482ca4eb1 169 // Get RSSIs and send all data through the UART
mcm 4:10d482ca4eb1 170 aux = myAS3933.AS3933_GetRSSI ( &myAS3933Data );
mcm 4:10d482ca4eb1 171 pc.printf( "Data: %x | RSS1: %x | RSSI2: %x | RSSI3: %x\r\n", myAS3933Data.data, myAS3933Data.rssi1, myAS3933Data.rssi2, myAS3933Data.rssi3 );
mcm 3:2de552c4ffbc 172
mcm 3:2de552c4ffbc 173 myState = 0; // Reset the variable
mcm 3:2de552c4ffbc 174 }
mcm 3:2de552c4ffbc 175
mcm 3:2de552c4ffbc 176 myled = 0;
mcm 3:2de552c4ffbc 177 }
mcm 3:2de552c4ffbc 178 }
mcm 1:944583d4b1de 179
mcm 1:944583d4b1de 180 */
mcm 1:944583d4b1de 181
mcm 1:944583d4b1de 182
mcm 1:944583d4b1de 183 /*!
mcm 1:944583d4b1de 184 Library for the AS3933 3D Low Frequency Wakeup Receiver.
mcm 1:944583d4b1de 185 */
mcm 1:944583d4b1de 186 class AS3933
mcm 1:944583d4b1de 187 {
mcm 1:944583d4b1de 188 public:
mcm 1:944583d4b1de 189 /* SPI COMMAND STRUCTURE */
mcm 1:944583d4b1de 190 /**
mcm 1:944583d4b1de 191 * @brief MODE. ( B15:B14 )
mcm 1:944583d4b1de 192 */
mcm 1:944583d4b1de 193 typedef enum {
mcm 1:944583d4b1de 194 AS3933_WRITE = ( 0x00 << 6 ), /*!< WRITE */
mcm 1:944583d4b1de 195 AS3933_READ = ( 0x01 << 6 ), /*!< READ */
mcm 1:944583d4b1de 196 AS3933_DIRECT_COMMAND = ( 0x03 << 6 ) /*!< DIRECT COMMAND */
mcm 1:944583d4b1de 197 } AS3933_spi_command_structure_mode_t;
mcm 1:944583d4b1de 198
mcm 1:944583d4b1de 199
mcm 1:944583d4b1de 200 /**
mcm 1:944583d4b1de 201 * @brief READ/WRITE REGISTER ( B13:B8 )
mcm 1:944583d4b1de 202 */
mcm 1:944583d4b1de 203 typedef enum {
mcm 1:944583d4b1de 204 AS3933_R0 = 0x00, /*!< R0 register */
mcm 1:944583d4b1de 205 AS3933_R1 = 0x01, /*!< R1 register */
mcm 1:944583d4b1de 206 AS3933_R2 = 0x02, /*!< R3 register */
mcm 1:944583d4b1de 207 AS3933_R3 = 0x03, /*!< R4 register */
mcm 1:944583d4b1de 208 AS3933_R4 = 0x04, /*!< R5 register */
mcm 1:944583d4b1de 209 AS3933_R5 = 0x05, /*!< R6 register */
mcm 1:944583d4b1de 210 AS3933_R6 = 0x06, /*!< R7 register */
mcm 1:944583d4b1de 211 AS3933_R7 = 0x07, /*!< R8 register */
mcm 1:944583d4b1de 212 AS3933_R8 = 0x08, /*!< R9 register */
mcm 1:944583d4b1de 213 AS3933_R9 = 0x09, /*!< R10 register */
mcm 1:944583d4b1de 214 AS3933_R10 = 0x0A, /*!< R11 register */
mcm 1:944583d4b1de 215 AS3933_R11 = 0x0B, /*!< R11 register */
mcm 1:944583d4b1de 216 AS3933_R12 = 0x0C, /*!< R12 register */
mcm 1:944583d4b1de 217 AS3933_R13 = 0x0D, /*!< R13 register */
mcm 1:944583d4b1de 218 AS3933_R14 = 0x0E, /*!< R14 register */
mcm 1:944583d4b1de 219 AS3933_R15 = 0x0F, /*!< R15 register */
mcm 1:944583d4b1de 220 AS3933_R16 = 0x10, /*!< R16 register */
mcm 1:944583d4b1de 221 AS3933_R17 = 0x11, /*!< R17 register */
mcm 1:944583d4b1de 222 AS3933_R18 = 0x12, /*!< R18 register */
mcm 1:944583d4b1de 223 AS3933_R19 = 0x13 /*!< R19 register */
mcm 1:944583d4b1de 224 } AS3933_spi_command_structure_registers_t;
mcm 1:944583d4b1de 225
mcm 1:944583d4b1de 226
mcm 1:944583d4b1de 227 /* SPI DIRECT COMMANDS */
mcm 1:944583d4b1de 228 /**
mcm 1:944583d4b1de 229 * @brief DIRECT COMMANDS. ( B13:B8 )
mcm 1:944583d4b1de 230 */
mcm 1:944583d4b1de 231 typedef enum {
mcm 1:944583d4b1de 232 CLEAR_WAKE = 0x00, /*!< Clears the wake state of the chip. In case the chip has woken up ( WAKE pin is high ) the chip is set back to listening mode */
mcm 1:944583d4b1de 233 RESET_RSSI = 0x01, /*!< Resets the RSSI measurement */
mcm 1:944583d4b1de 234 CALIB_RC_OSC = 0x02, /*!< Starts the trimming procedure of the internal RC oscillator */
mcm 1:944583d4b1de 235 CLEAR_FALSE = 0x03, /*!< Resets the false wakeup register ( R13 = 00 ) */
mcm 1:944583d4b1de 236 PRESET_DEFAULT = 0x04, /*!< Sets all register in the default mode */
mcm 1:944583d4b1de 237 CALIB_RCO_LC = 0x05 /*!< Calibration of the RC-oscillator with the external LC tank */
mcm 1:944583d4b1de 238 } AS3933_spi_direct_commands_t;
mcm 1:944583d4b1de 239
mcm 1:944583d4b1de 240
mcm 1:944583d4b1de 241 /* R0 REGISTER. COMMANDS */
mcm 1:944583d4b1de 242 /**
mcm 1:944583d4b1de 243 * @brief PATT32 ( R0<7> ). Pattern extended to 32 bits
mcm 1:944583d4b1de 244 *
mcm 1:944583d4b1de 245 * NOTE: Default value: PATT32_16_BITS
mcm 1:944583d4b1de 246 */
mcm 1:944583d4b1de 247 typedef enum {
mcm 1:944583d4b1de 248 PATT32_MASK = ( 1 << 7 ), /*!< PATT32 mask */
mcm 1:944583d4b1de 249 PATT32_16_BITS = ( 0 << 7 ), /*!< 16-bits pattern extended */
mcm 1:944583d4b1de 250 PATT32_32_BITS = ( 1 << 7 ) /*!< 32-bits pattern extended */
mcm 1:944583d4b1de 251 } AS3933_r0_patt32_value_t;
mcm 1:944583d4b1de 252
mcm 1:944583d4b1de 253
mcm 1:944583d4b1de 254 /**
mcm 1:944583d4b1de 255 * @brief DAT_MASK ( R0<6> ). Masks data on DAT pin before wakeup happens
mcm 1:944583d4b1de 256 *
mcm 1:944583d4b1de 257 * NOTE: Default value: DAT_MASK_DISABLED
mcm 1:944583d4b1de 258 */
mcm 1:944583d4b1de 259 typedef enum {
mcm 1:944583d4b1de 260 DAT_MASK_MASK = ( 1 << 6 ), /*!< DAT_MASK mask */
mcm 1:944583d4b1de 261 DAT_MASK_DISABLED = ( 0 << 6 ), /*!< Data is not masked on DAT pin */
mcm 1:944583d4b1de 262 DAT_MASK_ENABLED = ( 1 << 6 ) /*!< Data is masked on DAT pin */
mcm 1:944583d4b1de 263 } AS3933_r0_dat_mask_value_t;
mcm 1:944583d4b1de 264
mcm 1:944583d4b1de 265
mcm 1:944583d4b1de 266 /**
mcm 1:944583d4b1de 267 * @brief ON_OFF ( R0<5> ). On/Off operation mode. ( Duty-cycle defined in the register R4<7:6> )
mcm 1:944583d4b1de 268 *
mcm 1:944583d4b1de 269 * NOTE: Default value: ON_OFF_DISABLED
mcm 1:944583d4b1de 270 */
mcm 1:944583d4b1de 271 typedef enum {
mcm 1:944583d4b1de 272 ON_OFF_MASK = ( 1 << 5 ), /*!< ON_OFF mask */
mcm 1:944583d4b1de 273 ON_OFF_DISABLED = ( 0 << 5 ), /*!< ON_OFF is disabled */
mcm 1:944583d4b1de 274 ON_OFF_ENABLED = ( 1 << 5 ) /*!< ON_OFF is enabled */
mcm 1:944583d4b1de 275 } AS3933_r0_on_off_value_t;
mcm 1:944583d4b1de 276
mcm 1:944583d4b1de 277
mcm 1:944583d4b1de 278 /**
mcm 1:944583d4b1de 279 * @brief MUX_123 ( R0<4> ). Scan mode enable
mcm 1:944583d4b1de 280 *
mcm 1:944583d4b1de 281 * NOTE: Default value: MUX_123_DISABLED
mcm 1:944583d4b1de 282 */
mcm 1:944583d4b1de 283 typedef enum {
mcm 1:944583d4b1de 284 MUX_123_MASK = ( 1 << 4 ), /*!< MUX_123 mask */
mcm 1:944583d4b1de 285 MUX_123_DISABLED = ( 0 << 4 ), /*!< Scan mode enable is disabled */
mcm 1:944583d4b1de 286 MUX_123_ENABLED = ( 1 << 4 ) /*!< Scan mode enable is enabled */
mcm 1:944583d4b1de 287 } AS3933_r0_mux_123_value_t;
mcm 1:944583d4b1de 288
mcm 1:944583d4b1de 289
mcm 1:944583d4b1de 290 /**
mcm 1:944583d4b1de 291 * @brief EN_A2 ( R0<3> ). Channel 2 enable
mcm 1:944583d4b1de 292 *
mcm 1:944583d4b1de 293 * NOTE: Default value: EN_A2_ENABLED
mcm 1:944583d4b1de 294 */
mcm 1:944583d4b1de 295 typedef enum {
mcm 1:944583d4b1de 296 EN_A2_MASK = ( 1 << 3 ), /*!< EN_A2 mask */
mcm 1:944583d4b1de 297 EN_A2_DISABLED = ( 0 << 3 ), /*!< Channel 2 is disabled */
mcm 1:944583d4b1de 298 EN_A2_ENABLED = ( 1 << 3 ) /*!< Channel 2 is enabled */
mcm 1:944583d4b1de 299 } AS3933_r0_en_a2_value_t;
mcm 1:944583d4b1de 300
mcm 1:944583d4b1de 301
mcm 1:944583d4b1de 302 /**
mcm 1:944583d4b1de 303 * @brief EN_A3 ( R0<2> ). Channel 3 enable
mcm 1:944583d4b1de 304 *
mcm 1:944583d4b1de 305 * NOTE: Default value: EN_A3_ENABLED
mcm 1:944583d4b1de 306 */
mcm 1:944583d4b1de 307 typedef enum {
mcm 1:944583d4b1de 308 EN_A3_MASK = ( 1 << 2 ), /*!< EN_A3 mask */
mcm 1:944583d4b1de 309 EN_A3_DISABLED = ( 0 << 2 ), /*!< Channel 3 is disabled */
mcm 1:944583d4b1de 310 EN_A3_ENABLED = ( 1 << 2 ) /*!< Channel 3 is enabled */
mcm 1:944583d4b1de 311 } AS3933_r0_en_a3_value_t;
mcm 1:944583d4b1de 312
mcm 1:944583d4b1de 313
mcm 1:944583d4b1de 314 /**
mcm 1:944583d4b1de 315 * @brief EN_A1 ( R0<1> ). Channel 1 enable
mcm 1:944583d4b1de 316 *
mcm 1:944583d4b1de 317 * NOTE: Default value: EN_A1_ENABLED
mcm 1:944583d4b1de 318 */
mcm 1:944583d4b1de 319 typedef enum {
mcm 1:944583d4b1de 320 EN_A1_MASK = ( 1 << 1 ), /*!< EN_A1 mask */
mcm 1:944583d4b1de 321 EN_A1_DISABLED = ( 0 << 1 ), /*!< Channel 1 is disabled */
mcm 1:944583d4b1de 322 EN_A1_ENABLED = ( 1 << 1 ) /*!< Channel 1 is enabled */
mcm 1:944583d4b1de 323 } AS3933_r0_en_a1_value_t;
mcm 1:944583d4b1de 324
mcm 1:944583d4b1de 325
mcm 1:944583d4b1de 326 /* R1 REGISTER. COMMANDS */
mcm 1:944583d4b1de 327 /**
mcm 1:944583d4b1de 328 * @brief ABS_HY ( R1<7> ). Enable Data slicer absolute reference
mcm 1:944583d4b1de 329 *
mcm 1:944583d4b1de 330 * NOTE: Default value: ABS_HY_DISABLED
mcm 1:944583d4b1de 331 */
mcm 1:944583d4b1de 332 typedef enum {
mcm 1:944583d4b1de 333 ABS_HY_MASK = ( 1 << 7 ), /*!< ABS_HY mask */
mcm 1:944583d4b1de 334 ABS_HY_DISABLED = ( 0 << 7 ), /*!< Data slicer absolute reference is disabled */
mcm 1:944583d4b1de 335 ABS_HY_ENABLED = ( 1 << 7 ) /*!< Data slicer absolute reference is enabled */
mcm 1:944583d4b1de 336 } AS3933_r1_abs_hy_value_t;
mcm 1:944583d4b1de 337
mcm 1:944583d4b1de 338
mcm 1:944583d4b1de 339 /**
mcm 1:944583d4b1de 340 * @brief AGC_TLIM ( R1<6> ). AGC acting only on the first carrier burst
mcm 1:944583d4b1de 341 *
mcm 1:944583d4b1de 342 * NOTE: Default value: AGC_TLIM_DISABLED
mcm 1:944583d4b1de 343 */
mcm 1:944583d4b1de 344 typedef enum {
mcm 1:944583d4b1de 345 AGC_TLIM_MASK = ( 1 << 6 ), /*!< AGC_TLIM mask */
mcm 1:944583d4b1de 346 AGC_TLIM_DISABLED = ( 0 << 6 ), /*!< AGC is disabled */
mcm 1:944583d4b1de 347 AGC_TLIM_ENABLED = ( 1 << 6 ) /*!< AGC is enabled */
mcm 1:944583d4b1de 348 } AS3933_r1_agc_tlim_value_t;
mcm 1:944583d4b1de 349
mcm 1:944583d4b1de 350
mcm 1:944583d4b1de 351 /**
mcm 1:944583d4b1de 352 * @brief AGC_UD ( R1<5> ). AGC operating in both direction (up-down)
mcm 1:944583d4b1de 353 *
mcm 1:944583d4b1de 354 * NOTE: Default value: AGC_UD_UP_DOWN_MODE
mcm 1:944583d4b1de 355 */
mcm 1:944583d4b1de 356 typedef enum {
mcm 1:944583d4b1de 357 AGC_UD_MASK = ( 1 << 5 ), /*!< AGC_UD mask */
mcm 1:944583d4b1de 358 AGC_UD_DOWN_MODE = ( 0 << 5 ), /*!< AGC down mode only */
mcm 1:944583d4b1de 359 AGC_UD_UP_DOWN_MODE = ( 1 << 5 ) /*!< AGC up and down mode */
mcm 1:944583d4b1de 360 } AS3933_r1_agc_ud_value_t;
mcm 1:944583d4b1de 361
mcm 1:944583d4b1de 362
mcm 1:944583d4b1de 363 /**
mcm 1:944583d4b1de 364 * @brief ATT_ON ( R1<4> ). Antenna damper enable
mcm 1:944583d4b1de 365 *
mcm 1:944583d4b1de 366 * NOTE: Default value: ATT_ON_DISABLED
mcm 1:944583d4b1de 367 */
mcm 1:944583d4b1de 368 typedef enum {
mcm 1:944583d4b1de 369 ATT_ON_MASK = ( 1 << 4 ), /*!< ATT_ON mask */
mcm 1:944583d4b1de 370 ATT_ON_DISABLED = ( 0 << 4 ), /*!< Antenna damper disabled */
mcm 1:944583d4b1de 371 ATT_ON_ENABLED = ( 1 << 4 ) /*!< Antenna damper enabled */
mcm 1:944583d4b1de 372 } AS3933_r1_att_on_value_t;
mcm 1:944583d4b1de 373
mcm 1:944583d4b1de 374
mcm 1:944583d4b1de 375 /**
mcm 1:944583d4b1de 376 * @brief EN_MANCH ( R1<3> ). Manchester decoder enable
mcm 1:944583d4b1de 377 *
mcm 1:944583d4b1de 378 * NOTE: Default value: EN_MANCH_DISABLED
mcm 1:944583d4b1de 379 */
mcm 1:944583d4b1de 380 typedef enum {
mcm 1:944583d4b1de 381 EN_MANCH_MASK = ( 1 << 3 ), /*!< EN_MANCH mask */
mcm 1:944583d4b1de 382 EN_MANCH_DISABLED = ( 0 << 3 ), /*!< Manchester decoder disabled */
mcm 1:944583d4b1de 383 EN_MANCH_ENABLED = ( 1 << 3 ) /*!< Manchester decoder enabled */
mcm 1:944583d4b1de 384 } AS3933_r1_en_manch_value_t;
mcm 1:944583d4b1de 385
mcm 1:944583d4b1de 386
mcm 1:944583d4b1de 387 /**
mcm 1:944583d4b1de 388 * @brief EN_PAT2 ( R1<2> ). Double wakeup pattern correlation
mcm 1:944583d4b1de 389 *
mcm 1:944583d4b1de 390 * NOTE: Default value: EN_PAT2_DISABLED
mcm 1:944583d4b1de 391 */
mcm 1:944583d4b1de 392 typedef enum {
mcm 1:944583d4b1de 393 EN_PAT2_MASK = ( 1 << 2 ), /*!< EN_PAT2 mask */
mcm 1:944583d4b1de 394 EN_PAT2_DISABLED = ( 0 << 2 ), /*!< Double wakeup pattern correlation disabled */
mcm 1:944583d4b1de 395 EN_PAT2_ENABLED = ( 1 << 2 ) /*!< Double wakeup pattern correlation enabled */
mcm 1:944583d4b1de 396 } AS3933_r1_en_pat2_value_t;
mcm 1:944583d4b1de 397
mcm 1:944583d4b1de 398
mcm 1:944583d4b1de 399 /**
mcm 1:944583d4b1de 400 * @brief EN_WPAT ( R1<1> ). Correlator enable
mcm 1:944583d4b1de 401 *
mcm 1:944583d4b1de 402 * NOTE: Default value: EN_WPAT_ENABLED
mcm 1:944583d4b1de 403 */
mcm 1:944583d4b1de 404 typedef enum {
mcm 1:944583d4b1de 405 EN_WPAT_MASK = ( 1 << 1 ), /*!< EN_WPAT mask */
mcm 1:944583d4b1de 406 EN_WPAT_DISABLED = ( 0 << 1 ), /*!< Correlator disabled */
mcm 1:944583d4b1de 407 EN_WPAT_ENABLED = ( 1 << 1 ) /*!< Correlator enabled */
mcm 1:944583d4b1de 408 } AS3933_r1_en_wpat_value_t;
mcm 1:944583d4b1de 409
mcm 1:944583d4b1de 410
mcm 1:944583d4b1de 411 /**
mcm 1:944583d4b1de 412 * @brief EN_XTAL ( R1<0> ). Crystal oscillator enable
mcm 1:944583d4b1de 413 *
mcm 1:944583d4b1de 414 * NOTE: Default value: EN_XTAL_ENABLED
mcm 1:944583d4b1de 415 */
mcm 1:944583d4b1de 416 typedef enum {
mcm 1:944583d4b1de 417 EN_XTAL_MASK = ( 1 << 0 ), /*!< EN_XTAL mask */
mcm 1:944583d4b1de 418 EN_XTAL_DISABLED = ( 0 << 0 ), /*!< Crystal oscillator disabled */
mcm 1:944583d4b1de 419 EN_XTAL_ENABLED = ( 1 << 0 ) /*!< Crystal oscillator enabled */
mcm 1:944583d4b1de 420 } AS3933_r1_en_xtal_value_t;
mcm 1:944583d4b1de 421
mcm 1:944583d4b1de 422
mcm 1:944583d4b1de 423 /* R2 REGISTER. COMMANDS */
mcm 1:944583d4b1de 424 /**
mcm 1:944583d4b1de 425 * @brief S_ABSH ( R2<7> ). Data slicer absolute threshold reduction
mcm 1:944583d4b1de 426 *
mcm 1:944583d4b1de 427 * NOTE: Default value: S_ABSH_DISABLED
mcm 1:944583d4b1de 428 */
mcm 1:944583d4b1de 429 typedef enum {
mcm 1:944583d4b1de 430 S_ABSH_MASK = ( 1 << 7 ), /*!< S_ABSH mask */
mcm 1:944583d4b1de 431 S_ABSH_DISABLED = ( 0 << 7 ), /*!< Data slicer absolute threshold reduction is disabled */
mcm 1:944583d4b1de 432 S_ABSH_ENABLED = ( 1 << 7 ) /*!< Data slicer absolute threshold reduction is enabled */
mcm 1:944583d4b1de 433 } AS3933_r2_s_absh_value_t;
mcm 1:944583d4b1de 434
mcm 1:944583d4b1de 435
mcm 1:944583d4b1de 436 /**
mcm 1:944583d4b1de 437 * @brief EN_EXT_CLK ( R2<6> ). Enables external clock generator
mcm 1:944583d4b1de 438 *
mcm 1:944583d4b1de 439 * NOTE: Default value: EN_EXT_CLK_DISABLED
mcm 1:944583d4b1de 440 */
mcm 1:944583d4b1de 441 typedef enum {
mcm 1:944583d4b1de 442 EN_EXT_CLK_MASK = ( 1 << 6 ), /*!< EN_EXT_CLK mask */
mcm 1:944583d4b1de 443 EN_EXT_CLK_DISABLED = ( 0 << 6 ), /*!< Enables external clock generator is disabled */
mcm 1:944583d4b1de 444 EN_EXT_CLK_ENABLED = ( 1 << 6 ) /*!< Enables external clock generator is enabled */
mcm 1:944583d4b1de 445 } AS3933_r2_en_ext_clk_value_t;
mcm 1:944583d4b1de 446
mcm 1:944583d4b1de 447
mcm 1:944583d4b1de 448 /**
mcm 1:944583d4b1de 449 * @brief G_BOOST ( R2<5> ). +3dB Amplifier Gain Boost
mcm 1:944583d4b1de 450 *
mcm 1:944583d4b1de 451 * NOTE: Default value: G_BOOST_DISABLED
mcm 1:944583d4b1de 452 */
mcm 1:944583d4b1de 453 typedef enum {
mcm 1:944583d4b1de 454 G_BOOST_MASK = ( 1 << 5 ), /*!< G_BOOST mask */
mcm 1:944583d4b1de 455 G_BOOST_DISABLED = ( 0 << 5 ), /*!< Gain Boost is disabled */
mcm 1:944583d4b1de 456 G_BOOST_ENABLED = ( 1 << 5 ) /*!< Gain Boost is enabled */
mcm 1:944583d4b1de 457 } AS3933_r2_g_boost_value_t;
mcm 1:944583d4b1de 458
mcm 1:944583d4b1de 459
mcm 1:944583d4b1de 460 /**
mcm 1:944583d4b1de 461 * @brief S_WU1 ( R2<1:0> ). Tolerance setting for the stage wakeup ( 20 to 150 kHz )
mcm 1:944583d4b1de 462 *
mcm 1:944583d4b1de 463 * NOTE: Default value: S_WU1_20_150_KHZ_TOLERANCE_16_3
mcm 1:944583d4b1de 464 */
mcm 1:944583d4b1de 465 typedef enum {
mcm 1:944583d4b1de 466 S_WU1_20_150_KHZ_MASK = ( 0b11 << 0 ), /*!< S_WU1 mask ( 20 to 150 kHz ) */
mcm 1:944583d4b1de 467 S_WU1_20_150_KHZ_TOLERANCE_16_3 = ( 0b00 << 0 ), /*!< M = 8 +/- 3 */
mcm 1:944583d4b1de 468 S_WU1_20_150_KHZ_TOLERANCE_16_2 = ( 0b01 << 0 ), /*!< M = 8 +/- 2 */
mcm 1:944583d4b1de 469 S_WU1_20_150_KHZ_TOLERANCE_16_1 = ( 0b10 << 0 ) /*!< M = 8 +/- 1 */
mcm 1:944583d4b1de 470 } AS3933_r2_s_wu1_20_150_khz_value_t;
mcm 1:944583d4b1de 471
mcm 1:944583d4b1de 472
mcm 1:944583d4b1de 473
mcm 1:944583d4b1de 474 /**
mcm 1:944583d4b1de 475 * @brief S_WU1 ( R2<1:0> ). Tolerance setting for the stage wakeup ( 15 to 20 kHz )
mcm 1:944583d4b1de 476 *
mcm 1:944583d4b1de 477 * NOTE: Default value: S_WU1_15_20_KHZ_TOLERANCE_8_3
mcm 1:944583d4b1de 478 */
mcm 1:944583d4b1de 479 typedef enum {
mcm 1:944583d4b1de 480 S_WU1_15_20_KHZ_MASK = ( 0b11 << 0 ), /*!< S_WU1 mask ( 15 to 20 kHz ) */
mcm 1:944583d4b1de 481 S_WU1_15_20_KHZ_TOLERANCE_8_3 = ( 0b00 << 0 ), /*!< M = 8 +/- 3 */
mcm 1:944583d4b1de 482 S_WU1_15_20_KHZ_TOLERANCE_8_2 = ( 0b01 << 0 ), /*!< M = 8 +/- 2 */
mcm 1:944583d4b1de 483 S_WU1_15_20_KHZ_TOLERANCE_8_1 = ( 0b10 << 0 ) /*!< M = 8 +/- 1 */
mcm 1:944583d4b1de 484 } AS3933_r2_s_wu1_15_20_khz_value_t;
mcm 1:944583d4b1de 485
mcm 1:944583d4b1de 486
mcm 1:944583d4b1de 487 /* R3 REGISTER. COMMANDS */
mcm 1:944583d4b1de 488 /**
mcm 1:944583d4b1de 489 * @brief HY_20m ( R3<7> ). Data slicer hysteresis
mcm 1:944583d4b1de 490 *
mcm 1:944583d4b1de 491 * NOTE: Default value: HY_20M_COMPARATOR_HYSTERESIS_40MV
mcm 1:944583d4b1de 492 */
mcm 1:944583d4b1de 493 typedef enum {
mcm 1:944583d4b1de 494 HY_20M_MASK = ( 1 << 7 ), /*!< HY_20m mask */
mcm 1:944583d4b1de 495 HY_20M_COMPARATOR_HYSTERESIS_40MV = ( 0 << 7 ), /*!< Comparator hysteresis = 40mV */
mcm 1:944583d4b1de 496 HY_20M_COMPARATOR_HYSTERESIS_20MV = ( 1 << 7 ) /*!< Comparator hysteresis = 20mV */
mcm 1:944583d4b1de 497 } AS3933_r3_hy_20m_value_t;
mcm 1:944583d4b1de 498
mcm 1:944583d4b1de 499
mcm 1:944583d4b1de 500 /**
mcm 1:944583d4b1de 501 * @brief HY_POS ( R3<6> ). Data slicer hysteresis
mcm 1:944583d4b1de 502 *
mcm 1:944583d4b1de 503 * NOTE: Default value: HY_POS_HYSTERESIS_POSITIVE_EDGES
mcm 1:944583d4b1de 504 */
mcm 1:944583d4b1de 505 typedef enum {
mcm 1:944583d4b1de 506 HY_POS_MASK = ( 1 << 6 ), /*!< HY_POS mask */
mcm 1:944583d4b1de 507 HY_POS_HYSTERESIS_POSITIVE_EDGES = ( 0 << 6 ), /*!< Hysteresis only positive edges */
mcm 1:944583d4b1de 508 HY_POS_HYSTERESIS_BOTH_EDGES = ( 1 << 6 ) /*!< Hysteresis positive and negative edges */
mcm 1:944583d4b1de 509 } AS3933_r3_hy_pos_value_t;
mcm 1:944583d4b1de 510
mcm 1:944583d4b1de 511
mcm 1:944583d4b1de 512 /**
mcm 1:944583d4b1de 513 * @brief FS_SCL ( R3<3:5> ). Data slices time constant
mcm 1:944583d4b1de 514 *
mcm 1:944583d4b1de 515 * NOTE: Default value: FS_SCL_PREAMBLE_LENGTH_2_3
mcm 1:944583d4b1de 516 */
mcm 1:944583d4b1de 517 typedef enum {
mcm 1:944583d4b1de 518 FS_SCL_MASK = ( 0b111 << 3 ), /*!< FS_SCL mask */
mcm 1:944583d4b1de 519 FS_SCL_PREAMBLE_LENGTH_0_8 = ( 0b000 << 3 ), /*!< Minimum Preamble Length: 0.8ms */
mcm 1:944583d4b1de 520 FS_SCL_PREAMBLE_LENGTH_1_15 = ( 0b001 << 3 ), /*!< Minimum Preamble Length: 1.15ms */
mcm 1:944583d4b1de 521 FS_SCL_PREAMBLE_LENGTH_1_55 = ( 0b010 << 3 ), /*!< Minimum Preamble Length: 1.55ms */
mcm 1:944583d4b1de 522 FS_SCL_PREAMBLE_LENGTH_1_9 = ( 0b011 << 3 ), /*!< Minimum Preamble Length: 1.9ms */
mcm 1:944583d4b1de 523 FS_SCL_PREAMBLE_LENGTH_2_3 = ( 0b100 << 3 ), /*!< Minimum Preamble Length: 2.3ms */
mcm 1:944583d4b1de 524 FS_SCL_PREAMBLE_LENGTH_2_65 = ( 0b101 << 3 ), /*!< Minimum Preamble Length: 2.65ms */
mcm 1:944583d4b1de 525 FS_SCL_PREAMBLE_LENGTH_3 = ( 0b110 << 3 ), /*!< Minimum Preamble Length: 3ms */
mcm 1:944583d4b1de 526 FS_SCL_PREAMBLE_LENGTH_3_5 = ( 0b111 << 3 ) /*!< Minimum Preamble Length: 3.5ms */
mcm 1:944583d4b1de 527 } AS3933_r3_fs_scl_value_t;
mcm 1:944583d4b1de 528
mcm 1:944583d4b1de 529
mcm 1:944583d4b1de 530 /**
mcm 1:944583d4b1de 531 * @brief FS_ENV ( R3<2:0> ). Envelop detector time constant
mcm 1:944583d4b1de 532 *
mcm 1:944583d4b1de 533 * NOTE: Default value: FS_ENV_SYMBOL_RATE_4096
mcm 1:944583d4b1de 534 */
mcm 1:944583d4b1de 535 typedef enum {
mcm 1:944583d4b1de 536 FS_ENV_MASK = ( 0b111 << 0 ), /*!< FS_ENV mask */
mcm 1:944583d4b1de 537 FS_ENV_SYMBOL_RATE_4096 = ( 0b000 << 0 ), /*!< Symbol Rate [Manchester symbol/s]: 4096 */
mcm 1:944583d4b1de 538 FS_ENV_SYMBOL_RATE_2184 = ( 0b001 << 0 ), /*!< Symbol Rate [Manchester symbol/s]: 2184 */
mcm 1:944583d4b1de 539 FS_ENV_SYMBOL_RATE_1490 = ( 0b010 << 0 ), /*!< Symbol Rate [Manchester symbol/s]: 1490 */
mcm 1:944583d4b1de 540 FS_ENV_SYMBOL_RATE_1130 = ( 0b011 << 0 ), /*!< Symbol Rate [Manchester symbol/s]: 1130 */
mcm 1:944583d4b1de 541 FS_ENV_SYMBOL_RATE_910 = ( 0b100 << 0 ), /*!< Symbol Rate [Manchester symbol/s]: 910 */
mcm 1:944583d4b1de 542 FS_ENV_SYMBOL_RATE_762 = ( 0b101 << 0 ), /*!< Symbol Rate [Manchester symbol/s]: 762 */
mcm 1:944583d4b1de 543 FS_ENV_SYMBOL_RATE_655 = ( 0b110 << 0 ), /*!< Symbol Rate [Manchester symbol/s]: 655 */
mcm 1:944583d4b1de 544 FS_ENV_SYMBOL_RATE_512 = ( 0b111 << 0 ) /*!< Symbol Rate [Manchester symbol/s]: 512 */
mcm 1:944583d4b1de 545 } AS3933_r3_fs_env_value_t;
mcm 1:944583d4b1de 546
mcm 1:944583d4b1de 547
mcm 1:944583d4b1de 548 /* R4 REGISTER. COMMANDS */
mcm 1:944583d4b1de 549 /**
mcm 1:944583d4b1de 550 * @brief T_OFF ( R4<7:6> ). Off time in ON/OFF operation mode
mcm 1:944583d4b1de 551 *
mcm 1:944583d4b1de 552 * NOTE: Default value: T_OFF_1_MS
mcm 1:944583d4b1de 553 */
mcm 1:944583d4b1de 554 typedef enum {
mcm 1:944583d4b1de 555 T_OFF_MASK = ( 0b11 << 6 ), /*!< T_OFF mask */
mcm 1:944583d4b1de 556 T_OFF_1_MS = ( 0b00 << 6 ), /*!< Off time: 1ms */
mcm 1:944583d4b1de 557 T_OFF_2_MS = ( 0b01 << 6 ), /*!< Off time: 2ms */
mcm 1:944583d4b1de 558 T_OFF_4_MS = ( 0b10 << 6 ), /*!< Off time: 4ms */
mcm 1:944583d4b1de 559 T_OFF_8_MS = ( 0b11 << 6 ) /*!< Off time: 8ms */
mcm 1:944583d4b1de 560 } AS3933_r4_t_off_value_t;
mcm 1:944583d4b1de 561
mcm 1:944583d4b1de 562
mcm 1:944583d4b1de 563 /**
mcm 1:944583d4b1de 564 * @brief D_RES ( R4<5:4> ). Antenna damping resistor ( Shunt Resistor ( parallel to the resonator at 125 kHz ) )
mcm 1:944583d4b1de 565 *
mcm 1:944583d4b1de 566 * NOTE: Default value: D_RES_PARALLEL_SHUNT_RESISTOR_3_KOHM
mcm 1:944583d4b1de 567 */
mcm 1:944583d4b1de 568 typedef enum {
mcm 1:944583d4b1de 569 D_RES_MASK = ( 0b11 << 4 ), /*!< D_RES mask */
mcm 1:944583d4b1de 570 D_RES_PARALLEL_SHUNT_RESISTOR_1_KOHM = ( 0b00 << 4 ), /*!< Shunt Resistor: 1kOhm */
mcm 1:944583d4b1de 571 D_RES_PARALLEL_SHUNT_RESISTOR_3_KOHM = ( 0b01 << 4 ), /*!< Shunt Resistor: 3kOhm */
mcm 1:944583d4b1de 572 D_RES_PARALLEL_SHUNT_RESISTOR_9_KOHM = ( 0b10 << 4 ), /*!< Shunt Resistor: 9kOhm */
mcm 1:944583d4b1de 573 D_RES_PARALLEL_SHUNT_RESISTOR_27_KOHM = ( 0b11 << 4 ) /*!< Shunt Resistor: 27kOhm */
mcm 1:944583d4b1de 574 } AS3933_r4_d_res_value_t;
mcm 1:944583d4b1de 575
mcm 1:944583d4b1de 576
mcm 1:944583d4b1de 577 /**
mcm 1:944583d4b1de 578 * @brief GR ( R4<3:0> ). Gain reduction
mcm 1:944583d4b1de 579 *
mcm 1:944583d4b1de 580 * NOTE: Default value: GR_GAIN_REDUCTION_NO_GAIN_REDUCTION
mcm 1:944583d4b1de 581 */
mcm 1:944583d4b1de 582 typedef enum {
mcm 1:944583d4b1de 583 GR_MASK = ( 0b1111 << 0 ), /*!< GR mask */
mcm 1:944583d4b1de 584 GR_GAIN_REDUCTION_NO_GAIN_REDUCTION = ( 0b0000 << 0 ), /*!< No Gain Reduction */
mcm 1:944583d4b1de 585 GR_GAIN_REDUCTION_MINUS_4_DB = ( 0b0100 << 0 ), /*!< Gain Reduction: -4dB */
mcm 1:944583d4b1de 586 GR_GAIN_REDUCTION_MINUS_8_DB = ( 0b0110 << 0 ), /*!< Gain Reduction: -8dB */
mcm 1:944583d4b1de 587 GR_GAIN_REDUCTION_MINUS_12_DB = ( 0b1000 << 0 ), /*!< Gain Reduction: -12dB */
mcm 1:944583d4b1de 588 GR_GAIN_REDUCTION_MINUS_16_DB = ( 0b1010 << 0 ), /*!< Gain Reduction: -16dB */
mcm 1:944583d4b1de 589 GR_GAIN_REDUCTION_MINUS_20_DB = ( 0b1100 << 0 ), /*!< Gain Reduction: -20dB */
mcm 1:944583d4b1de 590 GR_GAIN_REDUCTION_MINUS_24_DB = ( 0b1110 << 0 ) /*!< Gain Reduction: -24dB */
mcm 1:944583d4b1de 591 } AS3933_r4_gr_value_t;
mcm 1:944583d4b1de 592
mcm 1:944583d4b1de 593
mcm 1:944583d4b1de 594 /* R5 REGISTER. COMMANDS */
mcm 1:944583d4b1de 595 /**
mcm 1:944583d4b1de 596 * @brief TS2 ( R5<7:0> ). 2nd Byte of wakeup pattern
mcm 1:944583d4b1de 597 *
mcm 1:944583d4b1de 598 * NOTE: Default value: TS2_WAKEUP_PATTERN_MSB
mcm 1:944583d4b1de 599 */
mcm 1:944583d4b1de 600 typedef enum {
mcm 1:944583d4b1de 601 TS2_PATT2B_MASK = ( 0xFF << 0 ), /*!< TS2 mask */
mcm 1:944583d4b1de 602 TS2_WAKEUP_PATTERN_PATT2B = ( 0b01101001 << 0 ) /*!< Default value */
mcm 1:944583d4b1de 603 } AS3933_r5_ts2_value_t;
mcm 1:944583d4b1de 604
mcm 1:944583d4b1de 605
mcm 1:944583d4b1de 606 /* R6 REGISTER. COMMANDS */
mcm 1:944583d4b1de 607 /**
mcm 1:944583d4b1de 608 * @brief TS1 ( R6<7:0> ). 1st Byte of wakeup pattern
mcm 1:944583d4b1de 609 *
mcm 1:944583d4b1de 610 * NOTE: Default value: TS1_WAKEUP_PATTERN_LSB
mcm 1:944583d4b1de 611 */
mcm 1:944583d4b1de 612 typedef enum {
mcm 1:944583d4b1de 613 TS1_PATT1B_MASK = ( 0xFF << 0 ), /*!< TS1 mask */
mcm 1:944583d4b1de 614 TS1_WAKEUP_PATTERN_PATT1B = ( 0b10010110 << 0 ) /*!< Default value */
mcm 1:944583d4b1de 615 } AS3933_r6_ts2_value_t;
mcm 1:944583d4b1de 616
mcm 1:944583d4b1de 617
mcm 1:944583d4b1de 618 /* R7 REGISTER. COMMANDS */
mcm 1:944583d4b1de 619 /**
mcm 1:944583d4b1de 620 * @brief T_OUT ( R7<7:5> ). Automatic time-out
mcm 1:944583d4b1de 621 *
mcm 1:944583d4b1de 622 * NOTE: Default value: T_OUT_0_SEC
mcm 1:944583d4b1de 623 */
mcm 1:944583d4b1de 624 typedef enum {
mcm 1:944583d4b1de 625 T_OUT_MASK = ( 0b111 << 5 ), /*!< T_OUT mask */
mcm 1:944583d4b1de 626 T_OUT_0_SEC = ( 0b000 << 5 ), /*!< Timeout: 0sec */
mcm 1:944583d4b1de 627 T_OUT_50_MSEC = ( 0b001 << 5 ), /*!< Timeout: 50msec */
mcm 1:944583d4b1de 628 T_OUT_100_MSEC = ( 0b010 << 5 ), /*!< Timeout: 100mecs */
mcm 1:944583d4b1de 629 T_OUT_150_MSEC = ( 0b011 << 5 ), /*!< Timeout: 150msec */
mcm 1:944583d4b1de 630 T_OUT_200_MSEC = ( 0b100 << 5 ), /*!< Timeout: 200msec */
mcm 1:944583d4b1de 631 T_OUT_250_MSEC = ( 0b101 << 5 ), /*!< Timeout: 250msec */
mcm 1:944583d4b1de 632 T_OUT_300_MSEC = ( 0b110 << 5 ), /*!< Timeout: 300msec */
mcm 1:944583d4b1de 633 T_OUT_350_MSEC = ( 0b111 << 5 ) /*!< Timeout: 350msec */
mcm 1:944583d4b1de 634 } AS3933_r7_t_out_value_t;
mcm 1:944583d4b1de 635
mcm 1:944583d4b1de 636
mcm 1:944583d4b1de 637 /**
mcm 1:944583d4b1de 638 * @brief T_HBIT ( R7<4:0> ). Bit rate definition
mcm 1:944583d4b1de 639 *
mcm 1:944583d4b1de 640 * NOTE: Default value: T_HBIT_BIT_RATE_12
mcm 1:944583d4b1de 641 */
mcm 1:944583d4b1de 642 typedef enum {
mcm 1:944583d4b1de 643 T_HBIT_MASK = ( 0b11111 << 0 ), /*!< T_HBIT mask */
mcm 1:944583d4b1de 644 T_HBIT_BIT_RATE_4 = ( 0b00011 << 0 ), /*!< Bit Duration in Clock Generator Periods: 4 */
mcm 1:944583d4b1de 645 T_HBIT_BIT_RATE_5 = ( 0b00100 << 0 ), /*!< Bit Duration in Clock Generator Periods: 5 */
mcm 1:944583d4b1de 646 T_HBIT_BIT_RATE_6 = ( 0b00101 << 0 ), /*!< Bit Duration in Clock Generator Periods: 6 */
mcm 1:944583d4b1de 647 T_HBIT_BIT_RATE_7 = ( 0b00110 << 0 ), /*!< Bit Duration in Clock Generator Periods: 7 */
mcm 1:944583d4b1de 648 T_HBIT_BIT_RATE_8 = ( 0b00111 << 0 ), /*!< Bit Duration in Clock Generator Periods: 8 */
mcm 1:944583d4b1de 649 T_HBIT_BIT_RATE_9 = ( 0b01000 << 0 ), /*!< Bit Duration in Clock Generator Periods: 9 */
mcm 1:944583d4b1de 650 T_HBIT_BIT_RATE_10 = ( 0b01001 << 0 ), /*!< Bit Duration in Clock Generator Periods: 10 */
mcm 1:944583d4b1de 651 T_HBIT_BIT_RATE_11 = ( 0b01010 << 0 ), /*!< Bit Duration in Clock Generator Periods: 11 */
mcm 1:944583d4b1de 652 T_HBIT_BIT_RATE_12 = ( 0b01011 << 0 ), /*!< Bit Duration in Clock Generator Periods: 12 */
mcm 1:944583d4b1de 653 T_HBIT_BIT_RATE_13 = ( 0b01100 << 0 ), /*!< Bit Duration in Clock Generator Periods: 13 */
mcm 1:944583d4b1de 654 T_HBIT_BIT_RATE_14 = ( 0b01101 << 0 ), /*!< Bit Duration in Clock Generator Periods: 14 */
mcm 1:944583d4b1de 655 T_HBIT_BIT_RATE_15 = ( 0b01110 << 0 ), /*!< Bit Duration in Clock Generator Periods: 15 */
mcm 1:944583d4b1de 656 T_HBIT_BIT_RATE_16 = ( 0b01111 << 0 ), /*!< Bit Duration in Clock Generator Periods: 16 */
mcm 1:944583d4b1de 657 T_HBIT_BIT_RATE_17 = ( 0b10000 << 0 ), /*!< Bit Duration in Clock Generator Periods: 17 */
mcm 1:944583d4b1de 658 T_HBIT_BIT_RATE_18 = ( 0b10001 << 0 ), /*!< Bit Duration in Clock Generator Periods: 18 */
mcm 1:944583d4b1de 659 T_HBIT_BIT_RATE_19 = ( 0b10010 << 0 ), /*!< Bit Duration in Clock Generator Periods: 19 */
mcm 1:944583d4b1de 660 T_HBIT_BIT_RATE_20 = ( 0b10011 << 0 ), /*!< Bit Duration in Clock Generator Periods: 20 */
mcm 1:944583d4b1de 661 T_HBIT_BIT_RATE_21 = ( 0b10100 << 0 ), /*!< Bit Duration in Clock Generator Periods: 21 */
mcm 1:944583d4b1de 662 T_HBIT_BIT_RATE_22 = ( 0b10101 << 0 ), /*!< Bit Duration in Clock Generator Periods: 22 */
mcm 1:944583d4b1de 663 T_HBIT_BIT_RATE_23 = ( 0b10110 << 0 ), /*!< Bit Duration in Clock Generator Periods: 23 */
mcm 1:944583d4b1de 664 T_HBIT_BIT_RATE_24 = ( 0b10111 << 0 ), /*!< Bit Duration in Clock Generator Periods: 24 */
mcm 1:944583d4b1de 665 T_HBIT_BIT_RATE_25 = ( 0b11000 << 0 ), /*!< Bit Duration in Clock Generator Periods: 25 */
mcm 1:944583d4b1de 666 T_HBIT_BIT_RATE_26 = ( 0b11001 << 0 ), /*!< Bit Duration in Clock Generator Periods: 26 */
mcm 1:944583d4b1de 667 T_HBIT_BIT_RATE_27 = ( 0b11010 << 0 ), /*!< Bit Duration in Clock Generator Periods: 27 */
mcm 1:944583d4b1de 668 T_HBIT_BIT_RATE_28 = ( 0b11011 << 0 ), /*!< Bit Duration in Clock Generator Periods: 28 */
mcm 1:944583d4b1de 669 T_HBIT_BIT_RATE_29 = ( 0b11100 << 0 ), /*!< Bit Duration in Clock Generator Periods: 29 */
mcm 1:944583d4b1de 670 T_HBIT_BIT_RATE_30 = ( 0b11101 << 0 ), /*!< Bit Duration in Clock Generator Periods: 30 */
mcm 1:944583d4b1de 671 T_HBIT_BIT_RATE_31 = ( 0b11110 << 0 ), /*!< Bit Duration in Clock Generator Periods: 31 */
mcm 1:944583d4b1de 672 T_HBIT_BIT_RATE_32 = ( 0b11111 << 0 ) /*!< Bit Duration in Clock Generator Periods: 32 */
mcm 1:944583d4b1de 673 } AS3933_r7_t_hbit_value_t;
mcm 1:944583d4b1de 674
mcm 1:944583d4b1de 675
mcm 1:944583d4b1de 676 /* R8 REGISTER. COMMANDS */
mcm 1:944583d4b1de 677 /**
mcm 1:944583d4b1de 678 * @brief BAND_SEL ( R8<7:5> ). Band selection
mcm 1:944583d4b1de 679 *
mcm 1:944583d4b1de 680 * NOTE: Default value: BAND_SEL_RANGE_95_150_KHZ
mcm 1:944583d4b1de 681 */
mcm 1:944583d4b1de 682 typedef enum {
mcm 1:944583d4b1de 683 BAND_SEL_MASK = ( 0b111 << 5 ), /*!< BAND_SEL mask */
mcm 1:944583d4b1de 684 BAND_SEL_RANGE_95_150_KHZ = ( 0b000 << 5 ), /*!< N = 4, Operating Frequency Range [kHz]: 95-150 */
mcm 1:944583d4b1de 685 BAND_SEL_RANGE_65_95_KHZ = ( 0b000 << 5 ), /*!< N = 6, Operating Frequency Range [kHz]: 65-95 */
mcm 1:944583d4b1de 686 BAND_SEL_RANGE_40_65_KHZ = ( 0b000 << 5 ), /*!< N = 10, Operating Frequency Range [kHz]: 40-65 */
mcm 1:944583d4b1de 687 BAND_SEL_RANGE_23_40_KHZ = ( 0b000 << 5 ), /*!< N = 18, Operating Frequency Range [kHz]: 23-40 */
mcm 1:944583d4b1de 688 BAND_SEL_RANGE_15_23_KHZ = ( 0b000 << 5 ) /*!< N = 14, Operating Frequency Range [kHz]: 15-23 */
mcm 1:944583d4b1de 689 } AS3933_r8_band_sel_value_t;
mcm 1:944583d4b1de 690
mcm 1:944583d4b1de 691
mcm 1:944583d4b1de 692 /**
mcm 1:944583d4b1de 693 * @brief T_AUTO ( R8<2:0> ). Artificial wake-up
mcm 1:944583d4b1de 694 *
mcm 1:944583d4b1de 695 * NOTE: Default value: T_AUTO_NO_ARTIFICIAL_WAKEUP
mcm 1:944583d4b1de 696 */
mcm 1:944583d4b1de 697 typedef enum {
mcm 1:944583d4b1de 698 T_AUTO_MASK = ( 0b111 << 0 ), /*!< T_AUTO mask */
mcm 1:944583d4b1de 699 T_AUTO_NO_ARTIFICIAL_WAKEUP = ( 0b000 << 0 ), /*!< No artificial wake-up */
mcm 1:944583d4b1de 700 T_AUTO_ARTIFICIAL_WAKEUP_1_SEC = ( 0b001 << 0 ), /*!< Artificial wake-up 1sec */
mcm 1:944583d4b1de 701 T_AUTO_ARTIFICIAL_WAKEUP_5_SEC = ( 0b010 << 0 ), /*!< Artificial wake-up 5sec */
mcm 1:944583d4b1de 702 T_AUTO_ARTIFICIAL_WAKEUP_20_SEC = ( 0b011 << 0 ), /*!< Artificial wake-up 20sec */
mcm 1:944583d4b1de 703 T_AUTO_ARTIFICIAL_WAKEUP_2_MIN = ( 0b100 << 0 ), /*!< Artificial wake-up 2min */
mcm 1:944583d4b1de 704 T_AUTO_ARTIFICIAL_WAKEUP_15_MIN = ( 0b101 << 0 ), /*!< Artificial wake-up 15min */
mcm 1:944583d4b1de 705 T_AUTO_ARTIFICIAL_WAKEUP_1_HOUR = ( 0b110 << 0 ), /*!< Artificial wake-up 1hour */
mcm 1:944583d4b1de 706 T_AUTO_ARTIFICIAL_WAKEUP_2_HOUR = ( 0b111 << 0 ), /*!< Artificial wake-up 2hour */
mcm 1:944583d4b1de 707 } AS3933_r8_t_auto_value_t;
mcm 1:944583d4b1de 708
mcm 1:944583d4b1de 709
mcm 1:944583d4b1de 710 /* R9 REGISTER. COMMANDS */
mcm 1:944583d4b1de 711 /**
mcm 1:944583d4b1de 712 * @brief BLOCK_AGC ( R9<7> ). Disables AGC
mcm 1:944583d4b1de 713 *
mcm 1:944583d4b1de 714 * NOTE: Default value: BLOCK_AGC_ENABLED
mcm 1:944583d4b1de 715 */
mcm 1:944583d4b1de 716 typedef enum {
mcm 1:944583d4b1de 717 BLOCK_AGC_MASK = ( 1 << 7 ), /*!< BLOCK_AGC mask */
mcm 1:944583d4b1de 718 BLOCK_AGC_DISABLED = ( 1 << 7 ), /*!< AGC is disabled */
mcm 1:944583d4b1de 719 BLOCK_AGC_ENABLED = ( 0 << 7 ) /*!< AGC is enabled */
mcm 1:944583d4b1de 720 } AS3933_r9_block_agc_value_t;
mcm 1:944583d4b1de 721
mcm 1:944583d4b1de 722
mcm 1:944583d4b1de 723
mcm 1:944583d4b1de 724 /* R10 REGISTER. COMMANDS */
mcm 1:944583d4b1de 725 /**
mcm 1:944583d4b1de 726 * @brief RSSI1 ( R10<4:0> ). RSSI channel 1
mcm 1:944583d4b1de 727 *
mcm 1:944583d4b1de 728 */
mcm 1:944583d4b1de 729 typedef enum {
mcm 1:944583d4b1de 730 RSSI1_MASK = ( 0b11111 << 0 ) /*!< RSSI1 mask */
mcm 1:944583d4b1de 731 } AS3933_r10_rssi1_value_t;
mcm 1:944583d4b1de 732
mcm 1:944583d4b1de 733
mcm 1:944583d4b1de 734 /* R11 REGISTER. COMMANDS */
mcm 1:944583d4b1de 735 /**
mcm 1:944583d4b1de 736 * @brief RSSI3 ( R11<4:0> ). RSSI channel 3
mcm 1:944583d4b1de 737 *
mcm 1:944583d4b1de 738 */
mcm 1:944583d4b1de 739 typedef enum {
mcm 1:944583d4b1de 740 RSSI3_MASK = ( 0b11111 << 0 ) /*!< RSSI3 mask */
mcm 1:944583d4b1de 741 } AS3933_r11_rssi3_value_t;
mcm 1:944583d4b1de 742
mcm 1:944583d4b1de 743
mcm 1:944583d4b1de 744 /* R12 REGISTER. COMMANDS */
mcm 1:944583d4b1de 745 /**
mcm 1:944583d4b1de 746 * @brief RSSI2 ( R11<4:0> ). RSSI channel 2
mcm 1:944583d4b1de 747 *
mcm 1:944583d4b1de 748 */
mcm 1:944583d4b1de 749 typedef enum {
mcm 1:944583d4b1de 750 RSSI2_MASK = ( 0b11111 << 0 ) /*!< RSSI2 mask */
mcm 1:944583d4b1de 751 } AS3933_r11_rssi2_value_t;
mcm 1:944583d4b1de 752
mcm 1:944583d4b1de 753
mcm 1:944583d4b1de 754 /* R14 REGISTER. COMMANDS */
mcm 1:944583d4b1de 755 /**
mcm 1:944583d4b1de 756 * @brief RC_CAL_KO ( R14<7> ). Unsuccessful RC calibration
mcm 1:944583d4b1de 757 *
mcm 1:944583d4b1de 758 */
mcm 1:944583d4b1de 759 typedef enum {
mcm 1:944583d4b1de 760 RC_CAL_KO_MASK = ( 1 << 7 ), /*!< RC_CAL_KO mask */
mcm 1:944583d4b1de 761 RC_CAL_KO_HIGH = ( 1 << 7 ), /*!< RC_CAL_KO Unsuccessful RC calibration */
mcm 1:944583d4b1de 762 RC_CAL_KO_LOW = ( 0 << 7 ) /*!< RC_CAL_KO Reset state */
mcm 1:944583d4b1de 763 } AS3933_r14_rc_cal_ko_value_t;
mcm 1:944583d4b1de 764
mcm 1:944583d4b1de 765
mcm 1:944583d4b1de 766 /**
mcm 1:944583d4b1de 767 * @brief RC_CAL_OK ( R14<6> ). Successful RC calibration
mcm 1:944583d4b1de 768 *
mcm 1:944583d4b1de 769 */
mcm 1:944583d4b1de 770 typedef enum {
mcm 1:944583d4b1de 771 RC_CAL_OK_MASK = ( 1 << 6 ), /*!< RC_CAL_OK mask */
mcm 1:944583d4b1de 772 RC_CAL_OK_HIGH = ( 1 << 6 ), /*!< RC_CAL_OK Successful RC calibration */
mcm 1:944583d4b1de 773 RC_CAL_OK_LOW = ( 0 << 6 ) /*!< RC_CAL_OK Reset state */
mcm 1:944583d4b1de 774 } AS3933_r14_rc_cal_ok_value_t;
mcm 1:944583d4b1de 775
mcm 1:944583d4b1de 776
mcm 1:944583d4b1de 777 /**
mcm 1:944583d4b1de 778 * @brief RC_OSC_TAPS ( R14<5:0> ). RC-Oscillator taps setting
mcm 1:944583d4b1de 779 *
mcm 1:944583d4b1de 780 */
mcm 1:944583d4b1de 781 typedef enum {
mcm 1:944583d4b1de 782 RC_OSC_TAPS_MASK = ( 0b111111 << 0 ) /*!< RC_OSC_TAPS mask */
mcm 1:944583d4b1de 783 } AS3933_r14_rc_osc_taps_value_t;
mcm 1:944583d4b1de 784
mcm 1:944583d4b1de 785
mcm 1:944583d4b1de 786 /* R15 REGISTER. COMMANDS */
mcm 1:944583d4b1de 787 /**
mcm 1:944583d4b1de 788 * @brief LC_OSC_KO ( R15<7> ). LC-Oscillator not working
mcm 1:944583d4b1de 789 *
mcm 1:944583d4b1de 790 */
mcm 1:944583d4b1de 791 typedef enum {
mcm 1:944583d4b1de 792 LC_OSC_KO_MASK = ( 1 << 7 ), /*!< LC_OSC_KO mask */
mcm 1:944583d4b1de 793 LC_OSC_KO_HIGH = ( 1 << 7 ), /*!< LC-Oscillator not working */
mcm 1:944583d4b1de 794 LC_OSC_KO_LOW = ( 0 << 7 ) /*!< LC_OSC_KO Reset state */
mcm 1:944583d4b1de 795 } AS3933_r15_lc_osc_ko_value_t;
mcm 1:944583d4b1de 796
mcm 1:944583d4b1de 797
mcm 1:944583d4b1de 798 /**
mcm 1:944583d4b1de 799 * @brief LC_OSC_OK ( R15<6> ). LC-Oscillator working
mcm 1:944583d4b1de 800 *
mcm 1:944583d4b1de 801 */
mcm 1:944583d4b1de 802 typedef enum {
mcm 1:944583d4b1de 803 LC_OSC_OK_MASK = ( 1 << 6 ), /*!< LC_OSC_OK mask */
mcm 1:944583d4b1de 804 LC_OSC_OK_HIGH = ( 1 << 6 ), /*!< LC_OSC_OK LC-Oscillator working */
mcm 1:944583d4b1de 805 LC_OSC_OK_LOW = ( 0 << 6 ) /*!< LC_OSC_OK Reset state */
mcm 1:944583d4b1de 806 } AS3933_r15_lc_osc_ok_value_t;
mcm 1:944583d4b1de 807
mcm 1:944583d4b1de 808
mcm 1:944583d4b1de 809 /* R16 REGISTER. COMMANDS */
mcm 1:944583d4b1de 810 /**
mcm 1:944583d4b1de 811 * @brief CLOCK_GEN_DIS ( R16<7> ). The Clock Generator output signal displayed on CL_DAT pin
mcm 1:944583d4b1de 812 *
mcm 1:944583d4b1de 813 * NOTE: Default value: CLOCK_GEN_DIS_DISABLED
mcm 1:944583d4b1de 814 */
mcm 1:944583d4b1de 815 typedef enum {
mcm 1:944583d4b1de 816 CLOCK_GEN_DIS_MASK = ( 1 << 7 ), /*!< CLOCK_GEN_DIS mask */
mcm 1:944583d4b1de 817 CLOCK_GEN_DIS_ENABLED = ( 1 << 7 ), /*!< CLOCK on CL_DAT pin */
mcm 1:944583d4b1de 818 CLOCK_GEN_DIS_DISABLED = ( 0 << 7 ) /*!< NO CLOCK on CL_DAT pin */
mcm 1:944583d4b1de 819 } AS3933_r16_clock_gen_dis_value_t;
mcm 1:944583d4b1de 820
mcm 1:944583d4b1de 821
mcm 1:944583d4b1de 822 /**
mcm 1:944583d4b1de 823 * @brief LC_OSC_DIS ( R16<6> ). The LC-oscillator output signal displayed on DAT pin
mcm 1:944583d4b1de 824 *
mcm 1:944583d4b1de 825 * NOTE: Default value: LC_OSC_DIS_DISABLED
mcm 1:944583d4b1de 826 */
mcm 1:944583d4b1de 827 typedef enum {
mcm 1:944583d4b1de 828 LC_OSC_DIS_MASK = ( 1 << 6 ), /*!< LC_OSC_DIS mask */
mcm 1:944583d4b1de 829 LC_OSC_DIS_ENABLED = ( 1 << 6 ), /*!< LC-CLOCK on CL_DAT pin */
mcm 1:944583d4b1de 830 LC_OSC_DIS_DISABLED = ( 0 << 6 ) /*!< NO LC-CLOCK on CL_DAT pin */
mcm 1:944583d4b1de 831 } AS3933_r16_lc_osc_dis_value_t;
mcm 1:944583d4b1de 832
mcm 1:944583d4b1de 833
mcm 1:944583d4b1de 834
mcm 1:944583d4b1de 835 /**
mcm 1:944583d4b1de 836 * @brief RC_OSC_MIN ( R16<5> ). Sets the RC-oscillator to minimum frequency
mcm 1:944583d4b1de 837 *
mcm 1:944583d4b1de 838 * NOTE: Default value: RC_OSC_MIN_DISABLED
mcm 1:944583d4b1de 839 */
mcm 1:944583d4b1de 840 typedef enum {
mcm 1:944583d4b1de 841 RC_OSC_MIN_MASK = ( 1 << 5 ), /*!< RC_OSC_MIN mask */
mcm 1:944583d4b1de 842 RC_OSC_MIN_ENABLED = ( 1 << 5 ), /*!< RC-oscillator to minimum frequency enabled */
mcm 1:944583d4b1de 843 RC_OSC_MIN_DISABLED = ( 0 << 5 ) /*!< RC-oscillator to minimum frequency disabled */
mcm 1:944583d4b1de 844 } AS3933_r16_rc_osc_min_value_t;
mcm 1:944583d4b1de 845
mcm 1:944583d4b1de 846
mcm 1:944583d4b1de 847 /**
mcm 1:944583d4b1de 848 * @brief RC_OSC_MIN ( R16<4> ). Sets the RC-oscillator to maximum frequency
mcm 1:944583d4b1de 849 *
mcm 1:944583d4b1de 850 * NOTE: Default value: RC_OSC_MAX_DISABLED
mcm 1:944583d4b1de 851 */
mcm 1:944583d4b1de 852 typedef enum {
mcm 1:944583d4b1de 853 RC_OSC_MAX_MASK = ( 1 << 4 ), /*!< RC_OSC_MAX mask */
mcm 1:944583d4b1de 854 RC_OSC_MAX_ENABLED = ( 1 << 4 ), /*!< RC-oscillator to maximum frequency enabled */
mcm 1:944583d4b1de 855 RC_OSC_MAX_DISABLED = ( 0 << 4 ) /*!< RC-oscillator to maximum frequency disabled */
mcm 1:944583d4b1de 856 } AS3933_r16_rc_osc_max_value_t;
mcm 1:944583d4b1de 857
mcm 1:944583d4b1de 858
mcm 1:944583d4b1de 859 /**
mcm 1:944583d4b1de 860 * @brief LC_OSC_MUX3 ( R16<2> ). Connects LF3P to the LCO
mcm 1:944583d4b1de 861 *
mcm 1:944583d4b1de 862 * NOTE: Default value: LC_OSC_MUX3_LF3P_AND_LCO_DISCONNECTED
mcm 1:944583d4b1de 863 */
mcm 1:944583d4b1de 864 typedef enum {
mcm 1:944583d4b1de 865 LC_OSC_MUX3_MASK = ( 1 << 2 ), /*!< LC_OSC_MUX3 mask */
mcm 1:944583d4b1de 866 LC_OSC_MUX3_LF3P_AND_LCO_CONNECTED = ( 1 << 2 ), /*!< LF3P and LCO connected */
mcm 1:944583d4b1de 867 LC_OSC_MUX3_LF3P_AND_LCO_DISCONNECTED = ( 0 << 2 ) /*!< LF3P and LCO disconnected */
mcm 1:944583d4b1de 868 } AS3933_r16_lc_osc_mux3_value_t;
mcm 1:944583d4b1de 869
mcm 1:944583d4b1de 870
mcm 1:944583d4b1de 871 /**
mcm 1:944583d4b1de 872 * @brief LC_OSC_MUX2 ( R16<1> ). Connects LF2P to the LCO
mcm 1:944583d4b1de 873 *
mcm 1:944583d4b1de 874 * NOTE: Default value: LC_OSC_MUX2_LF2P_AND_LCO_DISCONNECTED
mcm 1:944583d4b1de 875 */
mcm 1:944583d4b1de 876 typedef enum {
mcm 1:944583d4b1de 877 LC_OSC_MUX2_MASK = ( 1 << 1 ), /*!< LC_OSC_MUX2 mask */
mcm 1:944583d4b1de 878 LC_OSC_MUX2_LF2P_AND_LCO_CONNECTED = ( 1 << 1 ), /*!< LF2P and LCO connected */
mcm 1:944583d4b1de 879 LC_OSC_MUX2_LF2P_AND_LCO_DISCONNECTED = ( 0 << 1 ) /*!< LF2P and LCO disconnected */
mcm 1:944583d4b1de 880 } AS3933_r16_lc_osc_mux2_value_t;
mcm 1:944583d4b1de 881
mcm 1:944583d4b1de 882
mcm 1:944583d4b1de 883 /**
mcm 1:944583d4b1de 884 * @brief LC_OSC_MUX1 ( R16<0> ). Connects LF1P to the LCO
mcm 1:944583d4b1de 885 *
mcm 1:944583d4b1de 886 * NOTE: Default value: LC_OSC_MUX1_LF1P_AND_LCO_DISCONNECTED
mcm 1:944583d4b1de 887 */
mcm 1:944583d4b1de 888 typedef enum {
mcm 1:944583d4b1de 889 LC_OSC_MUX1_MASK = ( 1 << 0 ), /*!< LC_OSC_MUX1 mask */
mcm 1:944583d4b1de 890 LC_OSC_MUX1_LF1P_AND_LCO_CONNECTED = ( 1 << 0 ), /*!< LF1P and LCO connected */
mcm 1:944583d4b1de 891 LC_OSC_MUX1_LF1P_AND_LCO_DISCONNECTED = ( 0 << 0 ) /*!< LF1P and LCO disconnected */
mcm 1:944583d4b1de 892 } AS3933_r16_lc_osc_mux1_value_t;
mcm 1:944583d4b1de 893
mcm 1:944583d4b1de 894
mcm 1:944583d4b1de 895
mcm 1:944583d4b1de 896 /* R17 REGISTER. COMMANDS */
mcm 1:944583d4b1de 897 /**
mcm 1:944583d4b1de 898 * @brief CAPS_CH1 ( R17<4:0> ). Capacitor banks on the channel1
mcm 1:944583d4b1de 899 *
mcm 1:944583d4b1de 900 * NOTE: Default value: CAPS_CH1_ADDS_NONE
mcm 1:944583d4b1de 901 */
mcm 1:944583d4b1de 902 typedef enum {
mcm 1:944583d4b1de 903 CAPS_CH1_MASK = ( 0b11111 << 0 ), /*!< CAPS_CH1 mask */
mcm 1:944583d4b1de 904 CAPS_CH1_ADDS_NONE = ( 0b00000 << 0 ), /*!< None to LF1P */
mcm 1:944583d4b1de 905 CAPS_CH1_ADDS_1PF = ( 0b00001 << 0 ), /*!< Adds 1pF to LF1P */
mcm 1:944583d4b1de 906 CAPS_CH1_ADDS_2PF = ( 0b00010 << 0 ), /*!< Adds 2pF to LF1P */
mcm 1:944583d4b1de 907 CAPS_CH1_ADDS_4PF = ( 0b00100 << 0 ), /*!< Adds 4pF to LF1P */
mcm 1:944583d4b1de 908 CAPS_CH1_ADDS_8PF = ( 0b01000 << 0 ), /*!< Adds 8pF to LF1P */
mcm 1:944583d4b1de 909 CAPS_CH1_ADDS_16PF = ( 0b10000 << 0 ) /*!< Adds 16pF to LF1P */
mcm 1:944583d4b1de 910 } AS3933_r17_caps_ch1_value_t;
mcm 1:944583d4b1de 911
mcm 1:944583d4b1de 912
mcm 1:944583d4b1de 913 /* R18 REGISTER. COMMANDS */
mcm 1:944583d4b1de 914 /**
mcm 1:944583d4b1de 915 * @brief CAPS_CH2 ( R18<4:0> ). Capacitor banks on the channel2
mcm 1:944583d4b1de 916 *
mcm 1:944583d4b1de 917 * NOTE: Default value: CAPS_CH2_ADDS_NONE
mcm 1:944583d4b1de 918 */
mcm 1:944583d4b1de 919 typedef enum {
mcm 1:944583d4b1de 920 CAPS_CH2_MASK = ( 0b11111 << 0 ), /*!< CAPS_CH2 mask */
mcm 1:944583d4b1de 921 CAPS_CH2_ADDS_NONE = ( 0b00000 << 0 ), /*!< None to LF2P */
mcm 1:944583d4b1de 922 CAPS_CH2_ADDS_1PF = ( 0b00001 << 0 ), /*!< Adds 1pF to LF2P */
mcm 1:944583d4b1de 923 CAPS_CH2_ADDS_2PF = ( 0b00010 << 0 ), /*!< Adds 2pF to LF2P */
mcm 1:944583d4b1de 924 CAPS_CH2_ADDS_4PF = ( 0b00100 << 0 ), /*!< Adds 4pF to LF2P */
mcm 1:944583d4b1de 925 CAPS_CH2_ADDS_8PF = ( 0b01000 << 0 ), /*!< Adds 8pF to LF2P */
mcm 1:944583d4b1de 926 CAPS_CH2_ADDS_16PF = ( 0b10000 << 0 ) /*!< Adds 16pF to LF2P */
mcm 1:944583d4b1de 927 } AS3933_r18_caps_ch2_value_t;
mcm 1:944583d4b1de 928
mcm 1:944583d4b1de 929
mcm 1:944583d4b1de 930 /* R19 REGISTER. COMMANDS */
mcm 1:944583d4b1de 931 /**
mcm 1:944583d4b1de 932 * @brief CAPS_CH3 ( R19<4:0> ). Capacitor banks on the channel3
mcm 1:944583d4b1de 933 *
mcm 1:944583d4b1de 934 * NOTE: Default value: CAPS_CH3_ADDS_NONE
mcm 1:944583d4b1de 935 */
mcm 1:944583d4b1de 936 typedef enum {
mcm 1:944583d4b1de 937 CAPS_CH3_MASK = ( 0b11111 << 0 ), /*!< CAPS_CH3 mask */
mcm 1:944583d4b1de 938 CAPS_CH3_ADDS_NONE = ( 0b00000 << 0 ), /*!< None to LF3P */
mcm 1:944583d4b1de 939 CAPS_CH3_ADDS_1PF = ( 0b00001 << 0 ), /*!< Adds 1pF to LF3P */
mcm 1:944583d4b1de 940 CAPS_CH3_ADDS_2PF = ( 0b00010 << 0 ), /*!< Adds 2pF to LF3P */
mcm 1:944583d4b1de 941 CAPS_CH3_ADDS_4PF = ( 0b00100 << 0 ), /*!< Adds 4pF to LF3P */
mcm 1:944583d4b1de 942 CAPS_CH3_ADDS_8PF = ( 0b01000 << 0 ), /*!< Adds 8pF to LF3P */
mcm 1:944583d4b1de 943 CAPS_CH3_ADDS_16PF = ( 0b10000 << 0 ) /*!< Adds 16pF to LF3P */
mcm 1:944583d4b1de 944 } AS3933_r19_caps_ch3_value_t;
mcm 1:944583d4b1de 945
mcm 1:944583d4b1de 946
mcm 1:944583d4b1de 947
mcm 1:944583d4b1de 948
mcm 1:944583d4b1de 949 /* DRIVER COMMANDS */
mcm 1:944583d4b1de 950 /**
mcm 1:944583d4b1de 951 * @brief CHANNEL ENABLED
mcm 1:944583d4b1de 952 *
mcm 1:944583d4b1de 953 * NOTE: p.14 8.1.1 Listening Mode
mcm 1:944583d4b1de 954 */
mcm 1:944583d4b1de 955 typedef enum {
mcm 1:944583d4b1de 956 AS3933_CH1_OFF_CH2_OFF_CH3_OFF = 0, /*!< All channels disabled */
mcm 1:944583d4b1de 957 AS3933_CH1_ON_CH2_OFF_CH3_OFF = 1, /*!< Channels 1 enabled */
mcm 1:944583d4b1de 958 AS3933_CH1_OFF_CH2_ON_CH3_OFF = 2, /*!< Channel 2 enabled */
mcm 1:944583d4b1de 959 AS3933_CH1_ON_CH2_ON_CH3_OFF = 3, /*!< Channels 1 and 2 enabled */
mcm 1:944583d4b1de 960 AS3933_CH1_OFF_CH2_OFF_CH3_ON = 4, /*!< Channel 3 enabled */
mcm 1:944583d4b1de 961 AS3933_CH1_ON_CH2_OFF_CH3_ON = 5, /*!< Channels 1 and 3 enabled */
mcm 1:944583d4b1de 962 AS3933_CH1_OFF_CH2_ON_CH3_ON = 6, /*!< Channels 2 and 3 enabled */
mcm 1:944583d4b1de 963 AS3933_CH1_ON_CH2_ON_CH3_ON = 7 /*!< All channels enabled */
mcm 1:944583d4b1de 964 } AS3933_channels_enable_t;
mcm 1:944583d4b1de 965
mcm 1:944583d4b1de 966
mcm 1:944583d4b1de 967 /**
mcm 1:944583d4b1de 968 * @brief LISTENING MODE ( LOW POWER MODE )
mcm 1:944583d4b1de 969 *
mcm 1:944583d4b1de 970 * NOTE: p.14 8.1.1 Listening Mode
mcm 1:944583d4b1de 971 */
mcm 1:944583d4b1de 972 typedef enum {
mcm 1:944583d4b1de 973 AS3933_STANDARD_LISTENING_MODE = 0, /*!< All channels are active at the same time */
mcm 1:944583d4b1de 974 AS3933_SCANNING_MODE = 1, /*!< Low Power mode 1 */
mcm 1:944583d4b1de 975 AS3933_ON_OFF_MODE = 2 /*!< Low Power mode 2 */
mcm 1:944583d4b1de 976 } AS3933_scanning_mode_t;
mcm 1:944583d4b1de 977
mcm 1:944583d4b1de 978
mcm 1:944583d4b1de 979 /**
mcm 1:944583d4b1de 980 * @brief TOLERANCE SETTINGS
mcm 1:944583d4b1de 981 *
mcm 1:944583d4b1de 982 * NOTE: p.23 8.3.1 Frequency Detector / RSSI / Channel Selector
mcm 1:944583d4b1de 983 * The tolerance depends on the frequency detection band.
mcm 1:944583d4b1de 984 */
mcm 1:944583d4b1de 985 typedef enum {
mcm 1:944583d4b1de 986 AS3933_TOLERANCE_MASK = ( 0b11 << 0 ), /*!< Tolerance mask */
mcm 1:944583d4b1de 987 AS3933_TOLERANCE_TIGHT = ( 0b00 << 0 ),
mcm 1:944583d4b1de 988 AS3933_TOLERANCE_MEDIUM = ( 0b01 << 0 ),
mcm 1:944583d4b1de 989 AS3933_TOLERANCE_RELAX = ( 0b10 << 0 )
mcm 1:944583d4b1de 990 } AS3933_tolerance_settings_t;
mcm 1:944583d4b1de 991
mcm 1:944583d4b1de 992
mcm 1:944583d4b1de 993 /**
mcm 1:944583d4b1de 994 * @brief CHANNELS ( Parallel Tuning Capacitance )
mcm 1:944583d4b1de 995 *
mcm 1:944583d4b1de 996 */
mcm 1:944583d4b1de 997 typedef enum {
mcm 1:944583d4b1de 998 AS3933_CHANNEL_LF1P = 0, /*!< Channel 1 */
mcm 1:944583d4b1de 999 AS3933_CHANNEL_LF2P = 1, /*!< Channel 2 */
mcm 1:944583d4b1de 1000 AS3933_CHANNEL_LF3P = 2 /*!< Channel 3 */
mcm 1:944583d4b1de 1001 } AS3933_parallel_tuning_channels_t;
mcm 1:944583d4b1de 1002
mcm 1:944583d4b1de 1003
mcm 1:944583d4b1de 1004 /**
mcm 1:944583d4b1de 1005 * @brief CAPACITANCE ( Parallel Tuning Capacitance )
mcm 1:944583d4b1de 1006 *
mcm 1:944583d4b1de 1007 */
mcm 1:944583d4b1de 1008 typedef enum {
mcm 1:944583d4b1de 1009 AS3933_CAPACITANCE_MASK = ( 0b11111 << 0 ), /*!< AS3933_CAPACITANCE mask */
mcm 1:944583d4b1de 1010 AS3933_CAPACITANCE_ADDS_NONE = ( 0b00000 << 0 ), /*!< None to chosen channel */
mcm 1:944583d4b1de 1011 AS3933_CAPACITANCE_ADDS_1PF = ( 0b00001 << 0 ), /*!< Adds 1pF to chosen channel */
mcm 1:944583d4b1de 1012 AS3933_CAPACITANCE_ADDS_2PF = ( 0b00010 << 0 ), /*!< Adds 2pF to chosen channel */
mcm 1:944583d4b1de 1013 AS3933_CAPACITANCE_ADDS_4PF = ( 0b00100 << 0 ), /*!< Adds 4pF to chosen channel */
mcm 1:944583d4b1de 1014 AS3933_CAPACITANCE_ADDS_8PF = ( 0b01000 << 0 ), /*!< Adds 8pF to chosen channel */
mcm 1:944583d4b1de 1015 AS3933_CAPACITANCE_ADDS_16PF = ( 0b10000 << 0 ) /*!< Adds 16pF to chosen channel */
mcm 1:944583d4b1de 1016 } AS3933_parallel_tuning_capacitance_t;
mcm 1:944583d4b1de 1017
mcm 1:944583d4b1de 1018
mcm 1:944583d4b1de 1019
mcm 1:944583d4b1de 1020 #ifndef AS3933_VECTOR_STRUCT_H
mcm 1:944583d4b1de 1021 #define AS3933_VECTOR_STRUCT_H
mcm 1:944583d4b1de 1022 /* AS3933 DATA */
mcm 1:944583d4b1de 1023 typedef struct {
mcm 1:944583d4b1de 1024 int8_t f_wake; /*!< False wakeup register */
mcm 1:944583d4b1de 1025 uint8_t patt2b; /*!< Wakeup pattern PATT2B ( Manchester ) */
mcm 1:944583d4b1de 1026 uint8_t patt1b; /*!< Wakeup pattern PATT1B ( Manchester ) */
mcm 1:944583d4b1de 1027 uint8_t rssi1; /*!< RSSI1 Channel 1 */
mcm 1:944583d4b1de 1028 uint8_t rssi2; /*!< RSSI2 Channel 2 */
mcm 1:944583d4b1de 1029 uint8_t rssi3; /*!< RSSI3 Channel 3 */
mcm 1:944583d4b1de 1030
mcm 1:944583d4b1de 1031 uint32_t data; /*!< Data */
mcm 1:944583d4b1de 1032 } AS3933_data_t;
mcm 1:944583d4b1de 1033 #endif
mcm 1:944583d4b1de 1034
mcm 1:944583d4b1de 1035
mcm 1:944583d4b1de 1036
mcm 1:944583d4b1de 1037 /**
mcm 1:944583d4b1de 1038 * @brief INTERNAL CONSTANTS
mcm 1:944583d4b1de 1039 */
mcm 1:944583d4b1de 1040 typedef enum {
mcm 1:944583d4b1de 1041 AS3933_SUCCESS = 0,
mcm 1:944583d4b1de 1042 AS3933_FAILURE = 1,
mcm 1:944583d4b1de 1043 SPI_SUCCESS = 1
mcm 1:944583d4b1de 1044 } AS3933_status_t;
mcm 1:944583d4b1de 1045
mcm 1:944583d4b1de 1046
mcm 1:944583d4b1de 1047
mcm 1:944583d4b1de 1048
mcm 1:944583d4b1de 1049 /** Create an AS3933 object connected to the specified SPI pins.
mcm 1:944583d4b1de 1050 *
mcm 1:944583d4b1de 1051 * @param mosi SPI Master Output Slave Input
mcm 1:944583d4b1de 1052 * @param miso SPI Master Input Slave Output
mcm 1:944583d4b1de 1053 * @param sclk SPI clock
mcm 1:944583d4b1de 1054 * @param cs SPI Chip Select
mcm 1:944583d4b1de 1055 * @param freq SPI frequency in Hz.
mcm 1:944583d4b1de 1056 */
mcm 1:944583d4b1de 1057 AS3933 ( PinName mosi, PinName miso, PinName sclk, PinName cs, uint32_t freq );
mcm 1:944583d4b1de 1058
mcm 1:944583d4b1de 1059 /** Delete AS3933 object.
mcm 1:944583d4b1de 1060 */
mcm 1:944583d4b1de 1061 ~AS3933();
mcm 1:944583d4b1de 1062
mcm 1:944583d4b1de 1063 /** It configures the low power mode.
mcm 1:944583d4b1de 1064 */
mcm 1:944583d4b1de 1065 AS3933_status_t AS3933_SetLowPowerMode ( AS3933_channels_enable_t myEnabledChannels, AS3933_scanning_mode_t myLowPowerMode, AS3933_r4_t_off_value_t myT_Off );
mcm 1:944583d4b1de 1066
mcm 1:944583d4b1de 1067 /** It configures the artificial wakeup.
mcm 1:944583d4b1de 1068 */
mcm 1:944583d4b1de 1069 AS3933_status_t AS3933_SetArtificialWakeUp ( AS3933_r8_t_auto_value_t myArtificialWakeUp );
mcm 1:944583d4b1de 1070
mcm 1:944583d4b1de 1071 /** It gets feedback on the surrounding environment reading the false wakeup register.
mcm 1:944583d4b1de 1072 */
mcm 1:944583d4b1de 1073 AS3933_status_t AS3933_ReadFalseWakeUpRegister ( AS3933_data_t* myF_WAKE );
mcm 1:944583d4b1de 1074
mcm 1:944583d4b1de 1075 /** It configures the clock generator.
mcm 1:944583d4b1de 1076 */
mcm 1:944583d4b1de 1077 AS3933_status_t AS3933_SetClockGenerator ( AS3933_r1_en_xtal_value_t myClockGenerator, AS3933_r16_clock_gen_dis_value_t myClockGeneratorOutputMode );
mcm 1:944583d4b1de 1078
mcm 1:944583d4b1de 1079 /** It calibrates RC oscillator ( Self Calibration only ).
mcm 1:944583d4b1de 1080 */
mcm 1:944583d4b1de 1081 AS3933_status_t AS3933_CalibrateRC_Oscillator ( void );
mcm 1:944583d4b1de 1082
mcm 1:944583d4b1de 1083 /** It configures the antenna damper.
mcm 1:944583d4b1de 1084 */
mcm 1:944583d4b1de 1085 AS3933_status_t AS3933_SetAntennaDamper ( AS3933_r1_att_on_value_t myAntennaDamperMode, AS3933_r4_d_res_value_t myShuntResistor );
mcm 1:944583d4b1de 1086
mcm 1:944583d4b1de 1087 /** It configures the envelop detector for different symbol rates.
mcm 1:944583d4b1de 1088 */
mcm 1:944583d4b1de 1089 AS3933_status_t AS3933_SetEnvelopDetector ( AS3933_r3_fs_env_value_t mySymbolRates );
mcm 1:944583d4b1de 1090
mcm 1:944583d4b1de 1091 /** It configures the data slicer for different preamble length.
mcm 1:944583d4b1de 1092 */
mcm 1:944583d4b1de 1093 AS3933_status_t AS3933_SetDataSlicer ( AS3933_r1_abs_hy_value_t myAbsoluteThresholdMode, AS3933_r3_fs_scl_value_t myMinimumPreambleLength );
mcm 1:944583d4b1de 1094
mcm 1:944583d4b1de 1095 /** It configures the hysteresis on the data slicer comparator.
mcm 1:944583d4b1de 1096 */
mcm 1:944583d4b1de 1097 AS3933_status_t AS3933_SetComparatorHysteresis ( AS3933_r3_hy_pos_value_t myHysteresisMode, AS3933_r3_hy_20m_value_t myHysteresisRange );
mcm 1:944583d4b1de 1098
mcm 1:944583d4b1de 1099 /** It configures the gain reduction.
mcm 1:944583d4b1de 1100 */
mcm 1:944583d4b1de 1101 AS3933_status_t AS3933_SetGainReduction ( AS3933_r4_gr_value_t myGainReductionValue );
mcm 1:944583d4b1de 1102
mcm 1:944583d4b1de 1103 /** It configures the operating frequency range.
mcm 1:944583d4b1de 1104 */
mcm 1:944583d4b1de 1105 AS3933_status_t AS3933_SetOperatingFrequencyRange ( AS3933_r8_band_sel_value_t myOperatingFrequencyRange );
mcm 1:944583d4b1de 1106
mcm 1:944583d4b1de 1107 /** It configures the frequency detection tolerance.
mcm 1:944583d4b1de 1108 */
mcm 1:944583d4b1de 1109 AS3933_status_t AS3933_SetFrequencyDetectionTolerance ( AS3933_tolerance_settings_t myTolerance );
mcm 1:944583d4b1de 1110
mcm 1:944583d4b1de 1111 /** It configures the +3dB gain boost.
mcm 1:944583d4b1de 1112 */
mcm 1:944583d4b1de 1113 AS3933_status_t AS3933_SetGainBoost ( AS3933_r2_g_boost_value_t myGainBoostMode );
mcm 1:944583d4b1de 1114
mcm 1:944583d4b1de 1115 /** It configures the Automatic Gain Control ( AGC ).
mcm 1:944583d4b1de 1116 */
mcm 1:944583d4b1de 1117 AS3933_status_t AS3933_SetAGC ( AS3933_r1_agc_tlim_value_t myAGC_CarrierBurstMode, AS3933_r1_agc_ud_value_t myAGC_OperatingDirection );
mcm 1:944583d4b1de 1118
mcm 1:944583d4b1de 1119 /** It configures the mask data before wakeup.
mcm 1:944583d4b1de 1120 */
mcm 1:944583d4b1de 1121 AS3933_status_t AS3933_SetDataMask ( AS3933_r0_dat_mask_value_t myDataMaskMode );
mcm 1:944583d4b1de 1122
mcm 1:944583d4b1de 1123 /** It configures the correlator and the Manchester Decoder.
mcm 1:944583d4b1de 1124 */
mcm 1:944583d4b1de 1125 AS3933_status_t AS3933_SetCorrelator ( AS3933_r1_en_wpat_value_t myCorrelatorMode, AS3933_r0_patt32_value_t mySymbolPattern, AS3933_r7_t_hbit_value_t myRate,
mcm 3:2de552c4ffbc 1126 AS3933_r1_en_manch_value_t myManchesterDecoderMode );
mcm 1:944583d4b1de 1127
mcm 1:944583d4b1de 1128 /** It sets the wakeup pattern ( Manchester ).
mcm 1:944583d4b1de 1129 */
mcm 1:944583d4b1de 1130 AS3933_status_t AS3933_SetWakeUpPattern ( AS3933_data_t myWakeUpPattern );
mcm 1:944583d4b1de 1131
mcm 1:944583d4b1de 1132 /** It gets the wakeup pattern ( Manchester ).
mcm 1:944583d4b1de 1133 */
mcm 1:944583d4b1de 1134 AS3933_status_t AS3933_GetWakeUpPattern ( AS3933_data_t* myWakeUpPattern );
mcm 1:944583d4b1de 1135
mcm 1:944583d4b1de 1136 /** It sets the automatic time-out setup.
mcm 1:944583d4b1de 1137 */
mcm 1:944583d4b1de 1138 AS3933_status_t AS3933_SetAutomaticTimeOut ( AS3933_r7_t_out_value_t myAutomaticTimeOut );
mcm 1:944583d4b1de 1139
mcm 1:944583d4b1de 1140 /** It sets the parallel tuning capacitance on the chosen channel.
mcm 1:944583d4b1de 1141 */
mcm 1:944583d4b1de 1142 AS3933_status_t AS3933_SetParallelTuningCapacitance ( AS3933_parallel_tuning_channels_t myChannel, AS3933_parallel_tuning_capacitance_t myAddedCapacitance );
mcm 1:944583d4b1de 1143
mcm 1:944583d4b1de 1144 /** It gets the RSSI for all channels.
mcm 1:944583d4b1de 1145 */
mcm 1:944583d4b1de 1146 AS3933_status_t AS3933_GetRSSI ( AS3933_data_t* myChannelRSSI );
mcm 1:944583d4b1de 1147
mcm 1:944583d4b1de 1148 /** It sends a direct command
mcm 1:944583d4b1de 1149 */
mcm 1:944583d4b1de 1150 AS3933_status_t AS3933_Send_DirectCommand ( AS3933_spi_direct_commands_t myDirectCommand );
mcm 1:944583d4b1de 1151
mcm 1:944583d4b1de 1152 private:
mcm 1:944583d4b1de 1153 SPI _spi;
mcm 1:944583d4b1de 1154 DigitalOut _cs;
mcm 1:944583d4b1de 1155 };
mcm 1:944583d4b1de 1156
mcm 1:944583d4b1de 1157 #endif