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mbed 2

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TARGET_KL05Z/MKL05Z4.h@78:ed8466a608b4, 2014-02-18 (annotated)

Committer:
emilmont
Date:
Tue Feb 18 15:02:39 2014 +0000
Revision:
78:ed8466a608b4
Add KL05Z Target

Fix LPC11XX InterruptIn

Fix NUCLEO boards us_ticker

Fix NUCLEO_L152RE AnalogOut

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 78:ed8466a608b4 1 /*
emilmont 78:ed8466a608b4 2 ** ###################################################################
emilmont 78:ed8466a608b4 3 ** Processors: MKL05Z32FK4
emilmont 78:ed8466a608b4 4 ** MKL05Z32LC4
emilmont 78:ed8466a608b4 5 ** MKL05Z32VLF4
emilmont 78:ed8466a608b4 6 **
emilmont 78:ed8466a608b4 7 ** Compilers: ARM Compiler
emilmont 78:ed8466a608b4 8 ** Freescale C/C++ for Embedded ARM
emilmont 78:ed8466a608b4 9 ** GNU C Compiler
emilmont 78:ed8466a608b4 10 ** IAR ANSI C/C++ Compiler for ARM
emilmont 78:ed8466a608b4 11 **
emilmont 78:ed8466a608b4 12 ** Reference manual: KL05P48M48SF1RM, Rev.3, Sep 2012
emilmont 78:ed8466a608b4 13 ** Version: rev. 1.3, 2012-10-04
emilmont 78:ed8466a608b4 14 **
emilmont 78:ed8466a608b4 15 ** Abstract:
emilmont 78:ed8466a608b4 16 ** CMSIS Peripheral Access Layer for MKL05Z4
emilmont 78:ed8466a608b4 17 **
emilmont 78:ed8466a608b4 18 ** Copyright: 1997 - 2012 Freescale, Inc. All Rights Reserved.
emilmont 78:ed8466a608b4 19 **
emilmont 78:ed8466a608b4 20 ** http: www.freescale.com
emilmont 78:ed8466a608b4 21 ** mail: support@freescale.com
emilmont 78:ed8466a608b4 22 **
emilmont 78:ed8466a608b4 23 ** Revisions:
emilmont 78:ed8466a608b4 24 ** - rev. 1.0 (2012-06-08)
emilmont 78:ed8466a608b4 25 ** Initial version.
emilmont 78:ed8466a608b4 26 ** - rev. 1.1 (2012-06-21)
emilmont 78:ed8466a608b4 27 ** Update according to reference manual rev. 1.
emilmont 78:ed8466a608b4 28 ** - rev. 1.2 (2012-08-01)
emilmont 78:ed8466a608b4 29 ** Device type UARTLP changed to UART0.
emilmont 78:ed8466a608b4 30 ** Missing PORTB_IRQn interrupt number definition added.
emilmont 78:ed8466a608b4 31 ** - rev. 1.3 (2012-10-04)
emilmont 78:ed8466a608b4 32 ** Update according to reference manual rev. 3.
emilmont 78:ed8466a608b4 33 **
emilmont 78:ed8466a608b4 34 ** ###################################################################
emilmont 78:ed8466a608b4 35 */
emilmont 78:ed8466a608b4 36
emilmont 78:ed8466a608b4 37 /**
emilmont 78:ed8466a608b4 38 * @file MKL05Z4.h
emilmont 78:ed8466a608b4 39 * @version 1.3
emilmont 78:ed8466a608b4 40 * @date 2012-10-04
emilmont 78:ed8466a608b4 41 * @brief CMSIS Peripheral Access Layer for MKL05Z4
emilmont 78:ed8466a608b4 42 *
emilmont 78:ed8466a608b4 43 * CMSIS Peripheral Access Layer for MKL05Z4
emilmont 78:ed8466a608b4 44 */
emilmont 78:ed8466a608b4 45
emilmont 78:ed8466a608b4 46 #if !defined(MKL05Z4_H_)
emilmont 78:ed8466a608b4 47 #define MKL05Z4_H_ /**< Symbol preventing repeated inclusion */
emilmont 78:ed8466a608b4 48
emilmont 78:ed8466a608b4 49 /** Memory map major version (memory maps with equal major version number are
emilmont 78:ed8466a608b4 50 * compatible) */
emilmont 78:ed8466a608b4 51 #define MCU_MEM_MAP_VERSION 0x0100u
emilmont 78:ed8466a608b4 52 /** Memory map minor version */
emilmont 78:ed8466a608b4 53 #define MCU_MEM_MAP_VERSION_MINOR 0x0003u
emilmont 78:ed8466a608b4 54
emilmont 78:ed8466a608b4 55
emilmont 78:ed8466a608b4 56 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 57 -- Interrupt vector numbers
emilmont 78:ed8466a608b4 58 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 59
emilmont 78:ed8466a608b4 60 /**
emilmont 78:ed8466a608b4 61 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
emilmont 78:ed8466a608b4 62 * @{
emilmont 78:ed8466a608b4 63 */
emilmont 78:ed8466a608b4 64
emilmont 78:ed8466a608b4 65 /** Interrupt Number Definitions */
emilmont 78:ed8466a608b4 66 typedef enum IRQn {
emilmont 78:ed8466a608b4 67 /* Core interrupts */
emilmont 78:ed8466a608b4 68 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
emilmont 78:ed8466a608b4 69 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
emilmont 78:ed8466a608b4 70 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
emilmont 78:ed8466a608b4 71 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
emilmont 78:ed8466a608b4 72 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
emilmont 78:ed8466a608b4 73
emilmont 78:ed8466a608b4 74 /* Device specific interrupts */
emilmont 78:ed8466a608b4 75 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete/error interrupt */
emilmont 78:ed8466a608b4 76 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete/error interrupt */
emilmont 78:ed8466a608b4 77 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete/error interrupt */
emilmont 78:ed8466a608b4 78 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete/error interrupt */
emilmont 78:ed8466a608b4 79 Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
emilmont 78:ed8466a608b4 80 FTFA_IRQn = 5, /**< FTFA command complete/read collision interrupt */
emilmont 78:ed8466a608b4 81 LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */
emilmont 78:ed8466a608b4 82 LLW_IRQn = 7, /**< Low Leakage Wakeup */
emilmont 78:ed8466a608b4 83 I2C0_IRQn = 8, /**< I2C0 interrupt */
emilmont 78:ed8466a608b4 84 Reserved25_IRQn = 9, /**< Reserved interrupt 25 */
emilmont 78:ed8466a608b4 85 SPI0_IRQn = 10, /**< SPI0 interrupt */
emilmont 78:ed8466a608b4 86 Reserved27_IRQn = 11, /**< Reserved interrupt 27 */
emilmont 78:ed8466a608b4 87 UART0_IRQn = 12, /**< UART0 status/error interrupt */
emilmont 78:ed8466a608b4 88 Reserved29_IRQn = 13, /**< Reserved interrupt 29 */
emilmont 78:ed8466a608b4 89 Reserved30_IRQn = 14, /**< Reserved interrupt 30 */
emilmont 78:ed8466a608b4 90 ADC0_IRQn = 15, /**< ADC0 interrupt */
emilmont 78:ed8466a608b4 91 CMP0_IRQn = 16, /**< CMP0 interrupt */
emilmont 78:ed8466a608b4 92 TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */
emilmont 78:ed8466a608b4 93 TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */
emilmont 78:ed8466a608b4 94 Reserved35_IRQn = 19, /**< Reserved interrupt 35 */
emilmont 78:ed8466a608b4 95 RTC_IRQn = 20, /**< RTC interrupt */
emilmont 78:ed8466a608b4 96 RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
emilmont 78:ed8466a608b4 97 PIT_IRQn = 22, /**< PIT timer interrupt */
emilmont 78:ed8466a608b4 98 Reserved39_IRQn = 23, /**< Reserved interrupt 39 */
emilmont 78:ed8466a608b4 99 Reserved40_IRQn = 24, /**< Reserved interrupt 40 */
emilmont 78:ed8466a608b4 100 DAC0_IRQn = 25, /**< DAC0 interrupt */
emilmont 78:ed8466a608b4 101 TSI0_IRQn = 26, /**< TSI0 interrupt */
emilmont 78:ed8466a608b4 102 MCG_IRQn = 27, /**< MCG interrupt */
emilmont 78:ed8466a608b4 103 LPTimer_IRQn = 28, /**< LPTimer interrupt */
emilmont 78:ed8466a608b4 104 Reserved45_IRQn = 29, /**< Reserved interrupt 45 */
emilmont 78:ed8466a608b4 105 PORTA_IRQn = 30, /**< Port A interrupt */
emilmont 78:ed8466a608b4 106 PORTB_IRQn = 31 /**< Port B interrupt */
emilmont 78:ed8466a608b4 107 } IRQn_Type;
emilmont 78:ed8466a608b4 108
emilmont 78:ed8466a608b4 109 /**
emilmont 78:ed8466a608b4 110 * @}
emilmont 78:ed8466a608b4 111 */ /* end of group Interrupt_vector_numbers */
emilmont 78:ed8466a608b4 112
emilmont 78:ed8466a608b4 113
emilmont 78:ed8466a608b4 114 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 115 -- Cortex M0 Core Configuration
emilmont 78:ed8466a608b4 116 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 117
emilmont 78:ed8466a608b4 118 /**
emilmont 78:ed8466a608b4 119 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
emilmont 78:ed8466a608b4 120 * @{
emilmont 78:ed8466a608b4 121 */
emilmont 78:ed8466a608b4 122
emilmont 78:ed8466a608b4 123 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
emilmont 78:ed8466a608b4 124 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
emilmont 78:ed8466a608b4 125 #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
emilmont 78:ed8466a608b4 126 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
emilmont 78:ed8466a608b4 127 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
emilmont 78:ed8466a608b4 128
emilmont 78:ed8466a608b4 129 #include "core_cm0plus.h" /* Core Peripheral Access Layer */
emilmont 78:ed8466a608b4 130 #include "system_MKL05Z4.h" /* Device specific configuration file */
emilmont 78:ed8466a608b4 131
emilmont 78:ed8466a608b4 132 /**
emilmont 78:ed8466a608b4 133 * @}
emilmont 78:ed8466a608b4 134 */ /* end of group Cortex_Core_Configuration */
emilmont 78:ed8466a608b4 135
emilmont 78:ed8466a608b4 136
emilmont 78:ed8466a608b4 137 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 138 -- Device Peripheral Access Layer
emilmont 78:ed8466a608b4 139 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 140
emilmont 78:ed8466a608b4 141 /**
emilmont 78:ed8466a608b4 142 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
emilmont 78:ed8466a608b4 143 * @{
emilmont 78:ed8466a608b4 144 */
emilmont 78:ed8466a608b4 145
emilmont 78:ed8466a608b4 146
emilmont 78:ed8466a608b4 147 /*
emilmont 78:ed8466a608b4 148 ** Start of section using anonymous unions
emilmont 78:ed8466a608b4 149 */
emilmont 78:ed8466a608b4 150
emilmont 78:ed8466a608b4 151 #if defined(__ARMCC_VERSION)
emilmont 78:ed8466a608b4 152 #pragma push
emilmont 78:ed8466a608b4 153 #pragma anon_unions
emilmont 78:ed8466a608b4 154 #elif defined(__CWCC__)
emilmont 78:ed8466a608b4 155 #pragma push
emilmont 78:ed8466a608b4 156 #pragma cpp_extensions on
emilmont 78:ed8466a608b4 157 #elif defined(__GNUC__)
emilmont 78:ed8466a608b4 158 /* anonymous unions are enabled by default */
emilmont 78:ed8466a608b4 159 #elif defined(__IAR_SYSTEMS_ICC__)
emilmont 78:ed8466a608b4 160 #pragma language=extended
emilmont 78:ed8466a608b4 161 #else
emilmont 78:ed8466a608b4 162 #error Not supported compiler type
emilmont 78:ed8466a608b4 163 #endif
emilmont 78:ed8466a608b4 164
emilmont 78:ed8466a608b4 165 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 166 -- ADC Peripheral Access Layer
emilmont 78:ed8466a608b4 167 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 168
emilmont 78:ed8466a608b4 169 /**
emilmont 78:ed8466a608b4 170 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
emilmont 78:ed8466a608b4 171 * @{
emilmont 78:ed8466a608b4 172 */
emilmont 78:ed8466a608b4 173
emilmont 78:ed8466a608b4 174 /** ADC - Register Layout Typedef */
emilmont 78:ed8466a608b4 175 typedef struct {
emilmont 78:ed8466a608b4 176 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
emilmont 78:ed8466a608b4 177 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
emilmont 78:ed8466a608b4 178 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
emilmont 78:ed8466a608b4 179 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
emilmont 78:ed8466a608b4 180 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
emilmont 78:ed8466a608b4 181 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
emilmont 78:ed8466a608b4 182 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
emilmont 78:ed8466a608b4 183 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
emilmont 78:ed8466a608b4 184 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
emilmont 78:ed8466a608b4 185 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
emilmont 78:ed8466a608b4 186 uint8_t RESERVED_0[4];
emilmont 78:ed8466a608b4 187 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
emilmont 78:ed8466a608b4 188 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
emilmont 78:ed8466a608b4 189 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
emilmont 78:ed8466a608b4 190 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
emilmont 78:ed8466a608b4 191 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
emilmont 78:ed8466a608b4 192 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
emilmont 78:ed8466a608b4 193 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
emilmont 78:ed8466a608b4 194 } ADC_Type;
emilmont 78:ed8466a608b4 195
emilmont 78:ed8466a608b4 196 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 197 -- ADC Register Masks
emilmont 78:ed8466a608b4 198 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 199
emilmont 78:ed8466a608b4 200 /**
emilmont 78:ed8466a608b4 201 * @addtogroup ADC_Register_Masks ADC Register Masks
emilmont 78:ed8466a608b4 202 * @{
emilmont 78:ed8466a608b4 203 */
emilmont 78:ed8466a608b4 204
emilmont 78:ed8466a608b4 205 /* SC1 Bit Fields */
emilmont 78:ed8466a608b4 206 #define ADC_SC1_ADCH_MASK 0x1Fu
emilmont 78:ed8466a608b4 207 #define ADC_SC1_ADCH_SHIFT 0
emilmont 78:ed8466a608b4 208 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
emilmont 78:ed8466a608b4 209 #define ADC_SC1_AIEN_MASK 0x40u
emilmont 78:ed8466a608b4 210 #define ADC_SC1_AIEN_SHIFT 6
emilmont 78:ed8466a608b4 211 #define ADC_SC1_COCO_MASK 0x80u
emilmont 78:ed8466a608b4 212 #define ADC_SC1_COCO_SHIFT 7
emilmont 78:ed8466a608b4 213 /* CFG1 Bit Fields */
emilmont 78:ed8466a608b4 214 #define ADC_CFG1_ADICLK_MASK 0x3u
emilmont 78:ed8466a608b4 215 #define ADC_CFG1_ADICLK_SHIFT 0
emilmont 78:ed8466a608b4 216 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
emilmont 78:ed8466a608b4 217 #define ADC_CFG1_MODE_MASK 0xCu
emilmont 78:ed8466a608b4 218 #define ADC_CFG1_MODE_SHIFT 2
emilmont 78:ed8466a608b4 219 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
emilmont 78:ed8466a608b4 220 #define ADC_CFG1_ADLSMP_MASK 0x10u
emilmont 78:ed8466a608b4 221 #define ADC_CFG1_ADLSMP_SHIFT 4
emilmont 78:ed8466a608b4 222 #define ADC_CFG1_ADIV_MASK 0x60u
emilmont 78:ed8466a608b4 223 #define ADC_CFG1_ADIV_SHIFT 5
emilmont 78:ed8466a608b4 224 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
emilmont 78:ed8466a608b4 225 #define ADC_CFG1_ADLPC_MASK 0x80u
emilmont 78:ed8466a608b4 226 #define ADC_CFG1_ADLPC_SHIFT 7
emilmont 78:ed8466a608b4 227 /* CFG2 Bit Fields */
emilmont 78:ed8466a608b4 228 #define ADC_CFG2_ADLSTS_MASK 0x3u
emilmont 78:ed8466a608b4 229 #define ADC_CFG2_ADLSTS_SHIFT 0
emilmont 78:ed8466a608b4 230 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
emilmont 78:ed8466a608b4 231 #define ADC_CFG2_ADHSC_MASK 0x4u
emilmont 78:ed8466a608b4 232 #define ADC_CFG2_ADHSC_SHIFT 2
emilmont 78:ed8466a608b4 233 #define ADC_CFG2_ADACKEN_MASK 0x8u
emilmont 78:ed8466a608b4 234 #define ADC_CFG2_ADACKEN_SHIFT 3
emilmont 78:ed8466a608b4 235 #define ADC_CFG2_MUXSEL_MASK 0x10u
emilmont 78:ed8466a608b4 236 #define ADC_CFG2_MUXSEL_SHIFT 4
emilmont 78:ed8466a608b4 237 /* R Bit Fields */
emilmont 78:ed8466a608b4 238 #define ADC_R_D_MASK 0xFFFFu
emilmont 78:ed8466a608b4 239 #define ADC_R_D_SHIFT 0
emilmont 78:ed8466a608b4 240 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
emilmont 78:ed8466a608b4 241 /* CV1 Bit Fields */
emilmont 78:ed8466a608b4 242 #define ADC_CV1_CV_MASK 0xFFFFu
emilmont 78:ed8466a608b4 243 #define ADC_CV1_CV_SHIFT 0
emilmont 78:ed8466a608b4 244 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
emilmont 78:ed8466a608b4 245 /* CV2 Bit Fields */
emilmont 78:ed8466a608b4 246 #define ADC_CV2_CV_MASK 0xFFFFu
emilmont 78:ed8466a608b4 247 #define ADC_CV2_CV_SHIFT 0
emilmont 78:ed8466a608b4 248 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
emilmont 78:ed8466a608b4 249 /* SC2 Bit Fields */
emilmont 78:ed8466a608b4 250 #define ADC_SC2_REFSEL_MASK 0x3u
emilmont 78:ed8466a608b4 251 #define ADC_SC2_REFSEL_SHIFT 0
emilmont 78:ed8466a608b4 252 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
emilmont 78:ed8466a608b4 253 #define ADC_SC2_DMAEN_MASK 0x4u
emilmont 78:ed8466a608b4 254 #define ADC_SC2_DMAEN_SHIFT 2
emilmont 78:ed8466a608b4 255 #define ADC_SC2_ACREN_MASK 0x8u
emilmont 78:ed8466a608b4 256 #define ADC_SC2_ACREN_SHIFT 3
emilmont 78:ed8466a608b4 257 #define ADC_SC2_ACFGT_MASK 0x10u
emilmont 78:ed8466a608b4 258 #define ADC_SC2_ACFGT_SHIFT 4
emilmont 78:ed8466a608b4 259 #define ADC_SC2_ACFE_MASK 0x20u
emilmont 78:ed8466a608b4 260 #define ADC_SC2_ACFE_SHIFT 5
emilmont 78:ed8466a608b4 261 #define ADC_SC2_ADTRG_MASK 0x40u
emilmont 78:ed8466a608b4 262 #define ADC_SC2_ADTRG_SHIFT 6
emilmont 78:ed8466a608b4 263 #define ADC_SC2_ADACT_MASK 0x80u
emilmont 78:ed8466a608b4 264 #define ADC_SC2_ADACT_SHIFT 7
emilmont 78:ed8466a608b4 265 /* SC3 Bit Fields */
emilmont 78:ed8466a608b4 266 #define ADC_SC3_AVGS_MASK 0x3u
emilmont 78:ed8466a608b4 267 #define ADC_SC3_AVGS_SHIFT 0
emilmont 78:ed8466a608b4 268 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
emilmont 78:ed8466a608b4 269 #define ADC_SC3_AVGE_MASK 0x4u
emilmont 78:ed8466a608b4 270 #define ADC_SC3_AVGE_SHIFT 2
emilmont 78:ed8466a608b4 271 #define ADC_SC3_ADCO_MASK 0x8u
emilmont 78:ed8466a608b4 272 #define ADC_SC3_ADCO_SHIFT 3
emilmont 78:ed8466a608b4 273 #define ADC_SC3_CALF_MASK 0x40u
emilmont 78:ed8466a608b4 274 #define ADC_SC3_CALF_SHIFT 6
emilmont 78:ed8466a608b4 275 #define ADC_SC3_CAL_MASK 0x80u
emilmont 78:ed8466a608b4 276 #define ADC_SC3_CAL_SHIFT 7
emilmont 78:ed8466a608b4 277 /* OFS Bit Fields */
emilmont 78:ed8466a608b4 278 #define ADC_OFS_OFS_MASK 0xFFFFu
emilmont 78:ed8466a608b4 279 #define ADC_OFS_OFS_SHIFT 0
emilmont 78:ed8466a608b4 280 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
emilmont 78:ed8466a608b4 281 /* PG Bit Fields */
emilmont 78:ed8466a608b4 282 #define ADC_PG_PG_MASK 0xFFFFu
emilmont 78:ed8466a608b4 283 #define ADC_PG_PG_SHIFT 0
emilmont 78:ed8466a608b4 284 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
emilmont 78:ed8466a608b4 285 /* CLPD Bit Fields */
emilmont 78:ed8466a608b4 286 #define ADC_CLPD_CLPD_MASK 0x3Fu
emilmont 78:ed8466a608b4 287 #define ADC_CLPD_CLPD_SHIFT 0
emilmont 78:ed8466a608b4 288 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
emilmont 78:ed8466a608b4 289 /* CLPS Bit Fields */
emilmont 78:ed8466a608b4 290 #define ADC_CLPS_CLPS_MASK 0x3Fu
emilmont 78:ed8466a608b4 291 #define ADC_CLPS_CLPS_SHIFT 0
emilmont 78:ed8466a608b4 292 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
emilmont 78:ed8466a608b4 293 /* CLP4 Bit Fields */
emilmont 78:ed8466a608b4 294 #define ADC_CLP4_CLP4_MASK 0x3FFu
emilmont 78:ed8466a608b4 295 #define ADC_CLP4_CLP4_SHIFT 0
emilmont 78:ed8466a608b4 296 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
emilmont 78:ed8466a608b4 297 /* CLP3 Bit Fields */
emilmont 78:ed8466a608b4 298 #define ADC_CLP3_CLP3_MASK 0x1FFu
emilmont 78:ed8466a608b4 299 #define ADC_CLP3_CLP3_SHIFT 0
emilmont 78:ed8466a608b4 300 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
emilmont 78:ed8466a608b4 301 /* CLP2 Bit Fields */
emilmont 78:ed8466a608b4 302 #define ADC_CLP2_CLP2_MASK 0xFFu
emilmont 78:ed8466a608b4 303 #define ADC_CLP2_CLP2_SHIFT 0
emilmont 78:ed8466a608b4 304 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
emilmont 78:ed8466a608b4 305 /* CLP1 Bit Fields */
emilmont 78:ed8466a608b4 306 #define ADC_CLP1_CLP1_MASK 0x7Fu
emilmont 78:ed8466a608b4 307 #define ADC_CLP1_CLP1_SHIFT 0
emilmont 78:ed8466a608b4 308 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
emilmont 78:ed8466a608b4 309 /* CLP0 Bit Fields */
emilmont 78:ed8466a608b4 310 #define ADC_CLP0_CLP0_MASK 0x3Fu
emilmont 78:ed8466a608b4 311 #define ADC_CLP0_CLP0_SHIFT 0
emilmont 78:ed8466a608b4 312 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
emilmont 78:ed8466a608b4 313
emilmont 78:ed8466a608b4 314 /**
emilmont 78:ed8466a608b4 315 * @}
emilmont 78:ed8466a608b4 316 */ /* end of group ADC_Register_Masks */
emilmont 78:ed8466a608b4 317
emilmont 78:ed8466a608b4 318
emilmont 78:ed8466a608b4 319 /* ADC - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 320 /** Peripheral ADC0 base address */
emilmont 78:ed8466a608b4 321 #define ADC0_BASE (0x4003B000u)
emilmont 78:ed8466a608b4 322 /** Peripheral ADC0 base pointer */
emilmont 78:ed8466a608b4 323 #define ADC0 ((ADC_Type *)ADC0_BASE)
emilmont 78:ed8466a608b4 324 /** Array initializer of ADC peripheral base pointers */
emilmont 78:ed8466a608b4 325 #define ADC_BASES { ADC0 }
emilmont 78:ed8466a608b4 326
emilmont 78:ed8466a608b4 327 /**
emilmont 78:ed8466a608b4 328 * @}
emilmont 78:ed8466a608b4 329 */ /* end of group ADC_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 330
emilmont 78:ed8466a608b4 331
emilmont 78:ed8466a608b4 332 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 333 -- CMP Peripheral Access Layer
emilmont 78:ed8466a608b4 334 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 335
emilmont 78:ed8466a608b4 336 /**
emilmont 78:ed8466a608b4 337 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
emilmont 78:ed8466a608b4 338 * @{
emilmont 78:ed8466a608b4 339 */
emilmont 78:ed8466a608b4 340
emilmont 78:ed8466a608b4 341 /** CMP - Register Layout Typedef */
emilmont 78:ed8466a608b4 342 typedef struct {
emilmont 78:ed8466a608b4 343 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
emilmont 78:ed8466a608b4 344 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
emilmont 78:ed8466a608b4 345 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
emilmont 78:ed8466a608b4 346 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
emilmont 78:ed8466a608b4 347 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
emilmont 78:ed8466a608b4 348 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
emilmont 78:ed8466a608b4 349 } CMP_Type;
emilmont 78:ed8466a608b4 350
emilmont 78:ed8466a608b4 351 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 352 -- CMP Register Masks
emilmont 78:ed8466a608b4 353 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 354
emilmont 78:ed8466a608b4 355 /**
emilmont 78:ed8466a608b4 356 * @addtogroup CMP_Register_Masks CMP Register Masks
emilmont 78:ed8466a608b4 357 * @{
emilmont 78:ed8466a608b4 358 */
emilmont 78:ed8466a608b4 359
emilmont 78:ed8466a608b4 360 /* CR0 Bit Fields */
emilmont 78:ed8466a608b4 361 #define CMP_CR0_HYSTCTR_MASK 0x3u
emilmont 78:ed8466a608b4 362 #define CMP_CR0_HYSTCTR_SHIFT 0
emilmont 78:ed8466a608b4 363 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
emilmont 78:ed8466a608b4 364 #define CMP_CR0_FILTER_CNT_MASK 0x70u
emilmont 78:ed8466a608b4 365 #define CMP_CR0_FILTER_CNT_SHIFT 4
emilmont 78:ed8466a608b4 366 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
emilmont 78:ed8466a608b4 367 /* CR1 Bit Fields */
emilmont 78:ed8466a608b4 368 #define CMP_CR1_EN_MASK 0x1u
emilmont 78:ed8466a608b4 369 #define CMP_CR1_EN_SHIFT 0
emilmont 78:ed8466a608b4 370 #define CMP_CR1_OPE_MASK 0x2u
emilmont 78:ed8466a608b4 371 #define CMP_CR1_OPE_SHIFT 1
emilmont 78:ed8466a608b4 372 #define CMP_CR1_COS_MASK 0x4u
emilmont 78:ed8466a608b4 373 #define CMP_CR1_COS_SHIFT 2
emilmont 78:ed8466a608b4 374 #define CMP_CR1_INV_MASK 0x8u
emilmont 78:ed8466a608b4 375 #define CMP_CR1_INV_SHIFT 3
emilmont 78:ed8466a608b4 376 #define CMP_CR1_PMODE_MASK 0x10u
emilmont 78:ed8466a608b4 377 #define CMP_CR1_PMODE_SHIFT 4
emilmont 78:ed8466a608b4 378 #define CMP_CR1_TRIGM_MASK 0x20u
emilmont 78:ed8466a608b4 379 #define CMP_CR1_TRIGM_SHIFT 5
emilmont 78:ed8466a608b4 380 #define CMP_CR1_WE_MASK 0x40u
emilmont 78:ed8466a608b4 381 #define CMP_CR1_WE_SHIFT 6
emilmont 78:ed8466a608b4 382 #define CMP_CR1_SE_MASK 0x80u
emilmont 78:ed8466a608b4 383 #define CMP_CR1_SE_SHIFT 7
emilmont 78:ed8466a608b4 384 /* FPR Bit Fields */
emilmont 78:ed8466a608b4 385 #define CMP_FPR_FILT_PER_MASK 0xFFu
emilmont 78:ed8466a608b4 386 #define CMP_FPR_FILT_PER_SHIFT 0
emilmont 78:ed8466a608b4 387 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
emilmont 78:ed8466a608b4 388 /* SCR Bit Fields */
emilmont 78:ed8466a608b4 389 #define CMP_SCR_COUT_MASK 0x1u
emilmont 78:ed8466a608b4 390 #define CMP_SCR_COUT_SHIFT 0
emilmont 78:ed8466a608b4 391 #define CMP_SCR_CFF_MASK 0x2u
emilmont 78:ed8466a608b4 392 #define CMP_SCR_CFF_SHIFT 1
emilmont 78:ed8466a608b4 393 #define CMP_SCR_CFR_MASK 0x4u
emilmont 78:ed8466a608b4 394 #define CMP_SCR_CFR_SHIFT 2
emilmont 78:ed8466a608b4 395 #define CMP_SCR_IEF_MASK 0x8u
emilmont 78:ed8466a608b4 396 #define CMP_SCR_IEF_SHIFT 3
emilmont 78:ed8466a608b4 397 #define CMP_SCR_IER_MASK 0x10u
emilmont 78:ed8466a608b4 398 #define CMP_SCR_IER_SHIFT 4
emilmont 78:ed8466a608b4 399 #define CMP_SCR_DMAEN_MASK 0x40u
emilmont 78:ed8466a608b4 400 #define CMP_SCR_DMAEN_SHIFT 6
emilmont 78:ed8466a608b4 401 /* DACCR Bit Fields */
emilmont 78:ed8466a608b4 402 #define CMP_DACCR_VOSEL_MASK 0x3Fu
emilmont 78:ed8466a608b4 403 #define CMP_DACCR_VOSEL_SHIFT 0
emilmont 78:ed8466a608b4 404 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
emilmont 78:ed8466a608b4 405 #define CMP_DACCR_VRSEL_MASK 0x40u
emilmont 78:ed8466a608b4 406 #define CMP_DACCR_VRSEL_SHIFT 6
emilmont 78:ed8466a608b4 407 #define CMP_DACCR_DACEN_MASK 0x80u
emilmont 78:ed8466a608b4 408 #define CMP_DACCR_DACEN_SHIFT 7
emilmont 78:ed8466a608b4 409 /* MUXCR Bit Fields */
emilmont 78:ed8466a608b4 410 #define CMP_MUXCR_MSEL_MASK 0x7u
emilmont 78:ed8466a608b4 411 #define CMP_MUXCR_MSEL_SHIFT 0
emilmont 78:ed8466a608b4 412 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
emilmont 78:ed8466a608b4 413 #define CMP_MUXCR_PSEL_MASK 0x38u
emilmont 78:ed8466a608b4 414 #define CMP_MUXCR_PSEL_SHIFT 3
emilmont 78:ed8466a608b4 415 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
emilmont 78:ed8466a608b4 416 #define CMP_MUXCR_PSTM_MASK 0x80u
emilmont 78:ed8466a608b4 417 #define CMP_MUXCR_PSTM_SHIFT 7
emilmont 78:ed8466a608b4 418
emilmont 78:ed8466a608b4 419 /**
emilmont 78:ed8466a608b4 420 * @}
emilmont 78:ed8466a608b4 421 */ /* end of group CMP_Register_Masks */
emilmont 78:ed8466a608b4 422
emilmont 78:ed8466a608b4 423
emilmont 78:ed8466a608b4 424 /* CMP - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 425 /** Peripheral CMP0 base address */
emilmont 78:ed8466a608b4 426 #define CMP0_BASE (0x40073000u)
emilmont 78:ed8466a608b4 427 /** Peripheral CMP0 base pointer */
emilmont 78:ed8466a608b4 428 #define CMP0 ((CMP_Type *)CMP0_BASE)
emilmont 78:ed8466a608b4 429 /** Array initializer of CMP peripheral base pointers */
emilmont 78:ed8466a608b4 430 #define CMP_BASES { CMP0 }
emilmont 78:ed8466a608b4 431
emilmont 78:ed8466a608b4 432 /**
emilmont 78:ed8466a608b4 433 * @}
emilmont 78:ed8466a608b4 434 */ /* end of group CMP_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 435
emilmont 78:ed8466a608b4 436
emilmont 78:ed8466a608b4 437 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 438 -- DAC Peripheral Access Layer
emilmont 78:ed8466a608b4 439 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 440
emilmont 78:ed8466a608b4 441 /**
emilmont 78:ed8466a608b4 442 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
emilmont 78:ed8466a608b4 443 * @{
emilmont 78:ed8466a608b4 444 */
emilmont 78:ed8466a608b4 445
emilmont 78:ed8466a608b4 446 /** DAC - Register Layout Typedef */
emilmont 78:ed8466a608b4 447 typedef struct {
emilmont 78:ed8466a608b4 448 struct { /* offset: 0x0, array step: 0x2 */
emilmont 78:ed8466a608b4 449 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
emilmont 78:ed8466a608b4 450 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
emilmont 78:ed8466a608b4 451 } DAT[2];
emilmont 78:ed8466a608b4 452 uint8_t RESERVED_0[28];
emilmont 78:ed8466a608b4 453 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
emilmont 78:ed8466a608b4 454 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
emilmont 78:ed8466a608b4 455 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
emilmont 78:ed8466a608b4 456 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
emilmont 78:ed8466a608b4 457 } DAC_Type;
emilmont 78:ed8466a608b4 458
emilmont 78:ed8466a608b4 459 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 460 -- DAC Register Masks
emilmont 78:ed8466a608b4 461 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 462
emilmont 78:ed8466a608b4 463 /**
emilmont 78:ed8466a608b4 464 * @addtogroup DAC_Register_Masks DAC Register Masks
emilmont 78:ed8466a608b4 465 * @{
emilmont 78:ed8466a608b4 466 */
emilmont 78:ed8466a608b4 467
emilmont 78:ed8466a608b4 468 /* DATL Bit Fields */
emilmont 78:ed8466a608b4 469 #define DAC_DATL_DATA0_MASK 0xFFu
emilmont 78:ed8466a608b4 470 #define DAC_DATL_DATA0_SHIFT 0
emilmont 78:ed8466a608b4 471 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
emilmont 78:ed8466a608b4 472 /* DATH Bit Fields */
emilmont 78:ed8466a608b4 473 #define DAC_DATH_DATA1_MASK 0xFu
emilmont 78:ed8466a608b4 474 #define DAC_DATH_DATA1_SHIFT 0
emilmont 78:ed8466a608b4 475 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
emilmont 78:ed8466a608b4 476 /* SR Bit Fields */
emilmont 78:ed8466a608b4 477 #define DAC_SR_DACBFRPBF_MASK 0x1u
emilmont 78:ed8466a608b4 478 #define DAC_SR_DACBFRPBF_SHIFT 0
emilmont 78:ed8466a608b4 479 #define DAC_SR_DACBFRPTF_MASK 0x2u
emilmont 78:ed8466a608b4 480 #define DAC_SR_DACBFRPTF_SHIFT 1
emilmont 78:ed8466a608b4 481 /* C0 Bit Fields */
emilmont 78:ed8466a608b4 482 #define DAC_C0_DACBBIEN_MASK 0x1u
emilmont 78:ed8466a608b4 483 #define DAC_C0_DACBBIEN_SHIFT 0
emilmont 78:ed8466a608b4 484 #define DAC_C0_DACBTIEN_MASK 0x2u
emilmont 78:ed8466a608b4 485 #define DAC_C0_DACBTIEN_SHIFT 1
emilmont 78:ed8466a608b4 486 #define DAC_C0_LPEN_MASK 0x8u
emilmont 78:ed8466a608b4 487 #define DAC_C0_LPEN_SHIFT 3
emilmont 78:ed8466a608b4 488 #define DAC_C0_DACSWTRG_MASK 0x10u
emilmont 78:ed8466a608b4 489 #define DAC_C0_DACSWTRG_SHIFT 4
emilmont 78:ed8466a608b4 490 #define DAC_C0_DACTRGSEL_MASK 0x20u
emilmont 78:ed8466a608b4 491 #define DAC_C0_DACTRGSEL_SHIFT 5
emilmont 78:ed8466a608b4 492 #define DAC_C0_DACRFS_MASK 0x40u
emilmont 78:ed8466a608b4 493 #define DAC_C0_DACRFS_SHIFT 6
emilmont 78:ed8466a608b4 494 #define DAC_C0_DACEN_MASK 0x80u
emilmont 78:ed8466a608b4 495 #define DAC_C0_DACEN_SHIFT 7
emilmont 78:ed8466a608b4 496 /* C1 Bit Fields */
emilmont 78:ed8466a608b4 497 #define DAC_C1_DACBFEN_MASK 0x1u
emilmont 78:ed8466a608b4 498 #define DAC_C1_DACBFEN_SHIFT 0
emilmont 78:ed8466a608b4 499 #define DAC_C1_DACBFMD_MASK 0x4u
emilmont 78:ed8466a608b4 500 #define DAC_C1_DACBFMD_SHIFT 2
emilmont 78:ed8466a608b4 501 #define DAC_C1_DMAEN_MASK 0x80u
emilmont 78:ed8466a608b4 502 #define DAC_C1_DMAEN_SHIFT 7
emilmont 78:ed8466a608b4 503 /* C2 Bit Fields */
emilmont 78:ed8466a608b4 504 #define DAC_C2_DACBFUP_MASK 0x1u
emilmont 78:ed8466a608b4 505 #define DAC_C2_DACBFUP_SHIFT 0
emilmont 78:ed8466a608b4 506 #define DAC_C2_DACBFRP_MASK 0x10u
emilmont 78:ed8466a608b4 507 #define DAC_C2_DACBFRP_SHIFT 4
emilmont 78:ed8466a608b4 508
emilmont 78:ed8466a608b4 509 /**
emilmont 78:ed8466a608b4 510 * @}
emilmont 78:ed8466a608b4 511 */ /* end of group DAC_Register_Masks */
emilmont 78:ed8466a608b4 512
emilmont 78:ed8466a608b4 513
emilmont 78:ed8466a608b4 514 /* DAC - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 515 /** Peripheral DAC0 base address */
emilmont 78:ed8466a608b4 516 #define DAC0_BASE (0x4003F000u)
emilmont 78:ed8466a608b4 517 /** Peripheral DAC0 base pointer */
emilmont 78:ed8466a608b4 518 #define DAC0 ((DAC_Type *)DAC0_BASE)
emilmont 78:ed8466a608b4 519 /** Array initializer of DAC peripheral base pointers */
emilmont 78:ed8466a608b4 520 #define DAC_BASES { DAC0 }
emilmont 78:ed8466a608b4 521
emilmont 78:ed8466a608b4 522 /**
emilmont 78:ed8466a608b4 523 * @}
emilmont 78:ed8466a608b4 524 */ /* end of group DAC_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 525
emilmont 78:ed8466a608b4 526
emilmont 78:ed8466a608b4 527 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 528 -- DMA Peripheral Access Layer
emilmont 78:ed8466a608b4 529 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 530
emilmont 78:ed8466a608b4 531 /**
emilmont 78:ed8466a608b4 532 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
emilmont 78:ed8466a608b4 533 * @{
emilmont 78:ed8466a608b4 534 */
emilmont 78:ed8466a608b4 535
emilmont 78:ed8466a608b4 536 /** DMA - Register Layout Typedef */
emilmont 78:ed8466a608b4 537 typedef struct {
emilmont 78:ed8466a608b4 538 uint8_t RESERVED_0[256];
emilmont 78:ed8466a608b4 539 struct { /* offset: 0x100, array step: 0x10 */
emilmont 78:ed8466a608b4 540 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
emilmont 78:ed8466a608b4 541 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
emilmont 78:ed8466a608b4 542 union { /* offset: 0x108, array step: 0x10 */
emilmont 78:ed8466a608b4 543 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
emilmont 78:ed8466a608b4 544 struct { /* offset: 0x108, array step: 0x10 */
emilmont 78:ed8466a608b4 545 uint8_t RESERVED_0[3];
emilmont 78:ed8466a608b4 546 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
emilmont 78:ed8466a608b4 547 } DMA_DSR_ACCESS8BIT;
emilmont 78:ed8466a608b4 548 };
emilmont 78:ed8466a608b4 549 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
emilmont 78:ed8466a608b4 550 } DMA[4];
emilmont 78:ed8466a608b4 551 } DMA_Type;
emilmont 78:ed8466a608b4 552
emilmont 78:ed8466a608b4 553 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 554 -- DMA Register Masks
emilmont 78:ed8466a608b4 555 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 556
emilmont 78:ed8466a608b4 557 /**
emilmont 78:ed8466a608b4 558 * @addtogroup DMA_Register_Masks DMA Register Masks
emilmont 78:ed8466a608b4 559 * @{
emilmont 78:ed8466a608b4 560 */
emilmont 78:ed8466a608b4 561
emilmont 78:ed8466a608b4 562 /* SAR Bit Fields */
emilmont 78:ed8466a608b4 563 #define DMA_SAR_SAR_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 564 #define DMA_SAR_SAR_SHIFT 0
emilmont 78:ed8466a608b4 565 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
emilmont 78:ed8466a608b4 566 /* DAR Bit Fields */
emilmont 78:ed8466a608b4 567 #define DMA_DAR_DAR_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 568 #define DMA_DAR_DAR_SHIFT 0
emilmont 78:ed8466a608b4 569 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
emilmont 78:ed8466a608b4 570 /* DSR_BCR Bit Fields */
emilmont 78:ed8466a608b4 571 #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
emilmont 78:ed8466a608b4 572 #define DMA_DSR_BCR_BCR_SHIFT 0
emilmont 78:ed8466a608b4 573 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
emilmont 78:ed8466a608b4 574 #define DMA_DSR_BCR_DONE_MASK 0x1000000u
emilmont 78:ed8466a608b4 575 #define DMA_DSR_BCR_DONE_SHIFT 24
emilmont 78:ed8466a608b4 576 #define DMA_DSR_BCR_BSY_MASK 0x2000000u
emilmont 78:ed8466a608b4 577 #define DMA_DSR_BCR_BSY_SHIFT 25
emilmont 78:ed8466a608b4 578 #define DMA_DSR_BCR_REQ_MASK 0x4000000u
emilmont 78:ed8466a608b4 579 #define DMA_DSR_BCR_REQ_SHIFT 26
emilmont 78:ed8466a608b4 580 #define DMA_DSR_BCR_BED_MASK 0x10000000u
emilmont 78:ed8466a608b4 581 #define DMA_DSR_BCR_BED_SHIFT 28
emilmont 78:ed8466a608b4 582 #define DMA_DSR_BCR_BES_MASK 0x20000000u
emilmont 78:ed8466a608b4 583 #define DMA_DSR_BCR_BES_SHIFT 29
emilmont 78:ed8466a608b4 584 #define DMA_DSR_BCR_CE_MASK 0x40000000u
emilmont 78:ed8466a608b4 585 #define DMA_DSR_BCR_CE_SHIFT 30
emilmont 78:ed8466a608b4 586 /* DCR Bit Fields */
emilmont 78:ed8466a608b4 587 #define DMA_DCR_LCH2_MASK 0x3u
emilmont 78:ed8466a608b4 588 #define DMA_DCR_LCH2_SHIFT 0
emilmont 78:ed8466a608b4 589 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
emilmont 78:ed8466a608b4 590 #define DMA_DCR_LCH1_MASK 0xCu
emilmont 78:ed8466a608b4 591 #define DMA_DCR_LCH1_SHIFT 2
emilmont 78:ed8466a608b4 592 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
emilmont 78:ed8466a608b4 593 #define DMA_DCR_LINKCC_MASK 0x30u
emilmont 78:ed8466a608b4 594 #define DMA_DCR_LINKCC_SHIFT 4
emilmont 78:ed8466a608b4 595 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
emilmont 78:ed8466a608b4 596 #define DMA_DCR_D_REQ_MASK 0x80u
emilmont 78:ed8466a608b4 597 #define DMA_DCR_D_REQ_SHIFT 7
emilmont 78:ed8466a608b4 598 #define DMA_DCR_DMOD_MASK 0xF00u
emilmont 78:ed8466a608b4 599 #define DMA_DCR_DMOD_SHIFT 8
emilmont 78:ed8466a608b4 600 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
emilmont 78:ed8466a608b4 601 #define DMA_DCR_SMOD_MASK 0xF000u
emilmont 78:ed8466a608b4 602 #define DMA_DCR_SMOD_SHIFT 12
emilmont 78:ed8466a608b4 603 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
emilmont 78:ed8466a608b4 604 #define DMA_DCR_START_MASK 0x10000u
emilmont 78:ed8466a608b4 605 #define DMA_DCR_START_SHIFT 16
emilmont 78:ed8466a608b4 606 #define DMA_DCR_DSIZE_MASK 0x60000u
emilmont 78:ed8466a608b4 607 #define DMA_DCR_DSIZE_SHIFT 17
emilmont 78:ed8466a608b4 608 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
emilmont 78:ed8466a608b4 609 #define DMA_DCR_DINC_MASK 0x80000u
emilmont 78:ed8466a608b4 610 #define DMA_DCR_DINC_SHIFT 19
emilmont 78:ed8466a608b4 611 #define DMA_DCR_SSIZE_MASK 0x300000u
emilmont 78:ed8466a608b4 612 #define DMA_DCR_SSIZE_SHIFT 20
emilmont 78:ed8466a608b4 613 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
emilmont 78:ed8466a608b4 614 #define DMA_DCR_SINC_MASK 0x400000u
emilmont 78:ed8466a608b4 615 #define DMA_DCR_SINC_SHIFT 22
emilmont 78:ed8466a608b4 616 #define DMA_DCR_EADREQ_MASK 0x800000u
emilmont 78:ed8466a608b4 617 #define DMA_DCR_EADREQ_SHIFT 23
emilmont 78:ed8466a608b4 618 #define DMA_DCR_AA_MASK 0x10000000u
emilmont 78:ed8466a608b4 619 #define DMA_DCR_AA_SHIFT 28
emilmont 78:ed8466a608b4 620 #define DMA_DCR_CS_MASK 0x20000000u
emilmont 78:ed8466a608b4 621 #define DMA_DCR_CS_SHIFT 29
emilmont 78:ed8466a608b4 622 #define DMA_DCR_ERQ_MASK 0x40000000u
emilmont 78:ed8466a608b4 623 #define DMA_DCR_ERQ_SHIFT 30
emilmont 78:ed8466a608b4 624 #define DMA_DCR_EINT_MASK 0x80000000u
emilmont 78:ed8466a608b4 625 #define DMA_DCR_EINT_SHIFT 31
emilmont 78:ed8466a608b4 626
emilmont 78:ed8466a608b4 627 /**
emilmont 78:ed8466a608b4 628 * @}
emilmont 78:ed8466a608b4 629 */ /* end of group DMA_Register_Masks */
emilmont 78:ed8466a608b4 630
emilmont 78:ed8466a608b4 631
emilmont 78:ed8466a608b4 632 /* DMA - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 633 /** Peripheral DMA base address */
emilmont 78:ed8466a608b4 634 #define DMA_BASE (0x40008000u)
emilmont 78:ed8466a608b4 635 /** Peripheral DMA base pointer */
emilmont 78:ed8466a608b4 636 #define DMA0 ((DMA_Type *)DMA_BASE)
emilmont 78:ed8466a608b4 637 /** Array initializer of DMA peripheral base pointers */
emilmont 78:ed8466a608b4 638 #define DMA_BASES { DMA0 }
emilmont 78:ed8466a608b4 639
emilmont 78:ed8466a608b4 640 /**
emilmont 78:ed8466a608b4 641 * @}
emilmont 78:ed8466a608b4 642 */ /* end of group DMA_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 643
emilmont 78:ed8466a608b4 644
emilmont 78:ed8466a608b4 645 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 646 -- DMAMUX Peripheral Access Layer
emilmont 78:ed8466a608b4 647 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 648
emilmont 78:ed8466a608b4 649 /**
emilmont 78:ed8466a608b4 650 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
emilmont 78:ed8466a608b4 651 * @{
emilmont 78:ed8466a608b4 652 */
emilmont 78:ed8466a608b4 653
emilmont 78:ed8466a608b4 654 /** DMAMUX - Register Layout Typedef */
emilmont 78:ed8466a608b4 655 typedef struct {
emilmont 78:ed8466a608b4 656 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
emilmont 78:ed8466a608b4 657 } DMAMUX_Type;
emilmont 78:ed8466a608b4 658
emilmont 78:ed8466a608b4 659 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 660 -- DMAMUX Register Masks
emilmont 78:ed8466a608b4 661 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 662
emilmont 78:ed8466a608b4 663 /**
emilmont 78:ed8466a608b4 664 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
emilmont 78:ed8466a608b4 665 * @{
emilmont 78:ed8466a608b4 666 */
emilmont 78:ed8466a608b4 667
emilmont 78:ed8466a608b4 668 /* CHCFG Bit Fields */
emilmont 78:ed8466a608b4 669 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
emilmont 78:ed8466a608b4 670 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
emilmont 78:ed8466a608b4 671 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
emilmont 78:ed8466a608b4 672 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
emilmont 78:ed8466a608b4 673 #define DMAMUX_CHCFG_TRIG_SHIFT 6
emilmont 78:ed8466a608b4 674 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
emilmont 78:ed8466a608b4 675 #define DMAMUX_CHCFG_ENBL_SHIFT 7
emilmont 78:ed8466a608b4 676
emilmont 78:ed8466a608b4 677 /**
emilmont 78:ed8466a608b4 678 * @}
emilmont 78:ed8466a608b4 679 */ /* end of group DMAMUX_Register_Masks */
emilmont 78:ed8466a608b4 680
emilmont 78:ed8466a608b4 681
emilmont 78:ed8466a608b4 682 /* DMAMUX - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 683 /** Peripheral DMAMUX0 base address */
emilmont 78:ed8466a608b4 684 #define DMAMUX0_BASE (0x40021000u)
emilmont 78:ed8466a608b4 685 /** Peripheral DMAMUX0 base pointer */
emilmont 78:ed8466a608b4 686 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
emilmont 78:ed8466a608b4 687 /** Array initializer of DMAMUX peripheral base pointers */
emilmont 78:ed8466a608b4 688 #define DMAMUX_BASES { DMAMUX0 }
emilmont 78:ed8466a608b4 689
emilmont 78:ed8466a608b4 690 /**
emilmont 78:ed8466a608b4 691 * @}
emilmont 78:ed8466a608b4 692 */ /* end of group DMAMUX_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 693
emilmont 78:ed8466a608b4 694
emilmont 78:ed8466a608b4 695 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 696 -- FGPIO Peripheral Access Layer
emilmont 78:ed8466a608b4 697 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 698
emilmont 78:ed8466a608b4 699 /**
emilmont 78:ed8466a608b4 700 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
emilmont 78:ed8466a608b4 701 * @{
emilmont 78:ed8466a608b4 702 */
emilmont 78:ed8466a608b4 703
emilmont 78:ed8466a608b4 704 /** FGPIO - Register Layout Typedef */
emilmont 78:ed8466a608b4 705 typedef struct {
emilmont 78:ed8466a608b4 706 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
emilmont 78:ed8466a608b4 707 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
emilmont 78:ed8466a608b4 708 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
emilmont 78:ed8466a608b4 709 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
emilmont 78:ed8466a608b4 710 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
emilmont 78:ed8466a608b4 711 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
emilmont 78:ed8466a608b4 712 } FGPIO_Type;
emilmont 78:ed8466a608b4 713
emilmont 78:ed8466a608b4 714 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 715 -- FGPIO Register Masks
emilmont 78:ed8466a608b4 716 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 717
emilmont 78:ed8466a608b4 718 /**
emilmont 78:ed8466a608b4 719 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
emilmont 78:ed8466a608b4 720 * @{
emilmont 78:ed8466a608b4 721 */
emilmont 78:ed8466a608b4 722
emilmont 78:ed8466a608b4 723 /* PDOR Bit Fields */
emilmont 78:ed8466a608b4 724 #define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 725 #define FGPIO_PDOR_PDO_SHIFT 0
emilmont 78:ed8466a608b4 726 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
emilmont 78:ed8466a608b4 727 /* PSOR Bit Fields */
emilmont 78:ed8466a608b4 728 #define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 729 #define FGPIO_PSOR_PTSO_SHIFT 0
emilmont 78:ed8466a608b4 730 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
emilmont 78:ed8466a608b4 731 /* PCOR Bit Fields */
emilmont 78:ed8466a608b4 732 #define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 733 #define FGPIO_PCOR_PTCO_SHIFT 0
emilmont 78:ed8466a608b4 734 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
emilmont 78:ed8466a608b4 735 /* PTOR Bit Fields */
emilmont 78:ed8466a608b4 736 #define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 737 #define FGPIO_PTOR_PTTO_SHIFT 0
emilmont 78:ed8466a608b4 738 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
emilmont 78:ed8466a608b4 739 /* PDIR Bit Fields */
emilmont 78:ed8466a608b4 740 #define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 741 #define FGPIO_PDIR_PDI_SHIFT 0
emilmont 78:ed8466a608b4 742 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
emilmont 78:ed8466a608b4 743 /* PDDR Bit Fields */
emilmont 78:ed8466a608b4 744 #define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 745 #define FGPIO_PDDR_PDD_SHIFT 0
emilmont 78:ed8466a608b4 746 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
emilmont 78:ed8466a608b4 747
emilmont 78:ed8466a608b4 748 /**
emilmont 78:ed8466a608b4 749 * @}
emilmont 78:ed8466a608b4 750 */ /* end of group FGPIO_Register_Masks */
emilmont 78:ed8466a608b4 751
emilmont 78:ed8466a608b4 752
emilmont 78:ed8466a608b4 753 /* FGPIO - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 754 /** Peripheral FPTA base address */
emilmont 78:ed8466a608b4 755 #define FPTA_BASE (0xF80FF000u)
emilmont 78:ed8466a608b4 756 /** Peripheral FPTA base pointer */
emilmont 78:ed8466a608b4 757 #define FPTA ((FGPIO_Type *)FPTA_BASE)
emilmont 78:ed8466a608b4 758 /** Peripheral FPTB base address */
emilmont 78:ed8466a608b4 759 #define FPTB_BASE (0xF80FF040u)
emilmont 78:ed8466a608b4 760 /** Peripheral FPTB base pointer */
emilmont 78:ed8466a608b4 761 #define FPTB ((FGPIO_Type *)FPTB_BASE)
emilmont 78:ed8466a608b4 762 /** Array initializer of FGPIO peripheral base pointers */
emilmont 78:ed8466a608b4 763 #define FGPIO_BASES { FPTA, FPTB }
emilmont 78:ed8466a608b4 764
emilmont 78:ed8466a608b4 765 /**
emilmont 78:ed8466a608b4 766 * @}
emilmont 78:ed8466a608b4 767 */ /* end of group FGPIO_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 768
emilmont 78:ed8466a608b4 769
emilmont 78:ed8466a608b4 770 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 771 -- FTFA Peripheral Access Layer
emilmont 78:ed8466a608b4 772 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 773
emilmont 78:ed8466a608b4 774 /**
emilmont 78:ed8466a608b4 775 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
emilmont 78:ed8466a608b4 776 * @{
emilmont 78:ed8466a608b4 777 */
emilmont 78:ed8466a608b4 778
emilmont 78:ed8466a608b4 779 /** FTFA - Register Layout Typedef */
emilmont 78:ed8466a608b4 780 typedef struct {
emilmont 78:ed8466a608b4 781 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
emilmont 78:ed8466a608b4 782 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
emilmont 78:ed8466a608b4 783 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
emilmont 78:ed8466a608b4 784 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
emilmont 78:ed8466a608b4 785 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
emilmont 78:ed8466a608b4 786 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
emilmont 78:ed8466a608b4 787 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
emilmont 78:ed8466a608b4 788 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
emilmont 78:ed8466a608b4 789 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
emilmont 78:ed8466a608b4 790 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
emilmont 78:ed8466a608b4 791 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
emilmont 78:ed8466a608b4 792 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
emilmont 78:ed8466a608b4 793 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
emilmont 78:ed8466a608b4 794 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
emilmont 78:ed8466a608b4 795 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
emilmont 78:ed8466a608b4 796 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
emilmont 78:ed8466a608b4 797 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
emilmont 78:ed8466a608b4 798 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
emilmont 78:ed8466a608b4 799 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
emilmont 78:ed8466a608b4 800 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
emilmont 78:ed8466a608b4 801 } FTFA_Type;
emilmont 78:ed8466a608b4 802
emilmont 78:ed8466a608b4 803 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 804 -- FTFA Register Masks
emilmont 78:ed8466a608b4 805 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 806
emilmont 78:ed8466a608b4 807 /**
emilmont 78:ed8466a608b4 808 * @addtogroup FTFA_Register_Masks FTFA Register Masks
emilmont 78:ed8466a608b4 809 * @{
emilmont 78:ed8466a608b4 810 */
emilmont 78:ed8466a608b4 811
emilmont 78:ed8466a608b4 812 /* FSTAT Bit Fields */
emilmont 78:ed8466a608b4 813 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u
emilmont 78:ed8466a608b4 814 #define FTFA_FSTAT_MGSTAT0_SHIFT 0
emilmont 78:ed8466a608b4 815 #define FTFA_FSTAT_FPVIOL_MASK 0x10u
emilmont 78:ed8466a608b4 816 #define FTFA_FSTAT_FPVIOL_SHIFT 4
emilmont 78:ed8466a608b4 817 #define FTFA_FSTAT_ACCERR_MASK 0x20u
emilmont 78:ed8466a608b4 818 #define FTFA_FSTAT_ACCERR_SHIFT 5
emilmont 78:ed8466a608b4 819 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u
emilmont 78:ed8466a608b4 820 #define FTFA_FSTAT_RDCOLERR_SHIFT 6
emilmont 78:ed8466a608b4 821 #define FTFA_FSTAT_CCIF_MASK 0x80u
emilmont 78:ed8466a608b4 822 #define FTFA_FSTAT_CCIF_SHIFT 7
emilmont 78:ed8466a608b4 823 /* FCNFG Bit Fields */
emilmont 78:ed8466a608b4 824 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u
emilmont 78:ed8466a608b4 825 #define FTFA_FCNFG_ERSSUSP_SHIFT 4
emilmont 78:ed8466a608b4 826 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u
emilmont 78:ed8466a608b4 827 #define FTFA_FCNFG_ERSAREQ_SHIFT 5
emilmont 78:ed8466a608b4 828 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
emilmont 78:ed8466a608b4 829 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6
emilmont 78:ed8466a608b4 830 #define FTFA_FCNFG_CCIE_MASK 0x80u
emilmont 78:ed8466a608b4 831 #define FTFA_FCNFG_CCIE_SHIFT 7
emilmont 78:ed8466a608b4 832 /* FSEC Bit Fields */
emilmont 78:ed8466a608b4 833 #define FTFA_FSEC_SEC_MASK 0x3u
emilmont 78:ed8466a608b4 834 #define FTFA_FSEC_SEC_SHIFT 0
emilmont 78:ed8466a608b4 835 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
emilmont 78:ed8466a608b4 836 #define FTFA_FSEC_FSLACC_MASK 0xCu
emilmont 78:ed8466a608b4 837 #define FTFA_FSEC_FSLACC_SHIFT 2
emilmont 78:ed8466a608b4 838 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
emilmont 78:ed8466a608b4 839 #define FTFA_FSEC_MEEN_MASK 0x30u
emilmont 78:ed8466a608b4 840 #define FTFA_FSEC_MEEN_SHIFT 4
emilmont 78:ed8466a608b4 841 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
emilmont 78:ed8466a608b4 842 #define FTFA_FSEC_KEYEN_MASK 0xC0u
emilmont 78:ed8466a608b4 843 #define FTFA_FSEC_KEYEN_SHIFT 6
emilmont 78:ed8466a608b4 844 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
emilmont 78:ed8466a608b4 845 /* FOPT Bit Fields */
emilmont 78:ed8466a608b4 846 #define FTFA_FOPT_OPT_MASK 0xFFu
emilmont 78:ed8466a608b4 847 #define FTFA_FOPT_OPT_SHIFT 0
emilmont 78:ed8466a608b4 848 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
emilmont 78:ed8466a608b4 849 /* FCCOB3 Bit Fields */
emilmont 78:ed8466a608b4 850 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu
emilmont 78:ed8466a608b4 851 #define FTFA_FCCOB3_CCOBn_SHIFT 0
emilmont 78:ed8466a608b4 852 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
emilmont 78:ed8466a608b4 853 /* FCCOB2 Bit Fields */
emilmont 78:ed8466a608b4 854 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu
emilmont 78:ed8466a608b4 855 #define FTFA_FCCOB2_CCOBn_SHIFT 0
emilmont 78:ed8466a608b4 856 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
emilmont 78:ed8466a608b4 857 /* FCCOB1 Bit Fields */
emilmont 78:ed8466a608b4 858 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu
emilmont 78:ed8466a608b4 859 #define FTFA_FCCOB1_CCOBn_SHIFT 0
emilmont 78:ed8466a608b4 860 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
emilmont 78:ed8466a608b4 861 /* FCCOB0 Bit Fields */
emilmont 78:ed8466a608b4 862 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu
emilmont 78:ed8466a608b4 863 #define FTFA_FCCOB0_CCOBn_SHIFT 0
emilmont 78:ed8466a608b4 864 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
emilmont 78:ed8466a608b4 865 /* FCCOB7 Bit Fields */
emilmont 78:ed8466a608b4 866 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu
emilmont 78:ed8466a608b4 867 #define FTFA_FCCOB7_CCOBn_SHIFT 0
emilmont 78:ed8466a608b4 868 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
emilmont 78:ed8466a608b4 869 /* FCCOB6 Bit Fields */
emilmont 78:ed8466a608b4 870 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu
emilmont 78:ed8466a608b4 871 #define FTFA_FCCOB6_CCOBn_SHIFT 0
emilmont 78:ed8466a608b4 872 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
emilmont 78:ed8466a608b4 873 /* FCCOB5 Bit Fields */
emilmont 78:ed8466a608b4 874 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu
emilmont 78:ed8466a608b4 875 #define FTFA_FCCOB5_CCOBn_SHIFT 0
emilmont 78:ed8466a608b4 876 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
emilmont 78:ed8466a608b4 877 /* FCCOB4 Bit Fields */
emilmont 78:ed8466a608b4 878 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu
emilmont 78:ed8466a608b4 879 #define FTFA_FCCOB4_CCOBn_SHIFT 0
emilmont 78:ed8466a608b4 880 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
emilmont 78:ed8466a608b4 881 /* FCCOBB Bit Fields */
emilmont 78:ed8466a608b4 882 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu
emilmont 78:ed8466a608b4 883 #define FTFA_FCCOBB_CCOBn_SHIFT 0
emilmont 78:ed8466a608b4 884 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
emilmont 78:ed8466a608b4 885 /* FCCOBA Bit Fields */
emilmont 78:ed8466a608b4 886 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu
emilmont 78:ed8466a608b4 887 #define FTFA_FCCOBA_CCOBn_SHIFT 0
emilmont 78:ed8466a608b4 888 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
emilmont 78:ed8466a608b4 889 /* FCCOB9 Bit Fields */
emilmont 78:ed8466a608b4 890 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu
emilmont 78:ed8466a608b4 891 #define FTFA_FCCOB9_CCOBn_SHIFT 0
emilmont 78:ed8466a608b4 892 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
emilmont 78:ed8466a608b4 893 /* FCCOB8 Bit Fields */
emilmont 78:ed8466a608b4 894 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu
emilmont 78:ed8466a608b4 895 #define FTFA_FCCOB8_CCOBn_SHIFT 0
emilmont 78:ed8466a608b4 896 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
emilmont 78:ed8466a608b4 897 /* FPROT3 Bit Fields */
emilmont 78:ed8466a608b4 898 #define FTFA_FPROT3_PROT_MASK 0xFFu
emilmont 78:ed8466a608b4 899 #define FTFA_FPROT3_PROT_SHIFT 0
emilmont 78:ed8466a608b4 900 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
emilmont 78:ed8466a608b4 901 /* FPROT2 Bit Fields */
emilmont 78:ed8466a608b4 902 #define FTFA_FPROT2_PROT_MASK 0xFFu
emilmont 78:ed8466a608b4 903 #define FTFA_FPROT2_PROT_SHIFT 0
emilmont 78:ed8466a608b4 904 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
emilmont 78:ed8466a608b4 905 /* FPROT1 Bit Fields */
emilmont 78:ed8466a608b4 906 #define FTFA_FPROT1_PROT_MASK 0xFFu
emilmont 78:ed8466a608b4 907 #define FTFA_FPROT1_PROT_SHIFT 0
emilmont 78:ed8466a608b4 908 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
emilmont 78:ed8466a608b4 909 /* FPROT0 Bit Fields */
emilmont 78:ed8466a608b4 910 #define FTFA_FPROT0_PROT_MASK 0xFFu
emilmont 78:ed8466a608b4 911 #define FTFA_FPROT0_PROT_SHIFT 0
emilmont 78:ed8466a608b4 912 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
emilmont 78:ed8466a608b4 913
emilmont 78:ed8466a608b4 914 /**
emilmont 78:ed8466a608b4 915 * @}
emilmont 78:ed8466a608b4 916 */ /* end of group FTFA_Register_Masks */
emilmont 78:ed8466a608b4 917
emilmont 78:ed8466a608b4 918
emilmont 78:ed8466a608b4 919 /* FTFA - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 920 /** Peripheral FTFA base address */
emilmont 78:ed8466a608b4 921 #define FTFA_BASE (0x40020000u)
emilmont 78:ed8466a608b4 922 /** Peripheral FTFA base pointer */
emilmont 78:ed8466a608b4 923 #define FTFA ((FTFA_Type *)FTFA_BASE)
emilmont 78:ed8466a608b4 924 /** Array initializer of FTFA peripheral base pointers */
emilmont 78:ed8466a608b4 925 #define FTFA_BASES { FTFA }
emilmont 78:ed8466a608b4 926
emilmont 78:ed8466a608b4 927 /**
emilmont 78:ed8466a608b4 928 * @}
emilmont 78:ed8466a608b4 929 */ /* end of group FTFA_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 930
emilmont 78:ed8466a608b4 931
emilmont 78:ed8466a608b4 932 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 933 -- GPIO Peripheral Access Layer
emilmont 78:ed8466a608b4 934 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 935
emilmont 78:ed8466a608b4 936 /**
emilmont 78:ed8466a608b4 937 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
emilmont 78:ed8466a608b4 938 * @{
emilmont 78:ed8466a608b4 939 */
emilmont 78:ed8466a608b4 940
emilmont 78:ed8466a608b4 941 /** GPIO - Register Layout Typedef */
emilmont 78:ed8466a608b4 942 typedef struct {
emilmont 78:ed8466a608b4 943 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
emilmont 78:ed8466a608b4 944 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
emilmont 78:ed8466a608b4 945 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
emilmont 78:ed8466a608b4 946 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
emilmont 78:ed8466a608b4 947 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
emilmont 78:ed8466a608b4 948 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
emilmont 78:ed8466a608b4 949 } GPIO_Type;
emilmont 78:ed8466a608b4 950
emilmont 78:ed8466a608b4 951 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 952 -- GPIO Register Masks
emilmont 78:ed8466a608b4 953 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 954
emilmont 78:ed8466a608b4 955 /**
emilmont 78:ed8466a608b4 956 * @addtogroup GPIO_Register_Masks GPIO Register Masks
emilmont 78:ed8466a608b4 957 * @{
emilmont 78:ed8466a608b4 958 */
emilmont 78:ed8466a608b4 959
emilmont 78:ed8466a608b4 960 /* PDOR Bit Fields */
emilmont 78:ed8466a608b4 961 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 962 #define GPIO_PDOR_PDO_SHIFT 0
emilmont 78:ed8466a608b4 963 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
emilmont 78:ed8466a608b4 964 /* PSOR Bit Fields */
emilmont 78:ed8466a608b4 965 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 966 #define GPIO_PSOR_PTSO_SHIFT 0
emilmont 78:ed8466a608b4 967 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
emilmont 78:ed8466a608b4 968 /* PCOR Bit Fields */
emilmont 78:ed8466a608b4 969 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 970 #define GPIO_PCOR_PTCO_SHIFT 0
emilmont 78:ed8466a608b4 971 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
emilmont 78:ed8466a608b4 972 /* PTOR Bit Fields */
emilmont 78:ed8466a608b4 973 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 974 #define GPIO_PTOR_PTTO_SHIFT 0
emilmont 78:ed8466a608b4 975 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
emilmont 78:ed8466a608b4 976 /* PDIR Bit Fields */
emilmont 78:ed8466a608b4 977 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 978 #define GPIO_PDIR_PDI_SHIFT 0
emilmont 78:ed8466a608b4 979 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
emilmont 78:ed8466a608b4 980 /* PDDR Bit Fields */
emilmont 78:ed8466a608b4 981 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 982 #define GPIO_PDDR_PDD_SHIFT 0
emilmont 78:ed8466a608b4 983 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
emilmont 78:ed8466a608b4 984
emilmont 78:ed8466a608b4 985 /**
emilmont 78:ed8466a608b4 986 * @}
emilmont 78:ed8466a608b4 987 */ /* end of group GPIO_Register_Masks */
emilmont 78:ed8466a608b4 988
emilmont 78:ed8466a608b4 989
emilmont 78:ed8466a608b4 990 /* GPIO - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 991 /** Peripheral PTA base address */
emilmont 78:ed8466a608b4 992 #define PTA_BASE (0x400FF000u)
emilmont 78:ed8466a608b4 993 /** Peripheral PTA base pointer */
emilmont 78:ed8466a608b4 994 #define PTA ((GPIO_Type *)PTA_BASE)
emilmont 78:ed8466a608b4 995 /** Peripheral PTB base address */
emilmont 78:ed8466a608b4 996 #define PTB_BASE (0x400FF040u)
emilmont 78:ed8466a608b4 997 /** Peripheral PTB base pointer */
emilmont 78:ed8466a608b4 998 #define PTB ((GPIO_Type *)PTB_BASE)
emilmont 78:ed8466a608b4 999 /** Array initializer of GPIO peripheral base pointers */
emilmont 78:ed8466a608b4 1000 #define GPIO_BASES { PTA, PTB }
emilmont 78:ed8466a608b4 1001
emilmont 78:ed8466a608b4 1002 /**
emilmont 78:ed8466a608b4 1003 * @}
emilmont 78:ed8466a608b4 1004 */ /* end of group GPIO_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 1005
emilmont 78:ed8466a608b4 1006
emilmont 78:ed8466a608b4 1007 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 1008 -- I2C Peripheral Access Layer
emilmont 78:ed8466a608b4 1009 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 1010
emilmont 78:ed8466a608b4 1011 /**
emilmont 78:ed8466a608b4 1012 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
emilmont 78:ed8466a608b4 1013 * @{
emilmont 78:ed8466a608b4 1014 */
emilmont 78:ed8466a608b4 1015
emilmont 78:ed8466a608b4 1016 /** I2C - Register Layout Typedef */
emilmont 78:ed8466a608b4 1017 typedef struct {
emilmont 78:ed8466a608b4 1018 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
emilmont 78:ed8466a608b4 1019 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
emilmont 78:ed8466a608b4 1020 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
emilmont 78:ed8466a608b4 1021 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
emilmont 78:ed8466a608b4 1022 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
emilmont 78:ed8466a608b4 1023 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
emilmont 78:ed8466a608b4 1024 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
emilmont 78:ed8466a608b4 1025 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
emilmont 78:ed8466a608b4 1026 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
emilmont 78:ed8466a608b4 1027 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
emilmont 78:ed8466a608b4 1028 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
emilmont 78:ed8466a608b4 1029 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
emilmont 78:ed8466a608b4 1030 } I2C_Type;
emilmont 78:ed8466a608b4 1031
emilmont 78:ed8466a608b4 1032 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 1033 -- I2C Register Masks
emilmont 78:ed8466a608b4 1034 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 1035
emilmont 78:ed8466a608b4 1036 /**
emilmont 78:ed8466a608b4 1037 * @addtogroup I2C_Register_Masks I2C Register Masks
emilmont 78:ed8466a608b4 1038 * @{
emilmont 78:ed8466a608b4 1039 */
emilmont 78:ed8466a608b4 1040
emilmont 78:ed8466a608b4 1041 /* A1 Bit Fields */
emilmont 78:ed8466a608b4 1042 #define I2C_A1_AD_MASK 0xFEu
emilmont 78:ed8466a608b4 1043 #define I2C_A1_AD_SHIFT 1
emilmont 78:ed8466a608b4 1044 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
emilmont 78:ed8466a608b4 1045 /* F Bit Fields */
emilmont 78:ed8466a608b4 1046 #define I2C_F_ICR_MASK 0x3Fu
emilmont 78:ed8466a608b4 1047 #define I2C_F_ICR_SHIFT 0
emilmont 78:ed8466a608b4 1048 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
emilmont 78:ed8466a608b4 1049 #define I2C_F_MULT_MASK 0xC0u
emilmont 78:ed8466a608b4 1050 #define I2C_F_MULT_SHIFT 6
emilmont 78:ed8466a608b4 1051 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
emilmont 78:ed8466a608b4 1052 /* C1 Bit Fields */
emilmont 78:ed8466a608b4 1053 #define I2C_C1_DMAEN_MASK 0x1u
emilmont 78:ed8466a608b4 1054 #define I2C_C1_DMAEN_SHIFT 0
emilmont 78:ed8466a608b4 1055 #define I2C_C1_WUEN_MASK 0x2u
emilmont 78:ed8466a608b4 1056 #define I2C_C1_WUEN_SHIFT 1
emilmont 78:ed8466a608b4 1057 #define I2C_C1_RSTA_MASK 0x4u
emilmont 78:ed8466a608b4 1058 #define I2C_C1_RSTA_SHIFT 2
emilmont 78:ed8466a608b4 1059 #define I2C_C1_TXAK_MASK 0x8u
emilmont 78:ed8466a608b4 1060 #define I2C_C1_TXAK_SHIFT 3
emilmont 78:ed8466a608b4 1061 #define I2C_C1_TX_MASK 0x10u
emilmont 78:ed8466a608b4 1062 #define I2C_C1_TX_SHIFT 4
emilmont 78:ed8466a608b4 1063 #define I2C_C1_MST_MASK 0x20u
emilmont 78:ed8466a608b4 1064 #define I2C_C1_MST_SHIFT 5
emilmont 78:ed8466a608b4 1065 #define I2C_C1_IICIE_MASK 0x40u
emilmont 78:ed8466a608b4 1066 #define I2C_C1_IICIE_SHIFT 6
emilmont 78:ed8466a608b4 1067 #define I2C_C1_IICEN_MASK 0x80u
emilmont 78:ed8466a608b4 1068 #define I2C_C1_IICEN_SHIFT 7
emilmont 78:ed8466a608b4 1069 /* S Bit Fields */
emilmont 78:ed8466a608b4 1070 #define I2C_S_RXAK_MASK 0x1u
emilmont 78:ed8466a608b4 1071 #define I2C_S_RXAK_SHIFT 0
emilmont 78:ed8466a608b4 1072 #define I2C_S_IICIF_MASK 0x2u
emilmont 78:ed8466a608b4 1073 #define I2C_S_IICIF_SHIFT 1
emilmont 78:ed8466a608b4 1074 #define I2C_S_SRW_MASK 0x4u
emilmont 78:ed8466a608b4 1075 #define I2C_S_SRW_SHIFT 2
emilmont 78:ed8466a608b4 1076 #define I2C_S_RAM_MASK 0x8u
emilmont 78:ed8466a608b4 1077 #define I2C_S_RAM_SHIFT 3
emilmont 78:ed8466a608b4 1078 #define I2C_S_ARBL_MASK 0x10u
emilmont 78:ed8466a608b4 1079 #define I2C_S_ARBL_SHIFT 4
emilmont 78:ed8466a608b4 1080 #define I2C_S_BUSY_MASK 0x20u
emilmont 78:ed8466a608b4 1081 #define I2C_S_BUSY_SHIFT 5
emilmont 78:ed8466a608b4 1082 #define I2C_S_IAAS_MASK 0x40u
emilmont 78:ed8466a608b4 1083 #define I2C_S_IAAS_SHIFT 6
emilmont 78:ed8466a608b4 1084 #define I2C_S_TCF_MASK 0x80u
emilmont 78:ed8466a608b4 1085 #define I2C_S_TCF_SHIFT 7
emilmont 78:ed8466a608b4 1086 /* D Bit Fields */
emilmont 78:ed8466a608b4 1087 #define I2C_D_DATA_MASK 0xFFu
emilmont 78:ed8466a608b4 1088 #define I2C_D_DATA_SHIFT 0
emilmont 78:ed8466a608b4 1089 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
emilmont 78:ed8466a608b4 1090 /* C2 Bit Fields */
emilmont 78:ed8466a608b4 1091 #define I2C_C2_AD_MASK 0x7u
emilmont 78:ed8466a608b4 1092 #define I2C_C2_AD_SHIFT 0
emilmont 78:ed8466a608b4 1093 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
emilmont 78:ed8466a608b4 1094 #define I2C_C2_RMEN_MASK 0x8u
emilmont 78:ed8466a608b4 1095 #define I2C_C2_RMEN_SHIFT 3
emilmont 78:ed8466a608b4 1096 #define I2C_C2_SBRC_MASK 0x10u
emilmont 78:ed8466a608b4 1097 #define I2C_C2_SBRC_SHIFT 4
emilmont 78:ed8466a608b4 1098 #define I2C_C2_HDRS_MASK 0x20u
emilmont 78:ed8466a608b4 1099 #define I2C_C2_HDRS_SHIFT 5
emilmont 78:ed8466a608b4 1100 #define I2C_C2_ADEXT_MASK 0x40u
emilmont 78:ed8466a608b4 1101 #define I2C_C2_ADEXT_SHIFT 6
emilmont 78:ed8466a608b4 1102 #define I2C_C2_GCAEN_MASK 0x80u
emilmont 78:ed8466a608b4 1103 #define I2C_C2_GCAEN_SHIFT 7
emilmont 78:ed8466a608b4 1104 /* FLT Bit Fields */
emilmont 78:ed8466a608b4 1105 #define I2C_FLT_FLT_MASK 0x1Fu
emilmont 78:ed8466a608b4 1106 #define I2C_FLT_FLT_SHIFT 0
emilmont 78:ed8466a608b4 1107 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
emilmont 78:ed8466a608b4 1108 #define I2C_FLT_STOPIE_MASK 0x20u
emilmont 78:ed8466a608b4 1109 #define I2C_FLT_STOPIE_SHIFT 5
emilmont 78:ed8466a608b4 1110 #define I2C_FLT_STOPF_MASK 0x40u
emilmont 78:ed8466a608b4 1111 #define I2C_FLT_STOPF_SHIFT 6
emilmont 78:ed8466a608b4 1112 #define I2C_FLT_SHEN_MASK 0x80u
emilmont 78:ed8466a608b4 1113 #define I2C_FLT_SHEN_SHIFT 7
emilmont 78:ed8466a608b4 1114 /* RA Bit Fields */
emilmont 78:ed8466a608b4 1115 #define I2C_RA_RAD_MASK 0xFEu
emilmont 78:ed8466a608b4 1116 #define I2C_RA_RAD_SHIFT 1
emilmont 78:ed8466a608b4 1117 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
emilmont 78:ed8466a608b4 1118 /* SMB Bit Fields */
emilmont 78:ed8466a608b4 1119 #define I2C_SMB_SHTF2IE_MASK 0x1u
emilmont 78:ed8466a608b4 1120 #define I2C_SMB_SHTF2IE_SHIFT 0
emilmont 78:ed8466a608b4 1121 #define I2C_SMB_SHTF2_MASK 0x2u
emilmont 78:ed8466a608b4 1122 #define I2C_SMB_SHTF2_SHIFT 1
emilmont 78:ed8466a608b4 1123 #define I2C_SMB_SHTF1_MASK 0x4u
emilmont 78:ed8466a608b4 1124 #define I2C_SMB_SHTF1_SHIFT 2
emilmont 78:ed8466a608b4 1125 #define I2C_SMB_SLTF_MASK 0x8u
emilmont 78:ed8466a608b4 1126 #define I2C_SMB_SLTF_SHIFT 3
emilmont 78:ed8466a608b4 1127 #define I2C_SMB_TCKSEL_MASK 0x10u
emilmont 78:ed8466a608b4 1128 #define I2C_SMB_TCKSEL_SHIFT 4
emilmont 78:ed8466a608b4 1129 #define I2C_SMB_SIICAEN_MASK 0x20u
emilmont 78:ed8466a608b4 1130 #define I2C_SMB_SIICAEN_SHIFT 5
emilmont 78:ed8466a608b4 1131 #define I2C_SMB_ALERTEN_MASK 0x40u
emilmont 78:ed8466a608b4 1132 #define I2C_SMB_ALERTEN_SHIFT 6
emilmont 78:ed8466a608b4 1133 #define I2C_SMB_FACK_MASK 0x80u
emilmont 78:ed8466a608b4 1134 #define I2C_SMB_FACK_SHIFT 7
emilmont 78:ed8466a608b4 1135 /* A2 Bit Fields */
emilmont 78:ed8466a608b4 1136 #define I2C_A2_SAD_MASK 0xFEu
emilmont 78:ed8466a608b4 1137 #define I2C_A2_SAD_SHIFT 1
emilmont 78:ed8466a608b4 1138 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
emilmont 78:ed8466a608b4 1139 /* SLTH Bit Fields */
emilmont 78:ed8466a608b4 1140 #define I2C_SLTH_SSLT_MASK 0xFFu
emilmont 78:ed8466a608b4 1141 #define I2C_SLTH_SSLT_SHIFT 0
emilmont 78:ed8466a608b4 1142 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
emilmont 78:ed8466a608b4 1143 /* SLTL Bit Fields */
emilmont 78:ed8466a608b4 1144 #define I2C_SLTL_SSLT_MASK 0xFFu
emilmont 78:ed8466a608b4 1145 #define I2C_SLTL_SSLT_SHIFT 0
emilmont 78:ed8466a608b4 1146 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
emilmont 78:ed8466a608b4 1147
emilmont 78:ed8466a608b4 1148 /**
emilmont 78:ed8466a608b4 1149 * @}
emilmont 78:ed8466a608b4 1150 */ /* end of group I2C_Register_Masks */
emilmont 78:ed8466a608b4 1151
emilmont 78:ed8466a608b4 1152
emilmont 78:ed8466a608b4 1153 /* I2C - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 1154 /** Peripheral I2C0 base address */
emilmont 78:ed8466a608b4 1155 #define I2C0_BASE (0x40066000u)
emilmont 78:ed8466a608b4 1156 /** Peripheral I2C0 base pointer */
emilmont 78:ed8466a608b4 1157 #define I2C0 ((I2C_Type *)I2C0_BASE)
emilmont 78:ed8466a608b4 1158 /** Array initializer of I2C peripheral base pointers */
emilmont 78:ed8466a608b4 1159 #define I2C_BASES { I2C0 }
emilmont 78:ed8466a608b4 1160
emilmont 78:ed8466a608b4 1161 /**
emilmont 78:ed8466a608b4 1162 * @}
emilmont 78:ed8466a608b4 1163 */ /* end of group I2C_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 1164
emilmont 78:ed8466a608b4 1165
emilmont 78:ed8466a608b4 1166 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 1167 -- LLWU Peripheral Access Layer
emilmont 78:ed8466a608b4 1168 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 1169
emilmont 78:ed8466a608b4 1170 /**
emilmont 78:ed8466a608b4 1171 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
emilmont 78:ed8466a608b4 1172 * @{
emilmont 78:ed8466a608b4 1173 */
emilmont 78:ed8466a608b4 1174
emilmont 78:ed8466a608b4 1175 /** LLWU - Register Layout Typedef */
emilmont 78:ed8466a608b4 1176 typedef struct {
emilmont 78:ed8466a608b4 1177 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
emilmont 78:ed8466a608b4 1178 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
emilmont 78:ed8466a608b4 1179 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x2 */
emilmont 78:ed8466a608b4 1180 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x3 */
emilmont 78:ed8466a608b4 1181 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x4 */
emilmont 78:ed8466a608b4 1182 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x5 */
emilmont 78:ed8466a608b4 1183 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x6 */
emilmont 78:ed8466a608b4 1184 } LLWU_Type;
emilmont 78:ed8466a608b4 1185
emilmont 78:ed8466a608b4 1186 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 1187 -- LLWU Register Masks
emilmont 78:ed8466a608b4 1188 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 1189
emilmont 78:ed8466a608b4 1190 /**
emilmont 78:ed8466a608b4 1191 * @addtogroup LLWU_Register_Masks LLWU Register Masks
emilmont 78:ed8466a608b4 1192 * @{
emilmont 78:ed8466a608b4 1193 */
emilmont 78:ed8466a608b4 1194
emilmont 78:ed8466a608b4 1195 /* PE1 Bit Fields */
emilmont 78:ed8466a608b4 1196 #define LLWU_PE1_WUPE0_MASK 0x3u
emilmont 78:ed8466a608b4 1197 #define LLWU_PE1_WUPE0_SHIFT 0
emilmont 78:ed8466a608b4 1198 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
emilmont 78:ed8466a608b4 1199 #define LLWU_PE1_WUPE1_MASK 0xCu
emilmont 78:ed8466a608b4 1200 #define LLWU_PE1_WUPE1_SHIFT 2
emilmont 78:ed8466a608b4 1201 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
emilmont 78:ed8466a608b4 1202 #define LLWU_PE1_WUPE2_MASK 0x30u
emilmont 78:ed8466a608b4 1203 #define LLWU_PE1_WUPE2_SHIFT 4
emilmont 78:ed8466a608b4 1204 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
emilmont 78:ed8466a608b4 1205 #define LLWU_PE1_WUPE3_MASK 0xC0u
emilmont 78:ed8466a608b4 1206 #define LLWU_PE1_WUPE3_SHIFT 6
emilmont 78:ed8466a608b4 1207 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
emilmont 78:ed8466a608b4 1208 /* PE2 Bit Fields */
emilmont 78:ed8466a608b4 1209 #define LLWU_PE2_WUPE4_MASK 0x3u
emilmont 78:ed8466a608b4 1210 #define LLWU_PE2_WUPE4_SHIFT 0
emilmont 78:ed8466a608b4 1211 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
emilmont 78:ed8466a608b4 1212 #define LLWU_PE2_WUPE5_MASK 0xCu
emilmont 78:ed8466a608b4 1213 #define LLWU_PE2_WUPE5_SHIFT 2
emilmont 78:ed8466a608b4 1214 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
emilmont 78:ed8466a608b4 1215 #define LLWU_PE2_WUPE6_MASK 0x30u
emilmont 78:ed8466a608b4 1216 #define LLWU_PE2_WUPE6_SHIFT 4
emilmont 78:ed8466a608b4 1217 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
emilmont 78:ed8466a608b4 1218 #define LLWU_PE2_WUPE7_MASK 0xC0u
emilmont 78:ed8466a608b4 1219 #define LLWU_PE2_WUPE7_SHIFT 6
emilmont 78:ed8466a608b4 1220 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
emilmont 78:ed8466a608b4 1221 /* ME Bit Fields */
emilmont 78:ed8466a608b4 1222 #define LLWU_ME_WUME0_MASK 0x1u
emilmont 78:ed8466a608b4 1223 #define LLWU_ME_WUME0_SHIFT 0
emilmont 78:ed8466a608b4 1224 #define LLWU_ME_WUME1_MASK 0x2u
emilmont 78:ed8466a608b4 1225 #define LLWU_ME_WUME1_SHIFT 1
emilmont 78:ed8466a608b4 1226 #define LLWU_ME_WUME2_MASK 0x4u
emilmont 78:ed8466a608b4 1227 #define LLWU_ME_WUME2_SHIFT 2
emilmont 78:ed8466a608b4 1228 #define LLWU_ME_WUME3_MASK 0x8u
emilmont 78:ed8466a608b4 1229 #define LLWU_ME_WUME3_SHIFT 3
emilmont 78:ed8466a608b4 1230 #define LLWU_ME_WUME4_MASK 0x10u
emilmont 78:ed8466a608b4 1231 #define LLWU_ME_WUME4_SHIFT 4
emilmont 78:ed8466a608b4 1232 #define LLWU_ME_WUME5_MASK 0x20u
emilmont 78:ed8466a608b4 1233 #define LLWU_ME_WUME5_SHIFT 5
emilmont 78:ed8466a608b4 1234 #define LLWU_ME_WUME6_MASK 0x40u
emilmont 78:ed8466a608b4 1235 #define LLWU_ME_WUME6_SHIFT 6
emilmont 78:ed8466a608b4 1236 #define LLWU_ME_WUME7_MASK 0x80u
emilmont 78:ed8466a608b4 1237 #define LLWU_ME_WUME7_SHIFT 7
emilmont 78:ed8466a608b4 1238 /* F1 Bit Fields */
emilmont 78:ed8466a608b4 1239 #define LLWU_F1_WUF0_MASK 0x1u
emilmont 78:ed8466a608b4 1240 #define LLWU_F1_WUF0_SHIFT 0
emilmont 78:ed8466a608b4 1241 #define LLWU_F1_WUF1_MASK 0x2u
emilmont 78:ed8466a608b4 1242 #define LLWU_F1_WUF1_SHIFT 1
emilmont 78:ed8466a608b4 1243 #define LLWU_F1_WUF2_MASK 0x4u
emilmont 78:ed8466a608b4 1244 #define LLWU_F1_WUF2_SHIFT 2
emilmont 78:ed8466a608b4 1245 #define LLWU_F1_WUF3_MASK 0x8u
emilmont 78:ed8466a608b4 1246 #define LLWU_F1_WUF3_SHIFT 3
emilmont 78:ed8466a608b4 1247 #define LLWU_F1_WUF4_MASK 0x10u
emilmont 78:ed8466a608b4 1248 #define LLWU_F1_WUF4_SHIFT 4
emilmont 78:ed8466a608b4 1249 #define LLWU_F1_WUF5_MASK 0x20u
emilmont 78:ed8466a608b4 1250 #define LLWU_F1_WUF5_SHIFT 5
emilmont 78:ed8466a608b4 1251 #define LLWU_F1_WUF6_MASK 0x40u
emilmont 78:ed8466a608b4 1252 #define LLWU_F1_WUF6_SHIFT 6
emilmont 78:ed8466a608b4 1253 #define LLWU_F1_WUF7_MASK 0x80u
emilmont 78:ed8466a608b4 1254 #define LLWU_F1_WUF7_SHIFT 7
emilmont 78:ed8466a608b4 1255 /* F3 Bit Fields */
emilmont 78:ed8466a608b4 1256 #define LLWU_F3_MWUF0_MASK 0x1u
emilmont 78:ed8466a608b4 1257 #define LLWU_F3_MWUF0_SHIFT 0
emilmont 78:ed8466a608b4 1258 #define LLWU_F3_MWUF1_MASK 0x2u
emilmont 78:ed8466a608b4 1259 #define LLWU_F3_MWUF1_SHIFT 1
emilmont 78:ed8466a608b4 1260 #define LLWU_F3_MWUF2_MASK 0x4u
emilmont 78:ed8466a608b4 1261 #define LLWU_F3_MWUF2_SHIFT 2
emilmont 78:ed8466a608b4 1262 #define LLWU_F3_MWUF3_MASK 0x8u
emilmont 78:ed8466a608b4 1263 #define LLWU_F3_MWUF3_SHIFT 3
emilmont 78:ed8466a608b4 1264 #define LLWU_F3_MWUF4_MASK 0x10u
emilmont 78:ed8466a608b4 1265 #define LLWU_F3_MWUF4_SHIFT 4
emilmont 78:ed8466a608b4 1266 #define LLWU_F3_MWUF5_MASK 0x20u
emilmont 78:ed8466a608b4 1267 #define LLWU_F3_MWUF5_SHIFT 5
emilmont 78:ed8466a608b4 1268 #define LLWU_F3_MWUF6_MASK 0x40u
emilmont 78:ed8466a608b4 1269 #define LLWU_F3_MWUF6_SHIFT 6
emilmont 78:ed8466a608b4 1270 #define LLWU_F3_MWUF7_MASK 0x80u
emilmont 78:ed8466a608b4 1271 #define LLWU_F3_MWUF7_SHIFT 7
emilmont 78:ed8466a608b4 1272 /* FILT1 Bit Fields */
emilmont 78:ed8466a608b4 1273 #define LLWU_FILT1_FILTSEL_MASK 0xFu
emilmont 78:ed8466a608b4 1274 #define LLWU_FILT1_FILTSEL_SHIFT 0
emilmont 78:ed8466a608b4 1275 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
emilmont 78:ed8466a608b4 1276 #define LLWU_FILT1_FILTE_MASK 0x60u
emilmont 78:ed8466a608b4 1277 #define LLWU_FILT1_FILTE_SHIFT 5
emilmont 78:ed8466a608b4 1278 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
emilmont 78:ed8466a608b4 1279 #define LLWU_FILT1_FILTF_MASK 0x80u
emilmont 78:ed8466a608b4 1280 #define LLWU_FILT1_FILTF_SHIFT 7
emilmont 78:ed8466a608b4 1281 /* FILT2 Bit Fields */
emilmont 78:ed8466a608b4 1282 #define LLWU_FILT2_FILTSEL_MASK 0xFu
emilmont 78:ed8466a608b4 1283 #define LLWU_FILT2_FILTSEL_SHIFT 0
emilmont 78:ed8466a608b4 1284 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
emilmont 78:ed8466a608b4 1285 #define LLWU_FILT2_FILTE_MASK 0x60u
emilmont 78:ed8466a608b4 1286 #define LLWU_FILT2_FILTE_SHIFT 5
emilmont 78:ed8466a608b4 1287 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
emilmont 78:ed8466a608b4 1288 #define LLWU_FILT2_FILTF_MASK 0x80u
emilmont 78:ed8466a608b4 1289 #define LLWU_FILT2_FILTF_SHIFT 7
emilmont 78:ed8466a608b4 1290
emilmont 78:ed8466a608b4 1291 /**
emilmont 78:ed8466a608b4 1292 * @}
emilmont 78:ed8466a608b4 1293 */ /* end of group LLWU_Register_Masks */
emilmont 78:ed8466a608b4 1294
emilmont 78:ed8466a608b4 1295
emilmont 78:ed8466a608b4 1296 /* LLWU - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 1297 /** Peripheral LLWU base address */
emilmont 78:ed8466a608b4 1298 #define LLWU_BASE (0x4007C000u)
emilmont 78:ed8466a608b4 1299 /** Peripheral LLWU base pointer */
emilmont 78:ed8466a608b4 1300 #define LLWU ((LLWU_Type *)LLWU_BASE)
emilmont 78:ed8466a608b4 1301 /** Array initializer of LLWU peripheral base pointers */
emilmont 78:ed8466a608b4 1302 #define LLWU_BASES { LLWU }
emilmont 78:ed8466a608b4 1303
emilmont 78:ed8466a608b4 1304 /**
emilmont 78:ed8466a608b4 1305 * @}
emilmont 78:ed8466a608b4 1306 */ /* end of group LLWU_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 1307
emilmont 78:ed8466a608b4 1308
emilmont 78:ed8466a608b4 1309 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 1310 -- LPTMR Peripheral Access Layer
emilmont 78:ed8466a608b4 1311 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 1312
emilmont 78:ed8466a608b4 1313 /**
emilmont 78:ed8466a608b4 1314 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
emilmont 78:ed8466a608b4 1315 * @{
emilmont 78:ed8466a608b4 1316 */
emilmont 78:ed8466a608b4 1317
emilmont 78:ed8466a608b4 1318 /** LPTMR - Register Layout Typedef */
emilmont 78:ed8466a608b4 1319 typedef struct {
emilmont 78:ed8466a608b4 1320 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
emilmont 78:ed8466a608b4 1321 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
emilmont 78:ed8466a608b4 1322 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
emilmont 78:ed8466a608b4 1323 __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
emilmont 78:ed8466a608b4 1324 } LPTMR_Type;
emilmont 78:ed8466a608b4 1325
emilmont 78:ed8466a608b4 1326 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 1327 -- LPTMR Register Masks
emilmont 78:ed8466a608b4 1328 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 1329
emilmont 78:ed8466a608b4 1330 /**
emilmont 78:ed8466a608b4 1331 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
emilmont 78:ed8466a608b4 1332 * @{
emilmont 78:ed8466a608b4 1333 */
emilmont 78:ed8466a608b4 1334
emilmont 78:ed8466a608b4 1335 /* CSR Bit Fields */
emilmont 78:ed8466a608b4 1336 #define LPTMR_CSR_TEN_MASK 0x1u
emilmont 78:ed8466a608b4 1337 #define LPTMR_CSR_TEN_SHIFT 0
emilmont 78:ed8466a608b4 1338 #define LPTMR_CSR_TMS_MASK 0x2u
emilmont 78:ed8466a608b4 1339 #define LPTMR_CSR_TMS_SHIFT 1
emilmont 78:ed8466a608b4 1340 #define LPTMR_CSR_TFC_MASK 0x4u
emilmont 78:ed8466a608b4 1341 #define LPTMR_CSR_TFC_SHIFT 2
emilmont 78:ed8466a608b4 1342 #define LPTMR_CSR_TPP_MASK 0x8u
emilmont 78:ed8466a608b4 1343 #define LPTMR_CSR_TPP_SHIFT 3
emilmont 78:ed8466a608b4 1344 #define LPTMR_CSR_TPS_MASK 0x30u
emilmont 78:ed8466a608b4 1345 #define LPTMR_CSR_TPS_SHIFT 4
emilmont 78:ed8466a608b4 1346 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
emilmont 78:ed8466a608b4 1347 #define LPTMR_CSR_TIE_MASK 0x40u
emilmont 78:ed8466a608b4 1348 #define LPTMR_CSR_TIE_SHIFT 6
emilmont 78:ed8466a608b4 1349 #define LPTMR_CSR_TCF_MASK 0x80u
emilmont 78:ed8466a608b4 1350 #define LPTMR_CSR_TCF_SHIFT 7
emilmont 78:ed8466a608b4 1351 /* PSR Bit Fields */
emilmont 78:ed8466a608b4 1352 #define LPTMR_PSR_PCS_MASK 0x3u
emilmont 78:ed8466a608b4 1353 #define LPTMR_PSR_PCS_SHIFT 0
emilmont 78:ed8466a608b4 1354 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
emilmont 78:ed8466a608b4 1355 #define LPTMR_PSR_PBYP_MASK 0x4u
emilmont 78:ed8466a608b4 1356 #define LPTMR_PSR_PBYP_SHIFT 2
emilmont 78:ed8466a608b4 1357 #define LPTMR_PSR_PRESCALE_MASK 0x78u
emilmont 78:ed8466a608b4 1358 #define LPTMR_PSR_PRESCALE_SHIFT 3
emilmont 78:ed8466a608b4 1359 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
emilmont 78:ed8466a608b4 1360 /* CMR Bit Fields */
emilmont 78:ed8466a608b4 1361 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
emilmont 78:ed8466a608b4 1362 #define LPTMR_CMR_COMPARE_SHIFT 0
emilmont 78:ed8466a608b4 1363 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
emilmont 78:ed8466a608b4 1364 /* CNR Bit Fields */
emilmont 78:ed8466a608b4 1365 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
emilmont 78:ed8466a608b4 1366 #define LPTMR_CNR_COUNTER_SHIFT 0
emilmont 78:ed8466a608b4 1367 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
emilmont 78:ed8466a608b4 1368
emilmont 78:ed8466a608b4 1369 /**
emilmont 78:ed8466a608b4 1370 * @}
emilmont 78:ed8466a608b4 1371 */ /* end of group LPTMR_Register_Masks */
emilmont 78:ed8466a608b4 1372
emilmont 78:ed8466a608b4 1373
emilmont 78:ed8466a608b4 1374 /* LPTMR - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 1375 /** Peripheral LPTMR0 base address */
emilmont 78:ed8466a608b4 1376 #define LPTMR0_BASE (0x40040000u)
emilmont 78:ed8466a608b4 1377 /** Peripheral LPTMR0 base pointer */
emilmont 78:ed8466a608b4 1378 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
emilmont 78:ed8466a608b4 1379 /** Array initializer of LPTMR peripheral base pointers */
emilmont 78:ed8466a608b4 1380 #define LPTMR_BASES { LPTMR0 }
emilmont 78:ed8466a608b4 1381
emilmont 78:ed8466a608b4 1382 /**
emilmont 78:ed8466a608b4 1383 * @}
emilmont 78:ed8466a608b4 1384 */ /* end of group LPTMR_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 1385
emilmont 78:ed8466a608b4 1386
emilmont 78:ed8466a608b4 1387 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 1388 -- MCG Peripheral Access Layer
emilmont 78:ed8466a608b4 1389 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 1390
emilmont 78:ed8466a608b4 1391 /**
emilmont 78:ed8466a608b4 1392 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
emilmont 78:ed8466a608b4 1393 * @{
emilmont 78:ed8466a608b4 1394 */
emilmont 78:ed8466a608b4 1395
emilmont 78:ed8466a608b4 1396 /** MCG - Register Layout Typedef */
emilmont 78:ed8466a608b4 1397 typedef struct {
emilmont 78:ed8466a608b4 1398 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
emilmont 78:ed8466a608b4 1399 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
emilmont 78:ed8466a608b4 1400 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
emilmont 78:ed8466a608b4 1401 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
emilmont 78:ed8466a608b4 1402 __I uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
emilmont 78:ed8466a608b4 1403 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
emilmont 78:ed8466a608b4 1404 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
emilmont 78:ed8466a608b4 1405 uint8_t RESERVED_0[1];
emilmont 78:ed8466a608b4 1406 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
emilmont 78:ed8466a608b4 1407 uint8_t RESERVED_1[1];
emilmont 78:ed8466a608b4 1408 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
emilmont 78:ed8466a608b4 1409 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
emilmont 78:ed8466a608b4 1410 } MCG_Type;
emilmont 78:ed8466a608b4 1411
emilmont 78:ed8466a608b4 1412 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 1413 -- MCG Register Masks
emilmont 78:ed8466a608b4 1414 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 1415
emilmont 78:ed8466a608b4 1416 /**
emilmont 78:ed8466a608b4 1417 * @addtogroup MCG_Register_Masks MCG Register Masks
emilmont 78:ed8466a608b4 1418 * @{
emilmont 78:ed8466a608b4 1419 */
emilmont 78:ed8466a608b4 1420
emilmont 78:ed8466a608b4 1421 /* C1 Bit Fields */
emilmont 78:ed8466a608b4 1422 #define MCG_C1_IREFSTEN_MASK 0x1u
emilmont 78:ed8466a608b4 1423 #define MCG_C1_IREFSTEN_SHIFT 0
emilmont 78:ed8466a608b4 1424 #define MCG_C1_IRCLKEN_MASK 0x2u
emilmont 78:ed8466a608b4 1425 #define MCG_C1_IRCLKEN_SHIFT 1
emilmont 78:ed8466a608b4 1426 #define MCG_C1_IREFS_MASK 0x4u
emilmont 78:ed8466a608b4 1427 #define MCG_C1_IREFS_SHIFT 2
emilmont 78:ed8466a608b4 1428 #define MCG_C1_FRDIV_MASK 0x38u
emilmont 78:ed8466a608b4 1429 #define MCG_C1_FRDIV_SHIFT 3
emilmont 78:ed8466a608b4 1430 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
emilmont 78:ed8466a608b4 1431 #define MCG_C1_CLKS_MASK 0xC0u
emilmont 78:ed8466a608b4 1432 #define MCG_C1_CLKS_SHIFT 6
emilmont 78:ed8466a608b4 1433 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
emilmont 78:ed8466a608b4 1434 /* C2 Bit Fields */
emilmont 78:ed8466a608b4 1435 #define MCG_C2_IRCS_MASK 0x1u
emilmont 78:ed8466a608b4 1436 #define MCG_C2_IRCS_SHIFT 0
emilmont 78:ed8466a608b4 1437 #define MCG_C2_LP_MASK 0x2u
emilmont 78:ed8466a608b4 1438 #define MCG_C2_LP_SHIFT 1
emilmont 78:ed8466a608b4 1439 #define MCG_C2_EREFS0_MASK 0x4u
emilmont 78:ed8466a608b4 1440 #define MCG_C2_EREFS0_SHIFT 2
emilmont 78:ed8466a608b4 1441 #define MCG_C2_HGO0_MASK 0x8u
emilmont 78:ed8466a608b4 1442 #define MCG_C2_HGO0_SHIFT 3
emilmont 78:ed8466a608b4 1443 #define MCG_C2_RANGE0_MASK 0x30u
emilmont 78:ed8466a608b4 1444 #define MCG_C2_RANGE0_SHIFT 4
emilmont 78:ed8466a608b4 1445 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
emilmont 78:ed8466a608b4 1446 #define MCG_C2_LOCRE0_MASK 0x80u
emilmont 78:ed8466a608b4 1447 #define MCG_C2_LOCRE0_SHIFT 7
emilmont 78:ed8466a608b4 1448 /* C3 Bit Fields */
emilmont 78:ed8466a608b4 1449 #define MCG_C3_SCTRIM_MASK 0xFFu
emilmont 78:ed8466a608b4 1450 #define MCG_C3_SCTRIM_SHIFT 0
emilmont 78:ed8466a608b4 1451 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
emilmont 78:ed8466a608b4 1452 /* C4 Bit Fields */
emilmont 78:ed8466a608b4 1453 #define MCG_C4_SCFTRIM_MASK 0x1u
emilmont 78:ed8466a608b4 1454 #define MCG_C4_SCFTRIM_SHIFT 0
emilmont 78:ed8466a608b4 1455 #define MCG_C4_FCTRIM_MASK 0x1Eu
emilmont 78:ed8466a608b4 1456 #define MCG_C4_FCTRIM_SHIFT 1
emilmont 78:ed8466a608b4 1457 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
emilmont 78:ed8466a608b4 1458 #define MCG_C4_DRST_DRS_MASK 0x60u
emilmont 78:ed8466a608b4 1459 #define MCG_C4_DRST_DRS_SHIFT 5
emilmont 78:ed8466a608b4 1460 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
emilmont 78:ed8466a608b4 1461 #define MCG_C4_DMX32_MASK 0x80u
emilmont 78:ed8466a608b4 1462 #define MCG_C4_DMX32_SHIFT 7
emilmont 78:ed8466a608b4 1463 /* C6 Bit Fields */
emilmont 78:ed8466a608b4 1464 #define MCG_C6_CME_MASK 0x20u
emilmont 78:ed8466a608b4 1465 #define MCG_C6_CME_SHIFT 5
emilmont 78:ed8466a608b4 1466 /* S Bit Fields */
emilmont 78:ed8466a608b4 1467 #define MCG_S_IRCST_MASK 0x1u
emilmont 78:ed8466a608b4 1468 #define MCG_S_IRCST_SHIFT 0
emilmont 78:ed8466a608b4 1469 #define MCG_S_OSCINIT0_MASK 0x2u
emilmont 78:ed8466a608b4 1470 #define MCG_S_OSCINIT0_SHIFT 1
emilmont 78:ed8466a608b4 1471 #define MCG_S_CLKST_MASK 0xCu
emilmont 78:ed8466a608b4 1472 #define MCG_S_CLKST_SHIFT 2
emilmont 78:ed8466a608b4 1473 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
emilmont 78:ed8466a608b4 1474 #define MCG_S_IREFST_MASK 0x10u
emilmont 78:ed8466a608b4 1475 #define MCG_S_IREFST_SHIFT 4
emilmont 78:ed8466a608b4 1476 /* SC Bit Fields */
emilmont 78:ed8466a608b4 1477 #define MCG_SC_LOCS0_MASK 0x1u
emilmont 78:ed8466a608b4 1478 #define MCG_SC_LOCS0_SHIFT 0
emilmont 78:ed8466a608b4 1479 #define MCG_SC_FCRDIV_MASK 0xEu
emilmont 78:ed8466a608b4 1480 #define MCG_SC_FCRDIV_SHIFT 1
emilmont 78:ed8466a608b4 1481 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
emilmont 78:ed8466a608b4 1482 #define MCG_SC_FLTPRSRV_MASK 0x10u
emilmont 78:ed8466a608b4 1483 #define MCG_SC_FLTPRSRV_SHIFT 4
emilmont 78:ed8466a608b4 1484 #define MCG_SC_ATMF_MASK 0x20u
emilmont 78:ed8466a608b4 1485 #define MCG_SC_ATMF_SHIFT 5
emilmont 78:ed8466a608b4 1486 #define MCG_SC_ATMS_MASK 0x40u
emilmont 78:ed8466a608b4 1487 #define MCG_SC_ATMS_SHIFT 6
emilmont 78:ed8466a608b4 1488 #define MCG_SC_ATME_MASK 0x80u
emilmont 78:ed8466a608b4 1489 #define MCG_SC_ATME_SHIFT 7
emilmont 78:ed8466a608b4 1490 /* ATCVH Bit Fields */
emilmont 78:ed8466a608b4 1491 #define MCG_ATCVH_ATCVH_MASK 0xFFu
emilmont 78:ed8466a608b4 1492 #define MCG_ATCVH_ATCVH_SHIFT 0
emilmont 78:ed8466a608b4 1493 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
emilmont 78:ed8466a608b4 1494 /* ATCVL Bit Fields */
emilmont 78:ed8466a608b4 1495 #define MCG_ATCVL_ATCVL_MASK 0xFFu
emilmont 78:ed8466a608b4 1496 #define MCG_ATCVL_ATCVL_SHIFT 0
emilmont 78:ed8466a608b4 1497 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
emilmont 78:ed8466a608b4 1498
emilmont 78:ed8466a608b4 1499 /**
emilmont 78:ed8466a608b4 1500 * @}
emilmont 78:ed8466a608b4 1501 */ /* end of group MCG_Register_Masks */
emilmont 78:ed8466a608b4 1502
emilmont 78:ed8466a608b4 1503
emilmont 78:ed8466a608b4 1504 /* MCG - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 1505 /** Peripheral MCG base address */
emilmont 78:ed8466a608b4 1506 #define MCG_BASE (0x40064000u)
emilmont 78:ed8466a608b4 1507 /** Peripheral MCG base pointer */
emilmont 78:ed8466a608b4 1508 #define MCG ((MCG_Type *)MCG_BASE)
emilmont 78:ed8466a608b4 1509 /** Array initializer of MCG peripheral base pointers */
emilmont 78:ed8466a608b4 1510 #define MCG_BASES { MCG }
emilmont 78:ed8466a608b4 1511
emilmont 78:ed8466a608b4 1512 /**
emilmont 78:ed8466a608b4 1513 * @}
emilmont 78:ed8466a608b4 1514 */ /* end of group MCG_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 1515
emilmont 78:ed8466a608b4 1516
emilmont 78:ed8466a608b4 1517 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 1518 -- MCM Peripheral Access Layer
emilmont 78:ed8466a608b4 1519 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 1520
emilmont 78:ed8466a608b4 1521 /**
emilmont 78:ed8466a608b4 1522 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
emilmont 78:ed8466a608b4 1523 * @{
emilmont 78:ed8466a608b4 1524 */
emilmont 78:ed8466a608b4 1525
emilmont 78:ed8466a608b4 1526 /** MCM - Register Layout Typedef */
emilmont 78:ed8466a608b4 1527 typedef struct {
emilmont 78:ed8466a608b4 1528 uint8_t RESERVED_0[8];
emilmont 78:ed8466a608b4 1529 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
emilmont 78:ed8466a608b4 1530 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
emilmont 78:ed8466a608b4 1531 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
emilmont 78:ed8466a608b4 1532 uint8_t RESERVED_1[48];
emilmont 78:ed8466a608b4 1533 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
emilmont 78:ed8466a608b4 1534 } MCM_Type;
emilmont 78:ed8466a608b4 1535
emilmont 78:ed8466a608b4 1536 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 1537 -- MCM Register Masks
emilmont 78:ed8466a608b4 1538 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 1539
emilmont 78:ed8466a608b4 1540 /**
emilmont 78:ed8466a608b4 1541 * @addtogroup MCM_Register_Masks MCM Register Masks
emilmont 78:ed8466a608b4 1542 * @{
emilmont 78:ed8466a608b4 1543 */
emilmont 78:ed8466a608b4 1544
emilmont 78:ed8466a608b4 1545 /* PLASC Bit Fields */
emilmont 78:ed8466a608b4 1546 #define MCM_PLASC_ASC_MASK 0xFFu
emilmont 78:ed8466a608b4 1547 #define MCM_PLASC_ASC_SHIFT 0
emilmont 78:ed8466a608b4 1548 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
emilmont 78:ed8466a608b4 1549 /* PLAMC Bit Fields */
emilmont 78:ed8466a608b4 1550 #define MCM_PLAMC_AMC_MASK 0xFFu
emilmont 78:ed8466a608b4 1551 #define MCM_PLAMC_AMC_SHIFT 0
emilmont 78:ed8466a608b4 1552 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
emilmont 78:ed8466a608b4 1553 /* PLACR Bit Fields */
emilmont 78:ed8466a608b4 1554 #define MCM_PLACR_ARB_MASK 0x200u
emilmont 78:ed8466a608b4 1555 #define MCM_PLACR_ARB_SHIFT 9
emilmont 78:ed8466a608b4 1556 #define MCM_PLACR_CFCC_MASK 0x400u
emilmont 78:ed8466a608b4 1557 #define MCM_PLACR_CFCC_SHIFT 10
emilmont 78:ed8466a608b4 1558 #define MCM_PLACR_DFCDA_MASK 0x800u
emilmont 78:ed8466a608b4 1559 #define MCM_PLACR_DFCDA_SHIFT 11
emilmont 78:ed8466a608b4 1560 #define MCM_PLACR_DFCIC_MASK 0x1000u
emilmont 78:ed8466a608b4 1561 #define MCM_PLACR_DFCIC_SHIFT 12
emilmont 78:ed8466a608b4 1562 #define MCM_PLACR_DFCC_MASK 0x2000u
emilmont 78:ed8466a608b4 1563 #define MCM_PLACR_DFCC_SHIFT 13
emilmont 78:ed8466a608b4 1564 #define MCM_PLACR_EFDS_MASK 0x4000u
emilmont 78:ed8466a608b4 1565 #define MCM_PLACR_EFDS_SHIFT 14
emilmont 78:ed8466a608b4 1566 #define MCM_PLACR_DFCS_MASK 0x8000u
emilmont 78:ed8466a608b4 1567 #define MCM_PLACR_DFCS_SHIFT 15
emilmont 78:ed8466a608b4 1568 #define MCM_PLACR_ESFC_MASK 0x10000u
emilmont 78:ed8466a608b4 1569 #define MCM_PLACR_ESFC_SHIFT 16
emilmont 78:ed8466a608b4 1570 /* CPO Bit Fields */
emilmont 78:ed8466a608b4 1571 #define MCM_CPO_CPOREQ_MASK 0x1u
emilmont 78:ed8466a608b4 1572 #define MCM_CPO_CPOREQ_SHIFT 0
emilmont 78:ed8466a608b4 1573 #define MCM_CPO_CPOACK_MASK 0x2u
emilmont 78:ed8466a608b4 1574 #define MCM_CPO_CPOACK_SHIFT 1
emilmont 78:ed8466a608b4 1575 #define MCM_CPO_CPOWOI_MASK 0x4u
emilmont 78:ed8466a608b4 1576 #define MCM_CPO_CPOWOI_SHIFT 2
emilmont 78:ed8466a608b4 1577
emilmont 78:ed8466a608b4 1578 /**
emilmont 78:ed8466a608b4 1579 * @}
emilmont 78:ed8466a608b4 1580 */ /* end of group MCM_Register_Masks */
emilmont 78:ed8466a608b4 1581
emilmont 78:ed8466a608b4 1582
emilmont 78:ed8466a608b4 1583 /* MCM - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 1584 /** Peripheral MCM base address */
emilmont 78:ed8466a608b4 1585 #define MCM_BASE (0xF0003000u)
emilmont 78:ed8466a608b4 1586 /** Peripheral MCM base pointer */
emilmont 78:ed8466a608b4 1587 #define MCM ((MCM_Type *)MCM_BASE)
emilmont 78:ed8466a608b4 1588 /** Array initializer of MCM peripheral base pointers */
emilmont 78:ed8466a608b4 1589 #define MCM_BASES { MCM }
emilmont 78:ed8466a608b4 1590
emilmont 78:ed8466a608b4 1591 /**
emilmont 78:ed8466a608b4 1592 * @}
emilmont 78:ed8466a608b4 1593 */ /* end of group MCM_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 1594
emilmont 78:ed8466a608b4 1595
emilmont 78:ed8466a608b4 1596 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 1597 -- MTB Peripheral Access Layer
emilmont 78:ed8466a608b4 1598 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 1599
emilmont 78:ed8466a608b4 1600 /**
emilmont 78:ed8466a608b4 1601 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
emilmont 78:ed8466a608b4 1602 * @{
emilmont 78:ed8466a608b4 1603 */
emilmont 78:ed8466a608b4 1604
emilmont 78:ed8466a608b4 1605 /** MTB - Register Layout Typedef */
emilmont 78:ed8466a608b4 1606 typedef struct {
emilmont 78:ed8466a608b4 1607 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
emilmont 78:ed8466a608b4 1608 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
emilmont 78:ed8466a608b4 1609 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
emilmont 78:ed8466a608b4 1610 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
emilmont 78:ed8466a608b4 1611 uint8_t RESERVED_0[3824];
emilmont 78:ed8466a608b4 1612 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
emilmont 78:ed8466a608b4 1613 uint8_t RESERVED_1[156];
emilmont 78:ed8466a608b4 1614 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
emilmont 78:ed8466a608b4 1615 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
emilmont 78:ed8466a608b4 1616 uint8_t RESERVED_2[8];
emilmont 78:ed8466a608b4 1617 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
emilmont 78:ed8466a608b4 1618 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
emilmont 78:ed8466a608b4 1619 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
emilmont 78:ed8466a608b4 1620 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
emilmont 78:ed8466a608b4 1621 uint8_t RESERVED_3[8];
emilmont 78:ed8466a608b4 1622 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
emilmont 78:ed8466a608b4 1623 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
emilmont 78:ed8466a608b4 1624 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
emilmont 78:ed8466a608b4 1625 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
emilmont 78:ed8466a608b4 1626 } MTB_Type;
emilmont 78:ed8466a608b4 1627
emilmont 78:ed8466a608b4 1628 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 1629 -- MTB Register Masks
emilmont 78:ed8466a608b4 1630 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 1631
emilmont 78:ed8466a608b4 1632 /**
emilmont 78:ed8466a608b4 1633 * @addtogroup MTB_Register_Masks MTB Register Masks
emilmont 78:ed8466a608b4 1634 * @{
emilmont 78:ed8466a608b4 1635 */
emilmont 78:ed8466a608b4 1636
emilmont 78:ed8466a608b4 1637 /* POSITION Bit Fields */
emilmont 78:ed8466a608b4 1638 #define MTB_POSITION_WRAP_MASK 0x4u
emilmont 78:ed8466a608b4 1639 #define MTB_POSITION_WRAP_SHIFT 2
emilmont 78:ed8466a608b4 1640 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
emilmont 78:ed8466a608b4 1641 #define MTB_POSITION_POINTER_SHIFT 3
emilmont 78:ed8466a608b4 1642 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
emilmont 78:ed8466a608b4 1643 /* MASTER Bit Fields */
emilmont 78:ed8466a608b4 1644 #define MTB_MASTER_MASK_MASK 0x1Fu
emilmont 78:ed8466a608b4 1645 #define MTB_MASTER_MASK_SHIFT 0
emilmont 78:ed8466a608b4 1646 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
emilmont 78:ed8466a608b4 1647 #define MTB_MASTER_TSTARTEN_MASK 0x20u
emilmont 78:ed8466a608b4 1648 #define MTB_MASTER_TSTARTEN_SHIFT 5
emilmont 78:ed8466a608b4 1649 #define MTB_MASTER_TSTOPEN_MASK 0x40u
emilmont 78:ed8466a608b4 1650 #define MTB_MASTER_TSTOPEN_SHIFT 6
emilmont 78:ed8466a608b4 1651 #define MTB_MASTER_SFRWPRIV_MASK 0x80u
emilmont 78:ed8466a608b4 1652 #define MTB_MASTER_SFRWPRIV_SHIFT 7
emilmont 78:ed8466a608b4 1653 #define MTB_MASTER_RAMPRIV_MASK 0x100u
emilmont 78:ed8466a608b4 1654 #define MTB_MASTER_RAMPRIV_SHIFT 8
emilmont 78:ed8466a608b4 1655 #define MTB_MASTER_HALTREQ_MASK 0x200u
emilmont 78:ed8466a608b4 1656 #define MTB_MASTER_HALTREQ_SHIFT 9
emilmont 78:ed8466a608b4 1657 #define MTB_MASTER_EN_MASK 0x80000000u
emilmont 78:ed8466a608b4 1658 #define MTB_MASTER_EN_SHIFT 31
emilmont 78:ed8466a608b4 1659 /* FLOW Bit Fields */
emilmont 78:ed8466a608b4 1660 #define MTB_FLOW_AUTOSTOP_MASK 0x1u
emilmont 78:ed8466a608b4 1661 #define MTB_FLOW_AUTOSTOP_SHIFT 0
emilmont 78:ed8466a608b4 1662 #define MTB_FLOW_AUTOHALT_MASK 0x2u
emilmont 78:ed8466a608b4 1663 #define MTB_FLOW_AUTOHALT_SHIFT 1
emilmont 78:ed8466a608b4 1664 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
emilmont 78:ed8466a608b4 1665 #define MTB_FLOW_WATERMARK_SHIFT 3
emilmont 78:ed8466a608b4 1666 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
emilmont 78:ed8466a608b4 1667 /* BASE Bit Fields */
emilmont 78:ed8466a608b4 1668 #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 1669 #define MTB_BASE_BASEADDR_SHIFT 0
emilmont 78:ed8466a608b4 1670 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
emilmont 78:ed8466a608b4 1671 /* MODECTRL Bit Fields */
emilmont 78:ed8466a608b4 1672 #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 1673 #define MTB_MODECTRL_MODECTRL_SHIFT 0
emilmont 78:ed8466a608b4 1674 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
emilmont 78:ed8466a608b4 1675 /* TAGSET Bit Fields */
emilmont 78:ed8466a608b4 1676 #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 1677 #define MTB_TAGSET_TAGSET_SHIFT 0
emilmont 78:ed8466a608b4 1678 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
emilmont 78:ed8466a608b4 1679 /* TAGCLEAR Bit Fields */
emilmont 78:ed8466a608b4 1680 #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 1681 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
emilmont 78:ed8466a608b4 1682 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
emilmont 78:ed8466a608b4 1683 /* LOCKACCESS Bit Fields */
emilmont 78:ed8466a608b4 1684 #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 1685 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
emilmont 78:ed8466a608b4 1686 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
emilmont 78:ed8466a608b4 1687 /* LOCKSTAT Bit Fields */
emilmont 78:ed8466a608b4 1688 #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 1689 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
emilmont 78:ed8466a608b4 1690 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
emilmont 78:ed8466a608b4 1691 /* AUTHSTAT Bit Fields */
emilmont 78:ed8466a608b4 1692 #define MTB_AUTHSTAT_BIT0_MASK 0x1u
emilmont 78:ed8466a608b4 1693 #define MTB_AUTHSTAT_BIT0_SHIFT 0
emilmont 78:ed8466a608b4 1694 #define MTB_AUTHSTAT_BIT1_MASK 0x2u
emilmont 78:ed8466a608b4 1695 #define MTB_AUTHSTAT_BIT1_SHIFT 1
emilmont 78:ed8466a608b4 1696 #define MTB_AUTHSTAT_BIT2_MASK 0x4u
emilmont 78:ed8466a608b4 1697 #define MTB_AUTHSTAT_BIT2_SHIFT 2
emilmont 78:ed8466a608b4 1698 #define MTB_AUTHSTAT_BIT3_MASK 0x8u
emilmont 78:ed8466a608b4 1699 #define MTB_AUTHSTAT_BIT3_SHIFT 3
emilmont 78:ed8466a608b4 1700 /* DEVICEARCH Bit Fields */
emilmont 78:ed8466a608b4 1701 #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 1702 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
emilmont 78:ed8466a608b4 1703 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
emilmont 78:ed8466a608b4 1704 /* DEVICECFG Bit Fields */
emilmont 78:ed8466a608b4 1705 #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 1706 #define MTB_DEVICECFG_DEVICECFG_SHIFT 0
emilmont 78:ed8466a608b4 1707 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
emilmont 78:ed8466a608b4 1708 /* DEVICETYPID Bit Fields */
emilmont 78:ed8466a608b4 1709 #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 1710 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
emilmont 78:ed8466a608b4 1711 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
emilmont 78:ed8466a608b4 1712 /* PERIPHID Bit Fields */
emilmont 78:ed8466a608b4 1713 #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 1714 #define MTB_PERIPHID_PERIPHID_SHIFT 0
emilmont 78:ed8466a608b4 1715 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
emilmont 78:ed8466a608b4 1716 /* COMPID Bit Fields */
emilmont 78:ed8466a608b4 1717 #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 1718 #define MTB_COMPID_COMPID_SHIFT 0
emilmont 78:ed8466a608b4 1719 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
emilmont 78:ed8466a608b4 1720
emilmont 78:ed8466a608b4 1721 /**
emilmont 78:ed8466a608b4 1722 * @}
emilmont 78:ed8466a608b4 1723 */ /* end of group MTB_Register_Masks */
emilmont 78:ed8466a608b4 1724
emilmont 78:ed8466a608b4 1725
emilmont 78:ed8466a608b4 1726 /* MTB - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 1727 /** Peripheral MTB base address */
emilmont 78:ed8466a608b4 1728 #define MTB_BASE (0xF0000000u)
emilmont 78:ed8466a608b4 1729 /** Peripheral MTB base pointer */
emilmont 78:ed8466a608b4 1730 #define MTB ((MTB_Type *)MTB_BASE)
emilmont 78:ed8466a608b4 1731 /** Array initializer of MTB peripheral base pointers */
emilmont 78:ed8466a608b4 1732 #define MTB_BASES { MTB }
emilmont 78:ed8466a608b4 1733
emilmont 78:ed8466a608b4 1734 /**
emilmont 78:ed8466a608b4 1735 * @}
emilmont 78:ed8466a608b4 1736 */ /* end of group MTB_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 1737
emilmont 78:ed8466a608b4 1738
emilmont 78:ed8466a608b4 1739 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 1740 -- MTBDWT Peripheral Access Layer
emilmont 78:ed8466a608b4 1741 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 1742
emilmont 78:ed8466a608b4 1743 /**
emilmont 78:ed8466a608b4 1744 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
emilmont 78:ed8466a608b4 1745 * @{
emilmont 78:ed8466a608b4 1746 */
emilmont 78:ed8466a608b4 1747
emilmont 78:ed8466a608b4 1748 /** MTBDWT - Register Layout Typedef */
emilmont 78:ed8466a608b4 1749 typedef struct {
emilmont 78:ed8466a608b4 1750 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
emilmont 78:ed8466a608b4 1751 uint8_t RESERVED_0[28];
emilmont 78:ed8466a608b4 1752 struct { /* offset: 0x20, array step: 0x10 */
emilmont 78:ed8466a608b4 1753 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
emilmont 78:ed8466a608b4 1754 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
emilmont 78:ed8466a608b4 1755 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
emilmont 78:ed8466a608b4 1756 uint8_t RESERVED_0[4];
emilmont 78:ed8466a608b4 1757 } COMPARATOR[2];
emilmont 78:ed8466a608b4 1758 uint8_t RESERVED_1[448];
emilmont 78:ed8466a608b4 1759 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
emilmont 78:ed8466a608b4 1760 uint8_t RESERVED_2[3524];
emilmont 78:ed8466a608b4 1761 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
emilmont 78:ed8466a608b4 1762 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
emilmont 78:ed8466a608b4 1763 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
emilmont 78:ed8466a608b4 1764 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
emilmont 78:ed8466a608b4 1765 } MTBDWT_Type;
emilmont 78:ed8466a608b4 1766
emilmont 78:ed8466a608b4 1767 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 1768 -- MTBDWT Register Masks
emilmont 78:ed8466a608b4 1769 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 1770
emilmont 78:ed8466a608b4 1771 /**
emilmont 78:ed8466a608b4 1772 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
emilmont 78:ed8466a608b4 1773 * @{
emilmont 78:ed8466a608b4 1774 */
emilmont 78:ed8466a608b4 1775
emilmont 78:ed8466a608b4 1776 /* CTRL Bit Fields */
emilmont 78:ed8466a608b4 1777 #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
emilmont 78:ed8466a608b4 1778 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
emilmont 78:ed8466a608b4 1779 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
emilmont 78:ed8466a608b4 1780 #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
emilmont 78:ed8466a608b4 1781 #define MTBDWT_CTRL_NUMCMP_SHIFT 28
emilmont 78:ed8466a608b4 1782 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
emilmont 78:ed8466a608b4 1783 /* COMP Bit Fields */
emilmont 78:ed8466a608b4 1784 #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 1785 #define MTBDWT_COMP_COMP_SHIFT 0
emilmont 78:ed8466a608b4 1786 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
emilmont 78:ed8466a608b4 1787 /* MASK Bit Fields */
emilmont 78:ed8466a608b4 1788 #define MTBDWT_MASK_MASK_MASK 0x1Fu
emilmont 78:ed8466a608b4 1789 #define MTBDWT_MASK_MASK_SHIFT 0
emilmont 78:ed8466a608b4 1790 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
emilmont 78:ed8466a608b4 1791 /* FCT Bit Fields */
emilmont 78:ed8466a608b4 1792 #define MTBDWT_FCT_FUNCTION_MASK 0xFu
emilmont 78:ed8466a608b4 1793 #define MTBDWT_FCT_FUNCTION_SHIFT 0
emilmont 78:ed8466a608b4 1794 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
emilmont 78:ed8466a608b4 1795 #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
emilmont 78:ed8466a608b4 1796 #define MTBDWT_FCT_DATAVMATCH_SHIFT 8
emilmont 78:ed8466a608b4 1797 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
emilmont 78:ed8466a608b4 1798 #define MTBDWT_FCT_DATAVSIZE_SHIFT 10
emilmont 78:ed8466a608b4 1799 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
emilmont 78:ed8466a608b4 1800 #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
emilmont 78:ed8466a608b4 1801 #define MTBDWT_FCT_DATAVADDR0_SHIFT 12
emilmont 78:ed8466a608b4 1802 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
emilmont 78:ed8466a608b4 1803 #define MTBDWT_FCT_MATCHED_MASK 0x1000000u
emilmont 78:ed8466a608b4 1804 #define MTBDWT_FCT_MATCHED_SHIFT 24
emilmont 78:ed8466a608b4 1805 /* TBCTRL Bit Fields */
emilmont 78:ed8466a608b4 1806 #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
emilmont 78:ed8466a608b4 1807 #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
emilmont 78:ed8466a608b4 1808 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
emilmont 78:ed8466a608b4 1809 #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
emilmont 78:ed8466a608b4 1810 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
emilmont 78:ed8466a608b4 1811 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
emilmont 78:ed8466a608b4 1812 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
emilmont 78:ed8466a608b4 1813 /* DEVICECFG Bit Fields */
emilmont 78:ed8466a608b4 1814 #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 1815 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
emilmont 78:ed8466a608b4 1816 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
emilmont 78:ed8466a608b4 1817 /* DEVICETYPID Bit Fields */
emilmont 78:ed8466a608b4 1818 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 1819 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
emilmont 78:ed8466a608b4 1820 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
emilmont 78:ed8466a608b4 1821 /* PERIPHID Bit Fields */
emilmont 78:ed8466a608b4 1822 #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 1823 #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
emilmont 78:ed8466a608b4 1824 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
emilmont 78:ed8466a608b4 1825 /* COMPID Bit Fields */
emilmont 78:ed8466a608b4 1826 #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 1827 #define MTBDWT_COMPID_COMPID_SHIFT 0
emilmont 78:ed8466a608b4 1828 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
emilmont 78:ed8466a608b4 1829
emilmont 78:ed8466a608b4 1830 /**
emilmont 78:ed8466a608b4 1831 * @}
emilmont 78:ed8466a608b4 1832 */ /* end of group MTBDWT_Register_Masks */
emilmont 78:ed8466a608b4 1833
emilmont 78:ed8466a608b4 1834
emilmont 78:ed8466a608b4 1835 /* MTBDWT - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 1836 /** Peripheral MTBDWT base address */
emilmont 78:ed8466a608b4 1837 #define MTBDWT_BASE (0xF0001000u)
emilmont 78:ed8466a608b4 1838 /** Peripheral MTBDWT base pointer */
emilmont 78:ed8466a608b4 1839 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
emilmont 78:ed8466a608b4 1840 /** Array initializer of MTBDWT peripheral base pointers */
emilmont 78:ed8466a608b4 1841 #define MTBDWT_BASES { MTBDWT }
emilmont 78:ed8466a608b4 1842
emilmont 78:ed8466a608b4 1843 /**
emilmont 78:ed8466a608b4 1844 * @}
emilmont 78:ed8466a608b4 1845 */ /* end of group MTBDWT_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 1846
emilmont 78:ed8466a608b4 1847
emilmont 78:ed8466a608b4 1848 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 1849 -- NV Peripheral Access Layer
emilmont 78:ed8466a608b4 1850 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 1851
emilmont 78:ed8466a608b4 1852 /**
emilmont 78:ed8466a608b4 1853 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
emilmont 78:ed8466a608b4 1854 * @{
emilmont 78:ed8466a608b4 1855 */
emilmont 78:ed8466a608b4 1856
emilmont 78:ed8466a608b4 1857 /** NV - Register Layout Typedef */
emilmont 78:ed8466a608b4 1858 typedef struct {
emilmont 78:ed8466a608b4 1859 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
emilmont 78:ed8466a608b4 1860 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
emilmont 78:ed8466a608b4 1861 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
emilmont 78:ed8466a608b4 1862 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
emilmont 78:ed8466a608b4 1863 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
emilmont 78:ed8466a608b4 1864 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
emilmont 78:ed8466a608b4 1865 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
emilmont 78:ed8466a608b4 1866 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
emilmont 78:ed8466a608b4 1867 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
emilmont 78:ed8466a608b4 1868 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
emilmont 78:ed8466a608b4 1869 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
emilmont 78:ed8466a608b4 1870 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
emilmont 78:ed8466a608b4 1871 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
emilmont 78:ed8466a608b4 1872 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
emilmont 78:ed8466a608b4 1873 } NV_Type;
emilmont 78:ed8466a608b4 1874
emilmont 78:ed8466a608b4 1875 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 1876 -- NV Register Masks
emilmont 78:ed8466a608b4 1877 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 1878
emilmont 78:ed8466a608b4 1879 /**
emilmont 78:ed8466a608b4 1880 * @addtogroup NV_Register_Masks NV Register Masks
emilmont 78:ed8466a608b4 1881 * @{
emilmont 78:ed8466a608b4 1882 */
emilmont 78:ed8466a608b4 1883
emilmont 78:ed8466a608b4 1884 /* BACKKEY3 Bit Fields */
emilmont 78:ed8466a608b4 1885 #define NV_BACKKEY3_KEY_MASK 0xFFu
emilmont 78:ed8466a608b4 1886 #define NV_BACKKEY3_KEY_SHIFT 0
emilmont 78:ed8466a608b4 1887 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
emilmont 78:ed8466a608b4 1888 /* BACKKEY2 Bit Fields */
emilmont 78:ed8466a608b4 1889 #define NV_BACKKEY2_KEY_MASK 0xFFu
emilmont 78:ed8466a608b4 1890 #define NV_BACKKEY2_KEY_SHIFT 0
emilmont 78:ed8466a608b4 1891 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
emilmont 78:ed8466a608b4 1892 /* BACKKEY1 Bit Fields */
emilmont 78:ed8466a608b4 1893 #define NV_BACKKEY1_KEY_MASK 0xFFu
emilmont 78:ed8466a608b4 1894 #define NV_BACKKEY1_KEY_SHIFT 0
emilmont 78:ed8466a608b4 1895 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
emilmont 78:ed8466a608b4 1896 /* BACKKEY0 Bit Fields */
emilmont 78:ed8466a608b4 1897 #define NV_BACKKEY0_KEY_MASK 0xFFu
emilmont 78:ed8466a608b4 1898 #define NV_BACKKEY0_KEY_SHIFT 0
emilmont 78:ed8466a608b4 1899 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
emilmont 78:ed8466a608b4 1900 /* BACKKEY7 Bit Fields */
emilmont 78:ed8466a608b4 1901 #define NV_BACKKEY7_KEY_MASK 0xFFu
emilmont 78:ed8466a608b4 1902 #define NV_BACKKEY7_KEY_SHIFT 0
emilmont 78:ed8466a608b4 1903 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
emilmont 78:ed8466a608b4 1904 /* BACKKEY6 Bit Fields */
emilmont 78:ed8466a608b4 1905 #define NV_BACKKEY6_KEY_MASK 0xFFu
emilmont 78:ed8466a608b4 1906 #define NV_BACKKEY6_KEY_SHIFT 0
emilmont 78:ed8466a608b4 1907 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
emilmont 78:ed8466a608b4 1908 /* BACKKEY5 Bit Fields */
emilmont 78:ed8466a608b4 1909 #define NV_BACKKEY5_KEY_MASK 0xFFu
emilmont 78:ed8466a608b4 1910 #define NV_BACKKEY5_KEY_SHIFT 0
emilmont 78:ed8466a608b4 1911 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
emilmont 78:ed8466a608b4 1912 /* BACKKEY4 Bit Fields */
emilmont 78:ed8466a608b4 1913 #define NV_BACKKEY4_KEY_MASK 0xFFu
emilmont 78:ed8466a608b4 1914 #define NV_BACKKEY4_KEY_SHIFT 0
emilmont 78:ed8466a608b4 1915 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
emilmont 78:ed8466a608b4 1916 /* FPROT3 Bit Fields */
emilmont 78:ed8466a608b4 1917 #define NV_FPROT3_PROT_MASK 0xFFu
emilmont 78:ed8466a608b4 1918 #define NV_FPROT3_PROT_SHIFT 0
emilmont 78:ed8466a608b4 1919 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
emilmont 78:ed8466a608b4 1920 /* FPROT2 Bit Fields */
emilmont 78:ed8466a608b4 1921 #define NV_FPROT2_PROT_MASK 0xFFu
emilmont 78:ed8466a608b4 1922 #define NV_FPROT2_PROT_SHIFT 0
emilmont 78:ed8466a608b4 1923 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
emilmont 78:ed8466a608b4 1924 /* FPROT1 Bit Fields */
emilmont 78:ed8466a608b4 1925 #define NV_FPROT1_PROT_MASK 0xFFu
emilmont 78:ed8466a608b4 1926 #define NV_FPROT1_PROT_SHIFT 0
emilmont 78:ed8466a608b4 1927 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
emilmont 78:ed8466a608b4 1928 /* FPROT0 Bit Fields */
emilmont 78:ed8466a608b4 1929 #define NV_FPROT0_PROT_MASK 0xFFu
emilmont 78:ed8466a608b4 1930 #define NV_FPROT0_PROT_SHIFT 0
emilmont 78:ed8466a608b4 1931 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
emilmont 78:ed8466a608b4 1932 /* FSEC Bit Fields */
emilmont 78:ed8466a608b4 1933 #define NV_FSEC_SEC_MASK 0x3u
emilmont 78:ed8466a608b4 1934 #define NV_FSEC_SEC_SHIFT 0
emilmont 78:ed8466a608b4 1935 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
emilmont 78:ed8466a608b4 1936 #define NV_FSEC_FSLACC_MASK 0xCu
emilmont 78:ed8466a608b4 1937 #define NV_FSEC_FSLACC_SHIFT 2
emilmont 78:ed8466a608b4 1938 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
emilmont 78:ed8466a608b4 1939 #define NV_FSEC_MEEN_MASK 0x30u
emilmont 78:ed8466a608b4 1940 #define NV_FSEC_MEEN_SHIFT 4
emilmont 78:ed8466a608b4 1941 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
emilmont 78:ed8466a608b4 1942 #define NV_FSEC_KEYEN_MASK 0xC0u
emilmont 78:ed8466a608b4 1943 #define NV_FSEC_KEYEN_SHIFT 6
emilmont 78:ed8466a608b4 1944 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
emilmont 78:ed8466a608b4 1945 /* FOPT Bit Fields */
emilmont 78:ed8466a608b4 1946 #define NV_FOPT_LPBOOT0_MASK 0x1u
emilmont 78:ed8466a608b4 1947 #define NV_FOPT_LPBOOT0_SHIFT 0
emilmont 78:ed8466a608b4 1948 #define NV_FOPT_EZPORT_DIS_MASK 0x2u
emilmont 78:ed8466a608b4 1949 #define NV_FOPT_EZPORT_DIS_SHIFT 1
emilmont 78:ed8466a608b4 1950 #define NV_FOPT_NMI_DIS_MASK 0x4u
emilmont 78:ed8466a608b4 1951 #define NV_FOPT_NMI_DIS_SHIFT 2
emilmont 78:ed8466a608b4 1952 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
emilmont 78:ed8466a608b4 1953 #define NV_FOPT_RESET_PIN_CFG_SHIFT 3
emilmont 78:ed8466a608b4 1954 #define NV_FOPT_LPBOOT1_MASK 0x10u
emilmont 78:ed8466a608b4 1955 #define NV_FOPT_LPBOOT1_SHIFT 4
emilmont 78:ed8466a608b4 1956 #define NV_FOPT_FAST_INIT_MASK 0x20u
emilmont 78:ed8466a608b4 1957 #define NV_FOPT_FAST_INIT_SHIFT 5
emilmont 78:ed8466a608b4 1958
emilmont 78:ed8466a608b4 1959 /**
emilmont 78:ed8466a608b4 1960 * @}
emilmont 78:ed8466a608b4 1961 */ /* end of group NV_Register_Masks */
emilmont 78:ed8466a608b4 1962
emilmont 78:ed8466a608b4 1963
emilmont 78:ed8466a608b4 1964 /* NV - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 1965 /** Peripheral FTFA_FlashConfig base address */
emilmont 78:ed8466a608b4 1966 #define FTFA_FlashConfig_BASE (0x400u)
emilmont 78:ed8466a608b4 1967 /** Peripheral FTFA_FlashConfig base pointer */
emilmont 78:ed8466a608b4 1968 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
emilmont 78:ed8466a608b4 1969 /** Array initializer of NV peripheral base pointers */
emilmont 78:ed8466a608b4 1970 #define NV_BASES { FTFA_FlashConfig }
emilmont 78:ed8466a608b4 1971
emilmont 78:ed8466a608b4 1972 /**
emilmont 78:ed8466a608b4 1973 * @}
emilmont 78:ed8466a608b4 1974 */ /* end of group NV_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 1975
emilmont 78:ed8466a608b4 1976
emilmont 78:ed8466a608b4 1977 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 1978 -- OSC Peripheral Access Layer
emilmont 78:ed8466a608b4 1979 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 1980
emilmont 78:ed8466a608b4 1981 /**
emilmont 78:ed8466a608b4 1982 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
emilmont 78:ed8466a608b4 1983 * @{
emilmont 78:ed8466a608b4 1984 */
emilmont 78:ed8466a608b4 1985
emilmont 78:ed8466a608b4 1986 /** OSC - Register Layout Typedef */
emilmont 78:ed8466a608b4 1987 typedef struct {
emilmont 78:ed8466a608b4 1988 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
emilmont 78:ed8466a608b4 1989 } OSC_Type;
emilmont 78:ed8466a608b4 1990
emilmont 78:ed8466a608b4 1991 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 1992 -- OSC Register Masks
emilmont 78:ed8466a608b4 1993 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 1994
emilmont 78:ed8466a608b4 1995 /**
emilmont 78:ed8466a608b4 1996 * @addtogroup OSC_Register_Masks OSC Register Masks
emilmont 78:ed8466a608b4 1997 * @{
emilmont 78:ed8466a608b4 1998 */
emilmont 78:ed8466a608b4 1999
emilmont 78:ed8466a608b4 2000 /* CR Bit Fields */
emilmont 78:ed8466a608b4 2001 #define OSC_CR_SC16P_MASK 0x1u
emilmont 78:ed8466a608b4 2002 #define OSC_CR_SC16P_SHIFT 0
emilmont 78:ed8466a608b4 2003 #define OSC_CR_SC8P_MASK 0x2u
emilmont 78:ed8466a608b4 2004 #define OSC_CR_SC8P_SHIFT 1
emilmont 78:ed8466a608b4 2005 #define OSC_CR_SC4P_MASK 0x4u
emilmont 78:ed8466a608b4 2006 #define OSC_CR_SC4P_SHIFT 2
emilmont 78:ed8466a608b4 2007 #define OSC_CR_SC2P_MASK 0x8u
emilmont 78:ed8466a608b4 2008 #define OSC_CR_SC2P_SHIFT 3
emilmont 78:ed8466a608b4 2009 #define OSC_CR_EREFSTEN_MASK 0x20u
emilmont 78:ed8466a608b4 2010 #define OSC_CR_EREFSTEN_SHIFT 5
emilmont 78:ed8466a608b4 2011 #define OSC_CR_ERCLKEN_MASK 0x80u
emilmont 78:ed8466a608b4 2012 #define OSC_CR_ERCLKEN_SHIFT 7
emilmont 78:ed8466a608b4 2013
emilmont 78:ed8466a608b4 2014 /**
emilmont 78:ed8466a608b4 2015 * @}
emilmont 78:ed8466a608b4 2016 */ /* end of group OSC_Register_Masks */
emilmont 78:ed8466a608b4 2017
emilmont 78:ed8466a608b4 2018
emilmont 78:ed8466a608b4 2019 /* OSC - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 2020 /** Peripheral OSC0 base address */
emilmont 78:ed8466a608b4 2021 #define OSC0_BASE (0x40065000u)
emilmont 78:ed8466a608b4 2022 /** Peripheral OSC0 base pointer */
emilmont 78:ed8466a608b4 2023 #define OSC0 ((OSC_Type *)OSC0_BASE)
emilmont 78:ed8466a608b4 2024 /** Array initializer of OSC peripheral base pointers */
emilmont 78:ed8466a608b4 2025 #define OSC_BASES { OSC0 }
emilmont 78:ed8466a608b4 2026
emilmont 78:ed8466a608b4 2027 /**
emilmont 78:ed8466a608b4 2028 * @}
emilmont 78:ed8466a608b4 2029 */ /* end of group OSC_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 2030
emilmont 78:ed8466a608b4 2031
emilmont 78:ed8466a608b4 2032 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 2033 -- PIT Peripheral Access Layer
emilmont 78:ed8466a608b4 2034 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 2035
emilmont 78:ed8466a608b4 2036 /**
emilmont 78:ed8466a608b4 2037 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
emilmont 78:ed8466a608b4 2038 * @{
emilmont 78:ed8466a608b4 2039 */
emilmont 78:ed8466a608b4 2040
emilmont 78:ed8466a608b4 2041 /** PIT - Register Layout Typedef */
emilmont 78:ed8466a608b4 2042 typedef struct {
emilmont 78:ed8466a608b4 2043 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
emilmont 78:ed8466a608b4 2044 uint8_t RESERVED_0[220];
emilmont 78:ed8466a608b4 2045 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
emilmont 78:ed8466a608b4 2046 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
emilmont 78:ed8466a608b4 2047 uint8_t RESERVED_1[24];
emilmont 78:ed8466a608b4 2048 struct { /* offset: 0x100, array step: 0x10 */
emilmont 78:ed8466a608b4 2049 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
emilmont 78:ed8466a608b4 2050 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
emilmont 78:ed8466a608b4 2051 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
emilmont 78:ed8466a608b4 2052 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
emilmont 78:ed8466a608b4 2053 } CHANNEL[2];
emilmont 78:ed8466a608b4 2054 } PIT_Type;
emilmont 78:ed8466a608b4 2055
emilmont 78:ed8466a608b4 2056 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 2057 -- PIT Register Masks
emilmont 78:ed8466a608b4 2058 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 2059
emilmont 78:ed8466a608b4 2060 /**
emilmont 78:ed8466a608b4 2061 * @addtogroup PIT_Register_Masks PIT Register Masks
emilmont 78:ed8466a608b4 2062 * @{
emilmont 78:ed8466a608b4 2063 */
emilmont 78:ed8466a608b4 2064
emilmont 78:ed8466a608b4 2065 /* MCR Bit Fields */
emilmont 78:ed8466a608b4 2066 #define PIT_MCR_FRZ_MASK 0x1u
emilmont 78:ed8466a608b4 2067 #define PIT_MCR_FRZ_SHIFT 0
emilmont 78:ed8466a608b4 2068 #define PIT_MCR_MDIS_MASK 0x2u
emilmont 78:ed8466a608b4 2069 #define PIT_MCR_MDIS_SHIFT 1
emilmont 78:ed8466a608b4 2070 /* LTMR64H Bit Fields */
emilmont 78:ed8466a608b4 2071 #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 2072 #define PIT_LTMR64H_LTH_SHIFT 0
emilmont 78:ed8466a608b4 2073 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
emilmont 78:ed8466a608b4 2074 /* LTMR64L Bit Fields */
emilmont 78:ed8466a608b4 2075 #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 2076 #define PIT_LTMR64L_LTL_SHIFT 0
emilmont 78:ed8466a608b4 2077 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
emilmont 78:ed8466a608b4 2078 /* LDVAL Bit Fields */
emilmont 78:ed8466a608b4 2079 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 2080 #define PIT_LDVAL_TSV_SHIFT 0
emilmont 78:ed8466a608b4 2081 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
emilmont 78:ed8466a608b4 2082 /* CVAL Bit Fields */
emilmont 78:ed8466a608b4 2083 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 2084 #define PIT_CVAL_TVL_SHIFT 0
emilmont 78:ed8466a608b4 2085 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
emilmont 78:ed8466a608b4 2086 /* TCTRL Bit Fields */
emilmont 78:ed8466a608b4 2087 #define PIT_TCTRL_TEN_MASK 0x1u
emilmont 78:ed8466a608b4 2088 #define PIT_TCTRL_TEN_SHIFT 0
emilmont 78:ed8466a608b4 2089 #define PIT_TCTRL_TIE_MASK 0x2u
emilmont 78:ed8466a608b4 2090 #define PIT_TCTRL_TIE_SHIFT 1
emilmont 78:ed8466a608b4 2091 #define PIT_TCTRL_CHN_MASK 0x4u
emilmont 78:ed8466a608b4 2092 #define PIT_TCTRL_CHN_SHIFT 2
emilmont 78:ed8466a608b4 2093 /* TFLG Bit Fields */
emilmont 78:ed8466a608b4 2094 #define PIT_TFLG_TIF_MASK 0x1u
emilmont 78:ed8466a608b4 2095 #define PIT_TFLG_TIF_SHIFT 0
emilmont 78:ed8466a608b4 2096
emilmont 78:ed8466a608b4 2097 /**
emilmont 78:ed8466a608b4 2098 * @}
emilmont 78:ed8466a608b4 2099 */ /* end of group PIT_Register_Masks */
emilmont 78:ed8466a608b4 2100
emilmont 78:ed8466a608b4 2101
emilmont 78:ed8466a608b4 2102 /* PIT - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 2103 /** Peripheral PIT base address */
emilmont 78:ed8466a608b4 2104 #define PIT_BASE (0x40037000u)
emilmont 78:ed8466a608b4 2105 /** Peripheral PIT base pointer */
emilmont 78:ed8466a608b4 2106 #define PIT ((PIT_Type *)PIT_BASE)
emilmont 78:ed8466a608b4 2107 /** Array initializer of PIT peripheral base pointers */
emilmont 78:ed8466a608b4 2108 #define PIT_BASES { PIT }
emilmont 78:ed8466a608b4 2109
emilmont 78:ed8466a608b4 2110 /**
emilmont 78:ed8466a608b4 2111 * @}
emilmont 78:ed8466a608b4 2112 */ /* end of group PIT_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 2113
emilmont 78:ed8466a608b4 2114
emilmont 78:ed8466a608b4 2115 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 2116 -- PMC Peripheral Access Layer
emilmont 78:ed8466a608b4 2117 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 2118
emilmont 78:ed8466a608b4 2119 /**
emilmont 78:ed8466a608b4 2120 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
emilmont 78:ed8466a608b4 2121 * @{
emilmont 78:ed8466a608b4 2122 */
emilmont 78:ed8466a608b4 2123
emilmont 78:ed8466a608b4 2124 /** PMC - Register Layout Typedef */
emilmont 78:ed8466a608b4 2125 typedef struct {
emilmont 78:ed8466a608b4 2126 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
emilmont 78:ed8466a608b4 2127 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
emilmont 78:ed8466a608b4 2128 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
emilmont 78:ed8466a608b4 2129 } PMC_Type;
emilmont 78:ed8466a608b4 2130
emilmont 78:ed8466a608b4 2131 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 2132 -- PMC Register Masks
emilmont 78:ed8466a608b4 2133 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 2134
emilmont 78:ed8466a608b4 2135 /**
emilmont 78:ed8466a608b4 2136 * @addtogroup PMC_Register_Masks PMC Register Masks
emilmont 78:ed8466a608b4 2137 * @{
emilmont 78:ed8466a608b4 2138 */
emilmont 78:ed8466a608b4 2139
emilmont 78:ed8466a608b4 2140 /* LVDSC1 Bit Fields */
emilmont 78:ed8466a608b4 2141 #define PMC_LVDSC1_LVDV_MASK 0x3u
emilmont 78:ed8466a608b4 2142 #define PMC_LVDSC1_LVDV_SHIFT 0
emilmont 78:ed8466a608b4 2143 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
emilmont 78:ed8466a608b4 2144 #define PMC_LVDSC1_LVDRE_MASK 0x10u
emilmont 78:ed8466a608b4 2145 #define PMC_LVDSC1_LVDRE_SHIFT 4
emilmont 78:ed8466a608b4 2146 #define PMC_LVDSC1_LVDIE_MASK 0x20u
emilmont 78:ed8466a608b4 2147 #define PMC_LVDSC1_LVDIE_SHIFT 5
emilmont 78:ed8466a608b4 2148 #define PMC_LVDSC1_LVDACK_MASK 0x40u
emilmont 78:ed8466a608b4 2149 #define PMC_LVDSC1_LVDACK_SHIFT 6
emilmont 78:ed8466a608b4 2150 #define PMC_LVDSC1_LVDF_MASK 0x80u
emilmont 78:ed8466a608b4 2151 #define PMC_LVDSC1_LVDF_SHIFT 7
emilmont 78:ed8466a608b4 2152 /* LVDSC2 Bit Fields */
emilmont 78:ed8466a608b4 2153 #define PMC_LVDSC2_LVWV_MASK 0x3u
emilmont 78:ed8466a608b4 2154 #define PMC_LVDSC2_LVWV_SHIFT 0
emilmont 78:ed8466a608b4 2155 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
emilmont 78:ed8466a608b4 2156 #define PMC_LVDSC2_LVWIE_MASK 0x20u
emilmont 78:ed8466a608b4 2157 #define PMC_LVDSC2_LVWIE_SHIFT 5
emilmont 78:ed8466a608b4 2158 #define PMC_LVDSC2_LVWACK_MASK 0x40u
emilmont 78:ed8466a608b4 2159 #define PMC_LVDSC2_LVWACK_SHIFT 6
emilmont 78:ed8466a608b4 2160 #define PMC_LVDSC2_LVWF_MASK 0x80u
emilmont 78:ed8466a608b4 2161 #define PMC_LVDSC2_LVWF_SHIFT 7
emilmont 78:ed8466a608b4 2162 /* REGSC Bit Fields */
emilmont 78:ed8466a608b4 2163 #define PMC_REGSC_BGBE_MASK 0x1u
emilmont 78:ed8466a608b4 2164 #define PMC_REGSC_BGBE_SHIFT 0
emilmont 78:ed8466a608b4 2165 #define PMC_REGSC_REGONS_MASK 0x4u
emilmont 78:ed8466a608b4 2166 #define PMC_REGSC_REGONS_SHIFT 2
emilmont 78:ed8466a608b4 2167 #define PMC_REGSC_ACKISO_MASK 0x8u
emilmont 78:ed8466a608b4 2168 #define PMC_REGSC_ACKISO_SHIFT 3
emilmont 78:ed8466a608b4 2169 #define PMC_REGSC_BGEN_MASK 0x10u
emilmont 78:ed8466a608b4 2170 #define PMC_REGSC_BGEN_SHIFT 4
emilmont 78:ed8466a608b4 2171
emilmont 78:ed8466a608b4 2172 /**
emilmont 78:ed8466a608b4 2173 * @}
emilmont 78:ed8466a608b4 2174 */ /* end of group PMC_Register_Masks */
emilmont 78:ed8466a608b4 2175
emilmont 78:ed8466a608b4 2176
emilmont 78:ed8466a608b4 2177 /* PMC - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 2178 /** Peripheral PMC base address */
emilmont 78:ed8466a608b4 2179 #define PMC_BASE (0x4007D000u)
emilmont 78:ed8466a608b4 2180 /** Peripheral PMC base pointer */
emilmont 78:ed8466a608b4 2181 #define PMC ((PMC_Type *)PMC_BASE)
emilmont 78:ed8466a608b4 2182 /** Array initializer of PMC peripheral base pointers */
emilmont 78:ed8466a608b4 2183 #define PMC_BASES { PMC }
emilmont 78:ed8466a608b4 2184
emilmont 78:ed8466a608b4 2185 /**
emilmont 78:ed8466a608b4 2186 * @}
emilmont 78:ed8466a608b4 2187 */ /* end of group PMC_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 2188
emilmont 78:ed8466a608b4 2189
emilmont 78:ed8466a608b4 2190 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 2191 -- PORT Peripheral Access Layer
emilmont 78:ed8466a608b4 2192 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 2193
emilmont 78:ed8466a608b4 2194 /**
emilmont 78:ed8466a608b4 2195 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
emilmont 78:ed8466a608b4 2196 * @{
emilmont 78:ed8466a608b4 2197 */
emilmont 78:ed8466a608b4 2198
emilmont 78:ed8466a608b4 2199 /** PORT - Register Layout Typedef */
emilmont 78:ed8466a608b4 2200 typedef struct {
emilmont 78:ed8466a608b4 2201 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
emilmont 78:ed8466a608b4 2202 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
emilmont 78:ed8466a608b4 2203 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
emilmont 78:ed8466a608b4 2204 uint8_t RESERVED_0[24];
emilmont 78:ed8466a608b4 2205 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
emilmont 78:ed8466a608b4 2206 } PORT_Type;
emilmont 78:ed8466a608b4 2207
emilmont 78:ed8466a608b4 2208 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 2209 -- PORT Register Masks
emilmont 78:ed8466a608b4 2210 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 2211
emilmont 78:ed8466a608b4 2212 /**
emilmont 78:ed8466a608b4 2213 * @addtogroup PORT_Register_Masks PORT Register Masks
emilmont 78:ed8466a608b4 2214 * @{
emilmont 78:ed8466a608b4 2215 */
emilmont 78:ed8466a608b4 2216
emilmont 78:ed8466a608b4 2217 /* PCR Bit Fields */
emilmont 78:ed8466a608b4 2218 #define PORT_PCR_PS_MASK 0x1u
emilmont 78:ed8466a608b4 2219 #define PORT_PCR_PS_SHIFT 0
emilmont 78:ed8466a608b4 2220 #define PORT_PCR_PE_MASK 0x2u
emilmont 78:ed8466a608b4 2221 #define PORT_PCR_PE_SHIFT 1
emilmont 78:ed8466a608b4 2222 #define PORT_PCR_SRE_MASK 0x4u
emilmont 78:ed8466a608b4 2223 #define PORT_PCR_SRE_SHIFT 2
emilmont 78:ed8466a608b4 2224 #define PORT_PCR_PFE_MASK 0x10u
emilmont 78:ed8466a608b4 2225 #define PORT_PCR_PFE_SHIFT 4
emilmont 78:ed8466a608b4 2226 #define PORT_PCR_DSE_MASK 0x40u
emilmont 78:ed8466a608b4 2227 #define PORT_PCR_DSE_SHIFT 6
emilmont 78:ed8466a608b4 2228 #define PORT_PCR_MUX_MASK 0x700u
emilmont 78:ed8466a608b4 2229 #define PORT_PCR_MUX_SHIFT 8
emilmont 78:ed8466a608b4 2230 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
emilmont 78:ed8466a608b4 2231 #define PORT_PCR_IRQC_MASK 0xF0000u
emilmont 78:ed8466a608b4 2232 #define PORT_PCR_IRQC_SHIFT 16
emilmont 78:ed8466a608b4 2233 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
emilmont 78:ed8466a608b4 2234 #define PORT_PCR_ISF_MASK 0x1000000u
emilmont 78:ed8466a608b4 2235 #define PORT_PCR_ISF_SHIFT 24
emilmont 78:ed8466a608b4 2236 /* GPCLR Bit Fields */
emilmont 78:ed8466a608b4 2237 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
emilmont 78:ed8466a608b4 2238 #define PORT_GPCLR_GPWD_SHIFT 0
emilmont 78:ed8466a608b4 2239 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
emilmont 78:ed8466a608b4 2240 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
emilmont 78:ed8466a608b4 2241 #define PORT_GPCLR_GPWE_SHIFT 16
emilmont 78:ed8466a608b4 2242 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
emilmont 78:ed8466a608b4 2243 /* GPCHR Bit Fields */
emilmont 78:ed8466a608b4 2244 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
emilmont 78:ed8466a608b4 2245 #define PORT_GPCHR_GPWD_SHIFT 0
emilmont 78:ed8466a608b4 2246 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
emilmont 78:ed8466a608b4 2247 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
emilmont 78:ed8466a608b4 2248 #define PORT_GPCHR_GPWE_SHIFT 16
emilmont 78:ed8466a608b4 2249 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
emilmont 78:ed8466a608b4 2250 /* ISFR Bit Fields */
emilmont 78:ed8466a608b4 2251 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 2252 #define PORT_ISFR_ISF_SHIFT 0
emilmont 78:ed8466a608b4 2253 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
emilmont 78:ed8466a608b4 2254
emilmont 78:ed8466a608b4 2255 /**
emilmont 78:ed8466a608b4 2256 * @}
emilmont 78:ed8466a608b4 2257 */ /* end of group PORT_Register_Masks */
emilmont 78:ed8466a608b4 2258
emilmont 78:ed8466a608b4 2259
emilmont 78:ed8466a608b4 2260 /* PORT - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 2261 /** Peripheral PORTA base address */
emilmont 78:ed8466a608b4 2262 #define PORTA_BASE (0x40049000u)
emilmont 78:ed8466a608b4 2263 /** Peripheral PORTA base pointer */
emilmont 78:ed8466a608b4 2264 #define PORTA ((PORT_Type *)PORTA_BASE)
emilmont 78:ed8466a608b4 2265 /** Peripheral PORTB base address */
emilmont 78:ed8466a608b4 2266 #define PORTB_BASE (0x4004A000u)
emilmont 78:ed8466a608b4 2267 /** Peripheral PORTB base pointer */
emilmont 78:ed8466a608b4 2268 #define PORTB ((PORT_Type *)PORTB_BASE)
emilmont 78:ed8466a608b4 2269 /** Array initializer of PORT peripheral base pointers */
emilmont 78:ed8466a608b4 2270 #define PORT_BASES { PORTA, PORTB }
emilmont 78:ed8466a608b4 2271
emilmont 78:ed8466a608b4 2272 /**
emilmont 78:ed8466a608b4 2273 * @}
emilmont 78:ed8466a608b4 2274 */ /* end of group PORT_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 2275
emilmont 78:ed8466a608b4 2276
emilmont 78:ed8466a608b4 2277 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 2278 -- RCM Peripheral Access Layer
emilmont 78:ed8466a608b4 2279 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 2280
emilmont 78:ed8466a608b4 2281 /**
emilmont 78:ed8466a608b4 2282 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
emilmont 78:ed8466a608b4 2283 * @{
emilmont 78:ed8466a608b4 2284 */
emilmont 78:ed8466a608b4 2285
emilmont 78:ed8466a608b4 2286 /** RCM - Register Layout Typedef */
emilmont 78:ed8466a608b4 2287 typedef struct {
emilmont 78:ed8466a608b4 2288 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
emilmont 78:ed8466a608b4 2289 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
emilmont 78:ed8466a608b4 2290 uint8_t RESERVED_0[2];
emilmont 78:ed8466a608b4 2291 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
emilmont 78:ed8466a608b4 2292 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
emilmont 78:ed8466a608b4 2293 } RCM_Type;
emilmont 78:ed8466a608b4 2294
emilmont 78:ed8466a608b4 2295 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 2296 -- RCM Register Masks
emilmont 78:ed8466a608b4 2297 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 2298
emilmont 78:ed8466a608b4 2299 /**
emilmont 78:ed8466a608b4 2300 * @addtogroup RCM_Register_Masks RCM Register Masks
emilmont 78:ed8466a608b4 2301 * @{
emilmont 78:ed8466a608b4 2302 */
emilmont 78:ed8466a608b4 2303
emilmont 78:ed8466a608b4 2304 /* SRS0 Bit Fields */
emilmont 78:ed8466a608b4 2305 #define RCM_SRS0_WAKEUP_MASK 0x1u
emilmont 78:ed8466a608b4 2306 #define RCM_SRS0_WAKEUP_SHIFT 0
emilmont 78:ed8466a608b4 2307 #define RCM_SRS0_LVD_MASK 0x2u
emilmont 78:ed8466a608b4 2308 #define RCM_SRS0_LVD_SHIFT 1
emilmont 78:ed8466a608b4 2309 #define RCM_SRS0_LOC_MASK 0x4u
emilmont 78:ed8466a608b4 2310 #define RCM_SRS0_LOC_SHIFT 2
emilmont 78:ed8466a608b4 2311 #define RCM_SRS0_WDOG_MASK 0x20u
emilmont 78:ed8466a608b4 2312 #define RCM_SRS0_WDOG_SHIFT 5
emilmont 78:ed8466a608b4 2313 #define RCM_SRS0_PIN_MASK 0x40u
emilmont 78:ed8466a608b4 2314 #define RCM_SRS0_PIN_SHIFT 6
emilmont 78:ed8466a608b4 2315 #define RCM_SRS0_POR_MASK 0x80u
emilmont 78:ed8466a608b4 2316 #define RCM_SRS0_POR_SHIFT 7
emilmont 78:ed8466a608b4 2317 /* SRS1 Bit Fields */
emilmont 78:ed8466a608b4 2318 #define RCM_SRS1_LOCKUP_MASK 0x2u
emilmont 78:ed8466a608b4 2319 #define RCM_SRS1_LOCKUP_SHIFT 1
emilmont 78:ed8466a608b4 2320 #define RCM_SRS1_SW_MASK 0x4u
emilmont 78:ed8466a608b4 2321 #define RCM_SRS1_SW_SHIFT 2
emilmont 78:ed8466a608b4 2322 #define RCM_SRS1_MDM_AP_MASK 0x8u
emilmont 78:ed8466a608b4 2323 #define RCM_SRS1_MDM_AP_SHIFT 3
emilmont 78:ed8466a608b4 2324 #define RCM_SRS1_SACKERR_MASK 0x20u
emilmont 78:ed8466a608b4 2325 #define RCM_SRS1_SACKERR_SHIFT 5
emilmont 78:ed8466a608b4 2326 /* RPFC Bit Fields */
emilmont 78:ed8466a608b4 2327 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
emilmont 78:ed8466a608b4 2328 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
emilmont 78:ed8466a608b4 2329 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
emilmont 78:ed8466a608b4 2330 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
emilmont 78:ed8466a608b4 2331 #define RCM_RPFC_RSTFLTSS_SHIFT 2
emilmont 78:ed8466a608b4 2332 /* RPFW Bit Fields */
emilmont 78:ed8466a608b4 2333 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
emilmont 78:ed8466a608b4 2334 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
emilmont 78:ed8466a608b4 2335 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
emilmont 78:ed8466a608b4 2336
emilmont 78:ed8466a608b4 2337 /**
emilmont 78:ed8466a608b4 2338 * @}
emilmont 78:ed8466a608b4 2339 */ /* end of group RCM_Register_Masks */
emilmont 78:ed8466a608b4 2340
emilmont 78:ed8466a608b4 2341
emilmont 78:ed8466a608b4 2342 /* RCM - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 2343 /** Peripheral RCM base address */
emilmont 78:ed8466a608b4 2344 #define RCM_BASE (0x4007F000u)
emilmont 78:ed8466a608b4 2345 /** Peripheral RCM base pointer */
emilmont 78:ed8466a608b4 2346 #define RCM ((RCM_Type *)RCM_BASE)
emilmont 78:ed8466a608b4 2347 /** Array initializer of RCM peripheral base pointers */
emilmont 78:ed8466a608b4 2348 #define RCM_BASES { RCM }
emilmont 78:ed8466a608b4 2349
emilmont 78:ed8466a608b4 2350 /**
emilmont 78:ed8466a608b4 2351 * @}
emilmont 78:ed8466a608b4 2352 */ /* end of group RCM_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 2353
emilmont 78:ed8466a608b4 2354
emilmont 78:ed8466a608b4 2355 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 2356 -- ROM Peripheral Access Layer
emilmont 78:ed8466a608b4 2357 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 2358
emilmont 78:ed8466a608b4 2359 /**
emilmont 78:ed8466a608b4 2360 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
emilmont 78:ed8466a608b4 2361 * @{
emilmont 78:ed8466a608b4 2362 */
emilmont 78:ed8466a608b4 2363
emilmont 78:ed8466a608b4 2364 /** ROM - Register Layout Typedef */
emilmont 78:ed8466a608b4 2365 typedef struct {
emilmont 78:ed8466a608b4 2366 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
emilmont 78:ed8466a608b4 2367 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
emilmont 78:ed8466a608b4 2368 uint8_t RESERVED_0[4028];
emilmont 78:ed8466a608b4 2369 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
emilmont 78:ed8466a608b4 2370 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
emilmont 78:ed8466a608b4 2371 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
emilmont 78:ed8466a608b4 2372 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
emilmont 78:ed8466a608b4 2373 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
emilmont 78:ed8466a608b4 2374 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
emilmont 78:ed8466a608b4 2375 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
emilmont 78:ed8466a608b4 2376 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
emilmont 78:ed8466a608b4 2377 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
emilmont 78:ed8466a608b4 2378 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
emilmont 78:ed8466a608b4 2379 } ROM_Type;
emilmont 78:ed8466a608b4 2380
emilmont 78:ed8466a608b4 2381 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 2382 -- ROM Register Masks
emilmont 78:ed8466a608b4 2383 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 2384
emilmont 78:ed8466a608b4 2385 /**
emilmont 78:ed8466a608b4 2386 * @addtogroup ROM_Register_Masks ROM Register Masks
emilmont 78:ed8466a608b4 2387 * @{
emilmont 78:ed8466a608b4 2388 */
emilmont 78:ed8466a608b4 2389
emilmont 78:ed8466a608b4 2390 /* ENTRY Bit Fields */
emilmont 78:ed8466a608b4 2391 #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 2392 #define ROM_ENTRY_ENTRY_SHIFT 0
emilmont 78:ed8466a608b4 2393 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
emilmont 78:ed8466a608b4 2394 /* TABLEMARK Bit Fields */
emilmont 78:ed8466a608b4 2395 #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 2396 #define ROM_TABLEMARK_MARK_SHIFT 0
emilmont 78:ed8466a608b4 2397 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
emilmont 78:ed8466a608b4 2398 /* SYSACCESS Bit Fields */
emilmont 78:ed8466a608b4 2399 #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 2400 #define ROM_SYSACCESS_SYSACCESS_SHIFT 0
emilmont 78:ed8466a608b4 2401 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
emilmont 78:ed8466a608b4 2402 /* PERIPHID4 Bit Fields */
emilmont 78:ed8466a608b4 2403 #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 2404 #define ROM_PERIPHID4_PERIPHID_SHIFT 0
emilmont 78:ed8466a608b4 2405 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
emilmont 78:ed8466a608b4 2406 /* PERIPHID5 Bit Fields */
emilmont 78:ed8466a608b4 2407 #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 2408 #define ROM_PERIPHID5_PERIPHID_SHIFT 0
emilmont 78:ed8466a608b4 2409 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
emilmont 78:ed8466a608b4 2410 /* PERIPHID6 Bit Fields */
emilmont 78:ed8466a608b4 2411 #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 2412 #define ROM_PERIPHID6_PERIPHID_SHIFT 0
emilmont 78:ed8466a608b4 2413 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
emilmont 78:ed8466a608b4 2414 /* PERIPHID7 Bit Fields */
emilmont 78:ed8466a608b4 2415 #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 2416 #define ROM_PERIPHID7_PERIPHID_SHIFT 0
emilmont 78:ed8466a608b4 2417 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
emilmont 78:ed8466a608b4 2418 /* PERIPHID0 Bit Fields */
emilmont 78:ed8466a608b4 2419 #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 2420 #define ROM_PERIPHID0_PERIPHID_SHIFT 0
emilmont 78:ed8466a608b4 2421 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
emilmont 78:ed8466a608b4 2422 /* PERIPHID1 Bit Fields */
emilmont 78:ed8466a608b4 2423 #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 2424 #define ROM_PERIPHID1_PERIPHID_SHIFT 0
emilmont 78:ed8466a608b4 2425 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
emilmont 78:ed8466a608b4 2426 /* PERIPHID2 Bit Fields */
emilmont 78:ed8466a608b4 2427 #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 2428 #define ROM_PERIPHID2_PERIPHID_SHIFT 0
emilmont 78:ed8466a608b4 2429 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
emilmont 78:ed8466a608b4 2430 /* PERIPHID3 Bit Fields */
emilmont 78:ed8466a608b4 2431 #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 2432 #define ROM_PERIPHID3_PERIPHID_SHIFT 0
emilmont 78:ed8466a608b4 2433 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
emilmont 78:ed8466a608b4 2434 /* COMPID Bit Fields */
emilmont 78:ed8466a608b4 2435 #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 2436 #define ROM_COMPID_COMPID_SHIFT 0
emilmont 78:ed8466a608b4 2437 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
emilmont 78:ed8466a608b4 2438
emilmont 78:ed8466a608b4 2439 /**
emilmont 78:ed8466a608b4 2440 * @}
emilmont 78:ed8466a608b4 2441 */ /* end of group ROM_Register_Masks */
emilmont 78:ed8466a608b4 2442
emilmont 78:ed8466a608b4 2443
emilmont 78:ed8466a608b4 2444 /* ROM - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 2445 /** Peripheral ROM base address */
emilmont 78:ed8466a608b4 2446 #define ROM_BASE (0xF0002000u)
emilmont 78:ed8466a608b4 2447 /** Peripheral ROM base pointer */
emilmont 78:ed8466a608b4 2448 #define ROM ((ROM_Type *)ROM_BASE)
emilmont 78:ed8466a608b4 2449 /** Array initializer of ROM peripheral base pointers */
emilmont 78:ed8466a608b4 2450 #define ROM_BASES { ROM }
emilmont 78:ed8466a608b4 2451
emilmont 78:ed8466a608b4 2452 /**
emilmont 78:ed8466a608b4 2453 * @}
emilmont 78:ed8466a608b4 2454 */ /* end of group ROM_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 2455
emilmont 78:ed8466a608b4 2456
emilmont 78:ed8466a608b4 2457 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 2458 -- RTC Peripheral Access Layer
emilmont 78:ed8466a608b4 2459 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 2460
emilmont 78:ed8466a608b4 2461 /**
emilmont 78:ed8466a608b4 2462 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
emilmont 78:ed8466a608b4 2463 * @{
emilmont 78:ed8466a608b4 2464 */
emilmont 78:ed8466a608b4 2465
emilmont 78:ed8466a608b4 2466 /** RTC - Register Layout Typedef */
emilmont 78:ed8466a608b4 2467 typedef struct {
emilmont 78:ed8466a608b4 2468 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
emilmont 78:ed8466a608b4 2469 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
emilmont 78:ed8466a608b4 2470 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
emilmont 78:ed8466a608b4 2471 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
emilmont 78:ed8466a608b4 2472 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
emilmont 78:ed8466a608b4 2473 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
emilmont 78:ed8466a608b4 2474 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
emilmont 78:ed8466a608b4 2475 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
emilmont 78:ed8466a608b4 2476 } RTC_Type;
emilmont 78:ed8466a608b4 2477
emilmont 78:ed8466a608b4 2478 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 2479 -- RTC Register Masks
emilmont 78:ed8466a608b4 2480 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 2481
emilmont 78:ed8466a608b4 2482 /**
emilmont 78:ed8466a608b4 2483 * @addtogroup RTC_Register_Masks RTC Register Masks
emilmont 78:ed8466a608b4 2484 * @{
emilmont 78:ed8466a608b4 2485 */
emilmont 78:ed8466a608b4 2486
emilmont 78:ed8466a608b4 2487 /* TSR Bit Fields */
emilmont 78:ed8466a608b4 2488 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 2489 #define RTC_TSR_TSR_SHIFT 0
emilmont 78:ed8466a608b4 2490 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
emilmont 78:ed8466a608b4 2491 /* TPR Bit Fields */
emilmont 78:ed8466a608b4 2492 #define RTC_TPR_TPR_MASK 0xFFFFu
emilmont 78:ed8466a608b4 2493 #define RTC_TPR_TPR_SHIFT 0
emilmont 78:ed8466a608b4 2494 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
emilmont 78:ed8466a608b4 2495 /* TAR Bit Fields */
emilmont 78:ed8466a608b4 2496 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 2497 #define RTC_TAR_TAR_SHIFT 0
emilmont 78:ed8466a608b4 2498 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
emilmont 78:ed8466a608b4 2499 /* TCR Bit Fields */
emilmont 78:ed8466a608b4 2500 #define RTC_TCR_TCR_MASK 0xFFu
emilmont 78:ed8466a608b4 2501 #define RTC_TCR_TCR_SHIFT 0
emilmont 78:ed8466a608b4 2502 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
emilmont 78:ed8466a608b4 2503 #define RTC_TCR_CIR_MASK 0xFF00u
emilmont 78:ed8466a608b4 2504 #define RTC_TCR_CIR_SHIFT 8
emilmont 78:ed8466a608b4 2505 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
emilmont 78:ed8466a608b4 2506 #define RTC_TCR_TCV_MASK 0xFF0000u
emilmont 78:ed8466a608b4 2507 #define RTC_TCR_TCV_SHIFT 16
emilmont 78:ed8466a608b4 2508 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
emilmont 78:ed8466a608b4 2509 #define RTC_TCR_CIC_MASK 0xFF000000u
emilmont 78:ed8466a608b4 2510 #define RTC_TCR_CIC_SHIFT 24
emilmont 78:ed8466a608b4 2511 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
emilmont 78:ed8466a608b4 2512 /* CR Bit Fields */
emilmont 78:ed8466a608b4 2513 #define RTC_CR_SWR_MASK 0x1u
emilmont 78:ed8466a608b4 2514 #define RTC_CR_SWR_SHIFT 0
emilmont 78:ed8466a608b4 2515 #define RTC_CR_WPE_MASK 0x2u
emilmont 78:ed8466a608b4 2516 #define RTC_CR_WPE_SHIFT 1
emilmont 78:ed8466a608b4 2517 #define RTC_CR_SUP_MASK 0x4u
emilmont 78:ed8466a608b4 2518 #define RTC_CR_SUP_SHIFT 2
emilmont 78:ed8466a608b4 2519 #define RTC_CR_UM_MASK 0x8u
emilmont 78:ed8466a608b4 2520 #define RTC_CR_UM_SHIFT 3
emilmont 78:ed8466a608b4 2521 #define RTC_CR_OSCE_MASK 0x100u
emilmont 78:ed8466a608b4 2522 #define RTC_CR_OSCE_SHIFT 8
emilmont 78:ed8466a608b4 2523 #define RTC_CR_CLKO_MASK 0x200u
emilmont 78:ed8466a608b4 2524 #define RTC_CR_CLKO_SHIFT 9
emilmont 78:ed8466a608b4 2525 #define RTC_CR_SC16P_MASK 0x400u
emilmont 78:ed8466a608b4 2526 #define RTC_CR_SC16P_SHIFT 10
emilmont 78:ed8466a608b4 2527 #define RTC_CR_SC8P_MASK 0x800u
emilmont 78:ed8466a608b4 2528 #define RTC_CR_SC8P_SHIFT 11
emilmont 78:ed8466a608b4 2529 #define RTC_CR_SC4P_MASK 0x1000u
emilmont 78:ed8466a608b4 2530 #define RTC_CR_SC4P_SHIFT 12
emilmont 78:ed8466a608b4 2531 #define RTC_CR_SC2P_MASK 0x2000u
emilmont 78:ed8466a608b4 2532 #define RTC_CR_SC2P_SHIFT 13
emilmont 78:ed8466a608b4 2533 /* SR Bit Fields */
emilmont 78:ed8466a608b4 2534 #define RTC_SR_TIF_MASK 0x1u
emilmont 78:ed8466a608b4 2535 #define RTC_SR_TIF_SHIFT 0
emilmont 78:ed8466a608b4 2536 #define RTC_SR_TOF_MASK 0x2u
emilmont 78:ed8466a608b4 2537 #define RTC_SR_TOF_SHIFT 1
emilmont 78:ed8466a608b4 2538 #define RTC_SR_TAF_MASK 0x4u
emilmont 78:ed8466a608b4 2539 #define RTC_SR_TAF_SHIFT 2
emilmont 78:ed8466a608b4 2540 #define RTC_SR_TCE_MASK 0x10u
emilmont 78:ed8466a608b4 2541 #define RTC_SR_TCE_SHIFT 4
emilmont 78:ed8466a608b4 2542 /* LR Bit Fields */
emilmont 78:ed8466a608b4 2543 #define RTC_LR_TCL_MASK 0x8u
emilmont 78:ed8466a608b4 2544 #define RTC_LR_TCL_SHIFT 3
emilmont 78:ed8466a608b4 2545 #define RTC_LR_CRL_MASK 0x10u
emilmont 78:ed8466a608b4 2546 #define RTC_LR_CRL_SHIFT 4
emilmont 78:ed8466a608b4 2547 #define RTC_LR_SRL_MASK 0x20u
emilmont 78:ed8466a608b4 2548 #define RTC_LR_SRL_SHIFT 5
emilmont 78:ed8466a608b4 2549 #define RTC_LR_LRL_MASK 0x40u
emilmont 78:ed8466a608b4 2550 #define RTC_LR_LRL_SHIFT 6
emilmont 78:ed8466a608b4 2551 /* IER Bit Fields */
emilmont 78:ed8466a608b4 2552 #define RTC_IER_TIIE_MASK 0x1u
emilmont 78:ed8466a608b4 2553 #define RTC_IER_TIIE_SHIFT 0
emilmont 78:ed8466a608b4 2554 #define RTC_IER_TOIE_MASK 0x2u
emilmont 78:ed8466a608b4 2555 #define RTC_IER_TOIE_SHIFT 1
emilmont 78:ed8466a608b4 2556 #define RTC_IER_TAIE_MASK 0x4u
emilmont 78:ed8466a608b4 2557 #define RTC_IER_TAIE_SHIFT 2
emilmont 78:ed8466a608b4 2558 #define RTC_IER_TSIE_MASK 0x10u
emilmont 78:ed8466a608b4 2559 #define RTC_IER_TSIE_SHIFT 4
emilmont 78:ed8466a608b4 2560 #define RTC_IER_WPON_MASK 0x80u
emilmont 78:ed8466a608b4 2561 #define RTC_IER_WPON_SHIFT 7
emilmont 78:ed8466a608b4 2562
emilmont 78:ed8466a608b4 2563 /**
emilmont 78:ed8466a608b4 2564 * @}
emilmont 78:ed8466a608b4 2565 */ /* end of group RTC_Register_Masks */
emilmont 78:ed8466a608b4 2566
emilmont 78:ed8466a608b4 2567
emilmont 78:ed8466a608b4 2568 /* RTC - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 2569 /** Peripheral RTC base address */
emilmont 78:ed8466a608b4 2570 #define RTC_BASE (0x4003D000u)
emilmont 78:ed8466a608b4 2571 /** Peripheral RTC base pointer */
emilmont 78:ed8466a608b4 2572 #define RTC ((RTC_Type *)RTC_BASE)
emilmont 78:ed8466a608b4 2573 /** Array initializer of RTC peripheral base pointers */
emilmont 78:ed8466a608b4 2574 #define RTC_BASES { RTC }
emilmont 78:ed8466a608b4 2575
emilmont 78:ed8466a608b4 2576 /**
emilmont 78:ed8466a608b4 2577 * @}
emilmont 78:ed8466a608b4 2578 */ /* end of group RTC_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 2579
emilmont 78:ed8466a608b4 2580
emilmont 78:ed8466a608b4 2581 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 2582 -- SIM Peripheral Access Layer
emilmont 78:ed8466a608b4 2583 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 2584
emilmont 78:ed8466a608b4 2585 /**
emilmont 78:ed8466a608b4 2586 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
emilmont 78:ed8466a608b4 2587 * @{
emilmont 78:ed8466a608b4 2588 */
emilmont 78:ed8466a608b4 2589
emilmont 78:ed8466a608b4 2590 /** SIM - Register Layout Typedef */
emilmont 78:ed8466a608b4 2591 typedef struct {
emilmont 78:ed8466a608b4 2592 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
emilmont 78:ed8466a608b4 2593 __I uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
emilmont 78:ed8466a608b4 2594 uint8_t RESERVED_0[4092];
emilmont 78:ed8466a608b4 2595 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
emilmont 78:ed8466a608b4 2596 uint8_t RESERVED_1[4];
emilmont 78:ed8466a608b4 2597 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
emilmont 78:ed8466a608b4 2598 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
emilmont 78:ed8466a608b4 2599 uint8_t RESERVED_2[4];
emilmont 78:ed8466a608b4 2600 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
emilmont 78:ed8466a608b4 2601 uint8_t RESERVED_3[8];
emilmont 78:ed8466a608b4 2602 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
emilmont 78:ed8466a608b4 2603 uint8_t RESERVED_4[12];
emilmont 78:ed8466a608b4 2604 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
emilmont 78:ed8466a608b4 2605 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
emilmont 78:ed8466a608b4 2606 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
emilmont 78:ed8466a608b4 2607 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
emilmont 78:ed8466a608b4 2608 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
emilmont 78:ed8466a608b4 2609 uint8_t RESERVED_5[4];
emilmont 78:ed8466a608b4 2610 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
emilmont 78:ed8466a608b4 2611 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
emilmont 78:ed8466a608b4 2612 uint8_t RESERVED_6[4];
emilmont 78:ed8466a608b4 2613 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
emilmont 78:ed8466a608b4 2614 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
emilmont 78:ed8466a608b4 2615 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
emilmont 78:ed8466a608b4 2616 uint8_t RESERVED_7[156];
emilmont 78:ed8466a608b4 2617 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
emilmont 78:ed8466a608b4 2618 __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
emilmont 78:ed8466a608b4 2619 } SIM_Type;
emilmont 78:ed8466a608b4 2620
emilmont 78:ed8466a608b4 2621 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 2622 -- SIM Register Masks
emilmont 78:ed8466a608b4 2623 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 2624
emilmont 78:ed8466a608b4 2625 /**
emilmont 78:ed8466a608b4 2626 * @addtogroup SIM_Register_Masks SIM Register Masks
emilmont 78:ed8466a608b4 2627 * @{
emilmont 78:ed8466a608b4 2628 */
emilmont 78:ed8466a608b4 2629
emilmont 78:ed8466a608b4 2630 /* SOPT1 Bit Fields */
emilmont 78:ed8466a608b4 2631 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
emilmont 78:ed8466a608b4 2632 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
emilmont 78:ed8466a608b4 2633 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
emilmont 78:ed8466a608b4 2634 /* SOPT2 Bit Fields */
emilmont 78:ed8466a608b4 2635 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
emilmont 78:ed8466a608b4 2636 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
emilmont 78:ed8466a608b4 2637 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
emilmont 78:ed8466a608b4 2638 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
emilmont 78:ed8466a608b4 2639 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
emilmont 78:ed8466a608b4 2640 #define SIM_SOPT2_TPMSRC_MASK 0x3000000u
emilmont 78:ed8466a608b4 2641 #define SIM_SOPT2_TPMSRC_SHIFT 24
emilmont 78:ed8466a608b4 2642 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
emilmont 78:ed8466a608b4 2643 #define SIM_SOPT2_UART0SRC_MASK 0xC000000u
emilmont 78:ed8466a608b4 2644 #define SIM_SOPT2_UART0SRC_SHIFT 26
emilmont 78:ed8466a608b4 2645 #define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
emilmont 78:ed8466a608b4 2646 /* SOPT4 Bit Fields */
emilmont 78:ed8466a608b4 2647 #define SIM_SOPT4_TPM1CH0SRC_MASK 0x40000u
emilmont 78:ed8466a608b4 2648 #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
emilmont 78:ed8466a608b4 2649 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
emilmont 78:ed8466a608b4 2650 #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
emilmont 78:ed8466a608b4 2651 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
emilmont 78:ed8466a608b4 2652 #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
emilmont 78:ed8466a608b4 2653 /* SOPT5 Bit Fields */
emilmont 78:ed8466a608b4 2654 #define SIM_SOPT5_UART0TXSRC_MASK 0x1u
emilmont 78:ed8466a608b4 2655 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
emilmont 78:ed8466a608b4 2656 #define SIM_SOPT5_UART0RXSRC_MASK 0x4u
emilmont 78:ed8466a608b4 2657 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
emilmont 78:ed8466a608b4 2658 #define SIM_SOPT5_UART0ODE_MASK 0x10000u
emilmont 78:ed8466a608b4 2659 #define SIM_SOPT5_UART0ODE_SHIFT 16
emilmont 78:ed8466a608b4 2660 /* SOPT7 Bit Fields */
emilmont 78:ed8466a608b4 2661 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
emilmont 78:ed8466a608b4 2662 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
emilmont 78:ed8466a608b4 2663 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
emilmont 78:ed8466a608b4 2664 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
emilmont 78:ed8466a608b4 2665 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
emilmont 78:ed8466a608b4 2666 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
emilmont 78:ed8466a608b4 2667 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
emilmont 78:ed8466a608b4 2668 /* SDID Bit Fields */
emilmont 78:ed8466a608b4 2669 #define SIM_SDID_PINID_MASK 0xFu
emilmont 78:ed8466a608b4 2670 #define SIM_SDID_PINID_SHIFT 0
emilmont 78:ed8466a608b4 2671 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
emilmont 78:ed8466a608b4 2672 #define SIM_SDID_DIEID_MASK 0xF80u
emilmont 78:ed8466a608b4 2673 #define SIM_SDID_DIEID_SHIFT 7
emilmont 78:ed8466a608b4 2674 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
emilmont 78:ed8466a608b4 2675 #define SIM_SDID_REVID_MASK 0xF000u
emilmont 78:ed8466a608b4 2676 #define SIM_SDID_REVID_SHIFT 12
emilmont 78:ed8466a608b4 2677 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
emilmont 78:ed8466a608b4 2678 #define SIM_SDID_SRAMSIZE_MASK 0xF0000u
emilmont 78:ed8466a608b4 2679 #define SIM_SDID_SRAMSIZE_SHIFT 16
emilmont 78:ed8466a608b4 2680 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
emilmont 78:ed8466a608b4 2681 #define SIM_SDID_SERIESID_MASK 0xF00000u
emilmont 78:ed8466a608b4 2682 #define SIM_SDID_SERIESID_SHIFT 20
emilmont 78:ed8466a608b4 2683 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
emilmont 78:ed8466a608b4 2684 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
emilmont 78:ed8466a608b4 2685 #define SIM_SDID_SUBFAMID_SHIFT 24
emilmont 78:ed8466a608b4 2686 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
emilmont 78:ed8466a608b4 2687 #define SIM_SDID_FAMID_MASK 0xF0000000u
emilmont 78:ed8466a608b4 2688 #define SIM_SDID_FAMID_SHIFT 28
emilmont 78:ed8466a608b4 2689 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
emilmont 78:ed8466a608b4 2690 /* SCGC4 Bit Fields */
emilmont 78:ed8466a608b4 2691 #define SIM_SCGC4_I2C0_MASK 0x40u
emilmont 78:ed8466a608b4 2692 #define SIM_SCGC4_I2C0_SHIFT 6
emilmont 78:ed8466a608b4 2693 #define SIM_SCGC4_UART0_MASK 0x400u
emilmont 78:ed8466a608b4 2694 #define SIM_SCGC4_UART0_SHIFT 10
emilmont 78:ed8466a608b4 2695 #define SIM_SCGC4_CMP_MASK 0x80000u
emilmont 78:ed8466a608b4 2696 #define SIM_SCGC4_CMP_SHIFT 19
emilmont 78:ed8466a608b4 2697 #define SIM_SCGC4_SPI0_MASK 0x400000u
emilmont 78:ed8466a608b4 2698 #define SIM_SCGC4_SPI0_SHIFT 22
emilmont 78:ed8466a608b4 2699 /* SCGC5 Bit Fields */
emilmont 78:ed8466a608b4 2700 #define SIM_SCGC5_LPTMR_MASK 0x1u
emilmont 78:ed8466a608b4 2701 #define SIM_SCGC5_LPTMR_SHIFT 0
emilmont 78:ed8466a608b4 2702 #define SIM_SCGC5_TSI_MASK 0x20u
emilmont 78:ed8466a608b4 2703 #define SIM_SCGC5_TSI_SHIFT 5
emilmont 78:ed8466a608b4 2704 #define SIM_SCGC5_PORTA_MASK 0x200u
emilmont 78:ed8466a608b4 2705 #define SIM_SCGC5_PORTA_SHIFT 9
emilmont 78:ed8466a608b4 2706 #define SIM_SCGC5_PORTB_MASK 0x400u
emilmont 78:ed8466a608b4 2707 #define SIM_SCGC5_PORTB_SHIFT 10
emilmont 78:ed8466a608b4 2708 /* SCGC6 Bit Fields */
emilmont 78:ed8466a608b4 2709 #define SIM_SCGC6_FTF_MASK 0x1u
emilmont 78:ed8466a608b4 2710 #define SIM_SCGC6_FTF_SHIFT 0
emilmont 78:ed8466a608b4 2711 #define SIM_SCGC6_DMAMUX_MASK 0x2u
emilmont 78:ed8466a608b4 2712 #define SIM_SCGC6_DMAMUX_SHIFT 1
emilmont 78:ed8466a608b4 2713 #define SIM_SCGC6_PIT_MASK 0x800000u
emilmont 78:ed8466a608b4 2714 #define SIM_SCGC6_PIT_SHIFT 23
emilmont 78:ed8466a608b4 2715 #define SIM_SCGC6_TPM0_MASK 0x1000000u
emilmont 78:ed8466a608b4 2716 #define SIM_SCGC6_TPM0_SHIFT 24
emilmont 78:ed8466a608b4 2717 #define SIM_SCGC6_TPM1_MASK 0x2000000u
emilmont 78:ed8466a608b4 2718 #define SIM_SCGC6_TPM1_SHIFT 25
emilmont 78:ed8466a608b4 2719 #define SIM_SCGC6_ADC0_MASK 0x8000000u
emilmont 78:ed8466a608b4 2720 #define SIM_SCGC6_ADC0_SHIFT 27
emilmont 78:ed8466a608b4 2721 #define SIM_SCGC6_RTC_MASK 0x20000000u
emilmont 78:ed8466a608b4 2722 #define SIM_SCGC6_RTC_SHIFT 29
emilmont 78:ed8466a608b4 2723 #define SIM_SCGC6_DAC0_MASK 0x80000000u
emilmont 78:ed8466a608b4 2724 #define SIM_SCGC6_DAC0_SHIFT 31
emilmont 78:ed8466a608b4 2725 /* SCGC7 Bit Fields */
emilmont 78:ed8466a608b4 2726 #define SIM_SCGC7_DMA_MASK 0x100u
emilmont 78:ed8466a608b4 2727 #define SIM_SCGC7_DMA_SHIFT 8
emilmont 78:ed8466a608b4 2728 /* CLKDIV1 Bit Fields */
emilmont 78:ed8466a608b4 2729 #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
emilmont 78:ed8466a608b4 2730 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
emilmont 78:ed8466a608b4 2731 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
emilmont 78:ed8466a608b4 2732 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
emilmont 78:ed8466a608b4 2733 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
emilmont 78:ed8466a608b4 2734 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
emilmont 78:ed8466a608b4 2735 /* FCFG1 Bit Fields */
emilmont 78:ed8466a608b4 2736 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
emilmont 78:ed8466a608b4 2737 #define SIM_FCFG1_FLASHDIS_SHIFT 0
emilmont 78:ed8466a608b4 2738 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
emilmont 78:ed8466a608b4 2739 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
emilmont 78:ed8466a608b4 2740 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
emilmont 78:ed8466a608b4 2741 #define SIM_FCFG1_PFSIZE_SHIFT 24
emilmont 78:ed8466a608b4 2742 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
emilmont 78:ed8466a608b4 2743 /* FCFG2 Bit Fields */
emilmont 78:ed8466a608b4 2744 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
emilmont 78:ed8466a608b4 2745 #define SIM_FCFG2_MAXADDR0_SHIFT 24
emilmont 78:ed8466a608b4 2746 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
emilmont 78:ed8466a608b4 2747 /* UIDMH Bit Fields */
emilmont 78:ed8466a608b4 2748 #define SIM_UIDMH_UID_MASK 0xFFFFu
emilmont 78:ed8466a608b4 2749 #define SIM_UIDMH_UID_SHIFT 0
emilmont 78:ed8466a608b4 2750 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
emilmont 78:ed8466a608b4 2751 /* UIDML Bit Fields */
emilmont 78:ed8466a608b4 2752 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 2753 #define SIM_UIDML_UID_SHIFT 0
emilmont 78:ed8466a608b4 2754 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
emilmont 78:ed8466a608b4 2755 /* UIDL Bit Fields */
emilmont 78:ed8466a608b4 2756 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
emilmont 78:ed8466a608b4 2757 #define SIM_UIDL_UID_SHIFT 0
emilmont 78:ed8466a608b4 2758 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
emilmont 78:ed8466a608b4 2759 /* COPC Bit Fields */
emilmont 78:ed8466a608b4 2760 #define SIM_COPC_COPW_MASK 0x1u
emilmont 78:ed8466a608b4 2761 #define SIM_COPC_COPW_SHIFT 0
emilmont 78:ed8466a608b4 2762 #define SIM_COPC_COPCLKS_MASK 0x2u
emilmont 78:ed8466a608b4 2763 #define SIM_COPC_COPCLKS_SHIFT 1
emilmont 78:ed8466a608b4 2764 #define SIM_COPC_COPT_MASK 0xCu
emilmont 78:ed8466a608b4 2765 #define SIM_COPC_COPT_SHIFT 2
emilmont 78:ed8466a608b4 2766 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
emilmont 78:ed8466a608b4 2767 /* SRVCOP Bit Fields */
emilmont 78:ed8466a608b4 2768 #define SIM_SRVCOP_SRVCOP_MASK 0xFFu
emilmont 78:ed8466a608b4 2769 #define SIM_SRVCOP_SRVCOP_SHIFT 0
emilmont 78:ed8466a608b4 2770 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
emilmont 78:ed8466a608b4 2771
emilmont 78:ed8466a608b4 2772 /**
emilmont 78:ed8466a608b4 2773 * @}
emilmont 78:ed8466a608b4 2774 */ /* end of group SIM_Register_Masks */
emilmont 78:ed8466a608b4 2775
emilmont 78:ed8466a608b4 2776
emilmont 78:ed8466a608b4 2777 /* SIM - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 2778 /** Peripheral SIM base address */
emilmont 78:ed8466a608b4 2779 #define SIM_BASE (0x40047000u)
emilmont 78:ed8466a608b4 2780 /** Peripheral SIM base pointer */
emilmont 78:ed8466a608b4 2781 #define SIM ((SIM_Type *)SIM_BASE)
emilmont 78:ed8466a608b4 2782 /** Array initializer of SIM peripheral base pointers */
emilmont 78:ed8466a608b4 2783 #define SIM_BASES { SIM }
emilmont 78:ed8466a608b4 2784
emilmont 78:ed8466a608b4 2785 /**
emilmont 78:ed8466a608b4 2786 * @}
emilmont 78:ed8466a608b4 2787 */ /* end of group SIM_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 2788
emilmont 78:ed8466a608b4 2789
emilmont 78:ed8466a608b4 2790 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 2791 -- SMC Peripheral Access Layer
emilmont 78:ed8466a608b4 2792 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 2793
emilmont 78:ed8466a608b4 2794 /**
emilmont 78:ed8466a608b4 2795 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
emilmont 78:ed8466a608b4 2796 * @{
emilmont 78:ed8466a608b4 2797 */
emilmont 78:ed8466a608b4 2798
emilmont 78:ed8466a608b4 2799 /** SMC - Register Layout Typedef */
emilmont 78:ed8466a608b4 2800 typedef struct {
emilmont 78:ed8466a608b4 2801 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
emilmont 78:ed8466a608b4 2802 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
emilmont 78:ed8466a608b4 2803 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
emilmont 78:ed8466a608b4 2804 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
emilmont 78:ed8466a608b4 2805 } SMC_Type;
emilmont 78:ed8466a608b4 2806
emilmont 78:ed8466a608b4 2807 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 2808 -- SMC Register Masks
emilmont 78:ed8466a608b4 2809 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 2810
emilmont 78:ed8466a608b4 2811 /**
emilmont 78:ed8466a608b4 2812 * @addtogroup SMC_Register_Masks SMC Register Masks
emilmont 78:ed8466a608b4 2813 * @{
emilmont 78:ed8466a608b4 2814 */
emilmont 78:ed8466a608b4 2815
emilmont 78:ed8466a608b4 2816 /* PMPROT Bit Fields */
emilmont 78:ed8466a608b4 2817 #define SMC_PMPROT_AVLLS_MASK 0x2u
emilmont 78:ed8466a608b4 2818 #define SMC_PMPROT_AVLLS_SHIFT 1
emilmont 78:ed8466a608b4 2819 #define SMC_PMPROT_ALLS_MASK 0x8u
emilmont 78:ed8466a608b4 2820 #define SMC_PMPROT_ALLS_SHIFT 3
emilmont 78:ed8466a608b4 2821 #define SMC_PMPROT_AVLP_MASK 0x20u
emilmont 78:ed8466a608b4 2822 #define SMC_PMPROT_AVLP_SHIFT 5
emilmont 78:ed8466a608b4 2823 /* PMCTRL Bit Fields */
emilmont 78:ed8466a608b4 2824 #define SMC_PMCTRL_STOPM_MASK 0x7u
emilmont 78:ed8466a608b4 2825 #define SMC_PMCTRL_STOPM_SHIFT 0
emilmont 78:ed8466a608b4 2826 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
emilmont 78:ed8466a608b4 2827 #define SMC_PMCTRL_STOPA_MASK 0x8u
emilmont 78:ed8466a608b4 2828 #define SMC_PMCTRL_STOPA_SHIFT 3
emilmont 78:ed8466a608b4 2829 #define SMC_PMCTRL_RUNM_MASK 0x60u
emilmont 78:ed8466a608b4 2830 #define SMC_PMCTRL_RUNM_SHIFT 5
emilmont 78:ed8466a608b4 2831 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
emilmont 78:ed8466a608b4 2832 /* STOPCTRL Bit Fields */
emilmont 78:ed8466a608b4 2833 #define SMC_STOPCTRL_VLLSM_MASK 0x7u
emilmont 78:ed8466a608b4 2834 #define SMC_STOPCTRL_VLLSM_SHIFT 0
emilmont 78:ed8466a608b4 2835 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
emilmont 78:ed8466a608b4 2836 #define SMC_STOPCTRL_PORPO_MASK 0x20u
emilmont 78:ed8466a608b4 2837 #define SMC_STOPCTRL_PORPO_SHIFT 5
emilmont 78:ed8466a608b4 2838 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
emilmont 78:ed8466a608b4 2839 #define SMC_STOPCTRL_PSTOPO_SHIFT 6
emilmont 78:ed8466a608b4 2840 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
emilmont 78:ed8466a608b4 2841 /* PMSTAT Bit Fields */
emilmont 78:ed8466a608b4 2842 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
emilmont 78:ed8466a608b4 2843 #define SMC_PMSTAT_PMSTAT_SHIFT 0
emilmont 78:ed8466a608b4 2844 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
emilmont 78:ed8466a608b4 2845
emilmont 78:ed8466a608b4 2846 /**
emilmont 78:ed8466a608b4 2847 * @}
emilmont 78:ed8466a608b4 2848 */ /* end of group SMC_Register_Masks */
emilmont 78:ed8466a608b4 2849
emilmont 78:ed8466a608b4 2850
emilmont 78:ed8466a608b4 2851 /* SMC - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 2852 /** Peripheral SMC base address */
emilmont 78:ed8466a608b4 2853 #define SMC_BASE (0x4007E000u)
emilmont 78:ed8466a608b4 2854 /** Peripheral SMC base pointer */
emilmont 78:ed8466a608b4 2855 #define SMC ((SMC_Type *)SMC_BASE)
emilmont 78:ed8466a608b4 2856 /** Array initializer of SMC peripheral base pointers */
emilmont 78:ed8466a608b4 2857 #define SMC_BASES { SMC }
emilmont 78:ed8466a608b4 2858
emilmont 78:ed8466a608b4 2859 /**
emilmont 78:ed8466a608b4 2860 * @}
emilmont 78:ed8466a608b4 2861 */ /* end of group SMC_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 2862
emilmont 78:ed8466a608b4 2863
emilmont 78:ed8466a608b4 2864 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 2865 -- SPI Peripheral Access Layer
emilmont 78:ed8466a608b4 2866 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 2867
emilmont 78:ed8466a608b4 2868 /**
emilmont 78:ed8466a608b4 2869 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
emilmont 78:ed8466a608b4 2870 * @{
emilmont 78:ed8466a608b4 2871 */
emilmont 78:ed8466a608b4 2872
emilmont 78:ed8466a608b4 2873 /** SPI - Register Layout Typedef */
emilmont 78:ed8466a608b4 2874 typedef struct {
emilmont 78:ed8466a608b4 2875 __IO uint8_t C1; /**< SPI control register 1, offset: 0x0 */
emilmont 78:ed8466a608b4 2876 __IO uint8_t C2; /**< SPI control register 2, offset: 0x1 */
emilmont 78:ed8466a608b4 2877 __IO uint8_t BR; /**< SPI baud rate register, offset: 0x2 */
emilmont 78:ed8466a608b4 2878 __I uint8_t S; /**< SPI status register, offset: 0x3 */
emilmont 78:ed8466a608b4 2879 uint8_t RESERVED_0[1];
emilmont 78:ed8466a608b4 2880 __IO uint8_t D; /**< SPI data register, offset: 0x5 */
emilmont 78:ed8466a608b4 2881 uint8_t RESERVED_1[1];
emilmont 78:ed8466a608b4 2882 __IO uint8_t M; /**< SPI match register, offset: 0x7 */
emilmont 78:ed8466a608b4 2883 } SPI_Type;
emilmont 78:ed8466a608b4 2884
emilmont 78:ed8466a608b4 2885 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 2886 -- SPI Register Masks
emilmont 78:ed8466a608b4 2887 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 2888
emilmont 78:ed8466a608b4 2889 /**
emilmont 78:ed8466a608b4 2890 * @addtogroup SPI_Register_Masks SPI Register Masks
emilmont 78:ed8466a608b4 2891 * @{
emilmont 78:ed8466a608b4 2892 */
emilmont 78:ed8466a608b4 2893
emilmont 78:ed8466a608b4 2894 /* C1 Bit Fields */
emilmont 78:ed8466a608b4 2895 #define SPI_C1_LSBFE_MASK 0x1u
emilmont 78:ed8466a608b4 2896 #define SPI_C1_LSBFE_SHIFT 0
emilmont 78:ed8466a608b4 2897 #define SPI_C1_SSOE_MASK 0x2u
emilmont 78:ed8466a608b4 2898 #define SPI_C1_SSOE_SHIFT 1
emilmont 78:ed8466a608b4 2899 #define SPI_C1_CPHA_MASK 0x4u
emilmont 78:ed8466a608b4 2900 #define SPI_C1_CPHA_SHIFT 2
emilmont 78:ed8466a608b4 2901 #define SPI_C1_CPOL_MASK 0x8u
emilmont 78:ed8466a608b4 2902 #define SPI_C1_CPOL_SHIFT 3
emilmont 78:ed8466a608b4 2903 #define SPI_C1_MSTR_MASK 0x10u
emilmont 78:ed8466a608b4 2904 #define SPI_C1_MSTR_SHIFT 4
emilmont 78:ed8466a608b4 2905 #define SPI_C1_SPTIE_MASK 0x20u
emilmont 78:ed8466a608b4 2906 #define SPI_C1_SPTIE_SHIFT 5
emilmont 78:ed8466a608b4 2907 #define SPI_C1_SPE_MASK 0x40u
emilmont 78:ed8466a608b4 2908 #define SPI_C1_SPE_SHIFT 6
emilmont 78:ed8466a608b4 2909 #define SPI_C1_SPIE_MASK 0x80u
emilmont 78:ed8466a608b4 2910 #define SPI_C1_SPIE_SHIFT 7
emilmont 78:ed8466a608b4 2911 /* C2 Bit Fields */
emilmont 78:ed8466a608b4 2912 #define SPI_C2_SPC0_MASK 0x1u
emilmont 78:ed8466a608b4 2913 #define SPI_C2_SPC0_SHIFT 0
emilmont 78:ed8466a608b4 2914 #define SPI_C2_SPISWAI_MASK 0x2u
emilmont 78:ed8466a608b4 2915 #define SPI_C2_SPISWAI_SHIFT 1
emilmont 78:ed8466a608b4 2916 #define SPI_C2_RXDMAE_MASK 0x4u
emilmont 78:ed8466a608b4 2917 #define SPI_C2_RXDMAE_SHIFT 2
emilmont 78:ed8466a608b4 2918 #define SPI_C2_BIDIROE_MASK 0x8u
emilmont 78:ed8466a608b4 2919 #define SPI_C2_BIDIROE_SHIFT 3
emilmont 78:ed8466a608b4 2920 #define SPI_C2_MODFEN_MASK 0x10u
emilmont 78:ed8466a608b4 2921 #define SPI_C2_MODFEN_SHIFT 4
emilmont 78:ed8466a608b4 2922 #define SPI_C2_TXDMAE_MASK 0x20u
emilmont 78:ed8466a608b4 2923 #define SPI_C2_TXDMAE_SHIFT 5
emilmont 78:ed8466a608b4 2924 #define SPI_C2_SPMIE_MASK 0x80u
emilmont 78:ed8466a608b4 2925 #define SPI_C2_SPMIE_SHIFT 7
emilmont 78:ed8466a608b4 2926 /* BR Bit Fields */
emilmont 78:ed8466a608b4 2927 #define SPI_BR_SPR_MASK 0xFu
emilmont 78:ed8466a608b4 2928 #define SPI_BR_SPR_SHIFT 0
emilmont 78:ed8466a608b4 2929 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
emilmont 78:ed8466a608b4 2930 #define SPI_BR_SPPR_MASK 0x70u
emilmont 78:ed8466a608b4 2931 #define SPI_BR_SPPR_SHIFT 4
emilmont 78:ed8466a608b4 2932 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
emilmont 78:ed8466a608b4 2933 /* S Bit Fields */
emilmont 78:ed8466a608b4 2934 #define SPI_S_MODF_MASK 0x10u
emilmont 78:ed8466a608b4 2935 #define SPI_S_MODF_SHIFT 4
emilmont 78:ed8466a608b4 2936 #define SPI_S_SPTEF_MASK 0x20u
emilmont 78:ed8466a608b4 2937 #define SPI_S_SPTEF_SHIFT 5
emilmont 78:ed8466a608b4 2938 #define SPI_S_SPMF_MASK 0x40u
emilmont 78:ed8466a608b4 2939 #define SPI_S_SPMF_SHIFT 6
emilmont 78:ed8466a608b4 2940 #define SPI_S_SPRF_MASK 0x80u
emilmont 78:ed8466a608b4 2941 #define SPI_S_SPRF_SHIFT 7
emilmont 78:ed8466a608b4 2942 /* D Bit Fields */
emilmont 78:ed8466a608b4 2943 #define SPI_D_Bits_MASK 0xFFu
emilmont 78:ed8466a608b4 2944 #define SPI_D_Bits_SHIFT 0
emilmont 78:ed8466a608b4 2945 #define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
emilmont 78:ed8466a608b4 2946 /* M Bit Fields */
emilmont 78:ed8466a608b4 2947 #define SPI_M_Bits_MASK 0xFFu
emilmont 78:ed8466a608b4 2948 #define SPI_M_Bits_SHIFT 0
emilmont 78:ed8466a608b4 2949 #define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
emilmont 78:ed8466a608b4 2950
emilmont 78:ed8466a608b4 2951 /**
emilmont 78:ed8466a608b4 2952 * @}
emilmont 78:ed8466a608b4 2953 */ /* end of group SPI_Register_Masks */
emilmont 78:ed8466a608b4 2954
emilmont 78:ed8466a608b4 2955
emilmont 78:ed8466a608b4 2956 /* SPI - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 2957 /** Peripheral SPI0 base address */
emilmont 78:ed8466a608b4 2958 #define SPI0_BASE (0x40076000u)
emilmont 78:ed8466a608b4 2959 /** Peripheral SPI0 base pointer */
emilmont 78:ed8466a608b4 2960 #define SPI0 ((SPI_Type *)SPI0_BASE)
emilmont 78:ed8466a608b4 2961 /** Array initializer of SPI peripheral base pointers */
emilmont 78:ed8466a608b4 2962 #define SPI_BASES { SPI0 }
emilmont 78:ed8466a608b4 2963
emilmont 78:ed8466a608b4 2964 /**
emilmont 78:ed8466a608b4 2965 * @}
emilmont 78:ed8466a608b4 2966 */ /* end of group SPI_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 2967
emilmont 78:ed8466a608b4 2968
emilmont 78:ed8466a608b4 2969 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 2970 -- TPM Peripheral Access Layer
emilmont 78:ed8466a608b4 2971 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 2972
emilmont 78:ed8466a608b4 2973 /**
emilmont 78:ed8466a608b4 2974 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
emilmont 78:ed8466a608b4 2975 * @{
emilmont 78:ed8466a608b4 2976 */
emilmont 78:ed8466a608b4 2977
emilmont 78:ed8466a608b4 2978 /** TPM - Register Layout Typedef */
emilmont 78:ed8466a608b4 2979 typedef struct {
emilmont 78:ed8466a608b4 2980 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
emilmont 78:ed8466a608b4 2981 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
emilmont 78:ed8466a608b4 2982 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
emilmont 78:ed8466a608b4 2983 struct { /* offset: 0xC, array step: 0x8 */
emilmont 78:ed8466a608b4 2984 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
emilmont 78:ed8466a608b4 2985 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
emilmont 78:ed8466a608b4 2986 } CONTROLS[6];
emilmont 78:ed8466a608b4 2987 uint8_t RESERVED_0[20];
emilmont 78:ed8466a608b4 2988 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
emilmont 78:ed8466a608b4 2989 uint8_t RESERVED_1[48];
emilmont 78:ed8466a608b4 2990 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
emilmont 78:ed8466a608b4 2991 } TPM_Type;
emilmont 78:ed8466a608b4 2992
emilmont 78:ed8466a608b4 2993 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 2994 -- TPM Register Masks
emilmont 78:ed8466a608b4 2995 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 2996
emilmont 78:ed8466a608b4 2997 /**
emilmont 78:ed8466a608b4 2998 * @addtogroup TPM_Register_Masks TPM Register Masks
emilmont 78:ed8466a608b4 2999 * @{
emilmont 78:ed8466a608b4 3000 */
emilmont 78:ed8466a608b4 3001
emilmont 78:ed8466a608b4 3002 /* SC Bit Fields */
emilmont 78:ed8466a608b4 3003 #define TPM_SC_PS_MASK 0x7u
emilmont 78:ed8466a608b4 3004 #define TPM_SC_PS_SHIFT 0
emilmont 78:ed8466a608b4 3005 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
emilmont 78:ed8466a608b4 3006 #define TPM_SC_CMOD_MASK 0x18u
emilmont 78:ed8466a608b4 3007 #define TPM_SC_CMOD_SHIFT 3
emilmont 78:ed8466a608b4 3008 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
emilmont 78:ed8466a608b4 3009 #define TPM_SC_CPWMS_MASK 0x20u
emilmont 78:ed8466a608b4 3010 #define TPM_SC_CPWMS_SHIFT 5
emilmont 78:ed8466a608b4 3011 #define TPM_SC_TOIE_MASK 0x40u
emilmont 78:ed8466a608b4 3012 #define TPM_SC_TOIE_SHIFT 6
emilmont 78:ed8466a608b4 3013 #define TPM_SC_TOF_MASK 0x80u
emilmont 78:ed8466a608b4 3014 #define TPM_SC_TOF_SHIFT 7
emilmont 78:ed8466a608b4 3015 #define TPM_SC_DMA_MASK 0x100u
emilmont 78:ed8466a608b4 3016 #define TPM_SC_DMA_SHIFT 8
emilmont 78:ed8466a608b4 3017 /* CNT Bit Fields */
emilmont 78:ed8466a608b4 3018 #define TPM_CNT_COUNT_MASK 0xFFFFu
emilmont 78:ed8466a608b4 3019 #define TPM_CNT_COUNT_SHIFT 0
emilmont 78:ed8466a608b4 3020 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
emilmont 78:ed8466a608b4 3021 /* MOD Bit Fields */
emilmont 78:ed8466a608b4 3022 #define TPM_MOD_MOD_MASK 0xFFFFu
emilmont 78:ed8466a608b4 3023 #define TPM_MOD_MOD_SHIFT 0
emilmont 78:ed8466a608b4 3024 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
emilmont 78:ed8466a608b4 3025 /* CnSC Bit Fields */
emilmont 78:ed8466a608b4 3026 #define TPM_CnSC_DMA_MASK 0x1u
emilmont 78:ed8466a608b4 3027 #define TPM_CnSC_DMA_SHIFT 0
emilmont 78:ed8466a608b4 3028 #define TPM_CnSC_ELSA_MASK 0x4u
emilmont 78:ed8466a608b4 3029 #define TPM_CnSC_ELSA_SHIFT 2
emilmont 78:ed8466a608b4 3030 #define TPM_CnSC_ELSB_MASK 0x8u
emilmont 78:ed8466a608b4 3031 #define TPM_CnSC_ELSB_SHIFT 3
emilmont 78:ed8466a608b4 3032 #define TPM_CnSC_MSA_MASK 0x10u
emilmont 78:ed8466a608b4 3033 #define TPM_CnSC_MSA_SHIFT 4
emilmont 78:ed8466a608b4 3034 #define TPM_CnSC_MSB_MASK 0x20u
emilmont 78:ed8466a608b4 3035 #define TPM_CnSC_MSB_SHIFT 5
emilmont 78:ed8466a608b4 3036 #define TPM_CnSC_CHIE_MASK 0x40u
emilmont 78:ed8466a608b4 3037 #define TPM_CnSC_CHIE_SHIFT 6
emilmont 78:ed8466a608b4 3038 #define TPM_CnSC_CHF_MASK 0x80u
emilmont 78:ed8466a608b4 3039 #define TPM_CnSC_CHF_SHIFT 7
emilmont 78:ed8466a608b4 3040 /* CnV Bit Fields */
emilmont 78:ed8466a608b4 3041 #define TPM_CnV_VAL_MASK 0xFFFFu
emilmont 78:ed8466a608b4 3042 #define TPM_CnV_VAL_SHIFT 0
emilmont 78:ed8466a608b4 3043 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
emilmont 78:ed8466a608b4 3044 /* STATUS Bit Fields */
emilmont 78:ed8466a608b4 3045 #define TPM_STATUS_CH0F_MASK 0x1u
emilmont 78:ed8466a608b4 3046 #define TPM_STATUS_CH0F_SHIFT 0
emilmont 78:ed8466a608b4 3047 #define TPM_STATUS_CH1F_MASK 0x2u
emilmont 78:ed8466a608b4 3048 #define TPM_STATUS_CH1F_SHIFT 1
emilmont 78:ed8466a608b4 3049 #define TPM_STATUS_CH2F_MASK 0x4u
emilmont 78:ed8466a608b4 3050 #define TPM_STATUS_CH2F_SHIFT 2
emilmont 78:ed8466a608b4 3051 #define TPM_STATUS_CH3F_MASK 0x8u
emilmont 78:ed8466a608b4 3052 #define TPM_STATUS_CH3F_SHIFT 3
emilmont 78:ed8466a608b4 3053 #define TPM_STATUS_CH4F_MASK 0x10u
emilmont 78:ed8466a608b4 3054 #define TPM_STATUS_CH4F_SHIFT 4
emilmont 78:ed8466a608b4 3055 #define TPM_STATUS_CH5F_MASK 0x20u
emilmont 78:ed8466a608b4 3056 #define TPM_STATUS_CH5F_SHIFT 5
emilmont 78:ed8466a608b4 3057 #define TPM_STATUS_TOF_MASK 0x100u
emilmont 78:ed8466a608b4 3058 #define TPM_STATUS_TOF_SHIFT 8
emilmont 78:ed8466a608b4 3059 /* CONF Bit Fields */
emilmont 78:ed8466a608b4 3060 #define TPM_CONF_DOZEEN_MASK 0x20u
emilmont 78:ed8466a608b4 3061 #define TPM_CONF_DOZEEN_SHIFT 5
emilmont 78:ed8466a608b4 3062 #define TPM_CONF_DBGMODE_MASK 0xC0u
emilmont 78:ed8466a608b4 3063 #define TPM_CONF_DBGMODE_SHIFT 6
emilmont 78:ed8466a608b4 3064 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
emilmont 78:ed8466a608b4 3065 #define TPM_CONF_GTBEEN_MASK 0x200u
emilmont 78:ed8466a608b4 3066 #define TPM_CONF_GTBEEN_SHIFT 9
emilmont 78:ed8466a608b4 3067 #define TPM_CONF_CSOT_MASK 0x10000u
emilmont 78:ed8466a608b4 3068 #define TPM_CONF_CSOT_SHIFT 16
emilmont 78:ed8466a608b4 3069 #define TPM_CONF_CSOO_MASK 0x20000u
emilmont 78:ed8466a608b4 3070 #define TPM_CONF_CSOO_SHIFT 17
emilmont 78:ed8466a608b4 3071 #define TPM_CONF_CROT_MASK 0x40000u
emilmont 78:ed8466a608b4 3072 #define TPM_CONF_CROT_SHIFT 18
emilmont 78:ed8466a608b4 3073 #define TPM_CONF_TRGSEL_MASK 0xF000000u
emilmont 78:ed8466a608b4 3074 #define TPM_CONF_TRGSEL_SHIFT 24
emilmont 78:ed8466a608b4 3075 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
emilmont 78:ed8466a608b4 3076
emilmont 78:ed8466a608b4 3077 /**
emilmont 78:ed8466a608b4 3078 * @}
emilmont 78:ed8466a608b4 3079 */ /* end of group TPM_Register_Masks */
emilmont 78:ed8466a608b4 3080
emilmont 78:ed8466a608b4 3081
emilmont 78:ed8466a608b4 3082 /* TPM - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 3083 /** Peripheral TPM0 base address */
emilmont 78:ed8466a608b4 3084 #define TPM0_BASE (0x40038000u)
emilmont 78:ed8466a608b4 3085 /** Peripheral TPM0 base pointer */
emilmont 78:ed8466a608b4 3086 #define TPM0 ((TPM_Type *)TPM0_BASE)
emilmont 78:ed8466a608b4 3087 /** Peripheral TPM1 base address */
emilmont 78:ed8466a608b4 3088 #define TPM1_BASE (0x40039000u)
emilmont 78:ed8466a608b4 3089 /** Peripheral TPM1 base pointer */
emilmont 78:ed8466a608b4 3090 #define TPM1 ((TPM_Type *)TPM1_BASE)
emilmont 78:ed8466a608b4 3091 /** Array initializer of TPM peripheral base pointers */
emilmont 78:ed8466a608b4 3092 #define TPM_BASES { TPM0, TPM1 }
emilmont 78:ed8466a608b4 3093
emilmont 78:ed8466a608b4 3094 /**
emilmont 78:ed8466a608b4 3095 * @}
emilmont 78:ed8466a608b4 3096 */ /* end of group TPM_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 3097
emilmont 78:ed8466a608b4 3098
emilmont 78:ed8466a608b4 3099 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 3100 -- TSI Peripheral Access Layer
emilmont 78:ed8466a608b4 3101 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 3102
emilmont 78:ed8466a608b4 3103 /**
emilmont 78:ed8466a608b4 3104 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
emilmont 78:ed8466a608b4 3105 * @{
emilmont 78:ed8466a608b4 3106 */
emilmont 78:ed8466a608b4 3107
emilmont 78:ed8466a608b4 3108 /** TSI - Register Layout Typedef */
emilmont 78:ed8466a608b4 3109 typedef struct {
emilmont 78:ed8466a608b4 3110 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
emilmont 78:ed8466a608b4 3111 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
emilmont 78:ed8466a608b4 3112 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
emilmont 78:ed8466a608b4 3113 } TSI_Type;
emilmont 78:ed8466a608b4 3114
emilmont 78:ed8466a608b4 3115 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 3116 -- TSI Register Masks
emilmont 78:ed8466a608b4 3117 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 3118
emilmont 78:ed8466a608b4 3119 /**
emilmont 78:ed8466a608b4 3120 * @addtogroup TSI_Register_Masks TSI Register Masks
emilmont 78:ed8466a608b4 3121 * @{
emilmont 78:ed8466a608b4 3122 */
emilmont 78:ed8466a608b4 3123
emilmont 78:ed8466a608b4 3124 /* GENCS Bit Fields */
emilmont 78:ed8466a608b4 3125 #define TSI_GENCS_CURSW_MASK 0x2u
emilmont 78:ed8466a608b4 3126 #define TSI_GENCS_CURSW_SHIFT 1
emilmont 78:ed8466a608b4 3127 #define TSI_GENCS_EOSF_MASK 0x4u
emilmont 78:ed8466a608b4 3128 #define TSI_GENCS_EOSF_SHIFT 2
emilmont 78:ed8466a608b4 3129 #define TSI_GENCS_SCNIP_MASK 0x8u
emilmont 78:ed8466a608b4 3130 #define TSI_GENCS_SCNIP_SHIFT 3
emilmont 78:ed8466a608b4 3131 #define TSI_GENCS_STM_MASK 0x10u
emilmont 78:ed8466a608b4 3132 #define TSI_GENCS_STM_SHIFT 4
emilmont 78:ed8466a608b4 3133 #define TSI_GENCS_STPE_MASK 0x20u
emilmont 78:ed8466a608b4 3134 #define TSI_GENCS_STPE_SHIFT 5
emilmont 78:ed8466a608b4 3135 #define TSI_GENCS_TSIIEN_MASK 0x40u
emilmont 78:ed8466a608b4 3136 #define TSI_GENCS_TSIIEN_SHIFT 6
emilmont 78:ed8466a608b4 3137 #define TSI_GENCS_TSIEN_MASK 0x80u
emilmont 78:ed8466a608b4 3138 #define TSI_GENCS_TSIEN_SHIFT 7
emilmont 78:ed8466a608b4 3139 #define TSI_GENCS_NSCN_MASK 0x1F00u
emilmont 78:ed8466a608b4 3140 #define TSI_GENCS_NSCN_SHIFT 8
emilmont 78:ed8466a608b4 3141 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
emilmont 78:ed8466a608b4 3142 #define TSI_GENCS_PS_MASK 0xE000u
emilmont 78:ed8466a608b4 3143 #define TSI_GENCS_PS_SHIFT 13
emilmont 78:ed8466a608b4 3144 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
emilmont 78:ed8466a608b4 3145 #define TSI_GENCS_EXTCHRG_MASK 0x70000u
emilmont 78:ed8466a608b4 3146 #define TSI_GENCS_EXTCHRG_SHIFT 16
emilmont 78:ed8466a608b4 3147 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
emilmont 78:ed8466a608b4 3148 #define TSI_GENCS_DVOLT_MASK 0x180000u
emilmont 78:ed8466a608b4 3149 #define TSI_GENCS_DVOLT_SHIFT 19
emilmont 78:ed8466a608b4 3150 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
emilmont 78:ed8466a608b4 3151 #define TSI_GENCS_REFCHRG_MASK 0xE00000u
emilmont 78:ed8466a608b4 3152 #define TSI_GENCS_REFCHRG_SHIFT 21
emilmont 78:ed8466a608b4 3153 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
emilmont 78:ed8466a608b4 3154 #define TSI_GENCS_MODE_MASK 0xF000000u
emilmont 78:ed8466a608b4 3155 #define TSI_GENCS_MODE_SHIFT 24
emilmont 78:ed8466a608b4 3156 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
emilmont 78:ed8466a608b4 3157 #define TSI_GENCS_ESOR_MASK 0x10000000u
emilmont 78:ed8466a608b4 3158 #define TSI_GENCS_ESOR_SHIFT 28
emilmont 78:ed8466a608b4 3159 #define TSI_GENCS_OUTRGF_MASK 0x80000000u
emilmont 78:ed8466a608b4 3160 #define TSI_GENCS_OUTRGF_SHIFT 31
emilmont 78:ed8466a608b4 3161 /* DATA Bit Fields */
emilmont 78:ed8466a608b4 3162 #define TSI_DATA_TSICNT_MASK 0xFFFFu
emilmont 78:ed8466a608b4 3163 #define TSI_DATA_TSICNT_SHIFT 0
emilmont 78:ed8466a608b4 3164 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
emilmont 78:ed8466a608b4 3165 #define TSI_DATA_SWTS_MASK 0x400000u
emilmont 78:ed8466a608b4 3166 #define TSI_DATA_SWTS_SHIFT 22
emilmont 78:ed8466a608b4 3167 #define TSI_DATA_DMAEN_MASK 0x800000u
emilmont 78:ed8466a608b4 3168 #define TSI_DATA_DMAEN_SHIFT 23
emilmont 78:ed8466a608b4 3169 #define TSI_DATA_TSICH_MASK 0xF0000000u
emilmont 78:ed8466a608b4 3170 #define TSI_DATA_TSICH_SHIFT 28
emilmont 78:ed8466a608b4 3171 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
emilmont 78:ed8466a608b4 3172 /* TSHD Bit Fields */
emilmont 78:ed8466a608b4 3173 #define TSI_TSHD_THRESL_MASK 0xFFFFu
emilmont 78:ed8466a608b4 3174 #define TSI_TSHD_THRESL_SHIFT 0
emilmont 78:ed8466a608b4 3175 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
emilmont 78:ed8466a608b4 3176 #define TSI_TSHD_THRESH_MASK 0xFFFF0000u
emilmont 78:ed8466a608b4 3177 #define TSI_TSHD_THRESH_SHIFT 16
emilmont 78:ed8466a608b4 3178 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
emilmont 78:ed8466a608b4 3179
emilmont 78:ed8466a608b4 3180 /**
emilmont 78:ed8466a608b4 3181 * @}
emilmont 78:ed8466a608b4 3182 */ /* end of group TSI_Register_Masks */
emilmont 78:ed8466a608b4 3183
emilmont 78:ed8466a608b4 3184
emilmont 78:ed8466a608b4 3185 /* TSI - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 3186 /** Peripheral TSI0 base address */
emilmont 78:ed8466a608b4 3187 #define TSI0_BASE (0x40045000u)
emilmont 78:ed8466a608b4 3188 /** Peripheral TSI0 base pointer */
emilmont 78:ed8466a608b4 3189 #define TSI0 ((TSI_Type *)TSI0_BASE)
emilmont 78:ed8466a608b4 3190 /** Array initializer of TSI peripheral base pointers */
emilmont 78:ed8466a608b4 3191 #define TSI_BASES { TSI0 }
emilmont 78:ed8466a608b4 3192
emilmont 78:ed8466a608b4 3193 /**
emilmont 78:ed8466a608b4 3194 * @}
emilmont 78:ed8466a608b4 3195 */ /* end of group TSI_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 3196
emilmont 78:ed8466a608b4 3197
emilmont 78:ed8466a608b4 3198 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 3199 -- UART0 Peripheral Access Layer
emilmont 78:ed8466a608b4 3200 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 3201
emilmont 78:ed8466a608b4 3202 /**
emilmont 78:ed8466a608b4 3203 * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
emilmont 78:ed8466a608b4 3204 * @{
emilmont 78:ed8466a608b4 3205 */
emilmont 78:ed8466a608b4 3206
emilmont 78:ed8466a608b4 3207 /** UART0 - Register Layout Typedef */
emilmont 78:ed8466a608b4 3208 typedef struct {
emilmont 78:ed8466a608b4 3209 __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
emilmont 78:ed8466a608b4 3210 __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
emilmont 78:ed8466a608b4 3211 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
emilmont 78:ed8466a608b4 3212 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
emilmont 78:ed8466a608b4 3213 __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
emilmont 78:ed8466a608b4 3214 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
emilmont 78:ed8466a608b4 3215 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
emilmont 78:ed8466a608b4 3216 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
emilmont 78:ed8466a608b4 3217 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
emilmont 78:ed8466a608b4 3218 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
emilmont 78:ed8466a608b4 3219 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
emilmont 78:ed8466a608b4 3220 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
emilmont 78:ed8466a608b4 3221 } UART0_Type;
emilmont 78:ed8466a608b4 3222
emilmont 78:ed8466a608b4 3223 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 3224 -- UART0 Register Masks
emilmont 78:ed8466a608b4 3225 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 3226
emilmont 78:ed8466a608b4 3227 /**
emilmont 78:ed8466a608b4 3228 * @addtogroup UART0_Register_Masks UART0 Register Masks
emilmont 78:ed8466a608b4 3229 * @{
emilmont 78:ed8466a608b4 3230 */
emilmont 78:ed8466a608b4 3231
emilmont 78:ed8466a608b4 3232 /* BDH Bit Fields */
emilmont 78:ed8466a608b4 3233 #define UART0_BDH_SBR_MASK 0x1Fu
emilmont 78:ed8466a608b4 3234 #define UART0_BDH_SBR_SHIFT 0
emilmont 78:ed8466a608b4 3235 #define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK)
emilmont 78:ed8466a608b4 3236 #define UART0_BDH_SBNS_MASK 0x20u
emilmont 78:ed8466a608b4 3237 #define UART0_BDH_SBNS_SHIFT 5
emilmont 78:ed8466a608b4 3238 #define UART0_BDH_RXEDGIE_MASK 0x40u
emilmont 78:ed8466a608b4 3239 #define UART0_BDH_RXEDGIE_SHIFT 6
emilmont 78:ed8466a608b4 3240 #define UART0_BDH_LBKDIE_MASK 0x80u
emilmont 78:ed8466a608b4 3241 #define UART0_BDH_LBKDIE_SHIFT 7
emilmont 78:ed8466a608b4 3242 /* BDL Bit Fields */
emilmont 78:ed8466a608b4 3243 #define UART0_BDL_SBR_MASK 0xFFu
emilmont 78:ed8466a608b4 3244 #define UART0_BDL_SBR_SHIFT 0
emilmont 78:ed8466a608b4 3245 #define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK)
emilmont 78:ed8466a608b4 3246 /* C1 Bit Fields */
emilmont 78:ed8466a608b4 3247 #define UART0_C1_PT_MASK 0x1u
emilmont 78:ed8466a608b4 3248 #define UART0_C1_PT_SHIFT 0
emilmont 78:ed8466a608b4 3249 #define UART0_C1_PE_MASK 0x2u
emilmont 78:ed8466a608b4 3250 #define UART0_C1_PE_SHIFT 1
emilmont 78:ed8466a608b4 3251 #define UART0_C1_ILT_MASK 0x4u
emilmont 78:ed8466a608b4 3252 #define UART0_C1_ILT_SHIFT 2
emilmont 78:ed8466a608b4 3253 #define UART0_C1_WAKE_MASK 0x8u
emilmont 78:ed8466a608b4 3254 #define UART0_C1_WAKE_SHIFT 3
emilmont 78:ed8466a608b4 3255 #define UART0_C1_M_MASK 0x10u
emilmont 78:ed8466a608b4 3256 #define UART0_C1_M_SHIFT 4
emilmont 78:ed8466a608b4 3257 #define UART0_C1_RSRC_MASK 0x20u
emilmont 78:ed8466a608b4 3258 #define UART0_C1_RSRC_SHIFT 5
emilmont 78:ed8466a608b4 3259 #define UART0_C1_DOZEEN_MASK 0x40u
emilmont 78:ed8466a608b4 3260 #define UART0_C1_DOZEEN_SHIFT 6
emilmont 78:ed8466a608b4 3261 #define UART0_C1_LOOPS_MASK 0x80u
emilmont 78:ed8466a608b4 3262 #define UART0_C1_LOOPS_SHIFT 7
emilmont 78:ed8466a608b4 3263 /* C2 Bit Fields */
emilmont 78:ed8466a608b4 3264 #define UART0_C2_SBK_MASK 0x1u
emilmont 78:ed8466a608b4 3265 #define UART0_C2_SBK_SHIFT 0
emilmont 78:ed8466a608b4 3266 #define UART0_C2_RWU_MASK 0x2u
emilmont 78:ed8466a608b4 3267 #define UART0_C2_RWU_SHIFT 1
emilmont 78:ed8466a608b4 3268 #define UART0_C2_RE_MASK 0x4u
emilmont 78:ed8466a608b4 3269 #define UART0_C2_RE_SHIFT 2
emilmont 78:ed8466a608b4 3270 #define UART0_C2_TE_MASK 0x8u
emilmont 78:ed8466a608b4 3271 #define UART0_C2_TE_SHIFT 3
emilmont 78:ed8466a608b4 3272 #define UART0_C2_ILIE_MASK 0x10u
emilmont 78:ed8466a608b4 3273 #define UART0_C2_ILIE_SHIFT 4
emilmont 78:ed8466a608b4 3274 #define UART0_C2_RIE_MASK 0x20u
emilmont 78:ed8466a608b4 3275 #define UART0_C2_RIE_SHIFT 5
emilmont 78:ed8466a608b4 3276 #define UART0_C2_TCIE_MASK 0x40u
emilmont 78:ed8466a608b4 3277 #define UART0_C2_TCIE_SHIFT 6
emilmont 78:ed8466a608b4 3278 #define UART0_C2_TIE_MASK 0x80u
emilmont 78:ed8466a608b4 3279 #define UART0_C2_TIE_SHIFT 7
emilmont 78:ed8466a608b4 3280 /* S1 Bit Fields */
emilmont 78:ed8466a608b4 3281 #define UART0_S1_PF_MASK 0x1u
emilmont 78:ed8466a608b4 3282 #define UART0_S1_PF_SHIFT 0
emilmont 78:ed8466a608b4 3283 #define UART0_S1_FE_MASK 0x2u
emilmont 78:ed8466a608b4 3284 #define UART0_S1_FE_SHIFT 1
emilmont 78:ed8466a608b4 3285 #define UART0_S1_NF_MASK 0x4u
emilmont 78:ed8466a608b4 3286 #define UART0_S1_NF_SHIFT 2
emilmont 78:ed8466a608b4 3287 #define UART0_S1_OR_MASK 0x8u
emilmont 78:ed8466a608b4 3288 #define UART0_S1_OR_SHIFT 3
emilmont 78:ed8466a608b4 3289 #define UART0_S1_IDLE_MASK 0x10u
emilmont 78:ed8466a608b4 3290 #define UART0_S1_IDLE_SHIFT 4
emilmont 78:ed8466a608b4 3291 #define UART0_S1_RDRF_MASK 0x20u
emilmont 78:ed8466a608b4 3292 #define UART0_S1_RDRF_SHIFT 5
emilmont 78:ed8466a608b4 3293 #define UART0_S1_TC_MASK 0x40u
emilmont 78:ed8466a608b4 3294 #define UART0_S1_TC_SHIFT 6
emilmont 78:ed8466a608b4 3295 #define UART0_S1_TDRE_MASK 0x80u
emilmont 78:ed8466a608b4 3296 #define UART0_S1_TDRE_SHIFT 7
emilmont 78:ed8466a608b4 3297 /* S2 Bit Fields */
emilmont 78:ed8466a608b4 3298 #define UART0_S2_RAF_MASK 0x1u
emilmont 78:ed8466a608b4 3299 #define UART0_S2_RAF_SHIFT 0
emilmont 78:ed8466a608b4 3300 #define UART0_S2_LBKDE_MASK 0x2u
emilmont 78:ed8466a608b4 3301 #define UART0_S2_LBKDE_SHIFT 1
emilmont 78:ed8466a608b4 3302 #define UART0_S2_BRK13_MASK 0x4u
emilmont 78:ed8466a608b4 3303 #define UART0_S2_BRK13_SHIFT 2
emilmont 78:ed8466a608b4 3304 #define UART0_S2_RWUID_MASK 0x8u
emilmont 78:ed8466a608b4 3305 #define UART0_S2_RWUID_SHIFT 3
emilmont 78:ed8466a608b4 3306 #define UART0_S2_RXINV_MASK 0x10u
emilmont 78:ed8466a608b4 3307 #define UART0_S2_RXINV_SHIFT 4
emilmont 78:ed8466a608b4 3308 #define UART0_S2_MSBF_MASK 0x20u
emilmont 78:ed8466a608b4 3309 #define UART0_S2_MSBF_SHIFT 5
emilmont 78:ed8466a608b4 3310 #define UART0_S2_RXEDGIF_MASK 0x40u
emilmont 78:ed8466a608b4 3311 #define UART0_S2_RXEDGIF_SHIFT 6
emilmont 78:ed8466a608b4 3312 #define UART0_S2_LBKDIF_MASK 0x80u
emilmont 78:ed8466a608b4 3313 #define UART0_S2_LBKDIF_SHIFT 7
emilmont 78:ed8466a608b4 3314 /* C3 Bit Fields */
emilmont 78:ed8466a608b4 3315 #define UART0_C3_PEIE_MASK 0x1u
emilmont 78:ed8466a608b4 3316 #define UART0_C3_PEIE_SHIFT 0
emilmont 78:ed8466a608b4 3317 #define UART0_C3_FEIE_MASK 0x2u
emilmont 78:ed8466a608b4 3318 #define UART0_C3_FEIE_SHIFT 1
emilmont 78:ed8466a608b4 3319 #define UART0_C3_NEIE_MASK 0x4u
emilmont 78:ed8466a608b4 3320 #define UART0_C3_NEIE_SHIFT 2
emilmont 78:ed8466a608b4 3321 #define UART0_C3_ORIE_MASK 0x8u
emilmont 78:ed8466a608b4 3322 #define UART0_C3_ORIE_SHIFT 3
emilmont 78:ed8466a608b4 3323 #define UART0_C3_TXINV_MASK 0x10u
emilmont 78:ed8466a608b4 3324 #define UART0_C3_TXINV_SHIFT 4
emilmont 78:ed8466a608b4 3325 #define UART0_C3_TXDIR_MASK 0x20u
emilmont 78:ed8466a608b4 3326 #define UART0_C3_TXDIR_SHIFT 5
emilmont 78:ed8466a608b4 3327 #define UART0_C3_R9T8_MASK 0x40u
emilmont 78:ed8466a608b4 3328 #define UART0_C3_R9T8_SHIFT 6
emilmont 78:ed8466a608b4 3329 #define UART0_C3_R8T9_MASK 0x80u
emilmont 78:ed8466a608b4 3330 #define UART0_C3_R8T9_SHIFT 7
emilmont 78:ed8466a608b4 3331 /* D Bit Fields */
emilmont 78:ed8466a608b4 3332 #define UART0_D_R0T0_MASK 0x1u
emilmont 78:ed8466a608b4 3333 #define UART0_D_R0T0_SHIFT 0
emilmont 78:ed8466a608b4 3334 #define UART0_D_R1T1_MASK 0x2u
emilmont 78:ed8466a608b4 3335 #define UART0_D_R1T1_SHIFT 1
emilmont 78:ed8466a608b4 3336 #define UART0_D_R2T2_MASK 0x4u
emilmont 78:ed8466a608b4 3337 #define UART0_D_R2T2_SHIFT 2
emilmont 78:ed8466a608b4 3338 #define UART0_D_R3T3_MASK 0x8u
emilmont 78:ed8466a608b4 3339 #define UART0_D_R3T3_SHIFT 3
emilmont 78:ed8466a608b4 3340 #define UART0_D_R4T4_MASK 0x10u
emilmont 78:ed8466a608b4 3341 #define UART0_D_R4T4_SHIFT 4
emilmont 78:ed8466a608b4 3342 #define UART0_D_R5T5_MASK 0x20u
emilmont 78:ed8466a608b4 3343 #define UART0_D_R5T5_SHIFT 5
emilmont 78:ed8466a608b4 3344 #define UART0_D_R6T6_MASK 0x40u
emilmont 78:ed8466a608b4 3345 #define UART0_D_R6T6_SHIFT 6
emilmont 78:ed8466a608b4 3346 #define UART0_D_R7T7_MASK 0x80u
emilmont 78:ed8466a608b4 3347 #define UART0_D_R7T7_SHIFT 7
emilmont 78:ed8466a608b4 3348 /* MA1 Bit Fields */
emilmont 78:ed8466a608b4 3349 #define UART0_MA1_MA_MASK 0xFFu
emilmont 78:ed8466a608b4 3350 #define UART0_MA1_MA_SHIFT 0
emilmont 78:ed8466a608b4 3351 #define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK)
emilmont 78:ed8466a608b4 3352 /* MA2 Bit Fields */
emilmont 78:ed8466a608b4 3353 #define UART0_MA2_MA_MASK 0xFFu
emilmont 78:ed8466a608b4 3354 #define UART0_MA2_MA_SHIFT 0
emilmont 78:ed8466a608b4 3355 #define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK)
emilmont 78:ed8466a608b4 3356 /* C4 Bit Fields */
emilmont 78:ed8466a608b4 3357 #define UART0_C4_OSR_MASK 0x1Fu
emilmont 78:ed8466a608b4 3358 #define UART0_C4_OSR_SHIFT 0
emilmont 78:ed8466a608b4 3359 #define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK)
emilmont 78:ed8466a608b4 3360 #define UART0_C4_M10_MASK 0x20u
emilmont 78:ed8466a608b4 3361 #define UART0_C4_M10_SHIFT 5
emilmont 78:ed8466a608b4 3362 #define UART0_C4_MAEN2_MASK 0x40u
emilmont 78:ed8466a608b4 3363 #define UART0_C4_MAEN2_SHIFT 6
emilmont 78:ed8466a608b4 3364 #define UART0_C4_MAEN1_MASK 0x80u
emilmont 78:ed8466a608b4 3365 #define UART0_C4_MAEN1_SHIFT 7
emilmont 78:ed8466a608b4 3366 /* C5 Bit Fields */
emilmont 78:ed8466a608b4 3367 #define UART0_C5_RESYNCDIS_MASK 0x1u
emilmont 78:ed8466a608b4 3368 #define UART0_C5_RESYNCDIS_SHIFT 0
emilmont 78:ed8466a608b4 3369 #define UART0_C5_BOTHEDGE_MASK 0x2u
emilmont 78:ed8466a608b4 3370 #define UART0_C5_BOTHEDGE_SHIFT 1
emilmont 78:ed8466a608b4 3371 #define UART0_C5_RDMAE_MASK 0x20u
emilmont 78:ed8466a608b4 3372 #define UART0_C5_RDMAE_SHIFT 5
emilmont 78:ed8466a608b4 3373 #define UART0_C5_TDMAE_MASK 0x80u
emilmont 78:ed8466a608b4 3374 #define UART0_C5_TDMAE_SHIFT 7
emilmont 78:ed8466a608b4 3375
emilmont 78:ed8466a608b4 3376 /**
emilmont 78:ed8466a608b4 3377 * @}
emilmont 78:ed8466a608b4 3378 */ /* end of group UART0_Register_Masks */
emilmont 78:ed8466a608b4 3379
emilmont 78:ed8466a608b4 3380
emilmont 78:ed8466a608b4 3381 /* UART0 - Peripheral instance base addresses */
emilmont 78:ed8466a608b4 3382 /** Peripheral UART0 base address */
emilmont 78:ed8466a608b4 3383 #define UART0_BASE (0x4006A000u)
emilmont 78:ed8466a608b4 3384 /** Peripheral UART0 base pointer */
emilmont 78:ed8466a608b4 3385 #define UART0 ((UART0_Type *)UART0_BASE)
emilmont 78:ed8466a608b4 3386 /** Array initializer of UART0 peripheral base pointers */
emilmont 78:ed8466a608b4 3387 #define UART0_BASES { UART0 }
emilmont 78:ed8466a608b4 3388
emilmont 78:ed8466a608b4 3389 /**
emilmont 78:ed8466a608b4 3390 * @}
emilmont 78:ed8466a608b4 3391 */ /* end of group UART0_Peripheral_Access_Layer */
emilmont 78:ed8466a608b4 3392
emilmont 78:ed8466a608b4 3393
emilmont 78:ed8466a608b4 3394 /*
emilmont 78:ed8466a608b4 3395 ** End of section using anonymous unions
emilmont 78:ed8466a608b4 3396 */
emilmont 78:ed8466a608b4 3397
emilmont 78:ed8466a608b4 3398 #if defined(__ARMCC_VERSION)
emilmont 78:ed8466a608b4 3399 #pragma pop
emilmont 78:ed8466a608b4 3400 #elif defined(__CWCC__)
emilmont 78:ed8466a608b4 3401 #pragma pop
emilmont 78:ed8466a608b4 3402 #elif defined(__GNUC__)
emilmont 78:ed8466a608b4 3403 /* leave anonymous unions enabled */
emilmont 78:ed8466a608b4 3404 #elif defined(__IAR_SYSTEMS_ICC__)
emilmont 78:ed8466a608b4 3405 #pragma language=default
emilmont 78:ed8466a608b4 3406 #else
emilmont 78:ed8466a608b4 3407 #error Not supported compiler type
emilmont 78:ed8466a608b4 3408 #endif
emilmont 78:ed8466a608b4 3409
emilmont 78:ed8466a608b4 3410 /**
emilmont 78:ed8466a608b4 3411 * @}
emilmont 78:ed8466a608b4 3412 */ /* end of group Peripheral_access_layer */
emilmont 78:ed8466a608b4 3413
emilmont 78:ed8466a608b4 3414
emilmont 78:ed8466a608b4 3415 /* ----------------------------------------------------------------------------
emilmont 78:ed8466a608b4 3416 -- Backward Compatibility
emilmont 78:ed8466a608b4 3417 ---------------------------------------------------------------------------- */
emilmont 78:ed8466a608b4 3418
emilmont 78:ed8466a608b4 3419 /**
emilmont 78:ed8466a608b4 3420 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
emilmont 78:ed8466a608b4 3421 * @{
emilmont 78:ed8466a608b4 3422 */
emilmont 78:ed8466a608b4 3423
emilmont 78:ed8466a608b4 3424 #define DMA_REQC_ARR_DMAC_MASK This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3425 #define DMA_REQC_ARR_DMAC_SHIFT This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3426 #define DMA_REQC_ARR_DMAC(x) This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3427 #define DMA_REQC_ARR_CFSM_MASK This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3428 #define DMA_REQC_ARR_CFSM_SHIFT This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3429 #define DMA_REQC0 This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3430 #define DMA_REQC1 This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3431 #define DMA_REQC2 This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3432 #define DMA_REQC3 This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3433 #define MCG_C6_CME0_MASK MCG_C6_CME_MASK
emilmont 78:ed8466a608b4 3434 #define MCG_C6_CME0_SHIFT MCG_C6_CME_SHIFT
emilmont 78:ed8466a608b4 3435 #define MCM_MATCR_ATC0_MASK This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3436 #define MCM_MATCR_ATC0_SHIFT This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3437 #define MCM_MATCR_ATC0(x) This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3438 #define MCM_MATCR_RO0_MASK This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3439 #define MCM_MATCR_RO0_SHIFT This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3440 #define MCM_MATCR_ATC1_MASK This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3441 #define MCM_MATCR_ATC1_SHIFT This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3442 #define MCM_MATCR_ATC1(x) This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3443 #define MCM_MATCR_RO1_MASK This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3444 #define MCM_MATCR_RO1_SHIFT This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3445 #define MCM_MATCR_ATC2_MASK This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3446 #define MCM_MATCR_ATC2_SHIFT This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3447 #define MCM_MATCR_ATC2(x) This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3448 #define MCM_MATCR_RO2_MASK This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3449 #define MCM_MATCR_RO2_SHIFT This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3450 #define MCM_MATCR_ATC3_MASK This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3451 #define MCM_MATCR_ATC3_SHIFT This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3452 #define MCM_MATCR_ATC3(x) This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3453 #define MCM_MATCR_RO3_MASK This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3454 #define MCM_MATCR_RO3_SHIFT This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3455 #define SIM_FCFG2_MAXADDR_MASK SIM_FCFG2_MAXADDR0_MASK
emilmont 78:ed8466a608b4 3456 #define SIM_FCFG2_MAXADDR_SHIFT SIM_FCFG2_MAXADDR0_SHIFT
emilmont 78:ed8466a608b4 3457 #define SIM_FCFG2_MAXADDR SIM_FCFG2_MAXADDR0
emilmont 78:ed8466a608b4 3458 #define SPI_C2_SPLPIE_MASK This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3459 #define SPI_C2_SPLPIE_SHIFT This_symbol_has_been_deprecated
emilmont 78:ed8466a608b4 3460 #define UARTLP_Type UART0_Type
emilmont 78:ed8466a608b4 3461 #define UARTLP_BDH_REG UART0_BDH_REG
emilmont 78:ed8466a608b4 3462 #define UARTLP_BDL_REG UART0_BDL_REG
emilmont 78:ed8466a608b4 3463 #define UARTLP_C1_REG UART0_C1_REG
emilmont 78:ed8466a608b4 3464 #define UARTLP_C2_REG UART0_C2_REG
emilmont 78:ed8466a608b4 3465 #define UARTLP_S1_REG UART0_S1_REG
emilmont 78:ed8466a608b4 3466 #define UARTLP_S2_REG UART0_S2_REG
emilmont 78:ed8466a608b4 3467 #define UARTLP_C3_REG UART0_C3_REG
emilmont 78:ed8466a608b4 3468 #define UARTLP_D_REG UART0_D_REG
emilmont 78:ed8466a608b4 3469 #define UARTLP_MA1_REG UART0_MA1_REG
emilmont 78:ed8466a608b4 3470 #define UARTLP_MA2_REG UART0_MA2_REG
emilmont 78:ed8466a608b4 3471 #define UARTLP_C4_REG UART0_C4_REG
emilmont 78:ed8466a608b4 3472 #define UARTLP_C5_REG UART0_C5_REG
emilmont 78:ed8466a608b4 3473 #define UARTLP_BDH_SBR_MASK UART0_BDH_SBR_MASK
emilmont 78:ed8466a608b4 3474 #define UARTLP_BDH_SBR_SHIFT UART0_BDH_SBR_SHIFT
emilmont 78:ed8466a608b4 3475 #define UARTLP_BDH_SBR(x) UART0_BDH_SBR(x)
emilmont 78:ed8466a608b4 3476 #define UARTLP_BDH_SBNS_MASK UART0_BDH_SBNS_MASK
emilmont 78:ed8466a608b4 3477 #define UARTLP_BDH_SBNS_SHIFT UART0_BDH_SBNS_SHIFT
emilmont 78:ed8466a608b4 3478 #define UARTLP_BDH_RXEDGIE_MASK UART0_BDH_RXEDGIE_MASK
emilmont 78:ed8466a608b4 3479 #define UARTLP_BDH_RXEDGIE_SHIFT UART0_BDH_RXEDGIE_SHIFT
emilmont 78:ed8466a608b4 3480 #define UARTLP_BDH_LBKDIE_MASK UART0_BDH_LBKDIE_MASK
emilmont 78:ed8466a608b4 3481 #define UARTLP_BDH_LBKDIE_SHIFT UART0_BDH_LBKDIE_SHIFT
emilmont 78:ed8466a608b4 3482 #define UARTLP_BDL_SBR_MASK UART0_BDL_SBR_MASK
emilmont 78:ed8466a608b4 3483 #define UARTLP_BDL_SBR_SHIFT UART0_BDL_SBR_SHIFT
emilmont 78:ed8466a608b4 3484 #define UARTLP_BDL_SBR(x) UART0_BDL_SBR(x)
emilmont 78:ed8466a608b4 3485 #define UARTLP_C1_PT_MASK UART0_C1_PT_MASK
emilmont 78:ed8466a608b4 3486 #define UARTLP_C1_PT_SHIFT UART0_C1_PT_SHIFT
emilmont 78:ed8466a608b4 3487 #define UARTLP_C1_PE_MASK UART0_C1_PE_MASK
emilmont 78:ed8466a608b4 3488 #define UARTLP_C1_PE_SHIFT UART0_C1_PE_SHIFT
emilmont 78:ed8466a608b4 3489 #define UARTLP_C1_ILT_MASK UART0_C1_ILT_MASK
emilmont 78:ed8466a608b4 3490 #define UARTLP_C1_ILT_SHIFT UART0_C1_ILT_SHIFT
emilmont 78:ed8466a608b4 3491 #define UARTLP_C1_WAKE_MASK UART0_C1_WAKE_MASK
emilmont 78:ed8466a608b4 3492 #define UARTLP_C1_WAKE_SHIFT UART0_C1_WAKE_SHIFT
emilmont 78:ed8466a608b4 3493 #define UARTLP_C1_M_MASK UART0_C1_M_MASK
emilmont 78:ed8466a608b4 3494 #define UARTLP_C1_M_SHIFT UART0_C1_M_SHIFT
emilmont 78:ed8466a608b4 3495 #define UARTLP_C1_RSRC_MASK UART0_C1_RSRC_MASK
emilmont 78:ed8466a608b4 3496 #define UARTLP_C1_RSRC_SHIFT UART0_C1_RSRC_SHIFT
emilmont 78:ed8466a608b4 3497 #define UARTLP_C1_DOZEEN_MASK UART0_C1_DOZEEN_MASK
emilmont 78:ed8466a608b4 3498 #define UARTLP_C1_DOZEEN_SHIFT UART0_C1_DOZEEN_SHIFT
emilmont 78:ed8466a608b4 3499 #define UARTLP_C1_LOOPS_MASK UART0_C1_LOOPS_MASK
emilmont 78:ed8466a608b4 3500 #define UARTLP_C1_LOOPS_SHIFT UART0_C1_LOOPS_SHIFT
emilmont 78:ed8466a608b4 3501 #define UARTLP_C2_SBK_MASK UART0_C2_SBK_MASK
emilmont 78:ed8466a608b4 3502 #define UARTLP_C2_SBK_SHIFT UART0_C2_SBK_SHIFT
emilmont 78:ed8466a608b4 3503 #define UARTLP_C2_RWU_MASK UART0_C2_RWU_MASK
emilmont 78:ed8466a608b4 3504 #define UARTLP_C2_RWU_SHIFT UART0_C2_RWU_SHIFT
emilmont 78:ed8466a608b4 3505 #define UARTLP_C2_RE_MASK UART0_C2_RE_MASK
emilmont 78:ed8466a608b4 3506 #define UARTLP_C2_RE_SHIFT UART0_C2_RE_SHIFT
emilmont 78:ed8466a608b4 3507 #define UARTLP_C2_TE_MASK UART0_C2_TE_MASK
emilmont 78:ed8466a608b4 3508 #define UARTLP_C2_TE_SHIFT UART0_C2_TE_SHIFT
emilmont 78:ed8466a608b4 3509 #define UARTLP_C2_ILIE_MASK UART0_C2_ILIE_MASK
emilmont 78:ed8466a608b4 3510 #define UARTLP_C2_ILIE_SHIFT UART0_C2_ILIE_SHIFT
emilmont 78:ed8466a608b4 3511 #define UARTLP_C2_RIE_MASK UART0_C2_RIE_MASK
emilmont 78:ed8466a608b4 3512 #define UARTLP_C2_RIE_SHIFT UART0_C2_RIE_SHIFT
emilmont 78:ed8466a608b4 3513 #define UARTLP_C2_TCIE_MASK UART0_C2_TCIE_MASK
emilmont 78:ed8466a608b4 3514 #define UARTLP_C2_TCIE_SHIFT UART0_C2_TCIE_SHIFT
emilmont 78:ed8466a608b4 3515 #define UARTLP_C2_TIE_MASK UART0_C2_TIE_MASK
emilmont 78:ed8466a608b4 3516 #define UARTLP_C2_TIE_SHIFT UART0_C2_TIE_SHIFT
emilmont 78:ed8466a608b4 3517 #define UARTLP_S1_PF_MASK UART0_S1_PF_MASK
emilmont 78:ed8466a608b4 3518 #define UARTLP_S1_PF_SHIFT UART0_S1_PF_SHIFT
emilmont 78:ed8466a608b4 3519 #define UARTLP_S1_FE_MASK UART0_S1_FE_MASK
emilmont 78:ed8466a608b4 3520 #define UARTLP_S1_FE_SHIFT UART0_S1_FE_SHIFT
emilmont 78:ed8466a608b4 3521 #define UARTLP_S1_NF_MASK UART0_S1_NF_MASK
emilmont 78:ed8466a608b4 3522 #define UARTLP_S1_NF_SHIFT UART0_S1_NF_SHIFT
emilmont 78:ed8466a608b4 3523 #define UARTLP_S1_OR_MASK UART0_S1_OR_MASK
emilmont 78:ed8466a608b4 3524 #define UARTLP_S1_OR_SHIFT UART0_S1_OR_SHIFT
emilmont 78:ed8466a608b4 3525 #define UARTLP_S1_IDLE_MASK UART0_S1_IDLE_MASK
emilmont 78:ed8466a608b4 3526 #define UARTLP_S1_IDLE_SHIFT UART0_S1_IDLE_SHIFT
emilmont 78:ed8466a608b4 3527 #define UARTLP_S1_RDRF_MASK UART0_S1_RDRF_MASK
emilmont 78:ed8466a608b4 3528 #define UARTLP_S1_RDRF_SHIFT UART0_S1_RDRF_SHIFT
emilmont 78:ed8466a608b4 3529 #define UARTLP_S1_TC_MASK UART0_S1_TC_MASK
emilmont 78:ed8466a608b4 3530 #define UARTLP_S1_TC_SHIFT UART0_S1_TC_SHIFT
emilmont 78:ed8466a608b4 3531 #define UARTLP_S1_TDRE_MASK UART0_S1_TDRE_MASK
emilmont 78:ed8466a608b4 3532 #define UARTLP_S1_TDRE_SHIFT UART0_S1_TDRE_SHIFT
emilmont 78:ed8466a608b4 3533 #define UARTLP_S2_RAF_MASK UART0_S2_RAF_MASK
emilmont 78:ed8466a608b4 3534 #define UARTLP_S2_RAF_SHIFT UART0_S2_RAF_SHIFT
emilmont 78:ed8466a608b4 3535 #define UARTLP_S2_LBKDE_MASK UART0_S2_LBKDE_MASK
emilmont 78:ed8466a608b4 3536 #define UARTLP_S2_LBKDE_SHIFT UART0_S2_LBKDE_SHIFT
emilmont 78:ed8466a608b4 3537 #define UARTLP_S2_BRK13_MASK UART0_S2_BRK13_MASK
emilmont 78:ed8466a608b4 3538 #define UARTLP_S2_BRK13_SHIFT UART0_S2_BRK13_SHIFT
emilmont 78:ed8466a608b4 3539 #define UARTLP_S2_RWUID_MASK UART0_S2_RWUID_MASK
emilmont 78:ed8466a608b4 3540 #define UARTLP_S2_RWUID_SHIFT UART0_S2_RWUID_SHIFT
emilmont 78:ed8466a608b4 3541 #define UARTLP_S2_RXINV_MASK UART0_S2_RXINV_MASK
emilmont 78:ed8466a608b4 3542 #define UARTLP_S2_RXINV_SHIFT UART0_S2_RXINV_SHIFT
emilmont 78:ed8466a608b4 3543 #define UARTLP_S2_MSBF_MASK UART0_S2_MSBF_MASK
emilmont 78:ed8466a608b4 3544 #define UARTLP_S2_MSBF_SHIFT UART0_S2_MSBF_SHIFT
emilmont 78:ed8466a608b4 3545 #define UARTLP_S2_RXEDGIF_MASK UART0_S2_RXEDGIF_MASK
emilmont 78:ed8466a608b4 3546 #define UARTLP_S2_RXEDGIF_SHIFT UART0_S2_RXEDGIF_SHIFT
emilmont 78:ed8466a608b4 3547 #define UARTLP_S2_LBKDIF_MASK UART0_S2_LBKDIF_MASK
emilmont 78:ed8466a608b4 3548 #define UARTLP_S2_LBKDIF_SHIFT UART0_S2_LBKDIF_SHIFT
emilmont 78:ed8466a608b4 3549 #define UARTLP_C3_PEIE_MASK UART0_C3_PEIE_MASK
emilmont 78:ed8466a608b4 3550 #define UARTLP_C3_PEIE_SHIFT UART0_C3_PEIE_SHIFT
emilmont 78:ed8466a608b4 3551 #define UARTLP_C3_FEIE_MASK UART0_C3_FEIE_MASK
emilmont 78:ed8466a608b4 3552 #define UARTLP_C3_FEIE_SHIFT UART0_C3_FEIE_SHIFT
emilmont 78:ed8466a608b4 3553 #define UARTLP_C3_NEIE_MASK UART0_C3_NEIE_MASK
emilmont 78:ed8466a608b4 3554 #define UARTLP_C3_NEIE_SHIFT UART0_C3_NEIE_SHIFT
emilmont 78:ed8466a608b4 3555 #define UARTLP_C3_ORIE_MASK UART0_C3_ORIE_MASK
emilmont 78:ed8466a608b4 3556 #define UARTLP_C3_ORIE_SHIFT UART0_C3_ORIE_SHIFT
emilmont 78:ed8466a608b4 3557 #define UARTLP_C3_TXINV_MASK UART0_C3_TXINV_MASK
emilmont 78:ed8466a608b4 3558 #define UARTLP_C3_TXINV_SHIFT UART0_C3_TXINV_SHIFT
emilmont 78:ed8466a608b4 3559 #define UARTLP_C3_TXDIR_MASK UART0_C3_TXDIR_MASK
emilmont 78:ed8466a608b4 3560 #define UARTLP_C3_TXDIR_SHIFT UART0_C3_TXDIR_SHIFT
emilmont 78:ed8466a608b4 3561 #define UARTLP_C3_R9T8_MASK UART0_C3_R9T8_MASK
emilmont 78:ed8466a608b4 3562 #define UARTLP_C3_R9T8_SHIFT UART0_C3_R9T8_SHIFT
emilmont 78:ed8466a608b4 3563 #define UARTLP_C3_R8T9_MASK UART0_C3_R8T9_MASK
emilmont 78:ed8466a608b4 3564 #define UARTLP_C3_R8T9_SHIFT UART0_C3_R8T9_SHIFT
emilmont 78:ed8466a608b4 3565 #define UARTLP_D_R0T0_MASK UART0_D_R0T0_MASK
emilmont 78:ed8466a608b4 3566 #define UARTLP_D_R0T0_SHIFT UART0_D_R0T0_SHIFT
emilmont 78:ed8466a608b4 3567 #define UARTLP_D_R1T1_MASK UART0_D_R1T1_MASK
emilmont 78:ed8466a608b4 3568 #define UARTLP_D_R1T1_SHIFT UART0_D_R1T1_SHIFT
emilmont 78:ed8466a608b4 3569 #define UARTLP_D_R2T2_MASK UART0_D_R2T2_MASK
emilmont 78:ed8466a608b4 3570 #define UARTLP_D_R2T2_SHIFT UART0_D_R2T2_SHIFT
emilmont 78:ed8466a608b4 3571 #define UARTLP_D_R3T3_MASK UART0_D_R3T3_MASK
emilmont 78:ed8466a608b4 3572 #define UARTLP_D_R3T3_SHIFT UART0_D_R3T3_SHIFT
emilmont 78:ed8466a608b4 3573 #define UARTLP_D_R4T4_MASK UART0_D_R4T4_MASK
emilmont 78:ed8466a608b4 3574 #define UARTLP_D_R4T4_SHIFT UART0_D_R4T4_SHIFT
emilmont 78:ed8466a608b4 3575 #define UARTLP_D_R5T5_MASK UART0_D_R5T5_MASK
emilmont 78:ed8466a608b4 3576 #define UARTLP_D_R5T5_SHIFT UART0_D_R5T5_SHIFT
emilmont 78:ed8466a608b4 3577 #define UARTLP_D_R6T6_MASK UART0_D_R6T6_MASK
emilmont 78:ed8466a608b4 3578 #define UARTLP_D_R6T6_SHIFT UART0_D_R6T6_SHIFT
emilmont 78:ed8466a608b4 3579 #define UARTLP_D_R7T7_MASK UART0_D_R7T7_MASK
emilmont 78:ed8466a608b4 3580 #define UARTLP_D_R7T7_SHIFT UART0_D_R7T7_SHIFT
emilmont 78:ed8466a608b4 3581 #define UARTLP_MA1_MA_MASK UART0_MA1_MA_MASK
emilmont 78:ed8466a608b4 3582 #define UARTLP_MA1_MA_SHIFT UART0_MA1_MA_SHIFT
emilmont 78:ed8466a608b4 3583 #define UARTLP_MA1_MA(x) UART0_MA1_MA(x)
emilmont 78:ed8466a608b4 3584 #define UARTLP_MA2_MA_MASK UART0_MA2_MA_MASK
emilmont 78:ed8466a608b4 3585 #define UARTLP_MA2_MA_SHIFT UART0_MA2_MA_SHIFT
emilmont 78:ed8466a608b4 3586 #define UARTLP_MA2_MA(x) UART0_MA2_MA(x)
emilmont 78:ed8466a608b4 3587 #define UARTLP_C4_OSR_MASK UART0_C4_OSR_MASK
emilmont 78:ed8466a608b4 3588 #define UARTLP_C4_OSR_SHIFT UART0_C4_OSR_SHIFT
emilmont 78:ed8466a608b4 3589 #define UARTLP_C4_OSR(x) UART0_C4_OSR(x)
emilmont 78:ed8466a608b4 3590 #define UARTLP_C4_M10_MASK UART0_C4_M10_MASK
emilmont 78:ed8466a608b4 3591 #define UARTLP_C4_M10_SHIFT UART0_C4_M10_SHIFT
emilmont 78:ed8466a608b4 3592 #define UARTLP_C4_MAEN2_MASK UART0_C4_MAEN2_MASK
emilmont 78:ed8466a608b4 3593 #define UARTLP_C4_MAEN2_SHIFT UART0_C4_MAEN2_SHIFT
emilmont 78:ed8466a608b4 3594 #define UARTLP_C4_MAEN1_MASK UART0_C4_MAEN1_MASK
emilmont 78:ed8466a608b4 3595 #define UARTLP_C4_MAEN1_SHIFT UART0_C4_MAEN1_SHIFT
emilmont 78:ed8466a608b4 3596 #define UARTLP_C5_RESYNCDIS_MASK UART0_C5_RESYNCDIS_MASK
emilmont 78:ed8466a608b4 3597 #define UARTLP_C5_RESYNCDIS_SHIFT UART0_C5_RESYNCDIS_SHIFT
emilmont 78:ed8466a608b4 3598 #define UARTLP_C5_BOTHEDGE_MASK UART0_C5_BOTHEDGE_MASK
emilmont 78:ed8466a608b4 3599 #define UARTLP_C5_BOTHEDGE_SHIFT UART0_C5_BOTHEDGE_SHIFT
emilmont 78:ed8466a608b4 3600 #define UARTLP_C5_RDMAE_MASK UART0_C5_RDMAE_MASK
emilmont 78:ed8466a608b4 3601 #define UARTLP_C5_RDMAE_SHIFT UART0_C5_RDMAE_SHIFT
emilmont 78:ed8466a608b4 3602 #define UARTLP_C5_TDMAE_MASK UART0_C5_TDMAE_MASK
emilmont 78:ed8466a608b4 3603 #define UARTLP_C5_TDMAE_SHIFT UART0_C5_TDMAE_SHIFT
emilmont 78:ed8466a608b4 3604 #define UARTLP_BASES UARTLP_BASES
emilmont 78:ed8466a608b4 3605
emilmont 78:ed8466a608b4 3606 /**
emilmont 78:ed8466a608b4 3607 * @}
emilmont 78:ed8466a608b4 3608 */ /* end of group Backward_Compatibility_Symbols */
emilmont 78:ed8466a608b4 3609
emilmont 78:ed8466a608b4 3610
emilmont 78:ed8466a608b4 3611 #endif /* #if !defined(MKL05Z4_H_) */
emilmont 78:ed8466a608b4 3612
emilmont 78:ed8466a608b4 3613 /* MKL05Z4.h, eof. */