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TARGET_TB_SENSE_12/TOOLCHAIN_ARM_STD/em_msc.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_TB_SENSE_1/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_msc.h@160:5571c4ff569f
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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Anna Bridge |
142:4eea097334d6 | 1 | /***************************************************************************//** |
Anna Bridge |
142:4eea097334d6 | 2 | * @file em_msc.h |
Anna Bridge |
142:4eea097334d6 | 3 | * @brief Flash controller (MSC) peripheral API |
Anna Bridge |
160:5571c4ff569f | 4 | * @version 5.3.3 |
Anna Bridge |
142:4eea097334d6 | 5 | ******************************************************************************* |
Anna Bridge |
160:5571c4ff569f | 6 | * # License |
Anna Bridge |
142:4eea097334d6 | 7 | * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b> |
Anna Bridge |
142:4eea097334d6 | 8 | ******************************************************************************* |
Anna Bridge |
142:4eea097334d6 | 9 | * |
Anna Bridge |
142:4eea097334d6 | 10 | * Permission is granted to anyone to use this software for any purpose, |
Anna Bridge |
142:4eea097334d6 | 11 | * including commercial applications, and to alter it and redistribute it |
Anna Bridge |
142:4eea097334d6 | 12 | * freely, subject to the following restrictions: |
Anna Bridge |
142:4eea097334d6 | 13 | * |
Anna Bridge |
142:4eea097334d6 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
Anna Bridge |
142:4eea097334d6 | 15 | * claim that you wrote the original software. |
Anna Bridge |
142:4eea097334d6 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
Anna Bridge |
142:4eea097334d6 | 17 | * misrepresented as being the original software. |
Anna Bridge |
142:4eea097334d6 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
Anna Bridge |
142:4eea097334d6 | 19 | * |
Anna Bridge |
142:4eea097334d6 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no |
Anna Bridge |
142:4eea097334d6 | 21 | * obligation to support this Software. Silicon Labs is providing the |
Anna Bridge |
142:4eea097334d6 | 22 | * Software "AS IS", with no express or implied warranties of any kind, |
Anna Bridge |
142:4eea097334d6 | 23 | * including, but not limited to, any implied warranties of merchantability |
Anna Bridge |
142:4eea097334d6 | 24 | * or fitness for any particular purpose or warranties against infringement |
Anna Bridge |
142:4eea097334d6 | 25 | * of any proprietary rights of a third party. |
Anna Bridge |
142:4eea097334d6 | 26 | * |
Anna Bridge |
142:4eea097334d6 | 27 | * Silicon Labs will not be liable for any consequential, incidental, or |
Anna Bridge |
142:4eea097334d6 | 28 | * special damages, or any other relief, or for any claim by any third party, |
Anna Bridge |
142:4eea097334d6 | 29 | * arising from your use of this Software. |
Anna Bridge |
142:4eea097334d6 | 30 | * |
Anna Bridge |
142:4eea097334d6 | 31 | ******************************************************************************/ |
Anna Bridge |
142:4eea097334d6 | 32 | |
Anna Bridge |
142:4eea097334d6 | 33 | #ifndef EM_MSC_H |
Anna Bridge |
142:4eea097334d6 | 34 | #define EM_MSC_H |
Anna Bridge |
142:4eea097334d6 | 35 | |
Anna Bridge |
142:4eea097334d6 | 36 | #include "em_device.h" |
Anna Bridge |
142:4eea097334d6 | 37 | #if defined(MSC_COUNT) && (MSC_COUNT > 0) |
Anna Bridge |
142:4eea097334d6 | 38 | |
Anna Bridge |
142:4eea097334d6 | 39 | #include <stdint.h> |
Anna Bridge |
142:4eea097334d6 | 40 | #include <stdbool.h> |
Anna Bridge |
142:4eea097334d6 | 41 | #include "em_bus.h" |
Anna Bridge |
142:4eea097334d6 | 42 | #include "em_ramfunc.h" |
Anna Bridge |
142:4eea097334d6 | 43 | |
Anna Bridge |
142:4eea097334d6 | 44 | #ifdef __cplusplus |
Anna Bridge |
142:4eea097334d6 | 45 | extern "C" { |
Anna Bridge |
142:4eea097334d6 | 46 | #endif |
Anna Bridge |
142:4eea097334d6 | 47 | |
Anna Bridge |
142:4eea097334d6 | 48 | /***************************************************************************//** |
Anna Bridge |
142:4eea097334d6 | 49 | * @addtogroup emlib |
Anna Bridge |
142:4eea097334d6 | 50 | * @{ |
Anna Bridge |
142:4eea097334d6 | 51 | ******************************************************************************/ |
Anna Bridge |
142:4eea097334d6 | 52 | |
Anna Bridge |
142:4eea097334d6 | 53 | /***************************************************************************//** |
Anna Bridge |
142:4eea097334d6 | 54 | * @addtogroup MSC |
Anna Bridge |
142:4eea097334d6 | 55 | * @brief Memory System Controller API |
Anna Bridge |
142:4eea097334d6 | 56 | * @details |
Anna Bridge |
142:4eea097334d6 | 57 | * This module contain functions to control the MSC, primarily the Flash. |
Anna Bridge |
142:4eea097334d6 | 58 | * The user can perform Flash memory write and erase operations as well as |
Anna Bridge |
142:4eea097334d6 | 59 | * optimization of the CPU instruction fetch interface for the application. |
Anna Bridge |
142:4eea097334d6 | 60 | * Available instruction fetch features depends on the MCU or SoC family, but |
Anna Bridge |
142:4eea097334d6 | 61 | * features such as instruction pre-fetch, cache and configurable branch prediction |
Anna Bridge |
142:4eea097334d6 | 62 | * are typically available. |
Anna Bridge |
142:4eea097334d6 | 63 | * |
Anna Bridge |
142:4eea097334d6 | 64 | * @note Flash wait-state configuration is handled by the @ref CMU module. |
Anna Bridge |
142:4eea097334d6 | 65 | * When the core clock configuration is changed by a calls to functions such as |
Anna Bridge |
142:4eea097334d6 | 66 | * @ref CMU_ClockSelectSet() or @ref CMU_HFRCOBandSet(), then Flash wait-state |
Anna Bridge |
142:4eea097334d6 | 67 | * configuration is also updated. |
Anna Bridge |
142:4eea097334d6 | 68 | * |
Anna Bridge |
142:4eea097334d6 | 69 | * The MSC resets into a safe state. To initialize the instruction interface |
Anna Bridge |
142:4eea097334d6 | 70 | * to recommended settings: |
Anna Bridge |
142:4eea097334d6 | 71 | * @include em_msc_init_exec.c |
Anna Bridge |
142:4eea097334d6 | 72 | * |
Anna Bridge |
142:4eea097334d6 | 73 | * @note The optimal configuration is highly application dependent. Performance |
Anna Bridge |
142:4eea097334d6 | 74 | * benchmarking is supported by most families. See @ref MSC_StartCacheMeasurement() |
Anna Bridge |
142:4eea097334d6 | 75 | * and @ref MSC_GetCacheMeasurement() for more details. |
Anna Bridge |
142:4eea097334d6 | 76 | * |
Anna Bridge |
142:4eea097334d6 | 77 | * Support for Flash write and erase runs from RAM by default. This code may be |
Anna Bridge |
142:4eea097334d6 | 78 | * allocated to Flash by defining @ref EM_MSC_RUN_FROM_FLASH. |
Anna Bridge |
142:4eea097334d6 | 79 | * |
Anna Bridge |
142:4eea097334d6 | 80 | * @note |
Anna Bridge |
142:4eea097334d6 | 81 | * Flash erase may add ms of delay to interrupt latency if executing from Flash. |
Anna Bridge |
142:4eea097334d6 | 82 | * |
Anna Bridge |
142:4eea097334d6 | 83 | * Flash write and erase operations are supported by @ref MSC_WriteWord(), |
Anna Bridge |
142:4eea097334d6 | 84 | * @ref MSC_WriteWordFast(), @ref MSC_ErasePage() and @ref MSC_MassErase(). |
Anna Bridge |
142:4eea097334d6 | 85 | * Fast write is not supported for EFM32G and mass erase is supported for MCU and |
Anna Bridge |
142:4eea097334d6 | 86 | * SoC families with larger Flash sizes. |
Anna Bridge |
142:4eea097334d6 | 87 | * |
Anna Bridge |
142:4eea097334d6 | 88 | * @note |
Anna Bridge |
142:4eea097334d6 | 89 | * @ref MSC_Init() must be called prior to any Flash write or erase operation. |
Anna Bridge |
142:4eea097334d6 | 90 | * |
Anna Bridge |
142:4eea097334d6 | 91 | * The following steps are necessary to perform a page erase and write: |
Anna Bridge |
142:4eea097334d6 | 92 | * @include em_msc_erase_write.c |
Anna Bridge |
142:4eea097334d6 | 93 | * @{ |
Anna Bridge |
142:4eea097334d6 | 94 | ******************************************************************************/ |
Anna Bridge |
142:4eea097334d6 | 95 | |
Anna Bridge |
142:4eea097334d6 | 96 | /******************************************************************************* |
Anna Bridge |
142:4eea097334d6 | 97 | ************************* DEFINES ***************************************** |
Anna Bridge |
142:4eea097334d6 | 98 | ******************************************************************************/ |
Anna Bridge |
142:4eea097334d6 | 99 | |
Anna Bridge |
142:4eea097334d6 | 100 | /** |
Anna Bridge |
142:4eea097334d6 | 101 | * @brief |
Anna Bridge |
142:4eea097334d6 | 102 | * The timeout used while waiting for the flash to become ready after |
Anna Bridge |
142:4eea097334d6 | 103 | * a write. This number indicates the number of iterations to perform before |
Anna Bridge |
142:4eea097334d6 | 104 | * issuing a timeout. |
Anna Bridge |
142:4eea097334d6 | 105 | * |
Anna Bridge |
142:4eea097334d6 | 106 | * @note |
Anna Bridge |
142:4eea097334d6 | 107 | * This timeout is set very large (in the order of 100x longer than |
Anna Bridge |
142:4eea097334d6 | 108 | * necessary). This is to avoid any corner cases. |
Anna Bridge |
142:4eea097334d6 | 109 | */ |
Anna Bridge |
142:4eea097334d6 | 110 | #define MSC_PROGRAM_TIMEOUT 10000000ul |
Anna Bridge |
142:4eea097334d6 | 111 | |
Anna Bridge |
142:4eea097334d6 | 112 | /** |
Anna Bridge |
142:4eea097334d6 | 113 | * @brief |
Anna Bridge |
142:4eea097334d6 | 114 | * By compiling with the define EM_MSC_RUN_FROM_FLASH, the functions |
Anna Bridge |
142:4eea097334d6 | 115 | * performing erase or write operations will remain in and execute from Flash. |
Anna Bridge |
142:4eea097334d6 | 116 | * This is useful for targets that don't want to allocate RAM space to |
Anna Bridge |
142:4eea097334d6 | 117 | * hold the flash functions. Without this define, code for Flash operations |
Anna Bridge |
142:4eea097334d6 | 118 | * will be copied into RAM at startup. |
Anna Bridge |
142:4eea097334d6 | 119 | * |
Anna Bridge |
142:4eea097334d6 | 120 | * @note |
Anna Bridge |
142:4eea097334d6 | 121 | * This define is not present by default. The MSC controller API |
Anna Bridge |
142:4eea097334d6 | 122 | * will run from RAM by default. |
Anna Bridge |
142:4eea097334d6 | 123 | */ |
Anna Bridge |
142:4eea097334d6 | 124 | #if defined(DOXY_DOC_ONLY) |
Anna Bridge |
142:4eea097334d6 | 125 | #define EM_MSC_RUN_FROM_FLASH |
Anna Bridge |
142:4eea097334d6 | 126 | #endif |
Anna Bridge |
142:4eea097334d6 | 127 | |
Anna Bridge |
142:4eea097334d6 | 128 | /******************************************************************************* |
Anna Bridge |
142:4eea097334d6 | 129 | ************************* TYPEDEFS **************************************** |
Anna Bridge |
142:4eea097334d6 | 130 | ******************************************************************************/ |
Anna Bridge |
142:4eea097334d6 | 131 | |
Anna Bridge |
142:4eea097334d6 | 132 | /** Return codes for writing/erasing the flash */ |
Anna Bridge |
160:5571c4ff569f | 133 | typedef enum { |
Anna Bridge |
142:4eea097334d6 | 134 | mscReturnOk = 0, /**< Flash write/erase successful. */ |
Anna Bridge |
142:4eea097334d6 | 135 | mscReturnInvalidAddr = -1, /**< Invalid address. Write to an address that is not flash. */ |
Anna Bridge |
142:4eea097334d6 | 136 | mscReturnLocked = -2, /**< Flash address is locked. */ |
Anna Bridge |
142:4eea097334d6 | 137 | mscReturnTimeOut = -3, /**< Timeout while writing to flash. */ |
Anna Bridge |
142:4eea097334d6 | 138 | mscReturnUnaligned = -4 /**< Unaligned access to flash. */ |
Anna Bridge |
142:4eea097334d6 | 139 | } MSC_Status_TypeDef; |
Anna Bridge |
142:4eea097334d6 | 140 | |
Anna Bridge |
160:5571c4ff569f | 141 | #if defined(_MSC_READCTRL_BUSSTRATEGY_MASK) |
Anna Bridge |
142:4eea097334d6 | 142 | /** Strategy for prioritized bus access */ |
Anna Bridge |
160:5571c4ff569f | 143 | typedef enum { |
Anna Bridge |
142:4eea097334d6 | 144 | mscBusStrategyCPU = MSC_READCTRL_BUSSTRATEGY_CPU, /**< Prioritize CPU bus accesses */ |
Anna Bridge |
142:4eea097334d6 | 145 | mscBusStrategyDMA = MSC_READCTRL_BUSSTRATEGY_DMA, /**< Prioritize DMA bus accesses */ |
Anna Bridge |
142:4eea097334d6 | 146 | mscBusStrategyDMAEM1 = MSC_READCTRL_BUSSTRATEGY_DMAEM1, /**< Prioritize DMAEM1 for bus accesses */ |
Anna Bridge |
142:4eea097334d6 | 147 | mscBusStrategyNone = MSC_READCTRL_BUSSTRATEGY_NONE /**< No unit has bus priority */ |
Anna Bridge |
142:4eea097334d6 | 148 | } MSC_BusStrategy_Typedef; |
Anna Bridge |
142:4eea097334d6 | 149 | #endif |
Anna Bridge |
142:4eea097334d6 | 150 | |
Anna Bridge |
142:4eea097334d6 | 151 | /** Code execution configuration */ |
Anna Bridge |
160:5571c4ff569f | 152 | typedef struct { |
Anna Bridge |
142:4eea097334d6 | 153 | bool scbtEn; /**< Enable Suppressed Conditional Branch Target Prefetch */ |
Anna Bridge |
142:4eea097334d6 | 154 | bool prefetchEn; /**< Enable MSC prefetching */ |
Anna Bridge |
142:4eea097334d6 | 155 | bool ifcDis; /**< Disable instruction cache */ |
Anna Bridge |
142:4eea097334d6 | 156 | bool aiDis; /**< Disable automatic cache invalidation on write or erase */ |
Anna Bridge |
142:4eea097334d6 | 157 | bool iccDis; /**< Disable automatic caching of fetches in interrupt context */ |
Anna Bridge |
142:4eea097334d6 | 158 | bool useHprot; /**< Use ahb_hprot to determine if the instruction is cacheable or not */ |
Anna Bridge |
142:4eea097334d6 | 159 | } MSC_ExecConfig_TypeDef; |
Anna Bridge |
142:4eea097334d6 | 160 | |
Anna Bridge |
142:4eea097334d6 | 161 | /** Default MSC ExecConfig initialization */ |
Anna Bridge |
160:5571c4ff569f | 162 | #define MSC_EXECCONFIG_DEFAULT \ |
Anna Bridge |
160:5571c4ff569f | 163 | { \ |
Anna Bridge |
160:5571c4ff569f | 164 | false, \ |
Anna Bridge |
160:5571c4ff569f | 165 | true, \ |
Anna Bridge |
160:5571c4ff569f | 166 | false, \ |
Anna Bridge |
160:5571c4ff569f | 167 | false, \ |
Anna Bridge |
160:5571c4ff569f | 168 | false, \ |
Anna Bridge |
160:5571c4ff569f | 169 | false, \ |
Anna Bridge |
160:5571c4ff569f | 170 | } |
Anna Bridge |
142:4eea097334d6 | 171 | |
Anna Bridge |
142:4eea097334d6 | 172 | /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ |
Anna Bridge |
142:4eea097334d6 | 173 | /* Deprecated type names */ |
Anna Bridge |
142:4eea097334d6 | 174 | #define mscBusStrategy_Typedef MSC_BusStrategy_Typedef |
Anna Bridge |
142:4eea097334d6 | 175 | #define msc_Return_TypeDef MSC_Status_TypeDef |
Anna Bridge |
142:4eea097334d6 | 176 | /** @endcond */ |
Anna Bridge |
142:4eea097334d6 | 177 | |
Anna Bridge |
142:4eea097334d6 | 178 | /***************************************************************************//** |
Anna Bridge |
142:4eea097334d6 | 179 | * @brief |
Anna Bridge |
142:4eea097334d6 | 180 | * Clear one or more pending MSC interrupts. |
Anna Bridge |
142:4eea097334d6 | 181 | * |
Anna Bridge |
142:4eea097334d6 | 182 | * @param[in] flags |
Anna Bridge |
142:4eea097334d6 | 183 | * Pending MSC intterupt source to clear. Use a bitwise logic OR combination |
Anna Bridge |
142:4eea097334d6 | 184 | * of valid interrupt flags for the MSC module (MSC_IF_nnn). |
Anna Bridge |
142:4eea097334d6 | 185 | ******************************************************************************/ |
Anna Bridge |
142:4eea097334d6 | 186 | __STATIC_INLINE void MSC_IntClear(uint32_t flags) |
Anna Bridge |
142:4eea097334d6 | 187 | { |
Anna Bridge |
142:4eea097334d6 | 188 | MSC->IFC = flags; |
Anna Bridge |
142:4eea097334d6 | 189 | } |
Anna Bridge |
142:4eea097334d6 | 190 | |
Anna Bridge |
142:4eea097334d6 | 191 | /***************************************************************************//** |
Anna Bridge |
142:4eea097334d6 | 192 | * @brief |
Anna Bridge |
142:4eea097334d6 | 193 | * Disable one or more MSC interrupts. |
Anna Bridge |
142:4eea097334d6 | 194 | * |
Anna Bridge |
142:4eea097334d6 | 195 | * @param[in] flags |
Anna Bridge |
142:4eea097334d6 | 196 | * MSC interrupt sources to disable. Use a bitwise logic OR combination of |
Anna Bridge |
142:4eea097334d6 | 197 | * valid interrupt flags for the MSC module (MSC_IF_nnn). |
Anna Bridge |
142:4eea097334d6 | 198 | ******************************************************************************/ |
Anna Bridge |
142:4eea097334d6 | 199 | __STATIC_INLINE void MSC_IntDisable(uint32_t flags) |
Anna Bridge |
142:4eea097334d6 | 200 | { |
Anna Bridge |
142:4eea097334d6 | 201 | MSC->IEN &= ~(flags); |
Anna Bridge |
142:4eea097334d6 | 202 | } |
Anna Bridge |
142:4eea097334d6 | 203 | |
Anna Bridge |
142:4eea097334d6 | 204 | /***************************************************************************//** |
Anna Bridge |
142:4eea097334d6 | 205 | * @brief |
Anna Bridge |
142:4eea097334d6 | 206 | * Enable one or more MSC interrupts. |
Anna Bridge |
142:4eea097334d6 | 207 | * |
Anna Bridge |
142:4eea097334d6 | 208 | * @note |
Anna Bridge |
142:4eea097334d6 | 209 | * Depending on the use, a pending interrupt may already be set prior to |
Anna Bridge |
142:4eea097334d6 | 210 | * enabling the interrupt. Consider using MSC_IntClear() prior to enabling |
Anna Bridge |
142:4eea097334d6 | 211 | * if such a pending interrupt should be ignored. |
Anna Bridge |
142:4eea097334d6 | 212 | * |
Anna Bridge |
142:4eea097334d6 | 213 | * @param[in] flags |
Anna Bridge |
142:4eea097334d6 | 214 | * MSC interrupt sources to enable. Use a bitwise logic OR combination of |
Anna Bridge |
142:4eea097334d6 | 215 | * valid interrupt flags for the MSC module (MSC_IF_nnn). |
Anna Bridge |
142:4eea097334d6 | 216 | ******************************************************************************/ |
Anna Bridge |
142:4eea097334d6 | 217 | __STATIC_INLINE void MSC_IntEnable(uint32_t flags) |
Anna Bridge |
142:4eea097334d6 | 218 | { |
Anna Bridge |
142:4eea097334d6 | 219 | MSC->IEN |= flags; |
Anna Bridge |
142:4eea097334d6 | 220 | } |
Anna Bridge |
142:4eea097334d6 | 221 | |
Anna Bridge |
142:4eea097334d6 | 222 | /***************************************************************************//** |
Anna Bridge |
142:4eea097334d6 | 223 | * @brief |
Anna Bridge |
142:4eea097334d6 | 224 | * Get pending MSC interrupt flags. |
Anna Bridge |
142:4eea097334d6 | 225 | * |
Anna Bridge |
142:4eea097334d6 | 226 | * @note |
Anna Bridge |
142:4eea097334d6 | 227 | * The event bits are not cleared by the use of this function. |
Anna Bridge |
142:4eea097334d6 | 228 | * |
Anna Bridge |
142:4eea097334d6 | 229 | * @return |
Anna Bridge |
142:4eea097334d6 | 230 | * MSC interrupt sources pending. A bitwise logic OR combination of valid |
Anna Bridge |
142:4eea097334d6 | 231 | * interrupt flags for the MSC module (MSC_IF_nnn). |
Anna Bridge |
142:4eea097334d6 | 232 | ******************************************************************************/ |
Anna Bridge |
142:4eea097334d6 | 233 | __STATIC_INLINE uint32_t MSC_IntGet(void) |
Anna Bridge |
142:4eea097334d6 | 234 | { |
Anna Bridge |
142:4eea097334d6 | 235 | return(MSC->IF); |
Anna Bridge |
142:4eea097334d6 | 236 | } |
Anna Bridge |
142:4eea097334d6 | 237 | |
Anna Bridge |
142:4eea097334d6 | 238 | /***************************************************************************//** |
Anna Bridge |
142:4eea097334d6 | 239 | * @brief |
Anna Bridge |
142:4eea097334d6 | 240 | * Get enabled and pending MSC interrupt flags. |
Anna Bridge |
142:4eea097334d6 | 241 | * Useful for handling more interrupt sources in the same interrupt handler. |
Anna Bridge |
142:4eea097334d6 | 242 | * |
Anna Bridge |
142:4eea097334d6 | 243 | * @note |
Anna Bridge |
142:4eea097334d6 | 244 | * Interrupt flags are not cleared by the use of this function. |
Anna Bridge |
142:4eea097334d6 | 245 | * |
Anna Bridge |
142:4eea097334d6 | 246 | * @return |
Anna Bridge |
142:4eea097334d6 | 247 | * Pending and enabled MSC interrupt sources |
Anna Bridge |
142:4eea097334d6 | 248 | * The return value is the bitwise AND of |
Anna Bridge |
142:4eea097334d6 | 249 | * - the enabled interrupt sources in MSC_IEN and |
Anna Bridge |
142:4eea097334d6 | 250 | * - the pending interrupt flags MSC_IF |
Anna Bridge |
142:4eea097334d6 | 251 | ******************************************************************************/ |
Anna Bridge |
142:4eea097334d6 | 252 | __STATIC_INLINE uint32_t MSC_IntGetEnabled(void) |
Anna Bridge |
142:4eea097334d6 | 253 | { |
Anna Bridge |
142:4eea097334d6 | 254 | uint32_t ien; |
Anna Bridge |
142:4eea097334d6 | 255 | |
Anna Bridge |
142:4eea097334d6 | 256 | ien = MSC->IEN; |
Anna Bridge |
142:4eea097334d6 | 257 | return MSC->IF & ien; |
Anna Bridge |
142:4eea097334d6 | 258 | } |
Anna Bridge |
142:4eea097334d6 | 259 | |
Anna Bridge |
142:4eea097334d6 | 260 | /***************************************************************************//** |
Anna Bridge |
142:4eea097334d6 | 261 | * @brief |
Anna Bridge |
142:4eea097334d6 | 262 | * Set one or more pending MSC interrupts from SW. |
Anna Bridge |
142:4eea097334d6 | 263 | * |
Anna Bridge |
142:4eea097334d6 | 264 | * @param[in] flags |
Anna Bridge |
142:4eea097334d6 | 265 | * MSC interrupt sources to set to pending. Use a bitwise logic OR combination of |
Anna Bridge |
142:4eea097334d6 | 266 | * valid interrupt flags for the MSC module (MSC_IF_nnn). |
Anna Bridge |
142:4eea097334d6 | 267 | ******************************************************************************/ |
Anna Bridge |
142:4eea097334d6 | 268 | __STATIC_INLINE void MSC_IntSet(uint32_t flags) |
Anna Bridge |
142:4eea097334d6 | 269 | { |
Anna Bridge |
142:4eea097334d6 | 270 | MSC->IFS = flags; |
Anna Bridge |
142:4eea097334d6 | 271 | } |
Anna Bridge |
142:4eea097334d6 | 272 | |
Anna Bridge |
160:5571c4ff569f | 273 | #if defined(MSC_IF_CHOF) && defined(MSC_IF_CMOF) |
Anna Bridge |
142:4eea097334d6 | 274 | /***************************************************************************//** |
Anna Bridge |
142:4eea097334d6 | 275 | * @brief |
Anna Bridge |
142:4eea097334d6 | 276 | * Starts measuring cache hit ratio. |
Anna Bridge |
142:4eea097334d6 | 277 | * @details |
Anna Bridge |
142:4eea097334d6 | 278 | * This function starts the performance counters. It is defined inline to |
Anna Bridge |
142:4eea097334d6 | 279 | * minimize the impact of this code on the measurement itself. |
Anna Bridge |
142:4eea097334d6 | 280 | ******************************************************************************/ |
Anna Bridge |
142:4eea097334d6 | 281 | __STATIC_INLINE void MSC_StartCacheMeasurement(void) |
Anna Bridge |
142:4eea097334d6 | 282 | { |
Anna Bridge |
142:4eea097334d6 | 283 | /* Clear CMOF and CHOF to catch these later */ |
Anna Bridge |
142:4eea097334d6 | 284 | MSC->IFC = MSC_IF_CHOF | MSC_IF_CMOF; |
Anna Bridge |
142:4eea097334d6 | 285 | |
Anna Bridge |
142:4eea097334d6 | 286 | /* Start performance counters */ |
Anna Bridge |
160:5571c4ff569f | 287 | #if defined(_MSC_CACHECMD_MASK) |
Anna Bridge |
142:4eea097334d6 | 288 | MSC->CACHECMD = MSC_CACHECMD_STARTPC; |
Anna Bridge |
142:4eea097334d6 | 289 | #else |
Anna Bridge |
142:4eea097334d6 | 290 | MSC->CMD = MSC_CMD_STARTPC; |
Anna Bridge |
142:4eea097334d6 | 291 | #endif |
Anna Bridge |
142:4eea097334d6 | 292 | } |
Anna Bridge |
142:4eea097334d6 | 293 | |
Anna Bridge |
142:4eea097334d6 | 294 | /***************************************************************************//** |
Anna Bridge |
142:4eea097334d6 | 295 | * @brief |
Anna Bridge |
142:4eea097334d6 | 296 | * Stops measuring the hit rate. |
Anna Bridge |
142:4eea097334d6 | 297 | * @note |
Anna Bridge |
142:4eea097334d6 | 298 | * This function is defined inline to minimize the impact of this |
Anna Bridge |
142:4eea097334d6 | 299 | * code on the measurement itself. |
Anna Bridge |
142:4eea097334d6 | 300 | * This code only works for relatively short sections of code. If you wish |
Anna Bridge |
142:4eea097334d6 | 301 | * to measure longer sections of code you need to implement a IRQ Handler for |
Anna Bridge |
142:4eea097334d6 | 302 | * The CHOF and CMOF overflow interrupts. Theses overflows needs to be |
Anna Bridge |
142:4eea097334d6 | 303 | * counted and included in the total. |
Anna Bridge |
142:4eea097334d6 | 304 | * The functions can then be implemented as follows: |
Anna Bridge |
142:4eea097334d6 | 305 | * @verbatim |
Anna Bridge |
142:4eea097334d6 | 306 | * volatile uint32_t hitOverflows |
Anna Bridge |
142:4eea097334d6 | 307 | * volatile uint32_t missOverflows |
Anna Bridge |
142:4eea097334d6 | 308 | * |
Anna Bridge |
142:4eea097334d6 | 309 | * void MSC_IRQHandler(void) |
Anna Bridge |
142:4eea097334d6 | 310 | * { |
Anna Bridge |
142:4eea097334d6 | 311 | * uint32_t flags; |
Anna Bridge |
142:4eea097334d6 | 312 | * flags = MSC->IF; |
Anna Bridge |
160:5571c4ff569f | 313 | * if (flags & MSC_IF_CHOF) { |
Anna Bridge |
142:4eea097334d6 | 314 | * MSC->IFC = MSC_IF_CHOF; |
Anna Bridge |
142:4eea097334d6 | 315 | * hitOverflows++; |
Anna Bridge |
142:4eea097334d6 | 316 | * } |
Anna Bridge |
160:5571c4ff569f | 317 | * if (flags & MSC_IF_CMOF) { |
Anna Bridge |
142:4eea097334d6 | 318 | * MSC->IFC = MSC_IF_CMOF; |
Anna Bridge |
142:4eea097334d6 | 319 | * missOverflows++; |
Anna Bridge |
142:4eea097334d6 | 320 | * } |
Anna Bridge |
142:4eea097334d6 | 321 | * } |
Anna Bridge |
142:4eea097334d6 | 322 | * |
Anna Bridge |
142:4eea097334d6 | 323 | * void startPerformanceCounters(void) |
Anna Bridge |
142:4eea097334d6 | 324 | * { |
Anna Bridge |
142:4eea097334d6 | 325 | * hitOverflows = 0; |
Anna Bridge |
142:4eea097334d6 | 326 | * missOverflows = 0; |
Anna Bridge |
142:4eea097334d6 | 327 | * |
Anna Bridge |
142:4eea097334d6 | 328 | * MSC_IntEnable(MSC_IF_CHOF | MSC_IF_CMOF); |
Anna Bridge |
142:4eea097334d6 | 329 | * NVIC_EnableIRQ(MSC_IRQn); |
Anna Bridge |
142:4eea097334d6 | 330 | * |
Anna Bridge |
142:4eea097334d6 | 331 | * MSC_StartCacheMeasurement(); |
Anna Bridge |
142:4eea097334d6 | 332 | * } |
Anna Bridge |
142:4eea097334d6 | 333 | * @endverbatim |
Anna Bridge |
142:4eea097334d6 | 334 | * @return |
Anna Bridge |
142:4eea097334d6 | 335 | * Returns -1 if there has been no cache accesses. |
Anna Bridge |
142:4eea097334d6 | 336 | * Returns -2 if there has been an overflow in the performance counters. |
Anna Bridge |
142:4eea097334d6 | 337 | * If not, it will return the percentage of hits versus misses. |
Anna Bridge |
142:4eea097334d6 | 338 | ******************************************************************************/ |
Anna Bridge |
142:4eea097334d6 | 339 | __STATIC_INLINE int32_t MSC_GetCacheMeasurement(void) |
Anna Bridge |
142:4eea097334d6 | 340 | { |
Anna Bridge |
142:4eea097334d6 | 341 | int32_t total; |
Anna Bridge |
142:4eea097334d6 | 342 | int32_t hits; |
Anna Bridge |
142:4eea097334d6 | 343 | /* Stop the counter before computing the hit-rate */ |
Anna Bridge |
160:5571c4ff569f | 344 | #if defined(_MSC_CACHECMD_MASK) |
Anna Bridge |
142:4eea097334d6 | 345 | MSC->CACHECMD = MSC_CACHECMD_STOPPC; |
Anna Bridge |
142:4eea097334d6 | 346 | #else |
Anna Bridge |
142:4eea097334d6 | 347 | MSC->CMD = MSC_CMD_STOPPC; |
Anna Bridge |
142:4eea097334d6 | 348 | #endif |
Anna Bridge |
142:4eea097334d6 | 349 | |
Anna Bridge |
142:4eea097334d6 | 350 | /* Check for overflows in performance counters */ |
Anna Bridge |
160:5571c4ff569f | 351 | if (MSC->IF & (MSC_IF_CHOF | MSC_IF_CMOF)) { |
Anna Bridge |
142:4eea097334d6 | 352 | return -2; |
Anna Bridge |
142:4eea097334d6 | 353 | } |
Anna Bridge |
142:4eea097334d6 | 354 | |
Anna Bridge |
142:4eea097334d6 | 355 | hits = MSC->CACHEHITS; |
Anna Bridge |
142:4eea097334d6 | 356 | total = MSC->CACHEMISSES + hits; |
Anna Bridge |
142:4eea097334d6 | 357 | |
Anna Bridge |
142:4eea097334d6 | 358 | /* To avoid a division by zero. */ |
Anna Bridge |
160:5571c4ff569f | 359 | if (total == 0) { |
Anna Bridge |
142:4eea097334d6 | 360 | return -1; |
Anna Bridge |
142:4eea097334d6 | 361 | } |
Anna Bridge |
142:4eea097334d6 | 362 | |
Anna Bridge |
142:4eea097334d6 | 363 | return (hits * 100) / total; |
Anna Bridge |
142:4eea097334d6 | 364 | } |
Anna Bridge |
142:4eea097334d6 | 365 | |
Anna Bridge |
142:4eea097334d6 | 366 | /***************************************************************************//** |
Anna Bridge |
142:4eea097334d6 | 367 | * @brief |
Anna Bridge |
142:4eea097334d6 | 368 | * Flush the contents of the instruction cache. |
Anna Bridge |
142:4eea097334d6 | 369 | ******************************************************************************/ |
Anna Bridge |
142:4eea097334d6 | 370 | __STATIC_INLINE void MSC_FlushCache(void) |
Anna Bridge |
142:4eea097334d6 | 371 | { |
Anna Bridge |
160:5571c4ff569f | 372 | #if defined(_MSC_CACHECMD_MASK) |
Anna Bridge |
142:4eea097334d6 | 373 | MSC->CACHECMD = MSC_CACHECMD_INVCACHE; |
Anna Bridge |
142:4eea097334d6 | 374 | #else |
Anna Bridge |
142:4eea097334d6 | 375 | MSC->CMD = MSC_CMD_INVCACHE; |
Anna Bridge |
142:4eea097334d6 | 376 | #endif |
Anna Bridge |
142:4eea097334d6 | 377 | } |
Anna Bridge |
142:4eea097334d6 | 378 | |
Anna Bridge |
142:4eea097334d6 | 379 | /***************************************************************************//** |
Anna Bridge |
142:4eea097334d6 | 380 | * @brief |
Anna Bridge |
142:4eea097334d6 | 381 | * Enable or disable instruction cache functionality |
Anna Bridge |
142:4eea097334d6 | 382 | * @param[in] enable |
Anna Bridge |
142:4eea097334d6 | 383 | * Enable instruction cache. Default is on. |
Anna Bridge |
142:4eea097334d6 | 384 | ******************************************************************************/ |
Anna Bridge |
142:4eea097334d6 | 385 | __STATIC_INLINE void MSC_EnableCache(bool enable) |
Anna Bridge |
142:4eea097334d6 | 386 | { |
Anna Bridge |
142:4eea097334d6 | 387 | BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_IFCDIS_SHIFT, !enable); |
Anna Bridge |
142:4eea097334d6 | 388 | } |
Anna Bridge |
142:4eea097334d6 | 389 | |
Anna Bridge |
160:5571c4ff569f | 390 | #if defined(MSC_READCTRL_ICCDIS) |
Anna Bridge |
142:4eea097334d6 | 391 | /***************************************************************************//** |
Anna Bridge |
142:4eea097334d6 | 392 | * @brief |
Anna Bridge |
142:4eea097334d6 | 393 | * Enable or disable instruction cache functionality in IRQs |
Anna Bridge |
142:4eea097334d6 | 394 | * @param[in] enable |
Anna Bridge |
142:4eea097334d6 | 395 | * Enable instruction cache. Default is on. |
Anna Bridge |
142:4eea097334d6 | 396 | ******************************************************************************/ |
Anna Bridge |
142:4eea097334d6 | 397 | __STATIC_INLINE void MSC_EnableCacheIRQs(bool enable) |
Anna Bridge |
142:4eea097334d6 | 398 | { |
Anna Bridge |
142:4eea097334d6 | 399 | BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_ICCDIS_SHIFT, !enable); |
Anna Bridge |
142:4eea097334d6 | 400 | } |
Anna Bridge |
142:4eea097334d6 | 401 | #endif |
Anna Bridge |
142:4eea097334d6 | 402 | |
Anna Bridge |
142:4eea097334d6 | 403 | /***************************************************************************//** |
Anna Bridge |
142:4eea097334d6 | 404 | * @brief |
Anna Bridge |
142:4eea097334d6 | 405 | * Enable or disable instruction cache flushing when writing to flash |
Anna Bridge |
142:4eea097334d6 | 406 | * @param[in] enable |
Anna Bridge |
142:4eea097334d6 | 407 | * Enable automatic cache flushing. Default is on. |
Anna Bridge |
142:4eea097334d6 | 408 | ******************************************************************************/ |
Anna Bridge |
142:4eea097334d6 | 409 | __STATIC_INLINE void MSC_EnableAutoCacheFlush(bool enable) |
Anna Bridge |
142:4eea097334d6 | 410 | { |
Anna Bridge |
142:4eea097334d6 | 411 | BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_AIDIS_SHIFT, !enable); |
Anna Bridge |
142:4eea097334d6 | 412 | } |
Anna Bridge |
142:4eea097334d6 | 413 | #endif /* defined( MSC_IF_CHOF ) && defined( MSC_IF_CMOF ) */ |
Anna Bridge |
142:4eea097334d6 | 414 | |
Anna Bridge |
160:5571c4ff569f | 415 | #if defined(_MSC_READCTRL_BUSSTRATEGY_MASK) |
Anna Bridge |
142:4eea097334d6 | 416 | /***************************************************************************//** |
Anna Bridge |
142:4eea097334d6 | 417 | * @brief |
Anna Bridge |
142:4eea097334d6 | 418 | * Configure which unit should get priority on system bus. |
Anna Bridge |
142:4eea097334d6 | 419 | * @param[in] mode |
Anna Bridge |
142:4eea097334d6 | 420 | * Unit to prioritize bus accesses for. |
Anna Bridge |
142:4eea097334d6 | 421 | ******************************************************************************/ |
Anna Bridge |
142:4eea097334d6 | 422 | __STATIC_INLINE void MSC_BusStrategy(mscBusStrategy_Typedef mode) |
Anna Bridge |
142:4eea097334d6 | 423 | { |
Anna Bridge |
142:4eea097334d6 | 424 | MSC->READCTRL = (MSC->READCTRL & ~(_MSC_READCTRL_BUSSTRATEGY_MASK)) | mode; |
Anna Bridge |
142:4eea097334d6 | 425 | } |
Anna Bridge |
142:4eea097334d6 | 426 | #endif |
Anna Bridge |
142:4eea097334d6 | 427 | |
Anna Bridge |
142:4eea097334d6 | 428 | /******************************************************************************* |
Anna Bridge |
142:4eea097334d6 | 429 | ************************* PROTOTYPES ************************************** |
Anna Bridge |
142:4eea097334d6 | 430 | ******************************************************************************/ |
Anna Bridge |
142:4eea097334d6 | 431 | |
Anna Bridge |
142:4eea097334d6 | 432 | void MSC_Init(void); |
Anna Bridge |
142:4eea097334d6 | 433 | void MSC_Deinit(void); |
Anna Bridge |
142:4eea097334d6 | 434 | void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig); |
Anna Bridge |
142:4eea097334d6 | 435 | |
Anna Bridge |
142:4eea097334d6 | 436 | #if defined(EM_MSC_RUN_FROM_FLASH) |
Anna Bridge |
142:4eea097334d6 | 437 | /** @brief Expands to @ref SL_RAMFUNC_DECLARATOR if @ref EM_MSC_RUN_FROM_FLASH is undefined and to nothing if @ref EM_MSC_RUN_FROM_FLASH is defined. */ |
Anna Bridge |
142:4eea097334d6 | 438 | #define MSC_RAMFUNC_DECLARATOR |
Anna Bridge |
142:4eea097334d6 | 439 | /** @brief Expands to @ref SL_RAMFUNC_DEFINITION_BEGIN if @ref EM_MSC_RUN_FROM_FLASH is undefined and to nothing if @ref EM_MSC_RUN_FROM_FLASH is defined. */ |
Anna Bridge |
142:4eea097334d6 | 440 | #define MSC_RAMFUNC_DEFINITION_BEGIN |
Anna Bridge |
142:4eea097334d6 | 441 | /** @brief Expands to @ref SL_RAMFUNC_DEFINITION_END if @ref EM_MSC_RUN_FROM_FLASH is undefined and to nothing if @ref EM_MSC_RUN_FROM_FLASH is defined. */ |
Anna Bridge |
142:4eea097334d6 | 442 | #define MSC_RAMFUNC_DEFINITION_END |
Anna Bridge |
142:4eea097334d6 | 443 | #else |
Anna Bridge |
142:4eea097334d6 | 444 | #define MSC_RAMFUNC_DECLARATOR SL_RAMFUNC_DECLARATOR |
Anna Bridge |
142:4eea097334d6 | 445 | #define MSC_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DEFINITION_BEGIN |
Anna Bridge |
142:4eea097334d6 | 446 | #define MSC_RAMFUNC_DEFINITION_END SL_RAMFUNC_DEFINITION_END |
Anna Bridge |
142:4eea097334d6 | 447 | #endif |
Anna Bridge |
142:4eea097334d6 | 448 | |
Anna Bridge |
142:4eea097334d6 | 449 | MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef |
Anna Bridge |
160:5571c4ff569f | 450 | MSC_WriteWord(uint32_t *address, |
Anna Bridge |
160:5571c4ff569f | 451 | void const *data, |
Anna Bridge |
160:5571c4ff569f | 452 | uint32_t numBytes); |
Anna Bridge |
142:4eea097334d6 | 453 | |
Anna Bridge |
160:5571c4ff569f | 454 | #if !defined(_EFM32_GECKO_FAMILY) |
Anna Bridge |
160:5571c4ff569f | 455 | #if !defined (EM_MSC_RUN_FROM_FLASH) || (_SILICON_LABS_GECKO_INTERNAL_SDID < 84) |
Anna Bridge |
142:4eea097334d6 | 456 | MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef |
Anna Bridge |
160:5571c4ff569f | 457 | MSC_WriteWordFast(uint32_t *address, |
Anna Bridge |
160:5571c4ff569f | 458 | void const *data, |
Anna Bridge |
160:5571c4ff569f | 459 | uint32_t numBytes); |
Anna Bridge |
160:5571c4ff569f | 460 | #endif |
Anna Bridge |
142:4eea097334d6 | 461 | #endif |
Anna Bridge |
142:4eea097334d6 | 462 | |
Anna Bridge |
142:4eea097334d6 | 463 | MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef |
Anna Bridge |
160:5571c4ff569f | 464 | MSC_ErasePage(uint32_t *startAddress); |
Anna Bridge |
142:4eea097334d6 | 465 | |
Anna Bridge |
160:5571c4ff569f | 466 | #if defined(_MSC_MASSLOCK_MASK) |
Anna Bridge |
142:4eea097334d6 | 467 | MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef |
Anna Bridge |
160:5571c4ff569f | 468 | MSC_MassErase(void); |
Anna Bridge |
142:4eea097334d6 | 469 | #endif |
Anna Bridge |
142:4eea097334d6 | 470 | |
Anna Bridge |
142:4eea097334d6 | 471 | /** @} (end addtogroup MSC) */ |
Anna Bridge |
142:4eea097334d6 | 472 | /** @} (end addtogroup emlib) */ |
Anna Bridge |
142:4eea097334d6 | 473 | |
Anna Bridge |
142:4eea097334d6 | 474 | #ifdef __cplusplus |
Anna Bridge |
142:4eea097334d6 | 475 | } |
Anna Bridge |
142:4eea097334d6 | 476 | #endif |
Anna Bridge |
142:4eea097334d6 | 477 | |
Anna Bridge |
142:4eea097334d6 | 478 | #endif /* defined(MSC_COUNT) && (MSC_COUNT > 0) */ |
Anna Bridge |
142:4eea097334d6 | 479 | #endif /* EM_MSC_H */ |