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TARGET_NUCLEO_L073RZ/TOOLCHAIN_ARM_MICRO/stm32l0xx_ll_dac.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_dac.h@167:84c0a372a020
mbed library. Release version 164
Who changed what in which revision?
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AnnaBridge | 143:86740a56073b | 1 | /** |
AnnaBridge | 143:86740a56073b | 2 | ****************************************************************************** |
AnnaBridge | 143:86740a56073b | 3 | * @file stm32l0xx_ll_dac.h |
AnnaBridge | 143:86740a56073b | 4 | * @author MCD Application Team |
AnnaBridge | 143:86740a56073b | 5 | * @brief Header file of DAC LL module. |
AnnaBridge | 143:86740a56073b | 6 | ****************************************************************************** |
AnnaBridge | 143:86740a56073b | 7 | * @attention |
AnnaBridge | 143:86740a56073b | 8 | * |
AnnaBridge | 143:86740a56073b | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
AnnaBridge | 143:86740a56073b | 10 | * |
AnnaBridge | 143:86740a56073b | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 143:86740a56073b | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 143:86740a56073b | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 143:86740a56073b | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 143:86740a56073b | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 143:86740a56073b | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 143:86740a56073b | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 143:86740a56073b | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 143:86740a56073b | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 143:86740a56073b | 20 | * without specific prior written permission. |
AnnaBridge | 143:86740a56073b | 21 | * |
AnnaBridge | 143:86740a56073b | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 143:86740a56073b | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 143:86740a56073b | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 143:86740a56073b | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 143:86740a56073b | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 143:86740a56073b | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 143:86740a56073b | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 143:86740a56073b | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 143:86740a56073b | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 143:86740a56073b | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 143:86740a56073b | 32 | * |
AnnaBridge | 143:86740a56073b | 33 | ****************************************************************************** |
AnnaBridge | 143:86740a56073b | 34 | */ |
AnnaBridge | 143:86740a56073b | 35 | |
AnnaBridge | 143:86740a56073b | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 37 | #ifndef __STM32L0xx_LL_DAC_H |
AnnaBridge | 143:86740a56073b | 38 | #define __STM32L0xx_LL_DAC_H |
AnnaBridge | 143:86740a56073b | 39 | |
AnnaBridge | 143:86740a56073b | 40 | #ifdef __cplusplus |
AnnaBridge | 143:86740a56073b | 41 | extern "C" { |
AnnaBridge | 143:86740a56073b | 42 | #endif |
AnnaBridge | 143:86740a56073b | 43 | |
AnnaBridge | 143:86740a56073b | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 45 | #include "stm32l0xx.h" |
AnnaBridge | 143:86740a56073b | 46 | |
AnnaBridge | 143:86740a56073b | 47 | /** @addtogroup STM32L0xx_LL_Driver |
AnnaBridge | 143:86740a56073b | 48 | * @{ |
AnnaBridge | 143:86740a56073b | 49 | */ |
AnnaBridge | 143:86740a56073b | 50 | |
AnnaBridge | 143:86740a56073b | 51 | #if defined (DAC1) |
AnnaBridge | 143:86740a56073b | 52 | |
AnnaBridge | 143:86740a56073b | 53 | /** @defgroup DAC_LL DAC |
AnnaBridge | 143:86740a56073b | 54 | * @{ |
AnnaBridge | 143:86740a56073b | 55 | */ |
AnnaBridge | 143:86740a56073b | 56 | |
AnnaBridge | 143:86740a56073b | 57 | /* Private types -------------------------------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 58 | /* Private variables ---------------------------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 59 | |
AnnaBridge | 143:86740a56073b | 60 | /* Private constants ---------------------------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 61 | /** @defgroup DAC_LL_Private_Constants DAC Private Constants |
AnnaBridge | 143:86740a56073b | 62 | * @{ |
AnnaBridge | 143:86740a56073b | 63 | */ |
AnnaBridge | 143:86740a56073b | 64 | |
AnnaBridge | 143:86740a56073b | 65 | /* Internal masks for DAC channels definition */ |
AnnaBridge | 143:86740a56073b | 66 | /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ |
AnnaBridge | 143:86740a56073b | 67 | /* - channel bits position into register CR */ |
AnnaBridge | 143:86740a56073b | 68 | /* - channel bits position into register SWTRIG */ |
AnnaBridge | 143:86740a56073b | 69 | /* - channel register offset of data holding register DHRx */ |
AnnaBridge | 143:86740a56073b | 70 | /* - channel register offset of data output register DORx */ |
AnnaBridge | 167:84c0a372a020 | 71 | #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ |
AnnaBridge | 167:84c0a372a020 | 72 | #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ |
AnnaBridge | 143:86740a56073b | 73 | #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) |
AnnaBridge | 143:86740a56073b | 74 | |
AnnaBridge | 143:86740a56073b | 75 | #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ |
AnnaBridge | 143:86740a56073b | 76 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 143:86740a56073b | 77 | #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ |
AnnaBridge | 143:86740a56073b | 78 | #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) |
AnnaBridge | 143:86740a56073b | 79 | #else |
AnnaBridge | 143:86740a56073b | 80 | #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1) |
AnnaBridge | 143:86740a56073b | 81 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 143:86740a56073b | 82 | |
AnnaBridge | 167:84c0a372a020 | 83 | #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */ |
AnnaBridge | 167:84c0a372a020 | 84 | #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
AnnaBridge | 167:84c0a372a020 | 85 | #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
AnnaBridge | 143:86740a56073b | 86 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 167:84c0a372a020 | 87 | #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ |
AnnaBridge | 167:84c0a372a020 | 88 | #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
AnnaBridge | 167:84c0a372a020 | 89 | #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
AnnaBridge | 143:86740a56073b | 90 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 167:84c0a372a020 | 91 | #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U |
AnnaBridge | 167:84c0a372a020 | 92 | #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U |
AnnaBridge | 167:84c0a372a020 | 93 | #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U |
AnnaBridge | 143:86740a56073b | 94 | #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) |
AnnaBridge | 143:86740a56073b | 95 | |
AnnaBridge | 167:84c0a372a020 | 96 | #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ |
AnnaBridge | 143:86740a56073b | 97 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 167:84c0a372a020 | 98 | #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */ |
AnnaBridge | 143:86740a56073b | 99 | #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) |
AnnaBridge | 143:86740a56073b | 100 | #else |
AnnaBridge | 143:86740a56073b | 101 | #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET) |
AnnaBridge | 143:86740a56073b | 102 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 143:86740a56073b | 103 | |
AnnaBridge | 167:84c0a372a020 | 104 | #define DAC_REG_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of registers offset (DHR12Rx, DHR12Lx, DHR8Rx, DORx, ...) when shifted to position 0 */ |
AnnaBridge | 143:86740a56073b | 105 | |
AnnaBridge | 167:84c0a372a020 | 106 | #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ |
AnnaBridge | 167:84c0a372a020 | 107 | #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
AnnaBridge | 167:84c0a372a020 | 108 | #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
AnnaBridge | 167:84c0a372a020 | 109 | #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 28 bits) */ |
AnnaBridge | 143:86740a56073b | 110 | |
AnnaBridge | 143:86740a56073b | 111 | /* DAC registers bits positions */ |
AnnaBridge | 143:86740a56073b | 112 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 167:84c0a372a020 | 113 | #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */ |
AnnaBridge | 167:84c0a372a020 | 114 | #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */ |
AnnaBridge | 167:84c0a372a020 | 115 | #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */ |
AnnaBridge | 143:86740a56073b | 116 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 143:86740a56073b | 117 | |
AnnaBridge | 143:86740a56073b | 118 | /* Miscellaneous data */ |
AnnaBridge | 167:84c0a372a020 | 119 | #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ |
AnnaBridge | 143:86740a56073b | 120 | |
AnnaBridge | 143:86740a56073b | 121 | /** |
AnnaBridge | 143:86740a56073b | 122 | * @} |
AnnaBridge | 143:86740a56073b | 123 | */ |
AnnaBridge | 143:86740a56073b | 124 | |
AnnaBridge | 143:86740a56073b | 125 | |
AnnaBridge | 143:86740a56073b | 126 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 127 | /** @defgroup DAC_LL_Private_Macros DAC Private Macros |
AnnaBridge | 143:86740a56073b | 128 | * @{ |
AnnaBridge | 143:86740a56073b | 129 | */ |
AnnaBridge | 143:86740a56073b | 130 | |
AnnaBridge | 143:86740a56073b | 131 | /** |
AnnaBridge | 143:86740a56073b | 132 | * @brief Driver macro reserved for internal use: set a pointer to |
AnnaBridge | 143:86740a56073b | 133 | * a register from a register basis from which an offset |
AnnaBridge | 143:86740a56073b | 134 | * is applied. |
AnnaBridge | 143:86740a56073b | 135 | * @param __REG__ Register basis from which the offset is applied. |
AnnaBridge | 143:86740a56073b | 136 | * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). |
AnnaBridge | 143:86740a56073b | 137 | * @retval Pointer to register address |
AnnaBridge | 143:86740a56073b | 138 | */ |
AnnaBridge | 143:86740a56073b | 139 | #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ |
AnnaBridge | 143:86740a56073b | 140 | ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) |
AnnaBridge | 143:86740a56073b | 141 | |
AnnaBridge | 143:86740a56073b | 142 | /** |
AnnaBridge | 143:86740a56073b | 143 | * @} |
AnnaBridge | 143:86740a56073b | 144 | */ |
AnnaBridge | 143:86740a56073b | 145 | |
AnnaBridge | 143:86740a56073b | 146 | |
AnnaBridge | 143:86740a56073b | 147 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 148 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 143:86740a56073b | 149 | /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure |
AnnaBridge | 143:86740a56073b | 150 | * @{ |
AnnaBridge | 143:86740a56073b | 151 | */ |
AnnaBridge | 143:86740a56073b | 152 | |
AnnaBridge | 143:86740a56073b | 153 | /** |
AnnaBridge | 143:86740a56073b | 154 | * @brief Structure definition of some features of DAC instance. |
AnnaBridge | 143:86740a56073b | 155 | */ |
AnnaBridge | 143:86740a56073b | 156 | typedef struct |
AnnaBridge | 143:86740a56073b | 157 | { |
AnnaBridge | 143:86740a56073b | 158 | uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line). |
AnnaBridge | 143:86740a56073b | 159 | This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE |
AnnaBridge | 143:86740a56073b | 160 | |
AnnaBridge | 143:86740a56073b | 161 | This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */ |
AnnaBridge | 143:86740a56073b | 162 | |
AnnaBridge | 143:86740a56073b | 163 | uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. |
AnnaBridge | 143:86740a56073b | 164 | This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE |
AnnaBridge | 143:86740a56073b | 165 | |
AnnaBridge | 143:86740a56073b | 166 | This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */ |
AnnaBridge | 143:86740a56073b | 167 | |
AnnaBridge | 143:86740a56073b | 168 | uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. |
AnnaBridge | 143:86740a56073b | 169 | If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS |
AnnaBridge | 143:86740a56073b | 170 | If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE |
AnnaBridge | 143:86740a56073b | 171 | @note If waveform automatic generation mode is disabled, this parameter is discarded. |
AnnaBridge | 143:86740a56073b | 172 | |
AnnaBridge | 143:86740a56073b | 173 | This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */ |
AnnaBridge | 143:86740a56073b | 174 | |
AnnaBridge | 143:86740a56073b | 175 | uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. |
AnnaBridge | 143:86740a56073b | 176 | This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER |
AnnaBridge | 143:86740a56073b | 177 | |
AnnaBridge | 143:86740a56073b | 178 | This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */ |
AnnaBridge | 143:86740a56073b | 179 | |
AnnaBridge | 143:86740a56073b | 180 | } LL_DAC_InitTypeDef; |
AnnaBridge | 143:86740a56073b | 181 | |
AnnaBridge | 143:86740a56073b | 182 | /** |
AnnaBridge | 143:86740a56073b | 183 | * @} |
AnnaBridge | 143:86740a56073b | 184 | */ |
AnnaBridge | 143:86740a56073b | 185 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 143:86740a56073b | 186 | |
AnnaBridge | 143:86740a56073b | 187 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 188 | /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants |
AnnaBridge | 143:86740a56073b | 189 | * @{ |
AnnaBridge | 143:86740a56073b | 190 | */ |
AnnaBridge | 143:86740a56073b | 191 | |
AnnaBridge | 143:86740a56073b | 192 | /** @defgroup DAC_LL_EC_GET_FLAG DAC flags |
AnnaBridge | 143:86740a56073b | 193 | * @brief Flags defines which can be used with LL_DAC_ReadReg function |
AnnaBridge | 143:86740a56073b | 194 | * @{ |
AnnaBridge | 143:86740a56073b | 195 | */ |
AnnaBridge | 143:86740a56073b | 196 | /* DAC channel 1 flags */ |
AnnaBridge | 143:86740a56073b | 197 | #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */ |
AnnaBridge | 143:86740a56073b | 198 | |
AnnaBridge | 143:86740a56073b | 199 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 143:86740a56073b | 200 | /* DAC channel 2 flags */ |
AnnaBridge | 143:86740a56073b | 201 | #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ |
AnnaBridge | 143:86740a56073b | 202 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 143:86740a56073b | 203 | /** |
AnnaBridge | 143:86740a56073b | 204 | * @} |
AnnaBridge | 143:86740a56073b | 205 | */ |
AnnaBridge | 143:86740a56073b | 206 | |
AnnaBridge | 143:86740a56073b | 207 | /** @defgroup DAC_LL_EC_IT DAC interruptions |
AnnaBridge | 143:86740a56073b | 208 | * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions |
AnnaBridge | 143:86740a56073b | 209 | * @{ |
AnnaBridge | 143:86740a56073b | 210 | */ |
AnnaBridge | 143:86740a56073b | 211 | #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ |
AnnaBridge | 143:86740a56073b | 212 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 143:86740a56073b | 213 | #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ |
AnnaBridge | 143:86740a56073b | 214 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 143:86740a56073b | 215 | /** |
AnnaBridge | 143:86740a56073b | 216 | * @} |
AnnaBridge | 143:86740a56073b | 217 | */ |
AnnaBridge | 143:86740a56073b | 218 | |
AnnaBridge | 143:86740a56073b | 219 | /** @defgroup DAC_LL_EC_CHANNEL DAC channels |
AnnaBridge | 143:86740a56073b | 220 | * @{ |
AnnaBridge | 143:86740a56073b | 221 | */ |
AnnaBridge | 143:86740a56073b | 222 | #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */ |
AnnaBridge | 143:86740a56073b | 223 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 143:86740a56073b | 224 | #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */ |
AnnaBridge | 143:86740a56073b | 225 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 143:86740a56073b | 226 | /** |
AnnaBridge | 143:86740a56073b | 227 | * @} |
AnnaBridge | 143:86740a56073b | 228 | */ |
AnnaBridge | 143:86740a56073b | 229 | |
AnnaBridge | 143:86740a56073b | 230 | /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source |
AnnaBridge | 143:86740a56073b | 231 | * @{ |
AnnaBridge | 143:86740a56073b | 232 | */ |
AnnaBridge | 143:86740a56073b | 233 | #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ |
AnnaBridge | 143:86740a56073b | 234 | #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ |
AnnaBridge | 143:86740a56073b | 235 | #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */ |
AnnaBridge | 143:86740a56073b | 236 | #define LL_DAC_TRIG_EXT_TIM3_CH3 ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM3 CH3 event. */ |
AnnaBridge | 167:84c0a372a020 | 237 | #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ |
AnnaBridge | 143:86740a56073b | 238 | #define LL_DAC_TRIG_EXT_TIM7_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ |
AnnaBridge | 143:86740a56073b | 239 | #define LL_DAC_TRIG_EXT_TIM21_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM21 TRGO. */ |
AnnaBridge | 143:86740a56073b | 240 | #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ |
AnnaBridge | 143:86740a56073b | 241 | /** |
AnnaBridge | 143:86740a56073b | 242 | * @} |
AnnaBridge | 143:86740a56073b | 243 | */ |
AnnaBridge | 143:86740a56073b | 244 | |
AnnaBridge | 143:86740a56073b | 245 | /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode |
AnnaBridge | 143:86740a56073b | 246 | * @{ |
AnnaBridge | 143:86740a56073b | 247 | */ |
AnnaBridge | 167:84c0a372a020 | 248 | #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */ |
AnnaBridge | 143:86740a56073b | 249 | #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ |
AnnaBridge | 143:86740a56073b | 250 | #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ |
AnnaBridge | 143:86740a56073b | 251 | /** |
AnnaBridge | 143:86740a56073b | 252 | * @} |
AnnaBridge | 143:86740a56073b | 253 | */ |
AnnaBridge | 143:86740a56073b | 254 | |
AnnaBridge | 143:86740a56073b | 255 | /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits |
AnnaBridge | 143:86740a56073b | 256 | * @{ |
AnnaBridge | 143:86740a56073b | 257 | */ |
AnnaBridge | 167:84c0a372a020 | 258 | #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 259 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 260 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 261 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 262 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 263 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 264 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 265 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 266 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 267 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 268 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 269 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 270 | /** |
AnnaBridge | 143:86740a56073b | 271 | * @} |
AnnaBridge | 143:86740a56073b | 272 | */ |
AnnaBridge | 143:86740a56073b | 273 | |
AnnaBridge | 143:86740a56073b | 274 | /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude |
AnnaBridge | 143:86740a56073b | 275 | * @{ |
AnnaBridge | 143:86740a56073b | 276 | */ |
AnnaBridge | 167:84c0a372a020 | 277 | #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 278 | #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 279 | #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 280 | #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 281 | #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 282 | #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 283 | #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 284 | #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 285 | #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 286 | #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 287 | #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 288 | #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 143:86740a56073b | 289 | /** |
AnnaBridge | 143:86740a56073b | 290 | * @} |
AnnaBridge | 143:86740a56073b | 291 | */ |
AnnaBridge | 143:86740a56073b | 292 | |
AnnaBridge | 143:86740a56073b | 293 | /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer |
AnnaBridge | 143:86740a56073b | 294 | * @{ |
AnnaBridge | 143:86740a56073b | 295 | */ |
AnnaBridge | 167:84c0a372a020 | 296 | #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ |
AnnaBridge | 143:86740a56073b | 297 | #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ |
AnnaBridge | 143:86740a56073b | 298 | /** |
AnnaBridge | 143:86740a56073b | 299 | * @} |
AnnaBridge | 143:86740a56073b | 300 | */ |
AnnaBridge | 143:86740a56073b | 301 | |
AnnaBridge | 143:86740a56073b | 302 | |
AnnaBridge | 143:86740a56073b | 303 | /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution |
AnnaBridge | 143:86740a56073b | 304 | * @{ |
AnnaBridge | 143:86740a56073b | 305 | */ |
AnnaBridge | 167:84c0a372a020 | 306 | #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */ |
AnnaBridge | 167:84c0a372a020 | 307 | #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */ |
AnnaBridge | 143:86740a56073b | 308 | /** |
AnnaBridge | 143:86740a56073b | 309 | * @} |
AnnaBridge | 143:86740a56073b | 310 | */ |
AnnaBridge | 143:86740a56073b | 311 | |
AnnaBridge | 143:86740a56073b | 312 | /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose |
AnnaBridge | 143:86740a56073b | 313 | * @{ |
AnnaBridge | 143:86740a56073b | 314 | */ |
AnnaBridge | 143:86740a56073b | 315 | /* List of DAC registers intended to be used (most commonly) with */ |
AnnaBridge | 143:86740a56073b | 316 | /* DMA transfer. */ |
AnnaBridge | 143:86740a56073b | 317 | /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ |
AnnaBridge | 143:86740a56073b | 318 | #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */ |
AnnaBridge | 143:86740a56073b | 319 | #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */ |
AnnaBridge | 143:86740a56073b | 320 | #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */ |
AnnaBridge | 143:86740a56073b | 321 | /** |
AnnaBridge | 143:86740a56073b | 322 | * @} |
AnnaBridge | 143:86740a56073b | 323 | */ |
AnnaBridge | 143:86740a56073b | 324 | |
AnnaBridge | 143:86740a56073b | 325 | /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays |
AnnaBridge | 143:86740a56073b | 326 | * @note Only DAC IP HW delays are defined in DAC LL driver driver, |
AnnaBridge | 143:86740a56073b | 327 | * not timeout values. |
AnnaBridge | 143:86740a56073b | 328 | * For details on delays values, refer to descriptions in source code |
AnnaBridge | 143:86740a56073b | 329 | * above each literal definition. |
AnnaBridge | 143:86740a56073b | 330 | * @{ |
AnnaBridge | 143:86740a56073b | 331 | */ |
AnnaBridge | 143:86740a56073b | 332 | |
AnnaBridge | 143:86740a56073b | 333 | /* Delay for DAC channel voltage settling time from DAC channel startup */ |
AnnaBridge | 143:86740a56073b | 334 | /* (transition from disable to enable). */ |
AnnaBridge | 143:86740a56073b | 335 | /* Note: DAC channel startup time depends on board application environment: */ |
AnnaBridge | 143:86740a56073b | 336 | /* impedance connected to DAC channel output. */ |
AnnaBridge | 143:86740a56073b | 337 | /* The delay below is specified under conditions: */ |
AnnaBridge | 143:86740a56073b | 338 | /* - voltage maximum transition (lowest to highest value) */ |
AnnaBridge | 143:86740a56073b | 339 | /* - until voltage reaches final value +-1LSB */ |
AnnaBridge | 143:86740a56073b | 340 | /* - DAC channel output buffer enabled */ |
AnnaBridge | 143:86740a56073b | 341 | /* - load impedance of 5kOhm (min), 50pF (max) */ |
AnnaBridge | 143:86740a56073b | 342 | /* Literal set to maximum value (refer to device datasheet, */ |
AnnaBridge | 143:86740a56073b | 343 | /* parameter "tWAKEUP"). */ |
AnnaBridge | 143:86740a56073b | 344 | /* Unit: us */ |
AnnaBridge | 167:84c0a372a020 | 345 | #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ |
AnnaBridge | 143:86740a56073b | 346 | |
AnnaBridge | 143:86740a56073b | 347 | /* Delay for DAC channel voltage settling time. */ |
AnnaBridge | 143:86740a56073b | 348 | /* Note: DAC channel startup time depends on board application environment: */ |
AnnaBridge | 143:86740a56073b | 349 | /* impedance connected to DAC channel output. */ |
AnnaBridge | 143:86740a56073b | 350 | /* The delay below is specified under conditions: */ |
AnnaBridge | 143:86740a56073b | 351 | /* - voltage maximum transition (lowest to highest value) */ |
AnnaBridge | 143:86740a56073b | 352 | /* - until voltage reaches final value +-1LSB */ |
AnnaBridge | 143:86740a56073b | 353 | /* - DAC channel output buffer enabled */ |
AnnaBridge | 143:86740a56073b | 354 | /* - load impedance of 5kOhm min, 50pF max */ |
AnnaBridge | 143:86740a56073b | 355 | /* Literal set to maximum value (refer to device datasheet, */ |
AnnaBridge | 143:86740a56073b | 356 | /* parameter "tSETTLING"). */ |
AnnaBridge | 143:86740a56073b | 357 | /* Unit: us */ |
AnnaBridge | 167:84c0a372a020 | 358 | #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */ |
AnnaBridge | 143:86740a56073b | 359 | /** |
AnnaBridge | 143:86740a56073b | 360 | * @} |
AnnaBridge | 143:86740a56073b | 361 | */ |
AnnaBridge | 143:86740a56073b | 362 | |
AnnaBridge | 143:86740a56073b | 363 | /** |
AnnaBridge | 143:86740a56073b | 364 | * @} |
AnnaBridge | 143:86740a56073b | 365 | */ |
AnnaBridge | 143:86740a56073b | 366 | |
AnnaBridge | 143:86740a56073b | 367 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 368 | /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros |
AnnaBridge | 143:86740a56073b | 369 | * @{ |
AnnaBridge | 143:86740a56073b | 370 | */ |
AnnaBridge | 143:86740a56073b | 371 | |
AnnaBridge | 143:86740a56073b | 372 | /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros |
AnnaBridge | 143:86740a56073b | 373 | * @{ |
AnnaBridge | 143:86740a56073b | 374 | */ |
AnnaBridge | 143:86740a56073b | 375 | |
AnnaBridge | 143:86740a56073b | 376 | /** |
AnnaBridge | 143:86740a56073b | 377 | * @brief Write a value in DAC register |
AnnaBridge | 143:86740a56073b | 378 | * @param __INSTANCE__ DAC Instance |
AnnaBridge | 143:86740a56073b | 379 | * @param __REG__ Register to be written |
AnnaBridge | 143:86740a56073b | 380 | * @param __VALUE__ Value to be written in the register |
AnnaBridge | 143:86740a56073b | 381 | * @retval None |
AnnaBridge | 143:86740a56073b | 382 | */ |
AnnaBridge | 143:86740a56073b | 383 | #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
AnnaBridge | 143:86740a56073b | 384 | |
AnnaBridge | 143:86740a56073b | 385 | /** |
AnnaBridge | 143:86740a56073b | 386 | * @brief Read a value in DAC register |
AnnaBridge | 143:86740a56073b | 387 | * @param __INSTANCE__ DAC Instance |
AnnaBridge | 143:86740a56073b | 388 | * @param __REG__ Register to be read |
AnnaBridge | 143:86740a56073b | 389 | * @retval Register value |
AnnaBridge | 143:86740a56073b | 390 | */ |
AnnaBridge | 143:86740a56073b | 391 | #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
AnnaBridge | 143:86740a56073b | 392 | |
AnnaBridge | 143:86740a56073b | 393 | /** |
AnnaBridge | 143:86740a56073b | 394 | * @} |
AnnaBridge | 143:86740a56073b | 395 | */ |
AnnaBridge | 143:86740a56073b | 396 | |
AnnaBridge | 143:86740a56073b | 397 | /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro |
AnnaBridge | 143:86740a56073b | 398 | * @{ |
AnnaBridge | 143:86740a56073b | 399 | */ |
AnnaBridge | 143:86740a56073b | 400 | |
AnnaBridge | 143:86740a56073b | 401 | /** |
AnnaBridge | 143:86740a56073b | 402 | * @brief Helper macro to get DAC channel number in decimal format |
AnnaBridge | 143:86740a56073b | 403 | * from literals LL_DAC_CHANNEL_x. |
AnnaBridge | 143:86740a56073b | 404 | * Example: |
AnnaBridge | 143:86740a56073b | 405 | * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) |
AnnaBridge | 143:86740a56073b | 406 | * will return decimal number "1". |
AnnaBridge | 143:86740a56073b | 407 | * @note The input can be a value from functions where a channel |
AnnaBridge | 143:86740a56073b | 408 | * number is returned. |
AnnaBridge | 143:86740a56073b | 409 | * @param __CHANNEL__ This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 410 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 411 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 412 | * |
AnnaBridge | 143:86740a56073b | 413 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 414 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 415 | * @retval 1...2 (value "2" depending on DAC channel 2 availability) |
AnnaBridge | 143:86740a56073b | 416 | */ |
AnnaBridge | 143:86740a56073b | 417 | #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ |
AnnaBridge | 143:86740a56073b | 418 | ((__CHANNEL__) & DAC_SWTR_CHX_MASK) |
AnnaBridge | 143:86740a56073b | 419 | |
AnnaBridge | 143:86740a56073b | 420 | /** |
AnnaBridge | 143:86740a56073b | 421 | * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x |
AnnaBridge | 143:86740a56073b | 422 | * from number in decimal format. |
AnnaBridge | 143:86740a56073b | 423 | * Example: |
AnnaBridge | 143:86740a56073b | 424 | * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) |
AnnaBridge | 143:86740a56073b | 425 | * will return a data equivalent to "LL_DAC_CHANNEL_1". |
AnnaBridge | 143:86740a56073b | 426 | * @note If the input parameter does not correspond to a DAC channel, |
AnnaBridge | 143:86740a56073b | 427 | * this macro returns value '0'. |
AnnaBridge | 143:86740a56073b | 428 | * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability) |
AnnaBridge | 143:86740a56073b | 429 | * @retval Returned value can be one of the following values: |
AnnaBridge | 143:86740a56073b | 430 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 431 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 432 | * |
AnnaBridge | 143:86740a56073b | 433 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 434 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 435 | */ |
AnnaBridge | 143:86740a56073b | 436 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 143:86740a56073b | 437 | #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ |
AnnaBridge | 143:86740a56073b | 438 | (((__DECIMAL_NB__) == 1U) \ |
AnnaBridge | 143:86740a56073b | 439 | ? ( \ |
AnnaBridge | 143:86740a56073b | 440 | LL_DAC_CHANNEL_1 \ |
AnnaBridge | 143:86740a56073b | 441 | ) \ |
AnnaBridge | 143:86740a56073b | 442 | : \ |
AnnaBridge | 143:86740a56073b | 443 | (((__DECIMAL_NB__) == 2U) \ |
AnnaBridge | 143:86740a56073b | 444 | ? ( \ |
AnnaBridge | 143:86740a56073b | 445 | LL_DAC_CHANNEL_2 \ |
AnnaBridge | 143:86740a56073b | 446 | ) \ |
AnnaBridge | 143:86740a56073b | 447 | : \ |
AnnaBridge | 143:86740a56073b | 448 | ( \ |
AnnaBridge | 143:86740a56073b | 449 | 0 \ |
AnnaBridge | 143:86740a56073b | 450 | ) \ |
AnnaBridge | 143:86740a56073b | 451 | ) \ |
AnnaBridge | 143:86740a56073b | 452 | ) |
AnnaBridge | 143:86740a56073b | 453 | #else |
AnnaBridge | 143:86740a56073b | 454 | #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ |
AnnaBridge | 143:86740a56073b | 455 | (((__DECIMAL_NB__) == 1U) \ |
AnnaBridge | 143:86740a56073b | 456 | ? ( \ |
AnnaBridge | 143:86740a56073b | 457 | LL_DAC_CHANNEL_1 \ |
AnnaBridge | 143:86740a56073b | 458 | ) \ |
AnnaBridge | 143:86740a56073b | 459 | : \ |
AnnaBridge | 143:86740a56073b | 460 | ( \ |
AnnaBridge | 143:86740a56073b | 461 | 0 \ |
AnnaBridge | 143:86740a56073b | 462 | ) \ |
AnnaBridge | 143:86740a56073b | 463 | ) |
AnnaBridge | 143:86740a56073b | 464 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 143:86740a56073b | 465 | |
AnnaBridge | 143:86740a56073b | 466 | /** |
AnnaBridge | 143:86740a56073b | 467 | * @brief Helper macro to define the DAC conversion data full-scale digital |
AnnaBridge | 143:86740a56073b | 468 | * value corresponding to the selected DAC resolution. |
AnnaBridge | 143:86740a56073b | 469 | * @note DAC conversion data full-scale corresponds to voltage range |
AnnaBridge | 143:86740a56073b | 470 | * determined by analog voltage references Vref+ and Vref- |
AnnaBridge | 143:86740a56073b | 471 | * (refer to reference manual). |
AnnaBridge | 143:86740a56073b | 472 | * @param __DAC_RESOLUTION__ This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 473 | * @arg @ref LL_DAC_RESOLUTION_12B |
AnnaBridge | 143:86740a56073b | 474 | * @arg @ref LL_DAC_RESOLUTION_8B |
AnnaBridge | 143:86740a56073b | 475 | * @retval ADC conversion data equivalent voltage value (unit: mVolt) |
AnnaBridge | 143:86740a56073b | 476 | */ |
AnnaBridge | 143:86740a56073b | 477 | #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ |
AnnaBridge | 167:84c0a372a020 | 478 | ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U)) |
AnnaBridge | 143:86740a56073b | 479 | |
AnnaBridge | 143:86740a56073b | 480 | /** |
AnnaBridge | 143:86740a56073b | 481 | * @brief Helper macro to calculate the DAC conversion data (unit: digital |
AnnaBridge | 143:86740a56073b | 482 | * value) corresponding to a voltage (unit: mVolt). |
AnnaBridge | 143:86740a56073b | 483 | * @note This helper macro is intended to provide input data in voltage |
AnnaBridge | 143:86740a56073b | 484 | * rather than digital value, |
AnnaBridge | 143:86740a56073b | 485 | * to be used with LL DAC functions such as |
AnnaBridge | 143:86740a56073b | 486 | * @ref LL_DAC_ConvertData12RightAligned(). |
AnnaBridge | 143:86740a56073b | 487 | * @note Analog reference voltage (Vref+) must be either known from |
AnnaBridge | 143:86740a56073b | 488 | * user board environment or can be calculated using ADC measurement |
AnnaBridge | 143:86740a56073b | 489 | * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). |
AnnaBridge | 143:86740a56073b | 490 | * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) |
AnnaBridge | 143:86740a56073b | 491 | * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel |
AnnaBridge | 143:86740a56073b | 492 | * (unit: mVolt). |
AnnaBridge | 143:86740a56073b | 493 | * @param __DAC_RESOLUTION__ This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 494 | * @arg @ref LL_DAC_RESOLUTION_12B |
AnnaBridge | 143:86740a56073b | 495 | * @arg @ref LL_DAC_RESOLUTION_8B |
AnnaBridge | 143:86740a56073b | 496 | * @retval DAC conversion data (unit: digital value) |
AnnaBridge | 143:86740a56073b | 497 | */ |
AnnaBridge | 143:86740a56073b | 498 | #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ |
AnnaBridge | 143:86740a56073b | 499 | __DAC_VOLTAGE__,\ |
AnnaBridge | 143:86740a56073b | 500 | __DAC_RESOLUTION__) \ |
AnnaBridge | 143:86740a56073b | 501 | ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ |
AnnaBridge | 143:86740a56073b | 502 | / (__VREFANALOG_VOLTAGE__) \ |
AnnaBridge | 143:86740a56073b | 503 | ) |
AnnaBridge | 143:86740a56073b | 504 | |
AnnaBridge | 143:86740a56073b | 505 | /** |
AnnaBridge | 143:86740a56073b | 506 | * @} |
AnnaBridge | 143:86740a56073b | 507 | */ |
AnnaBridge | 143:86740a56073b | 508 | |
AnnaBridge | 143:86740a56073b | 509 | /** |
AnnaBridge | 143:86740a56073b | 510 | * @} |
AnnaBridge | 143:86740a56073b | 511 | */ |
AnnaBridge | 143:86740a56073b | 512 | |
AnnaBridge | 143:86740a56073b | 513 | |
AnnaBridge | 143:86740a56073b | 514 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 515 | /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions |
AnnaBridge | 143:86740a56073b | 516 | * @{ |
AnnaBridge | 143:86740a56073b | 517 | */ |
AnnaBridge | 143:86740a56073b | 518 | /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels |
AnnaBridge | 143:86740a56073b | 519 | * @{ |
AnnaBridge | 143:86740a56073b | 520 | */ |
AnnaBridge | 143:86740a56073b | 521 | |
AnnaBridge | 143:86740a56073b | 522 | /** |
AnnaBridge | 143:86740a56073b | 523 | * @brief Set the conversion trigger source for the selected DAC channel. |
AnnaBridge | 143:86740a56073b | 524 | * @note For conversion trigger source to be effective, DAC trigger |
AnnaBridge | 143:86740a56073b | 525 | * must be enabled using function @ref LL_DAC_EnableTrigger(). |
AnnaBridge | 143:86740a56073b | 526 | * @note To set conversion trigger source, DAC channel must be disabled. |
AnnaBridge | 143:86740a56073b | 527 | * Otherwise, the setting is discarded. |
AnnaBridge | 143:86740a56073b | 528 | * @note Availability of parameters of trigger sources from timer |
AnnaBridge | 143:86740a56073b | 529 | * depends on timers availability on the selected device. |
AnnaBridge | 143:86740a56073b | 530 | * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n |
AnnaBridge | 143:86740a56073b | 531 | * CR TSEL2 LL_DAC_SetTriggerSource |
AnnaBridge | 143:86740a56073b | 532 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 533 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 534 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 535 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 536 | * |
AnnaBridge | 143:86740a56073b | 537 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 538 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 539 | * @param TriggerSource This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 540 | * @arg @ref LL_DAC_TRIG_SOFTWARE |
AnnaBridge | 143:86740a56073b | 541 | * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO |
AnnaBridge | 143:86740a56073b | 542 | * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO |
AnnaBridge | 143:86740a56073b | 543 | * @arg @ref LL_DAC_TRIG_EXT_TIM3_CH3 |
AnnaBridge | 143:86740a56073b | 544 | * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO |
AnnaBridge | 143:86740a56073b | 545 | * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO |
AnnaBridge | 143:86740a56073b | 546 | * @arg @ref LL_DAC_TRIG_EXT_TIM21_TRGO |
AnnaBridge | 143:86740a56073b | 547 | * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 |
AnnaBridge | 143:86740a56073b | 548 | * @retval None |
AnnaBridge | 143:86740a56073b | 549 | */ |
AnnaBridge | 143:86740a56073b | 550 | __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource) |
AnnaBridge | 143:86740a56073b | 551 | { |
AnnaBridge | 143:86740a56073b | 552 | MODIFY_REG(DACx->CR, |
AnnaBridge | 143:86740a56073b | 553 | DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
AnnaBridge | 143:86740a56073b | 554 | TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 143:86740a56073b | 555 | } |
AnnaBridge | 143:86740a56073b | 556 | |
AnnaBridge | 143:86740a56073b | 557 | /** |
AnnaBridge | 143:86740a56073b | 558 | * @brief Get the conversion trigger source for the selected DAC channel. |
AnnaBridge | 143:86740a56073b | 559 | * @note For conversion trigger source to be effective, DAC trigger |
AnnaBridge | 143:86740a56073b | 560 | * must be enabled using function @ref LL_DAC_EnableTrigger(). |
AnnaBridge | 143:86740a56073b | 561 | * @note Availability of parameters of trigger sources from timer |
AnnaBridge | 143:86740a56073b | 562 | * depends on timers availability on the selected device. |
AnnaBridge | 143:86740a56073b | 563 | * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n |
AnnaBridge | 143:86740a56073b | 564 | * CR TSEL2 LL_DAC_GetTriggerSource |
AnnaBridge | 143:86740a56073b | 565 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 566 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 567 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 568 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 569 | * |
AnnaBridge | 143:86740a56073b | 570 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 571 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 572 | * @retval Returned value can be one of the following values: |
AnnaBridge | 143:86740a56073b | 573 | * @arg @ref LL_DAC_TRIG_SOFTWARE |
AnnaBridge | 143:86740a56073b | 574 | * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO |
AnnaBridge | 143:86740a56073b | 575 | * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO |
AnnaBridge | 143:86740a56073b | 576 | * @arg @ref LL_DAC_TRIG_EXT_TIM3_CH3 |
AnnaBridge | 143:86740a56073b | 577 | * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO |
AnnaBridge | 143:86740a56073b | 578 | * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO |
AnnaBridge | 143:86740a56073b | 579 | * @arg @ref LL_DAC_TRIG_EXT_TIM21_TRGO |
AnnaBridge | 143:86740a56073b | 580 | * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 |
AnnaBridge | 143:86740a56073b | 581 | */ |
AnnaBridge | 143:86740a56073b | 582 | __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 143:86740a56073b | 583 | { |
AnnaBridge | 143:86740a56073b | 584 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 143:86740a56073b | 585 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
AnnaBridge | 143:86740a56073b | 586 | ); |
AnnaBridge | 143:86740a56073b | 587 | } |
AnnaBridge | 143:86740a56073b | 588 | |
AnnaBridge | 143:86740a56073b | 589 | /** |
AnnaBridge | 143:86740a56073b | 590 | * @brief Set the waveform automatic generation mode |
AnnaBridge | 143:86740a56073b | 591 | * for the selected DAC channel. |
AnnaBridge | 143:86740a56073b | 592 | * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n |
AnnaBridge | 143:86740a56073b | 593 | * CR WAVE2 LL_DAC_SetWaveAutoGeneration |
AnnaBridge | 143:86740a56073b | 594 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 595 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 596 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 597 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 598 | * |
AnnaBridge | 143:86740a56073b | 599 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 600 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 601 | * @param WaveAutoGeneration This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 602 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE |
AnnaBridge | 143:86740a56073b | 603 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE |
AnnaBridge | 143:86740a56073b | 604 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE |
AnnaBridge | 143:86740a56073b | 605 | * @retval None |
AnnaBridge | 143:86740a56073b | 606 | */ |
AnnaBridge | 143:86740a56073b | 607 | __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration) |
AnnaBridge | 143:86740a56073b | 608 | { |
AnnaBridge | 143:86740a56073b | 609 | MODIFY_REG(DACx->CR, |
AnnaBridge | 143:86740a56073b | 610 | DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
AnnaBridge | 143:86740a56073b | 611 | WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 143:86740a56073b | 612 | } |
AnnaBridge | 143:86740a56073b | 613 | |
AnnaBridge | 143:86740a56073b | 614 | /** |
AnnaBridge | 143:86740a56073b | 615 | * @brief Get the waveform automatic generation mode |
AnnaBridge | 143:86740a56073b | 616 | * for the selected DAC channel. |
AnnaBridge | 143:86740a56073b | 617 | * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n |
AnnaBridge | 143:86740a56073b | 618 | * CR WAVE2 LL_DAC_GetWaveAutoGeneration |
AnnaBridge | 143:86740a56073b | 619 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 620 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 621 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 622 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 623 | * |
AnnaBridge | 143:86740a56073b | 624 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 625 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 626 | * @retval Returned value can be one of the following values: |
AnnaBridge | 143:86740a56073b | 627 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE |
AnnaBridge | 143:86740a56073b | 628 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE |
AnnaBridge | 143:86740a56073b | 629 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE |
AnnaBridge | 143:86740a56073b | 630 | */ |
AnnaBridge | 143:86740a56073b | 631 | __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 143:86740a56073b | 632 | { |
AnnaBridge | 143:86740a56073b | 633 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 143:86740a56073b | 634 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
AnnaBridge | 143:86740a56073b | 635 | ); |
AnnaBridge | 143:86740a56073b | 636 | } |
AnnaBridge | 143:86740a56073b | 637 | |
AnnaBridge | 143:86740a56073b | 638 | /** |
AnnaBridge | 143:86740a56073b | 639 | * @brief Set the noise waveform generation for the selected DAC channel: |
AnnaBridge | 143:86740a56073b | 640 | * Noise mode and parameters LFSR (linear feedback shift register). |
AnnaBridge | 143:86740a56073b | 641 | * @note For wave generation to be effective, DAC channel |
AnnaBridge | 143:86740a56073b | 642 | * wave generation mode must be enabled using |
AnnaBridge | 143:86740a56073b | 643 | * function @ref LL_DAC_SetWaveAutoGeneration(). |
AnnaBridge | 143:86740a56073b | 644 | * @note This setting can be set when the selected DAC channel is disabled |
AnnaBridge | 143:86740a56073b | 645 | * (otherwise, the setting operation is ignored). |
AnnaBridge | 143:86740a56073b | 646 | * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n |
AnnaBridge | 143:86740a56073b | 647 | * CR MAMP2 LL_DAC_SetWaveNoiseLFSR |
AnnaBridge | 143:86740a56073b | 648 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 649 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 650 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 651 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 652 | * |
AnnaBridge | 143:86740a56073b | 653 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 654 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 655 | * @param NoiseLFSRMask This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 656 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 |
AnnaBridge | 143:86740a56073b | 657 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 |
AnnaBridge | 143:86740a56073b | 658 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 |
AnnaBridge | 143:86740a56073b | 659 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 |
AnnaBridge | 143:86740a56073b | 660 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 |
AnnaBridge | 143:86740a56073b | 661 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 |
AnnaBridge | 143:86740a56073b | 662 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 |
AnnaBridge | 143:86740a56073b | 663 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 |
AnnaBridge | 143:86740a56073b | 664 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 |
AnnaBridge | 143:86740a56073b | 665 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 |
AnnaBridge | 143:86740a56073b | 666 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 |
AnnaBridge | 143:86740a56073b | 667 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 |
AnnaBridge | 143:86740a56073b | 668 | * @retval None |
AnnaBridge | 143:86740a56073b | 669 | */ |
AnnaBridge | 143:86740a56073b | 670 | __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask) |
AnnaBridge | 143:86740a56073b | 671 | { |
AnnaBridge | 143:86740a56073b | 672 | MODIFY_REG(DACx->CR, |
AnnaBridge | 143:86740a56073b | 673 | DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
AnnaBridge | 143:86740a56073b | 674 | NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 143:86740a56073b | 675 | } |
AnnaBridge | 143:86740a56073b | 676 | |
AnnaBridge | 143:86740a56073b | 677 | /** |
AnnaBridge | 143:86740a56073b | 678 | * @brief Set the noise waveform generation for the selected DAC channel: |
AnnaBridge | 143:86740a56073b | 679 | * Noise mode and parameters LFSR (linear feedback shift register). |
AnnaBridge | 143:86740a56073b | 680 | * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n |
AnnaBridge | 143:86740a56073b | 681 | * CR MAMP2 LL_DAC_GetWaveNoiseLFSR |
AnnaBridge | 143:86740a56073b | 682 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 683 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 684 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 685 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 686 | * |
AnnaBridge | 143:86740a56073b | 687 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 688 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 689 | * @retval Returned value can be one of the following values: |
AnnaBridge | 143:86740a56073b | 690 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 |
AnnaBridge | 143:86740a56073b | 691 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 |
AnnaBridge | 143:86740a56073b | 692 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 |
AnnaBridge | 143:86740a56073b | 693 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 |
AnnaBridge | 143:86740a56073b | 694 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 |
AnnaBridge | 143:86740a56073b | 695 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 |
AnnaBridge | 143:86740a56073b | 696 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 |
AnnaBridge | 143:86740a56073b | 697 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 |
AnnaBridge | 143:86740a56073b | 698 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 |
AnnaBridge | 143:86740a56073b | 699 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 |
AnnaBridge | 143:86740a56073b | 700 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 |
AnnaBridge | 143:86740a56073b | 701 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 |
AnnaBridge | 143:86740a56073b | 702 | */ |
AnnaBridge | 143:86740a56073b | 703 | __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 143:86740a56073b | 704 | { |
AnnaBridge | 143:86740a56073b | 705 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 143:86740a56073b | 706 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
AnnaBridge | 143:86740a56073b | 707 | ); |
AnnaBridge | 143:86740a56073b | 708 | } |
AnnaBridge | 143:86740a56073b | 709 | |
AnnaBridge | 143:86740a56073b | 710 | /** |
AnnaBridge | 143:86740a56073b | 711 | * @brief Set the triangle waveform generation for the selected DAC channel: |
AnnaBridge | 143:86740a56073b | 712 | * triangle mode and amplitude. |
AnnaBridge | 143:86740a56073b | 713 | * @note For wave generation to be effective, DAC channel |
AnnaBridge | 143:86740a56073b | 714 | * wave generation mode must be enabled using |
AnnaBridge | 143:86740a56073b | 715 | * function @ref LL_DAC_SetWaveAutoGeneration(). |
AnnaBridge | 143:86740a56073b | 716 | * @note This setting can be set when the selected DAC channel is disabled |
AnnaBridge | 143:86740a56073b | 717 | * (otherwise, the setting operation is ignored). |
AnnaBridge | 143:86740a56073b | 718 | * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n |
AnnaBridge | 143:86740a56073b | 719 | * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude |
AnnaBridge | 143:86740a56073b | 720 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 721 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 722 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 723 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 724 | * |
AnnaBridge | 143:86740a56073b | 725 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 726 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 727 | * @param TriangleAmplitude This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 728 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 |
AnnaBridge | 143:86740a56073b | 729 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 |
AnnaBridge | 143:86740a56073b | 730 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 |
AnnaBridge | 143:86740a56073b | 731 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 |
AnnaBridge | 143:86740a56073b | 732 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 |
AnnaBridge | 143:86740a56073b | 733 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 |
AnnaBridge | 143:86740a56073b | 734 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 |
AnnaBridge | 143:86740a56073b | 735 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 |
AnnaBridge | 143:86740a56073b | 736 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 |
AnnaBridge | 143:86740a56073b | 737 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 |
AnnaBridge | 143:86740a56073b | 738 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 |
AnnaBridge | 143:86740a56073b | 739 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 |
AnnaBridge | 143:86740a56073b | 740 | * @retval None |
AnnaBridge | 143:86740a56073b | 741 | */ |
AnnaBridge | 143:86740a56073b | 742 | __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude) |
AnnaBridge | 143:86740a56073b | 743 | { |
AnnaBridge | 143:86740a56073b | 744 | MODIFY_REG(DACx->CR, |
AnnaBridge | 143:86740a56073b | 745 | DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
AnnaBridge | 143:86740a56073b | 746 | TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 143:86740a56073b | 747 | } |
AnnaBridge | 143:86740a56073b | 748 | |
AnnaBridge | 143:86740a56073b | 749 | /** |
AnnaBridge | 143:86740a56073b | 750 | * @brief Set the triangle waveform generation for the selected DAC channel: |
AnnaBridge | 143:86740a56073b | 751 | * triangle mode and amplitude. |
AnnaBridge | 143:86740a56073b | 752 | * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n |
AnnaBridge | 143:86740a56073b | 753 | * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude |
AnnaBridge | 143:86740a56073b | 754 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 755 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 756 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 757 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 758 | * |
AnnaBridge | 143:86740a56073b | 759 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 760 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 761 | * @retval Returned value can be one of the following values: |
AnnaBridge | 143:86740a56073b | 762 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 |
AnnaBridge | 143:86740a56073b | 763 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 |
AnnaBridge | 143:86740a56073b | 764 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 |
AnnaBridge | 143:86740a56073b | 765 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 |
AnnaBridge | 143:86740a56073b | 766 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 |
AnnaBridge | 143:86740a56073b | 767 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 |
AnnaBridge | 143:86740a56073b | 768 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 |
AnnaBridge | 143:86740a56073b | 769 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 |
AnnaBridge | 143:86740a56073b | 770 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 |
AnnaBridge | 143:86740a56073b | 771 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 |
AnnaBridge | 143:86740a56073b | 772 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 |
AnnaBridge | 143:86740a56073b | 773 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 |
AnnaBridge | 143:86740a56073b | 774 | */ |
AnnaBridge | 143:86740a56073b | 775 | __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 143:86740a56073b | 776 | { |
AnnaBridge | 143:86740a56073b | 777 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 143:86740a56073b | 778 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
AnnaBridge | 143:86740a56073b | 779 | ); |
AnnaBridge | 143:86740a56073b | 780 | } |
AnnaBridge | 143:86740a56073b | 781 | |
AnnaBridge | 143:86740a56073b | 782 | /** |
AnnaBridge | 143:86740a56073b | 783 | * @brief Set the output buffer for the selected DAC channel. |
AnnaBridge | 143:86740a56073b | 784 | * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n |
AnnaBridge | 143:86740a56073b | 785 | * CR BOFF2 LL_DAC_SetOutputBuffer |
AnnaBridge | 143:86740a56073b | 786 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 787 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 788 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 789 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 790 | * |
AnnaBridge | 143:86740a56073b | 791 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 792 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 793 | * @param OutputBuffer This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 794 | * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE |
AnnaBridge | 143:86740a56073b | 795 | * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE |
AnnaBridge | 143:86740a56073b | 796 | * @retval None |
AnnaBridge | 143:86740a56073b | 797 | */ |
AnnaBridge | 143:86740a56073b | 798 | __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer) |
AnnaBridge | 143:86740a56073b | 799 | { |
AnnaBridge | 143:86740a56073b | 800 | MODIFY_REG(DACx->CR, |
AnnaBridge | 143:86740a56073b | 801 | DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
AnnaBridge | 143:86740a56073b | 802 | OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 143:86740a56073b | 803 | } |
AnnaBridge | 143:86740a56073b | 804 | |
AnnaBridge | 143:86740a56073b | 805 | /** |
AnnaBridge | 143:86740a56073b | 806 | * @brief Get the output buffer state for the selected DAC channel. |
AnnaBridge | 143:86740a56073b | 807 | * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n |
AnnaBridge | 143:86740a56073b | 808 | * CR BOFF2 LL_DAC_GetOutputBuffer |
AnnaBridge | 143:86740a56073b | 809 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 810 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 811 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 812 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 813 | * |
AnnaBridge | 143:86740a56073b | 814 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 815 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 816 | * @retval Returned value can be one of the following values: |
AnnaBridge | 143:86740a56073b | 817 | * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE |
AnnaBridge | 143:86740a56073b | 818 | * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE |
AnnaBridge | 143:86740a56073b | 819 | */ |
AnnaBridge | 143:86740a56073b | 820 | __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 143:86740a56073b | 821 | { |
AnnaBridge | 143:86740a56073b | 822 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 143:86740a56073b | 823 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
AnnaBridge | 143:86740a56073b | 824 | ); |
AnnaBridge | 143:86740a56073b | 825 | } |
AnnaBridge | 143:86740a56073b | 826 | |
AnnaBridge | 143:86740a56073b | 827 | /** |
AnnaBridge | 143:86740a56073b | 828 | * @} |
AnnaBridge | 143:86740a56073b | 829 | */ |
AnnaBridge | 143:86740a56073b | 830 | |
AnnaBridge | 143:86740a56073b | 831 | /** @defgroup DAC_LL_EF_DMA_Management DMA Management |
AnnaBridge | 143:86740a56073b | 832 | * @{ |
AnnaBridge | 143:86740a56073b | 833 | */ |
AnnaBridge | 143:86740a56073b | 834 | |
AnnaBridge | 143:86740a56073b | 835 | /** |
AnnaBridge | 143:86740a56073b | 836 | * @brief Enable DAC DMA transfer request of the selected channel. |
AnnaBridge | 143:86740a56073b | 837 | * @note To configure DMA source address (peripheral address), |
AnnaBridge | 143:86740a56073b | 838 | * use function @ref LL_DAC_DMA_GetRegAddr(). |
AnnaBridge | 143:86740a56073b | 839 | * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n |
AnnaBridge | 143:86740a56073b | 840 | * CR DMAEN2 LL_DAC_EnableDMAReq |
AnnaBridge | 143:86740a56073b | 841 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 842 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 843 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 844 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 845 | * |
AnnaBridge | 143:86740a56073b | 846 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 847 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 848 | * @retval None |
AnnaBridge | 143:86740a56073b | 849 | */ |
AnnaBridge | 143:86740a56073b | 850 | __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 143:86740a56073b | 851 | { |
AnnaBridge | 143:86740a56073b | 852 | SET_BIT(DACx->CR, |
AnnaBridge | 143:86740a56073b | 853 | DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 143:86740a56073b | 854 | } |
AnnaBridge | 143:86740a56073b | 855 | |
AnnaBridge | 143:86740a56073b | 856 | /** |
AnnaBridge | 143:86740a56073b | 857 | * @brief Disable DAC DMA transfer request of the selected channel. |
AnnaBridge | 143:86740a56073b | 858 | * @note To configure DMA source address (peripheral address), |
AnnaBridge | 143:86740a56073b | 859 | * use function @ref LL_DAC_DMA_GetRegAddr(). |
AnnaBridge | 143:86740a56073b | 860 | * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n |
AnnaBridge | 143:86740a56073b | 861 | * CR DMAEN2 LL_DAC_DisableDMAReq |
AnnaBridge | 143:86740a56073b | 862 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 863 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 864 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 865 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 866 | * |
AnnaBridge | 143:86740a56073b | 867 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 868 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 869 | * @retval None |
AnnaBridge | 143:86740a56073b | 870 | */ |
AnnaBridge | 143:86740a56073b | 871 | __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 143:86740a56073b | 872 | { |
AnnaBridge | 143:86740a56073b | 873 | CLEAR_BIT(DACx->CR, |
AnnaBridge | 143:86740a56073b | 874 | DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 143:86740a56073b | 875 | } |
AnnaBridge | 143:86740a56073b | 876 | |
AnnaBridge | 143:86740a56073b | 877 | /** |
AnnaBridge | 143:86740a56073b | 878 | * @brief Get DAC DMA transfer request state of the selected channel. |
AnnaBridge | 143:86740a56073b | 879 | * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled) |
AnnaBridge | 143:86740a56073b | 880 | * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n |
AnnaBridge | 143:86740a56073b | 881 | * CR DMAEN2 LL_DAC_IsDMAReqEnabled |
AnnaBridge | 143:86740a56073b | 882 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 883 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 884 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 885 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 886 | * |
AnnaBridge | 143:86740a56073b | 887 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 888 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 889 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 890 | */ |
AnnaBridge | 143:86740a56073b | 891 | __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 143:86740a56073b | 892 | { |
AnnaBridge | 143:86740a56073b | 893 | return (READ_BIT(DACx->CR, |
AnnaBridge | 143:86740a56073b | 894 | DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 143:86740a56073b | 895 | == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); |
AnnaBridge | 143:86740a56073b | 896 | } |
AnnaBridge | 143:86740a56073b | 897 | |
AnnaBridge | 143:86740a56073b | 898 | /** |
AnnaBridge | 143:86740a56073b | 899 | * @brief Function to help to configure DMA transfer to DAC: retrieve the |
AnnaBridge | 143:86740a56073b | 900 | * DAC register address from DAC instance and a list of DAC registers |
AnnaBridge | 143:86740a56073b | 901 | * intended to be used (most commonly) with DMA transfer. |
AnnaBridge | 143:86740a56073b | 902 | * @note These DAC registers are data holding registers: |
AnnaBridge | 143:86740a56073b | 903 | * when DAC conversion is requested, DAC generates a DMA transfer |
AnnaBridge | 143:86740a56073b | 904 | * request to have data available in DAC data holding registers. |
AnnaBridge | 143:86740a56073b | 905 | * @note This macro is intended to be used with LL DMA driver, refer to |
AnnaBridge | 143:86740a56073b | 906 | * function "LL_DMA_ConfigAddresses()". |
AnnaBridge | 143:86740a56073b | 907 | * Example: |
AnnaBridge | 143:86740a56073b | 908 | * LL_DMA_ConfigAddresses(DMA1, |
AnnaBridge | 143:86740a56073b | 909 | * LL_DMA_CHANNEL_1, |
AnnaBridge | 143:86740a56073b | 910 | * (uint32_t)&< array or variable >, |
AnnaBridge | 143:86740a56073b | 911 | * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), |
AnnaBridge | 143:86740a56073b | 912 | * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); |
AnnaBridge | 143:86740a56073b | 913 | * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n |
AnnaBridge | 143:86740a56073b | 914 | * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n |
AnnaBridge | 143:86740a56073b | 915 | * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n |
AnnaBridge | 143:86740a56073b | 916 | * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n |
AnnaBridge | 143:86740a56073b | 917 | * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n |
AnnaBridge | 143:86740a56073b | 918 | * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr |
AnnaBridge | 143:86740a56073b | 919 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 920 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 921 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 922 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 923 | * |
AnnaBridge | 143:86740a56073b | 924 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 925 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 926 | * @param Register This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 927 | * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED |
AnnaBridge | 143:86740a56073b | 928 | * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED |
AnnaBridge | 143:86740a56073b | 929 | * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED |
AnnaBridge | 143:86740a56073b | 930 | * @retval DAC register address |
AnnaBridge | 143:86740a56073b | 931 | */ |
AnnaBridge | 143:86740a56073b | 932 | __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) |
AnnaBridge | 143:86740a56073b | 933 | { |
AnnaBridge | 143:86740a56073b | 934 | /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ |
AnnaBridge | 143:86740a56073b | 935 | /* DAC channel selected. */ |
AnnaBridge | 143:86740a56073b | 936 | return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> Register) & DAC_REG_REGOFFSET_MASK_POSBIT0)))); |
AnnaBridge | 143:86740a56073b | 937 | } |
AnnaBridge | 143:86740a56073b | 938 | /** |
AnnaBridge | 143:86740a56073b | 939 | * @} |
AnnaBridge | 143:86740a56073b | 940 | */ |
AnnaBridge | 143:86740a56073b | 941 | |
AnnaBridge | 143:86740a56073b | 942 | /** @defgroup DAC_LL_EF_Operation Operation on DAC channels |
AnnaBridge | 143:86740a56073b | 943 | * @{ |
AnnaBridge | 143:86740a56073b | 944 | */ |
AnnaBridge | 143:86740a56073b | 945 | |
AnnaBridge | 143:86740a56073b | 946 | /** |
AnnaBridge | 143:86740a56073b | 947 | * @brief Enable DAC selected channel. |
AnnaBridge | 143:86740a56073b | 948 | * @rmtoll CR EN1 LL_DAC_Enable\n |
AnnaBridge | 143:86740a56073b | 949 | * CR EN2 LL_DAC_Enable |
AnnaBridge | 143:86740a56073b | 950 | * @note After enable from off state, DAC channel requires a delay |
AnnaBridge | 143:86740a56073b | 951 | * for output voltage to reach accuracy +/- 1 LSB. |
AnnaBridge | 143:86740a56073b | 952 | * Refer to device datasheet, parameter "tWAKEUP". |
AnnaBridge | 143:86740a56073b | 953 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 954 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 955 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 956 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 957 | * |
AnnaBridge | 143:86740a56073b | 958 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 959 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 960 | * @retval None |
AnnaBridge | 143:86740a56073b | 961 | */ |
AnnaBridge | 143:86740a56073b | 962 | __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 143:86740a56073b | 963 | { |
AnnaBridge | 143:86740a56073b | 964 | SET_BIT(DACx->CR, |
AnnaBridge | 143:86740a56073b | 965 | DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 143:86740a56073b | 966 | } |
AnnaBridge | 143:86740a56073b | 967 | |
AnnaBridge | 143:86740a56073b | 968 | /** |
AnnaBridge | 143:86740a56073b | 969 | * @brief Disable DAC selected channel. |
AnnaBridge | 143:86740a56073b | 970 | * @rmtoll CR EN1 LL_DAC_Disable\n |
AnnaBridge | 143:86740a56073b | 971 | * CR EN2 LL_DAC_Disable |
AnnaBridge | 143:86740a56073b | 972 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 973 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 974 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 975 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 976 | * |
AnnaBridge | 143:86740a56073b | 977 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 978 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 979 | * @retval None |
AnnaBridge | 143:86740a56073b | 980 | */ |
AnnaBridge | 143:86740a56073b | 981 | __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 143:86740a56073b | 982 | { |
AnnaBridge | 143:86740a56073b | 983 | CLEAR_BIT(DACx->CR, |
AnnaBridge | 143:86740a56073b | 984 | DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 143:86740a56073b | 985 | } |
AnnaBridge | 143:86740a56073b | 986 | |
AnnaBridge | 143:86740a56073b | 987 | /** |
AnnaBridge | 143:86740a56073b | 988 | * @brief Get DAC enable state of the selected channel. |
AnnaBridge | 143:86740a56073b | 989 | * (0: DAC channel is disabled, 1: DAC channel is enabled) |
AnnaBridge | 143:86740a56073b | 990 | * @rmtoll CR EN1 LL_DAC_IsEnabled\n |
AnnaBridge | 143:86740a56073b | 991 | * CR EN2 LL_DAC_IsEnabled |
AnnaBridge | 143:86740a56073b | 992 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 993 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 994 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 995 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 996 | * |
AnnaBridge | 143:86740a56073b | 997 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 998 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 999 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 1000 | */ |
AnnaBridge | 143:86740a56073b | 1001 | __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 143:86740a56073b | 1002 | { |
AnnaBridge | 143:86740a56073b | 1003 | return (READ_BIT(DACx->CR, |
AnnaBridge | 143:86740a56073b | 1004 | DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 143:86740a56073b | 1005 | == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); |
AnnaBridge | 143:86740a56073b | 1006 | } |
AnnaBridge | 143:86740a56073b | 1007 | |
AnnaBridge | 143:86740a56073b | 1008 | /** |
AnnaBridge | 143:86740a56073b | 1009 | * @brief Enable DAC trigger of the selected channel. |
AnnaBridge | 143:86740a56073b | 1010 | * @note - If DAC trigger is disabled, DAC conversion is performed |
AnnaBridge | 143:86740a56073b | 1011 | * automatically once the data holding register is updated, |
AnnaBridge | 143:86740a56073b | 1012 | * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": |
AnnaBridge | 143:86740a56073b | 1013 | * @ref LL_DAC_ConvertData12RightAligned(), ... |
AnnaBridge | 143:86740a56073b | 1014 | * - If DAC trigger is enabled, DAC conversion is performed |
AnnaBridge | 143:86740a56073b | 1015 | * only when a hardware of software trigger event is occurring. |
AnnaBridge | 143:86740a56073b | 1016 | * Select trigger source using |
AnnaBridge | 143:86740a56073b | 1017 | * function @ref LL_DAC_SetTriggerSource(). |
AnnaBridge | 143:86740a56073b | 1018 | * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n |
AnnaBridge | 143:86740a56073b | 1019 | * CR TEN2 LL_DAC_EnableTrigger |
AnnaBridge | 143:86740a56073b | 1020 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 1021 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1022 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 1023 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 1024 | * |
AnnaBridge | 143:86740a56073b | 1025 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 1026 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 1027 | * @retval None |
AnnaBridge | 143:86740a56073b | 1028 | */ |
AnnaBridge | 143:86740a56073b | 1029 | __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 143:86740a56073b | 1030 | { |
AnnaBridge | 143:86740a56073b | 1031 | SET_BIT(DACx->CR, |
AnnaBridge | 143:86740a56073b | 1032 | DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 143:86740a56073b | 1033 | } |
AnnaBridge | 143:86740a56073b | 1034 | |
AnnaBridge | 143:86740a56073b | 1035 | /** |
AnnaBridge | 143:86740a56073b | 1036 | * @brief Disable DAC trigger of the selected channel. |
AnnaBridge | 143:86740a56073b | 1037 | * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n |
AnnaBridge | 143:86740a56073b | 1038 | * CR TEN2 LL_DAC_DisableTrigger |
AnnaBridge | 143:86740a56073b | 1039 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 1040 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1041 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 1042 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 1043 | * |
AnnaBridge | 143:86740a56073b | 1044 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 1045 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 1046 | * @retval None |
AnnaBridge | 143:86740a56073b | 1047 | */ |
AnnaBridge | 143:86740a56073b | 1048 | __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 143:86740a56073b | 1049 | { |
AnnaBridge | 143:86740a56073b | 1050 | CLEAR_BIT(DACx->CR, |
AnnaBridge | 143:86740a56073b | 1051 | DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 143:86740a56073b | 1052 | } |
AnnaBridge | 143:86740a56073b | 1053 | |
AnnaBridge | 143:86740a56073b | 1054 | /** |
AnnaBridge | 143:86740a56073b | 1055 | * @brief Get DAC trigger state of the selected channel. |
AnnaBridge | 143:86740a56073b | 1056 | * (0: DAC trigger is disabled, 1: DAC trigger is enabled) |
AnnaBridge | 143:86740a56073b | 1057 | * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n |
AnnaBridge | 143:86740a56073b | 1058 | * CR TEN2 LL_DAC_IsTriggerEnabled |
AnnaBridge | 143:86740a56073b | 1059 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 1060 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1061 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 1062 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 1063 | * |
AnnaBridge | 143:86740a56073b | 1064 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 1065 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 1066 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 1067 | */ |
AnnaBridge | 143:86740a56073b | 1068 | __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 143:86740a56073b | 1069 | { |
AnnaBridge | 143:86740a56073b | 1070 | return (READ_BIT(DACx->CR, |
AnnaBridge | 143:86740a56073b | 1071 | DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 143:86740a56073b | 1072 | == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); |
AnnaBridge | 143:86740a56073b | 1073 | } |
AnnaBridge | 143:86740a56073b | 1074 | |
AnnaBridge | 143:86740a56073b | 1075 | /** |
AnnaBridge | 143:86740a56073b | 1076 | * @brief Trig DAC conversion by software for the selected DAC channel. |
AnnaBridge | 143:86740a56073b | 1077 | * @note Preliminarily, DAC trigger must be set to software trigger |
AnnaBridge | 143:86740a56073b | 1078 | * using function @ref LL_DAC_SetTriggerSource() |
AnnaBridge | 143:86740a56073b | 1079 | * with parameter "LL_DAC_TRIGGER_SOFTWARE". |
AnnaBridge | 143:86740a56073b | 1080 | * and DAC trigger must be enabled using |
AnnaBridge | 143:86740a56073b | 1081 | * function @ref LL_DAC_EnableTrigger(). |
AnnaBridge | 143:86740a56073b | 1082 | * @note For devices featuring DAC with 2 channels: this function |
AnnaBridge | 143:86740a56073b | 1083 | * can perform a SW start of both DAC channels simultaneously. |
AnnaBridge | 143:86740a56073b | 1084 | * Two channels can be selected as parameter. |
AnnaBridge | 143:86740a56073b | 1085 | * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2) |
AnnaBridge | 143:86740a56073b | 1086 | * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n |
AnnaBridge | 143:86740a56073b | 1087 | * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion |
AnnaBridge | 143:86740a56073b | 1088 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 1089 | * @param DAC_Channel This parameter can a combination of the following values: |
AnnaBridge | 143:86740a56073b | 1090 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 1091 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 1092 | * |
AnnaBridge | 143:86740a56073b | 1093 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 1094 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 1095 | * @retval None |
AnnaBridge | 143:86740a56073b | 1096 | */ |
AnnaBridge | 143:86740a56073b | 1097 | __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 143:86740a56073b | 1098 | { |
AnnaBridge | 143:86740a56073b | 1099 | SET_BIT(DACx->SWTRIGR, |
AnnaBridge | 143:86740a56073b | 1100 | (DAC_Channel & DAC_SWTR_CHX_MASK)); |
AnnaBridge | 143:86740a56073b | 1101 | } |
AnnaBridge | 143:86740a56073b | 1102 | |
AnnaBridge | 143:86740a56073b | 1103 | /** |
AnnaBridge | 143:86740a56073b | 1104 | * @brief Set the data to be loaded in the data holding register |
AnnaBridge | 143:86740a56073b | 1105 | * in format 12 bits left alignment (LSB aligned on bit 0), |
AnnaBridge | 143:86740a56073b | 1106 | * for the selected DAC channel. |
AnnaBridge | 143:86740a56073b | 1107 | * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n |
AnnaBridge | 143:86740a56073b | 1108 | * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned |
AnnaBridge | 143:86740a56073b | 1109 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 1110 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1111 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 1112 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 1113 | * |
AnnaBridge | 143:86740a56073b | 1114 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 1115 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 1116 | * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF |
AnnaBridge | 143:86740a56073b | 1117 | * @retval None |
AnnaBridge | 143:86740a56073b | 1118 | */ |
AnnaBridge | 143:86740a56073b | 1119 | __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) |
AnnaBridge | 143:86740a56073b | 1120 | { |
AnnaBridge | 143:86740a56073b | 1121 | register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0); |
AnnaBridge | 143:86740a56073b | 1122 | |
AnnaBridge | 143:86740a56073b | 1123 | MODIFY_REG(*preg, |
AnnaBridge | 143:86740a56073b | 1124 | DAC_DHR12R1_DACC1DHR, |
AnnaBridge | 143:86740a56073b | 1125 | Data); |
AnnaBridge | 143:86740a56073b | 1126 | } |
AnnaBridge | 143:86740a56073b | 1127 | |
AnnaBridge | 143:86740a56073b | 1128 | /** |
AnnaBridge | 143:86740a56073b | 1129 | * @brief Set the data to be loaded in the data holding register |
AnnaBridge | 143:86740a56073b | 1130 | * in format 12 bits left alignment (MSB aligned on bit 15), |
AnnaBridge | 143:86740a56073b | 1131 | * for the selected DAC channel. |
AnnaBridge | 143:86740a56073b | 1132 | * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n |
AnnaBridge | 143:86740a56073b | 1133 | * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned |
AnnaBridge | 143:86740a56073b | 1134 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 1135 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1136 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 1137 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 1138 | * |
AnnaBridge | 143:86740a56073b | 1139 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 1140 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 1141 | * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF |
AnnaBridge | 143:86740a56073b | 1142 | * @retval None |
AnnaBridge | 143:86740a56073b | 1143 | */ |
AnnaBridge | 143:86740a56073b | 1144 | __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) |
AnnaBridge | 143:86740a56073b | 1145 | { |
AnnaBridge | 143:86740a56073b | 1146 | register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0); |
AnnaBridge | 143:86740a56073b | 1147 | |
AnnaBridge | 143:86740a56073b | 1148 | MODIFY_REG(*preg, |
AnnaBridge | 143:86740a56073b | 1149 | DAC_DHR12L1_DACC1DHR, |
AnnaBridge | 143:86740a56073b | 1150 | Data); |
AnnaBridge | 143:86740a56073b | 1151 | } |
AnnaBridge | 143:86740a56073b | 1152 | |
AnnaBridge | 143:86740a56073b | 1153 | /** |
AnnaBridge | 143:86740a56073b | 1154 | * @brief Set the data to be loaded in the data holding register |
AnnaBridge | 143:86740a56073b | 1155 | * in format 8 bits left alignment (LSB aligned on bit 0), |
AnnaBridge | 143:86740a56073b | 1156 | * for the selected DAC channel. |
AnnaBridge | 143:86740a56073b | 1157 | * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n |
AnnaBridge | 143:86740a56073b | 1158 | * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned |
AnnaBridge | 143:86740a56073b | 1159 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 1160 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1161 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 1162 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 1163 | * |
AnnaBridge | 143:86740a56073b | 1164 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 1165 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 1166 | * @param Data Value between Min_Data=0x00 and Max_Data=0xFF |
AnnaBridge | 143:86740a56073b | 1167 | * @retval None |
AnnaBridge | 143:86740a56073b | 1168 | */ |
AnnaBridge | 143:86740a56073b | 1169 | __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) |
AnnaBridge | 143:86740a56073b | 1170 | { |
AnnaBridge | 143:86740a56073b | 1171 | register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0); |
AnnaBridge | 143:86740a56073b | 1172 | |
AnnaBridge | 143:86740a56073b | 1173 | MODIFY_REG(*preg, |
AnnaBridge | 143:86740a56073b | 1174 | DAC_DHR8R1_DACC1DHR, |
AnnaBridge | 143:86740a56073b | 1175 | Data); |
AnnaBridge | 143:86740a56073b | 1176 | } |
AnnaBridge | 143:86740a56073b | 1177 | |
AnnaBridge | 143:86740a56073b | 1178 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 143:86740a56073b | 1179 | /** |
AnnaBridge | 143:86740a56073b | 1180 | * @brief Set the data to be loaded in the data holding register |
AnnaBridge | 143:86740a56073b | 1181 | * in format 12 bits left alignment (LSB aligned on bit 0), |
AnnaBridge | 143:86740a56073b | 1182 | * for both DAC channels. |
AnnaBridge | 143:86740a56073b | 1183 | * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n |
AnnaBridge | 143:86740a56073b | 1184 | * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned |
AnnaBridge | 143:86740a56073b | 1185 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 1186 | * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF |
AnnaBridge | 143:86740a56073b | 1187 | * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF |
AnnaBridge | 143:86740a56073b | 1188 | * @retval None |
AnnaBridge | 143:86740a56073b | 1189 | */ |
AnnaBridge | 143:86740a56073b | 1190 | __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) |
AnnaBridge | 143:86740a56073b | 1191 | { |
AnnaBridge | 143:86740a56073b | 1192 | MODIFY_REG(DACx->DHR12RD, |
AnnaBridge | 143:86740a56073b | 1193 | (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), |
AnnaBridge | 143:86740a56073b | 1194 | ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); |
AnnaBridge | 143:86740a56073b | 1195 | } |
AnnaBridge | 143:86740a56073b | 1196 | |
AnnaBridge | 143:86740a56073b | 1197 | /** |
AnnaBridge | 143:86740a56073b | 1198 | * @brief Set the data to be loaded in the data holding register |
AnnaBridge | 143:86740a56073b | 1199 | * in format 12 bits left alignment (MSB aligned on bit 15), |
AnnaBridge | 143:86740a56073b | 1200 | * for both DAC channels. |
AnnaBridge | 143:86740a56073b | 1201 | * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n |
AnnaBridge | 143:86740a56073b | 1202 | * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned |
AnnaBridge | 143:86740a56073b | 1203 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 1204 | * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF |
AnnaBridge | 143:86740a56073b | 1205 | * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF |
AnnaBridge | 143:86740a56073b | 1206 | * @retval None |
AnnaBridge | 143:86740a56073b | 1207 | */ |
AnnaBridge | 143:86740a56073b | 1208 | __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) |
AnnaBridge | 143:86740a56073b | 1209 | { |
AnnaBridge | 143:86740a56073b | 1210 | /* Note: Data of DAC channel 2 shift value subtracted of 4 because */ |
AnnaBridge | 143:86740a56073b | 1211 | /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */ |
AnnaBridge | 143:86740a56073b | 1212 | /* the 4 LSB must be taken into account for the shift value. */ |
AnnaBridge | 143:86740a56073b | 1213 | MODIFY_REG(DACx->DHR12LD, |
AnnaBridge | 143:86740a56073b | 1214 | (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR), |
AnnaBridge | 143:86740a56073b | 1215 | ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1)); |
AnnaBridge | 143:86740a56073b | 1216 | } |
AnnaBridge | 143:86740a56073b | 1217 | |
AnnaBridge | 143:86740a56073b | 1218 | /** |
AnnaBridge | 143:86740a56073b | 1219 | * @brief Set the data to be loaded in the data holding register |
AnnaBridge | 143:86740a56073b | 1220 | * in format 8 bits left alignment (LSB aligned on bit 0), |
AnnaBridge | 143:86740a56073b | 1221 | * for both DAC channels. |
AnnaBridge | 143:86740a56073b | 1222 | * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n |
AnnaBridge | 143:86740a56073b | 1223 | * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned |
AnnaBridge | 143:86740a56073b | 1224 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 1225 | * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF |
AnnaBridge | 143:86740a56073b | 1226 | * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF |
AnnaBridge | 143:86740a56073b | 1227 | * @retval None |
AnnaBridge | 143:86740a56073b | 1228 | */ |
AnnaBridge | 143:86740a56073b | 1229 | __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) |
AnnaBridge | 143:86740a56073b | 1230 | { |
AnnaBridge | 143:86740a56073b | 1231 | MODIFY_REG(DACx->DHR8RD, |
AnnaBridge | 143:86740a56073b | 1232 | (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), |
AnnaBridge | 143:86740a56073b | 1233 | ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); |
AnnaBridge | 143:86740a56073b | 1234 | } |
AnnaBridge | 143:86740a56073b | 1235 | |
AnnaBridge | 143:86740a56073b | 1236 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 143:86740a56073b | 1237 | /** |
AnnaBridge | 143:86740a56073b | 1238 | * @brief Retrieve output data currently generated for the selected DAC channel. |
AnnaBridge | 143:86740a56073b | 1239 | * @note Whatever alignment and resolution settings |
AnnaBridge | 143:86740a56073b | 1240 | * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": |
AnnaBridge | 143:86740a56073b | 1241 | * @ref LL_DAC_ConvertData12RightAligned(), ...), |
AnnaBridge | 143:86740a56073b | 1242 | * output data format is 12 bits right aligned (LSB aligned on bit 0). |
AnnaBridge | 143:86740a56073b | 1243 | * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n |
AnnaBridge | 143:86740a56073b | 1244 | * DOR2 DACC2DOR LL_DAC_RetrieveOutputData |
AnnaBridge | 143:86740a56073b | 1245 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 1246 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1247 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 143:86740a56073b | 1248 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 143:86740a56073b | 1249 | * |
AnnaBridge | 143:86740a56073b | 1250 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 143:86740a56073b | 1251 | * Refer to device datasheet for channels availability. |
AnnaBridge | 143:86740a56073b | 1252 | * @retval Value between Min_Data=0x000 and Max_Data=0xFFF |
AnnaBridge | 143:86740a56073b | 1253 | */ |
AnnaBridge | 143:86740a56073b | 1254 | __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 143:86740a56073b | 1255 | { |
AnnaBridge | 143:86740a56073b | 1256 | register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0); |
AnnaBridge | 143:86740a56073b | 1257 | |
AnnaBridge | 143:86740a56073b | 1258 | return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); |
AnnaBridge | 143:86740a56073b | 1259 | } |
AnnaBridge | 143:86740a56073b | 1260 | |
AnnaBridge | 143:86740a56073b | 1261 | /** |
AnnaBridge | 143:86740a56073b | 1262 | * @} |
AnnaBridge | 143:86740a56073b | 1263 | */ |
AnnaBridge | 143:86740a56073b | 1264 | |
AnnaBridge | 143:86740a56073b | 1265 | /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management |
AnnaBridge | 143:86740a56073b | 1266 | * @{ |
AnnaBridge | 143:86740a56073b | 1267 | */ |
AnnaBridge | 143:86740a56073b | 1268 | /** |
AnnaBridge | 143:86740a56073b | 1269 | * @brief Get DAC underrun flag for DAC channel 1 |
AnnaBridge | 143:86740a56073b | 1270 | * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 |
AnnaBridge | 143:86740a56073b | 1271 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 1272 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 1273 | */ |
AnnaBridge | 143:86740a56073b | 1274 | __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) |
AnnaBridge | 143:86740a56073b | 1275 | { |
AnnaBridge | 143:86740a56073b | 1276 | return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)); |
AnnaBridge | 143:86740a56073b | 1277 | } |
AnnaBridge | 143:86740a56073b | 1278 | |
AnnaBridge | 143:86740a56073b | 1279 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 143:86740a56073b | 1280 | /** |
AnnaBridge | 143:86740a56073b | 1281 | * @brief Get DAC underrun flag for DAC channel 2 |
AnnaBridge | 143:86740a56073b | 1282 | * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2 |
AnnaBridge | 143:86740a56073b | 1283 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 1284 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 1285 | */ |
AnnaBridge | 143:86740a56073b | 1286 | __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) |
AnnaBridge | 143:86740a56073b | 1287 | { |
AnnaBridge | 143:86740a56073b | 1288 | return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)); |
AnnaBridge | 143:86740a56073b | 1289 | } |
AnnaBridge | 143:86740a56073b | 1290 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 143:86740a56073b | 1291 | |
AnnaBridge | 143:86740a56073b | 1292 | /** |
AnnaBridge | 143:86740a56073b | 1293 | * @brief Clear DAC underrun flag for DAC channel 1 |
AnnaBridge | 143:86740a56073b | 1294 | * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1 |
AnnaBridge | 143:86740a56073b | 1295 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 1296 | * @retval None |
AnnaBridge | 143:86740a56073b | 1297 | */ |
AnnaBridge | 143:86740a56073b | 1298 | __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx) |
AnnaBridge | 143:86740a56073b | 1299 | { |
AnnaBridge | 143:86740a56073b | 1300 | WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1); |
AnnaBridge | 143:86740a56073b | 1301 | } |
AnnaBridge | 143:86740a56073b | 1302 | |
AnnaBridge | 143:86740a56073b | 1303 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 143:86740a56073b | 1304 | /** |
AnnaBridge | 143:86740a56073b | 1305 | * @brief Clear DAC underrun flag for DAC channel 2 |
AnnaBridge | 143:86740a56073b | 1306 | * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2 |
AnnaBridge | 143:86740a56073b | 1307 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 1308 | * @retval None |
AnnaBridge | 143:86740a56073b | 1309 | */ |
AnnaBridge | 143:86740a56073b | 1310 | __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx) |
AnnaBridge | 143:86740a56073b | 1311 | { |
AnnaBridge | 143:86740a56073b | 1312 | WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2); |
AnnaBridge | 143:86740a56073b | 1313 | } |
AnnaBridge | 143:86740a56073b | 1314 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 143:86740a56073b | 1315 | |
AnnaBridge | 143:86740a56073b | 1316 | /** |
AnnaBridge | 143:86740a56073b | 1317 | * @} |
AnnaBridge | 143:86740a56073b | 1318 | */ |
AnnaBridge | 143:86740a56073b | 1319 | |
AnnaBridge | 143:86740a56073b | 1320 | /** @defgroup DAC_LL_EF_IT_Management IT management |
AnnaBridge | 143:86740a56073b | 1321 | * @{ |
AnnaBridge | 143:86740a56073b | 1322 | */ |
AnnaBridge | 143:86740a56073b | 1323 | |
AnnaBridge | 143:86740a56073b | 1324 | /** |
AnnaBridge | 143:86740a56073b | 1325 | * @brief Enable DMA underrun interrupt for DAC channel 1 |
AnnaBridge | 143:86740a56073b | 1326 | * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1 |
AnnaBridge | 143:86740a56073b | 1327 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 1328 | * @retval None |
AnnaBridge | 143:86740a56073b | 1329 | */ |
AnnaBridge | 143:86740a56073b | 1330 | __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx) |
AnnaBridge | 143:86740a56073b | 1331 | { |
AnnaBridge | 143:86740a56073b | 1332 | SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); |
AnnaBridge | 143:86740a56073b | 1333 | } |
AnnaBridge | 143:86740a56073b | 1334 | |
AnnaBridge | 143:86740a56073b | 1335 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 143:86740a56073b | 1336 | /** |
AnnaBridge | 143:86740a56073b | 1337 | * @brief Enable DMA underrun interrupt for DAC channel 2 |
AnnaBridge | 143:86740a56073b | 1338 | * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2 |
AnnaBridge | 143:86740a56073b | 1339 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 1340 | * @retval None |
AnnaBridge | 143:86740a56073b | 1341 | */ |
AnnaBridge | 143:86740a56073b | 1342 | __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx) |
AnnaBridge | 143:86740a56073b | 1343 | { |
AnnaBridge | 143:86740a56073b | 1344 | SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); |
AnnaBridge | 143:86740a56073b | 1345 | } |
AnnaBridge | 143:86740a56073b | 1346 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 143:86740a56073b | 1347 | |
AnnaBridge | 143:86740a56073b | 1348 | /** |
AnnaBridge | 143:86740a56073b | 1349 | * @brief Disable DMA underrun interrupt for DAC channel 1 |
AnnaBridge | 143:86740a56073b | 1350 | * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1 |
AnnaBridge | 143:86740a56073b | 1351 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 1352 | * @retval None |
AnnaBridge | 143:86740a56073b | 1353 | */ |
AnnaBridge | 143:86740a56073b | 1354 | __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx) |
AnnaBridge | 143:86740a56073b | 1355 | { |
AnnaBridge | 143:86740a56073b | 1356 | CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); |
AnnaBridge | 143:86740a56073b | 1357 | } |
AnnaBridge | 143:86740a56073b | 1358 | |
AnnaBridge | 143:86740a56073b | 1359 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 143:86740a56073b | 1360 | /** |
AnnaBridge | 143:86740a56073b | 1361 | * @brief Disable DMA underrun interrupt for DAC channel 2 |
AnnaBridge | 143:86740a56073b | 1362 | * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2 |
AnnaBridge | 143:86740a56073b | 1363 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 1364 | * @retval None |
AnnaBridge | 143:86740a56073b | 1365 | */ |
AnnaBridge | 143:86740a56073b | 1366 | __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) |
AnnaBridge | 143:86740a56073b | 1367 | { |
AnnaBridge | 143:86740a56073b | 1368 | CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); |
AnnaBridge | 143:86740a56073b | 1369 | } |
AnnaBridge | 143:86740a56073b | 1370 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 143:86740a56073b | 1371 | |
AnnaBridge | 143:86740a56073b | 1372 | /** |
AnnaBridge | 143:86740a56073b | 1373 | * @brief Get DMA underrun interrupt for DAC channel 1 |
AnnaBridge | 143:86740a56073b | 1374 | * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1 |
AnnaBridge | 143:86740a56073b | 1375 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 1376 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 1377 | */ |
AnnaBridge | 143:86740a56073b | 1378 | __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) |
AnnaBridge | 143:86740a56073b | 1379 | { |
AnnaBridge | 143:86740a56073b | 1380 | return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)); |
AnnaBridge | 143:86740a56073b | 1381 | } |
AnnaBridge | 143:86740a56073b | 1382 | |
AnnaBridge | 143:86740a56073b | 1383 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 143:86740a56073b | 1384 | /** |
AnnaBridge | 143:86740a56073b | 1385 | * @brief Get DMA underrun interrupt for DAC channel 2 |
AnnaBridge | 143:86740a56073b | 1386 | * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2 |
AnnaBridge | 143:86740a56073b | 1387 | * @param DACx DAC instance |
AnnaBridge | 143:86740a56073b | 1388 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 1389 | */ |
AnnaBridge | 143:86740a56073b | 1390 | __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) |
AnnaBridge | 143:86740a56073b | 1391 | { |
AnnaBridge | 143:86740a56073b | 1392 | return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)); |
AnnaBridge | 143:86740a56073b | 1393 | } |
AnnaBridge | 143:86740a56073b | 1394 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 143:86740a56073b | 1395 | |
AnnaBridge | 143:86740a56073b | 1396 | /** |
AnnaBridge | 143:86740a56073b | 1397 | * @} |
AnnaBridge | 143:86740a56073b | 1398 | */ |
AnnaBridge | 143:86740a56073b | 1399 | |
AnnaBridge | 143:86740a56073b | 1400 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 143:86740a56073b | 1401 | /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions |
AnnaBridge | 143:86740a56073b | 1402 | * @{ |
AnnaBridge | 143:86740a56073b | 1403 | */ |
AnnaBridge | 143:86740a56073b | 1404 | |
AnnaBridge | 143:86740a56073b | 1405 | ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx); |
AnnaBridge | 143:86740a56073b | 1406 | ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct); |
AnnaBridge | 143:86740a56073b | 1407 | void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct); |
AnnaBridge | 143:86740a56073b | 1408 | |
AnnaBridge | 143:86740a56073b | 1409 | /** |
AnnaBridge | 143:86740a56073b | 1410 | * @} |
AnnaBridge | 143:86740a56073b | 1411 | */ |
AnnaBridge | 143:86740a56073b | 1412 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 143:86740a56073b | 1413 | |
AnnaBridge | 143:86740a56073b | 1414 | /** |
AnnaBridge | 143:86740a56073b | 1415 | * @} |
AnnaBridge | 143:86740a56073b | 1416 | */ |
AnnaBridge | 143:86740a56073b | 1417 | |
AnnaBridge | 143:86740a56073b | 1418 | /** |
AnnaBridge | 143:86740a56073b | 1419 | * @} |
AnnaBridge | 143:86740a56073b | 1420 | */ |
AnnaBridge | 143:86740a56073b | 1421 | |
AnnaBridge | 143:86740a56073b | 1422 | #endif /* DAC1 */ |
AnnaBridge | 143:86740a56073b | 1423 | |
AnnaBridge | 143:86740a56073b | 1424 | /** |
AnnaBridge | 143:86740a56073b | 1425 | * @} |
AnnaBridge | 143:86740a56073b | 1426 | */ |
AnnaBridge | 143:86740a56073b | 1427 | |
AnnaBridge | 143:86740a56073b | 1428 | #ifdef __cplusplus |
AnnaBridge | 143:86740a56073b | 1429 | } |
AnnaBridge | 143:86740a56073b | 1430 | #endif |
AnnaBridge | 143:86740a56073b | 1431 | |
AnnaBridge | 143:86740a56073b | 1432 | #endif /* __STM32L0xx_LL_DAC_H */ |
AnnaBridge | 143:86740a56073b | 1433 | |
AnnaBridge | 143:86740a56073b | 1434 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |