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TARGET_NUCLEO_L011K4/TOOLCHAIN_ARM_MICRO/stm32l0xx_ll_cortex.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_NUCLEO_L011K4/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_cortex.h@167:84c0a372a020
mbed library. Release version 164
Who changed what in which revision?
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AnnaBridge | 157:e7ca05fa8600 | 1 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2 | ****************************************************************************** |
AnnaBridge | 157:e7ca05fa8600 | 3 | * @file stm32l0xx_ll_cortex.h |
AnnaBridge | 157:e7ca05fa8600 | 4 | * @author MCD Application Team |
AnnaBridge | 157:e7ca05fa8600 | 5 | * @brief Header file of CORTEX LL module. |
AnnaBridge | 157:e7ca05fa8600 | 6 | @verbatim |
AnnaBridge | 157:e7ca05fa8600 | 7 | ============================================================================== |
AnnaBridge | 157:e7ca05fa8600 | 8 | ##### How to use this driver ##### |
AnnaBridge | 157:e7ca05fa8600 | 9 | ============================================================================== |
AnnaBridge | 157:e7ca05fa8600 | 10 | [..] |
AnnaBridge | 157:e7ca05fa8600 | 11 | The LL CORTEX driver contains a set of generic APIs that can be |
AnnaBridge | 157:e7ca05fa8600 | 12 | used by user: |
AnnaBridge | 157:e7ca05fa8600 | 13 | (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick |
AnnaBridge | 157:e7ca05fa8600 | 14 | functions |
AnnaBridge | 157:e7ca05fa8600 | 15 | (+) Low power mode configuration (SCB register of Cortex-MCU) |
AnnaBridge | 157:e7ca05fa8600 | 16 | (+) MPU API to configure and enable regions |
AnnaBridge | 157:e7ca05fa8600 | 17 | (+) API to access to MCU info (CPUID register) |
AnnaBridge | 157:e7ca05fa8600 | 18 | |
AnnaBridge | 157:e7ca05fa8600 | 19 | @endverbatim |
AnnaBridge | 157:e7ca05fa8600 | 20 | ****************************************************************************** |
AnnaBridge | 157:e7ca05fa8600 | 21 | * @attention |
AnnaBridge | 157:e7ca05fa8600 | 22 | * |
AnnaBridge | 157:e7ca05fa8600 | 23 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
AnnaBridge | 157:e7ca05fa8600 | 24 | * |
AnnaBridge | 157:e7ca05fa8600 | 25 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 157:e7ca05fa8600 | 26 | * are permitted provided that the following conditions are met: |
AnnaBridge | 157:e7ca05fa8600 | 27 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 157:e7ca05fa8600 | 28 | * this list of conditions and the following disclaimer. |
AnnaBridge | 157:e7ca05fa8600 | 29 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 157:e7ca05fa8600 | 30 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 157:e7ca05fa8600 | 31 | * and/or other materials provided with the distribution. |
AnnaBridge | 157:e7ca05fa8600 | 32 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 157:e7ca05fa8600 | 33 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 157:e7ca05fa8600 | 34 | * without specific prior written permission. |
AnnaBridge | 157:e7ca05fa8600 | 35 | * |
AnnaBridge | 157:e7ca05fa8600 | 36 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 157:e7ca05fa8600 | 37 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 157:e7ca05fa8600 | 38 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 157:e7ca05fa8600 | 39 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 157:e7ca05fa8600 | 40 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 157:e7ca05fa8600 | 41 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 157:e7ca05fa8600 | 42 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 157:e7ca05fa8600 | 43 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 157:e7ca05fa8600 | 44 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 157:e7ca05fa8600 | 45 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 157:e7ca05fa8600 | 46 | * |
AnnaBridge | 157:e7ca05fa8600 | 47 | ****************************************************************************** |
AnnaBridge | 157:e7ca05fa8600 | 48 | */ |
AnnaBridge | 157:e7ca05fa8600 | 49 | |
AnnaBridge | 157:e7ca05fa8600 | 50 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 51 | #ifndef __STM32L0xx_LL_CORTEX_H |
AnnaBridge | 157:e7ca05fa8600 | 52 | #define __STM32L0xx_LL_CORTEX_H |
AnnaBridge | 157:e7ca05fa8600 | 53 | |
AnnaBridge | 157:e7ca05fa8600 | 54 | #ifdef __cplusplus |
AnnaBridge | 157:e7ca05fa8600 | 55 | extern "C" { |
AnnaBridge | 157:e7ca05fa8600 | 56 | #endif |
AnnaBridge | 157:e7ca05fa8600 | 57 | |
AnnaBridge | 157:e7ca05fa8600 | 58 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 59 | #include "stm32l0xx.h" |
AnnaBridge | 157:e7ca05fa8600 | 60 | |
AnnaBridge | 157:e7ca05fa8600 | 61 | /** @addtogroup STM32L0xx_LL_Driver |
AnnaBridge | 157:e7ca05fa8600 | 62 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 63 | */ |
AnnaBridge | 157:e7ca05fa8600 | 64 | |
AnnaBridge | 157:e7ca05fa8600 | 65 | /** @defgroup CORTEX_LL CORTEX |
AnnaBridge | 157:e7ca05fa8600 | 66 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 67 | */ |
AnnaBridge | 157:e7ca05fa8600 | 68 | |
AnnaBridge | 157:e7ca05fa8600 | 69 | /* Private types -------------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 70 | /* Private variables ---------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 71 | |
AnnaBridge | 157:e7ca05fa8600 | 72 | /* Private constants ---------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 73 | |
AnnaBridge | 157:e7ca05fa8600 | 74 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 75 | |
AnnaBridge | 157:e7ca05fa8600 | 76 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 77 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 78 | /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants |
AnnaBridge | 157:e7ca05fa8600 | 79 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 80 | */ |
AnnaBridge | 157:e7ca05fa8600 | 81 | |
AnnaBridge | 157:e7ca05fa8600 | 82 | /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source |
AnnaBridge | 157:e7ca05fa8600 | 83 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 84 | */ |
AnnaBridge | 157:e7ca05fa8600 | 85 | #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) /*!< AHB clock divided by 8 selected as SysTick clock source.*/ |
AnnaBridge | 157:e7ca05fa8600 | 86 | #define LL_SYSTICK_CLKSOURCE_HCLK ((uint32_t)SysTick_CTRL_CLKSOURCE_Msk) /*!< AHB clock selected as SysTick clock source. */ |
AnnaBridge | 157:e7ca05fa8600 | 87 | /** |
AnnaBridge | 157:e7ca05fa8600 | 88 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 89 | */ |
AnnaBridge | 157:e7ca05fa8600 | 90 | |
AnnaBridge | 157:e7ca05fa8600 | 91 | #if __MPU_PRESENT |
AnnaBridge | 157:e7ca05fa8600 | 92 | |
AnnaBridge | 157:e7ca05fa8600 | 93 | /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control |
AnnaBridge | 157:e7ca05fa8600 | 94 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 95 | */ |
AnnaBridge | 157:e7ca05fa8600 | 96 | #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) /*!< Disable NMI and privileged SW access */ |
AnnaBridge | 157:e7ca05fa8600 | 97 | #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ |
AnnaBridge | 157:e7ca05fa8600 | 98 | #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ |
AnnaBridge | 157:e7ca05fa8600 | 99 | #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ |
AnnaBridge | 157:e7ca05fa8600 | 100 | /** |
AnnaBridge | 157:e7ca05fa8600 | 101 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 102 | */ |
AnnaBridge | 157:e7ca05fa8600 | 103 | |
AnnaBridge | 157:e7ca05fa8600 | 104 | /** @defgroup CORTEX_LL_EC_REGION MPU Region Number |
AnnaBridge | 157:e7ca05fa8600 | 105 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 106 | */ |
AnnaBridge | 157:e7ca05fa8600 | 107 | #define LL_MPU_REGION_NUMBER0 ((uint32_t)0x00U) /*!< REGION Number 0 */ |
AnnaBridge | 157:e7ca05fa8600 | 108 | #define LL_MPU_REGION_NUMBER1 ((uint32_t)0x01U) /*!< REGION Number 1 */ |
AnnaBridge | 157:e7ca05fa8600 | 109 | #define LL_MPU_REGION_NUMBER2 ((uint32_t)0x02U) /*!< REGION Number 2 */ |
AnnaBridge | 157:e7ca05fa8600 | 110 | #define LL_MPU_REGION_NUMBER3 ((uint32_t)0x03U) /*!< REGION Number 3 */ |
AnnaBridge | 157:e7ca05fa8600 | 111 | #define LL_MPU_REGION_NUMBER4 ((uint32_t)0x04U) /*!< REGION Number 4 */ |
AnnaBridge | 157:e7ca05fa8600 | 112 | #define LL_MPU_REGION_NUMBER5 ((uint32_t)0x05U) /*!< REGION Number 5 */ |
AnnaBridge | 157:e7ca05fa8600 | 113 | #define LL_MPU_REGION_NUMBER6 ((uint32_t)0x06U) /*!< REGION Number 6 */ |
AnnaBridge | 157:e7ca05fa8600 | 114 | #define LL_MPU_REGION_NUMBER7 ((uint32_t)0x07U) /*!< REGION Number 7 */ |
AnnaBridge | 157:e7ca05fa8600 | 115 | /** |
AnnaBridge | 157:e7ca05fa8600 | 116 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 117 | */ |
AnnaBridge | 157:e7ca05fa8600 | 118 | |
AnnaBridge | 157:e7ca05fa8600 | 119 | /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size |
AnnaBridge | 157:e7ca05fa8600 | 120 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 121 | */ |
AnnaBridge | 157:e7ca05fa8600 | 122 | #define LL_MPU_REGION_SIZE_32B ((uint32_t)(0x04U << MPU_RASR_SIZE_Pos)) /*!< 32B Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 123 | #define LL_MPU_REGION_SIZE_64B ((uint32_t)(0x05U << MPU_RASR_SIZE_Pos)) /*!< 64B Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 124 | #define LL_MPU_REGION_SIZE_128B ((uint32_t)(0x06U << MPU_RASR_SIZE_Pos)) /*!< 128B Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 125 | #define LL_MPU_REGION_SIZE_256B ((uint32_t)(0x07U << MPU_RASR_SIZE_Pos)) /*!< 256B Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 126 | #define LL_MPU_REGION_SIZE_512B ((uint32_t)(0x08U << MPU_RASR_SIZE_Pos)) /*!< 512B Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 127 | #define LL_MPU_REGION_SIZE_1KB ((uint32_t)(0x09U << MPU_RASR_SIZE_Pos)) /*!< 1KB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 128 | #define LL_MPU_REGION_SIZE_2KB ((uint32_t)(0x0AU << MPU_RASR_SIZE_Pos)) /*!< 2KB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 129 | #define LL_MPU_REGION_SIZE_4KB ((uint32_t)(0x0BU << MPU_RASR_SIZE_Pos)) /*!< 4KB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 130 | #define LL_MPU_REGION_SIZE_8KB ((uint32_t)(0x0CU << MPU_RASR_SIZE_Pos)) /*!< 8KB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 131 | #define LL_MPU_REGION_SIZE_16KB ((uint32_t)(0x0DU << MPU_RASR_SIZE_Pos)) /*!< 16KB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 132 | #define LL_MPU_REGION_SIZE_32KB ((uint32_t)(0x0EU << MPU_RASR_SIZE_Pos)) /*!< 32KB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 133 | #define LL_MPU_REGION_SIZE_64KB ((uint32_t)(0x0FU << MPU_RASR_SIZE_Pos)) /*!< 64KB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 134 | #define LL_MPU_REGION_SIZE_128KB ((uint32_t)(0x10U << MPU_RASR_SIZE_Pos)) /*!< 128KB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 135 | #define LL_MPU_REGION_SIZE_256KB ((uint32_t)(0x11U << MPU_RASR_SIZE_Pos)) /*!< 256KB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 136 | #define LL_MPU_REGION_SIZE_512KB ((uint32_t)(0x12U << MPU_RASR_SIZE_Pos)) /*!< 512KB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 137 | #define LL_MPU_REGION_SIZE_1MB ((uint32_t)(0x13U << MPU_RASR_SIZE_Pos)) /*!< 1MB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 138 | #define LL_MPU_REGION_SIZE_2MB ((uint32_t)(0x14U << MPU_RASR_SIZE_Pos)) /*!< 2MB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 139 | #define LL_MPU_REGION_SIZE_4MB ((uint32_t)(0x15U << MPU_RASR_SIZE_Pos)) /*!< 4MB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 140 | #define LL_MPU_REGION_SIZE_8MB ((uint32_t)(0x16U << MPU_RASR_SIZE_Pos)) /*!< 8MB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 141 | #define LL_MPU_REGION_SIZE_16MB ((uint32_t)(0x17U << MPU_RASR_SIZE_Pos)) /*!< 16MB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 142 | #define LL_MPU_REGION_SIZE_32MB ((uint32_t)(0x18U << MPU_RASR_SIZE_Pos)) /*!< 32MB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 143 | #define LL_MPU_REGION_SIZE_64MB ((uint32_t)(0x19U << MPU_RASR_SIZE_Pos)) /*!< 64MB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 144 | #define LL_MPU_REGION_SIZE_128MB ((uint32_t)(0x1AU << MPU_RASR_SIZE_Pos)) /*!< 128MB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 145 | #define LL_MPU_REGION_SIZE_256MB ((uint32_t)(0x1BU << MPU_RASR_SIZE_Pos)) /*!< 256MB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 146 | #define LL_MPU_REGION_SIZE_512MB ((uint32_t)(0x1CU << MPU_RASR_SIZE_Pos)) /*!< 512MB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 147 | #define LL_MPU_REGION_SIZE_1GB ((uint32_t)(0x1DU << MPU_RASR_SIZE_Pos)) /*!< 1GB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 148 | #define LL_MPU_REGION_SIZE_2GB ((uint32_t)(0x1EU << MPU_RASR_SIZE_Pos)) /*!< 2GB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 149 | #define LL_MPU_REGION_SIZE_4GB ((uint32_t)(0x1FU << MPU_RASR_SIZE_Pos)) /*!< 4GB Size of the MPU protection region */ |
AnnaBridge | 157:e7ca05fa8600 | 150 | /** |
AnnaBridge | 157:e7ca05fa8600 | 151 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 152 | */ |
AnnaBridge | 157:e7ca05fa8600 | 153 | |
AnnaBridge | 157:e7ca05fa8600 | 154 | /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges |
AnnaBridge | 157:e7ca05fa8600 | 155 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 156 | */ |
AnnaBridge | 157:e7ca05fa8600 | 157 | #define LL_MPU_REGION_NO_ACCESS ((uint32_t)(0x00U << MPU_RASR_AP_Pos)) /*!< No access*/ |
AnnaBridge | 157:e7ca05fa8600 | 158 | #define LL_MPU_REGION_PRIV_RW ((uint32_t)(0x01U << MPU_RASR_AP_Pos)) /*!< RW privileged (privileged access only)*/ |
AnnaBridge | 157:e7ca05fa8600 | 159 | #define LL_MPU_REGION_PRIV_RW_URO ((uint32_t)(0x02U << MPU_RASR_AP_Pos)) /*!< RW privileged - RO user (Write in a user program generates a fault) */ |
AnnaBridge | 157:e7ca05fa8600 | 160 | #define LL_MPU_REGION_FULL_ACCESS ((uint32_t)(0x03U << MPU_RASR_AP_Pos)) /*!< RW privileged & user (Full access) */ |
AnnaBridge | 157:e7ca05fa8600 | 161 | #define LL_MPU_REGION_PRIV_RO ((uint32_t)(0x05U << MPU_RASR_AP_Pos)) /*!< RO privileged (privileged read only)*/ |
AnnaBridge | 157:e7ca05fa8600 | 162 | #define LL_MPU_REGION_PRIV_RO_URO ((uint32_t)(0x06U << MPU_RASR_AP_Pos)) /*!< RO privileged & user (read only) */ |
AnnaBridge | 157:e7ca05fa8600 | 163 | /** |
AnnaBridge | 157:e7ca05fa8600 | 164 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 165 | */ |
AnnaBridge | 157:e7ca05fa8600 | 166 | |
AnnaBridge | 157:e7ca05fa8600 | 167 | /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level |
AnnaBridge | 157:e7ca05fa8600 | 168 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 169 | */ |
AnnaBridge | 157:e7ca05fa8600 | 170 | #define LL_MPU_TEX_LEVEL0 ((uint32_t)(0x00U << MPU_RASR_TEX_Pos)) /*!< b000 for TEX bits */ |
AnnaBridge | 157:e7ca05fa8600 | 171 | #define LL_MPU_TEX_LEVEL1 ((uint32_t)(0x01U << MPU_RASR_TEX_Pos)) /*!< b001 for TEX bits */ |
AnnaBridge | 157:e7ca05fa8600 | 172 | #define LL_MPU_TEX_LEVEL2 ((uint32_t)(0x02U << MPU_RASR_TEX_Pos)) /*!< b010 for TEX bits */ |
AnnaBridge | 157:e7ca05fa8600 | 173 | #define LL_MPU_TEX_LEVEL4 ((uint32_t)(0x04U << MPU_RASR_TEX_Pos)) /*!< b100 for TEX bits */ |
AnnaBridge | 157:e7ca05fa8600 | 174 | /** |
AnnaBridge | 157:e7ca05fa8600 | 175 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 176 | */ |
AnnaBridge | 157:e7ca05fa8600 | 177 | |
AnnaBridge | 157:e7ca05fa8600 | 178 | /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access |
AnnaBridge | 157:e7ca05fa8600 | 179 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 180 | */ |
AnnaBridge | 157:e7ca05fa8600 | 181 | #define LL_MPU_INSTRUCTION_ACCESS_ENABLE ((uint32_t)0x00U) /*!< Instruction fetches enabled */ |
AnnaBridge | 157:e7ca05fa8600 | 182 | #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ |
AnnaBridge | 157:e7ca05fa8600 | 183 | /** |
AnnaBridge | 157:e7ca05fa8600 | 184 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 185 | */ |
AnnaBridge | 157:e7ca05fa8600 | 186 | |
AnnaBridge | 157:e7ca05fa8600 | 187 | /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access |
AnnaBridge | 157:e7ca05fa8600 | 188 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 189 | */ |
AnnaBridge | 157:e7ca05fa8600 | 190 | #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ |
AnnaBridge | 157:e7ca05fa8600 | 191 | #define LL_MPU_ACCESS_NOT_SHAREABLE ((uint32_t)0x00U) /*!< Not Shareable memory attribute */ |
AnnaBridge | 157:e7ca05fa8600 | 192 | /** |
AnnaBridge | 157:e7ca05fa8600 | 193 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 194 | */ |
AnnaBridge | 157:e7ca05fa8600 | 195 | |
AnnaBridge | 157:e7ca05fa8600 | 196 | /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access |
AnnaBridge | 157:e7ca05fa8600 | 197 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 198 | */ |
AnnaBridge | 157:e7ca05fa8600 | 199 | #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ |
AnnaBridge | 157:e7ca05fa8600 | 200 | #define LL_MPU_ACCESS_NOT_CACHEABLE ((uint32_t)0x00U) /*!< Not Cacheable memory attribute */ |
AnnaBridge | 157:e7ca05fa8600 | 201 | /** |
AnnaBridge | 157:e7ca05fa8600 | 202 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 203 | */ |
AnnaBridge | 157:e7ca05fa8600 | 204 | |
AnnaBridge | 157:e7ca05fa8600 | 205 | /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access |
AnnaBridge | 157:e7ca05fa8600 | 206 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 207 | */ |
AnnaBridge | 157:e7ca05fa8600 | 208 | #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ |
AnnaBridge | 157:e7ca05fa8600 | 209 | #define LL_MPU_ACCESS_NOT_BUFFERABLE ((uint32_t)0x00U) /*!< Not Bufferable memory attribute */ |
AnnaBridge | 157:e7ca05fa8600 | 210 | /** |
AnnaBridge | 157:e7ca05fa8600 | 211 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 212 | */ |
AnnaBridge | 157:e7ca05fa8600 | 213 | #endif /* __MPU_PRESENT */ |
AnnaBridge | 157:e7ca05fa8600 | 214 | /** |
AnnaBridge | 157:e7ca05fa8600 | 215 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 216 | */ |
AnnaBridge | 157:e7ca05fa8600 | 217 | |
AnnaBridge | 157:e7ca05fa8600 | 218 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 219 | |
AnnaBridge | 157:e7ca05fa8600 | 220 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 221 | /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions |
AnnaBridge | 157:e7ca05fa8600 | 222 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 223 | */ |
AnnaBridge | 157:e7ca05fa8600 | 224 | |
AnnaBridge | 157:e7ca05fa8600 | 225 | /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK |
AnnaBridge | 157:e7ca05fa8600 | 226 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 227 | */ |
AnnaBridge | 157:e7ca05fa8600 | 228 | |
AnnaBridge | 157:e7ca05fa8600 | 229 | /** |
AnnaBridge | 157:e7ca05fa8600 | 230 | * @brief This function checks if the Systick counter flag is active or not. |
AnnaBridge | 157:e7ca05fa8600 | 231 | * @note It can be used in timeout function on application side. |
AnnaBridge | 157:e7ca05fa8600 | 232 | * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag |
AnnaBridge | 157:e7ca05fa8600 | 233 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 234 | */ |
AnnaBridge | 157:e7ca05fa8600 | 235 | __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) |
AnnaBridge | 157:e7ca05fa8600 | 236 | { |
AnnaBridge | 157:e7ca05fa8600 | 237 | return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); |
AnnaBridge | 157:e7ca05fa8600 | 238 | } |
AnnaBridge | 157:e7ca05fa8600 | 239 | |
AnnaBridge | 157:e7ca05fa8600 | 240 | /** |
AnnaBridge | 157:e7ca05fa8600 | 241 | * @brief Configures the SysTick clock source |
AnnaBridge | 157:e7ca05fa8600 | 242 | * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource |
AnnaBridge | 157:e7ca05fa8600 | 243 | * @param Source This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 244 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 |
AnnaBridge | 157:e7ca05fa8600 | 245 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK |
AnnaBridge | 157:e7ca05fa8600 | 246 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 247 | */ |
AnnaBridge | 157:e7ca05fa8600 | 248 | __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) |
AnnaBridge | 157:e7ca05fa8600 | 249 | { |
AnnaBridge | 157:e7ca05fa8600 | 250 | if (Source == LL_SYSTICK_CLKSOURCE_HCLK) |
AnnaBridge | 157:e7ca05fa8600 | 251 | { |
AnnaBridge | 157:e7ca05fa8600 | 252 | SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); |
AnnaBridge | 157:e7ca05fa8600 | 253 | } |
AnnaBridge | 157:e7ca05fa8600 | 254 | else |
AnnaBridge | 157:e7ca05fa8600 | 255 | { |
AnnaBridge | 157:e7ca05fa8600 | 256 | CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); |
AnnaBridge | 157:e7ca05fa8600 | 257 | } |
AnnaBridge | 157:e7ca05fa8600 | 258 | } |
AnnaBridge | 157:e7ca05fa8600 | 259 | |
AnnaBridge | 157:e7ca05fa8600 | 260 | /** |
AnnaBridge | 157:e7ca05fa8600 | 261 | * @brief Get the SysTick clock source |
AnnaBridge | 157:e7ca05fa8600 | 262 | * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource |
AnnaBridge | 157:e7ca05fa8600 | 263 | * @retval Returned value can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 264 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 |
AnnaBridge | 157:e7ca05fa8600 | 265 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK |
AnnaBridge | 157:e7ca05fa8600 | 266 | */ |
AnnaBridge | 157:e7ca05fa8600 | 267 | __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) |
AnnaBridge | 157:e7ca05fa8600 | 268 | { |
AnnaBridge | 157:e7ca05fa8600 | 269 | return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); |
AnnaBridge | 157:e7ca05fa8600 | 270 | } |
AnnaBridge | 157:e7ca05fa8600 | 271 | |
AnnaBridge | 157:e7ca05fa8600 | 272 | /** |
AnnaBridge | 157:e7ca05fa8600 | 273 | * @brief Enable SysTick exception request |
AnnaBridge | 157:e7ca05fa8600 | 274 | * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT |
AnnaBridge | 157:e7ca05fa8600 | 275 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 276 | */ |
AnnaBridge | 157:e7ca05fa8600 | 277 | __STATIC_INLINE void LL_SYSTICK_EnableIT(void) |
AnnaBridge | 157:e7ca05fa8600 | 278 | { |
AnnaBridge | 157:e7ca05fa8600 | 279 | SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); |
AnnaBridge | 157:e7ca05fa8600 | 280 | } |
AnnaBridge | 157:e7ca05fa8600 | 281 | |
AnnaBridge | 157:e7ca05fa8600 | 282 | /** |
AnnaBridge | 157:e7ca05fa8600 | 283 | * @brief Disable SysTick exception request |
AnnaBridge | 157:e7ca05fa8600 | 284 | * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT |
AnnaBridge | 157:e7ca05fa8600 | 285 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 286 | */ |
AnnaBridge | 157:e7ca05fa8600 | 287 | __STATIC_INLINE void LL_SYSTICK_DisableIT(void) |
AnnaBridge | 157:e7ca05fa8600 | 288 | { |
AnnaBridge | 157:e7ca05fa8600 | 289 | CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); |
AnnaBridge | 157:e7ca05fa8600 | 290 | } |
AnnaBridge | 157:e7ca05fa8600 | 291 | |
AnnaBridge | 157:e7ca05fa8600 | 292 | /** |
AnnaBridge | 157:e7ca05fa8600 | 293 | * @brief Checks if the SYSTICK interrupt is enabled or disabled. |
AnnaBridge | 157:e7ca05fa8600 | 294 | * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT |
AnnaBridge | 157:e7ca05fa8600 | 295 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 296 | */ |
AnnaBridge | 157:e7ca05fa8600 | 297 | __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) |
AnnaBridge | 157:e7ca05fa8600 | 298 | { |
AnnaBridge | 157:e7ca05fa8600 | 299 | return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); |
AnnaBridge | 157:e7ca05fa8600 | 300 | } |
AnnaBridge | 157:e7ca05fa8600 | 301 | |
AnnaBridge | 157:e7ca05fa8600 | 302 | /** |
AnnaBridge | 157:e7ca05fa8600 | 303 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 304 | */ |
AnnaBridge | 157:e7ca05fa8600 | 305 | |
AnnaBridge | 157:e7ca05fa8600 | 306 | /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE |
AnnaBridge | 157:e7ca05fa8600 | 307 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 308 | */ |
AnnaBridge | 157:e7ca05fa8600 | 309 | |
AnnaBridge | 157:e7ca05fa8600 | 310 | /** |
AnnaBridge | 157:e7ca05fa8600 | 311 | * @brief Processor uses sleep as its low power mode |
AnnaBridge | 157:e7ca05fa8600 | 312 | * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep |
AnnaBridge | 157:e7ca05fa8600 | 313 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 314 | */ |
AnnaBridge | 157:e7ca05fa8600 | 315 | __STATIC_INLINE void LL_LPM_EnableSleep(void) |
AnnaBridge | 157:e7ca05fa8600 | 316 | { |
AnnaBridge | 157:e7ca05fa8600 | 317 | /* Clear SLEEPDEEP bit of Cortex System Control Register */ |
AnnaBridge | 157:e7ca05fa8600 | 318 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
AnnaBridge | 157:e7ca05fa8600 | 319 | } |
AnnaBridge | 157:e7ca05fa8600 | 320 | |
AnnaBridge | 157:e7ca05fa8600 | 321 | /** |
AnnaBridge | 157:e7ca05fa8600 | 322 | * @brief Processor uses deep sleep as its low power mode |
AnnaBridge | 157:e7ca05fa8600 | 323 | * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep |
AnnaBridge | 157:e7ca05fa8600 | 324 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 325 | */ |
AnnaBridge | 157:e7ca05fa8600 | 326 | __STATIC_INLINE void LL_LPM_EnableDeepSleep(void) |
AnnaBridge | 157:e7ca05fa8600 | 327 | { |
AnnaBridge | 157:e7ca05fa8600 | 328 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
AnnaBridge | 157:e7ca05fa8600 | 329 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
AnnaBridge | 157:e7ca05fa8600 | 330 | } |
AnnaBridge | 157:e7ca05fa8600 | 331 | |
AnnaBridge | 157:e7ca05fa8600 | 332 | /** |
AnnaBridge | 157:e7ca05fa8600 | 333 | * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. |
AnnaBridge | 157:e7ca05fa8600 | 334 | * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an |
AnnaBridge | 157:e7ca05fa8600 | 335 | * empty main application. |
AnnaBridge | 157:e7ca05fa8600 | 336 | * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit |
AnnaBridge | 157:e7ca05fa8600 | 337 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 338 | */ |
AnnaBridge | 157:e7ca05fa8600 | 339 | __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) |
AnnaBridge | 157:e7ca05fa8600 | 340 | { |
AnnaBridge | 157:e7ca05fa8600 | 341 | /* Set SLEEPONEXIT bit of Cortex System Control Register */ |
AnnaBridge | 157:e7ca05fa8600 | 342 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
AnnaBridge | 157:e7ca05fa8600 | 343 | } |
AnnaBridge | 157:e7ca05fa8600 | 344 | |
AnnaBridge | 157:e7ca05fa8600 | 345 | /** |
AnnaBridge | 157:e7ca05fa8600 | 346 | * @brief Do not sleep when returning to Thread mode. |
AnnaBridge | 157:e7ca05fa8600 | 347 | * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit |
AnnaBridge | 157:e7ca05fa8600 | 348 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 349 | */ |
AnnaBridge | 157:e7ca05fa8600 | 350 | __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) |
AnnaBridge | 157:e7ca05fa8600 | 351 | { |
AnnaBridge | 157:e7ca05fa8600 | 352 | /* Clear SLEEPONEXIT bit of Cortex System Control Register */ |
AnnaBridge | 157:e7ca05fa8600 | 353 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
AnnaBridge | 157:e7ca05fa8600 | 354 | } |
AnnaBridge | 157:e7ca05fa8600 | 355 | |
AnnaBridge | 157:e7ca05fa8600 | 356 | /** |
AnnaBridge | 157:e7ca05fa8600 | 357 | * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the |
AnnaBridge | 157:e7ca05fa8600 | 358 | * processor. |
AnnaBridge | 157:e7ca05fa8600 | 359 | * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend |
AnnaBridge | 157:e7ca05fa8600 | 360 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 361 | */ |
AnnaBridge | 157:e7ca05fa8600 | 362 | __STATIC_INLINE void LL_LPM_EnableEventOnPend(void) |
AnnaBridge | 157:e7ca05fa8600 | 363 | { |
AnnaBridge | 157:e7ca05fa8600 | 364 | /* Set SEVEONPEND bit of Cortex System Control Register */ |
AnnaBridge | 157:e7ca05fa8600 | 365 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
AnnaBridge | 157:e7ca05fa8600 | 366 | } |
AnnaBridge | 157:e7ca05fa8600 | 367 | |
AnnaBridge | 157:e7ca05fa8600 | 368 | /** |
AnnaBridge | 157:e7ca05fa8600 | 369 | * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are |
AnnaBridge | 157:e7ca05fa8600 | 370 | * excluded |
AnnaBridge | 157:e7ca05fa8600 | 371 | * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend |
AnnaBridge | 157:e7ca05fa8600 | 372 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 373 | */ |
AnnaBridge | 157:e7ca05fa8600 | 374 | __STATIC_INLINE void LL_LPM_DisableEventOnPend(void) |
AnnaBridge | 157:e7ca05fa8600 | 375 | { |
AnnaBridge | 157:e7ca05fa8600 | 376 | /* Clear SEVEONPEND bit of Cortex System Control Register */ |
AnnaBridge | 157:e7ca05fa8600 | 377 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
AnnaBridge | 157:e7ca05fa8600 | 378 | } |
AnnaBridge | 157:e7ca05fa8600 | 379 | |
AnnaBridge | 157:e7ca05fa8600 | 380 | /** |
AnnaBridge | 157:e7ca05fa8600 | 381 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 382 | */ |
AnnaBridge | 157:e7ca05fa8600 | 383 | |
AnnaBridge | 157:e7ca05fa8600 | 384 | /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO |
AnnaBridge | 157:e7ca05fa8600 | 385 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 386 | */ |
AnnaBridge | 157:e7ca05fa8600 | 387 | |
AnnaBridge | 157:e7ca05fa8600 | 388 | /** |
AnnaBridge | 157:e7ca05fa8600 | 389 | * @brief Get Implementer code |
AnnaBridge | 157:e7ca05fa8600 | 390 | * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer |
AnnaBridge | 157:e7ca05fa8600 | 391 | * @retval Value should be equal to 0x41 for ARM |
AnnaBridge | 157:e7ca05fa8600 | 392 | */ |
AnnaBridge | 157:e7ca05fa8600 | 393 | __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) |
AnnaBridge | 157:e7ca05fa8600 | 394 | { |
AnnaBridge | 157:e7ca05fa8600 | 395 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); |
AnnaBridge | 157:e7ca05fa8600 | 396 | } |
AnnaBridge | 157:e7ca05fa8600 | 397 | |
AnnaBridge | 157:e7ca05fa8600 | 398 | /** |
AnnaBridge | 157:e7ca05fa8600 | 399 | * @brief Get Variant number (The r value in the rnpn product revision identifier) |
AnnaBridge | 157:e7ca05fa8600 | 400 | * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant |
AnnaBridge | 157:e7ca05fa8600 | 401 | * @retval Value between 0 and 255 (0x0: revision 0) |
AnnaBridge | 157:e7ca05fa8600 | 402 | */ |
AnnaBridge | 157:e7ca05fa8600 | 403 | __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) |
AnnaBridge | 157:e7ca05fa8600 | 404 | { |
AnnaBridge | 157:e7ca05fa8600 | 405 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); |
AnnaBridge | 157:e7ca05fa8600 | 406 | } |
AnnaBridge | 157:e7ca05fa8600 | 407 | |
AnnaBridge | 157:e7ca05fa8600 | 408 | /** |
AnnaBridge | 157:e7ca05fa8600 | 409 | * @brief Get Architecture number |
AnnaBridge | 157:e7ca05fa8600 | 410 | * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture |
AnnaBridge | 157:e7ca05fa8600 | 411 | * @retval Value should be equal to 0xC for Cortex-M0+ devices |
AnnaBridge | 157:e7ca05fa8600 | 412 | */ |
AnnaBridge | 157:e7ca05fa8600 | 413 | __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) |
AnnaBridge | 157:e7ca05fa8600 | 414 | { |
AnnaBridge | 157:e7ca05fa8600 | 415 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); |
AnnaBridge | 157:e7ca05fa8600 | 416 | } |
AnnaBridge | 157:e7ca05fa8600 | 417 | |
AnnaBridge | 157:e7ca05fa8600 | 418 | /** |
AnnaBridge | 157:e7ca05fa8600 | 419 | * @brief Get Part number |
AnnaBridge | 157:e7ca05fa8600 | 420 | * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo |
AnnaBridge | 157:e7ca05fa8600 | 421 | * @retval Value should be equal to 0xC60 for Cortex-M0+ |
AnnaBridge | 157:e7ca05fa8600 | 422 | */ |
AnnaBridge | 157:e7ca05fa8600 | 423 | __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) |
AnnaBridge | 157:e7ca05fa8600 | 424 | { |
AnnaBridge | 157:e7ca05fa8600 | 425 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); |
AnnaBridge | 157:e7ca05fa8600 | 426 | } |
AnnaBridge | 157:e7ca05fa8600 | 427 | |
AnnaBridge | 157:e7ca05fa8600 | 428 | /** |
AnnaBridge | 157:e7ca05fa8600 | 429 | * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) |
AnnaBridge | 157:e7ca05fa8600 | 430 | * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision |
AnnaBridge | 157:e7ca05fa8600 | 431 | * @retval Value between 0 and 255 (0x1: patch 1) |
AnnaBridge | 157:e7ca05fa8600 | 432 | */ |
AnnaBridge | 157:e7ca05fa8600 | 433 | __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) |
AnnaBridge | 157:e7ca05fa8600 | 434 | { |
AnnaBridge | 157:e7ca05fa8600 | 435 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); |
AnnaBridge | 157:e7ca05fa8600 | 436 | } |
AnnaBridge | 157:e7ca05fa8600 | 437 | |
AnnaBridge | 157:e7ca05fa8600 | 438 | /** |
AnnaBridge | 157:e7ca05fa8600 | 439 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 440 | */ |
AnnaBridge | 157:e7ca05fa8600 | 441 | |
AnnaBridge | 157:e7ca05fa8600 | 442 | #if __MPU_PRESENT |
AnnaBridge | 157:e7ca05fa8600 | 443 | /** @defgroup CORTEX_LL_EF_MPU MPU |
AnnaBridge | 157:e7ca05fa8600 | 444 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 445 | */ |
AnnaBridge | 157:e7ca05fa8600 | 446 | |
AnnaBridge | 157:e7ca05fa8600 | 447 | /** |
AnnaBridge | 157:e7ca05fa8600 | 448 | * @brief Enable MPU with input options |
AnnaBridge | 157:e7ca05fa8600 | 449 | * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable |
AnnaBridge | 157:e7ca05fa8600 | 450 | * @param Options This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 451 | * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE |
AnnaBridge | 157:e7ca05fa8600 | 452 | * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI |
AnnaBridge | 157:e7ca05fa8600 | 453 | * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT |
AnnaBridge | 157:e7ca05fa8600 | 454 | * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF |
AnnaBridge | 157:e7ca05fa8600 | 455 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 456 | */ |
AnnaBridge | 157:e7ca05fa8600 | 457 | __STATIC_INLINE void LL_MPU_Enable(uint32_t Options) |
AnnaBridge | 157:e7ca05fa8600 | 458 | { |
AnnaBridge | 157:e7ca05fa8600 | 459 | /* Enable the MPU*/ |
AnnaBridge | 157:e7ca05fa8600 | 460 | WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); |
AnnaBridge | 157:e7ca05fa8600 | 461 | /* Ensure MPU settings take effects */ |
AnnaBridge | 157:e7ca05fa8600 | 462 | __DSB(); |
AnnaBridge | 157:e7ca05fa8600 | 463 | /* Sequence instruction fetches using update settings */ |
AnnaBridge | 157:e7ca05fa8600 | 464 | __ISB(); |
AnnaBridge | 157:e7ca05fa8600 | 465 | } |
AnnaBridge | 157:e7ca05fa8600 | 466 | |
AnnaBridge | 157:e7ca05fa8600 | 467 | /** |
AnnaBridge | 157:e7ca05fa8600 | 468 | * @brief Disable MPU |
AnnaBridge | 157:e7ca05fa8600 | 469 | * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable |
AnnaBridge | 157:e7ca05fa8600 | 470 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 471 | */ |
AnnaBridge | 157:e7ca05fa8600 | 472 | __STATIC_INLINE void LL_MPU_Disable(void) |
AnnaBridge | 157:e7ca05fa8600 | 473 | { |
AnnaBridge | 157:e7ca05fa8600 | 474 | /* Make sure outstanding transfers are done */ |
AnnaBridge | 157:e7ca05fa8600 | 475 | __DMB(); |
AnnaBridge | 157:e7ca05fa8600 | 476 | /* Disable MPU*/ |
AnnaBridge | 157:e7ca05fa8600 | 477 | WRITE_REG(MPU->CTRL, 0U); |
AnnaBridge | 157:e7ca05fa8600 | 478 | } |
AnnaBridge | 157:e7ca05fa8600 | 479 | |
AnnaBridge | 157:e7ca05fa8600 | 480 | /** |
AnnaBridge | 157:e7ca05fa8600 | 481 | * @brief Check if MPU is enabled or not |
AnnaBridge | 157:e7ca05fa8600 | 482 | * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled |
AnnaBridge | 157:e7ca05fa8600 | 483 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 484 | */ |
AnnaBridge | 157:e7ca05fa8600 | 485 | __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) |
AnnaBridge | 157:e7ca05fa8600 | 486 | { |
AnnaBridge | 157:e7ca05fa8600 | 487 | return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); |
AnnaBridge | 157:e7ca05fa8600 | 488 | } |
AnnaBridge | 157:e7ca05fa8600 | 489 | |
AnnaBridge | 157:e7ca05fa8600 | 490 | /** |
AnnaBridge | 157:e7ca05fa8600 | 491 | * @brief Enable a MPU region |
AnnaBridge | 157:e7ca05fa8600 | 492 | * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion |
AnnaBridge | 157:e7ca05fa8600 | 493 | * @param Region This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 494 | * @arg @ref LL_MPU_REGION_NUMBER0 |
AnnaBridge | 157:e7ca05fa8600 | 495 | * @arg @ref LL_MPU_REGION_NUMBER1 |
AnnaBridge | 157:e7ca05fa8600 | 496 | * @arg @ref LL_MPU_REGION_NUMBER2 |
AnnaBridge | 157:e7ca05fa8600 | 497 | * @arg @ref LL_MPU_REGION_NUMBER3 |
AnnaBridge | 157:e7ca05fa8600 | 498 | * @arg @ref LL_MPU_REGION_NUMBER4 |
AnnaBridge | 157:e7ca05fa8600 | 499 | * @arg @ref LL_MPU_REGION_NUMBER5 |
AnnaBridge | 157:e7ca05fa8600 | 500 | * @arg @ref LL_MPU_REGION_NUMBER6 |
AnnaBridge | 157:e7ca05fa8600 | 501 | * @arg @ref LL_MPU_REGION_NUMBER7 |
AnnaBridge | 157:e7ca05fa8600 | 502 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 503 | */ |
AnnaBridge | 157:e7ca05fa8600 | 504 | __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) |
AnnaBridge | 157:e7ca05fa8600 | 505 | { |
AnnaBridge | 157:e7ca05fa8600 | 506 | /* Set Region number */ |
AnnaBridge | 157:e7ca05fa8600 | 507 | WRITE_REG(MPU->RNR, Region); |
AnnaBridge | 157:e7ca05fa8600 | 508 | /* Enable the MPU region */ |
AnnaBridge | 157:e7ca05fa8600 | 509 | SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); |
AnnaBridge | 157:e7ca05fa8600 | 510 | } |
AnnaBridge | 157:e7ca05fa8600 | 511 | |
AnnaBridge | 157:e7ca05fa8600 | 512 | /** |
AnnaBridge | 157:e7ca05fa8600 | 513 | * @brief Configure and enable a region |
AnnaBridge | 157:e7ca05fa8600 | 514 | * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n |
AnnaBridge | 157:e7ca05fa8600 | 515 | * MPU_RBAR REGION LL_MPU_ConfigRegion\n |
AnnaBridge | 157:e7ca05fa8600 | 516 | * MPU_RBAR ADDR LL_MPU_ConfigRegion\n |
AnnaBridge | 157:e7ca05fa8600 | 517 | * MPU_RASR XN LL_MPU_ConfigRegion\n |
AnnaBridge | 157:e7ca05fa8600 | 518 | * MPU_RASR AP LL_MPU_ConfigRegion\n |
AnnaBridge | 157:e7ca05fa8600 | 519 | * MPU_RASR S LL_MPU_ConfigRegion\n |
AnnaBridge | 157:e7ca05fa8600 | 520 | * MPU_RASR C LL_MPU_ConfigRegion\n |
AnnaBridge | 157:e7ca05fa8600 | 521 | * MPU_RASR B LL_MPU_ConfigRegion\n |
AnnaBridge | 157:e7ca05fa8600 | 522 | * MPU_RASR SIZE LL_MPU_ConfigRegion |
AnnaBridge | 157:e7ca05fa8600 | 523 | * @param Region This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 524 | * @arg @ref LL_MPU_REGION_NUMBER0 |
AnnaBridge | 157:e7ca05fa8600 | 525 | * @arg @ref LL_MPU_REGION_NUMBER1 |
AnnaBridge | 157:e7ca05fa8600 | 526 | * @arg @ref LL_MPU_REGION_NUMBER2 |
AnnaBridge | 157:e7ca05fa8600 | 527 | * @arg @ref LL_MPU_REGION_NUMBER3 |
AnnaBridge | 157:e7ca05fa8600 | 528 | * @arg @ref LL_MPU_REGION_NUMBER4 |
AnnaBridge | 157:e7ca05fa8600 | 529 | * @arg @ref LL_MPU_REGION_NUMBER5 |
AnnaBridge | 157:e7ca05fa8600 | 530 | * @arg @ref LL_MPU_REGION_NUMBER6 |
AnnaBridge | 157:e7ca05fa8600 | 531 | * @arg @ref LL_MPU_REGION_NUMBER7 |
AnnaBridge | 157:e7ca05fa8600 | 532 | * @param Address Value of region base address |
AnnaBridge | 157:e7ca05fa8600 | 533 | * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF |
AnnaBridge | 157:e7ca05fa8600 | 534 | * @param Attributes This parameter can be a combination of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 535 | * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B |
AnnaBridge | 157:e7ca05fa8600 | 536 | * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB |
AnnaBridge | 157:e7ca05fa8600 | 537 | * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB |
AnnaBridge | 157:e7ca05fa8600 | 538 | * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB |
AnnaBridge | 157:e7ca05fa8600 | 539 | * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB |
AnnaBridge | 157:e7ca05fa8600 | 540 | * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB |
AnnaBridge | 157:e7ca05fa8600 | 541 | * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS |
AnnaBridge | 157:e7ca05fa8600 | 542 | * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO |
AnnaBridge | 157:e7ca05fa8600 | 543 | * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 |
AnnaBridge | 157:e7ca05fa8600 | 544 | * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE |
AnnaBridge | 157:e7ca05fa8600 | 545 | * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE |
AnnaBridge | 157:e7ca05fa8600 | 546 | * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE |
AnnaBridge | 157:e7ca05fa8600 | 547 | * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE |
AnnaBridge | 157:e7ca05fa8600 | 548 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 549 | */ |
AnnaBridge | 157:e7ca05fa8600 | 550 | __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) |
AnnaBridge | 157:e7ca05fa8600 | 551 | { |
AnnaBridge | 157:e7ca05fa8600 | 552 | /* Set Region number */ |
AnnaBridge | 157:e7ca05fa8600 | 553 | WRITE_REG(MPU->RNR, Region); |
AnnaBridge | 157:e7ca05fa8600 | 554 | /* Set base address */ |
AnnaBridge | 157:e7ca05fa8600 | 555 | WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); |
AnnaBridge | 157:e7ca05fa8600 | 556 | /* Configure MPU */ |
AnnaBridge | 157:e7ca05fa8600 | 557 | WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); |
AnnaBridge | 157:e7ca05fa8600 | 558 | } |
AnnaBridge | 157:e7ca05fa8600 | 559 | |
AnnaBridge | 157:e7ca05fa8600 | 560 | /** |
AnnaBridge | 157:e7ca05fa8600 | 561 | * @brief Disable a region |
AnnaBridge | 157:e7ca05fa8600 | 562 | * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n |
AnnaBridge | 157:e7ca05fa8600 | 563 | * MPU_RASR ENABLE LL_MPU_DisableRegion |
AnnaBridge | 157:e7ca05fa8600 | 564 | * @param Region This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 565 | * @arg @ref LL_MPU_REGION_NUMBER0 |
AnnaBridge | 157:e7ca05fa8600 | 566 | * @arg @ref LL_MPU_REGION_NUMBER1 |
AnnaBridge | 157:e7ca05fa8600 | 567 | * @arg @ref LL_MPU_REGION_NUMBER2 |
AnnaBridge | 157:e7ca05fa8600 | 568 | * @arg @ref LL_MPU_REGION_NUMBER3 |
AnnaBridge | 157:e7ca05fa8600 | 569 | * @arg @ref LL_MPU_REGION_NUMBER4 |
AnnaBridge | 157:e7ca05fa8600 | 570 | * @arg @ref LL_MPU_REGION_NUMBER5 |
AnnaBridge | 157:e7ca05fa8600 | 571 | * @arg @ref LL_MPU_REGION_NUMBER6 |
AnnaBridge | 157:e7ca05fa8600 | 572 | * @arg @ref LL_MPU_REGION_NUMBER7 |
AnnaBridge | 157:e7ca05fa8600 | 573 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 574 | */ |
AnnaBridge | 157:e7ca05fa8600 | 575 | __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) |
AnnaBridge | 157:e7ca05fa8600 | 576 | { |
AnnaBridge | 157:e7ca05fa8600 | 577 | /* Set Region number */ |
AnnaBridge | 157:e7ca05fa8600 | 578 | WRITE_REG(MPU->RNR, Region); |
AnnaBridge | 157:e7ca05fa8600 | 579 | /* Disable the MPU region */ |
AnnaBridge | 157:e7ca05fa8600 | 580 | CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); |
AnnaBridge | 157:e7ca05fa8600 | 581 | } |
AnnaBridge | 157:e7ca05fa8600 | 582 | |
AnnaBridge | 157:e7ca05fa8600 | 583 | /** |
AnnaBridge | 157:e7ca05fa8600 | 584 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 585 | */ |
AnnaBridge | 157:e7ca05fa8600 | 586 | |
AnnaBridge | 157:e7ca05fa8600 | 587 | #endif /* __MPU_PRESENT */ |
AnnaBridge | 157:e7ca05fa8600 | 588 | /** |
AnnaBridge | 157:e7ca05fa8600 | 589 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 590 | */ |
AnnaBridge | 157:e7ca05fa8600 | 591 | |
AnnaBridge | 157:e7ca05fa8600 | 592 | /** |
AnnaBridge | 157:e7ca05fa8600 | 593 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 594 | */ |
AnnaBridge | 157:e7ca05fa8600 | 595 | |
AnnaBridge | 157:e7ca05fa8600 | 596 | /** |
AnnaBridge | 157:e7ca05fa8600 | 597 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 598 | */ |
AnnaBridge | 157:e7ca05fa8600 | 599 | |
AnnaBridge | 157:e7ca05fa8600 | 600 | #ifdef __cplusplus |
AnnaBridge | 157:e7ca05fa8600 | 601 | } |
AnnaBridge | 157:e7ca05fa8600 | 602 | #endif |
AnnaBridge | 157:e7ca05fa8600 | 603 | |
AnnaBridge | 157:e7ca05fa8600 | 604 | #endif /* __STM32L0xx_LL_CORTEX_H */ |
AnnaBridge | 157:e7ca05fa8600 | 605 | |
AnnaBridge | 157:e7ca05fa8600 | 606 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |