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TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_MICRO/stm32f0xx_hal_tim.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f0xx_hal_tim.h |
AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of TIM HAL module. |
AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
AnnaBridge | 171:3a7713b1edbc | 8 | * |
AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
AnnaBridge | 171:3a7713b1edbc | 10 | * |
AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 32 | * |
AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 34 | */ |
AnnaBridge | 171:3a7713b1edbc | 35 | |
AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F0xx_HAL_TIM_H |
AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F0xx_HAL_TIM_H |
AnnaBridge | 171:3a7713b1edbc | 39 | |
AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
AnnaBridge | 171:3a7713b1edbc | 43 | |
AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f0xx_hal_def.h" |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32F0xx_HAL_Driver |
AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 49 | */ |
AnnaBridge | 171:3a7713b1edbc | 50 | |
AnnaBridge | 171:3a7713b1edbc | 51 | /** @addtogroup TIM |
AnnaBridge | 171:3a7713b1edbc | 52 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 53 | */ |
AnnaBridge | 171:3a7713b1edbc | 54 | |
AnnaBridge | 171:3a7713b1edbc | 55 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 56 | /** @defgroup TIM_Exported_Types TIM Exported Types |
AnnaBridge | 171:3a7713b1edbc | 57 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 58 | */ |
AnnaBridge | 171:3a7713b1edbc | 59 | /** |
AnnaBridge | 171:3a7713b1edbc | 60 | * @brief TIM Time base Configuration Structure definition |
AnnaBridge | 171:3a7713b1edbc | 61 | */ |
AnnaBridge | 171:3a7713b1edbc | 62 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 63 | { |
AnnaBridge | 171:3a7713b1edbc | 64 | uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
AnnaBridge | 171:3a7713b1edbc | 65 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
AnnaBridge | 171:3a7713b1edbc | 66 | |
AnnaBridge | 171:3a7713b1edbc | 67 | uint32_t CounterMode; /*!< Specifies the counter mode. |
AnnaBridge | 171:3a7713b1edbc | 68 | This parameter can be a value of @ref TIM_Counter_Mode */ |
AnnaBridge | 171:3a7713b1edbc | 69 | |
AnnaBridge | 171:3a7713b1edbc | 70 | uint32_t Period; /*!< Specifies the period value to be loaded into the active |
AnnaBridge | 171:3a7713b1edbc | 71 | Auto-Reload Register at the next update event. |
AnnaBridge | 171:3a7713b1edbc | 72 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ |
AnnaBridge | 171:3a7713b1edbc | 73 | |
AnnaBridge | 171:3a7713b1edbc | 74 | uint32_t ClockDivision; /*!< Specifies the clock division. |
AnnaBridge | 171:3a7713b1edbc | 75 | This parameter can be a value of @ref TIM_ClockDivision */ |
AnnaBridge | 171:3a7713b1edbc | 76 | |
AnnaBridge | 171:3a7713b1edbc | 77 | uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter |
AnnaBridge | 171:3a7713b1edbc | 78 | reaches zero, an update event is generated and counting restarts |
AnnaBridge | 171:3a7713b1edbc | 79 | from the RCR value (N). |
AnnaBridge | 171:3a7713b1edbc | 80 | This means in PWM mode that (N+1) corresponds to: |
AnnaBridge | 171:3a7713b1edbc | 81 | - the number of PWM periods in edge-aligned mode |
AnnaBridge | 171:3a7713b1edbc | 82 | - the number of half PWM period in center-aligned mode |
AnnaBridge | 171:3a7713b1edbc | 83 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. |
AnnaBridge | 171:3a7713b1edbc | 84 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 171:3a7713b1edbc | 85 | |
AnnaBridge | 171:3a7713b1edbc | 86 | uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. |
AnnaBridge | 171:3a7713b1edbc | 87 | This parameter can be a value of @ref TIM_AutoReloadPreload */ |
AnnaBridge | 171:3a7713b1edbc | 88 | } TIM_Base_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 89 | |
AnnaBridge | 171:3a7713b1edbc | 90 | /** |
AnnaBridge | 171:3a7713b1edbc | 91 | * @brief TIM Output Compare Configuration Structure definition |
AnnaBridge | 171:3a7713b1edbc | 92 | */ |
AnnaBridge | 171:3a7713b1edbc | 93 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 94 | { |
AnnaBridge | 171:3a7713b1edbc | 95 | uint32_t OCMode; /*!< Specifies the TIM mode. |
AnnaBridge | 171:3a7713b1edbc | 96 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
AnnaBridge | 171:3a7713b1edbc | 97 | |
AnnaBridge | 171:3a7713b1edbc | 98 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
AnnaBridge | 171:3a7713b1edbc | 99 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
AnnaBridge | 171:3a7713b1edbc | 100 | |
AnnaBridge | 171:3a7713b1edbc | 101 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
AnnaBridge | 171:3a7713b1edbc | 102 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
AnnaBridge | 171:3a7713b1edbc | 103 | |
AnnaBridge | 171:3a7713b1edbc | 104 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
AnnaBridge | 171:3a7713b1edbc | 105 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
AnnaBridge | 171:3a7713b1edbc | 106 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 171:3a7713b1edbc | 107 | |
AnnaBridge | 171:3a7713b1edbc | 108 | uint32_t OCFastMode; /*!< Specifies the Fast mode state. |
AnnaBridge | 171:3a7713b1edbc | 109 | This parameter can be a value of @ref TIM_Output_Fast_State |
AnnaBridge | 171:3a7713b1edbc | 110 | @note This parameter is valid only in PWM1 and PWM2 mode. */ |
AnnaBridge | 171:3a7713b1edbc | 111 | |
AnnaBridge | 171:3a7713b1edbc | 112 | |
AnnaBridge | 171:3a7713b1edbc | 113 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
AnnaBridge | 171:3a7713b1edbc | 114 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
AnnaBridge | 171:3a7713b1edbc | 115 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 171:3a7713b1edbc | 116 | |
AnnaBridge | 171:3a7713b1edbc | 117 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
AnnaBridge | 171:3a7713b1edbc | 118 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
AnnaBridge | 171:3a7713b1edbc | 119 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 171:3a7713b1edbc | 120 | } TIM_OC_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 121 | |
AnnaBridge | 171:3a7713b1edbc | 122 | /** |
AnnaBridge | 171:3a7713b1edbc | 123 | * @brief TIM One Pulse Mode Configuration Structure definition |
AnnaBridge | 171:3a7713b1edbc | 124 | */ |
AnnaBridge | 171:3a7713b1edbc | 125 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 126 | { |
AnnaBridge | 171:3a7713b1edbc | 127 | uint32_t OCMode; /*!< Specifies the TIM mode. |
AnnaBridge | 171:3a7713b1edbc | 128 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
AnnaBridge | 171:3a7713b1edbc | 129 | |
AnnaBridge | 171:3a7713b1edbc | 130 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
AnnaBridge | 171:3a7713b1edbc | 131 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
AnnaBridge | 171:3a7713b1edbc | 132 | |
AnnaBridge | 171:3a7713b1edbc | 133 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
AnnaBridge | 171:3a7713b1edbc | 134 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
AnnaBridge | 171:3a7713b1edbc | 135 | |
AnnaBridge | 171:3a7713b1edbc | 136 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
AnnaBridge | 171:3a7713b1edbc | 137 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
AnnaBridge | 171:3a7713b1edbc | 138 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 171:3a7713b1edbc | 139 | |
AnnaBridge | 171:3a7713b1edbc | 140 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
AnnaBridge | 171:3a7713b1edbc | 141 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
AnnaBridge | 171:3a7713b1edbc | 142 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 171:3a7713b1edbc | 143 | |
AnnaBridge | 171:3a7713b1edbc | 144 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
AnnaBridge | 171:3a7713b1edbc | 145 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
AnnaBridge | 171:3a7713b1edbc | 146 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 171:3a7713b1edbc | 147 | |
AnnaBridge | 171:3a7713b1edbc | 148 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 171:3a7713b1edbc | 149 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
AnnaBridge | 171:3a7713b1edbc | 150 | |
AnnaBridge | 171:3a7713b1edbc | 151 | uint32_t ICSelection; /*!< Specifies the input. |
AnnaBridge | 171:3a7713b1edbc | 152 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
AnnaBridge | 171:3a7713b1edbc | 153 | |
AnnaBridge | 171:3a7713b1edbc | 154 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
AnnaBridge | 171:3a7713b1edbc | 155 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 171:3a7713b1edbc | 156 | } TIM_OnePulse_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 157 | |
AnnaBridge | 171:3a7713b1edbc | 158 | |
AnnaBridge | 171:3a7713b1edbc | 159 | /** |
AnnaBridge | 171:3a7713b1edbc | 160 | * @brief TIM Input Capture Configuration Structure definition |
AnnaBridge | 171:3a7713b1edbc | 161 | */ |
AnnaBridge | 171:3a7713b1edbc | 162 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 163 | { |
AnnaBridge | 171:3a7713b1edbc | 164 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 171:3a7713b1edbc | 165 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
AnnaBridge | 171:3a7713b1edbc | 166 | |
AnnaBridge | 171:3a7713b1edbc | 167 | uint32_t ICSelection; /*!< Specifies the input. |
AnnaBridge | 171:3a7713b1edbc | 168 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
AnnaBridge | 171:3a7713b1edbc | 169 | |
AnnaBridge | 171:3a7713b1edbc | 170 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
AnnaBridge | 171:3a7713b1edbc | 171 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
AnnaBridge | 171:3a7713b1edbc | 172 | |
AnnaBridge | 171:3a7713b1edbc | 173 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
AnnaBridge | 171:3a7713b1edbc | 174 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 171:3a7713b1edbc | 175 | } TIM_IC_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 176 | |
AnnaBridge | 171:3a7713b1edbc | 177 | /** |
AnnaBridge | 171:3a7713b1edbc | 178 | * @brief TIM Encoder Configuration Structure definition |
AnnaBridge | 171:3a7713b1edbc | 179 | */ |
AnnaBridge | 171:3a7713b1edbc | 180 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 181 | { |
AnnaBridge | 171:3a7713b1edbc | 182 | uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 171:3a7713b1edbc | 183 | This parameter can be a value of @ref TIM_Encoder_Mode */ |
AnnaBridge | 171:3a7713b1edbc | 184 | |
AnnaBridge | 171:3a7713b1edbc | 185 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 171:3a7713b1edbc | 186 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
AnnaBridge | 171:3a7713b1edbc | 187 | |
AnnaBridge | 171:3a7713b1edbc | 188 | uint32_t IC1Selection; /*!< Specifies the input. |
AnnaBridge | 171:3a7713b1edbc | 189 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
AnnaBridge | 171:3a7713b1edbc | 190 | |
AnnaBridge | 171:3a7713b1edbc | 191 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. |
AnnaBridge | 171:3a7713b1edbc | 192 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
AnnaBridge | 171:3a7713b1edbc | 193 | |
AnnaBridge | 171:3a7713b1edbc | 194 | uint32_t IC1Filter; /*!< Specifies the input capture filter. |
AnnaBridge | 171:3a7713b1edbc | 195 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 171:3a7713b1edbc | 196 | |
AnnaBridge | 171:3a7713b1edbc | 197 | uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 171:3a7713b1edbc | 198 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
AnnaBridge | 171:3a7713b1edbc | 199 | |
AnnaBridge | 171:3a7713b1edbc | 200 | uint32_t IC2Selection; /*!< Specifies the input. |
AnnaBridge | 171:3a7713b1edbc | 201 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
AnnaBridge | 171:3a7713b1edbc | 202 | |
AnnaBridge | 171:3a7713b1edbc | 203 | uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. |
AnnaBridge | 171:3a7713b1edbc | 204 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
AnnaBridge | 171:3a7713b1edbc | 205 | |
AnnaBridge | 171:3a7713b1edbc | 206 | uint32_t IC2Filter; /*!< Specifies the input capture filter. |
AnnaBridge | 171:3a7713b1edbc | 207 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 171:3a7713b1edbc | 208 | } TIM_Encoder_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 209 | |
AnnaBridge | 171:3a7713b1edbc | 210 | |
AnnaBridge | 171:3a7713b1edbc | 211 | /** |
AnnaBridge | 171:3a7713b1edbc | 212 | * @brief TIM Clock Configuration Handle Structure definition |
AnnaBridge | 171:3a7713b1edbc | 213 | */ |
AnnaBridge | 171:3a7713b1edbc | 214 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 215 | { |
AnnaBridge | 171:3a7713b1edbc | 216 | uint32_t ClockSource; /*!< TIM clock sources |
AnnaBridge | 171:3a7713b1edbc | 217 | This parameter can be a value of @ref TIM_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 218 | uint32_t ClockPolarity; /*!< TIM clock polarity |
AnnaBridge | 171:3a7713b1edbc | 219 | This parameter can be a value of @ref TIM_Clock_Polarity */ |
AnnaBridge | 171:3a7713b1edbc | 220 | uint32_t ClockPrescaler; /*!< TIM clock prescaler |
AnnaBridge | 171:3a7713b1edbc | 221 | This parameter can be a value of @ref TIM_Clock_Prescaler */ |
AnnaBridge | 171:3a7713b1edbc | 222 | uint32_t ClockFilter; /*!< TIM clock filter |
AnnaBridge | 171:3a7713b1edbc | 223 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 171:3a7713b1edbc | 224 | }TIM_ClockConfigTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 225 | |
AnnaBridge | 171:3a7713b1edbc | 226 | /** |
AnnaBridge | 171:3a7713b1edbc | 227 | * @brief TIM Clear Input Configuration Handle Structure definition |
AnnaBridge | 171:3a7713b1edbc | 228 | */ |
AnnaBridge | 171:3a7713b1edbc | 229 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 230 | { |
AnnaBridge | 171:3a7713b1edbc | 231 | uint32_t ClearInputState; /*!< TIM clear Input state |
AnnaBridge | 171:3a7713b1edbc | 232 | This parameter can be ENABLE or DISABLE */ |
AnnaBridge | 171:3a7713b1edbc | 233 | uint32_t ClearInputSource; /*!< TIM clear Input sources |
AnnaBridge | 171:3a7713b1edbc | 234 | This parameter can be a value of @ref TIMEx_Clock_Clear_Input_Source */ |
AnnaBridge | 171:3a7713b1edbc | 235 | uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity |
AnnaBridge | 171:3a7713b1edbc | 236 | This parameter can be a value of @ref TIM_ClearInput_Polarity */ |
AnnaBridge | 171:3a7713b1edbc | 237 | uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler |
AnnaBridge | 171:3a7713b1edbc | 238 | This parameter can be a value of @ref TIM_ClearInput_Prescaler */ |
AnnaBridge | 171:3a7713b1edbc | 239 | uint32_t ClearInputFilter; /*!< TIM Clear Input filter |
AnnaBridge | 171:3a7713b1edbc | 240 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 171:3a7713b1edbc | 241 | }TIM_ClearInputConfigTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 242 | |
AnnaBridge | 171:3a7713b1edbc | 243 | /** |
AnnaBridge | 171:3a7713b1edbc | 244 | * @brief TIM Slave configuration Structure definition |
AnnaBridge | 171:3a7713b1edbc | 245 | */ |
AnnaBridge | 171:3a7713b1edbc | 246 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 247 | uint32_t SlaveMode; /*!< Slave mode selection |
AnnaBridge | 171:3a7713b1edbc | 248 | This parameter can be a value of @ref TIM_Slave_Mode */ |
AnnaBridge | 171:3a7713b1edbc | 249 | uint32_t InputTrigger; /*!< Input Trigger source |
AnnaBridge | 171:3a7713b1edbc | 250 | This parameter can be a value of @ref TIM_Trigger_Selection */ |
AnnaBridge | 171:3a7713b1edbc | 251 | uint32_t TriggerPolarity; /*!< Input Trigger polarity |
AnnaBridge | 171:3a7713b1edbc | 252 | This parameter can be a value of @ref TIM_Trigger_Polarity */ |
AnnaBridge | 171:3a7713b1edbc | 253 | uint32_t TriggerPrescaler; /*!< Input trigger prescaler |
AnnaBridge | 171:3a7713b1edbc | 254 | This parameter can be a value of @ref TIM_Trigger_Prescaler */ |
AnnaBridge | 171:3a7713b1edbc | 255 | uint32_t TriggerFilter; /*!< Input trigger filter |
AnnaBridge | 171:3a7713b1edbc | 256 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 171:3a7713b1edbc | 257 | |
AnnaBridge | 171:3a7713b1edbc | 258 | }TIM_SlaveConfigTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 259 | |
AnnaBridge | 171:3a7713b1edbc | 260 | /** |
AnnaBridge | 171:3a7713b1edbc | 261 | * @brief HAL State structures definition |
AnnaBridge | 171:3a7713b1edbc | 262 | */ |
AnnaBridge | 171:3a7713b1edbc | 263 | typedef enum |
AnnaBridge | 171:3a7713b1edbc | 264 | { |
AnnaBridge | 171:3a7713b1edbc | 265 | HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ |
AnnaBridge | 171:3a7713b1edbc | 266 | HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
AnnaBridge | 171:3a7713b1edbc | 267 | HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ |
AnnaBridge | 171:3a7713b1edbc | 268 | HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ |
AnnaBridge | 171:3a7713b1edbc | 269 | HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ |
AnnaBridge | 171:3a7713b1edbc | 270 | }HAL_TIM_StateTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 271 | |
AnnaBridge | 171:3a7713b1edbc | 272 | /** |
AnnaBridge | 171:3a7713b1edbc | 273 | * @brief HAL Active channel structures definition |
AnnaBridge | 171:3a7713b1edbc | 274 | */ |
AnnaBridge | 171:3a7713b1edbc | 275 | typedef enum |
AnnaBridge | 171:3a7713b1edbc | 276 | { |
AnnaBridge | 171:3a7713b1edbc | 277 | HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ |
AnnaBridge | 171:3a7713b1edbc | 278 | HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ |
AnnaBridge | 171:3a7713b1edbc | 279 | HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ |
AnnaBridge | 171:3a7713b1edbc | 280 | HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ |
AnnaBridge | 171:3a7713b1edbc | 281 | HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ |
AnnaBridge | 171:3a7713b1edbc | 282 | }HAL_TIM_ActiveChannel; |
AnnaBridge | 171:3a7713b1edbc | 283 | |
AnnaBridge | 171:3a7713b1edbc | 284 | /** |
AnnaBridge | 171:3a7713b1edbc | 285 | * @brief TIM Time Base Handle Structure definition |
AnnaBridge | 171:3a7713b1edbc | 286 | */ |
AnnaBridge | 171:3a7713b1edbc | 287 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 288 | { |
AnnaBridge | 171:3a7713b1edbc | 289 | TIM_TypeDef *Instance; /*!< Register base address */ |
AnnaBridge | 171:3a7713b1edbc | 290 | TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ |
AnnaBridge | 171:3a7713b1edbc | 291 | HAL_TIM_ActiveChannel Channel; /*!< Active channel */ |
AnnaBridge | 171:3a7713b1edbc | 292 | DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array |
AnnaBridge | 171:3a7713b1edbc | 293 | This array is accessed by a @ref TIM_DMA_Handle_index */ |
AnnaBridge | 171:3a7713b1edbc | 294 | HAL_LockTypeDef Lock; /*!< Locking object */ |
AnnaBridge | 171:3a7713b1edbc | 295 | __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ |
AnnaBridge | 171:3a7713b1edbc | 296 | }TIM_HandleTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 297 | |
AnnaBridge | 171:3a7713b1edbc | 298 | /** |
AnnaBridge | 171:3a7713b1edbc | 299 | * @} |
AnnaBridge | 171:3a7713b1edbc | 300 | */ |
AnnaBridge | 171:3a7713b1edbc | 301 | |
AnnaBridge | 171:3a7713b1edbc | 302 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 303 | /** @defgroup TIM_Exported_Constants TIM Exported Constants |
AnnaBridge | 171:3a7713b1edbc | 304 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 305 | */ |
AnnaBridge | 171:3a7713b1edbc | 306 | |
AnnaBridge | 171:3a7713b1edbc | 307 | /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity |
AnnaBridge | 171:3a7713b1edbc | 308 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 309 | */ |
AnnaBridge | 171:3a7713b1edbc | 310 | #define TIM_INPUTCHANNELPOLARITY_RISING (0x00000000U) /*!< Polarity for TIx source */ |
AnnaBridge | 171:3a7713b1edbc | 311 | #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ |
AnnaBridge | 171:3a7713b1edbc | 312 | #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ |
AnnaBridge | 171:3a7713b1edbc | 313 | /** |
AnnaBridge | 171:3a7713b1edbc | 314 | * @} |
AnnaBridge | 171:3a7713b1edbc | 315 | */ |
AnnaBridge | 171:3a7713b1edbc | 316 | |
AnnaBridge | 171:3a7713b1edbc | 317 | /** @defgroup TIM_ETR_Polarity TIM ETR Polarity |
AnnaBridge | 171:3a7713b1edbc | 318 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 319 | */ |
AnnaBridge | 171:3a7713b1edbc | 320 | #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ |
AnnaBridge | 171:3a7713b1edbc | 321 | #define TIM_ETRPOLARITY_NONINVERTED (0x0000U) /*!< Polarity for ETR source */ |
AnnaBridge | 171:3a7713b1edbc | 322 | /** |
AnnaBridge | 171:3a7713b1edbc | 323 | * @} |
AnnaBridge | 171:3a7713b1edbc | 324 | */ |
AnnaBridge | 171:3a7713b1edbc | 325 | |
AnnaBridge | 171:3a7713b1edbc | 326 | /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler |
AnnaBridge | 171:3a7713b1edbc | 327 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 328 | */ |
AnnaBridge | 171:3a7713b1edbc | 329 | #define TIM_ETRPRESCALER_DIV1 (0x0000U) /*!< No prescaler is used */ |
AnnaBridge | 171:3a7713b1edbc | 330 | #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ |
AnnaBridge | 171:3a7713b1edbc | 331 | #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ |
AnnaBridge | 171:3a7713b1edbc | 332 | #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ |
AnnaBridge | 171:3a7713b1edbc | 333 | /** |
AnnaBridge | 171:3a7713b1edbc | 334 | * @} |
AnnaBridge | 171:3a7713b1edbc | 335 | */ |
AnnaBridge | 171:3a7713b1edbc | 336 | |
AnnaBridge | 171:3a7713b1edbc | 337 | /** @defgroup TIM_Counter_Mode TIM Counter Mode |
AnnaBridge | 171:3a7713b1edbc | 338 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 339 | */ |
AnnaBridge | 171:3a7713b1edbc | 340 | #define TIM_COUNTERMODE_UP (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 341 | #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR |
AnnaBridge | 171:3a7713b1edbc | 342 | #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 |
AnnaBridge | 171:3a7713b1edbc | 343 | #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 |
AnnaBridge | 171:3a7713b1edbc | 344 | #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS |
AnnaBridge | 171:3a7713b1edbc | 345 | /** |
AnnaBridge | 171:3a7713b1edbc | 346 | * @} |
AnnaBridge | 171:3a7713b1edbc | 347 | */ |
AnnaBridge | 171:3a7713b1edbc | 348 | |
AnnaBridge | 171:3a7713b1edbc | 349 | /** @defgroup TIM_ClockDivision TIM Clock Division |
AnnaBridge | 171:3a7713b1edbc | 350 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 351 | */ |
AnnaBridge | 171:3a7713b1edbc | 352 | #define TIM_CLOCKDIVISION_DIV1 (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 353 | #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) |
AnnaBridge | 171:3a7713b1edbc | 354 | #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) |
AnnaBridge | 171:3a7713b1edbc | 355 | /** |
AnnaBridge | 171:3a7713b1edbc | 356 | * @} |
AnnaBridge | 171:3a7713b1edbc | 357 | */ |
AnnaBridge | 171:3a7713b1edbc | 358 | |
AnnaBridge | 171:3a7713b1edbc | 359 | /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload |
AnnaBridge | 171:3a7713b1edbc | 360 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 361 | */ |
AnnaBridge | 171:3a7713b1edbc | 362 | #define TIM_AUTORELOAD_PRELOAD_DISABLE (0x0000U) /*!< TIMx_ARR register is not buffered */ |
AnnaBridge | 171:3a7713b1edbc | 363 | #define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */ |
AnnaBridge | 171:3a7713b1edbc | 364 | /** |
AnnaBridge | 171:3a7713b1edbc | 365 | * @} |
AnnaBridge | 171:3a7713b1edbc | 366 | */ |
AnnaBridge | 171:3a7713b1edbc | 367 | |
AnnaBridge | 171:3a7713b1edbc | 368 | /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes |
AnnaBridge | 171:3a7713b1edbc | 369 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 370 | */ |
AnnaBridge | 171:3a7713b1edbc | 371 | #define TIM_OCMODE_TIMING (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 372 | #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) |
AnnaBridge | 171:3a7713b1edbc | 373 | #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) |
AnnaBridge | 171:3a7713b1edbc | 374 | #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) |
AnnaBridge | 171:3a7713b1edbc | 375 | #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) |
AnnaBridge | 171:3a7713b1edbc | 376 | #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) |
AnnaBridge | 171:3a7713b1edbc | 377 | #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) |
AnnaBridge | 171:3a7713b1edbc | 378 | #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) |
AnnaBridge | 171:3a7713b1edbc | 379 | /** |
AnnaBridge | 171:3a7713b1edbc | 380 | * @} |
AnnaBridge | 171:3a7713b1edbc | 381 | */ |
AnnaBridge | 171:3a7713b1edbc | 382 | |
AnnaBridge | 171:3a7713b1edbc | 383 | /** @defgroup TIM_Output_Fast_State TIM Output Fast State |
AnnaBridge | 171:3a7713b1edbc | 384 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 385 | */ |
AnnaBridge | 171:3a7713b1edbc | 386 | #define TIM_OCFAST_DISABLE (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 387 | #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) |
AnnaBridge | 171:3a7713b1edbc | 388 | /** |
AnnaBridge | 171:3a7713b1edbc | 389 | * @} |
AnnaBridge | 171:3a7713b1edbc | 390 | */ |
AnnaBridge | 171:3a7713b1edbc | 391 | |
AnnaBridge | 171:3a7713b1edbc | 392 | /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity |
AnnaBridge | 171:3a7713b1edbc | 393 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 394 | */ |
AnnaBridge | 171:3a7713b1edbc | 395 | #define TIM_OCPOLARITY_HIGH (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 396 | #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) |
AnnaBridge | 171:3a7713b1edbc | 397 | /** |
AnnaBridge | 171:3a7713b1edbc | 398 | * @} |
AnnaBridge | 171:3a7713b1edbc | 399 | */ |
AnnaBridge | 171:3a7713b1edbc | 400 | |
AnnaBridge | 171:3a7713b1edbc | 401 | /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity |
AnnaBridge | 171:3a7713b1edbc | 402 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 403 | */ |
AnnaBridge | 171:3a7713b1edbc | 404 | #define TIM_OCNPOLARITY_HIGH (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 405 | #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) |
AnnaBridge | 171:3a7713b1edbc | 406 | /** |
AnnaBridge | 171:3a7713b1edbc | 407 | * @} |
AnnaBridge | 171:3a7713b1edbc | 408 | */ |
AnnaBridge | 171:3a7713b1edbc | 409 | |
AnnaBridge | 171:3a7713b1edbc | 410 | /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State |
AnnaBridge | 171:3a7713b1edbc | 411 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 412 | */ |
AnnaBridge | 171:3a7713b1edbc | 413 | #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) |
AnnaBridge | 171:3a7713b1edbc | 414 | #define TIM_OCIDLESTATE_RESET (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 415 | /** |
AnnaBridge | 171:3a7713b1edbc | 416 | * @} |
AnnaBridge | 171:3a7713b1edbc | 417 | */ |
AnnaBridge | 171:3a7713b1edbc | 418 | |
AnnaBridge | 171:3a7713b1edbc | 419 | /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State |
AnnaBridge | 171:3a7713b1edbc | 420 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 421 | */ |
AnnaBridge | 171:3a7713b1edbc | 422 | #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) |
AnnaBridge | 171:3a7713b1edbc | 423 | #define TIM_OCNIDLESTATE_RESET (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 424 | /** |
AnnaBridge | 171:3a7713b1edbc | 425 | * @} |
AnnaBridge | 171:3a7713b1edbc | 426 | */ |
AnnaBridge | 171:3a7713b1edbc | 427 | |
AnnaBridge | 171:3a7713b1edbc | 428 | /** @defgroup TIM_Channel TIM Channel |
AnnaBridge | 171:3a7713b1edbc | 429 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 430 | */ |
AnnaBridge | 171:3a7713b1edbc | 431 | #define TIM_CHANNEL_1 (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 432 | #define TIM_CHANNEL_2 (0x0004U) |
AnnaBridge | 171:3a7713b1edbc | 433 | #define TIM_CHANNEL_3 (0x0008U) |
AnnaBridge | 171:3a7713b1edbc | 434 | #define TIM_CHANNEL_4 (0x000CU) |
AnnaBridge | 171:3a7713b1edbc | 435 | #define TIM_CHANNEL_ALL (0x0018U) |
AnnaBridge | 171:3a7713b1edbc | 436 | /** |
AnnaBridge | 171:3a7713b1edbc | 437 | * @} |
AnnaBridge | 171:3a7713b1edbc | 438 | */ |
AnnaBridge | 171:3a7713b1edbc | 439 | |
AnnaBridge | 171:3a7713b1edbc | 440 | /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity |
AnnaBridge | 171:3a7713b1edbc | 441 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 442 | */ |
AnnaBridge | 171:3a7713b1edbc | 443 | #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING |
AnnaBridge | 171:3a7713b1edbc | 444 | #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING |
AnnaBridge | 171:3a7713b1edbc | 445 | #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE |
AnnaBridge | 171:3a7713b1edbc | 446 | /** |
AnnaBridge | 171:3a7713b1edbc | 447 | * @} |
AnnaBridge | 171:3a7713b1edbc | 448 | */ |
AnnaBridge | 171:3a7713b1edbc | 449 | |
AnnaBridge | 171:3a7713b1edbc | 450 | /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection |
AnnaBridge | 171:3a7713b1edbc | 451 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 452 | */ |
AnnaBridge | 171:3a7713b1edbc | 453 | #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
AnnaBridge | 171:3a7713b1edbc | 454 | connected to IC1, IC2, IC3 or IC4, respectively */ |
AnnaBridge | 171:3a7713b1edbc | 455 | #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
AnnaBridge | 171:3a7713b1edbc | 456 | connected to IC2, IC1, IC4 or IC3, respectively */ |
AnnaBridge | 171:3a7713b1edbc | 457 | #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ |
AnnaBridge | 171:3a7713b1edbc | 458 | /** |
AnnaBridge | 171:3a7713b1edbc | 459 | * @} |
AnnaBridge | 171:3a7713b1edbc | 460 | */ |
AnnaBridge | 171:3a7713b1edbc | 461 | |
AnnaBridge | 171:3a7713b1edbc | 462 | /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler |
AnnaBridge | 171:3a7713b1edbc | 463 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 464 | */ |
AnnaBridge | 171:3a7713b1edbc | 465 | #define TIM_ICPSC_DIV1 (0x0000U) /*!< Capture performed each time an edge is detected on the capture input */ |
AnnaBridge | 171:3a7713b1edbc | 466 | #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ |
AnnaBridge | 171:3a7713b1edbc | 467 | #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ |
AnnaBridge | 171:3a7713b1edbc | 468 | #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ |
AnnaBridge | 171:3a7713b1edbc | 469 | /** |
AnnaBridge | 171:3a7713b1edbc | 470 | * @} |
AnnaBridge | 171:3a7713b1edbc | 471 | */ |
AnnaBridge | 171:3a7713b1edbc | 472 | |
AnnaBridge | 171:3a7713b1edbc | 473 | /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode |
AnnaBridge | 171:3a7713b1edbc | 474 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 475 | */ |
AnnaBridge | 171:3a7713b1edbc | 476 | #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) |
AnnaBridge | 171:3a7713b1edbc | 477 | #define TIM_OPMODE_REPETITIVE (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 478 | /** |
AnnaBridge | 171:3a7713b1edbc | 479 | * @} |
AnnaBridge | 171:3a7713b1edbc | 480 | */ |
AnnaBridge | 171:3a7713b1edbc | 481 | |
AnnaBridge | 171:3a7713b1edbc | 482 | /** @defgroup TIM_Encoder_Mode TIM Encoder Mode |
AnnaBridge | 171:3a7713b1edbc | 483 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 484 | */ |
AnnaBridge | 171:3a7713b1edbc | 485 | #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) |
AnnaBridge | 171:3a7713b1edbc | 486 | #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) |
AnnaBridge | 171:3a7713b1edbc | 487 | #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) |
AnnaBridge | 171:3a7713b1edbc | 488 | /** |
AnnaBridge | 171:3a7713b1edbc | 489 | * @} |
AnnaBridge | 171:3a7713b1edbc | 490 | */ |
AnnaBridge | 171:3a7713b1edbc | 491 | |
AnnaBridge | 171:3a7713b1edbc | 492 | /** @defgroup TIM_Interrupt_definition TIM Interrupt Definition |
AnnaBridge | 171:3a7713b1edbc | 493 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 494 | */ |
AnnaBridge | 171:3a7713b1edbc | 495 | #define TIM_IT_UPDATE (TIM_DIER_UIE) |
AnnaBridge | 171:3a7713b1edbc | 496 | #define TIM_IT_CC1 (TIM_DIER_CC1IE) |
AnnaBridge | 171:3a7713b1edbc | 497 | #define TIM_IT_CC2 (TIM_DIER_CC2IE) |
AnnaBridge | 171:3a7713b1edbc | 498 | #define TIM_IT_CC3 (TIM_DIER_CC3IE) |
AnnaBridge | 171:3a7713b1edbc | 499 | #define TIM_IT_CC4 (TIM_DIER_CC4IE) |
AnnaBridge | 171:3a7713b1edbc | 500 | #define TIM_IT_COM (TIM_DIER_COMIE) |
AnnaBridge | 171:3a7713b1edbc | 501 | #define TIM_IT_TRIGGER (TIM_DIER_TIE) |
AnnaBridge | 171:3a7713b1edbc | 502 | #define TIM_IT_BREAK (TIM_DIER_BIE) |
AnnaBridge | 171:3a7713b1edbc | 503 | /** |
AnnaBridge | 171:3a7713b1edbc | 504 | * @} |
AnnaBridge | 171:3a7713b1edbc | 505 | */ |
AnnaBridge | 171:3a7713b1edbc | 506 | |
AnnaBridge | 171:3a7713b1edbc | 507 | /** @defgroup TIM_Commutation_Source TIM Commutation Source |
AnnaBridge | 171:3a7713b1edbc | 508 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 509 | */ |
AnnaBridge | 171:3a7713b1edbc | 510 | #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) |
AnnaBridge | 171:3a7713b1edbc | 511 | #define TIM_COMMUTATION_SOFTWARE (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 512 | |
AnnaBridge | 171:3a7713b1edbc | 513 | /** |
AnnaBridge | 171:3a7713b1edbc | 514 | * @} |
AnnaBridge | 171:3a7713b1edbc | 515 | */ |
AnnaBridge | 171:3a7713b1edbc | 516 | |
AnnaBridge | 171:3a7713b1edbc | 517 | /** @defgroup TIM_DMA_sources TIM DMA Sources |
AnnaBridge | 171:3a7713b1edbc | 518 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 519 | */ |
AnnaBridge | 171:3a7713b1edbc | 520 | #define TIM_DMA_UPDATE (TIM_DIER_UDE) |
AnnaBridge | 171:3a7713b1edbc | 521 | #define TIM_DMA_CC1 (TIM_DIER_CC1DE) |
AnnaBridge | 171:3a7713b1edbc | 522 | #define TIM_DMA_CC2 (TIM_DIER_CC2DE) |
AnnaBridge | 171:3a7713b1edbc | 523 | #define TIM_DMA_CC3 (TIM_DIER_CC3DE) |
AnnaBridge | 171:3a7713b1edbc | 524 | #define TIM_DMA_CC4 (TIM_DIER_CC4DE) |
AnnaBridge | 171:3a7713b1edbc | 525 | #define TIM_DMA_COM (TIM_DIER_COMDE) |
AnnaBridge | 171:3a7713b1edbc | 526 | #define TIM_DMA_TRIGGER (TIM_DIER_TDE) |
AnnaBridge | 171:3a7713b1edbc | 527 | /** |
AnnaBridge | 171:3a7713b1edbc | 528 | * @} |
AnnaBridge | 171:3a7713b1edbc | 529 | */ |
AnnaBridge | 171:3a7713b1edbc | 530 | |
AnnaBridge | 171:3a7713b1edbc | 531 | /** @defgroup TIM_Event_Source TIM Event Source |
AnnaBridge | 171:3a7713b1edbc | 532 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 533 | */ |
AnnaBridge | 171:3a7713b1edbc | 534 | #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG |
AnnaBridge | 171:3a7713b1edbc | 535 | #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G |
AnnaBridge | 171:3a7713b1edbc | 536 | #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G |
AnnaBridge | 171:3a7713b1edbc | 537 | #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G |
AnnaBridge | 171:3a7713b1edbc | 538 | #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G |
AnnaBridge | 171:3a7713b1edbc | 539 | #define TIM_EVENTSOURCE_COM TIM_EGR_COMG |
AnnaBridge | 171:3a7713b1edbc | 540 | #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG |
AnnaBridge | 171:3a7713b1edbc | 541 | #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG |
AnnaBridge | 171:3a7713b1edbc | 542 | /** |
AnnaBridge | 171:3a7713b1edbc | 543 | * @} |
AnnaBridge | 171:3a7713b1edbc | 544 | */ |
AnnaBridge | 171:3a7713b1edbc | 545 | |
AnnaBridge | 171:3a7713b1edbc | 546 | /** @defgroup TIM_Flag_definition TIM Flag Definition |
AnnaBridge | 171:3a7713b1edbc | 547 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 548 | */ |
AnnaBridge | 171:3a7713b1edbc | 549 | #define TIM_FLAG_UPDATE (TIM_SR_UIF) |
AnnaBridge | 171:3a7713b1edbc | 550 | #define TIM_FLAG_CC1 (TIM_SR_CC1IF) |
AnnaBridge | 171:3a7713b1edbc | 551 | #define TIM_FLAG_CC2 (TIM_SR_CC2IF) |
AnnaBridge | 171:3a7713b1edbc | 552 | #define TIM_FLAG_CC3 (TIM_SR_CC3IF) |
AnnaBridge | 171:3a7713b1edbc | 553 | #define TIM_FLAG_CC4 (TIM_SR_CC4IF) |
AnnaBridge | 171:3a7713b1edbc | 554 | #define TIM_FLAG_COM (TIM_SR_COMIF) |
AnnaBridge | 171:3a7713b1edbc | 555 | #define TIM_FLAG_TRIGGER (TIM_SR_TIF) |
AnnaBridge | 171:3a7713b1edbc | 556 | #define TIM_FLAG_BREAK (TIM_SR_BIF) |
AnnaBridge | 171:3a7713b1edbc | 557 | #define TIM_FLAG_CC1OF (TIM_SR_CC1OF) |
AnnaBridge | 171:3a7713b1edbc | 558 | #define TIM_FLAG_CC2OF (TIM_SR_CC2OF) |
AnnaBridge | 171:3a7713b1edbc | 559 | #define TIM_FLAG_CC3OF (TIM_SR_CC3OF) |
AnnaBridge | 171:3a7713b1edbc | 560 | #define TIM_FLAG_CC4OF (TIM_SR_CC4OF) |
AnnaBridge | 171:3a7713b1edbc | 561 | /** |
AnnaBridge | 171:3a7713b1edbc | 562 | * @} |
AnnaBridge | 171:3a7713b1edbc | 563 | */ |
AnnaBridge | 171:3a7713b1edbc | 564 | |
AnnaBridge | 171:3a7713b1edbc | 565 | /** @defgroup TIM_Clock_Source TIM Clock Source |
AnnaBridge | 171:3a7713b1edbc | 566 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 567 | */ |
AnnaBridge | 171:3a7713b1edbc | 568 | #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) |
AnnaBridge | 171:3a7713b1edbc | 569 | #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) |
AnnaBridge | 171:3a7713b1edbc | 570 | #define TIM_CLOCKSOURCE_ITR0 (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 571 | #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) |
AnnaBridge | 171:3a7713b1edbc | 572 | #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) |
AnnaBridge | 171:3a7713b1edbc | 573 | #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) |
AnnaBridge | 171:3a7713b1edbc | 574 | #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) |
AnnaBridge | 171:3a7713b1edbc | 575 | #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) |
AnnaBridge | 171:3a7713b1edbc | 576 | #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) |
AnnaBridge | 171:3a7713b1edbc | 577 | #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) |
AnnaBridge | 171:3a7713b1edbc | 578 | /** |
AnnaBridge | 171:3a7713b1edbc | 579 | * @} |
AnnaBridge | 171:3a7713b1edbc | 580 | */ |
AnnaBridge | 171:3a7713b1edbc | 581 | |
AnnaBridge | 171:3a7713b1edbc | 582 | /** @defgroup TIM_Clock_Polarity TIM Clock Polarity |
AnnaBridge | 171:3a7713b1edbc | 583 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 584 | */ |
AnnaBridge | 171:3a7713b1edbc | 585 | #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ |
AnnaBridge | 171:3a7713b1edbc | 586 | #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ |
AnnaBridge | 171:3a7713b1edbc | 587 | #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ |
AnnaBridge | 171:3a7713b1edbc | 588 | #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ |
AnnaBridge | 171:3a7713b1edbc | 589 | #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ |
AnnaBridge | 171:3a7713b1edbc | 590 | /** |
AnnaBridge | 171:3a7713b1edbc | 591 | * @} |
AnnaBridge | 171:3a7713b1edbc | 592 | */ |
AnnaBridge | 171:3a7713b1edbc | 593 | |
AnnaBridge | 171:3a7713b1edbc | 594 | /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler |
AnnaBridge | 171:3a7713b1edbc | 595 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 596 | */ |
AnnaBridge | 171:3a7713b1edbc | 597 | #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
AnnaBridge | 171:3a7713b1edbc | 598 | #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ |
AnnaBridge | 171:3a7713b1edbc | 599 | #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ |
AnnaBridge | 171:3a7713b1edbc | 600 | #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ |
AnnaBridge | 171:3a7713b1edbc | 601 | /** |
AnnaBridge | 171:3a7713b1edbc | 602 | * @} |
AnnaBridge | 171:3a7713b1edbc | 603 | */ |
AnnaBridge | 171:3a7713b1edbc | 604 | |
AnnaBridge | 171:3a7713b1edbc | 605 | /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity |
AnnaBridge | 171:3a7713b1edbc | 606 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 607 | */ |
AnnaBridge | 171:3a7713b1edbc | 608 | #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ |
AnnaBridge | 171:3a7713b1edbc | 609 | #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ |
AnnaBridge | 171:3a7713b1edbc | 610 | /** |
AnnaBridge | 171:3a7713b1edbc | 611 | * @} |
AnnaBridge | 171:3a7713b1edbc | 612 | */ |
AnnaBridge | 171:3a7713b1edbc | 613 | |
AnnaBridge | 171:3a7713b1edbc | 614 | /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler |
AnnaBridge | 171:3a7713b1edbc | 615 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 616 | */ |
AnnaBridge | 171:3a7713b1edbc | 617 | #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
AnnaBridge | 171:3a7713b1edbc | 618 | #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ |
AnnaBridge | 171:3a7713b1edbc | 619 | #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ |
AnnaBridge | 171:3a7713b1edbc | 620 | #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ |
AnnaBridge | 171:3a7713b1edbc | 621 | /** |
AnnaBridge | 171:3a7713b1edbc | 622 | * @} |
AnnaBridge | 171:3a7713b1edbc | 623 | */ |
AnnaBridge | 171:3a7713b1edbc | 624 | |
AnnaBridge | 171:3a7713b1edbc | 625 | /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state |
AnnaBridge | 171:3a7713b1edbc | 626 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 627 | */ |
AnnaBridge | 171:3a7713b1edbc | 628 | #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) |
AnnaBridge | 171:3a7713b1edbc | 629 | #define TIM_OSSR_DISABLE (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 630 | /** |
AnnaBridge | 171:3a7713b1edbc | 631 | * @} |
AnnaBridge | 171:3a7713b1edbc | 632 | */ |
AnnaBridge | 171:3a7713b1edbc | 633 | |
AnnaBridge | 171:3a7713b1edbc | 634 | /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state |
AnnaBridge | 171:3a7713b1edbc | 635 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 636 | */ |
AnnaBridge | 171:3a7713b1edbc | 637 | #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) |
AnnaBridge | 171:3a7713b1edbc | 638 | #define TIM_OSSI_DISABLE (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 639 | /** |
AnnaBridge | 171:3a7713b1edbc | 640 | * @} |
AnnaBridge | 171:3a7713b1edbc | 641 | */ |
AnnaBridge | 171:3a7713b1edbc | 642 | |
AnnaBridge | 171:3a7713b1edbc | 643 | /** @defgroup TIM_Lock_level TIM Lock level |
AnnaBridge | 171:3a7713b1edbc | 644 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 645 | */ |
AnnaBridge | 171:3a7713b1edbc | 646 | #define TIM_LOCKLEVEL_OFF (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 647 | #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) |
AnnaBridge | 171:3a7713b1edbc | 648 | #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) |
AnnaBridge | 171:3a7713b1edbc | 649 | #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) |
AnnaBridge | 171:3a7713b1edbc | 650 | /** |
AnnaBridge | 171:3a7713b1edbc | 651 | * @} |
AnnaBridge | 171:3a7713b1edbc | 652 | */ |
AnnaBridge | 171:3a7713b1edbc | 653 | |
AnnaBridge | 171:3a7713b1edbc | 654 | /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable |
AnnaBridge | 171:3a7713b1edbc | 655 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 656 | */ |
AnnaBridge | 171:3a7713b1edbc | 657 | #define TIM_BREAK_ENABLE (TIM_BDTR_BKE) |
AnnaBridge | 171:3a7713b1edbc | 658 | #define TIM_BREAK_DISABLE (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 659 | /** |
AnnaBridge | 171:3a7713b1edbc | 660 | * @} |
AnnaBridge | 171:3a7713b1edbc | 661 | */ |
AnnaBridge | 171:3a7713b1edbc | 662 | |
AnnaBridge | 171:3a7713b1edbc | 663 | /** @defgroup TIM_Break_Polarity TIM Break Input Polarity |
AnnaBridge | 171:3a7713b1edbc | 664 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 665 | */ |
AnnaBridge | 171:3a7713b1edbc | 666 | #define TIM_BREAKPOLARITY_LOW (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 667 | #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) |
AnnaBridge | 171:3a7713b1edbc | 668 | /** |
AnnaBridge | 171:3a7713b1edbc | 669 | * @} |
AnnaBridge | 171:3a7713b1edbc | 670 | */ |
AnnaBridge | 171:3a7713b1edbc | 671 | /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable |
AnnaBridge | 171:3a7713b1edbc | 672 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 673 | */ |
AnnaBridge | 171:3a7713b1edbc | 674 | #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) |
AnnaBridge | 171:3a7713b1edbc | 675 | #define TIM_AUTOMATICOUTPUT_DISABLE (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 676 | /** |
AnnaBridge | 171:3a7713b1edbc | 677 | * @} |
AnnaBridge | 171:3a7713b1edbc | 678 | */ |
AnnaBridge | 171:3a7713b1edbc | 679 | |
AnnaBridge | 171:3a7713b1edbc | 680 | /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection |
AnnaBridge | 171:3a7713b1edbc | 681 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 682 | */ |
AnnaBridge | 171:3a7713b1edbc | 683 | #define TIM_TRGO_RESET (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 684 | #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) |
AnnaBridge | 171:3a7713b1edbc | 685 | #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) |
AnnaBridge | 171:3a7713b1edbc | 686 | #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
AnnaBridge | 171:3a7713b1edbc | 687 | #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) |
AnnaBridge | 171:3a7713b1edbc | 688 | #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) |
AnnaBridge | 171:3a7713b1edbc | 689 | #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) |
AnnaBridge | 171:3a7713b1edbc | 690 | #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
AnnaBridge | 171:3a7713b1edbc | 691 | /** |
AnnaBridge | 171:3a7713b1edbc | 692 | * @} |
AnnaBridge | 171:3a7713b1edbc | 693 | */ |
AnnaBridge | 171:3a7713b1edbc | 694 | |
AnnaBridge | 171:3a7713b1edbc | 695 | /** @defgroup TIM_Slave_Mode TIM Slave Mode |
AnnaBridge | 171:3a7713b1edbc | 696 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 697 | */ |
AnnaBridge | 171:3a7713b1edbc | 698 | #define TIM_SLAVEMODE_DISABLE (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 699 | #define TIM_SLAVEMODE_RESET (0x0004U) |
AnnaBridge | 171:3a7713b1edbc | 700 | #define TIM_SLAVEMODE_GATED (0x0005U) |
AnnaBridge | 171:3a7713b1edbc | 701 | #define TIM_SLAVEMODE_TRIGGER (0x0006U) |
AnnaBridge | 171:3a7713b1edbc | 702 | #define TIM_SLAVEMODE_EXTERNAL1 (0x0007U) |
AnnaBridge | 171:3a7713b1edbc | 703 | /** |
AnnaBridge | 171:3a7713b1edbc | 704 | * @} |
AnnaBridge | 171:3a7713b1edbc | 705 | */ |
AnnaBridge | 171:3a7713b1edbc | 706 | |
AnnaBridge | 171:3a7713b1edbc | 707 | /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode |
AnnaBridge | 171:3a7713b1edbc | 708 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 709 | */ |
AnnaBridge | 171:3a7713b1edbc | 710 | #define TIM_MASTERSLAVEMODE_ENABLE (0x0080U) |
AnnaBridge | 171:3a7713b1edbc | 711 | #define TIM_MASTERSLAVEMODE_DISABLE (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 712 | /** |
AnnaBridge | 171:3a7713b1edbc | 713 | * @} |
AnnaBridge | 171:3a7713b1edbc | 714 | */ |
AnnaBridge | 171:3a7713b1edbc | 715 | |
AnnaBridge | 171:3a7713b1edbc | 716 | /** @defgroup TIM_Trigger_Selection TIM Trigger Selection |
AnnaBridge | 171:3a7713b1edbc | 717 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 718 | */ |
AnnaBridge | 171:3a7713b1edbc | 719 | #define TIM_TS_ITR0 (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 720 | #define TIM_TS_ITR1 (0x0010U) |
AnnaBridge | 171:3a7713b1edbc | 721 | #define TIM_TS_ITR2 (0x0020U) |
AnnaBridge | 171:3a7713b1edbc | 722 | #define TIM_TS_ITR3 (0x0030U) |
AnnaBridge | 171:3a7713b1edbc | 723 | #define TIM_TS_TI1F_ED (0x0040U) |
AnnaBridge | 171:3a7713b1edbc | 724 | #define TIM_TS_TI1FP1 (0x0050U) |
AnnaBridge | 171:3a7713b1edbc | 725 | #define TIM_TS_TI2FP2 (0x0060U) |
AnnaBridge | 171:3a7713b1edbc | 726 | #define TIM_TS_ETRF (0x0070U) |
AnnaBridge | 171:3a7713b1edbc | 727 | #define TIM_TS_NONE (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 728 | /** |
AnnaBridge | 171:3a7713b1edbc | 729 | * @} |
AnnaBridge | 171:3a7713b1edbc | 730 | */ |
AnnaBridge | 171:3a7713b1edbc | 731 | |
AnnaBridge | 171:3a7713b1edbc | 732 | /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity |
AnnaBridge | 171:3a7713b1edbc | 733 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 734 | */ |
AnnaBridge | 171:3a7713b1edbc | 735 | #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ |
AnnaBridge | 171:3a7713b1edbc | 736 | #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ |
AnnaBridge | 171:3a7713b1edbc | 737 | #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
AnnaBridge | 171:3a7713b1edbc | 738 | #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
AnnaBridge | 171:3a7713b1edbc | 739 | #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
AnnaBridge | 171:3a7713b1edbc | 740 | /** |
AnnaBridge | 171:3a7713b1edbc | 741 | * @} |
AnnaBridge | 171:3a7713b1edbc | 742 | */ |
AnnaBridge | 171:3a7713b1edbc | 743 | |
AnnaBridge | 171:3a7713b1edbc | 744 | /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler |
AnnaBridge | 171:3a7713b1edbc | 745 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 746 | */ |
AnnaBridge | 171:3a7713b1edbc | 747 | #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
AnnaBridge | 171:3a7713b1edbc | 748 | #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ |
AnnaBridge | 171:3a7713b1edbc | 749 | #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ |
AnnaBridge | 171:3a7713b1edbc | 750 | #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ |
AnnaBridge | 171:3a7713b1edbc | 751 | /** |
AnnaBridge | 171:3a7713b1edbc | 752 | * @} |
AnnaBridge | 171:3a7713b1edbc | 753 | */ |
AnnaBridge | 171:3a7713b1edbc | 754 | |
AnnaBridge | 171:3a7713b1edbc | 755 | /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection |
AnnaBridge | 171:3a7713b1edbc | 756 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 757 | */ |
AnnaBridge | 171:3a7713b1edbc | 758 | #define TIM_TI1SELECTION_CH1 (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 759 | #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) |
AnnaBridge | 171:3a7713b1edbc | 760 | /** |
AnnaBridge | 171:3a7713b1edbc | 761 | * @} |
AnnaBridge | 171:3a7713b1edbc | 762 | */ |
AnnaBridge | 171:3a7713b1edbc | 763 | |
AnnaBridge | 171:3a7713b1edbc | 764 | /** @defgroup TIM_DMA_Base_address TIM DMA Base Address |
AnnaBridge | 171:3a7713b1edbc | 765 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 766 | */ |
AnnaBridge | 171:3a7713b1edbc | 767 | #define TIM_DMABASE_CR1 (0x00000000) |
AnnaBridge | 171:3a7713b1edbc | 768 | #define TIM_DMABASE_CR2 (0x00000001) |
AnnaBridge | 171:3a7713b1edbc | 769 | #define TIM_DMABASE_SMCR (0x00000002) |
AnnaBridge | 171:3a7713b1edbc | 770 | #define TIM_DMABASE_DIER (0x00000003) |
AnnaBridge | 171:3a7713b1edbc | 771 | #define TIM_DMABASE_SR (0x00000004) |
AnnaBridge | 171:3a7713b1edbc | 772 | #define TIM_DMABASE_EGR (0x00000005) |
AnnaBridge | 171:3a7713b1edbc | 773 | #define TIM_DMABASE_CCMR1 (0x00000006) |
AnnaBridge | 171:3a7713b1edbc | 774 | #define TIM_DMABASE_CCMR2 (0x00000007) |
AnnaBridge | 171:3a7713b1edbc | 775 | #define TIM_DMABASE_CCER (0x00000008) |
AnnaBridge | 171:3a7713b1edbc | 776 | #define TIM_DMABASE_CNT (0x00000009) |
AnnaBridge | 171:3a7713b1edbc | 777 | #define TIM_DMABASE_PSC (0x0000000A) |
AnnaBridge | 171:3a7713b1edbc | 778 | #define TIM_DMABASE_ARR (0x0000000B) |
AnnaBridge | 171:3a7713b1edbc | 779 | #define TIM_DMABASE_RCR (0x0000000C) |
AnnaBridge | 171:3a7713b1edbc | 780 | #define TIM_DMABASE_CCR1 (0x0000000D) |
AnnaBridge | 171:3a7713b1edbc | 781 | #define TIM_DMABASE_CCR2 (0x0000000E) |
AnnaBridge | 171:3a7713b1edbc | 782 | #define TIM_DMABASE_CCR3 (0x0000000F) |
AnnaBridge | 171:3a7713b1edbc | 783 | #define TIM_DMABASE_CCR4 (0x00000010) |
AnnaBridge | 171:3a7713b1edbc | 784 | #define TIM_DMABASE_BDTR (0x00000011) |
AnnaBridge | 171:3a7713b1edbc | 785 | #define TIM_DMABASE_DCR (0x00000012) |
AnnaBridge | 171:3a7713b1edbc | 786 | #define TIM_DMABASE_OR (0x00000013) |
AnnaBridge | 171:3a7713b1edbc | 787 | /** |
AnnaBridge | 171:3a7713b1edbc | 788 | * @} |
AnnaBridge | 171:3a7713b1edbc | 789 | */ |
AnnaBridge | 171:3a7713b1edbc | 790 | |
AnnaBridge | 171:3a7713b1edbc | 791 | /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length |
AnnaBridge | 171:3a7713b1edbc | 792 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 793 | */ |
AnnaBridge | 171:3a7713b1edbc | 794 | #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) |
AnnaBridge | 171:3a7713b1edbc | 795 | #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) |
AnnaBridge | 171:3a7713b1edbc | 796 | #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) |
AnnaBridge | 171:3a7713b1edbc | 797 | #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) |
AnnaBridge | 171:3a7713b1edbc | 798 | #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) |
AnnaBridge | 171:3a7713b1edbc | 799 | #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) |
AnnaBridge | 171:3a7713b1edbc | 800 | #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) |
AnnaBridge | 171:3a7713b1edbc | 801 | #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) |
AnnaBridge | 171:3a7713b1edbc | 802 | #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) |
AnnaBridge | 171:3a7713b1edbc | 803 | #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) |
AnnaBridge | 171:3a7713b1edbc | 804 | #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) |
AnnaBridge | 171:3a7713b1edbc | 805 | #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) |
AnnaBridge | 171:3a7713b1edbc | 806 | #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) |
AnnaBridge | 171:3a7713b1edbc | 807 | #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) |
AnnaBridge | 171:3a7713b1edbc | 808 | #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) |
AnnaBridge | 171:3a7713b1edbc | 809 | #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) |
AnnaBridge | 171:3a7713b1edbc | 810 | #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) |
AnnaBridge | 171:3a7713b1edbc | 811 | #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) |
AnnaBridge | 171:3a7713b1edbc | 812 | /** |
AnnaBridge | 171:3a7713b1edbc | 813 | * @} |
AnnaBridge | 171:3a7713b1edbc | 814 | */ |
AnnaBridge | 171:3a7713b1edbc | 815 | |
AnnaBridge | 171:3a7713b1edbc | 816 | /** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index |
AnnaBridge | 171:3a7713b1edbc | 817 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 818 | */ |
AnnaBridge | 171:3a7713b1edbc | 819 | #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */ |
AnnaBridge | 171:3a7713b1edbc | 820 | #define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ |
AnnaBridge | 171:3a7713b1edbc | 821 | #define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ |
AnnaBridge | 171:3a7713b1edbc | 822 | #define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ |
AnnaBridge | 171:3a7713b1edbc | 823 | #define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ |
AnnaBridge | 171:3a7713b1edbc | 824 | #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Commutation DMA requests */ |
AnnaBridge | 171:3a7713b1edbc | 825 | #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /*!< Index of the DMA handle used for Trigger DMA requests */ |
AnnaBridge | 171:3a7713b1edbc | 826 | /** |
AnnaBridge | 171:3a7713b1edbc | 827 | * @} |
AnnaBridge | 171:3a7713b1edbc | 828 | */ |
AnnaBridge | 171:3a7713b1edbc | 829 | |
AnnaBridge | 171:3a7713b1edbc | 830 | /** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State |
AnnaBridge | 171:3a7713b1edbc | 831 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 832 | */ |
AnnaBridge | 171:3a7713b1edbc | 833 | #define TIM_CCx_ENABLE (0x0001U) |
AnnaBridge | 171:3a7713b1edbc | 834 | #define TIM_CCx_DISABLE (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 835 | #define TIM_CCxN_ENABLE (0x0004U) |
AnnaBridge | 171:3a7713b1edbc | 836 | #define TIM_CCxN_DISABLE (0x0000U) |
AnnaBridge | 171:3a7713b1edbc | 837 | /** |
AnnaBridge | 171:3a7713b1edbc | 838 | * @} |
AnnaBridge | 171:3a7713b1edbc | 839 | */ |
AnnaBridge | 171:3a7713b1edbc | 840 | |
AnnaBridge | 171:3a7713b1edbc | 841 | /** |
AnnaBridge | 171:3a7713b1edbc | 842 | * @} |
AnnaBridge | 171:3a7713b1edbc | 843 | */ |
AnnaBridge | 171:3a7713b1edbc | 844 | |
AnnaBridge | 171:3a7713b1edbc | 845 | /* Private Constants -----------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 846 | /** @defgroup TIM_Private_Constants TIM Private Constants |
AnnaBridge | 171:3a7713b1edbc | 847 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 848 | */ |
AnnaBridge | 171:3a7713b1edbc | 849 | |
AnnaBridge | 171:3a7713b1edbc | 850 | /* The counter of a timer instance is disabled only if all the CCx and CCxN |
AnnaBridge | 171:3a7713b1edbc | 851 | channels have been disabled */ |
AnnaBridge | 171:3a7713b1edbc | 852 | #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) |
AnnaBridge | 171:3a7713b1edbc | 853 | #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) |
AnnaBridge | 171:3a7713b1edbc | 854 | |
AnnaBridge | 171:3a7713b1edbc | 855 | /** |
AnnaBridge | 171:3a7713b1edbc | 856 | * @} |
AnnaBridge | 171:3a7713b1edbc | 857 | */ |
AnnaBridge | 171:3a7713b1edbc | 858 | |
AnnaBridge | 171:3a7713b1edbc | 859 | /* Private Macros -----------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 860 | /** @defgroup TIM_Private_Macros TIM Private Macros |
AnnaBridge | 171:3a7713b1edbc | 861 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 862 | */ |
AnnaBridge | 171:3a7713b1edbc | 863 | |
AnnaBridge | 171:3a7713b1edbc | 864 | #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ |
AnnaBridge | 171:3a7713b1edbc | 865 | ((MODE) == TIM_COUNTERMODE_DOWN) || \ |
AnnaBridge | 171:3a7713b1edbc | 866 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ |
AnnaBridge | 171:3a7713b1edbc | 867 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ |
AnnaBridge | 171:3a7713b1edbc | 868 | ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) |
AnnaBridge | 171:3a7713b1edbc | 869 | |
AnnaBridge | 171:3a7713b1edbc | 870 | #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ |
AnnaBridge | 171:3a7713b1edbc | 871 | ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ |
AnnaBridge | 171:3a7713b1edbc | 872 | ((DIV) == TIM_CLOCKDIVISION_DIV4)) |
AnnaBridge | 171:3a7713b1edbc | 873 | |
AnnaBridge | 171:3a7713b1edbc | 874 | #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 875 | ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) |
AnnaBridge | 171:3a7713b1edbc | 876 | |
AnnaBridge | 171:3a7713b1edbc | 877 | #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ |
AnnaBridge | 171:3a7713b1edbc | 878 | ((MODE) == TIM_OCMODE_PWM2)) |
AnnaBridge | 171:3a7713b1edbc | 879 | |
AnnaBridge | 171:3a7713b1edbc | 880 | #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ |
AnnaBridge | 171:3a7713b1edbc | 881 | ((MODE) == TIM_OCMODE_ACTIVE) || \ |
AnnaBridge | 171:3a7713b1edbc | 882 | ((MODE) == TIM_OCMODE_INACTIVE) || \ |
AnnaBridge | 171:3a7713b1edbc | 883 | ((MODE) == TIM_OCMODE_TOGGLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 884 | ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ |
AnnaBridge | 171:3a7713b1edbc | 885 | ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) |
AnnaBridge | 171:3a7713b1edbc | 886 | |
AnnaBridge | 171:3a7713b1edbc | 887 | #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 888 | ((STATE) == TIM_OCFAST_ENABLE)) |
AnnaBridge | 171:3a7713b1edbc | 889 | |
AnnaBridge | 171:3a7713b1edbc | 890 | #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ |
AnnaBridge | 171:3a7713b1edbc | 891 | ((POLARITY) == TIM_OCPOLARITY_LOW)) |
AnnaBridge | 171:3a7713b1edbc | 892 | |
AnnaBridge | 171:3a7713b1edbc | 893 | #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \ |
AnnaBridge | 171:3a7713b1edbc | 894 | ((POLARITY) == TIM_OCNPOLARITY_LOW)) |
AnnaBridge | 171:3a7713b1edbc | 895 | |
AnnaBridge | 171:3a7713b1edbc | 896 | #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ |
AnnaBridge | 171:3a7713b1edbc | 897 | ((STATE) == TIM_OCIDLESTATE_RESET)) |
AnnaBridge | 171:3a7713b1edbc | 898 | |
AnnaBridge | 171:3a7713b1edbc | 899 | #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \ |
AnnaBridge | 171:3a7713b1edbc | 900 | ((STATE) == TIM_OCNIDLESTATE_RESET)) |
AnnaBridge | 171:3a7713b1edbc | 901 | |
AnnaBridge | 171:3a7713b1edbc | 902 | #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
AnnaBridge | 171:3a7713b1edbc | 903 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
AnnaBridge | 171:3a7713b1edbc | 904 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
AnnaBridge | 171:3a7713b1edbc | 905 | ((CHANNEL) == TIM_CHANNEL_4) || \ |
AnnaBridge | 171:3a7713b1edbc | 906 | ((CHANNEL) == TIM_CHANNEL_ALL)) |
AnnaBridge | 171:3a7713b1edbc | 907 | |
AnnaBridge | 171:3a7713b1edbc | 908 | #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
AnnaBridge | 171:3a7713b1edbc | 909 | ((CHANNEL) == TIM_CHANNEL_2)) |
AnnaBridge | 171:3a7713b1edbc | 910 | |
AnnaBridge | 171:3a7713b1edbc | 911 | #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
AnnaBridge | 171:3a7713b1edbc | 912 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
AnnaBridge | 171:3a7713b1edbc | 913 | ((CHANNEL) == TIM_CHANNEL_3)) |
AnnaBridge | 171:3a7713b1edbc | 914 | |
AnnaBridge | 171:3a7713b1edbc | 915 | #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ |
AnnaBridge | 171:3a7713b1edbc | 916 | ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ |
AnnaBridge | 171:3a7713b1edbc | 917 | ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) |
AnnaBridge | 171:3a7713b1edbc | 918 | |
AnnaBridge | 171:3a7713b1edbc | 919 | #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ |
AnnaBridge | 171:3a7713b1edbc | 920 | ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ |
AnnaBridge | 171:3a7713b1edbc | 921 | ((SELECTION) == TIM_ICSELECTION_TRC)) |
AnnaBridge | 171:3a7713b1edbc | 922 | |
AnnaBridge | 171:3a7713b1edbc | 923 | #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ |
AnnaBridge | 171:3a7713b1edbc | 924 | ((PRESCALER) == TIM_ICPSC_DIV2) || \ |
AnnaBridge | 171:3a7713b1edbc | 925 | ((PRESCALER) == TIM_ICPSC_DIV4) || \ |
AnnaBridge | 171:3a7713b1edbc | 926 | ((PRESCALER) == TIM_ICPSC_DIV8)) |
AnnaBridge | 171:3a7713b1edbc | 927 | |
AnnaBridge | 171:3a7713b1edbc | 928 | #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 929 | ((MODE) == TIM_OPMODE_REPETITIVE)) |
AnnaBridge | 171:3a7713b1edbc | 930 | |
AnnaBridge | 171:3a7713b1edbc | 931 | #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ |
AnnaBridge | 171:3a7713b1edbc | 932 | ((MODE) == TIM_ENCODERMODE_TI2) || \ |
AnnaBridge | 171:3a7713b1edbc | 933 | ((MODE) == TIM_ENCODERMODE_TI12)) |
AnnaBridge | 171:3a7713b1edbc | 934 | |
AnnaBridge | 171:3a7713b1edbc | 935 | #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U)) |
AnnaBridge | 171:3a7713b1edbc | 936 | |
AnnaBridge | 171:3a7713b1edbc | 937 | #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U)) |
AnnaBridge | 171:3a7713b1edbc | 938 | |
AnnaBridge | 171:3a7713b1edbc | 939 | #define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \ |
AnnaBridge | 171:3a7713b1edbc | 940 | ((FLAG) == TIM_FLAG_CC1) || \ |
AnnaBridge | 171:3a7713b1edbc | 941 | ((FLAG) == TIM_FLAG_CC2) || \ |
AnnaBridge | 171:3a7713b1edbc | 942 | ((FLAG) == TIM_FLAG_CC3) || \ |
AnnaBridge | 171:3a7713b1edbc | 943 | ((FLAG) == TIM_FLAG_CC4) || \ |
AnnaBridge | 171:3a7713b1edbc | 944 | ((FLAG) == TIM_FLAG_COM) || \ |
AnnaBridge | 171:3a7713b1edbc | 945 | ((FLAG) == TIM_FLAG_TRIGGER) || \ |
AnnaBridge | 171:3a7713b1edbc | 946 | ((FLAG) == TIM_FLAG_BREAK) || \ |
AnnaBridge | 171:3a7713b1edbc | 947 | ((FLAG) == TIM_FLAG_CC1OF) || \ |
AnnaBridge | 171:3a7713b1edbc | 948 | ((FLAG) == TIM_FLAG_CC2OF) || \ |
AnnaBridge | 171:3a7713b1edbc | 949 | ((FLAG) == TIM_FLAG_CC3OF) || \ |
AnnaBridge | 171:3a7713b1edbc | 950 | ((FLAG) == TIM_FLAG_CC4OF)) |
AnnaBridge | 171:3a7713b1edbc | 951 | |
AnnaBridge | 171:3a7713b1edbc | 952 | #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ |
AnnaBridge | 171:3a7713b1edbc | 953 | ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ |
AnnaBridge | 171:3a7713b1edbc | 954 | ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ |
AnnaBridge | 171:3a7713b1edbc | 955 | ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ |
AnnaBridge | 171:3a7713b1edbc | 956 | ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ |
AnnaBridge | 171:3a7713b1edbc | 957 | ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ |
AnnaBridge | 171:3a7713b1edbc | 958 | ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ |
AnnaBridge | 171:3a7713b1edbc | 959 | ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ |
AnnaBridge | 171:3a7713b1edbc | 960 | ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ |
AnnaBridge | 171:3a7713b1edbc | 961 | ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) |
AnnaBridge | 171:3a7713b1edbc | 962 | |
AnnaBridge | 171:3a7713b1edbc | 963 | #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ |
AnnaBridge | 171:3a7713b1edbc | 964 | ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ |
AnnaBridge | 171:3a7713b1edbc | 965 | ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ |
AnnaBridge | 171:3a7713b1edbc | 966 | ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ |
AnnaBridge | 171:3a7713b1edbc | 967 | ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) |
AnnaBridge | 171:3a7713b1edbc | 968 | |
AnnaBridge | 171:3a7713b1edbc | 969 | #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ |
AnnaBridge | 171:3a7713b1edbc | 970 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ |
AnnaBridge | 171:3a7713b1edbc | 971 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ |
AnnaBridge | 171:3a7713b1edbc | 972 | ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) |
AnnaBridge | 171:3a7713b1edbc | 973 | |
AnnaBridge | 171:3a7713b1edbc | 974 | #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xFU) |
AnnaBridge | 171:3a7713b1edbc | 975 | |
AnnaBridge | 171:3a7713b1edbc | 976 | #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ |
AnnaBridge | 171:3a7713b1edbc | 977 | ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) |
AnnaBridge | 171:3a7713b1edbc | 978 | |
AnnaBridge | 171:3a7713b1edbc | 979 | #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ |
AnnaBridge | 171:3a7713b1edbc | 980 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ |
AnnaBridge | 171:3a7713b1edbc | 981 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ |
AnnaBridge | 171:3a7713b1edbc | 982 | ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) |
AnnaBridge | 171:3a7713b1edbc | 983 | |
AnnaBridge | 171:3a7713b1edbc | 984 | #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU) |
AnnaBridge | 171:3a7713b1edbc | 985 | |
AnnaBridge | 171:3a7713b1edbc | 986 | #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 987 | ((STATE) == TIM_OSSR_DISABLE)) |
AnnaBridge | 171:3a7713b1edbc | 988 | |
AnnaBridge | 171:3a7713b1edbc | 989 | #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 990 | ((STATE) == TIM_OSSI_DISABLE)) |
AnnaBridge | 171:3a7713b1edbc | 991 | |
AnnaBridge | 171:3a7713b1edbc | 992 | #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ |
AnnaBridge | 171:3a7713b1edbc | 993 | ((LEVEL) == TIM_LOCKLEVEL_1) || \ |
AnnaBridge | 171:3a7713b1edbc | 994 | ((LEVEL) == TIM_LOCKLEVEL_2) || \ |
AnnaBridge | 171:3a7713b1edbc | 995 | ((LEVEL) == TIM_LOCKLEVEL_3)) |
AnnaBridge | 171:3a7713b1edbc | 996 | |
AnnaBridge | 171:3a7713b1edbc | 997 | #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 998 | ((STATE) == TIM_BREAK_DISABLE)) |
AnnaBridge | 171:3a7713b1edbc | 999 | |
AnnaBridge | 171:3a7713b1edbc | 1000 | #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \ |
AnnaBridge | 171:3a7713b1edbc | 1001 | ((POLARITY) == TIM_BREAKPOLARITY_HIGH)) |
AnnaBridge | 171:3a7713b1edbc | 1002 | |
AnnaBridge | 171:3a7713b1edbc | 1003 | #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 1004 | ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) |
AnnaBridge | 171:3a7713b1edbc | 1005 | |
AnnaBridge | 171:3a7713b1edbc | 1006 | #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ |
AnnaBridge | 171:3a7713b1edbc | 1007 | ((SOURCE) == TIM_TRGO_ENABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 1008 | ((SOURCE) == TIM_TRGO_UPDATE) || \ |
AnnaBridge | 171:3a7713b1edbc | 1009 | ((SOURCE) == TIM_TRGO_OC1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1010 | ((SOURCE) == TIM_TRGO_OC1REF) || \ |
AnnaBridge | 171:3a7713b1edbc | 1011 | ((SOURCE) == TIM_TRGO_OC2REF) || \ |
AnnaBridge | 171:3a7713b1edbc | 1012 | ((SOURCE) == TIM_TRGO_OC3REF) || \ |
AnnaBridge | 171:3a7713b1edbc | 1013 | ((SOURCE) == TIM_TRGO_OC4REF)) |
AnnaBridge | 171:3a7713b1edbc | 1014 | |
AnnaBridge | 171:3a7713b1edbc | 1015 | #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 1016 | ((MODE) == TIM_SLAVEMODE_GATED) || \ |
AnnaBridge | 171:3a7713b1edbc | 1017 | ((MODE) == TIM_SLAVEMODE_RESET) || \ |
AnnaBridge | 171:3a7713b1edbc | 1018 | ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ |
AnnaBridge | 171:3a7713b1edbc | 1019 | ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) |
AnnaBridge | 171:3a7713b1edbc | 1020 | |
AnnaBridge | 171:3a7713b1edbc | 1021 | #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 1022 | ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) |
AnnaBridge | 171:3a7713b1edbc | 1023 | |
AnnaBridge | 171:3a7713b1edbc | 1024 | #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
AnnaBridge | 171:3a7713b1edbc | 1025 | ((SELECTION) == TIM_TS_ITR1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1026 | ((SELECTION) == TIM_TS_ITR2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1027 | ((SELECTION) == TIM_TS_ITR3) || \ |
AnnaBridge | 171:3a7713b1edbc | 1028 | ((SELECTION) == TIM_TS_TI1F_ED) || \ |
AnnaBridge | 171:3a7713b1edbc | 1029 | ((SELECTION) == TIM_TS_TI1FP1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1030 | ((SELECTION) == TIM_TS_TI2FP2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1031 | ((SELECTION) == TIM_TS_ETRF)) |
AnnaBridge | 171:3a7713b1edbc | 1032 | |
AnnaBridge | 171:3a7713b1edbc | 1033 | #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
AnnaBridge | 171:3a7713b1edbc | 1034 | ((SELECTION) == TIM_TS_ITR1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1035 | ((SELECTION) == TIM_TS_ITR2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1036 | ((SELECTION) == TIM_TS_ITR3) || \ |
AnnaBridge | 171:3a7713b1edbc | 1037 | ((SELECTION) == TIM_TS_NONE)) |
AnnaBridge | 171:3a7713b1edbc | 1038 | |
AnnaBridge | 171:3a7713b1edbc | 1039 | #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ |
AnnaBridge | 171:3a7713b1edbc | 1040 | ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ |
AnnaBridge | 171:3a7713b1edbc | 1041 | ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ |
AnnaBridge | 171:3a7713b1edbc | 1042 | ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ |
AnnaBridge | 171:3a7713b1edbc | 1043 | ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) |
AnnaBridge | 171:3a7713b1edbc | 1044 | |
AnnaBridge | 171:3a7713b1edbc | 1045 | #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1046 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1047 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ |
AnnaBridge | 171:3a7713b1edbc | 1048 | ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) |
AnnaBridge | 171:3a7713b1edbc | 1049 | |
AnnaBridge | 171:3a7713b1edbc | 1050 | #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xFU) |
AnnaBridge | 171:3a7713b1edbc | 1051 | |
AnnaBridge | 171:3a7713b1edbc | 1052 | #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1053 | ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) |
AnnaBridge | 171:3a7713b1edbc | 1054 | |
AnnaBridge | 171:3a7713b1edbc | 1055 | #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1056 | ((BASE) == TIM_DMABASE_CR2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1057 | ((BASE) == TIM_DMABASE_SMCR) || \ |
AnnaBridge | 171:3a7713b1edbc | 1058 | ((BASE) == TIM_DMABASE_DIER) || \ |
AnnaBridge | 171:3a7713b1edbc | 1059 | ((BASE) == TIM_DMABASE_SR) || \ |
AnnaBridge | 171:3a7713b1edbc | 1060 | ((BASE) == TIM_DMABASE_EGR) || \ |
AnnaBridge | 171:3a7713b1edbc | 1061 | ((BASE) == TIM_DMABASE_CCMR1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1062 | ((BASE) == TIM_DMABASE_CCMR2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1063 | ((BASE) == TIM_DMABASE_CCER) || \ |
AnnaBridge | 171:3a7713b1edbc | 1064 | ((BASE) == TIM_DMABASE_CNT) || \ |
AnnaBridge | 171:3a7713b1edbc | 1065 | ((BASE) == TIM_DMABASE_PSC) || \ |
AnnaBridge | 171:3a7713b1edbc | 1066 | ((BASE) == TIM_DMABASE_ARR) || \ |
AnnaBridge | 171:3a7713b1edbc | 1067 | ((BASE) == TIM_DMABASE_RCR) || \ |
AnnaBridge | 171:3a7713b1edbc | 1068 | ((BASE) == TIM_DMABASE_CCR1) || \ |
AnnaBridge | 171:3a7713b1edbc | 1069 | ((BASE) == TIM_DMABASE_CCR2) || \ |
AnnaBridge | 171:3a7713b1edbc | 1070 | ((BASE) == TIM_DMABASE_CCR3) || \ |
AnnaBridge | 171:3a7713b1edbc | 1071 | ((BASE) == TIM_DMABASE_CCR4) || \ |
AnnaBridge | 171:3a7713b1edbc | 1072 | ((BASE) == TIM_DMABASE_BDTR) || \ |
AnnaBridge | 171:3a7713b1edbc | 1073 | ((BASE) == TIM_DMABASE_DCR) || \ |
AnnaBridge | 171:3a7713b1edbc | 1074 | ((BASE) == TIM_DMABASE_OR)) |
AnnaBridge | 171:3a7713b1edbc | 1075 | |
AnnaBridge | 171:3a7713b1edbc | 1076 | #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \ |
AnnaBridge | 171:3a7713b1edbc | 1077 | ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1078 | ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1079 | ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1080 | ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1081 | ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1082 | ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1083 | ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1084 | ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1085 | ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1086 | ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1087 | ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1088 | ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1089 | ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1090 | ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1091 | ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1092 | ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ |
AnnaBridge | 171:3a7713b1edbc | 1093 | ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS)) |
AnnaBridge | 171:3a7713b1edbc | 1094 | |
AnnaBridge | 171:3a7713b1edbc | 1095 | #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) |
AnnaBridge | 171:3a7713b1edbc | 1096 | |
AnnaBridge | 171:3a7713b1edbc | 1097 | #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU) |
AnnaBridge | 171:3a7713b1edbc | 1098 | |
AnnaBridge | 171:3a7713b1edbc | 1099 | /** @brief Set TIM IC prescaler |
AnnaBridge | 171:3a7713b1edbc | 1100 | * @param __HANDLE__ TIM handle |
AnnaBridge | 171:3a7713b1edbc | 1101 | * @param __CHANNEL__ specifies TIM Channel |
AnnaBridge | 171:3a7713b1edbc | 1102 | * @param __ICPSC__ specifies the prescaler value. |
AnnaBridge | 171:3a7713b1edbc | 1103 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1104 | */ |
AnnaBridge | 171:3a7713b1edbc | 1105 | #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
AnnaBridge | 171:3a7713b1edbc | 1106 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ |
AnnaBridge | 171:3a7713b1edbc | 1107 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ |
AnnaBridge | 171:3a7713b1edbc | 1108 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ |
AnnaBridge | 171:3a7713b1edbc | 1109 | ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) |
AnnaBridge | 171:3a7713b1edbc | 1110 | |
AnnaBridge | 171:3a7713b1edbc | 1111 | /** @brief Reset TIM IC prescaler |
AnnaBridge | 171:3a7713b1edbc | 1112 | * @param __HANDLE__ TIM handle |
AnnaBridge | 171:3a7713b1edbc | 1113 | * @param __CHANNEL__ specifies TIM Channel |
AnnaBridge | 171:3a7713b1edbc | 1114 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1115 | */ |
AnnaBridge | 171:3a7713b1edbc | 1116 | #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ |
AnnaBridge | 171:3a7713b1edbc | 1117 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ |
AnnaBridge | 171:3a7713b1edbc | 1118 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ |
AnnaBridge | 171:3a7713b1edbc | 1119 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ |
AnnaBridge | 171:3a7713b1edbc | 1120 | ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) |
AnnaBridge | 171:3a7713b1edbc | 1121 | |
AnnaBridge | 171:3a7713b1edbc | 1122 | |
AnnaBridge | 171:3a7713b1edbc | 1123 | /** @brief Set TIM IC polarity |
AnnaBridge | 171:3a7713b1edbc | 1124 | * @param __HANDLE__ TIM handle |
AnnaBridge | 171:3a7713b1edbc | 1125 | * @param __CHANNEL__ specifies TIM Channel |
AnnaBridge | 171:3a7713b1edbc | 1126 | * @param __POLARITY__ specifies TIM Channel Polarity |
AnnaBridge | 171:3a7713b1edbc | 1127 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1128 | */ |
AnnaBridge | 171:3a7713b1edbc | 1129 | #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
AnnaBridge | 171:3a7713b1edbc | 1130 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ |
AnnaBridge | 171:3a7713b1edbc | 1131 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ |
AnnaBridge | 171:3a7713b1edbc | 1132 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ |
AnnaBridge | 171:3a7713b1edbc | 1133 | ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 12U))) |
AnnaBridge | 171:3a7713b1edbc | 1134 | |
AnnaBridge | 171:3a7713b1edbc | 1135 | /** @brief Reset TIM IC polarity |
AnnaBridge | 171:3a7713b1edbc | 1136 | * @param __HANDLE__ TIM handle |
AnnaBridge | 171:3a7713b1edbc | 1137 | * @param __CHANNEL__ specifies TIM Channel |
AnnaBridge | 171:3a7713b1edbc | 1138 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1139 | */ |
AnnaBridge | 171:3a7713b1edbc | 1140 | #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ |
AnnaBridge | 171:3a7713b1edbc | 1141 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ |
AnnaBridge | 171:3a7713b1edbc | 1142 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ |
AnnaBridge | 171:3a7713b1edbc | 1143 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ |
AnnaBridge | 171:3a7713b1edbc | 1144 | ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) |
AnnaBridge | 171:3a7713b1edbc | 1145 | |
AnnaBridge | 171:3a7713b1edbc | 1146 | /** |
AnnaBridge | 171:3a7713b1edbc | 1147 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1148 | */ |
AnnaBridge | 171:3a7713b1edbc | 1149 | |
AnnaBridge | 171:3a7713b1edbc | 1150 | /* Private Functions --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 1151 | /** @addtogroup TIM_Private_Functions |
AnnaBridge | 171:3a7713b1edbc | 1152 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1153 | */ |
AnnaBridge | 171:3a7713b1edbc | 1154 | void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); |
AnnaBridge | 171:3a7713b1edbc | 1155 | void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); |
AnnaBridge | 171:3a7713b1edbc | 1156 | void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
AnnaBridge | 171:3a7713b1edbc | 1157 | void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); |
AnnaBridge | 171:3a7713b1edbc | 1158 | void TIM_DMAError(DMA_HandleTypeDef *hdma); |
AnnaBridge | 171:3a7713b1edbc | 1159 | void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); |
AnnaBridge | 171:3a7713b1edbc | 1160 | void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); |
AnnaBridge | 171:3a7713b1edbc | 1161 | /** |
AnnaBridge | 171:3a7713b1edbc | 1162 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1163 | */ |
AnnaBridge | 171:3a7713b1edbc | 1164 | |
AnnaBridge | 171:3a7713b1edbc | 1165 | /* Exported macros -----------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 1166 | /** @defgroup TIM_Exported_Macros TIM Exported Macros |
AnnaBridge | 171:3a7713b1edbc | 1167 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1168 | */ |
AnnaBridge | 171:3a7713b1edbc | 1169 | |
AnnaBridge | 171:3a7713b1edbc | 1170 | /** @brief Reset TIM handle state |
AnnaBridge | 171:3a7713b1edbc | 1171 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1172 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1173 | */ |
AnnaBridge | 171:3a7713b1edbc | 1174 | #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) |
AnnaBridge | 171:3a7713b1edbc | 1175 | |
AnnaBridge | 171:3a7713b1edbc | 1176 | /** |
AnnaBridge | 171:3a7713b1edbc | 1177 | * @brief Enable the TIM peripheral. |
AnnaBridge | 171:3a7713b1edbc | 1178 | * @param __HANDLE__ TIM handle |
AnnaBridge | 171:3a7713b1edbc | 1179 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1180 | */ |
AnnaBridge | 171:3a7713b1edbc | 1181 | #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) |
AnnaBridge | 171:3a7713b1edbc | 1182 | |
AnnaBridge | 171:3a7713b1edbc | 1183 | /** |
AnnaBridge | 171:3a7713b1edbc | 1184 | * @brief Enable the TIM main Output. |
AnnaBridge | 171:3a7713b1edbc | 1185 | * @param __HANDLE__ TIM handle |
AnnaBridge | 171:3a7713b1edbc | 1186 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1187 | */ |
AnnaBridge | 171:3a7713b1edbc | 1188 | #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) |
AnnaBridge | 171:3a7713b1edbc | 1189 | |
AnnaBridge | 171:3a7713b1edbc | 1190 | /** |
AnnaBridge | 171:3a7713b1edbc | 1191 | * @brief Disable the TIM peripheral. |
AnnaBridge | 171:3a7713b1edbc | 1192 | * @param __HANDLE__ TIM handle |
AnnaBridge | 171:3a7713b1edbc | 1193 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1194 | */ |
AnnaBridge | 171:3a7713b1edbc | 1195 | #define __HAL_TIM_DISABLE(__HANDLE__) \ |
AnnaBridge | 171:3a7713b1edbc | 1196 | do { \ |
AnnaBridge | 171:3a7713b1edbc | 1197 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ |
AnnaBridge | 171:3a7713b1edbc | 1198 | { \ |
AnnaBridge | 171:3a7713b1edbc | 1199 | if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ |
AnnaBridge | 171:3a7713b1edbc | 1200 | { \ |
AnnaBridge | 171:3a7713b1edbc | 1201 | (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ |
AnnaBridge | 171:3a7713b1edbc | 1202 | } \ |
AnnaBridge | 171:3a7713b1edbc | 1203 | } \ |
AnnaBridge | 171:3a7713b1edbc | 1204 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1205 | /* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN |
AnnaBridge | 171:3a7713b1edbc | 1206 | channels have been disabled */ |
AnnaBridge | 171:3a7713b1edbc | 1207 | /** |
AnnaBridge | 171:3a7713b1edbc | 1208 | * @brief Disable the TIM main Output. |
AnnaBridge | 171:3a7713b1edbc | 1209 | * @param __HANDLE__ TIM handle |
AnnaBridge | 171:3a7713b1edbc | 1210 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1211 | * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled |
AnnaBridge | 171:3a7713b1edbc | 1212 | */ |
AnnaBridge | 171:3a7713b1edbc | 1213 | #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ |
AnnaBridge | 171:3a7713b1edbc | 1214 | do { \ |
AnnaBridge | 171:3a7713b1edbc | 1215 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ |
AnnaBridge | 171:3a7713b1edbc | 1216 | { \ |
AnnaBridge | 171:3a7713b1edbc | 1217 | if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ |
AnnaBridge | 171:3a7713b1edbc | 1218 | { \ |
AnnaBridge | 171:3a7713b1edbc | 1219 | (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ |
AnnaBridge | 171:3a7713b1edbc | 1220 | } \ |
AnnaBridge | 171:3a7713b1edbc | 1221 | } \ |
AnnaBridge | 171:3a7713b1edbc | 1222 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1223 | |
AnnaBridge | 171:3a7713b1edbc | 1224 | /* The Main Output Enable of a timer instance is disabled unconditionally */ |
AnnaBridge | 171:3a7713b1edbc | 1225 | /** |
AnnaBridge | 171:3a7713b1edbc | 1226 | * @brief Disable the TIM main Output. |
AnnaBridge | 171:3a7713b1edbc | 1227 | * @param __HANDLE__ TIM handle |
AnnaBridge | 171:3a7713b1edbc | 1228 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1229 | * @note The Main Output Enable of a timer instance is disabled uncondiotionally |
AnnaBridge | 171:3a7713b1edbc | 1230 | */ |
AnnaBridge | 171:3a7713b1edbc | 1231 | #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) |
AnnaBridge | 171:3a7713b1edbc | 1232 | |
AnnaBridge | 171:3a7713b1edbc | 1233 | /** |
AnnaBridge | 171:3a7713b1edbc | 1234 | * @brief Enables the specified TIM interrupt. |
AnnaBridge | 171:3a7713b1edbc | 1235 | * @param __HANDLE__ specifies the TIM Handle. |
AnnaBridge | 171:3a7713b1edbc | 1236 | * @param __INTERRUPT__ specifies the TIM interrupt source to enable. |
AnnaBridge | 171:3a7713b1edbc | 1237 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1238 | * @arg TIM_IT_UPDATE: Update interrupt |
AnnaBridge | 171:3a7713b1edbc | 1239 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
AnnaBridge | 171:3a7713b1edbc | 1240 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
AnnaBridge | 171:3a7713b1edbc | 1241 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
AnnaBridge | 171:3a7713b1edbc | 1242 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
AnnaBridge | 171:3a7713b1edbc | 1243 | * @arg TIM_IT_COM: Commutation interrupt |
AnnaBridge | 171:3a7713b1edbc | 1244 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
AnnaBridge | 171:3a7713b1edbc | 1245 | * @arg TIM_IT_BREAK: Break interrupt |
AnnaBridge | 171:3a7713b1edbc | 1246 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1247 | */ |
AnnaBridge | 171:3a7713b1edbc | 1248 | #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) |
AnnaBridge | 171:3a7713b1edbc | 1249 | |
AnnaBridge | 171:3a7713b1edbc | 1250 | /** |
AnnaBridge | 171:3a7713b1edbc | 1251 | * @brief Disables the specified TIM interrupt. |
AnnaBridge | 171:3a7713b1edbc | 1252 | * @param __HANDLE__ specifies the TIM Handle. |
AnnaBridge | 171:3a7713b1edbc | 1253 | * @param __INTERRUPT__ specifies the TIM interrupt source to disable. |
AnnaBridge | 171:3a7713b1edbc | 1254 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1255 | * @arg TIM_IT_UPDATE: Update interrupt |
AnnaBridge | 171:3a7713b1edbc | 1256 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
AnnaBridge | 171:3a7713b1edbc | 1257 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
AnnaBridge | 171:3a7713b1edbc | 1258 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
AnnaBridge | 171:3a7713b1edbc | 1259 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
AnnaBridge | 171:3a7713b1edbc | 1260 | * @arg TIM_IT_COM: Commutation interrupt |
AnnaBridge | 171:3a7713b1edbc | 1261 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
AnnaBridge | 171:3a7713b1edbc | 1262 | * @arg TIM_IT_BREAK: Break interrupt |
AnnaBridge | 171:3a7713b1edbc | 1263 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1264 | */ |
AnnaBridge | 171:3a7713b1edbc | 1265 | #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) |
AnnaBridge | 171:3a7713b1edbc | 1266 | |
AnnaBridge | 171:3a7713b1edbc | 1267 | /** |
AnnaBridge | 171:3a7713b1edbc | 1268 | * @brief Enables the specified DMA request. |
AnnaBridge | 171:3a7713b1edbc | 1269 | * @param __HANDLE__ specifies the TIM Handle. |
AnnaBridge | 171:3a7713b1edbc | 1270 | * @param __DMA__ specifies the TIM DMA request to enable. |
AnnaBridge | 171:3a7713b1edbc | 1271 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1272 | * @arg TIM_DMA_UPDATE: Update DMA request |
AnnaBridge | 171:3a7713b1edbc | 1273 | * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request |
AnnaBridge | 171:3a7713b1edbc | 1274 | * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request |
AnnaBridge | 171:3a7713b1edbc | 1275 | * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request |
AnnaBridge | 171:3a7713b1edbc | 1276 | * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request |
AnnaBridge | 171:3a7713b1edbc | 1277 | * @arg TIM_DMA_COM: Commutation DMA request |
AnnaBridge | 171:3a7713b1edbc | 1278 | * @arg TIM_DMA_TRIGGER: Trigger DMA request |
AnnaBridge | 171:3a7713b1edbc | 1279 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1280 | */ |
AnnaBridge | 171:3a7713b1edbc | 1281 | #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) |
AnnaBridge | 171:3a7713b1edbc | 1282 | |
AnnaBridge | 171:3a7713b1edbc | 1283 | /** |
AnnaBridge | 171:3a7713b1edbc | 1284 | * @brief Disables the specified DMA request. |
AnnaBridge | 171:3a7713b1edbc | 1285 | * @param __HANDLE__ specifies the TIM Handle. |
AnnaBridge | 171:3a7713b1edbc | 1286 | * @param __DMA__ specifies the TIM DMA request to disable. |
AnnaBridge | 171:3a7713b1edbc | 1287 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1288 | * @arg TIM_DMA_UPDATE: Update DMA request |
AnnaBridge | 171:3a7713b1edbc | 1289 | * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request |
AnnaBridge | 171:3a7713b1edbc | 1290 | * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request |
AnnaBridge | 171:3a7713b1edbc | 1291 | * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request |
AnnaBridge | 171:3a7713b1edbc | 1292 | * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request |
AnnaBridge | 171:3a7713b1edbc | 1293 | * @arg TIM_DMA_COM: Commutation DMA request |
AnnaBridge | 171:3a7713b1edbc | 1294 | * @arg TIM_DMA_TRIGGER: Trigger DMA request |
AnnaBridge | 171:3a7713b1edbc | 1295 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1296 | */ |
AnnaBridge | 171:3a7713b1edbc | 1297 | #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) |
AnnaBridge | 171:3a7713b1edbc | 1298 | |
AnnaBridge | 171:3a7713b1edbc | 1299 | /** |
AnnaBridge | 171:3a7713b1edbc | 1300 | * @brief Checks whether the specified TIM interrupt flag is set or not. |
AnnaBridge | 171:3a7713b1edbc | 1301 | * @param __HANDLE__ specifies the TIM Handle. |
AnnaBridge | 171:3a7713b1edbc | 1302 | * @param __FLAG__ specifies the TIM interrupt flag to check. |
AnnaBridge | 171:3a7713b1edbc | 1303 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1304 | * @arg TIM_FLAG_UPDATE: Update interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1305 | * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1306 | * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1307 | * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1308 | * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1309 | * @arg TIM_FLAG_COM: Commutation interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1310 | * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1311 | * @arg TIM_FLAG_BREAK: Break interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1312 | * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag |
AnnaBridge | 171:3a7713b1edbc | 1313 | * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag |
AnnaBridge | 171:3a7713b1edbc | 1314 | * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag |
AnnaBridge | 171:3a7713b1edbc | 1315 | * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag |
AnnaBridge | 171:3a7713b1edbc | 1316 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
AnnaBridge | 171:3a7713b1edbc | 1317 | */ |
AnnaBridge | 171:3a7713b1edbc | 1318 | #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) |
AnnaBridge | 171:3a7713b1edbc | 1319 | |
AnnaBridge | 171:3a7713b1edbc | 1320 | /** |
AnnaBridge | 171:3a7713b1edbc | 1321 | * @brief Clears the specified TIM interrupt flag. |
AnnaBridge | 171:3a7713b1edbc | 1322 | * @param __HANDLE__ specifies the TIM Handle. |
AnnaBridge | 171:3a7713b1edbc | 1323 | * @param __FLAG__ specifies the TIM interrupt flag to clear. |
AnnaBridge | 171:3a7713b1edbc | 1324 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1325 | * @arg TIM_FLAG_UPDATE: Update interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1326 | * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1327 | * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1328 | * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1329 | * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1330 | * @arg TIM_FLAG_COM: Commutation interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1331 | * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1332 | * @arg TIM_FLAG_BREAK: Break interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 1333 | * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag |
AnnaBridge | 171:3a7713b1edbc | 1334 | * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag |
AnnaBridge | 171:3a7713b1edbc | 1335 | * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag |
AnnaBridge | 171:3a7713b1edbc | 1336 | * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag |
AnnaBridge | 171:3a7713b1edbc | 1337 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
AnnaBridge | 171:3a7713b1edbc | 1338 | */ |
AnnaBridge | 171:3a7713b1edbc | 1339 | #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) |
AnnaBridge | 171:3a7713b1edbc | 1340 | |
AnnaBridge | 171:3a7713b1edbc | 1341 | /** |
AnnaBridge | 171:3a7713b1edbc | 1342 | * @brief Checks whether the specified TIM interrupt has occurred or not. |
AnnaBridge | 171:3a7713b1edbc | 1343 | * @param __HANDLE__ TIM handle |
AnnaBridge | 171:3a7713b1edbc | 1344 | * @param __INTERRUPT__ specifies the TIM interrupt source to check. |
AnnaBridge | 171:3a7713b1edbc | 1345 | * @retval The state of TIM_IT (SET or RESET). |
AnnaBridge | 171:3a7713b1edbc | 1346 | */ |
AnnaBridge | 171:3a7713b1edbc | 1347 | #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
AnnaBridge | 171:3a7713b1edbc | 1348 | |
AnnaBridge | 171:3a7713b1edbc | 1349 | /** |
AnnaBridge | 171:3a7713b1edbc | 1350 | * @brief Clear the TIM interrupt pending bits |
AnnaBridge | 171:3a7713b1edbc | 1351 | * @param __HANDLE__ TIM handle |
AnnaBridge | 171:3a7713b1edbc | 1352 | * @param __INTERRUPT__ specifies the interrupt pending bit to clear. |
AnnaBridge | 171:3a7713b1edbc | 1353 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1354 | */ |
AnnaBridge | 171:3a7713b1edbc | 1355 | #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) |
AnnaBridge | 171:3a7713b1edbc | 1356 | |
AnnaBridge | 171:3a7713b1edbc | 1357 | /** |
AnnaBridge | 171:3a7713b1edbc | 1358 | * @brief Indicates whether or not the TIM Counter is used as downcounter |
AnnaBridge | 171:3a7713b1edbc | 1359 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1360 | * @retval False (Counter used as upcounter) or True (Counter used as downcounter) |
AnnaBridge | 171:3a7713b1edbc | 1361 | * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder |
AnnaBridge | 171:3a7713b1edbc | 1362 | mode. |
AnnaBridge | 171:3a7713b1edbc | 1363 | */ |
AnnaBridge | 171:3a7713b1edbc | 1364 | #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR)) |
AnnaBridge | 171:3a7713b1edbc | 1365 | |
AnnaBridge | 171:3a7713b1edbc | 1366 | /** |
AnnaBridge | 171:3a7713b1edbc | 1367 | * @brief Sets the TIM active prescaler register value on update event. |
AnnaBridge | 171:3a7713b1edbc | 1368 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1369 | * @param __PRESC__ specifies the active prescaler register new value. |
AnnaBridge | 171:3a7713b1edbc | 1370 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1371 | */ |
AnnaBridge | 171:3a7713b1edbc | 1372 | #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) |
AnnaBridge | 171:3a7713b1edbc | 1373 | |
AnnaBridge | 171:3a7713b1edbc | 1374 | /** |
AnnaBridge | 171:3a7713b1edbc | 1375 | * @brief Sets the TIM Capture Compare Register value on runtime without |
AnnaBridge | 171:3a7713b1edbc | 1376 | * calling another time ConfigChannel function. |
AnnaBridge | 171:3a7713b1edbc | 1377 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1378 | * @param __CHANNEL__ TIM Channels to be configured. |
AnnaBridge | 171:3a7713b1edbc | 1379 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1380 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
AnnaBridge | 171:3a7713b1edbc | 1381 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
AnnaBridge | 171:3a7713b1edbc | 1382 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
AnnaBridge | 171:3a7713b1edbc | 1383 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
AnnaBridge | 171:3a7713b1edbc | 1384 | * @param __COMPARE__ specifies the Capture Compare register new value. |
AnnaBridge | 171:3a7713b1edbc | 1385 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1386 | */ |
AnnaBridge | 171:3a7713b1edbc | 1387 | #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ |
AnnaBridge | 171:3a7713b1edbc | 1388 | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__)) |
AnnaBridge | 171:3a7713b1edbc | 1389 | |
AnnaBridge | 171:3a7713b1edbc | 1390 | /** |
AnnaBridge | 171:3a7713b1edbc | 1391 | * @brief Gets the TIM Capture Compare Register value on runtime |
AnnaBridge | 171:3a7713b1edbc | 1392 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1393 | * @param __CHANNEL__ TIM Channel associated with the capture compare register |
AnnaBridge | 171:3a7713b1edbc | 1394 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1395 | * @arg TIM_CHANNEL_1: get capture/compare 1 register value |
AnnaBridge | 171:3a7713b1edbc | 1396 | * @arg TIM_CHANNEL_2: get capture/compare 2 register value |
AnnaBridge | 171:3a7713b1edbc | 1397 | * @arg TIM_CHANNEL_3: get capture/compare 3 register value |
AnnaBridge | 171:3a7713b1edbc | 1398 | * @arg TIM_CHANNEL_4: get capture/compare 4 register value |
AnnaBridge | 171:3a7713b1edbc | 1399 | * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) |
AnnaBridge | 171:3a7713b1edbc | 1400 | */ |
AnnaBridge | 171:3a7713b1edbc | 1401 | #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ |
AnnaBridge | 171:3a7713b1edbc | 1402 | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U))) |
AnnaBridge | 171:3a7713b1edbc | 1403 | |
AnnaBridge | 171:3a7713b1edbc | 1404 | /** |
AnnaBridge | 171:3a7713b1edbc | 1405 | * @brief Sets the TIM Counter Register value on runtime. |
AnnaBridge | 171:3a7713b1edbc | 1406 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1407 | * @param __COUNTER__ specifies the Counter register new value. |
AnnaBridge | 171:3a7713b1edbc | 1408 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1409 | */ |
AnnaBridge | 171:3a7713b1edbc | 1410 | #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) |
AnnaBridge | 171:3a7713b1edbc | 1411 | |
AnnaBridge | 171:3a7713b1edbc | 1412 | /** |
AnnaBridge | 171:3a7713b1edbc | 1413 | * @brief Gets the TIM Counter Register value on runtime. |
AnnaBridge | 171:3a7713b1edbc | 1414 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1415 | * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) |
AnnaBridge | 171:3a7713b1edbc | 1416 | */ |
AnnaBridge | 171:3a7713b1edbc | 1417 | #define __HAL_TIM_GET_COUNTER(__HANDLE__) \ |
AnnaBridge | 171:3a7713b1edbc | 1418 | ((__HANDLE__)->Instance->CNT) |
AnnaBridge | 171:3a7713b1edbc | 1419 | |
AnnaBridge | 171:3a7713b1edbc | 1420 | /** |
AnnaBridge | 171:3a7713b1edbc | 1421 | * @brief Sets the TIM Autoreload Register value on runtime without calling |
AnnaBridge | 171:3a7713b1edbc | 1422 | * another time any Init function. |
AnnaBridge | 171:3a7713b1edbc | 1423 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1424 | * @param __AUTORELOAD__ specifies the Counter register new value. |
AnnaBridge | 171:3a7713b1edbc | 1425 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1426 | */ |
AnnaBridge | 171:3a7713b1edbc | 1427 | #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ |
AnnaBridge | 171:3a7713b1edbc | 1428 | do{ \ |
AnnaBridge | 171:3a7713b1edbc | 1429 | (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ |
AnnaBridge | 171:3a7713b1edbc | 1430 | (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ |
AnnaBridge | 171:3a7713b1edbc | 1431 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1432 | |
AnnaBridge | 171:3a7713b1edbc | 1433 | /** |
AnnaBridge | 171:3a7713b1edbc | 1434 | * @brief Gets the TIM Autoreload Register value on runtime |
AnnaBridge | 171:3a7713b1edbc | 1435 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1436 | * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) |
AnnaBridge | 171:3a7713b1edbc | 1437 | */ |
AnnaBridge | 171:3a7713b1edbc | 1438 | #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ |
AnnaBridge | 171:3a7713b1edbc | 1439 | ((__HANDLE__)->Instance->ARR) |
AnnaBridge | 171:3a7713b1edbc | 1440 | |
AnnaBridge | 171:3a7713b1edbc | 1441 | /** |
AnnaBridge | 171:3a7713b1edbc | 1442 | * @brief Sets the TIM Clock Division value on runtime without calling |
AnnaBridge | 171:3a7713b1edbc | 1443 | * another time any Init function. |
AnnaBridge | 171:3a7713b1edbc | 1444 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1445 | * @param __CKD__ specifies the clock division value. |
AnnaBridge | 171:3a7713b1edbc | 1446 | * This parameter can be one of the following value: |
AnnaBridge | 171:3a7713b1edbc | 1447 | * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT |
AnnaBridge | 171:3a7713b1edbc | 1448 | * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT |
AnnaBridge | 171:3a7713b1edbc | 1449 | * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT |
AnnaBridge | 171:3a7713b1edbc | 1450 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1451 | */ |
AnnaBridge | 171:3a7713b1edbc | 1452 | #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ |
AnnaBridge | 171:3a7713b1edbc | 1453 | do{ \ |
AnnaBridge | 171:3a7713b1edbc | 1454 | (__HANDLE__)->Instance->CR1 &= ~TIM_CR1_CKD; \ |
AnnaBridge | 171:3a7713b1edbc | 1455 | (__HANDLE__)->Instance->CR1 |= (__CKD__); \ |
AnnaBridge | 171:3a7713b1edbc | 1456 | (__HANDLE__)->Init.ClockDivision = (__CKD__); \ |
AnnaBridge | 171:3a7713b1edbc | 1457 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1458 | |
AnnaBridge | 171:3a7713b1edbc | 1459 | /** |
AnnaBridge | 171:3a7713b1edbc | 1460 | * @brief Gets the TIM Clock Division value on runtime |
AnnaBridge | 171:3a7713b1edbc | 1461 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1462 | * @retval The clock division can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1463 | * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT |
AnnaBridge | 171:3a7713b1edbc | 1464 | * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT |
AnnaBridge | 171:3a7713b1edbc | 1465 | * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT |
AnnaBridge | 171:3a7713b1edbc | 1466 | */ |
AnnaBridge | 171:3a7713b1edbc | 1467 | #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ |
AnnaBridge | 171:3a7713b1edbc | 1468 | ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) |
AnnaBridge | 171:3a7713b1edbc | 1469 | |
AnnaBridge | 171:3a7713b1edbc | 1470 | /** |
AnnaBridge | 171:3a7713b1edbc | 1471 | * @brief Sets the TIM Output compare preload. |
AnnaBridge | 171:3a7713b1edbc | 1472 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1473 | * @param __CHANNEL__ TIM Channels to be configured. |
AnnaBridge | 171:3a7713b1edbc | 1474 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1475 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
AnnaBridge | 171:3a7713b1edbc | 1476 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
AnnaBridge | 171:3a7713b1edbc | 1477 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
AnnaBridge | 171:3a7713b1edbc | 1478 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
AnnaBridge | 171:3a7713b1edbc | 1479 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1480 | */ |
AnnaBridge | 171:3a7713b1edbc | 1481 | #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ |
AnnaBridge | 171:3a7713b1edbc | 1482 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ |
AnnaBridge | 171:3a7713b1edbc | 1483 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ |
AnnaBridge | 171:3a7713b1edbc | 1484 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ |
AnnaBridge | 171:3a7713b1edbc | 1485 | ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) |
AnnaBridge | 171:3a7713b1edbc | 1486 | |
AnnaBridge | 171:3a7713b1edbc | 1487 | /** |
AnnaBridge | 171:3a7713b1edbc | 1488 | * @brief Resets the TIM Output compare preload. |
AnnaBridge | 171:3a7713b1edbc | 1489 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1490 | * @param __CHANNEL__ TIM Channels to be configured. |
AnnaBridge | 171:3a7713b1edbc | 1491 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1492 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
AnnaBridge | 171:3a7713b1edbc | 1493 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
AnnaBridge | 171:3a7713b1edbc | 1494 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
AnnaBridge | 171:3a7713b1edbc | 1495 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
AnnaBridge | 171:3a7713b1edbc | 1496 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1497 | */ |
AnnaBridge | 171:3a7713b1edbc | 1498 | #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ |
AnnaBridge | 171:3a7713b1edbc | 1499 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ |
AnnaBridge | 171:3a7713b1edbc | 1500 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ |
AnnaBridge | 171:3a7713b1edbc | 1501 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ |
AnnaBridge | 171:3a7713b1edbc | 1502 | ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE)) |
AnnaBridge | 171:3a7713b1edbc | 1503 | |
AnnaBridge | 171:3a7713b1edbc | 1504 | |
AnnaBridge | 171:3a7713b1edbc | 1505 | /** |
AnnaBridge | 171:3a7713b1edbc | 1506 | * @brief Sets the TIM Input Capture prescaler on runtime without calling |
AnnaBridge | 171:3a7713b1edbc | 1507 | * another time HAL_TIM_IC_ConfigChannel() function. |
AnnaBridge | 171:3a7713b1edbc | 1508 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1509 | * @param __CHANNEL__ TIM Channels to be configured. |
AnnaBridge | 171:3a7713b1edbc | 1510 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1511 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
AnnaBridge | 171:3a7713b1edbc | 1512 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
AnnaBridge | 171:3a7713b1edbc | 1513 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
AnnaBridge | 171:3a7713b1edbc | 1514 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
AnnaBridge | 171:3a7713b1edbc | 1515 | * @param __ICPSC__ specifies the Input Capture4 prescaler new value. |
AnnaBridge | 171:3a7713b1edbc | 1516 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1517 | * @arg TIM_ICPSC_DIV1: no prescaler |
AnnaBridge | 171:3a7713b1edbc | 1518 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
AnnaBridge | 171:3a7713b1edbc | 1519 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
AnnaBridge | 171:3a7713b1edbc | 1520 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
AnnaBridge | 171:3a7713b1edbc | 1521 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1522 | */ |
AnnaBridge | 171:3a7713b1edbc | 1523 | #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
AnnaBridge | 171:3a7713b1edbc | 1524 | do{ \ |
AnnaBridge | 171:3a7713b1edbc | 1525 | TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ |
AnnaBridge | 171:3a7713b1edbc | 1526 | TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ |
AnnaBridge | 171:3a7713b1edbc | 1527 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1528 | |
AnnaBridge | 171:3a7713b1edbc | 1529 | /** |
AnnaBridge | 171:3a7713b1edbc | 1530 | * @brief Gets the TIM Input Capture prescaler on runtime |
AnnaBridge | 171:3a7713b1edbc | 1531 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1532 | * @param __CHANNEL__ TIM Channels to be configured. |
AnnaBridge | 171:3a7713b1edbc | 1533 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1534 | * @arg TIM_CHANNEL_1: get input capture 1 prescaler value |
AnnaBridge | 171:3a7713b1edbc | 1535 | * @arg TIM_CHANNEL_2: get input capture 2 prescaler value |
AnnaBridge | 171:3a7713b1edbc | 1536 | * @arg TIM_CHANNEL_3: get input capture 3 prescaler value |
AnnaBridge | 171:3a7713b1edbc | 1537 | * @arg TIM_CHANNEL_4: get input capture 4 prescaler value |
AnnaBridge | 171:3a7713b1edbc | 1538 | * @retval The input capture prescaler can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1539 | * @arg TIM_ICPSC_DIV1: no prescaler |
AnnaBridge | 171:3a7713b1edbc | 1540 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
AnnaBridge | 171:3a7713b1edbc | 1541 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
AnnaBridge | 171:3a7713b1edbc | 1542 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
AnnaBridge | 171:3a7713b1edbc | 1543 | */ |
AnnaBridge | 171:3a7713b1edbc | 1544 | #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ |
AnnaBridge | 171:3a7713b1edbc | 1545 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ |
AnnaBridge | 171:3a7713b1edbc | 1546 | ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ |
AnnaBridge | 171:3a7713b1edbc | 1547 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ |
AnnaBridge | 171:3a7713b1edbc | 1548 | (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) |
AnnaBridge | 171:3a7713b1edbc | 1549 | |
AnnaBridge | 171:3a7713b1edbc | 1550 | /** |
AnnaBridge | 171:3a7713b1edbc | 1551 | * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register |
AnnaBridge | 171:3a7713b1edbc | 1552 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1553 | * @note When the USR bit of the TIMx_CR1 register is set, only counter |
AnnaBridge | 171:3a7713b1edbc | 1554 | * overflow/underflow generates an update interrupt or DMA request (if |
AnnaBridge | 171:3a7713b1edbc | 1555 | * enabled) |
AnnaBridge | 171:3a7713b1edbc | 1556 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1557 | */ |
AnnaBridge | 171:3a7713b1edbc | 1558 | #define __HAL_TIM_URS_ENABLE(__HANDLE__) \ |
AnnaBridge | 171:3a7713b1edbc | 1559 | ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS)) |
AnnaBridge | 171:3a7713b1edbc | 1560 | |
AnnaBridge | 171:3a7713b1edbc | 1561 | /** |
AnnaBridge | 171:3a7713b1edbc | 1562 | * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register |
AnnaBridge | 171:3a7713b1edbc | 1563 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1564 | * @note When the USR bit of the TIMx_CR1 register is reset, any of the |
AnnaBridge | 171:3a7713b1edbc | 1565 | * following events generate an update interrupt or DMA request (if |
AnnaBridge | 171:3a7713b1edbc | 1566 | * enabled): |
AnnaBridge | 171:3a7713b1edbc | 1567 | * (+) Counter overflow/underflow |
AnnaBridge | 171:3a7713b1edbc | 1568 | * (+) Setting the UG bit |
AnnaBridge | 171:3a7713b1edbc | 1569 | * (+) Update generation through the slave mode controller |
AnnaBridge | 171:3a7713b1edbc | 1570 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1571 | */ |
AnnaBridge | 171:3a7713b1edbc | 1572 | #define __HAL_TIM_URS_DISABLE(__HANDLE__) \ |
AnnaBridge | 171:3a7713b1edbc | 1573 | ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) |
AnnaBridge | 171:3a7713b1edbc | 1574 | |
AnnaBridge | 171:3a7713b1edbc | 1575 | /** |
AnnaBridge | 171:3a7713b1edbc | 1576 | * @brief Sets the TIM Capture x input polarity on runtime. |
AnnaBridge | 171:3a7713b1edbc | 1577 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 171:3a7713b1edbc | 1578 | * @param __CHANNEL__ TIM Channels to be configured. |
AnnaBridge | 171:3a7713b1edbc | 1579 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1580 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
AnnaBridge | 171:3a7713b1edbc | 1581 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
AnnaBridge | 171:3a7713b1edbc | 1582 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
AnnaBridge | 171:3a7713b1edbc | 1583 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
AnnaBridge | 171:3a7713b1edbc | 1584 | * @param __POLARITY__ Polarity for TIx source |
AnnaBridge | 171:3a7713b1edbc | 1585 | * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge |
AnnaBridge | 171:3a7713b1edbc | 1586 | * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge |
AnnaBridge | 171:3a7713b1edbc | 1587 | * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge |
AnnaBridge | 171:3a7713b1edbc | 1588 | * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. |
AnnaBridge | 171:3a7713b1edbc | 1589 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1590 | */ |
AnnaBridge | 171:3a7713b1edbc | 1591 | #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
AnnaBridge | 171:3a7713b1edbc | 1592 | do{ \ |
AnnaBridge | 171:3a7713b1edbc | 1593 | TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ |
AnnaBridge | 171:3a7713b1edbc | 1594 | TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ |
AnnaBridge | 171:3a7713b1edbc | 1595 | }while(0) |
AnnaBridge | 171:3a7713b1edbc | 1596 | |
AnnaBridge | 171:3a7713b1edbc | 1597 | /** |
AnnaBridge | 171:3a7713b1edbc | 1598 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1599 | */ |
AnnaBridge | 171:3a7713b1edbc | 1600 | |
AnnaBridge | 171:3a7713b1edbc | 1601 | /* Include TIM HAL Extension module */ |
AnnaBridge | 171:3a7713b1edbc | 1602 | #include "stm32f0xx_hal_tim_ex.h" |
AnnaBridge | 171:3a7713b1edbc | 1603 | |
AnnaBridge | 171:3a7713b1edbc | 1604 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 1605 | /** @addtogroup TIM_Exported_Functions |
AnnaBridge | 171:3a7713b1edbc | 1606 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1607 | */ |
AnnaBridge | 171:3a7713b1edbc | 1608 | |
AnnaBridge | 171:3a7713b1edbc | 1609 | /** @addtogroup TIM_Exported_Functions_Group1 |
AnnaBridge | 171:3a7713b1edbc | 1610 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1611 | */ |
AnnaBridge | 171:3a7713b1edbc | 1612 | /* Time Base functions ********************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 1613 | HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1614 | HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1615 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1616 | void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1617 | /* Blocking mode: Polling */ |
AnnaBridge | 171:3a7713b1edbc | 1618 | HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1619 | HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1620 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 1621 | HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1622 | HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1623 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 171:3a7713b1edbc | 1624 | HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); |
AnnaBridge | 171:3a7713b1edbc | 1625 | HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1626 | /** |
AnnaBridge | 171:3a7713b1edbc | 1627 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1628 | */ |
AnnaBridge | 171:3a7713b1edbc | 1629 | |
AnnaBridge | 171:3a7713b1edbc | 1630 | /** @addtogroup TIM_Exported_Functions_Group2 |
AnnaBridge | 171:3a7713b1edbc | 1631 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1632 | */ |
AnnaBridge | 171:3a7713b1edbc | 1633 | /* Timer Output Compare functions **********************************************/ |
AnnaBridge | 171:3a7713b1edbc | 1634 | HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1635 | HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1636 | void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1637 | void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1638 | /* Blocking mode: Polling */ |
AnnaBridge | 171:3a7713b1edbc | 1639 | HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1640 | HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1641 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 1642 | HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1643 | HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1644 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 171:3a7713b1edbc | 1645 | HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
AnnaBridge | 171:3a7713b1edbc | 1646 | HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1647 | |
AnnaBridge | 171:3a7713b1edbc | 1648 | /** |
AnnaBridge | 171:3a7713b1edbc | 1649 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1650 | */ |
AnnaBridge | 171:3a7713b1edbc | 1651 | |
AnnaBridge | 171:3a7713b1edbc | 1652 | /** @addtogroup TIM_Exported_Functions_Group3 |
AnnaBridge | 171:3a7713b1edbc | 1653 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1654 | */ |
AnnaBridge | 171:3a7713b1edbc | 1655 | /* Timer PWM functions *********************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 1656 | HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1657 | HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1658 | void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1659 | void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1660 | /* Blocking mode: Polling */ |
AnnaBridge | 171:3a7713b1edbc | 1661 | HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1662 | HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1663 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 1664 | HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1665 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1666 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 171:3a7713b1edbc | 1667 | HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
AnnaBridge | 171:3a7713b1edbc | 1668 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1669 | /** |
AnnaBridge | 171:3a7713b1edbc | 1670 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1671 | */ |
AnnaBridge | 171:3a7713b1edbc | 1672 | |
AnnaBridge | 171:3a7713b1edbc | 1673 | /** @addtogroup TIM_Exported_Functions_Group4 |
AnnaBridge | 171:3a7713b1edbc | 1674 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1675 | */ |
AnnaBridge | 171:3a7713b1edbc | 1676 | /* Timer Input Capture functions ***********************************************/ |
AnnaBridge | 171:3a7713b1edbc | 1677 | HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1678 | HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1679 | void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1680 | void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1681 | /* Blocking mode: Polling */ |
AnnaBridge | 171:3a7713b1edbc | 1682 | HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1683 | HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1684 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 1685 | HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1686 | HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1687 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 171:3a7713b1edbc | 1688 | HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
AnnaBridge | 171:3a7713b1edbc | 1689 | HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1690 | /** |
AnnaBridge | 171:3a7713b1edbc | 1691 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1692 | */ |
AnnaBridge | 171:3a7713b1edbc | 1693 | |
AnnaBridge | 171:3a7713b1edbc | 1694 | /** @addtogroup TIM_Exported_Functions_Group5 |
AnnaBridge | 171:3a7713b1edbc | 1695 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1696 | */ |
AnnaBridge | 171:3a7713b1edbc | 1697 | /* Timer One Pulse functions ***************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 1698 | HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); |
AnnaBridge | 171:3a7713b1edbc | 1699 | HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1700 | void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1701 | void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1702 | /* Blocking mode: Polling */ |
AnnaBridge | 171:3a7713b1edbc | 1703 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
AnnaBridge | 171:3a7713b1edbc | 1704 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
AnnaBridge | 171:3a7713b1edbc | 1705 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 1706 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
AnnaBridge | 171:3a7713b1edbc | 1707 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
AnnaBridge | 171:3a7713b1edbc | 1708 | /** |
AnnaBridge | 171:3a7713b1edbc | 1709 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1710 | */ |
AnnaBridge | 171:3a7713b1edbc | 1711 | |
AnnaBridge | 171:3a7713b1edbc | 1712 | /** @addtogroup TIM_Exported_Functions_Group6 |
AnnaBridge | 171:3a7713b1edbc | 1713 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1714 | */ |
AnnaBridge | 171:3a7713b1edbc | 1715 | /* Timer Encoder functions *****************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 1716 | HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); |
AnnaBridge | 171:3a7713b1edbc | 1717 | HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1718 | void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1719 | void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1720 | /* Blocking mode: Polling */ |
AnnaBridge | 171:3a7713b1edbc | 1721 | HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1722 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1723 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 1724 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1725 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1726 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 171:3a7713b1edbc | 1727 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); |
AnnaBridge | 171:3a7713b1edbc | 1728 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1729 | |
AnnaBridge | 171:3a7713b1edbc | 1730 | /** |
AnnaBridge | 171:3a7713b1edbc | 1731 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1732 | */ |
AnnaBridge | 171:3a7713b1edbc | 1733 | |
AnnaBridge | 171:3a7713b1edbc | 1734 | /** @addtogroup TIM_Exported_Functions_Group7 |
AnnaBridge | 171:3a7713b1edbc | 1735 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1736 | */ |
AnnaBridge | 171:3a7713b1edbc | 1737 | /* Interrupt Handler functions **********************************************/ |
AnnaBridge | 171:3a7713b1edbc | 1738 | void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1739 | /** |
AnnaBridge | 171:3a7713b1edbc | 1740 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1741 | */ |
AnnaBridge | 171:3a7713b1edbc | 1742 | |
AnnaBridge | 171:3a7713b1edbc | 1743 | /** @addtogroup TIM_Exported_Functions_Group8 |
AnnaBridge | 171:3a7713b1edbc | 1744 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1745 | */ |
AnnaBridge | 171:3a7713b1edbc | 1746 | /* Control functions *********************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 1747 | HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1748 | HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1749 | HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1750 | HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); |
AnnaBridge | 171:3a7713b1edbc | 1751 | HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1752 | HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); |
AnnaBridge | 171:3a7713b1edbc | 1753 | HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); |
AnnaBridge | 171:3a7713b1edbc | 1754 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); |
AnnaBridge | 171:3a7713b1edbc | 1755 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); |
AnnaBridge | 171:3a7713b1edbc | 1756 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
AnnaBridge | 171:3a7713b1edbc | 1757 | uint32_t *BurstBuffer, uint32_t BurstLength); |
AnnaBridge | 171:3a7713b1edbc | 1758 | HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
AnnaBridge | 171:3a7713b1edbc | 1759 | uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); |
AnnaBridge | 171:3a7713b1edbc | 1760 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
AnnaBridge | 171:3a7713b1edbc | 1761 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
AnnaBridge | 171:3a7713b1edbc | 1762 | uint32_t *BurstBuffer, uint32_t BurstLength); |
AnnaBridge | 171:3a7713b1edbc | 1763 | HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
AnnaBridge | 171:3a7713b1edbc | 1764 | uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); |
AnnaBridge | 171:3a7713b1edbc | 1765 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
AnnaBridge | 171:3a7713b1edbc | 1766 | HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); |
AnnaBridge | 171:3a7713b1edbc | 1767 | uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 1768 | |
AnnaBridge | 171:3a7713b1edbc | 1769 | /** |
AnnaBridge | 171:3a7713b1edbc | 1770 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1771 | */ |
AnnaBridge | 171:3a7713b1edbc | 1772 | |
AnnaBridge | 171:3a7713b1edbc | 1773 | /** @addtogroup TIM_Exported_Functions_Group9 |
AnnaBridge | 171:3a7713b1edbc | 1774 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1775 | */ |
AnnaBridge | 171:3a7713b1edbc | 1776 | /* Callback in non blocking modes (Interrupt and DMA) *************************/ |
AnnaBridge | 171:3a7713b1edbc | 1777 | void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1778 | void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1779 | void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1780 | void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1781 | void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1782 | void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1783 | /** |
AnnaBridge | 171:3a7713b1edbc | 1784 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1785 | */ |
AnnaBridge | 171:3a7713b1edbc | 1786 | |
AnnaBridge | 171:3a7713b1edbc | 1787 | /** @addtogroup TIM_Exported_Functions_Group10 |
AnnaBridge | 171:3a7713b1edbc | 1788 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1789 | */ |
AnnaBridge | 171:3a7713b1edbc | 1790 | /* Peripheral State functions **************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 1791 | HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1792 | HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1793 | HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1794 | HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1795 | HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1796 | HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 171:3a7713b1edbc | 1797 | |
AnnaBridge | 171:3a7713b1edbc | 1798 | /** |
AnnaBridge | 171:3a7713b1edbc | 1799 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1800 | */ |
AnnaBridge | 171:3a7713b1edbc | 1801 | |
AnnaBridge | 171:3a7713b1edbc | 1802 | /** |
AnnaBridge | 171:3a7713b1edbc | 1803 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1804 | */ |
AnnaBridge | 171:3a7713b1edbc | 1805 | |
AnnaBridge | 171:3a7713b1edbc | 1806 | /* Private Functions --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 1807 | /** @addtogroup TIM_Private_Functions |
AnnaBridge | 171:3a7713b1edbc | 1808 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1809 | */ |
AnnaBridge | 171:3a7713b1edbc | 1810 | void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, |
AnnaBridge | 171:3a7713b1edbc | 1811 | uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); |
AnnaBridge | 171:3a7713b1edbc | 1812 | /** |
AnnaBridge | 171:3a7713b1edbc | 1813 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1814 | */ |
AnnaBridge | 171:3a7713b1edbc | 1815 | |
AnnaBridge | 171:3a7713b1edbc | 1816 | /** |
AnnaBridge | 171:3a7713b1edbc | 1817 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1818 | */ |
AnnaBridge | 171:3a7713b1edbc | 1819 | |
AnnaBridge | 171:3a7713b1edbc | 1820 | /** |
AnnaBridge | 171:3a7713b1edbc | 1821 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1822 | */ |
AnnaBridge | 171:3a7713b1edbc | 1823 | |
AnnaBridge | 171:3a7713b1edbc | 1824 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 1825 | } |
AnnaBridge | 171:3a7713b1edbc | 1826 | #endif |
AnnaBridge | 171:3a7713b1edbc | 1827 | |
AnnaBridge | 171:3a7713b1edbc | 1828 | #endif /* __STM32F0xx_HAL_TIM_H */ |
AnnaBridge | 171:3a7713b1edbc | 1829 | |
AnnaBridge | 171:3a7713b1edbc | 1830 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |