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mbed 2

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TARGET_NUCLEO_L011K4/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_cortex.h@157:e7ca05fa8600, 2017-11-09 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 09 11:14:10 2017 +0000
Revision:
157:e7ca05fa8600
Child:
167:84c0a372a020
Release 155 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 157:e7ca05fa8600 1 /**
AnnaBridge 157:e7ca05fa8600 2 ******************************************************************************
AnnaBridge 157:e7ca05fa8600 3 * @file stm32l0xx_hal_cortex.h
AnnaBridge 157:e7ca05fa8600 4 * @author MCD Application Team
AnnaBridge 157:e7ca05fa8600 5 * @version V1.7.0
AnnaBridge 157:e7ca05fa8600 6 * @date 31-May-2016
AnnaBridge 157:e7ca05fa8600 7 * @brief Header file of CORTEX HAL module.
AnnaBridge 157:e7ca05fa8600 8 ******************************************************************************
AnnaBridge 157:e7ca05fa8600 9 * @attention
AnnaBridge 157:e7ca05fa8600 10 *
AnnaBridge 157:e7ca05fa8600 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 157:e7ca05fa8600 12 *
AnnaBridge 157:e7ca05fa8600 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 157:e7ca05fa8600 14 * are permitted provided that the following conditions are met:
AnnaBridge 157:e7ca05fa8600 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 157:e7ca05fa8600 16 * this list of conditions and the following disclaimer.
AnnaBridge 157:e7ca05fa8600 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 157:e7ca05fa8600 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 157:e7ca05fa8600 19 * and/or other materials provided with the distribution.
AnnaBridge 157:e7ca05fa8600 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 157:e7ca05fa8600 21 * may be used to endorse or promote products derived from this software
AnnaBridge 157:e7ca05fa8600 22 * without specific prior written permission.
AnnaBridge 157:e7ca05fa8600 23 *
AnnaBridge 157:e7ca05fa8600 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 157:e7ca05fa8600 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 157:e7ca05fa8600 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 157:e7ca05fa8600 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 157:e7ca05fa8600 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 157:e7ca05fa8600 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 157:e7ca05fa8600 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 157:e7ca05fa8600 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 157:e7ca05fa8600 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 157:e7ca05fa8600 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 157:e7ca05fa8600 34 *
AnnaBridge 157:e7ca05fa8600 35 ******************************************************************************
AnnaBridge 157:e7ca05fa8600 36 */
AnnaBridge 157:e7ca05fa8600 37
AnnaBridge 157:e7ca05fa8600 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 157:e7ca05fa8600 39 #ifndef __STM32L0xx_HAL_CORTEX_H
AnnaBridge 157:e7ca05fa8600 40 #define __STM32L0xx_HAL_CORTEX_H
AnnaBridge 157:e7ca05fa8600 41
AnnaBridge 157:e7ca05fa8600 42 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 43 extern "C" {
AnnaBridge 157:e7ca05fa8600 44 #endif
AnnaBridge 157:e7ca05fa8600 45
AnnaBridge 157:e7ca05fa8600 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 47 #include "stm32l0xx_hal_def.h"
AnnaBridge 157:e7ca05fa8600 48
AnnaBridge 157:e7ca05fa8600 49 /** @addtogroup STM32L0xx_HAL_Driver
AnnaBridge 157:e7ca05fa8600 50 * @{
AnnaBridge 157:e7ca05fa8600 51 */
AnnaBridge 157:e7ca05fa8600 52
AnnaBridge 157:e7ca05fa8600 53 /** @defgroup CORTEX CORTEX
AnnaBridge 157:e7ca05fa8600 54 * @{
AnnaBridge 157:e7ca05fa8600 55 */
AnnaBridge 157:e7ca05fa8600 56 /* Exported types ------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 57
AnnaBridge 157:e7ca05fa8600 58 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types
AnnaBridge 157:e7ca05fa8600 59 * @{
AnnaBridge 157:e7ca05fa8600 60 */
AnnaBridge 157:e7ca05fa8600 61
AnnaBridge 157:e7ca05fa8600 62 #if (__MPU_PRESENT == 1)
AnnaBridge 157:e7ca05fa8600 63 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
AnnaBridge 157:e7ca05fa8600 64 * @{
AnnaBridge 157:e7ca05fa8600 65 */
AnnaBridge 157:e7ca05fa8600 66 typedef struct
AnnaBridge 157:e7ca05fa8600 67 {
AnnaBridge 157:e7ca05fa8600 68 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
AnnaBridge 157:e7ca05fa8600 69
AnnaBridge 157:e7ca05fa8600 70 uint8_t Enable; /*!< Specifies the status of the region.
AnnaBridge 157:e7ca05fa8600 71 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
AnnaBridge 157:e7ca05fa8600 72 uint8_t Number; /*!< Specifies the number of the region to protect.
AnnaBridge 157:e7ca05fa8600 73 This parameter can be a value of @ref CORTEX_MPU_Region_Number */
AnnaBridge 157:e7ca05fa8600 74
AnnaBridge 157:e7ca05fa8600 75 uint8_t Size; /*!< Specifies the size of the region to protect.
AnnaBridge 157:e7ca05fa8600 76 This parameter can be a value of @ref CORTEX_MPU_Region_Size */
AnnaBridge 157:e7ca05fa8600 77 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
AnnaBridge 157:e7ca05fa8600 78 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
AnnaBridge 157:e7ca05fa8600 79 uint8_t TypeExtField; /*!< This parameter is NOT used but is kept to keep API unified through all families*/
AnnaBridge 157:e7ca05fa8600 80
AnnaBridge 157:e7ca05fa8600 81 uint8_t AccessPermission; /*!< Specifies the region access permission type.
AnnaBridge 157:e7ca05fa8600 82 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
AnnaBridge 157:e7ca05fa8600 83 uint8_t DisableExec; /*!< Specifies the instruction access status.
AnnaBridge 157:e7ca05fa8600 84 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
AnnaBridge 157:e7ca05fa8600 85 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
AnnaBridge 157:e7ca05fa8600 86 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
AnnaBridge 157:e7ca05fa8600 87 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
AnnaBridge 157:e7ca05fa8600 88 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
AnnaBridge 157:e7ca05fa8600 89 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
AnnaBridge 157:e7ca05fa8600 90 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
AnnaBridge 157:e7ca05fa8600 91 }MPU_Region_InitTypeDef;
AnnaBridge 157:e7ca05fa8600 92 /**
AnnaBridge 157:e7ca05fa8600 93 * @}
AnnaBridge 157:e7ca05fa8600 94 */
AnnaBridge 157:e7ca05fa8600 95 #endif /* __MPU_PRESENT */
AnnaBridge 157:e7ca05fa8600 96
AnnaBridge 157:e7ca05fa8600 97 /**
AnnaBridge 157:e7ca05fa8600 98 * @}
AnnaBridge 157:e7ca05fa8600 99 */
AnnaBridge 157:e7ca05fa8600 100
AnnaBridge 157:e7ca05fa8600 101
AnnaBridge 157:e7ca05fa8600 102 /* Exported constants --------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 103
AnnaBridge 157:e7ca05fa8600 104 /** @defgroup CORTEX_Exported_Constants CORTEx Exported Constants
AnnaBridge 157:e7ca05fa8600 105 * @{
AnnaBridge 157:e7ca05fa8600 106 */
AnnaBridge 157:e7ca05fa8600 107
AnnaBridge 157:e7ca05fa8600 108
AnnaBridge 157:e7ca05fa8600 109 #define IS_NVIC_PREEMPTION_PRIORITY(__PRIORITY__) ((__PRIORITY__) < 0x4U)
AnnaBridge 157:e7ca05fa8600 110
AnnaBridge 157:e7ca05fa8600 111 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x0)
AnnaBridge 157:e7ca05fa8600 112
AnnaBridge 157:e7ca05fa8600 113 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick Clock Source
AnnaBridge 157:e7ca05fa8600 114 * @{
AnnaBridge 157:e7ca05fa8600 115 */
AnnaBridge 157:e7ca05fa8600 116 #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)
AnnaBridge 157:e7ca05fa8600 117 #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)
AnnaBridge 157:e7ca05fa8600 118 #define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \
AnnaBridge 157:e7ca05fa8600 119 ((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8))
AnnaBridge 157:e7ca05fa8600 120 /**
AnnaBridge 157:e7ca05fa8600 121 * @}
AnnaBridge 157:e7ca05fa8600 122 */
AnnaBridge 157:e7ca05fa8600 123
AnnaBridge 157:e7ca05fa8600 124 #if (__MPU_PRESENT == 1)
AnnaBridge 157:e7ca05fa8600 125 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
AnnaBridge 157:e7ca05fa8600 126 * @{
AnnaBridge 157:e7ca05fa8600 127 */
AnnaBridge 157:e7ca05fa8600 128 #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)
AnnaBridge 157:e7ca05fa8600 129 #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)
AnnaBridge 157:e7ca05fa8600 130 #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)
AnnaBridge 157:e7ca05fa8600 131 #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)
AnnaBridge 157:e7ca05fa8600 132 /**
AnnaBridge 157:e7ca05fa8600 133 * @}
AnnaBridge 157:e7ca05fa8600 134 */
AnnaBridge 157:e7ca05fa8600 135
AnnaBridge 157:e7ca05fa8600 136 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
AnnaBridge 157:e7ca05fa8600 137 * @{
AnnaBridge 157:e7ca05fa8600 138 */
AnnaBridge 157:e7ca05fa8600 139 #define MPU_REGION_ENABLE ((uint8_t)0x01U)
AnnaBridge 157:e7ca05fa8600 140 #define MPU_REGION_DISABLE ((uint8_t)0x00U)
AnnaBridge 157:e7ca05fa8600 141 /**
AnnaBridge 157:e7ca05fa8600 142 * @}
AnnaBridge 157:e7ca05fa8600 143 */
AnnaBridge 157:e7ca05fa8600 144
AnnaBridge 157:e7ca05fa8600 145 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
AnnaBridge 157:e7ca05fa8600 146 * @{
AnnaBridge 157:e7ca05fa8600 147 */
AnnaBridge 157:e7ca05fa8600 148 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
AnnaBridge 157:e7ca05fa8600 149 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
AnnaBridge 157:e7ca05fa8600 150 /**
AnnaBridge 157:e7ca05fa8600 151 * @}
AnnaBridge 157:e7ca05fa8600 152 */
AnnaBridge 157:e7ca05fa8600 153
AnnaBridge 157:e7ca05fa8600 154 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
AnnaBridge 157:e7ca05fa8600 155 * @{
AnnaBridge 157:e7ca05fa8600 156 */
AnnaBridge 157:e7ca05fa8600 157 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
AnnaBridge 157:e7ca05fa8600 158 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
AnnaBridge 157:e7ca05fa8600 159 /**
AnnaBridge 157:e7ca05fa8600 160 * @}
AnnaBridge 157:e7ca05fa8600 161 */
AnnaBridge 157:e7ca05fa8600 162
AnnaBridge 157:e7ca05fa8600 163 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
AnnaBridge 157:e7ca05fa8600 164 * @{
AnnaBridge 157:e7ca05fa8600 165 */
AnnaBridge 157:e7ca05fa8600 166 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
AnnaBridge 157:e7ca05fa8600 167 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
AnnaBridge 157:e7ca05fa8600 168 /**
AnnaBridge 157:e7ca05fa8600 169 * @}
AnnaBridge 157:e7ca05fa8600 170 */
AnnaBridge 157:e7ca05fa8600 171
AnnaBridge 157:e7ca05fa8600 172 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
AnnaBridge 157:e7ca05fa8600 173 * @{
AnnaBridge 157:e7ca05fa8600 174 */
AnnaBridge 157:e7ca05fa8600 175 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
AnnaBridge 157:e7ca05fa8600 176 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
AnnaBridge 157:e7ca05fa8600 177 /**
AnnaBridge 157:e7ca05fa8600 178 * @}
AnnaBridge 157:e7ca05fa8600 179 */
AnnaBridge 157:e7ca05fa8600 180
AnnaBridge 157:e7ca05fa8600 181 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
AnnaBridge 157:e7ca05fa8600 182 * @{
AnnaBridge 157:e7ca05fa8600 183 */
AnnaBridge 157:e7ca05fa8600 184 #define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
AnnaBridge 157:e7ca05fa8600 185 #define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
AnnaBridge 157:e7ca05fa8600 186 #define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
AnnaBridge 157:e7ca05fa8600 187 #define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
AnnaBridge 157:e7ca05fa8600 188 #define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
AnnaBridge 157:e7ca05fa8600 189 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
AnnaBridge 157:e7ca05fa8600 190 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
AnnaBridge 157:e7ca05fa8600 191 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
AnnaBridge 157:e7ca05fa8600 192 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
AnnaBridge 157:e7ca05fa8600 193 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
AnnaBridge 157:e7ca05fa8600 194 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
AnnaBridge 157:e7ca05fa8600 195 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
AnnaBridge 157:e7ca05fa8600 196 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
AnnaBridge 157:e7ca05fa8600 197 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
AnnaBridge 157:e7ca05fa8600 198 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
AnnaBridge 157:e7ca05fa8600 199 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
AnnaBridge 157:e7ca05fa8600 200 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
AnnaBridge 157:e7ca05fa8600 201 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
AnnaBridge 157:e7ca05fa8600 202 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
AnnaBridge 157:e7ca05fa8600 203 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
AnnaBridge 157:e7ca05fa8600 204 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
AnnaBridge 157:e7ca05fa8600 205 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
AnnaBridge 157:e7ca05fa8600 206 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
AnnaBridge 157:e7ca05fa8600 207 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
AnnaBridge 157:e7ca05fa8600 208 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
AnnaBridge 157:e7ca05fa8600 209 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
AnnaBridge 157:e7ca05fa8600 210 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
AnnaBridge 157:e7ca05fa8600 211 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
AnnaBridge 157:e7ca05fa8600 212 /**
AnnaBridge 157:e7ca05fa8600 213 * @}
AnnaBridge 157:e7ca05fa8600 214 */
AnnaBridge 157:e7ca05fa8600 215
AnnaBridge 157:e7ca05fa8600 216 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
AnnaBridge 157:e7ca05fa8600 217 * @{
AnnaBridge 157:e7ca05fa8600 218 */
AnnaBridge 157:e7ca05fa8600 219 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
AnnaBridge 157:e7ca05fa8600 220 #define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
AnnaBridge 157:e7ca05fa8600 221 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
AnnaBridge 157:e7ca05fa8600 222 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
AnnaBridge 157:e7ca05fa8600 223 #define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
AnnaBridge 157:e7ca05fa8600 224 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
AnnaBridge 157:e7ca05fa8600 225 /**
AnnaBridge 157:e7ca05fa8600 226 * @}
AnnaBridge 157:e7ca05fa8600 227 */
AnnaBridge 157:e7ca05fa8600 228
AnnaBridge 157:e7ca05fa8600 229 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
AnnaBridge 157:e7ca05fa8600 230 * @{
AnnaBridge 157:e7ca05fa8600 231 */
AnnaBridge 157:e7ca05fa8600 232 #define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
AnnaBridge 157:e7ca05fa8600 233 #define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
AnnaBridge 157:e7ca05fa8600 234 #define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
AnnaBridge 157:e7ca05fa8600 235 #define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
AnnaBridge 157:e7ca05fa8600 236 #define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
AnnaBridge 157:e7ca05fa8600 237 #define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
AnnaBridge 157:e7ca05fa8600 238 #define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
AnnaBridge 157:e7ca05fa8600 239 #define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
AnnaBridge 157:e7ca05fa8600 240 /**
AnnaBridge 157:e7ca05fa8600 241 * @}
AnnaBridge 157:e7ca05fa8600 242 */
AnnaBridge 157:e7ca05fa8600 243 #endif /* __MPU_PRESENT */
AnnaBridge 157:e7ca05fa8600 244
AnnaBridge 157:e7ca05fa8600 245
AnnaBridge 157:e7ca05fa8600 246 /**
AnnaBridge 157:e7ca05fa8600 247 * @}
AnnaBridge 157:e7ca05fa8600 248 */
AnnaBridge 157:e7ca05fa8600 249
AnnaBridge 157:e7ca05fa8600 250 /* Exported functions --------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 251 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
AnnaBridge 157:e7ca05fa8600 252 * @{
AnnaBridge 157:e7ca05fa8600 253 */
AnnaBridge 157:e7ca05fa8600 254
AnnaBridge 157:e7ca05fa8600 255 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge 157:e7ca05fa8600 256 * @brief Initialization and Configuration functions
AnnaBridge 157:e7ca05fa8600 257 * @{
AnnaBridge 157:e7ca05fa8600 258 */
AnnaBridge 157:e7ca05fa8600 259 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
AnnaBridge 157:e7ca05fa8600 260 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
AnnaBridge 157:e7ca05fa8600 261 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
AnnaBridge 157:e7ca05fa8600 262 void HAL_NVIC_SystemReset(void);
AnnaBridge 157:e7ca05fa8600 263 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
AnnaBridge 157:e7ca05fa8600 264 #if (__MPU_PRESENT == 1)
AnnaBridge 157:e7ca05fa8600 265 /**
AnnaBridge 157:e7ca05fa8600 266 * @brief Disable the MPU.
AnnaBridge 157:e7ca05fa8600 267 * @retval None
AnnaBridge 157:e7ca05fa8600 268 */
AnnaBridge 157:e7ca05fa8600 269 __STATIC_INLINE void HAL_MPU_Disable(void)
AnnaBridge 157:e7ca05fa8600 270 {
AnnaBridge 157:e7ca05fa8600 271
AnnaBridge 157:e7ca05fa8600 272 /*Data Memory Barrier setup */
AnnaBridge 157:e7ca05fa8600 273 __DMB();
AnnaBridge 157:e7ca05fa8600 274 /* Disable the MPU */
AnnaBridge 157:e7ca05fa8600 275 MPU->CTRL = 0;
AnnaBridge 157:e7ca05fa8600 276 }
AnnaBridge 157:e7ca05fa8600 277
AnnaBridge 157:e7ca05fa8600 278 /**
AnnaBridge 157:e7ca05fa8600 279 * @brief Enable the MPU.
AnnaBridge 157:e7ca05fa8600 280 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
AnnaBridge 157:e7ca05fa8600 281 * NMI, FAULTMASK and privileged access to the default memory
AnnaBridge 157:e7ca05fa8600 282 * This parameter can be one of the following values:
AnnaBridge 157:e7ca05fa8600 283 * @arg MPU_HFNMI_PRIVDEF_NONE
AnnaBridge 157:e7ca05fa8600 284 * @arg MPU_HARDFAULT_NMI
AnnaBridge 157:e7ca05fa8600 285 * @arg MPU_PRIVILEGED_DEFAULT
AnnaBridge 157:e7ca05fa8600 286 * @arg MPU_HFNMI_PRIVDEF
AnnaBridge 157:e7ca05fa8600 287 * @retval None
AnnaBridge 157:e7ca05fa8600 288 */
AnnaBridge 157:e7ca05fa8600 289
AnnaBridge 157:e7ca05fa8600 290 __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
AnnaBridge 157:e7ca05fa8600 291 {
AnnaBridge 157:e7ca05fa8600 292 /* Enable the MPU */
AnnaBridge 157:e7ca05fa8600 293 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
AnnaBridge 157:e7ca05fa8600 294 /* Data Synchronization Barrier setup */
AnnaBridge 157:e7ca05fa8600 295 __DSB();
AnnaBridge 157:e7ca05fa8600 296 /* Instruction Synchronization Barrier setup */
AnnaBridge 157:e7ca05fa8600 297 __ISB();
AnnaBridge 157:e7ca05fa8600 298
AnnaBridge 157:e7ca05fa8600 299 }
AnnaBridge 157:e7ca05fa8600 300 #endif /* __MPU_PRESENT */
AnnaBridge 157:e7ca05fa8600 301 /**
AnnaBridge 157:e7ca05fa8600 302 * @}
AnnaBridge 157:e7ca05fa8600 303 */
AnnaBridge 157:e7ca05fa8600 304
AnnaBridge 157:e7ca05fa8600 305 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
AnnaBridge 157:e7ca05fa8600 306 * @brief Cortex control functions
AnnaBridge 157:e7ca05fa8600 307 * @{
AnnaBridge 157:e7ca05fa8600 308 */
AnnaBridge 157:e7ca05fa8600 309
AnnaBridge 157:e7ca05fa8600 310 uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn);
AnnaBridge 157:e7ca05fa8600 311 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
AnnaBridge 157:e7ca05fa8600 312 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
AnnaBridge 157:e7ca05fa8600 313 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
AnnaBridge 157:e7ca05fa8600 314 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
AnnaBridge 157:e7ca05fa8600 315 void HAL_SYSTICK_IRQHandler(void);
AnnaBridge 157:e7ca05fa8600 316 void HAL_SYSTICK_Callback(void);
AnnaBridge 157:e7ca05fa8600 317 #if (__MPU_PRESENT == 1)
AnnaBridge 157:e7ca05fa8600 318 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
AnnaBridge 157:e7ca05fa8600 319 #endif /* __MPU_PRESENT */
AnnaBridge 157:e7ca05fa8600 320 /**
AnnaBridge 157:e7ca05fa8600 321 * @}
AnnaBridge 157:e7ca05fa8600 322 */
AnnaBridge 157:e7ca05fa8600 323
AnnaBridge 157:e7ca05fa8600 324 /**
AnnaBridge 157:e7ca05fa8600 325 * @}
AnnaBridge 157:e7ca05fa8600 326 */
AnnaBridge 157:e7ca05fa8600 327
AnnaBridge 157:e7ca05fa8600 328 /* Private types -------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 329 /* Private variables ---------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 330 /* Private constants ---------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 331 /* Private macros ------------------------------------------------------------*/
AnnaBridge 157:e7ca05fa8600 332 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
AnnaBridge 157:e7ca05fa8600 333 * @{
AnnaBridge 157:e7ca05fa8600 334 */
AnnaBridge 157:e7ca05fa8600 335
AnnaBridge 157:e7ca05fa8600 336 #if (__MPU_PRESENT == 1)
AnnaBridge 157:e7ca05fa8600 337 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
AnnaBridge 157:e7ca05fa8600 338 ((STATE) == MPU_REGION_DISABLE))
AnnaBridge 157:e7ca05fa8600 339
AnnaBridge 157:e7ca05fa8600 340 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
AnnaBridge 157:e7ca05fa8600 341 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
AnnaBridge 157:e7ca05fa8600 342
AnnaBridge 157:e7ca05fa8600 343 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
AnnaBridge 157:e7ca05fa8600 344 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
AnnaBridge 157:e7ca05fa8600 345
AnnaBridge 157:e7ca05fa8600 346 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
AnnaBridge 157:e7ca05fa8600 347 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
AnnaBridge 157:e7ca05fa8600 348
AnnaBridge 157:e7ca05fa8600 349 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
AnnaBridge 157:e7ca05fa8600 350 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
AnnaBridge 157:e7ca05fa8600 351
AnnaBridge 157:e7ca05fa8600 352 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
AnnaBridge 157:e7ca05fa8600 353 ((TYPE) == MPU_REGION_PRIV_RW) || \
AnnaBridge 157:e7ca05fa8600 354 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
AnnaBridge 157:e7ca05fa8600 355 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
AnnaBridge 157:e7ca05fa8600 356 ((TYPE) == MPU_REGION_PRIV_RO) || \
AnnaBridge 157:e7ca05fa8600 357 ((TYPE) == MPU_REGION_PRIV_RO_URO))
AnnaBridge 157:e7ca05fa8600 358
AnnaBridge 157:e7ca05fa8600 359 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
AnnaBridge 157:e7ca05fa8600 360 ((NUMBER) == MPU_REGION_NUMBER1) || \
AnnaBridge 157:e7ca05fa8600 361 ((NUMBER) == MPU_REGION_NUMBER2) || \
AnnaBridge 157:e7ca05fa8600 362 ((NUMBER) == MPU_REGION_NUMBER3) || \
AnnaBridge 157:e7ca05fa8600 363 ((NUMBER) == MPU_REGION_NUMBER4) || \
AnnaBridge 157:e7ca05fa8600 364 ((NUMBER) == MPU_REGION_NUMBER5) || \
AnnaBridge 157:e7ca05fa8600 365 ((NUMBER) == MPU_REGION_NUMBER6) || \
AnnaBridge 157:e7ca05fa8600 366 ((NUMBER) == MPU_REGION_NUMBER7))
AnnaBridge 157:e7ca05fa8600 367
AnnaBridge 157:e7ca05fa8600 368 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \
AnnaBridge 157:e7ca05fa8600 369 ((SIZE) == MPU_REGION_SIZE_512B) || \
AnnaBridge 157:e7ca05fa8600 370 ((SIZE) == MPU_REGION_SIZE_1KB) || \
AnnaBridge 157:e7ca05fa8600 371 ((SIZE) == MPU_REGION_SIZE_2KB) || \
AnnaBridge 157:e7ca05fa8600 372 ((SIZE) == MPU_REGION_SIZE_4KB) || \
AnnaBridge 157:e7ca05fa8600 373 ((SIZE) == MPU_REGION_SIZE_8KB) || \
AnnaBridge 157:e7ca05fa8600 374 ((SIZE) == MPU_REGION_SIZE_16KB) || \
AnnaBridge 157:e7ca05fa8600 375 ((SIZE) == MPU_REGION_SIZE_32KB) || \
AnnaBridge 157:e7ca05fa8600 376 ((SIZE) == MPU_REGION_SIZE_64KB) || \
AnnaBridge 157:e7ca05fa8600 377 ((SIZE) == MPU_REGION_SIZE_128KB) || \
AnnaBridge 157:e7ca05fa8600 378 ((SIZE) == MPU_REGION_SIZE_256KB) || \
AnnaBridge 157:e7ca05fa8600 379 ((SIZE) == MPU_REGION_SIZE_512KB) || \
AnnaBridge 157:e7ca05fa8600 380 ((SIZE) == MPU_REGION_SIZE_1MB) || \
AnnaBridge 157:e7ca05fa8600 381 ((SIZE) == MPU_REGION_SIZE_2MB) || \
AnnaBridge 157:e7ca05fa8600 382 ((SIZE) == MPU_REGION_SIZE_4MB) || \
AnnaBridge 157:e7ca05fa8600 383 ((SIZE) == MPU_REGION_SIZE_8MB) || \
AnnaBridge 157:e7ca05fa8600 384 ((SIZE) == MPU_REGION_SIZE_16MB) || \
AnnaBridge 157:e7ca05fa8600 385 ((SIZE) == MPU_REGION_SIZE_32MB) || \
AnnaBridge 157:e7ca05fa8600 386 ((SIZE) == MPU_REGION_SIZE_64MB) || \
AnnaBridge 157:e7ca05fa8600 387 ((SIZE) == MPU_REGION_SIZE_128MB) || \
AnnaBridge 157:e7ca05fa8600 388 ((SIZE) == MPU_REGION_SIZE_256MB) || \
AnnaBridge 157:e7ca05fa8600 389 ((SIZE) == MPU_REGION_SIZE_512MB) || \
AnnaBridge 157:e7ca05fa8600 390 ((SIZE) == MPU_REGION_SIZE_1GB) || \
AnnaBridge 157:e7ca05fa8600 391 ((SIZE) == MPU_REGION_SIZE_2GB) || \
AnnaBridge 157:e7ca05fa8600 392 ((SIZE) == MPU_REGION_SIZE_4GB))
AnnaBridge 157:e7ca05fa8600 393
AnnaBridge 157:e7ca05fa8600 394 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
AnnaBridge 157:e7ca05fa8600 395 #endif /* __MPU_PRESENT */
AnnaBridge 157:e7ca05fa8600 396
AnnaBridge 157:e7ca05fa8600 397
AnnaBridge 157:e7ca05fa8600 398 /**
AnnaBridge 157:e7ca05fa8600 399 * @}
AnnaBridge 157:e7ca05fa8600 400 */
AnnaBridge 157:e7ca05fa8600 401
AnnaBridge 157:e7ca05fa8600 402 /**
AnnaBridge 157:e7ca05fa8600 403 * @}
AnnaBridge 157:e7ca05fa8600 404 */
AnnaBridge 157:e7ca05fa8600 405
AnnaBridge 157:e7ca05fa8600 406 /**
AnnaBridge 157:e7ca05fa8600 407 * @}
AnnaBridge 157:e7ca05fa8600 408 */
AnnaBridge 157:e7ca05fa8600 409
AnnaBridge 157:e7ca05fa8600 410 #ifdef __cplusplus
AnnaBridge 157:e7ca05fa8600 411 }
AnnaBridge 157:e7ca05fa8600 412 #endif
AnnaBridge 157:e7ca05fa8600 413
AnnaBridge 157:e7ca05fa8600 414 #endif /* __STM32L0xx_HAL_CORTEX_H */
AnnaBridge 157:e7ca05fa8600 415
AnnaBridge 157:e7ca05fa8600 416
AnnaBridge 157:e7ca05fa8600 417 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
AnnaBridge 157:e7ca05fa8600 418