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TARGET_DISCO_F303VC/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal.h@163:e59c8e839560, 2018-03-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Tue Mar 20 13:30:58 2018 +0000
- Revision:
- 163:e59c8e839560
- Child:
- 168:b9e159c1930a
mbed library. Release version 160
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 163:e59c8e839560 | 1 | /** |
| AnnaBridge | 163:e59c8e839560 | 2 | ****************************************************************************** |
| AnnaBridge | 163:e59c8e839560 | 3 | * @file stm32f3xx_hal.h |
| AnnaBridge | 163:e59c8e839560 | 4 | * @author MCD Application Team |
| AnnaBridge | 163:e59c8e839560 | 5 | * @version V1.4.0 |
| AnnaBridge | 163:e59c8e839560 | 6 | * @date 16-December-2016 |
| AnnaBridge | 163:e59c8e839560 | 7 | * @brief This file contains all the functions prototypes for the HAL |
| AnnaBridge | 163:e59c8e839560 | 8 | * module driver. |
| AnnaBridge | 163:e59c8e839560 | 9 | ****************************************************************************** |
| AnnaBridge | 163:e59c8e839560 | 10 | * @attention |
| AnnaBridge | 163:e59c8e839560 | 11 | * |
| AnnaBridge | 163:e59c8e839560 | 12 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 163:e59c8e839560 | 13 | * |
| AnnaBridge | 163:e59c8e839560 | 14 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 163:e59c8e839560 | 15 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 163:e59c8e839560 | 16 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 163:e59c8e839560 | 17 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 163:e59c8e839560 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 163:e59c8e839560 | 19 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 163:e59c8e839560 | 20 | * and/or other materials provided with the distribution. |
| AnnaBridge | 163:e59c8e839560 | 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 163:e59c8e839560 | 22 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 163:e59c8e839560 | 23 | * without specific prior written permission. |
| AnnaBridge | 163:e59c8e839560 | 24 | * |
| AnnaBridge | 163:e59c8e839560 | 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 163:e59c8e839560 | 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 163:e59c8e839560 | 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 163:e59c8e839560 | 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 163:e59c8e839560 | 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 163:e59c8e839560 | 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 163:e59c8e839560 | 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 163:e59c8e839560 | 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 163:e59c8e839560 | 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 163:e59c8e839560 | 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 163:e59c8e839560 | 35 | * |
| AnnaBridge | 163:e59c8e839560 | 36 | ****************************************************************************** |
| AnnaBridge | 163:e59c8e839560 | 37 | */ |
| AnnaBridge | 163:e59c8e839560 | 38 | |
| AnnaBridge | 163:e59c8e839560 | 39 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 40 | #ifndef __STM32F3xx_HAL_H |
| AnnaBridge | 163:e59c8e839560 | 41 | #define __STM32F3xx_HAL_H |
| AnnaBridge | 163:e59c8e839560 | 42 | |
| AnnaBridge | 163:e59c8e839560 | 43 | #ifdef __cplusplus |
| AnnaBridge | 163:e59c8e839560 | 44 | extern "C" { |
| AnnaBridge | 163:e59c8e839560 | 45 | #endif |
| AnnaBridge | 163:e59c8e839560 | 46 | |
| AnnaBridge | 163:e59c8e839560 | 47 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 48 | #include "stm32f3xx_hal_conf.h" |
| AnnaBridge | 163:e59c8e839560 | 49 | |
| AnnaBridge | 163:e59c8e839560 | 50 | /** @addtogroup STM32F3xx_HAL_Driver |
| AnnaBridge | 163:e59c8e839560 | 51 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 52 | */ |
| AnnaBridge | 163:e59c8e839560 | 53 | |
| AnnaBridge | 163:e59c8e839560 | 54 | /** @addtogroup HAL |
| AnnaBridge | 163:e59c8e839560 | 55 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 56 | */ |
| AnnaBridge | 163:e59c8e839560 | 57 | |
| AnnaBridge | 163:e59c8e839560 | 58 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 59 | /** @addtogroup HAL_Private_Macros |
| AnnaBridge | 163:e59c8e839560 | 60 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 61 | */ |
| AnnaBridge | 163:e59c8e839560 | 62 | #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ |
| AnnaBridge | 163:e59c8e839560 | 63 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ |
| AnnaBridge | 163:e59c8e839560 | 64 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ |
| AnnaBridge | 163:e59c8e839560 | 65 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) |
| AnnaBridge | 163:e59c8e839560 | 66 | /** |
| AnnaBridge | 163:e59c8e839560 | 67 | * @} |
| AnnaBridge | 163:e59c8e839560 | 68 | */ |
| AnnaBridge | 163:e59c8e839560 | 69 | |
| AnnaBridge | 163:e59c8e839560 | 70 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 71 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 72 | /** @defgroup HAL_Exported_Constants HAL Exported Constants |
| AnnaBridge | 163:e59c8e839560 | 73 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 74 | */ |
| AnnaBridge | 163:e59c8e839560 | 75 | /** @defgroup SYSCFG_BitAddress_AliasRegion SYSCFG registers bit address in the alias region |
| AnnaBridge | 163:e59c8e839560 | 76 | * @brief SYSCFG registers bit address in the alias region |
| AnnaBridge | 163:e59c8e839560 | 77 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 78 | */ |
| AnnaBridge | 163:e59c8e839560 | 79 | /* ------------ SYSCFG registers bit address in the alias region -------------*/ |
| AnnaBridge | 163:e59c8e839560 | 80 | #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) |
| AnnaBridge | 163:e59c8e839560 | 81 | /* --- CFGR2 Register ---*/ |
| AnnaBridge | 163:e59c8e839560 | 82 | /* Alias word address of BYP_ADDR_PAR bit */ |
| AnnaBridge | 163:e59c8e839560 | 83 | #define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18U) |
| AnnaBridge | 163:e59c8e839560 | 84 | #define BYPADDRPAR_BitNumber 0x04 |
| AnnaBridge | 163:e59c8e839560 | 85 | #define CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32U) + (BYPADDRPAR_BitNumber * 4U)) |
| AnnaBridge | 163:e59c8e839560 | 86 | /** |
| AnnaBridge | 163:e59c8e839560 | 87 | * @} |
| AnnaBridge | 163:e59c8e839560 | 88 | */ |
| AnnaBridge | 163:e59c8e839560 | 89 | |
| AnnaBridge | 163:e59c8e839560 | 90 | #if defined(SYSCFG_CFGR1_DMA_RMP) |
| AnnaBridge | 163:e59c8e839560 | 91 | /** @defgroup HAL_DMA_Remapping HAL DMA Remapping |
| AnnaBridge | 163:e59c8e839560 | 92 | * Elements values convention: 0xXXYYYYYY |
| AnnaBridge | 163:e59c8e839560 | 93 | * - YYYYYY : Position in the register |
| AnnaBridge | 163:e59c8e839560 | 94 | * - XX : Register index |
| AnnaBridge | 163:e59c8e839560 | 95 | * - 00: CFGR1 register in SYSCFG |
| AnnaBridge | 163:e59c8e839560 | 96 | * - 01: CFGR3 register in SYSCFG (not available on STM32F373xC/STM32F378xx devices) |
| AnnaBridge | 163:e59c8e839560 | 97 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 98 | */ |
| AnnaBridge | 163:e59c8e839560 | 99 | #define HAL_REMAPDMA_ADC24_DMA2_CH34 (0x00000100U) /*!< ADC24 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices) |
| AnnaBridge | 163:e59c8e839560 | 100 | 1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4U) */ |
| AnnaBridge | 163:e59c8e839560 | 101 | #define HAL_REMAPDMA_TIM16_DMA1_CH6 (0x00000800U) /*!< TIM16 DMA request remap |
| AnnaBridge | 163:e59c8e839560 | 102 | 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6U) */ |
| AnnaBridge | 163:e59c8e839560 | 103 | #define HAL_REMAPDMA_TIM17_DMA1_CH7 (0x00001000U) /*!< TIM17 DMA request remap |
| AnnaBridge | 163:e59c8e839560 | 104 | 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7U) */ |
| AnnaBridge | 163:e59c8e839560 | 105 | #define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 (0x00002000U) /*!< TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices) |
| AnnaBridge | 163:e59c8e839560 | 106 | 1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3U) */ |
| AnnaBridge | 163:e59c8e839560 | 107 | #define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 (0x00004000U) /*!< TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices) |
| AnnaBridge | 163:e59c8e839560 | 108 | 1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4U) */ |
| AnnaBridge | 163:e59c8e839560 | 109 | #define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6U/8 devices only) |
| AnnaBridge | 163:e59c8e839560 | 110 | 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5U) */ |
| AnnaBridge | 163:e59c8e839560 | 111 | #define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6U/8 devices only) |
| AnnaBridge | 163:e59c8e839560 | 112 | 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5U) */ |
| AnnaBridge | 163:e59c8e839560 | 113 | #if defined(SYSCFG_CFGR3_DMA_RMP) |
| AnnaBridge | 163:e59c8e839560 | 114 | #if !defined(HAL_REMAP_CFGR3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 115 | #define HAL_REMAP_CFGR3_MASK (0x01000000U) |
| AnnaBridge | 163:e59c8e839560 | 116 | #endif |
| AnnaBridge | 163:e59c8e839560 | 117 | |
| AnnaBridge | 163:e59c8e839560 | 118 | #define HAL_REMAPDMA_SPI1_RX_DMA1_CH2 (0x01000003U) /*!< SPI1_RX DMA remap (STM32F303x4/6U/8 devices only) |
| AnnaBridge | 163:e59c8e839560 | 119 | 11: Map on DMA1 channel 2U */ |
| AnnaBridge | 163:e59c8e839560 | 120 | #define HAL_REMAPDMA_SPI1_RX_DMA1_CH4 (0x01000001U) /*!< SPI1_RX DMA remap (STM32F303x4/6U/8 devices only) |
| AnnaBridge | 163:e59c8e839560 | 121 | 01: Map on DMA1 channel 4U */ |
| AnnaBridge | 163:e59c8e839560 | 122 | #define HAL_REMAPDMA_SPI1_RX_DMA1_CH6 (0x01000002U) /*!< SPI1_RX DMA remap (STM32F303x4/6U/8 devices only) |
| AnnaBridge | 163:e59c8e839560 | 123 | 10: Map on DMA1 channel 6U */ |
| AnnaBridge | 163:e59c8e839560 | 124 | #define HAL_REMAPDMA_SPI1_TX_DMA1_CH3 (0x0100000CU) /*!< SPI1_TX DMA remap (STM32F303x4/6U/8 devices only) |
| AnnaBridge | 163:e59c8e839560 | 125 | 11: Map on DMA1 channel 3U */ |
| AnnaBridge | 163:e59c8e839560 | 126 | #define HAL_REMAPDMA_SPI1_TX_DMA1_CH5 (0x01000004U) /*!< SPI1_TX DMA remap (STM32F303x4/6U/8 devices only) |
| AnnaBridge | 163:e59c8e839560 | 127 | 01: Map on DMA1 channel 5U */ |
| AnnaBridge | 163:e59c8e839560 | 128 | #define HAL_REMAPDMA_SPI1_TX_DMA1_CH7 (0x01000008U) /*!< SPI1_TX DMA remap (STM32F303x4/6U/8 devices only) |
| AnnaBridge | 163:e59c8e839560 | 129 | 10: Map on DMA1 channel 7U */ |
| AnnaBridge | 163:e59c8e839560 | 130 | #define HAL_REMAPDMA_I2C1_RX_DMA1_CH7 (0x01000030U) /*!< I2C1_RX DMA remap (STM32F303x4/6U/8 devices only) |
| AnnaBridge | 163:e59c8e839560 | 131 | 11: Map on DMA1 channel 7U */ |
| AnnaBridge | 163:e59c8e839560 | 132 | #define HAL_REMAPDMA_I2C1_RX_DMA1_CH3 (0x01000010U) /*!< I2C1_RX DMA remap (STM32F303x4/6U/8 devices only) |
| AnnaBridge | 163:e59c8e839560 | 133 | 01: Map on DMA1 channel 3U */ |
| AnnaBridge | 163:e59c8e839560 | 134 | #define HAL_REMAPDMA_I2C1_RX_DMA1_CH5 (0x01000020U) /*!< I2C1_RX DMA remap (STM32F303x4/6U/8 devices only) |
| AnnaBridge | 163:e59c8e839560 | 135 | 10: Map on DMA1 channel 5U */ |
| AnnaBridge | 163:e59c8e839560 | 136 | #define HAL_REMAPDMA_I2C1_TX_DMA1_CH6 (0x010000C0U) /*!< I2C1_TX DMA remap (STM32F303x4/6U/8 devices only) |
| AnnaBridge | 163:e59c8e839560 | 137 | 11: Map on DMA1 channel 6U */ |
| AnnaBridge | 163:e59c8e839560 | 138 | #define HAL_REMAPDMA_I2C1_TX_DMA1_CH2 (0x01000040U) /*!< I2C1_TX DMA remap (STM32F303x4/6U/8 devices only) |
| AnnaBridge | 163:e59c8e839560 | 139 | 01: Map on DMA1 channel 2U */ |
| AnnaBridge | 163:e59c8e839560 | 140 | #define HAL_REMAPDMA_I2C1_TX_DMA1_CH4 (0x01000080U) /*!< I2C1_TX DMA remap (STM32F303x4/6U/8 devices only) |
| AnnaBridge | 163:e59c8e839560 | 141 | 10: Map on DMA1 channel 4U */ |
| AnnaBridge | 163:e59c8e839560 | 142 | #define HAL_REMAPDMA_ADC2_DMA1_CH2 (0x01000100U) /*!< ADC2 DMA remap |
| AnnaBridge | 163:e59c8e839560 | 143 | x0: No remap (ADC2 on DMA2) |
| AnnaBridge | 163:e59c8e839560 | 144 | 10: Map on DMA1 channel 2U */ |
| AnnaBridge | 163:e59c8e839560 | 145 | #define HAL_REMAPDMA_ADC2_DMA1_CH4 (0x01000300U) /*!< ADC2 DMA remap |
| AnnaBridge | 163:e59c8e839560 | 146 | 11: Map on DMA1 channel 4U */ |
| AnnaBridge | 163:e59c8e839560 | 147 | #endif /* SYSCFG_CFGR3_DMA_RMP */ |
| AnnaBridge | 163:e59c8e839560 | 148 | |
| AnnaBridge | 163:e59c8e839560 | 149 | #if defined(SYSCFG_CFGR3_DMA_RMP) |
| AnnaBridge | 163:e59c8e839560 | 150 | #define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \ |
| AnnaBridge | 163:e59c8e839560 | 151 | (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \ |
| AnnaBridge | 163:e59c8e839560 | 152 | (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \ |
| AnnaBridge | 163:e59c8e839560 | 153 | (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \ |
| AnnaBridge | 163:e59c8e839560 | 154 | (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \ |
| AnnaBridge | 163:e59c8e839560 | 155 | (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \ |
| AnnaBridge | 163:e59c8e839560 | 156 | (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) || \ |
| AnnaBridge | 163:e59c8e839560 | 157 | (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH2) == HAL_REMAPDMA_SPI1_RX_DMA1_CH2) || \ |
| AnnaBridge | 163:e59c8e839560 | 158 | (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH4) == HAL_REMAPDMA_SPI1_RX_DMA1_CH4) || \ |
| AnnaBridge | 163:e59c8e839560 | 159 | (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH6) == HAL_REMAPDMA_SPI1_RX_DMA1_CH6) || \ |
| AnnaBridge | 163:e59c8e839560 | 160 | (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH3) == HAL_REMAPDMA_SPI1_TX_DMA1_CH3) || \ |
| AnnaBridge | 163:e59c8e839560 | 161 | (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH5) == HAL_REMAPDMA_SPI1_TX_DMA1_CH5) || \ |
| AnnaBridge | 163:e59c8e839560 | 162 | (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH7) == HAL_REMAPDMA_SPI1_TX_DMA1_CH7) || \ |
| AnnaBridge | 163:e59c8e839560 | 163 | (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH7) == HAL_REMAPDMA_I2C1_RX_DMA1_CH7) || \ |
| AnnaBridge | 163:e59c8e839560 | 164 | (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH3) == HAL_REMAPDMA_I2C1_RX_DMA1_CH3) || \ |
| AnnaBridge | 163:e59c8e839560 | 165 | (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH5) == HAL_REMAPDMA_I2C1_RX_DMA1_CH5) || \ |
| AnnaBridge | 163:e59c8e839560 | 166 | (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH6) == HAL_REMAPDMA_I2C1_TX_DMA1_CH6) || \ |
| AnnaBridge | 163:e59c8e839560 | 167 | (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH2) == HAL_REMAPDMA_I2C1_TX_DMA1_CH2) || \ |
| AnnaBridge | 163:e59c8e839560 | 168 | (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH4) == HAL_REMAPDMA_I2C1_TX_DMA1_CH4) || \ |
| AnnaBridge | 163:e59c8e839560 | 169 | (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH2) == HAL_REMAPDMA_ADC2_DMA1_CH2) || \ |
| AnnaBridge | 163:e59c8e839560 | 170 | (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH4) == HAL_REMAPDMA_ADC2_DMA1_CH4)) |
| AnnaBridge | 163:e59c8e839560 | 171 | #else |
| AnnaBridge | 163:e59c8e839560 | 172 | #define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \ |
| AnnaBridge | 163:e59c8e839560 | 173 | (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \ |
| AnnaBridge | 163:e59c8e839560 | 174 | (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \ |
| AnnaBridge | 163:e59c8e839560 | 175 | (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \ |
| AnnaBridge | 163:e59c8e839560 | 176 | (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \ |
| AnnaBridge | 163:e59c8e839560 | 177 | (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \ |
| AnnaBridge | 163:e59c8e839560 | 178 | (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5)) |
| AnnaBridge | 163:e59c8e839560 | 179 | #endif /* SYSCFG_CFGR3_DMA_RMP && SYSCFG_CFGR1_DMA_RMP*/ |
| AnnaBridge | 163:e59c8e839560 | 180 | /** |
| AnnaBridge | 163:e59c8e839560 | 181 | * @} |
| AnnaBridge | 163:e59c8e839560 | 182 | */ |
| AnnaBridge | 163:e59c8e839560 | 183 | #endif /* SYSCFG_CFGR1_DMA_RMP */ |
| AnnaBridge | 163:e59c8e839560 | 184 | |
| AnnaBridge | 163:e59c8e839560 | 185 | /** @defgroup HAL_Trigger_Remapping HAL Trigger Remapping |
| AnnaBridge | 163:e59c8e839560 | 186 | * Elements values convention: 0xXXYYYYYY |
| AnnaBridge | 163:e59c8e839560 | 187 | * - YYYYYY : Position in the register |
| AnnaBridge | 163:e59c8e839560 | 188 | * - XX : Register index |
| AnnaBridge | 163:e59c8e839560 | 189 | * - 00: CFGR1 register in SYSCFG |
| AnnaBridge | 163:e59c8e839560 | 190 | * - 01: CFGR3 register in SYSCFG |
| AnnaBridge | 163:e59c8e839560 | 191 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 192 | */ |
| AnnaBridge | 163:e59c8e839560 | 193 | #define HAL_REMAPTRIGGER_DAC1_TRIG (0x00000080U) /*!< DAC trigger remap (when TSEL = 001 on STM32F303xB/C and STM32F358xx devices) |
| AnnaBridge | 163:e59c8e839560 | 194 | 0: No remap (DAC trigger is TIM8_TRGO) |
| AnnaBridge | 163:e59c8e839560 | 195 | 1: Remap (DAC trigger is TIM3_TRGO) */ |
| AnnaBridge | 163:e59c8e839560 | 196 | #define HAL_REMAPTRIGGER_TIM1_ITR3 (0x00000040U) /*!< TIM1 ITR3 trigger remap |
| AnnaBridge | 163:e59c8e839560 | 197 | 0: No remap |
| AnnaBridge | 163:e59c8e839560 | 198 | 1: Remap (TIM1_TRG3 = TIM17_OC) */ |
| AnnaBridge | 163:e59c8e839560 | 199 | #if defined(SYSCFG_CFGR3_TRIGGER_RMP) |
| AnnaBridge | 163:e59c8e839560 | 200 | #if !defined(HAL_REMAP_CFGR3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 201 | #define HAL_REMAP_CFGR3_MASK (0x01000000U) |
| AnnaBridge | 163:e59c8e839560 | 202 | #endif |
| AnnaBridge | 163:e59c8e839560 | 203 | #define HAL_REMAPTRIGGER_DAC1_TRIG3 (0x01010000U) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap |
| AnnaBridge | 163:e59c8e839560 | 204 | 0: Remap (DAC trigger is TIM15_TRGO) |
| AnnaBridge | 163:e59c8e839560 | 205 | 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG1) */ |
| AnnaBridge | 163:e59c8e839560 | 206 | #define HAL_REMAPTRIGGER_DAC1_TRIG5 (0x01020000U) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap |
| AnnaBridge | 163:e59c8e839560 | 207 | 0: No remap |
| AnnaBridge | 163:e59c8e839560 | 208 | 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG2) */ |
| AnnaBridge | 163:e59c8e839560 | 209 | #define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \ |
| AnnaBridge | 163:e59c8e839560 | 210 | (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3) || \ |
| AnnaBridge | 163:e59c8e839560 | 211 | (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG3) == HAL_REMAPTRIGGER_DAC1_TRIG3) || \ |
| AnnaBridge | 163:e59c8e839560 | 212 | (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG5) == HAL_REMAPTRIGGER_DAC1_TRIG5)) |
| AnnaBridge | 163:e59c8e839560 | 213 | #else |
| AnnaBridge | 163:e59c8e839560 | 214 | #define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \ |
| AnnaBridge | 163:e59c8e839560 | 215 | (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3)) |
| AnnaBridge | 163:e59c8e839560 | 216 | #endif /* SYSCFG_CFGR3_TRIGGER_RMP */ |
| AnnaBridge | 163:e59c8e839560 | 217 | /** |
| AnnaBridge | 163:e59c8e839560 | 218 | * @} |
| AnnaBridge | 163:e59c8e839560 | 219 | */ |
| AnnaBridge | 163:e59c8e839560 | 220 | |
| AnnaBridge | 163:e59c8e839560 | 221 | #if defined (STM32F302xE) |
| AnnaBridge | 163:e59c8e839560 | 222 | /** @defgroup HAL_ADC_Trigger_Remapping HAL ADC Trigger Remapping |
| AnnaBridge | 163:e59c8e839560 | 223 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 224 | */ |
| AnnaBridge | 163:e59c8e839560 | 225 | #define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2 |
| AnnaBridge | 163:e59c8e839560 | 226 | 0: No remap (TIM1_CC3) |
| AnnaBridge | 163:e59c8e839560 | 227 | 1: Remap (TIM20_TRGO) */ |
| AnnaBridge | 163:e59c8e839560 | 228 | #define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3 |
| AnnaBridge | 163:e59c8e839560 | 229 | 0: No remap (TIM2_CC2) |
| AnnaBridge | 163:e59c8e839560 | 230 | 1: Remap (TIM20_TRGO2) */ |
| AnnaBridge | 163:e59c8e839560 | 231 | #define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5 |
| AnnaBridge | 163:e59c8e839560 | 232 | 0: No remap (TIM4_CC4) |
| AnnaBridge | 163:e59c8e839560 | 233 | 1: Remap (TIM20_CC1) */ |
| AnnaBridge | 163:e59c8e839560 | 234 | #define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13 |
| AnnaBridge | 163:e59c8e839560 | 235 | 0: No remap (TIM6_TRGO) |
| AnnaBridge | 163:e59c8e839560 | 236 | 1: Remap (TIM20_CC2) */ |
| AnnaBridge | 163:e59c8e839560 | 237 | #define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15 |
| AnnaBridge | 163:e59c8e839560 | 238 | 0: No remap (TIM3_CC4) |
| AnnaBridge | 163:e59c8e839560 | 239 | 1: Remap (TIM20_CC3) */ |
| AnnaBridge | 163:e59c8e839560 | 240 | #define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3 |
| AnnaBridge | 163:e59c8e839560 | 241 | 0: No remap (TIM2_CC1) |
| AnnaBridge | 163:e59c8e839560 | 242 | 1: Remap (TIM20_TRGO) */ |
| AnnaBridge | 163:e59c8e839560 | 243 | #define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6 |
| AnnaBridge | 163:e59c8e839560 | 244 | 0: No remap (EXTI line 15U) |
| AnnaBridge | 163:e59c8e839560 | 245 | 1: Remap (TIM20_TRGO2) */ |
| AnnaBridge | 163:e59c8e839560 | 246 | #define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13 |
| AnnaBridge | 163:e59c8e839560 | 247 | 0: No remap (TIM3_CC1) |
| AnnaBridge | 163:e59c8e839560 | 248 | 1: Remap (TIM20_CC4) */ |
| AnnaBridge | 163:e59c8e839560 | 249 | |
| AnnaBridge | 163:e59c8e839560 | 250 | #define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \ |
| AnnaBridge | 163:e59c8e839560 | 251 | (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \ |
| AnnaBridge | 163:e59c8e839560 | 252 | (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \ |
| AnnaBridge | 163:e59c8e839560 | 253 | (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13U) == HAL_REMAPADCTRIGGER_ADC12_EXT13U) || \ |
| AnnaBridge | 163:e59c8e839560 | 254 | (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15U) == HAL_REMAPADCTRIGGER_ADC12_EXT15U) || \ |
| AnnaBridge | 163:e59c8e839560 | 255 | (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \ |
| AnnaBridge | 163:e59c8e839560 | 256 | (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \ |
| AnnaBridge | 163:e59c8e839560 | 257 | (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13U) == HAL_REMAPADCTRIGGER_ADC12_JEXT13U)) |
| AnnaBridge | 163:e59c8e839560 | 258 | /** |
| AnnaBridge | 163:e59c8e839560 | 259 | * @} |
| AnnaBridge | 163:e59c8e839560 | 260 | */ |
| AnnaBridge | 163:e59c8e839560 | 261 | #endif /* STM32F302xE */ |
| AnnaBridge | 163:e59c8e839560 | 262 | |
| AnnaBridge | 163:e59c8e839560 | 263 | #if defined (STM32F303xE) || defined (STM32F398xx) |
| AnnaBridge | 163:e59c8e839560 | 264 | /** @defgroup HAL_ADC_Trigger_Remapping HAL ADC Trigger Remapping |
| AnnaBridge | 163:e59c8e839560 | 265 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 266 | */ |
| AnnaBridge | 163:e59c8e839560 | 267 | #define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2 |
| AnnaBridge | 163:e59c8e839560 | 268 | 0: No remap (TIM1_CC3) |
| AnnaBridge | 163:e59c8e839560 | 269 | 1: Remap (TIM20_TRGO) */ |
| AnnaBridge | 163:e59c8e839560 | 270 | #define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3 |
| AnnaBridge | 163:e59c8e839560 | 271 | 0: No remap (TIM2_CC2) |
| AnnaBridge | 163:e59c8e839560 | 272 | 1: Remap (TIM20_TRGO2) */ |
| AnnaBridge | 163:e59c8e839560 | 273 | #define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5 |
| AnnaBridge | 163:e59c8e839560 | 274 | 0: No remap (TIM4_CC4) |
| AnnaBridge | 163:e59c8e839560 | 275 | 1: Remap (TIM20_CC1) */ |
| AnnaBridge | 163:e59c8e839560 | 276 | #define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13 |
| AnnaBridge | 163:e59c8e839560 | 277 | 0: No remap (TIM6_TRGO) |
| AnnaBridge | 163:e59c8e839560 | 278 | 1: Remap (TIM20_CC2) */ |
| AnnaBridge | 163:e59c8e839560 | 279 | #define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15 |
| AnnaBridge | 163:e59c8e839560 | 280 | 0: No remap (TIM3_CC4) |
| AnnaBridge | 163:e59c8e839560 | 281 | 1: Remap (TIM20_CC3) */ |
| AnnaBridge | 163:e59c8e839560 | 282 | #define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3 |
| AnnaBridge | 163:e59c8e839560 | 283 | 0: No remap (TIM2_CC1) |
| AnnaBridge | 163:e59c8e839560 | 284 | 1: Remap (TIM20_TRGO) */ |
| AnnaBridge | 163:e59c8e839560 | 285 | #define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6 |
| AnnaBridge | 163:e59c8e839560 | 286 | 0: No remap (EXTI line 15U) |
| AnnaBridge | 163:e59c8e839560 | 287 | 1: Remap (TIM20_TRGO2) */ |
| AnnaBridge | 163:e59c8e839560 | 288 | #define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13 |
| AnnaBridge | 163:e59c8e839560 | 289 | 0: No remap (TIM3_CC1) |
| AnnaBridge | 163:e59c8e839560 | 290 | 1: Remap (TIM20_CC4) */ |
| AnnaBridge | 163:e59c8e839560 | 291 | #define HAL_REMAPADCTRIGGER_ADC34_EXT5 SYSCFG_CFGR4_ADC34_EXT5_RMP /*!< Input trigger of ADC34 regular channel EXT5 |
| AnnaBridge | 163:e59c8e839560 | 292 | 0: No remap (EXTI line 2U) |
| AnnaBridge | 163:e59c8e839560 | 293 | 1: Remap (TIM20_TRGO) */ |
| AnnaBridge | 163:e59c8e839560 | 294 | #define HAL_REMAPADCTRIGGER_ADC34_EXT6 SYSCFG_CFGR4_ADC34_EXT6_RMP /*!< Input trigger of ADC34 regular channel EXT6 |
| AnnaBridge | 163:e59c8e839560 | 295 | 0: No remap (TIM4_CC1) |
| AnnaBridge | 163:e59c8e839560 | 296 | 1: Remap (TIM20_TRGO2) */ |
| AnnaBridge | 163:e59c8e839560 | 297 | #define HAL_REMAPADCTRIGGER_ADC34_EXT15 SYSCFG_CFGR4_ADC34_EXT15_RMP /*!< Input trigger of ADC34 regular channel EXT15 |
| AnnaBridge | 163:e59c8e839560 | 298 | 0: No remap (TIM2_CC1) |
| AnnaBridge | 163:e59c8e839560 | 299 | 1: Remap (TIM20_CC1) */ |
| AnnaBridge | 163:e59c8e839560 | 300 | #define HAL_REMAPADCTRIGGER_ADC34_JEXT5 SYSCFG_CFGR4_ADC34_JEXT5_RMP /*!< Input trigger of ADC34 injected channel JEXT5 |
| AnnaBridge | 163:e59c8e839560 | 301 | 0: No remap (TIM4_CC3) |
| AnnaBridge | 163:e59c8e839560 | 302 | 1: Remap (TIM20_TRGO) */ |
| AnnaBridge | 163:e59c8e839560 | 303 | #define HAL_REMAPADCTRIGGER_ADC34_JEXT11 SYSCFG_CFGR4_ADC34_JEXT11_RMP /*!< Input trigger of ADC34 injected channel JEXT11 |
| AnnaBridge | 163:e59c8e839560 | 304 | 0: No remap (TIM1_CC3) |
| AnnaBridge | 163:e59c8e839560 | 305 | 1: Remap (TIM20_TRGO2) */ |
| AnnaBridge | 163:e59c8e839560 | 306 | #define HAL_REMAPADCTRIGGER_ADC34_JEXT14 SYSCFG_CFGR4_ADC34_JEXT14_RMP /*!< Input trigger of ADC34 injected channel JEXT14 |
| AnnaBridge | 163:e59c8e839560 | 307 | 0: No remap (TIM7_TRGO) |
| AnnaBridge | 163:e59c8e839560 | 308 | 1: Remap (TIM20_CC2) */ |
| AnnaBridge | 163:e59c8e839560 | 309 | |
| AnnaBridge | 163:e59c8e839560 | 310 | #define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \ |
| AnnaBridge | 163:e59c8e839560 | 311 | (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \ |
| AnnaBridge | 163:e59c8e839560 | 312 | (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \ |
| AnnaBridge | 163:e59c8e839560 | 313 | (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13U) == HAL_REMAPADCTRIGGER_ADC12_EXT13U) || \ |
| AnnaBridge | 163:e59c8e839560 | 314 | (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15U) == HAL_REMAPADCTRIGGER_ADC12_EXT15U) || \ |
| AnnaBridge | 163:e59c8e839560 | 315 | (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \ |
| AnnaBridge | 163:e59c8e839560 | 316 | (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \ |
| AnnaBridge | 163:e59c8e839560 | 317 | (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13U) == HAL_REMAPADCTRIGGER_ADC12_JEXT13U) || \ |
| AnnaBridge | 163:e59c8e839560 | 318 | (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT5) == HAL_REMAPADCTRIGGER_ADC34_EXT5) || \ |
| AnnaBridge | 163:e59c8e839560 | 319 | (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT6) == HAL_REMAPADCTRIGGER_ADC34_EXT6) || \ |
| AnnaBridge | 163:e59c8e839560 | 320 | (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT15U) == HAL_REMAPADCTRIGGER_ADC34_EXT15U) || \ |
| AnnaBridge | 163:e59c8e839560 | 321 | (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT5) == HAL_REMAPADCTRIGGER_ADC34_JEXT5) || \ |
| AnnaBridge | 163:e59c8e839560 | 322 | (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT11U) == HAL_REMAPADCTRIGGER_ADC34_JEXT11U) || \ |
| AnnaBridge | 163:e59c8e839560 | 323 | (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT14U) == HAL_REMAPADCTRIGGER_ADC34_JEXT14U)) |
| AnnaBridge | 163:e59c8e839560 | 324 | /** |
| AnnaBridge | 163:e59c8e839560 | 325 | * @} |
| AnnaBridge | 163:e59c8e839560 | 326 | */ |
| AnnaBridge | 163:e59c8e839560 | 327 | #endif /* STM32F303xE || STM32F398xx */ |
| AnnaBridge | 163:e59c8e839560 | 328 | |
| AnnaBridge | 163:e59c8e839560 | 329 | /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO |
| AnnaBridge | 163:e59c8e839560 | 330 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 331 | */ |
| AnnaBridge | 163:e59c8e839560 | 332 | |
| AnnaBridge | 163:e59c8e839560 | 333 | /** @brief Fast-mode Plus driving capability on a specific GPIO |
| AnnaBridge | 163:e59c8e839560 | 334 | */ |
| AnnaBridge | 163:e59c8e839560 | 335 | #if defined(SYSCFG_CFGR1_I2C_PB6_FMP) |
| AnnaBridge | 163:e59c8e839560 | 336 | #define SYSCFG_FASTMODEPLUS_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP) /*!< Enable Fast-mode Plus on PB6 */ |
| AnnaBridge | 163:e59c8e839560 | 337 | #endif /* SYSCFG_CFGR1_I2C_PB6_FMP */ |
| AnnaBridge | 163:e59c8e839560 | 338 | |
| AnnaBridge | 163:e59c8e839560 | 339 | #if defined(SYSCFG_CFGR1_I2C_PB7_FMP) |
| AnnaBridge | 163:e59c8e839560 | 340 | #define SYSCFG_FASTMODEPLUS_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP) /*!< Enable Fast-mode Plus on PB7 */ |
| AnnaBridge | 163:e59c8e839560 | 341 | #endif /* SYSCFG_CFGR1_I2C_PB7_FMP */ |
| AnnaBridge | 163:e59c8e839560 | 342 | |
| AnnaBridge | 163:e59c8e839560 | 343 | #if defined(SYSCFG_CFGR1_I2C_PB8_FMP) |
| AnnaBridge | 163:e59c8e839560 | 344 | #define SYSCFG_FASTMODEPLUS_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP) /*!< Enable Fast-mode Plus on PB8 */ |
| AnnaBridge | 163:e59c8e839560 | 345 | #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */ |
| AnnaBridge | 163:e59c8e839560 | 346 | |
| AnnaBridge | 163:e59c8e839560 | 347 | #if defined(SYSCFG_CFGR1_I2C_PB9_FMP) |
| AnnaBridge | 163:e59c8e839560 | 348 | #define SYSCFG_FASTMODEPLUS_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP) /*!< Enable Fast-mode Plus on PB9 */ |
| AnnaBridge | 163:e59c8e839560 | 349 | #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */ |
| AnnaBridge | 163:e59c8e839560 | 350 | /** |
| AnnaBridge | 163:e59c8e839560 | 351 | * @} |
| AnnaBridge | 163:e59c8e839560 | 352 | */ |
| AnnaBridge | 163:e59c8e839560 | 353 | |
| AnnaBridge | 163:e59c8e839560 | 354 | #if defined(SYSCFG_RCR_PAGE0) |
| AnnaBridge | 163:e59c8e839560 | 355 | /* CCM-SRAM defined */ |
| AnnaBridge | 163:e59c8e839560 | 356 | /** @defgroup HAL_Page_Write_Protection HAL CCM RAM page write protection |
| AnnaBridge | 163:e59c8e839560 | 357 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 358 | */ |
| AnnaBridge | 163:e59c8e839560 | 359 | #define HAL_SYSCFG_WP_PAGE0 (SYSCFG_RCR_PAGE0) /*!< ICODE SRAM Write protection page 0U */ |
| AnnaBridge | 163:e59c8e839560 | 360 | #define HAL_SYSCFG_WP_PAGE1 (SYSCFG_RCR_PAGE1) /*!< ICODE SRAM Write protection page 1U */ |
| AnnaBridge | 163:e59c8e839560 | 361 | #define HAL_SYSCFG_WP_PAGE2 (SYSCFG_RCR_PAGE2) /*!< ICODE SRAM Write protection page 2U */ |
| AnnaBridge | 163:e59c8e839560 | 362 | #define HAL_SYSCFG_WP_PAGE3 (SYSCFG_RCR_PAGE3) /*!< ICODE SRAM Write protection page 3U */ |
| AnnaBridge | 163:e59c8e839560 | 363 | #if defined(SYSCFG_RCR_PAGE4) |
| AnnaBridge | 163:e59c8e839560 | 364 | /* More than 4KB CCM-SRAM defined */ |
| AnnaBridge | 163:e59c8e839560 | 365 | #define HAL_SYSCFG_WP_PAGE4 (SYSCFG_RCR_PAGE4) /*!< ICODE SRAM Write protection page 4U */ |
| AnnaBridge | 163:e59c8e839560 | 366 | #define HAL_SYSCFG_WP_PAGE5 (SYSCFG_RCR_PAGE5) /*!< ICODE SRAM Write protection page 5U */ |
| AnnaBridge | 163:e59c8e839560 | 367 | #define HAL_SYSCFG_WP_PAGE6 (SYSCFG_RCR_PAGE6) /*!< ICODE SRAM Write protection page 6U */ |
| AnnaBridge | 163:e59c8e839560 | 368 | #define HAL_SYSCFG_WP_PAGE7 (SYSCFG_RCR_PAGE7) /*!< ICODE SRAM Write protection page 7U */ |
| AnnaBridge | 163:e59c8e839560 | 369 | #endif /* SYSCFG_RCR_PAGE4 */ |
| AnnaBridge | 163:e59c8e839560 | 370 | #if defined(SYSCFG_RCR_PAGE8) |
| AnnaBridge | 163:e59c8e839560 | 371 | #define HAL_SYSCFG_WP_PAGE8 (SYSCFG_RCR_PAGE8) /*!< ICODE SRAM Write protection page 8U */ |
| AnnaBridge | 163:e59c8e839560 | 372 | #define HAL_SYSCFG_WP_PAGE9 (SYSCFG_RCR_PAGE9) /*!< ICODE SRAM Write protection page 9U */ |
| AnnaBridge | 163:e59c8e839560 | 373 | #define HAL_SYSCFG_WP_PAGE10 (SYSCFG_RCR_PAGE10U) /*!< ICODE SRAM Write protection page 10U */ |
| AnnaBridge | 163:e59c8e839560 | 374 | #define HAL_SYSCFG_WP_PAGE11 (SYSCFG_RCR_PAGE11U) /*!< ICODE SRAM Write protection page 11U */ |
| AnnaBridge | 163:e59c8e839560 | 375 | #define HAL_SYSCFG_WP_PAGE12 (SYSCFG_RCR_PAGE12U) /*!< ICODE SRAM Write protection page 12U */ |
| AnnaBridge | 163:e59c8e839560 | 376 | #define HAL_SYSCFG_WP_PAGE13 (SYSCFG_RCR_PAGE13U) /*!< ICODE SRAM Write protection page 13U */ |
| AnnaBridge | 163:e59c8e839560 | 377 | #define HAL_SYSCFG_WP_PAGE14 (SYSCFG_RCR_PAGE14U) /*!< ICODE SRAM Write protection page 14U */ |
| AnnaBridge | 163:e59c8e839560 | 378 | #define HAL_SYSCFG_WP_PAGE15 (SYSCFG_RCR_PAGE15U) /*!< ICODE SRAM Write protection page 15U */ |
| AnnaBridge | 163:e59c8e839560 | 379 | #endif /* SYSCFG_RCR_PAGE8 */ |
| AnnaBridge | 163:e59c8e839560 | 380 | |
| AnnaBridge | 163:e59c8e839560 | 381 | #if defined(SYSCFG_RCR_PAGE8) |
| AnnaBridge | 163:e59c8e839560 | 382 | #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFU)) |
| AnnaBridge | 163:e59c8e839560 | 383 | #elif defined(SYSCFG_RCR_PAGE4) |
| AnnaBridge | 163:e59c8e839560 | 384 | #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x00FFU)) |
| AnnaBridge | 163:e59c8e839560 | 385 | #else |
| AnnaBridge | 163:e59c8e839560 | 386 | #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000FU)) |
| AnnaBridge | 163:e59c8e839560 | 387 | #endif /* SYSCFG_RCR_PAGE8 */ |
| AnnaBridge | 163:e59c8e839560 | 388 | /** |
| AnnaBridge | 163:e59c8e839560 | 389 | * @} |
| AnnaBridge | 163:e59c8e839560 | 390 | */ |
| AnnaBridge | 163:e59c8e839560 | 391 | #endif /* SYSCFG_RCR_PAGE0 */ |
| AnnaBridge | 163:e59c8e839560 | 392 | |
| AnnaBridge | 163:e59c8e839560 | 393 | /** @defgroup HAL_SYSCFG_Interrupts HAL SYSCFG Interrupts |
| AnnaBridge | 163:e59c8e839560 | 394 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 395 | */ |
| AnnaBridge | 163:e59c8e839560 | 396 | #define HAL_SYSCFG_IT_FPU_IOC (SYSCFG_CFGR1_FPU_IE_0) /*!< Floating Point Unit Invalid operation Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 397 | #define HAL_SYSCFG_IT_FPU_DZC (SYSCFG_CFGR1_FPU_IE_1) /*!< Floating Point Unit Divide-by-zero Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 398 | #define HAL_SYSCFG_IT_FPU_UFC (SYSCFG_CFGR1_FPU_IE_2) /*!< Floating Point Unit Underflow Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 399 | #define HAL_SYSCFG_IT_FPU_OFC (SYSCFG_CFGR1_FPU_IE_3) /*!< Floating Point Unit Overflow Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 400 | #define HAL_SYSCFG_IT_FPU_IDC (SYSCFG_CFGR1_FPU_IE_4) /*!< Floating Point Unit Input denormal Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 401 | #define HAL_SYSCFG_IT_FPU_IXC (SYSCFG_CFGR1_FPU_IE_5) /*!< Floating Point Unit Inexact Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 402 | |
| AnnaBridge | 163:e59c8e839560 | 403 | #define IS_HAL_SYSCFG_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_0) == SYSCFG_CFGR1_FPU_IE_0) || \ |
| AnnaBridge | 163:e59c8e839560 | 404 | (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_1) == SYSCFG_CFGR1_FPU_IE_1) || \ |
| AnnaBridge | 163:e59c8e839560 | 405 | (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_2) == SYSCFG_CFGR1_FPU_IE_2) || \ |
| AnnaBridge | 163:e59c8e839560 | 406 | (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_3) == SYSCFG_CFGR1_FPU_IE_3) || \ |
| AnnaBridge | 163:e59c8e839560 | 407 | (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_4) == SYSCFG_CFGR1_FPU_IE_4) || \ |
| AnnaBridge | 163:e59c8e839560 | 408 | (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_5) == SYSCFG_CFGR1_FPU_IE_5)) |
| AnnaBridge | 163:e59c8e839560 | 409 | |
| AnnaBridge | 163:e59c8e839560 | 410 | /** |
| AnnaBridge | 163:e59c8e839560 | 411 | * @} |
| AnnaBridge | 163:e59c8e839560 | 412 | */ |
| AnnaBridge | 163:e59c8e839560 | 413 | |
| AnnaBridge | 163:e59c8e839560 | 414 | /** |
| AnnaBridge | 163:e59c8e839560 | 415 | * @} |
| AnnaBridge | 163:e59c8e839560 | 416 | */ |
| AnnaBridge | 163:e59c8e839560 | 417 | |
| AnnaBridge | 163:e59c8e839560 | 418 | /* Exported macros -----------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 419 | /** @defgroup HAL_Exported_Macros HAL Exported Macros |
| AnnaBridge | 163:e59c8e839560 | 420 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 421 | */ |
| AnnaBridge | 163:e59c8e839560 | 422 | |
| AnnaBridge | 163:e59c8e839560 | 423 | /** @defgroup Debug_MCU_APB1_Freeze Freeze/Unfreeze APB1 Peripherals in Debug mode |
| AnnaBridge | 163:e59c8e839560 | 424 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 425 | */ |
| AnnaBridge | 163:e59c8e839560 | 426 | #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) |
| AnnaBridge | 163:e59c8e839560 | 427 | #define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 428 | #define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 429 | #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 430 | |
| AnnaBridge | 163:e59c8e839560 | 431 | #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP) |
| AnnaBridge | 163:e59c8e839560 | 432 | #define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 433 | #define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 434 | #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 435 | |
| AnnaBridge | 163:e59c8e839560 | 436 | #if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP) |
| AnnaBridge | 163:e59c8e839560 | 437 | #define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 438 | #define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 439 | #endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 440 | |
| AnnaBridge | 163:e59c8e839560 | 441 | #if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP) |
| AnnaBridge | 163:e59c8e839560 | 442 | #define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 443 | #define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 444 | #endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 445 | |
| AnnaBridge | 163:e59c8e839560 | 446 | #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) |
| AnnaBridge | 163:e59c8e839560 | 447 | #define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 448 | #define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 449 | #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 450 | |
| AnnaBridge | 163:e59c8e839560 | 451 | #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) |
| AnnaBridge | 163:e59c8e839560 | 452 | #define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 453 | #define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 454 | #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 455 | |
| AnnaBridge | 163:e59c8e839560 | 456 | #if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP) |
| AnnaBridge | 163:e59c8e839560 | 457 | #define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 458 | #define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 459 | #endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 460 | |
| AnnaBridge | 163:e59c8e839560 | 461 | #if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP) |
| AnnaBridge | 163:e59c8e839560 | 462 | #define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 463 | #define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 464 | #endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 465 | |
| AnnaBridge | 163:e59c8e839560 | 466 | #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP) |
| AnnaBridge | 163:e59c8e839560 | 467 | #define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 468 | #define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 469 | #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 470 | |
| AnnaBridge | 163:e59c8e839560 | 471 | #if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP) |
| AnnaBridge | 163:e59c8e839560 | 472 | #define __HAL_FREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM18_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 473 | #define __HAL_UNFREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM18_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 474 | #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 475 | |
| AnnaBridge | 163:e59c8e839560 | 476 | #if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP) |
| AnnaBridge | 163:e59c8e839560 | 477 | #define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 478 | #define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 479 | #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 480 | |
| AnnaBridge | 163:e59c8e839560 | 481 | #if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP) |
| AnnaBridge | 163:e59c8e839560 | 482 | #define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 483 | #define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 484 | #endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 485 | |
| AnnaBridge | 163:e59c8e839560 | 486 | #if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP) |
| AnnaBridge | 163:e59c8e839560 | 487 | #define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 488 | #define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 489 | #endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 490 | |
| AnnaBridge | 163:e59c8e839560 | 491 | #if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) |
| AnnaBridge | 163:e59c8e839560 | 492 | #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) |
| AnnaBridge | 163:e59c8e839560 | 493 | #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) |
| AnnaBridge | 163:e59c8e839560 | 494 | #endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */ |
| AnnaBridge | 163:e59c8e839560 | 495 | |
| AnnaBridge | 163:e59c8e839560 | 496 | #if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) |
| AnnaBridge | 163:e59c8e839560 | 497 | #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) |
| AnnaBridge | 163:e59c8e839560 | 498 | #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) |
| AnnaBridge | 163:e59c8e839560 | 499 | #endif /* DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT */ |
| AnnaBridge | 163:e59c8e839560 | 500 | |
| AnnaBridge | 163:e59c8e839560 | 501 | #if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT) |
| AnnaBridge | 163:e59c8e839560 | 502 | #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) |
| AnnaBridge | 163:e59c8e839560 | 503 | #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) |
| AnnaBridge | 163:e59c8e839560 | 504 | #endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */ |
| AnnaBridge | 163:e59c8e839560 | 505 | |
| AnnaBridge | 163:e59c8e839560 | 506 | #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP) |
| AnnaBridge | 163:e59c8e839560 | 507 | #define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 508 | #define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 509 | #endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 510 | /** |
| AnnaBridge | 163:e59c8e839560 | 511 | * @} |
| AnnaBridge | 163:e59c8e839560 | 512 | */ |
| AnnaBridge | 163:e59c8e839560 | 513 | |
| AnnaBridge | 163:e59c8e839560 | 514 | /** @defgroup Debug_MCU_APB2_Freeze Freeze/Unfreeze APB2 Peripherals in Debug mode |
| AnnaBridge | 163:e59c8e839560 | 515 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 516 | */ |
| AnnaBridge | 163:e59c8e839560 | 517 | #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP) |
| AnnaBridge | 163:e59c8e839560 | 518 | #define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 519 | #define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 520 | #endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 521 | |
| AnnaBridge | 163:e59c8e839560 | 522 | #if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP) |
| AnnaBridge | 163:e59c8e839560 | 523 | #define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 524 | #define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 525 | #endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 526 | |
| AnnaBridge | 163:e59c8e839560 | 527 | #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP) |
| AnnaBridge | 163:e59c8e839560 | 528 | #define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 529 | #define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 530 | #endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 531 | |
| AnnaBridge | 163:e59c8e839560 | 532 | #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP) |
| AnnaBridge | 163:e59c8e839560 | 533 | #define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 534 | #define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 535 | #endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 536 | |
| AnnaBridge | 163:e59c8e839560 | 537 | #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP) |
| AnnaBridge | 163:e59c8e839560 | 538 | #define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 539 | #define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 540 | #endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 541 | |
| AnnaBridge | 163:e59c8e839560 | 542 | #if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP) |
| AnnaBridge | 163:e59c8e839560 | 543 | #define __HAL_FREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 544 | #define __HAL_UNFREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 545 | #endif /* DBGMCU_APB2_FZ_DBG_TIM19_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 546 | |
| AnnaBridge | 163:e59c8e839560 | 547 | #if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP) |
| AnnaBridge | 163:e59c8e839560 | 548 | #define __HAL_FREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM20_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 549 | #define __HAL_UNFREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM20_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 550 | #endif /* DBGMCU_APB2_FZ_DBG_TIM20_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 551 | |
| AnnaBridge | 163:e59c8e839560 | 552 | #if defined(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP) |
| AnnaBridge | 163:e59c8e839560 | 553 | #define __HAL_FREEZE_HRTIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 554 | #define __HAL_UNFREEZE_HRTIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)) |
| AnnaBridge | 163:e59c8e839560 | 555 | #endif /* DBGMCU_APB2_FZ_DBG_HRTIM1_STOP */ |
| AnnaBridge | 163:e59c8e839560 | 556 | /** |
| AnnaBridge | 163:e59c8e839560 | 557 | * @} |
| AnnaBridge | 163:e59c8e839560 | 558 | */ |
| AnnaBridge | 163:e59c8e839560 | 559 | |
| AnnaBridge | 163:e59c8e839560 | 560 | /** @defgroup Memory_Mapping_Selection Memory Mapping Selection |
| AnnaBridge | 163:e59c8e839560 | 561 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 562 | */ |
| AnnaBridge | 163:e59c8e839560 | 563 | #if defined(SYSCFG_CFGR1_MEM_MODE) |
| AnnaBridge | 163:e59c8e839560 | 564 | /** @brief Main Flash memory mapped at 0x00000000 |
| AnnaBridge | 163:e59c8e839560 | 565 | */ |
| AnnaBridge | 163:e59c8e839560 | 566 | #define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE)) |
| AnnaBridge | 163:e59c8e839560 | 567 | #endif /* SYSCFG_CFGR1_MEM_MODE */ |
| AnnaBridge | 163:e59c8e839560 | 568 | |
| AnnaBridge | 163:e59c8e839560 | 569 | #if defined(SYSCFG_CFGR1_MEM_MODE_0) |
| AnnaBridge | 163:e59c8e839560 | 570 | /** @brief System Flash memory mapped at 0x00000000 |
| AnnaBridge | 163:e59c8e839560 | 571 | */ |
| AnnaBridge | 163:e59c8e839560 | 572 | #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ |
| AnnaBridge | 163:e59c8e839560 | 573 | SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \ |
| AnnaBridge | 163:e59c8e839560 | 574 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 575 | #endif /* SYSCFG_CFGR1_MEM_MODE_0 */ |
| AnnaBridge | 163:e59c8e839560 | 576 | |
| AnnaBridge | 163:e59c8e839560 | 577 | #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1) |
| AnnaBridge | 163:e59c8e839560 | 578 | /** @brief Embedded SRAM mapped at 0x00000000 |
| AnnaBridge | 163:e59c8e839560 | 579 | */ |
| AnnaBridge | 163:e59c8e839560 | 580 | #define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ |
| AnnaBridge | 163:e59c8e839560 | 581 | SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \ |
| AnnaBridge | 163:e59c8e839560 | 582 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 583 | #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */ |
| AnnaBridge | 163:e59c8e839560 | 584 | |
| AnnaBridge | 163:e59c8e839560 | 585 | #if defined(SYSCFG_CFGR1_MEM_MODE_2) |
| AnnaBridge | 163:e59c8e839560 | 586 | #define __HAL_SYSCFG_FMC_BANK() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ |
| AnnaBridge | 163:e59c8e839560 | 587 | SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_2); \ |
| AnnaBridge | 163:e59c8e839560 | 588 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 589 | #endif /* SYSCFG_CFGR1_MEM_MODE_2 */ |
| AnnaBridge | 163:e59c8e839560 | 590 | /** |
| AnnaBridge | 163:e59c8e839560 | 591 | * @} |
| AnnaBridge | 163:e59c8e839560 | 592 | */ |
| AnnaBridge | 163:e59c8e839560 | 593 | |
| AnnaBridge | 163:e59c8e839560 | 594 | /** @defgroup Encoder_Mode Encoder Mode |
| AnnaBridge | 163:e59c8e839560 | 595 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 596 | */ |
| AnnaBridge | 163:e59c8e839560 | 597 | #if defined(SYSCFG_CFGR1_ENCODER_MODE) |
| AnnaBridge | 163:e59c8e839560 | 598 | /** @brief No Encoder mode |
| AnnaBridge | 163:e59c8e839560 | 599 | */ |
| AnnaBridge | 163:e59c8e839560 | 600 | #define __HAL_REMAPENCODER_NONE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE)) |
| AnnaBridge | 163:e59c8e839560 | 601 | #endif /* SYSCFG_CFGR1_ENCODER_MODE */ |
| AnnaBridge | 163:e59c8e839560 | 602 | |
| AnnaBridge | 163:e59c8e839560 | 603 | #if defined(SYSCFG_CFGR1_ENCODER_MODE_0) |
| AnnaBridge | 163:e59c8e839560 | 604 | /** @brief Encoder mode : TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively |
| AnnaBridge | 163:e59c8e839560 | 605 | */ |
| AnnaBridge | 163:e59c8e839560 | 606 | #define __HAL_REMAPENCODER_TIM2() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \ |
| AnnaBridge | 163:e59c8e839560 | 607 | SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_0; \ |
| AnnaBridge | 163:e59c8e839560 | 608 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 609 | #endif /* SYSCFG_CFGR1_ENCODER_MODE_0 */ |
| AnnaBridge | 163:e59c8e839560 | 610 | |
| AnnaBridge | 163:e59c8e839560 | 611 | #if defined(SYSCFG_CFGR1_ENCODER_MODE_1) |
| AnnaBridge | 163:e59c8e839560 | 612 | /** @brief Encoder mode : TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively |
| AnnaBridge | 163:e59c8e839560 | 613 | */ |
| AnnaBridge | 163:e59c8e839560 | 614 | #define __HAL_REMAPENCODER_TIM3() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \ |
| AnnaBridge | 163:e59c8e839560 | 615 | SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_1; \ |
| AnnaBridge | 163:e59c8e839560 | 616 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 617 | #endif /* SYSCFG_CFGR1_ENCODER_MODE_1 */ |
| AnnaBridge | 163:e59c8e839560 | 618 | |
| AnnaBridge | 163:e59c8e839560 | 619 | #if defined(SYSCFG_CFGR1_ENCODER_MODE_0) && defined(SYSCFG_CFGR1_ENCODER_MODE_1) |
| AnnaBridge | 163:e59c8e839560 | 620 | /** @brief Encoder mode : TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 (STM32F303xB/C and STM32F358xx devices) |
| AnnaBridge | 163:e59c8e839560 | 621 | */ |
| AnnaBridge | 163:e59c8e839560 | 622 | #define __HAL_REMAPENCODER_TIM4() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \ |
| AnnaBridge | 163:e59c8e839560 | 623 | SYSCFG->CFGR1 |= (SYSCFG_CFGR1_ENCODER_MODE_0 | SYSCFG_CFGR1_ENCODER_MODE_1); \ |
| AnnaBridge | 163:e59c8e839560 | 624 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 625 | #endif /* SYSCFG_CFGR1_ENCODER_MODE_0 && SYSCFG_CFGR1_ENCODER_MODE_1 */ |
| AnnaBridge | 163:e59c8e839560 | 626 | /** |
| AnnaBridge | 163:e59c8e839560 | 627 | * @} |
| AnnaBridge | 163:e59c8e839560 | 628 | */ |
| AnnaBridge | 163:e59c8e839560 | 629 | |
| AnnaBridge | 163:e59c8e839560 | 630 | /** @defgroup DMA_Remap_Enable DMA Remap Enable |
| AnnaBridge | 163:e59c8e839560 | 631 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 632 | */ |
| AnnaBridge | 163:e59c8e839560 | 633 | #if defined(SYSCFG_CFGR3_DMA_RMP) && defined(SYSCFG_CFGR1_DMA_RMP) |
| AnnaBridge | 163:e59c8e839560 | 634 | /** @brief DMA remapping enable/disable macros |
| AnnaBridge | 163:e59c8e839560 | 635 | * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping |
| AnnaBridge | 163:e59c8e839560 | 636 | */ |
| AnnaBridge | 163:e59c8e839560 | 637 | #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ |
| AnnaBridge | 163:e59c8e839560 | 638 | (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \ |
| AnnaBridge | 163:e59c8e839560 | 639 | (SYSCFG->CFGR3 |= ((__DMA_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \ |
| AnnaBridge | 163:e59c8e839560 | 640 | (SYSCFG->CFGR1 |= (__DMA_REMAP__))); \ |
| AnnaBridge | 163:e59c8e839560 | 641 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 642 | #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ |
| AnnaBridge | 163:e59c8e839560 | 643 | (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \ |
| AnnaBridge | 163:e59c8e839560 | 644 | (SYSCFG->CFGR3 &= (~(__DMA_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \ |
| AnnaBridge | 163:e59c8e839560 | 645 | (SYSCFG->CFGR1 &= ~(__DMA_REMAP__))); \ |
| AnnaBridge | 163:e59c8e839560 | 646 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 647 | #elif defined(SYSCFG_CFGR1_DMA_RMP) |
| AnnaBridge | 163:e59c8e839560 | 648 | /** @brief DMA remapping enable/disable macros |
| AnnaBridge | 163:e59c8e839560 | 649 | * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping |
| AnnaBridge | 163:e59c8e839560 | 650 | */ |
| AnnaBridge | 163:e59c8e839560 | 651 | #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ |
| AnnaBridge | 163:e59c8e839560 | 652 | SYSCFG->CFGR1 |= (__DMA_REMAP__); \ |
| AnnaBridge | 163:e59c8e839560 | 653 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 654 | #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ |
| AnnaBridge | 163:e59c8e839560 | 655 | SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \ |
| AnnaBridge | 163:e59c8e839560 | 656 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 657 | #endif /* SYSCFG_CFGR3_DMA_RMP || SYSCFG_CFGR1_DMA_RMP */ |
| AnnaBridge | 163:e59c8e839560 | 658 | /** |
| AnnaBridge | 163:e59c8e839560 | 659 | * @} |
| AnnaBridge | 163:e59c8e839560 | 660 | */ |
| AnnaBridge | 163:e59c8e839560 | 661 | |
| AnnaBridge | 163:e59c8e839560 | 662 | /** @defgroup FastModePlus_GPIO Fast-mode Plus on GPIO |
| AnnaBridge | 163:e59c8e839560 | 663 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 664 | */ |
| AnnaBridge | 163:e59c8e839560 | 665 | /** @brief Fast-mode Plus driving capability enable/disable macros |
| AnnaBridge | 163:e59c8e839560 | 666 | * @param __FASTMODEPLUS__: This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values. |
| AnnaBridge | 163:e59c8e839560 | 667 | * That you can find above these macros. |
| AnnaBridge | 163:e59c8e839560 | 668 | */ |
| AnnaBridge | 163:e59c8e839560 | 669 | #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ |
| AnnaBridge | 163:e59c8e839560 | 670 | SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ |
| AnnaBridge | 163:e59c8e839560 | 671 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 672 | |
| AnnaBridge | 163:e59c8e839560 | 673 | #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ |
| AnnaBridge | 163:e59c8e839560 | 674 | CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ |
| AnnaBridge | 163:e59c8e839560 | 675 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 676 | /** |
| AnnaBridge | 163:e59c8e839560 | 677 | * @} |
| AnnaBridge | 163:e59c8e839560 | 678 | */ |
| AnnaBridge | 163:e59c8e839560 | 679 | |
| AnnaBridge | 163:e59c8e839560 | 680 | /** @defgroup Floating_Point_Unit_Interrupts_Enable Floating Point Unit Interrupts Enable |
| AnnaBridge | 163:e59c8e839560 | 681 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 682 | */ |
| AnnaBridge | 163:e59c8e839560 | 683 | /** @brief SYSCFG interrupt enable/disable macros |
| AnnaBridge | 163:e59c8e839560 | 684 | * @param __INTERRUPT__: This parameter can be a value of @ref HAL_SYSCFG_Interrupts |
| AnnaBridge | 163:e59c8e839560 | 685 | */ |
| AnnaBridge | 163:e59c8e839560 | 686 | #define __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \ |
| AnnaBridge | 163:e59c8e839560 | 687 | SYSCFG->CFGR1 |= (__INTERRUPT__); \ |
| AnnaBridge | 163:e59c8e839560 | 688 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 689 | |
| AnnaBridge | 163:e59c8e839560 | 690 | #define __HAL_SYSCFG_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \ |
| AnnaBridge | 163:e59c8e839560 | 691 | SYSCFG->CFGR1 &= ~(__INTERRUPT__); \ |
| AnnaBridge | 163:e59c8e839560 | 692 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 693 | /** |
| AnnaBridge | 163:e59c8e839560 | 694 | * @} |
| AnnaBridge | 163:e59c8e839560 | 695 | */ |
| AnnaBridge | 163:e59c8e839560 | 696 | |
| AnnaBridge | 163:e59c8e839560 | 697 | #if defined(SYSCFG_CFGR1_USB_IT_RMP) |
| AnnaBridge | 163:e59c8e839560 | 698 | /** @defgroup USB_Interrupt_Remap USB Interrupt Remap |
| AnnaBridge | 163:e59c8e839560 | 699 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 700 | */ |
| AnnaBridge | 163:e59c8e839560 | 701 | /** @brief USB interrupt remapping enable/disable macros |
| AnnaBridge | 163:e59c8e839560 | 702 | */ |
| AnnaBridge | 163:e59c8e839560 | 703 | #define __HAL_REMAPINTERRUPT_USB_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_USB_IT_RMP)) |
| AnnaBridge | 163:e59c8e839560 | 704 | #define __HAL_REMAPINTERRUPT_USB_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_USB_IT_RMP)) |
| AnnaBridge | 163:e59c8e839560 | 705 | /** |
| AnnaBridge | 163:e59c8e839560 | 706 | * @} |
| AnnaBridge | 163:e59c8e839560 | 707 | */ |
| AnnaBridge | 163:e59c8e839560 | 708 | #endif /* SYSCFG_CFGR1_USB_IT_RMP */ |
| AnnaBridge | 163:e59c8e839560 | 709 | |
| AnnaBridge | 163:e59c8e839560 | 710 | #if defined(SYSCFG_CFGR1_VBAT) |
| AnnaBridge | 163:e59c8e839560 | 711 | /** @defgroup VBAT_Monitoring_Enable VBAT Monitoring Enable |
| AnnaBridge | 163:e59c8e839560 | 712 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 713 | */ |
| AnnaBridge | 163:e59c8e839560 | 714 | /** @brief SYSCFG interrupt enable/disable macros |
| AnnaBridge | 163:e59c8e839560 | 715 | */ |
| AnnaBridge | 163:e59c8e839560 | 716 | #define __HAL_SYSCFG_VBAT_MONITORING_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_VBAT)) |
| AnnaBridge | 163:e59c8e839560 | 717 | #define __HAL_SYSCFG_VBAT_MONITORING_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT)) |
| AnnaBridge | 163:e59c8e839560 | 718 | /** |
| AnnaBridge | 163:e59c8e839560 | 719 | * @} |
| AnnaBridge | 163:e59c8e839560 | 720 | */ |
| AnnaBridge | 163:e59c8e839560 | 721 | #endif /* SYSCFG_CFGR1_VBAT */ |
| AnnaBridge | 163:e59c8e839560 | 722 | |
| AnnaBridge | 163:e59c8e839560 | 723 | #if defined(SYSCFG_CFGR2_LOCKUP_LOCK) |
| AnnaBridge | 163:e59c8e839560 | 724 | /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable |
| AnnaBridge | 163:e59c8e839560 | 725 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 726 | */ |
| AnnaBridge | 163:e59c8e839560 | 727 | /** @brief SYSCFG Break Lockup lock |
| AnnaBridge | 163:e59c8e839560 | 728 | * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input |
| AnnaBridge | 163:e59c8e839560 | 729 | * @note The selected configuration is locked and can be unlocked by system reset |
| AnnaBridge | 163:e59c8e839560 | 730 | */ |
| AnnaBridge | 163:e59c8e839560 | 731 | #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \ |
| AnnaBridge | 163:e59c8e839560 | 732 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \ |
| AnnaBridge | 163:e59c8e839560 | 733 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 734 | /** |
| AnnaBridge | 163:e59c8e839560 | 735 | * @} |
| AnnaBridge | 163:e59c8e839560 | 736 | */ |
| AnnaBridge | 163:e59c8e839560 | 737 | #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */ |
| AnnaBridge | 163:e59c8e839560 | 738 | |
| AnnaBridge | 163:e59c8e839560 | 739 | #if defined(SYSCFG_CFGR2_PVD_LOCK) |
| AnnaBridge | 163:e59c8e839560 | 740 | /** @defgroup PVD_Lock_Enable PVD Lock |
| AnnaBridge | 163:e59c8e839560 | 741 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 742 | */ |
| AnnaBridge | 163:e59c8e839560 | 743 | /** @brief SYSCFG Break PVD lock |
| AnnaBridge | 163:e59c8e839560 | 744 | * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register |
| AnnaBridge | 163:e59c8e839560 | 745 | * @note The selected configuration is locked and can be unlocked by system reset |
| AnnaBridge | 163:e59c8e839560 | 746 | */ |
| AnnaBridge | 163:e59c8e839560 | 747 | #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \ |
| AnnaBridge | 163:e59c8e839560 | 748 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \ |
| AnnaBridge | 163:e59c8e839560 | 749 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 750 | /** |
| AnnaBridge | 163:e59c8e839560 | 751 | * @} |
| AnnaBridge | 163:e59c8e839560 | 752 | */ |
| AnnaBridge | 163:e59c8e839560 | 753 | #endif /* SYSCFG_CFGR2_PVD_LOCK */ |
| AnnaBridge | 163:e59c8e839560 | 754 | |
| AnnaBridge | 163:e59c8e839560 | 755 | #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK) |
| AnnaBridge | 163:e59c8e839560 | 756 | /** @defgroup SRAM_Parity_Lock SRAM Parity Lock |
| AnnaBridge | 163:e59c8e839560 | 757 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 758 | */ |
| AnnaBridge | 163:e59c8e839560 | 759 | /** @brief SYSCFG Break SRAM PARITY lock |
| AnnaBridge | 163:e59c8e839560 | 760 | * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 |
| AnnaBridge | 163:e59c8e839560 | 761 | * @note The selected configuration is locked and can be unlocked by system reset |
| AnnaBridge | 163:e59c8e839560 | 762 | */ |
| AnnaBridge | 163:e59c8e839560 | 763 | #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \ |
| AnnaBridge | 163:e59c8e839560 | 764 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \ |
| AnnaBridge | 163:e59c8e839560 | 765 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 766 | /** |
| AnnaBridge | 163:e59c8e839560 | 767 | * @} |
| AnnaBridge | 163:e59c8e839560 | 768 | */ |
| AnnaBridge | 163:e59c8e839560 | 769 | #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */ |
| AnnaBridge | 163:e59c8e839560 | 770 | |
| AnnaBridge | 163:e59c8e839560 | 771 | /** @defgroup Trigger_Remapping_Enable Trigger Remapping Enable |
| AnnaBridge | 163:e59c8e839560 | 772 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 773 | */ |
| AnnaBridge | 163:e59c8e839560 | 774 | #if defined(SYSCFG_CFGR3_TRIGGER_RMP) |
| AnnaBridge | 163:e59c8e839560 | 775 | /** @brief Trigger remapping enable/disable macros |
| AnnaBridge | 163:e59c8e839560 | 776 | * @param __TRIGGER_REMAP__: This parameter can be a value of @ref HAL_Trigger_Remapping |
| AnnaBridge | 163:e59c8e839560 | 777 | */ |
| AnnaBridge | 163:e59c8e839560 | 778 | #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \ |
| AnnaBridge | 163:e59c8e839560 | 779 | (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \ |
| AnnaBridge | 163:e59c8e839560 | 780 | (SYSCFG->CFGR3 |= ((__TRIGGER_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \ |
| AnnaBridge | 163:e59c8e839560 | 781 | (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__))); \ |
| AnnaBridge | 163:e59c8e839560 | 782 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 783 | #define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \ |
| AnnaBridge | 163:e59c8e839560 | 784 | (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \ |
| AnnaBridge | 163:e59c8e839560 | 785 | (SYSCFG->CFGR3 &= (~(__TRIGGER_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \ |
| AnnaBridge | 163:e59c8e839560 | 786 | (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__))); \ |
| AnnaBridge | 163:e59c8e839560 | 787 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 788 | #else |
| AnnaBridge | 163:e59c8e839560 | 789 | /** @brief Trigger remapping enable/disable macros |
| AnnaBridge | 163:e59c8e839560 | 790 | * @param __TRIGGER_REMAP__: This parameter can be a value of @ref HAL_Trigger_Remapping |
| AnnaBridge | 163:e59c8e839560 | 791 | */ |
| AnnaBridge | 163:e59c8e839560 | 792 | #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \ |
| AnnaBridge | 163:e59c8e839560 | 793 | (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__)); \ |
| AnnaBridge | 163:e59c8e839560 | 794 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 795 | #define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \ |
| AnnaBridge | 163:e59c8e839560 | 796 | (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__)); \ |
| AnnaBridge | 163:e59c8e839560 | 797 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 798 | #endif /* SYSCFG_CFGR3_TRIGGER_RMP */ |
| AnnaBridge | 163:e59c8e839560 | 799 | /** |
| AnnaBridge | 163:e59c8e839560 | 800 | * @} |
| AnnaBridge | 163:e59c8e839560 | 801 | */ |
| AnnaBridge | 163:e59c8e839560 | 802 | |
| AnnaBridge | 163:e59c8e839560 | 803 | #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) |
| AnnaBridge | 163:e59c8e839560 | 804 | /** @defgroup ADC_Trigger_Remapping_Enable ADC Trigger Remapping Enable |
| AnnaBridge | 163:e59c8e839560 | 805 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 806 | */ |
| AnnaBridge | 163:e59c8e839560 | 807 | /** @brief ADC trigger remapping enable/disable macros |
| AnnaBridge | 163:e59c8e839560 | 808 | * @param __ADCTRIGGER_REMAP__: This parameter can be a value of @ref HAL_ADC_Trigger_Remapping |
| AnnaBridge | 163:e59c8e839560 | 809 | */ |
| AnnaBridge | 163:e59c8e839560 | 810 | #define __HAL_REMAPADCTRIGGER_ENABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \ |
| AnnaBridge | 163:e59c8e839560 | 811 | (SYSCFG->CFGR4 |= (__ADCTRIGGER_REMAP__)); \ |
| AnnaBridge | 163:e59c8e839560 | 812 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 813 | #define __HAL_REMAPADCTRIGGER_DISABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \ |
| AnnaBridge | 163:e59c8e839560 | 814 | (SYSCFG->CFGR4 &= ~(__ADCTRIGGER_REMAP__)); \ |
| AnnaBridge | 163:e59c8e839560 | 815 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 816 | /** |
| AnnaBridge | 163:e59c8e839560 | 817 | * @} |
| AnnaBridge | 163:e59c8e839560 | 818 | */ |
| AnnaBridge | 163:e59c8e839560 | 819 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ |
| AnnaBridge | 163:e59c8e839560 | 820 | |
| AnnaBridge | 163:e59c8e839560 | 821 | #if defined(SYSCFG_CFGR2_BYP_ADDR_PAR) |
| AnnaBridge | 163:e59c8e839560 | 822 | /** @defgroup RAM_Parity_Check_Disable RAM Parity Check Disable |
| AnnaBridge | 163:e59c8e839560 | 823 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 824 | */ |
| AnnaBridge | 163:e59c8e839560 | 825 | /** |
| AnnaBridge | 163:e59c8e839560 | 826 | * @brief Parity check on RAM disable macro |
| AnnaBridge | 163:e59c8e839560 | 827 | * @note Disabling the parity check on RAM locks the configuration bit. |
| AnnaBridge | 163:e59c8e839560 | 828 | * To re-enable the parity check on RAM perform a system reset. |
| AnnaBridge | 163:e59c8e839560 | 829 | */ |
| AnnaBridge | 163:e59c8e839560 | 830 | #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (*(__IO uint32_t *) CFGR2_BYPADDRPAR_BB = 0x00000001U) |
| AnnaBridge | 163:e59c8e839560 | 831 | /** |
| AnnaBridge | 163:e59c8e839560 | 832 | * @} |
| AnnaBridge | 163:e59c8e839560 | 833 | */ |
| AnnaBridge | 163:e59c8e839560 | 834 | #endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */ |
| AnnaBridge | 163:e59c8e839560 | 835 | |
| AnnaBridge | 163:e59c8e839560 | 836 | #if defined(SYSCFG_RCR_PAGE0) |
| AnnaBridge | 163:e59c8e839560 | 837 | /** @defgroup CCM_RAM_Page_Write_Protection_Enable CCM RAM page write protection enable |
| AnnaBridge | 163:e59c8e839560 | 838 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 839 | */ |
| AnnaBridge | 163:e59c8e839560 | 840 | /** @brief CCM RAM page write protection enable macro |
| AnnaBridge | 163:e59c8e839560 | 841 | * @param __PAGE_WP__: This parameter can be a value of @ref HAL_Page_Write_Protection |
| AnnaBridge | 163:e59c8e839560 | 842 | * @note write protection can only be disabled by a system reset |
| AnnaBridge | 163:e59c8e839560 | 843 | */ |
| AnnaBridge | 163:e59c8e839560 | 844 | #define __HAL_SYSCFG_SRAM_WRP_ENABLE(__PAGE_WP__) do {assert_param(IS_HAL_SYSCFG_WP_PAGE((__PAGE_WP__))); \ |
| AnnaBridge | 163:e59c8e839560 | 845 | SYSCFG->RCR |= (__PAGE_WP__); \ |
| AnnaBridge | 163:e59c8e839560 | 846 | }while(0U) |
| AnnaBridge | 163:e59c8e839560 | 847 | /** |
| AnnaBridge | 163:e59c8e839560 | 848 | * @} |
| AnnaBridge | 163:e59c8e839560 | 849 | */ |
| AnnaBridge | 163:e59c8e839560 | 850 | #endif /* SYSCFG_RCR_PAGE0 */ |
| AnnaBridge | 163:e59c8e839560 | 851 | |
| AnnaBridge | 163:e59c8e839560 | 852 | /** |
| AnnaBridge | 163:e59c8e839560 | 853 | * @} |
| AnnaBridge | 163:e59c8e839560 | 854 | */ |
| AnnaBridge | 163:e59c8e839560 | 855 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 163:e59c8e839560 | 856 | /** @addtogroup HAL_Exported_Functions HAL Exported Functions |
| AnnaBridge | 163:e59c8e839560 | 857 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 858 | */ |
| AnnaBridge | 163:e59c8e839560 | 859 | |
| AnnaBridge | 163:e59c8e839560 | 860 | /** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions |
| AnnaBridge | 163:e59c8e839560 | 861 | * @brief Initialization and de-initialization functions |
| AnnaBridge | 163:e59c8e839560 | 862 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 863 | */ |
| AnnaBridge | 163:e59c8e839560 | 864 | /* Initialization and de-initialization functions ******************************/ |
| AnnaBridge | 163:e59c8e839560 | 865 | HAL_StatusTypeDef HAL_Init(void); |
| AnnaBridge | 163:e59c8e839560 | 866 | HAL_StatusTypeDef HAL_DeInit(void); |
| AnnaBridge | 163:e59c8e839560 | 867 | void HAL_MspInit(void); |
| AnnaBridge | 163:e59c8e839560 | 868 | void HAL_MspDeInit(void); |
| AnnaBridge | 163:e59c8e839560 | 869 | HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); |
| AnnaBridge | 163:e59c8e839560 | 870 | /** |
| AnnaBridge | 163:e59c8e839560 | 871 | * @} |
| AnnaBridge | 163:e59c8e839560 | 872 | */ |
| AnnaBridge | 163:e59c8e839560 | 873 | |
| AnnaBridge | 163:e59c8e839560 | 874 | /** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions |
| AnnaBridge | 163:e59c8e839560 | 875 | * @brief HAL Control functions |
| AnnaBridge | 163:e59c8e839560 | 876 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 877 | */ |
| AnnaBridge | 163:e59c8e839560 | 878 | /* Peripheral Control functions ************************************************/ |
| AnnaBridge | 163:e59c8e839560 | 879 | void HAL_IncTick(void); |
| AnnaBridge | 163:e59c8e839560 | 880 | void HAL_Delay(__IO uint32_t Delay); |
| AnnaBridge | 163:e59c8e839560 | 881 | void HAL_SuspendTick(void); |
| AnnaBridge | 163:e59c8e839560 | 882 | void HAL_ResumeTick(void); |
| AnnaBridge | 163:e59c8e839560 | 883 | uint32_t HAL_GetTick(void); |
| AnnaBridge | 163:e59c8e839560 | 884 | uint32_t HAL_GetHalVersion(void); |
| AnnaBridge | 163:e59c8e839560 | 885 | uint32_t HAL_GetREVID(void); |
| AnnaBridge | 163:e59c8e839560 | 886 | uint32_t HAL_GetDEVID(void); |
| AnnaBridge | 163:e59c8e839560 | 887 | void HAL_DBGMCU_EnableDBGSleepMode(void); |
| AnnaBridge | 163:e59c8e839560 | 888 | void HAL_DBGMCU_DisableDBGSleepMode(void); |
| AnnaBridge | 163:e59c8e839560 | 889 | void HAL_DBGMCU_EnableDBGStopMode(void); |
| AnnaBridge | 163:e59c8e839560 | 890 | void HAL_DBGMCU_DisableDBGStopMode(void); |
| AnnaBridge | 163:e59c8e839560 | 891 | void HAL_DBGMCU_EnableDBGStandbyMode(void); |
| AnnaBridge | 163:e59c8e839560 | 892 | void HAL_DBGMCU_DisableDBGStandbyMode(void); |
| AnnaBridge | 163:e59c8e839560 | 893 | /** |
| AnnaBridge | 163:e59c8e839560 | 894 | * @} |
| AnnaBridge | 163:e59c8e839560 | 895 | */ |
| AnnaBridge | 163:e59c8e839560 | 896 | |
| AnnaBridge | 163:e59c8e839560 | 897 | /** |
| AnnaBridge | 163:e59c8e839560 | 898 | * @} |
| AnnaBridge | 163:e59c8e839560 | 899 | */ |
| AnnaBridge | 163:e59c8e839560 | 900 | |
| AnnaBridge | 163:e59c8e839560 | 901 | /** |
| AnnaBridge | 163:e59c8e839560 | 902 | * @} |
| AnnaBridge | 163:e59c8e839560 | 903 | */ |
| AnnaBridge | 163:e59c8e839560 | 904 | |
| AnnaBridge | 163:e59c8e839560 | 905 | /** |
| AnnaBridge | 163:e59c8e839560 | 906 | * @} |
| AnnaBridge | 163:e59c8e839560 | 907 | */ |
| AnnaBridge | 163:e59c8e839560 | 908 | |
| AnnaBridge | 163:e59c8e839560 | 909 | #ifdef __cplusplus |
| AnnaBridge | 163:e59c8e839560 | 910 | } |
| AnnaBridge | 163:e59c8e839560 | 911 | #endif |
| AnnaBridge | 163:e59c8e839560 | 912 | |
| AnnaBridge | 163:e59c8e839560 | 913 | #endif /* __STM32F3xx_HAL_H */ |
| AnnaBridge | 163:e59c8e839560 | 914 | |
| AnnaBridge | 163:e59c8e839560 | 915 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
