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TARGET_LPC4088_DM/core_cm3.h@93:e188a91d3eaa, 2015-02-03 (annotated)
- Committer:
- Kojto
- Date:
- Tue Feb 03 15:31:20 2015 +0000
- Revision:
- 93:e188a91d3eaa
- Child:
- 110:165afa46840b
Release 93 of the mbed library
Main changes:
- Renesas RZ_A1H bugfixes - i2c, ticker
- new targets - Nucleo F303RE, Nucleo F070RB, BLE SMURFS,
Dragonfly 411RE,
- BusXXX - is connected method, plus operators addition
- LPC8xx - I2c fixes
- timestamp_t reverted to uint32_t
- RTX - fixes regarding stack (alignment, magic word)
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Kojto | 93:e188a91d3eaa | 1 | /**************************************************************************//** |
Kojto | 93:e188a91d3eaa | 2 | * @file core_cm3.h |
Kojto | 93:e188a91d3eaa | 3 | * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File |
Kojto | 93:e188a91d3eaa | 4 | * @version V3.20 |
Kojto | 93:e188a91d3eaa | 5 | * @date 25. February 2013 |
Kojto | 93:e188a91d3eaa | 6 | * |
Kojto | 93:e188a91d3eaa | 7 | * @note |
Kojto | 93:e188a91d3eaa | 8 | * |
Kojto | 93:e188a91d3eaa | 9 | ******************************************************************************/ |
Kojto | 93:e188a91d3eaa | 10 | /* Copyright (c) 2009 - 2013 ARM LIMITED |
Kojto | 93:e188a91d3eaa | 11 | |
Kojto | 93:e188a91d3eaa | 12 | All rights reserved. |
Kojto | 93:e188a91d3eaa | 13 | Redistribution and use in source and binary forms, with or without |
Kojto | 93:e188a91d3eaa | 14 | modification, are permitted provided that the following conditions are met: |
Kojto | 93:e188a91d3eaa | 15 | - Redistributions of source code must retain the above copyright |
Kojto | 93:e188a91d3eaa | 16 | notice, this list of conditions and the following disclaimer. |
Kojto | 93:e188a91d3eaa | 17 | - Redistributions in binary form must reproduce the above copyright |
Kojto | 93:e188a91d3eaa | 18 | notice, this list of conditions and the following disclaimer in the |
Kojto | 93:e188a91d3eaa | 19 | documentation and/or other materials provided with the distribution. |
Kojto | 93:e188a91d3eaa | 20 | - Neither the name of ARM nor the names of its contributors may be used |
Kojto | 93:e188a91d3eaa | 21 | to endorse or promote products derived from this software without |
Kojto | 93:e188a91d3eaa | 22 | specific prior written permission. |
Kojto | 93:e188a91d3eaa | 23 | * |
Kojto | 93:e188a91d3eaa | 24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
Kojto | 93:e188a91d3eaa | 25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
Kojto | 93:e188a91d3eaa | 26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
Kojto | 93:e188a91d3eaa | 27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
Kojto | 93:e188a91d3eaa | 28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
Kojto | 93:e188a91d3eaa | 29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
Kojto | 93:e188a91d3eaa | 30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
Kojto | 93:e188a91d3eaa | 31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
Kojto | 93:e188a91d3eaa | 32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
Kojto | 93:e188a91d3eaa | 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
Kojto | 93:e188a91d3eaa | 34 | POSSIBILITY OF SUCH DAMAGE. |
Kojto | 93:e188a91d3eaa | 35 | ---------------------------------------------------------------------------*/ |
Kojto | 93:e188a91d3eaa | 36 | |
Kojto | 93:e188a91d3eaa | 37 | |
Kojto | 93:e188a91d3eaa | 38 | #if defined ( __ICCARM__ ) |
Kojto | 93:e188a91d3eaa | 39 | #pragma system_include /* treat file as system include file for MISRA check */ |
Kojto | 93:e188a91d3eaa | 40 | #endif |
Kojto | 93:e188a91d3eaa | 41 | |
Kojto | 93:e188a91d3eaa | 42 | #ifdef __cplusplus |
Kojto | 93:e188a91d3eaa | 43 | extern "C" { |
Kojto | 93:e188a91d3eaa | 44 | #endif |
Kojto | 93:e188a91d3eaa | 45 | |
Kojto | 93:e188a91d3eaa | 46 | #ifndef __CORE_CM3_H_GENERIC |
Kojto | 93:e188a91d3eaa | 47 | #define __CORE_CM3_H_GENERIC |
Kojto | 93:e188a91d3eaa | 48 | |
Kojto | 93:e188a91d3eaa | 49 | /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
Kojto | 93:e188a91d3eaa | 50 | CMSIS violates the following MISRA-C:2004 rules: |
Kojto | 93:e188a91d3eaa | 51 | |
Kojto | 93:e188a91d3eaa | 52 | \li Required Rule 8.5, object/function definition in header file.<br> |
Kojto | 93:e188a91d3eaa | 53 | Function definitions in header files are used to allow 'inlining'. |
Kojto | 93:e188a91d3eaa | 54 | |
Kojto | 93:e188a91d3eaa | 55 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
Kojto | 93:e188a91d3eaa | 56 | Unions are used for effective representation of core registers. |
Kojto | 93:e188a91d3eaa | 57 | |
Kojto | 93:e188a91d3eaa | 58 | \li Advisory Rule 19.7, Function-like macro defined.<br> |
Kojto | 93:e188a91d3eaa | 59 | Function-like macros are used to allow more efficient code. |
Kojto | 93:e188a91d3eaa | 60 | */ |
Kojto | 93:e188a91d3eaa | 61 | |
Kojto | 93:e188a91d3eaa | 62 | |
Kojto | 93:e188a91d3eaa | 63 | /******************************************************************************* |
Kojto | 93:e188a91d3eaa | 64 | * CMSIS definitions |
Kojto | 93:e188a91d3eaa | 65 | ******************************************************************************/ |
Kojto | 93:e188a91d3eaa | 66 | /** \ingroup Cortex_M3 |
Kojto | 93:e188a91d3eaa | 67 | @{ |
Kojto | 93:e188a91d3eaa | 68 | */ |
Kojto | 93:e188a91d3eaa | 69 | |
Kojto | 93:e188a91d3eaa | 70 | /* CMSIS CM3 definitions */ |
Kojto | 93:e188a91d3eaa | 71 | #define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ |
Kojto | 93:e188a91d3eaa | 72 | #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ |
Kojto | 93:e188a91d3eaa | 73 | #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ |
Kojto | 93:e188a91d3eaa | 74 | __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
Kojto | 93:e188a91d3eaa | 75 | |
Kojto | 93:e188a91d3eaa | 76 | #define __CORTEX_M (0x03) /*!< Cortex-M Core */ |
Kojto | 93:e188a91d3eaa | 77 | |
Kojto | 93:e188a91d3eaa | 78 | |
Kojto | 93:e188a91d3eaa | 79 | #if defined ( __CC_ARM ) |
Kojto | 93:e188a91d3eaa | 80 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
Kojto | 93:e188a91d3eaa | 81 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
Kojto | 93:e188a91d3eaa | 82 | #define __STATIC_INLINE static __inline |
Kojto | 93:e188a91d3eaa | 83 | |
Kojto | 93:e188a91d3eaa | 84 | #elif defined ( __ICCARM__ ) |
Kojto | 93:e188a91d3eaa | 85 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
Kojto | 93:e188a91d3eaa | 86 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
Kojto | 93:e188a91d3eaa | 87 | #define __STATIC_INLINE static inline |
Kojto | 93:e188a91d3eaa | 88 | |
Kojto | 93:e188a91d3eaa | 89 | #elif defined ( __TMS470__ ) |
Kojto | 93:e188a91d3eaa | 90 | #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ |
Kojto | 93:e188a91d3eaa | 91 | #define __STATIC_INLINE static inline |
Kojto | 93:e188a91d3eaa | 92 | |
Kojto | 93:e188a91d3eaa | 93 | #elif defined ( __GNUC__ ) |
Kojto | 93:e188a91d3eaa | 94 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
Kojto | 93:e188a91d3eaa | 95 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
Kojto | 93:e188a91d3eaa | 96 | #define __STATIC_INLINE static inline |
Kojto | 93:e188a91d3eaa | 97 | |
Kojto | 93:e188a91d3eaa | 98 | #elif defined ( __TASKING__ ) |
Kojto | 93:e188a91d3eaa | 99 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
Kojto | 93:e188a91d3eaa | 100 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
Kojto | 93:e188a91d3eaa | 101 | #define __STATIC_INLINE static inline |
Kojto | 93:e188a91d3eaa | 102 | |
Kojto | 93:e188a91d3eaa | 103 | #endif |
Kojto | 93:e188a91d3eaa | 104 | |
Kojto | 93:e188a91d3eaa | 105 | /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all |
Kojto | 93:e188a91d3eaa | 106 | */ |
Kojto | 93:e188a91d3eaa | 107 | #define __FPU_USED 0 |
Kojto | 93:e188a91d3eaa | 108 | |
Kojto | 93:e188a91d3eaa | 109 | #if defined ( __CC_ARM ) |
Kojto | 93:e188a91d3eaa | 110 | #if defined __TARGET_FPU_VFP |
Kojto | 93:e188a91d3eaa | 111 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
Kojto | 93:e188a91d3eaa | 112 | #endif |
Kojto | 93:e188a91d3eaa | 113 | |
Kojto | 93:e188a91d3eaa | 114 | #elif defined ( __ICCARM__ ) |
Kojto | 93:e188a91d3eaa | 115 | #if defined __ARMVFP__ |
Kojto | 93:e188a91d3eaa | 116 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
Kojto | 93:e188a91d3eaa | 117 | #endif |
Kojto | 93:e188a91d3eaa | 118 | |
Kojto | 93:e188a91d3eaa | 119 | #elif defined ( __TMS470__ ) |
Kojto | 93:e188a91d3eaa | 120 | #if defined __TI__VFP_SUPPORT____ |
Kojto | 93:e188a91d3eaa | 121 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
Kojto | 93:e188a91d3eaa | 122 | #endif |
Kojto | 93:e188a91d3eaa | 123 | |
Kojto | 93:e188a91d3eaa | 124 | #elif defined ( __GNUC__ ) |
Kojto | 93:e188a91d3eaa | 125 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
Kojto | 93:e188a91d3eaa | 126 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
Kojto | 93:e188a91d3eaa | 127 | #endif |
Kojto | 93:e188a91d3eaa | 128 | |
Kojto | 93:e188a91d3eaa | 129 | #elif defined ( __TASKING__ ) |
Kojto | 93:e188a91d3eaa | 130 | #if defined __FPU_VFP__ |
Kojto | 93:e188a91d3eaa | 131 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
Kojto | 93:e188a91d3eaa | 132 | #endif |
Kojto | 93:e188a91d3eaa | 133 | #endif |
Kojto | 93:e188a91d3eaa | 134 | |
Kojto | 93:e188a91d3eaa | 135 | #include <stdint.h> /* standard types definitions */ |
Kojto | 93:e188a91d3eaa | 136 | #include <core_cmInstr.h> /* Core Instruction Access */ |
Kojto | 93:e188a91d3eaa | 137 | #include <core_cmFunc.h> /* Core Function Access */ |
Kojto | 93:e188a91d3eaa | 138 | |
Kojto | 93:e188a91d3eaa | 139 | #endif /* __CORE_CM3_H_GENERIC */ |
Kojto | 93:e188a91d3eaa | 140 | |
Kojto | 93:e188a91d3eaa | 141 | #ifndef __CMSIS_GENERIC |
Kojto | 93:e188a91d3eaa | 142 | |
Kojto | 93:e188a91d3eaa | 143 | #ifndef __CORE_CM3_H_DEPENDANT |
Kojto | 93:e188a91d3eaa | 144 | #define __CORE_CM3_H_DEPENDANT |
Kojto | 93:e188a91d3eaa | 145 | |
Kojto | 93:e188a91d3eaa | 146 | /* check device defines and use defaults */ |
Kojto | 93:e188a91d3eaa | 147 | #if defined __CHECK_DEVICE_DEFINES |
Kojto | 93:e188a91d3eaa | 148 | #ifndef __CM3_REV |
Kojto | 93:e188a91d3eaa | 149 | #define __CM3_REV 0x0200 |
Kojto | 93:e188a91d3eaa | 150 | #warning "__CM3_REV not defined in device header file; using default!" |
Kojto | 93:e188a91d3eaa | 151 | #endif |
Kojto | 93:e188a91d3eaa | 152 | |
Kojto | 93:e188a91d3eaa | 153 | #ifndef __MPU_PRESENT |
Kojto | 93:e188a91d3eaa | 154 | #define __MPU_PRESENT 0 |
Kojto | 93:e188a91d3eaa | 155 | #warning "__MPU_PRESENT not defined in device header file; using default!" |
Kojto | 93:e188a91d3eaa | 156 | #endif |
Kojto | 93:e188a91d3eaa | 157 | |
Kojto | 93:e188a91d3eaa | 158 | #ifndef __NVIC_PRIO_BITS |
Kojto | 93:e188a91d3eaa | 159 | #define __NVIC_PRIO_BITS 4 |
Kojto | 93:e188a91d3eaa | 160 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
Kojto | 93:e188a91d3eaa | 161 | #endif |
Kojto | 93:e188a91d3eaa | 162 | |
Kojto | 93:e188a91d3eaa | 163 | #ifndef __Vendor_SysTickConfig |
Kojto | 93:e188a91d3eaa | 164 | #define __Vendor_SysTickConfig 0 |
Kojto | 93:e188a91d3eaa | 165 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
Kojto | 93:e188a91d3eaa | 166 | #endif |
Kojto | 93:e188a91d3eaa | 167 | #endif |
Kojto | 93:e188a91d3eaa | 168 | |
Kojto | 93:e188a91d3eaa | 169 | /* IO definitions (access restrictions to peripheral registers) */ |
Kojto | 93:e188a91d3eaa | 170 | /** |
Kojto | 93:e188a91d3eaa | 171 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
Kojto | 93:e188a91d3eaa | 172 | |
Kojto | 93:e188a91d3eaa | 173 | <strong>IO Type Qualifiers</strong> are used |
Kojto | 93:e188a91d3eaa | 174 | \li to specify the access to peripheral variables. |
Kojto | 93:e188a91d3eaa | 175 | \li for automatic generation of peripheral register debug information. |
Kojto | 93:e188a91d3eaa | 176 | */ |
Kojto | 93:e188a91d3eaa | 177 | #ifdef __cplusplus |
Kojto | 93:e188a91d3eaa | 178 | #define __I volatile /*!< Defines 'read only' permissions */ |
Kojto | 93:e188a91d3eaa | 179 | #else |
Kojto | 93:e188a91d3eaa | 180 | #define __I volatile const /*!< Defines 'read only' permissions */ |
Kojto | 93:e188a91d3eaa | 181 | #endif |
Kojto | 93:e188a91d3eaa | 182 | #define __O volatile /*!< Defines 'write only' permissions */ |
Kojto | 93:e188a91d3eaa | 183 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
Kojto | 93:e188a91d3eaa | 184 | |
Kojto | 93:e188a91d3eaa | 185 | /*@} end of group Cortex_M3 */ |
Kojto | 93:e188a91d3eaa | 186 | |
Kojto | 93:e188a91d3eaa | 187 | |
Kojto | 93:e188a91d3eaa | 188 | |
Kojto | 93:e188a91d3eaa | 189 | /******************************************************************************* |
Kojto | 93:e188a91d3eaa | 190 | * Register Abstraction |
Kojto | 93:e188a91d3eaa | 191 | Core Register contain: |
Kojto | 93:e188a91d3eaa | 192 | - Core Register |
Kojto | 93:e188a91d3eaa | 193 | - Core NVIC Register |
Kojto | 93:e188a91d3eaa | 194 | - Core SCB Register |
Kojto | 93:e188a91d3eaa | 195 | - Core SysTick Register |
Kojto | 93:e188a91d3eaa | 196 | - Core Debug Register |
Kojto | 93:e188a91d3eaa | 197 | - Core MPU Register |
Kojto | 93:e188a91d3eaa | 198 | ******************************************************************************/ |
Kojto | 93:e188a91d3eaa | 199 | /** \defgroup CMSIS_core_register Defines and Type Definitions |
Kojto | 93:e188a91d3eaa | 200 | \brief Type definitions and defines for Cortex-M processor based devices. |
Kojto | 93:e188a91d3eaa | 201 | */ |
Kojto | 93:e188a91d3eaa | 202 | |
Kojto | 93:e188a91d3eaa | 203 | /** \ingroup CMSIS_core_register |
Kojto | 93:e188a91d3eaa | 204 | \defgroup CMSIS_CORE Status and Control Registers |
Kojto | 93:e188a91d3eaa | 205 | \brief Core Register type definitions. |
Kojto | 93:e188a91d3eaa | 206 | @{ |
Kojto | 93:e188a91d3eaa | 207 | */ |
Kojto | 93:e188a91d3eaa | 208 | |
Kojto | 93:e188a91d3eaa | 209 | /** \brief Union type to access the Application Program Status Register (APSR). |
Kojto | 93:e188a91d3eaa | 210 | */ |
Kojto | 93:e188a91d3eaa | 211 | typedef union |
Kojto | 93:e188a91d3eaa | 212 | { |
Kojto | 93:e188a91d3eaa | 213 | struct |
Kojto | 93:e188a91d3eaa | 214 | { |
Kojto | 93:e188a91d3eaa | 215 | #if (__CORTEX_M != 0x04) |
Kojto | 93:e188a91d3eaa | 216 | uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ |
Kojto | 93:e188a91d3eaa | 217 | #else |
Kojto | 93:e188a91d3eaa | 218 | uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ |
Kojto | 93:e188a91d3eaa | 219 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
Kojto | 93:e188a91d3eaa | 220 | uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ |
Kojto | 93:e188a91d3eaa | 221 | #endif |
Kojto | 93:e188a91d3eaa | 222 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
Kojto | 93:e188a91d3eaa | 223 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
Kojto | 93:e188a91d3eaa | 224 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
Kojto | 93:e188a91d3eaa | 225 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
Kojto | 93:e188a91d3eaa | 226 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
Kojto | 93:e188a91d3eaa | 227 | } b; /*!< Structure used for bit access */ |
Kojto | 93:e188a91d3eaa | 228 | uint32_t w; /*!< Type used for word access */ |
Kojto | 93:e188a91d3eaa | 229 | } APSR_Type; |
Kojto | 93:e188a91d3eaa | 230 | |
Kojto | 93:e188a91d3eaa | 231 | |
Kojto | 93:e188a91d3eaa | 232 | /** \brief Union type to access the Interrupt Program Status Register (IPSR). |
Kojto | 93:e188a91d3eaa | 233 | */ |
Kojto | 93:e188a91d3eaa | 234 | typedef union |
Kojto | 93:e188a91d3eaa | 235 | { |
Kojto | 93:e188a91d3eaa | 236 | struct |
Kojto | 93:e188a91d3eaa | 237 | { |
Kojto | 93:e188a91d3eaa | 238 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
Kojto | 93:e188a91d3eaa | 239 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
Kojto | 93:e188a91d3eaa | 240 | } b; /*!< Structure used for bit access */ |
Kojto | 93:e188a91d3eaa | 241 | uint32_t w; /*!< Type used for word access */ |
Kojto | 93:e188a91d3eaa | 242 | } IPSR_Type; |
Kojto | 93:e188a91d3eaa | 243 | |
Kojto | 93:e188a91d3eaa | 244 | |
Kojto | 93:e188a91d3eaa | 245 | /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
Kojto | 93:e188a91d3eaa | 246 | */ |
Kojto | 93:e188a91d3eaa | 247 | typedef union |
Kojto | 93:e188a91d3eaa | 248 | { |
Kojto | 93:e188a91d3eaa | 249 | struct |
Kojto | 93:e188a91d3eaa | 250 | { |
Kojto | 93:e188a91d3eaa | 251 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
Kojto | 93:e188a91d3eaa | 252 | #if (__CORTEX_M != 0x04) |
Kojto | 93:e188a91d3eaa | 253 | uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
Kojto | 93:e188a91d3eaa | 254 | #else |
Kojto | 93:e188a91d3eaa | 255 | uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ |
Kojto | 93:e188a91d3eaa | 256 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
Kojto | 93:e188a91d3eaa | 257 | uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ |
Kojto | 93:e188a91d3eaa | 258 | #endif |
Kojto | 93:e188a91d3eaa | 259 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
Kojto | 93:e188a91d3eaa | 260 | uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ |
Kojto | 93:e188a91d3eaa | 261 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
Kojto | 93:e188a91d3eaa | 262 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
Kojto | 93:e188a91d3eaa | 263 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
Kojto | 93:e188a91d3eaa | 264 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
Kojto | 93:e188a91d3eaa | 265 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
Kojto | 93:e188a91d3eaa | 266 | } b; /*!< Structure used for bit access */ |
Kojto | 93:e188a91d3eaa | 267 | uint32_t w; /*!< Type used for word access */ |
Kojto | 93:e188a91d3eaa | 268 | } xPSR_Type; |
Kojto | 93:e188a91d3eaa | 269 | |
Kojto | 93:e188a91d3eaa | 270 | |
Kojto | 93:e188a91d3eaa | 271 | /** \brief Union type to access the Control Registers (CONTROL). |
Kojto | 93:e188a91d3eaa | 272 | */ |
Kojto | 93:e188a91d3eaa | 273 | typedef union |
Kojto | 93:e188a91d3eaa | 274 | { |
Kojto | 93:e188a91d3eaa | 275 | struct |
Kojto | 93:e188a91d3eaa | 276 | { |
Kojto | 93:e188a91d3eaa | 277 | uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ |
Kojto | 93:e188a91d3eaa | 278 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
Kojto | 93:e188a91d3eaa | 279 | uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ |
Kojto | 93:e188a91d3eaa | 280 | uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ |
Kojto | 93:e188a91d3eaa | 281 | } b; /*!< Structure used for bit access */ |
Kojto | 93:e188a91d3eaa | 282 | uint32_t w; /*!< Type used for word access */ |
Kojto | 93:e188a91d3eaa | 283 | } CONTROL_Type; |
Kojto | 93:e188a91d3eaa | 284 | |
Kojto | 93:e188a91d3eaa | 285 | /*@} end of group CMSIS_CORE */ |
Kojto | 93:e188a91d3eaa | 286 | |
Kojto | 93:e188a91d3eaa | 287 | |
Kojto | 93:e188a91d3eaa | 288 | /** \ingroup CMSIS_core_register |
Kojto | 93:e188a91d3eaa | 289 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
Kojto | 93:e188a91d3eaa | 290 | \brief Type definitions for the NVIC Registers |
Kojto | 93:e188a91d3eaa | 291 | @{ |
Kojto | 93:e188a91d3eaa | 292 | */ |
Kojto | 93:e188a91d3eaa | 293 | |
Kojto | 93:e188a91d3eaa | 294 | /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
Kojto | 93:e188a91d3eaa | 295 | */ |
Kojto | 93:e188a91d3eaa | 296 | typedef struct |
Kojto | 93:e188a91d3eaa | 297 | { |
Kojto | 93:e188a91d3eaa | 298 | __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
Kojto | 93:e188a91d3eaa | 299 | uint32_t RESERVED0[24]; |
Kojto | 93:e188a91d3eaa | 300 | __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
Kojto | 93:e188a91d3eaa | 301 | uint32_t RSERVED1[24]; |
Kojto | 93:e188a91d3eaa | 302 | __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
Kojto | 93:e188a91d3eaa | 303 | uint32_t RESERVED2[24]; |
Kojto | 93:e188a91d3eaa | 304 | __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
Kojto | 93:e188a91d3eaa | 305 | uint32_t RESERVED3[24]; |
Kojto | 93:e188a91d3eaa | 306 | __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ |
Kojto | 93:e188a91d3eaa | 307 | uint32_t RESERVED4[56]; |
Kojto | 93:e188a91d3eaa | 308 | __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ |
Kojto | 93:e188a91d3eaa | 309 | uint32_t RESERVED5[644]; |
Kojto | 93:e188a91d3eaa | 310 | __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ |
Kojto | 93:e188a91d3eaa | 311 | } NVIC_Type; |
Kojto | 93:e188a91d3eaa | 312 | |
Kojto | 93:e188a91d3eaa | 313 | /* Software Triggered Interrupt Register Definitions */ |
Kojto | 93:e188a91d3eaa | 314 | #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ |
Kojto | 93:e188a91d3eaa | 315 | #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ |
Kojto | 93:e188a91d3eaa | 316 | |
Kojto | 93:e188a91d3eaa | 317 | /*@} end of group CMSIS_NVIC */ |
Kojto | 93:e188a91d3eaa | 318 | |
Kojto | 93:e188a91d3eaa | 319 | |
Kojto | 93:e188a91d3eaa | 320 | /** \ingroup CMSIS_core_register |
Kojto | 93:e188a91d3eaa | 321 | \defgroup CMSIS_SCB System Control Block (SCB) |
Kojto | 93:e188a91d3eaa | 322 | \brief Type definitions for the System Control Block Registers |
Kojto | 93:e188a91d3eaa | 323 | @{ |
Kojto | 93:e188a91d3eaa | 324 | */ |
Kojto | 93:e188a91d3eaa | 325 | |
Kojto | 93:e188a91d3eaa | 326 | /** \brief Structure type to access the System Control Block (SCB). |
Kojto | 93:e188a91d3eaa | 327 | */ |
Kojto | 93:e188a91d3eaa | 328 | typedef struct |
Kojto | 93:e188a91d3eaa | 329 | { |
Kojto | 93:e188a91d3eaa | 330 | __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
Kojto | 93:e188a91d3eaa | 331 | __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
Kojto | 93:e188a91d3eaa | 332 | __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
Kojto | 93:e188a91d3eaa | 333 | __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
Kojto | 93:e188a91d3eaa | 334 | __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
Kojto | 93:e188a91d3eaa | 335 | __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
Kojto | 93:e188a91d3eaa | 336 | __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ |
Kojto | 93:e188a91d3eaa | 337 | __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
Kojto | 93:e188a91d3eaa | 338 | __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ |
Kojto | 93:e188a91d3eaa | 339 | __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ |
Kojto | 93:e188a91d3eaa | 340 | __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ |
Kojto | 93:e188a91d3eaa | 341 | __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ |
Kojto | 93:e188a91d3eaa | 342 | __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ |
Kojto | 93:e188a91d3eaa | 343 | __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ |
Kojto | 93:e188a91d3eaa | 344 | __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ |
Kojto | 93:e188a91d3eaa | 345 | __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ |
Kojto | 93:e188a91d3eaa | 346 | __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ |
Kojto | 93:e188a91d3eaa | 347 | __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ |
Kojto | 93:e188a91d3eaa | 348 | __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ |
Kojto | 93:e188a91d3eaa | 349 | uint32_t RESERVED0[5]; |
Kojto | 93:e188a91d3eaa | 350 | __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ |
Kojto | 93:e188a91d3eaa | 351 | } SCB_Type; |
Kojto | 93:e188a91d3eaa | 352 | |
Kojto | 93:e188a91d3eaa | 353 | /* SCB CPUID Register Definitions */ |
Kojto | 93:e188a91d3eaa | 354 | #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ |
Kojto | 93:e188a91d3eaa | 355 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
Kojto | 93:e188a91d3eaa | 356 | |
Kojto | 93:e188a91d3eaa | 357 | #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ |
Kojto | 93:e188a91d3eaa | 358 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
Kojto | 93:e188a91d3eaa | 359 | |
Kojto | 93:e188a91d3eaa | 360 | #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ |
Kojto | 93:e188a91d3eaa | 361 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
Kojto | 93:e188a91d3eaa | 362 | |
Kojto | 93:e188a91d3eaa | 363 | #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ |
Kojto | 93:e188a91d3eaa | 364 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
Kojto | 93:e188a91d3eaa | 365 | |
Kojto | 93:e188a91d3eaa | 366 | #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ |
Kojto | 93:e188a91d3eaa | 367 | #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ |
Kojto | 93:e188a91d3eaa | 368 | |
Kojto | 93:e188a91d3eaa | 369 | /* SCB Interrupt Control State Register Definitions */ |
Kojto | 93:e188a91d3eaa | 370 | #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ |
Kojto | 93:e188a91d3eaa | 371 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
Kojto | 93:e188a91d3eaa | 372 | |
Kojto | 93:e188a91d3eaa | 373 | #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ |
Kojto | 93:e188a91d3eaa | 374 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
Kojto | 93:e188a91d3eaa | 375 | |
Kojto | 93:e188a91d3eaa | 376 | #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ |
Kojto | 93:e188a91d3eaa | 377 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
Kojto | 93:e188a91d3eaa | 378 | |
Kojto | 93:e188a91d3eaa | 379 | #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ |
Kojto | 93:e188a91d3eaa | 380 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
Kojto | 93:e188a91d3eaa | 381 | |
Kojto | 93:e188a91d3eaa | 382 | #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ |
Kojto | 93:e188a91d3eaa | 383 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
Kojto | 93:e188a91d3eaa | 384 | |
Kojto | 93:e188a91d3eaa | 385 | #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ |
Kojto | 93:e188a91d3eaa | 386 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
Kojto | 93:e188a91d3eaa | 387 | |
Kojto | 93:e188a91d3eaa | 388 | #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ |
Kojto | 93:e188a91d3eaa | 389 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
Kojto | 93:e188a91d3eaa | 390 | |
Kojto | 93:e188a91d3eaa | 391 | #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ |
Kojto | 93:e188a91d3eaa | 392 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
Kojto | 93:e188a91d3eaa | 393 | |
Kojto | 93:e188a91d3eaa | 394 | #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ |
Kojto | 93:e188a91d3eaa | 395 | #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ |
Kojto | 93:e188a91d3eaa | 396 | |
Kojto | 93:e188a91d3eaa | 397 | #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ |
Kojto | 93:e188a91d3eaa | 398 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ |
Kojto | 93:e188a91d3eaa | 399 | |
Kojto | 93:e188a91d3eaa | 400 | /* SCB Vector Table Offset Register Definitions */ |
Kojto | 93:e188a91d3eaa | 401 | #if (__CM3_REV < 0x0201) /* core r2p1 */ |
Kojto | 93:e188a91d3eaa | 402 | #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ |
Kojto | 93:e188a91d3eaa | 403 | #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ |
Kojto | 93:e188a91d3eaa | 404 | |
Kojto | 93:e188a91d3eaa | 405 | #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ |
Kojto | 93:e188a91d3eaa | 406 | #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
Kojto | 93:e188a91d3eaa | 407 | #else |
Kojto | 93:e188a91d3eaa | 408 | #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ |
Kojto | 93:e188a91d3eaa | 409 | #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
Kojto | 93:e188a91d3eaa | 410 | #endif |
Kojto | 93:e188a91d3eaa | 411 | |
Kojto | 93:e188a91d3eaa | 412 | /* SCB Application Interrupt and Reset Control Register Definitions */ |
Kojto | 93:e188a91d3eaa | 413 | #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ |
Kojto | 93:e188a91d3eaa | 414 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
Kojto | 93:e188a91d3eaa | 415 | |
Kojto | 93:e188a91d3eaa | 416 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ |
Kojto | 93:e188a91d3eaa | 417 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
Kojto | 93:e188a91d3eaa | 418 | |
Kojto | 93:e188a91d3eaa | 419 | #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ |
Kojto | 93:e188a91d3eaa | 420 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
Kojto | 93:e188a91d3eaa | 421 | |
Kojto | 93:e188a91d3eaa | 422 | #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ |
Kojto | 93:e188a91d3eaa | 423 | #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ |
Kojto | 93:e188a91d3eaa | 424 | |
Kojto | 93:e188a91d3eaa | 425 | #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ |
Kojto | 93:e188a91d3eaa | 426 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
Kojto | 93:e188a91d3eaa | 427 | |
Kojto | 93:e188a91d3eaa | 428 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
Kojto | 93:e188a91d3eaa | 429 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
Kojto | 93:e188a91d3eaa | 430 | |
Kojto | 93:e188a91d3eaa | 431 | #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ |
Kojto | 93:e188a91d3eaa | 432 | #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ |
Kojto | 93:e188a91d3eaa | 433 | |
Kojto | 93:e188a91d3eaa | 434 | /* SCB System Control Register Definitions */ |
Kojto | 93:e188a91d3eaa | 435 | #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ |
Kojto | 93:e188a91d3eaa | 436 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
Kojto | 93:e188a91d3eaa | 437 | |
Kojto | 93:e188a91d3eaa | 438 | #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ |
Kojto | 93:e188a91d3eaa | 439 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
Kojto | 93:e188a91d3eaa | 440 | |
Kojto | 93:e188a91d3eaa | 441 | #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ |
Kojto | 93:e188a91d3eaa | 442 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
Kojto | 93:e188a91d3eaa | 443 | |
Kojto | 93:e188a91d3eaa | 444 | /* SCB Configuration Control Register Definitions */ |
Kojto | 93:e188a91d3eaa | 445 | #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ |
Kojto | 93:e188a91d3eaa | 446 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
Kojto | 93:e188a91d3eaa | 447 | |
Kojto | 93:e188a91d3eaa | 448 | #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ |
Kojto | 93:e188a91d3eaa | 449 | #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ |
Kojto | 93:e188a91d3eaa | 450 | |
Kojto | 93:e188a91d3eaa | 451 | #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ |
Kojto | 93:e188a91d3eaa | 452 | #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ |
Kojto | 93:e188a91d3eaa | 453 | |
Kojto | 93:e188a91d3eaa | 454 | #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ |
Kojto | 93:e188a91d3eaa | 455 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
Kojto | 93:e188a91d3eaa | 456 | |
Kojto | 93:e188a91d3eaa | 457 | #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ |
Kojto | 93:e188a91d3eaa | 458 | #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ |
Kojto | 93:e188a91d3eaa | 459 | |
Kojto | 93:e188a91d3eaa | 460 | #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ |
Kojto | 93:e188a91d3eaa | 461 | #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ |
Kojto | 93:e188a91d3eaa | 462 | |
Kojto | 93:e188a91d3eaa | 463 | /* SCB System Handler Control and State Register Definitions */ |
Kojto | 93:e188a91d3eaa | 464 | #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ |
Kojto | 93:e188a91d3eaa | 465 | #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ |
Kojto | 93:e188a91d3eaa | 466 | |
Kojto | 93:e188a91d3eaa | 467 | #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ |
Kojto | 93:e188a91d3eaa | 468 | #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ |
Kojto | 93:e188a91d3eaa | 469 | |
Kojto | 93:e188a91d3eaa | 470 | #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ |
Kojto | 93:e188a91d3eaa | 471 | #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ |
Kojto | 93:e188a91d3eaa | 472 | |
Kojto | 93:e188a91d3eaa | 473 | #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ |
Kojto | 93:e188a91d3eaa | 474 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
Kojto | 93:e188a91d3eaa | 475 | |
Kojto | 93:e188a91d3eaa | 476 | #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ |
Kojto | 93:e188a91d3eaa | 477 | #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ |
Kojto | 93:e188a91d3eaa | 478 | |
Kojto | 93:e188a91d3eaa | 479 | #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ |
Kojto | 93:e188a91d3eaa | 480 | #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ |
Kojto | 93:e188a91d3eaa | 481 | |
Kojto | 93:e188a91d3eaa | 482 | #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ |
Kojto | 93:e188a91d3eaa | 483 | #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ |
Kojto | 93:e188a91d3eaa | 484 | |
Kojto | 93:e188a91d3eaa | 485 | #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ |
Kojto | 93:e188a91d3eaa | 486 | #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ |
Kojto | 93:e188a91d3eaa | 487 | |
Kojto | 93:e188a91d3eaa | 488 | #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ |
Kojto | 93:e188a91d3eaa | 489 | #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ |
Kojto | 93:e188a91d3eaa | 490 | |
Kojto | 93:e188a91d3eaa | 491 | #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ |
Kojto | 93:e188a91d3eaa | 492 | #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ |
Kojto | 93:e188a91d3eaa | 493 | |
Kojto | 93:e188a91d3eaa | 494 | #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ |
Kojto | 93:e188a91d3eaa | 495 | #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ |
Kojto | 93:e188a91d3eaa | 496 | |
Kojto | 93:e188a91d3eaa | 497 | #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ |
Kojto | 93:e188a91d3eaa | 498 | #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ |
Kojto | 93:e188a91d3eaa | 499 | |
Kojto | 93:e188a91d3eaa | 500 | #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ |
Kojto | 93:e188a91d3eaa | 501 | #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ |
Kojto | 93:e188a91d3eaa | 502 | |
Kojto | 93:e188a91d3eaa | 503 | #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ |
Kojto | 93:e188a91d3eaa | 504 | #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ |
Kojto | 93:e188a91d3eaa | 505 | |
Kojto | 93:e188a91d3eaa | 506 | /* SCB Configurable Fault Status Registers Definitions */ |
Kojto | 93:e188a91d3eaa | 507 | #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ |
Kojto | 93:e188a91d3eaa | 508 | #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ |
Kojto | 93:e188a91d3eaa | 509 | |
Kojto | 93:e188a91d3eaa | 510 | #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ |
Kojto | 93:e188a91d3eaa | 511 | #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ |
Kojto | 93:e188a91d3eaa | 512 | |
Kojto | 93:e188a91d3eaa | 513 | #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ |
Kojto | 93:e188a91d3eaa | 514 | #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ |
Kojto | 93:e188a91d3eaa | 515 | |
Kojto | 93:e188a91d3eaa | 516 | /* SCB Hard Fault Status Registers Definitions */ |
Kojto | 93:e188a91d3eaa | 517 | #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ |
Kojto | 93:e188a91d3eaa | 518 | #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ |
Kojto | 93:e188a91d3eaa | 519 | |
Kojto | 93:e188a91d3eaa | 520 | #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ |
Kojto | 93:e188a91d3eaa | 521 | #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ |
Kojto | 93:e188a91d3eaa | 522 | |
Kojto | 93:e188a91d3eaa | 523 | #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ |
Kojto | 93:e188a91d3eaa | 524 | #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ |
Kojto | 93:e188a91d3eaa | 525 | |
Kojto | 93:e188a91d3eaa | 526 | /* SCB Debug Fault Status Register Definitions */ |
Kojto | 93:e188a91d3eaa | 527 | #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ |
Kojto | 93:e188a91d3eaa | 528 | #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ |
Kojto | 93:e188a91d3eaa | 529 | |
Kojto | 93:e188a91d3eaa | 530 | #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ |
Kojto | 93:e188a91d3eaa | 531 | #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ |
Kojto | 93:e188a91d3eaa | 532 | |
Kojto | 93:e188a91d3eaa | 533 | #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ |
Kojto | 93:e188a91d3eaa | 534 | #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ |
Kojto | 93:e188a91d3eaa | 535 | |
Kojto | 93:e188a91d3eaa | 536 | #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ |
Kojto | 93:e188a91d3eaa | 537 | #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ |
Kojto | 93:e188a91d3eaa | 538 | |
Kojto | 93:e188a91d3eaa | 539 | #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ |
Kojto | 93:e188a91d3eaa | 540 | #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ |
Kojto | 93:e188a91d3eaa | 541 | |
Kojto | 93:e188a91d3eaa | 542 | /*@} end of group CMSIS_SCB */ |
Kojto | 93:e188a91d3eaa | 543 | |
Kojto | 93:e188a91d3eaa | 544 | |
Kojto | 93:e188a91d3eaa | 545 | /** \ingroup CMSIS_core_register |
Kojto | 93:e188a91d3eaa | 546 | \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) |
Kojto | 93:e188a91d3eaa | 547 | \brief Type definitions for the System Control and ID Register not in the SCB |
Kojto | 93:e188a91d3eaa | 548 | @{ |
Kojto | 93:e188a91d3eaa | 549 | */ |
Kojto | 93:e188a91d3eaa | 550 | |
Kojto | 93:e188a91d3eaa | 551 | /** \brief Structure type to access the System Control and ID Register not in the SCB. |
Kojto | 93:e188a91d3eaa | 552 | */ |
Kojto | 93:e188a91d3eaa | 553 | typedef struct |
Kojto | 93:e188a91d3eaa | 554 | { |
Kojto | 93:e188a91d3eaa | 555 | uint32_t RESERVED0[1]; |
Kojto | 93:e188a91d3eaa | 556 | __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ |
Kojto | 93:e188a91d3eaa | 557 | #if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) |
Kojto | 93:e188a91d3eaa | 558 | __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ |
Kojto | 93:e188a91d3eaa | 559 | #else |
Kojto | 93:e188a91d3eaa | 560 | uint32_t RESERVED1[1]; |
Kojto | 93:e188a91d3eaa | 561 | #endif |
Kojto | 93:e188a91d3eaa | 562 | } SCnSCB_Type; |
Kojto | 93:e188a91d3eaa | 563 | |
Kojto | 93:e188a91d3eaa | 564 | /* Interrupt Controller Type Register Definitions */ |
Kojto | 93:e188a91d3eaa | 565 | #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ |
Kojto | 93:e188a91d3eaa | 566 | #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ |
Kojto | 93:e188a91d3eaa | 567 | |
Kojto | 93:e188a91d3eaa | 568 | /* Auxiliary Control Register Definitions */ |
Kojto | 93:e188a91d3eaa | 569 | |
Kojto | 93:e188a91d3eaa | 570 | #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ |
Kojto | 93:e188a91d3eaa | 571 | #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ |
Kojto | 93:e188a91d3eaa | 572 | |
Kojto | 93:e188a91d3eaa | 573 | #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ |
Kojto | 93:e188a91d3eaa | 574 | #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ |
Kojto | 93:e188a91d3eaa | 575 | |
Kojto | 93:e188a91d3eaa | 576 | #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ |
Kojto | 93:e188a91d3eaa | 577 | #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ |
Kojto | 93:e188a91d3eaa | 578 | |
Kojto | 93:e188a91d3eaa | 579 | /*@} end of group CMSIS_SCnotSCB */ |
Kojto | 93:e188a91d3eaa | 580 | |
Kojto | 93:e188a91d3eaa | 581 | |
Kojto | 93:e188a91d3eaa | 582 | /** \ingroup CMSIS_core_register |
Kojto | 93:e188a91d3eaa | 583 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
Kojto | 93:e188a91d3eaa | 584 | \brief Type definitions for the System Timer Registers. |
Kojto | 93:e188a91d3eaa | 585 | @{ |
Kojto | 93:e188a91d3eaa | 586 | */ |
Kojto | 93:e188a91d3eaa | 587 | |
Kojto | 93:e188a91d3eaa | 588 | /** \brief Structure type to access the System Timer (SysTick). |
Kojto | 93:e188a91d3eaa | 589 | */ |
Kojto | 93:e188a91d3eaa | 590 | typedef struct |
Kojto | 93:e188a91d3eaa | 591 | { |
Kojto | 93:e188a91d3eaa | 592 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
Kojto | 93:e188a91d3eaa | 593 | __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
Kojto | 93:e188a91d3eaa | 594 | __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
Kojto | 93:e188a91d3eaa | 595 | __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
Kojto | 93:e188a91d3eaa | 596 | } SysTick_Type; |
Kojto | 93:e188a91d3eaa | 597 | |
Kojto | 93:e188a91d3eaa | 598 | /* SysTick Control / Status Register Definitions */ |
Kojto | 93:e188a91d3eaa | 599 | #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ |
Kojto | 93:e188a91d3eaa | 600 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
Kojto | 93:e188a91d3eaa | 601 | |
Kojto | 93:e188a91d3eaa | 602 | #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ |
Kojto | 93:e188a91d3eaa | 603 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
Kojto | 93:e188a91d3eaa | 604 | |
Kojto | 93:e188a91d3eaa | 605 | #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ |
Kojto | 93:e188a91d3eaa | 606 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
Kojto | 93:e188a91d3eaa | 607 | |
Kojto | 93:e188a91d3eaa | 608 | #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ |
Kojto | 93:e188a91d3eaa | 609 | #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ |
Kojto | 93:e188a91d3eaa | 610 | |
Kojto | 93:e188a91d3eaa | 611 | /* SysTick Reload Register Definitions */ |
Kojto | 93:e188a91d3eaa | 612 | #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ |
Kojto | 93:e188a91d3eaa | 613 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ |
Kojto | 93:e188a91d3eaa | 614 | |
Kojto | 93:e188a91d3eaa | 615 | /* SysTick Current Register Definitions */ |
Kojto | 93:e188a91d3eaa | 616 | #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ |
Kojto | 93:e188a91d3eaa | 617 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ |
Kojto | 93:e188a91d3eaa | 618 | |
Kojto | 93:e188a91d3eaa | 619 | /* SysTick Calibration Register Definitions */ |
Kojto | 93:e188a91d3eaa | 620 | #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ |
Kojto | 93:e188a91d3eaa | 621 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
Kojto | 93:e188a91d3eaa | 622 | |
Kojto | 93:e188a91d3eaa | 623 | #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ |
Kojto | 93:e188a91d3eaa | 624 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
Kojto | 93:e188a91d3eaa | 625 | |
Kojto | 93:e188a91d3eaa | 626 | #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ |
Kojto | 93:e188a91d3eaa | 627 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ |
Kojto | 93:e188a91d3eaa | 628 | |
Kojto | 93:e188a91d3eaa | 629 | /*@} end of group CMSIS_SysTick */ |
Kojto | 93:e188a91d3eaa | 630 | |
Kojto | 93:e188a91d3eaa | 631 | |
Kojto | 93:e188a91d3eaa | 632 | /** \ingroup CMSIS_core_register |
Kojto | 93:e188a91d3eaa | 633 | \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) |
Kojto | 93:e188a91d3eaa | 634 | \brief Type definitions for the Instrumentation Trace Macrocell (ITM) |
Kojto | 93:e188a91d3eaa | 635 | @{ |
Kojto | 93:e188a91d3eaa | 636 | */ |
Kojto | 93:e188a91d3eaa | 637 | |
Kojto | 93:e188a91d3eaa | 638 | /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). |
Kojto | 93:e188a91d3eaa | 639 | */ |
Kojto | 93:e188a91d3eaa | 640 | typedef struct |
Kojto | 93:e188a91d3eaa | 641 | { |
Kojto | 93:e188a91d3eaa | 642 | __O union |
Kojto | 93:e188a91d3eaa | 643 | { |
Kojto | 93:e188a91d3eaa | 644 | __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ |
Kojto | 93:e188a91d3eaa | 645 | __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ |
Kojto | 93:e188a91d3eaa | 646 | __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ |
Kojto | 93:e188a91d3eaa | 647 | } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ |
Kojto | 93:e188a91d3eaa | 648 | uint32_t RESERVED0[864]; |
Kojto | 93:e188a91d3eaa | 649 | __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ |
Kojto | 93:e188a91d3eaa | 650 | uint32_t RESERVED1[15]; |
Kojto | 93:e188a91d3eaa | 651 | __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ |
Kojto | 93:e188a91d3eaa | 652 | uint32_t RESERVED2[15]; |
Kojto | 93:e188a91d3eaa | 653 | __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ |
Kojto | 93:e188a91d3eaa | 654 | uint32_t RESERVED3[29]; |
Kojto | 93:e188a91d3eaa | 655 | __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ |
Kojto | 93:e188a91d3eaa | 656 | __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ |
Kojto | 93:e188a91d3eaa | 657 | __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ |
Kojto | 93:e188a91d3eaa | 658 | uint32_t RESERVED4[43]; |
Kojto | 93:e188a91d3eaa | 659 | __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ |
Kojto | 93:e188a91d3eaa | 660 | __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ |
Kojto | 93:e188a91d3eaa | 661 | uint32_t RESERVED5[6]; |
Kojto | 93:e188a91d3eaa | 662 | __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ |
Kojto | 93:e188a91d3eaa | 663 | __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ |
Kojto | 93:e188a91d3eaa | 664 | __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ |
Kojto | 93:e188a91d3eaa | 665 | __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ |
Kojto | 93:e188a91d3eaa | 666 | __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ |
Kojto | 93:e188a91d3eaa | 667 | __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ |
Kojto | 93:e188a91d3eaa | 668 | __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ |
Kojto | 93:e188a91d3eaa | 669 | __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ |
Kojto | 93:e188a91d3eaa | 670 | __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ |
Kojto | 93:e188a91d3eaa | 671 | __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ |
Kojto | 93:e188a91d3eaa | 672 | __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ |
Kojto | 93:e188a91d3eaa | 673 | __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ |
Kojto | 93:e188a91d3eaa | 674 | } ITM_Type; |
Kojto | 93:e188a91d3eaa | 675 | |
Kojto | 93:e188a91d3eaa | 676 | /* ITM Trace Privilege Register Definitions */ |
Kojto | 93:e188a91d3eaa | 677 | #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ |
Kojto | 93:e188a91d3eaa | 678 | #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ |
Kojto | 93:e188a91d3eaa | 679 | |
Kojto | 93:e188a91d3eaa | 680 | /* ITM Trace Control Register Definitions */ |
Kojto | 93:e188a91d3eaa | 681 | #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ |
Kojto | 93:e188a91d3eaa | 682 | #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ |
Kojto | 93:e188a91d3eaa | 683 | |
Kojto | 93:e188a91d3eaa | 684 | #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ |
Kojto | 93:e188a91d3eaa | 685 | #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ |
Kojto | 93:e188a91d3eaa | 686 | |
Kojto | 93:e188a91d3eaa | 687 | #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ |
Kojto | 93:e188a91d3eaa | 688 | #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ |
Kojto | 93:e188a91d3eaa | 689 | |
Kojto | 93:e188a91d3eaa | 690 | #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ |
Kojto | 93:e188a91d3eaa | 691 | #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ |
Kojto | 93:e188a91d3eaa | 692 | |
Kojto | 93:e188a91d3eaa | 693 | #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ |
Kojto | 93:e188a91d3eaa | 694 | #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ |
Kojto | 93:e188a91d3eaa | 695 | |
Kojto | 93:e188a91d3eaa | 696 | #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ |
Kojto | 93:e188a91d3eaa | 697 | #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ |
Kojto | 93:e188a91d3eaa | 698 | |
Kojto | 93:e188a91d3eaa | 699 | #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ |
Kojto | 93:e188a91d3eaa | 700 | #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ |
Kojto | 93:e188a91d3eaa | 701 | |
Kojto | 93:e188a91d3eaa | 702 | #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ |
Kojto | 93:e188a91d3eaa | 703 | #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ |
Kojto | 93:e188a91d3eaa | 704 | |
Kojto | 93:e188a91d3eaa | 705 | #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ |
Kojto | 93:e188a91d3eaa | 706 | #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ |
Kojto | 93:e188a91d3eaa | 707 | |
Kojto | 93:e188a91d3eaa | 708 | /* ITM Integration Write Register Definitions */ |
Kojto | 93:e188a91d3eaa | 709 | #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ |
Kojto | 93:e188a91d3eaa | 710 | #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ |
Kojto | 93:e188a91d3eaa | 711 | |
Kojto | 93:e188a91d3eaa | 712 | /* ITM Integration Read Register Definitions */ |
Kojto | 93:e188a91d3eaa | 713 | #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ |
Kojto | 93:e188a91d3eaa | 714 | #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ |
Kojto | 93:e188a91d3eaa | 715 | |
Kojto | 93:e188a91d3eaa | 716 | /* ITM Integration Mode Control Register Definitions */ |
Kojto | 93:e188a91d3eaa | 717 | #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ |
Kojto | 93:e188a91d3eaa | 718 | #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ |
Kojto | 93:e188a91d3eaa | 719 | |
Kojto | 93:e188a91d3eaa | 720 | /* ITM Lock Status Register Definitions */ |
Kojto | 93:e188a91d3eaa | 721 | #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ |
Kojto | 93:e188a91d3eaa | 722 | #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ |
Kojto | 93:e188a91d3eaa | 723 | |
Kojto | 93:e188a91d3eaa | 724 | #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ |
Kojto | 93:e188a91d3eaa | 725 | #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ |
Kojto | 93:e188a91d3eaa | 726 | |
Kojto | 93:e188a91d3eaa | 727 | #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ |
Kojto | 93:e188a91d3eaa | 728 | #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ |
Kojto | 93:e188a91d3eaa | 729 | |
Kojto | 93:e188a91d3eaa | 730 | /*@}*/ /* end of group CMSIS_ITM */ |
Kojto | 93:e188a91d3eaa | 731 | |
Kojto | 93:e188a91d3eaa | 732 | |
Kojto | 93:e188a91d3eaa | 733 | /** \ingroup CMSIS_core_register |
Kojto | 93:e188a91d3eaa | 734 | \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) |
Kojto | 93:e188a91d3eaa | 735 | \brief Type definitions for the Data Watchpoint and Trace (DWT) |
Kojto | 93:e188a91d3eaa | 736 | @{ |
Kojto | 93:e188a91d3eaa | 737 | */ |
Kojto | 93:e188a91d3eaa | 738 | |
Kojto | 93:e188a91d3eaa | 739 | /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). |
Kojto | 93:e188a91d3eaa | 740 | */ |
Kojto | 93:e188a91d3eaa | 741 | typedef struct |
Kojto | 93:e188a91d3eaa | 742 | { |
Kojto | 93:e188a91d3eaa | 743 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ |
Kojto | 93:e188a91d3eaa | 744 | __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ |
Kojto | 93:e188a91d3eaa | 745 | __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ |
Kojto | 93:e188a91d3eaa | 746 | __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ |
Kojto | 93:e188a91d3eaa | 747 | __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ |
Kojto | 93:e188a91d3eaa | 748 | __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ |
Kojto | 93:e188a91d3eaa | 749 | __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ |
Kojto | 93:e188a91d3eaa | 750 | __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ |
Kojto | 93:e188a91d3eaa | 751 | __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ |
Kojto | 93:e188a91d3eaa | 752 | __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ |
Kojto | 93:e188a91d3eaa | 753 | __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ |
Kojto | 93:e188a91d3eaa | 754 | uint32_t RESERVED0[1]; |
Kojto | 93:e188a91d3eaa | 755 | __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ |
Kojto | 93:e188a91d3eaa | 756 | __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ |
Kojto | 93:e188a91d3eaa | 757 | __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ |
Kojto | 93:e188a91d3eaa | 758 | uint32_t RESERVED1[1]; |
Kojto | 93:e188a91d3eaa | 759 | __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ |
Kojto | 93:e188a91d3eaa | 760 | __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ |
Kojto | 93:e188a91d3eaa | 761 | __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ |
Kojto | 93:e188a91d3eaa | 762 | uint32_t RESERVED2[1]; |
Kojto | 93:e188a91d3eaa | 763 | __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ |
Kojto | 93:e188a91d3eaa | 764 | __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ |
Kojto | 93:e188a91d3eaa | 765 | __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ |
Kojto | 93:e188a91d3eaa | 766 | } DWT_Type; |
Kojto | 93:e188a91d3eaa | 767 | |
Kojto | 93:e188a91d3eaa | 768 | /* DWT Control Register Definitions */ |
Kojto | 93:e188a91d3eaa | 769 | #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ |
Kojto | 93:e188a91d3eaa | 770 | #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ |
Kojto | 93:e188a91d3eaa | 771 | |
Kojto | 93:e188a91d3eaa | 772 | #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ |
Kojto | 93:e188a91d3eaa | 773 | #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ |
Kojto | 93:e188a91d3eaa | 774 | |
Kojto | 93:e188a91d3eaa | 775 | #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ |
Kojto | 93:e188a91d3eaa | 776 | #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ |
Kojto | 93:e188a91d3eaa | 777 | |
Kojto | 93:e188a91d3eaa | 778 | #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ |
Kojto | 93:e188a91d3eaa | 779 | #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ |
Kojto | 93:e188a91d3eaa | 780 | |
Kojto | 93:e188a91d3eaa | 781 | #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ |
Kojto | 93:e188a91d3eaa | 782 | #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ |
Kojto | 93:e188a91d3eaa | 783 | |
Kojto | 93:e188a91d3eaa | 784 | #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ |
Kojto | 93:e188a91d3eaa | 785 | #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ |
Kojto | 93:e188a91d3eaa | 786 | |
Kojto | 93:e188a91d3eaa | 787 | #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ |
Kojto | 93:e188a91d3eaa | 788 | #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ |
Kojto | 93:e188a91d3eaa | 789 | |
Kojto | 93:e188a91d3eaa | 790 | #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ |
Kojto | 93:e188a91d3eaa | 791 | #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ |
Kojto | 93:e188a91d3eaa | 792 | |
Kojto | 93:e188a91d3eaa | 793 | #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ |
Kojto | 93:e188a91d3eaa | 794 | #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ |
Kojto | 93:e188a91d3eaa | 795 | |
Kojto | 93:e188a91d3eaa | 796 | #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ |
Kojto | 93:e188a91d3eaa | 797 | #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ |
Kojto | 93:e188a91d3eaa | 798 | |
Kojto | 93:e188a91d3eaa | 799 | #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ |
Kojto | 93:e188a91d3eaa | 800 | #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ |
Kojto | 93:e188a91d3eaa | 801 | |
Kojto | 93:e188a91d3eaa | 802 | #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ |
Kojto | 93:e188a91d3eaa | 803 | #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ |
Kojto | 93:e188a91d3eaa | 804 | |
Kojto | 93:e188a91d3eaa | 805 | #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ |
Kojto | 93:e188a91d3eaa | 806 | #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ |
Kojto | 93:e188a91d3eaa | 807 | |
Kojto | 93:e188a91d3eaa | 808 | #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ |
Kojto | 93:e188a91d3eaa | 809 | #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ |
Kojto | 93:e188a91d3eaa | 810 | |
Kojto | 93:e188a91d3eaa | 811 | #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ |
Kojto | 93:e188a91d3eaa | 812 | #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ |
Kojto | 93:e188a91d3eaa | 813 | |
Kojto | 93:e188a91d3eaa | 814 | #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ |
Kojto | 93:e188a91d3eaa | 815 | #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ |
Kojto | 93:e188a91d3eaa | 816 | |
Kojto | 93:e188a91d3eaa | 817 | #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ |
Kojto | 93:e188a91d3eaa | 818 | #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ |
Kojto | 93:e188a91d3eaa | 819 | |
Kojto | 93:e188a91d3eaa | 820 | #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ |
Kojto | 93:e188a91d3eaa | 821 | #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ |
Kojto | 93:e188a91d3eaa | 822 | |
Kojto | 93:e188a91d3eaa | 823 | /* DWT CPI Count Register Definitions */ |
Kojto | 93:e188a91d3eaa | 824 | #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ |
Kojto | 93:e188a91d3eaa | 825 | #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ |
Kojto | 93:e188a91d3eaa | 826 | |
Kojto | 93:e188a91d3eaa | 827 | /* DWT Exception Overhead Count Register Definitions */ |
Kojto | 93:e188a91d3eaa | 828 | #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ |
Kojto | 93:e188a91d3eaa | 829 | #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ |
Kojto | 93:e188a91d3eaa | 830 | |
Kojto | 93:e188a91d3eaa | 831 | /* DWT Sleep Count Register Definitions */ |
Kojto | 93:e188a91d3eaa | 832 | #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ |
Kojto | 93:e188a91d3eaa | 833 | #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ |
Kojto | 93:e188a91d3eaa | 834 | |
Kojto | 93:e188a91d3eaa | 835 | /* DWT LSU Count Register Definitions */ |
Kojto | 93:e188a91d3eaa | 836 | #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ |
Kojto | 93:e188a91d3eaa | 837 | #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ |
Kojto | 93:e188a91d3eaa | 838 | |
Kojto | 93:e188a91d3eaa | 839 | /* DWT Folded-instruction Count Register Definitions */ |
Kojto | 93:e188a91d3eaa | 840 | #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ |
Kojto | 93:e188a91d3eaa | 841 | #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ |
Kojto | 93:e188a91d3eaa | 842 | |
Kojto | 93:e188a91d3eaa | 843 | /* DWT Comparator Mask Register Definitions */ |
Kojto | 93:e188a91d3eaa | 844 | #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ |
Kojto | 93:e188a91d3eaa | 845 | #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ |
Kojto | 93:e188a91d3eaa | 846 | |
Kojto | 93:e188a91d3eaa | 847 | /* DWT Comparator Function Register Definitions */ |
Kojto | 93:e188a91d3eaa | 848 | #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ |
Kojto | 93:e188a91d3eaa | 849 | #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ |
Kojto | 93:e188a91d3eaa | 850 | |
Kojto | 93:e188a91d3eaa | 851 | #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ |
Kojto | 93:e188a91d3eaa | 852 | #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ |
Kojto | 93:e188a91d3eaa | 853 | |
Kojto | 93:e188a91d3eaa | 854 | #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ |
Kojto | 93:e188a91d3eaa | 855 | #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ |
Kojto | 93:e188a91d3eaa | 856 | |
Kojto | 93:e188a91d3eaa | 857 | #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ |
Kojto | 93:e188a91d3eaa | 858 | #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ |
Kojto | 93:e188a91d3eaa | 859 | |
Kojto | 93:e188a91d3eaa | 860 | #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ |
Kojto | 93:e188a91d3eaa | 861 | #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ |
Kojto | 93:e188a91d3eaa | 862 | |
Kojto | 93:e188a91d3eaa | 863 | #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ |
Kojto | 93:e188a91d3eaa | 864 | #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ |
Kojto | 93:e188a91d3eaa | 865 | |
Kojto | 93:e188a91d3eaa | 866 | #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ |
Kojto | 93:e188a91d3eaa | 867 | #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ |
Kojto | 93:e188a91d3eaa | 868 | |
Kojto | 93:e188a91d3eaa | 869 | #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ |
Kojto | 93:e188a91d3eaa | 870 | #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ |
Kojto | 93:e188a91d3eaa | 871 | |
Kojto | 93:e188a91d3eaa | 872 | #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ |
Kojto | 93:e188a91d3eaa | 873 | #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ |
Kojto | 93:e188a91d3eaa | 874 | |
Kojto | 93:e188a91d3eaa | 875 | /*@}*/ /* end of group CMSIS_DWT */ |
Kojto | 93:e188a91d3eaa | 876 | |
Kojto | 93:e188a91d3eaa | 877 | |
Kojto | 93:e188a91d3eaa | 878 | /** \ingroup CMSIS_core_register |
Kojto | 93:e188a91d3eaa | 879 | \defgroup CMSIS_TPI Trace Port Interface (TPI) |
Kojto | 93:e188a91d3eaa | 880 | \brief Type definitions for the Trace Port Interface (TPI) |
Kojto | 93:e188a91d3eaa | 881 | @{ |
Kojto | 93:e188a91d3eaa | 882 | */ |
Kojto | 93:e188a91d3eaa | 883 | |
Kojto | 93:e188a91d3eaa | 884 | /** \brief Structure type to access the Trace Port Interface Register (TPI). |
Kojto | 93:e188a91d3eaa | 885 | */ |
Kojto | 93:e188a91d3eaa | 886 | typedef struct |
Kojto | 93:e188a91d3eaa | 887 | { |
Kojto | 93:e188a91d3eaa | 888 | __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ |
Kojto | 93:e188a91d3eaa | 889 | __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ |
Kojto | 93:e188a91d3eaa | 890 | uint32_t RESERVED0[2]; |
Kojto | 93:e188a91d3eaa | 891 | __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ |
Kojto | 93:e188a91d3eaa | 892 | uint32_t RESERVED1[55]; |
Kojto | 93:e188a91d3eaa | 893 | __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ |
Kojto | 93:e188a91d3eaa | 894 | uint32_t RESERVED2[131]; |
Kojto | 93:e188a91d3eaa | 895 | __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ |
Kojto | 93:e188a91d3eaa | 896 | __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ |
Kojto | 93:e188a91d3eaa | 897 | __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ |
Kojto | 93:e188a91d3eaa | 898 | uint32_t RESERVED3[759]; |
Kojto | 93:e188a91d3eaa | 899 | __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ |
Kojto | 93:e188a91d3eaa | 900 | __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ |
Kojto | 93:e188a91d3eaa | 901 | __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ |
Kojto | 93:e188a91d3eaa | 902 | uint32_t RESERVED4[1]; |
Kojto | 93:e188a91d3eaa | 903 | __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ |
Kojto | 93:e188a91d3eaa | 904 | __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ |
Kojto | 93:e188a91d3eaa | 905 | __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ |
Kojto | 93:e188a91d3eaa | 906 | uint32_t RESERVED5[39]; |
Kojto | 93:e188a91d3eaa | 907 | __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ |
Kojto | 93:e188a91d3eaa | 908 | __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ |
Kojto | 93:e188a91d3eaa | 909 | uint32_t RESERVED7[8]; |
Kojto | 93:e188a91d3eaa | 910 | __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ |
Kojto | 93:e188a91d3eaa | 911 | __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ |
Kojto | 93:e188a91d3eaa | 912 | } TPI_Type; |
Kojto | 93:e188a91d3eaa | 913 | |
Kojto | 93:e188a91d3eaa | 914 | /* TPI Asynchronous Clock Prescaler Register Definitions */ |
Kojto | 93:e188a91d3eaa | 915 | #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ |
Kojto | 93:e188a91d3eaa | 916 | #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ |
Kojto | 93:e188a91d3eaa | 917 | |
Kojto | 93:e188a91d3eaa | 918 | /* TPI Selected Pin Protocol Register Definitions */ |
Kojto | 93:e188a91d3eaa | 919 | #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ |
Kojto | 93:e188a91d3eaa | 920 | #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ |
Kojto | 93:e188a91d3eaa | 921 | |
Kojto | 93:e188a91d3eaa | 922 | /* TPI Formatter and Flush Status Register Definitions */ |
Kojto | 93:e188a91d3eaa | 923 | #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ |
Kojto | 93:e188a91d3eaa | 924 | #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ |
Kojto | 93:e188a91d3eaa | 925 | |
Kojto | 93:e188a91d3eaa | 926 | #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ |
Kojto | 93:e188a91d3eaa | 927 | #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ |
Kojto | 93:e188a91d3eaa | 928 | |
Kojto | 93:e188a91d3eaa | 929 | #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ |
Kojto | 93:e188a91d3eaa | 930 | #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ |
Kojto | 93:e188a91d3eaa | 931 | |
Kojto | 93:e188a91d3eaa | 932 | #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ |
Kojto | 93:e188a91d3eaa | 933 | #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ |
Kojto | 93:e188a91d3eaa | 934 | |
Kojto | 93:e188a91d3eaa | 935 | /* TPI Formatter and Flush Control Register Definitions */ |
Kojto | 93:e188a91d3eaa | 936 | #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ |
Kojto | 93:e188a91d3eaa | 937 | #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ |
Kojto | 93:e188a91d3eaa | 938 | |
Kojto | 93:e188a91d3eaa | 939 | #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ |
Kojto | 93:e188a91d3eaa | 940 | #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ |
Kojto | 93:e188a91d3eaa | 941 | |
Kojto | 93:e188a91d3eaa | 942 | /* TPI TRIGGER Register Definitions */ |
Kojto | 93:e188a91d3eaa | 943 | #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ |
Kojto | 93:e188a91d3eaa | 944 | #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ |
Kojto | 93:e188a91d3eaa | 945 | |
Kojto | 93:e188a91d3eaa | 946 | /* TPI Integration ETM Data Register Definitions (FIFO0) */ |
Kojto | 93:e188a91d3eaa | 947 | #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ |
Kojto | 93:e188a91d3eaa | 948 | #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ |
Kojto | 93:e188a91d3eaa | 949 | |
Kojto | 93:e188a91d3eaa | 950 | #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ |
Kojto | 93:e188a91d3eaa | 951 | #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ |
Kojto | 93:e188a91d3eaa | 952 | |
Kojto | 93:e188a91d3eaa | 953 | #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ |
Kojto | 93:e188a91d3eaa | 954 | #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ |
Kojto | 93:e188a91d3eaa | 955 | |
Kojto | 93:e188a91d3eaa | 956 | #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ |
Kojto | 93:e188a91d3eaa | 957 | #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ |
Kojto | 93:e188a91d3eaa | 958 | |
Kojto | 93:e188a91d3eaa | 959 | #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ |
Kojto | 93:e188a91d3eaa | 960 | #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ |
Kojto | 93:e188a91d3eaa | 961 | |
Kojto | 93:e188a91d3eaa | 962 | #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ |
Kojto | 93:e188a91d3eaa | 963 | #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ |
Kojto | 93:e188a91d3eaa | 964 | |
Kojto | 93:e188a91d3eaa | 965 | #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ |
Kojto | 93:e188a91d3eaa | 966 | #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ |
Kojto | 93:e188a91d3eaa | 967 | |
Kojto | 93:e188a91d3eaa | 968 | /* TPI ITATBCTR2 Register Definitions */ |
Kojto | 93:e188a91d3eaa | 969 | #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ |
Kojto | 93:e188a91d3eaa | 970 | #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ |
Kojto | 93:e188a91d3eaa | 971 | |
Kojto | 93:e188a91d3eaa | 972 | /* TPI Integration ITM Data Register Definitions (FIFO1) */ |
Kojto | 93:e188a91d3eaa | 973 | #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ |
Kojto | 93:e188a91d3eaa | 974 | #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ |
Kojto | 93:e188a91d3eaa | 975 | |
Kojto | 93:e188a91d3eaa | 976 | #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ |
Kojto | 93:e188a91d3eaa | 977 | #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ |
Kojto | 93:e188a91d3eaa | 978 | |
Kojto | 93:e188a91d3eaa | 979 | #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ |
Kojto | 93:e188a91d3eaa | 980 | #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ |
Kojto | 93:e188a91d3eaa | 981 | |
Kojto | 93:e188a91d3eaa | 982 | #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ |
Kojto | 93:e188a91d3eaa | 983 | #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ |
Kojto | 93:e188a91d3eaa | 984 | |
Kojto | 93:e188a91d3eaa | 985 | #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ |
Kojto | 93:e188a91d3eaa | 986 | #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ |
Kojto | 93:e188a91d3eaa | 987 | |
Kojto | 93:e188a91d3eaa | 988 | #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ |
Kojto | 93:e188a91d3eaa | 989 | #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ |
Kojto | 93:e188a91d3eaa | 990 | |
Kojto | 93:e188a91d3eaa | 991 | #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ |
Kojto | 93:e188a91d3eaa | 992 | #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ |
Kojto | 93:e188a91d3eaa | 993 | |
Kojto | 93:e188a91d3eaa | 994 | /* TPI ITATBCTR0 Register Definitions */ |
Kojto | 93:e188a91d3eaa | 995 | #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ |
Kojto | 93:e188a91d3eaa | 996 | #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ |
Kojto | 93:e188a91d3eaa | 997 | |
Kojto | 93:e188a91d3eaa | 998 | /* TPI Integration Mode Control Register Definitions */ |
Kojto | 93:e188a91d3eaa | 999 | #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ |
Kojto | 93:e188a91d3eaa | 1000 | #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ |
Kojto | 93:e188a91d3eaa | 1001 | |
Kojto | 93:e188a91d3eaa | 1002 | /* TPI DEVID Register Definitions */ |
Kojto | 93:e188a91d3eaa | 1003 | #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ |
Kojto | 93:e188a91d3eaa | 1004 | #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ |
Kojto | 93:e188a91d3eaa | 1005 | |
Kojto | 93:e188a91d3eaa | 1006 | #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ |
Kojto | 93:e188a91d3eaa | 1007 | #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ |
Kojto | 93:e188a91d3eaa | 1008 | |
Kojto | 93:e188a91d3eaa | 1009 | #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ |
Kojto | 93:e188a91d3eaa | 1010 | #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ |
Kojto | 93:e188a91d3eaa | 1011 | |
Kojto | 93:e188a91d3eaa | 1012 | #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ |
Kojto | 93:e188a91d3eaa | 1013 | #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ |
Kojto | 93:e188a91d3eaa | 1014 | |
Kojto | 93:e188a91d3eaa | 1015 | #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ |
Kojto | 93:e188a91d3eaa | 1016 | #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ |
Kojto | 93:e188a91d3eaa | 1017 | |
Kojto | 93:e188a91d3eaa | 1018 | #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ |
Kojto | 93:e188a91d3eaa | 1019 | #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ |
Kojto | 93:e188a91d3eaa | 1020 | |
Kojto | 93:e188a91d3eaa | 1021 | /* TPI DEVTYPE Register Definitions */ |
Kojto | 93:e188a91d3eaa | 1022 | #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ |
Kojto | 93:e188a91d3eaa | 1023 | #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ |
Kojto | 93:e188a91d3eaa | 1024 | |
Kojto | 93:e188a91d3eaa | 1025 | #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ |
Kojto | 93:e188a91d3eaa | 1026 | #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ |
Kojto | 93:e188a91d3eaa | 1027 | |
Kojto | 93:e188a91d3eaa | 1028 | /*@}*/ /* end of group CMSIS_TPI */ |
Kojto | 93:e188a91d3eaa | 1029 | |
Kojto | 93:e188a91d3eaa | 1030 | |
Kojto | 93:e188a91d3eaa | 1031 | #if (__MPU_PRESENT == 1) |
Kojto | 93:e188a91d3eaa | 1032 | /** \ingroup CMSIS_core_register |
Kojto | 93:e188a91d3eaa | 1033 | \defgroup CMSIS_MPU Memory Protection Unit (MPU) |
Kojto | 93:e188a91d3eaa | 1034 | \brief Type definitions for the Memory Protection Unit (MPU) |
Kojto | 93:e188a91d3eaa | 1035 | @{ |
Kojto | 93:e188a91d3eaa | 1036 | */ |
Kojto | 93:e188a91d3eaa | 1037 | |
Kojto | 93:e188a91d3eaa | 1038 | /** \brief Structure type to access the Memory Protection Unit (MPU). |
Kojto | 93:e188a91d3eaa | 1039 | */ |
Kojto | 93:e188a91d3eaa | 1040 | typedef struct |
Kojto | 93:e188a91d3eaa | 1041 | { |
Kojto | 93:e188a91d3eaa | 1042 | __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
Kojto | 93:e188a91d3eaa | 1043 | __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
Kojto | 93:e188a91d3eaa | 1044 | __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ |
Kojto | 93:e188a91d3eaa | 1045 | __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
Kojto | 93:e188a91d3eaa | 1046 | __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ |
Kojto | 93:e188a91d3eaa | 1047 | __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ |
Kojto | 93:e188a91d3eaa | 1048 | __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ |
Kojto | 93:e188a91d3eaa | 1049 | __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ |
Kojto | 93:e188a91d3eaa | 1050 | __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ |
Kojto | 93:e188a91d3eaa | 1051 | __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ |
Kojto | 93:e188a91d3eaa | 1052 | __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ |
Kojto | 93:e188a91d3eaa | 1053 | } MPU_Type; |
Kojto | 93:e188a91d3eaa | 1054 | |
Kojto | 93:e188a91d3eaa | 1055 | /* MPU Type Register */ |
Kojto | 93:e188a91d3eaa | 1056 | #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ |
Kojto | 93:e188a91d3eaa | 1057 | #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
Kojto | 93:e188a91d3eaa | 1058 | |
Kojto | 93:e188a91d3eaa | 1059 | #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ |
Kojto | 93:e188a91d3eaa | 1060 | #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
Kojto | 93:e188a91d3eaa | 1061 | |
Kojto | 93:e188a91d3eaa | 1062 | #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ |
Kojto | 93:e188a91d3eaa | 1063 | #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ |
Kojto | 93:e188a91d3eaa | 1064 | |
Kojto | 93:e188a91d3eaa | 1065 | /* MPU Control Register */ |
Kojto | 93:e188a91d3eaa | 1066 | #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ |
Kojto | 93:e188a91d3eaa | 1067 | #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
Kojto | 93:e188a91d3eaa | 1068 | |
Kojto | 93:e188a91d3eaa | 1069 | #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ |
Kojto | 93:e188a91d3eaa | 1070 | #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
Kojto | 93:e188a91d3eaa | 1071 | |
Kojto | 93:e188a91d3eaa | 1072 | #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ |
Kojto | 93:e188a91d3eaa | 1073 | #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ |
Kojto | 93:e188a91d3eaa | 1074 | |
Kojto | 93:e188a91d3eaa | 1075 | /* MPU Region Number Register */ |
Kojto | 93:e188a91d3eaa | 1076 | #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ |
Kojto | 93:e188a91d3eaa | 1077 | #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ |
Kojto | 93:e188a91d3eaa | 1078 | |
Kojto | 93:e188a91d3eaa | 1079 | /* MPU Region Base Address Register */ |
Kojto | 93:e188a91d3eaa | 1080 | #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ |
Kojto | 93:e188a91d3eaa | 1081 | #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
Kojto | 93:e188a91d3eaa | 1082 | |
Kojto | 93:e188a91d3eaa | 1083 | #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ |
Kojto | 93:e188a91d3eaa | 1084 | #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
Kojto | 93:e188a91d3eaa | 1085 | |
Kojto | 93:e188a91d3eaa | 1086 | #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ |
Kojto | 93:e188a91d3eaa | 1087 | #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ |
Kojto | 93:e188a91d3eaa | 1088 | |
Kojto | 93:e188a91d3eaa | 1089 | /* MPU Region Attribute and Size Register */ |
Kojto | 93:e188a91d3eaa | 1090 | #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ |
Kojto | 93:e188a91d3eaa | 1091 | #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ |
Kojto | 93:e188a91d3eaa | 1092 | |
Kojto | 93:e188a91d3eaa | 1093 | #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ |
Kojto | 93:e188a91d3eaa | 1094 | #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ |
Kojto | 93:e188a91d3eaa | 1095 | |
Kojto | 93:e188a91d3eaa | 1096 | #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ |
Kojto | 93:e188a91d3eaa | 1097 | #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ |
Kojto | 93:e188a91d3eaa | 1098 | |
Kojto | 93:e188a91d3eaa | 1099 | #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ |
Kojto | 93:e188a91d3eaa | 1100 | #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ |
Kojto | 93:e188a91d3eaa | 1101 | |
Kojto | 93:e188a91d3eaa | 1102 | #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ |
Kojto | 93:e188a91d3eaa | 1103 | #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ |
Kojto | 93:e188a91d3eaa | 1104 | |
Kojto | 93:e188a91d3eaa | 1105 | #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ |
Kojto | 93:e188a91d3eaa | 1106 | #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ |
Kojto | 93:e188a91d3eaa | 1107 | |
Kojto | 93:e188a91d3eaa | 1108 | #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ |
Kojto | 93:e188a91d3eaa | 1109 | #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ |
Kojto | 93:e188a91d3eaa | 1110 | |
Kojto | 93:e188a91d3eaa | 1111 | #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ |
Kojto | 93:e188a91d3eaa | 1112 | #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
Kojto | 93:e188a91d3eaa | 1113 | |
Kojto | 93:e188a91d3eaa | 1114 | #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ |
Kojto | 93:e188a91d3eaa | 1115 | #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
Kojto | 93:e188a91d3eaa | 1116 | |
Kojto | 93:e188a91d3eaa | 1117 | #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ |
Kojto | 93:e188a91d3eaa | 1118 | #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ |
Kojto | 93:e188a91d3eaa | 1119 | |
Kojto | 93:e188a91d3eaa | 1120 | /*@} end of group CMSIS_MPU */ |
Kojto | 93:e188a91d3eaa | 1121 | #endif |
Kojto | 93:e188a91d3eaa | 1122 | |
Kojto | 93:e188a91d3eaa | 1123 | |
Kojto | 93:e188a91d3eaa | 1124 | /** \ingroup CMSIS_core_register |
Kojto | 93:e188a91d3eaa | 1125 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
Kojto | 93:e188a91d3eaa | 1126 | \brief Type definitions for the Core Debug Registers |
Kojto | 93:e188a91d3eaa | 1127 | @{ |
Kojto | 93:e188a91d3eaa | 1128 | */ |
Kojto | 93:e188a91d3eaa | 1129 | |
Kojto | 93:e188a91d3eaa | 1130 | /** \brief Structure type to access the Core Debug Register (CoreDebug). |
Kojto | 93:e188a91d3eaa | 1131 | */ |
Kojto | 93:e188a91d3eaa | 1132 | typedef struct |
Kojto | 93:e188a91d3eaa | 1133 | { |
Kojto | 93:e188a91d3eaa | 1134 | __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ |
Kojto | 93:e188a91d3eaa | 1135 | __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ |
Kojto | 93:e188a91d3eaa | 1136 | __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ |
Kojto | 93:e188a91d3eaa | 1137 | __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ |
Kojto | 93:e188a91d3eaa | 1138 | } CoreDebug_Type; |
Kojto | 93:e188a91d3eaa | 1139 | |
Kojto | 93:e188a91d3eaa | 1140 | /* Debug Halting Control and Status Register */ |
Kojto | 93:e188a91d3eaa | 1141 | #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ |
Kojto | 93:e188a91d3eaa | 1142 | #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ |
Kojto | 93:e188a91d3eaa | 1143 | |
Kojto | 93:e188a91d3eaa | 1144 | #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ |
Kojto | 93:e188a91d3eaa | 1145 | #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ |
Kojto | 93:e188a91d3eaa | 1146 | |
Kojto | 93:e188a91d3eaa | 1147 | #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ |
Kojto | 93:e188a91d3eaa | 1148 | #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ |
Kojto | 93:e188a91d3eaa | 1149 | |
Kojto | 93:e188a91d3eaa | 1150 | #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ |
Kojto | 93:e188a91d3eaa | 1151 | #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ |
Kojto | 93:e188a91d3eaa | 1152 | |
Kojto | 93:e188a91d3eaa | 1153 | #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ |
Kojto | 93:e188a91d3eaa | 1154 | #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ |
Kojto | 93:e188a91d3eaa | 1155 | |
Kojto | 93:e188a91d3eaa | 1156 | #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ |
Kojto | 93:e188a91d3eaa | 1157 | #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ |
Kojto | 93:e188a91d3eaa | 1158 | |
Kojto | 93:e188a91d3eaa | 1159 | #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ |
Kojto | 93:e188a91d3eaa | 1160 | #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ |
Kojto | 93:e188a91d3eaa | 1161 | |
Kojto | 93:e188a91d3eaa | 1162 | #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ |
Kojto | 93:e188a91d3eaa | 1163 | #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ |
Kojto | 93:e188a91d3eaa | 1164 | |
Kojto | 93:e188a91d3eaa | 1165 | #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ |
Kojto | 93:e188a91d3eaa | 1166 | #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ |
Kojto | 93:e188a91d3eaa | 1167 | |
Kojto | 93:e188a91d3eaa | 1168 | #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ |
Kojto | 93:e188a91d3eaa | 1169 | #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ |
Kojto | 93:e188a91d3eaa | 1170 | |
Kojto | 93:e188a91d3eaa | 1171 | #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ |
Kojto | 93:e188a91d3eaa | 1172 | #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ |
Kojto | 93:e188a91d3eaa | 1173 | |
Kojto | 93:e188a91d3eaa | 1174 | #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ |
Kojto | 93:e188a91d3eaa | 1175 | #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ |
Kojto | 93:e188a91d3eaa | 1176 | |
Kojto | 93:e188a91d3eaa | 1177 | /* Debug Core Register Selector Register */ |
Kojto | 93:e188a91d3eaa | 1178 | #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ |
Kojto | 93:e188a91d3eaa | 1179 | #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ |
Kojto | 93:e188a91d3eaa | 1180 | |
Kojto | 93:e188a91d3eaa | 1181 | #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ |
Kojto | 93:e188a91d3eaa | 1182 | #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ |
Kojto | 93:e188a91d3eaa | 1183 | |
Kojto | 93:e188a91d3eaa | 1184 | /* Debug Exception and Monitor Control Register */ |
Kojto | 93:e188a91d3eaa | 1185 | #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ |
Kojto | 93:e188a91d3eaa | 1186 | #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ |
Kojto | 93:e188a91d3eaa | 1187 | |
Kojto | 93:e188a91d3eaa | 1188 | #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ |
Kojto | 93:e188a91d3eaa | 1189 | #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ |
Kojto | 93:e188a91d3eaa | 1190 | |
Kojto | 93:e188a91d3eaa | 1191 | #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ |
Kojto | 93:e188a91d3eaa | 1192 | #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ |
Kojto | 93:e188a91d3eaa | 1193 | |
Kojto | 93:e188a91d3eaa | 1194 | #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ |
Kojto | 93:e188a91d3eaa | 1195 | #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ |
Kojto | 93:e188a91d3eaa | 1196 | |
Kojto | 93:e188a91d3eaa | 1197 | #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ |
Kojto | 93:e188a91d3eaa | 1198 | #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ |
Kojto | 93:e188a91d3eaa | 1199 | |
Kojto | 93:e188a91d3eaa | 1200 | #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ |
Kojto | 93:e188a91d3eaa | 1201 | #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ |
Kojto | 93:e188a91d3eaa | 1202 | |
Kojto | 93:e188a91d3eaa | 1203 | #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ |
Kojto | 93:e188a91d3eaa | 1204 | #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ |
Kojto | 93:e188a91d3eaa | 1205 | |
Kojto | 93:e188a91d3eaa | 1206 | #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ |
Kojto | 93:e188a91d3eaa | 1207 | #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ |
Kojto | 93:e188a91d3eaa | 1208 | |
Kojto | 93:e188a91d3eaa | 1209 | #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ |
Kojto | 93:e188a91d3eaa | 1210 | #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ |
Kojto | 93:e188a91d3eaa | 1211 | |
Kojto | 93:e188a91d3eaa | 1212 | #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ |
Kojto | 93:e188a91d3eaa | 1213 | #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ |
Kojto | 93:e188a91d3eaa | 1214 | |
Kojto | 93:e188a91d3eaa | 1215 | #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ |
Kojto | 93:e188a91d3eaa | 1216 | #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ |
Kojto | 93:e188a91d3eaa | 1217 | |
Kojto | 93:e188a91d3eaa | 1218 | #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ |
Kojto | 93:e188a91d3eaa | 1219 | #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ |
Kojto | 93:e188a91d3eaa | 1220 | |
Kojto | 93:e188a91d3eaa | 1221 | #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ |
Kojto | 93:e188a91d3eaa | 1222 | #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ |
Kojto | 93:e188a91d3eaa | 1223 | |
Kojto | 93:e188a91d3eaa | 1224 | /*@} end of group CMSIS_CoreDebug */ |
Kojto | 93:e188a91d3eaa | 1225 | |
Kojto | 93:e188a91d3eaa | 1226 | |
Kojto | 93:e188a91d3eaa | 1227 | /** \ingroup CMSIS_core_register |
Kojto | 93:e188a91d3eaa | 1228 | \defgroup CMSIS_core_base Core Definitions |
Kojto | 93:e188a91d3eaa | 1229 | \brief Definitions for base addresses, unions, and structures. |
Kojto | 93:e188a91d3eaa | 1230 | @{ |
Kojto | 93:e188a91d3eaa | 1231 | */ |
Kojto | 93:e188a91d3eaa | 1232 | |
Kojto | 93:e188a91d3eaa | 1233 | /* Memory mapping of Cortex-M3 Hardware */ |
Kojto | 93:e188a91d3eaa | 1234 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
Kojto | 93:e188a91d3eaa | 1235 | #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ |
Kojto | 93:e188a91d3eaa | 1236 | #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ |
Kojto | 93:e188a91d3eaa | 1237 | #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ |
Kojto | 93:e188a91d3eaa | 1238 | #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ |
Kojto | 93:e188a91d3eaa | 1239 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
Kojto | 93:e188a91d3eaa | 1240 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
Kojto | 93:e188a91d3eaa | 1241 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
Kojto | 93:e188a91d3eaa | 1242 | |
Kojto | 93:e188a91d3eaa | 1243 | #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ |
Kojto | 93:e188a91d3eaa | 1244 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
Kojto | 93:e188a91d3eaa | 1245 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
Kojto | 93:e188a91d3eaa | 1246 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
Kojto | 93:e188a91d3eaa | 1247 | #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ |
Kojto | 93:e188a91d3eaa | 1248 | #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ |
Kojto | 93:e188a91d3eaa | 1249 | #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ |
Kojto | 93:e188a91d3eaa | 1250 | #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ |
Kojto | 93:e188a91d3eaa | 1251 | |
Kojto | 93:e188a91d3eaa | 1252 | #if (__MPU_PRESENT == 1) |
Kojto | 93:e188a91d3eaa | 1253 | #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
Kojto | 93:e188a91d3eaa | 1254 | #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
Kojto | 93:e188a91d3eaa | 1255 | #endif |
Kojto | 93:e188a91d3eaa | 1256 | |
Kojto | 93:e188a91d3eaa | 1257 | /*@} */ |
Kojto | 93:e188a91d3eaa | 1258 | |
Kojto | 93:e188a91d3eaa | 1259 | |
Kojto | 93:e188a91d3eaa | 1260 | |
Kojto | 93:e188a91d3eaa | 1261 | /******************************************************************************* |
Kojto | 93:e188a91d3eaa | 1262 | * Hardware Abstraction Layer |
Kojto | 93:e188a91d3eaa | 1263 | Core Function Interface contains: |
Kojto | 93:e188a91d3eaa | 1264 | - Core NVIC Functions |
Kojto | 93:e188a91d3eaa | 1265 | - Core SysTick Functions |
Kojto | 93:e188a91d3eaa | 1266 | - Core Debug Functions |
Kojto | 93:e188a91d3eaa | 1267 | - Core Register Access Functions |
Kojto | 93:e188a91d3eaa | 1268 | ******************************************************************************/ |
Kojto | 93:e188a91d3eaa | 1269 | /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
Kojto | 93:e188a91d3eaa | 1270 | */ |
Kojto | 93:e188a91d3eaa | 1271 | |
Kojto | 93:e188a91d3eaa | 1272 | |
Kojto | 93:e188a91d3eaa | 1273 | |
Kojto | 93:e188a91d3eaa | 1274 | /* ########################## NVIC functions #################################### */ |
Kojto | 93:e188a91d3eaa | 1275 | /** \ingroup CMSIS_Core_FunctionInterface |
Kojto | 93:e188a91d3eaa | 1276 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
Kojto | 93:e188a91d3eaa | 1277 | \brief Functions that manage interrupts and exceptions via the NVIC. |
Kojto | 93:e188a91d3eaa | 1278 | @{ |
Kojto | 93:e188a91d3eaa | 1279 | */ |
Kojto | 93:e188a91d3eaa | 1280 | |
Kojto | 93:e188a91d3eaa | 1281 | /** \brief Set Priority Grouping |
Kojto | 93:e188a91d3eaa | 1282 | |
Kojto | 93:e188a91d3eaa | 1283 | The function sets the priority grouping field using the required unlock sequence. |
Kojto | 93:e188a91d3eaa | 1284 | The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. |
Kojto | 93:e188a91d3eaa | 1285 | Only values from 0..7 are used. |
Kojto | 93:e188a91d3eaa | 1286 | In case of a conflict between priority grouping and available |
Kojto | 93:e188a91d3eaa | 1287 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
Kojto | 93:e188a91d3eaa | 1288 | |
Kojto | 93:e188a91d3eaa | 1289 | \param [in] PriorityGroup Priority grouping field. |
Kojto | 93:e188a91d3eaa | 1290 | */ |
Kojto | 93:e188a91d3eaa | 1291 | __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) |
Kojto | 93:e188a91d3eaa | 1292 | { |
Kojto | 93:e188a91d3eaa | 1293 | uint32_t reg_value; |
Kojto | 93:e188a91d3eaa | 1294 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ |
Kojto | 93:e188a91d3eaa | 1295 | |
Kojto | 93:e188a91d3eaa | 1296 | reg_value = SCB->AIRCR; /* read old register configuration */ |
Kojto | 93:e188a91d3eaa | 1297 | reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ |
Kojto | 93:e188a91d3eaa | 1298 | reg_value = (reg_value | |
Kojto | 93:e188a91d3eaa | 1299 | ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | |
Kojto | 93:e188a91d3eaa | 1300 | (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ |
Kojto | 93:e188a91d3eaa | 1301 | SCB->AIRCR = reg_value; |
Kojto | 93:e188a91d3eaa | 1302 | } |
Kojto | 93:e188a91d3eaa | 1303 | |
Kojto | 93:e188a91d3eaa | 1304 | |
Kojto | 93:e188a91d3eaa | 1305 | /** \brief Get Priority Grouping |
Kojto | 93:e188a91d3eaa | 1306 | |
Kojto | 93:e188a91d3eaa | 1307 | The function reads the priority grouping field from the NVIC Interrupt Controller. |
Kojto | 93:e188a91d3eaa | 1308 | |
Kojto | 93:e188a91d3eaa | 1309 | \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). |
Kojto | 93:e188a91d3eaa | 1310 | */ |
Kojto | 93:e188a91d3eaa | 1311 | __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) |
Kojto | 93:e188a91d3eaa | 1312 | { |
Kojto | 93:e188a91d3eaa | 1313 | return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ |
Kojto | 93:e188a91d3eaa | 1314 | } |
Kojto | 93:e188a91d3eaa | 1315 | |
Kojto | 93:e188a91d3eaa | 1316 | |
Kojto | 93:e188a91d3eaa | 1317 | /** \brief Enable External Interrupt |
Kojto | 93:e188a91d3eaa | 1318 | |
Kojto | 93:e188a91d3eaa | 1319 | The function enables a device-specific interrupt in the NVIC interrupt controller. |
Kojto | 93:e188a91d3eaa | 1320 | |
Kojto | 93:e188a91d3eaa | 1321 | \param [in] IRQn External interrupt number. Value cannot be negative. |
Kojto | 93:e188a91d3eaa | 1322 | */ |
Kojto | 93:e188a91d3eaa | 1323 | __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
Kojto | 93:e188a91d3eaa | 1324 | { |
Kojto | 93:e188a91d3eaa | 1325 | NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ |
Kojto | 93:e188a91d3eaa | 1326 | } |
Kojto | 93:e188a91d3eaa | 1327 | |
Kojto | 93:e188a91d3eaa | 1328 | |
Kojto | 93:e188a91d3eaa | 1329 | /** \brief Disable External Interrupt |
Kojto | 93:e188a91d3eaa | 1330 | |
Kojto | 93:e188a91d3eaa | 1331 | The function disables a device-specific interrupt in the NVIC interrupt controller. |
Kojto | 93:e188a91d3eaa | 1332 | |
Kojto | 93:e188a91d3eaa | 1333 | \param [in] IRQn External interrupt number. Value cannot be negative. |
Kojto | 93:e188a91d3eaa | 1334 | */ |
Kojto | 93:e188a91d3eaa | 1335 | __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
Kojto | 93:e188a91d3eaa | 1336 | { |
Kojto | 93:e188a91d3eaa | 1337 | NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ |
Kojto | 93:e188a91d3eaa | 1338 | } |
Kojto | 93:e188a91d3eaa | 1339 | |
Kojto | 93:e188a91d3eaa | 1340 | |
Kojto | 93:e188a91d3eaa | 1341 | /** \brief Get Pending Interrupt |
Kojto | 93:e188a91d3eaa | 1342 | |
Kojto | 93:e188a91d3eaa | 1343 | The function reads the pending register in the NVIC and returns the pending bit |
Kojto | 93:e188a91d3eaa | 1344 | for the specified interrupt. |
Kojto | 93:e188a91d3eaa | 1345 | |
Kojto | 93:e188a91d3eaa | 1346 | \param [in] IRQn Interrupt number. |
Kojto | 93:e188a91d3eaa | 1347 | |
Kojto | 93:e188a91d3eaa | 1348 | \return 0 Interrupt status is not pending. |
Kojto | 93:e188a91d3eaa | 1349 | \return 1 Interrupt status is pending. |
Kojto | 93:e188a91d3eaa | 1350 | */ |
Kojto | 93:e188a91d3eaa | 1351 | __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
Kojto | 93:e188a91d3eaa | 1352 | { |
Kojto | 93:e188a91d3eaa | 1353 | return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ |
Kojto | 93:e188a91d3eaa | 1354 | } |
Kojto | 93:e188a91d3eaa | 1355 | |
Kojto | 93:e188a91d3eaa | 1356 | |
Kojto | 93:e188a91d3eaa | 1357 | /** \brief Set Pending Interrupt |
Kojto | 93:e188a91d3eaa | 1358 | |
Kojto | 93:e188a91d3eaa | 1359 | The function sets the pending bit of an external interrupt. |
Kojto | 93:e188a91d3eaa | 1360 | |
Kojto | 93:e188a91d3eaa | 1361 | \param [in] IRQn Interrupt number. Value cannot be negative. |
Kojto | 93:e188a91d3eaa | 1362 | */ |
Kojto | 93:e188a91d3eaa | 1363 | __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
Kojto | 93:e188a91d3eaa | 1364 | { |
Kojto | 93:e188a91d3eaa | 1365 | NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ |
Kojto | 93:e188a91d3eaa | 1366 | } |
Kojto | 93:e188a91d3eaa | 1367 | |
Kojto | 93:e188a91d3eaa | 1368 | |
Kojto | 93:e188a91d3eaa | 1369 | /** \brief Clear Pending Interrupt |
Kojto | 93:e188a91d3eaa | 1370 | |
Kojto | 93:e188a91d3eaa | 1371 | The function clears the pending bit of an external interrupt. |
Kojto | 93:e188a91d3eaa | 1372 | |
Kojto | 93:e188a91d3eaa | 1373 | \param [in] IRQn External interrupt number. Value cannot be negative. |
Kojto | 93:e188a91d3eaa | 1374 | */ |
Kojto | 93:e188a91d3eaa | 1375 | __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
Kojto | 93:e188a91d3eaa | 1376 | { |
Kojto | 93:e188a91d3eaa | 1377 | NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ |
Kojto | 93:e188a91d3eaa | 1378 | } |
Kojto | 93:e188a91d3eaa | 1379 | |
Kojto | 93:e188a91d3eaa | 1380 | |
Kojto | 93:e188a91d3eaa | 1381 | /** \brief Get Active Interrupt |
Kojto | 93:e188a91d3eaa | 1382 | |
Kojto | 93:e188a91d3eaa | 1383 | The function reads the active register in NVIC and returns the active bit. |
Kojto | 93:e188a91d3eaa | 1384 | |
Kojto | 93:e188a91d3eaa | 1385 | \param [in] IRQn Interrupt number. |
Kojto | 93:e188a91d3eaa | 1386 | |
Kojto | 93:e188a91d3eaa | 1387 | \return 0 Interrupt status is not active. |
Kojto | 93:e188a91d3eaa | 1388 | \return 1 Interrupt status is active. |
Kojto | 93:e188a91d3eaa | 1389 | */ |
Kojto | 93:e188a91d3eaa | 1390 | __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) |
Kojto | 93:e188a91d3eaa | 1391 | { |
Kojto | 93:e188a91d3eaa | 1392 | return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ |
Kojto | 93:e188a91d3eaa | 1393 | } |
Kojto | 93:e188a91d3eaa | 1394 | |
Kojto | 93:e188a91d3eaa | 1395 | |
Kojto | 93:e188a91d3eaa | 1396 | /** \brief Set Interrupt Priority |
Kojto | 93:e188a91d3eaa | 1397 | |
Kojto | 93:e188a91d3eaa | 1398 | The function sets the priority of an interrupt. |
Kojto | 93:e188a91d3eaa | 1399 | |
Kojto | 93:e188a91d3eaa | 1400 | \note The priority cannot be set for every core interrupt. |
Kojto | 93:e188a91d3eaa | 1401 | |
Kojto | 93:e188a91d3eaa | 1402 | \param [in] IRQn Interrupt number. |
Kojto | 93:e188a91d3eaa | 1403 | \param [in] priority Priority to set. |
Kojto | 93:e188a91d3eaa | 1404 | */ |
Kojto | 93:e188a91d3eaa | 1405 | __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
Kojto | 93:e188a91d3eaa | 1406 | { |
Kojto | 93:e188a91d3eaa | 1407 | if(IRQn < 0) { |
Kojto | 93:e188a91d3eaa | 1408 | SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ |
Kojto | 93:e188a91d3eaa | 1409 | else { |
Kojto | 93:e188a91d3eaa | 1410 | NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ |
Kojto | 93:e188a91d3eaa | 1411 | } |
Kojto | 93:e188a91d3eaa | 1412 | |
Kojto | 93:e188a91d3eaa | 1413 | |
Kojto | 93:e188a91d3eaa | 1414 | /** \brief Get Interrupt Priority |
Kojto | 93:e188a91d3eaa | 1415 | |
Kojto | 93:e188a91d3eaa | 1416 | The function reads the priority of an interrupt. The interrupt |
Kojto | 93:e188a91d3eaa | 1417 | number can be positive to specify an external (device specific) |
Kojto | 93:e188a91d3eaa | 1418 | interrupt, or negative to specify an internal (core) interrupt. |
Kojto | 93:e188a91d3eaa | 1419 | |
Kojto | 93:e188a91d3eaa | 1420 | |
Kojto | 93:e188a91d3eaa | 1421 | \param [in] IRQn Interrupt number. |
Kojto | 93:e188a91d3eaa | 1422 | \return Interrupt Priority. Value is aligned automatically to the implemented |
Kojto | 93:e188a91d3eaa | 1423 | priority bits of the microcontroller. |
Kojto | 93:e188a91d3eaa | 1424 | */ |
Kojto | 93:e188a91d3eaa | 1425 | __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
Kojto | 93:e188a91d3eaa | 1426 | { |
Kojto | 93:e188a91d3eaa | 1427 | |
Kojto | 93:e188a91d3eaa | 1428 | if(IRQn < 0) { |
Kojto | 93:e188a91d3eaa | 1429 | return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ |
Kojto | 93:e188a91d3eaa | 1430 | else { |
Kojto | 93:e188a91d3eaa | 1431 | return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ |
Kojto | 93:e188a91d3eaa | 1432 | } |
Kojto | 93:e188a91d3eaa | 1433 | |
Kojto | 93:e188a91d3eaa | 1434 | |
Kojto | 93:e188a91d3eaa | 1435 | /** \brief Encode Priority |
Kojto | 93:e188a91d3eaa | 1436 | |
Kojto | 93:e188a91d3eaa | 1437 | The function encodes the priority for an interrupt with the given priority group, |
Kojto | 93:e188a91d3eaa | 1438 | preemptive priority value, and subpriority value. |
Kojto | 93:e188a91d3eaa | 1439 | In case of a conflict between priority grouping and available |
Kojto | 93:e188a91d3eaa | 1440 | priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. |
Kojto | 93:e188a91d3eaa | 1441 | |
Kojto | 93:e188a91d3eaa | 1442 | \param [in] PriorityGroup Used priority group. |
Kojto | 93:e188a91d3eaa | 1443 | \param [in] PreemptPriority Preemptive priority value (starting from 0). |
Kojto | 93:e188a91d3eaa | 1444 | \param [in] SubPriority Subpriority value (starting from 0). |
Kojto | 93:e188a91d3eaa | 1445 | \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). |
Kojto | 93:e188a91d3eaa | 1446 | */ |
Kojto | 93:e188a91d3eaa | 1447 | __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) |
Kojto | 93:e188a91d3eaa | 1448 | { |
Kojto | 93:e188a91d3eaa | 1449 | uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ |
Kojto | 93:e188a91d3eaa | 1450 | uint32_t PreemptPriorityBits; |
Kojto | 93:e188a91d3eaa | 1451 | uint32_t SubPriorityBits; |
Kojto | 93:e188a91d3eaa | 1452 | |
Kojto | 93:e188a91d3eaa | 1453 | PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; |
Kojto | 93:e188a91d3eaa | 1454 | SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; |
Kojto | 93:e188a91d3eaa | 1455 | |
Kojto | 93:e188a91d3eaa | 1456 | return ( |
Kojto | 93:e188a91d3eaa | 1457 | ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | |
Kojto | 93:e188a91d3eaa | 1458 | ((SubPriority & ((1 << (SubPriorityBits )) - 1))) |
Kojto | 93:e188a91d3eaa | 1459 | ); |
Kojto | 93:e188a91d3eaa | 1460 | } |
Kojto | 93:e188a91d3eaa | 1461 | |
Kojto | 93:e188a91d3eaa | 1462 | |
Kojto | 93:e188a91d3eaa | 1463 | /** \brief Decode Priority |
Kojto | 93:e188a91d3eaa | 1464 | |
Kojto | 93:e188a91d3eaa | 1465 | The function decodes an interrupt priority value with a given priority group to |
Kojto | 93:e188a91d3eaa | 1466 | preemptive priority value and subpriority value. |
Kojto | 93:e188a91d3eaa | 1467 | In case of a conflict between priority grouping and available |
Kojto | 93:e188a91d3eaa | 1468 | priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. |
Kojto | 93:e188a91d3eaa | 1469 | |
Kojto | 93:e188a91d3eaa | 1470 | \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). |
Kojto | 93:e188a91d3eaa | 1471 | \param [in] PriorityGroup Used priority group. |
Kojto | 93:e188a91d3eaa | 1472 | \param [out] pPreemptPriority Preemptive priority value (starting from 0). |
Kojto | 93:e188a91d3eaa | 1473 | \param [out] pSubPriority Subpriority value (starting from 0). |
Kojto | 93:e188a91d3eaa | 1474 | */ |
Kojto | 93:e188a91d3eaa | 1475 | __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) |
Kojto | 93:e188a91d3eaa | 1476 | { |
Kojto | 93:e188a91d3eaa | 1477 | uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ |
Kojto | 93:e188a91d3eaa | 1478 | uint32_t PreemptPriorityBits; |
Kojto | 93:e188a91d3eaa | 1479 | uint32_t SubPriorityBits; |
Kojto | 93:e188a91d3eaa | 1480 | |
Kojto | 93:e188a91d3eaa | 1481 | PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; |
Kojto | 93:e188a91d3eaa | 1482 | SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; |
Kojto | 93:e188a91d3eaa | 1483 | |
Kojto | 93:e188a91d3eaa | 1484 | *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); |
Kojto | 93:e188a91d3eaa | 1485 | *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); |
Kojto | 93:e188a91d3eaa | 1486 | } |
Kojto | 93:e188a91d3eaa | 1487 | |
Kojto | 93:e188a91d3eaa | 1488 | |
Kojto | 93:e188a91d3eaa | 1489 | /** \brief System Reset |
Kojto | 93:e188a91d3eaa | 1490 | |
Kojto | 93:e188a91d3eaa | 1491 | The function initiates a system reset request to reset the MCU. |
Kojto | 93:e188a91d3eaa | 1492 | */ |
Kojto | 93:e188a91d3eaa | 1493 | __STATIC_INLINE void NVIC_SystemReset(void) |
Kojto | 93:e188a91d3eaa | 1494 | { |
Kojto | 93:e188a91d3eaa | 1495 | __DSB(); /* Ensure all outstanding memory accesses included |
Kojto | 93:e188a91d3eaa | 1496 | buffered write are completed before reset */ |
Kojto | 93:e188a91d3eaa | 1497 | SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | |
Kojto | 93:e188a91d3eaa | 1498 | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | |
Kojto | 93:e188a91d3eaa | 1499 | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ |
Kojto | 93:e188a91d3eaa | 1500 | __DSB(); /* Ensure completion of memory access */ |
Kojto | 93:e188a91d3eaa | 1501 | while(1); /* wait until reset */ |
Kojto | 93:e188a91d3eaa | 1502 | } |
Kojto | 93:e188a91d3eaa | 1503 | |
Kojto | 93:e188a91d3eaa | 1504 | /*@} end of CMSIS_Core_NVICFunctions */ |
Kojto | 93:e188a91d3eaa | 1505 | |
Kojto | 93:e188a91d3eaa | 1506 | |
Kojto | 93:e188a91d3eaa | 1507 | |
Kojto | 93:e188a91d3eaa | 1508 | /* ################################## SysTick function ############################################ */ |
Kojto | 93:e188a91d3eaa | 1509 | /** \ingroup CMSIS_Core_FunctionInterface |
Kojto | 93:e188a91d3eaa | 1510 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
Kojto | 93:e188a91d3eaa | 1511 | \brief Functions that configure the System. |
Kojto | 93:e188a91d3eaa | 1512 | @{ |
Kojto | 93:e188a91d3eaa | 1513 | */ |
Kojto | 93:e188a91d3eaa | 1514 | |
Kojto | 93:e188a91d3eaa | 1515 | #if (__Vendor_SysTickConfig == 0) |
Kojto | 93:e188a91d3eaa | 1516 | |
Kojto | 93:e188a91d3eaa | 1517 | /** \brief System Tick Configuration |
Kojto | 93:e188a91d3eaa | 1518 | |
Kojto | 93:e188a91d3eaa | 1519 | The function initializes the System Timer and its interrupt, and starts the System Tick Timer. |
Kojto | 93:e188a91d3eaa | 1520 | Counter is in free running mode to generate periodic interrupts. |
Kojto | 93:e188a91d3eaa | 1521 | |
Kojto | 93:e188a91d3eaa | 1522 | \param [in] ticks Number of ticks between two interrupts. |
Kojto | 93:e188a91d3eaa | 1523 | |
Kojto | 93:e188a91d3eaa | 1524 | \return 0 Function succeeded. |
Kojto | 93:e188a91d3eaa | 1525 | \return 1 Function failed. |
Kojto | 93:e188a91d3eaa | 1526 | |
Kojto | 93:e188a91d3eaa | 1527 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
Kojto | 93:e188a91d3eaa | 1528 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
Kojto | 93:e188a91d3eaa | 1529 | must contain a vendor-specific implementation of this function. |
Kojto | 93:e188a91d3eaa | 1530 | |
Kojto | 93:e188a91d3eaa | 1531 | */ |
Kojto | 93:e188a91d3eaa | 1532 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
Kojto | 93:e188a91d3eaa | 1533 | { |
Kojto | 93:e188a91d3eaa | 1534 | if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ |
Kojto | 93:e188a91d3eaa | 1535 | |
Kojto | 93:e188a91d3eaa | 1536 | SysTick->LOAD = ticks - 1; /* set reload register */ |
Kojto | 93:e188a91d3eaa | 1537 | NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ |
Kojto | 93:e188a91d3eaa | 1538 | SysTick->VAL = 0; /* Load the SysTick Counter Value */ |
Kojto | 93:e188a91d3eaa | 1539 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
Kojto | 93:e188a91d3eaa | 1540 | SysTick_CTRL_TICKINT_Msk | |
Kojto | 93:e188a91d3eaa | 1541 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
Kojto | 93:e188a91d3eaa | 1542 | return (0); /* Function successful */ |
Kojto | 93:e188a91d3eaa | 1543 | } |
Kojto | 93:e188a91d3eaa | 1544 | |
Kojto | 93:e188a91d3eaa | 1545 | #endif |
Kojto | 93:e188a91d3eaa | 1546 | |
Kojto | 93:e188a91d3eaa | 1547 | /*@} end of CMSIS_Core_SysTickFunctions */ |
Kojto | 93:e188a91d3eaa | 1548 | |
Kojto | 93:e188a91d3eaa | 1549 | |
Kojto | 93:e188a91d3eaa | 1550 | |
Kojto | 93:e188a91d3eaa | 1551 | /* ##################################### Debug In/Output function ########################################### */ |
Kojto | 93:e188a91d3eaa | 1552 | /** \ingroup CMSIS_Core_FunctionInterface |
Kojto | 93:e188a91d3eaa | 1553 | \defgroup CMSIS_core_DebugFunctions ITM Functions |
Kojto | 93:e188a91d3eaa | 1554 | \brief Functions that access the ITM debug interface. |
Kojto | 93:e188a91d3eaa | 1555 | @{ |
Kojto | 93:e188a91d3eaa | 1556 | */ |
Kojto | 93:e188a91d3eaa | 1557 | |
Kojto | 93:e188a91d3eaa | 1558 | extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ |
Kojto | 93:e188a91d3eaa | 1559 | #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ |
Kojto | 93:e188a91d3eaa | 1560 | |
Kojto | 93:e188a91d3eaa | 1561 | |
Kojto | 93:e188a91d3eaa | 1562 | /** \brief ITM Send Character |
Kojto | 93:e188a91d3eaa | 1563 | |
Kojto | 93:e188a91d3eaa | 1564 | The function transmits a character via the ITM channel 0, and |
Kojto | 93:e188a91d3eaa | 1565 | \li Just returns when no debugger is connected that has booked the output. |
Kojto | 93:e188a91d3eaa | 1566 | \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. |
Kojto | 93:e188a91d3eaa | 1567 | |
Kojto | 93:e188a91d3eaa | 1568 | \param [in] ch Character to transmit. |
Kojto | 93:e188a91d3eaa | 1569 | |
Kojto | 93:e188a91d3eaa | 1570 | \returns Character to transmit. |
Kojto | 93:e188a91d3eaa | 1571 | */ |
Kojto | 93:e188a91d3eaa | 1572 | __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) |
Kojto | 93:e188a91d3eaa | 1573 | { |
Kojto | 93:e188a91d3eaa | 1574 | if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ |
Kojto | 93:e188a91d3eaa | 1575 | (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ |
Kojto | 93:e188a91d3eaa | 1576 | { |
Kojto | 93:e188a91d3eaa | 1577 | while (ITM->PORT[0].u32 == 0); |
Kojto | 93:e188a91d3eaa | 1578 | ITM->PORT[0].u8 = (uint8_t) ch; |
Kojto | 93:e188a91d3eaa | 1579 | } |
Kojto | 93:e188a91d3eaa | 1580 | return (ch); |
Kojto | 93:e188a91d3eaa | 1581 | } |
Kojto | 93:e188a91d3eaa | 1582 | |
Kojto | 93:e188a91d3eaa | 1583 | |
Kojto | 93:e188a91d3eaa | 1584 | /** \brief ITM Receive Character |
Kojto | 93:e188a91d3eaa | 1585 | |
Kojto | 93:e188a91d3eaa | 1586 | The function inputs a character via the external variable \ref ITM_RxBuffer. |
Kojto | 93:e188a91d3eaa | 1587 | |
Kojto | 93:e188a91d3eaa | 1588 | \return Received character. |
Kojto | 93:e188a91d3eaa | 1589 | \return -1 No character pending. |
Kojto | 93:e188a91d3eaa | 1590 | */ |
Kojto | 93:e188a91d3eaa | 1591 | __STATIC_INLINE int32_t ITM_ReceiveChar (void) { |
Kojto | 93:e188a91d3eaa | 1592 | int32_t ch = -1; /* no character available */ |
Kojto | 93:e188a91d3eaa | 1593 | |
Kojto | 93:e188a91d3eaa | 1594 | if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { |
Kojto | 93:e188a91d3eaa | 1595 | ch = ITM_RxBuffer; |
Kojto | 93:e188a91d3eaa | 1596 | ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ |
Kojto | 93:e188a91d3eaa | 1597 | } |
Kojto | 93:e188a91d3eaa | 1598 | |
Kojto | 93:e188a91d3eaa | 1599 | return (ch); |
Kojto | 93:e188a91d3eaa | 1600 | } |
Kojto | 93:e188a91d3eaa | 1601 | |
Kojto | 93:e188a91d3eaa | 1602 | |
Kojto | 93:e188a91d3eaa | 1603 | /** \brief ITM Check Character |
Kojto | 93:e188a91d3eaa | 1604 | |
Kojto | 93:e188a91d3eaa | 1605 | The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. |
Kojto | 93:e188a91d3eaa | 1606 | |
Kojto | 93:e188a91d3eaa | 1607 | \return 0 No character available. |
Kojto | 93:e188a91d3eaa | 1608 | \return 1 Character available. |
Kojto | 93:e188a91d3eaa | 1609 | */ |
Kojto | 93:e188a91d3eaa | 1610 | __STATIC_INLINE int32_t ITM_CheckChar (void) { |
Kojto | 93:e188a91d3eaa | 1611 | |
Kojto | 93:e188a91d3eaa | 1612 | if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { |
Kojto | 93:e188a91d3eaa | 1613 | return (0); /* no character available */ |
Kojto | 93:e188a91d3eaa | 1614 | } else { |
Kojto | 93:e188a91d3eaa | 1615 | return (1); /* character available */ |
Kojto | 93:e188a91d3eaa | 1616 | } |
Kojto | 93:e188a91d3eaa | 1617 | } |
Kojto | 93:e188a91d3eaa | 1618 | |
Kojto | 93:e188a91d3eaa | 1619 | /*@} end of CMSIS_core_DebugFunctions */ |
Kojto | 93:e188a91d3eaa | 1620 | |
Kojto | 93:e188a91d3eaa | 1621 | #endif /* __CORE_CM3_H_DEPENDANT */ |
Kojto | 93:e188a91d3eaa | 1622 | |
Kojto | 93:e188a91d3eaa | 1623 | #endif /* __CMSIS_GENERIC */ |
Kojto | 93:e188a91d3eaa | 1624 | |
Kojto | 93:e188a91d3eaa | 1625 | #ifdef __cplusplus |
Kojto | 93:e188a91d3eaa | 1626 | } |
Kojto | 93:e188a91d3eaa | 1627 | #endif |