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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_wdog.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:
Kojto
Date:
Wed Aug 05 13:16:35 2015 +0100
Revision:
104:b9ad9a133dc7
Parent:
90:cb3d968589d8 
Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /*
Kojto 90:cb3d968589d8 2 ** ###################################################################
Kojto 90:cb3d968589d8 3 ** Compilers: Keil ARM C/C++ Compiler
Kojto 90:cb3d968589d8 4 ** Freescale C/C++ for Embedded ARM
Kojto 90:cb3d968589d8 5 ** GNU C Compiler
Kojto 90:cb3d968589d8 6 ** IAR ANSI C/C++ Compiler for ARM
Kojto 90:cb3d968589d8 7 **
Kojto 90:cb3d968589d8 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto 90:cb3d968589d8 9 ** Version: rev. 2.5, 2014-02-10
Kojto 90:cb3d968589d8 10 ** Build: b140604
Kojto 90:cb3d968589d8 11 **
Kojto 90:cb3d968589d8 12 ** Abstract:
Kojto 90:cb3d968589d8 13 ** Extension to the CMSIS register access layer header.
Kojto 90:cb3d968589d8 14 **
Kojto 90:cb3d968589d8 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto 90:cb3d968589d8 16 ** All rights reserved.
Kojto 90:cb3d968589d8 17 **
Kojto 90:cb3d968589d8 18 ** Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 19 ** are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 20 **
Kojto 90:cb3d968589d8 21 ** o Redistributions of source code must retain the above copyright notice, this list
Kojto 90:cb3d968589d8 22 ** of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 23 **
Kojto 90:cb3d968589d8 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto 90:cb3d968589d8 25 ** list of conditions and the following disclaimer in the documentation and/or
Kojto 90:cb3d968589d8 26 ** other materials provided with the distribution.
Kojto 90:cb3d968589d8 27 **
Kojto 90:cb3d968589d8 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto 90:cb3d968589d8 29 ** contributors may be used to endorse or promote products derived from this
Kojto 90:cb3d968589d8 30 ** software without specific prior written permission.
Kojto 90:cb3d968589d8 31 **
Kojto 90:cb3d968589d8 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 90:cb3d968589d8 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 90:cb3d968589d8 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 90:cb3d968589d8 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 90:cb3d968589d8 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 90:cb3d968589d8 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 90:cb3d968589d8 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 90:cb3d968589d8 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 90:cb3d968589d8 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 42 **
Kojto 90:cb3d968589d8 43 ** http: www.freescale.com
Kojto 90:cb3d968589d8 44 ** mail: support@freescale.com
Kojto 90:cb3d968589d8 45 **
Kojto 90:cb3d968589d8 46 ** Revisions:
Kojto 90:cb3d968589d8 47 ** - rev. 1.0 (2013-08-12)
Kojto 90:cb3d968589d8 48 ** Initial version.
Kojto 90:cb3d968589d8 49 ** - rev. 2.0 (2013-10-29)
Kojto 90:cb3d968589d8 50 ** Register accessor macros added to the memory map.
Kojto 90:cb3d968589d8 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto 90:cb3d968589d8 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto 90:cb3d968589d8 53 ** System initialization updated.
Kojto 90:cb3d968589d8 54 ** MCG - registers updated.
Kojto 90:cb3d968589d8 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto 90:cb3d968589d8 56 ** - rev. 2.1 (2013-10-30)
Kojto 90:cb3d968589d8 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto 90:cb3d968589d8 58 ** - rev. 2.2 (2013-12-09)
Kojto 90:cb3d968589d8 59 ** DMA - EARS register removed.
Kojto 90:cb3d968589d8 60 ** AIPS0, AIPS1 - MPRA register updated.
Kojto 90:cb3d968589d8 61 ** - rev. 2.3 (2014-01-24)
Kojto 90:cb3d968589d8 62 ** Update according to reference manual rev. 2
Kojto 90:cb3d968589d8 63 ** ENET, MCG, MCM, SIM, USB - registers updated
Kojto 90:cb3d968589d8 64 ** - rev. 2.4 (2014-02-10)
Kojto 90:cb3d968589d8 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 67 ** - rev. 2.5 (2014-02-10)
Kojto 90:cb3d968589d8 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto 90:cb3d968589d8 71 **
Kojto 90:cb3d968589d8 72 ** ###################################################################
Kojto 90:cb3d968589d8 73 */
Kojto 90:cb3d968589d8 74
Kojto 90:cb3d968589d8 75 /*
Kojto 90:cb3d968589d8 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto 90:cb3d968589d8 77 *
Kojto 90:cb3d968589d8 78 * This file was generated automatically and any changes may be lost.
Kojto 90:cb3d968589d8 79 */
Kojto 90:cb3d968589d8 80 #ifndef __HW_WDOG_REGISTERS_H__
Kojto 90:cb3d968589d8 81 #define __HW_WDOG_REGISTERS_H__
Kojto 90:cb3d968589d8 82
Kojto 90:cb3d968589d8 83 #include "MK64F12.h"
Kojto 90:cb3d968589d8 84 #include "fsl_bitaccess.h"
Kojto 90:cb3d968589d8 85
Kojto 90:cb3d968589d8 86 /*
Kojto 90:cb3d968589d8 87 * MK64F12 WDOG
Kojto 90:cb3d968589d8 88 *
Kojto 90:cb3d968589d8 89 * Generation 2008 Watchdog Timer
Kojto 90:cb3d968589d8 90 *
Kojto 90:cb3d968589d8 91 * Registers defined in this header file:
Kojto 90:cb3d968589d8 92 * - HW_WDOG_STCTRLH - Watchdog Status and Control Register High
Kojto 90:cb3d968589d8 93 * - HW_WDOG_STCTRLL - Watchdog Status and Control Register Low
Kojto 90:cb3d968589d8 94 * - HW_WDOG_TOVALH - Watchdog Time-out Value Register High
Kojto 90:cb3d968589d8 95 * - HW_WDOG_TOVALL - Watchdog Time-out Value Register Low
Kojto 90:cb3d968589d8 96 * - HW_WDOG_WINH - Watchdog Window Register High
Kojto 90:cb3d968589d8 97 * - HW_WDOG_WINL - Watchdog Window Register Low
Kojto 90:cb3d968589d8 98 * - HW_WDOG_REFRESH - Watchdog Refresh register
Kojto 90:cb3d968589d8 99 * - HW_WDOG_UNLOCK - Watchdog Unlock register
Kojto 90:cb3d968589d8 100 * - HW_WDOG_TMROUTH - Watchdog Timer Output Register High
Kojto 90:cb3d968589d8 101 * - HW_WDOG_TMROUTL - Watchdog Timer Output Register Low
Kojto 90:cb3d968589d8 102 * - HW_WDOG_RSTCNT - Watchdog Reset Count register
Kojto 90:cb3d968589d8 103 * - HW_WDOG_PRESC - Watchdog Prescaler register
Kojto 90:cb3d968589d8 104 *
Kojto 90:cb3d968589d8 105 * - hw_wdog_t - Struct containing all module registers.
Kojto 90:cb3d968589d8 106 */
Kojto 90:cb3d968589d8 107
Kojto 90:cb3d968589d8 108 #define HW_WDOG_INSTANCE_COUNT (1U) /*!< Number of instances of the WDOG module. */
Kojto 90:cb3d968589d8 109
Kojto 90:cb3d968589d8 110 /*******************************************************************************
Kojto 90:cb3d968589d8 111 * HW_WDOG_STCTRLH - Watchdog Status and Control Register High
Kojto 90:cb3d968589d8 112 ******************************************************************************/
Kojto 90:cb3d968589d8 113
Kojto 90:cb3d968589d8 114 /*!
Kojto 90:cb3d968589d8 115 * @brief HW_WDOG_STCTRLH - Watchdog Status and Control Register High (RW)
Kojto 90:cb3d968589d8 116 *
Kojto 90:cb3d968589d8 117 * Reset value: 0x01D3U
Kojto 90:cb3d968589d8 118 */
Kojto 90:cb3d968589d8 119 typedef union _hw_wdog_stctrlh
Kojto 90:cb3d968589d8 120 {
Kojto 90:cb3d968589d8 121 uint16_t U;
Kojto 90:cb3d968589d8 122 struct _hw_wdog_stctrlh_bitfields
Kojto 90:cb3d968589d8 123 {
Kojto 90:cb3d968589d8 124 uint16_t WDOGEN : 1; /*!< [0] */
Kojto 90:cb3d968589d8 125 uint16_t CLKSRC : 1; /*!< [1] */
Kojto 90:cb3d968589d8 126 uint16_t IRQRSTEN : 1; /*!< [2] */
Kojto 90:cb3d968589d8 127 uint16_t WINEN : 1; /*!< [3] */
Kojto 90:cb3d968589d8 128 uint16_t ALLOWUPDATE : 1; /*!< [4] */
Kojto 90:cb3d968589d8 129 uint16_t DBGEN : 1; /*!< [5] */
Kojto 90:cb3d968589d8 130 uint16_t STOPEN : 1; /*!< [6] */
Kojto 90:cb3d968589d8 131 uint16_t WAITEN : 1; /*!< [7] */
Kojto 90:cb3d968589d8 132 uint16_t RESERVED0 : 2; /*!< [9:8] */
Kojto 90:cb3d968589d8 133 uint16_t TESTWDOG : 1; /*!< [10] */
Kojto 90:cb3d968589d8 134 uint16_t TESTSEL : 1; /*!< [11] */
Kojto 90:cb3d968589d8 135 uint16_t BYTESEL : 2; /*!< [13:12] */
Kojto 90:cb3d968589d8 136 uint16_t DISTESTWDOG : 1; /*!< [14] */
Kojto 90:cb3d968589d8 137 uint16_t RESERVED1 : 1; /*!< [15] */
Kojto 90:cb3d968589d8 138 } B;
Kojto 90:cb3d968589d8 139 } hw_wdog_stctrlh_t;
Kojto 90:cb3d968589d8 140
Kojto 90:cb3d968589d8 141 /*!
Kojto 90:cb3d968589d8 142 * @name Constants and macros for entire WDOG_STCTRLH register
Kojto 90:cb3d968589d8 143 */
Kojto 90:cb3d968589d8 144 /*@{*/
Kojto 90:cb3d968589d8 145 #define HW_WDOG_STCTRLH_ADDR(x) ((x) + 0x0U)
Kojto 90:cb3d968589d8 146
Kojto 90:cb3d968589d8 147 #define HW_WDOG_STCTRLH(x) (*(__IO hw_wdog_stctrlh_t *) HW_WDOG_STCTRLH_ADDR(x))
Kojto 90:cb3d968589d8 148 #define HW_WDOG_STCTRLH_RD(x) (HW_WDOG_STCTRLH(x).U)
Kojto 90:cb3d968589d8 149 #define HW_WDOG_STCTRLH_WR(x, v) (HW_WDOG_STCTRLH(x).U = (v))
Kojto 90:cb3d968589d8 150 #define HW_WDOG_STCTRLH_SET(x, v) (HW_WDOG_STCTRLH_WR(x, HW_WDOG_STCTRLH_RD(x) | (v)))
Kojto 90:cb3d968589d8 151 #define HW_WDOG_STCTRLH_CLR(x, v) (HW_WDOG_STCTRLH_WR(x, HW_WDOG_STCTRLH_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 152 #define HW_WDOG_STCTRLH_TOG(x, v) (HW_WDOG_STCTRLH_WR(x, HW_WDOG_STCTRLH_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 153 /*@}*/
Kojto 90:cb3d968589d8 154
Kojto 90:cb3d968589d8 155 /*
Kojto 90:cb3d968589d8 156 * Constants & macros for individual WDOG_STCTRLH bitfields
Kojto 90:cb3d968589d8 157 */
Kojto 90:cb3d968589d8 158
Kojto 90:cb3d968589d8 159 /*!
Kojto 90:cb3d968589d8 160 * @name Register WDOG_STCTRLH, field WDOGEN[0] (RW)
Kojto 90:cb3d968589d8 161 *
Kojto 90:cb3d968589d8 162 * Enables or disables the WDOG's operation. In the disabled state, the watchdog
Kojto 90:cb3d968589d8 163 * timer is kept in the reset state, but the other exception conditions can
Kojto 90:cb3d968589d8 164 * still trigger a reset/interrupt. A change in the value of this bit must be held
Kojto 90:cb3d968589d8 165 * for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled.
Kojto 90:cb3d968589d8 166 *
Kojto 90:cb3d968589d8 167 * Values:
Kojto 90:cb3d968589d8 168 * - 0 - WDOG is disabled.
Kojto 90:cb3d968589d8 169 * - 1 - WDOG is enabled.
Kojto 90:cb3d968589d8 170 */
Kojto 90:cb3d968589d8 171 /*@{*/
Kojto 90:cb3d968589d8 172 #define BP_WDOG_STCTRLH_WDOGEN (0U) /*!< Bit position for WDOG_STCTRLH_WDOGEN. */
Kojto 90:cb3d968589d8 173 #define BM_WDOG_STCTRLH_WDOGEN (0x0001U) /*!< Bit mask for WDOG_STCTRLH_WDOGEN. */
Kojto 90:cb3d968589d8 174 #define BS_WDOG_STCTRLH_WDOGEN (1U) /*!< Bit field size in bits for WDOG_STCTRLH_WDOGEN. */
Kojto 90:cb3d968589d8 175
Kojto 90:cb3d968589d8 176 /*! @brief Read current value of the WDOG_STCTRLH_WDOGEN field. */
Kojto 90:cb3d968589d8 177 #define BR_WDOG_STCTRLH_WDOGEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WDOGEN))
Kojto 90:cb3d968589d8 178
Kojto 90:cb3d968589d8 179 /*! @brief Format value for bitfield WDOG_STCTRLH_WDOGEN. */
Kojto 90:cb3d968589d8 180 #define BF_WDOG_STCTRLH_WDOGEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_WDOGEN) & BM_WDOG_STCTRLH_WDOGEN)
Kojto 90:cb3d968589d8 181
Kojto 90:cb3d968589d8 182 /*! @brief Set the WDOGEN field to a new value. */
Kojto 90:cb3d968589d8 183 #define BW_WDOG_STCTRLH_WDOGEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WDOGEN) = (v))
Kojto 90:cb3d968589d8 184 /*@}*/
Kojto 90:cb3d968589d8 185
Kojto 90:cb3d968589d8 186 /*!
Kojto 90:cb3d968589d8 187 * @name Register WDOG_STCTRLH, field CLKSRC[1] (RW)
Kojto 90:cb3d968589d8 188 *
Kojto 90:cb3d968589d8 189 * Selects clock source for the WDOG timer and other internal timing operations.
Kojto 90:cb3d968589d8 190 *
Kojto 90:cb3d968589d8 191 * Values:
Kojto 90:cb3d968589d8 192 * - 0 - WDOG clock sourced from LPO .
Kojto 90:cb3d968589d8 193 * - 1 - WDOG clock sourced from alternate clock source.
Kojto 90:cb3d968589d8 194 */
Kojto 90:cb3d968589d8 195 /*@{*/
Kojto 90:cb3d968589d8 196 #define BP_WDOG_STCTRLH_CLKSRC (1U) /*!< Bit position for WDOG_STCTRLH_CLKSRC. */
Kojto 90:cb3d968589d8 197 #define BM_WDOG_STCTRLH_CLKSRC (0x0002U) /*!< Bit mask for WDOG_STCTRLH_CLKSRC. */
Kojto 90:cb3d968589d8 198 #define BS_WDOG_STCTRLH_CLKSRC (1U) /*!< Bit field size in bits for WDOG_STCTRLH_CLKSRC. */
Kojto 90:cb3d968589d8 199
Kojto 90:cb3d968589d8 200 /*! @brief Read current value of the WDOG_STCTRLH_CLKSRC field. */
Kojto 90:cb3d968589d8 201 #define BR_WDOG_STCTRLH_CLKSRC(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_CLKSRC))
Kojto 90:cb3d968589d8 202
Kojto 90:cb3d968589d8 203 /*! @brief Format value for bitfield WDOG_STCTRLH_CLKSRC. */
Kojto 90:cb3d968589d8 204 #define BF_WDOG_STCTRLH_CLKSRC(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_CLKSRC) & BM_WDOG_STCTRLH_CLKSRC)
Kojto 90:cb3d968589d8 205
Kojto 90:cb3d968589d8 206 /*! @brief Set the CLKSRC field to a new value. */
Kojto 90:cb3d968589d8 207 #define BW_WDOG_STCTRLH_CLKSRC(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_CLKSRC) = (v))
Kojto 90:cb3d968589d8 208 /*@}*/
Kojto 90:cb3d968589d8 209
Kojto 90:cb3d968589d8 210 /*!
Kojto 90:cb3d968589d8 211 * @name Register WDOG_STCTRLH, field IRQRSTEN[2] (RW)
Kojto 90:cb3d968589d8 212 *
Kojto 90:cb3d968589d8 213 * Used to enable the debug breadcrumbs feature. A change in this bit is updated
Kojto 90:cb3d968589d8 214 * immediately, as opposed to updating after WCT.
Kojto 90:cb3d968589d8 215 *
Kojto 90:cb3d968589d8 216 * Values:
Kojto 90:cb3d968589d8 217 * - 0 - WDOG time-out generates reset only.
Kojto 90:cb3d968589d8 218 * - 1 - WDOG time-out initially generates an interrupt. After WCT, it generates
Kojto 90:cb3d968589d8 219 * a reset.
Kojto 90:cb3d968589d8 220 */
Kojto 90:cb3d968589d8 221 /*@{*/
Kojto 90:cb3d968589d8 222 #define BP_WDOG_STCTRLH_IRQRSTEN (2U) /*!< Bit position for WDOG_STCTRLH_IRQRSTEN. */
Kojto 90:cb3d968589d8 223 #define BM_WDOG_STCTRLH_IRQRSTEN (0x0004U) /*!< Bit mask for WDOG_STCTRLH_IRQRSTEN. */
Kojto 90:cb3d968589d8 224 #define BS_WDOG_STCTRLH_IRQRSTEN (1U) /*!< Bit field size in bits for WDOG_STCTRLH_IRQRSTEN. */
Kojto 90:cb3d968589d8 225
Kojto 90:cb3d968589d8 226 /*! @brief Read current value of the WDOG_STCTRLH_IRQRSTEN field. */
Kojto 90:cb3d968589d8 227 #define BR_WDOG_STCTRLH_IRQRSTEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_IRQRSTEN))
Kojto 90:cb3d968589d8 228
Kojto 90:cb3d968589d8 229 /*! @brief Format value for bitfield WDOG_STCTRLH_IRQRSTEN. */
Kojto 90:cb3d968589d8 230 #define BF_WDOG_STCTRLH_IRQRSTEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_IRQRSTEN) & BM_WDOG_STCTRLH_IRQRSTEN)
Kojto 90:cb3d968589d8 231
Kojto 90:cb3d968589d8 232 /*! @brief Set the IRQRSTEN field to a new value. */
Kojto 90:cb3d968589d8 233 #define BW_WDOG_STCTRLH_IRQRSTEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_IRQRSTEN) = (v))
Kojto 90:cb3d968589d8 234 /*@}*/
Kojto 90:cb3d968589d8 235
Kojto 90:cb3d968589d8 236 /*!
Kojto 90:cb3d968589d8 237 * @name Register WDOG_STCTRLH, field WINEN[3] (RW)
Kojto 90:cb3d968589d8 238 *
Kojto 90:cb3d968589d8 239 * Enables Windowing mode.
Kojto 90:cb3d968589d8 240 *
Kojto 90:cb3d968589d8 241 * Values:
Kojto 90:cb3d968589d8 242 * - 0 - Windowing mode is disabled.
Kojto 90:cb3d968589d8 243 * - 1 - Windowing mode is enabled.
Kojto 90:cb3d968589d8 244 */
Kojto 90:cb3d968589d8 245 /*@{*/
Kojto 90:cb3d968589d8 246 #define BP_WDOG_STCTRLH_WINEN (3U) /*!< Bit position for WDOG_STCTRLH_WINEN. */
Kojto 90:cb3d968589d8 247 #define BM_WDOG_STCTRLH_WINEN (0x0008U) /*!< Bit mask for WDOG_STCTRLH_WINEN. */
Kojto 90:cb3d968589d8 248 #define BS_WDOG_STCTRLH_WINEN (1U) /*!< Bit field size in bits for WDOG_STCTRLH_WINEN. */
Kojto 90:cb3d968589d8 249
Kojto 90:cb3d968589d8 250 /*! @brief Read current value of the WDOG_STCTRLH_WINEN field. */
Kojto 90:cb3d968589d8 251 #define BR_WDOG_STCTRLH_WINEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WINEN))
Kojto 90:cb3d968589d8 252
Kojto 90:cb3d968589d8 253 /*! @brief Format value for bitfield WDOG_STCTRLH_WINEN. */
Kojto 90:cb3d968589d8 254 #define BF_WDOG_STCTRLH_WINEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_WINEN) & BM_WDOG_STCTRLH_WINEN)
Kojto 90:cb3d968589d8 255
Kojto 90:cb3d968589d8 256 /*! @brief Set the WINEN field to a new value. */
Kojto 90:cb3d968589d8 257 #define BW_WDOG_STCTRLH_WINEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WINEN) = (v))
Kojto 90:cb3d968589d8 258 /*@}*/
Kojto 90:cb3d968589d8 259
Kojto 90:cb3d968589d8 260 /*!
Kojto 90:cb3d968589d8 261 * @name Register WDOG_STCTRLH, field ALLOWUPDATE[4] (RW)
Kojto 90:cb3d968589d8 262 *
Kojto 90:cb3d968589d8 263 * Enables updates to watchdog write-once registers, after the reset-triggered
Kojto 90:cb3d968589d8 264 * initial configuration window (WCT) closes, through unlock sequence.
Kojto 90:cb3d968589d8 265 *
Kojto 90:cb3d968589d8 266 * Values:
Kojto 90:cb3d968589d8 267 * - 0 - No further updates allowed to WDOG write-once registers.
Kojto 90:cb3d968589d8 268 * - 1 - WDOG write-once registers can be unlocked for updating.
Kojto 90:cb3d968589d8 269 */
Kojto 90:cb3d968589d8 270 /*@{*/
Kojto 90:cb3d968589d8 271 #define BP_WDOG_STCTRLH_ALLOWUPDATE (4U) /*!< Bit position for WDOG_STCTRLH_ALLOWUPDATE. */
Kojto 90:cb3d968589d8 272 #define BM_WDOG_STCTRLH_ALLOWUPDATE (0x0010U) /*!< Bit mask for WDOG_STCTRLH_ALLOWUPDATE. */
Kojto 90:cb3d968589d8 273 #define BS_WDOG_STCTRLH_ALLOWUPDATE (1U) /*!< Bit field size in bits for WDOG_STCTRLH_ALLOWUPDATE. */
Kojto 90:cb3d968589d8 274
Kojto 90:cb3d968589d8 275 /*! @brief Read current value of the WDOG_STCTRLH_ALLOWUPDATE field. */
Kojto 90:cb3d968589d8 276 #define BR_WDOG_STCTRLH_ALLOWUPDATE(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_ALLOWUPDATE))
Kojto 90:cb3d968589d8 277
Kojto 90:cb3d968589d8 278 /*! @brief Format value for bitfield WDOG_STCTRLH_ALLOWUPDATE. */
Kojto 90:cb3d968589d8 279 #define BF_WDOG_STCTRLH_ALLOWUPDATE(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_ALLOWUPDATE) & BM_WDOG_STCTRLH_ALLOWUPDATE)
Kojto 90:cb3d968589d8 280
Kojto 90:cb3d968589d8 281 /*! @brief Set the ALLOWUPDATE field to a new value. */
Kojto 90:cb3d968589d8 282 #define BW_WDOG_STCTRLH_ALLOWUPDATE(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_ALLOWUPDATE) = (v))
Kojto 90:cb3d968589d8 283 /*@}*/
Kojto 90:cb3d968589d8 284
Kojto 90:cb3d968589d8 285 /*!
Kojto 90:cb3d968589d8 286 * @name Register WDOG_STCTRLH, field DBGEN[5] (RW)
Kojto 90:cb3d968589d8 287 *
Kojto 90:cb3d968589d8 288 * Enables or disables WDOG in Debug mode.
Kojto 90:cb3d968589d8 289 *
Kojto 90:cb3d968589d8 290 * Values:
Kojto 90:cb3d968589d8 291 * - 0 - WDOG is disabled in CPU Debug mode.
Kojto 90:cb3d968589d8 292 * - 1 - WDOG is enabled in CPU Debug mode.
Kojto 90:cb3d968589d8 293 */
Kojto 90:cb3d968589d8 294 /*@{*/
Kojto 90:cb3d968589d8 295 #define BP_WDOG_STCTRLH_DBGEN (5U) /*!< Bit position for WDOG_STCTRLH_DBGEN. */
Kojto 90:cb3d968589d8 296 #define BM_WDOG_STCTRLH_DBGEN (0x0020U) /*!< Bit mask for WDOG_STCTRLH_DBGEN. */
Kojto 90:cb3d968589d8 297 #define BS_WDOG_STCTRLH_DBGEN (1U) /*!< Bit field size in bits for WDOG_STCTRLH_DBGEN. */
Kojto 90:cb3d968589d8 298
Kojto 90:cb3d968589d8 299 /*! @brief Read current value of the WDOG_STCTRLH_DBGEN field. */
Kojto 90:cb3d968589d8 300 #define BR_WDOG_STCTRLH_DBGEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DBGEN))
Kojto 90:cb3d968589d8 301
Kojto 90:cb3d968589d8 302 /*! @brief Format value for bitfield WDOG_STCTRLH_DBGEN. */
Kojto 90:cb3d968589d8 303 #define BF_WDOG_STCTRLH_DBGEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_DBGEN) & BM_WDOG_STCTRLH_DBGEN)
Kojto 90:cb3d968589d8 304
Kojto 90:cb3d968589d8 305 /*! @brief Set the DBGEN field to a new value. */
Kojto 90:cb3d968589d8 306 #define BW_WDOG_STCTRLH_DBGEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DBGEN) = (v))
Kojto 90:cb3d968589d8 307 /*@}*/
Kojto 90:cb3d968589d8 308
Kojto 90:cb3d968589d8 309 /*!
Kojto 90:cb3d968589d8 310 * @name Register WDOG_STCTRLH, field STOPEN[6] (RW)
Kojto 90:cb3d968589d8 311 *
Kojto 90:cb3d968589d8 312 * Enables or disables WDOG in Stop mode.
Kojto 90:cb3d968589d8 313 *
Kojto 90:cb3d968589d8 314 * Values:
Kojto 90:cb3d968589d8 315 * - 0 - WDOG is disabled in CPU Stop mode.
Kojto 90:cb3d968589d8 316 * - 1 - WDOG is enabled in CPU Stop mode.
Kojto 90:cb3d968589d8 317 */
Kojto 90:cb3d968589d8 318 /*@{*/
Kojto 90:cb3d968589d8 319 #define BP_WDOG_STCTRLH_STOPEN (6U) /*!< Bit position for WDOG_STCTRLH_STOPEN. */
Kojto 90:cb3d968589d8 320 #define BM_WDOG_STCTRLH_STOPEN (0x0040U) /*!< Bit mask for WDOG_STCTRLH_STOPEN. */
Kojto 90:cb3d968589d8 321 #define BS_WDOG_STCTRLH_STOPEN (1U) /*!< Bit field size in bits for WDOG_STCTRLH_STOPEN. */
Kojto 90:cb3d968589d8 322
Kojto 90:cb3d968589d8 323 /*! @brief Read current value of the WDOG_STCTRLH_STOPEN field. */
Kojto 90:cb3d968589d8 324 #define BR_WDOG_STCTRLH_STOPEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_STOPEN))
Kojto 90:cb3d968589d8 325
Kojto 90:cb3d968589d8 326 /*! @brief Format value for bitfield WDOG_STCTRLH_STOPEN. */
Kojto 90:cb3d968589d8 327 #define BF_WDOG_STCTRLH_STOPEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_STOPEN) & BM_WDOG_STCTRLH_STOPEN)
Kojto 90:cb3d968589d8 328
Kojto 90:cb3d968589d8 329 /*! @brief Set the STOPEN field to a new value. */
Kojto 90:cb3d968589d8 330 #define BW_WDOG_STCTRLH_STOPEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_STOPEN) = (v))
Kojto 90:cb3d968589d8 331 /*@}*/
Kojto 90:cb3d968589d8 332
Kojto 90:cb3d968589d8 333 /*!
Kojto 90:cb3d968589d8 334 * @name Register WDOG_STCTRLH, field WAITEN[7] (RW)
Kojto 90:cb3d968589d8 335 *
Kojto 90:cb3d968589d8 336 * Enables or disables WDOG in Wait mode.
Kojto 90:cb3d968589d8 337 *
Kojto 90:cb3d968589d8 338 * Values:
Kojto 90:cb3d968589d8 339 * - 0 - WDOG is disabled in CPU Wait mode.
Kojto 90:cb3d968589d8 340 * - 1 - WDOG is enabled in CPU Wait mode.
Kojto 90:cb3d968589d8 341 */
Kojto 90:cb3d968589d8 342 /*@{*/
Kojto 90:cb3d968589d8 343 #define BP_WDOG_STCTRLH_WAITEN (7U) /*!< Bit position for WDOG_STCTRLH_WAITEN. */
Kojto 90:cb3d968589d8 344 #define BM_WDOG_STCTRLH_WAITEN (0x0080U) /*!< Bit mask for WDOG_STCTRLH_WAITEN. */
Kojto 90:cb3d968589d8 345 #define BS_WDOG_STCTRLH_WAITEN (1U) /*!< Bit field size in bits for WDOG_STCTRLH_WAITEN. */
Kojto 90:cb3d968589d8 346
Kojto 90:cb3d968589d8 347 /*! @brief Read current value of the WDOG_STCTRLH_WAITEN field. */
Kojto 90:cb3d968589d8 348 #define BR_WDOG_STCTRLH_WAITEN(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WAITEN))
Kojto 90:cb3d968589d8 349
Kojto 90:cb3d968589d8 350 /*! @brief Format value for bitfield WDOG_STCTRLH_WAITEN. */
Kojto 90:cb3d968589d8 351 #define BF_WDOG_STCTRLH_WAITEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_WAITEN) & BM_WDOG_STCTRLH_WAITEN)
Kojto 90:cb3d968589d8 352
Kojto 90:cb3d968589d8 353 /*! @brief Set the WAITEN field to a new value. */
Kojto 90:cb3d968589d8 354 #define BW_WDOG_STCTRLH_WAITEN(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WAITEN) = (v))
Kojto 90:cb3d968589d8 355 /*@}*/
Kojto 90:cb3d968589d8 356
Kojto 90:cb3d968589d8 357 /*!
Kojto 90:cb3d968589d8 358 * @name Register WDOG_STCTRLH, field TESTWDOG[10] (RW)
Kojto 90:cb3d968589d8 359 *
Kojto 90:cb3d968589d8 360 * Puts the watchdog in the functional test mode. In this mode, the watchdog
Kojto 90:cb3d968589d8 361 * timer and the associated compare and reset generation logic is tested for correct
Kojto 90:cb3d968589d8 362 * operation. The clock for the timer is switched from the main watchdog clock
Kojto 90:cb3d968589d8 363 * to the fast clock input for watchdog functional test. The TESTSEL bit selects
Kojto 90:cb3d968589d8 364 * the test to be run.
Kojto 90:cb3d968589d8 365 */
Kojto 90:cb3d968589d8 366 /*@{*/
Kojto 90:cb3d968589d8 367 #define BP_WDOG_STCTRLH_TESTWDOG (10U) /*!< Bit position for WDOG_STCTRLH_TESTWDOG. */
Kojto 90:cb3d968589d8 368 #define BM_WDOG_STCTRLH_TESTWDOG (0x0400U) /*!< Bit mask for WDOG_STCTRLH_TESTWDOG. */
Kojto 90:cb3d968589d8 369 #define BS_WDOG_STCTRLH_TESTWDOG (1U) /*!< Bit field size in bits for WDOG_STCTRLH_TESTWDOG. */
Kojto 90:cb3d968589d8 370
Kojto 90:cb3d968589d8 371 /*! @brief Read current value of the WDOG_STCTRLH_TESTWDOG field. */
Kojto 90:cb3d968589d8 372 #define BR_WDOG_STCTRLH_TESTWDOG(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTWDOG))
Kojto 90:cb3d968589d8 373
Kojto 90:cb3d968589d8 374 /*! @brief Format value for bitfield WDOG_STCTRLH_TESTWDOG. */
Kojto 90:cb3d968589d8 375 #define BF_WDOG_STCTRLH_TESTWDOG(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_TESTWDOG) & BM_WDOG_STCTRLH_TESTWDOG)
Kojto 90:cb3d968589d8 376
Kojto 90:cb3d968589d8 377 /*! @brief Set the TESTWDOG field to a new value. */
Kojto 90:cb3d968589d8 378 #define BW_WDOG_STCTRLH_TESTWDOG(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTWDOG) = (v))
Kojto 90:cb3d968589d8 379 /*@}*/
Kojto 90:cb3d968589d8 380
Kojto 90:cb3d968589d8 381 /*!
Kojto 90:cb3d968589d8 382 * @name Register WDOG_STCTRLH, field TESTSEL[11] (RW)
Kojto 90:cb3d968589d8 383 *
Kojto 90:cb3d968589d8 384 * Effective only if TESTWDOG is set. Selects the test to be run on the watchdog
Kojto 90:cb3d968589d8 385 * timer.
Kojto 90:cb3d968589d8 386 *
Kojto 90:cb3d968589d8 387 * Values:
Kojto 90:cb3d968589d8 388 * - 0 - Quick test. The timer runs in normal operation. You can load a small
Kojto 90:cb3d968589d8 389 * time-out value to do a quick test.
Kojto 90:cb3d968589d8 390 * - 1 - Byte test. Puts the timer in the byte test mode where individual bytes
Kojto 90:cb3d968589d8 391 * of the timer are enabled for operation and are compared for time-out
Kojto 90:cb3d968589d8 392 * against the corresponding byte of the programmed time-out value. Select the
Kojto 90:cb3d968589d8 393 * byte through BYTESEL[1:0] for testing.
Kojto 90:cb3d968589d8 394 */
Kojto 90:cb3d968589d8 395 /*@{*/
Kojto 90:cb3d968589d8 396 #define BP_WDOG_STCTRLH_TESTSEL (11U) /*!< Bit position for WDOG_STCTRLH_TESTSEL. */
Kojto 90:cb3d968589d8 397 #define BM_WDOG_STCTRLH_TESTSEL (0x0800U) /*!< Bit mask for WDOG_STCTRLH_TESTSEL. */
Kojto 90:cb3d968589d8 398 #define BS_WDOG_STCTRLH_TESTSEL (1U) /*!< Bit field size in bits for WDOG_STCTRLH_TESTSEL. */
Kojto 90:cb3d968589d8 399
Kojto 90:cb3d968589d8 400 /*! @brief Read current value of the WDOG_STCTRLH_TESTSEL field. */
Kojto 90:cb3d968589d8 401 #define BR_WDOG_STCTRLH_TESTSEL(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTSEL))
Kojto 90:cb3d968589d8 402
Kojto 90:cb3d968589d8 403 /*! @brief Format value for bitfield WDOG_STCTRLH_TESTSEL. */
Kojto 90:cb3d968589d8 404 #define BF_WDOG_STCTRLH_TESTSEL(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_TESTSEL) & BM_WDOG_STCTRLH_TESTSEL)
Kojto 90:cb3d968589d8 405
Kojto 90:cb3d968589d8 406 /*! @brief Set the TESTSEL field to a new value. */
Kojto 90:cb3d968589d8 407 #define BW_WDOG_STCTRLH_TESTSEL(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTSEL) = (v))
Kojto 90:cb3d968589d8 408 /*@}*/
Kojto 90:cb3d968589d8 409
Kojto 90:cb3d968589d8 410 /*!
Kojto 90:cb3d968589d8 411 * @name Register WDOG_STCTRLH, field BYTESEL[13:12] (RW)
Kojto 90:cb3d968589d8 412 *
Kojto 90:cb3d968589d8 413 * This 2-bit field selects the byte to be tested when the watchdog is in the
Kojto 90:cb3d968589d8 414 * byte test mode.
Kojto 90:cb3d968589d8 415 *
Kojto 90:cb3d968589d8 416 * Values:
Kojto 90:cb3d968589d8 417 * - 00 - Byte 0 selected
Kojto 90:cb3d968589d8 418 * - 01 - Byte 1 selected
Kojto 90:cb3d968589d8 419 * - 10 - Byte 2 selected
Kojto 90:cb3d968589d8 420 * - 11 - Byte 3 selected
Kojto 90:cb3d968589d8 421 */
Kojto 90:cb3d968589d8 422 /*@{*/
Kojto 90:cb3d968589d8 423 #define BP_WDOG_STCTRLH_BYTESEL (12U) /*!< Bit position for WDOG_STCTRLH_BYTESEL. */
Kojto 90:cb3d968589d8 424 #define BM_WDOG_STCTRLH_BYTESEL (0x3000U) /*!< Bit mask for WDOG_STCTRLH_BYTESEL. */
Kojto 90:cb3d968589d8 425 #define BS_WDOG_STCTRLH_BYTESEL (2U) /*!< Bit field size in bits for WDOG_STCTRLH_BYTESEL. */
Kojto 90:cb3d968589d8 426
Kojto 90:cb3d968589d8 427 /*! @brief Read current value of the WDOG_STCTRLH_BYTESEL field. */
Kojto 90:cb3d968589d8 428 #define BR_WDOG_STCTRLH_BYTESEL(x) (HW_WDOG_STCTRLH(x).B.BYTESEL)
Kojto 90:cb3d968589d8 429
Kojto 90:cb3d968589d8 430 /*! @brief Format value for bitfield WDOG_STCTRLH_BYTESEL. */
Kojto 90:cb3d968589d8 431 #define BF_WDOG_STCTRLH_BYTESEL(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_BYTESEL) & BM_WDOG_STCTRLH_BYTESEL)
Kojto 90:cb3d968589d8 432
Kojto 90:cb3d968589d8 433 /*! @brief Set the BYTESEL field to a new value. */
Kojto 90:cb3d968589d8 434 #define BW_WDOG_STCTRLH_BYTESEL(x, v) (HW_WDOG_STCTRLH_WR(x, (HW_WDOG_STCTRLH_RD(x) & ~BM_WDOG_STCTRLH_BYTESEL) | BF_WDOG_STCTRLH_BYTESEL(v)))
Kojto 90:cb3d968589d8 435 /*@}*/
Kojto 90:cb3d968589d8 436
Kojto 90:cb3d968589d8 437 /*!
Kojto 90:cb3d968589d8 438 * @name Register WDOG_STCTRLH, field DISTESTWDOG[14] (RW)
Kojto 90:cb3d968589d8 439 *
Kojto 90:cb3d968589d8 440 * Allows the WDOG's functional test mode to be disabled permanently. After it
Kojto 90:cb3d968589d8 441 * is set, it can only be cleared by a reset. It cannot be unlocked for editing
Kojto 90:cb3d968589d8 442 * after it is set.
Kojto 90:cb3d968589d8 443 *
Kojto 90:cb3d968589d8 444 * Values:
Kojto 90:cb3d968589d8 445 * - 0 - WDOG functional test mode is not disabled.
Kojto 90:cb3d968589d8 446 * - 1 - WDOG functional test mode is disabled permanently until reset.
Kojto 90:cb3d968589d8 447 */
Kojto 90:cb3d968589d8 448 /*@{*/
Kojto 90:cb3d968589d8 449 #define BP_WDOG_STCTRLH_DISTESTWDOG (14U) /*!< Bit position for WDOG_STCTRLH_DISTESTWDOG. */
Kojto 90:cb3d968589d8 450 #define BM_WDOG_STCTRLH_DISTESTWDOG (0x4000U) /*!< Bit mask for WDOG_STCTRLH_DISTESTWDOG. */
Kojto 90:cb3d968589d8 451 #define BS_WDOG_STCTRLH_DISTESTWDOG (1U) /*!< Bit field size in bits for WDOG_STCTRLH_DISTESTWDOG. */
Kojto 90:cb3d968589d8 452
Kojto 90:cb3d968589d8 453 /*! @brief Read current value of the WDOG_STCTRLH_DISTESTWDOG field. */
Kojto 90:cb3d968589d8 454 #define BR_WDOG_STCTRLH_DISTESTWDOG(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DISTESTWDOG))
Kojto 90:cb3d968589d8 455
Kojto 90:cb3d968589d8 456 /*! @brief Format value for bitfield WDOG_STCTRLH_DISTESTWDOG. */
Kojto 90:cb3d968589d8 457 #define BF_WDOG_STCTRLH_DISTESTWDOG(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_DISTESTWDOG) & BM_WDOG_STCTRLH_DISTESTWDOG)
Kojto 90:cb3d968589d8 458
Kojto 90:cb3d968589d8 459 /*! @brief Set the DISTESTWDOG field to a new value. */
Kojto 90:cb3d968589d8 460 #define BW_WDOG_STCTRLH_DISTESTWDOG(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DISTESTWDOG) = (v))
Kojto 90:cb3d968589d8 461 /*@}*/
Kojto 90:cb3d968589d8 462
Kojto 90:cb3d968589d8 463 /*******************************************************************************
Kojto 90:cb3d968589d8 464 * HW_WDOG_STCTRLL - Watchdog Status and Control Register Low
Kojto 90:cb3d968589d8 465 ******************************************************************************/
Kojto 90:cb3d968589d8 466
Kojto 90:cb3d968589d8 467 /*!
Kojto 90:cb3d968589d8 468 * @brief HW_WDOG_STCTRLL - Watchdog Status and Control Register Low (RW)
Kojto 90:cb3d968589d8 469 *
Kojto 90:cb3d968589d8 470 * Reset value: 0x0001U
Kojto 90:cb3d968589d8 471 */
Kojto 90:cb3d968589d8 472 typedef union _hw_wdog_stctrll
Kojto 90:cb3d968589d8 473 {
Kojto 90:cb3d968589d8 474 uint16_t U;
Kojto 90:cb3d968589d8 475 struct _hw_wdog_stctrll_bitfields
Kojto 90:cb3d968589d8 476 {
Kojto 90:cb3d968589d8 477 uint16_t RESERVED0 : 15; /*!< [14:0] */
Kojto 90:cb3d968589d8 478 uint16_t INTFLG : 1; /*!< [15] */
Kojto 90:cb3d968589d8 479 } B;
Kojto 90:cb3d968589d8 480 } hw_wdog_stctrll_t;
Kojto 90:cb3d968589d8 481
Kojto 90:cb3d968589d8 482 /*!
Kojto 90:cb3d968589d8 483 * @name Constants and macros for entire WDOG_STCTRLL register
Kojto 90:cb3d968589d8 484 */
Kojto 90:cb3d968589d8 485 /*@{*/
Kojto 90:cb3d968589d8 486 #define HW_WDOG_STCTRLL_ADDR(x) ((x) + 0x2U)
Kojto 90:cb3d968589d8 487
Kojto 90:cb3d968589d8 488 #define HW_WDOG_STCTRLL(x) (*(__IO hw_wdog_stctrll_t *) HW_WDOG_STCTRLL_ADDR(x))
Kojto 90:cb3d968589d8 489 #define HW_WDOG_STCTRLL_RD(x) (HW_WDOG_STCTRLL(x).U)
Kojto 90:cb3d968589d8 490 #define HW_WDOG_STCTRLL_WR(x, v) (HW_WDOG_STCTRLL(x).U = (v))
Kojto 90:cb3d968589d8 491 #define HW_WDOG_STCTRLL_SET(x, v) (HW_WDOG_STCTRLL_WR(x, HW_WDOG_STCTRLL_RD(x) | (v)))
Kojto 90:cb3d968589d8 492 #define HW_WDOG_STCTRLL_CLR(x, v) (HW_WDOG_STCTRLL_WR(x, HW_WDOG_STCTRLL_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 493 #define HW_WDOG_STCTRLL_TOG(x, v) (HW_WDOG_STCTRLL_WR(x, HW_WDOG_STCTRLL_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 494 /*@}*/
Kojto 90:cb3d968589d8 495
Kojto 90:cb3d968589d8 496 /*
Kojto 90:cb3d968589d8 497 * Constants & macros for individual WDOG_STCTRLL bitfields
Kojto 90:cb3d968589d8 498 */
Kojto 90:cb3d968589d8 499
Kojto 90:cb3d968589d8 500 /*!
Kojto 90:cb3d968589d8 501 * @name Register WDOG_STCTRLL, field INTFLG[15] (RW)
Kojto 90:cb3d968589d8 502 *
Kojto 90:cb3d968589d8 503 * Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a
Kojto 90:cb3d968589d8 504 * precondition to set this flag. INTFLG = 1 results in an interrupt being issued
Kojto 90:cb3d968589d8 505 * followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this
Kojto 90:cb3d968589d8 506 * bit. It also gets cleared on a system reset.
Kojto 90:cb3d968589d8 507 */
Kojto 90:cb3d968589d8 508 /*@{*/
Kojto 90:cb3d968589d8 509 #define BP_WDOG_STCTRLL_INTFLG (15U) /*!< Bit position for WDOG_STCTRLL_INTFLG. */
Kojto 90:cb3d968589d8 510 #define BM_WDOG_STCTRLL_INTFLG (0x8000U) /*!< Bit mask for WDOG_STCTRLL_INTFLG. */
Kojto 90:cb3d968589d8 511 #define BS_WDOG_STCTRLL_INTFLG (1U) /*!< Bit field size in bits for WDOG_STCTRLL_INTFLG. */
Kojto 90:cb3d968589d8 512
Kojto 90:cb3d968589d8 513 /*! @brief Read current value of the WDOG_STCTRLL_INTFLG field. */
Kojto 90:cb3d968589d8 514 #define BR_WDOG_STCTRLL_INTFLG(x) (BITBAND_ACCESS16(HW_WDOG_STCTRLL_ADDR(x), BP_WDOG_STCTRLL_INTFLG))
Kojto 90:cb3d968589d8 515
Kojto 90:cb3d968589d8 516 /*! @brief Format value for bitfield WDOG_STCTRLL_INTFLG. */
Kojto 90:cb3d968589d8 517 #define BF_WDOG_STCTRLL_INTFLG(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLL_INTFLG) & BM_WDOG_STCTRLL_INTFLG)
Kojto 90:cb3d968589d8 518
Kojto 90:cb3d968589d8 519 /*! @brief Set the INTFLG field to a new value. */
Kojto 90:cb3d968589d8 520 #define BW_WDOG_STCTRLL_INTFLG(x, v) (BITBAND_ACCESS16(HW_WDOG_STCTRLL_ADDR(x), BP_WDOG_STCTRLL_INTFLG) = (v))
Kojto 90:cb3d968589d8 521 /*@}*/
Kojto 90:cb3d968589d8 522
Kojto 90:cb3d968589d8 523 /*******************************************************************************
Kojto 90:cb3d968589d8 524 * HW_WDOG_TOVALH - Watchdog Time-out Value Register High
Kojto 90:cb3d968589d8 525 ******************************************************************************/
Kojto 90:cb3d968589d8 526
Kojto 90:cb3d968589d8 527 /*!
Kojto 90:cb3d968589d8 528 * @brief HW_WDOG_TOVALH - Watchdog Time-out Value Register High (RW)
Kojto 90:cb3d968589d8 529 *
Kojto 90:cb3d968589d8 530 * Reset value: 0x004CU
Kojto 90:cb3d968589d8 531 */
Kojto 90:cb3d968589d8 532 typedef union _hw_wdog_tovalh
Kojto 90:cb3d968589d8 533 {
Kojto 90:cb3d968589d8 534 uint16_t U;
Kojto 90:cb3d968589d8 535 struct _hw_wdog_tovalh_bitfields
Kojto 90:cb3d968589d8 536 {
Kojto 90:cb3d968589d8 537 uint16_t TOVALHIGH : 16; /*!< [15:0] */
Kojto 90:cb3d968589d8 538 } B;
Kojto 90:cb3d968589d8 539 } hw_wdog_tovalh_t;
Kojto 90:cb3d968589d8 540
Kojto 90:cb3d968589d8 541 /*!
Kojto 90:cb3d968589d8 542 * @name Constants and macros for entire WDOG_TOVALH register
Kojto 90:cb3d968589d8 543 */
Kojto 90:cb3d968589d8 544 /*@{*/
Kojto 90:cb3d968589d8 545 #define HW_WDOG_TOVALH_ADDR(x) ((x) + 0x4U)
Kojto 90:cb3d968589d8 546
Kojto 90:cb3d968589d8 547 #define HW_WDOG_TOVALH(x) (*(__IO hw_wdog_tovalh_t *) HW_WDOG_TOVALH_ADDR(x))
Kojto 90:cb3d968589d8 548 #define HW_WDOG_TOVALH_RD(x) (HW_WDOG_TOVALH(x).U)
Kojto 90:cb3d968589d8 549 #define HW_WDOG_TOVALH_WR(x, v) (HW_WDOG_TOVALH(x).U = (v))
Kojto 90:cb3d968589d8 550 #define HW_WDOG_TOVALH_SET(x, v) (HW_WDOG_TOVALH_WR(x, HW_WDOG_TOVALH_RD(x) | (v)))
Kojto 90:cb3d968589d8 551 #define HW_WDOG_TOVALH_CLR(x, v) (HW_WDOG_TOVALH_WR(x, HW_WDOG_TOVALH_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 552 #define HW_WDOG_TOVALH_TOG(x, v) (HW_WDOG_TOVALH_WR(x, HW_WDOG_TOVALH_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 553 /*@}*/
Kojto 90:cb3d968589d8 554
Kojto 90:cb3d968589d8 555 /*
Kojto 90:cb3d968589d8 556 * Constants & macros for individual WDOG_TOVALH bitfields
Kojto 90:cb3d968589d8 557 */
Kojto 90:cb3d968589d8 558
Kojto 90:cb3d968589d8 559 /*!
Kojto 90:cb3d968589d8 560 * @name Register WDOG_TOVALH, field TOVALHIGH[15:0] (RW)
Kojto 90:cb3d968589d8 561 *
Kojto 90:cb3d968589d8 562 * Defines the upper 16 bits of the 32-bit time-out value for the watchdog
Kojto 90:cb3d968589d8 563 * timer. It is defined in terms of cycles of the watchdog clock.
Kojto 90:cb3d968589d8 564 */
Kojto 90:cb3d968589d8 565 /*@{*/
Kojto 90:cb3d968589d8 566 #define BP_WDOG_TOVALH_TOVALHIGH (0U) /*!< Bit position for WDOG_TOVALH_TOVALHIGH. */
Kojto 90:cb3d968589d8 567 #define BM_WDOG_TOVALH_TOVALHIGH (0xFFFFU) /*!< Bit mask for WDOG_TOVALH_TOVALHIGH. */
Kojto 90:cb3d968589d8 568 #define BS_WDOG_TOVALH_TOVALHIGH (16U) /*!< Bit field size in bits for WDOG_TOVALH_TOVALHIGH. */
Kojto 90:cb3d968589d8 569
Kojto 90:cb3d968589d8 570 /*! @brief Read current value of the WDOG_TOVALH_TOVALHIGH field. */
Kojto 90:cb3d968589d8 571 #define BR_WDOG_TOVALH_TOVALHIGH(x) (HW_WDOG_TOVALH(x).U)
Kojto 90:cb3d968589d8 572
Kojto 90:cb3d968589d8 573 /*! @brief Format value for bitfield WDOG_TOVALH_TOVALHIGH. */
Kojto 90:cb3d968589d8 574 #define BF_WDOG_TOVALH_TOVALHIGH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TOVALH_TOVALHIGH) & BM_WDOG_TOVALH_TOVALHIGH)
Kojto 90:cb3d968589d8 575
Kojto 90:cb3d968589d8 576 /*! @brief Set the TOVALHIGH field to a new value. */
Kojto 90:cb3d968589d8 577 #define BW_WDOG_TOVALH_TOVALHIGH(x, v) (HW_WDOG_TOVALH_WR(x, v))
Kojto 90:cb3d968589d8 578 /*@}*/
Kojto 90:cb3d968589d8 579
Kojto 90:cb3d968589d8 580 /*******************************************************************************
Kojto 90:cb3d968589d8 581 * HW_WDOG_TOVALL - Watchdog Time-out Value Register Low
Kojto 90:cb3d968589d8 582 ******************************************************************************/
Kojto 90:cb3d968589d8 583
Kojto 90:cb3d968589d8 584 /*!
Kojto 90:cb3d968589d8 585 * @brief HW_WDOG_TOVALL - Watchdog Time-out Value Register Low (RW)
Kojto 90:cb3d968589d8 586 *
Kojto 90:cb3d968589d8 587 * Reset value: 0x4B4CU
Kojto 90:cb3d968589d8 588 *
Kojto 90:cb3d968589d8 589 * The time-out value of the watchdog must be set to a minimum of four watchdog
Kojto 90:cb3d968589d8 590 * clock cycles. This is to take into account the delay in new settings taking
Kojto 90:cb3d968589d8 591 * effect in the watchdog clock domain.
Kojto 90:cb3d968589d8 592 */
Kojto 90:cb3d968589d8 593 typedef union _hw_wdog_tovall
Kojto 90:cb3d968589d8 594 {
Kojto 90:cb3d968589d8 595 uint16_t U;
Kojto 90:cb3d968589d8 596 struct _hw_wdog_tovall_bitfields
Kojto 90:cb3d968589d8 597 {
Kojto 90:cb3d968589d8 598 uint16_t TOVALLOW : 16; /*!< [15:0] */
Kojto 90:cb3d968589d8 599 } B;
Kojto 90:cb3d968589d8 600 } hw_wdog_tovall_t;
Kojto 90:cb3d968589d8 601
Kojto 90:cb3d968589d8 602 /*!
Kojto 90:cb3d968589d8 603 * @name Constants and macros for entire WDOG_TOVALL register
Kojto 90:cb3d968589d8 604 */
Kojto 90:cb3d968589d8 605 /*@{*/
Kojto 90:cb3d968589d8 606 #define HW_WDOG_TOVALL_ADDR(x) ((x) + 0x6U)
Kojto 90:cb3d968589d8 607
Kojto 90:cb3d968589d8 608 #define HW_WDOG_TOVALL(x) (*(__IO hw_wdog_tovall_t *) HW_WDOG_TOVALL_ADDR(x))
Kojto 90:cb3d968589d8 609 #define HW_WDOG_TOVALL_RD(x) (HW_WDOG_TOVALL(x).U)
Kojto 90:cb3d968589d8 610 #define HW_WDOG_TOVALL_WR(x, v) (HW_WDOG_TOVALL(x).U = (v))
Kojto 90:cb3d968589d8 611 #define HW_WDOG_TOVALL_SET(x, v) (HW_WDOG_TOVALL_WR(x, HW_WDOG_TOVALL_RD(x) | (v)))
Kojto 90:cb3d968589d8 612 #define HW_WDOG_TOVALL_CLR(x, v) (HW_WDOG_TOVALL_WR(x, HW_WDOG_TOVALL_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 613 #define HW_WDOG_TOVALL_TOG(x, v) (HW_WDOG_TOVALL_WR(x, HW_WDOG_TOVALL_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 614 /*@}*/
Kojto 90:cb3d968589d8 615
Kojto 90:cb3d968589d8 616 /*
Kojto 90:cb3d968589d8 617 * Constants & macros for individual WDOG_TOVALL bitfields
Kojto 90:cb3d968589d8 618 */
Kojto 90:cb3d968589d8 619
Kojto 90:cb3d968589d8 620 /*!
Kojto 90:cb3d968589d8 621 * @name Register WDOG_TOVALL, field TOVALLOW[15:0] (RW)
Kojto 90:cb3d968589d8 622 *
Kojto 90:cb3d968589d8 623 * Defines the lower 16 bits of the 32-bit time-out value for the watchdog
Kojto 90:cb3d968589d8 624 * timer. It is defined in terms of cycles of the watchdog clock.
Kojto 90:cb3d968589d8 625 */
Kojto 90:cb3d968589d8 626 /*@{*/
Kojto 90:cb3d968589d8 627 #define BP_WDOG_TOVALL_TOVALLOW (0U) /*!< Bit position for WDOG_TOVALL_TOVALLOW. */
Kojto 90:cb3d968589d8 628 #define BM_WDOG_TOVALL_TOVALLOW (0xFFFFU) /*!< Bit mask for WDOG_TOVALL_TOVALLOW. */
Kojto 90:cb3d968589d8 629 #define BS_WDOG_TOVALL_TOVALLOW (16U) /*!< Bit field size in bits for WDOG_TOVALL_TOVALLOW. */
Kojto 90:cb3d968589d8 630
Kojto 90:cb3d968589d8 631 /*! @brief Read current value of the WDOG_TOVALL_TOVALLOW field. */
Kojto 90:cb3d968589d8 632 #define BR_WDOG_TOVALL_TOVALLOW(x) (HW_WDOG_TOVALL(x).U)
Kojto 90:cb3d968589d8 633
Kojto 90:cb3d968589d8 634 /*! @brief Format value for bitfield WDOG_TOVALL_TOVALLOW. */
Kojto 90:cb3d968589d8 635 #define BF_WDOG_TOVALL_TOVALLOW(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TOVALL_TOVALLOW) & BM_WDOG_TOVALL_TOVALLOW)
Kojto 90:cb3d968589d8 636
Kojto 90:cb3d968589d8 637 /*! @brief Set the TOVALLOW field to a new value. */
Kojto 90:cb3d968589d8 638 #define BW_WDOG_TOVALL_TOVALLOW(x, v) (HW_WDOG_TOVALL_WR(x, v))
Kojto 90:cb3d968589d8 639 /*@}*/
Kojto 90:cb3d968589d8 640
Kojto 90:cb3d968589d8 641 /*******************************************************************************
Kojto 90:cb3d968589d8 642 * HW_WDOG_WINH - Watchdog Window Register High
Kojto 90:cb3d968589d8 643 ******************************************************************************/
Kojto 90:cb3d968589d8 644
Kojto 90:cb3d968589d8 645 /*!
Kojto 90:cb3d968589d8 646 * @brief HW_WDOG_WINH - Watchdog Window Register High (RW)
Kojto 90:cb3d968589d8 647 *
Kojto 90:cb3d968589d8 648 * Reset value: 0x0000U
Kojto 90:cb3d968589d8 649 *
Kojto 90:cb3d968589d8 650 * You must set the Window Register value lower than the Time-out Value Register.
Kojto 90:cb3d968589d8 651 */
Kojto 90:cb3d968589d8 652 typedef union _hw_wdog_winh
Kojto 90:cb3d968589d8 653 {
Kojto 90:cb3d968589d8 654 uint16_t U;
Kojto 90:cb3d968589d8 655 struct _hw_wdog_winh_bitfields
Kojto 90:cb3d968589d8 656 {
Kojto 90:cb3d968589d8 657 uint16_t WINHIGH : 16; /*!< [15:0] */
Kojto 90:cb3d968589d8 658 } B;
Kojto 90:cb3d968589d8 659 } hw_wdog_winh_t;
Kojto 90:cb3d968589d8 660
Kojto 90:cb3d968589d8 661 /*!
Kojto 90:cb3d968589d8 662 * @name Constants and macros for entire WDOG_WINH register
Kojto 90:cb3d968589d8 663 */
Kojto 90:cb3d968589d8 664 /*@{*/
Kojto 90:cb3d968589d8 665 #define HW_WDOG_WINH_ADDR(x) ((x) + 0x8U)
Kojto 90:cb3d968589d8 666
Kojto 90:cb3d968589d8 667 #define HW_WDOG_WINH(x) (*(__IO hw_wdog_winh_t *) HW_WDOG_WINH_ADDR(x))
Kojto 90:cb3d968589d8 668 #define HW_WDOG_WINH_RD(x) (HW_WDOG_WINH(x).U)
Kojto 90:cb3d968589d8 669 #define HW_WDOG_WINH_WR(x, v) (HW_WDOG_WINH(x).U = (v))
Kojto 90:cb3d968589d8 670 #define HW_WDOG_WINH_SET(x, v) (HW_WDOG_WINH_WR(x, HW_WDOG_WINH_RD(x) | (v)))
Kojto 90:cb3d968589d8 671 #define HW_WDOG_WINH_CLR(x, v) (HW_WDOG_WINH_WR(x, HW_WDOG_WINH_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 672 #define HW_WDOG_WINH_TOG(x, v) (HW_WDOG_WINH_WR(x, HW_WDOG_WINH_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 673 /*@}*/
Kojto 90:cb3d968589d8 674
Kojto 90:cb3d968589d8 675 /*
Kojto 90:cb3d968589d8 676 * Constants & macros for individual WDOG_WINH bitfields
Kojto 90:cb3d968589d8 677 */
Kojto 90:cb3d968589d8 678
Kojto 90:cb3d968589d8 679 /*!
Kojto 90:cb3d968589d8 680 * @name Register WDOG_WINH, field WINHIGH[15:0] (RW)
Kojto 90:cb3d968589d8 681 *
Kojto 90:cb3d968589d8 682 * Defines the upper 16 bits of the 32-bit window for the windowed mode of
Kojto 90:cb3d968589d8 683 * operation of the watchdog. It is defined in terms of cycles of the watchdog clock.
Kojto 90:cb3d968589d8 684 * In this mode, the watchdog can be refreshed only when the timer has reached a
Kojto 90:cb3d968589d8 685 * value greater than or equal to this window length. A refresh outside this
Kojto 90:cb3d968589d8 686 * window resets the system or if IRQRSTEN is set, it interrupts and then resets the
Kojto 90:cb3d968589d8 687 * system.
Kojto 90:cb3d968589d8 688 */
Kojto 90:cb3d968589d8 689 /*@{*/
Kojto 90:cb3d968589d8 690 #define BP_WDOG_WINH_WINHIGH (0U) /*!< Bit position for WDOG_WINH_WINHIGH. */
Kojto 90:cb3d968589d8 691 #define BM_WDOG_WINH_WINHIGH (0xFFFFU) /*!< Bit mask for WDOG_WINH_WINHIGH. */
Kojto 90:cb3d968589d8 692 #define BS_WDOG_WINH_WINHIGH (16U) /*!< Bit field size in bits for WDOG_WINH_WINHIGH. */
Kojto 90:cb3d968589d8 693
Kojto 90:cb3d968589d8 694 /*! @brief Read current value of the WDOG_WINH_WINHIGH field. */
Kojto 90:cb3d968589d8 695 #define BR_WDOG_WINH_WINHIGH(x) (HW_WDOG_WINH(x).U)
Kojto 90:cb3d968589d8 696
Kojto 90:cb3d968589d8 697 /*! @brief Format value for bitfield WDOG_WINH_WINHIGH. */
Kojto 90:cb3d968589d8 698 #define BF_WDOG_WINH_WINHIGH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_WINH_WINHIGH) & BM_WDOG_WINH_WINHIGH)
Kojto 90:cb3d968589d8 699
Kojto 90:cb3d968589d8 700 /*! @brief Set the WINHIGH field to a new value. */
Kojto 90:cb3d968589d8 701 #define BW_WDOG_WINH_WINHIGH(x, v) (HW_WDOG_WINH_WR(x, v))
Kojto 90:cb3d968589d8 702 /*@}*/
Kojto 90:cb3d968589d8 703
Kojto 90:cb3d968589d8 704 /*******************************************************************************
Kojto 90:cb3d968589d8 705 * HW_WDOG_WINL - Watchdog Window Register Low
Kojto 90:cb3d968589d8 706 ******************************************************************************/
Kojto 90:cb3d968589d8 707
Kojto 90:cb3d968589d8 708 /*!
Kojto 90:cb3d968589d8 709 * @brief HW_WDOG_WINL - Watchdog Window Register Low (RW)
Kojto 90:cb3d968589d8 710 *
Kojto 90:cb3d968589d8 711 * Reset value: 0x0010U
Kojto 90:cb3d968589d8 712 *
Kojto 90:cb3d968589d8 713 * You must set the Window Register value lower than the Time-out Value Register.
Kojto 90:cb3d968589d8 714 */
Kojto 90:cb3d968589d8 715 typedef union _hw_wdog_winl
Kojto 90:cb3d968589d8 716 {
Kojto 90:cb3d968589d8 717 uint16_t U;
Kojto 90:cb3d968589d8 718 struct _hw_wdog_winl_bitfields
Kojto 90:cb3d968589d8 719 {
Kojto 90:cb3d968589d8 720 uint16_t WINLOW : 16; /*!< [15:0] */
Kojto 90:cb3d968589d8 721 } B;
Kojto 90:cb3d968589d8 722 } hw_wdog_winl_t;
Kojto 90:cb3d968589d8 723
Kojto 90:cb3d968589d8 724 /*!
Kojto 90:cb3d968589d8 725 * @name Constants and macros for entire WDOG_WINL register
Kojto 90:cb3d968589d8 726 */
Kojto 90:cb3d968589d8 727 /*@{*/
Kojto 90:cb3d968589d8 728 #define HW_WDOG_WINL_ADDR(x) ((x) + 0xAU)
Kojto 90:cb3d968589d8 729
Kojto 90:cb3d968589d8 730 #define HW_WDOG_WINL(x) (*(__IO hw_wdog_winl_t *) HW_WDOG_WINL_ADDR(x))
Kojto 90:cb3d968589d8 731 #define HW_WDOG_WINL_RD(x) (HW_WDOG_WINL(x).U)
Kojto 90:cb3d968589d8 732 #define HW_WDOG_WINL_WR(x, v) (HW_WDOG_WINL(x).U = (v))
Kojto 90:cb3d968589d8 733 #define HW_WDOG_WINL_SET(x, v) (HW_WDOG_WINL_WR(x, HW_WDOG_WINL_RD(x) | (v)))
Kojto 90:cb3d968589d8 734 #define HW_WDOG_WINL_CLR(x, v) (HW_WDOG_WINL_WR(x, HW_WDOG_WINL_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 735 #define HW_WDOG_WINL_TOG(x, v) (HW_WDOG_WINL_WR(x, HW_WDOG_WINL_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 736 /*@}*/
Kojto 90:cb3d968589d8 737
Kojto 90:cb3d968589d8 738 /*
Kojto 90:cb3d968589d8 739 * Constants & macros for individual WDOG_WINL bitfields
Kojto 90:cb3d968589d8 740 */
Kojto 90:cb3d968589d8 741
Kojto 90:cb3d968589d8 742 /*!
Kojto 90:cb3d968589d8 743 * @name Register WDOG_WINL, field WINLOW[15:0] (RW)
Kojto 90:cb3d968589d8 744 *
Kojto 90:cb3d968589d8 745 * Defines the lower 16 bits of the 32-bit window for the windowed mode of
Kojto 90:cb3d968589d8 746 * operation of the watchdog. It is defined in terms of cycles of the pre-scaled
Kojto 90:cb3d968589d8 747 * watchdog clock. In this mode, the watchdog can be refreshed only when the timer
Kojto 90:cb3d968589d8 748 * reaches a value greater than or equal to this window length value. A refresh
Kojto 90:cb3d968589d8 749 * outside of this window resets the system or if IRQRSTEN is set, it interrupts and
Kojto 90:cb3d968589d8 750 * then resets the system.
Kojto 90:cb3d968589d8 751 */
Kojto 90:cb3d968589d8 752 /*@{*/
Kojto 90:cb3d968589d8 753 #define BP_WDOG_WINL_WINLOW (0U) /*!< Bit position for WDOG_WINL_WINLOW. */
Kojto 90:cb3d968589d8 754 #define BM_WDOG_WINL_WINLOW (0xFFFFU) /*!< Bit mask for WDOG_WINL_WINLOW. */
Kojto 90:cb3d968589d8 755 #define BS_WDOG_WINL_WINLOW (16U) /*!< Bit field size in bits for WDOG_WINL_WINLOW. */
Kojto 90:cb3d968589d8 756
Kojto 90:cb3d968589d8 757 /*! @brief Read current value of the WDOG_WINL_WINLOW field. */
Kojto 90:cb3d968589d8 758 #define BR_WDOG_WINL_WINLOW(x) (HW_WDOG_WINL(x).U)
Kojto 90:cb3d968589d8 759
Kojto 90:cb3d968589d8 760 /*! @brief Format value for bitfield WDOG_WINL_WINLOW. */
Kojto 90:cb3d968589d8 761 #define BF_WDOG_WINL_WINLOW(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_WINL_WINLOW) & BM_WDOG_WINL_WINLOW)
Kojto 90:cb3d968589d8 762
Kojto 90:cb3d968589d8 763 /*! @brief Set the WINLOW field to a new value. */
Kojto 90:cb3d968589d8 764 #define BW_WDOG_WINL_WINLOW(x, v) (HW_WDOG_WINL_WR(x, v))
Kojto 90:cb3d968589d8 765 /*@}*/
Kojto 90:cb3d968589d8 766
Kojto 90:cb3d968589d8 767 /*******************************************************************************
Kojto 90:cb3d968589d8 768 * HW_WDOG_REFRESH - Watchdog Refresh register
Kojto 90:cb3d968589d8 769 ******************************************************************************/
Kojto 90:cb3d968589d8 770
Kojto 90:cb3d968589d8 771 /*!
Kojto 90:cb3d968589d8 772 * @brief HW_WDOG_REFRESH - Watchdog Refresh register (RW)
Kojto 90:cb3d968589d8 773 *
Kojto 90:cb3d968589d8 774 * Reset value: 0xB480U
Kojto 90:cb3d968589d8 775 */
Kojto 90:cb3d968589d8 776 typedef union _hw_wdog_refresh
Kojto 90:cb3d968589d8 777 {
Kojto 90:cb3d968589d8 778 uint16_t U;
Kojto 90:cb3d968589d8 779 struct _hw_wdog_refresh_bitfields
Kojto 90:cb3d968589d8 780 {
Kojto 90:cb3d968589d8 781 uint16_t WDOGREFRESH : 16; /*!< [15:0] */
Kojto 90:cb3d968589d8 782 } B;
Kojto 90:cb3d968589d8 783 } hw_wdog_refresh_t;
Kojto 90:cb3d968589d8 784
Kojto 90:cb3d968589d8 785 /*!
Kojto 90:cb3d968589d8 786 * @name Constants and macros for entire WDOG_REFRESH register
Kojto 90:cb3d968589d8 787 */
Kojto 90:cb3d968589d8 788 /*@{*/
Kojto 90:cb3d968589d8 789 #define HW_WDOG_REFRESH_ADDR(x) ((x) + 0xCU)
Kojto 90:cb3d968589d8 790
Kojto 90:cb3d968589d8 791 #define HW_WDOG_REFRESH(x) (*(__IO hw_wdog_refresh_t *) HW_WDOG_REFRESH_ADDR(x))
Kojto 90:cb3d968589d8 792 #define HW_WDOG_REFRESH_RD(x) (HW_WDOG_REFRESH(x).U)
Kojto 90:cb3d968589d8 793 #define HW_WDOG_REFRESH_WR(x, v) (HW_WDOG_REFRESH(x).U = (v))
Kojto 90:cb3d968589d8 794 #define HW_WDOG_REFRESH_SET(x, v) (HW_WDOG_REFRESH_WR(x, HW_WDOG_REFRESH_RD(x) | (v)))
Kojto 90:cb3d968589d8 795 #define HW_WDOG_REFRESH_CLR(x, v) (HW_WDOG_REFRESH_WR(x, HW_WDOG_REFRESH_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 796 #define HW_WDOG_REFRESH_TOG(x, v) (HW_WDOG_REFRESH_WR(x, HW_WDOG_REFRESH_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 797 /*@}*/
Kojto 90:cb3d968589d8 798
Kojto 90:cb3d968589d8 799 /*
Kojto 90:cb3d968589d8 800 * Constants & macros for individual WDOG_REFRESH bitfields
Kojto 90:cb3d968589d8 801 */
Kojto 90:cb3d968589d8 802
Kojto 90:cb3d968589d8 803 /*!
Kojto 90:cb3d968589d8 804 * @name Register WDOG_REFRESH, field WDOGREFRESH[15:0] (RW)
Kojto 90:cb3d968589d8 805 *
Kojto 90:cb3d968589d8 806 * Watchdog refresh register. A sequence of 0xA602 followed by 0xB480 within 20
Kojto 90:cb3d968589d8 807 * bus clock cycles written to this register refreshes the WDOG and prevents it
Kojto 90:cb3d968589d8 808 * from resetting the system. Writing a value other than the above mentioned
Kojto 90:cb3d968589d8 809 * sequence or if the sequence is longer than 20 bus cycles, resets the system, or if
Kojto 90:cb3d968589d8 810 * IRQRSTEN is set, it interrupts and then resets the system.
Kojto 90:cb3d968589d8 811 */
Kojto 90:cb3d968589d8 812 /*@{*/
Kojto 90:cb3d968589d8 813 #define BP_WDOG_REFRESH_WDOGREFRESH (0U) /*!< Bit position for WDOG_REFRESH_WDOGREFRESH. */
Kojto 90:cb3d968589d8 814 #define BM_WDOG_REFRESH_WDOGREFRESH (0xFFFFU) /*!< Bit mask for WDOG_REFRESH_WDOGREFRESH. */
Kojto 90:cb3d968589d8 815 #define BS_WDOG_REFRESH_WDOGREFRESH (16U) /*!< Bit field size in bits for WDOG_REFRESH_WDOGREFRESH. */
Kojto 90:cb3d968589d8 816
Kojto 90:cb3d968589d8 817 /*! @brief Read current value of the WDOG_REFRESH_WDOGREFRESH field. */
Kojto 90:cb3d968589d8 818 #define BR_WDOG_REFRESH_WDOGREFRESH(x) (HW_WDOG_REFRESH(x).U)
Kojto 90:cb3d968589d8 819
Kojto 90:cb3d968589d8 820 /*! @brief Format value for bitfield WDOG_REFRESH_WDOGREFRESH. */
Kojto 90:cb3d968589d8 821 #define BF_WDOG_REFRESH_WDOGREFRESH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_REFRESH_WDOGREFRESH) & BM_WDOG_REFRESH_WDOGREFRESH)
Kojto 90:cb3d968589d8 822
Kojto 90:cb3d968589d8 823 /*! @brief Set the WDOGREFRESH field to a new value. */
Kojto 90:cb3d968589d8 824 #define BW_WDOG_REFRESH_WDOGREFRESH(x, v) (HW_WDOG_REFRESH_WR(x, v))
Kojto 90:cb3d968589d8 825 /*@}*/
Kojto 90:cb3d968589d8 826
Kojto 90:cb3d968589d8 827 /*******************************************************************************
Kojto 90:cb3d968589d8 828 * HW_WDOG_UNLOCK - Watchdog Unlock register
Kojto 90:cb3d968589d8 829 ******************************************************************************/
Kojto 90:cb3d968589d8 830
Kojto 90:cb3d968589d8 831 /*!
Kojto 90:cb3d968589d8 832 * @brief HW_WDOG_UNLOCK - Watchdog Unlock register (RW)
Kojto 90:cb3d968589d8 833 *
Kojto 90:cb3d968589d8 834 * Reset value: 0xD928U
Kojto 90:cb3d968589d8 835 */
Kojto 90:cb3d968589d8 836 typedef union _hw_wdog_unlock
Kojto 90:cb3d968589d8 837 {
Kojto 90:cb3d968589d8 838 uint16_t U;
Kojto 90:cb3d968589d8 839 struct _hw_wdog_unlock_bitfields
Kojto 90:cb3d968589d8 840 {
Kojto 90:cb3d968589d8 841 uint16_t WDOGUNLOCK : 16; /*!< [15:0] */
Kojto 90:cb3d968589d8 842 } B;
Kojto 90:cb3d968589d8 843 } hw_wdog_unlock_t;
Kojto 90:cb3d968589d8 844
Kojto 90:cb3d968589d8 845 /*!
Kojto 90:cb3d968589d8 846 * @name Constants and macros for entire WDOG_UNLOCK register
Kojto 90:cb3d968589d8 847 */
Kojto 90:cb3d968589d8 848 /*@{*/
Kojto 90:cb3d968589d8 849 #define HW_WDOG_UNLOCK_ADDR(x) ((x) + 0xEU)
Kojto 90:cb3d968589d8 850
Kojto 90:cb3d968589d8 851 #define HW_WDOG_UNLOCK(x) (*(__IO hw_wdog_unlock_t *) HW_WDOG_UNLOCK_ADDR(x))
Kojto 90:cb3d968589d8 852 #define HW_WDOG_UNLOCK_RD(x) (HW_WDOG_UNLOCK(x).U)
Kojto 90:cb3d968589d8 853 #define HW_WDOG_UNLOCK_WR(x, v) (HW_WDOG_UNLOCK(x).U = (v))
Kojto 90:cb3d968589d8 854 #define HW_WDOG_UNLOCK_SET(x, v) (HW_WDOG_UNLOCK_WR(x, HW_WDOG_UNLOCK_RD(x) | (v)))
Kojto 90:cb3d968589d8 855 #define HW_WDOG_UNLOCK_CLR(x, v) (HW_WDOG_UNLOCK_WR(x, HW_WDOG_UNLOCK_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 856 #define HW_WDOG_UNLOCK_TOG(x, v) (HW_WDOG_UNLOCK_WR(x, HW_WDOG_UNLOCK_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 857 /*@}*/
Kojto 90:cb3d968589d8 858
Kojto 90:cb3d968589d8 859 /*
Kojto 90:cb3d968589d8 860 * Constants & macros for individual WDOG_UNLOCK bitfields
Kojto 90:cb3d968589d8 861 */
Kojto 90:cb3d968589d8 862
Kojto 90:cb3d968589d8 863 /*!
Kojto 90:cb3d968589d8 864 * @name Register WDOG_UNLOCK, field WDOGUNLOCK[15:0] (RW)
Kojto 90:cb3d968589d8 865 *
Kojto 90:cb3d968589d8 866 * Writing the unlock sequence values to this register to makes the watchdog
Kojto 90:cb3d968589d8 867 * write-once registers writable again. The required unlock sequence is 0xC520
Kojto 90:cb3d968589d8 868 * followed by 0xD928 within 20 bus clock cycles. A valid unlock sequence opens a
Kojto 90:cb3d968589d8 869 * window equal in length to the WCT within which you can update the registers.
Kojto 90:cb3d968589d8 870 * Writing a value other than the above mentioned sequence or if the sequence is
Kojto 90:cb3d968589d8 871 * longer than 20 bus cycles, resets the system or if IRQRSTEN is set, it interrupts
Kojto 90:cb3d968589d8 872 * and then resets the system. The unlock sequence is effective only if
Kojto 90:cb3d968589d8 873 * ALLOWUPDATE is set.
Kojto 90:cb3d968589d8 874 */
Kojto 90:cb3d968589d8 875 /*@{*/
Kojto 90:cb3d968589d8 876 #define BP_WDOG_UNLOCK_WDOGUNLOCK (0U) /*!< Bit position for WDOG_UNLOCK_WDOGUNLOCK. */
Kojto 90:cb3d968589d8 877 #define BM_WDOG_UNLOCK_WDOGUNLOCK (0xFFFFU) /*!< Bit mask for WDOG_UNLOCK_WDOGUNLOCK. */
Kojto 90:cb3d968589d8 878 #define BS_WDOG_UNLOCK_WDOGUNLOCK (16U) /*!< Bit field size in bits for WDOG_UNLOCK_WDOGUNLOCK. */
Kojto 90:cb3d968589d8 879
Kojto 90:cb3d968589d8 880 /*! @brief Read current value of the WDOG_UNLOCK_WDOGUNLOCK field. */
Kojto 90:cb3d968589d8 881 #define BR_WDOG_UNLOCK_WDOGUNLOCK(x) (HW_WDOG_UNLOCK(x).U)
Kojto 90:cb3d968589d8 882
Kojto 90:cb3d968589d8 883 /*! @brief Format value for bitfield WDOG_UNLOCK_WDOGUNLOCK. */
Kojto 90:cb3d968589d8 884 #define BF_WDOG_UNLOCK_WDOGUNLOCK(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_UNLOCK_WDOGUNLOCK) & BM_WDOG_UNLOCK_WDOGUNLOCK)
Kojto 90:cb3d968589d8 885
Kojto 90:cb3d968589d8 886 /*! @brief Set the WDOGUNLOCK field to a new value. */
Kojto 90:cb3d968589d8 887 #define BW_WDOG_UNLOCK_WDOGUNLOCK(x, v) (HW_WDOG_UNLOCK_WR(x, v))
Kojto 90:cb3d968589d8 888 /*@}*/
Kojto 90:cb3d968589d8 889
Kojto 90:cb3d968589d8 890 /*******************************************************************************
Kojto 90:cb3d968589d8 891 * HW_WDOG_TMROUTH - Watchdog Timer Output Register High
Kojto 90:cb3d968589d8 892 ******************************************************************************/
Kojto 90:cb3d968589d8 893
Kojto 90:cb3d968589d8 894 /*!
Kojto 90:cb3d968589d8 895 * @brief HW_WDOG_TMROUTH - Watchdog Timer Output Register High (RW)
Kojto 90:cb3d968589d8 896 *
Kojto 90:cb3d968589d8 897 * Reset value: 0x0000U
Kojto 90:cb3d968589d8 898 */
Kojto 90:cb3d968589d8 899 typedef union _hw_wdog_tmrouth
Kojto 90:cb3d968589d8 900 {
Kojto 90:cb3d968589d8 901 uint16_t U;
Kojto 90:cb3d968589d8 902 struct _hw_wdog_tmrouth_bitfields
Kojto 90:cb3d968589d8 903 {
Kojto 90:cb3d968589d8 904 uint16_t TIMEROUTHIGH : 16; /*!< [15:0] */
Kojto 90:cb3d968589d8 905 } B;
Kojto 90:cb3d968589d8 906 } hw_wdog_tmrouth_t;
Kojto 90:cb3d968589d8 907
Kojto 90:cb3d968589d8 908 /*!
Kojto 90:cb3d968589d8 909 * @name Constants and macros for entire WDOG_TMROUTH register
Kojto 90:cb3d968589d8 910 */
Kojto 90:cb3d968589d8 911 /*@{*/
Kojto 90:cb3d968589d8 912 #define HW_WDOG_TMROUTH_ADDR(x) ((x) + 0x10U)
Kojto 90:cb3d968589d8 913
Kojto 90:cb3d968589d8 914 #define HW_WDOG_TMROUTH(x) (*(__IO hw_wdog_tmrouth_t *) HW_WDOG_TMROUTH_ADDR(x))
Kojto 90:cb3d968589d8 915 #define HW_WDOG_TMROUTH_RD(x) (HW_WDOG_TMROUTH(x).U)
Kojto 90:cb3d968589d8 916 #define HW_WDOG_TMROUTH_WR(x, v) (HW_WDOG_TMROUTH(x).U = (v))
Kojto 90:cb3d968589d8 917 #define HW_WDOG_TMROUTH_SET(x, v) (HW_WDOG_TMROUTH_WR(x, HW_WDOG_TMROUTH_RD(x) | (v)))
Kojto 90:cb3d968589d8 918 #define HW_WDOG_TMROUTH_CLR(x, v) (HW_WDOG_TMROUTH_WR(x, HW_WDOG_TMROUTH_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 919 #define HW_WDOG_TMROUTH_TOG(x, v) (HW_WDOG_TMROUTH_WR(x, HW_WDOG_TMROUTH_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 920 /*@}*/
Kojto 90:cb3d968589d8 921
Kojto 90:cb3d968589d8 922 /*
Kojto 90:cb3d968589d8 923 * Constants & macros for individual WDOG_TMROUTH bitfields
Kojto 90:cb3d968589d8 924 */
Kojto 90:cb3d968589d8 925
Kojto 90:cb3d968589d8 926 /*!
Kojto 90:cb3d968589d8 927 * @name Register WDOG_TMROUTH, field TIMEROUTHIGH[15:0] (RW)
Kojto 90:cb3d968589d8 928 *
Kojto 90:cb3d968589d8 929 * Shows the value of the upper 16 bits of the watchdog timer.
Kojto 90:cb3d968589d8 930 */
Kojto 90:cb3d968589d8 931 /*@{*/
Kojto 90:cb3d968589d8 932 #define BP_WDOG_TMROUTH_TIMEROUTHIGH (0U) /*!< Bit position for WDOG_TMROUTH_TIMEROUTHIGH. */
Kojto 90:cb3d968589d8 933 #define BM_WDOG_TMROUTH_TIMEROUTHIGH (0xFFFFU) /*!< Bit mask for WDOG_TMROUTH_TIMEROUTHIGH. */
Kojto 90:cb3d968589d8 934 #define BS_WDOG_TMROUTH_TIMEROUTHIGH (16U) /*!< Bit field size in bits for WDOG_TMROUTH_TIMEROUTHIGH. */
Kojto 90:cb3d968589d8 935
Kojto 90:cb3d968589d8 936 /*! @brief Read current value of the WDOG_TMROUTH_TIMEROUTHIGH field. */
Kojto 90:cb3d968589d8 937 #define BR_WDOG_TMROUTH_TIMEROUTHIGH(x) (HW_WDOG_TMROUTH(x).U)
Kojto 90:cb3d968589d8 938
Kojto 90:cb3d968589d8 939 /*! @brief Format value for bitfield WDOG_TMROUTH_TIMEROUTHIGH. */
Kojto 90:cb3d968589d8 940 #define BF_WDOG_TMROUTH_TIMEROUTHIGH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TMROUTH_TIMEROUTHIGH) & BM_WDOG_TMROUTH_TIMEROUTHIGH)
Kojto 90:cb3d968589d8 941
Kojto 90:cb3d968589d8 942 /*! @brief Set the TIMEROUTHIGH field to a new value. */
Kojto 90:cb3d968589d8 943 #define BW_WDOG_TMROUTH_TIMEROUTHIGH(x, v) (HW_WDOG_TMROUTH_WR(x, v))
Kojto 90:cb3d968589d8 944 /*@}*/
Kojto 90:cb3d968589d8 945
Kojto 90:cb3d968589d8 946 /*******************************************************************************
Kojto 90:cb3d968589d8 947 * HW_WDOG_TMROUTL - Watchdog Timer Output Register Low
Kojto 90:cb3d968589d8 948 ******************************************************************************/
Kojto 90:cb3d968589d8 949
Kojto 90:cb3d968589d8 950 /*!
Kojto 90:cb3d968589d8 951 * @brief HW_WDOG_TMROUTL - Watchdog Timer Output Register Low (RW)
Kojto 90:cb3d968589d8 952 *
Kojto 90:cb3d968589d8 953 * Reset value: 0x0000U
Kojto 90:cb3d968589d8 954 *
Kojto 90:cb3d968589d8 955 * During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of
Kojto 90:cb3d968589d8 956 * the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK
Kojto 90:cb3d968589d8 957 * cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following
Kojto 90:cb3d968589d8 958 * the watchdog timer.
Kojto 90:cb3d968589d8 959 */
Kojto 90:cb3d968589d8 960 typedef union _hw_wdog_tmroutl
Kojto 90:cb3d968589d8 961 {
Kojto 90:cb3d968589d8 962 uint16_t U;
Kojto 90:cb3d968589d8 963 struct _hw_wdog_tmroutl_bitfields
Kojto 90:cb3d968589d8 964 {
Kojto 90:cb3d968589d8 965 uint16_t TIMEROUTLOW : 16; /*!< [15:0] */
Kojto 90:cb3d968589d8 966 } B;
Kojto 90:cb3d968589d8 967 } hw_wdog_tmroutl_t;
Kojto 90:cb3d968589d8 968
Kojto 90:cb3d968589d8 969 /*!
Kojto 90:cb3d968589d8 970 * @name Constants and macros for entire WDOG_TMROUTL register
Kojto 90:cb3d968589d8 971 */
Kojto 90:cb3d968589d8 972 /*@{*/
Kojto 90:cb3d968589d8 973 #define HW_WDOG_TMROUTL_ADDR(x) ((x) + 0x12U)
Kojto 90:cb3d968589d8 974
Kojto 90:cb3d968589d8 975 #define HW_WDOG_TMROUTL(x) (*(__IO hw_wdog_tmroutl_t *) HW_WDOG_TMROUTL_ADDR(x))
Kojto 90:cb3d968589d8 976 #define HW_WDOG_TMROUTL_RD(x) (HW_WDOG_TMROUTL(x).U)
Kojto 90:cb3d968589d8 977 #define HW_WDOG_TMROUTL_WR(x, v) (HW_WDOG_TMROUTL(x).U = (v))
Kojto 90:cb3d968589d8 978 #define HW_WDOG_TMROUTL_SET(x, v) (HW_WDOG_TMROUTL_WR(x, HW_WDOG_TMROUTL_RD(x) | (v)))
Kojto 90:cb3d968589d8 979 #define HW_WDOG_TMROUTL_CLR(x, v) (HW_WDOG_TMROUTL_WR(x, HW_WDOG_TMROUTL_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 980 #define HW_WDOG_TMROUTL_TOG(x, v) (HW_WDOG_TMROUTL_WR(x, HW_WDOG_TMROUTL_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 981 /*@}*/
Kojto 90:cb3d968589d8 982
Kojto 90:cb3d968589d8 983 /*
Kojto 90:cb3d968589d8 984 * Constants & macros for individual WDOG_TMROUTL bitfields
Kojto 90:cb3d968589d8 985 */
Kojto 90:cb3d968589d8 986
Kojto 90:cb3d968589d8 987 /*!
Kojto 90:cb3d968589d8 988 * @name Register WDOG_TMROUTL, field TIMEROUTLOW[15:0] (RW)
Kojto 90:cb3d968589d8 989 *
Kojto 90:cb3d968589d8 990 * Shows the value of the lower 16 bits of the watchdog timer.
Kojto 90:cb3d968589d8 991 */
Kojto 90:cb3d968589d8 992 /*@{*/
Kojto 90:cb3d968589d8 993 #define BP_WDOG_TMROUTL_TIMEROUTLOW (0U) /*!< Bit position for WDOG_TMROUTL_TIMEROUTLOW. */
Kojto 90:cb3d968589d8 994 #define BM_WDOG_TMROUTL_TIMEROUTLOW (0xFFFFU) /*!< Bit mask for WDOG_TMROUTL_TIMEROUTLOW. */
Kojto 90:cb3d968589d8 995 #define BS_WDOG_TMROUTL_TIMEROUTLOW (16U) /*!< Bit field size in bits for WDOG_TMROUTL_TIMEROUTLOW. */
Kojto 90:cb3d968589d8 996
Kojto 90:cb3d968589d8 997 /*! @brief Read current value of the WDOG_TMROUTL_TIMEROUTLOW field. */
Kojto 90:cb3d968589d8 998 #define BR_WDOG_TMROUTL_TIMEROUTLOW(x) (HW_WDOG_TMROUTL(x).U)
Kojto 90:cb3d968589d8 999
Kojto 90:cb3d968589d8 1000 /*! @brief Format value for bitfield WDOG_TMROUTL_TIMEROUTLOW. */
Kojto 90:cb3d968589d8 1001 #define BF_WDOG_TMROUTL_TIMEROUTLOW(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TMROUTL_TIMEROUTLOW) & BM_WDOG_TMROUTL_TIMEROUTLOW)
Kojto 90:cb3d968589d8 1002
Kojto 90:cb3d968589d8 1003 /*! @brief Set the TIMEROUTLOW field to a new value. */
Kojto 90:cb3d968589d8 1004 #define BW_WDOG_TMROUTL_TIMEROUTLOW(x, v) (HW_WDOG_TMROUTL_WR(x, v))
Kojto 90:cb3d968589d8 1005 /*@}*/
Kojto 90:cb3d968589d8 1006
Kojto 90:cb3d968589d8 1007 /*******************************************************************************
Kojto 90:cb3d968589d8 1008 * HW_WDOG_RSTCNT - Watchdog Reset Count register
Kojto 90:cb3d968589d8 1009 ******************************************************************************/
Kojto 90:cb3d968589d8 1010
Kojto 90:cb3d968589d8 1011 /*!
Kojto 90:cb3d968589d8 1012 * @brief HW_WDOG_RSTCNT - Watchdog Reset Count register (RW)
Kojto 90:cb3d968589d8 1013 *
Kojto 90:cb3d968589d8 1014 * Reset value: 0x0000U
Kojto 90:cb3d968589d8 1015 */
Kojto 90:cb3d968589d8 1016 typedef union _hw_wdog_rstcnt
Kojto 90:cb3d968589d8 1017 {
Kojto 90:cb3d968589d8 1018 uint16_t U;
Kojto 90:cb3d968589d8 1019 struct _hw_wdog_rstcnt_bitfields
Kojto 90:cb3d968589d8 1020 {
Kojto 90:cb3d968589d8 1021 uint16_t RSTCNT : 16; /*!< [15:0] */
Kojto 90:cb3d968589d8 1022 } B;
Kojto 90:cb3d968589d8 1023 } hw_wdog_rstcnt_t;
Kojto 90:cb3d968589d8 1024
Kojto 90:cb3d968589d8 1025 /*!
Kojto 90:cb3d968589d8 1026 * @name Constants and macros for entire WDOG_RSTCNT register
Kojto 90:cb3d968589d8 1027 */
Kojto 90:cb3d968589d8 1028 /*@{*/
Kojto 90:cb3d968589d8 1029 #define HW_WDOG_RSTCNT_ADDR(x) ((x) + 0x14U)
Kojto 90:cb3d968589d8 1030
Kojto 90:cb3d968589d8 1031 #define HW_WDOG_RSTCNT(x) (*(__IO hw_wdog_rstcnt_t *) HW_WDOG_RSTCNT_ADDR(x))
Kojto 90:cb3d968589d8 1032 #define HW_WDOG_RSTCNT_RD(x) (HW_WDOG_RSTCNT(x).U)
Kojto 90:cb3d968589d8 1033 #define HW_WDOG_RSTCNT_WR(x, v) (HW_WDOG_RSTCNT(x).U = (v))
Kojto 90:cb3d968589d8 1034 #define HW_WDOG_RSTCNT_SET(x, v) (HW_WDOG_RSTCNT_WR(x, HW_WDOG_RSTCNT_RD(x) | (v)))
Kojto 90:cb3d968589d8 1035 #define HW_WDOG_RSTCNT_CLR(x, v) (HW_WDOG_RSTCNT_WR(x, HW_WDOG_RSTCNT_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 1036 #define HW_WDOG_RSTCNT_TOG(x, v) (HW_WDOG_RSTCNT_WR(x, HW_WDOG_RSTCNT_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 1037 /*@}*/
Kojto 90:cb3d968589d8 1038
Kojto 90:cb3d968589d8 1039 /*
Kojto 90:cb3d968589d8 1040 * Constants & macros for individual WDOG_RSTCNT bitfields
Kojto 90:cb3d968589d8 1041 */
Kojto 90:cb3d968589d8 1042
Kojto 90:cb3d968589d8 1043 /*!
Kojto 90:cb3d968589d8 1044 * @name Register WDOG_RSTCNT, field RSTCNT[15:0] (RW)
Kojto 90:cb3d968589d8 1045 *
Kojto 90:cb3d968589d8 1046 * Counts the number of times the watchdog resets the system. This register is
Kojto 90:cb3d968589d8 1047 * reset only on a POR. Writing 1 to the bit to be cleared enables you to clear
Kojto 90:cb3d968589d8 1048 * the contents of this register.
Kojto 90:cb3d968589d8 1049 */
Kojto 90:cb3d968589d8 1050 /*@{*/
Kojto 90:cb3d968589d8 1051 #define BP_WDOG_RSTCNT_RSTCNT (0U) /*!< Bit position for WDOG_RSTCNT_RSTCNT. */
Kojto 90:cb3d968589d8 1052 #define BM_WDOG_RSTCNT_RSTCNT (0xFFFFU) /*!< Bit mask for WDOG_RSTCNT_RSTCNT. */
Kojto 90:cb3d968589d8 1053 #define BS_WDOG_RSTCNT_RSTCNT (16U) /*!< Bit field size in bits for WDOG_RSTCNT_RSTCNT. */
Kojto 90:cb3d968589d8 1054
Kojto 90:cb3d968589d8 1055 /*! @brief Read current value of the WDOG_RSTCNT_RSTCNT field. */
Kojto 90:cb3d968589d8 1056 #define BR_WDOG_RSTCNT_RSTCNT(x) (HW_WDOG_RSTCNT(x).U)
Kojto 90:cb3d968589d8 1057
Kojto 90:cb3d968589d8 1058 /*! @brief Format value for bitfield WDOG_RSTCNT_RSTCNT. */
Kojto 90:cb3d968589d8 1059 #define BF_WDOG_RSTCNT_RSTCNT(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_RSTCNT_RSTCNT) & BM_WDOG_RSTCNT_RSTCNT)
Kojto 90:cb3d968589d8 1060
Kojto 90:cb3d968589d8 1061 /*! @brief Set the RSTCNT field to a new value. */
Kojto 90:cb3d968589d8 1062 #define BW_WDOG_RSTCNT_RSTCNT(x, v) (HW_WDOG_RSTCNT_WR(x, v))
Kojto 90:cb3d968589d8 1063 /*@}*/
Kojto 90:cb3d968589d8 1064
Kojto 90:cb3d968589d8 1065 /*******************************************************************************
Kojto 90:cb3d968589d8 1066 * HW_WDOG_PRESC - Watchdog Prescaler register
Kojto 90:cb3d968589d8 1067 ******************************************************************************/
Kojto 90:cb3d968589d8 1068
Kojto 90:cb3d968589d8 1069 /*!
Kojto 90:cb3d968589d8 1070 * @brief HW_WDOG_PRESC - Watchdog Prescaler register (RW)
Kojto 90:cb3d968589d8 1071 *
Kojto 90:cb3d968589d8 1072 * Reset value: 0x0400U
Kojto 90:cb3d968589d8 1073 */
Kojto 90:cb3d968589d8 1074 typedef union _hw_wdog_presc
Kojto 90:cb3d968589d8 1075 {
Kojto 90:cb3d968589d8 1076 uint16_t U;
Kojto 90:cb3d968589d8 1077 struct _hw_wdog_presc_bitfields
Kojto 90:cb3d968589d8 1078 {
Kojto 90:cb3d968589d8 1079 uint16_t RESERVED0 : 8; /*!< [7:0] */
Kojto 90:cb3d968589d8 1080 uint16_t PRESCVAL : 3; /*!< [10:8] */
Kojto 90:cb3d968589d8 1081 uint16_t RESERVED1 : 5; /*!< [15:11] */
Kojto 90:cb3d968589d8 1082 } B;
Kojto 90:cb3d968589d8 1083 } hw_wdog_presc_t;
Kojto 90:cb3d968589d8 1084
Kojto 90:cb3d968589d8 1085 /*!
Kojto 90:cb3d968589d8 1086 * @name Constants and macros for entire WDOG_PRESC register
Kojto 90:cb3d968589d8 1087 */
Kojto 90:cb3d968589d8 1088 /*@{*/
Kojto 90:cb3d968589d8 1089 #define HW_WDOG_PRESC_ADDR(x) ((x) + 0x16U)
Kojto 90:cb3d968589d8 1090
Kojto 90:cb3d968589d8 1091 #define HW_WDOG_PRESC(x) (*(__IO hw_wdog_presc_t *) HW_WDOG_PRESC_ADDR(x))
Kojto 90:cb3d968589d8 1092 #define HW_WDOG_PRESC_RD(x) (HW_WDOG_PRESC(x).U)
Kojto 90:cb3d968589d8 1093 #define HW_WDOG_PRESC_WR(x, v) (HW_WDOG_PRESC(x).U = (v))
Kojto 90:cb3d968589d8 1094 #define HW_WDOG_PRESC_SET(x, v) (HW_WDOG_PRESC_WR(x, HW_WDOG_PRESC_RD(x) | (v)))
Kojto 90:cb3d968589d8 1095 #define HW_WDOG_PRESC_CLR(x, v) (HW_WDOG_PRESC_WR(x, HW_WDOG_PRESC_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 1096 #define HW_WDOG_PRESC_TOG(x, v) (HW_WDOG_PRESC_WR(x, HW_WDOG_PRESC_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 1097 /*@}*/
Kojto 90:cb3d968589d8 1098
Kojto 90:cb3d968589d8 1099 /*
Kojto 90:cb3d968589d8 1100 * Constants & macros for individual WDOG_PRESC bitfields
Kojto 90:cb3d968589d8 1101 */
Kojto 90:cb3d968589d8 1102
Kojto 90:cb3d968589d8 1103 /*!
Kojto 90:cb3d968589d8 1104 * @name Register WDOG_PRESC, field PRESCVAL[10:8] (RW)
Kojto 90:cb3d968589d8 1105 *
Kojto 90:cb3d968589d8 1106 * 3-bit prescaler for the watchdog clock source. A value of zero indicates no
Kojto 90:cb3d968589d8 1107 * division of the input WDOG clock. The watchdog clock is divided by (PRESCVAL +
Kojto 90:cb3d968589d8 1108 * 1) to provide the prescaled WDOG_CLK.
Kojto 90:cb3d968589d8 1109 */
Kojto 90:cb3d968589d8 1110 /*@{*/
Kojto 90:cb3d968589d8 1111 #define BP_WDOG_PRESC_PRESCVAL (8U) /*!< Bit position for WDOG_PRESC_PRESCVAL. */
Kojto 90:cb3d968589d8 1112 #define BM_WDOG_PRESC_PRESCVAL (0x0700U) /*!< Bit mask for WDOG_PRESC_PRESCVAL. */
Kojto 90:cb3d968589d8 1113 #define BS_WDOG_PRESC_PRESCVAL (3U) /*!< Bit field size in bits for WDOG_PRESC_PRESCVAL. */
Kojto 90:cb3d968589d8 1114
Kojto 90:cb3d968589d8 1115 /*! @brief Read current value of the WDOG_PRESC_PRESCVAL field. */
Kojto 90:cb3d968589d8 1116 #define BR_WDOG_PRESC_PRESCVAL(x) (HW_WDOG_PRESC(x).B.PRESCVAL)
Kojto 90:cb3d968589d8 1117
Kojto 90:cb3d968589d8 1118 /*! @brief Format value for bitfield WDOG_PRESC_PRESCVAL. */
Kojto 90:cb3d968589d8 1119 #define BF_WDOG_PRESC_PRESCVAL(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_PRESC_PRESCVAL) & BM_WDOG_PRESC_PRESCVAL)
Kojto 90:cb3d968589d8 1120
Kojto 90:cb3d968589d8 1121 /*! @brief Set the PRESCVAL field to a new value. */
Kojto 90:cb3d968589d8 1122 #define BW_WDOG_PRESC_PRESCVAL(x, v) (HW_WDOG_PRESC_WR(x, (HW_WDOG_PRESC_RD(x) & ~BM_WDOG_PRESC_PRESCVAL) | BF_WDOG_PRESC_PRESCVAL(v)))
Kojto 90:cb3d968589d8 1123 /*@}*/
Kojto 90:cb3d968589d8 1124
Kojto 90:cb3d968589d8 1125 /*******************************************************************************
Kojto 90:cb3d968589d8 1126 * hw_wdog_t - module struct
Kojto 90:cb3d968589d8 1127 ******************************************************************************/
Kojto 90:cb3d968589d8 1128 /*!
Kojto 90:cb3d968589d8 1129 * @brief All WDOG module registers.
Kojto 90:cb3d968589d8 1130 */
Kojto 90:cb3d968589d8 1131 #pragma pack(1)
Kojto 90:cb3d968589d8 1132 typedef struct _hw_wdog
Kojto 90:cb3d968589d8 1133 {
Kojto 90:cb3d968589d8 1134 __IO hw_wdog_stctrlh_t STCTRLH; /*!< [0x0] Watchdog Status and Control Register High */
Kojto 90:cb3d968589d8 1135 __IO hw_wdog_stctrll_t STCTRLL; /*!< [0x2] Watchdog Status and Control Register Low */
Kojto 90:cb3d968589d8 1136 __IO hw_wdog_tovalh_t TOVALH; /*!< [0x4] Watchdog Time-out Value Register High */
Kojto 90:cb3d968589d8 1137 __IO hw_wdog_tovall_t TOVALL; /*!< [0x6] Watchdog Time-out Value Register Low */
Kojto 90:cb3d968589d8 1138 __IO hw_wdog_winh_t WINH; /*!< [0x8] Watchdog Window Register High */
Kojto 90:cb3d968589d8 1139 __IO hw_wdog_winl_t WINL; /*!< [0xA] Watchdog Window Register Low */
Kojto 90:cb3d968589d8 1140 __IO hw_wdog_refresh_t REFRESH; /*!< [0xC] Watchdog Refresh register */
Kojto 90:cb3d968589d8 1141 __IO hw_wdog_unlock_t UNLOCK; /*!< [0xE] Watchdog Unlock register */
Kojto 90:cb3d968589d8 1142 __IO hw_wdog_tmrouth_t TMROUTH; /*!< [0x10] Watchdog Timer Output Register High */
Kojto 90:cb3d968589d8 1143 __IO hw_wdog_tmroutl_t TMROUTL; /*!< [0x12] Watchdog Timer Output Register Low */
Kojto 90:cb3d968589d8 1144 __IO hw_wdog_rstcnt_t RSTCNT; /*!< [0x14] Watchdog Reset Count register */
Kojto 90:cb3d968589d8 1145 __IO hw_wdog_presc_t PRESC; /*!< [0x16] Watchdog Prescaler register */
Kojto 90:cb3d968589d8 1146 } hw_wdog_t;
Kojto 90:cb3d968589d8 1147 #pragma pack()
Kojto 90:cb3d968589d8 1148
Kojto 90:cb3d968589d8 1149 /*! @brief Macro to access all WDOG registers. */
Kojto 90:cb3d968589d8 1150 /*! @param x WDOG module instance base address. */
Kojto 90:cb3d968589d8 1151 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto 90:cb3d968589d8 1152 * use the '&' operator, like <code>&HW_WDOG(WDOG_BASE)</code>. */
Kojto 90:cb3d968589d8 1153 #define HW_WDOG(x) (*(hw_wdog_t *)(x))
Kojto 90:cb3d968589d8 1154
Kojto 90:cb3d968589d8 1155 #endif /* __HW_WDOG_REGISTERS_H__ */
Kojto 90:cb3d968589d8 1156 /* EOF */