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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_spi.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:: Kojto
Date:: Wed Aug 05 13:16:35 2015 +0100
Revision:: 104:b9ad9a133dc7
Parent:: 90:cb3d968589d8

Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	90:cb3d968589d8	1	/*
Kojto	90:cb3d968589d8	2	** ###################################################################
Kojto	90:cb3d968589d8	3	** Compilers: Keil ARM C/C++ Compiler
Kojto	90:cb3d968589d8	4	** Freescale C/C++ for Embedded ARM
Kojto	90:cb3d968589d8	5	** GNU C Compiler
Kojto	90:cb3d968589d8	6	** IAR ANSI C/C++ Compiler for ARM
Kojto	90:cb3d968589d8	7	**
Kojto	90:cb3d968589d8	8	** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto	90:cb3d968589d8	9	** Version: rev. 2.5, 2014-02-10
Kojto	90:cb3d968589d8	10	** Build: b140604
Kojto	90:cb3d968589d8	11	**
Kojto	90:cb3d968589d8	12	** Abstract:
Kojto	90:cb3d968589d8	13	** Extension to the CMSIS register access layer header.
Kojto	90:cb3d968589d8	14	**
Kojto	90:cb3d968589d8	15	** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto	90:cb3d968589d8	16	** All rights reserved.
Kojto	90:cb3d968589d8	17	**
Kojto	90:cb3d968589d8	18	** Redistribution and use in source and binary forms, with or without modification,
Kojto	90:cb3d968589d8	19	** are permitted provided that the following conditions are met:
Kojto	90:cb3d968589d8	20	**
Kojto	90:cb3d968589d8	21	** o Redistributions of source code must retain the above copyright notice, this list
Kojto	90:cb3d968589d8	22	** of conditions and the following disclaimer.
Kojto	90:cb3d968589d8	23	**
Kojto	90:cb3d968589d8	24	** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto	90:cb3d968589d8	25	** list of conditions and the following disclaimer in the documentation and/or
Kojto	90:cb3d968589d8	26	** other materials provided with the distribution.
Kojto	90:cb3d968589d8	27	**
Kojto	90:cb3d968589d8	28	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto	90:cb3d968589d8	29	** contributors may be used to endorse or promote products derived from this
Kojto	90:cb3d968589d8	30	** software without specific prior written permission.
Kojto	90:cb3d968589d8	31	**
Kojto	90:cb3d968589d8	32	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto	90:cb3d968589d8	33	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto	90:cb3d968589d8	34	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	90:cb3d968589d8	35	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto	90:cb3d968589d8	36	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto	90:cb3d968589d8	37	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto	90:cb3d968589d8	38	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto	90:cb3d968589d8	39	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto	90:cb3d968589d8	40	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto	90:cb3d968589d8	41	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	90:cb3d968589d8	42	**
Kojto	90:cb3d968589d8	43	** http: www.freescale.com
Kojto	90:cb3d968589d8	44	** mail: support@freescale.com
Kojto	90:cb3d968589d8	45	**
Kojto	90:cb3d968589d8	46	** Revisions:
Kojto	90:cb3d968589d8	47	** - rev. 1.0 (2013-08-12)
Kojto	90:cb3d968589d8	48	** Initial version.
Kojto	90:cb3d968589d8	49	** - rev. 2.0 (2013-10-29)
Kojto	90:cb3d968589d8	50	** Register accessor macros added to the memory map.
Kojto	90:cb3d968589d8	51	** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto	90:cb3d968589d8	52	** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto	90:cb3d968589d8	53	** System initialization updated.
Kojto	90:cb3d968589d8	54	** MCG - registers updated.
Kojto	90:cb3d968589d8	55	** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto	90:cb3d968589d8	56	** - rev. 2.1 (2013-10-30)
Kojto	90:cb3d968589d8	57	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto	90:cb3d968589d8	58	** - rev. 2.2 (2013-12-09)
Kojto	90:cb3d968589d8	59	** DMA - EARS register removed.
Kojto	90:cb3d968589d8	60	** AIPS0, AIPS1 - MPRA register updated.
Kojto	90:cb3d968589d8	61	** - rev. 2.3 (2014-01-24)
Kojto	90:cb3d968589d8	62	** Update according to reference manual rev. 2
Kojto	90:cb3d968589d8	63	** ENET, MCG, MCM, SIM, USB - registers updated
Kojto	90:cb3d968589d8	64	** - rev. 2.4 (2014-02-10)
Kojto	90:cb3d968589d8	65	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	66	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	67	** - rev. 2.5 (2014-02-10)
Kojto	90:cb3d968589d8	68	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	69	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	70	** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto	90:cb3d968589d8	71	**
Kojto	90:cb3d968589d8	72	** ###################################################################
Kojto	90:cb3d968589d8	73	*/
Kojto	90:cb3d968589d8	74
Kojto	90:cb3d968589d8	75	/*
Kojto	90:cb3d968589d8	76	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto	90:cb3d968589d8	77	*
Kojto	90:cb3d968589d8	78	* This file was generated automatically and any changes may be lost.
Kojto	90:cb3d968589d8	79	*/
Kojto	90:cb3d968589d8	80	#ifndef __HW_SPI_REGISTERS_H__
Kojto	90:cb3d968589d8	81	#define __HW_SPI_REGISTERS_H__
Kojto	90:cb3d968589d8	82
Kojto	90:cb3d968589d8	83	#include "MK64F12.h"
Kojto	90:cb3d968589d8	84	#include "fsl_bitaccess.h"
Kojto	90:cb3d968589d8	85
Kojto	90:cb3d968589d8	86	/*
Kojto	90:cb3d968589d8	87	* MK64F12 SPI
Kojto	90:cb3d968589d8	88	*
Kojto	90:cb3d968589d8	89	* Serial Peripheral Interface
Kojto	90:cb3d968589d8	90	*
Kojto	90:cb3d968589d8	91	* Registers defined in this header file:
Kojto	90:cb3d968589d8	92	* - HW_SPI_MCR - Module Configuration Register
Kojto	90:cb3d968589d8	93	* - HW_SPI_TCR - Transfer Count Register
Kojto	90:cb3d968589d8	94	* - HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode)
Kojto	90:cb3d968589d8	95	* - HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
Kojto	90:cb3d968589d8	96	* - HW_SPI_SR - Status Register
Kojto	90:cb3d968589d8	97	* - HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register
Kojto	90:cb3d968589d8	98	* - HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode
Kojto	90:cb3d968589d8	99	* - HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
Kojto	90:cb3d968589d8	100	* - HW_SPI_POPR - POP RX FIFO Register
Kojto	90:cb3d968589d8	101	* - HW_SPI_TXFRn - Transmit FIFO Registers
Kojto	90:cb3d968589d8	102	* - HW_SPI_RXFRn - Receive FIFO Registers
Kojto	90:cb3d968589d8	103	*
Kojto	90:cb3d968589d8	104	* - hw_spi_t - Struct containing all module registers.
Kojto	90:cb3d968589d8	105	*/
Kojto	90:cb3d968589d8	106
Kojto	90:cb3d968589d8	107	#define HW_SPI_INSTANCE_COUNT (3U) /!< Number of instances of the SPI module. /
Kojto	90:cb3d968589d8	108	#define HW_SPI0 (0U) /!< Instance number for SPI0. /
Kojto	90:cb3d968589d8	109	#define HW_SPI1 (1U) /!< Instance number for SPI1. /
Kojto	90:cb3d968589d8	110	#define HW_SPI2 (2U) /!< Instance number for SPI2. /
Kojto	90:cb3d968589d8	111
Kojto	90:cb3d968589d8	112	/*******************************************************************************
Kojto	90:cb3d968589d8	113	* HW_SPI_MCR - Module Configuration Register
Kojto	90:cb3d968589d8	114	******************************************************************************/
Kojto	90:cb3d968589d8	115
Kojto	90:cb3d968589d8	116	/*!
Kojto	90:cb3d968589d8	117	* @brief HW_SPI_MCR - Module Configuration Register (RW)
Kojto	90:cb3d968589d8	118	*
Kojto	90:cb3d968589d8	119	* Reset value: 0x00004001U
Kojto	90:cb3d968589d8	120	*
Kojto	90:cb3d968589d8	121	* Contains bits to configure various attributes associated with the module
Kojto	90:cb3d968589d8	122	* operations. The HALT and MDIS bits can be changed at any time, but the effect
Kojto	90:cb3d968589d8	123	* takes place only on the next frame boundary. Only the HALT and MDIS bits in the
Kojto	90:cb3d968589d8	124	* MCR can be changed, while the module is in the Running state.
Kojto	90:cb3d968589d8	125	*/
Kojto	90:cb3d968589d8	126	typedef union _hw_spi_mcr
Kojto	90:cb3d968589d8	127	{
Kojto	90:cb3d968589d8	128	uint32_t U;
Kojto	90:cb3d968589d8	129	struct _hw_spi_mcr_bitfields
Kojto	90:cb3d968589d8	130	{
Kojto	90:cb3d968589d8	131	uint32_t HALT : 1; /!< [0] Halt /
Kojto	90:cb3d968589d8	132	uint32_t RESERVED0 : 7; /!< [7:1] /
Kojto	90:cb3d968589d8	133	uint32_t SMPL_PT : 2; /!< [9:8] Sample Point /
Kojto	90:cb3d968589d8	134	uint32_t CLR_RXF : 1; /!< [10] /
Kojto	90:cb3d968589d8	135	uint32_t CLR_TXF : 1; /!< [11] Clear TX FIFO /
Kojto	90:cb3d968589d8	136	uint32_t DIS_RXF : 1; /!< [12] Disable Receive FIFO /
Kojto	90:cb3d968589d8	137	uint32_t DIS_TXF : 1; /!< [13] Disable Transmit FIFO /
Kojto	90:cb3d968589d8	138	uint32_t MDIS : 1; /!< [14] Module Disable /
Kojto	90:cb3d968589d8	139	uint32_t DOZE : 1; /!< [15] Doze Enable /
Kojto	90:cb3d968589d8	140	uint32_t PCSIS : 6; /*!< [21:16] Peripheral Chip Select x Inactive
Kojto	90:cb3d968589d8	141	* State */
Kojto	90:cb3d968589d8	142	uint32_t RESERVED1 : 2; /!< [23:22] /
Kojto	90:cb3d968589d8	143	uint32_t ROOE : 1; /!< [24] Receive FIFO Overflow Overwrite Enable /
Kojto	90:cb3d968589d8	144	uint32_t PCSSE : 1; /!< [25] Peripheral Chip Select Strobe Enable /
Kojto	90:cb3d968589d8	145	uint32_t MTFE : 1; /!< [26] Modified Timing Format Enable /
Kojto	90:cb3d968589d8	146	uint32_t FRZ : 1; /!< [27] Freeze /
Kojto	90:cb3d968589d8	147	uint32_t DCONF : 2; /!< [29:28] SPI Configuration. /
Kojto	90:cb3d968589d8	148	uint32_t CONT_SCKE : 1; /!< [30] Continuous SCK Enable /
Kojto	90:cb3d968589d8	149	uint32_t MSTR : 1; /!< [31] Master/Slave Mode Select /
Kojto	90:cb3d968589d8	150	} B;
Kojto	90:cb3d968589d8	151	} hw_spi_mcr_t;
Kojto	90:cb3d968589d8	152
Kojto	90:cb3d968589d8	153	/*!
Kojto	90:cb3d968589d8	154	* @name Constants and macros for entire SPI_MCR register
Kojto	90:cb3d968589d8	155	*/
Kojto	90:cb3d968589d8	156	/@{/
Kojto	90:cb3d968589d8	157	#define HW_SPI_MCR_ADDR(x) ((x) + 0x0U)
Kojto	90:cb3d968589d8	158
Kojto	90:cb3d968589d8	159	#define HW_SPI_MCR(x) ((__IO hw_spi_mcr_t ) HW_SPI_MCR_ADDR(x))
Kojto	90:cb3d968589d8	160	#define HW_SPI_MCR_RD(x) (HW_SPI_MCR(x).U)
Kojto	90:cb3d968589d8	161	#define HW_SPI_MCR_WR(x, v) (HW_SPI_MCR(x).U = (v))
Kojto	90:cb3d968589d8	162	#define HW_SPI_MCR_SET(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	163	#define HW_SPI_MCR_CLR(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	164	#define HW_SPI_MCR_TOG(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	165	/@}/
Kojto	90:cb3d968589d8	166
Kojto	90:cb3d968589d8	167	/*
Kojto	90:cb3d968589d8	168	* Constants & macros for individual SPI_MCR bitfields
Kojto	90:cb3d968589d8	169	*/
Kojto	90:cb3d968589d8	170
Kojto	90:cb3d968589d8	171	/*!
Kojto	90:cb3d968589d8	172	* @name Register SPI_MCR, field HALT[0] (RW)
Kojto	90:cb3d968589d8	173	*
Kojto	90:cb3d968589d8	174	* The HALT bit starts and stops frame transfers. See Start and Stop of Module
Kojto	90:cb3d968589d8	175	* transfers
Kojto	90:cb3d968589d8	176	*
Kojto	90:cb3d968589d8	177	* Values:
Kojto	90:cb3d968589d8	178	* - 0 - Start transfers.
Kojto	90:cb3d968589d8	179	* - 1 - Stop transfers.
Kojto	90:cb3d968589d8	180	*/
Kojto	90:cb3d968589d8	181	/@{/
Kojto	90:cb3d968589d8	182	#define BP_SPI_MCR_HALT (0U) /!< Bit position for SPI_MCR_HALT. /
Kojto	90:cb3d968589d8	183	#define BM_SPI_MCR_HALT (0x00000001U) /!< Bit mask for SPI_MCR_HALT. /
Kojto	90:cb3d968589d8	184	#define BS_SPI_MCR_HALT (1U) /!< Bit field size in bits for SPI_MCR_HALT. /
Kojto	90:cb3d968589d8	185
Kojto	90:cb3d968589d8	186	/! @brief Read current value of the SPI_MCR_HALT field. /
Kojto	90:cb3d968589d8	187	#define BR_SPI_MCR_HALT(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT))
Kojto	90:cb3d968589d8	188
Kojto	90:cb3d968589d8	189	/! @brief Format value for bitfield SPI_MCR_HALT. /
Kojto	90:cb3d968589d8	190	#define BF_SPI_MCR_HALT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_HALT) & BM_SPI_MCR_HALT)
Kojto	90:cb3d968589d8	191
Kojto	90:cb3d968589d8	192	/! @brief Set the HALT field to a new value. /
Kojto	90:cb3d968589d8	193	#define BW_SPI_MCR_HALT(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT) = (v))
Kojto	90:cb3d968589d8	194	/@}/
Kojto	90:cb3d968589d8	195
Kojto	90:cb3d968589d8	196	/*!
Kojto	90:cb3d968589d8	197	* @name Register SPI_MCR, field SMPL_PT[9:8] (RW)
Kojto	90:cb3d968589d8	198	*
Kojto	90:cb3d968589d8	199	* Controls when the module master samples SIN in Modified Transfer Format. This
Kojto	90:cb3d968589d8	200	* field is valid only when CPHA bit in CTARn[CPHA] is 0.
Kojto	90:cb3d968589d8	201	*
Kojto	90:cb3d968589d8	202	* Values:
Kojto	90:cb3d968589d8	203	* - 00 - 0 protocol clock cycles between SCK edge and SIN sample
Kojto	90:cb3d968589d8	204	* - 01 - 1 protocol clock cycle between SCK edge and SIN sample
Kojto	90:cb3d968589d8	205	* - 10 - 2 protocol clock cycles between SCK edge and SIN sample
Kojto	90:cb3d968589d8	206	* - 11 - Reserved
Kojto	90:cb3d968589d8	207	*/
Kojto	90:cb3d968589d8	208	/@{/
Kojto	90:cb3d968589d8	209	#define BP_SPI_MCR_SMPL_PT (8U) /!< Bit position for SPI_MCR_SMPL_PT. /
Kojto	90:cb3d968589d8	210	#define BM_SPI_MCR_SMPL_PT (0x00000300U) /!< Bit mask for SPI_MCR_SMPL_PT. /
Kojto	90:cb3d968589d8	211	#define BS_SPI_MCR_SMPL_PT (2U) /!< Bit field size in bits for SPI_MCR_SMPL_PT. /
Kojto	90:cb3d968589d8	212
Kojto	90:cb3d968589d8	213	/! @brief Read current value of the SPI_MCR_SMPL_PT field. /
Kojto	90:cb3d968589d8	214	#define BR_SPI_MCR_SMPL_PT(x) (HW_SPI_MCR(x).B.SMPL_PT)
Kojto	90:cb3d968589d8	215
Kojto	90:cb3d968589d8	216	/! @brief Format value for bitfield SPI_MCR_SMPL_PT. /
Kojto	90:cb3d968589d8	217	#define BF_SPI_MCR_SMPL_PT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_SMPL_PT) & BM_SPI_MCR_SMPL_PT)
Kojto	90:cb3d968589d8	218
Kojto	90:cb3d968589d8	219	/! @brief Set the SMPL_PT field to a new value. /
Kojto	90:cb3d968589d8	220	#define BW_SPI_MCR_SMPL_PT(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_SMPL_PT) \| BF_SPI_MCR_SMPL_PT(v)))
Kojto	90:cb3d968589d8	221	/@}/
Kojto	90:cb3d968589d8	222
Kojto	90:cb3d968589d8	223	/*!
Kojto	90:cb3d968589d8	224	* @name Register SPI_MCR, field CLR_RXF[10] (WORZ)
Kojto	90:cb3d968589d8	225	*
Kojto	90:cb3d968589d8	226	* Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The
Kojto	90:cb3d968589d8	227	* CLR_RXF bit is always read as zero.
Kojto	90:cb3d968589d8	228	*
Kojto	90:cb3d968589d8	229	* Values:
Kojto	90:cb3d968589d8	230	* - 0 - Do not clear the RX FIFO counter.
Kojto	90:cb3d968589d8	231	* - 1 - Clear the RX FIFO counter.
Kojto	90:cb3d968589d8	232	*/
Kojto	90:cb3d968589d8	233	/@{/
Kojto	90:cb3d968589d8	234	#define BP_SPI_MCR_CLR_RXF (10U) /!< Bit position for SPI_MCR_CLR_RXF. /
Kojto	90:cb3d968589d8	235	#define BM_SPI_MCR_CLR_RXF (0x00000400U) /!< Bit mask for SPI_MCR_CLR_RXF. /
Kojto	90:cb3d968589d8	236	#define BS_SPI_MCR_CLR_RXF (1U) /!< Bit field size in bits for SPI_MCR_CLR_RXF. /
Kojto	90:cb3d968589d8	237
Kojto	90:cb3d968589d8	238	/! @brief Format value for bitfield SPI_MCR_CLR_RXF. /
Kojto	90:cb3d968589d8	239	#define BF_SPI_MCR_CLR_RXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_CLR_RXF) & BM_SPI_MCR_CLR_RXF)
Kojto	90:cb3d968589d8	240
Kojto	90:cb3d968589d8	241	/! @brief Set the CLR_RXF field to a new value. /
Kojto	90:cb3d968589d8	242	#define BW_SPI_MCR_CLR_RXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_RXF) = (v))
Kojto	90:cb3d968589d8	243	/@}/
Kojto	90:cb3d968589d8	244
Kojto	90:cb3d968589d8	245	/*!
Kojto	90:cb3d968589d8	246	* @name Register SPI_MCR, field CLR_TXF[11] (WORZ)
Kojto	90:cb3d968589d8	247	*
Kojto	90:cb3d968589d8	248	* Flushes the TX FIFO. Writing a 1 to CLR_TXF clears the TX FIFO Counter. The
Kojto	90:cb3d968589d8	249	* CLR_TXF bit is always read as zero.
Kojto	90:cb3d968589d8	250	*
Kojto	90:cb3d968589d8	251	* Values:
Kojto	90:cb3d968589d8	252	* - 0 - Do not clear the TX FIFO counter.
Kojto	90:cb3d968589d8	253	* - 1 - Clear the TX FIFO counter.
Kojto	90:cb3d968589d8	254	*/
Kojto	90:cb3d968589d8	255	/@{/
Kojto	90:cb3d968589d8	256	#define BP_SPI_MCR_CLR_TXF (11U) /!< Bit position for SPI_MCR_CLR_TXF. /
Kojto	90:cb3d968589d8	257	#define BM_SPI_MCR_CLR_TXF (0x00000800U) /!< Bit mask for SPI_MCR_CLR_TXF. /
Kojto	90:cb3d968589d8	258	#define BS_SPI_MCR_CLR_TXF (1U) /!< Bit field size in bits for SPI_MCR_CLR_TXF. /
Kojto	90:cb3d968589d8	259
Kojto	90:cb3d968589d8	260	/! @brief Format value for bitfield SPI_MCR_CLR_TXF. /
Kojto	90:cb3d968589d8	261	#define BF_SPI_MCR_CLR_TXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_CLR_TXF) & BM_SPI_MCR_CLR_TXF)
Kojto	90:cb3d968589d8	262
Kojto	90:cb3d968589d8	263	/! @brief Set the CLR_TXF field to a new value. /
Kojto	90:cb3d968589d8	264	#define BW_SPI_MCR_CLR_TXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_TXF) = (v))
Kojto	90:cb3d968589d8	265	/@}/
Kojto	90:cb3d968589d8	266
Kojto	90:cb3d968589d8	267	/*!
Kojto	90:cb3d968589d8	268	* @name Register SPI_MCR, field DIS_RXF[12] (RW)
Kojto	90:cb3d968589d8	269	*
Kojto	90:cb3d968589d8	270	* When the RX FIFO is disabled, the receive part of the module operates as a
Kojto	90:cb3d968589d8	271	* simplified double-buffered SPI. This bit can only be written when the MDIS bit
Kojto	90:cb3d968589d8	272	* is cleared.
Kojto	90:cb3d968589d8	273	*
Kojto	90:cb3d968589d8	274	* Values:
Kojto	90:cb3d968589d8	275	* - 0 - RX FIFO is enabled.
Kojto	90:cb3d968589d8	276	* - 1 - RX FIFO is disabled.
Kojto	90:cb3d968589d8	277	*/
Kojto	90:cb3d968589d8	278	/@{/
Kojto	90:cb3d968589d8	279	#define BP_SPI_MCR_DIS_RXF (12U) /!< Bit position for SPI_MCR_DIS_RXF. /
Kojto	90:cb3d968589d8	280	#define BM_SPI_MCR_DIS_RXF (0x00001000U) /!< Bit mask for SPI_MCR_DIS_RXF. /
Kojto	90:cb3d968589d8	281	#define BS_SPI_MCR_DIS_RXF (1U) /!< Bit field size in bits for SPI_MCR_DIS_RXF. /
Kojto	90:cb3d968589d8	282
Kojto	90:cb3d968589d8	283	/! @brief Read current value of the SPI_MCR_DIS_RXF field. /
Kojto	90:cb3d968589d8	284	#define BR_SPI_MCR_DIS_RXF(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF))
Kojto	90:cb3d968589d8	285
Kojto	90:cb3d968589d8	286	/! @brief Format value for bitfield SPI_MCR_DIS_RXF. /
Kojto	90:cb3d968589d8	287	#define BF_SPI_MCR_DIS_RXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_DIS_RXF) & BM_SPI_MCR_DIS_RXF)
Kojto	90:cb3d968589d8	288
Kojto	90:cb3d968589d8	289	/! @brief Set the DIS_RXF field to a new value. /
Kojto	90:cb3d968589d8	290	#define BW_SPI_MCR_DIS_RXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF) = (v))
Kojto	90:cb3d968589d8	291	/@}/
Kojto	90:cb3d968589d8	292
Kojto	90:cb3d968589d8	293	/*!
Kojto	90:cb3d968589d8	294	* @name Register SPI_MCR, field DIS_TXF[13] (RW)
Kojto	90:cb3d968589d8	295	*
Kojto	90:cb3d968589d8	296	* When the TX FIFO is disabled, the transmit part of the module operates as a
Kojto	90:cb3d968589d8	297	* simplified double-buffered SPI. This bit can be written only when the MDIS bit
Kojto	90:cb3d968589d8	298	* is cleared.
Kojto	90:cb3d968589d8	299	*
Kojto	90:cb3d968589d8	300	* Values:
Kojto	90:cb3d968589d8	301	* - 0 - TX FIFO is enabled.
Kojto	90:cb3d968589d8	302	* - 1 - TX FIFO is disabled.
Kojto	90:cb3d968589d8	303	*/
Kojto	90:cb3d968589d8	304	/@{/
Kojto	90:cb3d968589d8	305	#define BP_SPI_MCR_DIS_TXF (13U) /!< Bit position for SPI_MCR_DIS_TXF. /
Kojto	90:cb3d968589d8	306	#define BM_SPI_MCR_DIS_TXF (0x00002000U) /!< Bit mask for SPI_MCR_DIS_TXF. /
Kojto	90:cb3d968589d8	307	#define BS_SPI_MCR_DIS_TXF (1U) /!< Bit field size in bits for SPI_MCR_DIS_TXF. /
Kojto	90:cb3d968589d8	308
Kojto	90:cb3d968589d8	309	/! @brief Read current value of the SPI_MCR_DIS_TXF field. /
Kojto	90:cb3d968589d8	310	#define BR_SPI_MCR_DIS_TXF(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF))
Kojto	90:cb3d968589d8	311
Kojto	90:cb3d968589d8	312	/! @brief Format value for bitfield SPI_MCR_DIS_TXF. /
Kojto	90:cb3d968589d8	313	#define BF_SPI_MCR_DIS_TXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_DIS_TXF) & BM_SPI_MCR_DIS_TXF)
Kojto	90:cb3d968589d8	314
Kojto	90:cb3d968589d8	315	/! @brief Set the DIS_TXF field to a new value. /
Kojto	90:cb3d968589d8	316	#define BW_SPI_MCR_DIS_TXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF) = (v))
Kojto	90:cb3d968589d8	317	/@}/
Kojto	90:cb3d968589d8	318
Kojto	90:cb3d968589d8	319	/*!
Kojto	90:cb3d968589d8	320	* @name Register SPI_MCR, field MDIS[14] (RW)
Kojto	90:cb3d968589d8	321	*
Kojto	90:cb3d968589d8	322	* Allows the clock to be stopped to the non-memory mapped logic in the module
Kojto	90:cb3d968589d8	323	* effectively putting it in a software-controlled power-saving state. The reset
Kojto	90:cb3d968589d8	324	* value of the MDIS bit is parameterized, with a default reset value of 0. When
Kojto	90:cb3d968589d8	325	* the module is used in Slave Mode, we recommend leaving this bit 0, because a
Kojto	90:cb3d968589d8	326	* slave doesn't have control over master transactions.
Kojto	90:cb3d968589d8	327	*
Kojto	90:cb3d968589d8	328	* Values:
Kojto	90:cb3d968589d8	329	* - 0 - Enables the module clocks.
Kojto	90:cb3d968589d8	330	* - 1 - Allows external logic to disable the module clocks.
Kojto	90:cb3d968589d8	331	*/
Kojto	90:cb3d968589d8	332	/@{/
Kojto	90:cb3d968589d8	333	#define BP_SPI_MCR_MDIS (14U) /!< Bit position for SPI_MCR_MDIS. /
Kojto	90:cb3d968589d8	334	#define BM_SPI_MCR_MDIS (0x00004000U) /!< Bit mask for SPI_MCR_MDIS. /
Kojto	90:cb3d968589d8	335	#define BS_SPI_MCR_MDIS (1U) /!< Bit field size in bits for SPI_MCR_MDIS. /
Kojto	90:cb3d968589d8	336
Kojto	90:cb3d968589d8	337	/! @brief Read current value of the SPI_MCR_MDIS field. /
Kojto	90:cb3d968589d8	338	#define BR_SPI_MCR_MDIS(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS))
Kojto	90:cb3d968589d8	339
Kojto	90:cb3d968589d8	340	/! @brief Format value for bitfield SPI_MCR_MDIS. /
Kojto	90:cb3d968589d8	341	#define BF_SPI_MCR_MDIS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_MDIS) & BM_SPI_MCR_MDIS)
Kojto	90:cb3d968589d8	342
Kojto	90:cb3d968589d8	343	/! @brief Set the MDIS field to a new value. /
Kojto	90:cb3d968589d8	344	#define BW_SPI_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS) = (v))
Kojto	90:cb3d968589d8	345	/@}/
Kojto	90:cb3d968589d8	346
Kojto	90:cb3d968589d8	347	/*!
Kojto	90:cb3d968589d8	348	* @name Register SPI_MCR, field DOZE[15] (RW)
Kojto	90:cb3d968589d8	349	*
Kojto	90:cb3d968589d8	350	* Provides support for an externally controlled Doze mode power-saving
Kojto	90:cb3d968589d8	351	* mechanism.
Kojto	90:cb3d968589d8	352	*
Kojto	90:cb3d968589d8	353	* Values:
Kojto	90:cb3d968589d8	354	* - 0 - Doze mode has no effect on the module.
Kojto	90:cb3d968589d8	355	* - 1 - Doze mode disables the module.
Kojto	90:cb3d968589d8	356	*/
Kojto	90:cb3d968589d8	357	/@{/
Kojto	90:cb3d968589d8	358	#define BP_SPI_MCR_DOZE (15U) /!< Bit position for SPI_MCR_DOZE. /
Kojto	90:cb3d968589d8	359	#define BM_SPI_MCR_DOZE (0x00008000U) /!< Bit mask for SPI_MCR_DOZE. /
Kojto	90:cb3d968589d8	360	#define BS_SPI_MCR_DOZE (1U) /!< Bit field size in bits for SPI_MCR_DOZE. /
Kojto	90:cb3d968589d8	361
Kojto	90:cb3d968589d8	362	/! @brief Read current value of the SPI_MCR_DOZE field. /
Kojto	90:cb3d968589d8	363	#define BR_SPI_MCR_DOZE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE))
Kojto	90:cb3d968589d8	364
Kojto	90:cb3d968589d8	365	/! @brief Format value for bitfield SPI_MCR_DOZE. /
Kojto	90:cb3d968589d8	366	#define BF_SPI_MCR_DOZE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_DOZE) & BM_SPI_MCR_DOZE)
Kojto	90:cb3d968589d8	367
Kojto	90:cb3d968589d8	368	/! @brief Set the DOZE field to a new value. /
Kojto	90:cb3d968589d8	369	#define BW_SPI_MCR_DOZE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE) = (v))
Kojto	90:cb3d968589d8	370	/@}/
Kojto	90:cb3d968589d8	371
Kojto	90:cb3d968589d8	372	/*!
Kojto	90:cb3d968589d8	373	* @name Register SPI_MCR, field PCSIS[21:16] (RW)
Kojto	90:cb3d968589d8	374	*
Kojto	90:cb3d968589d8	375	* Determines the inactive state of PCSx.
Kojto	90:cb3d968589d8	376	*
Kojto	90:cb3d968589d8	377	* Values:
Kojto	90:cb3d968589d8	378	* - 0 - The inactive state of PCSx is low.
Kojto	90:cb3d968589d8	379	* - 1 - The inactive state of PCSx is high.
Kojto	90:cb3d968589d8	380	*/
Kojto	90:cb3d968589d8	381	/@{/
Kojto	90:cb3d968589d8	382	#define BP_SPI_MCR_PCSIS (16U) /!< Bit position for SPI_MCR_PCSIS. /
Kojto	90:cb3d968589d8	383	#define BM_SPI_MCR_PCSIS (0x003F0000U) /!< Bit mask for SPI_MCR_PCSIS. /
Kojto	90:cb3d968589d8	384	#define BS_SPI_MCR_PCSIS (6U) /!< Bit field size in bits for SPI_MCR_PCSIS. /
Kojto	90:cb3d968589d8	385
Kojto	90:cb3d968589d8	386	/! @brief Read current value of the SPI_MCR_PCSIS field. /
Kojto	90:cb3d968589d8	387	#define BR_SPI_MCR_PCSIS(x) (HW_SPI_MCR(x).B.PCSIS)
Kojto	90:cb3d968589d8	388
Kojto	90:cb3d968589d8	389	/! @brief Format value for bitfield SPI_MCR_PCSIS. /
Kojto	90:cb3d968589d8	390	#define BF_SPI_MCR_PCSIS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_PCSIS) & BM_SPI_MCR_PCSIS)
Kojto	90:cb3d968589d8	391
Kojto	90:cb3d968589d8	392	/! @brief Set the PCSIS field to a new value. /
Kojto	90:cb3d968589d8	393	#define BW_SPI_MCR_PCSIS(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_PCSIS) \| BF_SPI_MCR_PCSIS(v)))
Kojto	90:cb3d968589d8	394	/@}/
Kojto	90:cb3d968589d8	395
Kojto	90:cb3d968589d8	396	/*!
Kojto	90:cb3d968589d8	397	* @name Register SPI_MCR, field ROOE[24] (RW)
Kojto	90:cb3d968589d8	398	*
Kojto	90:cb3d968589d8	399	* In the RX FIFO overflow condition, configures the module to ignore the
Kojto	90:cb3d968589d8	400	* incoming serial data or overwrite existing data. If the RX FIFO is full and new data
Kojto	90:cb3d968589d8	401	* is received, the data from the transfer, generating the overflow, is ignored
Kojto	90:cb3d968589d8	402	* or shifted into the shift register.
Kojto	90:cb3d968589d8	403	*
Kojto	90:cb3d968589d8	404	* Values:
Kojto	90:cb3d968589d8	405	* - 0 - Incoming data is ignored.
Kojto	90:cb3d968589d8	406	* - 1 - Incoming data is shifted into the shift register.
Kojto	90:cb3d968589d8	407	*/
Kojto	90:cb3d968589d8	408	/@{/
Kojto	90:cb3d968589d8	409	#define BP_SPI_MCR_ROOE (24U) /!< Bit position for SPI_MCR_ROOE. /
Kojto	90:cb3d968589d8	410	#define BM_SPI_MCR_ROOE (0x01000000U) /!< Bit mask for SPI_MCR_ROOE. /
Kojto	90:cb3d968589d8	411	#define BS_SPI_MCR_ROOE (1U) /!< Bit field size in bits for SPI_MCR_ROOE. /
Kojto	90:cb3d968589d8	412
Kojto	90:cb3d968589d8	413	/! @brief Read current value of the SPI_MCR_ROOE field. /
Kojto	90:cb3d968589d8	414	#define BR_SPI_MCR_ROOE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE))
Kojto	90:cb3d968589d8	415
Kojto	90:cb3d968589d8	416	/! @brief Format value for bitfield SPI_MCR_ROOE. /
Kojto	90:cb3d968589d8	417	#define BF_SPI_MCR_ROOE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_ROOE) & BM_SPI_MCR_ROOE)
Kojto	90:cb3d968589d8	418
Kojto	90:cb3d968589d8	419	/! @brief Set the ROOE field to a new value. /
Kojto	90:cb3d968589d8	420	#define BW_SPI_MCR_ROOE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE) = (v))
Kojto	90:cb3d968589d8	421	/@}/
Kojto	90:cb3d968589d8	422
Kojto	90:cb3d968589d8	423	/*!
Kojto	90:cb3d968589d8	424	* @name Register SPI_MCR, field PCSSE[25] (RW)
Kojto	90:cb3d968589d8	425	*
Kojto	90:cb3d968589d8	426	* Enables the PCS5/ PCSS to operate as a PCS Strobe output signal.
Kojto	90:cb3d968589d8	427	*
Kojto	90:cb3d968589d8	428	* Values:
Kojto	90:cb3d968589d8	429	* - 0 - PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
Kojto	90:cb3d968589d8	430	* - 1 - PCS5/ PCSS is used as an active-low PCS Strobe signal.
Kojto	90:cb3d968589d8	431	*/
Kojto	90:cb3d968589d8	432	/@{/
Kojto	90:cb3d968589d8	433	#define BP_SPI_MCR_PCSSE (25U) /!< Bit position for SPI_MCR_PCSSE. /
Kojto	90:cb3d968589d8	434	#define BM_SPI_MCR_PCSSE (0x02000000U) /!< Bit mask for SPI_MCR_PCSSE. /
Kojto	90:cb3d968589d8	435	#define BS_SPI_MCR_PCSSE (1U) /!< Bit field size in bits for SPI_MCR_PCSSE. /
Kojto	90:cb3d968589d8	436
Kojto	90:cb3d968589d8	437	/! @brief Read current value of the SPI_MCR_PCSSE field. /
Kojto	90:cb3d968589d8	438	#define BR_SPI_MCR_PCSSE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE))
Kojto	90:cb3d968589d8	439
Kojto	90:cb3d968589d8	440	/! @brief Format value for bitfield SPI_MCR_PCSSE. /
Kojto	90:cb3d968589d8	441	#define BF_SPI_MCR_PCSSE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_PCSSE) & BM_SPI_MCR_PCSSE)
Kojto	90:cb3d968589d8	442
Kojto	90:cb3d968589d8	443	/! @brief Set the PCSSE field to a new value. /
Kojto	90:cb3d968589d8	444	#define BW_SPI_MCR_PCSSE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE) = (v))
Kojto	90:cb3d968589d8	445	/@}/
Kojto	90:cb3d968589d8	446
Kojto	90:cb3d968589d8	447	/*!
Kojto	90:cb3d968589d8	448	* @name Register SPI_MCR, field MTFE[26] (RW)
Kojto	90:cb3d968589d8	449	*
Kojto	90:cb3d968589d8	450	* Enables a modified transfer format to be used.
Kojto	90:cb3d968589d8	451	*
Kojto	90:cb3d968589d8	452	* Values:
Kojto	90:cb3d968589d8	453	* - 0 - Modified SPI transfer format disabled.
Kojto	90:cb3d968589d8	454	* - 1 - Modified SPI transfer format enabled.
Kojto	90:cb3d968589d8	455	*/
Kojto	90:cb3d968589d8	456	/@{/
Kojto	90:cb3d968589d8	457	#define BP_SPI_MCR_MTFE (26U) /!< Bit position for SPI_MCR_MTFE. /
Kojto	90:cb3d968589d8	458	#define BM_SPI_MCR_MTFE (0x04000000U) /!< Bit mask for SPI_MCR_MTFE. /
Kojto	90:cb3d968589d8	459	#define BS_SPI_MCR_MTFE (1U) /!< Bit field size in bits for SPI_MCR_MTFE. /
Kojto	90:cb3d968589d8	460
Kojto	90:cb3d968589d8	461	/! @brief Read current value of the SPI_MCR_MTFE field. /
Kojto	90:cb3d968589d8	462	#define BR_SPI_MCR_MTFE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE))
Kojto	90:cb3d968589d8	463
Kojto	90:cb3d968589d8	464	/! @brief Format value for bitfield SPI_MCR_MTFE. /
Kojto	90:cb3d968589d8	465	#define BF_SPI_MCR_MTFE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_MTFE) & BM_SPI_MCR_MTFE)
Kojto	90:cb3d968589d8	466
Kojto	90:cb3d968589d8	467	/! @brief Set the MTFE field to a new value. /
Kojto	90:cb3d968589d8	468	#define BW_SPI_MCR_MTFE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE) = (v))
Kojto	90:cb3d968589d8	469	/@}/
Kojto	90:cb3d968589d8	470
Kojto	90:cb3d968589d8	471	/*!
Kojto	90:cb3d968589d8	472	* @name Register SPI_MCR, field FRZ[27] (RW)
Kojto	90:cb3d968589d8	473	*
Kojto	90:cb3d968589d8	474	* Enables transfers to be stopped on the next frame boundary when the device
Kojto	90:cb3d968589d8	475	* enters Debug mode.
Kojto	90:cb3d968589d8	476	*
Kojto	90:cb3d968589d8	477	* Values:
Kojto	90:cb3d968589d8	478	* - 0 - Do not halt serial transfers in Debug mode.
Kojto	90:cb3d968589d8	479	* - 1 - Halt serial transfers in Debug mode.
Kojto	90:cb3d968589d8	480	*/
Kojto	90:cb3d968589d8	481	/@{/
Kojto	90:cb3d968589d8	482	#define BP_SPI_MCR_FRZ (27U) /!< Bit position for SPI_MCR_FRZ. /
Kojto	90:cb3d968589d8	483	#define BM_SPI_MCR_FRZ (0x08000000U) /!< Bit mask for SPI_MCR_FRZ. /
Kojto	90:cb3d968589d8	484	#define BS_SPI_MCR_FRZ (1U) /!< Bit field size in bits for SPI_MCR_FRZ. /
Kojto	90:cb3d968589d8	485
Kojto	90:cb3d968589d8	486	/! @brief Read current value of the SPI_MCR_FRZ field. /
Kojto	90:cb3d968589d8	487	#define BR_SPI_MCR_FRZ(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ))
Kojto	90:cb3d968589d8	488
Kojto	90:cb3d968589d8	489	/! @brief Format value for bitfield SPI_MCR_FRZ. /
Kojto	90:cb3d968589d8	490	#define BF_SPI_MCR_FRZ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_FRZ) & BM_SPI_MCR_FRZ)
Kojto	90:cb3d968589d8	491
Kojto	90:cb3d968589d8	492	/! @brief Set the FRZ field to a new value. /
Kojto	90:cb3d968589d8	493	#define BW_SPI_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ) = (v))
Kojto	90:cb3d968589d8	494	/@}/
Kojto	90:cb3d968589d8	495
Kojto	90:cb3d968589d8	496	/*!
Kojto	90:cb3d968589d8	497	* @name Register SPI_MCR, field DCONF[29:28] (RO)
Kojto	90:cb3d968589d8	498	*
Kojto	90:cb3d968589d8	499	* Selects among the different configurations of the module.
Kojto	90:cb3d968589d8	500	*
Kojto	90:cb3d968589d8	501	* Values:
Kojto	90:cb3d968589d8	502	* - 00 - SPI
Kojto	90:cb3d968589d8	503	* - 01 - Reserved
Kojto	90:cb3d968589d8	504	* - 10 - Reserved
Kojto	90:cb3d968589d8	505	* - 11 - Reserved
Kojto	90:cb3d968589d8	506	*/
Kojto	90:cb3d968589d8	507	/@{/
Kojto	90:cb3d968589d8	508	#define BP_SPI_MCR_DCONF (28U) /!< Bit position for SPI_MCR_DCONF. /
Kojto	90:cb3d968589d8	509	#define BM_SPI_MCR_DCONF (0x30000000U) /!< Bit mask for SPI_MCR_DCONF. /
Kojto	90:cb3d968589d8	510	#define BS_SPI_MCR_DCONF (2U) /!< Bit field size in bits for SPI_MCR_DCONF. /
Kojto	90:cb3d968589d8	511
Kojto	90:cb3d968589d8	512	/! @brief Read current value of the SPI_MCR_DCONF field. /
Kojto	90:cb3d968589d8	513	#define BR_SPI_MCR_DCONF(x) (HW_SPI_MCR(x).B.DCONF)
Kojto	90:cb3d968589d8	514	/@}/
Kojto	90:cb3d968589d8	515
Kojto	90:cb3d968589d8	516	/*!
Kojto	90:cb3d968589d8	517	* @name Register SPI_MCR, field CONT_SCKE[30] (RW)
Kojto	90:cb3d968589d8	518	*
Kojto	90:cb3d968589d8	519	* Enables the Serial Communication Clock (SCK) to run continuously.
Kojto	90:cb3d968589d8	520	*
Kojto	90:cb3d968589d8	521	* Values:
Kojto	90:cb3d968589d8	522	* - 0 - Continuous SCK disabled.
Kojto	90:cb3d968589d8	523	* - 1 - Continuous SCK enabled.
Kojto	90:cb3d968589d8	524	*/
Kojto	90:cb3d968589d8	525	/@{/
Kojto	90:cb3d968589d8	526	#define BP_SPI_MCR_CONT_SCKE (30U) /!< Bit position for SPI_MCR_CONT_SCKE. /
Kojto	90:cb3d968589d8	527	#define BM_SPI_MCR_CONT_SCKE (0x40000000U) /!< Bit mask for SPI_MCR_CONT_SCKE. /
Kojto	90:cb3d968589d8	528	#define BS_SPI_MCR_CONT_SCKE (1U) /!< Bit field size in bits for SPI_MCR_CONT_SCKE. /
Kojto	90:cb3d968589d8	529
Kojto	90:cb3d968589d8	530	/! @brief Read current value of the SPI_MCR_CONT_SCKE field. /
Kojto	90:cb3d968589d8	531	#define BR_SPI_MCR_CONT_SCKE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE))
Kojto	90:cb3d968589d8	532
Kojto	90:cb3d968589d8	533	/! @brief Format value for bitfield SPI_MCR_CONT_SCKE. /
Kojto	90:cb3d968589d8	534	#define BF_SPI_MCR_CONT_SCKE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_CONT_SCKE) & BM_SPI_MCR_CONT_SCKE)
Kojto	90:cb3d968589d8	535
Kojto	90:cb3d968589d8	536	/! @brief Set the CONT_SCKE field to a new value. /
Kojto	90:cb3d968589d8	537	#define BW_SPI_MCR_CONT_SCKE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE) = (v))
Kojto	90:cb3d968589d8	538	/@}/
Kojto	90:cb3d968589d8	539
Kojto	90:cb3d968589d8	540	/*!
Kojto	90:cb3d968589d8	541	* @name Register SPI_MCR, field MSTR[31] (RW)
Kojto	90:cb3d968589d8	542	*
Kojto	90:cb3d968589d8	543	* Enables either Master mode (if supported) or Slave mode (if supported)
Kojto	90:cb3d968589d8	544	* operation.
Kojto	90:cb3d968589d8	545	*
Kojto	90:cb3d968589d8	546	* Values:
Kojto	90:cb3d968589d8	547	* - 0 - Enables Slave mode
Kojto	90:cb3d968589d8	548	* - 1 - Enables Master mode
Kojto	90:cb3d968589d8	549	*/
Kojto	90:cb3d968589d8	550	/@{/
Kojto	90:cb3d968589d8	551	#define BP_SPI_MCR_MSTR (31U) /!< Bit position for SPI_MCR_MSTR. /
Kojto	90:cb3d968589d8	552	#define BM_SPI_MCR_MSTR (0x80000000U) /!< Bit mask for SPI_MCR_MSTR. /
Kojto	90:cb3d968589d8	553	#define BS_SPI_MCR_MSTR (1U) /!< Bit field size in bits for SPI_MCR_MSTR. /
Kojto	90:cb3d968589d8	554
Kojto	90:cb3d968589d8	555	/! @brief Read current value of the SPI_MCR_MSTR field. /
Kojto	90:cb3d968589d8	556	#define BR_SPI_MCR_MSTR(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR))
Kojto	90:cb3d968589d8	557
Kojto	90:cb3d968589d8	558	/! @brief Format value for bitfield SPI_MCR_MSTR. /
Kojto	90:cb3d968589d8	559	#define BF_SPI_MCR_MSTR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_MSTR) & BM_SPI_MCR_MSTR)
Kojto	90:cb3d968589d8	560
Kojto	90:cb3d968589d8	561	/! @brief Set the MSTR field to a new value. /
Kojto	90:cb3d968589d8	562	#define BW_SPI_MCR_MSTR(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR) = (v))
Kojto	90:cb3d968589d8	563	/@}/
Kojto	90:cb3d968589d8	564
Kojto	90:cb3d968589d8	565	/*******************************************************************************
Kojto	90:cb3d968589d8	566	* HW_SPI_TCR - Transfer Count Register
Kojto	90:cb3d968589d8	567	******************************************************************************/
Kojto	90:cb3d968589d8	568
Kojto	90:cb3d968589d8	569	/*!
Kojto	90:cb3d968589d8	570	* @brief HW_SPI_TCR - Transfer Count Register (RW)
Kojto	90:cb3d968589d8	571	*
Kojto	90:cb3d968589d8	572	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	573	*
Kojto	90:cb3d968589d8	574	* TCR contains a counter that indicates the number of SPI transfers made. The
Kojto	90:cb3d968589d8	575	* transfer counter is intended to assist in queue management. Do not write the
Kojto	90:cb3d968589d8	576	* TCR when the module is in the Running state.
Kojto	90:cb3d968589d8	577	*/
Kojto	90:cb3d968589d8	578	typedef union _hw_spi_tcr
Kojto	90:cb3d968589d8	579	{
Kojto	90:cb3d968589d8	580	uint32_t U;
Kojto	90:cb3d968589d8	581	struct _hw_spi_tcr_bitfields
Kojto	90:cb3d968589d8	582	{
Kojto	90:cb3d968589d8	583	uint32_t RESERVED0 : 16; /!< [15:0] /
Kojto	90:cb3d968589d8	584	uint32_t SPI_TCNT : 16; /!< [31:16] SPI Transfer Counter /
Kojto	90:cb3d968589d8	585	} B;
Kojto	90:cb3d968589d8	586	} hw_spi_tcr_t;
Kojto	90:cb3d968589d8	587
Kojto	90:cb3d968589d8	588	/*!
Kojto	90:cb3d968589d8	589	* @name Constants and macros for entire SPI_TCR register
Kojto	90:cb3d968589d8	590	*/
Kojto	90:cb3d968589d8	591	/@{/
Kojto	90:cb3d968589d8	592	#define HW_SPI_TCR_ADDR(x) ((x) + 0x8U)
Kojto	90:cb3d968589d8	593
Kojto	90:cb3d968589d8	594	#define HW_SPI_TCR(x) ((__IO hw_spi_tcr_t ) HW_SPI_TCR_ADDR(x))
Kojto	90:cb3d968589d8	595	#define HW_SPI_TCR_RD(x) (HW_SPI_TCR(x).U)
Kojto	90:cb3d968589d8	596	#define HW_SPI_TCR_WR(x, v) (HW_SPI_TCR(x).U = (v))
Kojto	90:cb3d968589d8	597	#define HW_SPI_TCR_SET(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	598	#define HW_SPI_TCR_CLR(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	599	#define HW_SPI_TCR_TOG(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	600	/@}/
Kojto	90:cb3d968589d8	601
Kojto	90:cb3d968589d8	602	/*
Kojto	90:cb3d968589d8	603	* Constants & macros for individual SPI_TCR bitfields
Kojto	90:cb3d968589d8	604	*/
Kojto	90:cb3d968589d8	605
Kojto	90:cb3d968589d8	606	/*!
Kojto	90:cb3d968589d8	607	* @name Register SPI_TCR, field SPI_TCNT[31:16] (RW)
Kojto	90:cb3d968589d8	608	*
Kojto	90:cb3d968589d8	609	* Counts the number of SPI transfers the module makes. The SPI_TCNT field
Kojto	90:cb3d968589d8	610	* increments every time the last bit of an SPI frame is transmitted. A value written
Kojto	90:cb3d968589d8	611	* to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to zero at
Kojto	90:cb3d968589d8	612	* the beginning of the frame when the CTCNT field is set in the executing SPI
Kojto	90:cb3d968589d8	613	* command. The Transfer Counter wraps around; incrementing the counter past 65535
Kojto	90:cb3d968589d8	614	* resets the counter to zero.
Kojto	90:cb3d968589d8	615	*/
Kojto	90:cb3d968589d8	616	/@{/
Kojto	90:cb3d968589d8	617	#define BP_SPI_TCR_SPI_TCNT (16U) /!< Bit position for SPI_TCR_SPI_TCNT. /
Kojto	90:cb3d968589d8	618	#define BM_SPI_TCR_SPI_TCNT (0xFFFF0000U) /!< Bit mask for SPI_TCR_SPI_TCNT. /
Kojto	90:cb3d968589d8	619	#define BS_SPI_TCR_SPI_TCNT (16U) /!< Bit field size in bits for SPI_TCR_SPI_TCNT. /
Kojto	90:cb3d968589d8	620
Kojto	90:cb3d968589d8	621	/! @brief Read current value of the SPI_TCR_SPI_TCNT field. /
Kojto	90:cb3d968589d8	622	#define BR_SPI_TCR_SPI_TCNT(x) (HW_SPI_TCR(x).B.SPI_TCNT)
Kojto	90:cb3d968589d8	623
Kojto	90:cb3d968589d8	624	/! @brief Format value for bitfield SPI_TCR_SPI_TCNT. /
Kojto	90:cb3d968589d8	625	#define BF_SPI_TCR_SPI_TCNT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_TCR_SPI_TCNT) & BM_SPI_TCR_SPI_TCNT)
Kojto	90:cb3d968589d8	626
Kojto	90:cb3d968589d8	627	/! @brief Set the SPI_TCNT field to a new value. /
Kojto	90:cb3d968589d8	628	#define BW_SPI_TCR_SPI_TCNT(x, v) (HW_SPI_TCR_WR(x, (HW_SPI_TCR_RD(x) & ~BM_SPI_TCR_SPI_TCNT) \| BF_SPI_TCR_SPI_TCNT(v)))
Kojto	90:cb3d968589d8	629	/@}/
Kojto	90:cb3d968589d8	630
Kojto	90:cb3d968589d8	631	/*******************************************************************************
Kojto	90:cb3d968589d8	632	* HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode)
Kojto	90:cb3d968589d8	633	******************************************************************************/
Kojto	90:cb3d968589d8	634
Kojto	90:cb3d968589d8	635	/*!
Kojto	90:cb3d968589d8	636	* @brief HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode) (RW)
Kojto	90:cb3d968589d8	637	*
Kojto	90:cb3d968589d8	638	* Reset value: 0x78000000U
Kojto	90:cb3d968589d8	639	*
Kojto	90:cb3d968589d8	640	* CTAR registers are used to define different transfer attributes. Do not write
Kojto	90:cb3d968589d8	641	* to the CTAR registers while the module is in the Running state. In Master
Kojto	90:cb3d968589d8	642	* mode, the CTAR registers define combinations of transfer attributes such as frame
Kojto	90:cb3d968589d8	643	* size, clock phase and polarity, data bit ordering, baud rate, and various
Kojto	90:cb3d968589d8	644	* delays. In slave mode, a subset of the bitfields in CTAR0 are used to set the
Kojto	90:cb3d968589d8	645	* slave transfer attributes. When the module is configured as an SPI master, the
Kojto	90:cb3d968589d8	646	* CTAS field in the command portion of the TX FIFO entry selects which of the CTAR
Kojto	90:cb3d968589d8	647	* registers is used. When the module is configured as an SPI bus slave, it uses
Kojto	90:cb3d968589d8	648	* the CTAR0 register.
Kojto	90:cb3d968589d8	649	*/
Kojto	90:cb3d968589d8	650	typedef union _hw_spi_ctarn
Kojto	90:cb3d968589d8	651	{
Kojto	90:cb3d968589d8	652	uint32_t U;
Kojto	90:cb3d968589d8	653	struct _hw_spi_ctarn_bitfields
Kojto	90:cb3d968589d8	654	{
Kojto	90:cb3d968589d8	655	uint32_t BR : 4; /!< [3:0] Baud Rate Scaler /
Kojto	90:cb3d968589d8	656	uint32_t DT : 4; /!< [7:4] Delay After Transfer Scaler /
Kojto	90:cb3d968589d8	657	uint32_t ASC : 4; /!< [11:8] After SCK Delay Scaler /
Kojto	90:cb3d968589d8	658	uint32_t CSSCK : 4; /!< [15:12] PCS to SCK Delay Scaler /
Kojto	90:cb3d968589d8	659	uint32_t PBR : 2; /!< [17:16] Baud Rate Prescaler /
Kojto	90:cb3d968589d8	660	uint32_t PDT : 2; /!< [19:18] Delay after Transfer Prescaler /
Kojto	90:cb3d968589d8	661	uint32_t PASC : 2; /!< [21:20] After SCK Delay Prescaler /
Kojto	90:cb3d968589d8	662	uint32_t PCSSCK : 2; /!< [23:22] PCS to SCK Delay Prescaler /
Kojto	90:cb3d968589d8	663	uint32_t LSBFE : 1; /!< [24] LSB First /
Kojto	90:cb3d968589d8	664	uint32_t CPHA : 1; /!< [25] Clock Phase /
Kojto	90:cb3d968589d8	665	uint32_t CPOL : 1; /!< [26] Clock Polarity /
Kojto	90:cb3d968589d8	666	uint32_t FMSZ : 4; /!< [30:27] Frame Size /
Kojto	90:cb3d968589d8	667	uint32_t DBR : 1; /!< [31] Double Baud Rate /
Kojto	90:cb3d968589d8	668	} B;
Kojto	90:cb3d968589d8	669	} hw_spi_ctarn_t;
Kojto	90:cb3d968589d8	670
Kojto	90:cb3d968589d8	671	/*!
Kojto	90:cb3d968589d8	672	* @name Constants and macros for entire SPI_CTARn register
Kojto	90:cb3d968589d8	673	*/
Kojto	90:cb3d968589d8	674	/@{/
Kojto	90:cb3d968589d8	675	#define HW_SPI_CTARn_COUNT (2U)
Kojto	90:cb3d968589d8	676
Kojto	90:cb3d968589d8	677	#define HW_SPI_CTARn_ADDR(x, n) ((x) + 0xCU + (0x4U * (n)))
Kojto	90:cb3d968589d8	678
Kojto	90:cb3d968589d8	679	#define HW_SPI_CTARn(x, n) ((__IO hw_spi_ctarn_t ) HW_SPI_CTARn_ADDR(x, n))
Kojto	90:cb3d968589d8	680	#define HW_SPI_CTARn_RD(x, n) (HW_SPI_CTARn(x, n).U)
Kojto	90:cb3d968589d8	681	#define HW_SPI_CTARn_WR(x, n, v) (HW_SPI_CTARn(x, n).U = (v))
Kojto	90:cb3d968589d8	682	#define HW_SPI_CTARn_SET(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) \| (v)))
Kojto	90:cb3d968589d8	683	#define HW_SPI_CTARn_CLR(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) & ~(v)))
Kojto	90:cb3d968589d8	684	#define HW_SPI_CTARn_TOG(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) ^ (v)))
Kojto	90:cb3d968589d8	685	/@}/
Kojto	90:cb3d968589d8	686
Kojto	90:cb3d968589d8	687	/*
Kojto	90:cb3d968589d8	688	* Constants & macros for individual SPI_CTARn bitfields
Kojto	90:cb3d968589d8	689	*/
Kojto	90:cb3d968589d8	690
Kojto	90:cb3d968589d8	691	/*!
Kojto	90:cb3d968589d8	692	* @name Register SPI_CTARn, field BR[3:0] (RW)
Kojto	90:cb3d968589d8	693	*
Kojto	90:cb3d968589d8	694	* Selects the scaler value for the baud rate. This field is used only in master
Kojto	90:cb3d968589d8	695	* mode. The prescaled protocol clock is divided by the Baud Rate Scaler to
Kojto	90:cb3d968589d8	696	* generate the frequency of the SCK. The baud rate is computed according to the
Kojto	90:cb3d968589d8	697	* following equation: SCK baud rate = (fP /PBR) x [(1+DBR)/BR] The following table
Kojto	90:cb3d968589d8	698	* lists the baud rate scaler values. Baud Rate Scaler CTARn[BR] Baud Rate Scaler
Kojto	90:cb3d968589d8	699	* Value 0000 2 0001 4 0010 6 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256
Kojto	90:cb3d968589d8	700	* 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768
Kojto	90:cb3d968589d8	701	*/
Kojto	90:cb3d968589d8	702	/@{/
Kojto	90:cb3d968589d8	703	#define BP_SPI_CTARn_BR (0U) /!< Bit position for SPI_CTARn_BR. /
Kojto	90:cb3d968589d8	704	#define BM_SPI_CTARn_BR (0x0000000FU) /!< Bit mask for SPI_CTARn_BR. /
Kojto	90:cb3d968589d8	705	#define BS_SPI_CTARn_BR (4U) /!< Bit field size in bits for SPI_CTARn_BR. /
Kojto	90:cb3d968589d8	706
Kojto	90:cb3d968589d8	707	/! @brief Read current value of the SPI_CTARn_BR field. /
Kojto	90:cb3d968589d8	708	#define BR_SPI_CTARn_BR(x, n) (HW_SPI_CTARn(x, n).B.BR)
Kojto	90:cb3d968589d8	709
Kojto	90:cb3d968589d8	710	/! @brief Format value for bitfield SPI_CTARn_BR. /
Kojto	90:cb3d968589d8	711	#define BF_SPI_CTARn_BR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_BR) & BM_SPI_CTARn_BR)
Kojto	90:cb3d968589d8	712
Kojto	90:cb3d968589d8	713	/! @brief Set the BR field to a new value. /
Kojto	90:cb3d968589d8	714	#define BW_SPI_CTARn_BR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_BR) \| BF_SPI_CTARn_BR(v)))
Kojto	90:cb3d968589d8	715	/@}/
Kojto	90:cb3d968589d8	716
Kojto	90:cb3d968589d8	717	/*!
Kojto	90:cb3d968589d8	718	* @name Register SPI_CTARn, field DT[7:4] (RW)
Kojto	90:cb3d968589d8	719	*
Kojto	90:cb3d968589d8	720	* Selects the Delay after Transfer Scaler. This field is used only in master
Kojto	90:cb3d968589d8	721	* mode. The Delay after Transfer is the time between the negation of the PCS
Kojto	90:cb3d968589d8	722	* signal at the end of a frame and the assertion of PCS at the beginning of the next
Kojto	90:cb3d968589d8	723	* frame. In the Continuous Serial Communications Clock operation, the DT value
Kojto	90:cb3d968589d8	724	* is fixed to one SCK clock period, The Delay after Transfer is a multiple of the
Kojto	90:cb3d968589d8	725	* protocol clock period, and it is computed according to the following
Kojto	90:cb3d968589d8	726	* equation: tDT = (1/fP ) x PDT x DT See Delay Scaler Encoding table in CTARn[CSSCK] bit
Kojto	90:cb3d968589d8	727	* field description for scaler values.
Kojto	90:cb3d968589d8	728	*/
Kojto	90:cb3d968589d8	729	/@{/
Kojto	90:cb3d968589d8	730	#define BP_SPI_CTARn_DT (4U) /!< Bit position for SPI_CTARn_DT. /
Kojto	90:cb3d968589d8	731	#define BM_SPI_CTARn_DT (0x000000F0U) /!< Bit mask for SPI_CTARn_DT. /
Kojto	90:cb3d968589d8	732	#define BS_SPI_CTARn_DT (4U) /!< Bit field size in bits for SPI_CTARn_DT. /
Kojto	90:cb3d968589d8	733
Kojto	90:cb3d968589d8	734	/! @brief Read current value of the SPI_CTARn_DT field. /
Kojto	90:cb3d968589d8	735	#define BR_SPI_CTARn_DT(x, n) (HW_SPI_CTARn(x, n).B.DT)
Kojto	90:cb3d968589d8	736
Kojto	90:cb3d968589d8	737	/! @brief Format value for bitfield SPI_CTARn_DT. /
Kojto	90:cb3d968589d8	738	#define BF_SPI_CTARn_DT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_DT) & BM_SPI_CTARn_DT)
Kojto	90:cb3d968589d8	739
Kojto	90:cb3d968589d8	740	/! @brief Set the DT field to a new value. /
Kojto	90:cb3d968589d8	741	#define BW_SPI_CTARn_DT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_DT) \| BF_SPI_CTARn_DT(v)))
Kojto	90:cb3d968589d8	742	/@}/
Kojto	90:cb3d968589d8	743
Kojto	90:cb3d968589d8	744	/*!
Kojto	90:cb3d968589d8	745	* @name Register SPI_CTARn, field ASC[11:8] (RW)
Kojto	90:cb3d968589d8	746	*
Kojto	90:cb3d968589d8	747	* Selects the scaler value for the After SCK Delay. This field is used only in
Kojto	90:cb3d968589d8	748	* master mode. The After SCK Delay is the delay between the last edge of SCK and
Kojto	90:cb3d968589d8	749	* the negation of PCS. The delay is a multiple of the protocol clock period,
Kojto	90:cb3d968589d8	750	* and it is computed according to the following equation: t ASC = (1/fP) x PASC x
Kojto	90:cb3d968589d8	751	* ASC See Delay Scaler Encoding table in CTARn[CSSCK] bit field description for
Kojto	90:cb3d968589d8	752	* scaler values. Refer After SCK Delay (tASC ) for more details.
Kojto	90:cb3d968589d8	753	*/
Kojto	90:cb3d968589d8	754	/@{/
Kojto	90:cb3d968589d8	755	#define BP_SPI_CTARn_ASC (8U) /!< Bit position for SPI_CTARn_ASC. /
Kojto	90:cb3d968589d8	756	#define BM_SPI_CTARn_ASC (0x00000F00U) /!< Bit mask for SPI_CTARn_ASC. /
Kojto	90:cb3d968589d8	757	#define BS_SPI_CTARn_ASC (4U) /!< Bit field size in bits for SPI_CTARn_ASC. /
Kojto	90:cb3d968589d8	758
Kojto	90:cb3d968589d8	759	/! @brief Read current value of the SPI_CTARn_ASC field. /
Kojto	90:cb3d968589d8	760	#define BR_SPI_CTARn_ASC(x, n) (HW_SPI_CTARn(x, n).B.ASC)
Kojto	90:cb3d968589d8	761
Kojto	90:cb3d968589d8	762	/! @brief Format value for bitfield SPI_CTARn_ASC. /
Kojto	90:cb3d968589d8	763	#define BF_SPI_CTARn_ASC(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_ASC) & BM_SPI_CTARn_ASC)
Kojto	90:cb3d968589d8	764
Kojto	90:cb3d968589d8	765	/! @brief Set the ASC field to a new value. /
Kojto	90:cb3d968589d8	766	#define BW_SPI_CTARn_ASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_ASC) \| BF_SPI_CTARn_ASC(v)))
Kojto	90:cb3d968589d8	767	/@}/
Kojto	90:cb3d968589d8	768
Kojto	90:cb3d968589d8	769	/*!
Kojto	90:cb3d968589d8	770	* @name Register SPI_CTARn, field CSSCK[15:12] (RW)
Kojto	90:cb3d968589d8	771	*
Kojto	90:cb3d968589d8	772	* Selects the scaler value for the PCS to SCK delay. This field is used only in
Kojto	90:cb3d968589d8	773	* master mode. The PCS to SCK Delay is the delay between the assertion of PCS
Kojto	90:cb3d968589d8	774	* and the first edge of the SCK. The delay is a multiple of the protocol clock
Kojto	90:cb3d968589d8	775	* period, and it is computed according to the following equation: t CSC = (1/fP )
Kojto	90:cb3d968589d8	776	* x PCSSCK x CSSCK. The following table lists the delay scaler values. Delay
Kojto	90:cb3d968589d8	777	* Scaler Encoding Field Value Delay Scaler Value 0000 2 0001 4 0010 8 0011 16 0100
Kojto	90:cb3d968589d8	778	* 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010 2048 1011 4096 1100 8192
Kojto	90:cb3d968589d8	779	* 1101 16384 1110 32768 1111 65536 Refer PCS to SCK Delay (tCSC ) for more
Kojto	90:cb3d968589d8	780	* details.
Kojto	90:cb3d968589d8	781	*/
Kojto	90:cb3d968589d8	782	/@{/
Kojto	90:cb3d968589d8	783	#define BP_SPI_CTARn_CSSCK (12U) /!< Bit position for SPI_CTARn_CSSCK. /
Kojto	90:cb3d968589d8	784	#define BM_SPI_CTARn_CSSCK (0x0000F000U) /!< Bit mask for SPI_CTARn_CSSCK. /
Kojto	90:cb3d968589d8	785	#define BS_SPI_CTARn_CSSCK (4U) /!< Bit field size in bits for SPI_CTARn_CSSCK. /
Kojto	90:cb3d968589d8	786
Kojto	90:cb3d968589d8	787	/! @brief Read current value of the SPI_CTARn_CSSCK field. /
Kojto	90:cb3d968589d8	788	#define BR_SPI_CTARn_CSSCK(x, n) (HW_SPI_CTARn(x, n).B.CSSCK)
Kojto	90:cb3d968589d8	789
Kojto	90:cb3d968589d8	790	/! @brief Format value for bitfield SPI_CTARn_CSSCK. /
Kojto	90:cb3d968589d8	791	#define BF_SPI_CTARn_CSSCK(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_CSSCK) & BM_SPI_CTARn_CSSCK)
Kojto	90:cb3d968589d8	792
Kojto	90:cb3d968589d8	793	/! @brief Set the CSSCK field to a new value. /
Kojto	90:cb3d968589d8	794	#define BW_SPI_CTARn_CSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_CSSCK) \| BF_SPI_CTARn_CSSCK(v)))
Kojto	90:cb3d968589d8	795	/@}/
Kojto	90:cb3d968589d8	796
Kojto	90:cb3d968589d8	797	/*!
Kojto	90:cb3d968589d8	798	* @name Register SPI_CTARn, field PBR[17:16] (RW)
Kojto	90:cb3d968589d8	799	*
Kojto	90:cb3d968589d8	800	* Selects the prescaler value for the baud rate. This field is used only in
Kojto	90:cb3d968589d8	801	* master mode. The baud rate is the frequency of the SCK. The protocol clock is
Kojto	90:cb3d968589d8	802	* divided by the prescaler value before the baud rate selection takes place. See
Kojto	90:cb3d968589d8	803	* the BR field description for details on how to compute the baud rate.
Kojto	90:cb3d968589d8	804	*
Kojto	90:cb3d968589d8	805	* Values:
Kojto	90:cb3d968589d8	806	* - 00 - Baud Rate Prescaler value is 2.
Kojto	90:cb3d968589d8	807	* - 01 - Baud Rate Prescaler value is 3.
Kojto	90:cb3d968589d8	808	* - 10 - Baud Rate Prescaler value is 5.
Kojto	90:cb3d968589d8	809	* - 11 - Baud Rate Prescaler value is 7.
Kojto	90:cb3d968589d8	810	*/
Kojto	90:cb3d968589d8	811	/@{/
Kojto	90:cb3d968589d8	812	#define BP_SPI_CTARn_PBR (16U) /!< Bit position for SPI_CTARn_PBR. /
Kojto	90:cb3d968589d8	813	#define BM_SPI_CTARn_PBR (0x00030000U) /!< Bit mask for SPI_CTARn_PBR. /
Kojto	90:cb3d968589d8	814	#define BS_SPI_CTARn_PBR (2U) /!< Bit field size in bits for SPI_CTARn_PBR. /
Kojto	90:cb3d968589d8	815
Kojto	90:cb3d968589d8	816	/! @brief Read current value of the SPI_CTARn_PBR field. /
Kojto	90:cb3d968589d8	817	#define BR_SPI_CTARn_PBR(x, n) (HW_SPI_CTARn(x, n).B.PBR)
Kojto	90:cb3d968589d8	818
Kojto	90:cb3d968589d8	819	/! @brief Format value for bitfield SPI_CTARn_PBR. /
Kojto	90:cb3d968589d8	820	#define BF_SPI_CTARn_PBR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PBR) & BM_SPI_CTARn_PBR)
Kojto	90:cb3d968589d8	821
Kojto	90:cb3d968589d8	822	/! @brief Set the PBR field to a new value. /
Kojto	90:cb3d968589d8	823	#define BW_SPI_CTARn_PBR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PBR) \| BF_SPI_CTARn_PBR(v)))
Kojto	90:cb3d968589d8	824	/@}/
Kojto	90:cb3d968589d8	825
Kojto	90:cb3d968589d8	826	/*!
Kojto	90:cb3d968589d8	827	* @name Register SPI_CTARn, field PDT[19:18] (RW)
Kojto	90:cb3d968589d8	828	*
Kojto	90:cb3d968589d8	829	* Selects the prescaler value for the delay between the negation of the PCS
Kojto	90:cb3d968589d8	830	* signal at the end of a frame and the assertion of PCS at the beginning of the
Kojto	90:cb3d968589d8	831	* next frame. The PDT field is only used in master mode. See the DT field
Kojto	90:cb3d968589d8	832	* description for details on how to compute the Delay after Transfer. Refer Delay after
Kojto	90:cb3d968589d8	833	* Transfer (tDT ) for more details.
Kojto	90:cb3d968589d8	834	*
Kojto	90:cb3d968589d8	835	* Values:
Kojto	90:cb3d968589d8	836	* - 00 - Delay after Transfer Prescaler value is 1.
Kojto	90:cb3d968589d8	837	* - 01 - Delay after Transfer Prescaler value is 3.
Kojto	90:cb3d968589d8	838	* - 10 - Delay after Transfer Prescaler value is 5.
Kojto	90:cb3d968589d8	839	* - 11 - Delay after Transfer Prescaler value is 7.
Kojto	90:cb3d968589d8	840	*/
Kojto	90:cb3d968589d8	841	/@{/
Kojto	90:cb3d968589d8	842	#define BP_SPI_CTARn_PDT (18U) /!< Bit position for SPI_CTARn_PDT. /
Kojto	90:cb3d968589d8	843	#define BM_SPI_CTARn_PDT (0x000C0000U) /!< Bit mask for SPI_CTARn_PDT. /
Kojto	90:cb3d968589d8	844	#define BS_SPI_CTARn_PDT (2U) /!< Bit field size in bits for SPI_CTARn_PDT. /
Kojto	90:cb3d968589d8	845
Kojto	90:cb3d968589d8	846	/! @brief Read current value of the SPI_CTARn_PDT field. /
Kojto	90:cb3d968589d8	847	#define BR_SPI_CTARn_PDT(x, n) (HW_SPI_CTARn(x, n).B.PDT)
Kojto	90:cb3d968589d8	848
Kojto	90:cb3d968589d8	849	/! @brief Format value for bitfield SPI_CTARn_PDT. /
Kojto	90:cb3d968589d8	850	#define BF_SPI_CTARn_PDT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PDT) & BM_SPI_CTARn_PDT)
Kojto	90:cb3d968589d8	851
Kojto	90:cb3d968589d8	852	/! @brief Set the PDT field to a new value. /
Kojto	90:cb3d968589d8	853	#define BW_SPI_CTARn_PDT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PDT) \| BF_SPI_CTARn_PDT(v)))
Kojto	90:cb3d968589d8	854	/@}/
Kojto	90:cb3d968589d8	855
Kojto	90:cb3d968589d8	856	/*!
Kojto	90:cb3d968589d8	857	* @name Register SPI_CTARn, field PASC[21:20] (RW)
Kojto	90:cb3d968589d8	858	*
Kojto	90:cb3d968589d8	859	* Selects the prescaler value for the delay between the last edge of SCK and
Kojto	90:cb3d968589d8	860	* the negation of PCS. See the ASC field description for information on how to
Kojto	90:cb3d968589d8	861	* compute the After SCK Delay. Refer After SCK Delay (tASC ) for more details.
Kojto	90:cb3d968589d8	862	*
Kojto	90:cb3d968589d8	863	* Values:
Kojto	90:cb3d968589d8	864	* - 00 - Delay after Transfer Prescaler value is 1.
Kojto	90:cb3d968589d8	865	* - 01 - Delay after Transfer Prescaler value is 3.
Kojto	90:cb3d968589d8	866	* - 10 - Delay after Transfer Prescaler value is 5.
Kojto	90:cb3d968589d8	867	* - 11 - Delay after Transfer Prescaler value is 7.
Kojto	90:cb3d968589d8	868	*/
Kojto	90:cb3d968589d8	869	/@{/
Kojto	90:cb3d968589d8	870	#define BP_SPI_CTARn_PASC (20U) /!< Bit position for SPI_CTARn_PASC. /
Kojto	90:cb3d968589d8	871	#define BM_SPI_CTARn_PASC (0x00300000U) /!< Bit mask for SPI_CTARn_PASC. /
Kojto	90:cb3d968589d8	872	#define BS_SPI_CTARn_PASC (2U) /!< Bit field size in bits for SPI_CTARn_PASC. /
Kojto	90:cb3d968589d8	873
Kojto	90:cb3d968589d8	874	/! @brief Read current value of the SPI_CTARn_PASC field. /
Kojto	90:cb3d968589d8	875	#define BR_SPI_CTARn_PASC(x, n) (HW_SPI_CTARn(x, n).B.PASC)
Kojto	90:cb3d968589d8	876
Kojto	90:cb3d968589d8	877	/! @brief Format value for bitfield SPI_CTARn_PASC. /
Kojto	90:cb3d968589d8	878	#define BF_SPI_CTARn_PASC(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PASC) & BM_SPI_CTARn_PASC)
Kojto	90:cb3d968589d8	879
Kojto	90:cb3d968589d8	880	/! @brief Set the PASC field to a new value. /
Kojto	90:cb3d968589d8	881	#define BW_SPI_CTARn_PASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PASC) \| BF_SPI_CTARn_PASC(v)))
Kojto	90:cb3d968589d8	882	/@}/
Kojto	90:cb3d968589d8	883
Kojto	90:cb3d968589d8	884	/*!
Kojto	90:cb3d968589d8	885	* @name Register SPI_CTARn, field PCSSCK[23:22] (RW)
Kojto	90:cb3d968589d8	886	*
Kojto	90:cb3d968589d8	887	* Selects the prescaler value for the delay between assertion of PCS and the
Kojto	90:cb3d968589d8	888	* first edge of the SCK. See the CSSCK field description for information on how to
Kojto	90:cb3d968589d8	889	* compute the PCS to SCK Delay. Refer PCS to SCK Delay (tCSC ) for more details.
Kojto	90:cb3d968589d8	890	*
Kojto	90:cb3d968589d8	891	* Values:
Kojto	90:cb3d968589d8	892	* - 00 - PCS to SCK Prescaler value is 1.
Kojto	90:cb3d968589d8	893	* - 01 - PCS to SCK Prescaler value is 3.
Kojto	90:cb3d968589d8	894	* - 10 - PCS to SCK Prescaler value is 5.
Kojto	90:cb3d968589d8	895	* - 11 - PCS to SCK Prescaler value is 7.
Kojto	90:cb3d968589d8	896	*/
Kojto	90:cb3d968589d8	897	/@{/
Kojto	90:cb3d968589d8	898	#define BP_SPI_CTARn_PCSSCK (22U) /!< Bit position for SPI_CTARn_PCSSCK. /
Kojto	90:cb3d968589d8	899	#define BM_SPI_CTARn_PCSSCK (0x00C00000U) /!< Bit mask for SPI_CTARn_PCSSCK. /
Kojto	90:cb3d968589d8	900	#define BS_SPI_CTARn_PCSSCK (2U) /!< Bit field size in bits for SPI_CTARn_PCSSCK. /
Kojto	90:cb3d968589d8	901
Kojto	90:cb3d968589d8	902	/! @brief Read current value of the SPI_CTARn_PCSSCK field. /
Kojto	90:cb3d968589d8	903	#define BR_SPI_CTARn_PCSSCK(x, n) (HW_SPI_CTARn(x, n).B.PCSSCK)
Kojto	90:cb3d968589d8	904
Kojto	90:cb3d968589d8	905	/! @brief Format value for bitfield SPI_CTARn_PCSSCK. /
Kojto	90:cb3d968589d8	906	#define BF_SPI_CTARn_PCSSCK(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PCSSCK) & BM_SPI_CTARn_PCSSCK)
Kojto	90:cb3d968589d8	907
Kojto	90:cb3d968589d8	908	/! @brief Set the PCSSCK field to a new value. /
Kojto	90:cb3d968589d8	909	#define BW_SPI_CTARn_PCSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PCSSCK) \| BF_SPI_CTARn_PCSSCK(v)))
Kojto	90:cb3d968589d8	910	/@}/
Kojto	90:cb3d968589d8	911
Kojto	90:cb3d968589d8	912	/*!
Kojto	90:cb3d968589d8	913	* @name Register SPI_CTARn, field LSBFE[24] (RW)
Kojto	90:cb3d968589d8	914	*
Kojto	90:cb3d968589d8	915	* Specifies whether the LSB or MSB of the frame is transferred first.
Kojto	90:cb3d968589d8	916	*
Kojto	90:cb3d968589d8	917	* Values:
Kojto	90:cb3d968589d8	918	* - 0 - Data is transferred MSB first.
Kojto	90:cb3d968589d8	919	* - 1 - Data is transferred LSB first.
Kojto	90:cb3d968589d8	920	*/
Kojto	90:cb3d968589d8	921	/@{/
Kojto	90:cb3d968589d8	922	#define BP_SPI_CTARn_LSBFE (24U) /!< Bit position for SPI_CTARn_LSBFE. /
Kojto	90:cb3d968589d8	923	#define BM_SPI_CTARn_LSBFE (0x01000000U) /!< Bit mask for SPI_CTARn_LSBFE. /
Kojto	90:cb3d968589d8	924	#define BS_SPI_CTARn_LSBFE (1U) /!< Bit field size in bits for SPI_CTARn_LSBFE. /
Kojto	90:cb3d968589d8	925
Kojto	90:cb3d968589d8	926	/! @brief Read current value of the SPI_CTARn_LSBFE field. /
Kojto	90:cb3d968589d8	927	#define BR_SPI_CTARn_LSBFE(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE))
Kojto	90:cb3d968589d8	928
Kojto	90:cb3d968589d8	929	/! @brief Format value for bitfield SPI_CTARn_LSBFE. /
Kojto	90:cb3d968589d8	930	#define BF_SPI_CTARn_LSBFE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_LSBFE) & BM_SPI_CTARn_LSBFE)
Kojto	90:cb3d968589d8	931
Kojto	90:cb3d968589d8	932	/! @brief Set the LSBFE field to a new value. /
Kojto	90:cb3d968589d8	933	#define BW_SPI_CTARn_LSBFE(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE) = (v))
Kojto	90:cb3d968589d8	934	/@}/
Kojto	90:cb3d968589d8	935
Kojto	90:cb3d968589d8	936	/*!
Kojto	90:cb3d968589d8	937	* @name Register SPI_CTARn, field CPHA[25] (RW)
Kojto	90:cb3d968589d8	938	*
Kojto	90:cb3d968589d8	939	* Selects which edge of SCK causes data to change and which edge causes data to
Kojto	90:cb3d968589d8	940	* be captured. This bit is used in both master and slave mode. For successful
Kojto	90:cb3d968589d8	941	* communication between serial devices, the devices must have identical clock
Kojto	90:cb3d968589d8	942	* phase settings. In Continuous SCK mode, the bit value is ignored and the
Kojto	90:cb3d968589d8	943	* transfers are done as if the CPHA bit is set to 1.
Kojto	90:cb3d968589d8	944	*
Kojto	90:cb3d968589d8	945	* Values:
Kojto	90:cb3d968589d8	946	* - 0 - Data is captured on the leading edge of SCK and changed on the
Kojto	90:cb3d968589d8	947	* following edge.
Kojto	90:cb3d968589d8	948	* - 1 - Data is changed on the leading edge of SCK and captured on the
Kojto	90:cb3d968589d8	949	* following edge.
Kojto	90:cb3d968589d8	950	*/
Kojto	90:cb3d968589d8	951	/@{/
Kojto	90:cb3d968589d8	952	#define BP_SPI_CTARn_CPHA (25U) /!< Bit position for SPI_CTARn_CPHA. /
Kojto	90:cb3d968589d8	953	#define BM_SPI_CTARn_CPHA (0x02000000U) /!< Bit mask for SPI_CTARn_CPHA. /
Kojto	90:cb3d968589d8	954	#define BS_SPI_CTARn_CPHA (1U) /!< Bit field size in bits for SPI_CTARn_CPHA. /
Kojto	90:cb3d968589d8	955
Kojto	90:cb3d968589d8	956	/! @brief Read current value of the SPI_CTARn_CPHA field. /
Kojto	90:cb3d968589d8	957	#define BR_SPI_CTARn_CPHA(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA))
Kojto	90:cb3d968589d8	958
Kojto	90:cb3d968589d8	959	/! @brief Format value for bitfield SPI_CTARn_CPHA. /
Kojto	90:cb3d968589d8	960	#define BF_SPI_CTARn_CPHA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_CPHA) & BM_SPI_CTARn_CPHA)
Kojto	90:cb3d968589d8	961
Kojto	90:cb3d968589d8	962	/! @brief Set the CPHA field to a new value. /
Kojto	90:cb3d968589d8	963	#define BW_SPI_CTARn_CPHA(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA) = (v))
Kojto	90:cb3d968589d8	964	/@}/
Kojto	90:cb3d968589d8	965
Kojto	90:cb3d968589d8	966	/*!
Kojto	90:cb3d968589d8	967	* @name Register SPI_CTARn, field CPOL[26] (RW)
Kojto	90:cb3d968589d8	968	*
Kojto	90:cb3d968589d8	969	* Selects the inactive state of the Serial Communications Clock (SCK). This bit
Kojto	90:cb3d968589d8	970	* is used in both master and slave mode. For successful communication between
Kojto	90:cb3d968589d8	971	* serial devices, the devices must have identical clock polarities. When the
Kojto	90:cb3d968589d8	972	* Continuous Selection Format is selected, switching between clock polarities
Kojto	90:cb3d968589d8	973	* without stopping the module can cause errors in the transfer due to the peripheral
Kojto	90:cb3d968589d8	974	* device interpreting the switch of clock polarity as a valid clock edge. In case
Kojto	90:cb3d968589d8	975	* of continous sck mode, when the module goes in low power mode(disabled),
Kojto	90:cb3d968589d8	976	* inactive state of sck is not guaranted.
Kojto	90:cb3d968589d8	977	*
Kojto	90:cb3d968589d8	978	* Values:
Kojto	90:cb3d968589d8	979	* - 0 - The inactive state value of SCK is low.
Kojto	90:cb3d968589d8	980	* - 1 - The inactive state value of SCK is high.
Kojto	90:cb3d968589d8	981	*/
Kojto	90:cb3d968589d8	982	/@{/
Kojto	90:cb3d968589d8	983	#define BP_SPI_CTARn_CPOL (26U) /!< Bit position for SPI_CTARn_CPOL. /
Kojto	90:cb3d968589d8	984	#define BM_SPI_CTARn_CPOL (0x04000000U) /!< Bit mask for SPI_CTARn_CPOL. /
Kojto	90:cb3d968589d8	985	#define BS_SPI_CTARn_CPOL (1U) /!< Bit field size in bits for SPI_CTARn_CPOL. /
Kojto	90:cb3d968589d8	986
Kojto	90:cb3d968589d8	987	/! @brief Read current value of the SPI_CTARn_CPOL field. /
Kojto	90:cb3d968589d8	988	#define BR_SPI_CTARn_CPOL(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL))
Kojto	90:cb3d968589d8	989
Kojto	90:cb3d968589d8	990	/! @brief Format value for bitfield SPI_CTARn_CPOL. /
Kojto	90:cb3d968589d8	991	#define BF_SPI_CTARn_CPOL(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_CPOL) & BM_SPI_CTARn_CPOL)
Kojto	90:cb3d968589d8	992
Kojto	90:cb3d968589d8	993	/! @brief Set the CPOL field to a new value. /
Kojto	90:cb3d968589d8	994	#define BW_SPI_CTARn_CPOL(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL) = (v))
Kojto	90:cb3d968589d8	995	/@}/
Kojto	90:cb3d968589d8	996
Kojto	90:cb3d968589d8	997	/*!
Kojto	90:cb3d968589d8	998	* @name Register SPI_CTARn, field FMSZ[30:27] (RW)
Kojto	90:cb3d968589d8	999	*
Kojto	90:cb3d968589d8	1000	* The number of bits transferred per frame is equal to the FMSZ value plus 1.
Kojto	90:cb3d968589d8	1001	* Regardless of the transmission mode, the minimum valid frame size value is 4.
Kojto	90:cb3d968589d8	1002	*/
Kojto	90:cb3d968589d8	1003	/@{/
Kojto	90:cb3d968589d8	1004	#define BP_SPI_CTARn_FMSZ (27U) /!< Bit position for SPI_CTARn_FMSZ. /
Kojto	90:cb3d968589d8	1005	#define BM_SPI_CTARn_FMSZ (0x78000000U) /!< Bit mask for SPI_CTARn_FMSZ. /
Kojto	90:cb3d968589d8	1006	#define BS_SPI_CTARn_FMSZ (4U) /!< Bit field size in bits for SPI_CTARn_FMSZ. /
Kojto	90:cb3d968589d8	1007
Kojto	90:cb3d968589d8	1008	/! @brief Read current value of the SPI_CTARn_FMSZ field. /
Kojto	90:cb3d968589d8	1009	#define BR_SPI_CTARn_FMSZ(x, n) (HW_SPI_CTARn(x, n).B.FMSZ)
Kojto	90:cb3d968589d8	1010
Kojto	90:cb3d968589d8	1011	/! @brief Format value for bitfield SPI_CTARn_FMSZ. /
Kojto	90:cb3d968589d8	1012	#define BF_SPI_CTARn_FMSZ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_FMSZ) & BM_SPI_CTARn_FMSZ)
Kojto	90:cb3d968589d8	1013
Kojto	90:cb3d968589d8	1014	/! @brief Set the FMSZ field to a new value. /
Kojto	90:cb3d968589d8	1015	#define BW_SPI_CTARn_FMSZ(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_FMSZ) \| BF_SPI_CTARn_FMSZ(v)))
Kojto	90:cb3d968589d8	1016	/@}/
Kojto	90:cb3d968589d8	1017
Kojto	90:cb3d968589d8	1018	/*!
Kojto	90:cb3d968589d8	1019	* @name Register SPI_CTARn, field DBR[31] (RW)
Kojto	90:cb3d968589d8	1020	*
Kojto	90:cb3d968589d8	1021	* Doubles the effective baud rate of the Serial Communications Clock (SCK).
Kojto	90:cb3d968589d8	1022	* This field is used only in master mode. It effectively halves the Baud Rate
Kojto	90:cb3d968589d8	1023	* division ratio, supporting faster frequencies, and odd division ratios for the
Kojto	90:cb3d968589d8	1024	* Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the
Kojto	90:cb3d968589d8	1025	* Serial Communications Clock (SCK) depends on the value in the Baud Rate
Kojto	90:cb3d968589d8	1026	* Prescaler and the Clock Phase bit as listed in the following table. See the BR field
Kojto	90:cb3d968589d8	1027	* description for details on how to compute the baud rate. SPI SCK Duty Cycle
Kojto	90:cb3d968589d8	1028	* DBR CPHA PBR SCK Duty Cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10
Kojto	90:cb3d968589d8	1029	* 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43
Kojto	90:cb3d968589d8	1030	*
Kojto	90:cb3d968589d8	1031	* Values:
Kojto	90:cb3d968589d8	1032	* - 0 - The baud rate is computed normally with a 50/50 duty cycle.
Kojto	90:cb3d968589d8	1033	* - 1 - The baud rate is doubled with the duty cycle depending on the Baud Rate
Kojto	90:cb3d968589d8	1034	* Prescaler.
Kojto	90:cb3d968589d8	1035	*/
Kojto	90:cb3d968589d8	1036	/@{/
Kojto	90:cb3d968589d8	1037	#define BP_SPI_CTARn_DBR (31U) /!< Bit position for SPI_CTARn_DBR. /
Kojto	90:cb3d968589d8	1038	#define BM_SPI_CTARn_DBR (0x80000000U) /!< Bit mask for SPI_CTARn_DBR. /
Kojto	90:cb3d968589d8	1039	#define BS_SPI_CTARn_DBR (1U) /!< Bit field size in bits for SPI_CTARn_DBR. /
Kojto	90:cb3d968589d8	1040
Kojto	90:cb3d968589d8	1041	/! @brief Read current value of the SPI_CTARn_DBR field. /
Kojto	90:cb3d968589d8	1042	#define BR_SPI_CTARn_DBR(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR))
Kojto	90:cb3d968589d8	1043
Kojto	90:cb3d968589d8	1044	/! @brief Format value for bitfield SPI_CTARn_DBR. /
Kojto	90:cb3d968589d8	1045	#define BF_SPI_CTARn_DBR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_DBR) & BM_SPI_CTARn_DBR)
Kojto	90:cb3d968589d8	1046
Kojto	90:cb3d968589d8	1047	/! @brief Set the DBR field to a new value. /
Kojto	90:cb3d968589d8	1048	#define BW_SPI_CTARn_DBR(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR) = (v))
Kojto	90:cb3d968589d8	1049	/@}/
Kojto	90:cb3d968589d8	1050	/*******************************************************************************
Kojto	90:cb3d968589d8	1051	* HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
Kojto	90:cb3d968589d8	1052	******************************************************************************/
Kojto	90:cb3d968589d8	1053
Kojto	90:cb3d968589d8	1054	/*!
Kojto	90:cb3d968589d8	1055	* @brief HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) (RW)
Kojto	90:cb3d968589d8	1056	*
Kojto	90:cb3d968589d8	1057	* Reset value: 0x78000000U
Kojto	90:cb3d968589d8	1058	*
Kojto	90:cb3d968589d8	1059	* When the module is configured as an SPI bus slave, the CTAR0 register is used.
Kojto	90:cb3d968589d8	1060	*/
Kojto	90:cb3d968589d8	1061	typedef union _hw_spi_ctarn_slave
Kojto	90:cb3d968589d8	1062	{
Kojto	90:cb3d968589d8	1063	uint32_t U;
Kojto	90:cb3d968589d8	1064	struct _hw_spi_ctarn_slave_bitfields
Kojto	90:cb3d968589d8	1065	{
Kojto	90:cb3d968589d8	1066	uint32_t RESERVED0 : 25; /!< [24:0] /
Kojto	90:cb3d968589d8	1067	uint32_t CPHA : 1; /!< [25] Clock Phase /
Kojto	90:cb3d968589d8	1068	uint32_t CPOL : 1; /!< [26] Clock Polarity /
Kojto	90:cb3d968589d8	1069	uint32_t FMSZ : 5; /!< [31:27] Frame Size /
Kojto	90:cb3d968589d8	1070	} B;
Kojto	90:cb3d968589d8	1071	} hw_spi_ctarn_slave_t;
Kojto	90:cb3d968589d8	1072
Kojto	90:cb3d968589d8	1073	/*!
Kojto	90:cb3d968589d8	1074	* @name Constants and macros for entire SPI_CTARn_SLAVE register
Kojto	90:cb3d968589d8	1075	*/
Kojto	90:cb3d968589d8	1076	/@{/
Kojto	90:cb3d968589d8	1077	#define HW_SPI_CTARn_SLAVE_COUNT (1U)
Kojto	90:cb3d968589d8	1078
Kojto	90:cb3d968589d8	1079	#define HW_SPI_CTARn_SLAVE_ADDR(x, n) ((x) + 0xCU + (0x4U * (n)))
Kojto	90:cb3d968589d8	1080
Kojto	90:cb3d968589d8	1081	#define HW_SPI_CTARn_SLAVE(x, n) ((__IO hw_spi_ctarn_slave_t ) HW_SPI_CTARn_SLAVE_ADDR(x, n))
Kojto	90:cb3d968589d8	1082	#define HW_SPI_CTARn_SLAVE_RD(x, n) (HW_SPI_CTARn_SLAVE(x, n).U)
Kojto	90:cb3d968589d8	1083	#define HW_SPI_CTARn_SLAVE_WR(x, n, v) (HW_SPI_CTARn_SLAVE(x, n).U = (v))
Kojto	90:cb3d968589d8	1084	#define HW_SPI_CTARn_SLAVE_SET(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) \| (v)))
Kojto	90:cb3d968589d8	1085	#define HW_SPI_CTARn_SLAVE_CLR(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) & ~(v)))
Kojto	90:cb3d968589d8	1086	#define HW_SPI_CTARn_SLAVE_TOG(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) ^ (v)))
Kojto	90:cb3d968589d8	1087	/@}/
Kojto	90:cb3d968589d8	1088
Kojto	90:cb3d968589d8	1089	/*
Kojto	90:cb3d968589d8	1090	* Constants & macros for individual SPI_CTARn_SLAVE bitfields
Kojto	90:cb3d968589d8	1091	*/
Kojto	90:cb3d968589d8	1092
Kojto	90:cb3d968589d8	1093	/*!
Kojto	90:cb3d968589d8	1094	* @name Register SPI_CTARn_SLAVE, field CPHA[25] (RW)
Kojto	90:cb3d968589d8	1095	*
Kojto	90:cb3d968589d8	1096	* Selects which edge of SCK causes data to change and which edge causes data to
Kojto	90:cb3d968589d8	1097	* be captured. This bit is used in both master and slave mode. For successful
Kojto	90:cb3d968589d8	1098	* communication between serial devices, the devices must have identical clock
Kojto	90:cb3d968589d8	1099	* phase settings. In Continuous SCK mode, the bit value is ignored and the
Kojto	90:cb3d968589d8	1100	* transfers are done as if the CPHA bit is set to 1.
Kojto	90:cb3d968589d8	1101	*
Kojto	90:cb3d968589d8	1102	* Values:
Kojto	90:cb3d968589d8	1103	* - 0 - Data is captured on the leading edge of SCK and changed on the
Kojto	90:cb3d968589d8	1104	* following edge.
Kojto	90:cb3d968589d8	1105	* - 1 - Data is changed on the leading edge of SCK and captured on the
Kojto	90:cb3d968589d8	1106	* following edge.
Kojto	90:cb3d968589d8	1107	*/
Kojto	90:cb3d968589d8	1108	/@{/
Kojto	90:cb3d968589d8	1109	#define BP_SPI_CTARn_SLAVE_CPHA (25U) /!< Bit position for SPI_CTARn_SLAVE_CPHA. /
Kojto	90:cb3d968589d8	1110	#define BM_SPI_CTARn_SLAVE_CPHA (0x02000000U) /!< Bit mask for SPI_CTARn_SLAVE_CPHA. /
Kojto	90:cb3d968589d8	1111	#define BS_SPI_CTARn_SLAVE_CPHA (1U) /!< Bit field size in bits for SPI_CTARn_SLAVE_CPHA. /
Kojto	90:cb3d968589d8	1112
Kojto	90:cb3d968589d8	1113	/! @brief Read current value of the SPI_CTARn_SLAVE_CPHA field. /
Kojto	90:cb3d968589d8	1114	#define BR_SPI_CTARn_SLAVE_CPHA(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA))
Kojto	90:cb3d968589d8	1115
Kojto	90:cb3d968589d8	1116	/! @brief Format value for bitfield SPI_CTARn_SLAVE_CPHA. /
Kojto	90:cb3d968589d8	1117	#define BF_SPI_CTARn_SLAVE_CPHA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_SLAVE_CPHA) & BM_SPI_CTARn_SLAVE_CPHA)
Kojto	90:cb3d968589d8	1118
Kojto	90:cb3d968589d8	1119	/! @brief Set the CPHA field to a new value. /
Kojto	90:cb3d968589d8	1120	#define BW_SPI_CTARn_SLAVE_CPHA(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA) = (v))
Kojto	90:cb3d968589d8	1121	/@}/
Kojto	90:cb3d968589d8	1122
Kojto	90:cb3d968589d8	1123	/*!
Kojto	90:cb3d968589d8	1124	* @name Register SPI_CTARn_SLAVE, field CPOL[26] (RW)
Kojto	90:cb3d968589d8	1125	*
Kojto	90:cb3d968589d8	1126	* Selects the inactive state of the Serial Communications Clock (SCK). In case
Kojto	90:cb3d968589d8	1127	* of continous sck mode, when the module goes in low power mode(disabled),
Kojto	90:cb3d968589d8	1128	* inactive state of sck is not guaranted.
Kojto	90:cb3d968589d8	1129	*
Kojto	90:cb3d968589d8	1130	* Values:
Kojto	90:cb3d968589d8	1131	* - 0 - The inactive state value of SCK is low.
Kojto	90:cb3d968589d8	1132	* - 1 - The inactive state value of SCK is high.
Kojto	90:cb3d968589d8	1133	*/
Kojto	90:cb3d968589d8	1134	/@{/
Kojto	90:cb3d968589d8	1135	#define BP_SPI_CTARn_SLAVE_CPOL (26U) /!< Bit position for SPI_CTARn_SLAVE_CPOL. /
Kojto	90:cb3d968589d8	1136	#define BM_SPI_CTARn_SLAVE_CPOL (0x04000000U) /!< Bit mask for SPI_CTARn_SLAVE_CPOL. /
Kojto	90:cb3d968589d8	1137	#define BS_SPI_CTARn_SLAVE_CPOL (1U) /!< Bit field size in bits for SPI_CTARn_SLAVE_CPOL. /
Kojto	90:cb3d968589d8	1138
Kojto	90:cb3d968589d8	1139	/! @brief Read current value of the SPI_CTARn_SLAVE_CPOL field. /
Kojto	90:cb3d968589d8	1140	#define BR_SPI_CTARn_SLAVE_CPOL(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL))
Kojto	90:cb3d968589d8	1141
Kojto	90:cb3d968589d8	1142	/! @brief Format value for bitfield SPI_CTARn_SLAVE_CPOL. /
Kojto	90:cb3d968589d8	1143	#define BF_SPI_CTARn_SLAVE_CPOL(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_SLAVE_CPOL) & BM_SPI_CTARn_SLAVE_CPOL)
Kojto	90:cb3d968589d8	1144
Kojto	90:cb3d968589d8	1145	/! @brief Set the CPOL field to a new value. /
Kojto	90:cb3d968589d8	1146	#define BW_SPI_CTARn_SLAVE_CPOL(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL) = (v))
Kojto	90:cb3d968589d8	1147	/@}/
Kojto	90:cb3d968589d8	1148
Kojto	90:cb3d968589d8	1149	/*!
Kojto	90:cb3d968589d8	1150	* @name Register SPI_CTARn_SLAVE, field FMSZ[31:27] (RW)
Kojto	90:cb3d968589d8	1151	*
Kojto	90:cb3d968589d8	1152	* The number of bits transfered per frame is equal to the FMSZ field value plus
Kojto	90:cb3d968589d8	1153	* 1. Note that the minimum valid value of frame size is 4.
Kojto	90:cb3d968589d8	1154	*/
Kojto	90:cb3d968589d8	1155	/@{/
Kojto	90:cb3d968589d8	1156	#define BP_SPI_CTARn_SLAVE_FMSZ (27U) /!< Bit position for SPI_CTARn_SLAVE_FMSZ. /
Kojto	90:cb3d968589d8	1157	#define BM_SPI_CTARn_SLAVE_FMSZ (0xF8000000U) /!< Bit mask for SPI_CTARn_SLAVE_FMSZ. /
Kojto	90:cb3d968589d8	1158	#define BS_SPI_CTARn_SLAVE_FMSZ (5U) /!< Bit field size in bits for SPI_CTARn_SLAVE_FMSZ. /
Kojto	90:cb3d968589d8	1159
Kojto	90:cb3d968589d8	1160	/! @brief Read current value of the SPI_CTARn_SLAVE_FMSZ field. /
Kojto	90:cb3d968589d8	1161	#define BR_SPI_CTARn_SLAVE_FMSZ(x, n) (HW_SPI_CTARn_SLAVE(x, n).B.FMSZ)
Kojto	90:cb3d968589d8	1162
Kojto	90:cb3d968589d8	1163	/! @brief Format value for bitfield SPI_CTARn_SLAVE_FMSZ. /
Kojto	90:cb3d968589d8	1164	#define BF_SPI_CTARn_SLAVE_FMSZ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_SLAVE_FMSZ) & BM_SPI_CTARn_SLAVE_FMSZ)
Kojto	90:cb3d968589d8	1165
Kojto	90:cb3d968589d8	1166	/! @brief Set the FMSZ field to a new value. /
Kojto	90:cb3d968589d8	1167	#define BW_SPI_CTARn_SLAVE_FMSZ(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, (HW_SPI_CTARn_SLAVE_RD(x, n) & ~BM_SPI_CTARn_SLAVE_FMSZ) \| BF_SPI_CTARn_SLAVE_FMSZ(v)))
Kojto	90:cb3d968589d8	1168	/@}/
Kojto	90:cb3d968589d8	1169
Kojto	90:cb3d968589d8	1170	/*******************************************************************************
Kojto	90:cb3d968589d8	1171	* HW_SPI_SR - Status Register
Kojto	90:cb3d968589d8	1172	******************************************************************************/
Kojto	90:cb3d968589d8	1173
Kojto	90:cb3d968589d8	1174	/*!
Kojto	90:cb3d968589d8	1175	* @brief HW_SPI_SR - Status Register (RW)
Kojto	90:cb3d968589d8	1176	*
Kojto	90:cb3d968589d8	1177	* Reset value: 0x02000000U
Kojto	90:cb3d968589d8	1178	*
Kojto	90:cb3d968589d8	1179	* SR contains status and flag bits. The bits reflect the status of the module
Kojto	90:cb3d968589d8	1180	* and indicate the occurrence of events that can generate interrupt or DMA
Kojto	90:cb3d968589d8	1181	* requests. Software can clear flag bits in the SR by writing a 1 to them. Writing a 0
Kojto	90:cb3d968589d8	1182	* to a flag bit has no effect. This register may not be writable in Module
Kojto	90:cb3d968589d8	1183	* Disable mode due to the use of power saving mechanisms.
Kojto	90:cb3d968589d8	1184	*/
Kojto	90:cb3d968589d8	1185	typedef union _hw_spi_sr
Kojto	90:cb3d968589d8	1186	{
Kojto	90:cb3d968589d8	1187	uint32_t U;
Kojto	90:cb3d968589d8	1188	struct _hw_spi_sr_bitfields
Kojto	90:cb3d968589d8	1189	{
Kojto	90:cb3d968589d8	1190	uint32_t POPNXTPTR : 4; /!< [3:0] Pop Next Pointer /
Kojto	90:cb3d968589d8	1191	uint32_t RXCTR : 4; /!< [7:4] RX FIFO Counter /
Kojto	90:cb3d968589d8	1192	uint32_t TXNXTPTR : 4; /!< [11:8] Transmit Next Pointer /
Kojto	90:cb3d968589d8	1193	uint32_t TXCTR : 4; /!< [15:12] TX FIFO Counter /
Kojto	90:cb3d968589d8	1194	uint32_t RESERVED0 : 1; /!< [16] /
Kojto	90:cb3d968589d8	1195	uint32_t RFDF : 1; /!< [17] Receive FIFO Drain Flag /
Kojto	90:cb3d968589d8	1196	uint32_t RESERVED1 : 1; /!< [18] /
Kojto	90:cb3d968589d8	1197	uint32_t RFOF : 1; /!< [19] Receive FIFO Overflow Flag /
Kojto	90:cb3d968589d8	1198	uint32_t RESERVED2 : 5; /!< [24:20] /
Kojto	90:cb3d968589d8	1199	uint32_t TFFF : 1; /!< [25] Transmit FIFO Fill Flag /
Kojto	90:cb3d968589d8	1200	uint32_t RESERVED3 : 1; /!< [26] /
Kojto	90:cb3d968589d8	1201	uint32_t TFUF : 1; /!< [27] Transmit FIFO Underflow Flag /
Kojto	90:cb3d968589d8	1202	uint32_t EOQF : 1; /!< [28] End of Queue Flag /
Kojto	90:cb3d968589d8	1203	uint32_t RESERVED4 : 1; /!< [29] /
Kojto	90:cb3d968589d8	1204	uint32_t TXRXS : 1; /!< [30] TX and RX Status /
Kojto	90:cb3d968589d8	1205	uint32_t TCF : 1; /!< [31] Transfer Complete Flag /
Kojto	90:cb3d968589d8	1206	} B;
Kojto	90:cb3d968589d8	1207	} hw_spi_sr_t;
Kojto	90:cb3d968589d8	1208
Kojto	90:cb3d968589d8	1209	/*!
Kojto	90:cb3d968589d8	1210	* @name Constants and macros for entire SPI_SR register
Kojto	90:cb3d968589d8	1211	*/
Kojto	90:cb3d968589d8	1212	/@{/
Kojto	90:cb3d968589d8	1213	#define HW_SPI_SR_ADDR(x) ((x) + 0x2CU)
Kojto	90:cb3d968589d8	1214
Kojto	90:cb3d968589d8	1215	#define HW_SPI_SR(x) ((__IO hw_spi_sr_t ) HW_SPI_SR_ADDR(x))
Kojto	90:cb3d968589d8	1216	#define HW_SPI_SR_RD(x) (HW_SPI_SR(x).U)
Kojto	90:cb3d968589d8	1217	#define HW_SPI_SR_WR(x, v) (HW_SPI_SR(x).U = (v))
Kojto	90:cb3d968589d8	1218	#define HW_SPI_SR_SET(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1219	#define HW_SPI_SR_CLR(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1220	#define HW_SPI_SR_TOG(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1221	/@}/
Kojto	90:cb3d968589d8	1222
Kojto	90:cb3d968589d8	1223	/*
Kojto	90:cb3d968589d8	1224	* Constants & macros for individual SPI_SR bitfields
Kojto	90:cb3d968589d8	1225	*/
Kojto	90:cb3d968589d8	1226
Kojto	90:cb3d968589d8	1227	/*!
Kojto	90:cb3d968589d8	1228	* @name Register SPI_SR, field POPNXTPTR[3:0] (RO)
Kojto	90:cb3d968589d8	1229	*
Kojto	90:cb3d968589d8	1230	* Contains a pointer to the RX FIFO entry to be returned when the POPR is read.
Kojto	90:cb3d968589d8	1231	* The POPNXTPTR is updated when the POPR is read.
Kojto	90:cb3d968589d8	1232	*/
Kojto	90:cb3d968589d8	1233	/@{/
Kojto	90:cb3d968589d8	1234	#define BP_SPI_SR_POPNXTPTR (0U) /!< Bit position for SPI_SR_POPNXTPTR. /
Kojto	90:cb3d968589d8	1235	#define BM_SPI_SR_POPNXTPTR (0x0000000FU) /!< Bit mask for SPI_SR_POPNXTPTR. /
Kojto	90:cb3d968589d8	1236	#define BS_SPI_SR_POPNXTPTR (4U) /!< Bit field size in bits for SPI_SR_POPNXTPTR. /
Kojto	90:cb3d968589d8	1237
Kojto	90:cb3d968589d8	1238	/! @brief Read current value of the SPI_SR_POPNXTPTR field. /
Kojto	90:cb3d968589d8	1239	#define BR_SPI_SR_POPNXTPTR(x) (HW_SPI_SR(x).B.POPNXTPTR)
Kojto	90:cb3d968589d8	1240	/@}/
Kojto	90:cb3d968589d8	1241
Kojto	90:cb3d968589d8	1242	/*!
Kojto	90:cb3d968589d8	1243	* @name Register SPI_SR, field RXCTR[7:4] (RO)
Kojto	90:cb3d968589d8	1244	*
Kojto	90:cb3d968589d8	1245	* Indicates the number of entries in the RX FIFO. The RXCTR is decremented
Kojto	90:cb3d968589d8	1246	* every time the POPR is read. The RXCTR is incremented every time data is
Kojto	90:cb3d968589d8	1247	* transferred from the shift register to the RX FIFO.
Kojto	90:cb3d968589d8	1248	*/
Kojto	90:cb3d968589d8	1249	/@{/
Kojto	90:cb3d968589d8	1250	#define BP_SPI_SR_RXCTR (4U) /!< Bit position for SPI_SR_RXCTR. /
Kojto	90:cb3d968589d8	1251	#define BM_SPI_SR_RXCTR (0x000000F0U) /!< Bit mask for SPI_SR_RXCTR. /
Kojto	90:cb3d968589d8	1252	#define BS_SPI_SR_RXCTR (4U) /!< Bit field size in bits for SPI_SR_RXCTR. /
Kojto	90:cb3d968589d8	1253
Kojto	90:cb3d968589d8	1254	/! @brief Read current value of the SPI_SR_RXCTR field. /
Kojto	90:cb3d968589d8	1255	#define BR_SPI_SR_RXCTR(x) (HW_SPI_SR(x).B.RXCTR)
Kojto	90:cb3d968589d8	1256	/@}/
Kojto	90:cb3d968589d8	1257
Kojto	90:cb3d968589d8	1258	/*!
Kojto	90:cb3d968589d8	1259	* @name Register SPI_SR, field TXNXTPTR[11:8] (RO)
Kojto	90:cb3d968589d8	1260	*
Kojto	90:cb3d968589d8	1261	* Indicates which TX FIFO entry is transmitted during the next transfer. The
Kojto	90:cb3d968589d8	1262	* TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to
Kojto	90:cb3d968589d8	1263	* the shift register.
Kojto	90:cb3d968589d8	1264	*/
Kojto	90:cb3d968589d8	1265	/@{/
Kojto	90:cb3d968589d8	1266	#define BP_SPI_SR_TXNXTPTR (8U) /!< Bit position for SPI_SR_TXNXTPTR. /
Kojto	90:cb3d968589d8	1267	#define BM_SPI_SR_TXNXTPTR (0x00000F00U) /!< Bit mask for SPI_SR_TXNXTPTR. /
Kojto	90:cb3d968589d8	1268	#define BS_SPI_SR_TXNXTPTR (4U) /!< Bit field size in bits for SPI_SR_TXNXTPTR. /
Kojto	90:cb3d968589d8	1269
Kojto	90:cb3d968589d8	1270	/! @brief Read current value of the SPI_SR_TXNXTPTR field. /
Kojto	90:cb3d968589d8	1271	#define BR_SPI_SR_TXNXTPTR(x) (HW_SPI_SR(x).B.TXNXTPTR)
Kojto	90:cb3d968589d8	1272	/@}/
Kojto	90:cb3d968589d8	1273
Kojto	90:cb3d968589d8	1274	/*!
Kojto	90:cb3d968589d8	1275	* @name Register SPI_SR, field TXCTR[15:12] (RO)
Kojto	90:cb3d968589d8	1276	*
Kojto	90:cb3d968589d8	1277	* Indicates the number of valid entries in the TX FIFO. The TXCTR is
Kojto	90:cb3d968589d8	1278	* incremented every time the PUSHR is written. The TXCTR is decremented every time an SPI
Kojto	90:cb3d968589d8	1279	* command is executed and the SPI data is transferred to the shift register.
Kojto	90:cb3d968589d8	1280	*/
Kojto	90:cb3d968589d8	1281	/@{/
Kojto	90:cb3d968589d8	1282	#define BP_SPI_SR_TXCTR (12U) /!< Bit position for SPI_SR_TXCTR. /
Kojto	90:cb3d968589d8	1283	#define BM_SPI_SR_TXCTR (0x0000F000U) /!< Bit mask for SPI_SR_TXCTR. /
Kojto	90:cb3d968589d8	1284	#define BS_SPI_SR_TXCTR (4U) /!< Bit field size in bits for SPI_SR_TXCTR. /
Kojto	90:cb3d968589d8	1285
Kojto	90:cb3d968589d8	1286	/! @brief Read current value of the SPI_SR_TXCTR field. /
Kojto	90:cb3d968589d8	1287	#define BR_SPI_SR_TXCTR(x) (HW_SPI_SR(x).B.TXCTR)
Kojto	90:cb3d968589d8	1288	/@}/
Kojto	90:cb3d968589d8	1289
Kojto	90:cb3d968589d8	1290	/*!
Kojto	90:cb3d968589d8	1291	* @name Register SPI_SR, field RFDF[17] (W1C)
Kojto	90:cb3d968589d8	1292	*
Kojto	90:cb3d968589d8	1293	* Provides a method for the module to request that entries be removed from the
Kojto	90:cb3d968589d8	1294	* RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be
Kojto	90:cb3d968589d8	1295	* cleared by writing 1 to it or by acknowledgement from the DMA controller when
Kojto	90:cb3d968589d8	1296	* the RX FIFO is empty.
Kojto	90:cb3d968589d8	1297	*
Kojto	90:cb3d968589d8	1298	* Values:
Kojto	90:cb3d968589d8	1299	* - 0 - RX FIFO is empty.
Kojto	90:cb3d968589d8	1300	* - 1 - RX FIFO is not empty.
Kojto	90:cb3d968589d8	1301	*/
Kojto	90:cb3d968589d8	1302	/@{/
Kojto	90:cb3d968589d8	1303	#define BP_SPI_SR_RFDF (17U) /!< Bit position for SPI_SR_RFDF. /
Kojto	90:cb3d968589d8	1304	#define BM_SPI_SR_RFDF (0x00020000U) /!< Bit mask for SPI_SR_RFDF. /
Kojto	90:cb3d968589d8	1305	#define BS_SPI_SR_RFDF (1U) /!< Bit field size in bits for SPI_SR_RFDF. /
Kojto	90:cb3d968589d8	1306
Kojto	90:cb3d968589d8	1307	/! @brief Read current value of the SPI_SR_RFDF field. /
Kojto	90:cb3d968589d8	1308	#define BR_SPI_SR_RFDF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF))
Kojto	90:cb3d968589d8	1309
Kojto	90:cb3d968589d8	1310	/! @brief Format value for bitfield SPI_SR_RFDF. /
Kojto	90:cb3d968589d8	1311	#define BF_SPI_SR_RFDF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_RFDF) & BM_SPI_SR_RFDF)
Kojto	90:cb3d968589d8	1312
Kojto	90:cb3d968589d8	1313	/! @brief Set the RFDF field to a new value. /
Kojto	90:cb3d968589d8	1314	#define BW_SPI_SR_RFDF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF) = (v))
Kojto	90:cb3d968589d8	1315	/@}/
Kojto	90:cb3d968589d8	1316
Kojto	90:cb3d968589d8	1317	/*!
Kojto	90:cb3d968589d8	1318	* @name Register SPI_SR, field RFOF[19] (W1C)
Kojto	90:cb3d968589d8	1319	*
Kojto	90:cb3d968589d8	1320	* Indicates an overflow condition in the RX FIFO. The field is set when the RX
Kojto	90:cb3d968589d8	1321	* FIFO and shift register are full and a transfer is initiated. The bit remains
Kojto	90:cb3d968589d8	1322	* set until it is cleared by writing a 1 to it.
Kojto	90:cb3d968589d8	1323	*
Kojto	90:cb3d968589d8	1324	* Values:
Kojto	90:cb3d968589d8	1325	* - 0 - No Rx FIFO overflow.
Kojto	90:cb3d968589d8	1326	* - 1 - Rx FIFO overflow has occurred.
Kojto	90:cb3d968589d8	1327	*/
Kojto	90:cb3d968589d8	1328	/@{/
Kojto	90:cb3d968589d8	1329	#define BP_SPI_SR_RFOF (19U) /!< Bit position for SPI_SR_RFOF. /
Kojto	90:cb3d968589d8	1330	#define BM_SPI_SR_RFOF (0x00080000U) /!< Bit mask for SPI_SR_RFOF. /
Kojto	90:cb3d968589d8	1331	#define BS_SPI_SR_RFOF (1U) /!< Bit field size in bits for SPI_SR_RFOF. /
Kojto	90:cb3d968589d8	1332
Kojto	90:cb3d968589d8	1333	/! @brief Read current value of the SPI_SR_RFOF field. /
Kojto	90:cb3d968589d8	1334	#define BR_SPI_SR_RFOF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF))
Kojto	90:cb3d968589d8	1335
Kojto	90:cb3d968589d8	1336	/! @brief Format value for bitfield SPI_SR_RFOF. /
Kojto	90:cb3d968589d8	1337	#define BF_SPI_SR_RFOF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_RFOF) & BM_SPI_SR_RFOF)
Kojto	90:cb3d968589d8	1338
Kojto	90:cb3d968589d8	1339	/! @brief Set the RFOF field to a new value. /
Kojto	90:cb3d968589d8	1340	#define BW_SPI_SR_RFOF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF) = (v))
Kojto	90:cb3d968589d8	1341	/@}/
Kojto	90:cb3d968589d8	1342
Kojto	90:cb3d968589d8	1343	/*!
Kojto	90:cb3d968589d8	1344	* @name Register SPI_SR, field TFFF[25] (W1C)
Kojto	90:cb3d968589d8	1345	*
Kojto	90:cb3d968589d8	1346	* Provides a method for the module to request more entries to be added to the
Kojto	90:cb3d968589d8	1347	* TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be
Kojto	90:cb3d968589d8	1348	* cleared by writing 1 to it or by acknowledgement from the DMA controller to
Kojto	90:cb3d968589d8	1349	* the TX FIFO full request.
Kojto	90:cb3d968589d8	1350	*
Kojto	90:cb3d968589d8	1351	* Values:
Kojto	90:cb3d968589d8	1352	* - 0 - TX FIFO is full.
Kojto	90:cb3d968589d8	1353	* - 1 - TX FIFO is not full.
Kojto	90:cb3d968589d8	1354	*/
Kojto	90:cb3d968589d8	1355	/@{/
Kojto	90:cb3d968589d8	1356	#define BP_SPI_SR_TFFF (25U) /!< Bit position for SPI_SR_TFFF. /
Kojto	90:cb3d968589d8	1357	#define BM_SPI_SR_TFFF (0x02000000U) /!< Bit mask for SPI_SR_TFFF. /
Kojto	90:cb3d968589d8	1358	#define BS_SPI_SR_TFFF (1U) /!< Bit field size in bits for SPI_SR_TFFF. /
Kojto	90:cb3d968589d8	1359
Kojto	90:cb3d968589d8	1360	/! @brief Read current value of the SPI_SR_TFFF field. /
Kojto	90:cb3d968589d8	1361	#define BR_SPI_SR_TFFF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF))
Kojto	90:cb3d968589d8	1362
Kojto	90:cb3d968589d8	1363	/! @brief Format value for bitfield SPI_SR_TFFF. /
Kojto	90:cb3d968589d8	1364	#define BF_SPI_SR_TFFF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TFFF) & BM_SPI_SR_TFFF)
Kojto	90:cb3d968589d8	1365
Kojto	90:cb3d968589d8	1366	/! @brief Set the TFFF field to a new value. /
Kojto	90:cb3d968589d8	1367	#define BW_SPI_SR_TFFF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF) = (v))
Kojto	90:cb3d968589d8	1368	/@}/
Kojto	90:cb3d968589d8	1369
Kojto	90:cb3d968589d8	1370	/*!
Kojto	90:cb3d968589d8	1371	* @name Register SPI_SR, field TFUF[27] (W1C)
Kojto	90:cb3d968589d8	1372	*
Kojto	90:cb3d968589d8	1373	* Indicates an underflow condition in the TX FIFO. The transmit underflow
Kojto	90:cb3d968589d8	1374	* condition is detected only for SPI blocks operating in Slave mode and SPI
Kojto	90:cb3d968589d8	1375	* configuration. TFUF is set when the TX FIFO of the module operating in SPI Slave mode
Kojto	90:cb3d968589d8	1376	* is empty and an external SPI master initiates a transfer. The TFUF bit remains
Kojto	90:cb3d968589d8	1377	* set until cleared by writing 1 to it.
Kojto	90:cb3d968589d8	1378	*
Kojto	90:cb3d968589d8	1379	* Values:
Kojto	90:cb3d968589d8	1380	* - 0 - No TX FIFO underflow.
Kojto	90:cb3d968589d8	1381	* - 1 - TX FIFO underflow has occurred.
Kojto	90:cb3d968589d8	1382	*/
Kojto	90:cb3d968589d8	1383	/@{/
Kojto	90:cb3d968589d8	1384	#define BP_SPI_SR_TFUF (27U) /!< Bit position for SPI_SR_TFUF. /
Kojto	90:cb3d968589d8	1385	#define BM_SPI_SR_TFUF (0x08000000U) /!< Bit mask for SPI_SR_TFUF. /
Kojto	90:cb3d968589d8	1386	#define BS_SPI_SR_TFUF (1U) /!< Bit field size in bits for SPI_SR_TFUF. /
Kojto	90:cb3d968589d8	1387
Kojto	90:cb3d968589d8	1388	/! @brief Read current value of the SPI_SR_TFUF field. /
Kojto	90:cb3d968589d8	1389	#define BR_SPI_SR_TFUF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF))
Kojto	90:cb3d968589d8	1390
Kojto	90:cb3d968589d8	1391	/! @brief Format value for bitfield SPI_SR_TFUF. /
Kojto	90:cb3d968589d8	1392	#define BF_SPI_SR_TFUF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TFUF) & BM_SPI_SR_TFUF)
Kojto	90:cb3d968589d8	1393
Kojto	90:cb3d968589d8	1394	/! @brief Set the TFUF field to a new value. /
Kojto	90:cb3d968589d8	1395	#define BW_SPI_SR_TFUF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF) = (v))
Kojto	90:cb3d968589d8	1396	/@}/
Kojto	90:cb3d968589d8	1397
Kojto	90:cb3d968589d8	1398	/*!
Kojto	90:cb3d968589d8	1399	* @name Register SPI_SR, field EOQF[28] (W1C)
Kojto	90:cb3d968589d8	1400	*
Kojto	90:cb3d968589d8	1401	* Indicates that the last entry in a queue has been transmitted when the module
Kojto	90:cb3d968589d8	1402	* is in Master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit
Kojto	90:cb3d968589d8	1403	* set in the command halfword and the end of the transfer is reached. The EOQF
Kojto	90:cb3d968589d8	1404	* bit remains set until cleared by writing a 1 to it. When the EOQF bit is set,
Kojto	90:cb3d968589d8	1405	* the TXRXS bit is automatically cleared.
Kojto	90:cb3d968589d8	1406	*
Kojto	90:cb3d968589d8	1407	* Values:
Kojto	90:cb3d968589d8	1408	* - 0 - EOQ is not set in the executing command.
Kojto	90:cb3d968589d8	1409	* - 1 - EOQ is set in the executing SPI command.
Kojto	90:cb3d968589d8	1410	*/
Kojto	90:cb3d968589d8	1411	/@{/
Kojto	90:cb3d968589d8	1412	#define BP_SPI_SR_EOQF (28U) /!< Bit position for SPI_SR_EOQF. /
Kojto	90:cb3d968589d8	1413	#define BM_SPI_SR_EOQF (0x10000000U) /!< Bit mask for SPI_SR_EOQF. /
Kojto	90:cb3d968589d8	1414	#define BS_SPI_SR_EOQF (1U) /!< Bit field size in bits for SPI_SR_EOQF. /
Kojto	90:cb3d968589d8	1415
Kojto	90:cb3d968589d8	1416	/! @brief Read current value of the SPI_SR_EOQF field. /
Kojto	90:cb3d968589d8	1417	#define BR_SPI_SR_EOQF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF))
Kojto	90:cb3d968589d8	1418
Kojto	90:cb3d968589d8	1419	/! @brief Format value for bitfield SPI_SR_EOQF. /
Kojto	90:cb3d968589d8	1420	#define BF_SPI_SR_EOQF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_EOQF) & BM_SPI_SR_EOQF)
Kojto	90:cb3d968589d8	1421
Kojto	90:cb3d968589d8	1422	/! @brief Set the EOQF field to a new value. /
Kojto	90:cb3d968589d8	1423	#define BW_SPI_SR_EOQF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF) = (v))
Kojto	90:cb3d968589d8	1424	/@}/
Kojto	90:cb3d968589d8	1425
Kojto	90:cb3d968589d8	1426	/*!
Kojto	90:cb3d968589d8	1427	* @name Register SPI_SR, field TXRXS[30] (W1C)
Kojto	90:cb3d968589d8	1428	*
Kojto	90:cb3d968589d8	1429	* Reflects the run status of the module.
Kojto	90:cb3d968589d8	1430	*
Kojto	90:cb3d968589d8	1431	* Values:
Kojto	90:cb3d968589d8	1432	* - 0 - Transmit and receive operations are disabled (The module is in Stopped
Kojto	90:cb3d968589d8	1433	* state).
Kojto	90:cb3d968589d8	1434	* - 1 - Transmit and receive operations are enabled (The module is in Running
Kojto	90:cb3d968589d8	1435	* state).
Kojto	90:cb3d968589d8	1436	*/
Kojto	90:cb3d968589d8	1437	/@{/
Kojto	90:cb3d968589d8	1438	#define BP_SPI_SR_TXRXS (30U) /!< Bit position for SPI_SR_TXRXS. /
Kojto	90:cb3d968589d8	1439	#define BM_SPI_SR_TXRXS (0x40000000U) /!< Bit mask for SPI_SR_TXRXS. /
Kojto	90:cb3d968589d8	1440	#define BS_SPI_SR_TXRXS (1U) /!< Bit field size in bits for SPI_SR_TXRXS. /
Kojto	90:cb3d968589d8	1441
Kojto	90:cb3d968589d8	1442	/! @brief Read current value of the SPI_SR_TXRXS field. /
Kojto	90:cb3d968589d8	1443	#define BR_SPI_SR_TXRXS(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS))
Kojto	90:cb3d968589d8	1444
Kojto	90:cb3d968589d8	1445	/! @brief Format value for bitfield SPI_SR_TXRXS. /
Kojto	90:cb3d968589d8	1446	#define BF_SPI_SR_TXRXS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TXRXS) & BM_SPI_SR_TXRXS)
Kojto	90:cb3d968589d8	1447
Kojto	90:cb3d968589d8	1448	/! @brief Set the TXRXS field to a new value. /
Kojto	90:cb3d968589d8	1449	#define BW_SPI_SR_TXRXS(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS) = (v))
Kojto	90:cb3d968589d8	1450	/@}/
Kojto	90:cb3d968589d8	1451
Kojto	90:cb3d968589d8	1452	/*!
Kojto	90:cb3d968589d8	1453	* @name Register SPI_SR, field TCF[31] (W1C)
Kojto	90:cb3d968589d8	1454	*
Kojto	90:cb3d968589d8	1455	* Indicates that all bits in a frame have been shifted out. TCF remains set
Kojto	90:cb3d968589d8	1456	* until it is cleared by writing a 1 to it.
Kojto	90:cb3d968589d8	1457	*
Kojto	90:cb3d968589d8	1458	* Values:
Kojto	90:cb3d968589d8	1459	* - 0 - Transfer not complete.
Kojto	90:cb3d968589d8	1460	* - 1 - Transfer complete.
Kojto	90:cb3d968589d8	1461	*/
Kojto	90:cb3d968589d8	1462	/@{/
Kojto	90:cb3d968589d8	1463	#define BP_SPI_SR_TCF (31U) /!< Bit position for SPI_SR_TCF. /
Kojto	90:cb3d968589d8	1464	#define BM_SPI_SR_TCF (0x80000000U) /!< Bit mask for SPI_SR_TCF. /
Kojto	90:cb3d968589d8	1465	#define BS_SPI_SR_TCF (1U) /!< Bit field size in bits for SPI_SR_TCF. /
Kojto	90:cb3d968589d8	1466
Kojto	90:cb3d968589d8	1467	/! @brief Read current value of the SPI_SR_TCF field. /
Kojto	90:cb3d968589d8	1468	#define BR_SPI_SR_TCF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF))
Kojto	90:cb3d968589d8	1469
Kojto	90:cb3d968589d8	1470	/! @brief Format value for bitfield SPI_SR_TCF. /
Kojto	90:cb3d968589d8	1471	#define BF_SPI_SR_TCF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TCF) & BM_SPI_SR_TCF)
Kojto	90:cb3d968589d8	1472
Kojto	90:cb3d968589d8	1473	/! @brief Set the TCF field to a new value. /
Kojto	90:cb3d968589d8	1474	#define BW_SPI_SR_TCF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF) = (v))
Kojto	90:cb3d968589d8	1475	/@}/
Kojto	90:cb3d968589d8	1476
Kojto	90:cb3d968589d8	1477	/*******************************************************************************
Kojto	90:cb3d968589d8	1478	* HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register
Kojto	90:cb3d968589d8	1479	******************************************************************************/
Kojto	90:cb3d968589d8	1480
Kojto	90:cb3d968589d8	1481	/*!
Kojto	90:cb3d968589d8	1482	* @brief HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register (RW)
Kojto	90:cb3d968589d8	1483	*
Kojto	90:cb3d968589d8	1484	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1485	*
Kojto	90:cb3d968589d8	1486	* RSER controls DMA and interrupt requests. Do not write to the RSER while the
Kojto	90:cb3d968589d8	1487	* module is in the Running state.
Kojto	90:cb3d968589d8	1488	*/
Kojto	90:cb3d968589d8	1489	typedef union _hw_spi_rser
Kojto	90:cb3d968589d8	1490	{
Kojto	90:cb3d968589d8	1491	uint32_t U;
Kojto	90:cb3d968589d8	1492	struct _hw_spi_rser_bitfields
Kojto	90:cb3d968589d8	1493	{
Kojto	90:cb3d968589d8	1494	uint32_t RESERVED0 : 16; /!< [15:0] /
Kojto	90:cb3d968589d8	1495	uint32_t RFDF_DIRS : 1; /*!< [16] Receive FIFO Drain DMA or Interrupt
Kojto	90:cb3d968589d8	1496	* Request Select */
Kojto	90:cb3d968589d8	1497	uint32_t RFDF_RE : 1; /!< [17] Receive FIFO Drain Request Enable /
Kojto	90:cb3d968589d8	1498	uint32_t RESERVED1 : 1; /!< [18] /
Kojto	90:cb3d968589d8	1499	uint32_t RFOF_RE : 1; /*!< [19] Receive FIFO Overflow Request Enable
Kojto	90:cb3d968589d8	1500	* */
Kojto	90:cb3d968589d8	1501	uint32_t RESERVED2 : 4; /!< [23:20] /
Kojto	90:cb3d968589d8	1502	uint32_t TFFF_DIRS : 1; /*!< [24] Transmit FIFO Fill DMA or Interrupt
Kojto	90:cb3d968589d8	1503	* Request Select */
Kojto	90:cb3d968589d8	1504	uint32_t TFFF_RE : 1; /!< [25] Transmit FIFO Fill Request Enable /
Kojto	90:cb3d968589d8	1505	uint32_t RESERVED3 : 1; /!< [26] /
Kojto	90:cb3d968589d8	1506	uint32_t TFUF_RE : 1; /*!< [27] Transmit FIFO Underflow Request
Kojto	90:cb3d968589d8	1507	* Enable */
Kojto	90:cb3d968589d8	1508	uint32_t EOQF_RE : 1; /!< [28] Finished Request Enable /
Kojto	90:cb3d968589d8	1509	uint32_t RESERVED4 : 2; /!< [30:29] /
Kojto	90:cb3d968589d8	1510	uint32_t TCF_RE : 1; /!< [31] Transmission Complete Request Enable /
Kojto	90:cb3d968589d8	1511	} B;
Kojto	90:cb3d968589d8	1512	} hw_spi_rser_t;
Kojto	90:cb3d968589d8	1513
Kojto	90:cb3d968589d8	1514	/*!
Kojto	90:cb3d968589d8	1515	* @name Constants and macros for entire SPI_RSER register
Kojto	90:cb3d968589d8	1516	*/
Kojto	90:cb3d968589d8	1517	/@{/
Kojto	90:cb3d968589d8	1518	#define HW_SPI_RSER_ADDR(x) ((x) + 0x30U)
Kojto	90:cb3d968589d8	1519
Kojto	90:cb3d968589d8	1520	#define HW_SPI_RSER(x) ((__IO hw_spi_rser_t ) HW_SPI_RSER_ADDR(x))
Kojto	90:cb3d968589d8	1521	#define HW_SPI_RSER_RD(x) (HW_SPI_RSER(x).U)
Kojto	90:cb3d968589d8	1522	#define HW_SPI_RSER_WR(x, v) (HW_SPI_RSER(x).U = (v))
Kojto	90:cb3d968589d8	1523	#define HW_SPI_RSER_SET(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1524	#define HW_SPI_RSER_CLR(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1525	#define HW_SPI_RSER_TOG(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1526	/@}/
Kojto	90:cb3d968589d8	1527
Kojto	90:cb3d968589d8	1528	/*
Kojto	90:cb3d968589d8	1529	* Constants & macros for individual SPI_RSER bitfields
Kojto	90:cb3d968589d8	1530	*/
Kojto	90:cb3d968589d8	1531
Kojto	90:cb3d968589d8	1532	/*!
Kojto	90:cb3d968589d8	1533	* @name Register SPI_RSER, field RFDF_DIRS[16] (RW)
Kojto	90:cb3d968589d8	1534	*
Kojto	90:cb3d968589d8	1535	* Selects between generating a DMA request or an interrupt request. When the
Kojto	90:cb3d968589d8	1536	* RFDF flag bit in the SR is set, and the RFDF_RE bit in the RSER is set, the
Kojto	90:cb3d968589d8	1537	* RFDF_DIRS bit selects between generating an interrupt request or a DMA request.
Kojto	90:cb3d968589d8	1538	*
Kojto	90:cb3d968589d8	1539	* Values:
Kojto	90:cb3d968589d8	1540	* - 0 - Interrupt request.
Kojto	90:cb3d968589d8	1541	* - 1 - DMA request.
Kojto	90:cb3d968589d8	1542	*/
Kojto	90:cb3d968589d8	1543	/@{/
Kojto	90:cb3d968589d8	1544	#define BP_SPI_RSER_RFDF_DIRS (16U) /!< Bit position for SPI_RSER_RFDF_DIRS. /
Kojto	90:cb3d968589d8	1545	#define BM_SPI_RSER_RFDF_DIRS (0x00010000U) /!< Bit mask for SPI_RSER_RFDF_DIRS. /
Kojto	90:cb3d968589d8	1546	#define BS_SPI_RSER_RFDF_DIRS (1U) /!< Bit field size in bits for SPI_RSER_RFDF_DIRS. /
Kojto	90:cb3d968589d8	1547
Kojto	90:cb3d968589d8	1548	/! @brief Read current value of the SPI_RSER_RFDF_DIRS field. /
Kojto	90:cb3d968589d8	1549	#define BR_SPI_RSER_RFDF_DIRS(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS))
Kojto	90:cb3d968589d8	1550
Kojto	90:cb3d968589d8	1551	/! @brief Format value for bitfield SPI_RSER_RFDF_DIRS. /
Kojto	90:cb3d968589d8	1552	#define BF_SPI_RSER_RFDF_DIRS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_RFDF_DIRS) & BM_SPI_RSER_RFDF_DIRS)
Kojto	90:cb3d968589d8	1553
Kojto	90:cb3d968589d8	1554	/! @brief Set the RFDF_DIRS field to a new value. /
Kojto	90:cb3d968589d8	1555	#define BW_SPI_RSER_RFDF_DIRS(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS) = (v))
Kojto	90:cb3d968589d8	1556	/@}/
Kojto	90:cb3d968589d8	1557
Kojto	90:cb3d968589d8	1558	/*!
Kojto	90:cb3d968589d8	1559	* @name Register SPI_RSER, field RFDF_RE[17] (RW)
Kojto	90:cb3d968589d8	1560	*
Kojto	90:cb3d968589d8	1561	* Enables the RFDF flag in the SR to generate a request. The RFDF_DIRS bit
Kojto	90:cb3d968589d8	1562	* selects between generating an interrupt request or a DMA request.
Kojto	90:cb3d968589d8	1563	*
Kojto	90:cb3d968589d8	1564	* Values:
Kojto	90:cb3d968589d8	1565	* - 0 - RFDF interrupt or DMA requests are disabled.
Kojto	90:cb3d968589d8	1566	* - 1 - RFDF interrupt or DMA requests are enabled.
Kojto	90:cb3d968589d8	1567	*/
Kojto	90:cb3d968589d8	1568	/@{/
Kojto	90:cb3d968589d8	1569	#define BP_SPI_RSER_RFDF_RE (17U) /!< Bit position for SPI_RSER_RFDF_RE. /
Kojto	90:cb3d968589d8	1570	#define BM_SPI_RSER_RFDF_RE (0x00020000U) /!< Bit mask for SPI_RSER_RFDF_RE. /
Kojto	90:cb3d968589d8	1571	#define BS_SPI_RSER_RFDF_RE (1U) /!< Bit field size in bits for SPI_RSER_RFDF_RE. /
Kojto	90:cb3d968589d8	1572
Kojto	90:cb3d968589d8	1573	/! @brief Read current value of the SPI_RSER_RFDF_RE field. /
Kojto	90:cb3d968589d8	1574	#define BR_SPI_RSER_RFDF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE))
Kojto	90:cb3d968589d8	1575
Kojto	90:cb3d968589d8	1576	/! @brief Format value for bitfield SPI_RSER_RFDF_RE. /
Kojto	90:cb3d968589d8	1577	#define BF_SPI_RSER_RFDF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_RFDF_RE) & BM_SPI_RSER_RFDF_RE)
Kojto	90:cb3d968589d8	1578
Kojto	90:cb3d968589d8	1579	/! @brief Set the RFDF_RE field to a new value. /
Kojto	90:cb3d968589d8	1580	#define BW_SPI_RSER_RFDF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE) = (v))
Kojto	90:cb3d968589d8	1581	/@}/
Kojto	90:cb3d968589d8	1582
Kojto	90:cb3d968589d8	1583	/*!
Kojto	90:cb3d968589d8	1584	* @name Register SPI_RSER, field RFOF_RE[19] (RW)
Kojto	90:cb3d968589d8	1585	*
Kojto	90:cb3d968589d8	1586	* Enables the RFOF flag in the SR to generate an interrupt request.
Kojto	90:cb3d968589d8	1587	*
Kojto	90:cb3d968589d8	1588	* Values:
Kojto	90:cb3d968589d8	1589	* - 0 - RFOF interrupt requests are disabled.
Kojto	90:cb3d968589d8	1590	* - 1 - RFOF interrupt requests are enabled.
Kojto	90:cb3d968589d8	1591	*/
Kojto	90:cb3d968589d8	1592	/@{/
Kojto	90:cb3d968589d8	1593	#define BP_SPI_RSER_RFOF_RE (19U) /!< Bit position for SPI_RSER_RFOF_RE. /
Kojto	90:cb3d968589d8	1594	#define BM_SPI_RSER_RFOF_RE (0x00080000U) /!< Bit mask for SPI_RSER_RFOF_RE. /
Kojto	90:cb3d968589d8	1595	#define BS_SPI_RSER_RFOF_RE (1U) /!< Bit field size in bits for SPI_RSER_RFOF_RE. /
Kojto	90:cb3d968589d8	1596
Kojto	90:cb3d968589d8	1597	/! @brief Read current value of the SPI_RSER_RFOF_RE field. /
Kojto	90:cb3d968589d8	1598	#define BR_SPI_RSER_RFOF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE))
Kojto	90:cb3d968589d8	1599
Kojto	90:cb3d968589d8	1600	/! @brief Format value for bitfield SPI_RSER_RFOF_RE. /
Kojto	90:cb3d968589d8	1601	#define BF_SPI_RSER_RFOF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_RFOF_RE) & BM_SPI_RSER_RFOF_RE)
Kojto	90:cb3d968589d8	1602
Kojto	90:cb3d968589d8	1603	/! @brief Set the RFOF_RE field to a new value. /
Kojto	90:cb3d968589d8	1604	#define BW_SPI_RSER_RFOF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE) = (v))
Kojto	90:cb3d968589d8	1605	/@}/
Kojto	90:cb3d968589d8	1606
Kojto	90:cb3d968589d8	1607	/*!
Kojto	90:cb3d968589d8	1608	* @name Register SPI_RSER, field TFFF_DIRS[24] (RW)
Kojto	90:cb3d968589d8	1609	*
Kojto	90:cb3d968589d8	1610	* Selects between generating a DMA request or an interrupt request. When
Kojto	90:cb3d968589d8	1611	* SR[TFFF] and RSER[TFFF_RE] are set, this field selects between generating an
Kojto	90:cb3d968589d8	1612	* interrupt request or a DMA request.
Kojto	90:cb3d968589d8	1613	*
Kojto	90:cb3d968589d8	1614	* Values:
Kojto	90:cb3d968589d8	1615	* - 0 - TFFF flag generates interrupt requests.
Kojto	90:cb3d968589d8	1616	* - 1 - TFFF flag generates DMA requests.
Kojto	90:cb3d968589d8	1617	*/
Kojto	90:cb3d968589d8	1618	/@{/
Kojto	90:cb3d968589d8	1619	#define BP_SPI_RSER_TFFF_DIRS (24U) /!< Bit position for SPI_RSER_TFFF_DIRS. /
Kojto	90:cb3d968589d8	1620	#define BM_SPI_RSER_TFFF_DIRS (0x01000000U) /!< Bit mask for SPI_RSER_TFFF_DIRS. /
Kojto	90:cb3d968589d8	1621	#define BS_SPI_RSER_TFFF_DIRS (1U) /!< Bit field size in bits for SPI_RSER_TFFF_DIRS. /
Kojto	90:cb3d968589d8	1622
Kojto	90:cb3d968589d8	1623	/! @brief Read current value of the SPI_RSER_TFFF_DIRS field. /
Kojto	90:cb3d968589d8	1624	#define BR_SPI_RSER_TFFF_DIRS(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS))
Kojto	90:cb3d968589d8	1625
Kojto	90:cb3d968589d8	1626	/! @brief Format value for bitfield SPI_RSER_TFFF_DIRS. /
Kojto	90:cb3d968589d8	1627	#define BF_SPI_RSER_TFFF_DIRS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TFFF_DIRS) & BM_SPI_RSER_TFFF_DIRS)
Kojto	90:cb3d968589d8	1628
Kojto	90:cb3d968589d8	1629	/! @brief Set the TFFF_DIRS field to a new value. /
Kojto	90:cb3d968589d8	1630	#define BW_SPI_RSER_TFFF_DIRS(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS) = (v))
Kojto	90:cb3d968589d8	1631	/@}/
Kojto	90:cb3d968589d8	1632
Kojto	90:cb3d968589d8	1633	/*!
Kojto	90:cb3d968589d8	1634	* @name Register SPI_RSER, field TFFF_RE[25] (RW)
Kojto	90:cb3d968589d8	1635	*
Kojto	90:cb3d968589d8	1636	* Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit
Kojto	90:cb3d968589d8	1637	* selects between generating an interrupt request or a DMA request.
Kojto	90:cb3d968589d8	1638	*
Kojto	90:cb3d968589d8	1639	* Values:
Kojto	90:cb3d968589d8	1640	* - 0 - TFFF interrupts or DMA requests are disabled.
Kojto	90:cb3d968589d8	1641	* - 1 - TFFF interrupts or DMA requests are enabled.
Kojto	90:cb3d968589d8	1642	*/
Kojto	90:cb3d968589d8	1643	/@{/
Kojto	90:cb3d968589d8	1644	#define BP_SPI_RSER_TFFF_RE (25U) /!< Bit position for SPI_RSER_TFFF_RE. /
Kojto	90:cb3d968589d8	1645	#define BM_SPI_RSER_TFFF_RE (0x02000000U) /!< Bit mask for SPI_RSER_TFFF_RE. /
Kojto	90:cb3d968589d8	1646	#define BS_SPI_RSER_TFFF_RE (1U) /!< Bit field size in bits for SPI_RSER_TFFF_RE. /
Kojto	90:cb3d968589d8	1647
Kojto	90:cb3d968589d8	1648	/! @brief Read current value of the SPI_RSER_TFFF_RE field. /
Kojto	90:cb3d968589d8	1649	#define BR_SPI_RSER_TFFF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE))
Kojto	90:cb3d968589d8	1650
Kojto	90:cb3d968589d8	1651	/! @brief Format value for bitfield SPI_RSER_TFFF_RE. /
Kojto	90:cb3d968589d8	1652	#define BF_SPI_RSER_TFFF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TFFF_RE) & BM_SPI_RSER_TFFF_RE)
Kojto	90:cb3d968589d8	1653
Kojto	90:cb3d968589d8	1654	/! @brief Set the TFFF_RE field to a new value. /
Kojto	90:cb3d968589d8	1655	#define BW_SPI_RSER_TFFF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE) = (v))
Kojto	90:cb3d968589d8	1656	/@}/
Kojto	90:cb3d968589d8	1657
Kojto	90:cb3d968589d8	1658	/*!
Kojto	90:cb3d968589d8	1659	* @name Register SPI_RSER, field TFUF_RE[27] (RW)
Kojto	90:cb3d968589d8	1660	*
Kojto	90:cb3d968589d8	1661	* Enables the TFUF flag in the SR to generate an interrupt request.
Kojto	90:cb3d968589d8	1662	*
Kojto	90:cb3d968589d8	1663	* Values:
Kojto	90:cb3d968589d8	1664	* - 0 - TFUF interrupt requests are disabled.
Kojto	90:cb3d968589d8	1665	* - 1 - TFUF interrupt requests are enabled.
Kojto	90:cb3d968589d8	1666	*/
Kojto	90:cb3d968589d8	1667	/@{/
Kojto	90:cb3d968589d8	1668	#define BP_SPI_RSER_TFUF_RE (27U) /!< Bit position for SPI_RSER_TFUF_RE. /
Kojto	90:cb3d968589d8	1669	#define BM_SPI_RSER_TFUF_RE (0x08000000U) /!< Bit mask for SPI_RSER_TFUF_RE. /
Kojto	90:cb3d968589d8	1670	#define BS_SPI_RSER_TFUF_RE (1U) /!< Bit field size in bits for SPI_RSER_TFUF_RE. /
Kojto	90:cb3d968589d8	1671
Kojto	90:cb3d968589d8	1672	/! @brief Read current value of the SPI_RSER_TFUF_RE field. /
Kojto	90:cb3d968589d8	1673	#define BR_SPI_RSER_TFUF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE))
Kojto	90:cb3d968589d8	1674
Kojto	90:cb3d968589d8	1675	/! @brief Format value for bitfield SPI_RSER_TFUF_RE. /
Kojto	90:cb3d968589d8	1676	#define BF_SPI_RSER_TFUF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TFUF_RE) & BM_SPI_RSER_TFUF_RE)
Kojto	90:cb3d968589d8	1677
Kojto	90:cb3d968589d8	1678	/! @brief Set the TFUF_RE field to a new value. /
Kojto	90:cb3d968589d8	1679	#define BW_SPI_RSER_TFUF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE) = (v))
Kojto	90:cb3d968589d8	1680	/@}/
Kojto	90:cb3d968589d8	1681
Kojto	90:cb3d968589d8	1682	/*!
Kojto	90:cb3d968589d8	1683	* @name Register SPI_RSER, field EOQF_RE[28] (RW)
Kojto	90:cb3d968589d8	1684	*
Kojto	90:cb3d968589d8	1685	* Enables the EOQF flag in the SR to generate an interrupt request.
Kojto	90:cb3d968589d8	1686	*
Kojto	90:cb3d968589d8	1687	* Values:
Kojto	90:cb3d968589d8	1688	* - 0 - EOQF interrupt requests are disabled.
Kojto	90:cb3d968589d8	1689	* - 1 - EOQF interrupt requests are enabled.
Kojto	90:cb3d968589d8	1690	*/
Kojto	90:cb3d968589d8	1691	/@{/
Kojto	90:cb3d968589d8	1692	#define BP_SPI_RSER_EOQF_RE (28U) /!< Bit position for SPI_RSER_EOQF_RE. /
Kojto	90:cb3d968589d8	1693	#define BM_SPI_RSER_EOQF_RE (0x10000000U) /!< Bit mask for SPI_RSER_EOQF_RE. /
Kojto	90:cb3d968589d8	1694	#define BS_SPI_RSER_EOQF_RE (1U) /!< Bit field size in bits for SPI_RSER_EOQF_RE. /
Kojto	90:cb3d968589d8	1695
Kojto	90:cb3d968589d8	1696	/! @brief Read current value of the SPI_RSER_EOQF_RE field. /
Kojto	90:cb3d968589d8	1697	#define BR_SPI_RSER_EOQF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE))
Kojto	90:cb3d968589d8	1698
Kojto	90:cb3d968589d8	1699	/! @brief Format value for bitfield SPI_RSER_EOQF_RE. /
Kojto	90:cb3d968589d8	1700	#define BF_SPI_RSER_EOQF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_EOQF_RE) & BM_SPI_RSER_EOQF_RE)
Kojto	90:cb3d968589d8	1701
Kojto	90:cb3d968589d8	1702	/! @brief Set the EOQF_RE field to a new value. /
Kojto	90:cb3d968589d8	1703	#define BW_SPI_RSER_EOQF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE) = (v))
Kojto	90:cb3d968589d8	1704	/@}/
Kojto	90:cb3d968589d8	1705
Kojto	90:cb3d968589d8	1706	/*!
Kojto	90:cb3d968589d8	1707	* @name Register SPI_RSER, field TCF_RE[31] (RW)
Kojto	90:cb3d968589d8	1708	*
Kojto	90:cb3d968589d8	1709	* Enables TCF flag in the SR to generate an interrupt request.
Kojto	90:cb3d968589d8	1710	*
Kojto	90:cb3d968589d8	1711	* Values:
Kojto	90:cb3d968589d8	1712	* - 0 - TCF interrupt requests are disabled.
Kojto	90:cb3d968589d8	1713	* - 1 - TCF interrupt requests are enabled.
Kojto	90:cb3d968589d8	1714	*/
Kojto	90:cb3d968589d8	1715	/@{/
Kojto	90:cb3d968589d8	1716	#define BP_SPI_RSER_TCF_RE (31U) /!< Bit position for SPI_RSER_TCF_RE. /
Kojto	90:cb3d968589d8	1717	#define BM_SPI_RSER_TCF_RE (0x80000000U) /!< Bit mask for SPI_RSER_TCF_RE. /
Kojto	90:cb3d968589d8	1718	#define BS_SPI_RSER_TCF_RE (1U) /!< Bit field size in bits for SPI_RSER_TCF_RE. /
Kojto	90:cb3d968589d8	1719
Kojto	90:cb3d968589d8	1720	/! @brief Read current value of the SPI_RSER_TCF_RE field. /
Kojto	90:cb3d968589d8	1721	#define BR_SPI_RSER_TCF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE))
Kojto	90:cb3d968589d8	1722
Kojto	90:cb3d968589d8	1723	/! @brief Format value for bitfield SPI_RSER_TCF_RE. /
Kojto	90:cb3d968589d8	1724	#define BF_SPI_RSER_TCF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TCF_RE) & BM_SPI_RSER_TCF_RE)
Kojto	90:cb3d968589d8	1725
Kojto	90:cb3d968589d8	1726	/! @brief Set the TCF_RE field to a new value. /
Kojto	90:cb3d968589d8	1727	#define BW_SPI_RSER_TCF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE) = (v))
Kojto	90:cb3d968589d8	1728	/@}/
Kojto	90:cb3d968589d8	1729
Kojto	90:cb3d968589d8	1730	/*******************************************************************************
Kojto	90:cb3d968589d8	1731	* HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode
Kojto	90:cb3d968589d8	1732	******************************************************************************/
Kojto	90:cb3d968589d8	1733
Kojto	90:cb3d968589d8	1734	/*!
Kojto	90:cb3d968589d8	1735	* @brief HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode (RW)
Kojto	90:cb3d968589d8	1736	*
Kojto	90:cb3d968589d8	1737	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1738	*
Kojto	90:cb3d968589d8	1739	* Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
Kojto	90:cb3d968589d8	1740	* transfers all 32 bits to the TX FIFO. In Master mode, the register transfers
Kojto	90:cb3d968589d8	1741	* 16 bits of data and 16 bits of command information. In Slave mode, all 32 bits
Kojto	90:cb3d968589d8	1742	* can be used as data, supporting up to 32-bit frame operation. A read access
Kojto	90:cb3d968589d8	1743	* of PUSHR returns the topmost TX FIFO entry. When the module is disabled,
Kojto	90:cb3d968589d8	1744	* writing to this register does not update the FIFO. Therefore, any reads performed
Kojto	90:cb3d968589d8	1745	* while the module is disabled return the last PUSHR write performed while the
Kojto	90:cb3d968589d8	1746	* module was still enabled.
Kojto	90:cb3d968589d8	1747	*/
Kojto	90:cb3d968589d8	1748	typedef union _hw_spi_pushr
Kojto	90:cb3d968589d8	1749	{
Kojto	90:cb3d968589d8	1750	uint32_t U;
Kojto	90:cb3d968589d8	1751	struct _hw_spi_pushr_bitfields
Kojto	90:cb3d968589d8	1752	{
Kojto	90:cb3d968589d8	1753	uint32_t TXDATA : 16; /!< [15:0] Transmit Data /
Kojto	90:cb3d968589d8	1754	uint32_t PCS : 6; /!< [21:16] /
Kojto	90:cb3d968589d8	1755	uint32_t RESERVED0 : 4; /!< [25:22] /
Kojto	90:cb3d968589d8	1756	uint32_t CTCNT : 1; /!< [26] Clear Transfer Counter /
Kojto	90:cb3d968589d8	1757	uint32_t EOQ : 1; /!< [27] End Of Queue /
Kojto	90:cb3d968589d8	1758	uint32_t CTAS : 3; /*!< [30:28] Clock and Transfer Attributes Select
Kojto	90:cb3d968589d8	1759	* */
Kojto	90:cb3d968589d8	1760	uint32_t CONT : 1; /*!< [31] Continuous Peripheral Chip Select Enable
Kojto	90:cb3d968589d8	1761	* */
Kojto	90:cb3d968589d8	1762	} B;
Kojto	90:cb3d968589d8	1763	} hw_spi_pushr_t;
Kojto	90:cb3d968589d8	1764
Kojto	90:cb3d968589d8	1765	/*!
Kojto	90:cb3d968589d8	1766	* @name Constants and macros for entire SPI_PUSHR register
Kojto	90:cb3d968589d8	1767	*/
Kojto	90:cb3d968589d8	1768	/@{/
Kojto	90:cb3d968589d8	1769	#define HW_SPI_PUSHR_ADDR(x) ((x) + 0x34U)
Kojto	90:cb3d968589d8	1770
Kojto	90:cb3d968589d8	1771	#define HW_SPI_PUSHR(x) ((__IO hw_spi_pushr_t ) HW_SPI_PUSHR_ADDR(x))
Kojto	90:cb3d968589d8	1772	#define HW_SPI_PUSHR_RD(x) (HW_SPI_PUSHR(x).U)
Kojto	90:cb3d968589d8	1773	#define HW_SPI_PUSHR_WR(x, v) (HW_SPI_PUSHR(x).U = (v))
Kojto	90:cb3d968589d8	1774	#define HW_SPI_PUSHR_SET(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1775	#define HW_SPI_PUSHR_CLR(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1776	#define HW_SPI_PUSHR_TOG(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1777	/@}/
Kojto	90:cb3d968589d8	1778
Kojto	90:cb3d968589d8	1779	/*
Kojto	90:cb3d968589d8	1780	* Constants & macros for individual SPI_PUSHR bitfields
Kojto	90:cb3d968589d8	1781	*/
Kojto	90:cb3d968589d8	1782
Kojto	90:cb3d968589d8	1783	/*!
Kojto	90:cb3d968589d8	1784	* @name Register SPI_PUSHR, field TXDATA[15:0] (RW)
Kojto	90:cb3d968589d8	1785	*
Kojto	90:cb3d968589d8	1786	* Holds SPI data to be transferred according to the associated SPI command.
Kojto	90:cb3d968589d8	1787	*/
Kojto	90:cb3d968589d8	1788	/@{/
Kojto	90:cb3d968589d8	1789	#define BP_SPI_PUSHR_TXDATA (0U) /!< Bit position for SPI_PUSHR_TXDATA. /
Kojto	90:cb3d968589d8	1790	#define BM_SPI_PUSHR_TXDATA (0x0000FFFFU) /!< Bit mask for SPI_PUSHR_TXDATA. /
Kojto	90:cb3d968589d8	1791	#define BS_SPI_PUSHR_TXDATA (16U) /!< Bit field size in bits for SPI_PUSHR_TXDATA. /
Kojto	90:cb3d968589d8	1792
Kojto	90:cb3d968589d8	1793	/! @brief Read current value of the SPI_PUSHR_TXDATA field. /
Kojto	90:cb3d968589d8	1794	#define BR_SPI_PUSHR_TXDATA(x) (HW_SPI_PUSHR(x).B.TXDATA)
Kojto	90:cb3d968589d8	1795
Kojto	90:cb3d968589d8	1796	/! @brief Format value for bitfield SPI_PUSHR_TXDATA. /
Kojto	90:cb3d968589d8	1797	#define BF_SPI_PUSHR_TXDATA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_TXDATA) & BM_SPI_PUSHR_TXDATA)
Kojto	90:cb3d968589d8	1798
Kojto	90:cb3d968589d8	1799	/! @brief Set the TXDATA field to a new value. /
Kojto	90:cb3d968589d8	1800	#define BW_SPI_PUSHR_TXDATA(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_TXDATA) \| BF_SPI_PUSHR_TXDATA(v)))
Kojto	90:cb3d968589d8	1801	/@}/
Kojto	90:cb3d968589d8	1802
Kojto	90:cb3d968589d8	1803	/*!
Kojto	90:cb3d968589d8	1804	* @name Register SPI_PUSHR, field PCS[21:16] (RW)
Kojto	90:cb3d968589d8	1805	*
Kojto	90:cb3d968589d8	1806	* Select which PCS signals are to be asserted for the transfer. Refer to the
Kojto	90:cb3d968589d8	1807	* chip configuration details for the number of PCS signals used in this MCU.
Kojto	90:cb3d968589d8	1808	*
Kojto	90:cb3d968589d8	1809	* Values:
Kojto	90:cb3d968589d8	1810	* - 0 - Negate the PCS[x] signal.
Kojto	90:cb3d968589d8	1811	* - 1 - Assert the PCS[x] signal.
Kojto	90:cb3d968589d8	1812	*/
Kojto	90:cb3d968589d8	1813	/@{/
Kojto	90:cb3d968589d8	1814	#define BP_SPI_PUSHR_PCS (16U) /!< Bit position for SPI_PUSHR_PCS. /
Kojto	90:cb3d968589d8	1815	#define BM_SPI_PUSHR_PCS (0x003F0000U) /!< Bit mask for SPI_PUSHR_PCS. /
Kojto	90:cb3d968589d8	1816	#define BS_SPI_PUSHR_PCS (6U) /!< Bit field size in bits for SPI_PUSHR_PCS. /
Kojto	90:cb3d968589d8	1817
Kojto	90:cb3d968589d8	1818	/! @brief Read current value of the SPI_PUSHR_PCS field. /
Kojto	90:cb3d968589d8	1819	#define BR_SPI_PUSHR_PCS(x) (HW_SPI_PUSHR(x).B.PCS)
Kojto	90:cb3d968589d8	1820
Kojto	90:cb3d968589d8	1821	/! @brief Format value for bitfield SPI_PUSHR_PCS. /
Kojto	90:cb3d968589d8	1822	#define BF_SPI_PUSHR_PCS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_PCS) & BM_SPI_PUSHR_PCS)
Kojto	90:cb3d968589d8	1823
Kojto	90:cb3d968589d8	1824	/! @brief Set the PCS field to a new value. /
Kojto	90:cb3d968589d8	1825	#define BW_SPI_PUSHR_PCS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_PCS) \| BF_SPI_PUSHR_PCS(v)))
Kojto	90:cb3d968589d8	1826	/@}/
Kojto	90:cb3d968589d8	1827
Kojto	90:cb3d968589d8	1828	/*!
Kojto	90:cb3d968589d8	1829	* @name Register SPI_PUSHR, field CTCNT[26] (RW)
Kojto	90:cb3d968589d8	1830	*
Kojto	90:cb3d968589d8	1831	* Clears the TCNT field in the TCR register. The TCNT field is cleared before
Kojto	90:cb3d968589d8	1832	* the module starts transmitting the current SPI frame.
Kojto	90:cb3d968589d8	1833	*
Kojto	90:cb3d968589d8	1834	* Values:
Kojto	90:cb3d968589d8	1835	* - 0 - Do not clear the TCR[TCNT] field.
Kojto	90:cb3d968589d8	1836	* - 1 - Clear the TCR[TCNT] field.
Kojto	90:cb3d968589d8	1837	*/
Kojto	90:cb3d968589d8	1838	/@{/
Kojto	90:cb3d968589d8	1839	#define BP_SPI_PUSHR_CTCNT (26U) /!< Bit position for SPI_PUSHR_CTCNT. /
Kojto	90:cb3d968589d8	1840	#define BM_SPI_PUSHR_CTCNT (0x04000000U) /!< Bit mask for SPI_PUSHR_CTCNT. /
Kojto	90:cb3d968589d8	1841	#define BS_SPI_PUSHR_CTCNT (1U) /!< Bit field size in bits for SPI_PUSHR_CTCNT. /
Kojto	90:cb3d968589d8	1842
Kojto	90:cb3d968589d8	1843	/! @brief Read current value of the SPI_PUSHR_CTCNT field. /
Kojto	90:cb3d968589d8	1844	#define BR_SPI_PUSHR_CTCNT(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT))
Kojto	90:cb3d968589d8	1845
Kojto	90:cb3d968589d8	1846	/! @brief Format value for bitfield SPI_PUSHR_CTCNT. /
Kojto	90:cb3d968589d8	1847	#define BF_SPI_PUSHR_CTCNT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_CTCNT) & BM_SPI_PUSHR_CTCNT)
Kojto	90:cb3d968589d8	1848
Kojto	90:cb3d968589d8	1849	/! @brief Set the CTCNT field to a new value. /
Kojto	90:cb3d968589d8	1850	#define BW_SPI_PUSHR_CTCNT(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT) = (v))
Kojto	90:cb3d968589d8	1851	/@}/
Kojto	90:cb3d968589d8	1852
Kojto	90:cb3d968589d8	1853	/*!
Kojto	90:cb3d968589d8	1854	* @name Register SPI_PUSHR, field EOQ[27] (RW)
Kojto	90:cb3d968589d8	1855	*
Kojto	90:cb3d968589d8	1856	* Host software uses this bit to signal to the module that the current SPI
Kojto	90:cb3d968589d8	1857	* transfer is the last in a queue. At the end of the transfer, the EOQF bit in the
Kojto	90:cb3d968589d8	1858	* SR is set.
Kojto	90:cb3d968589d8	1859	*
Kojto	90:cb3d968589d8	1860	* Values:
Kojto	90:cb3d968589d8	1861	* - 0 - The SPI data is not the last data to transfer.
Kojto	90:cb3d968589d8	1862	* - 1 - The SPI data is the last data to transfer.
Kojto	90:cb3d968589d8	1863	*/
Kojto	90:cb3d968589d8	1864	/@{/
Kojto	90:cb3d968589d8	1865	#define BP_SPI_PUSHR_EOQ (27U) /!< Bit position for SPI_PUSHR_EOQ. /
Kojto	90:cb3d968589d8	1866	#define BM_SPI_PUSHR_EOQ (0x08000000U) /!< Bit mask for SPI_PUSHR_EOQ. /
Kojto	90:cb3d968589d8	1867	#define BS_SPI_PUSHR_EOQ (1U) /!< Bit field size in bits for SPI_PUSHR_EOQ. /
Kojto	90:cb3d968589d8	1868
Kojto	90:cb3d968589d8	1869	/! @brief Read current value of the SPI_PUSHR_EOQ field. /
Kojto	90:cb3d968589d8	1870	#define BR_SPI_PUSHR_EOQ(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ))
Kojto	90:cb3d968589d8	1871
Kojto	90:cb3d968589d8	1872	/! @brief Format value for bitfield SPI_PUSHR_EOQ. /
Kojto	90:cb3d968589d8	1873	#define BF_SPI_PUSHR_EOQ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_EOQ) & BM_SPI_PUSHR_EOQ)
Kojto	90:cb3d968589d8	1874
Kojto	90:cb3d968589d8	1875	/! @brief Set the EOQ field to a new value. /
Kojto	90:cb3d968589d8	1876	#define BW_SPI_PUSHR_EOQ(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ) = (v))
Kojto	90:cb3d968589d8	1877	/@}/
Kojto	90:cb3d968589d8	1878
Kojto	90:cb3d968589d8	1879	/*!
Kojto	90:cb3d968589d8	1880	* @name Register SPI_PUSHR, field CTAS[30:28] (RW)
Kojto	90:cb3d968589d8	1881	*
Kojto	90:cb3d968589d8	1882	* Selects which CTAR to use in master mode to specify the transfer attributes
Kojto	90:cb3d968589d8	1883	* for the associated SPI frame. In SPI Slave mode, CTAR0 is used. See the chip
Kojto	90:cb3d968589d8	1884	* configuration details to determine how many CTARs this device has. You should
Kojto	90:cb3d968589d8	1885	* not program a value in this field for a register that is not present.
Kojto	90:cb3d968589d8	1886	*
Kojto	90:cb3d968589d8	1887	* Values:
Kojto	90:cb3d968589d8	1888	* - 000 - CTAR0
Kojto	90:cb3d968589d8	1889	* - 001 - CTAR1
Kojto	90:cb3d968589d8	1890	* - 010 - Reserved
Kojto	90:cb3d968589d8	1891	* - 011 - Reserved
Kojto	90:cb3d968589d8	1892	* - 100 - Reserved
Kojto	90:cb3d968589d8	1893	* - 101 - Reserved
Kojto	90:cb3d968589d8	1894	* - 110 - Reserved
Kojto	90:cb3d968589d8	1895	* - 111 - Reserved
Kojto	90:cb3d968589d8	1896	*/
Kojto	90:cb3d968589d8	1897	/@{/
Kojto	90:cb3d968589d8	1898	#define BP_SPI_PUSHR_CTAS (28U) /!< Bit position for SPI_PUSHR_CTAS. /
Kojto	90:cb3d968589d8	1899	#define BM_SPI_PUSHR_CTAS (0x70000000U) /!< Bit mask for SPI_PUSHR_CTAS. /
Kojto	90:cb3d968589d8	1900	#define BS_SPI_PUSHR_CTAS (3U) /!< Bit field size in bits for SPI_PUSHR_CTAS. /
Kojto	90:cb3d968589d8	1901
Kojto	90:cb3d968589d8	1902	/! @brief Read current value of the SPI_PUSHR_CTAS field. /
Kojto	90:cb3d968589d8	1903	#define BR_SPI_PUSHR_CTAS(x) (HW_SPI_PUSHR(x).B.CTAS)
Kojto	90:cb3d968589d8	1904
Kojto	90:cb3d968589d8	1905	/! @brief Format value for bitfield SPI_PUSHR_CTAS. /
Kojto	90:cb3d968589d8	1906	#define BF_SPI_PUSHR_CTAS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_CTAS) & BM_SPI_PUSHR_CTAS)
Kojto	90:cb3d968589d8	1907
Kojto	90:cb3d968589d8	1908	/! @brief Set the CTAS field to a new value. /
Kojto	90:cb3d968589d8	1909	#define BW_SPI_PUSHR_CTAS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_CTAS) \| BF_SPI_PUSHR_CTAS(v)))
Kojto	90:cb3d968589d8	1910	/@}/
Kojto	90:cb3d968589d8	1911
Kojto	90:cb3d968589d8	1912	/*!
Kojto	90:cb3d968589d8	1913	* @name Register SPI_PUSHR, field CONT[31] (RW)
Kojto	90:cb3d968589d8	1914	*
Kojto	90:cb3d968589d8	1915	* Selects a continuous selection format. The bit is used in SPI Master mode.
Kojto	90:cb3d968589d8	1916	* The bit enables the selected PCS signals to remain asserted between transfers.
Kojto	90:cb3d968589d8	1917	*
Kojto	90:cb3d968589d8	1918	* Values:
Kojto	90:cb3d968589d8	1919	* - 0 - Return PCSn signals to their inactive state between transfers.
Kojto	90:cb3d968589d8	1920	* - 1 - Keep PCSn signals asserted between transfers.
Kojto	90:cb3d968589d8	1921	*/
Kojto	90:cb3d968589d8	1922	/@{/
Kojto	90:cb3d968589d8	1923	#define BP_SPI_PUSHR_CONT (31U) /!< Bit position for SPI_PUSHR_CONT. /
Kojto	90:cb3d968589d8	1924	#define BM_SPI_PUSHR_CONT (0x80000000U) /!< Bit mask for SPI_PUSHR_CONT. /
Kojto	90:cb3d968589d8	1925	#define BS_SPI_PUSHR_CONT (1U) /!< Bit field size in bits for SPI_PUSHR_CONT. /
Kojto	90:cb3d968589d8	1926
Kojto	90:cb3d968589d8	1927	/! @brief Read current value of the SPI_PUSHR_CONT field. /
Kojto	90:cb3d968589d8	1928	#define BR_SPI_PUSHR_CONT(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT))
Kojto	90:cb3d968589d8	1929
Kojto	90:cb3d968589d8	1930	/! @brief Format value for bitfield SPI_PUSHR_CONT. /
Kojto	90:cb3d968589d8	1931	#define BF_SPI_PUSHR_CONT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_CONT) & BM_SPI_PUSHR_CONT)
Kojto	90:cb3d968589d8	1932
Kojto	90:cb3d968589d8	1933	/! @brief Set the CONT field to a new value. /
Kojto	90:cb3d968589d8	1934	#define BW_SPI_PUSHR_CONT(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT) = (v))
Kojto	90:cb3d968589d8	1935	/@}/
Kojto	90:cb3d968589d8	1936	/*******************************************************************************
Kojto	90:cb3d968589d8	1937	* HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
Kojto	90:cb3d968589d8	1938	******************************************************************************/
Kojto	90:cb3d968589d8	1939
Kojto	90:cb3d968589d8	1940	/*!
Kojto	90:cb3d968589d8	1941	* @brief HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode (RW)
Kojto	90:cb3d968589d8	1942	*
Kojto	90:cb3d968589d8	1943	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1944	*
Kojto	90:cb3d968589d8	1945	* Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
Kojto	90:cb3d968589d8	1946	* to PUSHR transfers all 32 bits to the TX FIFO. In master mode, the register
Kojto	90:cb3d968589d8	1947	* transfers 16 bits of data and 16 bits of command information to the TX FIFO. In
Kojto	90:cb3d968589d8	1948	* slave mode, all 32 register bits can be used as data, supporting up to 32-bit
Kojto	90:cb3d968589d8	1949	* SPI Frame operation.
Kojto	90:cb3d968589d8	1950	*/
Kojto	90:cb3d968589d8	1951	typedef union _hw_spi_pushr_slave
Kojto	90:cb3d968589d8	1952	{
Kojto	90:cb3d968589d8	1953	uint32_t U;
Kojto	90:cb3d968589d8	1954	struct _hw_spi_pushr_slave_bitfields
Kojto	90:cb3d968589d8	1955	{
Kojto	90:cb3d968589d8	1956	uint32_t TXDATA : 32; /!< [31:0] Transmit Data /
Kojto	90:cb3d968589d8	1957	} B;
Kojto	90:cb3d968589d8	1958	} hw_spi_pushr_slave_t;
Kojto	90:cb3d968589d8	1959
Kojto	90:cb3d968589d8	1960	/*!
Kojto	90:cb3d968589d8	1961	* @name Constants and macros for entire SPI_PUSHR_SLAVE register
Kojto	90:cb3d968589d8	1962	*/
Kojto	90:cb3d968589d8	1963	/@{/
Kojto	90:cb3d968589d8	1964	#define HW_SPI_PUSHR_SLAVE_ADDR(x) ((x) + 0x34U)
Kojto	90:cb3d968589d8	1965
Kojto	90:cb3d968589d8	1966	#define HW_SPI_PUSHR_SLAVE(x) ((__IO hw_spi_pushr_slave_t ) HW_SPI_PUSHR_SLAVE_ADDR(x))
Kojto	90:cb3d968589d8	1967	#define HW_SPI_PUSHR_SLAVE_RD(x) (HW_SPI_PUSHR_SLAVE(x).U)
Kojto	90:cb3d968589d8	1968	#define HW_SPI_PUSHR_SLAVE_WR(x, v) (HW_SPI_PUSHR_SLAVE(x).U = (v))
Kojto	90:cb3d968589d8	1969	#define HW_SPI_PUSHR_SLAVE_SET(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1970	#define HW_SPI_PUSHR_SLAVE_CLR(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1971	#define HW_SPI_PUSHR_SLAVE_TOG(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1972	/@}/
Kojto	90:cb3d968589d8	1973
Kojto	90:cb3d968589d8	1974	/*
Kojto	90:cb3d968589d8	1975	* Constants & macros for individual SPI_PUSHR_SLAVE bitfields
Kojto	90:cb3d968589d8	1976	*/
Kojto	90:cb3d968589d8	1977
Kojto	90:cb3d968589d8	1978	/*!
Kojto	90:cb3d968589d8	1979	* @name Register SPI_PUSHR_SLAVE, field TXDATA[31:0] (RW)
Kojto	90:cb3d968589d8	1980	*
Kojto	90:cb3d968589d8	1981	* Holds SPI data to be transferred according to the associated SPI command.
Kojto	90:cb3d968589d8	1982	*/
Kojto	90:cb3d968589d8	1983	/@{/
Kojto	90:cb3d968589d8	1984	#define BP_SPI_PUSHR_SLAVE_TXDATA (0U) /!< Bit position for SPI_PUSHR_SLAVE_TXDATA. /
Kojto	90:cb3d968589d8	1985	#define BM_SPI_PUSHR_SLAVE_TXDATA (0xFFFFFFFFU) /!< Bit mask for SPI_PUSHR_SLAVE_TXDATA. /
Kojto	90:cb3d968589d8	1986	#define BS_SPI_PUSHR_SLAVE_TXDATA (32U) /!< Bit field size in bits for SPI_PUSHR_SLAVE_TXDATA. /
Kojto	90:cb3d968589d8	1987
Kojto	90:cb3d968589d8	1988	/! @brief Read current value of the SPI_PUSHR_SLAVE_TXDATA field. /
Kojto	90:cb3d968589d8	1989	#define BR_SPI_PUSHR_SLAVE_TXDATA(x) (HW_SPI_PUSHR_SLAVE(x).U)
Kojto	90:cb3d968589d8	1990
Kojto	90:cb3d968589d8	1991	/! @brief Format value for bitfield SPI_PUSHR_SLAVE_TXDATA. /
Kojto	90:cb3d968589d8	1992	#define BF_SPI_PUSHR_SLAVE_TXDATA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_SLAVE_TXDATA) & BM_SPI_PUSHR_SLAVE_TXDATA)
Kojto	90:cb3d968589d8	1993
Kojto	90:cb3d968589d8	1994	/! @brief Set the TXDATA field to a new value. /
Kojto	90:cb3d968589d8	1995	#define BW_SPI_PUSHR_SLAVE_TXDATA(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, v))
Kojto	90:cb3d968589d8	1996	/@}/
Kojto	90:cb3d968589d8	1997
Kojto	90:cb3d968589d8	1998	/*******************************************************************************
Kojto	90:cb3d968589d8	1999	* HW_SPI_POPR - POP RX FIFO Register
Kojto	90:cb3d968589d8	2000	******************************************************************************/
Kojto	90:cb3d968589d8	2001
Kojto	90:cb3d968589d8	2002	/*!
Kojto	90:cb3d968589d8	2003	* @brief HW_SPI_POPR - POP RX FIFO Register (RO)
Kojto	90:cb3d968589d8	2004	*
Kojto	90:cb3d968589d8	2005	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2006	*
Kojto	90:cb3d968589d8	2007	* POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the
Kojto	90:cb3d968589d8	2008	* POPR have the same effect on the RX FIFO as 32-bit read accesses. A write to
Kojto	90:cb3d968589d8	2009	* this register will generate a Transfer Error.
Kojto	90:cb3d968589d8	2010	*/
Kojto	90:cb3d968589d8	2011	typedef union _hw_spi_popr
Kojto	90:cb3d968589d8	2012	{
Kojto	90:cb3d968589d8	2013	uint32_t U;
Kojto	90:cb3d968589d8	2014	struct _hw_spi_popr_bitfields
Kojto	90:cb3d968589d8	2015	{
Kojto	90:cb3d968589d8	2016	uint32_t RXDATA : 32; /!< [31:0] Received Data /
Kojto	90:cb3d968589d8	2017	} B;
Kojto	90:cb3d968589d8	2018	} hw_spi_popr_t;
Kojto	90:cb3d968589d8	2019
Kojto	90:cb3d968589d8	2020	/*!
Kojto	90:cb3d968589d8	2021	* @name Constants and macros for entire SPI_POPR register
Kojto	90:cb3d968589d8	2022	*/
Kojto	90:cb3d968589d8	2023	/@{/
Kojto	90:cb3d968589d8	2024	#define HW_SPI_POPR_ADDR(x) ((x) + 0x38U)
Kojto	90:cb3d968589d8	2025
Kojto	90:cb3d968589d8	2026	#define HW_SPI_POPR(x) ((__I hw_spi_popr_t ) HW_SPI_POPR_ADDR(x))
Kojto	90:cb3d968589d8	2027	#define HW_SPI_POPR_RD(x) (HW_SPI_POPR(x).U)
Kojto	90:cb3d968589d8	2028	/@}/
Kojto	90:cb3d968589d8	2029
Kojto	90:cb3d968589d8	2030	/*
Kojto	90:cb3d968589d8	2031	* Constants & macros for individual SPI_POPR bitfields
Kojto	90:cb3d968589d8	2032	*/
Kojto	90:cb3d968589d8	2033
Kojto	90:cb3d968589d8	2034	/*!
Kojto	90:cb3d968589d8	2035	* @name Register SPI_POPR, field RXDATA[31:0] (RO)
Kojto	90:cb3d968589d8	2036	*
Kojto	90:cb3d968589d8	2037	* Contains the SPI data from the RX FIFO entry to which the Pop Next Data
Kojto	90:cb3d968589d8	2038	* Pointer points.
Kojto	90:cb3d968589d8	2039	*/
Kojto	90:cb3d968589d8	2040	/@{/
Kojto	90:cb3d968589d8	2041	#define BP_SPI_POPR_RXDATA (0U) /!< Bit position for SPI_POPR_RXDATA. /
Kojto	90:cb3d968589d8	2042	#define BM_SPI_POPR_RXDATA (0xFFFFFFFFU) /!< Bit mask for SPI_POPR_RXDATA. /
Kojto	90:cb3d968589d8	2043	#define BS_SPI_POPR_RXDATA (32U) /!< Bit field size in bits for SPI_POPR_RXDATA. /
Kojto	90:cb3d968589d8	2044
Kojto	90:cb3d968589d8	2045	/! @brief Read current value of the SPI_POPR_RXDATA field. /
Kojto	90:cb3d968589d8	2046	#define BR_SPI_POPR_RXDATA(x) (HW_SPI_POPR(x).U)
Kojto	90:cb3d968589d8	2047	/@}/
Kojto	90:cb3d968589d8	2048
Kojto	90:cb3d968589d8	2049	/*******************************************************************************
Kojto	90:cb3d968589d8	2050	* HW_SPI_TXFRn - Transmit FIFO Registers
Kojto	90:cb3d968589d8	2051	******************************************************************************/
Kojto	90:cb3d968589d8	2052
Kojto	90:cb3d968589d8	2053	/*!
Kojto	90:cb3d968589d8	2054	* @brief HW_SPI_TXFRn - Transmit FIFO Registers (RO)
Kojto	90:cb3d968589d8	2055	*
Kojto	90:cb3d968589d8	2056	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2057	*
Kojto	90:cb3d968589d8	2058	* TXFRn registers provide visibility into the TX FIFO for debugging purposes.
Kojto	90:cb3d968589d8	2059	* Each register is an entry in the TX FIFO. The registers are read-only and
Kojto	90:cb3d968589d8	2060	* cannot be modified. Reading the TXFRx registers does not alter the state of the TX
Kojto	90:cb3d968589d8	2061	* FIFO.
Kojto	90:cb3d968589d8	2062	*/
Kojto	90:cb3d968589d8	2063	typedef union _hw_spi_txfrn
Kojto	90:cb3d968589d8	2064	{
Kojto	90:cb3d968589d8	2065	uint32_t U;
Kojto	90:cb3d968589d8	2066	struct _hw_spi_txfrn_bitfields
Kojto	90:cb3d968589d8	2067	{
Kojto	90:cb3d968589d8	2068	uint32_t TXDATA : 16; /!< [15:0] Transmit Data /
Kojto	90:cb3d968589d8	2069	uint32_t TXCMD_TXDATA : 16; /*!< [31:16] Transmit Command or Transmit
Kojto	90:cb3d968589d8	2070	* Data */
Kojto	90:cb3d968589d8	2071	} B;
Kojto	90:cb3d968589d8	2072	} hw_spi_txfrn_t;
Kojto	90:cb3d968589d8	2073
Kojto	90:cb3d968589d8	2074	/*!
Kojto	90:cb3d968589d8	2075	* @name Constants and macros for entire SPI_TXFRn register
Kojto	90:cb3d968589d8	2076	*/
Kojto	90:cb3d968589d8	2077	/@{/
Kojto	90:cb3d968589d8	2078	#define HW_SPI_TXFRn_COUNT (4U)
Kojto	90:cb3d968589d8	2079
Kojto	90:cb3d968589d8	2080	#define HW_SPI_TXFRn_ADDR(x, n) ((x) + 0x3CU + (0x4U * (n)))
Kojto	90:cb3d968589d8	2081
Kojto	90:cb3d968589d8	2082	#define HW_SPI_TXFRn(x, n) ((__I hw_spi_txfrn_t ) HW_SPI_TXFRn_ADDR(x, n))
Kojto	90:cb3d968589d8	2083	#define HW_SPI_TXFRn_RD(x, n) (HW_SPI_TXFRn(x, n).U)
Kojto	90:cb3d968589d8	2084	/@}/
Kojto	90:cb3d968589d8	2085
Kojto	90:cb3d968589d8	2086	/*
Kojto	90:cb3d968589d8	2087	* Constants & macros for individual SPI_TXFRn bitfields
Kojto	90:cb3d968589d8	2088	*/
Kojto	90:cb3d968589d8	2089
Kojto	90:cb3d968589d8	2090	/*!
Kojto	90:cb3d968589d8	2091	* @name Register SPI_TXFRn, field TXDATA[15:0] (RO)
Kojto	90:cb3d968589d8	2092	*
Kojto	90:cb3d968589d8	2093	* Contains the SPI data to be shifted out.
Kojto	90:cb3d968589d8	2094	*/
Kojto	90:cb3d968589d8	2095	/@{/
Kojto	90:cb3d968589d8	2096	#define BP_SPI_TXFRn_TXDATA (0U) /!< Bit position for SPI_TXFRn_TXDATA. /
Kojto	90:cb3d968589d8	2097	#define BM_SPI_TXFRn_TXDATA (0x0000FFFFU) /!< Bit mask for SPI_TXFRn_TXDATA. /
Kojto	90:cb3d968589d8	2098	#define BS_SPI_TXFRn_TXDATA (16U) /!< Bit field size in bits for SPI_TXFRn_TXDATA. /
Kojto	90:cb3d968589d8	2099
Kojto	90:cb3d968589d8	2100	/! @brief Read current value of the SPI_TXFRn_TXDATA field. /
Kojto	90:cb3d968589d8	2101	#define BR_SPI_TXFRn_TXDATA(x, n) (HW_SPI_TXFRn(x, n).B.TXDATA)
Kojto	90:cb3d968589d8	2102	/@}/
Kojto	90:cb3d968589d8	2103
Kojto	90:cb3d968589d8	2104	/*!
Kojto	90:cb3d968589d8	2105	* @name Register SPI_TXFRn, field TXCMD_TXDATA[31:16] (RO)
Kojto	90:cb3d968589d8	2106	*
Kojto	90:cb3d968589d8	2107	* In Master mode the TXCMD field contains the command that sets the transfer
Kojto	90:cb3d968589d8	2108	* attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
Kojto	90:cb3d968589d8	2109	* the SPI data to be shifted out.
Kojto	90:cb3d968589d8	2110	*/
Kojto	90:cb3d968589d8	2111	/@{/
Kojto	90:cb3d968589d8	2112	#define BP_SPI_TXFRn_TXCMD_TXDATA (16U) /!< Bit position for SPI_TXFRn_TXCMD_TXDATA. /
Kojto	90:cb3d968589d8	2113	#define BM_SPI_TXFRn_TXCMD_TXDATA (0xFFFF0000U) /!< Bit mask for SPI_TXFRn_TXCMD_TXDATA. /
Kojto	90:cb3d968589d8	2114	#define BS_SPI_TXFRn_TXCMD_TXDATA (16U) /!< Bit field size in bits for SPI_TXFRn_TXCMD_TXDATA. /
Kojto	90:cb3d968589d8	2115
Kojto	90:cb3d968589d8	2116	/! @brief Read current value of the SPI_TXFRn_TXCMD_TXDATA field. /
Kojto	90:cb3d968589d8	2117	#define BR_SPI_TXFRn_TXCMD_TXDATA(x, n) (HW_SPI_TXFRn(x, n).B.TXCMD_TXDATA)
Kojto	90:cb3d968589d8	2118	/@}/
Kojto	90:cb3d968589d8	2119
Kojto	90:cb3d968589d8	2120	/*******************************************************************************
Kojto	90:cb3d968589d8	2121	* HW_SPI_RXFRn - Receive FIFO Registers
Kojto	90:cb3d968589d8	2122	******************************************************************************/
Kojto	90:cb3d968589d8	2123
Kojto	90:cb3d968589d8	2124	/*!
Kojto	90:cb3d968589d8	2125	* @brief HW_SPI_RXFRn - Receive FIFO Registers (RO)
Kojto	90:cb3d968589d8	2126	*
Kojto	90:cb3d968589d8	2127	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2128	*
Kojto	90:cb3d968589d8	2129	* RXFRn provide visibility into the RX FIFO for debugging purposes. Each
Kojto	90:cb3d968589d8	2130	* register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
Kojto	90:cb3d968589d8	2131	* RXFRx registers does not alter the state of the RX FIFO.
Kojto	90:cb3d968589d8	2132	*/
Kojto	90:cb3d968589d8	2133	typedef union _hw_spi_rxfrn
Kojto	90:cb3d968589d8	2134	{
Kojto	90:cb3d968589d8	2135	uint32_t U;
Kojto	90:cb3d968589d8	2136	struct _hw_spi_rxfrn_bitfields
Kojto	90:cb3d968589d8	2137	{
Kojto	90:cb3d968589d8	2138	uint32_t RXDATA : 32; /!< [31:0] Receive Data /
Kojto	90:cb3d968589d8	2139	} B;
Kojto	90:cb3d968589d8	2140	} hw_spi_rxfrn_t;
Kojto	90:cb3d968589d8	2141
Kojto	90:cb3d968589d8	2142	/*!
Kojto	90:cb3d968589d8	2143	* @name Constants and macros for entire SPI_RXFRn register
Kojto	90:cb3d968589d8	2144	*/
Kojto	90:cb3d968589d8	2145	/@{/
Kojto	90:cb3d968589d8	2146	#define HW_SPI_RXFRn_COUNT (4U)
Kojto	90:cb3d968589d8	2147
Kojto	90:cb3d968589d8	2148	#define HW_SPI_RXFRn_ADDR(x, n) ((x) + 0x7CU + (0x4U * (n)))
Kojto	90:cb3d968589d8	2149
Kojto	90:cb3d968589d8	2150	#define HW_SPI_RXFRn(x, n) ((__I hw_spi_rxfrn_t ) HW_SPI_RXFRn_ADDR(x, n))
Kojto	90:cb3d968589d8	2151	#define HW_SPI_RXFRn_RD(x, n) (HW_SPI_RXFRn(x, n).U)
Kojto	90:cb3d968589d8	2152	/@}/
Kojto	90:cb3d968589d8	2153
Kojto	90:cb3d968589d8	2154	/*
Kojto	90:cb3d968589d8	2155	* Constants & macros for individual SPI_RXFRn bitfields
Kojto	90:cb3d968589d8	2156	*/
Kojto	90:cb3d968589d8	2157
Kojto	90:cb3d968589d8	2158	/*!
Kojto	90:cb3d968589d8	2159	* @name Register SPI_RXFRn, field RXDATA[31:0] (RO)
Kojto	90:cb3d968589d8	2160	*
Kojto	90:cb3d968589d8	2161	* Contains the received SPI data.
Kojto	90:cb3d968589d8	2162	*/
Kojto	90:cb3d968589d8	2163	/@{/
Kojto	90:cb3d968589d8	2164	#define BP_SPI_RXFRn_RXDATA (0U) /!< Bit position for SPI_RXFRn_RXDATA. /
Kojto	90:cb3d968589d8	2165	#define BM_SPI_RXFRn_RXDATA (0xFFFFFFFFU) /!< Bit mask for SPI_RXFRn_RXDATA. /
Kojto	90:cb3d968589d8	2166	#define BS_SPI_RXFRn_RXDATA (32U) /!< Bit field size in bits for SPI_RXFRn_RXDATA. /
Kojto	90:cb3d968589d8	2167
Kojto	90:cb3d968589d8	2168	/! @brief Read current value of the SPI_RXFRn_RXDATA field. /
Kojto	90:cb3d968589d8	2169	#define BR_SPI_RXFRn_RXDATA(x, n) (HW_SPI_RXFRn(x, n).U)
Kojto	90:cb3d968589d8	2170	/@}/
Kojto	90:cb3d968589d8	2171
Kojto	90:cb3d968589d8	2172	/*
Kojto	90:cb3d968589d8	2173	** Start of section using anonymous unions
Kojto	90:cb3d968589d8	2174	*/
Kojto	90:cb3d968589d8	2175
Kojto	90:cb3d968589d8	2176	#if defined(__ARMCC_VERSION)
Kojto	90:cb3d968589d8	2177	#pragma push
Kojto	90:cb3d968589d8	2178	#pragma anon_unions
Kojto	90:cb3d968589d8	2179	#elif defined(__CWCC__)
Kojto	90:cb3d968589d8	2180	#pragma push
Kojto	90:cb3d968589d8	2181	#pragma cpp_extensions on
Kojto	90:cb3d968589d8	2182	#elif defined(__GNUC__)
Kojto	90:cb3d968589d8	2183	/* anonymous unions are enabled by default */
Kojto	90:cb3d968589d8	2184	#elif defined(__IAR_SYSTEMS_ICC__)
Kojto	90:cb3d968589d8	2185	#pragma language=extended
Kojto	90:cb3d968589d8	2186	#else
Kojto	90:cb3d968589d8	2187	#error Not supported compiler type
Kojto	90:cb3d968589d8	2188	#endif
Kojto	90:cb3d968589d8	2189
Kojto	90:cb3d968589d8	2190	/*******************************************************************************
Kojto	90:cb3d968589d8	2191	* hw_spi_t - module struct
Kojto	90:cb3d968589d8	2192	******************************************************************************/
Kojto	90:cb3d968589d8	2193	/*!
Kojto	90:cb3d968589d8	2194	* @brief All SPI module registers.
Kojto	90:cb3d968589d8	2195	*/
Kojto	90:cb3d968589d8	2196	#pragma pack(1)
Kojto	90:cb3d968589d8	2197	typedef struct _hw_spi
Kojto	90:cb3d968589d8	2198	{
Kojto	90:cb3d968589d8	2199	__IO hw_spi_mcr_t MCR; /!< [0x0] Module Configuration Register /
Kojto	90:cb3d968589d8	2200	uint8_t _reserved0[4];
Kojto	90:cb3d968589d8	2201	__IO hw_spi_tcr_t TCR; /!< [0x8] Transfer Count Register /
Kojto	90:cb3d968589d8	2202	union {
Kojto	90:cb3d968589d8	2203	__IO hw_spi_ctarn_t CTARn[2]; /!< [0xC] Clock and Transfer Attributes Register (In Master Mode) /
Kojto	90:cb3d968589d8	2204	__IO hw_spi_ctarn_slave_t CTARn_SLAVE[1]; /!< [0xC] Clock and Transfer Attributes Register (In Slave Mode) /
Kojto	90:cb3d968589d8	2205	};
Kojto	90:cb3d968589d8	2206	uint8_t _reserved1[24];
Kojto	90:cb3d968589d8	2207	__IO hw_spi_sr_t SR; /!< [0x2C] Status Register /
Kojto	90:cb3d968589d8	2208	__IO hw_spi_rser_t RSER; /!< [0x30] DMA/Interrupt Request Select and Enable Register /
Kojto	90:cb3d968589d8	2209	union {
Kojto	90:cb3d968589d8	2210	__IO hw_spi_pushr_t PUSHR; /!< [0x34] PUSH TX FIFO Register In Master Mode /
Kojto	90:cb3d968589d8	2211	__IO hw_spi_pushr_slave_t PUSHR_SLAVE; /!< [0x34] PUSH TX FIFO Register In Slave Mode /
Kojto	90:cb3d968589d8	2212	};
Kojto	90:cb3d968589d8	2213	__I hw_spi_popr_t POPR; /!< [0x38] POP RX FIFO Register /
Kojto	90:cb3d968589d8	2214	__I hw_spi_txfrn_t TXFRn[4]; /!< [0x3C] Transmit FIFO Registers /
Kojto	90:cb3d968589d8	2215	uint8_t _reserved2[48];
Kojto	90:cb3d968589d8	2216	__I hw_spi_rxfrn_t RXFRn[4]; /!< [0x7C] Receive FIFO Registers /
Kojto	90:cb3d968589d8	2217	} hw_spi_t;
Kojto	90:cb3d968589d8	2218	#pragma pack()
Kojto	90:cb3d968589d8	2219
Kojto	90:cb3d968589d8	2220	/! @brief Macro to access all SPI registers. /
Kojto	90:cb3d968589d8	2221	/! @param x SPI module instance base address. /
Kojto	90:cb3d968589d8	2222	/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto	90:cb3d968589d8	2223	* use the '&' operator, like <code>&HW_SPI(SPI0_BASE)</code>. */
Kojto	90:cb3d968589d8	2224	#define HW_SPI(x) ((hw_spi_t )(x))
Kojto	90:cb3d968589d8	2225
Kojto	90:cb3d968589d8	2226	/*
Kojto	90:cb3d968589d8	2227	** End of section using anonymous unions
Kojto	90:cb3d968589d8	2228	*/
Kojto	90:cb3d968589d8	2229
Kojto	90:cb3d968589d8	2230	#if defined(__ARMCC_VERSION)
Kojto	90:cb3d968589d8	2231	#pragma pop
Kojto	90:cb3d968589d8	2232	#elif defined(__CWCC__)
Kojto	90:cb3d968589d8	2233	#pragma pop
Kojto	90:cb3d968589d8	2234	#elif defined(__GNUC__)
Kojto	90:cb3d968589d8	2235	/* leave anonymous unions enabled */
Kojto	90:cb3d968589d8	2236	#elif defined(__IAR_SYSTEMS_ICC__)
Kojto	90:cb3d968589d8	2237	#pragma language=default
Kojto	90:cb3d968589d8	2238	#else
Kojto	90:cb3d968589d8	2239	#error Not supported compiler type
Kojto	90:cb3d968589d8	2240	#endif
Kojto	90:cb3d968589d8	2241
Kojto	90:cb3d968589d8	2242	#endif /* __HW_SPI_REGISTERS_H__ */
Kojto	90:cb3d968589d8	2243	/* EOF */