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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_sim.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:: Kojto
Date:: Wed Aug 05 13:16:35 2015 +0100
Revision:: 104:b9ad9a133dc7
Parent:: 90:cb3d968589d8

Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	90:cb3d968589d8	1	/*
Kojto	90:cb3d968589d8	2	** ###################################################################
Kojto	90:cb3d968589d8	3	** Compilers: Keil ARM C/C++ Compiler
Kojto	90:cb3d968589d8	4	** Freescale C/C++ for Embedded ARM
Kojto	90:cb3d968589d8	5	** GNU C Compiler
Kojto	90:cb3d968589d8	6	** IAR ANSI C/C++ Compiler for ARM
Kojto	90:cb3d968589d8	7	**
Kojto	90:cb3d968589d8	8	** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto	90:cb3d968589d8	9	** Version: rev. 2.5, 2014-02-10
Kojto	90:cb3d968589d8	10	** Build: b140604
Kojto	90:cb3d968589d8	11	**
Kojto	90:cb3d968589d8	12	** Abstract:
Kojto	90:cb3d968589d8	13	** Extension to the CMSIS register access layer header.
Kojto	90:cb3d968589d8	14	**
Kojto	90:cb3d968589d8	15	** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto	90:cb3d968589d8	16	** All rights reserved.
Kojto	90:cb3d968589d8	17	**
Kojto	90:cb3d968589d8	18	** Redistribution and use in source and binary forms, with or without modification,
Kojto	90:cb3d968589d8	19	** are permitted provided that the following conditions are met:
Kojto	90:cb3d968589d8	20	**
Kojto	90:cb3d968589d8	21	** o Redistributions of source code must retain the above copyright notice, this list
Kojto	90:cb3d968589d8	22	** of conditions and the following disclaimer.
Kojto	90:cb3d968589d8	23	**
Kojto	90:cb3d968589d8	24	** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto	90:cb3d968589d8	25	** list of conditions and the following disclaimer in the documentation and/or
Kojto	90:cb3d968589d8	26	** other materials provided with the distribution.
Kojto	90:cb3d968589d8	27	**
Kojto	90:cb3d968589d8	28	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto	90:cb3d968589d8	29	** contributors may be used to endorse or promote products derived from this
Kojto	90:cb3d968589d8	30	** software without specific prior written permission.
Kojto	90:cb3d968589d8	31	**
Kojto	90:cb3d968589d8	32	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto	90:cb3d968589d8	33	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto	90:cb3d968589d8	34	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	90:cb3d968589d8	35	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto	90:cb3d968589d8	36	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto	90:cb3d968589d8	37	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto	90:cb3d968589d8	38	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto	90:cb3d968589d8	39	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto	90:cb3d968589d8	40	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto	90:cb3d968589d8	41	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	90:cb3d968589d8	42	**
Kojto	90:cb3d968589d8	43	** http: www.freescale.com
Kojto	90:cb3d968589d8	44	** mail: support@freescale.com
Kojto	90:cb3d968589d8	45	**
Kojto	90:cb3d968589d8	46	** Revisions:
Kojto	90:cb3d968589d8	47	** - rev. 1.0 (2013-08-12)
Kojto	90:cb3d968589d8	48	** Initial version.
Kojto	90:cb3d968589d8	49	** - rev. 2.0 (2013-10-29)
Kojto	90:cb3d968589d8	50	** Register accessor macros added to the memory map.
Kojto	90:cb3d968589d8	51	** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto	90:cb3d968589d8	52	** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto	90:cb3d968589d8	53	** System initialization updated.
Kojto	90:cb3d968589d8	54	** MCG - registers updated.
Kojto	90:cb3d968589d8	55	** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto	90:cb3d968589d8	56	** - rev. 2.1 (2013-10-30)
Kojto	90:cb3d968589d8	57	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto	90:cb3d968589d8	58	** - rev. 2.2 (2013-12-09)
Kojto	90:cb3d968589d8	59	** DMA - EARS register removed.
Kojto	90:cb3d968589d8	60	** AIPS0, AIPS1 - MPRA register updated.
Kojto	90:cb3d968589d8	61	** - rev. 2.3 (2014-01-24)
Kojto	90:cb3d968589d8	62	** Update according to reference manual rev. 2
Kojto	90:cb3d968589d8	63	** ENET, MCG, MCM, SIM, USB - registers updated
Kojto	90:cb3d968589d8	64	** - rev. 2.4 (2014-02-10)
Kojto	90:cb3d968589d8	65	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	66	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	67	** - rev. 2.5 (2014-02-10)
Kojto	90:cb3d968589d8	68	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	69	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	70	** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto	90:cb3d968589d8	71	**
Kojto	90:cb3d968589d8	72	** ###################################################################
Kojto	90:cb3d968589d8	73	*/
Kojto	90:cb3d968589d8	74
Kojto	90:cb3d968589d8	75	/*
Kojto	90:cb3d968589d8	76	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto	90:cb3d968589d8	77	*
Kojto	90:cb3d968589d8	78	* This file was generated automatically and any changes may be lost.
Kojto	90:cb3d968589d8	79	*/
Kojto	90:cb3d968589d8	80	#ifndef __HW_SIM_REGISTERS_H__
Kojto	90:cb3d968589d8	81	#define __HW_SIM_REGISTERS_H__
Kojto	90:cb3d968589d8	82
Kojto	90:cb3d968589d8	83	#include "MK64F12.h"
Kojto	90:cb3d968589d8	84	#include "fsl_bitaccess.h"
Kojto	90:cb3d968589d8	85
Kojto	90:cb3d968589d8	86	/*
Kojto	90:cb3d968589d8	87	* MK64F12 SIM
Kojto	90:cb3d968589d8	88	*
Kojto	90:cb3d968589d8	89	* System Integration Module
Kojto	90:cb3d968589d8	90	*
Kojto	90:cb3d968589d8	91	* Registers defined in this header file:
Kojto	90:cb3d968589d8	92	* - HW_SIM_SOPT1 - System Options Register 1
Kojto	90:cb3d968589d8	93	* - HW_SIM_SOPT1CFG - SOPT1 Configuration Register
Kojto	90:cb3d968589d8	94	* - HW_SIM_SOPT2 - System Options Register 2
Kojto	90:cb3d968589d8	95	* - HW_SIM_SOPT4 - System Options Register 4
Kojto	90:cb3d968589d8	96	* - HW_SIM_SOPT5 - System Options Register 5
Kojto	90:cb3d968589d8	97	* - HW_SIM_SOPT7 - System Options Register 7
Kojto	90:cb3d968589d8	98	* - HW_SIM_SDID - System Device Identification Register
Kojto	90:cb3d968589d8	99	* - HW_SIM_SCGC1 - System Clock Gating Control Register 1
Kojto	90:cb3d968589d8	100	* - HW_SIM_SCGC2 - System Clock Gating Control Register 2
Kojto	90:cb3d968589d8	101	* - HW_SIM_SCGC3 - System Clock Gating Control Register 3
Kojto	90:cb3d968589d8	102	* - HW_SIM_SCGC4 - System Clock Gating Control Register 4
Kojto	90:cb3d968589d8	103	* - HW_SIM_SCGC5 - System Clock Gating Control Register 5
Kojto	90:cb3d968589d8	104	* - HW_SIM_SCGC6 - System Clock Gating Control Register 6
Kojto	90:cb3d968589d8	105	* - HW_SIM_SCGC7 - System Clock Gating Control Register 7
Kojto	90:cb3d968589d8	106	* - HW_SIM_CLKDIV1 - System Clock Divider Register 1
Kojto	90:cb3d968589d8	107	* - HW_SIM_CLKDIV2 - System Clock Divider Register 2
Kojto	90:cb3d968589d8	108	* - HW_SIM_FCFG1 - Flash Configuration Register 1
Kojto	90:cb3d968589d8	109	* - HW_SIM_FCFG2 - Flash Configuration Register 2
Kojto	90:cb3d968589d8	110	* - HW_SIM_UIDH - Unique Identification Register High
Kojto	90:cb3d968589d8	111	* - HW_SIM_UIDMH - Unique Identification Register Mid-High
Kojto	90:cb3d968589d8	112	* - HW_SIM_UIDML - Unique Identification Register Mid Low
Kojto	90:cb3d968589d8	113	* - HW_SIM_UIDL - Unique Identification Register Low
Kojto	90:cb3d968589d8	114	*
Kojto	90:cb3d968589d8	115	* - hw_sim_t - Struct containing all module registers.
Kojto	90:cb3d968589d8	116	*/
Kojto	90:cb3d968589d8	117
Kojto	90:cb3d968589d8	118	#define HW_SIM_INSTANCE_COUNT (1U) /!< Number of instances of the SIM module. /
Kojto	90:cb3d968589d8	119
Kojto	90:cb3d968589d8	120	/*******************************************************************************
Kojto	90:cb3d968589d8	121	* HW_SIM_SOPT1 - System Options Register 1
Kojto	90:cb3d968589d8	122	******************************************************************************/
Kojto	90:cb3d968589d8	123
Kojto	90:cb3d968589d8	124	/*!
Kojto	90:cb3d968589d8	125	* @brief HW_SIM_SOPT1 - System Options Register 1 (RW)
Kojto	90:cb3d968589d8	126	*
Kojto	90:cb3d968589d8	127	* Reset value: 0x80000000U
Kojto	90:cb3d968589d8	128	*
Kojto	90:cb3d968589d8	129	* The SOPT1 register is only reset on POR or LVD.
Kojto	90:cb3d968589d8	130	*/
Kojto	90:cb3d968589d8	131	typedef union _hw_sim_sopt1
Kojto	90:cb3d968589d8	132	{
Kojto	90:cb3d968589d8	133	uint32_t U;
Kojto	90:cb3d968589d8	134	struct _hw_sim_sopt1_bitfields
Kojto	90:cb3d968589d8	135	{
Kojto	90:cb3d968589d8	136	uint32_t RESERVED0 : 12; /!< [11:0] /
Kojto	90:cb3d968589d8	137	uint32_t RAMSIZE : 4; /!< [15:12] RAM size /
Kojto	90:cb3d968589d8	138	uint32_t RESERVED1 : 2; /!< [17:16] /
Kojto	90:cb3d968589d8	139	uint32_t OSC32KSEL : 2; /!< [19:18] 32K oscillator clock select /
Kojto	90:cb3d968589d8	140	uint32_t RESERVED2 : 9; /!< [28:20] /
Kojto	90:cb3d968589d8	141	uint32_t USBVSTBY : 1; /*!< [29] USB voltage regulator in standby
Kojto	90:cb3d968589d8	142	* mode during VLPR and VLPW modes */
Kojto	90:cb3d968589d8	143	uint32_t USBSSTBY : 1; /*!< [30] USB voltage regulator in standby
Kojto	90:cb3d968589d8	144	* mode during Stop, VLPS, LLS and VLLS modes. */
Kojto	90:cb3d968589d8	145	uint32_t USBREGEN : 1; /!< [31] USB voltage regulator enable /
Kojto	90:cb3d968589d8	146	} B;
Kojto	90:cb3d968589d8	147	} hw_sim_sopt1_t;
Kojto	90:cb3d968589d8	148
Kojto	90:cb3d968589d8	149	/*!
Kojto	90:cb3d968589d8	150	* @name Constants and macros for entire SIM_SOPT1 register
Kojto	90:cb3d968589d8	151	*/
Kojto	90:cb3d968589d8	152	/@{/
Kojto	90:cb3d968589d8	153	#define HW_SIM_SOPT1_ADDR(x) ((x) + 0x0U)
Kojto	90:cb3d968589d8	154
Kojto	90:cb3d968589d8	155	#define HW_SIM_SOPT1(x) ((__IO hw_sim_sopt1_t ) HW_SIM_SOPT1_ADDR(x))
Kojto	90:cb3d968589d8	156	#define HW_SIM_SOPT1_RD(x) (HW_SIM_SOPT1(x).U)
Kojto	90:cb3d968589d8	157	#define HW_SIM_SOPT1_WR(x, v) (HW_SIM_SOPT1(x).U = (v))
Kojto	90:cb3d968589d8	158	#define HW_SIM_SOPT1_SET(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) \| (v)))
Kojto	90:cb3d968589d8	159	#define HW_SIM_SOPT1_CLR(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	160	#define HW_SIM_SOPT1_TOG(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	161	/@}/
Kojto	90:cb3d968589d8	162
Kojto	90:cb3d968589d8	163	/*
Kojto	90:cb3d968589d8	164	* Constants & macros for individual SIM_SOPT1 bitfields
Kojto	90:cb3d968589d8	165	*/
Kojto	90:cb3d968589d8	166
Kojto	90:cb3d968589d8	167	/*!
Kojto	90:cb3d968589d8	168	* @name Register SIM_SOPT1, field RAMSIZE[15:12] (RO)
Kojto	90:cb3d968589d8	169	*
Kojto	90:cb3d968589d8	170	* This field specifies the amount of system RAM available on the device.
Kojto	90:cb3d968589d8	171	*
Kojto	90:cb3d968589d8	172	* Values:
Kojto	90:cb3d968589d8	173	* - 0001 - 8 KB
Kojto	90:cb3d968589d8	174	* - 0011 - 16 KB
Kojto	90:cb3d968589d8	175	* - 0100 - 24 KB
Kojto	90:cb3d968589d8	176	* - 0101 - 32 KB
Kojto	90:cb3d968589d8	177	* - 0110 - 48 KB
Kojto	90:cb3d968589d8	178	* - 0111 - 64 KB
Kojto	90:cb3d968589d8	179	* - 1000 - 96 KB
Kojto	90:cb3d968589d8	180	* - 1001 - 128 KB
Kojto	90:cb3d968589d8	181	* - 1011 - 256 KB
Kojto	90:cb3d968589d8	182	*/
Kojto	90:cb3d968589d8	183	/@{/
Kojto	90:cb3d968589d8	184	#define BP_SIM_SOPT1_RAMSIZE (12U) /!< Bit position for SIM_SOPT1_RAMSIZE. /
Kojto	90:cb3d968589d8	185	#define BM_SIM_SOPT1_RAMSIZE (0x0000F000U) /!< Bit mask for SIM_SOPT1_RAMSIZE. /
Kojto	90:cb3d968589d8	186	#define BS_SIM_SOPT1_RAMSIZE (4U) /!< Bit field size in bits for SIM_SOPT1_RAMSIZE. /
Kojto	90:cb3d968589d8	187
Kojto	90:cb3d968589d8	188	/! @brief Read current value of the SIM_SOPT1_RAMSIZE field. /
Kojto	90:cb3d968589d8	189	#define BR_SIM_SOPT1_RAMSIZE(x) (HW_SIM_SOPT1(x).B.RAMSIZE)
Kojto	90:cb3d968589d8	190	/@}/
Kojto	90:cb3d968589d8	191
Kojto	90:cb3d968589d8	192	/*!
Kojto	90:cb3d968589d8	193	* @name Register SIM_SOPT1, field OSC32KSEL[19:18] (RW)
Kojto	90:cb3d968589d8	194	*
Kojto	90:cb3d968589d8	195	* Selects the 32 kHz clock source (ERCLK32K) for LPTMR. This field is reset
Kojto	90:cb3d968589d8	196	* only on POR/LVD.
Kojto	90:cb3d968589d8	197	*
Kojto	90:cb3d968589d8	198	* Values:
Kojto	90:cb3d968589d8	199	* - 00 - System oscillator (OSC32KCLK)
Kojto	90:cb3d968589d8	200	* - 01 - Reserved
Kojto	90:cb3d968589d8	201	* - 10 - RTC 32.768kHz oscillator
Kojto	90:cb3d968589d8	202	* - 11 - LPO 1 kHz
Kojto	90:cb3d968589d8	203	*/
Kojto	90:cb3d968589d8	204	/@{/
Kojto	90:cb3d968589d8	205	#define BP_SIM_SOPT1_OSC32KSEL (18U) /!< Bit position for SIM_SOPT1_OSC32KSEL. /
Kojto	90:cb3d968589d8	206	#define BM_SIM_SOPT1_OSC32KSEL (0x000C0000U) /!< Bit mask for SIM_SOPT1_OSC32KSEL. /
Kojto	90:cb3d968589d8	207	#define BS_SIM_SOPT1_OSC32KSEL (2U) /!< Bit field size in bits for SIM_SOPT1_OSC32KSEL. /
Kojto	90:cb3d968589d8	208
Kojto	90:cb3d968589d8	209	/! @brief Read current value of the SIM_SOPT1_OSC32KSEL field. /
Kojto	90:cb3d968589d8	210	#define BR_SIM_SOPT1_OSC32KSEL(x) (HW_SIM_SOPT1(x).B.OSC32KSEL)
Kojto	90:cb3d968589d8	211
Kojto	90:cb3d968589d8	212	/! @brief Format value for bitfield SIM_SOPT1_OSC32KSEL. /
Kojto	90:cb3d968589d8	213	#define BF_SIM_SOPT1_OSC32KSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_OSC32KSEL) & BM_SIM_SOPT1_OSC32KSEL)
Kojto	90:cb3d968589d8	214
Kojto	90:cb3d968589d8	215	/! @brief Set the OSC32KSEL field to a new value. /
Kojto	90:cb3d968589d8	216	#define BW_SIM_SOPT1_OSC32KSEL(x, v) (HW_SIM_SOPT1_WR(x, (HW_SIM_SOPT1_RD(x) & ~BM_SIM_SOPT1_OSC32KSEL) \| BF_SIM_SOPT1_OSC32KSEL(v)))
Kojto	90:cb3d968589d8	217	/@}/
Kojto	90:cb3d968589d8	218
Kojto	90:cb3d968589d8	219	/*!
Kojto	90:cb3d968589d8	220	* @name Register SIM_SOPT1, field USBVSTBY[29] (RW)
Kojto	90:cb3d968589d8	221	*
Kojto	90:cb3d968589d8	222	* Controls whether the USB voltage regulator is placed in standby mode during
Kojto	90:cb3d968589d8	223	* VLPR and VLPW modes.
Kojto	90:cb3d968589d8	224	*
Kojto	90:cb3d968589d8	225	* Values:
Kojto	90:cb3d968589d8	226	* - 0 - USB voltage regulator not in standby during VLPR and VLPW modes.
Kojto	90:cb3d968589d8	227	* - 1 - USB voltage regulator in standby during VLPR and VLPW modes.
Kojto	90:cb3d968589d8	228	*/
Kojto	90:cb3d968589d8	229	/@{/
Kojto	90:cb3d968589d8	230	#define BP_SIM_SOPT1_USBVSTBY (29U) /!< Bit position for SIM_SOPT1_USBVSTBY. /
Kojto	90:cb3d968589d8	231	#define BM_SIM_SOPT1_USBVSTBY (0x20000000U) /!< Bit mask for SIM_SOPT1_USBVSTBY. /
Kojto	90:cb3d968589d8	232	#define BS_SIM_SOPT1_USBVSTBY (1U) /!< Bit field size in bits for SIM_SOPT1_USBVSTBY. /
Kojto	90:cb3d968589d8	233
Kojto	90:cb3d968589d8	234	/! @brief Read current value of the SIM_SOPT1_USBVSTBY field. /
Kojto	90:cb3d968589d8	235	#define BR_SIM_SOPT1_USBVSTBY(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBVSTBY))
Kojto	90:cb3d968589d8	236
Kojto	90:cb3d968589d8	237	/! @brief Format value for bitfield SIM_SOPT1_USBVSTBY. /
Kojto	90:cb3d968589d8	238	#define BF_SIM_SOPT1_USBVSTBY(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBVSTBY) & BM_SIM_SOPT1_USBVSTBY)
Kojto	90:cb3d968589d8	239
Kojto	90:cb3d968589d8	240	/! @brief Set the USBVSTBY field to a new value. /
Kojto	90:cb3d968589d8	241	#define BW_SIM_SOPT1_USBVSTBY(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBVSTBY) = (v))
Kojto	90:cb3d968589d8	242	/@}/
Kojto	90:cb3d968589d8	243
Kojto	90:cb3d968589d8	244	/*!
Kojto	90:cb3d968589d8	245	* @name Register SIM_SOPT1, field USBSSTBY[30] (RW)
Kojto	90:cb3d968589d8	246	*
Kojto	90:cb3d968589d8	247	* Controls whether the USB voltage regulator is placed in standby mode during
Kojto	90:cb3d968589d8	248	* Stop, VLPS, LLS and VLLS modes.
Kojto	90:cb3d968589d8	249	*
Kojto	90:cb3d968589d8	250	* Values:
Kojto	90:cb3d968589d8	251	* - 0 - USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS
Kojto	90:cb3d968589d8	252	* modes.
Kojto	90:cb3d968589d8	253	* - 1 - USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
Kojto	90:cb3d968589d8	254	*/
Kojto	90:cb3d968589d8	255	/@{/
Kojto	90:cb3d968589d8	256	#define BP_SIM_SOPT1_USBSSTBY (30U) /!< Bit position for SIM_SOPT1_USBSSTBY. /
Kojto	90:cb3d968589d8	257	#define BM_SIM_SOPT1_USBSSTBY (0x40000000U) /!< Bit mask for SIM_SOPT1_USBSSTBY. /
Kojto	90:cb3d968589d8	258	#define BS_SIM_SOPT1_USBSSTBY (1U) /!< Bit field size in bits for SIM_SOPT1_USBSSTBY. /
Kojto	90:cb3d968589d8	259
Kojto	90:cb3d968589d8	260	/! @brief Read current value of the SIM_SOPT1_USBSSTBY field. /
Kojto	90:cb3d968589d8	261	#define BR_SIM_SOPT1_USBSSTBY(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBSSTBY))
Kojto	90:cb3d968589d8	262
Kojto	90:cb3d968589d8	263	/! @brief Format value for bitfield SIM_SOPT1_USBSSTBY. /
Kojto	90:cb3d968589d8	264	#define BF_SIM_SOPT1_USBSSTBY(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBSSTBY) & BM_SIM_SOPT1_USBSSTBY)
Kojto	90:cb3d968589d8	265
Kojto	90:cb3d968589d8	266	/! @brief Set the USBSSTBY field to a new value. /
Kojto	90:cb3d968589d8	267	#define BW_SIM_SOPT1_USBSSTBY(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBSSTBY) = (v))
Kojto	90:cb3d968589d8	268	/@}/
Kojto	90:cb3d968589d8	269
Kojto	90:cb3d968589d8	270	/*!
Kojto	90:cb3d968589d8	271	* @name Register SIM_SOPT1, field USBREGEN[31] (RW)
Kojto	90:cb3d968589d8	272	*
Kojto	90:cb3d968589d8	273	* Controls whether the USB voltage regulator is enabled.
Kojto	90:cb3d968589d8	274	*
Kojto	90:cb3d968589d8	275	* Values:
Kojto	90:cb3d968589d8	276	* - 0 - USB voltage regulator is disabled.
Kojto	90:cb3d968589d8	277	* - 1 - USB voltage regulator is enabled.
Kojto	90:cb3d968589d8	278	*/
Kojto	90:cb3d968589d8	279	/@{/
Kojto	90:cb3d968589d8	280	#define BP_SIM_SOPT1_USBREGEN (31U) /!< Bit position for SIM_SOPT1_USBREGEN. /
Kojto	90:cb3d968589d8	281	#define BM_SIM_SOPT1_USBREGEN (0x80000000U) /!< Bit mask for SIM_SOPT1_USBREGEN. /
Kojto	90:cb3d968589d8	282	#define BS_SIM_SOPT1_USBREGEN (1U) /!< Bit field size in bits for SIM_SOPT1_USBREGEN. /
Kojto	90:cb3d968589d8	283
Kojto	90:cb3d968589d8	284	/! @brief Read current value of the SIM_SOPT1_USBREGEN field. /
Kojto	90:cb3d968589d8	285	#define BR_SIM_SOPT1_USBREGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBREGEN))
Kojto	90:cb3d968589d8	286
Kojto	90:cb3d968589d8	287	/! @brief Format value for bitfield SIM_SOPT1_USBREGEN. /
Kojto	90:cb3d968589d8	288	#define BF_SIM_SOPT1_USBREGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBREGEN) & BM_SIM_SOPT1_USBREGEN)
Kojto	90:cb3d968589d8	289
Kojto	90:cb3d968589d8	290	/! @brief Set the USBREGEN field to a new value. /
Kojto	90:cb3d968589d8	291	#define BW_SIM_SOPT1_USBREGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBREGEN) = (v))
Kojto	90:cb3d968589d8	292	/@}/
Kojto	90:cb3d968589d8	293
Kojto	90:cb3d968589d8	294	/*******************************************************************************
Kojto	90:cb3d968589d8	295	* HW_SIM_SOPT1CFG - SOPT1 Configuration Register
Kojto	90:cb3d968589d8	296	******************************************************************************/
Kojto	90:cb3d968589d8	297
Kojto	90:cb3d968589d8	298	/*!
Kojto	90:cb3d968589d8	299	* @brief HW_SIM_SOPT1CFG - SOPT1 Configuration Register (RW)
Kojto	90:cb3d968589d8	300	*
Kojto	90:cb3d968589d8	301	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	302	*
Kojto	90:cb3d968589d8	303	* The SOPT1CFG register is reset on System Reset not VLLS.
Kojto	90:cb3d968589d8	304	*/
Kojto	90:cb3d968589d8	305	typedef union _hw_sim_sopt1cfg
Kojto	90:cb3d968589d8	306	{
Kojto	90:cb3d968589d8	307	uint32_t U;
Kojto	90:cb3d968589d8	308	struct _hw_sim_sopt1cfg_bitfields
Kojto	90:cb3d968589d8	309	{
Kojto	90:cb3d968589d8	310	uint32_t RESERVED0 : 24; /!< [23:0] /
Kojto	90:cb3d968589d8	311	uint32_t URWE : 1; /*!< [24] USB voltage regulator enable write
Kojto	90:cb3d968589d8	312	* enable */
Kojto	90:cb3d968589d8	313	uint32_t UVSWE : 1; /*!< [25] USB voltage regulator VLP standby write
Kojto	90:cb3d968589d8	314	* enable */
Kojto	90:cb3d968589d8	315	uint32_t USSWE : 1; /*!< [26] USB voltage regulator stop standby
Kojto	90:cb3d968589d8	316	* write enable */
Kojto	90:cb3d968589d8	317	uint32_t RESERVED1 : 5; /!< [31:27] /
Kojto	90:cb3d968589d8	318	} B;
Kojto	90:cb3d968589d8	319	} hw_sim_sopt1cfg_t;
Kojto	90:cb3d968589d8	320
Kojto	90:cb3d968589d8	321	/*!
Kojto	90:cb3d968589d8	322	* @name Constants and macros for entire SIM_SOPT1CFG register
Kojto	90:cb3d968589d8	323	*/
Kojto	90:cb3d968589d8	324	/@{/
Kojto	90:cb3d968589d8	325	#define HW_SIM_SOPT1CFG_ADDR(x) ((x) + 0x4U)
Kojto	90:cb3d968589d8	326
Kojto	90:cb3d968589d8	327	#define HW_SIM_SOPT1CFG(x) ((__IO hw_sim_sopt1cfg_t ) HW_SIM_SOPT1CFG_ADDR(x))
Kojto	90:cb3d968589d8	328	#define HW_SIM_SOPT1CFG_RD(x) (HW_SIM_SOPT1CFG(x).U)
Kojto	90:cb3d968589d8	329	#define HW_SIM_SOPT1CFG_WR(x, v) (HW_SIM_SOPT1CFG(x).U = (v))
Kojto	90:cb3d968589d8	330	#define HW_SIM_SOPT1CFG_SET(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) \| (v)))
Kojto	90:cb3d968589d8	331	#define HW_SIM_SOPT1CFG_CLR(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	332	#define HW_SIM_SOPT1CFG_TOG(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	333	/@}/
Kojto	90:cb3d968589d8	334
Kojto	90:cb3d968589d8	335	/*
Kojto	90:cb3d968589d8	336	* Constants & macros for individual SIM_SOPT1CFG bitfields
Kojto	90:cb3d968589d8	337	*/
Kojto	90:cb3d968589d8	338
Kojto	90:cb3d968589d8	339	/*!
Kojto	90:cb3d968589d8	340	* @name Register SIM_SOPT1CFG, field URWE[24] (RW)
Kojto	90:cb3d968589d8	341	*
Kojto	90:cb3d968589d8	342	* Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This
Kojto	90:cb3d968589d8	343	* register bit clears after a write to USBREGEN.
Kojto	90:cb3d968589d8	344	*
Kojto	90:cb3d968589d8	345	* Values:
Kojto	90:cb3d968589d8	346	* - 0 - SOPT1 USBREGEN cannot be written.
Kojto	90:cb3d968589d8	347	* - 1 - SOPT1 USBREGEN can be written.
Kojto	90:cb3d968589d8	348	*/
Kojto	90:cb3d968589d8	349	/@{/
Kojto	90:cb3d968589d8	350	#define BP_SIM_SOPT1CFG_URWE (24U) /!< Bit position for SIM_SOPT1CFG_URWE. /
Kojto	90:cb3d968589d8	351	#define BM_SIM_SOPT1CFG_URWE (0x01000000U) /!< Bit mask for SIM_SOPT1CFG_URWE. /
Kojto	90:cb3d968589d8	352	#define BS_SIM_SOPT1CFG_URWE (1U) /!< Bit field size in bits for SIM_SOPT1CFG_URWE. /
Kojto	90:cb3d968589d8	353
Kojto	90:cb3d968589d8	354	/! @brief Read current value of the SIM_SOPT1CFG_URWE field. /
Kojto	90:cb3d968589d8	355	#define BR_SIM_SOPT1CFG_URWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_URWE))
Kojto	90:cb3d968589d8	356
Kojto	90:cb3d968589d8	357	/! @brief Format value for bitfield SIM_SOPT1CFG_URWE. /
Kojto	90:cb3d968589d8	358	#define BF_SIM_SOPT1CFG_URWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_URWE) & BM_SIM_SOPT1CFG_URWE)
Kojto	90:cb3d968589d8	359
Kojto	90:cb3d968589d8	360	/! @brief Set the URWE field to a new value. /
Kojto	90:cb3d968589d8	361	#define BW_SIM_SOPT1CFG_URWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_URWE) = (v))
Kojto	90:cb3d968589d8	362	/@}/
Kojto	90:cb3d968589d8	363
Kojto	90:cb3d968589d8	364	/*!
Kojto	90:cb3d968589d8	365	* @name Register SIM_SOPT1CFG, field UVSWE[25] (RW)
Kojto	90:cb3d968589d8	366	*
Kojto	90:cb3d968589d8	367	* Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written.
Kojto	90:cb3d968589d8	368	* This register bit clears after a write to USBVSTBY.
Kojto	90:cb3d968589d8	369	*
Kojto	90:cb3d968589d8	370	* Values:
Kojto	90:cb3d968589d8	371	* - 0 - SOPT1 USBVSTBY cannot be written.
Kojto	90:cb3d968589d8	372	* - 1 - SOPT1 USBVSTBY can be written.
Kojto	90:cb3d968589d8	373	*/
Kojto	90:cb3d968589d8	374	/@{/
Kojto	90:cb3d968589d8	375	#define BP_SIM_SOPT1CFG_UVSWE (25U) /!< Bit position for SIM_SOPT1CFG_UVSWE. /
Kojto	90:cb3d968589d8	376	#define BM_SIM_SOPT1CFG_UVSWE (0x02000000U) /!< Bit mask for SIM_SOPT1CFG_UVSWE. /
Kojto	90:cb3d968589d8	377	#define BS_SIM_SOPT1CFG_UVSWE (1U) /!< Bit field size in bits for SIM_SOPT1CFG_UVSWE. /
Kojto	90:cb3d968589d8	378
Kojto	90:cb3d968589d8	379	/! @brief Read current value of the SIM_SOPT1CFG_UVSWE field. /
Kojto	90:cb3d968589d8	380	#define BR_SIM_SOPT1CFG_UVSWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_UVSWE))
Kojto	90:cb3d968589d8	381
Kojto	90:cb3d968589d8	382	/! @brief Format value for bitfield SIM_SOPT1CFG_UVSWE. /
Kojto	90:cb3d968589d8	383	#define BF_SIM_SOPT1CFG_UVSWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_UVSWE) & BM_SIM_SOPT1CFG_UVSWE)
Kojto	90:cb3d968589d8	384
Kojto	90:cb3d968589d8	385	/! @brief Set the UVSWE field to a new value. /
Kojto	90:cb3d968589d8	386	#define BW_SIM_SOPT1CFG_UVSWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_UVSWE) = (v))
Kojto	90:cb3d968589d8	387	/@}/
Kojto	90:cb3d968589d8	388
Kojto	90:cb3d968589d8	389	/*!
Kojto	90:cb3d968589d8	390	* @name Register SIM_SOPT1CFG, field USSWE[26] (RW)
Kojto	90:cb3d968589d8	391	*
Kojto	90:cb3d968589d8	392	* Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written.
Kojto	90:cb3d968589d8	393	* This register bit clears after a write to USBSSTBY.
Kojto	90:cb3d968589d8	394	*
Kojto	90:cb3d968589d8	395	* Values:
Kojto	90:cb3d968589d8	396	* - 0 - SOPT1 USBSSTBY cannot be written.
Kojto	90:cb3d968589d8	397	* - 1 - SOPT1 USBSSTBY can be written.
Kojto	90:cb3d968589d8	398	*/
Kojto	90:cb3d968589d8	399	/@{/
Kojto	90:cb3d968589d8	400	#define BP_SIM_SOPT1CFG_USSWE (26U) /!< Bit position for SIM_SOPT1CFG_USSWE. /
Kojto	90:cb3d968589d8	401	#define BM_SIM_SOPT1CFG_USSWE (0x04000000U) /!< Bit mask for SIM_SOPT1CFG_USSWE. /
Kojto	90:cb3d968589d8	402	#define BS_SIM_SOPT1CFG_USSWE (1U) /!< Bit field size in bits for SIM_SOPT1CFG_USSWE. /
Kojto	90:cb3d968589d8	403
Kojto	90:cb3d968589d8	404	/! @brief Read current value of the SIM_SOPT1CFG_USSWE field. /
Kojto	90:cb3d968589d8	405	#define BR_SIM_SOPT1CFG_USSWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_USSWE))
Kojto	90:cb3d968589d8	406
Kojto	90:cb3d968589d8	407	/! @brief Format value for bitfield SIM_SOPT1CFG_USSWE. /
Kojto	90:cb3d968589d8	408	#define BF_SIM_SOPT1CFG_USSWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_USSWE) & BM_SIM_SOPT1CFG_USSWE)
Kojto	90:cb3d968589d8	409
Kojto	90:cb3d968589d8	410	/! @brief Set the USSWE field to a new value. /
Kojto	90:cb3d968589d8	411	#define BW_SIM_SOPT1CFG_USSWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_USSWE) = (v))
Kojto	90:cb3d968589d8	412	/@}/
Kojto	90:cb3d968589d8	413
Kojto	90:cb3d968589d8	414	/*******************************************************************************
Kojto	90:cb3d968589d8	415	* HW_SIM_SOPT2 - System Options Register 2
Kojto	90:cb3d968589d8	416	******************************************************************************/
Kojto	90:cb3d968589d8	417
Kojto	90:cb3d968589d8	418	/*!
Kojto	90:cb3d968589d8	419	* @brief HW_SIM_SOPT2 - System Options Register 2 (RW)
Kojto	90:cb3d968589d8	420	*
Kojto	90:cb3d968589d8	421	* Reset value: 0x00001000U
Kojto	90:cb3d968589d8	422	*
Kojto	90:cb3d968589d8	423	* SOPT2 contains the controls for selecting many of the module clock source
Kojto	90:cb3d968589d8	424	* options on this device. See the Clock Distribution chapter for more information
Kojto	90:cb3d968589d8	425	* including clocking diagrams and definitions of device clocks.
Kojto	90:cb3d968589d8	426	*/
Kojto	90:cb3d968589d8	427	typedef union _hw_sim_sopt2
Kojto	90:cb3d968589d8	428	{
Kojto	90:cb3d968589d8	429	uint32_t U;
Kojto	90:cb3d968589d8	430	struct _hw_sim_sopt2_bitfields
Kojto	90:cb3d968589d8	431	{
Kojto	90:cb3d968589d8	432	uint32_t RESERVED0 : 4; /!< [3:0] /
Kojto	90:cb3d968589d8	433	uint32_t RTCCLKOUTSEL : 1; /!< [4] RTC clock out select /
Kojto	90:cb3d968589d8	434	uint32_t CLKOUTSEL : 3; /!< [7:5] CLKOUT select /
Kojto	90:cb3d968589d8	435	uint32_t FBSL : 2; /!< [9:8] FlexBus security level /
Kojto	90:cb3d968589d8	436	uint32_t RESERVED1 : 1; /!< [10] /
Kojto	90:cb3d968589d8	437	uint32_t PTD7PAD : 1; /!< [11] PTD7 pad drive strength /
Kojto	90:cb3d968589d8	438	uint32_t TRACECLKSEL : 1; /!< [12] Debug trace clock select /
Kojto	90:cb3d968589d8	439	uint32_t RESERVED2 : 3; /!< [15:13] /
Kojto	90:cb3d968589d8	440	uint32_t PLLFLLSEL : 2; /!< [17:16] PLL/FLL clock select /
Kojto	90:cb3d968589d8	441	uint32_t USBSRC : 1; /!< [18] USB clock source select /
Kojto	90:cb3d968589d8	442	uint32_t RMIISRC : 1; /!< [19] RMII clock source select /
Kojto	90:cb3d968589d8	443	uint32_t TIMESRC : 2; /*!< [21:20] IEEE 1588 timestamp clock source
Kojto	90:cb3d968589d8	444	* select */
Kojto	90:cb3d968589d8	445	uint32_t RESERVED3 : 6; /!< [27:22] /
Kojto	90:cb3d968589d8	446	uint32_t SDHCSRC : 2; /!< [29:28] SDHC clock source select /
Kojto	90:cb3d968589d8	447	uint32_t RESERVED4 : 2; /!< [31:30] /
Kojto	90:cb3d968589d8	448	} B;
Kojto	90:cb3d968589d8	449	} hw_sim_sopt2_t;
Kojto	90:cb3d968589d8	450
Kojto	90:cb3d968589d8	451	/*!
Kojto	90:cb3d968589d8	452	* @name Constants and macros for entire SIM_SOPT2 register
Kojto	90:cb3d968589d8	453	*/
Kojto	90:cb3d968589d8	454	/@{/
Kojto	90:cb3d968589d8	455	#define HW_SIM_SOPT2_ADDR(x) ((x) + 0x1004U)
Kojto	90:cb3d968589d8	456
Kojto	90:cb3d968589d8	457	#define HW_SIM_SOPT2(x) ((__IO hw_sim_sopt2_t ) HW_SIM_SOPT2_ADDR(x))
Kojto	90:cb3d968589d8	458	#define HW_SIM_SOPT2_RD(x) (HW_SIM_SOPT2(x).U)
Kojto	90:cb3d968589d8	459	#define HW_SIM_SOPT2_WR(x, v) (HW_SIM_SOPT2(x).U = (v))
Kojto	90:cb3d968589d8	460	#define HW_SIM_SOPT2_SET(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) \| (v)))
Kojto	90:cb3d968589d8	461	#define HW_SIM_SOPT2_CLR(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	462	#define HW_SIM_SOPT2_TOG(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	463	/@}/
Kojto	90:cb3d968589d8	464
Kojto	90:cb3d968589d8	465	/*
Kojto	90:cb3d968589d8	466	* Constants & macros for individual SIM_SOPT2 bitfields
Kojto	90:cb3d968589d8	467	*/
Kojto	90:cb3d968589d8	468
Kojto	90:cb3d968589d8	469	/*!
Kojto	90:cb3d968589d8	470	* @name Register SIM_SOPT2, field RTCCLKOUTSEL[4] (RW)
Kojto	90:cb3d968589d8	471	*
Kojto	90:cb3d968589d8	472	* Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the
Kojto	90:cb3d968589d8	473	* RTC_CLKOUT pin.
Kojto	90:cb3d968589d8	474	*
Kojto	90:cb3d968589d8	475	* Values:
Kojto	90:cb3d968589d8	476	* - 0 - RTC 1 Hz clock is output on the RTC_CLKOUT pin.
Kojto	90:cb3d968589d8	477	* - 1 - RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
Kojto	90:cb3d968589d8	478	*/
Kojto	90:cb3d968589d8	479	/@{/
Kojto	90:cb3d968589d8	480	#define BP_SIM_SOPT2_RTCCLKOUTSEL (4U) /!< Bit position for SIM_SOPT2_RTCCLKOUTSEL. /
Kojto	90:cb3d968589d8	481	#define BM_SIM_SOPT2_RTCCLKOUTSEL (0x00000010U) /!< Bit mask for SIM_SOPT2_RTCCLKOUTSEL. /
Kojto	90:cb3d968589d8	482	#define BS_SIM_SOPT2_RTCCLKOUTSEL (1U) /!< Bit field size in bits for SIM_SOPT2_RTCCLKOUTSEL. /
Kojto	90:cb3d968589d8	483
Kojto	90:cb3d968589d8	484	/! @brief Read current value of the SIM_SOPT2_RTCCLKOUTSEL field. /
Kojto	90:cb3d968589d8	485	#define BR_SIM_SOPT2_RTCCLKOUTSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RTCCLKOUTSEL))
Kojto	90:cb3d968589d8	486
Kojto	90:cb3d968589d8	487	/! @brief Format value for bitfield SIM_SOPT2_RTCCLKOUTSEL. /
Kojto	90:cb3d968589d8	488	#define BF_SIM_SOPT2_RTCCLKOUTSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_RTCCLKOUTSEL) & BM_SIM_SOPT2_RTCCLKOUTSEL)
Kojto	90:cb3d968589d8	489
Kojto	90:cb3d968589d8	490	/! @brief Set the RTCCLKOUTSEL field to a new value. /
Kojto	90:cb3d968589d8	491	#define BW_SIM_SOPT2_RTCCLKOUTSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RTCCLKOUTSEL) = (v))
Kojto	90:cb3d968589d8	492	/@}/
Kojto	90:cb3d968589d8	493
Kojto	90:cb3d968589d8	494	/*!
Kojto	90:cb3d968589d8	495	* @name Register SIM_SOPT2, field CLKOUTSEL[7:5] (RW)
Kojto	90:cb3d968589d8	496	*
Kojto	90:cb3d968589d8	497	* Selects the clock to output on the CLKOUT pin.
Kojto	90:cb3d968589d8	498	*
Kojto	90:cb3d968589d8	499	* Values:
Kojto	90:cb3d968589d8	500	* - 000 - FlexBus CLKOUT
Kojto	90:cb3d968589d8	501	* - 001 - Reserved
Kojto	90:cb3d968589d8	502	* - 010 - Flash clock
Kojto	90:cb3d968589d8	503	* - 011 - LPO clock (1 kHz)
Kojto	90:cb3d968589d8	504	* - 100 - MCGIRCLK
Kojto	90:cb3d968589d8	505	* - 101 - RTC 32.768kHz clock
Kojto	90:cb3d968589d8	506	* - 110 - OSCERCLK0
Kojto	90:cb3d968589d8	507	* - 111 - IRC 48 MHz clock
Kojto	90:cb3d968589d8	508	*/
Kojto	90:cb3d968589d8	509	/@{/
Kojto	90:cb3d968589d8	510	#define BP_SIM_SOPT2_CLKOUTSEL (5U) /!< Bit position for SIM_SOPT2_CLKOUTSEL. /
Kojto	90:cb3d968589d8	511	#define BM_SIM_SOPT2_CLKOUTSEL (0x000000E0U) /!< Bit mask for SIM_SOPT2_CLKOUTSEL. /
Kojto	90:cb3d968589d8	512	#define BS_SIM_SOPT2_CLKOUTSEL (3U) /!< Bit field size in bits for SIM_SOPT2_CLKOUTSEL. /
Kojto	90:cb3d968589d8	513
Kojto	90:cb3d968589d8	514	/! @brief Read current value of the SIM_SOPT2_CLKOUTSEL field. /
Kojto	90:cb3d968589d8	515	#define BR_SIM_SOPT2_CLKOUTSEL(x) (HW_SIM_SOPT2(x).B.CLKOUTSEL)
Kojto	90:cb3d968589d8	516
Kojto	90:cb3d968589d8	517	/! @brief Format value for bitfield SIM_SOPT2_CLKOUTSEL. /
Kojto	90:cb3d968589d8	518	#define BF_SIM_SOPT2_CLKOUTSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_CLKOUTSEL) & BM_SIM_SOPT2_CLKOUTSEL)
Kojto	90:cb3d968589d8	519
Kojto	90:cb3d968589d8	520	/! @brief Set the CLKOUTSEL field to a new value. /
Kojto	90:cb3d968589d8	521	#define BW_SIM_SOPT2_CLKOUTSEL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_CLKOUTSEL) \| BF_SIM_SOPT2_CLKOUTSEL(v)))
Kojto	90:cb3d968589d8	522	/@}/
Kojto	90:cb3d968589d8	523
Kojto	90:cb3d968589d8	524	/*!
Kojto	90:cb3d968589d8	525	* @name Register SIM_SOPT2, field FBSL[9:8] (RW)
Kojto	90:cb3d968589d8	526	*
Kojto	90:cb3d968589d8	527	* If flash security is enabled, then this field affects what CPU operations can
Kojto	90:cb3d968589d8	528	* access off-chip via the FlexBus interface. This field has no effect if flash
Kojto	90:cb3d968589d8	529	* security is not enabled.
Kojto	90:cb3d968589d8	530	*
Kojto	90:cb3d968589d8	531	* Values:
Kojto	90:cb3d968589d8	532	* - 00 - All off-chip accesses (instruction and data) via the FlexBus are
Kojto	90:cb3d968589d8	533	* disallowed.
Kojto	90:cb3d968589d8	534	* - 01 - All off-chip accesses (instruction and data) via the FlexBus are
Kojto	90:cb3d968589d8	535	* disallowed.
Kojto	90:cb3d968589d8	536	* - 10 - Off-chip instruction accesses are disallowed. Data accesses are
Kojto	90:cb3d968589d8	537	* allowed.
Kojto	90:cb3d968589d8	538	* - 11 - Off-chip instruction accesses and data accesses are allowed.
Kojto	90:cb3d968589d8	539	*/
Kojto	90:cb3d968589d8	540	/@{/
Kojto	90:cb3d968589d8	541	#define BP_SIM_SOPT2_FBSL (8U) /!< Bit position for SIM_SOPT2_FBSL. /
Kojto	90:cb3d968589d8	542	#define BM_SIM_SOPT2_FBSL (0x00000300U) /!< Bit mask for SIM_SOPT2_FBSL. /
Kojto	90:cb3d968589d8	543	#define BS_SIM_SOPT2_FBSL (2U) /!< Bit field size in bits for SIM_SOPT2_FBSL. /
Kojto	90:cb3d968589d8	544
Kojto	90:cb3d968589d8	545	/! @brief Read current value of the SIM_SOPT2_FBSL field. /
Kojto	90:cb3d968589d8	546	#define BR_SIM_SOPT2_FBSL(x) (HW_SIM_SOPT2(x).B.FBSL)
Kojto	90:cb3d968589d8	547
Kojto	90:cb3d968589d8	548	/! @brief Format value for bitfield SIM_SOPT2_FBSL. /
Kojto	90:cb3d968589d8	549	#define BF_SIM_SOPT2_FBSL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_FBSL) & BM_SIM_SOPT2_FBSL)
Kojto	90:cb3d968589d8	550
Kojto	90:cb3d968589d8	551	/! @brief Set the FBSL field to a new value. /
Kojto	90:cb3d968589d8	552	#define BW_SIM_SOPT2_FBSL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_FBSL) \| BF_SIM_SOPT2_FBSL(v)))
Kojto	90:cb3d968589d8	553	/@}/
Kojto	90:cb3d968589d8	554
Kojto	90:cb3d968589d8	555	/*!
Kojto	90:cb3d968589d8	556	* @name Register SIM_SOPT2, field PTD7PAD[11] (RW)
Kojto	90:cb3d968589d8	557	*
Kojto	90:cb3d968589d8	558	* Controls the output drive strength of the PTD7 pin by selecting either one or
Kojto	90:cb3d968589d8	559	* two pads to drive it.
Kojto	90:cb3d968589d8	560	*
Kojto	90:cb3d968589d8	561	* Values:
Kojto	90:cb3d968589d8	562	* - 0 - Single-pad drive strength for PTD7.
Kojto	90:cb3d968589d8	563	* - 1 - Double pad drive strength for PTD7.
Kojto	90:cb3d968589d8	564	*/
Kojto	90:cb3d968589d8	565	/@{/
Kojto	90:cb3d968589d8	566	#define BP_SIM_SOPT2_PTD7PAD (11U) /!< Bit position for SIM_SOPT2_PTD7PAD. /
Kojto	90:cb3d968589d8	567	#define BM_SIM_SOPT2_PTD7PAD (0x00000800U) /!< Bit mask for SIM_SOPT2_PTD7PAD. /
Kojto	90:cb3d968589d8	568	#define BS_SIM_SOPT2_PTD7PAD (1U) /!< Bit field size in bits for SIM_SOPT2_PTD7PAD. /
Kojto	90:cb3d968589d8	569
Kojto	90:cb3d968589d8	570	/! @brief Read current value of the SIM_SOPT2_PTD7PAD field. /
Kojto	90:cb3d968589d8	571	#define BR_SIM_SOPT2_PTD7PAD(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_PTD7PAD))
Kojto	90:cb3d968589d8	572
Kojto	90:cb3d968589d8	573	/! @brief Format value for bitfield SIM_SOPT2_PTD7PAD. /
Kojto	90:cb3d968589d8	574	#define BF_SIM_SOPT2_PTD7PAD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_PTD7PAD) & BM_SIM_SOPT2_PTD7PAD)
Kojto	90:cb3d968589d8	575
Kojto	90:cb3d968589d8	576	/! @brief Set the PTD7PAD field to a new value. /
Kojto	90:cb3d968589d8	577	#define BW_SIM_SOPT2_PTD7PAD(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_PTD7PAD) = (v))
Kojto	90:cb3d968589d8	578	/@}/
Kojto	90:cb3d968589d8	579
Kojto	90:cb3d968589d8	580	/*!
Kojto	90:cb3d968589d8	581	* @name Register SIM_SOPT2, field TRACECLKSEL[12] (RW)
Kojto	90:cb3d968589d8	582	*
Kojto	90:cb3d968589d8	583	* Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace
Kojto	90:cb3d968589d8	584	* clock source.
Kojto	90:cb3d968589d8	585	*
Kojto	90:cb3d968589d8	586	* Values:
Kojto	90:cb3d968589d8	587	* - 0 - MCGOUTCLK
Kojto	90:cb3d968589d8	588	* - 1 - Core/system clock
Kojto	90:cb3d968589d8	589	*/
Kojto	90:cb3d968589d8	590	/@{/
Kojto	90:cb3d968589d8	591	#define BP_SIM_SOPT2_TRACECLKSEL (12U) /!< Bit position for SIM_SOPT2_TRACECLKSEL. /
Kojto	90:cb3d968589d8	592	#define BM_SIM_SOPT2_TRACECLKSEL (0x00001000U) /!< Bit mask for SIM_SOPT2_TRACECLKSEL. /
Kojto	90:cb3d968589d8	593	#define BS_SIM_SOPT2_TRACECLKSEL (1U) /!< Bit field size in bits for SIM_SOPT2_TRACECLKSEL. /
Kojto	90:cb3d968589d8	594
Kojto	90:cb3d968589d8	595	/! @brief Read current value of the SIM_SOPT2_TRACECLKSEL field. /
Kojto	90:cb3d968589d8	596	#define BR_SIM_SOPT2_TRACECLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_TRACECLKSEL))
Kojto	90:cb3d968589d8	597
Kojto	90:cb3d968589d8	598	/! @brief Format value for bitfield SIM_SOPT2_TRACECLKSEL. /
Kojto	90:cb3d968589d8	599	#define BF_SIM_SOPT2_TRACECLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_TRACECLKSEL) & BM_SIM_SOPT2_TRACECLKSEL)
Kojto	90:cb3d968589d8	600
Kojto	90:cb3d968589d8	601	/! @brief Set the TRACECLKSEL field to a new value. /
Kojto	90:cb3d968589d8	602	#define BW_SIM_SOPT2_TRACECLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_TRACECLKSEL) = (v))
Kojto	90:cb3d968589d8	603	/@}/
Kojto	90:cb3d968589d8	604
Kojto	90:cb3d968589d8	605	/*!
Kojto	90:cb3d968589d8	606	* @name Register SIM_SOPT2, field PLLFLLSEL[17:16] (RW)
Kojto	90:cb3d968589d8	607	*
Kojto	90:cb3d968589d8	608	* Selects the high frequency clock for various peripheral clocking options.
Kojto	90:cb3d968589d8	609	*
Kojto	90:cb3d968589d8	610	* Values:
Kojto	90:cb3d968589d8	611	* - 00 - MCGFLLCLK clock
Kojto	90:cb3d968589d8	612	* - 01 - MCGPLLCLK clock
Kojto	90:cb3d968589d8	613	* - 10 - Reserved
Kojto	90:cb3d968589d8	614	* - 11 - IRC48 MHz clock
Kojto	90:cb3d968589d8	615	*/
Kojto	90:cb3d968589d8	616	/@{/
Kojto	90:cb3d968589d8	617	#define BP_SIM_SOPT2_PLLFLLSEL (16U) /!< Bit position for SIM_SOPT2_PLLFLLSEL. /
Kojto	90:cb3d968589d8	618	#define BM_SIM_SOPT2_PLLFLLSEL (0x00030000U) /!< Bit mask for SIM_SOPT2_PLLFLLSEL. /
Kojto	90:cb3d968589d8	619	#define BS_SIM_SOPT2_PLLFLLSEL (2U) /!< Bit field size in bits for SIM_SOPT2_PLLFLLSEL. /
Kojto	90:cb3d968589d8	620
Kojto	90:cb3d968589d8	621	/! @brief Read current value of the SIM_SOPT2_PLLFLLSEL field. /
Kojto	90:cb3d968589d8	622	#define BR_SIM_SOPT2_PLLFLLSEL(x) (HW_SIM_SOPT2(x).B.PLLFLLSEL)
Kojto	90:cb3d968589d8	623
Kojto	90:cb3d968589d8	624	/! @brief Format value for bitfield SIM_SOPT2_PLLFLLSEL. /
Kojto	90:cb3d968589d8	625	#define BF_SIM_SOPT2_PLLFLLSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_PLLFLLSEL) & BM_SIM_SOPT2_PLLFLLSEL)
Kojto	90:cb3d968589d8	626
Kojto	90:cb3d968589d8	627	/! @brief Set the PLLFLLSEL field to a new value. /
Kojto	90:cb3d968589d8	628	#define BW_SIM_SOPT2_PLLFLLSEL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_PLLFLLSEL) \| BF_SIM_SOPT2_PLLFLLSEL(v)))
Kojto	90:cb3d968589d8	629	/@}/
Kojto	90:cb3d968589d8	630
Kojto	90:cb3d968589d8	631	/*!
Kojto	90:cb3d968589d8	632	* @name Register SIM_SOPT2, field USBSRC[18] (RW)
Kojto	90:cb3d968589d8	633	*
Kojto	90:cb3d968589d8	634	* Selects the clock source for the USB 48 MHz clock.
Kojto	90:cb3d968589d8	635	*
Kojto	90:cb3d968589d8	636	* Values:
Kojto	90:cb3d968589d8	637	* - 0 - External bypass clock (USB_CLKIN).
Kojto	90:cb3d968589d8	638	* - 1 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
Kojto	90:cb3d968589d8	639	* SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by
Kojto	90:cb3d968589d8	640	* SIM_CLKDIV2[USBFRAC, USBDIV].
Kojto	90:cb3d968589d8	641	*/
Kojto	90:cb3d968589d8	642	/@{/
Kojto	90:cb3d968589d8	643	#define BP_SIM_SOPT2_USBSRC (18U) /!< Bit position for SIM_SOPT2_USBSRC. /
Kojto	90:cb3d968589d8	644	#define BM_SIM_SOPT2_USBSRC (0x00040000U) /!< Bit mask for SIM_SOPT2_USBSRC. /
Kojto	90:cb3d968589d8	645	#define BS_SIM_SOPT2_USBSRC (1U) /!< Bit field size in bits for SIM_SOPT2_USBSRC. /
Kojto	90:cb3d968589d8	646
Kojto	90:cb3d968589d8	647	/! @brief Read current value of the SIM_SOPT2_USBSRC field. /
Kojto	90:cb3d968589d8	648	#define BR_SIM_SOPT2_USBSRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_USBSRC))
Kojto	90:cb3d968589d8	649
Kojto	90:cb3d968589d8	650	/! @brief Format value for bitfield SIM_SOPT2_USBSRC. /
Kojto	90:cb3d968589d8	651	#define BF_SIM_SOPT2_USBSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_USBSRC) & BM_SIM_SOPT2_USBSRC)
Kojto	90:cb3d968589d8	652
Kojto	90:cb3d968589d8	653	/! @brief Set the USBSRC field to a new value. /
Kojto	90:cb3d968589d8	654	#define BW_SIM_SOPT2_USBSRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_USBSRC) = (v))
Kojto	90:cb3d968589d8	655	/@}/
Kojto	90:cb3d968589d8	656
Kojto	90:cb3d968589d8	657	/*!
Kojto	90:cb3d968589d8	658	* @name Register SIM_SOPT2, field RMIISRC[19] (RW)
Kojto	90:cb3d968589d8	659	*
Kojto	90:cb3d968589d8	660	* Selects the clock source for the Ethernet RMII interface
Kojto	90:cb3d968589d8	661	*
Kojto	90:cb3d968589d8	662	* Values:
Kojto	90:cb3d968589d8	663	* - 0 - EXTAL clock
Kojto	90:cb3d968589d8	664	* - 1 - External bypass clock (ENET_1588_CLKIN).
Kojto	90:cb3d968589d8	665	*/
Kojto	90:cb3d968589d8	666	/@{/
Kojto	90:cb3d968589d8	667	#define BP_SIM_SOPT2_RMIISRC (19U) /!< Bit position for SIM_SOPT2_RMIISRC. /
Kojto	90:cb3d968589d8	668	#define BM_SIM_SOPT2_RMIISRC (0x00080000U) /!< Bit mask for SIM_SOPT2_RMIISRC. /
Kojto	90:cb3d968589d8	669	#define BS_SIM_SOPT2_RMIISRC (1U) /!< Bit field size in bits for SIM_SOPT2_RMIISRC. /
Kojto	90:cb3d968589d8	670
Kojto	90:cb3d968589d8	671	/! @brief Read current value of the SIM_SOPT2_RMIISRC field. /
Kojto	90:cb3d968589d8	672	#define BR_SIM_SOPT2_RMIISRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RMIISRC))
Kojto	90:cb3d968589d8	673
Kojto	90:cb3d968589d8	674	/! @brief Format value for bitfield SIM_SOPT2_RMIISRC. /
Kojto	90:cb3d968589d8	675	#define BF_SIM_SOPT2_RMIISRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_RMIISRC) & BM_SIM_SOPT2_RMIISRC)
Kojto	90:cb3d968589d8	676
Kojto	90:cb3d968589d8	677	/! @brief Set the RMIISRC field to a new value. /
Kojto	90:cb3d968589d8	678	#define BW_SIM_SOPT2_RMIISRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RMIISRC) = (v))
Kojto	90:cb3d968589d8	679	/@}/
Kojto	90:cb3d968589d8	680
Kojto	90:cb3d968589d8	681	/*!
Kojto	90:cb3d968589d8	682	* @name Register SIM_SOPT2, field TIMESRC[21:20] (RW)
Kojto	90:cb3d968589d8	683	*
Kojto	90:cb3d968589d8	684	* Selects the clock source for the Ethernet timestamp clock.
Kojto	90:cb3d968589d8	685	*
Kojto	90:cb3d968589d8	686	* Values:
Kojto	90:cb3d968589d8	687	* - 00 - Core/system clock.
Kojto	90:cb3d968589d8	688	* - 01 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
Kojto	90:cb3d968589d8	689	* SOPT2[PLLFLLSEL].
Kojto	90:cb3d968589d8	690	* - 10 - OSCERCLK clock
Kojto	90:cb3d968589d8	691	* - 11 - External bypass clock (ENET_1588_CLKIN).
Kojto	90:cb3d968589d8	692	*/
Kojto	90:cb3d968589d8	693	/@{/
Kojto	90:cb3d968589d8	694	#define BP_SIM_SOPT2_TIMESRC (20U) /!< Bit position for SIM_SOPT2_TIMESRC. /
Kojto	90:cb3d968589d8	695	#define BM_SIM_SOPT2_TIMESRC (0x00300000U) /!< Bit mask for SIM_SOPT2_TIMESRC. /
Kojto	90:cb3d968589d8	696	#define BS_SIM_SOPT2_TIMESRC (2U) /!< Bit field size in bits for SIM_SOPT2_TIMESRC. /
Kojto	90:cb3d968589d8	697
Kojto	90:cb3d968589d8	698	/! @brief Read current value of the SIM_SOPT2_TIMESRC field. /
Kojto	90:cb3d968589d8	699	#define BR_SIM_SOPT2_TIMESRC(x) (HW_SIM_SOPT2(x).B.TIMESRC)
Kojto	90:cb3d968589d8	700
Kojto	90:cb3d968589d8	701	/! @brief Format value for bitfield SIM_SOPT2_TIMESRC. /
Kojto	90:cb3d968589d8	702	#define BF_SIM_SOPT2_TIMESRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_TIMESRC) & BM_SIM_SOPT2_TIMESRC)
Kojto	90:cb3d968589d8	703
Kojto	90:cb3d968589d8	704	/! @brief Set the TIMESRC field to a new value. /
Kojto	90:cb3d968589d8	705	#define BW_SIM_SOPT2_TIMESRC(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_TIMESRC) \| BF_SIM_SOPT2_TIMESRC(v)))
Kojto	90:cb3d968589d8	706	/@}/
Kojto	90:cb3d968589d8	707
Kojto	90:cb3d968589d8	708	/*!
Kojto	90:cb3d968589d8	709	* @name Register SIM_SOPT2, field SDHCSRC[29:28] (RW)
Kojto	90:cb3d968589d8	710	*
Kojto	90:cb3d968589d8	711	* Selects the clock source for the SDHC clock .
Kojto	90:cb3d968589d8	712	*
Kojto	90:cb3d968589d8	713	* Values:
Kojto	90:cb3d968589d8	714	* - 00 - Core/system clock.
Kojto	90:cb3d968589d8	715	* - 01 - MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by
Kojto	90:cb3d968589d8	716	* SOPT2[PLLFLLSEL].
Kojto	90:cb3d968589d8	717	* - 10 - OSCERCLK clock
Kojto	90:cb3d968589d8	718	* - 11 - External bypass clock (SDHC0_CLKIN)
Kojto	90:cb3d968589d8	719	*/
Kojto	90:cb3d968589d8	720	/@{/
Kojto	90:cb3d968589d8	721	#define BP_SIM_SOPT2_SDHCSRC (28U) /!< Bit position for SIM_SOPT2_SDHCSRC. /
Kojto	90:cb3d968589d8	722	#define BM_SIM_SOPT2_SDHCSRC (0x30000000U) /!< Bit mask for SIM_SOPT2_SDHCSRC. /
Kojto	90:cb3d968589d8	723	#define BS_SIM_SOPT2_SDHCSRC (2U) /!< Bit field size in bits for SIM_SOPT2_SDHCSRC. /
Kojto	90:cb3d968589d8	724
Kojto	90:cb3d968589d8	725	/! @brief Read current value of the SIM_SOPT2_SDHCSRC field. /
Kojto	90:cb3d968589d8	726	#define BR_SIM_SOPT2_SDHCSRC(x) (HW_SIM_SOPT2(x).B.SDHCSRC)
Kojto	90:cb3d968589d8	727
Kojto	90:cb3d968589d8	728	/! @brief Format value for bitfield SIM_SOPT2_SDHCSRC. /
Kojto	90:cb3d968589d8	729	#define BF_SIM_SOPT2_SDHCSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_SDHCSRC) & BM_SIM_SOPT2_SDHCSRC)
Kojto	90:cb3d968589d8	730
Kojto	90:cb3d968589d8	731	/! @brief Set the SDHCSRC field to a new value. /
Kojto	90:cb3d968589d8	732	#define BW_SIM_SOPT2_SDHCSRC(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_SDHCSRC) \| BF_SIM_SOPT2_SDHCSRC(v)))
Kojto	90:cb3d968589d8	733	/@}/
Kojto	90:cb3d968589d8	734
Kojto	90:cb3d968589d8	735	/*******************************************************************************
Kojto	90:cb3d968589d8	736	* HW_SIM_SOPT4 - System Options Register 4
Kojto	90:cb3d968589d8	737	******************************************************************************/
Kojto	90:cb3d968589d8	738
Kojto	90:cb3d968589d8	739	/*!
Kojto	90:cb3d968589d8	740	* @brief HW_SIM_SOPT4 - System Options Register 4 (RW)
Kojto	90:cb3d968589d8	741	*
Kojto	90:cb3d968589d8	742	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	743	*/
Kojto	90:cb3d968589d8	744	typedef union _hw_sim_sopt4
Kojto	90:cb3d968589d8	745	{
Kojto	90:cb3d968589d8	746	uint32_t U;
Kojto	90:cb3d968589d8	747	struct _hw_sim_sopt4_bitfields
Kojto	90:cb3d968589d8	748	{
Kojto	90:cb3d968589d8	749	uint32_t FTM0FLT0 : 1; /!< [0] FTM0 Fault 0 Select /
Kojto	90:cb3d968589d8	750	uint32_t FTM0FLT1 : 1; /!< [1] FTM0 Fault 1 Select /
Kojto	90:cb3d968589d8	751	uint32_t FTM0FLT2 : 1; /!< [2] FTM0 Fault 2 Select /
Kojto	90:cb3d968589d8	752	uint32_t RESERVED0 : 1; /!< [3] /
Kojto	90:cb3d968589d8	753	uint32_t FTM1FLT0 : 1; /!< [4] FTM1 Fault 0 Select /
Kojto	90:cb3d968589d8	754	uint32_t RESERVED1 : 3; /!< [7:5] /
Kojto	90:cb3d968589d8	755	uint32_t FTM2FLT0 : 1; /!< [8] FTM2 Fault 0 Select /
Kojto	90:cb3d968589d8	756	uint32_t RESERVED2 : 3; /!< [11:9] /
Kojto	90:cb3d968589d8	757	uint32_t FTM3FLT0 : 1; /!< [12] FTM3 Fault 0 Select /
Kojto	90:cb3d968589d8	758	uint32_t RESERVED3 : 5; /!< [17:13] /
Kojto	90:cb3d968589d8	759	uint32_t FTM1CH0SRC : 2; /*!< [19:18] FTM1 channel 0 input capture
Kojto	90:cb3d968589d8	760	* source select */
Kojto	90:cb3d968589d8	761	uint32_t FTM2CH0SRC : 2; /*!< [21:20] FTM2 channel 0 input capture
Kojto	90:cb3d968589d8	762	* source select */
Kojto	90:cb3d968589d8	763	uint32_t RESERVED4 : 2; /!< [23:22] /
Kojto	90:cb3d968589d8	764	uint32_t FTM0CLKSEL : 1; /*!< [24] FlexTimer 0 External Clock Pin
Kojto	90:cb3d968589d8	765	* Select */
Kojto	90:cb3d968589d8	766	uint32_t FTM1CLKSEL : 1; /!< [25] FTM1 External Clock Pin Select /
Kojto	90:cb3d968589d8	767	uint32_t FTM2CLKSEL : 1; /*!< [26] FlexTimer 2 External Clock Pin
Kojto	90:cb3d968589d8	768	* Select */
Kojto	90:cb3d968589d8	769	uint32_t FTM3CLKSEL : 1; /*!< [27] FlexTimer 3 External Clock Pin
Kojto	90:cb3d968589d8	770	* Select */
Kojto	90:cb3d968589d8	771	uint32_t FTM0TRG0SRC : 1; /*!< [28] FlexTimer 0 Hardware Trigger 0
Kojto	90:cb3d968589d8	772	* Source Select */
Kojto	90:cb3d968589d8	773	uint32_t FTM0TRG1SRC : 1; /*!< [29] FlexTimer 0 Hardware Trigger 1
Kojto	90:cb3d968589d8	774	* Source Select */
Kojto	90:cb3d968589d8	775	uint32_t FTM3TRG0SRC : 1; /*!< [30] FlexTimer 3 Hardware Trigger 0
Kojto	90:cb3d968589d8	776	* Source Select */
Kojto	90:cb3d968589d8	777	uint32_t FTM3TRG1SRC : 1; /*!< [31] FlexTimer 3 Hardware Trigger 1
Kojto	90:cb3d968589d8	778	* Source Select */
Kojto	90:cb3d968589d8	779	} B;
Kojto	90:cb3d968589d8	780	} hw_sim_sopt4_t;
Kojto	90:cb3d968589d8	781
Kojto	90:cb3d968589d8	782	/*!
Kojto	90:cb3d968589d8	783	* @name Constants and macros for entire SIM_SOPT4 register
Kojto	90:cb3d968589d8	784	*/
Kojto	90:cb3d968589d8	785	/@{/
Kojto	90:cb3d968589d8	786	#define HW_SIM_SOPT4_ADDR(x) ((x) + 0x100CU)
Kojto	90:cb3d968589d8	787
Kojto	90:cb3d968589d8	788	#define HW_SIM_SOPT4(x) ((__IO hw_sim_sopt4_t ) HW_SIM_SOPT4_ADDR(x))
Kojto	90:cb3d968589d8	789	#define HW_SIM_SOPT4_RD(x) (HW_SIM_SOPT4(x).U)
Kojto	90:cb3d968589d8	790	#define HW_SIM_SOPT4_WR(x, v) (HW_SIM_SOPT4(x).U = (v))
Kojto	90:cb3d968589d8	791	#define HW_SIM_SOPT4_SET(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) \| (v)))
Kojto	90:cb3d968589d8	792	#define HW_SIM_SOPT4_CLR(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	793	#define HW_SIM_SOPT4_TOG(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	794	/@}/
Kojto	90:cb3d968589d8	795
Kojto	90:cb3d968589d8	796	/*
Kojto	90:cb3d968589d8	797	* Constants & macros for individual SIM_SOPT4 bitfields
Kojto	90:cb3d968589d8	798	*/
Kojto	90:cb3d968589d8	799
Kojto	90:cb3d968589d8	800	/*!
Kojto	90:cb3d968589d8	801	* @name Register SIM_SOPT4, field FTM0FLT0[0] (RW)
Kojto	90:cb3d968589d8	802	*
Kojto	90:cb3d968589d8	803	* Selects the source of FTM0 fault 0. The pin source for fault 0 must be
Kojto	90:cb3d968589d8	804	* configured for the FTM module fault function through the appropriate pin control
Kojto	90:cb3d968589d8	805	* register in the port control module.
Kojto	90:cb3d968589d8	806	*
Kojto	90:cb3d968589d8	807	* Values:
Kojto	90:cb3d968589d8	808	* - 0 - FTM0_FLT0 pin
Kojto	90:cb3d968589d8	809	* - 1 - CMP0 out
Kojto	90:cb3d968589d8	810	*/
Kojto	90:cb3d968589d8	811	/@{/
Kojto	90:cb3d968589d8	812	#define BP_SIM_SOPT4_FTM0FLT0 (0U) /!< Bit position for SIM_SOPT4_FTM0FLT0. /
Kojto	90:cb3d968589d8	813	#define BM_SIM_SOPT4_FTM0FLT0 (0x00000001U) /!< Bit mask for SIM_SOPT4_FTM0FLT0. /
Kojto	90:cb3d968589d8	814	#define BS_SIM_SOPT4_FTM0FLT0 (1U) /!< Bit field size in bits for SIM_SOPT4_FTM0FLT0. /
Kojto	90:cb3d968589d8	815
Kojto	90:cb3d968589d8	816	/! @brief Read current value of the SIM_SOPT4_FTM0FLT0 field. /
Kojto	90:cb3d968589d8	817	#define BR_SIM_SOPT4_FTM0FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT0))
Kojto	90:cb3d968589d8	818
Kojto	90:cb3d968589d8	819	/! @brief Format value for bitfield SIM_SOPT4_FTM0FLT0. /
Kojto	90:cb3d968589d8	820	#define BF_SIM_SOPT4_FTM0FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT0) & BM_SIM_SOPT4_FTM0FLT0)
Kojto	90:cb3d968589d8	821
Kojto	90:cb3d968589d8	822	/! @brief Set the FTM0FLT0 field to a new value. /
Kojto	90:cb3d968589d8	823	#define BW_SIM_SOPT4_FTM0FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT0) = (v))
Kojto	90:cb3d968589d8	824	/@}/
Kojto	90:cb3d968589d8	825
Kojto	90:cb3d968589d8	826	/*!
Kojto	90:cb3d968589d8	827	* @name Register SIM_SOPT4, field FTM0FLT1[1] (RW)
Kojto	90:cb3d968589d8	828	*
Kojto	90:cb3d968589d8	829	* Selects the source of FTM0 fault 1. The pin source for fault 1 must be
Kojto	90:cb3d968589d8	830	* configured for the FTM module fault function through the appropriate pin control
Kojto	90:cb3d968589d8	831	* register in the port control module.
Kojto	90:cb3d968589d8	832	*
Kojto	90:cb3d968589d8	833	* Values:
Kojto	90:cb3d968589d8	834	* - 0 - FTM0_FLT1 pin
Kojto	90:cb3d968589d8	835	* - 1 - CMP1 out
Kojto	90:cb3d968589d8	836	*/
Kojto	90:cb3d968589d8	837	/@{/
Kojto	90:cb3d968589d8	838	#define BP_SIM_SOPT4_FTM0FLT1 (1U) /!< Bit position for SIM_SOPT4_FTM0FLT1. /
Kojto	90:cb3d968589d8	839	#define BM_SIM_SOPT4_FTM0FLT1 (0x00000002U) /!< Bit mask for SIM_SOPT4_FTM0FLT1. /
Kojto	90:cb3d968589d8	840	#define BS_SIM_SOPT4_FTM0FLT1 (1U) /!< Bit field size in bits for SIM_SOPT4_FTM0FLT1. /
Kojto	90:cb3d968589d8	841
Kojto	90:cb3d968589d8	842	/! @brief Read current value of the SIM_SOPT4_FTM0FLT1 field. /
Kojto	90:cb3d968589d8	843	#define BR_SIM_SOPT4_FTM0FLT1(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT1))
Kojto	90:cb3d968589d8	844
Kojto	90:cb3d968589d8	845	/! @brief Format value for bitfield SIM_SOPT4_FTM0FLT1. /
Kojto	90:cb3d968589d8	846	#define BF_SIM_SOPT4_FTM0FLT1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT1) & BM_SIM_SOPT4_FTM0FLT1)
Kojto	90:cb3d968589d8	847
Kojto	90:cb3d968589d8	848	/! @brief Set the FTM0FLT1 field to a new value. /
Kojto	90:cb3d968589d8	849	#define BW_SIM_SOPT4_FTM0FLT1(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT1) = (v))
Kojto	90:cb3d968589d8	850	/@}/
Kojto	90:cb3d968589d8	851
Kojto	90:cb3d968589d8	852	/*!
Kojto	90:cb3d968589d8	853	* @name Register SIM_SOPT4, field FTM0FLT2[2] (RW)
Kojto	90:cb3d968589d8	854	*
Kojto	90:cb3d968589d8	855	* Selects the source of FTM0 fault 2. The pin source for fault 2 must be
Kojto	90:cb3d968589d8	856	* configured for the FTM module fault function through the appropriate pin control
Kojto	90:cb3d968589d8	857	* register in the port control module.
Kojto	90:cb3d968589d8	858	*
Kojto	90:cb3d968589d8	859	* Values:
Kojto	90:cb3d968589d8	860	* - 0 - FTM0_FLT2 pin
Kojto	90:cb3d968589d8	861	* - 1 - CMP2 out
Kojto	90:cb3d968589d8	862	*/
Kojto	90:cb3d968589d8	863	/@{/
Kojto	90:cb3d968589d8	864	#define BP_SIM_SOPT4_FTM0FLT2 (2U) /!< Bit position for SIM_SOPT4_FTM0FLT2. /
Kojto	90:cb3d968589d8	865	#define BM_SIM_SOPT4_FTM0FLT2 (0x00000004U) /!< Bit mask for SIM_SOPT4_FTM0FLT2. /
Kojto	90:cb3d968589d8	866	#define BS_SIM_SOPT4_FTM0FLT2 (1U) /!< Bit field size in bits for SIM_SOPT4_FTM0FLT2. /
Kojto	90:cb3d968589d8	867
Kojto	90:cb3d968589d8	868	/! @brief Read current value of the SIM_SOPT4_FTM0FLT2 field. /
Kojto	90:cb3d968589d8	869	#define BR_SIM_SOPT4_FTM0FLT2(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT2))
Kojto	90:cb3d968589d8	870
Kojto	90:cb3d968589d8	871	/! @brief Format value for bitfield SIM_SOPT4_FTM0FLT2. /
Kojto	90:cb3d968589d8	872	#define BF_SIM_SOPT4_FTM0FLT2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT2) & BM_SIM_SOPT4_FTM0FLT2)
Kojto	90:cb3d968589d8	873
Kojto	90:cb3d968589d8	874	/! @brief Set the FTM0FLT2 field to a new value. /
Kojto	90:cb3d968589d8	875	#define BW_SIM_SOPT4_FTM0FLT2(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT2) = (v))
Kojto	90:cb3d968589d8	876	/@}/
Kojto	90:cb3d968589d8	877
Kojto	90:cb3d968589d8	878	/*!
Kojto	90:cb3d968589d8	879	* @name Register SIM_SOPT4, field FTM1FLT0[4] (RW)
Kojto	90:cb3d968589d8	880	*
Kojto	90:cb3d968589d8	881	* Selects the source of FTM1 fault 0. The pin source for fault 0 must be
Kojto	90:cb3d968589d8	882	* configured for the FTM module fault function through the appropriate pin control
Kojto	90:cb3d968589d8	883	* register in the port control module.
Kojto	90:cb3d968589d8	884	*
Kojto	90:cb3d968589d8	885	* Values:
Kojto	90:cb3d968589d8	886	* - 0 - FTM1_FLT0 pin
Kojto	90:cb3d968589d8	887	* - 1 - CMP0 out
Kojto	90:cb3d968589d8	888	*/
Kojto	90:cb3d968589d8	889	/@{/
Kojto	90:cb3d968589d8	890	#define BP_SIM_SOPT4_FTM1FLT0 (4U) /!< Bit position for SIM_SOPT4_FTM1FLT0. /
Kojto	90:cb3d968589d8	891	#define BM_SIM_SOPT4_FTM1FLT0 (0x00000010U) /!< Bit mask for SIM_SOPT4_FTM1FLT0. /
Kojto	90:cb3d968589d8	892	#define BS_SIM_SOPT4_FTM1FLT0 (1U) /!< Bit field size in bits for SIM_SOPT4_FTM1FLT0. /
Kojto	90:cb3d968589d8	893
Kojto	90:cb3d968589d8	894	/! @brief Read current value of the SIM_SOPT4_FTM1FLT0 field. /
Kojto	90:cb3d968589d8	895	#define BR_SIM_SOPT4_FTM1FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1FLT0))
Kojto	90:cb3d968589d8	896
Kojto	90:cb3d968589d8	897	/! @brief Format value for bitfield SIM_SOPT4_FTM1FLT0. /
Kojto	90:cb3d968589d8	898	#define BF_SIM_SOPT4_FTM1FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1FLT0) & BM_SIM_SOPT4_FTM1FLT0)
Kojto	90:cb3d968589d8	899
Kojto	90:cb3d968589d8	900	/! @brief Set the FTM1FLT0 field to a new value. /
Kojto	90:cb3d968589d8	901	#define BW_SIM_SOPT4_FTM1FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1FLT0) = (v))
Kojto	90:cb3d968589d8	902	/@}/
Kojto	90:cb3d968589d8	903
Kojto	90:cb3d968589d8	904	/*!
Kojto	90:cb3d968589d8	905	* @name Register SIM_SOPT4, field FTM2FLT0[8] (RW)
Kojto	90:cb3d968589d8	906	*
Kojto	90:cb3d968589d8	907	* Selects the source of FTM2 fault 0. The pin source for fault 0 must be
Kojto	90:cb3d968589d8	908	* configured for the FTM module fault function through the appropriate PORTx pin
Kojto	90:cb3d968589d8	909	* control register.
Kojto	90:cb3d968589d8	910	*
Kojto	90:cb3d968589d8	911	* Values:
Kojto	90:cb3d968589d8	912	* - 0 - FTM2_FLT0 pin
Kojto	90:cb3d968589d8	913	* - 1 - CMP0 out
Kojto	90:cb3d968589d8	914	*/
Kojto	90:cb3d968589d8	915	/@{/
Kojto	90:cb3d968589d8	916	#define BP_SIM_SOPT4_FTM2FLT0 (8U) /!< Bit position for SIM_SOPT4_FTM2FLT0. /
Kojto	90:cb3d968589d8	917	#define BM_SIM_SOPT4_FTM2FLT0 (0x00000100U) /!< Bit mask for SIM_SOPT4_FTM2FLT0. /
Kojto	90:cb3d968589d8	918	#define BS_SIM_SOPT4_FTM2FLT0 (1U) /!< Bit field size in bits for SIM_SOPT4_FTM2FLT0. /
Kojto	90:cb3d968589d8	919
Kojto	90:cb3d968589d8	920	/! @brief Read current value of the SIM_SOPT4_FTM2FLT0 field. /
Kojto	90:cb3d968589d8	921	#define BR_SIM_SOPT4_FTM2FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2FLT0))
Kojto	90:cb3d968589d8	922
Kojto	90:cb3d968589d8	923	/! @brief Format value for bitfield SIM_SOPT4_FTM2FLT0. /
Kojto	90:cb3d968589d8	924	#define BF_SIM_SOPT4_FTM2FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2FLT0) & BM_SIM_SOPT4_FTM2FLT0)
Kojto	90:cb3d968589d8	925
Kojto	90:cb3d968589d8	926	/! @brief Set the FTM2FLT0 field to a new value. /
Kojto	90:cb3d968589d8	927	#define BW_SIM_SOPT4_FTM2FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2FLT0) = (v))
Kojto	90:cb3d968589d8	928	/@}/
Kojto	90:cb3d968589d8	929
Kojto	90:cb3d968589d8	930	/*!
Kojto	90:cb3d968589d8	931	* @name Register SIM_SOPT4, field FTM3FLT0[12] (RW)
Kojto	90:cb3d968589d8	932	*
Kojto	90:cb3d968589d8	933	* Selects the source of FTM3 fault 0. The pin source for fault 0 must be
Kojto	90:cb3d968589d8	934	* configured for the FTM module fault function through the appropriate PORTx pin
Kojto	90:cb3d968589d8	935	* control register.
Kojto	90:cb3d968589d8	936	*
Kojto	90:cb3d968589d8	937	* Values:
Kojto	90:cb3d968589d8	938	* - 0 - FTM3_FLT0 pin
Kojto	90:cb3d968589d8	939	* - 1 - CMP0 out
Kojto	90:cb3d968589d8	940	*/
Kojto	90:cb3d968589d8	941	/@{/
Kojto	90:cb3d968589d8	942	#define BP_SIM_SOPT4_FTM3FLT0 (12U) /!< Bit position for SIM_SOPT4_FTM3FLT0. /
Kojto	90:cb3d968589d8	943	#define BM_SIM_SOPT4_FTM3FLT0 (0x00001000U) /!< Bit mask for SIM_SOPT4_FTM3FLT0. /
Kojto	90:cb3d968589d8	944	#define BS_SIM_SOPT4_FTM3FLT0 (1U) /!< Bit field size in bits for SIM_SOPT4_FTM3FLT0. /
Kojto	90:cb3d968589d8	945
Kojto	90:cb3d968589d8	946	/! @brief Read current value of the SIM_SOPT4_FTM3FLT0 field. /
Kojto	90:cb3d968589d8	947	#define BR_SIM_SOPT4_FTM3FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3FLT0))
Kojto	90:cb3d968589d8	948
Kojto	90:cb3d968589d8	949	/! @brief Format value for bitfield SIM_SOPT4_FTM3FLT0. /
Kojto	90:cb3d968589d8	950	#define BF_SIM_SOPT4_FTM3FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3FLT0) & BM_SIM_SOPT4_FTM3FLT0)
Kojto	90:cb3d968589d8	951
Kojto	90:cb3d968589d8	952	/! @brief Set the FTM3FLT0 field to a new value. /
Kojto	90:cb3d968589d8	953	#define BW_SIM_SOPT4_FTM3FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3FLT0) = (v))
Kojto	90:cb3d968589d8	954	/@}/
Kojto	90:cb3d968589d8	955
Kojto	90:cb3d968589d8	956	/*!
Kojto	90:cb3d968589d8	957	* @name Register SIM_SOPT4, field FTM1CH0SRC[19:18] (RW)
Kojto	90:cb3d968589d8	958	*
Kojto	90:cb3d968589d8	959	* Selects the source for FTM1 channel 0 input capture. When the FTM is not in
Kojto	90:cb3d968589d8	960	* input capture mode, clear this field.
Kojto	90:cb3d968589d8	961	*
Kojto	90:cb3d968589d8	962	* Values:
Kojto	90:cb3d968589d8	963	* - 00 - FTM1_CH0 signal
Kojto	90:cb3d968589d8	964	* - 01 - CMP0 output
Kojto	90:cb3d968589d8	965	* - 10 - CMP1 output
Kojto	90:cb3d968589d8	966	* - 11 - USB start of frame pulse
Kojto	90:cb3d968589d8	967	*/
Kojto	90:cb3d968589d8	968	/@{/
Kojto	90:cb3d968589d8	969	#define BP_SIM_SOPT4_FTM1CH0SRC (18U) /!< Bit position for SIM_SOPT4_FTM1CH0SRC. /
Kojto	90:cb3d968589d8	970	#define BM_SIM_SOPT4_FTM1CH0SRC (0x000C0000U) /!< Bit mask for SIM_SOPT4_FTM1CH0SRC. /
Kojto	90:cb3d968589d8	971	#define BS_SIM_SOPT4_FTM1CH0SRC (2U) /!< Bit field size in bits for SIM_SOPT4_FTM1CH0SRC. /
Kojto	90:cb3d968589d8	972
Kojto	90:cb3d968589d8	973	/! @brief Read current value of the SIM_SOPT4_FTM1CH0SRC field. /
Kojto	90:cb3d968589d8	974	#define BR_SIM_SOPT4_FTM1CH0SRC(x) (HW_SIM_SOPT4(x).B.FTM1CH0SRC)
Kojto	90:cb3d968589d8	975
Kojto	90:cb3d968589d8	976	/! @brief Format value for bitfield SIM_SOPT4_FTM1CH0SRC. /
Kojto	90:cb3d968589d8	977	#define BF_SIM_SOPT4_FTM1CH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1CH0SRC) & BM_SIM_SOPT4_FTM1CH0SRC)
Kojto	90:cb3d968589d8	978
Kojto	90:cb3d968589d8	979	/! @brief Set the FTM1CH0SRC field to a new value. /
Kojto	90:cb3d968589d8	980	#define BW_SIM_SOPT4_FTM1CH0SRC(x, v) (HW_SIM_SOPT4_WR(x, (HW_SIM_SOPT4_RD(x) & ~BM_SIM_SOPT4_FTM1CH0SRC) \| BF_SIM_SOPT4_FTM1CH0SRC(v)))
Kojto	90:cb3d968589d8	981	/@}/
Kojto	90:cb3d968589d8	982
Kojto	90:cb3d968589d8	983	/*!
Kojto	90:cb3d968589d8	984	* @name Register SIM_SOPT4, field FTM2CH0SRC[21:20] (RW)
Kojto	90:cb3d968589d8	985	*
Kojto	90:cb3d968589d8	986	* Selects the source for FTM2 channel 0 input capture. When the FTM is not in
Kojto	90:cb3d968589d8	987	* input capture mode, clear this field.
Kojto	90:cb3d968589d8	988	*
Kojto	90:cb3d968589d8	989	* Values:
Kojto	90:cb3d968589d8	990	* - 00 - FTM2_CH0 signal
Kojto	90:cb3d968589d8	991	* - 01 - CMP0 output
Kojto	90:cb3d968589d8	992	* - 10 - CMP1 output
Kojto	90:cb3d968589d8	993	* - 11 - Reserved
Kojto	90:cb3d968589d8	994	*/
Kojto	90:cb3d968589d8	995	/@{/
Kojto	90:cb3d968589d8	996	#define BP_SIM_SOPT4_FTM2CH0SRC (20U) /!< Bit position for SIM_SOPT4_FTM2CH0SRC. /
Kojto	90:cb3d968589d8	997	#define BM_SIM_SOPT4_FTM2CH0SRC (0x00300000U) /!< Bit mask for SIM_SOPT4_FTM2CH0SRC. /
Kojto	90:cb3d968589d8	998	#define BS_SIM_SOPT4_FTM2CH0SRC (2U) /!< Bit field size in bits for SIM_SOPT4_FTM2CH0SRC. /
Kojto	90:cb3d968589d8	999
Kojto	90:cb3d968589d8	1000	/! @brief Read current value of the SIM_SOPT4_FTM2CH0SRC field. /
Kojto	90:cb3d968589d8	1001	#define BR_SIM_SOPT4_FTM2CH0SRC(x) (HW_SIM_SOPT4(x).B.FTM2CH0SRC)
Kojto	90:cb3d968589d8	1002
Kojto	90:cb3d968589d8	1003	/! @brief Format value for bitfield SIM_SOPT4_FTM2CH0SRC. /
Kojto	90:cb3d968589d8	1004	#define BF_SIM_SOPT4_FTM2CH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2CH0SRC) & BM_SIM_SOPT4_FTM2CH0SRC)
Kojto	90:cb3d968589d8	1005
Kojto	90:cb3d968589d8	1006	/! @brief Set the FTM2CH0SRC field to a new value. /
Kojto	90:cb3d968589d8	1007	#define BW_SIM_SOPT4_FTM2CH0SRC(x, v) (HW_SIM_SOPT4_WR(x, (HW_SIM_SOPT4_RD(x) & ~BM_SIM_SOPT4_FTM2CH0SRC) \| BF_SIM_SOPT4_FTM2CH0SRC(v)))
Kojto	90:cb3d968589d8	1008	/@}/
Kojto	90:cb3d968589d8	1009
Kojto	90:cb3d968589d8	1010	/*!
Kojto	90:cb3d968589d8	1011	* @name Register SIM_SOPT4, field FTM0CLKSEL[24] (RW)
Kojto	90:cb3d968589d8	1012	*
Kojto	90:cb3d968589d8	1013	* Selects the external pin used to drive the clock to the FTM0 module. The
Kojto	90:cb3d968589d8	1014	* selected pin must also be configured for the FTM external clock function through
Kojto	90:cb3d968589d8	1015	* the appropriate pin control register in the port control module.
Kojto	90:cb3d968589d8	1016	*
Kojto	90:cb3d968589d8	1017	* Values:
Kojto	90:cb3d968589d8	1018	* - 0 - FTM_CLK0 pin
Kojto	90:cb3d968589d8	1019	* - 1 - FTM_CLK1 pin
Kojto	90:cb3d968589d8	1020	*/
Kojto	90:cb3d968589d8	1021	/@{/
Kojto	90:cb3d968589d8	1022	#define BP_SIM_SOPT4_FTM0CLKSEL (24U) /!< Bit position for SIM_SOPT4_FTM0CLKSEL. /
Kojto	90:cb3d968589d8	1023	#define BM_SIM_SOPT4_FTM0CLKSEL (0x01000000U) /!< Bit mask for SIM_SOPT4_FTM0CLKSEL. /
Kojto	90:cb3d968589d8	1024	#define BS_SIM_SOPT4_FTM0CLKSEL (1U) /!< Bit field size in bits for SIM_SOPT4_FTM0CLKSEL. /
Kojto	90:cb3d968589d8	1025
Kojto	90:cb3d968589d8	1026	/! @brief Read current value of the SIM_SOPT4_FTM0CLKSEL field. /
Kojto	90:cb3d968589d8	1027	#define BR_SIM_SOPT4_FTM0CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0CLKSEL))
Kojto	90:cb3d968589d8	1028
Kojto	90:cb3d968589d8	1029	/! @brief Format value for bitfield SIM_SOPT4_FTM0CLKSEL. /
Kojto	90:cb3d968589d8	1030	#define BF_SIM_SOPT4_FTM0CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0CLKSEL) & BM_SIM_SOPT4_FTM0CLKSEL)
Kojto	90:cb3d968589d8	1031
Kojto	90:cb3d968589d8	1032	/! @brief Set the FTM0CLKSEL field to a new value. /
Kojto	90:cb3d968589d8	1033	#define BW_SIM_SOPT4_FTM0CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0CLKSEL) = (v))
Kojto	90:cb3d968589d8	1034	/@}/
Kojto	90:cb3d968589d8	1035
Kojto	90:cb3d968589d8	1036	/*!
Kojto	90:cb3d968589d8	1037	* @name Register SIM_SOPT4, field FTM1CLKSEL[25] (RW)
Kojto	90:cb3d968589d8	1038	*
Kojto	90:cb3d968589d8	1039	* Selects the external pin used to drive the clock to the FTM1 module. The
Kojto	90:cb3d968589d8	1040	* selected pin must also be configured for the FTM external clock function through
Kojto	90:cb3d968589d8	1041	* the appropriate pin control register in the port control module.
Kojto	90:cb3d968589d8	1042	*
Kojto	90:cb3d968589d8	1043	* Values:
Kojto	90:cb3d968589d8	1044	* - 0 - FTM_CLK0 pin
Kojto	90:cb3d968589d8	1045	* - 1 - FTM_CLK1 pin
Kojto	90:cb3d968589d8	1046	*/
Kojto	90:cb3d968589d8	1047	/@{/
Kojto	90:cb3d968589d8	1048	#define BP_SIM_SOPT4_FTM1CLKSEL (25U) /!< Bit position for SIM_SOPT4_FTM1CLKSEL. /
Kojto	90:cb3d968589d8	1049	#define BM_SIM_SOPT4_FTM1CLKSEL (0x02000000U) /!< Bit mask for SIM_SOPT4_FTM1CLKSEL. /
Kojto	90:cb3d968589d8	1050	#define BS_SIM_SOPT4_FTM1CLKSEL (1U) /!< Bit field size in bits for SIM_SOPT4_FTM1CLKSEL. /
Kojto	90:cb3d968589d8	1051
Kojto	90:cb3d968589d8	1052	/! @brief Read current value of the SIM_SOPT4_FTM1CLKSEL field. /
Kojto	90:cb3d968589d8	1053	#define BR_SIM_SOPT4_FTM1CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1CLKSEL))
Kojto	90:cb3d968589d8	1054
Kojto	90:cb3d968589d8	1055	/! @brief Format value for bitfield SIM_SOPT4_FTM1CLKSEL. /
Kojto	90:cb3d968589d8	1056	#define BF_SIM_SOPT4_FTM1CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1CLKSEL) & BM_SIM_SOPT4_FTM1CLKSEL)
Kojto	90:cb3d968589d8	1057
Kojto	90:cb3d968589d8	1058	/! @brief Set the FTM1CLKSEL field to a new value. /
Kojto	90:cb3d968589d8	1059	#define BW_SIM_SOPT4_FTM1CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1CLKSEL) = (v))
Kojto	90:cb3d968589d8	1060	/@}/
Kojto	90:cb3d968589d8	1061
Kojto	90:cb3d968589d8	1062	/*!
Kojto	90:cb3d968589d8	1063	* @name Register SIM_SOPT4, field FTM2CLKSEL[26] (RW)
Kojto	90:cb3d968589d8	1064	*
Kojto	90:cb3d968589d8	1065	* Selects the external pin used to drive the clock to the FTM2 module. The
Kojto	90:cb3d968589d8	1066	* selected pin must also be configured for the FTM2 module external clock function
Kojto	90:cb3d968589d8	1067	* through the appropriate pin control register in the port control module.
Kojto	90:cb3d968589d8	1068	*
Kojto	90:cb3d968589d8	1069	* Values:
Kojto	90:cb3d968589d8	1070	* - 0 - FTM2 external clock driven by FTM_CLK0 pin.
Kojto	90:cb3d968589d8	1071	* - 1 - FTM2 external clock driven by FTM_CLK1 pin.
Kojto	90:cb3d968589d8	1072	*/
Kojto	90:cb3d968589d8	1073	/@{/
Kojto	90:cb3d968589d8	1074	#define BP_SIM_SOPT4_FTM2CLKSEL (26U) /!< Bit position for SIM_SOPT4_FTM2CLKSEL. /
Kojto	90:cb3d968589d8	1075	#define BM_SIM_SOPT4_FTM2CLKSEL (0x04000000U) /!< Bit mask for SIM_SOPT4_FTM2CLKSEL. /
Kojto	90:cb3d968589d8	1076	#define BS_SIM_SOPT4_FTM2CLKSEL (1U) /!< Bit field size in bits for SIM_SOPT4_FTM2CLKSEL. /
Kojto	90:cb3d968589d8	1077
Kojto	90:cb3d968589d8	1078	/! @brief Read current value of the SIM_SOPT4_FTM2CLKSEL field. /
Kojto	90:cb3d968589d8	1079	#define BR_SIM_SOPT4_FTM2CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CLKSEL))
Kojto	90:cb3d968589d8	1080
Kojto	90:cb3d968589d8	1081	/! @brief Format value for bitfield SIM_SOPT4_FTM2CLKSEL. /
Kojto	90:cb3d968589d8	1082	#define BF_SIM_SOPT4_FTM2CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2CLKSEL) & BM_SIM_SOPT4_FTM2CLKSEL)
Kojto	90:cb3d968589d8	1083
Kojto	90:cb3d968589d8	1084	/! @brief Set the FTM2CLKSEL field to a new value. /
Kojto	90:cb3d968589d8	1085	#define BW_SIM_SOPT4_FTM2CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CLKSEL) = (v))
Kojto	90:cb3d968589d8	1086	/@}/
Kojto	90:cb3d968589d8	1087
Kojto	90:cb3d968589d8	1088	/*!
Kojto	90:cb3d968589d8	1089	* @name Register SIM_SOPT4, field FTM3CLKSEL[27] (RW)
Kojto	90:cb3d968589d8	1090	*
Kojto	90:cb3d968589d8	1091	* Selects the external pin used to drive the clock to the FTM3 module. The
Kojto	90:cb3d968589d8	1092	* selected pin must also be configured for the FTM3 module external clock function
Kojto	90:cb3d968589d8	1093	* through the appropriate pin control register in the port control module.
Kojto	90:cb3d968589d8	1094	*
Kojto	90:cb3d968589d8	1095	* Values:
Kojto	90:cb3d968589d8	1096	* - 0 - FTM3 external clock driven by FTM_CLK0 pin.
Kojto	90:cb3d968589d8	1097	* - 1 - FTM3 external clock driven by FTM_CLK1 pin.
Kojto	90:cb3d968589d8	1098	*/
Kojto	90:cb3d968589d8	1099	/@{/
Kojto	90:cb3d968589d8	1100	#define BP_SIM_SOPT4_FTM3CLKSEL (27U) /!< Bit position for SIM_SOPT4_FTM3CLKSEL. /
Kojto	90:cb3d968589d8	1101	#define BM_SIM_SOPT4_FTM3CLKSEL (0x08000000U) /!< Bit mask for SIM_SOPT4_FTM3CLKSEL. /
Kojto	90:cb3d968589d8	1102	#define BS_SIM_SOPT4_FTM3CLKSEL (1U) /!< Bit field size in bits for SIM_SOPT4_FTM3CLKSEL. /
Kojto	90:cb3d968589d8	1103
Kojto	90:cb3d968589d8	1104	/! @brief Read current value of the SIM_SOPT4_FTM3CLKSEL field. /
Kojto	90:cb3d968589d8	1105	#define BR_SIM_SOPT4_FTM3CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3CLKSEL))
Kojto	90:cb3d968589d8	1106
Kojto	90:cb3d968589d8	1107	/! @brief Format value for bitfield SIM_SOPT4_FTM3CLKSEL. /
Kojto	90:cb3d968589d8	1108	#define BF_SIM_SOPT4_FTM3CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3CLKSEL) & BM_SIM_SOPT4_FTM3CLKSEL)
Kojto	90:cb3d968589d8	1109
Kojto	90:cb3d968589d8	1110	/! @brief Set the FTM3CLKSEL field to a new value. /
Kojto	90:cb3d968589d8	1111	#define BW_SIM_SOPT4_FTM3CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3CLKSEL) = (v))
Kojto	90:cb3d968589d8	1112	/@}/
Kojto	90:cb3d968589d8	1113
Kojto	90:cb3d968589d8	1114	/*!
Kojto	90:cb3d968589d8	1115	* @name Register SIM_SOPT4, field FTM0TRG0SRC[28] (RW)
Kojto	90:cb3d968589d8	1116	*
Kojto	90:cb3d968589d8	1117	* Selects the source of FTM0 hardware trigger 0.
Kojto	90:cb3d968589d8	1118	*
Kojto	90:cb3d968589d8	1119	* Values:
Kojto	90:cb3d968589d8	1120	* - 0 - HSCMP0 output drives FTM0 hardware trigger 0
Kojto	90:cb3d968589d8	1121	* - 1 - FTM1 channel match drives FTM0 hardware trigger 0
Kojto	90:cb3d968589d8	1122	*/
Kojto	90:cb3d968589d8	1123	/@{/
Kojto	90:cb3d968589d8	1124	#define BP_SIM_SOPT4_FTM0TRG0SRC (28U) /!< Bit position for SIM_SOPT4_FTM0TRG0SRC. /
Kojto	90:cb3d968589d8	1125	#define BM_SIM_SOPT4_FTM0TRG0SRC (0x10000000U) /!< Bit mask for SIM_SOPT4_FTM0TRG0SRC. /
Kojto	90:cb3d968589d8	1126	#define BS_SIM_SOPT4_FTM0TRG0SRC (1U) /!< Bit field size in bits for SIM_SOPT4_FTM0TRG0SRC. /
Kojto	90:cb3d968589d8	1127
Kojto	90:cb3d968589d8	1128	/! @brief Read current value of the SIM_SOPT4_FTM0TRG0SRC field. /
Kojto	90:cb3d968589d8	1129	#define BR_SIM_SOPT4_FTM0TRG0SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG0SRC))
Kojto	90:cb3d968589d8	1130
Kojto	90:cb3d968589d8	1131	/! @brief Format value for bitfield SIM_SOPT4_FTM0TRG0SRC. /
Kojto	90:cb3d968589d8	1132	#define BF_SIM_SOPT4_FTM0TRG0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0TRG0SRC) & BM_SIM_SOPT4_FTM0TRG0SRC)
Kojto	90:cb3d968589d8	1133
Kojto	90:cb3d968589d8	1134	/! @brief Set the FTM0TRG0SRC field to a new value. /
Kojto	90:cb3d968589d8	1135	#define BW_SIM_SOPT4_FTM0TRG0SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG0SRC) = (v))
Kojto	90:cb3d968589d8	1136	/@}/
Kojto	90:cb3d968589d8	1137
Kojto	90:cb3d968589d8	1138	/*!
Kojto	90:cb3d968589d8	1139	* @name Register SIM_SOPT4, field FTM0TRG1SRC[29] (RW)
Kojto	90:cb3d968589d8	1140	*
Kojto	90:cb3d968589d8	1141	* Selects the source of FTM0 hardware trigger 1.
Kojto	90:cb3d968589d8	1142	*
Kojto	90:cb3d968589d8	1143	* Values:
Kojto	90:cb3d968589d8	1144	* - 0 - PDB output trigger 1 drives FTM0 hardware trigger 1
Kojto	90:cb3d968589d8	1145	* - 1 - FTM2 channel match drives FTM0 hardware trigger 1
Kojto	90:cb3d968589d8	1146	*/
Kojto	90:cb3d968589d8	1147	/@{/
Kojto	90:cb3d968589d8	1148	#define BP_SIM_SOPT4_FTM0TRG1SRC (29U) /!< Bit position for SIM_SOPT4_FTM0TRG1SRC. /
Kojto	90:cb3d968589d8	1149	#define BM_SIM_SOPT4_FTM0TRG1SRC (0x20000000U) /!< Bit mask for SIM_SOPT4_FTM0TRG1SRC. /
Kojto	90:cb3d968589d8	1150	#define BS_SIM_SOPT4_FTM0TRG1SRC (1U) /!< Bit field size in bits for SIM_SOPT4_FTM0TRG1SRC. /
Kojto	90:cb3d968589d8	1151
Kojto	90:cb3d968589d8	1152	/! @brief Read current value of the SIM_SOPT4_FTM0TRG1SRC field. /
Kojto	90:cb3d968589d8	1153	#define BR_SIM_SOPT4_FTM0TRG1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG1SRC))
Kojto	90:cb3d968589d8	1154
Kojto	90:cb3d968589d8	1155	/! @brief Format value for bitfield SIM_SOPT4_FTM0TRG1SRC. /
Kojto	90:cb3d968589d8	1156	#define BF_SIM_SOPT4_FTM0TRG1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0TRG1SRC) & BM_SIM_SOPT4_FTM0TRG1SRC)
Kojto	90:cb3d968589d8	1157
Kojto	90:cb3d968589d8	1158	/! @brief Set the FTM0TRG1SRC field to a new value. /
Kojto	90:cb3d968589d8	1159	#define BW_SIM_SOPT4_FTM0TRG1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG1SRC) = (v))
Kojto	90:cb3d968589d8	1160	/@}/
Kojto	90:cb3d968589d8	1161
Kojto	90:cb3d968589d8	1162	/*!
Kojto	90:cb3d968589d8	1163	* @name Register SIM_SOPT4, field FTM3TRG0SRC[30] (RW)
Kojto	90:cb3d968589d8	1164	*
Kojto	90:cb3d968589d8	1165	* Selects the source of FTM3 hardware trigger 0.
Kojto	90:cb3d968589d8	1166	*
Kojto	90:cb3d968589d8	1167	* Values:
Kojto	90:cb3d968589d8	1168	* - 0 - Reserved
Kojto	90:cb3d968589d8	1169	* - 1 - FTM1 channel match drives FTM3 hardware trigger 0
Kojto	90:cb3d968589d8	1170	*/
Kojto	90:cb3d968589d8	1171	/@{/
Kojto	90:cb3d968589d8	1172	#define BP_SIM_SOPT4_FTM3TRG0SRC (30U) /!< Bit position for SIM_SOPT4_FTM3TRG0SRC. /
Kojto	90:cb3d968589d8	1173	#define BM_SIM_SOPT4_FTM3TRG0SRC (0x40000000U) /!< Bit mask for SIM_SOPT4_FTM3TRG0SRC. /
Kojto	90:cb3d968589d8	1174	#define BS_SIM_SOPT4_FTM3TRG0SRC (1U) /!< Bit field size in bits for SIM_SOPT4_FTM3TRG0SRC. /
Kojto	90:cb3d968589d8	1175
Kojto	90:cb3d968589d8	1176	/! @brief Read current value of the SIM_SOPT4_FTM3TRG0SRC field. /
Kojto	90:cb3d968589d8	1177	#define BR_SIM_SOPT4_FTM3TRG0SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG0SRC))
Kojto	90:cb3d968589d8	1178
Kojto	90:cb3d968589d8	1179	/! @brief Format value for bitfield SIM_SOPT4_FTM3TRG0SRC. /
Kojto	90:cb3d968589d8	1180	#define BF_SIM_SOPT4_FTM3TRG0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3TRG0SRC) & BM_SIM_SOPT4_FTM3TRG0SRC)
Kojto	90:cb3d968589d8	1181
Kojto	90:cb3d968589d8	1182	/! @brief Set the FTM3TRG0SRC field to a new value. /
Kojto	90:cb3d968589d8	1183	#define BW_SIM_SOPT4_FTM3TRG0SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG0SRC) = (v))
Kojto	90:cb3d968589d8	1184	/@}/
Kojto	90:cb3d968589d8	1185
Kojto	90:cb3d968589d8	1186	/*!
Kojto	90:cb3d968589d8	1187	* @name Register SIM_SOPT4, field FTM3TRG1SRC[31] (RW)
Kojto	90:cb3d968589d8	1188	*
Kojto	90:cb3d968589d8	1189	* Selects the source of FTM3 hardware trigger 1.
Kojto	90:cb3d968589d8	1190	*
Kojto	90:cb3d968589d8	1191	* Values:
Kojto	90:cb3d968589d8	1192	* - 0 - Reserved
Kojto	90:cb3d968589d8	1193	* - 1 - FTM2 channel match drives FTM3 hardware trigger 1
Kojto	90:cb3d968589d8	1194	*/
Kojto	90:cb3d968589d8	1195	/@{/
Kojto	90:cb3d968589d8	1196	#define BP_SIM_SOPT4_FTM3TRG1SRC (31U) /!< Bit position for SIM_SOPT4_FTM3TRG1SRC. /
Kojto	90:cb3d968589d8	1197	#define BM_SIM_SOPT4_FTM3TRG1SRC (0x80000000U) /!< Bit mask for SIM_SOPT4_FTM3TRG1SRC. /
Kojto	90:cb3d968589d8	1198	#define BS_SIM_SOPT4_FTM3TRG1SRC (1U) /!< Bit field size in bits for SIM_SOPT4_FTM3TRG1SRC. /
Kojto	90:cb3d968589d8	1199
Kojto	90:cb3d968589d8	1200	/! @brief Read current value of the SIM_SOPT4_FTM3TRG1SRC field. /
Kojto	90:cb3d968589d8	1201	#define BR_SIM_SOPT4_FTM3TRG1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG1SRC))
Kojto	90:cb3d968589d8	1202
Kojto	90:cb3d968589d8	1203	/! @brief Format value for bitfield SIM_SOPT4_FTM3TRG1SRC. /
Kojto	90:cb3d968589d8	1204	#define BF_SIM_SOPT4_FTM3TRG1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3TRG1SRC) & BM_SIM_SOPT4_FTM3TRG1SRC)
Kojto	90:cb3d968589d8	1205
Kojto	90:cb3d968589d8	1206	/! @brief Set the FTM3TRG1SRC field to a new value. /
Kojto	90:cb3d968589d8	1207	#define BW_SIM_SOPT4_FTM3TRG1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG1SRC) = (v))
Kojto	90:cb3d968589d8	1208	/@}/
Kojto	90:cb3d968589d8	1209
Kojto	90:cb3d968589d8	1210	/*******************************************************************************
Kojto	90:cb3d968589d8	1211	* HW_SIM_SOPT5 - System Options Register 5
Kojto	90:cb3d968589d8	1212	******************************************************************************/
Kojto	90:cb3d968589d8	1213
Kojto	90:cb3d968589d8	1214	/*!
Kojto	90:cb3d968589d8	1215	* @brief HW_SIM_SOPT5 - System Options Register 5 (RW)
Kojto	90:cb3d968589d8	1216	*
Kojto	90:cb3d968589d8	1217	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1218	*/
Kojto	90:cb3d968589d8	1219	typedef union _hw_sim_sopt5
Kojto	90:cb3d968589d8	1220	{
Kojto	90:cb3d968589d8	1221	uint32_t U;
Kojto	90:cb3d968589d8	1222	struct _hw_sim_sopt5_bitfields
Kojto	90:cb3d968589d8	1223	{
Kojto	90:cb3d968589d8	1224	uint32_t UART0TXSRC : 2; /*!< [1:0] UART 0 transmit data source
Kojto	90:cb3d968589d8	1225	* select */
Kojto	90:cb3d968589d8	1226	uint32_t UART0RXSRC : 2; /*!< [3:2] UART 0 receive data source select
Kojto	90:cb3d968589d8	1227	* */
Kojto	90:cb3d968589d8	1228	uint32_t UART1TXSRC : 2; /*!< [5:4] UART 1 transmit data source
Kojto	90:cb3d968589d8	1229	* select */
Kojto	90:cb3d968589d8	1230	uint32_t UART1RXSRC : 2; /*!< [7:6] UART 1 receive data source select
Kojto	90:cb3d968589d8	1231	* */
Kojto	90:cb3d968589d8	1232	uint32_t RESERVED0 : 24; /!< [31:8] /
Kojto	90:cb3d968589d8	1233	} B;
Kojto	90:cb3d968589d8	1234	} hw_sim_sopt5_t;
Kojto	90:cb3d968589d8	1235
Kojto	90:cb3d968589d8	1236	/*!
Kojto	90:cb3d968589d8	1237	* @name Constants and macros for entire SIM_SOPT5 register
Kojto	90:cb3d968589d8	1238	*/
Kojto	90:cb3d968589d8	1239	/@{/
Kojto	90:cb3d968589d8	1240	#define HW_SIM_SOPT5_ADDR(x) ((x) + 0x1010U)
Kojto	90:cb3d968589d8	1241
Kojto	90:cb3d968589d8	1242	#define HW_SIM_SOPT5(x) ((__IO hw_sim_sopt5_t ) HW_SIM_SOPT5_ADDR(x))
Kojto	90:cb3d968589d8	1243	#define HW_SIM_SOPT5_RD(x) (HW_SIM_SOPT5(x).U)
Kojto	90:cb3d968589d8	1244	#define HW_SIM_SOPT5_WR(x, v) (HW_SIM_SOPT5(x).U = (v))
Kojto	90:cb3d968589d8	1245	#define HW_SIM_SOPT5_SET(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1246	#define HW_SIM_SOPT5_CLR(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1247	#define HW_SIM_SOPT5_TOG(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1248	/@}/
Kojto	90:cb3d968589d8	1249
Kojto	90:cb3d968589d8	1250	/*
Kojto	90:cb3d968589d8	1251	* Constants & macros for individual SIM_SOPT5 bitfields
Kojto	90:cb3d968589d8	1252	*/
Kojto	90:cb3d968589d8	1253
Kojto	90:cb3d968589d8	1254	/*!
Kojto	90:cb3d968589d8	1255	* @name Register SIM_SOPT5, field UART0TXSRC[1:0] (RW)
Kojto	90:cb3d968589d8	1256	*
Kojto	90:cb3d968589d8	1257	* Selects the source for the UART 0 transmit data.
Kojto	90:cb3d968589d8	1258	*
Kojto	90:cb3d968589d8	1259	* Values:
Kojto	90:cb3d968589d8	1260	* - 00 - UART0_TX pin
Kojto	90:cb3d968589d8	1261	* - 01 - UART0_TX pin modulated with FTM1 channel 0 output
Kojto	90:cb3d968589d8	1262	* - 10 - UART0_TX pin modulated with FTM2 channel 0 output
Kojto	90:cb3d968589d8	1263	* - 11 - Reserved
Kojto	90:cb3d968589d8	1264	*/
Kojto	90:cb3d968589d8	1265	/@{/
Kojto	90:cb3d968589d8	1266	#define BP_SIM_SOPT5_UART0TXSRC (0U) /!< Bit position for SIM_SOPT5_UART0TXSRC. /
Kojto	90:cb3d968589d8	1267	#define BM_SIM_SOPT5_UART0TXSRC (0x00000003U) /!< Bit mask for SIM_SOPT5_UART0TXSRC. /
Kojto	90:cb3d968589d8	1268	#define BS_SIM_SOPT5_UART0TXSRC (2U) /!< Bit field size in bits for SIM_SOPT5_UART0TXSRC. /
Kojto	90:cb3d968589d8	1269
Kojto	90:cb3d968589d8	1270	/! @brief Read current value of the SIM_SOPT5_UART0TXSRC field. /
Kojto	90:cb3d968589d8	1271	#define BR_SIM_SOPT5_UART0TXSRC(x) (HW_SIM_SOPT5(x).B.UART0TXSRC)
Kojto	90:cb3d968589d8	1272
Kojto	90:cb3d968589d8	1273	/! @brief Format value for bitfield SIM_SOPT5_UART0TXSRC. /
Kojto	90:cb3d968589d8	1274	#define BF_SIM_SOPT5_UART0TXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART0TXSRC) & BM_SIM_SOPT5_UART0TXSRC)
Kojto	90:cb3d968589d8	1275
Kojto	90:cb3d968589d8	1276	/! @brief Set the UART0TXSRC field to a new value. /
Kojto	90:cb3d968589d8	1277	#define BW_SIM_SOPT5_UART0TXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART0TXSRC) \| BF_SIM_SOPT5_UART0TXSRC(v)))
Kojto	90:cb3d968589d8	1278	/@}/
Kojto	90:cb3d968589d8	1279
Kojto	90:cb3d968589d8	1280	/*!
Kojto	90:cb3d968589d8	1281	* @name Register SIM_SOPT5, field UART0RXSRC[3:2] (RW)
Kojto	90:cb3d968589d8	1282	*
Kojto	90:cb3d968589d8	1283	* Selects the source for the UART 0 receive data.
Kojto	90:cb3d968589d8	1284	*
Kojto	90:cb3d968589d8	1285	* Values:
Kojto	90:cb3d968589d8	1286	* - 00 - UART0_RX pin
Kojto	90:cb3d968589d8	1287	* - 01 - CMP0
Kojto	90:cb3d968589d8	1288	* - 10 - CMP1
Kojto	90:cb3d968589d8	1289	* - 11 - Reserved
Kojto	90:cb3d968589d8	1290	*/
Kojto	90:cb3d968589d8	1291	/@{/
Kojto	90:cb3d968589d8	1292	#define BP_SIM_SOPT5_UART0RXSRC (2U) /!< Bit position for SIM_SOPT5_UART0RXSRC. /
Kojto	90:cb3d968589d8	1293	#define BM_SIM_SOPT5_UART0RXSRC (0x0000000CU) /!< Bit mask for SIM_SOPT5_UART0RXSRC. /
Kojto	90:cb3d968589d8	1294	#define BS_SIM_SOPT5_UART0RXSRC (2U) /!< Bit field size in bits for SIM_SOPT5_UART0RXSRC. /
Kojto	90:cb3d968589d8	1295
Kojto	90:cb3d968589d8	1296	/! @brief Read current value of the SIM_SOPT5_UART0RXSRC field. /
Kojto	90:cb3d968589d8	1297	#define BR_SIM_SOPT5_UART0RXSRC(x) (HW_SIM_SOPT5(x).B.UART0RXSRC)
Kojto	90:cb3d968589d8	1298
Kojto	90:cb3d968589d8	1299	/! @brief Format value for bitfield SIM_SOPT5_UART0RXSRC. /
Kojto	90:cb3d968589d8	1300	#define BF_SIM_SOPT5_UART0RXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART0RXSRC) & BM_SIM_SOPT5_UART0RXSRC)
Kojto	90:cb3d968589d8	1301
Kojto	90:cb3d968589d8	1302	/! @brief Set the UART0RXSRC field to a new value. /
Kojto	90:cb3d968589d8	1303	#define BW_SIM_SOPT5_UART0RXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART0RXSRC) \| BF_SIM_SOPT5_UART0RXSRC(v)))
Kojto	90:cb3d968589d8	1304	/@}/
Kojto	90:cb3d968589d8	1305
Kojto	90:cb3d968589d8	1306	/*!
Kojto	90:cb3d968589d8	1307	* @name Register SIM_SOPT5, field UART1TXSRC[5:4] (RW)
Kojto	90:cb3d968589d8	1308	*
Kojto	90:cb3d968589d8	1309	* Selects the source for the UART 1 transmit data.
Kojto	90:cb3d968589d8	1310	*
Kojto	90:cb3d968589d8	1311	* Values:
Kojto	90:cb3d968589d8	1312	* - 00 - UART1_TX pin
Kojto	90:cb3d968589d8	1313	* - 01 - UART1_TX pin modulated with FTM1 channel 0 output
Kojto	90:cb3d968589d8	1314	* - 10 - UART1_TX pin modulated with FTM2 channel 0 output
Kojto	90:cb3d968589d8	1315	* - 11 - Reserved
Kojto	90:cb3d968589d8	1316	*/
Kojto	90:cb3d968589d8	1317	/@{/
Kojto	90:cb3d968589d8	1318	#define BP_SIM_SOPT5_UART1TXSRC (4U) /!< Bit position for SIM_SOPT5_UART1TXSRC. /
Kojto	90:cb3d968589d8	1319	#define BM_SIM_SOPT5_UART1TXSRC (0x00000030U) /!< Bit mask for SIM_SOPT5_UART1TXSRC. /
Kojto	90:cb3d968589d8	1320	#define BS_SIM_SOPT5_UART1TXSRC (2U) /!< Bit field size in bits for SIM_SOPT5_UART1TXSRC. /
Kojto	90:cb3d968589d8	1321
Kojto	90:cb3d968589d8	1322	/! @brief Read current value of the SIM_SOPT5_UART1TXSRC field. /
Kojto	90:cb3d968589d8	1323	#define BR_SIM_SOPT5_UART1TXSRC(x) (HW_SIM_SOPT5(x).B.UART1TXSRC)
Kojto	90:cb3d968589d8	1324
Kojto	90:cb3d968589d8	1325	/! @brief Format value for bitfield SIM_SOPT5_UART1TXSRC. /
Kojto	90:cb3d968589d8	1326	#define BF_SIM_SOPT5_UART1TXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART1TXSRC) & BM_SIM_SOPT5_UART1TXSRC)
Kojto	90:cb3d968589d8	1327
Kojto	90:cb3d968589d8	1328	/! @brief Set the UART1TXSRC field to a new value. /
Kojto	90:cb3d968589d8	1329	#define BW_SIM_SOPT5_UART1TXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART1TXSRC) \| BF_SIM_SOPT5_UART1TXSRC(v)))
Kojto	90:cb3d968589d8	1330	/@}/
Kojto	90:cb3d968589d8	1331
Kojto	90:cb3d968589d8	1332	/*!
Kojto	90:cb3d968589d8	1333	* @name Register SIM_SOPT5, field UART1RXSRC[7:6] (RW)
Kojto	90:cb3d968589d8	1334	*
Kojto	90:cb3d968589d8	1335	* Selects the source for the UART 1 receive data.
Kojto	90:cb3d968589d8	1336	*
Kojto	90:cb3d968589d8	1337	* Values:
Kojto	90:cb3d968589d8	1338	* - 00 - UART1_RX pin
Kojto	90:cb3d968589d8	1339	* - 01 - CMP0
Kojto	90:cb3d968589d8	1340	* - 10 - CMP1
Kojto	90:cb3d968589d8	1341	* - 11 - Reserved
Kojto	90:cb3d968589d8	1342	*/
Kojto	90:cb3d968589d8	1343	/@{/
Kojto	90:cb3d968589d8	1344	#define BP_SIM_SOPT5_UART1RXSRC (6U) /!< Bit position for SIM_SOPT5_UART1RXSRC. /
Kojto	90:cb3d968589d8	1345	#define BM_SIM_SOPT5_UART1RXSRC (0x000000C0U) /!< Bit mask for SIM_SOPT5_UART1RXSRC. /
Kojto	90:cb3d968589d8	1346	#define BS_SIM_SOPT5_UART1RXSRC (2U) /!< Bit field size in bits for SIM_SOPT5_UART1RXSRC. /
Kojto	90:cb3d968589d8	1347
Kojto	90:cb3d968589d8	1348	/! @brief Read current value of the SIM_SOPT5_UART1RXSRC field. /
Kojto	90:cb3d968589d8	1349	#define BR_SIM_SOPT5_UART1RXSRC(x) (HW_SIM_SOPT5(x).B.UART1RXSRC)
Kojto	90:cb3d968589d8	1350
Kojto	90:cb3d968589d8	1351	/! @brief Format value for bitfield SIM_SOPT5_UART1RXSRC. /
Kojto	90:cb3d968589d8	1352	#define BF_SIM_SOPT5_UART1RXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART1RXSRC) & BM_SIM_SOPT5_UART1RXSRC)
Kojto	90:cb3d968589d8	1353
Kojto	90:cb3d968589d8	1354	/! @brief Set the UART1RXSRC field to a new value. /
Kojto	90:cb3d968589d8	1355	#define BW_SIM_SOPT5_UART1RXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART1RXSRC) \| BF_SIM_SOPT5_UART1RXSRC(v)))
Kojto	90:cb3d968589d8	1356	/@}/
Kojto	90:cb3d968589d8	1357
Kojto	90:cb3d968589d8	1358	/*******************************************************************************
Kojto	90:cb3d968589d8	1359	* HW_SIM_SOPT7 - System Options Register 7
Kojto	90:cb3d968589d8	1360	******************************************************************************/
Kojto	90:cb3d968589d8	1361
Kojto	90:cb3d968589d8	1362	/*!
Kojto	90:cb3d968589d8	1363	* @brief HW_SIM_SOPT7 - System Options Register 7 (RW)
Kojto	90:cb3d968589d8	1364	*
Kojto	90:cb3d968589d8	1365	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1366	*/
Kojto	90:cb3d968589d8	1367	typedef union _hw_sim_sopt7
Kojto	90:cb3d968589d8	1368	{
Kojto	90:cb3d968589d8	1369	uint32_t U;
Kojto	90:cb3d968589d8	1370	struct _hw_sim_sopt7_bitfields
Kojto	90:cb3d968589d8	1371	{
Kojto	90:cb3d968589d8	1372	uint32_t ADC0TRGSEL : 4; /!< [3:0] ADC0 trigger select /
Kojto	90:cb3d968589d8	1373	uint32_t ADC0PRETRGSEL : 1; /!< [4] ADC0 pretrigger select /
Kojto	90:cb3d968589d8	1374	uint32_t RESERVED0 : 2; /!< [6:5] /
Kojto	90:cb3d968589d8	1375	uint32_t ADC0ALTTRGEN : 1; /!< [7] ADC0 alternate trigger enable /
Kojto	90:cb3d968589d8	1376	uint32_t ADC1TRGSEL : 4; /!< [11:8] ADC1 trigger select /
Kojto	90:cb3d968589d8	1377	uint32_t ADC1PRETRGSEL : 1; /!< [12] ADC1 pre-trigger select /
Kojto	90:cb3d968589d8	1378	uint32_t RESERVED1 : 2; /!< [14:13] /
Kojto	90:cb3d968589d8	1379	uint32_t ADC1ALTTRGEN : 1; /!< [15] ADC1 alternate trigger enable /
Kojto	90:cb3d968589d8	1380	uint32_t RESERVED2 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	1381	} B;
Kojto	90:cb3d968589d8	1382	} hw_sim_sopt7_t;
Kojto	90:cb3d968589d8	1383
Kojto	90:cb3d968589d8	1384	/*!
Kojto	90:cb3d968589d8	1385	* @name Constants and macros for entire SIM_SOPT7 register
Kojto	90:cb3d968589d8	1386	*/
Kojto	90:cb3d968589d8	1387	/@{/
Kojto	90:cb3d968589d8	1388	#define HW_SIM_SOPT7_ADDR(x) ((x) + 0x1018U)
Kojto	90:cb3d968589d8	1389
Kojto	90:cb3d968589d8	1390	#define HW_SIM_SOPT7(x) ((__IO hw_sim_sopt7_t ) HW_SIM_SOPT7_ADDR(x))
Kojto	90:cb3d968589d8	1391	#define HW_SIM_SOPT7_RD(x) (HW_SIM_SOPT7(x).U)
Kojto	90:cb3d968589d8	1392	#define HW_SIM_SOPT7_WR(x, v) (HW_SIM_SOPT7(x).U = (v))
Kojto	90:cb3d968589d8	1393	#define HW_SIM_SOPT7_SET(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1394	#define HW_SIM_SOPT7_CLR(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1395	#define HW_SIM_SOPT7_TOG(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1396	/@}/
Kojto	90:cb3d968589d8	1397
Kojto	90:cb3d968589d8	1398	/*
Kojto	90:cb3d968589d8	1399	* Constants & macros for individual SIM_SOPT7 bitfields
Kojto	90:cb3d968589d8	1400	*/
Kojto	90:cb3d968589d8	1401
Kojto	90:cb3d968589d8	1402	/*!
Kojto	90:cb3d968589d8	1403	* @name Register SIM_SOPT7, field ADC0TRGSEL[3:0] (RW)
Kojto	90:cb3d968589d8	1404	*
Kojto	90:cb3d968589d8	1405	* Selects the ADC0 trigger source when alternative triggers are functional in
Kojto	90:cb3d968589d8	1406	* stop and VLPS modes. .
Kojto	90:cb3d968589d8	1407	*
Kojto	90:cb3d968589d8	1408	* Values:
Kojto	90:cb3d968589d8	1409	* - 0000 - PDB external trigger pin input (PDB0_EXTRG)
Kojto	90:cb3d968589d8	1410	* - 0001 - High speed comparator 0 output
Kojto	90:cb3d968589d8	1411	* - 0010 - High speed comparator 1 output
Kojto	90:cb3d968589d8	1412	* - 0011 - High speed comparator 2 output
Kojto	90:cb3d968589d8	1413	* - 0100 - PIT trigger 0
Kojto	90:cb3d968589d8	1414	* - 0101 - PIT trigger 1
Kojto	90:cb3d968589d8	1415	* - 0110 - PIT trigger 2
Kojto	90:cb3d968589d8	1416	* - 0111 - PIT trigger 3
Kojto	90:cb3d968589d8	1417	* - 1000 - FTM0 trigger
Kojto	90:cb3d968589d8	1418	* - 1001 - FTM1 trigger
Kojto	90:cb3d968589d8	1419	* - 1010 - FTM2 trigger
Kojto	90:cb3d968589d8	1420	* - 1011 - FTM3 trigger
Kojto	90:cb3d968589d8	1421	* - 1100 - RTC alarm
Kojto	90:cb3d968589d8	1422	* - 1101 - RTC seconds
Kojto	90:cb3d968589d8	1423	* - 1110 - Low-power timer (LPTMR) trigger
Kojto	90:cb3d968589d8	1424	* - 1111 - Reserved
Kojto	90:cb3d968589d8	1425	*/
Kojto	90:cb3d968589d8	1426	/@{/
Kojto	90:cb3d968589d8	1427	#define BP_SIM_SOPT7_ADC0TRGSEL (0U) /!< Bit position for SIM_SOPT7_ADC0TRGSEL. /
Kojto	90:cb3d968589d8	1428	#define BM_SIM_SOPT7_ADC0TRGSEL (0x0000000FU) /!< Bit mask for SIM_SOPT7_ADC0TRGSEL. /
Kojto	90:cb3d968589d8	1429	#define BS_SIM_SOPT7_ADC0TRGSEL (4U) /!< Bit field size in bits for SIM_SOPT7_ADC0TRGSEL. /
Kojto	90:cb3d968589d8	1430
Kojto	90:cb3d968589d8	1431	/! @brief Read current value of the SIM_SOPT7_ADC0TRGSEL field. /
Kojto	90:cb3d968589d8	1432	#define BR_SIM_SOPT7_ADC0TRGSEL(x) (HW_SIM_SOPT7(x).B.ADC0TRGSEL)
Kojto	90:cb3d968589d8	1433
Kojto	90:cb3d968589d8	1434	/! @brief Format value for bitfield SIM_SOPT7_ADC0TRGSEL. /
Kojto	90:cb3d968589d8	1435	#define BF_SIM_SOPT7_ADC0TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0TRGSEL) & BM_SIM_SOPT7_ADC0TRGSEL)
Kojto	90:cb3d968589d8	1436
Kojto	90:cb3d968589d8	1437	/! @brief Set the ADC0TRGSEL field to a new value. /
Kojto	90:cb3d968589d8	1438	#define BW_SIM_SOPT7_ADC0TRGSEL(x, v) (HW_SIM_SOPT7_WR(x, (HW_SIM_SOPT7_RD(x) & ~BM_SIM_SOPT7_ADC0TRGSEL) \| BF_SIM_SOPT7_ADC0TRGSEL(v)))
Kojto	90:cb3d968589d8	1439	/@}/
Kojto	90:cb3d968589d8	1440
Kojto	90:cb3d968589d8	1441	/*!
Kojto	90:cb3d968589d8	1442	* @name Register SIM_SOPT7, field ADC0PRETRGSEL[4] (RW)
Kojto	90:cb3d968589d8	1443	*
Kojto	90:cb3d968589d8	1444	* Selects the ADC0 pre-trigger source when alternative triggers are enabled
Kojto	90:cb3d968589d8	1445	* through ADC0ALTTRGEN.
Kojto	90:cb3d968589d8	1446	*
Kojto	90:cb3d968589d8	1447	* Values:
Kojto	90:cb3d968589d8	1448	* - 0 - Pre-trigger A
Kojto	90:cb3d968589d8	1449	* - 1 - Pre-trigger B
Kojto	90:cb3d968589d8	1450	*/
Kojto	90:cb3d968589d8	1451	/@{/
Kojto	90:cb3d968589d8	1452	#define BP_SIM_SOPT7_ADC0PRETRGSEL (4U) /!< Bit position for SIM_SOPT7_ADC0PRETRGSEL. /
Kojto	90:cb3d968589d8	1453	#define BM_SIM_SOPT7_ADC0PRETRGSEL (0x00000010U) /!< Bit mask for SIM_SOPT7_ADC0PRETRGSEL. /
Kojto	90:cb3d968589d8	1454	#define BS_SIM_SOPT7_ADC0PRETRGSEL (1U) /!< Bit field size in bits for SIM_SOPT7_ADC0PRETRGSEL. /
Kojto	90:cb3d968589d8	1455
Kojto	90:cb3d968589d8	1456	/! @brief Read current value of the SIM_SOPT7_ADC0PRETRGSEL field. /
Kojto	90:cb3d968589d8	1457	#define BR_SIM_SOPT7_ADC0PRETRGSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0PRETRGSEL))
Kojto	90:cb3d968589d8	1458
Kojto	90:cb3d968589d8	1459	/! @brief Format value for bitfield SIM_SOPT7_ADC0PRETRGSEL. /
Kojto	90:cb3d968589d8	1460	#define BF_SIM_SOPT7_ADC0PRETRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0PRETRGSEL) & BM_SIM_SOPT7_ADC0PRETRGSEL)
Kojto	90:cb3d968589d8	1461
Kojto	90:cb3d968589d8	1462	/! @brief Set the ADC0PRETRGSEL field to a new value. /
Kojto	90:cb3d968589d8	1463	#define BW_SIM_SOPT7_ADC0PRETRGSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0PRETRGSEL) = (v))
Kojto	90:cb3d968589d8	1464	/@}/
Kojto	90:cb3d968589d8	1465
Kojto	90:cb3d968589d8	1466	/*!
Kojto	90:cb3d968589d8	1467	* @name Register SIM_SOPT7, field ADC0ALTTRGEN[7] (RW)
Kojto	90:cb3d968589d8	1468	*
Kojto	90:cb3d968589d8	1469	* Enable alternative conversion triggers for ADC0.
Kojto	90:cb3d968589d8	1470	*
Kojto	90:cb3d968589d8	1471	* Values:
Kojto	90:cb3d968589d8	1472	* - 0 - PDB trigger selected for ADC0.
Kojto	90:cb3d968589d8	1473	* - 1 - Alternate trigger selected for ADC0.
Kojto	90:cb3d968589d8	1474	*/
Kojto	90:cb3d968589d8	1475	/@{/
Kojto	90:cb3d968589d8	1476	#define BP_SIM_SOPT7_ADC0ALTTRGEN (7U) /!< Bit position for SIM_SOPT7_ADC0ALTTRGEN. /
Kojto	90:cb3d968589d8	1477	#define BM_SIM_SOPT7_ADC0ALTTRGEN (0x00000080U) /!< Bit mask for SIM_SOPT7_ADC0ALTTRGEN. /
Kojto	90:cb3d968589d8	1478	#define BS_SIM_SOPT7_ADC0ALTTRGEN (1U) /!< Bit field size in bits for SIM_SOPT7_ADC0ALTTRGEN. /
Kojto	90:cb3d968589d8	1479
Kojto	90:cb3d968589d8	1480	/! @brief Read current value of the SIM_SOPT7_ADC0ALTTRGEN field. /
Kojto	90:cb3d968589d8	1481	#define BR_SIM_SOPT7_ADC0ALTTRGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0ALTTRGEN))
Kojto	90:cb3d968589d8	1482
Kojto	90:cb3d968589d8	1483	/! @brief Format value for bitfield SIM_SOPT7_ADC0ALTTRGEN. /
Kojto	90:cb3d968589d8	1484	#define BF_SIM_SOPT7_ADC0ALTTRGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0ALTTRGEN) & BM_SIM_SOPT7_ADC0ALTTRGEN)
Kojto	90:cb3d968589d8	1485
Kojto	90:cb3d968589d8	1486	/! @brief Set the ADC0ALTTRGEN field to a new value. /
Kojto	90:cb3d968589d8	1487	#define BW_SIM_SOPT7_ADC0ALTTRGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0ALTTRGEN) = (v))
Kojto	90:cb3d968589d8	1488	/@}/
Kojto	90:cb3d968589d8	1489
Kojto	90:cb3d968589d8	1490	/*!
Kojto	90:cb3d968589d8	1491	* @name Register SIM_SOPT7, field ADC1TRGSEL[11:8] (RW)
Kojto	90:cb3d968589d8	1492	*
Kojto	90:cb3d968589d8	1493	* Selects the ADC1 trigger source when alternative triggers are functional in
Kojto	90:cb3d968589d8	1494	* stop and VLPS modes.
Kojto	90:cb3d968589d8	1495	*
Kojto	90:cb3d968589d8	1496	* Values:
Kojto	90:cb3d968589d8	1497	* - 0000 - PDB external trigger pin input (PDB0_EXTRG)
Kojto	90:cb3d968589d8	1498	* - 0001 - High speed comparator 0 output
Kojto	90:cb3d968589d8	1499	* - 0010 - High speed comparator 1 output
Kojto	90:cb3d968589d8	1500	* - 0011 - High speed comparator 2 output
Kojto	90:cb3d968589d8	1501	* - 0100 - PIT trigger 0
Kojto	90:cb3d968589d8	1502	* - 0101 - PIT trigger 1
Kojto	90:cb3d968589d8	1503	* - 0110 - PIT trigger 2
Kojto	90:cb3d968589d8	1504	* - 0111 - PIT trigger 3
Kojto	90:cb3d968589d8	1505	* - 1000 - FTM0 trigger
Kojto	90:cb3d968589d8	1506	* - 1001 - FTM1 trigger
Kojto	90:cb3d968589d8	1507	* - 1010 - FTM2 trigger
Kojto	90:cb3d968589d8	1508	* - 1011 - FTM3 trigger
Kojto	90:cb3d968589d8	1509	* - 1100 - RTC alarm
Kojto	90:cb3d968589d8	1510	* - 1101 - RTC seconds
Kojto	90:cb3d968589d8	1511	* - 1110 - Low-power timer (LPTMR) trigger
Kojto	90:cb3d968589d8	1512	* - 1111 - Reserved
Kojto	90:cb3d968589d8	1513	*/
Kojto	90:cb3d968589d8	1514	/@{/
Kojto	90:cb3d968589d8	1515	#define BP_SIM_SOPT7_ADC1TRGSEL (8U) /!< Bit position for SIM_SOPT7_ADC1TRGSEL. /
Kojto	90:cb3d968589d8	1516	#define BM_SIM_SOPT7_ADC1TRGSEL (0x00000F00U) /!< Bit mask for SIM_SOPT7_ADC1TRGSEL. /
Kojto	90:cb3d968589d8	1517	#define BS_SIM_SOPT7_ADC1TRGSEL (4U) /!< Bit field size in bits for SIM_SOPT7_ADC1TRGSEL. /
Kojto	90:cb3d968589d8	1518
Kojto	90:cb3d968589d8	1519	/! @brief Read current value of the SIM_SOPT7_ADC1TRGSEL field. /
Kojto	90:cb3d968589d8	1520	#define BR_SIM_SOPT7_ADC1TRGSEL(x) (HW_SIM_SOPT7(x).B.ADC1TRGSEL)
Kojto	90:cb3d968589d8	1521
Kojto	90:cb3d968589d8	1522	/! @brief Format value for bitfield SIM_SOPT7_ADC1TRGSEL. /
Kojto	90:cb3d968589d8	1523	#define BF_SIM_SOPT7_ADC1TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1TRGSEL) & BM_SIM_SOPT7_ADC1TRGSEL)
Kojto	90:cb3d968589d8	1524
Kojto	90:cb3d968589d8	1525	/! @brief Set the ADC1TRGSEL field to a new value. /
Kojto	90:cb3d968589d8	1526	#define BW_SIM_SOPT7_ADC1TRGSEL(x, v) (HW_SIM_SOPT7_WR(x, (HW_SIM_SOPT7_RD(x) & ~BM_SIM_SOPT7_ADC1TRGSEL) \| BF_SIM_SOPT7_ADC1TRGSEL(v)))
Kojto	90:cb3d968589d8	1527	/@}/
Kojto	90:cb3d968589d8	1528
Kojto	90:cb3d968589d8	1529	/*!
Kojto	90:cb3d968589d8	1530	* @name Register SIM_SOPT7, field ADC1PRETRGSEL[12] (RW)
Kojto	90:cb3d968589d8	1531	*
Kojto	90:cb3d968589d8	1532	* Selects the ADC1 pre-trigger source when alternative triggers are enabled
Kojto	90:cb3d968589d8	1533	* through ADC1ALTTRGEN.
Kojto	90:cb3d968589d8	1534	*
Kojto	90:cb3d968589d8	1535	* Values:
Kojto	90:cb3d968589d8	1536	* - 0 - Pre-trigger A selected for ADC1.
Kojto	90:cb3d968589d8	1537	* - 1 - Pre-trigger B selected for ADC1.
Kojto	90:cb3d968589d8	1538	*/
Kojto	90:cb3d968589d8	1539	/@{/
Kojto	90:cb3d968589d8	1540	#define BP_SIM_SOPT7_ADC1PRETRGSEL (12U) /!< Bit position for SIM_SOPT7_ADC1PRETRGSEL. /
Kojto	90:cb3d968589d8	1541	#define BM_SIM_SOPT7_ADC1PRETRGSEL (0x00001000U) /!< Bit mask for SIM_SOPT7_ADC1PRETRGSEL. /
Kojto	90:cb3d968589d8	1542	#define BS_SIM_SOPT7_ADC1PRETRGSEL (1U) /!< Bit field size in bits for SIM_SOPT7_ADC1PRETRGSEL. /
Kojto	90:cb3d968589d8	1543
Kojto	90:cb3d968589d8	1544	/! @brief Read current value of the SIM_SOPT7_ADC1PRETRGSEL field. /
Kojto	90:cb3d968589d8	1545	#define BR_SIM_SOPT7_ADC1PRETRGSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1PRETRGSEL))
Kojto	90:cb3d968589d8	1546
Kojto	90:cb3d968589d8	1547	/! @brief Format value for bitfield SIM_SOPT7_ADC1PRETRGSEL. /
Kojto	90:cb3d968589d8	1548	#define BF_SIM_SOPT7_ADC1PRETRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1PRETRGSEL) & BM_SIM_SOPT7_ADC1PRETRGSEL)
Kojto	90:cb3d968589d8	1549
Kojto	90:cb3d968589d8	1550	/! @brief Set the ADC1PRETRGSEL field to a new value. /
Kojto	90:cb3d968589d8	1551	#define BW_SIM_SOPT7_ADC1PRETRGSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1PRETRGSEL) = (v))
Kojto	90:cb3d968589d8	1552	/@}/
Kojto	90:cb3d968589d8	1553
Kojto	90:cb3d968589d8	1554	/*!
Kojto	90:cb3d968589d8	1555	* @name Register SIM_SOPT7, field ADC1ALTTRGEN[15] (RW)
Kojto	90:cb3d968589d8	1556	*
Kojto	90:cb3d968589d8	1557	* Enable alternative conversion triggers for ADC1.
Kojto	90:cb3d968589d8	1558	*
Kojto	90:cb3d968589d8	1559	* Values:
Kojto	90:cb3d968589d8	1560	* - 0 - PDB trigger selected for ADC1
Kojto	90:cb3d968589d8	1561	* - 1 - Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
Kojto	90:cb3d968589d8	1562	*/
Kojto	90:cb3d968589d8	1563	/@{/
Kojto	90:cb3d968589d8	1564	#define BP_SIM_SOPT7_ADC1ALTTRGEN (15U) /!< Bit position for SIM_SOPT7_ADC1ALTTRGEN. /
Kojto	90:cb3d968589d8	1565	#define BM_SIM_SOPT7_ADC1ALTTRGEN (0x00008000U) /!< Bit mask for SIM_SOPT7_ADC1ALTTRGEN. /
Kojto	90:cb3d968589d8	1566	#define BS_SIM_SOPT7_ADC1ALTTRGEN (1U) /!< Bit field size in bits for SIM_SOPT7_ADC1ALTTRGEN. /
Kojto	90:cb3d968589d8	1567
Kojto	90:cb3d968589d8	1568	/! @brief Read current value of the SIM_SOPT7_ADC1ALTTRGEN field. /
Kojto	90:cb3d968589d8	1569	#define BR_SIM_SOPT7_ADC1ALTTRGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1ALTTRGEN))
Kojto	90:cb3d968589d8	1570
Kojto	90:cb3d968589d8	1571	/! @brief Format value for bitfield SIM_SOPT7_ADC1ALTTRGEN. /
Kojto	90:cb3d968589d8	1572	#define BF_SIM_SOPT7_ADC1ALTTRGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1ALTTRGEN) & BM_SIM_SOPT7_ADC1ALTTRGEN)
Kojto	90:cb3d968589d8	1573
Kojto	90:cb3d968589d8	1574	/! @brief Set the ADC1ALTTRGEN field to a new value. /
Kojto	90:cb3d968589d8	1575	#define BW_SIM_SOPT7_ADC1ALTTRGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1ALTTRGEN) = (v))
Kojto	90:cb3d968589d8	1576	/@}/
Kojto	90:cb3d968589d8	1577
Kojto	90:cb3d968589d8	1578	/*******************************************************************************
Kojto	90:cb3d968589d8	1579	* HW_SIM_SDID - System Device Identification Register
Kojto	90:cb3d968589d8	1580	******************************************************************************/
Kojto	90:cb3d968589d8	1581
Kojto	90:cb3d968589d8	1582	/*!
Kojto	90:cb3d968589d8	1583	* @brief HW_SIM_SDID - System Device Identification Register (RO)
Kojto	90:cb3d968589d8	1584	*
Kojto	90:cb3d968589d8	1585	* Reset value: 0x00000380U
Kojto	90:cb3d968589d8	1586	*/
Kojto	90:cb3d968589d8	1587	typedef union _hw_sim_sdid
Kojto	90:cb3d968589d8	1588	{
Kojto	90:cb3d968589d8	1589	uint32_t U;
Kojto	90:cb3d968589d8	1590	struct _hw_sim_sdid_bitfields
Kojto	90:cb3d968589d8	1591	{
Kojto	90:cb3d968589d8	1592	uint32_t PINID : 4; /!< [3:0] Pincount identification /
Kojto	90:cb3d968589d8	1593	uint32_t FAMID : 3; /!< [6:4] Kinetis family identification /
Kojto	90:cb3d968589d8	1594	uint32_t DIEID : 5; /!< [11:7] Device Die ID /
Kojto	90:cb3d968589d8	1595	uint32_t REVID : 4; /!< [15:12] Device revision number /
Kojto	90:cb3d968589d8	1596	uint32_t RESERVED0 : 4; /!< [19:16] /
Kojto	90:cb3d968589d8	1597	uint32_t SERIESID : 4; /!< [23:20] Kinetis Series ID /
Kojto	90:cb3d968589d8	1598	uint32_t SUBFAMID : 4; /!< [27:24] Kinetis Sub-Family ID /
Kojto	90:cb3d968589d8	1599	uint32_t FAMILYID : 4; /!< [31:28] Kinetis Family ID /
Kojto	90:cb3d968589d8	1600	} B;
Kojto	90:cb3d968589d8	1601	} hw_sim_sdid_t;
Kojto	90:cb3d968589d8	1602
Kojto	90:cb3d968589d8	1603	/*!
Kojto	90:cb3d968589d8	1604	* @name Constants and macros for entire SIM_SDID register
Kojto	90:cb3d968589d8	1605	*/
Kojto	90:cb3d968589d8	1606	/@{/
Kojto	90:cb3d968589d8	1607	#define HW_SIM_SDID_ADDR(x) ((x) + 0x1024U)
Kojto	90:cb3d968589d8	1608
Kojto	90:cb3d968589d8	1609	#define HW_SIM_SDID(x) ((__I hw_sim_sdid_t ) HW_SIM_SDID_ADDR(x))
Kojto	90:cb3d968589d8	1610	#define HW_SIM_SDID_RD(x) (HW_SIM_SDID(x).U)
Kojto	90:cb3d968589d8	1611	/@}/
Kojto	90:cb3d968589d8	1612
Kojto	90:cb3d968589d8	1613	/*
Kojto	90:cb3d968589d8	1614	* Constants & macros for individual SIM_SDID bitfields
Kojto	90:cb3d968589d8	1615	*/
Kojto	90:cb3d968589d8	1616
Kojto	90:cb3d968589d8	1617	/*!
Kojto	90:cb3d968589d8	1618	* @name Register SIM_SDID, field PINID[3:0] (RO)
Kojto	90:cb3d968589d8	1619	*
Kojto	90:cb3d968589d8	1620	* Specifies the pincount of the device.
Kojto	90:cb3d968589d8	1621	*
Kojto	90:cb3d968589d8	1622	* Values:
Kojto	90:cb3d968589d8	1623	* - 0000 - Reserved
Kojto	90:cb3d968589d8	1624	* - 0001 - Reserved
Kojto	90:cb3d968589d8	1625	* - 0010 - 32-pin
Kojto	90:cb3d968589d8	1626	* - 0011 - Reserved
Kojto	90:cb3d968589d8	1627	* - 0100 - 48-pin
Kojto	90:cb3d968589d8	1628	* - 0101 - 64-pin
Kojto	90:cb3d968589d8	1629	* - 0110 - 80-pin
Kojto	90:cb3d968589d8	1630	* - 0111 - 81-pin or 121-pin
Kojto	90:cb3d968589d8	1631	* - 1000 - 100-pin
Kojto	90:cb3d968589d8	1632	* - 1001 - 121-pin
Kojto	90:cb3d968589d8	1633	* - 1010 - 144-pin
Kojto	90:cb3d968589d8	1634	* - 1011 - Custom pinout (WLCSP)
Kojto	90:cb3d968589d8	1635	* - 1100 - 169-pin
Kojto	90:cb3d968589d8	1636	* - 1101 - Reserved
Kojto	90:cb3d968589d8	1637	* - 1110 - 256-pin
Kojto	90:cb3d968589d8	1638	* - 1111 - Reserved
Kojto	90:cb3d968589d8	1639	*/
Kojto	90:cb3d968589d8	1640	/@{/
Kojto	90:cb3d968589d8	1641	#define BP_SIM_SDID_PINID (0U) /!< Bit position for SIM_SDID_PINID. /
Kojto	90:cb3d968589d8	1642	#define BM_SIM_SDID_PINID (0x0000000FU) /!< Bit mask for SIM_SDID_PINID. /
Kojto	90:cb3d968589d8	1643	#define BS_SIM_SDID_PINID (4U) /!< Bit field size in bits for SIM_SDID_PINID. /
Kojto	90:cb3d968589d8	1644
Kojto	90:cb3d968589d8	1645	/! @brief Read current value of the SIM_SDID_PINID field. /
Kojto	90:cb3d968589d8	1646	#define BR_SIM_SDID_PINID(x) (HW_SIM_SDID(x).B.PINID)
Kojto	90:cb3d968589d8	1647	/@}/
Kojto	90:cb3d968589d8	1648
Kojto	90:cb3d968589d8	1649	/*!
Kojto	90:cb3d968589d8	1650	* @name Register SIM_SDID, field FAMID[6:4] (RO)
Kojto	90:cb3d968589d8	1651	*
Kojto	90:cb3d968589d8	1652	* This field is maintained for compatibility only, but has been superceded by
Kojto	90:cb3d968589d8	1653	* the SERIESID, FAMILYID and SUBFAMID fields in this register.
Kojto	90:cb3d968589d8	1654	*
Kojto	90:cb3d968589d8	1655	* Values:
Kojto	90:cb3d968589d8	1656	* - 000 - K1x Family (without tamper)
Kojto	90:cb3d968589d8	1657	* - 001 - K2x Family (without tamper)
Kojto	90:cb3d968589d8	1658	* - 010 - K3x Family or K1x/K6x Family (with tamper)
Kojto	90:cb3d968589d8	1659	* - 011 - K4x Family or K2x Family (with tamper)
Kojto	90:cb3d968589d8	1660	* - 100 - K6x Family (without tamper)
Kojto	90:cb3d968589d8	1661	* - 101 - K7x Family
Kojto	90:cb3d968589d8	1662	* - 110 - Reserved
Kojto	90:cb3d968589d8	1663	* - 111 - Reserved
Kojto	90:cb3d968589d8	1664	*/
Kojto	90:cb3d968589d8	1665	/@{/
Kojto	90:cb3d968589d8	1666	#define BP_SIM_SDID_FAMID (4U) /!< Bit position for SIM_SDID_FAMID. /
Kojto	90:cb3d968589d8	1667	#define BM_SIM_SDID_FAMID (0x00000070U) /!< Bit mask for SIM_SDID_FAMID. /
Kojto	90:cb3d968589d8	1668	#define BS_SIM_SDID_FAMID (3U) /!< Bit field size in bits for SIM_SDID_FAMID. /
Kojto	90:cb3d968589d8	1669
Kojto	90:cb3d968589d8	1670	/! @brief Read current value of the SIM_SDID_FAMID field. /
Kojto	90:cb3d968589d8	1671	#define BR_SIM_SDID_FAMID(x) (HW_SIM_SDID(x).B.FAMID)
Kojto	90:cb3d968589d8	1672	/@}/
Kojto	90:cb3d968589d8	1673
Kojto	90:cb3d968589d8	1674	/*!
Kojto	90:cb3d968589d8	1675	* @name Register SIM_SDID, field DIEID[11:7] (RO)
Kojto	90:cb3d968589d8	1676	*
Kojto	90:cb3d968589d8	1677	* Specifies the silicon feature set identication number for the device.
Kojto	90:cb3d968589d8	1678	*/
Kojto	90:cb3d968589d8	1679	/@{/
Kojto	90:cb3d968589d8	1680	#define BP_SIM_SDID_DIEID (7U) /!< Bit position for SIM_SDID_DIEID. /
Kojto	90:cb3d968589d8	1681	#define BM_SIM_SDID_DIEID (0x00000F80U) /!< Bit mask for SIM_SDID_DIEID. /
Kojto	90:cb3d968589d8	1682	#define BS_SIM_SDID_DIEID (5U) /!< Bit field size in bits for SIM_SDID_DIEID. /
Kojto	90:cb3d968589d8	1683
Kojto	90:cb3d968589d8	1684	/! @brief Read current value of the SIM_SDID_DIEID field. /
Kojto	90:cb3d968589d8	1685	#define BR_SIM_SDID_DIEID(x) (HW_SIM_SDID(x).B.DIEID)
Kojto	90:cb3d968589d8	1686	/@}/
Kojto	90:cb3d968589d8	1687
Kojto	90:cb3d968589d8	1688	/*!
Kojto	90:cb3d968589d8	1689	* @name Register SIM_SDID, field REVID[15:12] (RO)
Kojto	90:cb3d968589d8	1690	*
Kojto	90:cb3d968589d8	1691	* Specifies the silicon implementation number for the device.
Kojto	90:cb3d968589d8	1692	*/
Kojto	90:cb3d968589d8	1693	/@{/
Kojto	90:cb3d968589d8	1694	#define BP_SIM_SDID_REVID (12U) /!< Bit position for SIM_SDID_REVID. /
Kojto	90:cb3d968589d8	1695	#define BM_SIM_SDID_REVID (0x0000F000U) /!< Bit mask for SIM_SDID_REVID. /
Kojto	90:cb3d968589d8	1696	#define BS_SIM_SDID_REVID (4U) /!< Bit field size in bits for SIM_SDID_REVID. /
Kojto	90:cb3d968589d8	1697
Kojto	90:cb3d968589d8	1698	/! @brief Read current value of the SIM_SDID_REVID field. /
Kojto	90:cb3d968589d8	1699	#define BR_SIM_SDID_REVID(x) (HW_SIM_SDID(x).B.REVID)
Kojto	90:cb3d968589d8	1700	/@}/
Kojto	90:cb3d968589d8	1701
Kojto	90:cb3d968589d8	1702	/*!
Kojto	90:cb3d968589d8	1703	* @name Register SIM_SDID, field SERIESID[23:20] (RO)
Kojto	90:cb3d968589d8	1704	*
Kojto	90:cb3d968589d8	1705	* Specifies the Kinetis series of the device.
Kojto	90:cb3d968589d8	1706	*
Kojto	90:cb3d968589d8	1707	* Values:
Kojto	90:cb3d968589d8	1708	* - 0000 - Kinetis K series
Kojto	90:cb3d968589d8	1709	* - 0001 - Kinetis L series
Kojto	90:cb3d968589d8	1710	* - 0101 - Kinetis W series
Kojto	90:cb3d968589d8	1711	* - 0110 - Kinetis V series
Kojto	90:cb3d968589d8	1712	*/
Kojto	90:cb3d968589d8	1713	/@{/
Kojto	90:cb3d968589d8	1714	#define BP_SIM_SDID_SERIESID (20U) /!< Bit position for SIM_SDID_SERIESID. /
Kojto	90:cb3d968589d8	1715	#define BM_SIM_SDID_SERIESID (0x00F00000U) /!< Bit mask for SIM_SDID_SERIESID. /
Kojto	90:cb3d968589d8	1716	#define BS_SIM_SDID_SERIESID (4U) /!< Bit field size in bits for SIM_SDID_SERIESID. /
Kojto	90:cb3d968589d8	1717
Kojto	90:cb3d968589d8	1718	/! @brief Read current value of the SIM_SDID_SERIESID field. /
Kojto	90:cb3d968589d8	1719	#define BR_SIM_SDID_SERIESID(x) (HW_SIM_SDID(x).B.SERIESID)
Kojto	90:cb3d968589d8	1720	/@}/
Kojto	90:cb3d968589d8	1721
Kojto	90:cb3d968589d8	1722	/*!
Kojto	90:cb3d968589d8	1723	* @name Register SIM_SDID, field SUBFAMID[27:24] (RO)
Kojto	90:cb3d968589d8	1724	*
Kojto	90:cb3d968589d8	1725	* Specifies the Kinetis sub-family of the device.
Kojto	90:cb3d968589d8	1726	*
Kojto	90:cb3d968589d8	1727	* Values:
Kojto	90:cb3d968589d8	1728	* - 0000 - Kx0 Subfamily
Kojto	90:cb3d968589d8	1729	* - 0001 - Kx1 Subfamily (tamper detect)
Kojto	90:cb3d968589d8	1730	* - 0010 - Kx2 Subfamily
Kojto	90:cb3d968589d8	1731	* - 0011 - Kx3 Subfamily (tamper detect)
Kojto	90:cb3d968589d8	1732	* - 0100 - Kx4 Subfamily
Kojto	90:cb3d968589d8	1733	* - 0101 - Kx5 Subfamily (tamper detect)
Kojto	90:cb3d968589d8	1734	* - 0110 - Kx6 Subfamily
Kojto	90:cb3d968589d8	1735	*/
Kojto	90:cb3d968589d8	1736	/@{/
Kojto	90:cb3d968589d8	1737	#define BP_SIM_SDID_SUBFAMID (24U) /!< Bit position for SIM_SDID_SUBFAMID. /
Kojto	90:cb3d968589d8	1738	#define BM_SIM_SDID_SUBFAMID (0x0F000000U) /!< Bit mask for SIM_SDID_SUBFAMID. /
Kojto	90:cb3d968589d8	1739	#define BS_SIM_SDID_SUBFAMID (4U) /!< Bit field size in bits for SIM_SDID_SUBFAMID. /
Kojto	90:cb3d968589d8	1740
Kojto	90:cb3d968589d8	1741	/! @brief Read current value of the SIM_SDID_SUBFAMID field. /
Kojto	90:cb3d968589d8	1742	#define BR_SIM_SDID_SUBFAMID(x) (HW_SIM_SDID(x).B.SUBFAMID)
Kojto	90:cb3d968589d8	1743	/@}/
Kojto	90:cb3d968589d8	1744
Kojto	90:cb3d968589d8	1745	/*!
Kojto	90:cb3d968589d8	1746	* @name Register SIM_SDID, field FAMILYID[31:28] (RO)
Kojto	90:cb3d968589d8	1747	*
Kojto	90:cb3d968589d8	1748	* Specifies the Kinetis family of the device.
Kojto	90:cb3d968589d8	1749	*
Kojto	90:cb3d968589d8	1750	* Values:
Kojto	90:cb3d968589d8	1751	* - 0001 - K1x Family
Kojto	90:cb3d968589d8	1752	* - 0010 - K2x Family
Kojto	90:cb3d968589d8	1753	* - 0011 - K3x Family
Kojto	90:cb3d968589d8	1754	* - 0100 - K4x Family
Kojto	90:cb3d968589d8	1755	* - 0110 - K6x Family
Kojto	90:cb3d968589d8	1756	* - 0111 - K7x Family
Kojto	90:cb3d968589d8	1757	*/
Kojto	90:cb3d968589d8	1758	/@{/
Kojto	90:cb3d968589d8	1759	#define BP_SIM_SDID_FAMILYID (28U) /!< Bit position for SIM_SDID_FAMILYID. /
Kojto	90:cb3d968589d8	1760	#define BM_SIM_SDID_FAMILYID (0xF0000000U) /!< Bit mask for SIM_SDID_FAMILYID. /
Kojto	90:cb3d968589d8	1761	#define BS_SIM_SDID_FAMILYID (4U) /!< Bit field size in bits for SIM_SDID_FAMILYID. /
Kojto	90:cb3d968589d8	1762
Kojto	90:cb3d968589d8	1763	/! @brief Read current value of the SIM_SDID_FAMILYID field. /
Kojto	90:cb3d968589d8	1764	#define BR_SIM_SDID_FAMILYID(x) (HW_SIM_SDID(x).B.FAMILYID)
Kojto	90:cb3d968589d8	1765	/@}/
Kojto	90:cb3d968589d8	1766
Kojto	90:cb3d968589d8	1767	/*******************************************************************************
Kojto	90:cb3d968589d8	1768	* HW_SIM_SCGC1 - System Clock Gating Control Register 1
Kojto	90:cb3d968589d8	1769	******************************************************************************/
Kojto	90:cb3d968589d8	1770
Kojto	90:cb3d968589d8	1771	/*!
Kojto	90:cb3d968589d8	1772	* @brief HW_SIM_SCGC1 - System Clock Gating Control Register 1 (RW)
Kojto	90:cb3d968589d8	1773	*
Kojto	90:cb3d968589d8	1774	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1775	*/
Kojto	90:cb3d968589d8	1776	typedef union _hw_sim_scgc1
Kojto	90:cb3d968589d8	1777	{
Kojto	90:cb3d968589d8	1778	uint32_t U;
Kojto	90:cb3d968589d8	1779	struct _hw_sim_scgc1_bitfields
Kojto	90:cb3d968589d8	1780	{
Kojto	90:cb3d968589d8	1781	uint32_t RESERVED0 : 6; /!< [5:0] /
Kojto	90:cb3d968589d8	1782	uint32_t I2C2b : 1; /!< [6] I2C2 Clock Gate Control /
Kojto	90:cb3d968589d8	1783	uint32_t RESERVED1 : 3; /!< [9:7] /
Kojto	90:cb3d968589d8	1784	uint32_t UART4b : 1; /!< [10] UART4 Clock Gate Control /
Kojto	90:cb3d968589d8	1785	uint32_t UART5b : 1; /!< [11] UART5 Clock Gate Control /
Kojto	90:cb3d968589d8	1786	uint32_t RESERVED2 : 20; /!< [31:12] /
Kojto	90:cb3d968589d8	1787	} B;
Kojto	90:cb3d968589d8	1788	} hw_sim_scgc1_t;
Kojto	90:cb3d968589d8	1789
Kojto	90:cb3d968589d8	1790	/*!
Kojto	90:cb3d968589d8	1791	* @name Constants and macros for entire SIM_SCGC1 register
Kojto	90:cb3d968589d8	1792	*/
Kojto	90:cb3d968589d8	1793	/@{/
Kojto	90:cb3d968589d8	1794	#define HW_SIM_SCGC1_ADDR(x) ((x) + 0x1028U)
Kojto	90:cb3d968589d8	1795
Kojto	90:cb3d968589d8	1796	#define HW_SIM_SCGC1(x) ((__IO hw_sim_scgc1_t ) HW_SIM_SCGC1_ADDR(x))
Kojto	90:cb3d968589d8	1797	#define HW_SIM_SCGC1_RD(x) (HW_SIM_SCGC1(x).U)
Kojto	90:cb3d968589d8	1798	#define HW_SIM_SCGC1_WR(x, v) (HW_SIM_SCGC1(x).U = (v))
Kojto	90:cb3d968589d8	1799	#define HW_SIM_SCGC1_SET(x, v) (HW_SIM_SCGC1_WR(x, HW_SIM_SCGC1_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1800	#define HW_SIM_SCGC1_CLR(x, v) (HW_SIM_SCGC1_WR(x, HW_SIM_SCGC1_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1801	#define HW_SIM_SCGC1_TOG(x, v) (HW_SIM_SCGC1_WR(x, HW_SIM_SCGC1_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1802	/@}/
Kojto	90:cb3d968589d8	1803
Kojto	90:cb3d968589d8	1804	/*
Kojto	90:cb3d968589d8	1805	* Constants & macros for individual SIM_SCGC1 bitfields
Kojto	90:cb3d968589d8	1806	*/
Kojto	90:cb3d968589d8	1807
Kojto	90:cb3d968589d8	1808	/*!
Kojto	90:cb3d968589d8	1809	* @name Register SIM_SCGC1, field I2C2[6] (RW)
Kojto	90:cb3d968589d8	1810	*
Kojto	90:cb3d968589d8	1811	* This bit controls the clock gate to the I2C2 module.
Kojto	90:cb3d968589d8	1812	*
Kojto	90:cb3d968589d8	1813	* Values:
Kojto	90:cb3d968589d8	1814	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	1815	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	1816	*/
Kojto	90:cb3d968589d8	1817	/@{/
Kojto	90:cb3d968589d8	1818	#define BP_SIM_SCGC1_I2C2 (6U) /!< Bit position for SIM_SCGC1_I2C2. /
Kojto	90:cb3d968589d8	1819	#define BM_SIM_SCGC1_I2C2 (0x00000040U) /!< Bit mask for SIM_SCGC1_I2C2. /
Kojto	90:cb3d968589d8	1820	#define BS_SIM_SCGC1_I2C2 (1U) /!< Bit field size in bits for SIM_SCGC1_I2C2. /
Kojto	90:cb3d968589d8	1821
Kojto	90:cb3d968589d8	1822	/! @brief Read current value of the SIM_SCGC1_I2C2 field. /
Kojto	90:cb3d968589d8	1823	#define BR_SIM_SCGC1_I2C2(x) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_I2C2))
Kojto	90:cb3d968589d8	1824
Kojto	90:cb3d968589d8	1825	/! @brief Format value for bitfield SIM_SCGC1_I2C2. /
Kojto	90:cb3d968589d8	1826	#define BF_SIM_SCGC1_I2C2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC1_I2C2) & BM_SIM_SCGC1_I2C2)
Kojto	90:cb3d968589d8	1827
Kojto	90:cb3d968589d8	1828	/! @brief Set the I2C2 field to a new value. /
Kojto	90:cb3d968589d8	1829	#define BW_SIM_SCGC1_I2C2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_I2C2) = (v))
Kojto	90:cb3d968589d8	1830	/@}/
Kojto	90:cb3d968589d8	1831
Kojto	90:cb3d968589d8	1832	/*!
Kojto	90:cb3d968589d8	1833	* @name Register SIM_SCGC1, field UART4[10] (RW)
Kojto	90:cb3d968589d8	1834	*
Kojto	90:cb3d968589d8	1835	* This bit controls the clock gate to the UART4 module.
Kojto	90:cb3d968589d8	1836	*
Kojto	90:cb3d968589d8	1837	* Values:
Kojto	90:cb3d968589d8	1838	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	1839	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	1840	*/
Kojto	90:cb3d968589d8	1841	/@{/
Kojto	90:cb3d968589d8	1842	#define BP_SIM_SCGC1_UART4 (10U) /!< Bit position for SIM_SCGC1_UART4. /
Kojto	90:cb3d968589d8	1843	#define BM_SIM_SCGC1_UART4 (0x00000400U) /!< Bit mask for SIM_SCGC1_UART4. /
Kojto	90:cb3d968589d8	1844	#define BS_SIM_SCGC1_UART4 (1U) /!< Bit field size in bits for SIM_SCGC1_UART4. /
Kojto	90:cb3d968589d8	1845
Kojto	90:cb3d968589d8	1846	/! @brief Read current value of the SIM_SCGC1_UART4 field. /
Kojto	90:cb3d968589d8	1847	#define BR_SIM_SCGC1_UART4(x) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART4))
Kojto	90:cb3d968589d8	1848
Kojto	90:cb3d968589d8	1849	/! @brief Format value for bitfield SIM_SCGC1_UART4. /
Kojto	90:cb3d968589d8	1850	#define BF_SIM_SCGC1_UART4(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC1_UART4) & BM_SIM_SCGC1_UART4)
Kojto	90:cb3d968589d8	1851
Kojto	90:cb3d968589d8	1852	/! @brief Set the UART4 field to a new value. /
Kojto	90:cb3d968589d8	1853	#define BW_SIM_SCGC1_UART4(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART4) = (v))
Kojto	90:cb3d968589d8	1854	/@}/
Kojto	90:cb3d968589d8	1855
Kojto	90:cb3d968589d8	1856	/*!
Kojto	90:cb3d968589d8	1857	* @name Register SIM_SCGC1, field UART5[11] (RW)
Kojto	90:cb3d968589d8	1858	*
Kojto	90:cb3d968589d8	1859	* This bit controls the clock gate to the UART5 module.
Kojto	90:cb3d968589d8	1860	*
Kojto	90:cb3d968589d8	1861	* Values:
Kojto	90:cb3d968589d8	1862	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	1863	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	1864	*/
Kojto	90:cb3d968589d8	1865	/@{/
Kojto	90:cb3d968589d8	1866	#define BP_SIM_SCGC1_UART5 (11U) /!< Bit position for SIM_SCGC1_UART5. /
Kojto	90:cb3d968589d8	1867	#define BM_SIM_SCGC1_UART5 (0x00000800U) /!< Bit mask for SIM_SCGC1_UART5. /
Kojto	90:cb3d968589d8	1868	#define BS_SIM_SCGC1_UART5 (1U) /!< Bit field size in bits for SIM_SCGC1_UART5. /
Kojto	90:cb3d968589d8	1869
Kojto	90:cb3d968589d8	1870	/! @brief Read current value of the SIM_SCGC1_UART5 field. /
Kojto	90:cb3d968589d8	1871	#define BR_SIM_SCGC1_UART5(x) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART5))
Kojto	90:cb3d968589d8	1872
Kojto	90:cb3d968589d8	1873	/! @brief Format value for bitfield SIM_SCGC1_UART5. /
Kojto	90:cb3d968589d8	1874	#define BF_SIM_SCGC1_UART5(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC1_UART5) & BM_SIM_SCGC1_UART5)
Kojto	90:cb3d968589d8	1875
Kojto	90:cb3d968589d8	1876	/! @brief Set the UART5 field to a new value. /
Kojto	90:cb3d968589d8	1877	#define BW_SIM_SCGC1_UART5(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART5) = (v))
Kojto	90:cb3d968589d8	1878	/@}/
Kojto	90:cb3d968589d8	1879
Kojto	90:cb3d968589d8	1880	/*******************************************************************************
Kojto	90:cb3d968589d8	1881	* HW_SIM_SCGC2 - System Clock Gating Control Register 2
Kojto	90:cb3d968589d8	1882	******************************************************************************/
Kojto	90:cb3d968589d8	1883
Kojto	90:cb3d968589d8	1884	/*!
Kojto	90:cb3d968589d8	1885	* @brief HW_SIM_SCGC2 - System Clock Gating Control Register 2 (RW)
Kojto	90:cb3d968589d8	1886	*
Kojto	90:cb3d968589d8	1887	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1888	*
Kojto	90:cb3d968589d8	1889	* DAC0 can be accessed through both AIPS0 and AIPS1. When accessing through
Kojto	90:cb3d968589d8	1890	* AIPS1, define the clock gate control bits in the SCGC2. When accessing through
Kojto	90:cb3d968589d8	1891	* AIPS0, define the clock gate control bits in SCGC6.
Kojto	90:cb3d968589d8	1892	*/
Kojto	90:cb3d968589d8	1893	typedef union _hw_sim_scgc2
Kojto	90:cb3d968589d8	1894	{
Kojto	90:cb3d968589d8	1895	uint32_t U;
Kojto	90:cb3d968589d8	1896	struct _hw_sim_scgc2_bitfields
Kojto	90:cb3d968589d8	1897	{
Kojto	90:cb3d968589d8	1898	uint32_t ENETb : 1; /!< [0] ENET Clock Gate Control /
Kojto	90:cb3d968589d8	1899	uint32_t RESERVED0 : 11; /!< [11:1] /
Kojto	90:cb3d968589d8	1900	uint32_t DAC0b : 1; /!< [12] DAC0 Clock Gate Control /
Kojto	90:cb3d968589d8	1901	uint32_t DAC1b : 1; /!< [13] DAC1 Clock Gate Control /
Kojto	90:cb3d968589d8	1902	uint32_t RESERVED1 : 18; /!< [31:14] /
Kojto	90:cb3d968589d8	1903	} B;
Kojto	90:cb3d968589d8	1904	} hw_sim_scgc2_t;
Kojto	90:cb3d968589d8	1905
Kojto	90:cb3d968589d8	1906	/*!
Kojto	90:cb3d968589d8	1907	* @name Constants and macros for entire SIM_SCGC2 register
Kojto	90:cb3d968589d8	1908	*/
Kojto	90:cb3d968589d8	1909	/@{/
Kojto	90:cb3d968589d8	1910	#define HW_SIM_SCGC2_ADDR(x) ((x) + 0x102CU)
Kojto	90:cb3d968589d8	1911
Kojto	90:cb3d968589d8	1912	#define HW_SIM_SCGC2(x) ((__IO hw_sim_scgc2_t ) HW_SIM_SCGC2_ADDR(x))
Kojto	90:cb3d968589d8	1913	#define HW_SIM_SCGC2_RD(x) (HW_SIM_SCGC2(x).U)
Kojto	90:cb3d968589d8	1914	#define HW_SIM_SCGC2_WR(x, v) (HW_SIM_SCGC2(x).U = (v))
Kojto	90:cb3d968589d8	1915	#define HW_SIM_SCGC2_SET(x, v) (HW_SIM_SCGC2_WR(x, HW_SIM_SCGC2_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1916	#define HW_SIM_SCGC2_CLR(x, v) (HW_SIM_SCGC2_WR(x, HW_SIM_SCGC2_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1917	#define HW_SIM_SCGC2_TOG(x, v) (HW_SIM_SCGC2_WR(x, HW_SIM_SCGC2_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1918	/@}/
Kojto	90:cb3d968589d8	1919
Kojto	90:cb3d968589d8	1920	/*
Kojto	90:cb3d968589d8	1921	* Constants & macros for individual SIM_SCGC2 bitfields
Kojto	90:cb3d968589d8	1922	*/
Kojto	90:cb3d968589d8	1923
Kojto	90:cb3d968589d8	1924	/*!
Kojto	90:cb3d968589d8	1925	* @name Register SIM_SCGC2, field ENET[0] (RW)
Kojto	90:cb3d968589d8	1926	*
Kojto	90:cb3d968589d8	1927	* This bit controls the clock gate to the ENET module.
Kojto	90:cb3d968589d8	1928	*
Kojto	90:cb3d968589d8	1929	* Values:
Kojto	90:cb3d968589d8	1930	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	1931	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	1932	*/
Kojto	90:cb3d968589d8	1933	/@{/
Kojto	90:cb3d968589d8	1934	#define BP_SIM_SCGC2_ENET (0U) /!< Bit position for SIM_SCGC2_ENET. /
Kojto	90:cb3d968589d8	1935	#define BM_SIM_SCGC2_ENET (0x00000001U) /!< Bit mask for SIM_SCGC2_ENET. /
Kojto	90:cb3d968589d8	1936	#define BS_SIM_SCGC2_ENET (1U) /!< Bit field size in bits for SIM_SCGC2_ENET. /
Kojto	90:cb3d968589d8	1937
Kojto	90:cb3d968589d8	1938	/! @brief Read current value of the SIM_SCGC2_ENET field. /
Kojto	90:cb3d968589d8	1939	#define BR_SIM_SCGC2_ENET(x) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_ENET))
Kojto	90:cb3d968589d8	1940
Kojto	90:cb3d968589d8	1941	/! @brief Format value for bitfield SIM_SCGC2_ENET. /
Kojto	90:cb3d968589d8	1942	#define BF_SIM_SCGC2_ENET(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC2_ENET) & BM_SIM_SCGC2_ENET)
Kojto	90:cb3d968589d8	1943
Kojto	90:cb3d968589d8	1944	/! @brief Set the ENET field to a new value. /
Kojto	90:cb3d968589d8	1945	#define BW_SIM_SCGC2_ENET(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_ENET) = (v))
Kojto	90:cb3d968589d8	1946	/@}/
Kojto	90:cb3d968589d8	1947
Kojto	90:cb3d968589d8	1948	/*!
Kojto	90:cb3d968589d8	1949	* @name Register SIM_SCGC2, field DAC0[12] (RW)
Kojto	90:cb3d968589d8	1950	*
Kojto	90:cb3d968589d8	1951	* This bit controls the clock gate to the DAC0 module.
Kojto	90:cb3d968589d8	1952	*
Kojto	90:cb3d968589d8	1953	* Values:
Kojto	90:cb3d968589d8	1954	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	1955	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	1956	*/
Kojto	90:cb3d968589d8	1957	/@{/
Kojto	90:cb3d968589d8	1958	#define BP_SIM_SCGC2_DAC0 (12U) /!< Bit position for SIM_SCGC2_DAC0. /
Kojto	90:cb3d968589d8	1959	#define BM_SIM_SCGC2_DAC0 (0x00001000U) /!< Bit mask for SIM_SCGC2_DAC0. /
Kojto	90:cb3d968589d8	1960	#define BS_SIM_SCGC2_DAC0 (1U) /!< Bit field size in bits for SIM_SCGC2_DAC0. /
Kojto	90:cb3d968589d8	1961
Kojto	90:cb3d968589d8	1962	/! @brief Read current value of the SIM_SCGC2_DAC0 field. /
Kojto	90:cb3d968589d8	1963	#define BR_SIM_SCGC2_DAC0(x) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC0))
Kojto	90:cb3d968589d8	1964
Kojto	90:cb3d968589d8	1965	/! @brief Format value for bitfield SIM_SCGC2_DAC0. /
Kojto	90:cb3d968589d8	1966	#define BF_SIM_SCGC2_DAC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC2_DAC0) & BM_SIM_SCGC2_DAC0)
Kojto	90:cb3d968589d8	1967
Kojto	90:cb3d968589d8	1968	/! @brief Set the DAC0 field to a new value. /
Kojto	90:cb3d968589d8	1969	#define BW_SIM_SCGC2_DAC0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC0) = (v))
Kojto	90:cb3d968589d8	1970	/@}/
Kojto	90:cb3d968589d8	1971
Kojto	90:cb3d968589d8	1972	/*!
Kojto	90:cb3d968589d8	1973	* @name Register SIM_SCGC2, field DAC1[13] (RW)
Kojto	90:cb3d968589d8	1974	*
Kojto	90:cb3d968589d8	1975	* This bit controls the clock gate to the DAC1 module.
Kojto	90:cb3d968589d8	1976	*
Kojto	90:cb3d968589d8	1977	* Values:
Kojto	90:cb3d968589d8	1978	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	1979	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	1980	*/
Kojto	90:cb3d968589d8	1981	/@{/
Kojto	90:cb3d968589d8	1982	#define BP_SIM_SCGC2_DAC1 (13U) /!< Bit position for SIM_SCGC2_DAC1. /
Kojto	90:cb3d968589d8	1983	#define BM_SIM_SCGC2_DAC1 (0x00002000U) /!< Bit mask for SIM_SCGC2_DAC1. /
Kojto	90:cb3d968589d8	1984	#define BS_SIM_SCGC2_DAC1 (1U) /!< Bit field size in bits for SIM_SCGC2_DAC1. /
Kojto	90:cb3d968589d8	1985
Kojto	90:cb3d968589d8	1986	/! @brief Read current value of the SIM_SCGC2_DAC1 field. /
Kojto	90:cb3d968589d8	1987	#define BR_SIM_SCGC2_DAC1(x) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC1))
Kojto	90:cb3d968589d8	1988
Kojto	90:cb3d968589d8	1989	/! @brief Format value for bitfield SIM_SCGC2_DAC1. /
Kojto	90:cb3d968589d8	1990	#define BF_SIM_SCGC2_DAC1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC2_DAC1) & BM_SIM_SCGC2_DAC1)
Kojto	90:cb3d968589d8	1991
Kojto	90:cb3d968589d8	1992	/! @brief Set the DAC1 field to a new value. /
Kojto	90:cb3d968589d8	1993	#define BW_SIM_SCGC2_DAC1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC1) = (v))
Kojto	90:cb3d968589d8	1994	/@}/
Kojto	90:cb3d968589d8	1995
Kojto	90:cb3d968589d8	1996	/*******************************************************************************
Kojto	90:cb3d968589d8	1997	* HW_SIM_SCGC3 - System Clock Gating Control Register 3
Kojto	90:cb3d968589d8	1998	******************************************************************************/
Kojto	90:cb3d968589d8	1999
Kojto	90:cb3d968589d8	2000	/*!
Kojto	90:cb3d968589d8	2001	* @brief HW_SIM_SCGC3 - System Clock Gating Control Register 3 (RW)
Kojto	90:cb3d968589d8	2002	*
Kojto	90:cb3d968589d8	2003	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2004	*
Kojto	90:cb3d968589d8	2005	* FTM2 and RNGA can be accessed through both AIPS0 and AIPS1. When accessing
Kojto	90:cb3d968589d8	2006	* through AIPS1, define the clock gate control bits in the SCGC3. When accessing
Kojto	90:cb3d968589d8	2007	* through AIPS0, define the clock gate control bits in SCGC6.
Kojto	90:cb3d968589d8	2008	*/
Kojto	90:cb3d968589d8	2009	typedef union _hw_sim_scgc3
Kojto	90:cb3d968589d8	2010	{
Kojto	90:cb3d968589d8	2011	uint32_t U;
Kojto	90:cb3d968589d8	2012	struct _hw_sim_scgc3_bitfields
Kojto	90:cb3d968589d8	2013	{
Kojto	90:cb3d968589d8	2014	uint32_t RNGA : 1; /!< [0] RNGA Clock Gate Control /
Kojto	90:cb3d968589d8	2015	uint32_t RESERVED0 : 11; /!< [11:1] /
Kojto	90:cb3d968589d8	2016	uint32_t SPI2b : 1; /!< [12] SPI2 Clock Gate Control /
Kojto	90:cb3d968589d8	2017	uint32_t RESERVED1 : 4; /!< [16:13] /
Kojto	90:cb3d968589d8	2018	uint32_t SDHCb : 1; /!< [17] SDHC Clock Gate Control /
Kojto	90:cb3d968589d8	2019	uint32_t RESERVED2 : 6; /!< [23:18] /
Kojto	90:cb3d968589d8	2020	uint32_t FTM2b : 1; /!< [24] FTM2 Clock Gate Control /
Kojto	90:cb3d968589d8	2021	uint32_t FTM3b : 1; /!< [25] FTM3 Clock Gate Control /
Kojto	90:cb3d968589d8	2022	uint32_t RESERVED3 : 1; /!< [26] /
Kojto	90:cb3d968589d8	2023	uint32_t ADC1b : 1; /!< [27] ADC1 Clock Gate Control /
Kojto	90:cb3d968589d8	2024	uint32_t RESERVED4 : 4; /!< [31:28] /
Kojto	90:cb3d968589d8	2025	} B;
Kojto	90:cb3d968589d8	2026	} hw_sim_scgc3_t;
Kojto	90:cb3d968589d8	2027
Kojto	90:cb3d968589d8	2028	/*!
Kojto	90:cb3d968589d8	2029	* @name Constants and macros for entire SIM_SCGC3 register
Kojto	90:cb3d968589d8	2030	*/
Kojto	90:cb3d968589d8	2031	/@{/
Kojto	90:cb3d968589d8	2032	#define HW_SIM_SCGC3_ADDR(x) ((x) + 0x1030U)
Kojto	90:cb3d968589d8	2033
Kojto	90:cb3d968589d8	2034	#define HW_SIM_SCGC3(x) ((__IO hw_sim_scgc3_t ) HW_SIM_SCGC3_ADDR(x))
Kojto	90:cb3d968589d8	2035	#define HW_SIM_SCGC3_RD(x) (HW_SIM_SCGC3(x).U)
Kojto	90:cb3d968589d8	2036	#define HW_SIM_SCGC3_WR(x, v) (HW_SIM_SCGC3(x).U = (v))
Kojto	90:cb3d968589d8	2037	#define HW_SIM_SCGC3_SET(x, v) (HW_SIM_SCGC3_WR(x, HW_SIM_SCGC3_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2038	#define HW_SIM_SCGC3_CLR(x, v) (HW_SIM_SCGC3_WR(x, HW_SIM_SCGC3_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2039	#define HW_SIM_SCGC3_TOG(x, v) (HW_SIM_SCGC3_WR(x, HW_SIM_SCGC3_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2040	/@}/
Kojto	90:cb3d968589d8	2041
Kojto	90:cb3d968589d8	2042	/*
Kojto	90:cb3d968589d8	2043	* Constants & macros for individual SIM_SCGC3 bitfields
Kojto	90:cb3d968589d8	2044	*/
Kojto	90:cb3d968589d8	2045
Kojto	90:cb3d968589d8	2046	/*!
Kojto	90:cb3d968589d8	2047	* @name Register SIM_SCGC3, field RNGA[0] (RW)
Kojto	90:cb3d968589d8	2048	*
Kojto	90:cb3d968589d8	2049	* This bit controls the clock gate to the RNGA module.
Kojto	90:cb3d968589d8	2050	*
Kojto	90:cb3d968589d8	2051	* Values:
Kojto	90:cb3d968589d8	2052	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2053	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2054	*/
Kojto	90:cb3d968589d8	2055	/@{/
Kojto	90:cb3d968589d8	2056	#define BP_SIM_SCGC3_RNGA (0U) /!< Bit position for SIM_SCGC3_RNGA. /
Kojto	90:cb3d968589d8	2057	#define BM_SIM_SCGC3_RNGA (0x00000001U) /!< Bit mask for SIM_SCGC3_RNGA. /
Kojto	90:cb3d968589d8	2058	#define BS_SIM_SCGC3_RNGA (1U) /!< Bit field size in bits for SIM_SCGC3_RNGA. /
Kojto	90:cb3d968589d8	2059
Kojto	90:cb3d968589d8	2060	/! @brief Read current value of the SIM_SCGC3_RNGA field. /
Kojto	90:cb3d968589d8	2061	#define BR_SIM_SCGC3_RNGA(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_RNGA))
Kojto	90:cb3d968589d8	2062
Kojto	90:cb3d968589d8	2063	/! @brief Format value for bitfield SIM_SCGC3_RNGA. /
Kojto	90:cb3d968589d8	2064	#define BF_SIM_SCGC3_RNGA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_RNGA) & BM_SIM_SCGC3_RNGA)
Kojto	90:cb3d968589d8	2065
Kojto	90:cb3d968589d8	2066	/! @brief Set the RNGA field to a new value. /
Kojto	90:cb3d968589d8	2067	#define BW_SIM_SCGC3_RNGA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_RNGA) = (v))
Kojto	90:cb3d968589d8	2068	/@}/
Kojto	90:cb3d968589d8	2069
Kojto	90:cb3d968589d8	2070	/*!
Kojto	90:cb3d968589d8	2071	* @name Register SIM_SCGC3, field SPI2[12] (RW)
Kojto	90:cb3d968589d8	2072	*
Kojto	90:cb3d968589d8	2073	* This bit controls the clock gate to the SPI2 module.
Kojto	90:cb3d968589d8	2074	*
Kojto	90:cb3d968589d8	2075	* Values:
Kojto	90:cb3d968589d8	2076	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2077	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2078	*/
Kojto	90:cb3d968589d8	2079	/@{/
Kojto	90:cb3d968589d8	2080	#define BP_SIM_SCGC3_SPI2 (12U) /!< Bit position for SIM_SCGC3_SPI2. /
Kojto	90:cb3d968589d8	2081	#define BM_SIM_SCGC3_SPI2 (0x00001000U) /!< Bit mask for SIM_SCGC3_SPI2. /
Kojto	90:cb3d968589d8	2082	#define BS_SIM_SCGC3_SPI2 (1U) /!< Bit field size in bits for SIM_SCGC3_SPI2. /
Kojto	90:cb3d968589d8	2083
Kojto	90:cb3d968589d8	2084	/! @brief Read current value of the SIM_SCGC3_SPI2 field. /
Kojto	90:cb3d968589d8	2085	#define BR_SIM_SCGC3_SPI2(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SPI2))
Kojto	90:cb3d968589d8	2086
Kojto	90:cb3d968589d8	2087	/! @brief Format value for bitfield SIM_SCGC3_SPI2. /
Kojto	90:cb3d968589d8	2088	#define BF_SIM_SCGC3_SPI2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_SPI2) & BM_SIM_SCGC3_SPI2)
Kojto	90:cb3d968589d8	2089
Kojto	90:cb3d968589d8	2090	/! @brief Set the SPI2 field to a new value. /
Kojto	90:cb3d968589d8	2091	#define BW_SIM_SCGC3_SPI2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SPI2) = (v))
Kojto	90:cb3d968589d8	2092	/@}/
Kojto	90:cb3d968589d8	2093
Kojto	90:cb3d968589d8	2094	/*!
Kojto	90:cb3d968589d8	2095	* @name Register SIM_SCGC3, field SDHC[17] (RW)
Kojto	90:cb3d968589d8	2096	*
Kojto	90:cb3d968589d8	2097	* This bit controls the clock gate to the SDHC module.
Kojto	90:cb3d968589d8	2098	*
Kojto	90:cb3d968589d8	2099	* Values:
Kojto	90:cb3d968589d8	2100	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2101	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2102	*/
Kojto	90:cb3d968589d8	2103	/@{/
Kojto	90:cb3d968589d8	2104	#define BP_SIM_SCGC3_SDHC (17U) /!< Bit position for SIM_SCGC3_SDHC. /
Kojto	90:cb3d968589d8	2105	#define BM_SIM_SCGC3_SDHC (0x00020000U) /!< Bit mask for SIM_SCGC3_SDHC. /
Kojto	90:cb3d968589d8	2106	#define BS_SIM_SCGC3_SDHC (1U) /!< Bit field size in bits for SIM_SCGC3_SDHC. /
Kojto	90:cb3d968589d8	2107
Kojto	90:cb3d968589d8	2108	/! @brief Read current value of the SIM_SCGC3_SDHC field. /
Kojto	90:cb3d968589d8	2109	#define BR_SIM_SCGC3_SDHC(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SDHC))
Kojto	90:cb3d968589d8	2110
Kojto	90:cb3d968589d8	2111	/! @brief Format value for bitfield SIM_SCGC3_SDHC. /
Kojto	90:cb3d968589d8	2112	#define BF_SIM_SCGC3_SDHC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_SDHC) & BM_SIM_SCGC3_SDHC)
Kojto	90:cb3d968589d8	2113
Kojto	90:cb3d968589d8	2114	/! @brief Set the SDHC field to a new value. /
Kojto	90:cb3d968589d8	2115	#define BW_SIM_SCGC3_SDHC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SDHC) = (v))
Kojto	90:cb3d968589d8	2116	/@}/
Kojto	90:cb3d968589d8	2117
Kojto	90:cb3d968589d8	2118	/*!
Kojto	90:cb3d968589d8	2119	* @name Register SIM_SCGC3, field FTM2[24] (RW)
Kojto	90:cb3d968589d8	2120	*
Kojto	90:cb3d968589d8	2121	* This bit controls the clock gate to the FTM2 module.
Kojto	90:cb3d968589d8	2122	*
Kojto	90:cb3d968589d8	2123	* Values:
Kojto	90:cb3d968589d8	2124	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2125	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2126	*/
Kojto	90:cb3d968589d8	2127	/@{/
Kojto	90:cb3d968589d8	2128	#define BP_SIM_SCGC3_FTM2 (24U) /!< Bit position for SIM_SCGC3_FTM2. /
Kojto	90:cb3d968589d8	2129	#define BM_SIM_SCGC3_FTM2 (0x01000000U) /!< Bit mask for SIM_SCGC3_FTM2. /
Kojto	90:cb3d968589d8	2130	#define BS_SIM_SCGC3_FTM2 (1U) /!< Bit field size in bits for SIM_SCGC3_FTM2. /
Kojto	90:cb3d968589d8	2131
Kojto	90:cb3d968589d8	2132	/! @brief Read current value of the SIM_SCGC3_FTM2 field. /
Kojto	90:cb3d968589d8	2133	#define BR_SIM_SCGC3_FTM2(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM2))
Kojto	90:cb3d968589d8	2134
Kojto	90:cb3d968589d8	2135	/! @brief Format value for bitfield SIM_SCGC3_FTM2. /
Kojto	90:cb3d968589d8	2136	#define BF_SIM_SCGC3_FTM2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_FTM2) & BM_SIM_SCGC3_FTM2)
Kojto	90:cb3d968589d8	2137
Kojto	90:cb3d968589d8	2138	/! @brief Set the FTM2 field to a new value. /
Kojto	90:cb3d968589d8	2139	#define BW_SIM_SCGC3_FTM2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM2) = (v))
Kojto	90:cb3d968589d8	2140	/@}/
Kojto	90:cb3d968589d8	2141
Kojto	90:cb3d968589d8	2142	/*!
Kojto	90:cb3d968589d8	2143	* @name Register SIM_SCGC3, field FTM3[25] (RW)
Kojto	90:cb3d968589d8	2144	*
Kojto	90:cb3d968589d8	2145	* This bit controls the clock gate to the FTM3 module.
Kojto	90:cb3d968589d8	2146	*
Kojto	90:cb3d968589d8	2147	* Values:
Kojto	90:cb3d968589d8	2148	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2149	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2150	*/
Kojto	90:cb3d968589d8	2151	/@{/
Kojto	90:cb3d968589d8	2152	#define BP_SIM_SCGC3_FTM3 (25U) /!< Bit position for SIM_SCGC3_FTM3. /
Kojto	90:cb3d968589d8	2153	#define BM_SIM_SCGC3_FTM3 (0x02000000U) /!< Bit mask for SIM_SCGC3_FTM3. /
Kojto	90:cb3d968589d8	2154	#define BS_SIM_SCGC3_FTM3 (1U) /!< Bit field size in bits for SIM_SCGC3_FTM3. /
Kojto	90:cb3d968589d8	2155
Kojto	90:cb3d968589d8	2156	/! @brief Read current value of the SIM_SCGC3_FTM3 field. /
Kojto	90:cb3d968589d8	2157	#define BR_SIM_SCGC3_FTM3(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM3))
Kojto	90:cb3d968589d8	2158
Kojto	90:cb3d968589d8	2159	/! @brief Format value for bitfield SIM_SCGC3_FTM3. /
Kojto	90:cb3d968589d8	2160	#define BF_SIM_SCGC3_FTM3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_FTM3) & BM_SIM_SCGC3_FTM3)
Kojto	90:cb3d968589d8	2161
Kojto	90:cb3d968589d8	2162	/! @brief Set the FTM3 field to a new value. /
Kojto	90:cb3d968589d8	2163	#define BW_SIM_SCGC3_FTM3(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM3) = (v))
Kojto	90:cb3d968589d8	2164	/@}/
Kojto	90:cb3d968589d8	2165
Kojto	90:cb3d968589d8	2166	/*!
Kojto	90:cb3d968589d8	2167	* @name Register SIM_SCGC3, field ADC1[27] (RW)
Kojto	90:cb3d968589d8	2168	*
Kojto	90:cb3d968589d8	2169	* This bit controls the clock gate to the ADC1 module.
Kojto	90:cb3d968589d8	2170	*
Kojto	90:cb3d968589d8	2171	* Values:
Kojto	90:cb3d968589d8	2172	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2173	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2174	*/
Kojto	90:cb3d968589d8	2175	/@{/
Kojto	90:cb3d968589d8	2176	#define BP_SIM_SCGC3_ADC1 (27U) /!< Bit position for SIM_SCGC3_ADC1. /
Kojto	90:cb3d968589d8	2177	#define BM_SIM_SCGC3_ADC1 (0x08000000U) /!< Bit mask for SIM_SCGC3_ADC1. /
Kojto	90:cb3d968589d8	2178	#define BS_SIM_SCGC3_ADC1 (1U) /!< Bit field size in bits for SIM_SCGC3_ADC1. /
Kojto	90:cb3d968589d8	2179
Kojto	90:cb3d968589d8	2180	/! @brief Read current value of the SIM_SCGC3_ADC1 field. /
Kojto	90:cb3d968589d8	2181	#define BR_SIM_SCGC3_ADC1(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_ADC1))
Kojto	90:cb3d968589d8	2182
Kojto	90:cb3d968589d8	2183	/! @brief Format value for bitfield SIM_SCGC3_ADC1. /
Kojto	90:cb3d968589d8	2184	#define BF_SIM_SCGC3_ADC1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_ADC1) & BM_SIM_SCGC3_ADC1)
Kojto	90:cb3d968589d8	2185
Kojto	90:cb3d968589d8	2186	/! @brief Set the ADC1 field to a new value. /
Kojto	90:cb3d968589d8	2187	#define BW_SIM_SCGC3_ADC1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_ADC1) = (v))
Kojto	90:cb3d968589d8	2188	/@}/
Kojto	90:cb3d968589d8	2189
Kojto	90:cb3d968589d8	2190	/*******************************************************************************
Kojto	90:cb3d968589d8	2191	* HW_SIM_SCGC4 - System Clock Gating Control Register 4
Kojto	90:cb3d968589d8	2192	******************************************************************************/
Kojto	90:cb3d968589d8	2193
Kojto	90:cb3d968589d8	2194	/*!
Kojto	90:cb3d968589d8	2195	* @brief HW_SIM_SCGC4 - System Clock Gating Control Register 4 (RW)
Kojto	90:cb3d968589d8	2196	*
Kojto	90:cb3d968589d8	2197	* Reset value: 0xF0100030U
Kojto	90:cb3d968589d8	2198	*/
Kojto	90:cb3d968589d8	2199	typedef union _hw_sim_scgc4
Kojto	90:cb3d968589d8	2200	{
Kojto	90:cb3d968589d8	2201	uint32_t U;
Kojto	90:cb3d968589d8	2202	struct _hw_sim_scgc4_bitfields
Kojto	90:cb3d968589d8	2203	{
Kojto	90:cb3d968589d8	2204	uint32_t RESERVED0 : 1; /!< [0] /
Kojto	90:cb3d968589d8	2205	uint32_t EWMb : 1; /!< [1] EWM Clock Gate Control /
Kojto	90:cb3d968589d8	2206	uint32_t CMTb : 1; /!< [2] CMT Clock Gate Control /
Kojto	90:cb3d968589d8	2207	uint32_t RESERVED1 : 3; /!< [5:3] /
Kojto	90:cb3d968589d8	2208	uint32_t I2C0b : 1; /!< [6] I2C0 Clock Gate Control /
Kojto	90:cb3d968589d8	2209	uint32_t I2C1b : 1; /!< [7] I2C1 Clock Gate Control /
Kojto	90:cb3d968589d8	2210	uint32_t RESERVED2 : 2; /!< [9:8] /
Kojto	90:cb3d968589d8	2211	uint32_t UART0b : 1; /!< [10] UART0 Clock Gate Control /
Kojto	90:cb3d968589d8	2212	uint32_t UART1b : 1; /!< [11] UART1 Clock Gate Control /
Kojto	90:cb3d968589d8	2213	uint32_t UART2b : 1; /!< [12] UART2 Clock Gate Control /
Kojto	90:cb3d968589d8	2214	uint32_t UART3b : 1; /!< [13] UART3 Clock Gate Control /
Kojto	90:cb3d968589d8	2215	uint32_t RESERVED3 : 4; /!< [17:14] /
Kojto	90:cb3d968589d8	2216	uint32_t USBOTG : 1; /!< [18] USB Clock Gate Control /
Kojto	90:cb3d968589d8	2217	uint32_t CMP : 1; /!< [19] Comparator Clock Gate Control /
Kojto	90:cb3d968589d8	2218	uint32_t VREFb : 1; /!< [20] VREF Clock Gate Control /
Kojto	90:cb3d968589d8	2219	uint32_t RESERVED4 : 11; /!< [31:21] /
Kojto	90:cb3d968589d8	2220	} B;
Kojto	90:cb3d968589d8	2221	} hw_sim_scgc4_t;
Kojto	90:cb3d968589d8	2222
Kojto	90:cb3d968589d8	2223	/*!
Kojto	90:cb3d968589d8	2224	* @name Constants and macros for entire SIM_SCGC4 register
Kojto	90:cb3d968589d8	2225	*/
Kojto	90:cb3d968589d8	2226	/@{/
Kojto	90:cb3d968589d8	2227	#define HW_SIM_SCGC4_ADDR(x) ((x) + 0x1034U)
Kojto	90:cb3d968589d8	2228
Kojto	90:cb3d968589d8	2229	#define HW_SIM_SCGC4(x) ((__IO hw_sim_scgc4_t ) HW_SIM_SCGC4_ADDR(x))
Kojto	90:cb3d968589d8	2230	#define HW_SIM_SCGC4_RD(x) (HW_SIM_SCGC4(x).U)
Kojto	90:cb3d968589d8	2231	#define HW_SIM_SCGC4_WR(x, v) (HW_SIM_SCGC4(x).U = (v))
Kojto	90:cb3d968589d8	2232	#define HW_SIM_SCGC4_SET(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2233	#define HW_SIM_SCGC4_CLR(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2234	#define HW_SIM_SCGC4_TOG(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2235	/@}/
Kojto	90:cb3d968589d8	2236
Kojto	90:cb3d968589d8	2237	/*
Kojto	90:cb3d968589d8	2238	* Constants & macros for individual SIM_SCGC4 bitfields
Kojto	90:cb3d968589d8	2239	*/
Kojto	90:cb3d968589d8	2240
Kojto	90:cb3d968589d8	2241	/*!
Kojto	90:cb3d968589d8	2242	* @name Register SIM_SCGC4, field EWM[1] (RW)
Kojto	90:cb3d968589d8	2243	*
Kojto	90:cb3d968589d8	2244	* This bit controls the clock gate to the EWM module.
Kojto	90:cb3d968589d8	2245	*
Kojto	90:cb3d968589d8	2246	* Values:
Kojto	90:cb3d968589d8	2247	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2248	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2249	*/
Kojto	90:cb3d968589d8	2250	/@{/
Kojto	90:cb3d968589d8	2251	#define BP_SIM_SCGC4_EWM (1U) /!< Bit position for SIM_SCGC4_EWM. /
Kojto	90:cb3d968589d8	2252	#define BM_SIM_SCGC4_EWM (0x00000002U) /!< Bit mask for SIM_SCGC4_EWM. /
Kojto	90:cb3d968589d8	2253	#define BS_SIM_SCGC4_EWM (1U) /!< Bit field size in bits for SIM_SCGC4_EWM. /
Kojto	90:cb3d968589d8	2254
Kojto	90:cb3d968589d8	2255	/! @brief Read current value of the SIM_SCGC4_EWM field. /
Kojto	90:cb3d968589d8	2256	#define BR_SIM_SCGC4_EWM(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_EWM))
Kojto	90:cb3d968589d8	2257
Kojto	90:cb3d968589d8	2258	/! @brief Format value for bitfield SIM_SCGC4_EWM. /
Kojto	90:cb3d968589d8	2259	#define BF_SIM_SCGC4_EWM(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_EWM) & BM_SIM_SCGC4_EWM)
Kojto	90:cb3d968589d8	2260
Kojto	90:cb3d968589d8	2261	/! @brief Set the EWM field to a new value. /
Kojto	90:cb3d968589d8	2262	#define BW_SIM_SCGC4_EWM(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_EWM) = (v))
Kojto	90:cb3d968589d8	2263	/@}/
Kojto	90:cb3d968589d8	2264
Kojto	90:cb3d968589d8	2265	/*!
Kojto	90:cb3d968589d8	2266	* @name Register SIM_SCGC4, field CMT[2] (RW)
Kojto	90:cb3d968589d8	2267	*
Kojto	90:cb3d968589d8	2268	* This bit controls the clock gate to the CMT module.
Kojto	90:cb3d968589d8	2269	*
Kojto	90:cb3d968589d8	2270	* Values:
Kojto	90:cb3d968589d8	2271	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2272	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2273	*/
Kojto	90:cb3d968589d8	2274	/@{/
Kojto	90:cb3d968589d8	2275	#define BP_SIM_SCGC4_CMT (2U) /!< Bit position for SIM_SCGC4_CMT. /
Kojto	90:cb3d968589d8	2276	#define BM_SIM_SCGC4_CMT (0x00000004U) /!< Bit mask for SIM_SCGC4_CMT. /
Kojto	90:cb3d968589d8	2277	#define BS_SIM_SCGC4_CMT (1U) /!< Bit field size in bits for SIM_SCGC4_CMT. /
Kojto	90:cb3d968589d8	2278
Kojto	90:cb3d968589d8	2279	/! @brief Read current value of the SIM_SCGC4_CMT field. /
Kojto	90:cb3d968589d8	2280	#define BR_SIM_SCGC4_CMT(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMT))
Kojto	90:cb3d968589d8	2281
Kojto	90:cb3d968589d8	2282	/! @brief Format value for bitfield SIM_SCGC4_CMT. /
Kojto	90:cb3d968589d8	2283	#define BF_SIM_SCGC4_CMT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_CMT) & BM_SIM_SCGC4_CMT)
Kojto	90:cb3d968589d8	2284
Kojto	90:cb3d968589d8	2285	/! @brief Set the CMT field to a new value. /
Kojto	90:cb3d968589d8	2286	#define BW_SIM_SCGC4_CMT(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMT) = (v))
Kojto	90:cb3d968589d8	2287	/@}/
Kojto	90:cb3d968589d8	2288
Kojto	90:cb3d968589d8	2289	/*!
Kojto	90:cb3d968589d8	2290	* @name Register SIM_SCGC4, field I2C0[6] (RW)
Kojto	90:cb3d968589d8	2291	*
Kojto	90:cb3d968589d8	2292	* This bit controls the clock gate to the I 2 C0 module.
Kojto	90:cb3d968589d8	2293	*
Kojto	90:cb3d968589d8	2294	* Values:
Kojto	90:cb3d968589d8	2295	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2296	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2297	*/
Kojto	90:cb3d968589d8	2298	/@{/
Kojto	90:cb3d968589d8	2299	#define BP_SIM_SCGC4_I2C0 (6U) /!< Bit position for SIM_SCGC4_I2C0. /
Kojto	90:cb3d968589d8	2300	#define BM_SIM_SCGC4_I2C0 (0x00000040U) /!< Bit mask for SIM_SCGC4_I2C0. /
Kojto	90:cb3d968589d8	2301	#define BS_SIM_SCGC4_I2C0 (1U) /!< Bit field size in bits for SIM_SCGC4_I2C0. /
Kojto	90:cb3d968589d8	2302
Kojto	90:cb3d968589d8	2303	/! @brief Read current value of the SIM_SCGC4_I2C0 field. /
Kojto	90:cb3d968589d8	2304	#define BR_SIM_SCGC4_I2C0(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C0))
Kojto	90:cb3d968589d8	2305
Kojto	90:cb3d968589d8	2306	/! @brief Format value for bitfield SIM_SCGC4_I2C0. /
Kojto	90:cb3d968589d8	2307	#define BF_SIM_SCGC4_I2C0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_I2C0) & BM_SIM_SCGC4_I2C0)
Kojto	90:cb3d968589d8	2308
Kojto	90:cb3d968589d8	2309	/! @brief Set the I2C0 field to a new value. /
Kojto	90:cb3d968589d8	2310	#define BW_SIM_SCGC4_I2C0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C0) = (v))
Kojto	90:cb3d968589d8	2311	/@}/
Kojto	90:cb3d968589d8	2312
Kojto	90:cb3d968589d8	2313	/*!
Kojto	90:cb3d968589d8	2314	* @name Register SIM_SCGC4, field I2C1[7] (RW)
Kojto	90:cb3d968589d8	2315	*
Kojto	90:cb3d968589d8	2316	* This bit controls the clock gate to the I 2 C1 module.
Kojto	90:cb3d968589d8	2317	*
Kojto	90:cb3d968589d8	2318	* Values:
Kojto	90:cb3d968589d8	2319	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2320	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2321	*/
Kojto	90:cb3d968589d8	2322	/@{/
Kojto	90:cb3d968589d8	2323	#define BP_SIM_SCGC4_I2C1 (7U) /!< Bit position for SIM_SCGC4_I2C1. /
Kojto	90:cb3d968589d8	2324	#define BM_SIM_SCGC4_I2C1 (0x00000080U) /!< Bit mask for SIM_SCGC4_I2C1. /
Kojto	90:cb3d968589d8	2325	#define BS_SIM_SCGC4_I2C1 (1U) /!< Bit field size in bits for SIM_SCGC4_I2C1. /
Kojto	90:cb3d968589d8	2326
Kojto	90:cb3d968589d8	2327	/! @brief Read current value of the SIM_SCGC4_I2C1 field. /
Kojto	90:cb3d968589d8	2328	#define BR_SIM_SCGC4_I2C1(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C1))
Kojto	90:cb3d968589d8	2329
Kojto	90:cb3d968589d8	2330	/! @brief Format value for bitfield SIM_SCGC4_I2C1. /
Kojto	90:cb3d968589d8	2331	#define BF_SIM_SCGC4_I2C1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_I2C1) & BM_SIM_SCGC4_I2C1)
Kojto	90:cb3d968589d8	2332
Kojto	90:cb3d968589d8	2333	/! @brief Set the I2C1 field to a new value. /
Kojto	90:cb3d968589d8	2334	#define BW_SIM_SCGC4_I2C1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C1) = (v))
Kojto	90:cb3d968589d8	2335	/@}/
Kojto	90:cb3d968589d8	2336
Kojto	90:cb3d968589d8	2337	/*!
Kojto	90:cb3d968589d8	2338	* @name Register SIM_SCGC4, field UART0[10] (RW)
Kojto	90:cb3d968589d8	2339	*
Kojto	90:cb3d968589d8	2340	* This bit controls the clock gate to the UART0 module.
Kojto	90:cb3d968589d8	2341	*
Kojto	90:cb3d968589d8	2342	* Values:
Kojto	90:cb3d968589d8	2343	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2344	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2345	*/
Kojto	90:cb3d968589d8	2346	/@{/
Kojto	90:cb3d968589d8	2347	#define BP_SIM_SCGC4_UART0 (10U) /!< Bit position for SIM_SCGC4_UART0. /
Kojto	90:cb3d968589d8	2348	#define BM_SIM_SCGC4_UART0 (0x00000400U) /!< Bit mask for SIM_SCGC4_UART0. /
Kojto	90:cb3d968589d8	2349	#define BS_SIM_SCGC4_UART0 (1U) /!< Bit field size in bits for SIM_SCGC4_UART0. /
Kojto	90:cb3d968589d8	2350
Kojto	90:cb3d968589d8	2351	/! @brief Read current value of the SIM_SCGC4_UART0 field. /
Kojto	90:cb3d968589d8	2352	#define BR_SIM_SCGC4_UART0(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART0))
Kojto	90:cb3d968589d8	2353
Kojto	90:cb3d968589d8	2354	/! @brief Format value for bitfield SIM_SCGC4_UART0. /
Kojto	90:cb3d968589d8	2355	#define BF_SIM_SCGC4_UART0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART0) & BM_SIM_SCGC4_UART0)
Kojto	90:cb3d968589d8	2356
Kojto	90:cb3d968589d8	2357	/! @brief Set the UART0 field to a new value. /
Kojto	90:cb3d968589d8	2358	#define BW_SIM_SCGC4_UART0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART0) = (v))
Kojto	90:cb3d968589d8	2359	/@}/
Kojto	90:cb3d968589d8	2360
Kojto	90:cb3d968589d8	2361	/*!
Kojto	90:cb3d968589d8	2362	* @name Register SIM_SCGC4, field UART1[11] (RW)
Kojto	90:cb3d968589d8	2363	*
Kojto	90:cb3d968589d8	2364	* This bit controls the clock gate to the UART1 module.
Kojto	90:cb3d968589d8	2365	*
Kojto	90:cb3d968589d8	2366	* Values:
Kojto	90:cb3d968589d8	2367	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2368	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2369	*/
Kojto	90:cb3d968589d8	2370	/@{/
Kojto	90:cb3d968589d8	2371	#define BP_SIM_SCGC4_UART1 (11U) /!< Bit position for SIM_SCGC4_UART1. /
Kojto	90:cb3d968589d8	2372	#define BM_SIM_SCGC4_UART1 (0x00000800U) /!< Bit mask for SIM_SCGC4_UART1. /
Kojto	90:cb3d968589d8	2373	#define BS_SIM_SCGC4_UART1 (1U) /!< Bit field size in bits for SIM_SCGC4_UART1. /
Kojto	90:cb3d968589d8	2374
Kojto	90:cb3d968589d8	2375	/! @brief Read current value of the SIM_SCGC4_UART1 field. /
Kojto	90:cb3d968589d8	2376	#define BR_SIM_SCGC4_UART1(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART1))
Kojto	90:cb3d968589d8	2377
Kojto	90:cb3d968589d8	2378	/! @brief Format value for bitfield SIM_SCGC4_UART1. /
Kojto	90:cb3d968589d8	2379	#define BF_SIM_SCGC4_UART1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART1) & BM_SIM_SCGC4_UART1)
Kojto	90:cb3d968589d8	2380
Kojto	90:cb3d968589d8	2381	/! @brief Set the UART1 field to a new value. /
Kojto	90:cb3d968589d8	2382	#define BW_SIM_SCGC4_UART1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART1) = (v))
Kojto	90:cb3d968589d8	2383	/@}/
Kojto	90:cb3d968589d8	2384
Kojto	90:cb3d968589d8	2385	/*!
Kojto	90:cb3d968589d8	2386	* @name Register SIM_SCGC4, field UART2[12] (RW)
Kojto	90:cb3d968589d8	2387	*
Kojto	90:cb3d968589d8	2388	* This bit controls the clock gate to the UART2 module.
Kojto	90:cb3d968589d8	2389	*
Kojto	90:cb3d968589d8	2390	* Values:
Kojto	90:cb3d968589d8	2391	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2392	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2393	*/
Kojto	90:cb3d968589d8	2394	/@{/
Kojto	90:cb3d968589d8	2395	#define BP_SIM_SCGC4_UART2 (12U) /!< Bit position for SIM_SCGC4_UART2. /
Kojto	90:cb3d968589d8	2396	#define BM_SIM_SCGC4_UART2 (0x00001000U) /!< Bit mask for SIM_SCGC4_UART2. /
Kojto	90:cb3d968589d8	2397	#define BS_SIM_SCGC4_UART2 (1U) /!< Bit field size in bits for SIM_SCGC4_UART2. /
Kojto	90:cb3d968589d8	2398
Kojto	90:cb3d968589d8	2399	/! @brief Read current value of the SIM_SCGC4_UART2 field. /
Kojto	90:cb3d968589d8	2400	#define BR_SIM_SCGC4_UART2(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART2))
Kojto	90:cb3d968589d8	2401
Kojto	90:cb3d968589d8	2402	/! @brief Format value for bitfield SIM_SCGC4_UART2. /
Kojto	90:cb3d968589d8	2403	#define BF_SIM_SCGC4_UART2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART2) & BM_SIM_SCGC4_UART2)
Kojto	90:cb3d968589d8	2404
Kojto	90:cb3d968589d8	2405	/! @brief Set the UART2 field to a new value. /
Kojto	90:cb3d968589d8	2406	#define BW_SIM_SCGC4_UART2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART2) = (v))
Kojto	90:cb3d968589d8	2407	/@}/
Kojto	90:cb3d968589d8	2408
Kojto	90:cb3d968589d8	2409	/*!
Kojto	90:cb3d968589d8	2410	* @name Register SIM_SCGC4, field UART3[13] (RW)
Kojto	90:cb3d968589d8	2411	*
Kojto	90:cb3d968589d8	2412	* This bit controls the clock gate to the UART3 module.
Kojto	90:cb3d968589d8	2413	*
Kojto	90:cb3d968589d8	2414	* Values:
Kojto	90:cb3d968589d8	2415	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2416	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2417	*/
Kojto	90:cb3d968589d8	2418	/@{/
Kojto	90:cb3d968589d8	2419	#define BP_SIM_SCGC4_UART3 (13U) /!< Bit position for SIM_SCGC4_UART3. /
Kojto	90:cb3d968589d8	2420	#define BM_SIM_SCGC4_UART3 (0x00002000U) /!< Bit mask for SIM_SCGC4_UART3. /
Kojto	90:cb3d968589d8	2421	#define BS_SIM_SCGC4_UART3 (1U) /!< Bit field size in bits for SIM_SCGC4_UART3. /
Kojto	90:cb3d968589d8	2422
Kojto	90:cb3d968589d8	2423	/! @brief Read current value of the SIM_SCGC4_UART3 field. /
Kojto	90:cb3d968589d8	2424	#define BR_SIM_SCGC4_UART3(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART3))
Kojto	90:cb3d968589d8	2425
Kojto	90:cb3d968589d8	2426	/! @brief Format value for bitfield SIM_SCGC4_UART3. /
Kojto	90:cb3d968589d8	2427	#define BF_SIM_SCGC4_UART3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART3) & BM_SIM_SCGC4_UART3)
Kojto	90:cb3d968589d8	2428
Kojto	90:cb3d968589d8	2429	/! @brief Set the UART3 field to a new value. /
Kojto	90:cb3d968589d8	2430	#define BW_SIM_SCGC4_UART3(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART3) = (v))
Kojto	90:cb3d968589d8	2431	/@}/
Kojto	90:cb3d968589d8	2432
Kojto	90:cb3d968589d8	2433	/*!
Kojto	90:cb3d968589d8	2434	* @name Register SIM_SCGC4, field USBOTG[18] (RW)
Kojto	90:cb3d968589d8	2435	*
Kojto	90:cb3d968589d8	2436	* This bit controls the clock gate to the USB module.
Kojto	90:cb3d968589d8	2437	*
Kojto	90:cb3d968589d8	2438	* Values:
Kojto	90:cb3d968589d8	2439	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2440	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2441	*/
Kojto	90:cb3d968589d8	2442	/@{/
Kojto	90:cb3d968589d8	2443	#define BP_SIM_SCGC4_USBOTG (18U) /!< Bit position for SIM_SCGC4_USBOTG. /
Kojto	90:cb3d968589d8	2444	#define BM_SIM_SCGC4_USBOTG (0x00040000U) /!< Bit mask for SIM_SCGC4_USBOTG. /
Kojto	90:cb3d968589d8	2445	#define BS_SIM_SCGC4_USBOTG (1U) /!< Bit field size in bits for SIM_SCGC4_USBOTG. /
Kojto	90:cb3d968589d8	2446
Kojto	90:cb3d968589d8	2447	/! @brief Read current value of the SIM_SCGC4_USBOTG field. /
Kojto	90:cb3d968589d8	2448	#define BR_SIM_SCGC4_USBOTG(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_USBOTG))
Kojto	90:cb3d968589d8	2449
Kojto	90:cb3d968589d8	2450	/! @brief Format value for bitfield SIM_SCGC4_USBOTG. /
Kojto	90:cb3d968589d8	2451	#define BF_SIM_SCGC4_USBOTG(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_USBOTG) & BM_SIM_SCGC4_USBOTG)
Kojto	90:cb3d968589d8	2452
Kojto	90:cb3d968589d8	2453	/! @brief Set the USBOTG field to a new value. /
Kojto	90:cb3d968589d8	2454	#define BW_SIM_SCGC4_USBOTG(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_USBOTG) = (v))
Kojto	90:cb3d968589d8	2455	/@}/
Kojto	90:cb3d968589d8	2456
Kojto	90:cb3d968589d8	2457	/*!
Kojto	90:cb3d968589d8	2458	* @name Register SIM_SCGC4, field CMP[19] (RW)
Kojto	90:cb3d968589d8	2459	*
Kojto	90:cb3d968589d8	2460	* This bit controls the clock gate to the comparator module.
Kojto	90:cb3d968589d8	2461	*
Kojto	90:cb3d968589d8	2462	* Values:
Kojto	90:cb3d968589d8	2463	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2464	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2465	*/
Kojto	90:cb3d968589d8	2466	/@{/
Kojto	90:cb3d968589d8	2467	#define BP_SIM_SCGC4_CMP (19U) /!< Bit position for SIM_SCGC4_CMP. /
Kojto	90:cb3d968589d8	2468	#define BM_SIM_SCGC4_CMP (0x00080000U) /!< Bit mask for SIM_SCGC4_CMP. /
Kojto	90:cb3d968589d8	2469	#define BS_SIM_SCGC4_CMP (1U) /!< Bit field size in bits for SIM_SCGC4_CMP. /
Kojto	90:cb3d968589d8	2470
Kojto	90:cb3d968589d8	2471	/! @brief Read current value of the SIM_SCGC4_CMP field. /
Kojto	90:cb3d968589d8	2472	#define BR_SIM_SCGC4_CMP(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMP))
Kojto	90:cb3d968589d8	2473
Kojto	90:cb3d968589d8	2474	/! @brief Format value for bitfield SIM_SCGC4_CMP. /
Kojto	90:cb3d968589d8	2475	#define BF_SIM_SCGC4_CMP(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_CMP) & BM_SIM_SCGC4_CMP)
Kojto	90:cb3d968589d8	2476
Kojto	90:cb3d968589d8	2477	/! @brief Set the CMP field to a new value. /
Kojto	90:cb3d968589d8	2478	#define BW_SIM_SCGC4_CMP(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMP) = (v))
Kojto	90:cb3d968589d8	2479	/@}/
Kojto	90:cb3d968589d8	2480
Kojto	90:cb3d968589d8	2481	/*!
Kojto	90:cb3d968589d8	2482	* @name Register SIM_SCGC4, field VREF[20] (RW)
Kojto	90:cb3d968589d8	2483	*
Kojto	90:cb3d968589d8	2484	* This bit controls the clock gate to the VREF module.
Kojto	90:cb3d968589d8	2485	*
Kojto	90:cb3d968589d8	2486	* Values:
Kojto	90:cb3d968589d8	2487	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2488	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2489	*/
Kojto	90:cb3d968589d8	2490	/@{/
Kojto	90:cb3d968589d8	2491	#define BP_SIM_SCGC4_VREF (20U) /!< Bit position for SIM_SCGC4_VREF. /
Kojto	90:cb3d968589d8	2492	#define BM_SIM_SCGC4_VREF (0x00100000U) /!< Bit mask for SIM_SCGC4_VREF. /
Kojto	90:cb3d968589d8	2493	#define BS_SIM_SCGC4_VREF (1U) /!< Bit field size in bits for SIM_SCGC4_VREF. /
Kojto	90:cb3d968589d8	2494
Kojto	90:cb3d968589d8	2495	/! @brief Read current value of the SIM_SCGC4_VREF field. /
Kojto	90:cb3d968589d8	2496	#define BR_SIM_SCGC4_VREF(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_VREF))
Kojto	90:cb3d968589d8	2497
Kojto	90:cb3d968589d8	2498	/! @brief Format value for bitfield SIM_SCGC4_VREF. /
Kojto	90:cb3d968589d8	2499	#define BF_SIM_SCGC4_VREF(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_VREF) & BM_SIM_SCGC4_VREF)
Kojto	90:cb3d968589d8	2500
Kojto	90:cb3d968589d8	2501	/! @brief Set the VREF field to a new value. /
Kojto	90:cb3d968589d8	2502	#define BW_SIM_SCGC4_VREF(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_VREF) = (v))
Kojto	90:cb3d968589d8	2503	/@}/
Kojto	90:cb3d968589d8	2504
Kojto	90:cb3d968589d8	2505	/*******************************************************************************
Kojto	90:cb3d968589d8	2506	* HW_SIM_SCGC5 - System Clock Gating Control Register 5
Kojto	90:cb3d968589d8	2507	******************************************************************************/
Kojto	90:cb3d968589d8	2508
Kojto	90:cb3d968589d8	2509	/*!
Kojto	90:cb3d968589d8	2510	* @brief HW_SIM_SCGC5 - System Clock Gating Control Register 5 (RW)
Kojto	90:cb3d968589d8	2511	*
Kojto	90:cb3d968589d8	2512	* Reset value: 0x00040182U
Kojto	90:cb3d968589d8	2513	*/
Kojto	90:cb3d968589d8	2514	typedef union _hw_sim_scgc5
Kojto	90:cb3d968589d8	2515	{
Kojto	90:cb3d968589d8	2516	uint32_t U;
Kojto	90:cb3d968589d8	2517	struct _hw_sim_scgc5_bitfields
Kojto	90:cb3d968589d8	2518	{
Kojto	90:cb3d968589d8	2519	uint32_t LPTMR : 1; /!< [0] Low Power Timer Access Control /
Kojto	90:cb3d968589d8	2520	uint32_t RESERVED0 : 8; /!< [8:1] /
Kojto	90:cb3d968589d8	2521	uint32_t PORTAb : 1; /!< [9] Port A Clock Gate Control /
Kojto	90:cb3d968589d8	2522	uint32_t PORTBb : 1; /!< [10] Port B Clock Gate Control /
Kojto	90:cb3d968589d8	2523	uint32_t PORTCb : 1; /!< [11] Port C Clock Gate Control /
Kojto	90:cb3d968589d8	2524	uint32_t PORTDb : 1; /!< [12] Port D Clock Gate Control /
Kojto	90:cb3d968589d8	2525	uint32_t PORTEb : 1; /!< [13] Port E Clock Gate Control /
Kojto	90:cb3d968589d8	2526	uint32_t RESERVED1 : 18; /!< [31:14] /
Kojto	90:cb3d968589d8	2527	} B;
Kojto	90:cb3d968589d8	2528	} hw_sim_scgc5_t;
Kojto	90:cb3d968589d8	2529
Kojto	90:cb3d968589d8	2530	/*!
Kojto	90:cb3d968589d8	2531	* @name Constants and macros for entire SIM_SCGC5 register
Kojto	90:cb3d968589d8	2532	*/
Kojto	90:cb3d968589d8	2533	/@{/
Kojto	90:cb3d968589d8	2534	#define HW_SIM_SCGC5_ADDR(x) ((x) + 0x1038U)
Kojto	90:cb3d968589d8	2535
Kojto	90:cb3d968589d8	2536	#define HW_SIM_SCGC5(x) ((__IO hw_sim_scgc5_t ) HW_SIM_SCGC5_ADDR(x))
Kojto	90:cb3d968589d8	2537	#define HW_SIM_SCGC5_RD(x) (HW_SIM_SCGC5(x).U)
Kojto	90:cb3d968589d8	2538	#define HW_SIM_SCGC5_WR(x, v) (HW_SIM_SCGC5(x).U = (v))
Kojto	90:cb3d968589d8	2539	#define HW_SIM_SCGC5_SET(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2540	#define HW_SIM_SCGC5_CLR(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2541	#define HW_SIM_SCGC5_TOG(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2542	/@}/
Kojto	90:cb3d968589d8	2543
Kojto	90:cb3d968589d8	2544	/*
Kojto	90:cb3d968589d8	2545	* Constants & macros for individual SIM_SCGC5 bitfields
Kojto	90:cb3d968589d8	2546	*/
Kojto	90:cb3d968589d8	2547
Kojto	90:cb3d968589d8	2548	/*!
Kojto	90:cb3d968589d8	2549	* @name Register SIM_SCGC5, field LPTMR[0] (RW)
Kojto	90:cb3d968589d8	2550	*
Kojto	90:cb3d968589d8	2551	* This bit controls software access to the Low Power Timer module.
Kojto	90:cb3d968589d8	2552	*
Kojto	90:cb3d968589d8	2553	* Values:
Kojto	90:cb3d968589d8	2554	* - 0 - Access disabled
Kojto	90:cb3d968589d8	2555	* - 1 - Access enabled
Kojto	90:cb3d968589d8	2556	*/
Kojto	90:cb3d968589d8	2557	/@{/
Kojto	90:cb3d968589d8	2558	#define BP_SIM_SCGC5_LPTMR (0U) /!< Bit position for SIM_SCGC5_LPTMR. /
Kojto	90:cb3d968589d8	2559	#define BM_SIM_SCGC5_LPTMR (0x00000001U) /!< Bit mask for SIM_SCGC5_LPTMR. /
Kojto	90:cb3d968589d8	2560	#define BS_SIM_SCGC5_LPTMR (1U) /!< Bit field size in bits for SIM_SCGC5_LPTMR. /
Kojto	90:cb3d968589d8	2561
Kojto	90:cb3d968589d8	2562	/! @brief Read current value of the SIM_SCGC5_LPTMR field. /
Kojto	90:cb3d968589d8	2563	#define BR_SIM_SCGC5_LPTMR(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_LPTMR))
Kojto	90:cb3d968589d8	2564
Kojto	90:cb3d968589d8	2565	/! @brief Format value for bitfield SIM_SCGC5_LPTMR. /
Kojto	90:cb3d968589d8	2566	#define BF_SIM_SCGC5_LPTMR(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_LPTMR) & BM_SIM_SCGC5_LPTMR)
Kojto	90:cb3d968589d8	2567
Kojto	90:cb3d968589d8	2568	/! @brief Set the LPTMR field to a new value. /
Kojto	90:cb3d968589d8	2569	#define BW_SIM_SCGC5_LPTMR(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_LPTMR) = (v))
Kojto	90:cb3d968589d8	2570	/@}/
Kojto	90:cb3d968589d8	2571
Kojto	90:cb3d968589d8	2572	/*!
Kojto	90:cb3d968589d8	2573	* @name Register SIM_SCGC5, field PORTA[9] (RW)
Kojto	90:cb3d968589d8	2574	*
Kojto	90:cb3d968589d8	2575	* This bit controls the clock gate to the Port A module.
Kojto	90:cb3d968589d8	2576	*
Kojto	90:cb3d968589d8	2577	* Values:
Kojto	90:cb3d968589d8	2578	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2579	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2580	*/
Kojto	90:cb3d968589d8	2581	/@{/
Kojto	90:cb3d968589d8	2582	#define BP_SIM_SCGC5_PORTA (9U) /!< Bit position for SIM_SCGC5_PORTA. /
Kojto	90:cb3d968589d8	2583	#define BM_SIM_SCGC5_PORTA (0x00000200U) /!< Bit mask for SIM_SCGC5_PORTA. /
Kojto	90:cb3d968589d8	2584	#define BS_SIM_SCGC5_PORTA (1U) /!< Bit field size in bits for SIM_SCGC5_PORTA. /
Kojto	90:cb3d968589d8	2585
Kojto	90:cb3d968589d8	2586	/! @brief Read current value of the SIM_SCGC5_PORTA field. /
Kojto	90:cb3d968589d8	2587	#define BR_SIM_SCGC5_PORTA(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTA))
Kojto	90:cb3d968589d8	2588
Kojto	90:cb3d968589d8	2589	/! @brief Format value for bitfield SIM_SCGC5_PORTA. /
Kojto	90:cb3d968589d8	2590	#define BF_SIM_SCGC5_PORTA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTA) & BM_SIM_SCGC5_PORTA)
Kojto	90:cb3d968589d8	2591
Kojto	90:cb3d968589d8	2592	/! @brief Set the PORTA field to a new value. /
Kojto	90:cb3d968589d8	2593	#define BW_SIM_SCGC5_PORTA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTA) = (v))
Kojto	90:cb3d968589d8	2594	/@}/
Kojto	90:cb3d968589d8	2595
Kojto	90:cb3d968589d8	2596	/*!
Kojto	90:cb3d968589d8	2597	* @name Register SIM_SCGC5, field PORTB[10] (RW)
Kojto	90:cb3d968589d8	2598	*
Kojto	90:cb3d968589d8	2599	* This bit controls the clock gate to the Port B module.
Kojto	90:cb3d968589d8	2600	*
Kojto	90:cb3d968589d8	2601	* Values:
Kojto	90:cb3d968589d8	2602	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2603	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2604	*/
Kojto	90:cb3d968589d8	2605	/@{/
Kojto	90:cb3d968589d8	2606	#define BP_SIM_SCGC5_PORTB (10U) /!< Bit position for SIM_SCGC5_PORTB. /
Kojto	90:cb3d968589d8	2607	#define BM_SIM_SCGC5_PORTB (0x00000400U) /!< Bit mask for SIM_SCGC5_PORTB. /
Kojto	90:cb3d968589d8	2608	#define BS_SIM_SCGC5_PORTB (1U) /!< Bit field size in bits for SIM_SCGC5_PORTB. /
Kojto	90:cb3d968589d8	2609
Kojto	90:cb3d968589d8	2610	/! @brief Read current value of the SIM_SCGC5_PORTB field. /
Kojto	90:cb3d968589d8	2611	#define BR_SIM_SCGC5_PORTB(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTB))
Kojto	90:cb3d968589d8	2612
Kojto	90:cb3d968589d8	2613	/! @brief Format value for bitfield SIM_SCGC5_PORTB. /
Kojto	90:cb3d968589d8	2614	#define BF_SIM_SCGC5_PORTB(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTB) & BM_SIM_SCGC5_PORTB)
Kojto	90:cb3d968589d8	2615
Kojto	90:cb3d968589d8	2616	/! @brief Set the PORTB field to a new value. /
Kojto	90:cb3d968589d8	2617	#define BW_SIM_SCGC5_PORTB(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTB) = (v))
Kojto	90:cb3d968589d8	2618	/@}/
Kojto	90:cb3d968589d8	2619
Kojto	90:cb3d968589d8	2620	/*!
Kojto	90:cb3d968589d8	2621	* @name Register SIM_SCGC5, field PORTC[11] (RW)
Kojto	90:cb3d968589d8	2622	*
Kojto	90:cb3d968589d8	2623	* This bit controls the clock gate to the Port C module.
Kojto	90:cb3d968589d8	2624	*
Kojto	90:cb3d968589d8	2625	* Values:
Kojto	90:cb3d968589d8	2626	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2627	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2628	*/
Kojto	90:cb3d968589d8	2629	/@{/
Kojto	90:cb3d968589d8	2630	#define BP_SIM_SCGC5_PORTC (11U) /!< Bit position for SIM_SCGC5_PORTC. /
Kojto	90:cb3d968589d8	2631	#define BM_SIM_SCGC5_PORTC (0x00000800U) /!< Bit mask for SIM_SCGC5_PORTC. /
Kojto	90:cb3d968589d8	2632	#define BS_SIM_SCGC5_PORTC (1U) /!< Bit field size in bits for SIM_SCGC5_PORTC. /
Kojto	90:cb3d968589d8	2633
Kojto	90:cb3d968589d8	2634	/! @brief Read current value of the SIM_SCGC5_PORTC field. /
Kojto	90:cb3d968589d8	2635	#define BR_SIM_SCGC5_PORTC(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTC))
Kojto	90:cb3d968589d8	2636
Kojto	90:cb3d968589d8	2637	/! @brief Format value for bitfield SIM_SCGC5_PORTC. /
Kojto	90:cb3d968589d8	2638	#define BF_SIM_SCGC5_PORTC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTC) & BM_SIM_SCGC5_PORTC)
Kojto	90:cb3d968589d8	2639
Kojto	90:cb3d968589d8	2640	/! @brief Set the PORTC field to a new value. /
Kojto	90:cb3d968589d8	2641	#define BW_SIM_SCGC5_PORTC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTC) = (v))
Kojto	90:cb3d968589d8	2642	/@}/
Kojto	90:cb3d968589d8	2643
Kojto	90:cb3d968589d8	2644	/*!
Kojto	90:cb3d968589d8	2645	* @name Register SIM_SCGC5, field PORTD[12] (RW)
Kojto	90:cb3d968589d8	2646	*
Kojto	90:cb3d968589d8	2647	* This bit controls the clock gate to the Port D module.
Kojto	90:cb3d968589d8	2648	*
Kojto	90:cb3d968589d8	2649	* Values:
Kojto	90:cb3d968589d8	2650	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2651	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2652	*/
Kojto	90:cb3d968589d8	2653	/@{/
Kojto	90:cb3d968589d8	2654	#define BP_SIM_SCGC5_PORTD (12U) /!< Bit position for SIM_SCGC5_PORTD. /
Kojto	90:cb3d968589d8	2655	#define BM_SIM_SCGC5_PORTD (0x00001000U) /!< Bit mask for SIM_SCGC5_PORTD. /
Kojto	90:cb3d968589d8	2656	#define BS_SIM_SCGC5_PORTD (1U) /!< Bit field size in bits for SIM_SCGC5_PORTD. /
Kojto	90:cb3d968589d8	2657
Kojto	90:cb3d968589d8	2658	/! @brief Read current value of the SIM_SCGC5_PORTD field. /
Kojto	90:cb3d968589d8	2659	#define BR_SIM_SCGC5_PORTD(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTD))
Kojto	90:cb3d968589d8	2660
Kojto	90:cb3d968589d8	2661	/! @brief Format value for bitfield SIM_SCGC5_PORTD. /
Kojto	90:cb3d968589d8	2662	#define BF_SIM_SCGC5_PORTD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTD) & BM_SIM_SCGC5_PORTD)
Kojto	90:cb3d968589d8	2663
Kojto	90:cb3d968589d8	2664	/! @brief Set the PORTD field to a new value. /
Kojto	90:cb3d968589d8	2665	#define BW_SIM_SCGC5_PORTD(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTD) = (v))
Kojto	90:cb3d968589d8	2666	/@}/
Kojto	90:cb3d968589d8	2667
Kojto	90:cb3d968589d8	2668	/*!
Kojto	90:cb3d968589d8	2669	* @name Register SIM_SCGC5, field PORTE[13] (RW)
Kojto	90:cb3d968589d8	2670	*
Kojto	90:cb3d968589d8	2671	* This bit controls the clock gate to the Port E module.
Kojto	90:cb3d968589d8	2672	*
Kojto	90:cb3d968589d8	2673	* Values:
Kojto	90:cb3d968589d8	2674	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2675	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2676	*/
Kojto	90:cb3d968589d8	2677	/@{/
Kojto	90:cb3d968589d8	2678	#define BP_SIM_SCGC5_PORTE (13U) /!< Bit position for SIM_SCGC5_PORTE. /
Kojto	90:cb3d968589d8	2679	#define BM_SIM_SCGC5_PORTE (0x00002000U) /!< Bit mask for SIM_SCGC5_PORTE. /
Kojto	90:cb3d968589d8	2680	#define BS_SIM_SCGC5_PORTE (1U) /!< Bit field size in bits for SIM_SCGC5_PORTE. /
Kojto	90:cb3d968589d8	2681
Kojto	90:cb3d968589d8	2682	/! @brief Read current value of the SIM_SCGC5_PORTE field. /
Kojto	90:cb3d968589d8	2683	#define BR_SIM_SCGC5_PORTE(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTE))
Kojto	90:cb3d968589d8	2684
Kojto	90:cb3d968589d8	2685	/! @brief Format value for bitfield SIM_SCGC5_PORTE. /
Kojto	90:cb3d968589d8	2686	#define BF_SIM_SCGC5_PORTE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTE) & BM_SIM_SCGC5_PORTE)
Kojto	90:cb3d968589d8	2687
Kojto	90:cb3d968589d8	2688	/! @brief Set the PORTE field to a new value. /
Kojto	90:cb3d968589d8	2689	#define BW_SIM_SCGC5_PORTE(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTE) = (v))
Kojto	90:cb3d968589d8	2690	/@}/
Kojto	90:cb3d968589d8	2691
Kojto	90:cb3d968589d8	2692	/*******************************************************************************
Kojto	90:cb3d968589d8	2693	* HW_SIM_SCGC6 - System Clock Gating Control Register 6
Kojto	90:cb3d968589d8	2694	******************************************************************************/
Kojto	90:cb3d968589d8	2695
Kojto	90:cb3d968589d8	2696	/*!
Kojto	90:cb3d968589d8	2697	* @brief HW_SIM_SCGC6 - System Clock Gating Control Register 6 (RW)
Kojto	90:cb3d968589d8	2698	*
Kojto	90:cb3d968589d8	2699	* Reset value: 0x40000001U
Kojto	90:cb3d968589d8	2700	*
Kojto	90:cb3d968589d8	2701	* DAC0, FTM2, and RNGA can be accessed through both AIPS0 and AIPS1. When
Kojto	90:cb3d968589d8	2702	* accessing through AIPS1, define the clock gate control bits in the SCGC2 and SCGC3.
Kojto	90:cb3d968589d8	2703	* When accessing through AIPS0, define the clock gate control bits in SCGC6.
Kojto	90:cb3d968589d8	2704	*/
Kojto	90:cb3d968589d8	2705	typedef union _hw_sim_scgc6
Kojto	90:cb3d968589d8	2706	{
Kojto	90:cb3d968589d8	2707	uint32_t U;
Kojto	90:cb3d968589d8	2708	struct _hw_sim_scgc6_bitfields
Kojto	90:cb3d968589d8	2709	{
Kojto	90:cb3d968589d8	2710	uint32_t FTF : 1; /!< [0] Flash Memory Clock Gate Control /
Kojto	90:cb3d968589d8	2711	uint32_t DMAMUXb : 1; /!< [1] DMA Mux Clock Gate Control /
Kojto	90:cb3d968589d8	2712	uint32_t RESERVED0 : 2; /!< [3:2] /
Kojto	90:cb3d968589d8	2713	uint32_t FLEXCAN0 : 1; /!< [4] FlexCAN0 Clock Gate Control /
Kojto	90:cb3d968589d8	2714	uint32_t RESERVED1 : 4; /!< [8:5] /
Kojto	90:cb3d968589d8	2715	uint32_t RNGA : 1; /!< [9] RNGA Clock Gate Control /
Kojto	90:cb3d968589d8	2716	uint32_t RESERVED2 : 2; /!< [11:10] /
Kojto	90:cb3d968589d8	2717	uint32_t SPI0b : 1; /!< [12] SPI0 Clock Gate Control /
Kojto	90:cb3d968589d8	2718	uint32_t SPI1b : 1; /!< [13] SPI1 Clock Gate Control /
Kojto	90:cb3d968589d8	2719	uint32_t RESERVED3 : 1; /!< [14] /
Kojto	90:cb3d968589d8	2720	uint32_t I2S : 1; /!< [15] I2S Clock Gate Control /
Kojto	90:cb3d968589d8	2721	uint32_t RESERVED4 : 2; /!< [17:16] /
Kojto	90:cb3d968589d8	2722	uint32_t CRC : 1; /!< [18] CRC Clock Gate Control /
Kojto	90:cb3d968589d8	2723	uint32_t RESERVED5 : 2; /!< [20:19] /
Kojto	90:cb3d968589d8	2724	uint32_t USBDCDb : 1; /!< [21] USB DCD Clock Gate Control /
Kojto	90:cb3d968589d8	2725	uint32_t PDB : 1; /!< [22] PDB Clock Gate Control /
Kojto	90:cb3d968589d8	2726	uint32_t PITb : 1; /!< [23] PIT Clock Gate Control /
Kojto	90:cb3d968589d8	2727	uint32_t FTM0b : 1; /!< [24] FTM0 Clock Gate Control /
Kojto	90:cb3d968589d8	2728	uint32_t FTM1b : 1; /!< [25] FTM1 Clock Gate Control /
Kojto	90:cb3d968589d8	2729	uint32_t FTM2b : 1; /!< [26] FTM2 Clock Gate Control /
Kojto	90:cb3d968589d8	2730	uint32_t ADC0b : 1; /!< [27] ADC0 Clock Gate Control /
Kojto	90:cb3d968589d8	2731	uint32_t RESERVED6 : 1; /!< [28] /
Kojto	90:cb3d968589d8	2732	uint32_t RTCb : 1; /!< [29] RTC Access Control /
Kojto	90:cb3d968589d8	2733	uint32_t RESERVED7 : 1; /!< [30] /
Kojto	90:cb3d968589d8	2734	uint32_t DAC0b : 1; /!< [31] DAC0 Clock Gate Control /
Kojto	90:cb3d968589d8	2735	} B;
Kojto	90:cb3d968589d8	2736	} hw_sim_scgc6_t;
Kojto	90:cb3d968589d8	2737
Kojto	90:cb3d968589d8	2738	/*!
Kojto	90:cb3d968589d8	2739	* @name Constants and macros for entire SIM_SCGC6 register
Kojto	90:cb3d968589d8	2740	*/
Kojto	90:cb3d968589d8	2741	/@{/
Kojto	90:cb3d968589d8	2742	#define HW_SIM_SCGC6_ADDR(x) ((x) + 0x103CU)
Kojto	90:cb3d968589d8	2743
Kojto	90:cb3d968589d8	2744	#define HW_SIM_SCGC6(x) ((__IO hw_sim_scgc6_t ) HW_SIM_SCGC6_ADDR(x))
Kojto	90:cb3d968589d8	2745	#define HW_SIM_SCGC6_RD(x) (HW_SIM_SCGC6(x).U)
Kojto	90:cb3d968589d8	2746	#define HW_SIM_SCGC6_WR(x, v) (HW_SIM_SCGC6(x).U = (v))
Kojto	90:cb3d968589d8	2747	#define HW_SIM_SCGC6_SET(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2748	#define HW_SIM_SCGC6_CLR(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2749	#define HW_SIM_SCGC6_TOG(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2750	/@}/
Kojto	90:cb3d968589d8	2751
Kojto	90:cb3d968589d8	2752	/*
Kojto	90:cb3d968589d8	2753	* Constants & macros for individual SIM_SCGC6 bitfields
Kojto	90:cb3d968589d8	2754	*/
Kojto	90:cb3d968589d8	2755
Kojto	90:cb3d968589d8	2756	/*!
Kojto	90:cb3d968589d8	2757	* @name Register SIM_SCGC6, field FTF[0] (RW)
Kojto	90:cb3d968589d8	2758	*
Kojto	90:cb3d968589d8	2759	* This bit controls the clock gate to the flash memory. Flash reads are still
Kojto	90:cb3d968589d8	2760	* supported while the flash memory is clock gated, but entry into low power modes
Kojto	90:cb3d968589d8	2761	* is blocked.
Kojto	90:cb3d968589d8	2762	*
Kojto	90:cb3d968589d8	2763	* Values:
Kojto	90:cb3d968589d8	2764	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2765	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2766	*/
Kojto	90:cb3d968589d8	2767	/@{/
Kojto	90:cb3d968589d8	2768	#define BP_SIM_SCGC6_FTF (0U) /!< Bit position for SIM_SCGC6_FTF. /
Kojto	90:cb3d968589d8	2769	#define BM_SIM_SCGC6_FTF (0x00000001U) /!< Bit mask for SIM_SCGC6_FTF. /
Kojto	90:cb3d968589d8	2770	#define BS_SIM_SCGC6_FTF (1U) /!< Bit field size in bits for SIM_SCGC6_FTF. /
Kojto	90:cb3d968589d8	2771
Kojto	90:cb3d968589d8	2772	/! @brief Read current value of the SIM_SCGC6_FTF field. /
Kojto	90:cb3d968589d8	2773	#define BR_SIM_SCGC6_FTF(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTF))
Kojto	90:cb3d968589d8	2774
Kojto	90:cb3d968589d8	2775	/! @brief Format value for bitfield SIM_SCGC6_FTF. /
Kojto	90:cb3d968589d8	2776	#define BF_SIM_SCGC6_FTF(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTF) & BM_SIM_SCGC6_FTF)
Kojto	90:cb3d968589d8	2777
Kojto	90:cb3d968589d8	2778	/! @brief Set the FTF field to a new value. /
Kojto	90:cb3d968589d8	2779	#define BW_SIM_SCGC6_FTF(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTF) = (v))
Kojto	90:cb3d968589d8	2780	/@}/
Kojto	90:cb3d968589d8	2781
Kojto	90:cb3d968589d8	2782	/*!
Kojto	90:cb3d968589d8	2783	* @name Register SIM_SCGC6, field DMAMUX[1] (RW)
Kojto	90:cb3d968589d8	2784	*
Kojto	90:cb3d968589d8	2785	* This bit controls the clock gate to the DMA Mux module.
Kojto	90:cb3d968589d8	2786	*
Kojto	90:cb3d968589d8	2787	* Values:
Kojto	90:cb3d968589d8	2788	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2789	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2790	*/
Kojto	90:cb3d968589d8	2791	/@{/
Kojto	90:cb3d968589d8	2792	#define BP_SIM_SCGC6_DMAMUX (1U) /!< Bit position for SIM_SCGC6_DMAMUX. /
Kojto	90:cb3d968589d8	2793	#define BM_SIM_SCGC6_DMAMUX (0x00000002U) /!< Bit mask for SIM_SCGC6_DMAMUX. /
Kojto	90:cb3d968589d8	2794	#define BS_SIM_SCGC6_DMAMUX (1U) /!< Bit field size in bits for SIM_SCGC6_DMAMUX. /
Kojto	90:cb3d968589d8	2795
Kojto	90:cb3d968589d8	2796	/! @brief Read current value of the SIM_SCGC6_DMAMUX field. /
Kojto	90:cb3d968589d8	2797	#define BR_SIM_SCGC6_DMAMUX(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DMAMUX))
Kojto	90:cb3d968589d8	2798
Kojto	90:cb3d968589d8	2799	/! @brief Format value for bitfield SIM_SCGC6_DMAMUX. /
Kojto	90:cb3d968589d8	2800	#define BF_SIM_SCGC6_DMAMUX(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DMAMUX) & BM_SIM_SCGC6_DMAMUX)
Kojto	90:cb3d968589d8	2801
Kojto	90:cb3d968589d8	2802	/! @brief Set the DMAMUX field to a new value. /
Kojto	90:cb3d968589d8	2803	#define BW_SIM_SCGC6_DMAMUX(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DMAMUX) = (v))
Kojto	90:cb3d968589d8	2804	/@}/
Kojto	90:cb3d968589d8	2805
Kojto	90:cb3d968589d8	2806	/*!
Kojto	90:cb3d968589d8	2807	* @name Register SIM_SCGC6, field FLEXCAN0[4] (RW)
Kojto	90:cb3d968589d8	2808	*
Kojto	90:cb3d968589d8	2809	* This bit controls the clock gate to the FlexCAN0 module.
Kojto	90:cb3d968589d8	2810	*
Kojto	90:cb3d968589d8	2811	* Values:
Kojto	90:cb3d968589d8	2812	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2813	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2814	*/
Kojto	90:cb3d968589d8	2815	/@{/
Kojto	90:cb3d968589d8	2816	#define BP_SIM_SCGC6_FLEXCAN0 (4U) /!< Bit position for SIM_SCGC6_FLEXCAN0. /
Kojto	90:cb3d968589d8	2817	#define BM_SIM_SCGC6_FLEXCAN0 (0x00000010U) /!< Bit mask for SIM_SCGC6_FLEXCAN0. /
Kojto	90:cb3d968589d8	2818	#define BS_SIM_SCGC6_FLEXCAN0 (1U) /!< Bit field size in bits for SIM_SCGC6_FLEXCAN0. /
Kojto	90:cb3d968589d8	2819
Kojto	90:cb3d968589d8	2820	/! @brief Read current value of the SIM_SCGC6_FLEXCAN0 field. /
Kojto	90:cb3d968589d8	2821	#define BR_SIM_SCGC6_FLEXCAN0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FLEXCAN0))
Kojto	90:cb3d968589d8	2822
Kojto	90:cb3d968589d8	2823	/! @brief Format value for bitfield SIM_SCGC6_FLEXCAN0. /
Kojto	90:cb3d968589d8	2824	#define BF_SIM_SCGC6_FLEXCAN0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FLEXCAN0) & BM_SIM_SCGC6_FLEXCAN0)
Kojto	90:cb3d968589d8	2825
Kojto	90:cb3d968589d8	2826	/! @brief Set the FLEXCAN0 field to a new value. /
Kojto	90:cb3d968589d8	2827	#define BW_SIM_SCGC6_FLEXCAN0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FLEXCAN0) = (v))
Kojto	90:cb3d968589d8	2828	/@}/
Kojto	90:cb3d968589d8	2829
Kojto	90:cb3d968589d8	2830	/*!
Kojto	90:cb3d968589d8	2831	* @name Register SIM_SCGC6, field RNGA[9] (RW)
Kojto	90:cb3d968589d8	2832	*
Kojto	90:cb3d968589d8	2833	* This bit controls the clock gate to the RNGA module.
Kojto	90:cb3d968589d8	2834	*/
Kojto	90:cb3d968589d8	2835	/@{/
Kojto	90:cb3d968589d8	2836	#define BP_SIM_SCGC6_RNGA (9U) /!< Bit position for SIM_SCGC6_RNGA. /
Kojto	90:cb3d968589d8	2837	#define BM_SIM_SCGC6_RNGA (0x00000200U) /!< Bit mask for SIM_SCGC6_RNGA. /
Kojto	90:cb3d968589d8	2838	#define BS_SIM_SCGC6_RNGA (1U) /!< Bit field size in bits for SIM_SCGC6_RNGA. /
Kojto	90:cb3d968589d8	2839
Kojto	90:cb3d968589d8	2840	/! @brief Read current value of the SIM_SCGC6_RNGA field. /
Kojto	90:cb3d968589d8	2841	#define BR_SIM_SCGC6_RNGA(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RNGA))
Kojto	90:cb3d968589d8	2842
Kojto	90:cb3d968589d8	2843	/! @brief Format value for bitfield SIM_SCGC6_RNGA. /
Kojto	90:cb3d968589d8	2844	#define BF_SIM_SCGC6_RNGA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_RNGA) & BM_SIM_SCGC6_RNGA)
Kojto	90:cb3d968589d8	2845
Kojto	90:cb3d968589d8	2846	/! @brief Set the RNGA field to a new value. /
Kojto	90:cb3d968589d8	2847	#define BW_SIM_SCGC6_RNGA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RNGA) = (v))
Kojto	90:cb3d968589d8	2848	/@}/
Kojto	90:cb3d968589d8	2849
Kojto	90:cb3d968589d8	2850	/*!
Kojto	90:cb3d968589d8	2851	* @name Register SIM_SCGC6, field SPI0[12] (RW)
Kojto	90:cb3d968589d8	2852	*
Kojto	90:cb3d968589d8	2853	* This bit controls the clock gate to the SPI0 module.
Kojto	90:cb3d968589d8	2854	*
Kojto	90:cb3d968589d8	2855	* Values:
Kojto	90:cb3d968589d8	2856	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2857	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2858	*/
Kojto	90:cb3d968589d8	2859	/@{/
Kojto	90:cb3d968589d8	2860	#define BP_SIM_SCGC6_SPI0 (12U) /!< Bit position for SIM_SCGC6_SPI0. /
Kojto	90:cb3d968589d8	2861	#define BM_SIM_SCGC6_SPI0 (0x00001000U) /!< Bit mask for SIM_SCGC6_SPI0. /
Kojto	90:cb3d968589d8	2862	#define BS_SIM_SCGC6_SPI0 (1U) /!< Bit field size in bits for SIM_SCGC6_SPI0. /
Kojto	90:cb3d968589d8	2863
Kojto	90:cb3d968589d8	2864	/! @brief Read current value of the SIM_SCGC6_SPI0 field. /
Kojto	90:cb3d968589d8	2865	#define BR_SIM_SCGC6_SPI0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI0))
Kojto	90:cb3d968589d8	2866
Kojto	90:cb3d968589d8	2867	/! @brief Format value for bitfield SIM_SCGC6_SPI0. /
Kojto	90:cb3d968589d8	2868	#define BF_SIM_SCGC6_SPI0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_SPI0) & BM_SIM_SCGC6_SPI0)
Kojto	90:cb3d968589d8	2869
Kojto	90:cb3d968589d8	2870	/! @brief Set the SPI0 field to a new value. /
Kojto	90:cb3d968589d8	2871	#define BW_SIM_SCGC6_SPI0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI0) = (v))
Kojto	90:cb3d968589d8	2872	/@}/
Kojto	90:cb3d968589d8	2873
Kojto	90:cb3d968589d8	2874	/*!
Kojto	90:cb3d968589d8	2875	* @name Register SIM_SCGC6, field SPI1[13] (RW)
Kojto	90:cb3d968589d8	2876	*
Kojto	90:cb3d968589d8	2877	* This bit controls the clock gate to the SPI1 module.
Kojto	90:cb3d968589d8	2878	*
Kojto	90:cb3d968589d8	2879	* Values:
Kojto	90:cb3d968589d8	2880	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2881	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2882	*/
Kojto	90:cb3d968589d8	2883	/@{/
Kojto	90:cb3d968589d8	2884	#define BP_SIM_SCGC6_SPI1 (13U) /!< Bit position for SIM_SCGC6_SPI1. /
Kojto	90:cb3d968589d8	2885	#define BM_SIM_SCGC6_SPI1 (0x00002000U) /!< Bit mask for SIM_SCGC6_SPI1. /
Kojto	90:cb3d968589d8	2886	#define BS_SIM_SCGC6_SPI1 (1U) /!< Bit field size in bits for SIM_SCGC6_SPI1. /
Kojto	90:cb3d968589d8	2887
Kojto	90:cb3d968589d8	2888	/! @brief Read current value of the SIM_SCGC6_SPI1 field. /
Kojto	90:cb3d968589d8	2889	#define BR_SIM_SCGC6_SPI1(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI1))
Kojto	90:cb3d968589d8	2890
Kojto	90:cb3d968589d8	2891	/! @brief Format value for bitfield SIM_SCGC6_SPI1. /
Kojto	90:cb3d968589d8	2892	#define BF_SIM_SCGC6_SPI1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_SPI1) & BM_SIM_SCGC6_SPI1)
Kojto	90:cb3d968589d8	2893
Kojto	90:cb3d968589d8	2894	/! @brief Set the SPI1 field to a new value. /
Kojto	90:cb3d968589d8	2895	#define BW_SIM_SCGC6_SPI1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI1) = (v))
Kojto	90:cb3d968589d8	2896	/@}/
Kojto	90:cb3d968589d8	2897
Kojto	90:cb3d968589d8	2898	/*!
Kojto	90:cb3d968589d8	2899	* @name Register SIM_SCGC6, field I2S[15] (RW)
Kojto	90:cb3d968589d8	2900	*
Kojto	90:cb3d968589d8	2901	* This bit controls the clock gate to the I 2 S module.
Kojto	90:cb3d968589d8	2902	*
Kojto	90:cb3d968589d8	2903	* Values:
Kojto	90:cb3d968589d8	2904	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2905	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2906	*/
Kojto	90:cb3d968589d8	2907	/@{/
Kojto	90:cb3d968589d8	2908	#define BP_SIM_SCGC6_I2S (15U) /!< Bit position for SIM_SCGC6_I2S. /
Kojto	90:cb3d968589d8	2909	#define BM_SIM_SCGC6_I2S (0x00008000U) /!< Bit mask for SIM_SCGC6_I2S. /
Kojto	90:cb3d968589d8	2910	#define BS_SIM_SCGC6_I2S (1U) /!< Bit field size in bits for SIM_SCGC6_I2S. /
Kojto	90:cb3d968589d8	2911
Kojto	90:cb3d968589d8	2912	/! @brief Read current value of the SIM_SCGC6_I2S field. /
Kojto	90:cb3d968589d8	2913	#define BR_SIM_SCGC6_I2S(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_I2S))
Kojto	90:cb3d968589d8	2914
Kojto	90:cb3d968589d8	2915	/! @brief Format value for bitfield SIM_SCGC6_I2S. /
Kojto	90:cb3d968589d8	2916	#define BF_SIM_SCGC6_I2S(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_I2S) & BM_SIM_SCGC6_I2S)
Kojto	90:cb3d968589d8	2917
Kojto	90:cb3d968589d8	2918	/! @brief Set the I2S field to a new value. /
Kojto	90:cb3d968589d8	2919	#define BW_SIM_SCGC6_I2S(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_I2S) = (v))
Kojto	90:cb3d968589d8	2920	/@}/
Kojto	90:cb3d968589d8	2921
Kojto	90:cb3d968589d8	2922	/*!
Kojto	90:cb3d968589d8	2923	* @name Register SIM_SCGC6, field CRC[18] (RW)
Kojto	90:cb3d968589d8	2924	*
Kojto	90:cb3d968589d8	2925	* This bit controls the clock gate to the CRC module.
Kojto	90:cb3d968589d8	2926	*
Kojto	90:cb3d968589d8	2927	* Values:
Kojto	90:cb3d968589d8	2928	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2929	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2930	*/
Kojto	90:cb3d968589d8	2931	/@{/
Kojto	90:cb3d968589d8	2932	#define BP_SIM_SCGC6_CRC (18U) /!< Bit position for SIM_SCGC6_CRC. /
Kojto	90:cb3d968589d8	2933	#define BM_SIM_SCGC6_CRC (0x00040000U) /!< Bit mask for SIM_SCGC6_CRC. /
Kojto	90:cb3d968589d8	2934	#define BS_SIM_SCGC6_CRC (1U) /!< Bit field size in bits for SIM_SCGC6_CRC. /
Kojto	90:cb3d968589d8	2935
Kojto	90:cb3d968589d8	2936	/! @brief Read current value of the SIM_SCGC6_CRC field. /
Kojto	90:cb3d968589d8	2937	#define BR_SIM_SCGC6_CRC(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_CRC))
Kojto	90:cb3d968589d8	2938
Kojto	90:cb3d968589d8	2939	/! @brief Format value for bitfield SIM_SCGC6_CRC. /
Kojto	90:cb3d968589d8	2940	#define BF_SIM_SCGC6_CRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_CRC) & BM_SIM_SCGC6_CRC)
Kojto	90:cb3d968589d8	2941
Kojto	90:cb3d968589d8	2942	/! @brief Set the CRC field to a new value. /
Kojto	90:cb3d968589d8	2943	#define BW_SIM_SCGC6_CRC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_CRC) = (v))
Kojto	90:cb3d968589d8	2944	/@}/
Kojto	90:cb3d968589d8	2945
Kojto	90:cb3d968589d8	2946	/*!
Kojto	90:cb3d968589d8	2947	* @name Register SIM_SCGC6, field USBDCD[21] (RW)
Kojto	90:cb3d968589d8	2948	*
Kojto	90:cb3d968589d8	2949	* This bit controls the clock gate to the USB DCD module.
Kojto	90:cb3d968589d8	2950	*
Kojto	90:cb3d968589d8	2951	* Values:
Kojto	90:cb3d968589d8	2952	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2953	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2954	*/
Kojto	90:cb3d968589d8	2955	/@{/
Kojto	90:cb3d968589d8	2956	#define BP_SIM_SCGC6_USBDCD (21U) /!< Bit position for SIM_SCGC6_USBDCD. /
Kojto	90:cb3d968589d8	2957	#define BM_SIM_SCGC6_USBDCD (0x00200000U) /!< Bit mask for SIM_SCGC6_USBDCD. /
Kojto	90:cb3d968589d8	2958	#define BS_SIM_SCGC6_USBDCD (1U) /!< Bit field size in bits for SIM_SCGC6_USBDCD. /
Kojto	90:cb3d968589d8	2959
Kojto	90:cb3d968589d8	2960	/! @brief Read current value of the SIM_SCGC6_USBDCD field. /
Kojto	90:cb3d968589d8	2961	#define BR_SIM_SCGC6_USBDCD(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_USBDCD))
Kojto	90:cb3d968589d8	2962
Kojto	90:cb3d968589d8	2963	/! @brief Format value for bitfield SIM_SCGC6_USBDCD. /
Kojto	90:cb3d968589d8	2964	#define BF_SIM_SCGC6_USBDCD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_USBDCD) & BM_SIM_SCGC6_USBDCD)
Kojto	90:cb3d968589d8	2965
Kojto	90:cb3d968589d8	2966	/! @brief Set the USBDCD field to a new value. /
Kojto	90:cb3d968589d8	2967	#define BW_SIM_SCGC6_USBDCD(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_USBDCD) = (v))
Kojto	90:cb3d968589d8	2968	/@}/
Kojto	90:cb3d968589d8	2969
Kojto	90:cb3d968589d8	2970	/*!
Kojto	90:cb3d968589d8	2971	* @name Register SIM_SCGC6, field PDB[22] (RW)
Kojto	90:cb3d968589d8	2972	*
Kojto	90:cb3d968589d8	2973	* This bit controls the clock gate to the PDB module.
Kojto	90:cb3d968589d8	2974	*
Kojto	90:cb3d968589d8	2975	* Values:
Kojto	90:cb3d968589d8	2976	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	2977	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	2978	*/
Kojto	90:cb3d968589d8	2979	/@{/
Kojto	90:cb3d968589d8	2980	#define BP_SIM_SCGC6_PDB (22U) /!< Bit position for SIM_SCGC6_PDB. /
Kojto	90:cb3d968589d8	2981	#define BM_SIM_SCGC6_PDB (0x00400000U) /!< Bit mask for SIM_SCGC6_PDB. /
Kojto	90:cb3d968589d8	2982	#define BS_SIM_SCGC6_PDB (1U) /!< Bit field size in bits for SIM_SCGC6_PDB. /
Kojto	90:cb3d968589d8	2983
Kojto	90:cb3d968589d8	2984	/! @brief Read current value of the SIM_SCGC6_PDB field. /
Kojto	90:cb3d968589d8	2985	#define BR_SIM_SCGC6_PDB(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PDB))
Kojto	90:cb3d968589d8	2986
Kojto	90:cb3d968589d8	2987	/! @brief Format value for bitfield SIM_SCGC6_PDB. /
Kojto	90:cb3d968589d8	2988	#define BF_SIM_SCGC6_PDB(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_PDB) & BM_SIM_SCGC6_PDB)
Kojto	90:cb3d968589d8	2989
Kojto	90:cb3d968589d8	2990	/! @brief Set the PDB field to a new value. /
Kojto	90:cb3d968589d8	2991	#define BW_SIM_SCGC6_PDB(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PDB) = (v))
Kojto	90:cb3d968589d8	2992	/@}/
Kojto	90:cb3d968589d8	2993
Kojto	90:cb3d968589d8	2994	/*!
Kojto	90:cb3d968589d8	2995	* @name Register SIM_SCGC6, field PIT[23] (RW)
Kojto	90:cb3d968589d8	2996	*
Kojto	90:cb3d968589d8	2997	* This bit controls the clock gate to the PIT module.
Kojto	90:cb3d968589d8	2998	*
Kojto	90:cb3d968589d8	2999	* Values:
Kojto	90:cb3d968589d8	3000	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	3001	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	3002	*/
Kojto	90:cb3d968589d8	3003	/@{/
Kojto	90:cb3d968589d8	3004	#define BP_SIM_SCGC6_PIT (23U) /!< Bit position for SIM_SCGC6_PIT. /
Kojto	90:cb3d968589d8	3005	#define BM_SIM_SCGC6_PIT (0x00800000U) /!< Bit mask for SIM_SCGC6_PIT. /
Kojto	90:cb3d968589d8	3006	#define BS_SIM_SCGC6_PIT (1U) /!< Bit field size in bits for SIM_SCGC6_PIT. /
Kojto	90:cb3d968589d8	3007
Kojto	90:cb3d968589d8	3008	/! @brief Read current value of the SIM_SCGC6_PIT field. /
Kojto	90:cb3d968589d8	3009	#define BR_SIM_SCGC6_PIT(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PIT))
Kojto	90:cb3d968589d8	3010
Kojto	90:cb3d968589d8	3011	/! @brief Format value for bitfield SIM_SCGC6_PIT. /
Kojto	90:cb3d968589d8	3012	#define BF_SIM_SCGC6_PIT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_PIT) & BM_SIM_SCGC6_PIT)
Kojto	90:cb3d968589d8	3013
Kojto	90:cb3d968589d8	3014	/! @brief Set the PIT field to a new value. /
Kojto	90:cb3d968589d8	3015	#define BW_SIM_SCGC6_PIT(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PIT) = (v))
Kojto	90:cb3d968589d8	3016	/@}/
Kojto	90:cb3d968589d8	3017
Kojto	90:cb3d968589d8	3018	/*!
Kojto	90:cb3d968589d8	3019	* @name Register SIM_SCGC6, field FTM0[24] (RW)
Kojto	90:cb3d968589d8	3020	*
Kojto	90:cb3d968589d8	3021	* This bit controls the clock gate to the FTM0 module.
Kojto	90:cb3d968589d8	3022	*
Kojto	90:cb3d968589d8	3023	* Values:
Kojto	90:cb3d968589d8	3024	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	3025	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	3026	*/
Kojto	90:cb3d968589d8	3027	/@{/
Kojto	90:cb3d968589d8	3028	#define BP_SIM_SCGC6_FTM0 (24U) /!< Bit position for SIM_SCGC6_FTM0. /
Kojto	90:cb3d968589d8	3029	#define BM_SIM_SCGC6_FTM0 (0x01000000U) /!< Bit mask for SIM_SCGC6_FTM0. /
Kojto	90:cb3d968589d8	3030	#define BS_SIM_SCGC6_FTM0 (1U) /!< Bit field size in bits for SIM_SCGC6_FTM0. /
Kojto	90:cb3d968589d8	3031
Kojto	90:cb3d968589d8	3032	/! @brief Read current value of the SIM_SCGC6_FTM0 field. /
Kojto	90:cb3d968589d8	3033	#define BR_SIM_SCGC6_FTM0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM0))
Kojto	90:cb3d968589d8	3034
Kojto	90:cb3d968589d8	3035	/! @brief Format value for bitfield SIM_SCGC6_FTM0. /
Kojto	90:cb3d968589d8	3036	#define BF_SIM_SCGC6_FTM0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM0) & BM_SIM_SCGC6_FTM0)
Kojto	90:cb3d968589d8	3037
Kojto	90:cb3d968589d8	3038	/! @brief Set the FTM0 field to a new value. /
Kojto	90:cb3d968589d8	3039	#define BW_SIM_SCGC6_FTM0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM0) = (v))
Kojto	90:cb3d968589d8	3040	/@}/
Kojto	90:cb3d968589d8	3041
Kojto	90:cb3d968589d8	3042	/*!
Kojto	90:cb3d968589d8	3043	* @name Register SIM_SCGC6, field FTM1[25] (RW)
Kojto	90:cb3d968589d8	3044	*
Kojto	90:cb3d968589d8	3045	* This bit controls the clock gate to the FTM1 module.
Kojto	90:cb3d968589d8	3046	*
Kojto	90:cb3d968589d8	3047	* Values:
Kojto	90:cb3d968589d8	3048	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	3049	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	3050	*/
Kojto	90:cb3d968589d8	3051	/@{/
Kojto	90:cb3d968589d8	3052	#define BP_SIM_SCGC6_FTM1 (25U) /!< Bit position for SIM_SCGC6_FTM1. /
Kojto	90:cb3d968589d8	3053	#define BM_SIM_SCGC6_FTM1 (0x02000000U) /!< Bit mask for SIM_SCGC6_FTM1. /
Kojto	90:cb3d968589d8	3054	#define BS_SIM_SCGC6_FTM1 (1U) /!< Bit field size in bits for SIM_SCGC6_FTM1. /
Kojto	90:cb3d968589d8	3055
Kojto	90:cb3d968589d8	3056	/! @brief Read current value of the SIM_SCGC6_FTM1 field. /
Kojto	90:cb3d968589d8	3057	#define BR_SIM_SCGC6_FTM1(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM1))
Kojto	90:cb3d968589d8	3058
Kojto	90:cb3d968589d8	3059	/! @brief Format value for bitfield SIM_SCGC6_FTM1. /
Kojto	90:cb3d968589d8	3060	#define BF_SIM_SCGC6_FTM1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM1) & BM_SIM_SCGC6_FTM1)
Kojto	90:cb3d968589d8	3061
Kojto	90:cb3d968589d8	3062	/! @brief Set the FTM1 field to a new value. /
Kojto	90:cb3d968589d8	3063	#define BW_SIM_SCGC6_FTM1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM1) = (v))
Kojto	90:cb3d968589d8	3064	/@}/
Kojto	90:cb3d968589d8	3065
Kojto	90:cb3d968589d8	3066	/*!
Kojto	90:cb3d968589d8	3067	* @name Register SIM_SCGC6, field FTM2[26] (RW)
Kojto	90:cb3d968589d8	3068	*
Kojto	90:cb3d968589d8	3069	* This bit controls the clock gate to the FTM2 module.
Kojto	90:cb3d968589d8	3070	*
Kojto	90:cb3d968589d8	3071	* Values:
Kojto	90:cb3d968589d8	3072	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	3073	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	3074	*/
Kojto	90:cb3d968589d8	3075	/@{/
Kojto	90:cb3d968589d8	3076	#define BP_SIM_SCGC6_FTM2 (26U) /!< Bit position for SIM_SCGC6_FTM2. /
Kojto	90:cb3d968589d8	3077	#define BM_SIM_SCGC6_FTM2 (0x04000000U) /!< Bit mask for SIM_SCGC6_FTM2. /
Kojto	90:cb3d968589d8	3078	#define BS_SIM_SCGC6_FTM2 (1U) /!< Bit field size in bits for SIM_SCGC6_FTM2. /
Kojto	90:cb3d968589d8	3079
Kojto	90:cb3d968589d8	3080	/! @brief Read current value of the SIM_SCGC6_FTM2 field. /
Kojto	90:cb3d968589d8	3081	#define BR_SIM_SCGC6_FTM2(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM2))
Kojto	90:cb3d968589d8	3082
Kojto	90:cb3d968589d8	3083	/! @brief Format value for bitfield SIM_SCGC6_FTM2. /
Kojto	90:cb3d968589d8	3084	#define BF_SIM_SCGC6_FTM2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM2) & BM_SIM_SCGC6_FTM2)
Kojto	90:cb3d968589d8	3085
Kojto	90:cb3d968589d8	3086	/! @brief Set the FTM2 field to a new value. /
Kojto	90:cb3d968589d8	3087	#define BW_SIM_SCGC6_FTM2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM2) = (v))
Kojto	90:cb3d968589d8	3088	/@}/
Kojto	90:cb3d968589d8	3089
Kojto	90:cb3d968589d8	3090	/*!
Kojto	90:cb3d968589d8	3091	* @name Register SIM_SCGC6, field ADC0[27] (RW)
Kojto	90:cb3d968589d8	3092	*
Kojto	90:cb3d968589d8	3093	* This bit controls the clock gate to the ADC0 module.
Kojto	90:cb3d968589d8	3094	*
Kojto	90:cb3d968589d8	3095	* Values:
Kojto	90:cb3d968589d8	3096	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	3097	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	3098	*/
Kojto	90:cb3d968589d8	3099	/@{/
Kojto	90:cb3d968589d8	3100	#define BP_SIM_SCGC6_ADC0 (27U) /!< Bit position for SIM_SCGC6_ADC0. /
Kojto	90:cb3d968589d8	3101	#define BM_SIM_SCGC6_ADC0 (0x08000000U) /!< Bit mask for SIM_SCGC6_ADC0. /
Kojto	90:cb3d968589d8	3102	#define BS_SIM_SCGC6_ADC0 (1U) /!< Bit field size in bits for SIM_SCGC6_ADC0. /
Kojto	90:cb3d968589d8	3103
Kojto	90:cb3d968589d8	3104	/! @brief Read current value of the SIM_SCGC6_ADC0 field. /
Kojto	90:cb3d968589d8	3105	#define BR_SIM_SCGC6_ADC0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC0))
Kojto	90:cb3d968589d8	3106
Kojto	90:cb3d968589d8	3107	/! @brief Format value for bitfield SIM_SCGC6_ADC0. /
Kojto	90:cb3d968589d8	3108	#define BF_SIM_SCGC6_ADC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_ADC0) & BM_SIM_SCGC6_ADC0)
Kojto	90:cb3d968589d8	3109
Kojto	90:cb3d968589d8	3110	/! @brief Set the ADC0 field to a new value. /
Kojto	90:cb3d968589d8	3111	#define BW_SIM_SCGC6_ADC0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC0) = (v))
Kojto	90:cb3d968589d8	3112	/@}/
Kojto	90:cb3d968589d8	3113
Kojto	90:cb3d968589d8	3114	/*!
Kojto	90:cb3d968589d8	3115	* @name Register SIM_SCGC6, field RTC[29] (RW)
Kojto	90:cb3d968589d8	3116	*
Kojto	90:cb3d968589d8	3117	* This bit controls software access and interrupts to the RTC module.
Kojto	90:cb3d968589d8	3118	*
Kojto	90:cb3d968589d8	3119	* Values:
Kojto	90:cb3d968589d8	3120	* - 0 - Access and interrupts disabled
Kojto	90:cb3d968589d8	3121	* - 1 - Access and interrupts enabled
Kojto	90:cb3d968589d8	3122	*/
Kojto	90:cb3d968589d8	3123	/@{/
Kojto	90:cb3d968589d8	3124	#define BP_SIM_SCGC6_RTC (29U) /!< Bit position for SIM_SCGC6_RTC. /
Kojto	90:cb3d968589d8	3125	#define BM_SIM_SCGC6_RTC (0x20000000U) /!< Bit mask for SIM_SCGC6_RTC. /
Kojto	90:cb3d968589d8	3126	#define BS_SIM_SCGC6_RTC (1U) /!< Bit field size in bits for SIM_SCGC6_RTC. /
Kojto	90:cb3d968589d8	3127
Kojto	90:cb3d968589d8	3128	/! @brief Read current value of the SIM_SCGC6_RTC field. /
Kojto	90:cb3d968589d8	3129	#define BR_SIM_SCGC6_RTC(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RTC))
Kojto	90:cb3d968589d8	3130
Kojto	90:cb3d968589d8	3131	/! @brief Format value for bitfield SIM_SCGC6_RTC. /
Kojto	90:cb3d968589d8	3132	#define BF_SIM_SCGC6_RTC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_RTC) & BM_SIM_SCGC6_RTC)
Kojto	90:cb3d968589d8	3133
Kojto	90:cb3d968589d8	3134	/! @brief Set the RTC field to a new value. /
Kojto	90:cb3d968589d8	3135	#define BW_SIM_SCGC6_RTC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RTC) = (v))
Kojto	90:cb3d968589d8	3136	/@}/
Kojto	90:cb3d968589d8	3137
Kojto	90:cb3d968589d8	3138	/*!
Kojto	90:cb3d968589d8	3139	* @name Register SIM_SCGC6, field DAC0[31] (RW)
Kojto	90:cb3d968589d8	3140	*
Kojto	90:cb3d968589d8	3141	* This bit controls the clock gate to the DAC0 module.
Kojto	90:cb3d968589d8	3142	*
Kojto	90:cb3d968589d8	3143	* Values:
Kojto	90:cb3d968589d8	3144	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	3145	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	3146	*/
Kojto	90:cb3d968589d8	3147	/@{/
Kojto	90:cb3d968589d8	3148	#define BP_SIM_SCGC6_DAC0 (31U) /!< Bit position for SIM_SCGC6_DAC0. /
Kojto	90:cb3d968589d8	3149	#define BM_SIM_SCGC6_DAC0 (0x80000000U) /!< Bit mask for SIM_SCGC6_DAC0. /
Kojto	90:cb3d968589d8	3150	#define BS_SIM_SCGC6_DAC0 (1U) /!< Bit field size in bits for SIM_SCGC6_DAC0. /
Kojto	90:cb3d968589d8	3151
Kojto	90:cb3d968589d8	3152	/! @brief Read current value of the SIM_SCGC6_DAC0 field. /
Kojto	90:cb3d968589d8	3153	#define BR_SIM_SCGC6_DAC0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DAC0))
Kojto	90:cb3d968589d8	3154
Kojto	90:cb3d968589d8	3155	/! @brief Format value for bitfield SIM_SCGC6_DAC0. /
Kojto	90:cb3d968589d8	3156	#define BF_SIM_SCGC6_DAC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DAC0) & BM_SIM_SCGC6_DAC0)
Kojto	90:cb3d968589d8	3157
Kojto	90:cb3d968589d8	3158	/! @brief Set the DAC0 field to a new value. /
Kojto	90:cb3d968589d8	3159	#define BW_SIM_SCGC6_DAC0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DAC0) = (v))
Kojto	90:cb3d968589d8	3160	/@}/
Kojto	90:cb3d968589d8	3161
Kojto	90:cb3d968589d8	3162	/*******************************************************************************
Kojto	90:cb3d968589d8	3163	* HW_SIM_SCGC7 - System Clock Gating Control Register 7
Kojto	90:cb3d968589d8	3164	******************************************************************************/
Kojto	90:cb3d968589d8	3165
Kojto	90:cb3d968589d8	3166	/*!
Kojto	90:cb3d968589d8	3167	* @brief HW_SIM_SCGC7 - System Clock Gating Control Register 7 (RW)
Kojto	90:cb3d968589d8	3168	*
Kojto	90:cb3d968589d8	3169	* Reset value: 0x00000006U
Kojto	90:cb3d968589d8	3170	*/
Kojto	90:cb3d968589d8	3171	typedef union _hw_sim_scgc7
Kojto	90:cb3d968589d8	3172	{
Kojto	90:cb3d968589d8	3173	uint32_t U;
Kojto	90:cb3d968589d8	3174	struct _hw_sim_scgc7_bitfields
Kojto	90:cb3d968589d8	3175	{
Kojto	90:cb3d968589d8	3176	uint32_t FLEXBUS : 1; /!< [0] FlexBus Clock Gate Control /
Kojto	90:cb3d968589d8	3177	uint32_t DMA : 1; /!< [1] DMA Clock Gate Control /
Kojto	90:cb3d968589d8	3178	uint32_t MPUb : 1; /!< [2] MPU Clock Gate Control /
Kojto	90:cb3d968589d8	3179	uint32_t RESERVED0 : 29; /!< [31:3] /
Kojto	90:cb3d968589d8	3180	} B;
Kojto	90:cb3d968589d8	3181	} hw_sim_scgc7_t;
Kojto	90:cb3d968589d8	3182
Kojto	90:cb3d968589d8	3183	/*!
Kojto	90:cb3d968589d8	3184	* @name Constants and macros for entire SIM_SCGC7 register
Kojto	90:cb3d968589d8	3185	*/
Kojto	90:cb3d968589d8	3186	/@{/
Kojto	90:cb3d968589d8	3187	#define HW_SIM_SCGC7_ADDR(x) ((x) + 0x1040U)
Kojto	90:cb3d968589d8	3188
Kojto	90:cb3d968589d8	3189	#define HW_SIM_SCGC7(x) ((__IO hw_sim_scgc7_t ) HW_SIM_SCGC7_ADDR(x))
Kojto	90:cb3d968589d8	3190	#define HW_SIM_SCGC7_RD(x) (HW_SIM_SCGC7(x).U)
Kojto	90:cb3d968589d8	3191	#define HW_SIM_SCGC7_WR(x, v) (HW_SIM_SCGC7(x).U = (v))
Kojto	90:cb3d968589d8	3192	#define HW_SIM_SCGC7_SET(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) \| (v)))
Kojto	90:cb3d968589d8	3193	#define HW_SIM_SCGC7_CLR(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	3194	#define HW_SIM_SCGC7_TOG(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	3195	/@}/
Kojto	90:cb3d968589d8	3196
Kojto	90:cb3d968589d8	3197	/*
Kojto	90:cb3d968589d8	3198	* Constants & macros for individual SIM_SCGC7 bitfields
Kojto	90:cb3d968589d8	3199	*/
Kojto	90:cb3d968589d8	3200
Kojto	90:cb3d968589d8	3201	/*!
Kojto	90:cb3d968589d8	3202	* @name Register SIM_SCGC7, field FLEXBUS[0] (RW)
Kojto	90:cb3d968589d8	3203	*
Kojto	90:cb3d968589d8	3204	* This bit controls the clock gate to the FlexBus module.
Kojto	90:cb3d968589d8	3205	*
Kojto	90:cb3d968589d8	3206	* Values:
Kojto	90:cb3d968589d8	3207	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	3208	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	3209	*/
Kojto	90:cb3d968589d8	3210	/@{/
Kojto	90:cb3d968589d8	3211	#define BP_SIM_SCGC7_FLEXBUS (0U) /!< Bit position for SIM_SCGC7_FLEXBUS. /
Kojto	90:cb3d968589d8	3212	#define BM_SIM_SCGC7_FLEXBUS (0x00000001U) /!< Bit mask for SIM_SCGC7_FLEXBUS. /
Kojto	90:cb3d968589d8	3213	#define BS_SIM_SCGC7_FLEXBUS (1U) /!< Bit field size in bits for SIM_SCGC7_FLEXBUS. /
Kojto	90:cb3d968589d8	3214
Kojto	90:cb3d968589d8	3215	/! @brief Read current value of the SIM_SCGC7_FLEXBUS field. /
Kojto	90:cb3d968589d8	3216	#define BR_SIM_SCGC7_FLEXBUS(x) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_FLEXBUS))
Kojto	90:cb3d968589d8	3217
Kojto	90:cb3d968589d8	3218	/! @brief Format value for bitfield SIM_SCGC7_FLEXBUS. /
Kojto	90:cb3d968589d8	3219	#define BF_SIM_SCGC7_FLEXBUS(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_FLEXBUS) & BM_SIM_SCGC7_FLEXBUS)
Kojto	90:cb3d968589d8	3220
Kojto	90:cb3d968589d8	3221	/! @brief Set the FLEXBUS field to a new value. /
Kojto	90:cb3d968589d8	3222	#define BW_SIM_SCGC7_FLEXBUS(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_FLEXBUS) = (v))
Kojto	90:cb3d968589d8	3223	/@}/
Kojto	90:cb3d968589d8	3224
Kojto	90:cb3d968589d8	3225	/*!
Kojto	90:cb3d968589d8	3226	* @name Register SIM_SCGC7, field DMA[1] (RW)
Kojto	90:cb3d968589d8	3227	*
Kojto	90:cb3d968589d8	3228	* This bit controls the clock gate to the DMA module.
Kojto	90:cb3d968589d8	3229	*
Kojto	90:cb3d968589d8	3230	* Values:
Kojto	90:cb3d968589d8	3231	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	3232	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	3233	*/
Kojto	90:cb3d968589d8	3234	/@{/
Kojto	90:cb3d968589d8	3235	#define BP_SIM_SCGC7_DMA (1U) /!< Bit position for SIM_SCGC7_DMA. /
Kojto	90:cb3d968589d8	3236	#define BM_SIM_SCGC7_DMA (0x00000002U) /!< Bit mask for SIM_SCGC7_DMA. /
Kojto	90:cb3d968589d8	3237	#define BS_SIM_SCGC7_DMA (1U) /!< Bit field size in bits for SIM_SCGC7_DMA. /
Kojto	90:cb3d968589d8	3238
Kojto	90:cb3d968589d8	3239	/! @brief Read current value of the SIM_SCGC7_DMA field. /
Kojto	90:cb3d968589d8	3240	#define BR_SIM_SCGC7_DMA(x) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_DMA))
Kojto	90:cb3d968589d8	3241
Kojto	90:cb3d968589d8	3242	/! @brief Format value for bitfield SIM_SCGC7_DMA. /
Kojto	90:cb3d968589d8	3243	#define BF_SIM_SCGC7_DMA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_DMA) & BM_SIM_SCGC7_DMA)
Kojto	90:cb3d968589d8	3244
Kojto	90:cb3d968589d8	3245	/! @brief Set the DMA field to a new value. /
Kojto	90:cb3d968589d8	3246	#define BW_SIM_SCGC7_DMA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_DMA) = (v))
Kojto	90:cb3d968589d8	3247	/@}/
Kojto	90:cb3d968589d8	3248
Kojto	90:cb3d968589d8	3249	/*!
Kojto	90:cb3d968589d8	3250	* @name Register SIM_SCGC7, field MPU[2] (RW)
Kojto	90:cb3d968589d8	3251	*
Kojto	90:cb3d968589d8	3252	* This bit controls the clock gate to the MPU module.
Kojto	90:cb3d968589d8	3253	*
Kojto	90:cb3d968589d8	3254	* Values:
Kojto	90:cb3d968589d8	3255	* - 0 - Clock disabled
Kojto	90:cb3d968589d8	3256	* - 1 - Clock enabled
Kojto	90:cb3d968589d8	3257	*/
Kojto	90:cb3d968589d8	3258	/@{/
Kojto	90:cb3d968589d8	3259	#define BP_SIM_SCGC7_MPU (2U) /!< Bit position for SIM_SCGC7_MPU. /
Kojto	90:cb3d968589d8	3260	#define BM_SIM_SCGC7_MPU (0x00000004U) /!< Bit mask for SIM_SCGC7_MPU. /
Kojto	90:cb3d968589d8	3261	#define BS_SIM_SCGC7_MPU (1U) /!< Bit field size in bits for SIM_SCGC7_MPU. /
Kojto	90:cb3d968589d8	3262
Kojto	90:cb3d968589d8	3263	/! @brief Read current value of the SIM_SCGC7_MPU field. /
Kojto	90:cb3d968589d8	3264	#define BR_SIM_SCGC7_MPU(x) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_MPU))
Kojto	90:cb3d968589d8	3265
Kojto	90:cb3d968589d8	3266	/! @brief Format value for bitfield SIM_SCGC7_MPU. /
Kojto	90:cb3d968589d8	3267	#define BF_SIM_SCGC7_MPU(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_MPU) & BM_SIM_SCGC7_MPU)
Kojto	90:cb3d968589d8	3268
Kojto	90:cb3d968589d8	3269	/! @brief Set the MPU field to a new value. /
Kojto	90:cb3d968589d8	3270	#define BW_SIM_SCGC7_MPU(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_MPU) = (v))
Kojto	90:cb3d968589d8	3271	/@}/
Kojto	90:cb3d968589d8	3272
Kojto	90:cb3d968589d8	3273	/*******************************************************************************
Kojto	90:cb3d968589d8	3274	* HW_SIM_CLKDIV1 - System Clock Divider Register 1
Kojto	90:cb3d968589d8	3275	******************************************************************************/
Kojto	90:cb3d968589d8	3276
Kojto	90:cb3d968589d8	3277	/*!
Kojto	90:cb3d968589d8	3278	* @brief HW_SIM_CLKDIV1 - System Clock Divider Register 1 (RW)
Kojto	90:cb3d968589d8	3279	*
Kojto	90:cb3d968589d8	3280	* Reset value: 0x00010000U
Kojto	90:cb3d968589d8	3281	*
Kojto	90:cb3d968589d8	3282	* When updating CLKDIV1, update all fields using the one write command.
Kojto	90:cb3d968589d8	3283	* Attempting to write an invalid clock ratio to the CLKDIV1 register will cause the
Kojto	90:cb3d968589d8	3284	* write to be ignored. The maximum divide ratio that can be programmed between
Kojto	90:cb3d968589d8	3285	* core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals
Kojto	90:cb3d968589d8	3286	* 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide
Kojto	90:cb3d968589d8	3287	* by 8). The CLKDIV1 register cannot be written to when the device is in VLPR
Kojto	90:cb3d968589d8	3288	* mode.
Kojto	90:cb3d968589d8	3289	*/
Kojto	90:cb3d968589d8	3290	typedef union _hw_sim_clkdiv1
Kojto	90:cb3d968589d8	3291	{
Kojto	90:cb3d968589d8	3292	uint32_t U;
Kojto	90:cb3d968589d8	3293	struct _hw_sim_clkdiv1_bitfields
Kojto	90:cb3d968589d8	3294	{
Kojto	90:cb3d968589d8	3295	uint32_t RESERVED0 : 16; /!< [15:0] /
Kojto	90:cb3d968589d8	3296	uint32_t OUTDIV4 : 4; /!< [19:16] Clock 4 output divider value /
Kojto	90:cb3d968589d8	3297	uint32_t OUTDIV3 : 4; /!< [23:20] Clock 3 output divider value /
Kojto	90:cb3d968589d8	3298	uint32_t OUTDIV2 : 4; /!< [27:24] Clock 2 output divider value /
Kojto	90:cb3d968589d8	3299	uint32_t OUTDIV1 : 4; /!< [31:28] Clock 1 output divider value /
Kojto	90:cb3d968589d8	3300	} B;
Kojto	90:cb3d968589d8	3301	} hw_sim_clkdiv1_t;
Kojto	90:cb3d968589d8	3302
Kojto	90:cb3d968589d8	3303	/*!
Kojto	90:cb3d968589d8	3304	* @name Constants and macros for entire SIM_CLKDIV1 register
Kojto	90:cb3d968589d8	3305	*/
Kojto	90:cb3d968589d8	3306	/@{/
Kojto	90:cb3d968589d8	3307	#define HW_SIM_CLKDIV1_ADDR(x) ((x) + 0x1044U)
Kojto	90:cb3d968589d8	3308
Kojto	90:cb3d968589d8	3309	#define HW_SIM_CLKDIV1(x) ((__IO hw_sim_clkdiv1_t ) HW_SIM_CLKDIV1_ADDR(x))
Kojto	90:cb3d968589d8	3310	#define HW_SIM_CLKDIV1_RD(x) (HW_SIM_CLKDIV1(x).U)
Kojto	90:cb3d968589d8	3311	#define HW_SIM_CLKDIV1_WR(x, v) (HW_SIM_CLKDIV1(x).U = (v))
Kojto	90:cb3d968589d8	3312	#define HW_SIM_CLKDIV1_SET(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) \| (v)))
Kojto	90:cb3d968589d8	3313	#define HW_SIM_CLKDIV1_CLR(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	3314	#define HW_SIM_CLKDIV1_TOG(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	3315	/@}/
Kojto	90:cb3d968589d8	3316
Kojto	90:cb3d968589d8	3317	/*
Kojto	90:cb3d968589d8	3318	* Constants & macros for individual SIM_CLKDIV1 bitfields
Kojto	90:cb3d968589d8	3319	*/
Kojto	90:cb3d968589d8	3320
Kojto	90:cb3d968589d8	3321	/*!
Kojto	90:cb3d968589d8	3322	* @name Register SIM_CLKDIV1, field OUTDIV4[19:16] (RW)
Kojto	90:cb3d968589d8	3323	*
Kojto	90:cb3d968589d8	3324	* This field sets the divide value for the flash clock from MCGOUTCLK. At the
Kojto	90:cb3d968589d8	3325	* end of reset, it is loaded with either 0001 or 1111 depending on
Kojto	90:cb3d968589d8	3326	* FTF_FOPT[LPBOOT]. The flash clock frequency must be an integer divide of the system clock
Kojto	90:cb3d968589d8	3327	* frequency.
Kojto	90:cb3d968589d8	3328	*
Kojto	90:cb3d968589d8	3329	* Values:
Kojto	90:cb3d968589d8	3330	* - 0000 - Divide-by-1.
Kojto	90:cb3d968589d8	3331	* - 0001 - Divide-by-2.
Kojto	90:cb3d968589d8	3332	* - 0010 - Divide-by-3.
Kojto	90:cb3d968589d8	3333	* - 0011 - Divide-by-4.
Kojto	90:cb3d968589d8	3334	* - 0100 - Divide-by-5.
Kojto	90:cb3d968589d8	3335	* - 0101 - Divide-by-6.
Kojto	90:cb3d968589d8	3336	* - 0110 - Divide-by-7.
Kojto	90:cb3d968589d8	3337	* - 0111 - Divide-by-8.
Kojto	90:cb3d968589d8	3338	* - 1000 - Divide-by-9.
Kojto	90:cb3d968589d8	3339	* - 1001 - Divide-by-10.
Kojto	90:cb3d968589d8	3340	* - 1010 - Divide-by-11.
Kojto	90:cb3d968589d8	3341	* - 1011 - Divide-by-12.
Kojto	90:cb3d968589d8	3342	* - 1100 - Divide-by-13.
Kojto	90:cb3d968589d8	3343	* - 1101 - Divide-by-14.
Kojto	90:cb3d968589d8	3344	* - 1110 - Divide-by-15.
Kojto	90:cb3d968589d8	3345	* - 1111 - Divide-by-16.
Kojto	90:cb3d968589d8	3346	*/
Kojto	90:cb3d968589d8	3347	/@{/
Kojto	90:cb3d968589d8	3348	#define BP_SIM_CLKDIV1_OUTDIV4 (16U) /!< Bit position for SIM_CLKDIV1_OUTDIV4. /
Kojto	90:cb3d968589d8	3349	#define BM_SIM_CLKDIV1_OUTDIV4 (0x000F0000U) /!< Bit mask for SIM_CLKDIV1_OUTDIV4. /
Kojto	90:cb3d968589d8	3350	#define BS_SIM_CLKDIV1_OUTDIV4 (4U) /!< Bit field size in bits for SIM_CLKDIV1_OUTDIV4. /
Kojto	90:cb3d968589d8	3351
Kojto	90:cb3d968589d8	3352	/! @brief Read current value of the SIM_CLKDIV1_OUTDIV4 field. /
Kojto	90:cb3d968589d8	3353	#define BR_SIM_CLKDIV1_OUTDIV4(x) (HW_SIM_CLKDIV1(x).B.OUTDIV4)
Kojto	90:cb3d968589d8	3354
Kojto	90:cb3d968589d8	3355	/! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV4. /
Kojto	90:cb3d968589d8	3356	#define BF_SIM_CLKDIV1_OUTDIV4(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV4) & BM_SIM_CLKDIV1_OUTDIV4)
Kojto	90:cb3d968589d8	3357
Kojto	90:cb3d968589d8	3358	/! @brief Set the OUTDIV4 field to a new value. /
Kojto	90:cb3d968589d8	3359	#define BW_SIM_CLKDIV1_OUTDIV4(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV4) \| BF_SIM_CLKDIV1_OUTDIV4(v)))
Kojto	90:cb3d968589d8	3360	/@}/
Kojto	90:cb3d968589d8	3361
Kojto	90:cb3d968589d8	3362	/*!
Kojto	90:cb3d968589d8	3363	* @name Register SIM_CLKDIV1, field OUTDIV3[23:20] (RW)
Kojto	90:cb3d968589d8	3364	*
Kojto	90:cb3d968589d8	3365	* This field sets the divide value for the FlexBus clock (external pin FB_CLK)
Kojto	90:cb3d968589d8	3366	* from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111
Kojto	90:cb3d968589d8	3367	* depending on FTF_FOPT[LPBOOT]. The FlexBus clock frequency must be an integer
Kojto	90:cb3d968589d8	3368	* divide of the system clock frequency.
Kojto	90:cb3d968589d8	3369	*
Kojto	90:cb3d968589d8	3370	* Values:
Kojto	90:cb3d968589d8	3371	* - 0000 - Divide-by-1.
Kojto	90:cb3d968589d8	3372	* - 0001 - Divide-by-2.
Kojto	90:cb3d968589d8	3373	* - 0010 - Divide-by-3.
Kojto	90:cb3d968589d8	3374	* - 0011 - Divide-by-4.
Kojto	90:cb3d968589d8	3375	* - 0100 - Divide-by-5.
Kojto	90:cb3d968589d8	3376	* - 0101 - Divide-by-6.
Kojto	90:cb3d968589d8	3377	* - 0110 - Divide-by-7.
Kojto	90:cb3d968589d8	3378	* - 0111 - Divide-by-8.
Kojto	90:cb3d968589d8	3379	* - 1000 - Divide-by-9.
Kojto	90:cb3d968589d8	3380	* - 1001 - Divide-by-10.
Kojto	90:cb3d968589d8	3381	* - 1010 - Divide-by-11.
Kojto	90:cb3d968589d8	3382	* - 1011 - Divide-by-12.
Kojto	90:cb3d968589d8	3383	* - 1100 - Divide-by-13.
Kojto	90:cb3d968589d8	3384	* - 1101 - Divide-by-14.
Kojto	90:cb3d968589d8	3385	* - 1110 - Divide-by-15.
Kojto	90:cb3d968589d8	3386	* - 1111 - Divide-by-16.
Kojto	90:cb3d968589d8	3387	*/
Kojto	90:cb3d968589d8	3388	/@{/
Kojto	90:cb3d968589d8	3389	#define BP_SIM_CLKDIV1_OUTDIV3 (20U) /!< Bit position for SIM_CLKDIV1_OUTDIV3. /
Kojto	90:cb3d968589d8	3390	#define BM_SIM_CLKDIV1_OUTDIV3 (0x00F00000U) /!< Bit mask for SIM_CLKDIV1_OUTDIV3. /
Kojto	90:cb3d968589d8	3391	#define BS_SIM_CLKDIV1_OUTDIV3 (4U) /!< Bit field size in bits for SIM_CLKDIV1_OUTDIV3. /
Kojto	90:cb3d968589d8	3392
Kojto	90:cb3d968589d8	3393	/! @brief Read current value of the SIM_CLKDIV1_OUTDIV3 field. /
Kojto	90:cb3d968589d8	3394	#define BR_SIM_CLKDIV1_OUTDIV3(x) (HW_SIM_CLKDIV1(x).B.OUTDIV3)
Kojto	90:cb3d968589d8	3395
Kojto	90:cb3d968589d8	3396	/! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV3. /
Kojto	90:cb3d968589d8	3397	#define BF_SIM_CLKDIV1_OUTDIV3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV3) & BM_SIM_CLKDIV1_OUTDIV3)
Kojto	90:cb3d968589d8	3398
Kojto	90:cb3d968589d8	3399	/! @brief Set the OUTDIV3 field to a new value. /
Kojto	90:cb3d968589d8	3400	#define BW_SIM_CLKDIV1_OUTDIV3(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV3) \| BF_SIM_CLKDIV1_OUTDIV3(v)))
Kojto	90:cb3d968589d8	3401	/@}/
Kojto	90:cb3d968589d8	3402
Kojto	90:cb3d968589d8	3403	/*!
Kojto	90:cb3d968589d8	3404	* @name Register SIM_CLKDIV1, field OUTDIV2[27:24] (RW)
Kojto	90:cb3d968589d8	3405	*
Kojto	90:cb3d968589d8	3406	* This field sets the divide value for the bus clock from MCGOUTCLK. At the end
Kojto	90:cb3d968589d8	3407	* of reset, it is loaded with either 0000 or 0111 depending on
Kojto	90:cb3d968589d8	3408	* FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock
Kojto	90:cb3d968589d8	3409	* frequency.
Kojto	90:cb3d968589d8	3410	*
Kojto	90:cb3d968589d8	3411	* Values:
Kojto	90:cb3d968589d8	3412	* - 0000 - Divide-by-1.
Kojto	90:cb3d968589d8	3413	* - 0001 - Divide-by-2.
Kojto	90:cb3d968589d8	3414	* - 0010 - Divide-by-3.
Kojto	90:cb3d968589d8	3415	* - 0011 - Divide-by-4.
Kojto	90:cb3d968589d8	3416	* - 0100 - Divide-by-5.
Kojto	90:cb3d968589d8	3417	* - 0101 - Divide-by-6.
Kojto	90:cb3d968589d8	3418	* - 0110 - Divide-by-7.
Kojto	90:cb3d968589d8	3419	* - 0111 - Divide-by-8.
Kojto	90:cb3d968589d8	3420	* - 1000 - Divide-by-9.
Kojto	90:cb3d968589d8	3421	* - 1001 - Divide-by-10.
Kojto	90:cb3d968589d8	3422	* - 1010 - Divide-by-11.
Kojto	90:cb3d968589d8	3423	* - 1011 - Divide-by-12.
Kojto	90:cb3d968589d8	3424	* - 1100 - Divide-by-13.
Kojto	90:cb3d968589d8	3425	* - 1101 - Divide-by-14.
Kojto	90:cb3d968589d8	3426	* - 1110 - Divide-by-15.
Kojto	90:cb3d968589d8	3427	* - 1111 - Divide-by-16.
Kojto	90:cb3d968589d8	3428	*/
Kojto	90:cb3d968589d8	3429	/@{/
Kojto	90:cb3d968589d8	3430	#define BP_SIM_CLKDIV1_OUTDIV2 (24U) /!< Bit position for SIM_CLKDIV1_OUTDIV2. /
Kojto	90:cb3d968589d8	3431	#define BM_SIM_CLKDIV1_OUTDIV2 (0x0F000000U) /!< Bit mask for SIM_CLKDIV1_OUTDIV2. /
Kojto	90:cb3d968589d8	3432	#define BS_SIM_CLKDIV1_OUTDIV2 (4U) /!< Bit field size in bits for SIM_CLKDIV1_OUTDIV2. /
Kojto	90:cb3d968589d8	3433
Kojto	90:cb3d968589d8	3434	/! @brief Read current value of the SIM_CLKDIV1_OUTDIV2 field. /
Kojto	90:cb3d968589d8	3435	#define BR_SIM_CLKDIV1_OUTDIV2(x) (HW_SIM_CLKDIV1(x).B.OUTDIV2)
Kojto	90:cb3d968589d8	3436
Kojto	90:cb3d968589d8	3437	/! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV2. /
Kojto	90:cb3d968589d8	3438	#define BF_SIM_CLKDIV1_OUTDIV2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV2) & BM_SIM_CLKDIV1_OUTDIV2)
Kojto	90:cb3d968589d8	3439
Kojto	90:cb3d968589d8	3440	/! @brief Set the OUTDIV2 field to a new value. /
Kojto	90:cb3d968589d8	3441	#define BW_SIM_CLKDIV1_OUTDIV2(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV2) \| BF_SIM_CLKDIV1_OUTDIV2(v)))
Kojto	90:cb3d968589d8	3442	/@}/
Kojto	90:cb3d968589d8	3443
Kojto	90:cb3d968589d8	3444	/*!
Kojto	90:cb3d968589d8	3445	* @name Register SIM_CLKDIV1, field OUTDIV1[31:28] (RW)
Kojto	90:cb3d968589d8	3446	*
Kojto	90:cb3d968589d8	3447	* This field sets the divide value for the core/system clock from MCGOUTCLK. At
Kojto	90:cb3d968589d8	3448	* the end of reset, it is loaded with either 0000 or 0111 depending on
Kojto	90:cb3d968589d8	3449	* FTF_FOPT[LPBOOT].
Kojto	90:cb3d968589d8	3450	*
Kojto	90:cb3d968589d8	3451	* Values:
Kojto	90:cb3d968589d8	3452	* - 0000 - Divide-by-1.
Kojto	90:cb3d968589d8	3453	* - 0001 - Divide-by-2.
Kojto	90:cb3d968589d8	3454	* - 0010 - Divide-by-3.
Kojto	90:cb3d968589d8	3455	* - 0011 - Divide-by-4.
Kojto	90:cb3d968589d8	3456	* - 0100 - Divide-by-5.
Kojto	90:cb3d968589d8	3457	* - 0101 - Divide-by-6.
Kojto	90:cb3d968589d8	3458	* - 0110 - Divide-by-7.
Kojto	90:cb3d968589d8	3459	* - 0111 - Divide-by-8.
Kojto	90:cb3d968589d8	3460	* - 1000 - Divide-by-9.
Kojto	90:cb3d968589d8	3461	* - 1001 - Divide-by-10.
Kojto	90:cb3d968589d8	3462	* - 1010 - Divide-by-11.
Kojto	90:cb3d968589d8	3463	* - 1011 - Divide-by-12.
Kojto	90:cb3d968589d8	3464	* - 1100 - Divide-by-13.
Kojto	90:cb3d968589d8	3465	* - 1101 - Divide-by-14.
Kojto	90:cb3d968589d8	3466	* - 1110 - Divide-by-15.
Kojto	90:cb3d968589d8	3467	* - 1111 - Divide-by-16.
Kojto	90:cb3d968589d8	3468	*/
Kojto	90:cb3d968589d8	3469	/@{/
Kojto	90:cb3d968589d8	3470	#define BP_SIM_CLKDIV1_OUTDIV1 (28U) /!< Bit position for SIM_CLKDIV1_OUTDIV1. /
Kojto	90:cb3d968589d8	3471	#define BM_SIM_CLKDIV1_OUTDIV1 (0xF0000000U) /!< Bit mask for SIM_CLKDIV1_OUTDIV1. /
Kojto	90:cb3d968589d8	3472	#define BS_SIM_CLKDIV1_OUTDIV1 (4U) /!< Bit field size in bits for SIM_CLKDIV1_OUTDIV1. /
Kojto	90:cb3d968589d8	3473
Kojto	90:cb3d968589d8	3474	/! @brief Read current value of the SIM_CLKDIV1_OUTDIV1 field. /
Kojto	90:cb3d968589d8	3475	#define BR_SIM_CLKDIV1_OUTDIV1(x) (HW_SIM_CLKDIV1(x).B.OUTDIV1)
Kojto	90:cb3d968589d8	3476
Kojto	90:cb3d968589d8	3477	/! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV1. /
Kojto	90:cb3d968589d8	3478	#define BF_SIM_CLKDIV1_OUTDIV1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV1) & BM_SIM_CLKDIV1_OUTDIV1)
Kojto	90:cb3d968589d8	3479
Kojto	90:cb3d968589d8	3480	/! @brief Set the OUTDIV1 field to a new value. /
Kojto	90:cb3d968589d8	3481	#define BW_SIM_CLKDIV1_OUTDIV1(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV1) \| BF_SIM_CLKDIV1_OUTDIV1(v)))
Kojto	90:cb3d968589d8	3482	/@}/
Kojto	90:cb3d968589d8	3483
Kojto	90:cb3d968589d8	3484	/*******************************************************************************
Kojto	90:cb3d968589d8	3485	* HW_SIM_CLKDIV2 - System Clock Divider Register 2
Kojto	90:cb3d968589d8	3486	******************************************************************************/
Kojto	90:cb3d968589d8	3487
Kojto	90:cb3d968589d8	3488	/*!
Kojto	90:cb3d968589d8	3489	* @brief HW_SIM_CLKDIV2 - System Clock Divider Register 2 (RW)
Kojto	90:cb3d968589d8	3490	*
Kojto	90:cb3d968589d8	3491	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	3492	*/
Kojto	90:cb3d968589d8	3493	typedef union _hw_sim_clkdiv2
Kojto	90:cb3d968589d8	3494	{
Kojto	90:cb3d968589d8	3495	uint32_t U;
Kojto	90:cb3d968589d8	3496	struct _hw_sim_clkdiv2_bitfields
Kojto	90:cb3d968589d8	3497	{
Kojto	90:cb3d968589d8	3498	uint32_t USBFRAC : 1; /!< [0] USB clock divider fraction /
Kojto	90:cb3d968589d8	3499	uint32_t USBDIV : 3; /!< [3:1] USB clock divider divisor /
Kojto	90:cb3d968589d8	3500	uint32_t RESERVED0 : 28; /!< [31:4] /
Kojto	90:cb3d968589d8	3501	} B;
Kojto	90:cb3d968589d8	3502	} hw_sim_clkdiv2_t;
Kojto	90:cb3d968589d8	3503
Kojto	90:cb3d968589d8	3504	/*!
Kojto	90:cb3d968589d8	3505	* @name Constants and macros for entire SIM_CLKDIV2 register
Kojto	90:cb3d968589d8	3506	*/
Kojto	90:cb3d968589d8	3507	/@{/
Kojto	90:cb3d968589d8	3508	#define HW_SIM_CLKDIV2_ADDR(x) ((x) + 0x1048U)
Kojto	90:cb3d968589d8	3509
Kojto	90:cb3d968589d8	3510	#define HW_SIM_CLKDIV2(x) ((__IO hw_sim_clkdiv2_t ) HW_SIM_CLKDIV2_ADDR(x))
Kojto	90:cb3d968589d8	3511	#define HW_SIM_CLKDIV2_RD(x) (HW_SIM_CLKDIV2(x).U)
Kojto	90:cb3d968589d8	3512	#define HW_SIM_CLKDIV2_WR(x, v) (HW_SIM_CLKDIV2(x).U = (v))
Kojto	90:cb3d968589d8	3513	#define HW_SIM_CLKDIV2_SET(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) \| (v)))
Kojto	90:cb3d968589d8	3514	#define HW_SIM_CLKDIV2_CLR(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	3515	#define HW_SIM_CLKDIV2_TOG(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	3516	/@}/
Kojto	90:cb3d968589d8	3517
Kojto	90:cb3d968589d8	3518	/*
Kojto	90:cb3d968589d8	3519	* Constants & macros for individual SIM_CLKDIV2 bitfields
Kojto	90:cb3d968589d8	3520	*/
Kojto	90:cb3d968589d8	3521
Kojto	90:cb3d968589d8	3522	/*!
Kojto	90:cb3d968589d8	3523	* @name Register SIM_CLKDIV2, field USBFRAC[0] (RW)
Kojto	90:cb3d968589d8	3524	*
Kojto	90:cb3d968589d8	3525	* This field sets the fraction multiply value for the fractional clock divider
Kojto	90:cb3d968589d8	3526	* when the MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] =
Kojto	90:cb3d968589d8	3527	* 1). Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
Kojto	90:cb3d968589d8	3528	*/
Kojto	90:cb3d968589d8	3529	/@{/
Kojto	90:cb3d968589d8	3530	#define BP_SIM_CLKDIV2_USBFRAC (0U) /!< Bit position for SIM_CLKDIV2_USBFRAC. /
Kojto	90:cb3d968589d8	3531	#define BM_SIM_CLKDIV2_USBFRAC (0x00000001U) /!< Bit mask for SIM_CLKDIV2_USBFRAC. /
Kojto	90:cb3d968589d8	3532	#define BS_SIM_CLKDIV2_USBFRAC (1U) /!< Bit field size in bits for SIM_CLKDIV2_USBFRAC. /
Kojto	90:cb3d968589d8	3533
Kojto	90:cb3d968589d8	3534	/! @brief Read current value of the SIM_CLKDIV2_USBFRAC field. /
Kojto	90:cb3d968589d8	3535	#define BR_SIM_CLKDIV2_USBFRAC(x) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR(x), BP_SIM_CLKDIV2_USBFRAC))
Kojto	90:cb3d968589d8	3536
Kojto	90:cb3d968589d8	3537	/! @brief Format value for bitfield SIM_CLKDIV2_USBFRAC. /
Kojto	90:cb3d968589d8	3538	#define BF_SIM_CLKDIV2_USBFRAC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV2_USBFRAC) & BM_SIM_CLKDIV2_USBFRAC)
Kojto	90:cb3d968589d8	3539
Kojto	90:cb3d968589d8	3540	/! @brief Set the USBFRAC field to a new value. /
Kojto	90:cb3d968589d8	3541	#define BW_SIM_CLKDIV2_USBFRAC(x, v) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR(x), BP_SIM_CLKDIV2_USBFRAC) = (v))
Kojto	90:cb3d968589d8	3542	/@}/
Kojto	90:cb3d968589d8	3543
Kojto	90:cb3d968589d8	3544	/*!
Kojto	90:cb3d968589d8	3545	* @name Register SIM_CLKDIV2, field USBDIV[3:1] (RW)
Kojto	90:cb3d968589d8	3546	*
Kojto	90:cb3d968589d8	3547	* This field sets the divide value for the fractional clock divider when the
Kojto	90:cb3d968589d8	3548	* MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider
Kojto	90:cb3d968589d8	3549	* output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
Kojto	90:cb3d968589d8	3550	*/
Kojto	90:cb3d968589d8	3551	/@{/
Kojto	90:cb3d968589d8	3552	#define BP_SIM_CLKDIV2_USBDIV (1U) /!< Bit position for SIM_CLKDIV2_USBDIV. /
Kojto	90:cb3d968589d8	3553	#define BM_SIM_CLKDIV2_USBDIV (0x0000000EU) /!< Bit mask for SIM_CLKDIV2_USBDIV. /
Kojto	90:cb3d968589d8	3554	#define BS_SIM_CLKDIV2_USBDIV (3U) /!< Bit field size in bits for SIM_CLKDIV2_USBDIV. /
Kojto	90:cb3d968589d8	3555
Kojto	90:cb3d968589d8	3556	/! @brief Read current value of the SIM_CLKDIV2_USBDIV field. /
Kojto	90:cb3d968589d8	3557	#define BR_SIM_CLKDIV2_USBDIV(x) (HW_SIM_CLKDIV2(x).B.USBDIV)
Kojto	90:cb3d968589d8	3558
Kojto	90:cb3d968589d8	3559	/! @brief Format value for bitfield SIM_CLKDIV2_USBDIV. /
Kojto	90:cb3d968589d8	3560	#define BF_SIM_CLKDIV2_USBDIV(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV2_USBDIV) & BM_SIM_CLKDIV2_USBDIV)
Kojto	90:cb3d968589d8	3561
Kojto	90:cb3d968589d8	3562	/! @brief Set the USBDIV field to a new value. /
Kojto	90:cb3d968589d8	3563	#define BW_SIM_CLKDIV2_USBDIV(x, v) (HW_SIM_CLKDIV2_WR(x, (HW_SIM_CLKDIV2_RD(x) & ~BM_SIM_CLKDIV2_USBDIV) \| BF_SIM_CLKDIV2_USBDIV(v)))
Kojto	90:cb3d968589d8	3564	/@}/
Kojto	90:cb3d968589d8	3565
Kojto	90:cb3d968589d8	3566	/*******************************************************************************
Kojto	90:cb3d968589d8	3567	* HW_SIM_FCFG1 - Flash Configuration Register 1
Kojto	90:cb3d968589d8	3568	******************************************************************************/
Kojto	90:cb3d968589d8	3569
Kojto	90:cb3d968589d8	3570	/*!
Kojto	90:cb3d968589d8	3571	* @brief HW_SIM_FCFG1 - Flash Configuration Register 1 (RW)
Kojto	90:cb3d968589d8	3572	*
Kojto	90:cb3d968589d8	3573	* Reset value: 0xFF0F0F00U
Kojto	90:cb3d968589d8	3574	*
Kojto	90:cb3d968589d8	3575	* For devices with FlexNVM: The reset value of EESIZE and DEPART are based on
Kojto	90:cb3d968589d8	3576	* user programming in user IFR via the PGMPART flash command. For devices with
Kojto	90:cb3d968589d8	3577	* program flash only:
Kojto	90:cb3d968589d8	3578	*/
Kojto	90:cb3d968589d8	3579	typedef union _hw_sim_fcfg1
Kojto	90:cb3d968589d8	3580	{
Kojto	90:cb3d968589d8	3581	uint32_t U;
Kojto	90:cb3d968589d8	3582	struct _hw_sim_fcfg1_bitfields
Kojto	90:cb3d968589d8	3583	{
Kojto	90:cb3d968589d8	3584	uint32_t FLASHDIS : 1; /!< [0] Flash Disable /
Kojto	90:cb3d968589d8	3585	uint32_t FLASHDOZE : 1; /!< [1] Flash Doze /
Kojto	90:cb3d968589d8	3586	uint32_t RESERVED0 : 6; /!< [7:2] /
Kojto	90:cb3d968589d8	3587	uint32_t DEPART : 4; /!< [11:8] FlexNVM partition /
Kojto	90:cb3d968589d8	3588	uint32_t RESERVED1 : 4; /!< [15:12] /
Kojto	90:cb3d968589d8	3589	uint32_t EESIZE : 4; /!< [19:16] EEPROM size /
Kojto	90:cb3d968589d8	3590	uint32_t RESERVED2 : 4; /!< [23:20] /
Kojto	90:cb3d968589d8	3591	uint32_t PFSIZE : 4; /!< [27:24] Program flash size /
Kojto	90:cb3d968589d8	3592	uint32_t NVMSIZE : 4; /!< [31:28] FlexNVM size /
Kojto	90:cb3d968589d8	3593	} B;
Kojto	90:cb3d968589d8	3594	} hw_sim_fcfg1_t;
Kojto	90:cb3d968589d8	3595
Kojto	90:cb3d968589d8	3596	/*!
Kojto	90:cb3d968589d8	3597	* @name Constants and macros for entire SIM_FCFG1 register
Kojto	90:cb3d968589d8	3598	*/
Kojto	90:cb3d968589d8	3599	/@{/
Kojto	90:cb3d968589d8	3600	#define HW_SIM_FCFG1_ADDR(x) ((x) + 0x104CU)
Kojto	90:cb3d968589d8	3601
Kojto	90:cb3d968589d8	3602	#define HW_SIM_FCFG1(x) ((__IO hw_sim_fcfg1_t ) HW_SIM_FCFG1_ADDR(x))
Kojto	90:cb3d968589d8	3603	#define HW_SIM_FCFG1_RD(x) (HW_SIM_FCFG1(x).U)
Kojto	90:cb3d968589d8	3604	#define HW_SIM_FCFG1_WR(x, v) (HW_SIM_FCFG1(x).U = (v))
Kojto	90:cb3d968589d8	3605	#define HW_SIM_FCFG1_SET(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) \| (v)))
Kojto	90:cb3d968589d8	3606	#define HW_SIM_FCFG1_CLR(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	3607	#define HW_SIM_FCFG1_TOG(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	3608	/@}/
Kojto	90:cb3d968589d8	3609
Kojto	90:cb3d968589d8	3610	/*
Kojto	90:cb3d968589d8	3611	* Constants & macros for individual SIM_FCFG1 bitfields
Kojto	90:cb3d968589d8	3612	*/
Kojto	90:cb3d968589d8	3613
Kojto	90:cb3d968589d8	3614	/*!
Kojto	90:cb3d968589d8	3615	* @name Register SIM_FCFG1, field FLASHDIS[0] (RW)
Kojto	90:cb3d968589d8	3616	*
Kojto	90:cb3d968589d8	3617	* Flash accesses are disabled (and generate a bus error) and the Flash memory
Kojto	90:cb3d968589d8	3618	* is placed in a low power state. This bit should not be changed during VLP
Kojto	90:cb3d968589d8	3619	* modes. Relocate the interrupt vectors out of Flash memory before disabling the
Kojto	90:cb3d968589d8	3620	* Flash.
Kojto	90:cb3d968589d8	3621	*
Kojto	90:cb3d968589d8	3622	* Values:
Kojto	90:cb3d968589d8	3623	* - 0 - Flash is enabled
Kojto	90:cb3d968589d8	3624	* - 1 - Flash is disabled
Kojto	90:cb3d968589d8	3625	*/
Kojto	90:cb3d968589d8	3626	/@{/
Kojto	90:cb3d968589d8	3627	#define BP_SIM_FCFG1_FLASHDIS (0U) /!< Bit position for SIM_FCFG1_FLASHDIS. /
Kojto	90:cb3d968589d8	3628	#define BM_SIM_FCFG1_FLASHDIS (0x00000001U) /!< Bit mask for SIM_FCFG1_FLASHDIS. /
Kojto	90:cb3d968589d8	3629	#define BS_SIM_FCFG1_FLASHDIS (1U) /!< Bit field size in bits for SIM_FCFG1_FLASHDIS. /
Kojto	90:cb3d968589d8	3630
Kojto	90:cb3d968589d8	3631	/! @brief Read current value of the SIM_FCFG1_FLASHDIS field. /
Kojto	90:cb3d968589d8	3632	#define BR_SIM_FCFG1_FLASHDIS(x) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDIS))
Kojto	90:cb3d968589d8	3633
Kojto	90:cb3d968589d8	3634	/! @brief Format value for bitfield SIM_FCFG1_FLASHDIS. /
Kojto	90:cb3d968589d8	3635	#define BF_SIM_FCFG1_FLASHDIS(v) ((uint32_t)((uint32_t)(v) << BP_SIM_FCFG1_FLASHDIS) & BM_SIM_FCFG1_FLASHDIS)
Kojto	90:cb3d968589d8	3636
Kojto	90:cb3d968589d8	3637	/! @brief Set the FLASHDIS field to a new value. /
Kojto	90:cb3d968589d8	3638	#define BW_SIM_FCFG1_FLASHDIS(x, v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDIS) = (v))
Kojto	90:cb3d968589d8	3639	/@}/
Kojto	90:cb3d968589d8	3640
Kojto	90:cb3d968589d8	3641	/*!
Kojto	90:cb3d968589d8	3642	* @name Register SIM_FCFG1, field FLASHDOZE[1] (RW)
Kojto	90:cb3d968589d8	3643	*
Kojto	90:cb3d968589d8	3644	* When set, Flash memory is disabled for the duration of Wait mode. An attempt
Kojto	90:cb3d968589d8	3645	* by the DMA or other bus master to access the Flash when the Flash is disabled
Kojto	90:cb3d968589d8	3646	* will result in a bus error. This bit should be clear during VLP modes. The
Kojto	90:cb3d968589d8	3647	* Flash will be automatically enabled again at the end of Wait mode so interrupt
Kojto	90:cb3d968589d8	3648	* vectors do not need to be relocated out of Flash memory. The wakeup time from
Kojto	90:cb3d968589d8	3649	* Wait mode is extended when this bit is set.
Kojto	90:cb3d968589d8	3650	*
Kojto	90:cb3d968589d8	3651	* Values:
Kojto	90:cb3d968589d8	3652	* - 0 - Flash remains enabled during Wait mode
Kojto	90:cb3d968589d8	3653	* - 1 - Flash is disabled for the duration of Wait mode
Kojto	90:cb3d968589d8	3654	*/
Kojto	90:cb3d968589d8	3655	/@{/
Kojto	90:cb3d968589d8	3656	#define BP_SIM_FCFG1_FLASHDOZE (1U) /!< Bit position for SIM_FCFG1_FLASHDOZE. /
Kojto	90:cb3d968589d8	3657	#define BM_SIM_FCFG1_FLASHDOZE (0x00000002U) /!< Bit mask for SIM_FCFG1_FLASHDOZE. /
Kojto	90:cb3d968589d8	3658	#define BS_SIM_FCFG1_FLASHDOZE (1U) /!< Bit field size in bits for SIM_FCFG1_FLASHDOZE. /
Kojto	90:cb3d968589d8	3659
Kojto	90:cb3d968589d8	3660	/! @brief Read current value of the SIM_FCFG1_FLASHDOZE field. /
Kojto	90:cb3d968589d8	3661	#define BR_SIM_FCFG1_FLASHDOZE(x) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDOZE))
Kojto	90:cb3d968589d8	3662
Kojto	90:cb3d968589d8	3663	/! @brief Format value for bitfield SIM_FCFG1_FLASHDOZE. /
Kojto	90:cb3d968589d8	3664	#define BF_SIM_FCFG1_FLASHDOZE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_FCFG1_FLASHDOZE) & BM_SIM_FCFG1_FLASHDOZE)
Kojto	90:cb3d968589d8	3665
Kojto	90:cb3d968589d8	3666	/! @brief Set the FLASHDOZE field to a new value. /
Kojto	90:cb3d968589d8	3667	#define BW_SIM_FCFG1_FLASHDOZE(x, v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDOZE) = (v))
Kojto	90:cb3d968589d8	3668	/@}/
Kojto	90:cb3d968589d8	3669
Kojto	90:cb3d968589d8	3670	/*!
Kojto	90:cb3d968589d8	3671	* @name Register SIM_FCFG1, field DEPART[11:8] (RO)
Kojto	90:cb3d968589d8	3672	*
Kojto	90:cb3d968589d8	3673	* For devices with FlexNVM: Data flash / EEPROM backup split . See DEPART bit
Kojto	90:cb3d968589d8	3674	* description in FTFE chapter. For devices without FlexNVM: Reserved
Kojto	90:cb3d968589d8	3675	*/
Kojto	90:cb3d968589d8	3676	/@{/
Kojto	90:cb3d968589d8	3677	#define BP_SIM_FCFG1_DEPART (8U) /!< Bit position for SIM_FCFG1_DEPART. /
Kojto	90:cb3d968589d8	3678	#define BM_SIM_FCFG1_DEPART (0x00000F00U) /!< Bit mask for SIM_FCFG1_DEPART. /
Kojto	90:cb3d968589d8	3679	#define BS_SIM_FCFG1_DEPART (4U) /!< Bit field size in bits for SIM_FCFG1_DEPART. /
Kojto	90:cb3d968589d8	3680
Kojto	90:cb3d968589d8	3681	/! @brief Read current value of the SIM_FCFG1_DEPART field. /
Kojto	90:cb3d968589d8	3682	#define BR_SIM_FCFG1_DEPART(x) (HW_SIM_FCFG1(x).B.DEPART)
Kojto	90:cb3d968589d8	3683	/@}/
Kojto	90:cb3d968589d8	3684
Kojto	90:cb3d968589d8	3685	/*!
Kojto	90:cb3d968589d8	3686	* @name Register SIM_FCFG1, field EESIZE[19:16] (RO)
Kojto	90:cb3d968589d8	3687	*
Kojto	90:cb3d968589d8	3688	* EEPROM data size .
Kojto	90:cb3d968589d8	3689	*
Kojto	90:cb3d968589d8	3690	* Values:
Kojto	90:cb3d968589d8	3691	* - 0000 - 16 KB
Kojto	90:cb3d968589d8	3692	* - 0001 - 8 KB
Kojto	90:cb3d968589d8	3693	* - 0010 - 4 KB
Kojto	90:cb3d968589d8	3694	* - 0011 - 2 KB
Kojto	90:cb3d968589d8	3695	* - 0100 - 1 KB
Kojto	90:cb3d968589d8	3696	* - 0101 - 512 Bytes
Kojto	90:cb3d968589d8	3697	* - 0110 - 256 Bytes
Kojto	90:cb3d968589d8	3698	* - 0111 - 128 Bytes
Kojto	90:cb3d968589d8	3699	* - 1000 - 64 Bytes
Kojto	90:cb3d968589d8	3700	* - 1001 - 32 Bytes
Kojto	90:cb3d968589d8	3701	* - 1111 - 0 Bytes
Kojto	90:cb3d968589d8	3702	*/
Kojto	90:cb3d968589d8	3703	/@{/
Kojto	90:cb3d968589d8	3704	#define BP_SIM_FCFG1_EESIZE (16U) /!< Bit position for SIM_FCFG1_EESIZE. /
Kojto	90:cb3d968589d8	3705	#define BM_SIM_FCFG1_EESIZE (0x000F0000U) /!< Bit mask for SIM_FCFG1_EESIZE. /
Kojto	90:cb3d968589d8	3706	#define BS_SIM_FCFG1_EESIZE (4U) /!< Bit field size in bits for SIM_FCFG1_EESIZE. /
Kojto	90:cb3d968589d8	3707
Kojto	90:cb3d968589d8	3708	/! @brief Read current value of the SIM_FCFG1_EESIZE field. /
Kojto	90:cb3d968589d8	3709	#define BR_SIM_FCFG1_EESIZE(x) (HW_SIM_FCFG1(x).B.EESIZE)
Kojto	90:cb3d968589d8	3710	/@}/
Kojto	90:cb3d968589d8	3711
Kojto	90:cb3d968589d8	3712	/*!
Kojto	90:cb3d968589d8	3713	* @name Register SIM_FCFG1, field PFSIZE[27:24] (RO)
Kojto	90:cb3d968589d8	3714	*
Kojto	90:cb3d968589d8	3715	* This field specifies the amount of program flash memory available on the
Kojto	90:cb3d968589d8	3716	* device . Undefined values are reserved.
Kojto	90:cb3d968589d8	3717	*
Kojto	90:cb3d968589d8	3718	* Values:
Kojto	90:cb3d968589d8	3719	* - 0011 - 32 KB of program flash memory
Kojto	90:cb3d968589d8	3720	* - 0101 - 64 KB of program flash memory
Kojto	90:cb3d968589d8	3721	* - 0111 - 128 KB of program flash memory
Kojto	90:cb3d968589d8	3722	* - 1001 - 256 KB of program flash memory
Kojto	90:cb3d968589d8	3723	* - 1011 - 512 KB of program flash memory
Kojto	90:cb3d968589d8	3724	* - 1101 - 1024 KB of program flash memory
Kojto	90:cb3d968589d8	3725	* - 1111 - 1024 KB of program flash memory
Kojto	90:cb3d968589d8	3726	*/
Kojto	90:cb3d968589d8	3727	/@{/
Kojto	90:cb3d968589d8	3728	#define BP_SIM_FCFG1_PFSIZE (24U) /!< Bit position for SIM_FCFG1_PFSIZE. /
Kojto	90:cb3d968589d8	3729	#define BM_SIM_FCFG1_PFSIZE (0x0F000000U) /!< Bit mask for SIM_FCFG1_PFSIZE. /
Kojto	90:cb3d968589d8	3730	#define BS_SIM_FCFG1_PFSIZE (4U) /!< Bit field size in bits for SIM_FCFG1_PFSIZE. /
Kojto	90:cb3d968589d8	3731
Kojto	90:cb3d968589d8	3732	/! @brief Read current value of the SIM_FCFG1_PFSIZE field. /
Kojto	90:cb3d968589d8	3733	#define BR_SIM_FCFG1_PFSIZE(x) (HW_SIM_FCFG1(x).B.PFSIZE)
Kojto	90:cb3d968589d8	3734	/@}/
Kojto	90:cb3d968589d8	3735
Kojto	90:cb3d968589d8	3736	/*!
Kojto	90:cb3d968589d8	3737	* @name Register SIM_FCFG1, field NVMSIZE[31:28] (RO)
Kojto	90:cb3d968589d8	3738	*
Kojto	90:cb3d968589d8	3739	* This field specifies the amount of FlexNVM memory available on the device .
Kojto	90:cb3d968589d8	3740	* Undefined values are reserved.
Kojto	90:cb3d968589d8	3741	*
Kojto	90:cb3d968589d8	3742	* Values:
Kojto	90:cb3d968589d8	3743	* - 0000 - 0 KB of FlexNVM
Kojto	90:cb3d968589d8	3744	* - 0011 - 32 KB of FlexNVM
Kojto	90:cb3d968589d8	3745	* - 0101 - 64 KB of FlexNVM
Kojto	90:cb3d968589d8	3746	* - 0111 - 128 KB of FlexNVM
Kojto	90:cb3d968589d8	3747	* - 1001 - 256 KB of FlexNVM
Kojto	90:cb3d968589d8	3748	* - 1011 - 512 KB of FlexNVM
Kojto	90:cb3d968589d8	3749	* - 1111 - 512 KB of FlexNVM
Kojto	90:cb3d968589d8	3750	*/
Kojto	90:cb3d968589d8	3751	/@{/
Kojto	90:cb3d968589d8	3752	#define BP_SIM_FCFG1_NVMSIZE (28U) /!< Bit position for SIM_FCFG1_NVMSIZE. /
Kojto	90:cb3d968589d8	3753	#define BM_SIM_FCFG1_NVMSIZE (0xF0000000U) /!< Bit mask for SIM_FCFG1_NVMSIZE. /
Kojto	90:cb3d968589d8	3754	#define BS_SIM_FCFG1_NVMSIZE (4U) /!< Bit field size in bits for SIM_FCFG1_NVMSIZE. /
Kojto	90:cb3d968589d8	3755
Kojto	90:cb3d968589d8	3756	/! @brief Read current value of the SIM_FCFG1_NVMSIZE field. /
Kojto	90:cb3d968589d8	3757	#define BR_SIM_FCFG1_NVMSIZE(x) (HW_SIM_FCFG1(x).B.NVMSIZE)
Kojto	90:cb3d968589d8	3758	/@}/
Kojto	90:cb3d968589d8	3759
Kojto	90:cb3d968589d8	3760	/*******************************************************************************
Kojto	90:cb3d968589d8	3761	* HW_SIM_FCFG2 - Flash Configuration Register 2
Kojto	90:cb3d968589d8	3762	******************************************************************************/
Kojto	90:cb3d968589d8	3763
Kojto	90:cb3d968589d8	3764	/*!
Kojto	90:cb3d968589d8	3765	* @brief HW_SIM_FCFG2 - Flash Configuration Register 2 (RO)
Kojto	90:cb3d968589d8	3766	*
Kojto	90:cb3d968589d8	3767	* Reset value: 0x7F7F0000U
Kojto	90:cb3d968589d8	3768	*/
Kojto	90:cb3d968589d8	3769	typedef union _hw_sim_fcfg2
Kojto	90:cb3d968589d8	3770	{
Kojto	90:cb3d968589d8	3771	uint32_t U;
Kojto	90:cb3d968589d8	3772	struct _hw_sim_fcfg2_bitfields
Kojto	90:cb3d968589d8	3773	{
Kojto	90:cb3d968589d8	3774	uint32_t RESERVED0 : 16; /!< [15:0] /
Kojto	90:cb3d968589d8	3775	uint32_t MAXADDR1 : 7; /!< [22:16] Max address block 1 /
Kojto	90:cb3d968589d8	3776	uint32_t PFLSH : 1; /!< [23] Program flash only /
Kojto	90:cb3d968589d8	3777	uint32_t MAXADDR0 : 7; /!< [30:24] Max address block 0 /
Kojto	90:cb3d968589d8	3778	uint32_t RESERVED1 : 1; /!< [31] /
Kojto	90:cb3d968589d8	3779	} B;
Kojto	90:cb3d968589d8	3780	} hw_sim_fcfg2_t;
Kojto	90:cb3d968589d8	3781
Kojto	90:cb3d968589d8	3782	/*!
Kojto	90:cb3d968589d8	3783	* @name Constants and macros for entire SIM_FCFG2 register
Kojto	90:cb3d968589d8	3784	*/
Kojto	90:cb3d968589d8	3785	/@{/
Kojto	90:cb3d968589d8	3786	#define HW_SIM_FCFG2_ADDR(x) ((x) + 0x1050U)
Kojto	90:cb3d968589d8	3787
Kojto	90:cb3d968589d8	3788	#define HW_SIM_FCFG2(x) ((__I hw_sim_fcfg2_t ) HW_SIM_FCFG2_ADDR(x))
Kojto	90:cb3d968589d8	3789	#define HW_SIM_FCFG2_RD(x) (HW_SIM_FCFG2(x).U)
Kojto	90:cb3d968589d8	3790	/@}/
Kojto	90:cb3d968589d8	3791
Kojto	90:cb3d968589d8	3792	/*
Kojto	90:cb3d968589d8	3793	* Constants & macros for individual SIM_FCFG2 bitfields
Kojto	90:cb3d968589d8	3794	*/
Kojto	90:cb3d968589d8	3795
Kojto	90:cb3d968589d8	3796	/*!
Kojto	90:cb3d968589d8	3797	* @name Register SIM_FCFG2, field MAXADDR1[22:16] (RO)
Kojto	90:cb3d968589d8	3798	*
Kojto	90:cb3d968589d8	3799	* For devices with FlexNVM: This field concatenated with 13 trailing zeros plus
Kojto	90:cb3d968589d8	3800	* the FlexNVM base address indicates the first invalid address of the FlexNVM
Kojto	90:cb3d968589d8	3801	* flash block. For example, if MAXADDR1 = 0x20 the first invalid address of
Kojto	90:cb3d968589d8	3802	* FlexNVM flash block is 0x4_0000 + 0x1000_0000 . This would be the MAXADDR1 value
Kojto	90:cb3d968589d8	3803	* for a device with 256 KB FlexNVM. For devices with program flash only: This
Kojto	90:cb3d968589d8	3804	* field equals zero if there is only one program flash block, otherwise it equals
Kojto	90:cb3d968589d8	3805	* the value of the MAXADDR0 field. For example, with MAXADDR0 = MAXADDR1 = 0x20
Kojto	90:cb3d968589d8	3806	* the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. This would be
Kojto	90:cb3d968589d8	3807	* the MAXADDR1 value for a device with 512 KB program flash memory across two
Kojto	90:cb3d968589d8	3808	* flash blocks and no FlexNVM.
Kojto	90:cb3d968589d8	3809	*/
Kojto	90:cb3d968589d8	3810	/@{/
Kojto	90:cb3d968589d8	3811	#define BP_SIM_FCFG2_MAXADDR1 (16U) /!< Bit position for SIM_FCFG2_MAXADDR1. /
Kojto	90:cb3d968589d8	3812	#define BM_SIM_FCFG2_MAXADDR1 (0x007F0000U) /!< Bit mask for SIM_FCFG2_MAXADDR1. /
Kojto	90:cb3d968589d8	3813	#define BS_SIM_FCFG2_MAXADDR1 (7U) /!< Bit field size in bits for SIM_FCFG2_MAXADDR1. /
Kojto	90:cb3d968589d8	3814
Kojto	90:cb3d968589d8	3815	/! @brief Read current value of the SIM_FCFG2_MAXADDR1 field. /
Kojto	90:cb3d968589d8	3816	#define BR_SIM_FCFG2_MAXADDR1(x) (HW_SIM_FCFG2(x).B.MAXADDR1)
Kojto	90:cb3d968589d8	3817	/@}/
Kojto	90:cb3d968589d8	3818
Kojto	90:cb3d968589d8	3819	/*!
Kojto	90:cb3d968589d8	3820	* @name Register SIM_FCFG2, field PFLSH[23] (RO)
Kojto	90:cb3d968589d8	3821	*
Kojto	90:cb3d968589d8	3822	* For devices with FlexNVM, this bit is always clear. For devices without
Kojto	90:cb3d968589d8	3823	* FlexNVM, this bit is always set.
Kojto	90:cb3d968589d8	3824	*
Kojto	90:cb3d968589d8	3825	* Values:
Kojto	90:cb3d968589d8	3826	* - 0 - Device supports FlexNVM
Kojto	90:cb3d968589d8	3827	* - 1 - Program Flash only, device does not support FlexNVM
Kojto	90:cb3d968589d8	3828	*/
Kojto	90:cb3d968589d8	3829	/@{/
Kojto	90:cb3d968589d8	3830	#define BP_SIM_FCFG2_PFLSH (23U) /!< Bit position for SIM_FCFG2_PFLSH. /
Kojto	90:cb3d968589d8	3831	#define BM_SIM_FCFG2_PFLSH (0x00800000U) /!< Bit mask for SIM_FCFG2_PFLSH. /
Kojto	90:cb3d968589d8	3832	#define BS_SIM_FCFG2_PFLSH (1U) /!< Bit field size in bits for SIM_FCFG2_PFLSH. /
Kojto	90:cb3d968589d8	3833
Kojto	90:cb3d968589d8	3834	/! @brief Read current value of the SIM_FCFG2_PFLSH field. /
Kojto	90:cb3d968589d8	3835	#define BR_SIM_FCFG2_PFLSH(x) (BITBAND_ACCESS32(HW_SIM_FCFG2_ADDR(x), BP_SIM_FCFG2_PFLSH))
Kojto	90:cb3d968589d8	3836	/@}/
Kojto	90:cb3d968589d8	3837
Kojto	90:cb3d968589d8	3838	/*!
Kojto	90:cb3d968589d8	3839	* @name Register SIM_FCFG2, field MAXADDR0[30:24] (RO)
Kojto	90:cb3d968589d8	3840	*
Kojto	90:cb3d968589d8	3841	* This field concatenated with 13 trailing zeros indicates the first invalid
Kojto	90:cb3d968589d8	3842	* address of each program flash block. For example, if MAXADDR0 = 0x20 the first
Kojto	90:cb3d968589d8	3843	* invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0
Kojto	90:cb3d968589d8	3844	* value for a device with 256 KB program flash in flash block 0.
Kojto	90:cb3d968589d8	3845	*/
Kojto	90:cb3d968589d8	3846	/@{/
Kojto	90:cb3d968589d8	3847	#define BP_SIM_FCFG2_MAXADDR0 (24U) /!< Bit position for SIM_FCFG2_MAXADDR0. /
Kojto	90:cb3d968589d8	3848	#define BM_SIM_FCFG2_MAXADDR0 (0x7F000000U) /!< Bit mask for SIM_FCFG2_MAXADDR0. /
Kojto	90:cb3d968589d8	3849	#define BS_SIM_FCFG2_MAXADDR0 (7U) /!< Bit field size in bits for SIM_FCFG2_MAXADDR0. /
Kojto	90:cb3d968589d8	3850
Kojto	90:cb3d968589d8	3851	/! @brief Read current value of the SIM_FCFG2_MAXADDR0 field. /
Kojto	90:cb3d968589d8	3852	#define BR_SIM_FCFG2_MAXADDR0(x) (HW_SIM_FCFG2(x).B.MAXADDR0)
Kojto	90:cb3d968589d8	3853	/@}/
Kojto	90:cb3d968589d8	3854
Kojto	90:cb3d968589d8	3855	/*******************************************************************************
Kojto	90:cb3d968589d8	3856	* HW_SIM_UIDH - Unique Identification Register High
Kojto	90:cb3d968589d8	3857	******************************************************************************/
Kojto	90:cb3d968589d8	3858
Kojto	90:cb3d968589d8	3859	/*!
Kojto	90:cb3d968589d8	3860	* @brief HW_SIM_UIDH - Unique Identification Register High (RO)
Kojto	90:cb3d968589d8	3861	*
Kojto	90:cb3d968589d8	3862	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	3863	*/
Kojto	90:cb3d968589d8	3864	typedef union _hw_sim_uidh
Kojto	90:cb3d968589d8	3865	{
Kojto	90:cb3d968589d8	3866	uint32_t U;
Kojto	90:cb3d968589d8	3867	struct _hw_sim_uidh_bitfields
Kojto	90:cb3d968589d8	3868	{
Kojto	90:cb3d968589d8	3869	uint32_t UID : 32; /!< [31:0] Unique Identification /
Kojto	90:cb3d968589d8	3870	} B;
Kojto	90:cb3d968589d8	3871	} hw_sim_uidh_t;
Kojto	90:cb3d968589d8	3872
Kojto	90:cb3d968589d8	3873	/*!
Kojto	90:cb3d968589d8	3874	* @name Constants and macros for entire SIM_UIDH register
Kojto	90:cb3d968589d8	3875	*/
Kojto	90:cb3d968589d8	3876	/@{/
Kojto	90:cb3d968589d8	3877	#define HW_SIM_UIDH_ADDR(x) ((x) + 0x1054U)
Kojto	90:cb3d968589d8	3878
Kojto	90:cb3d968589d8	3879	#define HW_SIM_UIDH(x) ((__I hw_sim_uidh_t ) HW_SIM_UIDH_ADDR(x))
Kojto	90:cb3d968589d8	3880	#define HW_SIM_UIDH_RD(x) (HW_SIM_UIDH(x).U)
Kojto	90:cb3d968589d8	3881	/@}/
Kojto	90:cb3d968589d8	3882
Kojto	90:cb3d968589d8	3883	/*
Kojto	90:cb3d968589d8	3884	* Constants & macros for individual SIM_UIDH bitfields
Kojto	90:cb3d968589d8	3885	*/
Kojto	90:cb3d968589d8	3886
Kojto	90:cb3d968589d8	3887	/*!
Kojto	90:cb3d968589d8	3888	* @name Register SIM_UIDH, field UID[31:0] (RO)
Kojto	90:cb3d968589d8	3889	*
Kojto	90:cb3d968589d8	3890	* Unique identification for the device.
Kojto	90:cb3d968589d8	3891	*/
Kojto	90:cb3d968589d8	3892	/@{/
Kojto	90:cb3d968589d8	3893	#define BP_SIM_UIDH_UID (0U) /!< Bit position for SIM_UIDH_UID. /
Kojto	90:cb3d968589d8	3894	#define BM_SIM_UIDH_UID (0xFFFFFFFFU) /!< Bit mask for SIM_UIDH_UID. /
Kojto	90:cb3d968589d8	3895	#define BS_SIM_UIDH_UID (32U) /!< Bit field size in bits for SIM_UIDH_UID. /
Kojto	90:cb3d968589d8	3896
Kojto	90:cb3d968589d8	3897	/! @brief Read current value of the SIM_UIDH_UID field. /
Kojto	90:cb3d968589d8	3898	#define BR_SIM_UIDH_UID(x) (HW_SIM_UIDH(x).U)
Kojto	90:cb3d968589d8	3899	/@}/
Kojto	90:cb3d968589d8	3900
Kojto	90:cb3d968589d8	3901	/*******************************************************************************
Kojto	90:cb3d968589d8	3902	* HW_SIM_UIDMH - Unique Identification Register Mid-High
Kojto	90:cb3d968589d8	3903	******************************************************************************/
Kojto	90:cb3d968589d8	3904
Kojto	90:cb3d968589d8	3905	/*!
Kojto	90:cb3d968589d8	3906	* @brief HW_SIM_UIDMH - Unique Identification Register Mid-High (RO)
Kojto	90:cb3d968589d8	3907	*
Kojto	90:cb3d968589d8	3908	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	3909	*/
Kojto	90:cb3d968589d8	3910	typedef union _hw_sim_uidmh
Kojto	90:cb3d968589d8	3911	{
Kojto	90:cb3d968589d8	3912	uint32_t U;
Kojto	90:cb3d968589d8	3913	struct _hw_sim_uidmh_bitfields
Kojto	90:cb3d968589d8	3914	{
Kojto	90:cb3d968589d8	3915	uint32_t UID : 32; /!< [31:0] Unique Identification /
Kojto	90:cb3d968589d8	3916	} B;
Kojto	90:cb3d968589d8	3917	} hw_sim_uidmh_t;
Kojto	90:cb3d968589d8	3918
Kojto	90:cb3d968589d8	3919	/*!
Kojto	90:cb3d968589d8	3920	* @name Constants and macros for entire SIM_UIDMH register
Kojto	90:cb3d968589d8	3921	*/
Kojto	90:cb3d968589d8	3922	/@{/
Kojto	90:cb3d968589d8	3923	#define HW_SIM_UIDMH_ADDR(x) ((x) + 0x1058U)
Kojto	90:cb3d968589d8	3924
Kojto	90:cb3d968589d8	3925	#define HW_SIM_UIDMH(x) ((__I hw_sim_uidmh_t ) HW_SIM_UIDMH_ADDR(x))
Kojto	90:cb3d968589d8	3926	#define HW_SIM_UIDMH_RD(x) (HW_SIM_UIDMH(x).U)
Kojto	90:cb3d968589d8	3927	/@}/
Kojto	90:cb3d968589d8	3928
Kojto	90:cb3d968589d8	3929	/*
Kojto	90:cb3d968589d8	3930	* Constants & macros for individual SIM_UIDMH bitfields
Kojto	90:cb3d968589d8	3931	*/
Kojto	90:cb3d968589d8	3932
Kojto	90:cb3d968589d8	3933	/*!
Kojto	90:cb3d968589d8	3934	* @name Register SIM_UIDMH, field UID[31:0] (RO)
Kojto	90:cb3d968589d8	3935	*
Kojto	90:cb3d968589d8	3936	* Unique identification for the device.
Kojto	90:cb3d968589d8	3937	*/
Kojto	90:cb3d968589d8	3938	/@{/
Kojto	90:cb3d968589d8	3939	#define BP_SIM_UIDMH_UID (0U) /!< Bit position for SIM_UIDMH_UID. /
Kojto	90:cb3d968589d8	3940	#define BM_SIM_UIDMH_UID (0xFFFFFFFFU) /!< Bit mask for SIM_UIDMH_UID. /
Kojto	90:cb3d968589d8	3941	#define BS_SIM_UIDMH_UID (32U) /!< Bit field size in bits for SIM_UIDMH_UID. /
Kojto	90:cb3d968589d8	3942
Kojto	90:cb3d968589d8	3943	/! @brief Read current value of the SIM_UIDMH_UID field. /
Kojto	90:cb3d968589d8	3944	#define BR_SIM_UIDMH_UID(x) (HW_SIM_UIDMH(x).U)
Kojto	90:cb3d968589d8	3945	/@}/
Kojto	90:cb3d968589d8	3946
Kojto	90:cb3d968589d8	3947	/*******************************************************************************
Kojto	90:cb3d968589d8	3948	* HW_SIM_UIDML - Unique Identification Register Mid Low
Kojto	90:cb3d968589d8	3949	******************************************************************************/
Kojto	90:cb3d968589d8	3950
Kojto	90:cb3d968589d8	3951	/*!
Kojto	90:cb3d968589d8	3952	* @brief HW_SIM_UIDML - Unique Identification Register Mid Low (RO)
Kojto	90:cb3d968589d8	3953	*
Kojto	90:cb3d968589d8	3954	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	3955	*/
Kojto	90:cb3d968589d8	3956	typedef union _hw_sim_uidml
Kojto	90:cb3d968589d8	3957	{
Kojto	90:cb3d968589d8	3958	uint32_t U;
Kojto	90:cb3d968589d8	3959	struct _hw_sim_uidml_bitfields
Kojto	90:cb3d968589d8	3960	{
Kojto	90:cb3d968589d8	3961	uint32_t UID : 32; /!< [31:0] Unique Identification /
Kojto	90:cb3d968589d8	3962	} B;
Kojto	90:cb3d968589d8	3963	} hw_sim_uidml_t;
Kojto	90:cb3d968589d8	3964
Kojto	90:cb3d968589d8	3965	/*!
Kojto	90:cb3d968589d8	3966	* @name Constants and macros for entire SIM_UIDML register
Kojto	90:cb3d968589d8	3967	*/
Kojto	90:cb3d968589d8	3968	/@{/
Kojto	90:cb3d968589d8	3969	#define HW_SIM_UIDML_ADDR(x) ((x) + 0x105CU)
Kojto	90:cb3d968589d8	3970
Kojto	90:cb3d968589d8	3971	#define HW_SIM_UIDML(x) ((__I hw_sim_uidml_t ) HW_SIM_UIDML_ADDR(x))
Kojto	90:cb3d968589d8	3972	#define HW_SIM_UIDML_RD(x) (HW_SIM_UIDML(x).U)
Kojto	90:cb3d968589d8	3973	/@}/
Kojto	90:cb3d968589d8	3974
Kojto	90:cb3d968589d8	3975	/*
Kojto	90:cb3d968589d8	3976	* Constants & macros for individual SIM_UIDML bitfields
Kojto	90:cb3d968589d8	3977	*/
Kojto	90:cb3d968589d8	3978
Kojto	90:cb3d968589d8	3979	/*!
Kojto	90:cb3d968589d8	3980	* @name Register SIM_UIDML, field UID[31:0] (RO)
Kojto	90:cb3d968589d8	3981	*
Kojto	90:cb3d968589d8	3982	* Unique identification for the device.
Kojto	90:cb3d968589d8	3983	*/
Kojto	90:cb3d968589d8	3984	/@{/
Kojto	90:cb3d968589d8	3985	#define BP_SIM_UIDML_UID (0U) /!< Bit position for SIM_UIDML_UID. /
Kojto	90:cb3d968589d8	3986	#define BM_SIM_UIDML_UID (0xFFFFFFFFU) /!< Bit mask for SIM_UIDML_UID. /
Kojto	90:cb3d968589d8	3987	#define BS_SIM_UIDML_UID (32U) /!< Bit field size in bits for SIM_UIDML_UID. /
Kojto	90:cb3d968589d8	3988
Kojto	90:cb3d968589d8	3989	/! @brief Read current value of the SIM_UIDML_UID field. /
Kojto	90:cb3d968589d8	3990	#define BR_SIM_UIDML_UID(x) (HW_SIM_UIDML(x).U)
Kojto	90:cb3d968589d8	3991	/@}/
Kojto	90:cb3d968589d8	3992
Kojto	90:cb3d968589d8	3993	/*******************************************************************************
Kojto	90:cb3d968589d8	3994	* HW_SIM_UIDL - Unique Identification Register Low
Kojto	90:cb3d968589d8	3995	******************************************************************************/
Kojto	90:cb3d968589d8	3996
Kojto	90:cb3d968589d8	3997	/*!
Kojto	90:cb3d968589d8	3998	* @brief HW_SIM_UIDL - Unique Identification Register Low (RO)
Kojto	90:cb3d968589d8	3999	*
Kojto	90:cb3d968589d8	4000	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4001	*/
Kojto	90:cb3d968589d8	4002	typedef union _hw_sim_uidl
Kojto	90:cb3d968589d8	4003	{
Kojto	90:cb3d968589d8	4004	uint32_t U;
Kojto	90:cb3d968589d8	4005	struct _hw_sim_uidl_bitfields
Kojto	90:cb3d968589d8	4006	{
Kojto	90:cb3d968589d8	4007	uint32_t UID : 32; /!< [31:0] Unique Identification /
Kojto	90:cb3d968589d8	4008	} B;
Kojto	90:cb3d968589d8	4009	} hw_sim_uidl_t;
Kojto	90:cb3d968589d8	4010
Kojto	90:cb3d968589d8	4011	/*!
Kojto	90:cb3d968589d8	4012	* @name Constants and macros for entire SIM_UIDL register
Kojto	90:cb3d968589d8	4013	*/
Kojto	90:cb3d968589d8	4014	/@{/
Kojto	90:cb3d968589d8	4015	#define HW_SIM_UIDL_ADDR(x) ((x) + 0x1060U)
Kojto	90:cb3d968589d8	4016
Kojto	90:cb3d968589d8	4017	#define HW_SIM_UIDL(x) ((__I hw_sim_uidl_t ) HW_SIM_UIDL_ADDR(x))
Kojto	90:cb3d968589d8	4018	#define HW_SIM_UIDL_RD(x) (HW_SIM_UIDL(x).U)
Kojto	90:cb3d968589d8	4019	/@}/
Kojto	90:cb3d968589d8	4020
Kojto	90:cb3d968589d8	4021	/*
Kojto	90:cb3d968589d8	4022	* Constants & macros for individual SIM_UIDL bitfields
Kojto	90:cb3d968589d8	4023	*/
Kojto	90:cb3d968589d8	4024
Kojto	90:cb3d968589d8	4025	/*!
Kojto	90:cb3d968589d8	4026	* @name Register SIM_UIDL, field UID[31:0] (RO)
Kojto	90:cb3d968589d8	4027	*
Kojto	90:cb3d968589d8	4028	* Unique identification for the device.
Kojto	90:cb3d968589d8	4029	*/
Kojto	90:cb3d968589d8	4030	/@{/
Kojto	90:cb3d968589d8	4031	#define BP_SIM_UIDL_UID (0U) /!< Bit position for SIM_UIDL_UID. /
Kojto	90:cb3d968589d8	4032	#define BM_SIM_UIDL_UID (0xFFFFFFFFU) /!< Bit mask for SIM_UIDL_UID. /
Kojto	90:cb3d968589d8	4033	#define BS_SIM_UIDL_UID (32U) /!< Bit field size in bits for SIM_UIDL_UID. /
Kojto	90:cb3d968589d8	4034
Kojto	90:cb3d968589d8	4035	/! @brief Read current value of the SIM_UIDL_UID field. /
Kojto	90:cb3d968589d8	4036	#define BR_SIM_UIDL_UID(x) (HW_SIM_UIDL(x).U)
Kojto	90:cb3d968589d8	4037	/@}/
Kojto	90:cb3d968589d8	4038
Kojto	90:cb3d968589d8	4039	/*******************************************************************************
Kojto	90:cb3d968589d8	4040	* hw_sim_t - module struct
Kojto	90:cb3d968589d8	4041	******************************************************************************/
Kojto	90:cb3d968589d8	4042	/*!
Kojto	90:cb3d968589d8	4043	* @brief All SIM module registers.
Kojto	90:cb3d968589d8	4044	*/
Kojto	90:cb3d968589d8	4045	#pragma pack(1)
Kojto	90:cb3d968589d8	4046	typedef struct _hw_sim
Kojto	90:cb3d968589d8	4047	{
Kojto	90:cb3d968589d8	4048	__IO hw_sim_sopt1_t SOPT1; /!< [0x0] System Options Register 1 /
Kojto	90:cb3d968589d8	4049	__IO hw_sim_sopt1cfg_t SOPT1CFG; /!< [0x4] SOPT1 Configuration Register /
Kojto	90:cb3d968589d8	4050	uint8_t _reserved0[4092];
Kojto	90:cb3d968589d8	4051	__IO hw_sim_sopt2_t SOPT2; /!< [0x1004] System Options Register 2 /
Kojto	90:cb3d968589d8	4052	uint8_t _reserved1[4];
Kojto	90:cb3d968589d8	4053	__IO hw_sim_sopt4_t SOPT4; /!< [0x100C] System Options Register 4 /
Kojto	90:cb3d968589d8	4054	__IO hw_sim_sopt5_t SOPT5; /!< [0x1010] System Options Register 5 /
Kojto	90:cb3d968589d8	4055	uint8_t _reserved2[4];
Kojto	90:cb3d968589d8	4056	__IO hw_sim_sopt7_t SOPT7; /!< [0x1018] System Options Register 7 /
Kojto	90:cb3d968589d8	4057	uint8_t _reserved3[8];
Kojto	90:cb3d968589d8	4058	__I hw_sim_sdid_t SDID; /!< [0x1024] System Device Identification Register /
Kojto	90:cb3d968589d8	4059	__IO hw_sim_scgc1_t SCGC1; /!< [0x1028] System Clock Gating Control Register 1 /
Kojto	90:cb3d968589d8	4060	__IO hw_sim_scgc2_t SCGC2; /!< [0x102C] System Clock Gating Control Register 2 /
Kojto	90:cb3d968589d8	4061	__IO hw_sim_scgc3_t SCGC3; /!< [0x1030] System Clock Gating Control Register 3 /
Kojto	90:cb3d968589d8	4062	__IO hw_sim_scgc4_t SCGC4; /!< [0x1034] System Clock Gating Control Register 4 /
Kojto	90:cb3d968589d8	4063	__IO hw_sim_scgc5_t SCGC5; /!< [0x1038] System Clock Gating Control Register 5 /
Kojto	90:cb3d968589d8	4064	__IO hw_sim_scgc6_t SCGC6; /!< [0x103C] System Clock Gating Control Register 6 /
Kojto	90:cb3d968589d8	4065	__IO hw_sim_scgc7_t SCGC7; /!< [0x1040] System Clock Gating Control Register 7 /
Kojto	90:cb3d968589d8	4066	__IO hw_sim_clkdiv1_t CLKDIV1; /!< [0x1044] System Clock Divider Register 1 /
Kojto	90:cb3d968589d8	4067	__IO hw_sim_clkdiv2_t CLKDIV2; /!< [0x1048] System Clock Divider Register 2 /
Kojto	90:cb3d968589d8	4068	__IO hw_sim_fcfg1_t FCFG1; /!< [0x104C] Flash Configuration Register 1 /
Kojto	90:cb3d968589d8	4069	__I hw_sim_fcfg2_t FCFG2; /!< [0x1050] Flash Configuration Register 2 /
Kojto	90:cb3d968589d8	4070	__I hw_sim_uidh_t UIDH; /!< [0x1054] Unique Identification Register High /
Kojto	90:cb3d968589d8	4071	__I hw_sim_uidmh_t UIDMH; /!< [0x1058] Unique Identification Register Mid-High /
Kojto	90:cb3d968589d8	4072	__I hw_sim_uidml_t UIDML; /!< [0x105C] Unique Identification Register Mid Low /
Kojto	90:cb3d968589d8	4073	__I hw_sim_uidl_t UIDL; /!< [0x1060] Unique Identification Register Low /
Kojto	90:cb3d968589d8	4074	} hw_sim_t;
Kojto	90:cb3d968589d8	4075	#pragma pack()
Kojto	90:cb3d968589d8	4076
Kojto	90:cb3d968589d8	4077	/! @brief Macro to access all SIM registers. /
Kojto	90:cb3d968589d8	4078	/! @param x SIM module instance base address. /
Kojto	90:cb3d968589d8	4079	/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto	90:cb3d968589d8	4080	* use the '&' operator, like <code>&HW_SIM(SIM_BASE)</code>. */
Kojto	90:cb3d968589d8	4081	#define HW_SIM(x) ((hw_sim_t )(x))
Kojto	90:cb3d968589d8	4082
Kojto	90:cb3d968589d8	4083	#endif /* __HW_SIM_REGISTERS_H__ */
Kojto	90:cb3d968589d8	4084	/* EOF */