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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_sdhc.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:: Kojto
Date:: Wed Aug 05 13:16:35 2015 +0100
Revision:: 104:b9ad9a133dc7
Parent:: 90:cb3d968589d8

Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	90:cb3d968589d8	1	/*
Kojto	90:cb3d968589d8	2	** ###################################################################
Kojto	90:cb3d968589d8	3	** Compilers: Keil ARM C/C++ Compiler
Kojto	90:cb3d968589d8	4	** Freescale C/C++ for Embedded ARM
Kojto	90:cb3d968589d8	5	** GNU C Compiler
Kojto	90:cb3d968589d8	6	** IAR ANSI C/C++ Compiler for ARM
Kojto	90:cb3d968589d8	7	**
Kojto	90:cb3d968589d8	8	** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto	90:cb3d968589d8	9	** Version: rev. 2.5, 2014-02-10
Kojto	90:cb3d968589d8	10	** Build: b140604
Kojto	90:cb3d968589d8	11	**
Kojto	90:cb3d968589d8	12	** Abstract:
Kojto	90:cb3d968589d8	13	** Extension to the CMSIS register access layer header.
Kojto	90:cb3d968589d8	14	**
Kojto	90:cb3d968589d8	15	** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto	90:cb3d968589d8	16	** All rights reserved.
Kojto	90:cb3d968589d8	17	**
Kojto	90:cb3d968589d8	18	** Redistribution and use in source and binary forms, with or without modification,
Kojto	90:cb3d968589d8	19	** are permitted provided that the following conditions are met:
Kojto	90:cb3d968589d8	20	**
Kojto	90:cb3d968589d8	21	** o Redistributions of source code must retain the above copyright notice, this list
Kojto	90:cb3d968589d8	22	** of conditions and the following disclaimer.
Kojto	90:cb3d968589d8	23	**
Kojto	90:cb3d968589d8	24	** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto	90:cb3d968589d8	25	** list of conditions and the following disclaimer in the documentation and/or
Kojto	90:cb3d968589d8	26	** other materials provided with the distribution.
Kojto	90:cb3d968589d8	27	**
Kojto	90:cb3d968589d8	28	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto	90:cb3d968589d8	29	** contributors may be used to endorse or promote products derived from this
Kojto	90:cb3d968589d8	30	** software without specific prior written permission.
Kojto	90:cb3d968589d8	31	**
Kojto	90:cb3d968589d8	32	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto	90:cb3d968589d8	33	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto	90:cb3d968589d8	34	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	90:cb3d968589d8	35	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto	90:cb3d968589d8	36	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto	90:cb3d968589d8	37	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto	90:cb3d968589d8	38	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto	90:cb3d968589d8	39	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto	90:cb3d968589d8	40	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto	90:cb3d968589d8	41	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	90:cb3d968589d8	42	**
Kojto	90:cb3d968589d8	43	** http: www.freescale.com
Kojto	90:cb3d968589d8	44	** mail: support@freescale.com
Kojto	90:cb3d968589d8	45	**
Kojto	90:cb3d968589d8	46	** Revisions:
Kojto	90:cb3d968589d8	47	** - rev. 1.0 (2013-08-12)
Kojto	90:cb3d968589d8	48	** Initial version.
Kojto	90:cb3d968589d8	49	** - rev. 2.0 (2013-10-29)
Kojto	90:cb3d968589d8	50	** Register accessor macros added to the memory map.
Kojto	90:cb3d968589d8	51	** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto	90:cb3d968589d8	52	** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto	90:cb3d968589d8	53	** System initialization updated.
Kojto	90:cb3d968589d8	54	** MCG - registers updated.
Kojto	90:cb3d968589d8	55	** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto	90:cb3d968589d8	56	** - rev. 2.1 (2013-10-30)
Kojto	90:cb3d968589d8	57	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto	90:cb3d968589d8	58	** - rev. 2.2 (2013-12-09)
Kojto	90:cb3d968589d8	59	** DMA - EARS register removed.
Kojto	90:cb3d968589d8	60	** AIPS0, AIPS1 - MPRA register updated.
Kojto	90:cb3d968589d8	61	** - rev. 2.3 (2014-01-24)
Kojto	90:cb3d968589d8	62	** Update according to reference manual rev. 2
Kojto	90:cb3d968589d8	63	** ENET, MCG, MCM, SIM, USB - registers updated
Kojto	90:cb3d968589d8	64	** - rev. 2.4 (2014-02-10)
Kojto	90:cb3d968589d8	65	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	66	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	67	** - rev. 2.5 (2014-02-10)
Kojto	90:cb3d968589d8	68	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	69	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	70	** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto	90:cb3d968589d8	71	**
Kojto	90:cb3d968589d8	72	** ###################################################################
Kojto	90:cb3d968589d8	73	*/
Kojto	90:cb3d968589d8	74
Kojto	90:cb3d968589d8	75	/*
Kojto	90:cb3d968589d8	76	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto	90:cb3d968589d8	77	*
Kojto	90:cb3d968589d8	78	* This file was generated automatically and any changes may be lost.
Kojto	90:cb3d968589d8	79	*/
Kojto	90:cb3d968589d8	80	#ifndef __HW_SDHC_REGISTERS_H__
Kojto	90:cb3d968589d8	81	#define __HW_SDHC_REGISTERS_H__
Kojto	90:cb3d968589d8	82
Kojto	90:cb3d968589d8	83	#include "MK64F12.h"
Kojto	90:cb3d968589d8	84	#include "fsl_bitaccess.h"
Kojto	90:cb3d968589d8	85
Kojto	90:cb3d968589d8	86	/*
Kojto	90:cb3d968589d8	87	* MK64F12 SDHC
Kojto	90:cb3d968589d8	88	*
Kojto	90:cb3d968589d8	89	* Secured Digital Host Controller
Kojto	90:cb3d968589d8	90	*
Kojto	90:cb3d968589d8	91	* Registers defined in this header file:
Kojto	90:cb3d968589d8	92	* - HW_SDHC_DSADDR - DMA System Address register
Kojto	90:cb3d968589d8	93	* - HW_SDHC_BLKATTR - Block Attributes register
Kojto	90:cb3d968589d8	94	* - HW_SDHC_CMDARG - Command Argument register
Kojto	90:cb3d968589d8	95	* - HW_SDHC_XFERTYP - Transfer Type register
Kojto	90:cb3d968589d8	96	* - HW_SDHC_CMDRSP0 - Command Response 0
Kojto	90:cb3d968589d8	97	* - HW_SDHC_CMDRSP1 - Command Response 1
Kojto	90:cb3d968589d8	98	* - HW_SDHC_CMDRSP2 - Command Response 2
Kojto	90:cb3d968589d8	99	* - HW_SDHC_CMDRSP3 - Command Response 3
Kojto	90:cb3d968589d8	100	* - HW_SDHC_DATPORT - Buffer Data Port register
Kojto	90:cb3d968589d8	101	* - HW_SDHC_PRSSTAT - Present State register
Kojto	90:cb3d968589d8	102	* - HW_SDHC_PROCTL - Protocol Control register
Kojto	90:cb3d968589d8	103	* - HW_SDHC_SYSCTL - System Control register
Kojto	90:cb3d968589d8	104	* - HW_SDHC_IRQSTAT - Interrupt Status register
Kojto	90:cb3d968589d8	105	* - HW_SDHC_IRQSTATEN - Interrupt Status Enable register
Kojto	90:cb3d968589d8	106	* - HW_SDHC_IRQSIGEN - Interrupt Signal Enable register
Kojto	90:cb3d968589d8	107	* - HW_SDHC_AC12ERR - Auto CMD12 Error Status Register
Kojto	90:cb3d968589d8	108	* - HW_SDHC_HTCAPBLT - Host Controller Capabilities
Kojto	90:cb3d968589d8	109	* - HW_SDHC_WML - Watermark Level Register
Kojto	90:cb3d968589d8	110	* - HW_SDHC_FEVT - Force Event register
Kojto	90:cb3d968589d8	111	* - HW_SDHC_ADMAES - ADMA Error Status register
Kojto	90:cb3d968589d8	112	* - HW_SDHC_ADSADDR - ADMA System Addressregister
Kojto	90:cb3d968589d8	113	* - HW_SDHC_VENDOR - Vendor Specific register
Kojto	90:cb3d968589d8	114	* - HW_SDHC_MMCBOOT - MMC Boot register
Kojto	90:cb3d968589d8	115	* - HW_SDHC_HOSTVER - Host Controller Version
Kojto	90:cb3d968589d8	116	*
Kojto	90:cb3d968589d8	117	* - hw_sdhc_t - Struct containing all module registers.
Kojto	90:cb3d968589d8	118	*/
Kojto	90:cb3d968589d8	119
Kojto	90:cb3d968589d8	120	#define HW_SDHC_INSTANCE_COUNT (1U) /!< Number of instances of the SDHC module. /
Kojto	90:cb3d968589d8	121
Kojto	90:cb3d968589d8	122	/*******************************************************************************
Kojto	90:cb3d968589d8	123	* HW_SDHC_DSADDR - DMA System Address register
Kojto	90:cb3d968589d8	124	******************************************************************************/
Kojto	90:cb3d968589d8	125
Kojto	90:cb3d968589d8	126	/*!
Kojto	90:cb3d968589d8	127	* @brief HW_SDHC_DSADDR - DMA System Address register (RW)
Kojto	90:cb3d968589d8	128	*
Kojto	90:cb3d968589d8	129	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	130	*
Kojto	90:cb3d968589d8	131	* This register contains the physical system memory address used for DMA
Kojto	90:cb3d968589d8	132	* transfers.
Kojto	90:cb3d968589d8	133	*/
Kojto	90:cb3d968589d8	134	typedef union _hw_sdhc_dsaddr
Kojto	90:cb3d968589d8	135	{
Kojto	90:cb3d968589d8	136	uint32_t U;
Kojto	90:cb3d968589d8	137	struct _hw_sdhc_dsaddr_bitfields
Kojto	90:cb3d968589d8	138	{
Kojto	90:cb3d968589d8	139	uint32_t RESERVED0 : 2; /!< [1:0] /
Kojto	90:cb3d968589d8	140	uint32_t DSADDR : 30; /!< [31:2] DMA System Address /
Kojto	90:cb3d968589d8	141	} B;
Kojto	90:cb3d968589d8	142	} hw_sdhc_dsaddr_t;
Kojto	90:cb3d968589d8	143
Kojto	90:cb3d968589d8	144	/*!
Kojto	90:cb3d968589d8	145	* @name Constants and macros for entire SDHC_DSADDR register
Kojto	90:cb3d968589d8	146	*/
Kojto	90:cb3d968589d8	147	/@{/
Kojto	90:cb3d968589d8	148	#define HW_SDHC_DSADDR_ADDR(x) ((x) + 0x0U)
Kojto	90:cb3d968589d8	149
Kojto	90:cb3d968589d8	150	#define HW_SDHC_DSADDR(x) ((__IO hw_sdhc_dsaddr_t ) HW_SDHC_DSADDR_ADDR(x))
Kojto	90:cb3d968589d8	151	#define HW_SDHC_DSADDR_RD(x) (HW_SDHC_DSADDR(x).U)
Kojto	90:cb3d968589d8	152	#define HW_SDHC_DSADDR_WR(x, v) (HW_SDHC_DSADDR(x).U = (v))
Kojto	90:cb3d968589d8	153	#define HW_SDHC_DSADDR_SET(x, v) (HW_SDHC_DSADDR_WR(x, HW_SDHC_DSADDR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	154	#define HW_SDHC_DSADDR_CLR(x, v) (HW_SDHC_DSADDR_WR(x, HW_SDHC_DSADDR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	155	#define HW_SDHC_DSADDR_TOG(x, v) (HW_SDHC_DSADDR_WR(x, HW_SDHC_DSADDR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	156	/@}/
Kojto	90:cb3d968589d8	157
Kojto	90:cb3d968589d8	158	/*
Kojto	90:cb3d968589d8	159	* Constants & macros for individual SDHC_DSADDR bitfields
Kojto	90:cb3d968589d8	160	*/
Kojto	90:cb3d968589d8	161
Kojto	90:cb3d968589d8	162	/*!
Kojto	90:cb3d968589d8	163	* @name Register SDHC_DSADDR, field DSADDR[31:2] (RW)
Kojto	90:cb3d968589d8	164	*
Kojto	90:cb3d968589d8	165	* Contains the 32-bit system memory address for a DMA transfer. Because the
Kojto	90:cb3d968589d8	166	* address must be word (4 bytes) align, the least 2 bits are reserved, always 0.
Kojto	90:cb3d968589d8	167	* When the SDHC stops a DMA transfer, this register points to the system address
Kojto	90:cb3d968589d8	168	* of the next contiguous data position. It can be accessed only when no
Kojto	90:cb3d968589d8	169	* transaction is executing, that is, after a transaction has stopped. Read operation
Kojto	90:cb3d968589d8	170	* during transfers may return an invalid value. The host driver shall initialize
Kojto	90:cb3d968589d8	171	* this register before starting a DMA transaction. After DMA has stopped, the
Kojto	90:cb3d968589d8	172	* system address of the next contiguous data position can be read from this register.
Kojto	90:cb3d968589d8	173	* This register is protected during a data transfer. When data lines are
Kojto	90:cb3d968589d8	174	* active, write to this register is ignored. The host driver shall wait, until
Kojto	90:cb3d968589d8	175	* PRSSTAT[DLA] is cleared, before writing to this register. The SDHC internal DMA does
Kojto	90:cb3d968589d8	176	* not support a virtual memory system. It supports only continuous physical
Kojto	90:cb3d968589d8	177	* memory access. And due to AHB burst limitations, if the burst must cross the 1 KB
Kojto	90:cb3d968589d8	178	* boundary, SDHC will automatically change SEQ burst type to NSEQ. Because this
Kojto	90:cb3d968589d8	179	* register supports dynamic address reflecting, when IRQSTAT[TC] bit is set, it
Kojto	90:cb3d968589d8	180	* automatically alters the value of internal address counter, so SW cannot
Kojto	90:cb3d968589d8	181	* change this register when IRQSTAT[TC] is set.
Kojto	90:cb3d968589d8	182	*/
Kojto	90:cb3d968589d8	183	/@{/
Kojto	90:cb3d968589d8	184	#define BP_SDHC_DSADDR_DSADDR (2U) /!< Bit position for SDHC_DSADDR_DSADDR. /
Kojto	90:cb3d968589d8	185	#define BM_SDHC_DSADDR_DSADDR (0xFFFFFFFCU) /!< Bit mask for SDHC_DSADDR_DSADDR. /
Kojto	90:cb3d968589d8	186	#define BS_SDHC_DSADDR_DSADDR (30U) /!< Bit field size in bits for SDHC_DSADDR_DSADDR. /
Kojto	90:cb3d968589d8	187
Kojto	90:cb3d968589d8	188	/! @brief Read current value of the SDHC_DSADDR_DSADDR field. /
Kojto	90:cb3d968589d8	189	#define BR_SDHC_DSADDR_DSADDR(x) (HW_SDHC_DSADDR(x).B.DSADDR)
Kojto	90:cb3d968589d8	190
Kojto	90:cb3d968589d8	191	/! @brief Format value for bitfield SDHC_DSADDR_DSADDR. /
Kojto	90:cb3d968589d8	192	#define BF_SDHC_DSADDR_DSADDR(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_DSADDR_DSADDR) & BM_SDHC_DSADDR_DSADDR)
Kojto	90:cb3d968589d8	193
Kojto	90:cb3d968589d8	194	/! @brief Set the DSADDR field to a new value. /
Kojto	90:cb3d968589d8	195	#define BW_SDHC_DSADDR_DSADDR(x, v) (HW_SDHC_DSADDR_WR(x, (HW_SDHC_DSADDR_RD(x) & ~BM_SDHC_DSADDR_DSADDR) \| BF_SDHC_DSADDR_DSADDR(v)))
Kojto	90:cb3d968589d8	196	/@}/
Kojto	90:cb3d968589d8	197
Kojto	90:cb3d968589d8	198	/*******************************************************************************
Kojto	90:cb3d968589d8	199	* HW_SDHC_BLKATTR - Block Attributes register
Kojto	90:cb3d968589d8	200	******************************************************************************/
Kojto	90:cb3d968589d8	201
Kojto	90:cb3d968589d8	202	/*!
Kojto	90:cb3d968589d8	203	* @brief HW_SDHC_BLKATTR - Block Attributes register (RW)
Kojto	90:cb3d968589d8	204	*
Kojto	90:cb3d968589d8	205	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	206	*
Kojto	90:cb3d968589d8	207	* This register is used to configure the number of data blocks and the number
Kojto	90:cb3d968589d8	208	* of bytes in each block.
Kojto	90:cb3d968589d8	209	*/
Kojto	90:cb3d968589d8	210	typedef union _hw_sdhc_blkattr
Kojto	90:cb3d968589d8	211	{
Kojto	90:cb3d968589d8	212	uint32_t U;
Kojto	90:cb3d968589d8	213	struct _hw_sdhc_blkattr_bitfields
Kojto	90:cb3d968589d8	214	{
Kojto	90:cb3d968589d8	215	uint32_t BLKSIZE : 13; /!< [12:0] Transfer Block Size /
Kojto	90:cb3d968589d8	216	uint32_t RESERVED0 : 3; /!< [15:13] /
Kojto	90:cb3d968589d8	217	uint32_t BLKCNT : 16; /*!< [31:16] Blocks Count For Current Transfer
Kojto	90:cb3d968589d8	218	* */
Kojto	90:cb3d968589d8	219	} B;
Kojto	90:cb3d968589d8	220	} hw_sdhc_blkattr_t;
Kojto	90:cb3d968589d8	221
Kojto	90:cb3d968589d8	222	/*!
Kojto	90:cb3d968589d8	223	* @name Constants and macros for entire SDHC_BLKATTR register
Kojto	90:cb3d968589d8	224	*/
Kojto	90:cb3d968589d8	225	/@{/
Kojto	90:cb3d968589d8	226	#define HW_SDHC_BLKATTR_ADDR(x) ((x) + 0x4U)
Kojto	90:cb3d968589d8	227
Kojto	90:cb3d968589d8	228	#define HW_SDHC_BLKATTR(x) ((__IO hw_sdhc_blkattr_t ) HW_SDHC_BLKATTR_ADDR(x))
Kojto	90:cb3d968589d8	229	#define HW_SDHC_BLKATTR_RD(x) (HW_SDHC_BLKATTR(x).U)
Kojto	90:cb3d968589d8	230	#define HW_SDHC_BLKATTR_WR(x, v) (HW_SDHC_BLKATTR(x).U = (v))
Kojto	90:cb3d968589d8	231	#define HW_SDHC_BLKATTR_SET(x, v) (HW_SDHC_BLKATTR_WR(x, HW_SDHC_BLKATTR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	232	#define HW_SDHC_BLKATTR_CLR(x, v) (HW_SDHC_BLKATTR_WR(x, HW_SDHC_BLKATTR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	233	#define HW_SDHC_BLKATTR_TOG(x, v) (HW_SDHC_BLKATTR_WR(x, HW_SDHC_BLKATTR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	234	/@}/
Kojto	90:cb3d968589d8	235
Kojto	90:cb3d968589d8	236	/*
Kojto	90:cb3d968589d8	237	* Constants & macros for individual SDHC_BLKATTR bitfields
Kojto	90:cb3d968589d8	238	*/
Kojto	90:cb3d968589d8	239
Kojto	90:cb3d968589d8	240	/*!
Kojto	90:cb3d968589d8	241	* @name Register SDHC_BLKATTR, field BLKSIZE[12:0] (RW)
Kojto	90:cb3d968589d8	242	*
Kojto	90:cb3d968589d8	243	* Specifies the block size for block data transfers. Values ranging from 1 byte
Kojto	90:cb3d968589d8	244	* up to the maximum buffer size can be set. It can be accessed only when no
Kojto	90:cb3d968589d8	245	* transaction is executing, that is, after a transaction has stopped. Read
Kojto	90:cb3d968589d8	246	* operations during transfers may return an invalid value, and write operations will be
Kojto	90:cb3d968589d8	247	* ignored.
Kojto	90:cb3d968589d8	248	*
Kojto	90:cb3d968589d8	249	* Values:
Kojto	90:cb3d968589d8	250	* - 0 - No data transfer.
Kojto	90:cb3d968589d8	251	* - 1 - 1 Byte
Kojto	90:cb3d968589d8	252	* - 10 - 2 Bytes
Kojto	90:cb3d968589d8	253	* - 11 - 3 Bytes
Kojto	90:cb3d968589d8	254	* - 100 - 4 Bytes
Kojto	90:cb3d968589d8	255	* - 111111111 - 511 Bytes
Kojto	90:cb3d968589d8	256	* - 1000000000 - 512 Bytes
Kojto	90:cb3d968589d8	257	* - 100000000000 - 2048 Bytes
Kojto	90:cb3d968589d8	258	* - 1000000000000 - 4096 Bytes
Kojto	90:cb3d968589d8	259	*/
Kojto	90:cb3d968589d8	260	/@{/
Kojto	90:cb3d968589d8	261	#define BP_SDHC_BLKATTR_BLKSIZE (0U) /!< Bit position for SDHC_BLKATTR_BLKSIZE. /
Kojto	90:cb3d968589d8	262	#define BM_SDHC_BLKATTR_BLKSIZE (0x00001FFFU) /!< Bit mask for SDHC_BLKATTR_BLKSIZE. /
Kojto	90:cb3d968589d8	263	#define BS_SDHC_BLKATTR_BLKSIZE (13U) /!< Bit field size in bits for SDHC_BLKATTR_BLKSIZE. /
Kojto	90:cb3d968589d8	264
Kojto	90:cb3d968589d8	265	/! @brief Read current value of the SDHC_BLKATTR_BLKSIZE field. /
Kojto	90:cb3d968589d8	266	#define BR_SDHC_BLKATTR_BLKSIZE(x) (HW_SDHC_BLKATTR(x).B.BLKSIZE)
Kojto	90:cb3d968589d8	267
Kojto	90:cb3d968589d8	268	/! @brief Format value for bitfield SDHC_BLKATTR_BLKSIZE. /
Kojto	90:cb3d968589d8	269	#define BF_SDHC_BLKATTR_BLKSIZE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_BLKATTR_BLKSIZE) & BM_SDHC_BLKATTR_BLKSIZE)
Kojto	90:cb3d968589d8	270
Kojto	90:cb3d968589d8	271	/! @brief Set the BLKSIZE field to a new value. /
Kojto	90:cb3d968589d8	272	#define BW_SDHC_BLKATTR_BLKSIZE(x, v) (HW_SDHC_BLKATTR_WR(x, (HW_SDHC_BLKATTR_RD(x) & ~BM_SDHC_BLKATTR_BLKSIZE) \| BF_SDHC_BLKATTR_BLKSIZE(v)))
Kojto	90:cb3d968589d8	273	/@}/
Kojto	90:cb3d968589d8	274
Kojto	90:cb3d968589d8	275	/*!
Kojto	90:cb3d968589d8	276	* @name Register SDHC_BLKATTR, field BLKCNT[31:16] (RW)
Kojto	90:cb3d968589d8	277	*
Kojto	90:cb3d968589d8	278	* This register is enabled when XFERTYP[BCEN] is set to 1 and is valid only for
Kojto	90:cb3d968589d8	279	* multiple block transfers. For single block transfer, this register will
Kojto	90:cb3d968589d8	280	* always read as 1. The host driver shall set this register to a value between 1 and
Kojto	90:cb3d968589d8	281	* the maximum block count. The SDHC decrements the block count after each block
Kojto	90:cb3d968589d8	282	* transfer and stops when the count reaches zero. Setting the block count to 0
Kojto	90:cb3d968589d8	283	* results in no data blocks being transferred. This register must be accessed
Kojto	90:cb3d968589d8	284	* only when no transaction is executing, that is, after transactions are stopped.
Kojto	90:cb3d968589d8	285	* During data transfer, read operations on this register may return an invalid
Kojto	90:cb3d968589d8	286	* value and write operations are ignored. When saving transfer content as a result
Kojto	90:cb3d968589d8	287	* of a suspend command, the number of blocks yet to be transferred can be
Kojto	90:cb3d968589d8	288	* determined by reading this register. The reading of this register must be applied
Kojto	90:cb3d968589d8	289	* after transfer is paused by stop at block gap operation and before sending the
Kojto	90:cb3d968589d8	290	* command marked as suspend. This is because when suspend command is sent out,
Kojto	90:cb3d968589d8	291	* SDHC will regard the current transfer as aborted and change BLKCNT back to its
Kojto	90:cb3d968589d8	292	* original value instead of keeping the dynamical indicator of remained block
Kojto	90:cb3d968589d8	293	* count. When restoring transfer content prior to issuing a resume command, the
Kojto	90:cb3d968589d8	294	* host driver shall restore the previously saved block count. Although the BLKCNT
Kojto	90:cb3d968589d8	295	* field is 0 after reset, the read of reset value is 0x1. This is because when
Kojto	90:cb3d968589d8	296	* XFERTYP[MSBSEL] is 0, indicating a single block transfer, the read value of
Kojto	90:cb3d968589d8	297	* BLKCNT is always 1.
Kojto	90:cb3d968589d8	298	*
Kojto	90:cb3d968589d8	299	* Values:
Kojto	90:cb3d968589d8	300	* - 0 - Stop count.
Kojto	90:cb3d968589d8	301	* - 1 - 1 block
Kojto	90:cb3d968589d8	302	* - 10 - 2 blocks
Kojto	90:cb3d968589d8	303	* - 1111111111111111 - 65535 blocks
Kojto	90:cb3d968589d8	304	*/
Kojto	90:cb3d968589d8	305	/@{/
Kojto	90:cb3d968589d8	306	#define BP_SDHC_BLKATTR_BLKCNT (16U) /!< Bit position for SDHC_BLKATTR_BLKCNT. /
Kojto	90:cb3d968589d8	307	#define BM_SDHC_BLKATTR_BLKCNT (0xFFFF0000U) /!< Bit mask for SDHC_BLKATTR_BLKCNT. /
Kojto	90:cb3d968589d8	308	#define BS_SDHC_BLKATTR_BLKCNT (16U) /!< Bit field size in bits for SDHC_BLKATTR_BLKCNT. /
Kojto	90:cb3d968589d8	309
Kojto	90:cb3d968589d8	310	/! @brief Read current value of the SDHC_BLKATTR_BLKCNT field. /
Kojto	90:cb3d968589d8	311	#define BR_SDHC_BLKATTR_BLKCNT(x) (HW_SDHC_BLKATTR(x).B.BLKCNT)
Kojto	90:cb3d968589d8	312
Kojto	90:cb3d968589d8	313	/! @brief Format value for bitfield SDHC_BLKATTR_BLKCNT. /
Kojto	90:cb3d968589d8	314	#define BF_SDHC_BLKATTR_BLKCNT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_BLKATTR_BLKCNT) & BM_SDHC_BLKATTR_BLKCNT)
Kojto	90:cb3d968589d8	315
Kojto	90:cb3d968589d8	316	/! @brief Set the BLKCNT field to a new value. /
Kojto	90:cb3d968589d8	317	#define BW_SDHC_BLKATTR_BLKCNT(x, v) (HW_SDHC_BLKATTR_WR(x, (HW_SDHC_BLKATTR_RD(x) & ~BM_SDHC_BLKATTR_BLKCNT) \| BF_SDHC_BLKATTR_BLKCNT(v)))
Kojto	90:cb3d968589d8	318	/@}/
Kojto	90:cb3d968589d8	319
Kojto	90:cb3d968589d8	320	/*******************************************************************************
Kojto	90:cb3d968589d8	321	* HW_SDHC_CMDARG - Command Argument register
Kojto	90:cb3d968589d8	322	******************************************************************************/
Kojto	90:cb3d968589d8	323
Kojto	90:cb3d968589d8	324	/*!
Kojto	90:cb3d968589d8	325	* @brief HW_SDHC_CMDARG - Command Argument register (RW)
Kojto	90:cb3d968589d8	326	*
Kojto	90:cb3d968589d8	327	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	328	*
Kojto	90:cb3d968589d8	329	* This register contains the SD/MMC command argument.
Kojto	90:cb3d968589d8	330	*/
Kojto	90:cb3d968589d8	331	typedef union _hw_sdhc_cmdarg
Kojto	90:cb3d968589d8	332	{
Kojto	90:cb3d968589d8	333	uint32_t U;
Kojto	90:cb3d968589d8	334	struct _hw_sdhc_cmdarg_bitfields
Kojto	90:cb3d968589d8	335	{
Kojto	90:cb3d968589d8	336	uint32_t CMDARG : 32; /!< [31:0] Command Argument /
Kojto	90:cb3d968589d8	337	} B;
Kojto	90:cb3d968589d8	338	} hw_sdhc_cmdarg_t;
Kojto	90:cb3d968589d8	339
Kojto	90:cb3d968589d8	340	/*!
Kojto	90:cb3d968589d8	341	* @name Constants and macros for entire SDHC_CMDARG register
Kojto	90:cb3d968589d8	342	*/
Kojto	90:cb3d968589d8	343	/@{/
Kojto	90:cb3d968589d8	344	#define HW_SDHC_CMDARG_ADDR(x) ((x) + 0x8U)
Kojto	90:cb3d968589d8	345
Kojto	90:cb3d968589d8	346	#define HW_SDHC_CMDARG(x) ((__IO hw_sdhc_cmdarg_t ) HW_SDHC_CMDARG_ADDR(x))
Kojto	90:cb3d968589d8	347	#define HW_SDHC_CMDARG_RD(x) (HW_SDHC_CMDARG(x).U)
Kojto	90:cb3d968589d8	348	#define HW_SDHC_CMDARG_WR(x, v) (HW_SDHC_CMDARG(x).U = (v))
Kojto	90:cb3d968589d8	349	#define HW_SDHC_CMDARG_SET(x, v) (HW_SDHC_CMDARG_WR(x, HW_SDHC_CMDARG_RD(x) \| (v)))
Kojto	90:cb3d968589d8	350	#define HW_SDHC_CMDARG_CLR(x, v) (HW_SDHC_CMDARG_WR(x, HW_SDHC_CMDARG_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	351	#define HW_SDHC_CMDARG_TOG(x, v) (HW_SDHC_CMDARG_WR(x, HW_SDHC_CMDARG_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	352	/@}/
Kojto	90:cb3d968589d8	353
Kojto	90:cb3d968589d8	354	/*
Kojto	90:cb3d968589d8	355	* Constants & macros for individual SDHC_CMDARG bitfields
Kojto	90:cb3d968589d8	356	*/
Kojto	90:cb3d968589d8	357
Kojto	90:cb3d968589d8	358	/*!
Kojto	90:cb3d968589d8	359	* @name Register SDHC_CMDARG, field CMDARG[31:0] (RW)
Kojto	90:cb3d968589d8	360	*
Kojto	90:cb3d968589d8	361	* The SD/MMC command argument is specified as bits 39-8 of the command format
Kojto	90:cb3d968589d8	362	* in the SD or MMC specification. This register is write protected when
Kojto	90:cb3d968589d8	363	* PRSSTAT[CDIHB0] is set.
Kojto	90:cb3d968589d8	364	*/
Kojto	90:cb3d968589d8	365	/@{/
Kojto	90:cb3d968589d8	366	#define BP_SDHC_CMDARG_CMDARG (0U) /!< Bit position for SDHC_CMDARG_CMDARG. /
Kojto	90:cb3d968589d8	367	#define BM_SDHC_CMDARG_CMDARG (0xFFFFFFFFU) /!< Bit mask for SDHC_CMDARG_CMDARG. /
Kojto	90:cb3d968589d8	368	#define BS_SDHC_CMDARG_CMDARG (32U) /!< Bit field size in bits for SDHC_CMDARG_CMDARG. /
Kojto	90:cb3d968589d8	369
Kojto	90:cb3d968589d8	370	/! @brief Read current value of the SDHC_CMDARG_CMDARG field. /
Kojto	90:cb3d968589d8	371	#define BR_SDHC_CMDARG_CMDARG(x) (HW_SDHC_CMDARG(x).U)
Kojto	90:cb3d968589d8	372
Kojto	90:cb3d968589d8	373	/! @brief Format value for bitfield SDHC_CMDARG_CMDARG. /
Kojto	90:cb3d968589d8	374	#define BF_SDHC_CMDARG_CMDARG(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_CMDARG_CMDARG) & BM_SDHC_CMDARG_CMDARG)
Kojto	90:cb3d968589d8	375
Kojto	90:cb3d968589d8	376	/! @brief Set the CMDARG field to a new value. /
Kojto	90:cb3d968589d8	377	#define BW_SDHC_CMDARG_CMDARG(x, v) (HW_SDHC_CMDARG_WR(x, v))
Kojto	90:cb3d968589d8	378	/@}/
Kojto	90:cb3d968589d8	379
Kojto	90:cb3d968589d8	380	/*******************************************************************************
Kojto	90:cb3d968589d8	381	* HW_SDHC_XFERTYP - Transfer Type register
Kojto	90:cb3d968589d8	382	******************************************************************************/
Kojto	90:cb3d968589d8	383
Kojto	90:cb3d968589d8	384	/*!
Kojto	90:cb3d968589d8	385	* @brief HW_SDHC_XFERTYP - Transfer Type register (RW)
Kojto	90:cb3d968589d8	386	*
Kojto	90:cb3d968589d8	387	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	388	*
Kojto	90:cb3d968589d8	389	* This register is used to control the operation of data transfers. The host
Kojto	90:cb3d968589d8	390	* driver shall set this register before issuing a command followed by a data
Kojto	90:cb3d968589d8	391	* transfer, or before issuing a resume command. To prevent data loss, the SDHC
Kojto	90:cb3d968589d8	392	* prevents writing to the bits that are involved in the data transfer of this
Kojto	90:cb3d968589d8	393	* register, when data transfer is active. These bits are DPSEL, MBSEL, DTDSEL, AC12EN,
Kojto	90:cb3d968589d8	394	* BCEN, and DMAEN. The host driver shall check PRSSTAT[CDIHB] and PRSSTAT[CIHB]
Kojto	90:cb3d968589d8	395	* before writing to this register. When PRSSTAT[CDIHB] is set, any attempt to
Kojto	90:cb3d968589d8	396	* send a command with data by writing to this register is ignored; when
Kojto	90:cb3d968589d8	397	* PRSSTAT[CIHB] bit is set, any write to this register is ignored. On sending commands with
Kojto	90:cb3d968589d8	398	* data transfer involved, it is mandatory that the block size is nonzero.
Kojto	90:cb3d968589d8	399	* Besides, block count must also be nonzero, or indicated as single block transfer
Kojto	90:cb3d968589d8	400	* (bit 5 of this register is 0 when written), or block count is disabled (bit 1 of
Kojto	90:cb3d968589d8	401	* this register is 0 when written), otherwise SDHC will ignore the sending of
Kojto	90:cb3d968589d8	402	* this command and do nothing. For write command, with all above restrictions, it
Kojto	90:cb3d968589d8	403	* is also mandatory that the write protect switch is not active (WPSPL bit of
Kojto	90:cb3d968589d8	404	* Present State Register is 1), otherwise SDHC will also ignore the command. If
Kojto	90:cb3d968589d8	405	* the commands with data transfer does not receive the response in 64 clock
Kojto	90:cb3d968589d8	406	* cycles, that is, response time-out, SDHC will regard the external device does not
Kojto	90:cb3d968589d8	407	* accept the command and abort the data transfer. In this scenario, the driver
Kojto	90:cb3d968589d8	408	* must issue the command again to retry the transfer. It is also possible that,
Kojto	90:cb3d968589d8	409	* for some reason, the card responds to the command but SDHC does not receive the
Kojto	90:cb3d968589d8	410	* response, and if it is internal DMA (either simple DMA or ADMA) read
Kojto	90:cb3d968589d8	411	* operation, the external system memory is over-written by the internal DMA with data
Kojto	90:cb3d968589d8	412	* sent back from the card. The following table shows the summary of how register
Kojto	90:cb3d968589d8	413	* settings determine the type of data transfer. Transfer Type register setting for
Kojto	90:cb3d968589d8	414	* various transfer types Multi/Single block select Block count enable Block
Kojto	90:cb3d968589d8	415	* count Function 0 Don't care Don't care Single transfer 1 0 Don't care Infinite
Kojto	90:cb3d968589d8	416	* transfer 1 1 Positive number Multiple transfer 1 1 Zero No data transfer The
Kojto	90:cb3d968589d8	417	* following table shows the relationship between XFERTYP[CICEN] and XFERTYP[CCCEN],
Kojto	90:cb3d968589d8	418	* in regards to XFERTYP[RSPTYP] as well as the name of the response type.
Kojto	90:cb3d968589d8	419	* Relationship between parameters and the name of the response type Response type
Kojto	90:cb3d968589d8	420	* (RSPTYP) Index check enable (CICEN) CRC check enable (CCCEN) Name of response
Kojto	90:cb3d968589d8	421	* type 00 0 0 No Response 01 0 1 IR2 10 0 0 R3,R4 10 1 1 R1,R5,R6 11 1 1 R1b,R5b In
Kojto	90:cb3d968589d8	422	* the SDIO specification, response type notation for R5b is not defined. R5
Kojto	90:cb3d968589d8	423	* includes R5b in the SDIO specification. But R5b is defined in this specification
Kojto	90:cb3d968589d8	424	* to specify that the SDHC will check the busy status after receiving a
Kojto	90:cb3d968589d8	425	* response. For example, usually CMD52 is used with R5, but the I/O abort command shall
Kojto	90:cb3d968589d8	426	* be used with R5b. The CRC field for R3 and R4 is expected to be all 1 bits.
Kojto	90:cb3d968589d8	427	* The CRC check shall be disabled for these response types.
Kojto	90:cb3d968589d8	428	*/
Kojto	90:cb3d968589d8	429	typedef union _hw_sdhc_xfertyp
Kojto	90:cb3d968589d8	430	{
Kojto	90:cb3d968589d8	431	uint32_t U;
Kojto	90:cb3d968589d8	432	struct _hw_sdhc_xfertyp_bitfields
Kojto	90:cb3d968589d8	433	{
Kojto	90:cb3d968589d8	434	uint32_t DMAEN : 1; /!< [0] DMA Enable /
Kojto	90:cb3d968589d8	435	uint32_t BCEN : 1; /!< [1] Block Count Enable /
Kojto	90:cb3d968589d8	436	uint32_t AC12EN : 1; /!< [2] Auto CMD12 Enable /
Kojto	90:cb3d968589d8	437	uint32_t RESERVED0 : 1; /!< [3] /
Kojto	90:cb3d968589d8	438	uint32_t DTDSEL : 1; /!< [4] Data Transfer Direction Select /
Kojto	90:cb3d968589d8	439	uint32_t MSBSEL : 1; /!< [5] Multi/Single Block Select /
Kojto	90:cb3d968589d8	440	uint32_t RESERVED1 : 10; /!< [15:6] /
Kojto	90:cb3d968589d8	441	uint32_t RSPTYP : 2; /!< [17:16] Response Type Select /
Kojto	90:cb3d968589d8	442	uint32_t RESERVED2 : 1; /!< [18] /
Kojto	90:cb3d968589d8	443	uint32_t CCCEN : 1; /!< [19] Command CRC Check Enable /
Kojto	90:cb3d968589d8	444	uint32_t CICEN : 1; /!< [20] Command Index Check Enable /
Kojto	90:cb3d968589d8	445	uint32_t DPSEL : 1; /!< [21] Data Present Select /
Kojto	90:cb3d968589d8	446	uint32_t CMDTYP : 2; /!< [23:22] Command Type /
Kojto	90:cb3d968589d8	447	uint32_t CMDINX : 6; /!< [29:24] Command Index /
Kojto	90:cb3d968589d8	448	uint32_t RESERVED3 : 2; /!< [31:30] /
Kojto	90:cb3d968589d8	449	} B;
Kojto	90:cb3d968589d8	450	} hw_sdhc_xfertyp_t;
Kojto	90:cb3d968589d8	451
Kojto	90:cb3d968589d8	452	/*!
Kojto	90:cb3d968589d8	453	* @name Constants and macros for entire SDHC_XFERTYP register
Kojto	90:cb3d968589d8	454	*/
Kojto	90:cb3d968589d8	455	/@{/
Kojto	90:cb3d968589d8	456	#define HW_SDHC_XFERTYP_ADDR(x) ((x) + 0xCU)
Kojto	90:cb3d968589d8	457
Kojto	90:cb3d968589d8	458	#define HW_SDHC_XFERTYP(x) ((__IO hw_sdhc_xfertyp_t ) HW_SDHC_XFERTYP_ADDR(x))
Kojto	90:cb3d968589d8	459	#define HW_SDHC_XFERTYP_RD(x) (HW_SDHC_XFERTYP(x).U)
Kojto	90:cb3d968589d8	460	#define HW_SDHC_XFERTYP_WR(x, v) (HW_SDHC_XFERTYP(x).U = (v))
Kojto	90:cb3d968589d8	461	#define HW_SDHC_XFERTYP_SET(x, v) (HW_SDHC_XFERTYP_WR(x, HW_SDHC_XFERTYP_RD(x) \| (v)))
Kojto	90:cb3d968589d8	462	#define HW_SDHC_XFERTYP_CLR(x, v) (HW_SDHC_XFERTYP_WR(x, HW_SDHC_XFERTYP_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	463	#define HW_SDHC_XFERTYP_TOG(x, v) (HW_SDHC_XFERTYP_WR(x, HW_SDHC_XFERTYP_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	464	/@}/
Kojto	90:cb3d968589d8	465
Kojto	90:cb3d968589d8	466	/*
Kojto	90:cb3d968589d8	467	* Constants & macros for individual SDHC_XFERTYP bitfields
Kojto	90:cb3d968589d8	468	*/
Kojto	90:cb3d968589d8	469
Kojto	90:cb3d968589d8	470	/*!
Kojto	90:cb3d968589d8	471	* @name Register SDHC_XFERTYP, field DMAEN[0] (RW)
Kojto	90:cb3d968589d8	472	*
Kojto	90:cb3d968589d8	473	* Enables DMA functionality. If this bit is set to 1, a DMA operation shall
Kojto	90:cb3d968589d8	474	* begin when the host driver sets the DPSEL bit of this register. Whether the
Kojto	90:cb3d968589d8	475	* simple DMA, or the advanced DMA, is active depends on PROCTL[DMAS].
Kojto	90:cb3d968589d8	476	*
Kojto	90:cb3d968589d8	477	* Values:
Kojto	90:cb3d968589d8	478	* - 0 - Disable
Kojto	90:cb3d968589d8	479	* - 1 - Enable
Kojto	90:cb3d968589d8	480	*/
Kojto	90:cb3d968589d8	481	/@{/
Kojto	90:cb3d968589d8	482	#define BP_SDHC_XFERTYP_DMAEN (0U) /!< Bit position for SDHC_XFERTYP_DMAEN. /
Kojto	90:cb3d968589d8	483	#define BM_SDHC_XFERTYP_DMAEN (0x00000001U) /!< Bit mask for SDHC_XFERTYP_DMAEN. /
Kojto	90:cb3d968589d8	484	#define BS_SDHC_XFERTYP_DMAEN (1U) /!< Bit field size in bits for SDHC_XFERTYP_DMAEN. /
Kojto	90:cb3d968589d8	485
Kojto	90:cb3d968589d8	486	/! @brief Read current value of the SDHC_XFERTYP_DMAEN field. /
Kojto	90:cb3d968589d8	487	#define BR_SDHC_XFERTYP_DMAEN(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DMAEN))
Kojto	90:cb3d968589d8	488
Kojto	90:cb3d968589d8	489	/! @brief Format value for bitfield SDHC_XFERTYP_DMAEN. /
Kojto	90:cb3d968589d8	490	#define BF_SDHC_XFERTYP_DMAEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_DMAEN) & BM_SDHC_XFERTYP_DMAEN)
Kojto	90:cb3d968589d8	491
Kojto	90:cb3d968589d8	492	/! @brief Set the DMAEN field to a new value. /
Kojto	90:cb3d968589d8	493	#define BW_SDHC_XFERTYP_DMAEN(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DMAEN) = (v))
Kojto	90:cb3d968589d8	494	/@}/
Kojto	90:cb3d968589d8	495
Kojto	90:cb3d968589d8	496	/*!
Kojto	90:cb3d968589d8	497	* @name Register SDHC_XFERTYP, field BCEN[1] (RW)
Kojto	90:cb3d968589d8	498	*
Kojto	90:cb3d968589d8	499	* Used to enable the Block Count register, which is only relevant for multiple
Kojto	90:cb3d968589d8	500	* block transfers. When this bit is 0, the internal counter for block is
Kojto	90:cb3d968589d8	501	* disabled, which is useful in executing an infinite transfer.
Kojto	90:cb3d968589d8	502	*
Kojto	90:cb3d968589d8	503	* Values:
Kojto	90:cb3d968589d8	504	* - 0 - Disable
Kojto	90:cb3d968589d8	505	* - 1 - Enable
Kojto	90:cb3d968589d8	506	*/
Kojto	90:cb3d968589d8	507	/@{/
Kojto	90:cb3d968589d8	508	#define BP_SDHC_XFERTYP_BCEN (1U) /!< Bit position for SDHC_XFERTYP_BCEN. /
Kojto	90:cb3d968589d8	509	#define BM_SDHC_XFERTYP_BCEN (0x00000002U) /!< Bit mask for SDHC_XFERTYP_BCEN. /
Kojto	90:cb3d968589d8	510	#define BS_SDHC_XFERTYP_BCEN (1U) /!< Bit field size in bits for SDHC_XFERTYP_BCEN. /
Kojto	90:cb3d968589d8	511
Kojto	90:cb3d968589d8	512	/! @brief Read current value of the SDHC_XFERTYP_BCEN field. /
Kojto	90:cb3d968589d8	513	#define BR_SDHC_XFERTYP_BCEN(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_BCEN))
Kojto	90:cb3d968589d8	514
Kojto	90:cb3d968589d8	515	/! @brief Format value for bitfield SDHC_XFERTYP_BCEN. /
Kojto	90:cb3d968589d8	516	#define BF_SDHC_XFERTYP_BCEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_BCEN) & BM_SDHC_XFERTYP_BCEN)
Kojto	90:cb3d968589d8	517
Kojto	90:cb3d968589d8	518	/! @brief Set the BCEN field to a new value. /
Kojto	90:cb3d968589d8	519	#define BW_SDHC_XFERTYP_BCEN(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_BCEN) = (v))
Kojto	90:cb3d968589d8	520	/@}/
Kojto	90:cb3d968589d8	521
Kojto	90:cb3d968589d8	522	/*!
Kojto	90:cb3d968589d8	523	* @name Register SDHC_XFERTYP, field AC12EN[2] (RW)
Kojto	90:cb3d968589d8	524	*
Kojto	90:cb3d968589d8	525	* Multiple block transfers for memory require a CMD12 to stop the transaction.
Kojto	90:cb3d968589d8	526	* When this bit is set to 1, the SDHC will issue a CMD12 automatically when the
Kojto	90:cb3d968589d8	527	* last block transfer has completed. The host driver shall not set this bit to
Kojto	90:cb3d968589d8	528	* issue commands that do not require CMD12 to stop a multiple block data
Kojto	90:cb3d968589d8	529	* transfer. In particular, secure commands defined in File Security Specification (see
Kojto	90:cb3d968589d8	530	* reference list) do not require CMD12. In single block transfer, the SDHC will
Kojto	90:cb3d968589d8	531	* ignore this bit whether it is set or not.
Kojto	90:cb3d968589d8	532	*
Kojto	90:cb3d968589d8	533	* Values:
Kojto	90:cb3d968589d8	534	* - 0 - Disable
Kojto	90:cb3d968589d8	535	* - 1 - Enable
Kojto	90:cb3d968589d8	536	*/
Kojto	90:cb3d968589d8	537	/@{/
Kojto	90:cb3d968589d8	538	#define BP_SDHC_XFERTYP_AC12EN (2U) /!< Bit position for SDHC_XFERTYP_AC12EN. /
Kojto	90:cb3d968589d8	539	#define BM_SDHC_XFERTYP_AC12EN (0x00000004U) /!< Bit mask for SDHC_XFERTYP_AC12EN. /
Kojto	90:cb3d968589d8	540	#define BS_SDHC_XFERTYP_AC12EN (1U) /!< Bit field size in bits for SDHC_XFERTYP_AC12EN. /
Kojto	90:cb3d968589d8	541
Kojto	90:cb3d968589d8	542	/! @brief Read current value of the SDHC_XFERTYP_AC12EN field. /
Kojto	90:cb3d968589d8	543	#define BR_SDHC_XFERTYP_AC12EN(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_AC12EN))
Kojto	90:cb3d968589d8	544
Kojto	90:cb3d968589d8	545	/! @brief Format value for bitfield SDHC_XFERTYP_AC12EN. /
Kojto	90:cb3d968589d8	546	#define BF_SDHC_XFERTYP_AC12EN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_AC12EN) & BM_SDHC_XFERTYP_AC12EN)
Kojto	90:cb3d968589d8	547
Kojto	90:cb3d968589d8	548	/! @brief Set the AC12EN field to a new value. /
Kojto	90:cb3d968589d8	549	#define BW_SDHC_XFERTYP_AC12EN(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_AC12EN) = (v))
Kojto	90:cb3d968589d8	550	/@}/
Kojto	90:cb3d968589d8	551
Kojto	90:cb3d968589d8	552	/*!
Kojto	90:cb3d968589d8	553	* @name Register SDHC_XFERTYP, field DTDSEL[4] (RW)
Kojto	90:cb3d968589d8	554	*
Kojto	90:cb3d968589d8	555	* Defines the direction of DAT line data transfers. The bit is set to 1 by the
Kojto	90:cb3d968589d8	556	* host driver to transfer data from the SD card to the SDHC and is set to 0 for
Kojto	90:cb3d968589d8	557	* all other commands.
Kojto	90:cb3d968589d8	558	*
Kojto	90:cb3d968589d8	559	* Values:
Kojto	90:cb3d968589d8	560	* - 0 - Write host to card.
Kojto	90:cb3d968589d8	561	* - 1 - Read card to host.
Kojto	90:cb3d968589d8	562	*/
Kojto	90:cb3d968589d8	563	/@{/
Kojto	90:cb3d968589d8	564	#define BP_SDHC_XFERTYP_DTDSEL (4U) /!< Bit position for SDHC_XFERTYP_DTDSEL. /
Kojto	90:cb3d968589d8	565	#define BM_SDHC_XFERTYP_DTDSEL (0x00000010U) /!< Bit mask for SDHC_XFERTYP_DTDSEL. /
Kojto	90:cb3d968589d8	566	#define BS_SDHC_XFERTYP_DTDSEL (1U) /!< Bit field size in bits for SDHC_XFERTYP_DTDSEL. /
Kojto	90:cb3d968589d8	567
Kojto	90:cb3d968589d8	568	/! @brief Read current value of the SDHC_XFERTYP_DTDSEL field. /
Kojto	90:cb3d968589d8	569	#define BR_SDHC_XFERTYP_DTDSEL(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DTDSEL))
Kojto	90:cb3d968589d8	570
Kojto	90:cb3d968589d8	571	/! @brief Format value for bitfield SDHC_XFERTYP_DTDSEL. /
Kojto	90:cb3d968589d8	572	#define BF_SDHC_XFERTYP_DTDSEL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_DTDSEL) & BM_SDHC_XFERTYP_DTDSEL)
Kojto	90:cb3d968589d8	573
Kojto	90:cb3d968589d8	574	/! @brief Set the DTDSEL field to a new value. /
Kojto	90:cb3d968589d8	575	#define BW_SDHC_XFERTYP_DTDSEL(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DTDSEL) = (v))
Kojto	90:cb3d968589d8	576	/@}/
Kojto	90:cb3d968589d8	577
Kojto	90:cb3d968589d8	578	/*!
Kojto	90:cb3d968589d8	579	* @name Register SDHC_XFERTYP, field MSBSEL[5] (RW)
Kojto	90:cb3d968589d8	580	*
Kojto	90:cb3d968589d8	581	* Enables multiple block DAT line data transfers. For any other commands, this
Kojto	90:cb3d968589d8	582	* bit shall be set to 0. If this bit is 0, it is not necessary to set the block
Kojto	90:cb3d968589d8	583	* count register.
Kojto	90:cb3d968589d8	584	*
Kojto	90:cb3d968589d8	585	* Values:
Kojto	90:cb3d968589d8	586	* - 0 - Single block.
Kojto	90:cb3d968589d8	587	* - 1 - Multiple blocks.
Kojto	90:cb3d968589d8	588	*/
Kojto	90:cb3d968589d8	589	/@{/
Kojto	90:cb3d968589d8	590	#define BP_SDHC_XFERTYP_MSBSEL (5U) /!< Bit position for SDHC_XFERTYP_MSBSEL. /
Kojto	90:cb3d968589d8	591	#define BM_SDHC_XFERTYP_MSBSEL (0x00000020U) /!< Bit mask for SDHC_XFERTYP_MSBSEL. /
Kojto	90:cb3d968589d8	592	#define BS_SDHC_XFERTYP_MSBSEL (1U) /!< Bit field size in bits for SDHC_XFERTYP_MSBSEL. /
Kojto	90:cb3d968589d8	593
Kojto	90:cb3d968589d8	594	/! @brief Read current value of the SDHC_XFERTYP_MSBSEL field. /
Kojto	90:cb3d968589d8	595	#define BR_SDHC_XFERTYP_MSBSEL(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_MSBSEL))
Kojto	90:cb3d968589d8	596
Kojto	90:cb3d968589d8	597	/! @brief Format value for bitfield SDHC_XFERTYP_MSBSEL. /
Kojto	90:cb3d968589d8	598	#define BF_SDHC_XFERTYP_MSBSEL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_MSBSEL) & BM_SDHC_XFERTYP_MSBSEL)
Kojto	90:cb3d968589d8	599
Kojto	90:cb3d968589d8	600	/! @brief Set the MSBSEL field to a new value. /
Kojto	90:cb3d968589d8	601	#define BW_SDHC_XFERTYP_MSBSEL(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_MSBSEL) = (v))
Kojto	90:cb3d968589d8	602	/@}/
Kojto	90:cb3d968589d8	603
Kojto	90:cb3d968589d8	604	/*!
Kojto	90:cb3d968589d8	605	* @name Register SDHC_XFERTYP, field RSPTYP[17:16] (RW)
Kojto	90:cb3d968589d8	606	*
Kojto	90:cb3d968589d8	607	* Values:
Kojto	90:cb3d968589d8	608	* - 00 - No response.
Kojto	90:cb3d968589d8	609	* - 01 - Response length 136.
Kojto	90:cb3d968589d8	610	* - 10 - Response length 48.
Kojto	90:cb3d968589d8	611	* - 11 - Response length 48, check busy after response.
Kojto	90:cb3d968589d8	612	*/
Kojto	90:cb3d968589d8	613	/@{/
Kojto	90:cb3d968589d8	614	#define BP_SDHC_XFERTYP_RSPTYP (16U) /!< Bit position for SDHC_XFERTYP_RSPTYP. /
Kojto	90:cb3d968589d8	615	#define BM_SDHC_XFERTYP_RSPTYP (0x00030000U) /!< Bit mask for SDHC_XFERTYP_RSPTYP. /
Kojto	90:cb3d968589d8	616	#define BS_SDHC_XFERTYP_RSPTYP (2U) /!< Bit field size in bits for SDHC_XFERTYP_RSPTYP. /
Kojto	90:cb3d968589d8	617
Kojto	90:cb3d968589d8	618	/! @brief Read current value of the SDHC_XFERTYP_RSPTYP field. /
Kojto	90:cb3d968589d8	619	#define BR_SDHC_XFERTYP_RSPTYP(x) (HW_SDHC_XFERTYP(x).B.RSPTYP)
Kojto	90:cb3d968589d8	620
Kojto	90:cb3d968589d8	621	/! @brief Format value for bitfield SDHC_XFERTYP_RSPTYP. /
Kojto	90:cb3d968589d8	622	#define BF_SDHC_XFERTYP_RSPTYP(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_RSPTYP) & BM_SDHC_XFERTYP_RSPTYP)
Kojto	90:cb3d968589d8	623
Kojto	90:cb3d968589d8	624	/! @brief Set the RSPTYP field to a new value. /
Kojto	90:cb3d968589d8	625	#define BW_SDHC_XFERTYP_RSPTYP(x, v) (HW_SDHC_XFERTYP_WR(x, (HW_SDHC_XFERTYP_RD(x) & ~BM_SDHC_XFERTYP_RSPTYP) \| BF_SDHC_XFERTYP_RSPTYP(v)))
Kojto	90:cb3d968589d8	626	/@}/
Kojto	90:cb3d968589d8	627
Kojto	90:cb3d968589d8	628	/*!
Kojto	90:cb3d968589d8	629	* @name Register SDHC_XFERTYP, field CCCEN[19] (RW)
Kojto	90:cb3d968589d8	630	*
Kojto	90:cb3d968589d8	631	* If this bit is set to 1, the SDHC shall check the CRC field in the response.
Kojto	90:cb3d968589d8	632	* If an error is detected, it is reported as a Command CRC Error. If this bit is
Kojto	90:cb3d968589d8	633	* set to 0, the CRC field is not checked. The number of bits checked by the CRC
Kojto	90:cb3d968589d8	634	* field value changes according to the length of the response.
Kojto	90:cb3d968589d8	635	*
Kojto	90:cb3d968589d8	636	* Values:
Kojto	90:cb3d968589d8	637	* - 0 - Disable
Kojto	90:cb3d968589d8	638	* - 1 - Enable
Kojto	90:cb3d968589d8	639	*/
Kojto	90:cb3d968589d8	640	/@{/
Kojto	90:cb3d968589d8	641	#define BP_SDHC_XFERTYP_CCCEN (19U) /!< Bit position for SDHC_XFERTYP_CCCEN. /
Kojto	90:cb3d968589d8	642	#define BM_SDHC_XFERTYP_CCCEN (0x00080000U) /!< Bit mask for SDHC_XFERTYP_CCCEN. /
Kojto	90:cb3d968589d8	643	#define BS_SDHC_XFERTYP_CCCEN (1U) /!< Bit field size in bits for SDHC_XFERTYP_CCCEN. /
Kojto	90:cb3d968589d8	644
Kojto	90:cb3d968589d8	645	/! @brief Read current value of the SDHC_XFERTYP_CCCEN field. /
Kojto	90:cb3d968589d8	646	#define BR_SDHC_XFERTYP_CCCEN(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_CCCEN))
Kojto	90:cb3d968589d8	647
Kojto	90:cb3d968589d8	648	/! @brief Format value for bitfield SDHC_XFERTYP_CCCEN. /
Kojto	90:cb3d968589d8	649	#define BF_SDHC_XFERTYP_CCCEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_CCCEN) & BM_SDHC_XFERTYP_CCCEN)
Kojto	90:cb3d968589d8	650
Kojto	90:cb3d968589d8	651	/! @brief Set the CCCEN field to a new value. /
Kojto	90:cb3d968589d8	652	#define BW_SDHC_XFERTYP_CCCEN(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_CCCEN) = (v))
Kojto	90:cb3d968589d8	653	/@}/
Kojto	90:cb3d968589d8	654
Kojto	90:cb3d968589d8	655	/*!
Kojto	90:cb3d968589d8	656	* @name Register SDHC_XFERTYP, field CICEN[20] (RW)
Kojto	90:cb3d968589d8	657	*
Kojto	90:cb3d968589d8	658	* If this bit is set to 1, the SDHC will check the index field in the response
Kojto	90:cb3d968589d8	659	* to see if it has the same value as the command index. If it is not, it is
Kojto	90:cb3d968589d8	660	* reported as a command index error. If this bit is set to 0, the index field is not
Kojto	90:cb3d968589d8	661	* checked.
Kojto	90:cb3d968589d8	662	*
Kojto	90:cb3d968589d8	663	* Values:
Kojto	90:cb3d968589d8	664	* - 0 - Disable
Kojto	90:cb3d968589d8	665	* - 1 - Enable
Kojto	90:cb3d968589d8	666	*/
Kojto	90:cb3d968589d8	667	/@{/
Kojto	90:cb3d968589d8	668	#define BP_SDHC_XFERTYP_CICEN (20U) /!< Bit position for SDHC_XFERTYP_CICEN. /
Kojto	90:cb3d968589d8	669	#define BM_SDHC_XFERTYP_CICEN (0x00100000U) /!< Bit mask for SDHC_XFERTYP_CICEN. /
Kojto	90:cb3d968589d8	670	#define BS_SDHC_XFERTYP_CICEN (1U) /!< Bit field size in bits for SDHC_XFERTYP_CICEN. /
Kojto	90:cb3d968589d8	671
Kojto	90:cb3d968589d8	672	/! @brief Read current value of the SDHC_XFERTYP_CICEN field. /
Kojto	90:cb3d968589d8	673	#define BR_SDHC_XFERTYP_CICEN(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_CICEN))
Kojto	90:cb3d968589d8	674
Kojto	90:cb3d968589d8	675	/! @brief Format value for bitfield SDHC_XFERTYP_CICEN. /
Kojto	90:cb3d968589d8	676	#define BF_SDHC_XFERTYP_CICEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_CICEN) & BM_SDHC_XFERTYP_CICEN)
Kojto	90:cb3d968589d8	677
Kojto	90:cb3d968589d8	678	/! @brief Set the CICEN field to a new value. /
Kojto	90:cb3d968589d8	679	#define BW_SDHC_XFERTYP_CICEN(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_CICEN) = (v))
Kojto	90:cb3d968589d8	680	/@}/
Kojto	90:cb3d968589d8	681
Kojto	90:cb3d968589d8	682	/*!
Kojto	90:cb3d968589d8	683	* @name Register SDHC_XFERTYP, field DPSEL[21] (RW)
Kojto	90:cb3d968589d8	684	*
Kojto	90:cb3d968589d8	685	* This bit is set to 1 to indicate that data is present and shall be
Kojto	90:cb3d968589d8	686	* transferred using the DAT line. It is set to 0 for the following: Commands using only
Kojto	90:cb3d968589d8	687	* the CMD line, for example: CMD52. Commands with no data transfer, but using the
Kojto	90:cb3d968589d8	688	* busy signal on DAT[0] line, R1b or R5b, for example: CMD38. In resume command,
Kojto	90:cb3d968589d8	689	* this bit shall be set, and other bits in this register shall be set the same
Kojto	90:cb3d968589d8	690	* as when the transfer was initially launched. When the Write Protect switch is
Kojto	90:cb3d968589d8	691	* on, that is, the WPSPL bit is active as 0, any command with a write operation
Kojto	90:cb3d968589d8	692	* will be ignored. That is to say, when this bit is set, while the DTDSEL bit is
Kojto	90:cb3d968589d8	693	* 0, writes to the register Transfer Type are ignored.
Kojto	90:cb3d968589d8	694	*
Kojto	90:cb3d968589d8	695	* Values:
Kojto	90:cb3d968589d8	696	* - 0 - No data present.
Kojto	90:cb3d968589d8	697	* - 1 - Data present.
Kojto	90:cb3d968589d8	698	*/
Kojto	90:cb3d968589d8	699	/@{/
Kojto	90:cb3d968589d8	700	#define BP_SDHC_XFERTYP_DPSEL (21U) /!< Bit position for SDHC_XFERTYP_DPSEL. /
Kojto	90:cb3d968589d8	701	#define BM_SDHC_XFERTYP_DPSEL (0x00200000U) /!< Bit mask for SDHC_XFERTYP_DPSEL. /
Kojto	90:cb3d968589d8	702	#define BS_SDHC_XFERTYP_DPSEL (1U) /!< Bit field size in bits for SDHC_XFERTYP_DPSEL. /
Kojto	90:cb3d968589d8	703
Kojto	90:cb3d968589d8	704	/! @brief Read current value of the SDHC_XFERTYP_DPSEL field. /
Kojto	90:cb3d968589d8	705	#define BR_SDHC_XFERTYP_DPSEL(x) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DPSEL))
Kojto	90:cb3d968589d8	706
Kojto	90:cb3d968589d8	707	/! @brief Format value for bitfield SDHC_XFERTYP_DPSEL. /
Kojto	90:cb3d968589d8	708	#define BF_SDHC_XFERTYP_DPSEL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_DPSEL) & BM_SDHC_XFERTYP_DPSEL)
Kojto	90:cb3d968589d8	709
Kojto	90:cb3d968589d8	710	/! @brief Set the DPSEL field to a new value. /
Kojto	90:cb3d968589d8	711	#define BW_SDHC_XFERTYP_DPSEL(x, v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DPSEL) = (v))
Kojto	90:cb3d968589d8	712	/@}/
Kojto	90:cb3d968589d8	713
Kojto	90:cb3d968589d8	714	/*!
Kojto	90:cb3d968589d8	715	* @name Register SDHC_XFERTYP, field CMDTYP[23:22] (RW)
Kojto	90:cb3d968589d8	716	*
Kojto	90:cb3d968589d8	717	* There are three types of special commands: suspend, resume, and abort. These
Kojto	90:cb3d968589d8	718	* bits shall be set to 00b for all other commands. Suspend command: If the
Kojto	90:cb3d968589d8	719	* suspend command succeeds, the SDHC shall assume that the card bus has been released
Kojto	90:cb3d968589d8	720	* and that it is possible to issue the next command which uses the DAT line.
Kojto	90:cb3d968589d8	721	* Because the SDHC does not monitor the content of command response, it does not
Kojto	90:cb3d968589d8	722	* know if the suspend command succeeded or not. It is the host driver's
Kojto	90:cb3d968589d8	723	* responsibility to check the status of the suspend command and send another command
Kojto	90:cb3d968589d8	724	* marked as suspend to inform the SDHC that a suspend command was successfully
Kojto	90:cb3d968589d8	725	* issued. After the end bit of command is sent, the SDHC deasserts read wait for read
Kojto	90:cb3d968589d8	726	* transactions and stops checking busy for write transactions. In 4-bit mode,
Kojto	90:cb3d968589d8	727	* the interrupt cycle starts. If the suspend command fails, the SDHC will
Kojto	90:cb3d968589d8	728	* maintain its current state, and the host driver shall restart the transfer by setting
Kojto	90:cb3d968589d8	729	* PROCTL[CREQ]. Resume command: The host driver restarts the data transfer by
Kojto	90:cb3d968589d8	730	* restoring the registers saved before sending the suspend command and then sends
Kojto	90:cb3d968589d8	731	* the resume command. The SDHC will check for a pending busy state before
Kojto	90:cb3d968589d8	732	* starting write transfers. Abort command: If this command is set when executing a
Kojto	90:cb3d968589d8	733	* read transfer, the SDHC will stop reads to the buffer. If this command is set
Kojto	90:cb3d968589d8	734	* when executing a write transfer, the SDHC will stop driving the DAT line. After
Kojto	90:cb3d968589d8	735	* issuing the abort command, the host driver must issue a software reset (abort
Kojto	90:cb3d968589d8	736	* transaction).
Kojto	90:cb3d968589d8	737	*
Kojto	90:cb3d968589d8	738	* Values:
Kojto	90:cb3d968589d8	739	* - 00 - Normal other commands.
Kojto	90:cb3d968589d8	740	* - 01 - Suspend CMD52 for writing bus suspend in CCCR.
Kojto	90:cb3d968589d8	741	* - 10 - Resume CMD52 for writing function select in CCCR.
Kojto	90:cb3d968589d8	742	* - 11 - Abort CMD12, CMD52 for writing I/O abort in CCCR.
Kojto	90:cb3d968589d8	743	*/
Kojto	90:cb3d968589d8	744	/@{/
Kojto	90:cb3d968589d8	745	#define BP_SDHC_XFERTYP_CMDTYP (22U) /!< Bit position for SDHC_XFERTYP_CMDTYP. /
Kojto	90:cb3d968589d8	746	#define BM_SDHC_XFERTYP_CMDTYP (0x00C00000U) /!< Bit mask for SDHC_XFERTYP_CMDTYP. /
Kojto	90:cb3d968589d8	747	#define BS_SDHC_XFERTYP_CMDTYP (2U) /!< Bit field size in bits for SDHC_XFERTYP_CMDTYP. /
Kojto	90:cb3d968589d8	748
Kojto	90:cb3d968589d8	749	/! @brief Read current value of the SDHC_XFERTYP_CMDTYP field. /
Kojto	90:cb3d968589d8	750	#define BR_SDHC_XFERTYP_CMDTYP(x) (HW_SDHC_XFERTYP(x).B.CMDTYP)
Kojto	90:cb3d968589d8	751
Kojto	90:cb3d968589d8	752	/! @brief Format value for bitfield SDHC_XFERTYP_CMDTYP. /
Kojto	90:cb3d968589d8	753	#define BF_SDHC_XFERTYP_CMDTYP(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_CMDTYP) & BM_SDHC_XFERTYP_CMDTYP)
Kojto	90:cb3d968589d8	754
Kojto	90:cb3d968589d8	755	/! @brief Set the CMDTYP field to a new value. /
Kojto	90:cb3d968589d8	756	#define BW_SDHC_XFERTYP_CMDTYP(x, v) (HW_SDHC_XFERTYP_WR(x, (HW_SDHC_XFERTYP_RD(x) & ~BM_SDHC_XFERTYP_CMDTYP) \| BF_SDHC_XFERTYP_CMDTYP(v)))
Kojto	90:cb3d968589d8	757	/@}/
Kojto	90:cb3d968589d8	758
Kojto	90:cb3d968589d8	759	/*!
Kojto	90:cb3d968589d8	760	* @name Register SDHC_XFERTYP, field CMDINX[29:24] (RW)
Kojto	90:cb3d968589d8	761	*
Kojto	90:cb3d968589d8	762	* These bits shall be set to the command number that is specified in bits 45-40
Kojto	90:cb3d968589d8	763	* of the command-format in the SD Memory Card Physical Layer Specification and
Kojto	90:cb3d968589d8	764	* SDIO Card Specification.
Kojto	90:cb3d968589d8	765	*/
Kojto	90:cb3d968589d8	766	/@{/
Kojto	90:cb3d968589d8	767	#define BP_SDHC_XFERTYP_CMDINX (24U) /!< Bit position for SDHC_XFERTYP_CMDINX. /
Kojto	90:cb3d968589d8	768	#define BM_SDHC_XFERTYP_CMDINX (0x3F000000U) /!< Bit mask for SDHC_XFERTYP_CMDINX. /
Kojto	90:cb3d968589d8	769	#define BS_SDHC_XFERTYP_CMDINX (6U) /!< Bit field size in bits for SDHC_XFERTYP_CMDINX. /
Kojto	90:cb3d968589d8	770
Kojto	90:cb3d968589d8	771	/! @brief Read current value of the SDHC_XFERTYP_CMDINX field. /
Kojto	90:cb3d968589d8	772	#define BR_SDHC_XFERTYP_CMDINX(x) (HW_SDHC_XFERTYP(x).B.CMDINX)
Kojto	90:cb3d968589d8	773
Kojto	90:cb3d968589d8	774	/! @brief Format value for bitfield SDHC_XFERTYP_CMDINX. /
Kojto	90:cb3d968589d8	775	#define BF_SDHC_XFERTYP_CMDINX(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_CMDINX) & BM_SDHC_XFERTYP_CMDINX)
Kojto	90:cb3d968589d8	776
Kojto	90:cb3d968589d8	777	/! @brief Set the CMDINX field to a new value. /
Kojto	90:cb3d968589d8	778	#define BW_SDHC_XFERTYP_CMDINX(x, v) (HW_SDHC_XFERTYP_WR(x, (HW_SDHC_XFERTYP_RD(x) & ~BM_SDHC_XFERTYP_CMDINX) \| BF_SDHC_XFERTYP_CMDINX(v)))
Kojto	90:cb3d968589d8	779	/@}/
Kojto	90:cb3d968589d8	780
Kojto	90:cb3d968589d8	781	/*******************************************************************************
Kojto	90:cb3d968589d8	782	* HW_SDHC_CMDRSP0 - Command Response 0
Kojto	90:cb3d968589d8	783	******************************************************************************/
Kojto	90:cb3d968589d8	784
Kojto	90:cb3d968589d8	785	/*!
Kojto	90:cb3d968589d8	786	* @brief HW_SDHC_CMDRSP0 - Command Response 0 (RO)
Kojto	90:cb3d968589d8	787	*
Kojto	90:cb3d968589d8	788	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	789	*
Kojto	90:cb3d968589d8	790	* This register is used to store part 0 of the response bits from the card.
Kojto	90:cb3d968589d8	791	*/
Kojto	90:cb3d968589d8	792	typedef union _hw_sdhc_cmdrsp0
Kojto	90:cb3d968589d8	793	{
Kojto	90:cb3d968589d8	794	uint32_t U;
Kojto	90:cb3d968589d8	795	struct _hw_sdhc_cmdrsp0_bitfields
Kojto	90:cb3d968589d8	796	{
Kojto	90:cb3d968589d8	797	uint32_t CMDRSP0 : 32; /!< [31:0] Command Response 0 /
Kojto	90:cb3d968589d8	798	} B;
Kojto	90:cb3d968589d8	799	} hw_sdhc_cmdrsp0_t;
Kojto	90:cb3d968589d8	800
Kojto	90:cb3d968589d8	801	/*!
Kojto	90:cb3d968589d8	802	* @name Constants and macros for entire SDHC_CMDRSP0 register
Kojto	90:cb3d968589d8	803	*/
Kojto	90:cb3d968589d8	804	/@{/
Kojto	90:cb3d968589d8	805	#define HW_SDHC_CMDRSP0_ADDR(x) ((x) + 0x10U)
Kojto	90:cb3d968589d8	806
Kojto	90:cb3d968589d8	807	#define HW_SDHC_CMDRSP0(x) ((__I hw_sdhc_cmdrsp0_t ) HW_SDHC_CMDRSP0_ADDR(x))
Kojto	90:cb3d968589d8	808	#define HW_SDHC_CMDRSP0_RD(x) (HW_SDHC_CMDRSP0(x).U)
Kojto	90:cb3d968589d8	809	/@}/
Kojto	90:cb3d968589d8	810
Kojto	90:cb3d968589d8	811	/*
Kojto	90:cb3d968589d8	812	* Constants & macros for individual SDHC_CMDRSP0 bitfields
Kojto	90:cb3d968589d8	813	*/
Kojto	90:cb3d968589d8	814
Kojto	90:cb3d968589d8	815	/*!
Kojto	90:cb3d968589d8	816	* @name Register SDHC_CMDRSP0, field CMDRSP0[31:0] (RO)
Kojto	90:cb3d968589d8	817	*/
Kojto	90:cb3d968589d8	818	/@{/
Kojto	90:cb3d968589d8	819	#define BP_SDHC_CMDRSP0_CMDRSP0 (0U) /!< Bit position for SDHC_CMDRSP0_CMDRSP0. /
Kojto	90:cb3d968589d8	820	#define BM_SDHC_CMDRSP0_CMDRSP0 (0xFFFFFFFFU) /!< Bit mask for SDHC_CMDRSP0_CMDRSP0. /
Kojto	90:cb3d968589d8	821	#define BS_SDHC_CMDRSP0_CMDRSP0 (32U) /!< Bit field size in bits for SDHC_CMDRSP0_CMDRSP0. /
Kojto	90:cb3d968589d8	822
Kojto	90:cb3d968589d8	823	/! @brief Read current value of the SDHC_CMDRSP0_CMDRSP0 field. /
Kojto	90:cb3d968589d8	824	#define BR_SDHC_CMDRSP0_CMDRSP0(x) (HW_SDHC_CMDRSP0(x).U)
Kojto	90:cb3d968589d8	825	/@}/
Kojto	90:cb3d968589d8	826
Kojto	90:cb3d968589d8	827	/*******************************************************************************
Kojto	90:cb3d968589d8	828	* HW_SDHC_CMDRSP1 - Command Response 1
Kojto	90:cb3d968589d8	829	******************************************************************************/
Kojto	90:cb3d968589d8	830
Kojto	90:cb3d968589d8	831	/*!
Kojto	90:cb3d968589d8	832	* @brief HW_SDHC_CMDRSP1 - Command Response 1 (RO)
Kojto	90:cb3d968589d8	833	*
Kojto	90:cb3d968589d8	834	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	835	*
Kojto	90:cb3d968589d8	836	* This register is used to store part 1 of the response bits from the card.
Kojto	90:cb3d968589d8	837	*/
Kojto	90:cb3d968589d8	838	typedef union _hw_sdhc_cmdrsp1
Kojto	90:cb3d968589d8	839	{
Kojto	90:cb3d968589d8	840	uint32_t U;
Kojto	90:cb3d968589d8	841	struct _hw_sdhc_cmdrsp1_bitfields
Kojto	90:cb3d968589d8	842	{
Kojto	90:cb3d968589d8	843	uint32_t CMDRSP1 : 32; /!< [31:0] Command Response 1 /
Kojto	90:cb3d968589d8	844	} B;
Kojto	90:cb3d968589d8	845	} hw_sdhc_cmdrsp1_t;
Kojto	90:cb3d968589d8	846
Kojto	90:cb3d968589d8	847	/*!
Kojto	90:cb3d968589d8	848	* @name Constants and macros for entire SDHC_CMDRSP1 register
Kojto	90:cb3d968589d8	849	*/
Kojto	90:cb3d968589d8	850	/@{/
Kojto	90:cb3d968589d8	851	#define HW_SDHC_CMDRSP1_ADDR(x) ((x) + 0x14U)
Kojto	90:cb3d968589d8	852
Kojto	90:cb3d968589d8	853	#define HW_SDHC_CMDRSP1(x) ((__I hw_sdhc_cmdrsp1_t ) HW_SDHC_CMDRSP1_ADDR(x))
Kojto	90:cb3d968589d8	854	#define HW_SDHC_CMDRSP1_RD(x) (HW_SDHC_CMDRSP1(x).U)
Kojto	90:cb3d968589d8	855	/@}/
Kojto	90:cb3d968589d8	856
Kojto	90:cb3d968589d8	857	/*
Kojto	90:cb3d968589d8	858	* Constants & macros for individual SDHC_CMDRSP1 bitfields
Kojto	90:cb3d968589d8	859	*/
Kojto	90:cb3d968589d8	860
Kojto	90:cb3d968589d8	861	/*!
Kojto	90:cb3d968589d8	862	* @name Register SDHC_CMDRSP1, field CMDRSP1[31:0] (RO)
Kojto	90:cb3d968589d8	863	*/
Kojto	90:cb3d968589d8	864	/@{/
Kojto	90:cb3d968589d8	865	#define BP_SDHC_CMDRSP1_CMDRSP1 (0U) /!< Bit position for SDHC_CMDRSP1_CMDRSP1. /
Kojto	90:cb3d968589d8	866	#define BM_SDHC_CMDRSP1_CMDRSP1 (0xFFFFFFFFU) /!< Bit mask for SDHC_CMDRSP1_CMDRSP1. /
Kojto	90:cb3d968589d8	867	#define BS_SDHC_CMDRSP1_CMDRSP1 (32U) /!< Bit field size in bits for SDHC_CMDRSP1_CMDRSP1. /
Kojto	90:cb3d968589d8	868
Kojto	90:cb3d968589d8	869	/! @brief Read current value of the SDHC_CMDRSP1_CMDRSP1 field. /
Kojto	90:cb3d968589d8	870	#define BR_SDHC_CMDRSP1_CMDRSP1(x) (HW_SDHC_CMDRSP1(x).U)
Kojto	90:cb3d968589d8	871	/@}/
Kojto	90:cb3d968589d8	872
Kojto	90:cb3d968589d8	873	/*******************************************************************************
Kojto	90:cb3d968589d8	874	* HW_SDHC_CMDRSP2 - Command Response 2
Kojto	90:cb3d968589d8	875	******************************************************************************/
Kojto	90:cb3d968589d8	876
Kojto	90:cb3d968589d8	877	/*!
Kojto	90:cb3d968589d8	878	* @brief HW_SDHC_CMDRSP2 - Command Response 2 (RO)
Kojto	90:cb3d968589d8	879	*
Kojto	90:cb3d968589d8	880	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	881	*
Kojto	90:cb3d968589d8	882	* This register is used to store part 2 of the response bits from the card.
Kojto	90:cb3d968589d8	883	*/
Kojto	90:cb3d968589d8	884	typedef union _hw_sdhc_cmdrsp2
Kojto	90:cb3d968589d8	885	{
Kojto	90:cb3d968589d8	886	uint32_t U;
Kojto	90:cb3d968589d8	887	struct _hw_sdhc_cmdrsp2_bitfields
Kojto	90:cb3d968589d8	888	{
Kojto	90:cb3d968589d8	889	uint32_t CMDRSP2 : 32; /!< [31:0] Command Response 2 /
Kojto	90:cb3d968589d8	890	} B;
Kojto	90:cb3d968589d8	891	} hw_sdhc_cmdrsp2_t;
Kojto	90:cb3d968589d8	892
Kojto	90:cb3d968589d8	893	/*!
Kojto	90:cb3d968589d8	894	* @name Constants and macros for entire SDHC_CMDRSP2 register
Kojto	90:cb3d968589d8	895	*/
Kojto	90:cb3d968589d8	896	/@{/
Kojto	90:cb3d968589d8	897	#define HW_SDHC_CMDRSP2_ADDR(x) ((x) + 0x18U)
Kojto	90:cb3d968589d8	898
Kojto	90:cb3d968589d8	899	#define HW_SDHC_CMDRSP2(x) ((__I hw_sdhc_cmdrsp2_t ) HW_SDHC_CMDRSP2_ADDR(x))
Kojto	90:cb3d968589d8	900	#define HW_SDHC_CMDRSP2_RD(x) (HW_SDHC_CMDRSP2(x).U)
Kojto	90:cb3d968589d8	901	/@}/
Kojto	90:cb3d968589d8	902
Kojto	90:cb3d968589d8	903	/*
Kojto	90:cb3d968589d8	904	* Constants & macros for individual SDHC_CMDRSP2 bitfields
Kojto	90:cb3d968589d8	905	*/
Kojto	90:cb3d968589d8	906
Kojto	90:cb3d968589d8	907	/*!
Kojto	90:cb3d968589d8	908	* @name Register SDHC_CMDRSP2, field CMDRSP2[31:0] (RO)
Kojto	90:cb3d968589d8	909	*/
Kojto	90:cb3d968589d8	910	/@{/
Kojto	90:cb3d968589d8	911	#define BP_SDHC_CMDRSP2_CMDRSP2 (0U) /!< Bit position for SDHC_CMDRSP2_CMDRSP2. /
Kojto	90:cb3d968589d8	912	#define BM_SDHC_CMDRSP2_CMDRSP2 (0xFFFFFFFFU) /!< Bit mask for SDHC_CMDRSP2_CMDRSP2. /
Kojto	90:cb3d968589d8	913	#define BS_SDHC_CMDRSP2_CMDRSP2 (32U) /!< Bit field size in bits for SDHC_CMDRSP2_CMDRSP2. /
Kojto	90:cb3d968589d8	914
Kojto	90:cb3d968589d8	915	/! @brief Read current value of the SDHC_CMDRSP2_CMDRSP2 field. /
Kojto	90:cb3d968589d8	916	#define BR_SDHC_CMDRSP2_CMDRSP2(x) (HW_SDHC_CMDRSP2(x).U)
Kojto	90:cb3d968589d8	917	/@}/
Kojto	90:cb3d968589d8	918
Kojto	90:cb3d968589d8	919	/*******************************************************************************
Kojto	90:cb3d968589d8	920	* HW_SDHC_CMDRSP3 - Command Response 3
Kojto	90:cb3d968589d8	921	******************************************************************************/
Kojto	90:cb3d968589d8	922
Kojto	90:cb3d968589d8	923	/*!
Kojto	90:cb3d968589d8	924	* @brief HW_SDHC_CMDRSP3 - Command Response 3 (RO)
Kojto	90:cb3d968589d8	925	*
Kojto	90:cb3d968589d8	926	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	927	*
Kojto	90:cb3d968589d8	928	* This register is used to store part 3 of the response bits from the card. The
Kojto	90:cb3d968589d8	929	* following table describes the mapping of command responses from the SD bus to
Kojto	90:cb3d968589d8	930	* command response registers for each response type. In the table, R[ ] refers
Kojto	90:cb3d968589d8	931	* to a bit range within the response data as transmitted on the SD bus. Response
Kojto	90:cb3d968589d8	932	* bit definition for each response type Response type Meaning of response
Kojto	90:cb3d968589d8	933	* Response field Response register R1,R1b (normal response) Card status R[39:8]
Kojto	90:cb3d968589d8	934	* CMDRSP0 R1b (Auto CMD12 response) Card status for auto CMD12 R[39:8] CMDRSP3 R2
Kojto	90:cb3d968589d8	935	* (CID, CSD register) CID/CSD register [127:8] R[127:8] {CMDRSP3[23:0], CMDRSP2,
Kojto	90:cb3d968589d8	936	* CMDRSP1, CMDRSP0} R3 (OCR register) OCR register for memory R[39:8] CMDRSP0 R4
Kojto	90:cb3d968589d8	937	* (OCR register) OCR register for I/O etc. R[39:8] CMDRSP0 R5, R5b SDIO response
Kojto	90:cb3d968589d8	938	* R[39:8] CMDRSP0 R6 (Publish RCA) New published RCA[31:16] and card
Kojto	90:cb3d968589d8	939	* status[15:0] R[39:9] CMDRSP0 This table shows that most responses with a length of 48
Kojto	90:cb3d968589d8	940	* (R[47:0]) have 32-bit of the response data (R[39:8]) stored in the CMDRSP0
Kojto	90:cb3d968589d8	941	* register. Responses of type R1b (auto CMD12 responses) have response data bits
Kojto	90:cb3d968589d8	942	* (R[39:8]) stored in the CMDRSP3 register. Responses with length 136 (R[135:0]) have
Kojto	90:cb3d968589d8	943	* 120-bit of the response data (R[127:8]) stored in the CMDRSP0, 1, 2, and 3
Kojto	90:cb3d968589d8	944	* registers. To be able to read the response status efficiently, the SDHC stores
Kojto	90:cb3d968589d8	945	* only a part of the response data in the command response registers. This
Kojto	90:cb3d968589d8	946	* enables the host driver to efficiently read 32-bit of response data in one read
Kojto	90:cb3d968589d8	947	* cycle on a 32-bit bus system. Parts of the response, the index field and the CRC,
Kojto	90:cb3d968589d8	948	* are checked by the SDHC, as specified by XFERTYP[CICEN] and XFERTYP[CCCEN],
Kojto	90:cb3d968589d8	949	* and generate an error interrupt if any error is detected. The bit range for the
Kojto	90:cb3d968589d8	950	* CRC check depends on the response length. If the response length is 48, the
Kojto	90:cb3d968589d8	951	* SDHC will check R[47:1], and if the response length is 136 the SDHC will check
Kojto	90:cb3d968589d8	952	* R[119:1]. Because the SDHC may have a multiple block data transfer executing
Kojto	90:cb3d968589d8	953	* concurrently with a CMD_wo_DAT command, the SDHC stores the auto CMD12 response
Kojto	90:cb3d968589d8	954	* in the CMDRSP3 register. The CMD_wo_DAT response is stored in CMDRSP0. This
Kojto	90:cb3d968589d8	955	* allows the SDHC to avoid overwriting the Auto CMD12 response with the CMD_wo_DAT
Kojto	90:cb3d968589d8	956	* and vice versa. When the SDHC modifies part of the command response
Kojto	90:cb3d968589d8	957	* registers, as shown in the table above, it preserves the unmodified bits.
Kojto	90:cb3d968589d8	958	*/
Kojto	90:cb3d968589d8	959	typedef union _hw_sdhc_cmdrsp3
Kojto	90:cb3d968589d8	960	{
Kojto	90:cb3d968589d8	961	uint32_t U;
Kojto	90:cb3d968589d8	962	struct _hw_sdhc_cmdrsp3_bitfields
Kojto	90:cb3d968589d8	963	{
Kojto	90:cb3d968589d8	964	uint32_t CMDRSP3 : 32; /!< [31:0] Command Response 3 /
Kojto	90:cb3d968589d8	965	} B;
Kojto	90:cb3d968589d8	966	} hw_sdhc_cmdrsp3_t;
Kojto	90:cb3d968589d8	967
Kojto	90:cb3d968589d8	968	/*!
Kojto	90:cb3d968589d8	969	* @name Constants and macros for entire SDHC_CMDRSP3 register
Kojto	90:cb3d968589d8	970	*/
Kojto	90:cb3d968589d8	971	/@{/
Kojto	90:cb3d968589d8	972	#define HW_SDHC_CMDRSP3_ADDR(x) ((x) + 0x1CU)
Kojto	90:cb3d968589d8	973
Kojto	90:cb3d968589d8	974	#define HW_SDHC_CMDRSP3(x) ((__I hw_sdhc_cmdrsp3_t ) HW_SDHC_CMDRSP3_ADDR(x))
Kojto	90:cb3d968589d8	975	#define HW_SDHC_CMDRSP3_RD(x) (HW_SDHC_CMDRSP3(x).U)
Kojto	90:cb3d968589d8	976	/@}/
Kojto	90:cb3d968589d8	977
Kojto	90:cb3d968589d8	978	/*
Kojto	90:cb3d968589d8	979	* Constants & macros for individual SDHC_CMDRSP3 bitfields
Kojto	90:cb3d968589d8	980	*/
Kojto	90:cb3d968589d8	981
Kojto	90:cb3d968589d8	982	/*!
Kojto	90:cb3d968589d8	983	* @name Register SDHC_CMDRSP3, field CMDRSP3[31:0] (RO)
Kojto	90:cb3d968589d8	984	*/
Kojto	90:cb3d968589d8	985	/@{/
Kojto	90:cb3d968589d8	986	#define BP_SDHC_CMDRSP3_CMDRSP3 (0U) /!< Bit position for SDHC_CMDRSP3_CMDRSP3. /
Kojto	90:cb3d968589d8	987	#define BM_SDHC_CMDRSP3_CMDRSP3 (0xFFFFFFFFU) /!< Bit mask for SDHC_CMDRSP3_CMDRSP3. /
Kojto	90:cb3d968589d8	988	#define BS_SDHC_CMDRSP3_CMDRSP3 (32U) /!< Bit field size in bits for SDHC_CMDRSP3_CMDRSP3. /
Kojto	90:cb3d968589d8	989
Kojto	90:cb3d968589d8	990	/! @brief Read current value of the SDHC_CMDRSP3_CMDRSP3 field. /
Kojto	90:cb3d968589d8	991	#define BR_SDHC_CMDRSP3_CMDRSP3(x) (HW_SDHC_CMDRSP3(x).U)
Kojto	90:cb3d968589d8	992	/@}/
Kojto	90:cb3d968589d8	993
Kojto	90:cb3d968589d8	994	/*******************************************************************************
Kojto	90:cb3d968589d8	995	* HW_SDHC_DATPORT - Buffer Data Port register
Kojto	90:cb3d968589d8	996	******************************************************************************/
Kojto	90:cb3d968589d8	997
Kojto	90:cb3d968589d8	998	/*!
Kojto	90:cb3d968589d8	999	* @brief HW_SDHC_DATPORT - Buffer Data Port register (RW)
Kojto	90:cb3d968589d8	1000	*
Kojto	90:cb3d968589d8	1001	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1002	*
Kojto	90:cb3d968589d8	1003	* This is a 32-bit data port register used to access the internal buffer and it
Kojto	90:cb3d968589d8	1004	* cannot be updated in Idle mode.
Kojto	90:cb3d968589d8	1005	*/
Kojto	90:cb3d968589d8	1006	typedef union _hw_sdhc_datport
Kojto	90:cb3d968589d8	1007	{
Kojto	90:cb3d968589d8	1008	uint32_t U;
Kojto	90:cb3d968589d8	1009	struct _hw_sdhc_datport_bitfields
Kojto	90:cb3d968589d8	1010	{
Kojto	90:cb3d968589d8	1011	uint32_t DATCONT : 32; /!< [31:0] Data Content /
Kojto	90:cb3d968589d8	1012	} B;
Kojto	90:cb3d968589d8	1013	} hw_sdhc_datport_t;
Kojto	90:cb3d968589d8	1014
Kojto	90:cb3d968589d8	1015	/*!
Kojto	90:cb3d968589d8	1016	* @name Constants and macros for entire SDHC_DATPORT register
Kojto	90:cb3d968589d8	1017	*/
Kojto	90:cb3d968589d8	1018	/@{/
Kojto	90:cb3d968589d8	1019	#define HW_SDHC_DATPORT_ADDR(x) ((x) + 0x20U)
Kojto	90:cb3d968589d8	1020
Kojto	90:cb3d968589d8	1021	#define HW_SDHC_DATPORT(x) ((__IO hw_sdhc_datport_t ) HW_SDHC_DATPORT_ADDR(x))
Kojto	90:cb3d968589d8	1022	#define HW_SDHC_DATPORT_RD(x) (HW_SDHC_DATPORT(x).U)
Kojto	90:cb3d968589d8	1023	#define HW_SDHC_DATPORT_WR(x, v) (HW_SDHC_DATPORT(x).U = (v))
Kojto	90:cb3d968589d8	1024	#define HW_SDHC_DATPORT_SET(x, v) (HW_SDHC_DATPORT_WR(x, HW_SDHC_DATPORT_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1025	#define HW_SDHC_DATPORT_CLR(x, v) (HW_SDHC_DATPORT_WR(x, HW_SDHC_DATPORT_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1026	#define HW_SDHC_DATPORT_TOG(x, v) (HW_SDHC_DATPORT_WR(x, HW_SDHC_DATPORT_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1027	/@}/
Kojto	90:cb3d968589d8	1028
Kojto	90:cb3d968589d8	1029	/*
Kojto	90:cb3d968589d8	1030	* Constants & macros for individual SDHC_DATPORT bitfields
Kojto	90:cb3d968589d8	1031	*/
Kojto	90:cb3d968589d8	1032
Kojto	90:cb3d968589d8	1033	/*!
Kojto	90:cb3d968589d8	1034	* @name Register SDHC_DATPORT, field DATCONT[31:0] (RW)
Kojto	90:cb3d968589d8	1035	*
Kojto	90:cb3d968589d8	1036	* The Buffer Data Port register is for 32-bit data access by the CPU or the
Kojto	90:cb3d968589d8	1037	* external DMA. When the internal DMA is enabled, any write to this register is
Kojto	90:cb3d968589d8	1038	* ignored, and any read from this register will always yield 0s.
Kojto	90:cb3d968589d8	1039	*/
Kojto	90:cb3d968589d8	1040	/@{/
Kojto	90:cb3d968589d8	1041	#define BP_SDHC_DATPORT_DATCONT (0U) /!< Bit position for SDHC_DATPORT_DATCONT. /
Kojto	90:cb3d968589d8	1042	#define BM_SDHC_DATPORT_DATCONT (0xFFFFFFFFU) /!< Bit mask for SDHC_DATPORT_DATCONT. /
Kojto	90:cb3d968589d8	1043	#define BS_SDHC_DATPORT_DATCONT (32U) /!< Bit field size in bits for SDHC_DATPORT_DATCONT. /
Kojto	90:cb3d968589d8	1044
Kojto	90:cb3d968589d8	1045	/! @brief Read current value of the SDHC_DATPORT_DATCONT field. /
Kojto	90:cb3d968589d8	1046	#define BR_SDHC_DATPORT_DATCONT(x) (HW_SDHC_DATPORT(x).U)
Kojto	90:cb3d968589d8	1047
Kojto	90:cb3d968589d8	1048	/! @brief Format value for bitfield SDHC_DATPORT_DATCONT. /
Kojto	90:cb3d968589d8	1049	#define BF_SDHC_DATPORT_DATCONT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_DATPORT_DATCONT) & BM_SDHC_DATPORT_DATCONT)
Kojto	90:cb3d968589d8	1050
Kojto	90:cb3d968589d8	1051	/! @brief Set the DATCONT field to a new value. /
Kojto	90:cb3d968589d8	1052	#define BW_SDHC_DATPORT_DATCONT(x, v) (HW_SDHC_DATPORT_WR(x, v))
Kojto	90:cb3d968589d8	1053	/@}/
Kojto	90:cb3d968589d8	1054
Kojto	90:cb3d968589d8	1055	/*******************************************************************************
Kojto	90:cb3d968589d8	1056	* HW_SDHC_PRSSTAT - Present State register
Kojto	90:cb3d968589d8	1057	******************************************************************************/
Kojto	90:cb3d968589d8	1058
Kojto	90:cb3d968589d8	1059	/*!
Kojto	90:cb3d968589d8	1060	* @brief HW_SDHC_PRSSTAT - Present State register (RO)
Kojto	90:cb3d968589d8	1061	*
Kojto	90:cb3d968589d8	1062	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1063	*
Kojto	90:cb3d968589d8	1064	* The host driver can get status of the SDHC from this 32-bit read-only
Kojto	90:cb3d968589d8	1065	* register. The host driver can issue CMD0, CMD12, CMD13 (for memory) and CMD52 (for
Kojto	90:cb3d968589d8	1066	* SDIO) when the DAT lines are busy during a data transfer. These commands can be
Kojto	90:cb3d968589d8	1067	* issued when Command Inhibit (CIHB) is set to zero. Other commands shall be
Kojto	90:cb3d968589d8	1068	* issued when Command Inhibit (CDIHB) is set to zero. Possible changes to the SD
Kojto	90:cb3d968589d8	1069	* Physical Specification may add other commands to this list in the future.
Kojto	90:cb3d968589d8	1070	*/
Kojto	90:cb3d968589d8	1071	typedef union _hw_sdhc_prsstat
Kojto	90:cb3d968589d8	1072	{
Kojto	90:cb3d968589d8	1073	uint32_t U;
Kojto	90:cb3d968589d8	1074	struct _hw_sdhc_prsstat_bitfields
Kojto	90:cb3d968589d8	1075	{
Kojto	90:cb3d968589d8	1076	uint32_t CIHB : 1; /!< [0] Command Inhibit (CMD) /
Kojto	90:cb3d968589d8	1077	uint32_t CDIHB : 1; /!< [1] Command Inhibit (DAT) /
Kojto	90:cb3d968589d8	1078	uint32_t DLA : 1; /!< [2] Data Line Active /
Kojto	90:cb3d968589d8	1079	uint32_t SDSTB : 1; /!< [3] SD Clock Stable /
Kojto	90:cb3d968589d8	1080	uint32_t IPGOFF : 1; /!< [4] Bus Clock Gated Off Internally /
Kojto	90:cb3d968589d8	1081	uint32_t HCKOFF : 1; /!< [5] System Clock Gated Off Internally /
Kojto	90:cb3d968589d8	1082	uint32_t PEROFF : 1; /!< [6] SDHC clock Gated Off Internally /
Kojto	90:cb3d968589d8	1083	uint32_t SDOFF : 1; /!< [7] SD Clock Gated Off Internally /
Kojto	90:cb3d968589d8	1084	uint32_t WTA : 1; /!< [8] Write Transfer Active /
Kojto	90:cb3d968589d8	1085	uint32_t RTA : 1; /!< [9] Read Transfer Active /
Kojto	90:cb3d968589d8	1086	uint32_t BWEN : 1; /!< [10] Buffer Write Enable /
Kojto	90:cb3d968589d8	1087	uint32_t BREN : 1; /!< [11] Buffer Read Enable /
Kojto	90:cb3d968589d8	1088	uint32_t RESERVED0 : 4; /!< [15:12] /
Kojto	90:cb3d968589d8	1089	uint32_t CINS : 1; /!< [16] Card Inserted /
Kojto	90:cb3d968589d8	1090	uint32_t RESERVED1 : 6; /!< [22:17] /
Kojto	90:cb3d968589d8	1091	uint32_t CLSL : 1; /!< [23] CMD Line Signal Level /
Kojto	90:cb3d968589d8	1092	uint32_t DLSL : 8; /!< [31:24] DAT Line Signal Level /
Kojto	90:cb3d968589d8	1093	} B;
Kojto	90:cb3d968589d8	1094	} hw_sdhc_prsstat_t;
Kojto	90:cb3d968589d8	1095
Kojto	90:cb3d968589d8	1096	/*!
Kojto	90:cb3d968589d8	1097	* @name Constants and macros for entire SDHC_PRSSTAT register
Kojto	90:cb3d968589d8	1098	*/
Kojto	90:cb3d968589d8	1099	/@{/
Kojto	90:cb3d968589d8	1100	#define HW_SDHC_PRSSTAT_ADDR(x) ((x) + 0x24U)
Kojto	90:cb3d968589d8	1101
Kojto	90:cb3d968589d8	1102	#define HW_SDHC_PRSSTAT(x) ((__I hw_sdhc_prsstat_t ) HW_SDHC_PRSSTAT_ADDR(x))
Kojto	90:cb3d968589d8	1103	#define HW_SDHC_PRSSTAT_RD(x) (HW_SDHC_PRSSTAT(x).U)
Kojto	90:cb3d968589d8	1104	/@}/
Kojto	90:cb3d968589d8	1105
Kojto	90:cb3d968589d8	1106	/*
Kojto	90:cb3d968589d8	1107	* Constants & macros for individual SDHC_PRSSTAT bitfields
Kojto	90:cb3d968589d8	1108	*/
Kojto	90:cb3d968589d8	1109
Kojto	90:cb3d968589d8	1110	/*!
Kojto	90:cb3d968589d8	1111	* @name Register SDHC_PRSSTAT, field CIHB[0] (RO)
Kojto	90:cb3d968589d8	1112	*
Kojto	90:cb3d968589d8	1113	* If this status bit is 0, it indicates that the CMD line is not in use and the
Kojto	90:cb3d968589d8	1114	* SDHC can issue a SD/MMC Command using the CMD line. This bit is set also
Kojto	90:cb3d968589d8	1115	* immediately after the Transfer Type register is written. This bit is cleared when
Kojto	90:cb3d968589d8	1116	* the command response is received. Even if the CDIHB bit is set to 1, Commands
Kojto	90:cb3d968589d8	1117	* using only the CMD line can be issued if this bit is 0. Changing from 1 to 0
Kojto	90:cb3d968589d8	1118	* generates a command complete interrupt in the interrupt status register. If the
Kojto	90:cb3d968589d8	1119	* SDHC cannot issue the command because of a command conflict error (see
Kojto	90:cb3d968589d8	1120	* command CRC error) or because of a command not issued by auto CMD12 error, this bit
Kojto	90:cb3d968589d8	1121	* will remain 1 and the command complete is not set. The status of issuing an
Kojto	90:cb3d968589d8	1122	* auto CMD12 does not show on this bit.
Kojto	90:cb3d968589d8	1123	*
Kojto	90:cb3d968589d8	1124	* Values:
Kojto	90:cb3d968589d8	1125	* - 0 - Can issue command using only CMD line.
Kojto	90:cb3d968589d8	1126	* - 1 - Cannot issue command.
Kojto	90:cb3d968589d8	1127	*/
Kojto	90:cb3d968589d8	1128	/@{/
Kojto	90:cb3d968589d8	1129	#define BP_SDHC_PRSSTAT_CIHB (0U) /!< Bit position for SDHC_PRSSTAT_CIHB. /
Kojto	90:cb3d968589d8	1130	#define BM_SDHC_PRSSTAT_CIHB (0x00000001U) /!< Bit mask for SDHC_PRSSTAT_CIHB. /
Kojto	90:cb3d968589d8	1131	#define BS_SDHC_PRSSTAT_CIHB (1U) /!< Bit field size in bits for SDHC_PRSSTAT_CIHB. /
Kojto	90:cb3d968589d8	1132
Kojto	90:cb3d968589d8	1133	/! @brief Read current value of the SDHC_PRSSTAT_CIHB field. /
Kojto	90:cb3d968589d8	1134	#define BR_SDHC_PRSSTAT_CIHB(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_CIHB))
Kojto	90:cb3d968589d8	1135	/@}/
Kojto	90:cb3d968589d8	1136
Kojto	90:cb3d968589d8	1137	/*!
Kojto	90:cb3d968589d8	1138	* @name Register SDHC_PRSSTAT, field CDIHB[1] (RO)
Kojto	90:cb3d968589d8	1139	*
Kojto	90:cb3d968589d8	1140	* This status bit is generated if either the DLA or the RTA is set to 1. If
Kojto	90:cb3d968589d8	1141	* this bit is 0, it indicates that the SDHC can issue the next SD/MMC Command.
Kojto	90:cb3d968589d8	1142	* Commands with a busy signal belong to CDIHB, for example, R1b, R5b type. Except in
Kojto	90:cb3d968589d8	1143	* the case when the command busy is finished, changing from 1 to 0 generates a
Kojto	90:cb3d968589d8	1144	* transfer complete interrupt in the Interrupt Status register. The SD host
Kojto	90:cb3d968589d8	1145	* driver can save registers for a suspend transaction after this bit has changed
Kojto	90:cb3d968589d8	1146	* from 1 to 0.
Kojto	90:cb3d968589d8	1147	*
Kojto	90:cb3d968589d8	1148	* Values:
Kojto	90:cb3d968589d8	1149	* - 0 - Can issue command which uses the DAT line.
Kojto	90:cb3d968589d8	1150	* - 1 - Cannot issue command which uses the DAT line.
Kojto	90:cb3d968589d8	1151	*/
Kojto	90:cb3d968589d8	1152	/@{/
Kojto	90:cb3d968589d8	1153	#define BP_SDHC_PRSSTAT_CDIHB (1U) /!< Bit position for SDHC_PRSSTAT_CDIHB. /
Kojto	90:cb3d968589d8	1154	#define BM_SDHC_PRSSTAT_CDIHB (0x00000002U) /!< Bit mask for SDHC_PRSSTAT_CDIHB. /
Kojto	90:cb3d968589d8	1155	#define BS_SDHC_PRSSTAT_CDIHB (1U) /!< Bit field size in bits for SDHC_PRSSTAT_CDIHB. /
Kojto	90:cb3d968589d8	1156
Kojto	90:cb3d968589d8	1157	/! @brief Read current value of the SDHC_PRSSTAT_CDIHB field. /
Kojto	90:cb3d968589d8	1158	#define BR_SDHC_PRSSTAT_CDIHB(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_CDIHB))
Kojto	90:cb3d968589d8	1159	/@}/
Kojto	90:cb3d968589d8	1160
Kojto	90:cb3d968589d8	1161	/*!
Kojto	90:cb3d968589d8	1162	* @name Register SDHC_PRSSTAT, field DLA[2] (RO)
Kojto	90:cb3d968589d8	1163	*
Kojto	90:cb3d968589d8	1164	* Indicates whether one of the DAT lines on the SD bus is in use. In the case
Kojto	90:cb3d968589d8	1165	* of read transactions: This status indicates whether a read transfer is
Kojto	90:cb3d968589d8	1166	* executing on the SD bus. Changes in this value from 1 to 0, between data blocks,
Kojto	90:cb3d968589d8	1167	* generates a block gap event interrupt in the Interrupt Status register. This bit
Kojto	90:cb3d968589d8	1168	* will be set in either of the following cases: After the end bit of the read
Kojto	90:cb3d968589d8	1169	* command. When writing a 1 to PROCTL[CREQ] to restart a read transfer. This bit
Kojto	90:cb3d968589d8	1170	* will be cleared in either of the following cases: When the end bit of the last
Kojto	90:cb3d968589d8	1171	* data block is sent from the SD bus to the SDHC. When the read wait state is
Kojto	90:cb3d968589d8	1172	* stopped by a suspend command and the DAT2 line is released. The SDHC will wait at
Kojto	90:cb3d968589d8	1173	* the next block gap by driving read wait at the start of the interrupt cycle.
Kojto	90:cb3d968589d8	1174	* If the read wait signal is already driven (data buffer cannot receive data),
Kojto	90:cb3d968589d8	1175	* the SDHC can wait for a current block gap by continuing to drive the read wait
Kojto	90:cb3d968589d8	1176	* signal. It is necessary to support read wait to use the suspend / resume
Kojto	90:cb3d968589d8	1177	* function. This bit will remain 1 during read wait. In the case of write
Kojto	90:cb3d968589d8	1178	* transactions: This status indicates that a write transfer is executing on the SD bus.
Kojto	90:cb3d968589d8	1179	* Changes in this value from 1 to 0 generate a transfer complete interrupt in the
Kojto	90:cb3d968589d8	1180	* interrupt status register. This bit will be set in either of the following
Kojto	90:cb3d968589d8	1181	* cases: After the end bit of the write command. When writing to 1 to PROCTL[CREQ] to
Kojto	90:cb3d968589d8	1182	* continue a write transfer. This bit will be cleared in either of the
Kojto	90:cb3d968589d8	1183	* following cases: When the SD card releases write busy of the last data block, the SDHC
Kojto	90:cb3d968589d8	1184	* will also detect if the output is not busy. If the SD card does not drive the
Kojto	90:cb3d968589d8	1185	* busy signal after the CRC status is received, the SDHC shall assume the card
Kojto	90:cb3d968589d8	1186	* drive "Not busy". When the SD card releases write busy, prior to waiting for
Kojto	90:cb3d968589d8	1187	* write transfer, and as a result of a stop at block gap request. In the case of
Kojto	90:cb3d968589d8	1188	* command with busy pending: This status indicates that a busy state follows the
Kojto	90:cb3d968589d8	1189	* command and the data line is in use. This bit will be cleared when the DAT0
Kojto	90:cb3d968589d8	1190	* line is released.
Kojto	90:cb3d968589d8	1191	*
Kojto	90:cb3d968589d8	1192	* Values:
Kojto	90:cb3d968589d8	1193	* - 0 - DAT line inactive.
Kojto	90:cb3d968589d8	1194	* - 1 - DAT line active.
Kojto	90:cb3d968589d8	1195	*/
Kojto	90:cb3d968589d8	1196	/@{/
Kojto	90:cb3d968589d8	1197	#define BP_SDHC_PRSSTAT_DLA (2U) /!< Bit position for SDHC_PRSSTAT_DLA. /
Kojto	90:cb3d968589d8	1198	#define BM_SDHC_PRSSTAT_DLA (0x00000004U) /!< Bit mask for SDHC_PRSSTAT_DLA. /
Kojto	90:cb3d968589d8	1199	#define BS_SDHC_PRSSTAT_DLA (1U) /!< Bit field size in bits for SDHC_PRSSTAT_DLA. /
Kojto	90:cb3d968589d8	1200
Kojto	90:cb3d968589d8	1201	/! @brief Read current value of the SDHC_PRSSTAT_DLA field. /
Kojto	90:cb3d968589d8	1202	#define BR_SDHC_PRSSTAT_DLA(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_DLA))
Kojto	90:cb3d968589d8	1203	/@}/
Kojto	90:cb3d968589d8	1204
Kojto	90:cb3d968589d8	1205	/*!
Kojto	90:cb3d968589d8	1206	* @name Register SDHC_PRSSTAT, field SDSTB[3] (RO)
Kojto	90:cb3d968589d8	1207	*
Kojto	90:cb3d968589d8	1208	* Indicates that the internal card clock is stable. This bit is for the host
Kojto	90:cb3d968589d8	1209	* driver to poll clock status when changing the clock frequency. It is recommended
Kojto	90:cb3d968589d8	1210	* to clear SYSCTL[SDCLKEN] to remove glitch on the card clock when the
Kojto	90:cb3d968589d8	1211	* frequency is changing.
Kojto	90:cb3d968589d8	1212	*
Kojto	90:cb3d968589d8	1213	* Values:
Kojto	90:cb3d968589d8	1214	* - 0 - Clock is changing frequency and not stable.
Kojto	90:cb3d968589d8	1215	* - 1 - Clock is stable.
Kojto	90:cb3d968589d8	1216	*/
Kojto	90:cb3d968589d8	1217	/@{/
Kojto	90:cb3d968589d8	1218	#define BP_SDHC_PRSSTAT_SDSTB (3U) /!< Bit position for SDHC_PRSSTAT_SDSTB. /
Kojto	90:cb3d968589d8	1219	#define BM_SDHC_PRSSTAT_SDSTB (0x00000008U) /!< Bit mask for SDHC_PRSSTAT_SDSTB. /
Kojto	90:cb3d968589d8	1220	#define BS_SDHC_PRSSTAT_SDSTB (1U) /!< Bit field size in bits for SDHC_PRSSTAT_SDSTB. /
Kojto	90:cb3d968589d8	1221
Kojto	90:cb3d968589d8	1222	/! @brief Read current value of the SDHC_PRSSTAT_SDSTB field. /
Kojto	90:cb3d968589d8	1223	#define BR_SDHC_PRSSTAT_SDSTB(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_SDSTB))
Kojto	90:cb3d968589d8	1224	/@}/
Kojto	90:cb3d968589d8	1225
Kojto	90:cb3d968589d8	1226	/*!
Kojto	90:cb3d968589d8	1227	* @name Register SDHC_PRSSTAT, field IPGOFF[4] (RO)
Kojto	90:cb3d968589d8	1228	*
Kojto	90:cb3d968589d8	1229	* Indicates that the bus clock is internally gated off. This bit is for the
Kojto	90:cb3d968589d8	1230	* host driver to debug.
Kojto	90:cb3d968589d8	1231	*
Kojto	90:cb3d968589d8	1232	* Values:
Kojto	90:cb3d968589d8	1233	* - 0 - Bus clock is active.
Kojto	90:cb3d968589d8	1234	* - 1 - Bus clock is gated off.
Kojto	90:cb3d968589d8	1235	*/
Kojto	90:cb3d968589d8	1236	/@{/
Kojto	90:cb3d968589d8	1237	#define BP_SDHC_PRSSTAT_IPGOFF (4U) /!< Bit position for SDHC_PRSSTAT_IPGOFF. /
Kojto	90:cb3d968589d8	1238	#define BM_SDHC_PRSSTAT_IPGOFF (0x00000010U) /!< Bit mask for SDHC_PRSSTAT_IPGOFF. /
Kojto	90:cb3d968589d8	1239	#define BS_SDHC_PRSSTAT_IPGOFF (1U) /!< Bit field size in bits for SDHC_PRSSTAT_IPGOFF. /
Kojto	90:cb3d968589d8	1240
Kojto	90:cb3d968589d8	1241	/! @brief Read current value of the SDHC_PRSSTAT_IPGOFF field. /
Kojto	90:cb3d968589d8	1242	#define BR_SDHC_PRSSTAT_IPGOFF(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_IPGOFF))
Kojto	90:cb3d968589d8	1243	/@}/
Kojto	90:cb3d968589d8	1244
Kojto	90:cb3d968589d8	1245	/*!
Kojto	90:cb3d968589d8	1246	* @name Register SDHC_PRSSTAT, field HCKOFF[5] (RO)
Kojto	90:cb3d968589d8	1247	*
Kojto	90:cb3d968589d8	1248	* Indicates that the system clock is internally gated off. This bit is for the
Kojto	90:cb3d968589d8	1249	* host driver to debug during a data transfer.
Kojto	90:cb3d968589d8	1250	*
Kojto	90:cb3d968589d8	1251	* Values:
Kojto	90:cb3d968589d8	1252	* - 0 - System clock is active.
Kojto	90:cb3d968589d8	1253	* - 1 - System clock is gated off.
Kojto	90:cb3d968589d8	1254	*/
Kojto	90:cb3d968589d8	1255	/@{/
Kojto	90:cb3d968589d8	1256	#define BP_SDHC_PRSSTAT_HCKOFF (5U) /!< Bit position for SDHC_PRSSTAT_HCKOFF. /
Kojto	90:cb3d968589d8	1257	#define BM_SDHC_PRSSTAT_HCKOFF (0x00000020U) /!< Bit mask for SDHC_PRSSTAT_HCKOFF. /
Kojto	90:cb3d968589d8	1258	#define BS_SDHC_PRSSTAT_HCKOFF (1U) /!< Bit field size in bits for SDHC_PRSSTAT_HCKOFF. /
Kojto	90:cb3d968589d8	1259
Kojto	90:cb3d968589d8	1260	/! @brief Read current value of the SDHC_PRSSTAT_HCKOFF field. /
Kojto	90:cb3d968589d8	1261	#define BR_SDHC_PRSSTAT_HCKOFF(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_HCKOFF))
Kojto	90:cb3d968589d8	1262	/@}/
Kojto	90:cb3d968589d8	1263
Kojto	90:cb3d968589d8	1264	/*!
Kojto	90:cb3d968589d8	1265	* @name Register SDHC_PRSSTAT, field PEROFF[6] (RO)
Kojto	90:cb3d968589d8	1266	*
Kojto	90:cb3d968589d8	1267	* Indicates that the is internally gated off. This bit is for the host driver
Kojto	90:cb3d968589d8	1268	* to debug transaction on the SD bus. When INITA bit is set, SDHC sending 80
Kojto	90:cb3d968589d8	1269	* clock cycles to the card, SDCLKEN must be 1 to enable the output card clock,
Kojto	90:cb3d968589d8	1270	* otherwise the will never be gate off, so and will be always active. SDHC clock SDHC
Kojto	90:cb3d968589d8	1271	* clock SDHC clock bus clock
Kojto	90:cb3d968589d8	1272	*
Kojto	90:cb3d968589d8	1273	* Values:
Kojto	90:cb3d968589d8	1274	* - 0 - SDHC clock is active.
Kojto	90:cb3d968589d8	1275	* - 1 - SDHC clock is gated off.
Kojto	90:cb3d968589d8	1276	*/
Kojto	90:cb3d968589d8	1277	/@{/
Kojto	90:cb3d968589d8	1278	#define BP_SDHC_PRSSTAT_PEROFF (6U) /!< Bit position for SDHC_PRSSTAT_PEROFF. /
Kojto	90:cb3d968589d8	1279	#define BM_SDHC_PRSSTAT_PEROFF (0x00000040U) /!< Bit mask for SDHC_PRSSTAT_PEROFF. /
Kojto	90:cb3d968589d8	1280	#define BS_SDHC_PRSSTAT_PEROFF (1U) /!< Bit field size in bits for SDHC_PRSSTAT_PEROFF. /
Kojto	90:cb3d968589d8	1281
Kojto	90:cb3d968589d8	1282	/! @brief Read current value of the SDHC_PRSSTAT_PEROFF field. /
Kojto	90:cb3d968589d8	1283	#define BR_SDHC_PRSSTAT_PEROFF(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_PEROFF))
Kojto	90:cb3d968589d8	1284	/@}/
Kojto	90:cb3d968589d8	1285
Kojto	90:cb3d968589d8	1286	/*!
Kojto	90:cb3d968589d8	1287	* @name Register SDHC_PRSSTAT, field SDOFF[7] (RO)
Kojto	90:cb3d968589d8	1288	*
Kojto	90:cb3d968589d8	1289	* Indicates that the SD clock is internally gated off, because of buffer
Kojto	90:cb3d968589d8	1290	* over/under-run or read pause without read wait assertion, or the driver has cleared
Kojto	90:cb3d968589d8	1291	* SYSCTL[SDCLKEN] to stop the SD clock. This bit is for the host driver to debug
Kojto	90:cb3d968589d8	1292	* data transaction on the SD bus.
Kojto	90:cb3d968589d8	1293	*
Kojto	90:cb3d968589d8	1294	* Values:
Kojto	90:cb3d968589d8	1295	* - 0 - SD clock is active.
Kojto	90:cb3d968589d8	1296	* - 1 - SD clock is gated off.
Kojto	90:cb3d968589d8	1297	*/
Kojto	90:cb3d968589d8	1298	/@{/
Kojto	90:cb3d968589d8	1299	#define BP_SDHC_PRSSTAT_SDOFF (7U) /!< Bit position for SDHC_PRSSTAT_SDOFF. /
Kojto	90:cb3d968589d8	1300	#define BM_SDHC_PRSSTAT_SDOFF (0x00000080U) /!< Bit mask for SDHC_PRSSTAT_SDOFF. /
Kojto	90:cb3d968589d8	1301	#define BS_SDHC_PRSSTAT_SDOFF (1U) /!< Bit field size in bits for SDHC_PRSSTAT_SDOFF. /
Kojto	90:cb3d968589d8	1302
Kojto	90:cb3d968589d8	1303	/! @brief Read current value of the SDHC_PRSSTAT_SDOFF field. /
Kojto	90:cb3d968589d8	1304	#define BR_SDHC_PRSSTAT_SDOFF(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_SDOFF))
Kojto	90:cb3d968589d8	1305	/@}/
Kojto	90:cb3d968589d8	1306
Kojto	90:cb3d968589d8	1307	/*!
Kojto	90:cb3d968589d8	1308	* @name Register SDHC_PRSSTAT, field WTA[8] (RO)
Kojto	90:cb3d968589d8	1309	*
Kojto	90:cb3d968589d8	1310	* Indicates that a write transfer is active. If this bit is 0, it means no
Kojto	90:cb3d968589d8	1311	* valid write data exists in the SDHC. This bit is set in either of the following
Kojto	90:cb3d968589d8	1312	* cases: After the end bit of the write command. When writing 1 to PROCTL[CREQ] to
Kojto	90:cb3d968589d8	1313	* restart a write transfer. This bit is cleared in either of the following
Kojto	90:cb3d968589d8	1314	* cases: After getting the CRC status of the last data block as specified by the
Kojto	90:cb3d968589d8	1315	* transfer count (single and multiple). After getting the CRC status of any block
Kojto	90:cb3d968589d8	1316	* where data transmission is about to be stopped by a stop at block gap request.
Kojto	90:cb3d968589d8	1317	* During a write transaction, a block gap event interrupt is generated when this
Kojto	90:cb3d968589d8	1318	* bit is changed to 0, as result of the stop at block gap request being set.
Kojto	90:cb3d968589d8	1319	* This status is useful for the host driver in determining when to issue commands
Kojto	90:cb3d968589d8	1320	* during write busy state.
Kojto	90:cb3d968589d8	1321	*
Kojto	90:cb3d968589d8	1322	* Values:
Kojto	90:cb3d968589d8	1323	* - 0 - No valid data.
Kojto	90:cb3d968589d8	1324	* - 1 - Transferring data.
Kojto	90:cb3d968589d8	1325	*/
Kojto	90:cb3d968589d8	1326	/@{/
Kojto	90:cb3d968589d8	1327	#define BP_SDHC_PRSSTAT_WTA (8U) /!< Bit position for SDHC_PRSSTAT_WTA. /
Kojto	90:cb3d968589d8	1328	#define BM_SDHC_PRSSTAT_WTA (0x00000100U) /!< Bit mask for SDHC_PRSSTAT_WTA. /
Kojto	90:cb3d968589d8	1329	#define BS_SDHC_PRSSTAT_WTA (1U) /!< Bit field size in bits for SDHC_PRSSTAT_WTA. /
Kojto	90:cb3d968589d8	1330
Kojto	90:cb3d968589d8	1331	/! @brief Read current value of the SDHC_PRSSTAT_WTA field. /
Kojto	90:cb3d968589d8	1332	#define BR_SDHC_PRSSTAT_WTA(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_WTA))
Kojto	90:cb3d968589d8	1333	/@}/
Kojto	90:cb3d968589d8	1334
Kojto	90:cb3d968589d8	1335	/*!
Kojto	90:cb3d968589d8	1336	* @name Register SDHC_PRSSTAT, field RTA[9] (RO)
Kojto	90:cb3d968589d8	1337	*
Kojto	90:cb3d968589d8	1338	* Used for detecting completion of a read transfer. This bit is set for either
Kojto	90:cb3d968589d8	1339	* of the following conditions: After the end bit of the read command. When
Kojto	90:cb3d968589d8	1340	* writing a 1 to PROCTL[CREQ] to restart a read transfer. A transfer complete
Kojto	90:cb3d968589d8	1341	* interrupt is generated when this bit changes to 0. This bit is cleared for either of
Kojto	90:cb3d968589d8	1342	* the following conditions: When the last data block as specified by block
Kojto	90:cb3d968589d8	1343	* length is transferred to the system, that is, all data are read away from SDHC
Kojto	90:cb3d968589d8	1344	* internal buffer. When all valid data blocks have been transferred from SDHC
Kojto	90:cb3d968589d8	1345	* internal buffer to the system and no current block transfers are being sent as a
Kojto	90:cb3d968589d8	1346	* result of the stop at block gap request being set to 1.
Kojto	90:cb3d968589d8	1347	*
Kojto	90:cb3d968589d8	1348	* Values:
Kojto	90:cb3d968589d8	1349	* - 0 - No valid data.
Kojto	90:cb3d968589d8	1350	* - 1 - Transferring data.
Kojto	90:cb3d968589d8	1351	*/
Kojto	90:cb3d968589d8	1352	/@{/
Kojto	90:cb3d968589d8	1353	#define BP_SDHC_PRSSTAT_RTA (9U) /!< Bit position for SDHC_PRSSTAT_RTA. /
Kojto	90:cb3d968589d8	1354	#define BM_SDHC_PRSSTAT_RTA (0x00000200U) /!< Bit mask for SDHC_PRSSTAT_RTA. /
Kojto	90:cb3d968589d8	1355	#define BS_SDHC_PRSSTAT_RTA (1U) /!< Bit field size in bits for SDHC_PRSSTAT_RTA. /
Kojto	90:cb3d968589d8	1356
Kojto	90:cb3d968589d8	1357	/! @brief Read current value of the SDHC_PRSSTAT_RTA field. /
Kojto	90:cb3d968589d8	1358	#define BR_SDHC_PRSSTAT_RTA(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_RTA))
Kojto	90:cb3d968589d8	1359	/@}/
Kojto	90:cb3d968589d8	1360
Kojto	90:cb3d968589d8	1361	/*!
Kojto	90:cb3d968589d8	1362	* @name Register SDHC_PRSSTAT, field BWEN[10] (RO)
Kojto	90:cb3d968589d8	1363	*
Kojto	90:cb3d968589d8	1364	* Used for non-DMA write transfers. The SDHC can implement multiple buffers to
Kojto	90:cb3d968589d8	1365	* transfer data efficiently. This read-only flag indicates whether space is
Kojto	90:cb3d968589d8	1366	* available for write data. If this bit is 1, valid data greater than the watermark
Kojto	90:cb3d968589d8	1367	* level can be written to the buffer. This read-only flag indicates whether
Kojto	90:cb3d968589d8	1368	* space is available for write data.
Kojto	90:cb3d968589d8	1369	*
Kojto	90:cb3d968589d8	1370	* Values:
Kojto	90:cb3d968589d8	1371	* - 0 - Write disable, the buffer can hold valid data less than the write
Kojto	90:cb3d968589d8	1372	* watermark level.
Kojto	90:cb3d968589d8	1373	* - 1 - Write enable, the buffer can hold valid data greater than the write
Kojto	90:cb3d968589d8	1374	* watermark level.
Kojto	90:cb3d968589d8	1375	*/
Kojto	90:cb3d968589d8	1376	/@{/
Kojto	90:cb3d968589d8	1377	#define BP_SDHC_PRSSTAT_BWEN (10U) /!< Bit position for SDHC_PRSSTAT_BWEN. /
Kojto	90:cb3d968589d8	1378	#define BM_SDHC_PRSSTAT_BWEN (0x00000400U) /!< Bit mask for SDHC_PRSSTAT_BWEN. /
Kojto	90:cb3d968589d8	1379	#define BS_SDHC_PRSSTAT_BWEN (1U) /!< Bit field size in bits for SDHC_PRSSTAT_BWEN. /
Kojto	90:cb3d968589d8	1380
Kojto	90:cb3d968589d8	1381	/! @brief Read current value of the SDHC_PRSSTAT_BWEN field. /
Kojto	90:cb3d968589d8	1382	#define BR_SDHC_PRSSTAT_BWEN(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_BWEN))
Kojto	90:cb3d968589d8	1383	/@}/
Kojto	90:cb3d968589d8	1384
Kojto	90:cb3d968589d8	1385	/*!
Kojto	90:cb3d968589d8	1386	* @name Register SDHC_PRSSTAT, field BREN[11] (RO)
Kojto	90:cb3d968589d8	1387	*
Kojto	90:cb3d968589d8	1388	* Used for non-DMA read transfers. The SDHC may implement multiple buffers to
Kojto	90:cb3d968589d8	1389	* transfer data efficiently. This read-only flag indicates that valid data exists
Kojto	90:cb3d968589d8	1390	* in the host side buffer. If this bit is high, valid data greater than the
Kojto	90:cb3d968589d8	1391	* watermark level exist in the buffer. This read-only flag indicates that valid
Kojto	90:cb3d968589d8	1392	* data exists in the host side buffer.
Kojto	90:cb3d968589d8	1393	*
Kojto	90:cb3d968589d8	1394	* Values:
Kojto	90:cb3d968589d8	1395	* - 0 - Read disable, valid data less than the watermark level exist in the
Kojto	90:cb3d968589d8	1396	* buffer.
Kojto	90:cb3d968589d8	1397	* - 1 - Read enable, valid data greater than the watermark level exist in the
Kojto	90:cb3d968589d8	1398	* buffer.
Kojto	90:cb3d968589d8	1399	*/
Kojto	90:cb3d968589d8	1400	/@{/
Kojto	90:cb3d968589d8	1401	#define BP_SDHC_PRSSTAT_BREN (11U) /!< Bit position for SDHC_PRSSTAT_BREN. /
Kojto	90:cb3d968589d8	1402	#define BM_SDHC_PRSSTAT_BREN (0x00000800U) /!< Bit mask for SDHC_PRSSTAT_BREN. /
Kojto	90:cb3d968589d8	1403	#define BS_SDHC_PRSSTAT_BREN (1U) /!< Bit field size in bits for SDHC_PRSSTAT_BREN. /
Kojto	90:cb3d968589d8	1404
Kojto	90:cb3d968589d8	1405	/! @brief Read current value of the SDHC_PRSSTAT_BREN field. /
Kojto	90:cb3d968589d8	1406	#define BR_SDHC_PRSSTAT_BREN(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_BREN))
Kojto	90:cb3d968589d8	1407	/@}/
Kojto	90:cb3d968589d8	1408
Kojto	90:cb3d968589d8	1409	/*!
Kojto	90:cb3d968589d8	1410	* @name Register SDHC_PRSSTAT, field CINS[16] (RO)
Kojto	90:cb3d968589d8	1411	*
Kojto	90:cb3d968589d8	1412	* Indicates whether a card has been inserted. The SDHC debounces this signal so
Kojto	90:cb3d968589d8	1413	* that the host driver will not need to wait for it to stabilize. Changing from
Kojto	90:cb3d968589d8	1414	* a 0 to 1 generates a card insertion interrupt in the Interrupt Status
Kojto	90:cb3d968589d8	1415	* register. Changing from a 1 to 0 generates a card removal interrupt in the Interrupt
Kojto	90:cb3d968589d8	1416	* Status register. A write to the force event register does not effect this bit.
Kojto	90:cb3d968589d8	1417	* SYSCTL[RSTA] does not effect this bit. A software reset does not effect this
Kojto	90:cb3d968589d8	1418	* bit.
Kojto	90:cb3d968589d8	1419	*
Kojto	90:cb3d968589d8	1420	* Values:
Kojto	90:cb3d968589d8	1421	* - 0 - Power on reset or no card.
Kojto	90:cb3d968589d8	1422	* - 1 - Card inserted.
Kojto	90:cb3d968589d8	1423	*/
Kojto	90:cb3d968589d8	1424	/@{/
Kojto	90:cb3d968589d8	1425	#define BP_SDHC_PRSSTAT_CINS (16U) /!< Bit position for SDHC_PRSSTAT_CINS. /
Kojto	90:cb3d968589d8	1426	#define BM_SDHC_PRSSTAT_CINS (0x00010000U) /!< Bit mask for SDHC_PRSSTAT_CINS. /
Kojto	90:cb3d968589d8	1427	#define BS_SDHC_PRSSTAT_CINS (1U) /!< Bit field size in bits for SDHC_PRSSTAT_CINS. /
Kojto	90:cb3d968589d8	1428
Kojto	90:cb3d968589d8	1429	/! @brief Read current value of the SDHC_PRSSTAT_CINS field. /
Kojto	90:cb3d968589d8	1430	#define BR_SDHC_PRSSTAT_CINS(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_CINS))
Kojto	90:cb3d968589d8	1431	/@}/
Kojto	90:cb3d968589d8	1432
Kojto	90:cb3d968589d8	1433	/*!
Kojto	90:cb3d968589d8	1434	* @name Register SDHC_PRSSTAT, field CLSL[23] (RO)
Kojto	90:cb3d968589d8	1435	*
Kojto	90:cb3d968589d8	1436	* Used to check the CMD line level to recover from errors, and for debugging.
Kojto	90:cb3d968589d8	1437	* The reset value is effected by the external pullup/pulldown resistor, by
Kojto	90:cb3d968589d8	1438	* default, the read value of this bit after reset is 1b, when the command line is
Kojto	90:cb3d968589d8	1439	* pulled up.
Kojto	90:cb3d968589d8	1440	*/
Kojto	90:cb3d968589d8	1441	/@{/
Kojto	90:cb3d968589d8	1442	#define BP_SDHC_PRSSTAT_CLSL (23U) /!< Bit position for SDHC_PRSSTAT_CLSL. /
Kojto	90:cb3d968589d8	1443	#define BM_SDHC_PRSSTAT_CLSL (0x00800000U) /!< Bit mask for SDHC_PRSSTAT_CLSL. /
Kojto	90:cb3d968589d8	1444	#define BS_SDHC_PRSSTAT_CLSL (1U) /!< Bit field size in bits for SDHC_PRSSTAT_CLSL. /
Kojto	90:cb3d968589d8	1445
Kojto	90:cb3d968589d8	1446	/! @brief Read current value of the SDHC_PRSSTAT_CLSL field. /
Kojto	90:cb3d968589d8	1447	#define BR_SDHC_PRSSTAT_CLSL(x) (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_CLSL))
Kojto	90:cb3d968589d8	1448	/@}/
Kojto	90:cb3d968589d8	1449
Kojto	90:cb3d968589d8	1450	/*!
Kojto	90:cb3d968589d8	1451	* @name Register SDHC_PRSSTAT, field DLSL[31:24] (RO)
Kojto	90:cb3d968589d8	1452	*
Kojto	90:cb3d968589d8	1453	* Used to check the DAT line level to recover from errors, and for debugging.
Kojto	90:cb3d968589d8	1454	* This is especially useful in detecting the busy signal level from DAT[0]. The
Kojto	90:cb3d968589d8	1455	* reset value is effected by the external pullup/pulldown resistors. By default,
Kojto	90:cb3d968589d8	1456	* the read value of this field after reset is 8'b11110111, when DAT[3] is pulled
Kojto	90:cb3d968589d8	1457	* down and the other lines are pulled up.
Kojto	90:cb3d968589d8	1458	*/
Kojto	90:cb3d968589d8	1459	/@{/
Kojto	90:cb3d968589d8	1460	#define BP_SDHC_PRSSTAT_DLSL (24U) /!< Bit position for SDHC_PRSSTAT_DLSL. /
Kojto	90:cb3d968589d8	1461	#define BM_SDHC_PRSSTAT_DLSL (0xFF000000U) /!< Bit mask for SDHC_PRSSTAT_DLSL. /
Kojto	90:cb3d968589d8	1462	#define BS_SDHC_PRSSTAT_DLSL (8U) /!< Bit field size in bits for SDHC_PRSSTAT_DLSL. /
Kojto	90:cb3d968589d8	1463
Kojto	90:cb3d968589d8	1464	/! @brief Read current value of the SDHC_PRSSTAT_DLSL field. /
Kojto	90:cb3d968589d8	1465	#define BR_SDHC_PRSSTAT_DLSL(x) (HW_SDHC_PRSSTAT(x).B.DLSL)
Kojto	90:cb3d968589d8	1466	/@}/
Kojto	90:cb3d968589d8	1467
Kojto	90:cb3d968589d8	1468	/*******************************************************************************
Kojto	90:cb3d968589d8	1469	* HW_SDHC_PROCTL - Protocol Control register
Kojto	90:cb3d968589d8	1470	******************************************************************************/
Kojto	90:cb3d968589d8	1471
Kojto	90:cb3d968589d8	1472	/*!
Kojto	90:cb3d968589d8	1473	* @brief HW_SDHC_PROCTL - Protocol Control register (RW)
Kojto	90:cb3d968589d8	1474	*
Kojto	90:cb3d968589d8	1475	* Reset value: 0x00000020U
Kojto	90:cb3d968589d8	1476	*
Kojto	90:cb3d968589d8	1477	* There are three cases to restart the transfer after stop at the block gap.
Kojto	90:cb3d968589d8	1478	* Which case is appropriate depends on whether the SDHC issues a suspend command
Kojto	90:cb3d968589d8	1479	* or the SD card accepts the suspend command: If the host driver does not issue a
Kojto	90:cb3d968589d8	1480	* suspend command, the continue request shall be used to restart the transfer.
Kojto	90:cb3d968589d8	1481	* If the host driver issues a suspend command and the SD card accepts it, a
Kojto	90:cb3d968589d8	1482	* resume command shall be used to restart the transfer. If the host driver issues a
Kojto	90:cb3d968589d8	1483	* suspend command and the SD card does not accept it, the continue request shall
Kojto	90:cb3d968589d8	1484	* be used to restart the transfer. Any time stop at block gap request stops the
Kojto	90:cb3d968589d8	1485	* data transfer, the host driver shall wait for a transfer complete (in the
Kojto	90:cb3d968589d8	1486	* interrupt status register), before attempting to restart the transfer. When
Kojto	90:cb3d968589d8	1487	* restarting the data transfer by continue request, the host driver shall clear the
Kojto	90:cb3d968589d8	1488	* stop at block gap request before or simultaneously.
Kojto	90:cb3d968589d8	1489	*/
Kojto	90:cb3d968589d8	1490	typedef union _hw_sdhc_proctl
Kojto	90:cb3d968589d8	1491	{
Kojto	90:cb3d968589d8	1492	uint32_t U;
Kojto	90:cb3d968589d8	1493	struct _hw_sdhc_proctl_bitfields
Kojto	90:cb3d968589d8	1494	{
Kojto	90:cb3d968589d8	1495	uint32_t LCTL : 1; /!< [0] LED Control /
Kojto	90:cb3d968589d8	1496	uint32_t DTW : 2; /!< [2:1] Data Transfer Width /
Kojto	90:cb3d968589d8	1497	uint32_t D3CD : 1; /!< [3] DAT3 As Card Detection Pin /
Kojto	90:cb3d968589d8	1498	uint32_t EMODE : 2; /!< [5:4] Endian Mode /
Kojto	90:cb3d968589d8	1499	uint32_t CDTL : 1; /!< [6] Card Detect Test Level /
Kojto	90:cb3d968589d8	1500	uint32_t CDSS : 1; /!< [7] Card Detect Signal Selection /
Kojto	90:cb3d968589d8	1501	uint32_t DMAS : 2; /!< [9:8] DMA Select /
Kojto	90:cb3d968589d8	1502	uint32_t RESERVED0 : 6; /!< [15:10] /
Kojto	90:cb3d968589d8	1503	uint32_t SABGREQ : 1; /!< [16] Stop At Block Gap Request /
Kojto	90:cb3d968589d8	1504	uint32_t CREQ : 1; /!< [17] Continue Request /
Kojto	90:cb3d968589d8	1505	uint32_t RWCTL : 1; /!< [18] Read Wait Control /
Kojto	90:cb3d968589d8	1506	uint32_t IABG : 1; /!< [19] Interrupt At Block Gap /
Kojto	90:cb3d968589d8	1507	uint32_t RESERVED1 : 4; /!< [23:20] /
Kojto	90:cb3d968589d8	1508	uint32_t WECINT : 1; /*!< [24] Wakeup Event Enable On Card Interrupt
Kojto	90:cb3d968589d8	1509	* */
Kojto	90:cb3d968589d8	1510	uint32_t WECINS : 1; /*!< [25] Wakeup Event Enable On SD Card
Kojto	90:cb3d968589d8	1511	* Insertion */
Kojto	90:cb3d968589d8	1512	uint32_t WECRM : 1; /*!< [26] Wakeup Event Enable On SD Card Removal
Kojto	90:cb3d968589d8	1513	* */
Kojto	90:cb3d968589d8	1514	uint32_t RESERVED2 : 5; /!< [31:27] /
Kojto	90:cb3d968589d8	1515	} B;
Kojto	90:cb3d968589d8	1516	} hw_sdhc_proctl_t;
Kojto	90:cb3d968589d8	1517
Kojto	90:cb3d968589d8	1518	/*!
Kojto	90:cb3d968589d8	1519	* @name Constants and macros for entire SDHC_PROCTL register
Kojto	90:cb3d968589d8	1520	*/
Kojto	90:cb3d968589d8	1521	/@{/
Kojto	90:cb3d968589d8	1522	#define HW_SDHC_PROCTL_ADDR(x) ((x) + 0x28U)
Kojto	90:cb3d968589d8	1523
Kojto	90:cb3d968589d8	1524	#define HW_SDHC_PROCTL(x) ((__IO hw_sdhc_proctl_t ) HW_SDHC_PROCTL_ADDR(x))
Kojto	90:cb3d968589d8	1525	#define HW_SDHC_PROCTL_RD(x) (HW_SDHC_PROCTL(x).U)
Kojto	90:cb3d968589d8	1526	#define HW_SDHC_PROCTL_WR(x, v) (HW_SDHC_PROCTL(x).U = (v))
Kojto	90:cb3d968589d8	1527	#define HW_SDHC_PROCTL_SET(x, v) (HW_SDHC_PROCTL_WR(x, HW_SDHC_PROCTL_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1528	#define HW_SDHC_PROCTL_CLR(x, v) (HW_SDHC_PROCTL_WR(x, HW_SDHC_PROCTL_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1529	#define HW_SDHC_PROCTL_TOG(x, v) (HW_SDHC_PROCTL_WR(x, HW_SDHC_PROCTL_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1530	/@}/
Kojto	90:cb3d968589d8	1531
Kojto	90:cb3d968589d8	1532	/*
Kojto	90:cb3d968589d8	1533	* Constants & macros for individual SDHC_PROCTL bitfields
Kojto	90:cb3d968589d8	1534	*/
Kojto	90:cb3d968589d8	1535
Kojto	90:cb3d968589d8	1536	/*!
Kojto	90:cb3d968589d8	1537	* @name Register SDHC_PROCTL, field LCTL[0] (RW)
Kojto	90:cb3d968589d8	1538	*
Kojto	90:cb3d968589d8	1539	* This bit, fully controlled by the host driver, is used to caution the user
Kojto	90:cb3d968589d8	1540	* not to remove the card while the card is being accessed. If the software is
Kojto	90:cb3d968589d8	1541	* going to issue multiple SD commands, this bit can be set during all these
Kojto	90:cb3d968589d8	1542	* transactions. It is not necessary to change for each transaction. When the software
Kojto	90:cb3d968589d8	1543	* issues multiple SD commands, setting the bit once before the first command is
Kojto	90:cb3d968589d8	1544	* sufficient: it is not necessary to reset the bit between commands.
Kojto	90:cb3d968589d8	1545	*
Kojto	90:cb3d968589d8	1546	* Values:
Kojto	90:cb3d968589d8	1547	* - 0 - LED off.
Kojto	90:cb3d968589d8	1548	* - 1 - LED on.
Kojto	90:cb3d968589d8	1549	*/
Kojto	90:cb3d968589d8	1550	/@{/
Kojto	90:cb3d968589d8	1551	#define BP_SDHC_PROCTL_LCTL (0U) /!< Bit position for SDHC_PROCTL_LCTL. /
Kojto	90:cb3d968589d8	1552	#define BM_SDHC_PROCTL_LCTL (0x00000001U) /!< Bit mask for SDHC_PROCTL_LCTL. /
Kojto	90:cb3d968589d8	1553	#define BS_SDHC_PROCTL_LCTL (1U) /!< Bit field size in bits for SDHC_PROCTL_LCTL. /
Kojto	90:cb3d968589d8	1554
Kojto	90:cb3d968589d8	1555	/! @brief Read current value of the SDHC_PROCTL_LCTL field. /
Kojto	90:cb3d968589d8	1556	#define BR_SDHC_PROCTL_LCTL(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_LCTL))
Kojto	90:cb3d968589d8	1557
Kojto	90:cb3d968589d8	1558	/! @brief Format value for bitfield SDHC_PROCTL_LCTL. /
Kojto	90:cb3d968589d8	1559	#define BF_SDHC_PROCTL_LCTL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_LCTL) & BM_SDHC_PROCTL_LCTL)
Kojto	90:cb3d968589d8	1560
Kojto	90:cb3d968589d8	1561	/! @brief Set the LCTL field to a new value. /
Kojto	90:cb3d968589d8	1562	#define BW_SDHC_PROCTL_LCTL(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_LCTL) = (v))
Kojto	90:cb3d968589d8	1563	/@}/
Kojto	90:cb3d968589d8	1564
Kojto	90:cb3d968589d8	1565	/*!
Kojto	90:cb3d968589d8	1566	* @name Register SDHC_PROCTL, field DTW[2:1] (RW)
Kojto	90:cb3d968589d8	1567	*
Kojto	90:cb3d968589d8	1568	* Selects the data width of the SD bus for a data transfer. The host driver
Kojto	90:cb3d968589d8	1569	* shall set it to match the data width of the card. Possible data transfer width is
Kojto	90:cb3d968589d8	1570	* 1-bit, 4-bits or 8-bits.
Kojto	90:cb3d968589d8	1571	*
Kojto	90:cb3d968589d8	1572	* Values:
Kojto	90:cb3d968589d8	1573	* - 00 - 1-bit mode
Kojto	90:cb3d968589d8	1574	* - 01 - 4-bit mode
Kojto	90:cb3d968589d8	1575	* - 10 - 8-bit mode
Kojto	90:cb3d968589d8	1576	* - 11 - Reserved
Kojto	90:cb3d968589d8	1577	*/
Kojto	90:cb3d968589d8	1578	/@{/
Kojto	90:cb3d968589d8	1579	#define BP_SDHC_PROCTL_DTW (1U) /!< Bit position for SDHC_PROCTL_DTW. /
Kojto	90:cb3d968589d8	1580	#define BM_SDHC_PROCTL_DTW (0x00000006U) /!< Bit mask for SDHC_PROCTL_DTW. /
Kojto	90:cb3d968589d8	1581	#define BS_SDHC_PROCTL_DTW (2U) /!< Bit field size in bits for SDHC_PROCTL_DTW. /
Kojto	90:cb3d968589d8	1582
Kojto	90:cb3d968589d8	1583	/! @brief Read current value of the SDHC_PROCTL_DTW field. /
Kojto	90:cb3d968589d8	1584	#define BR_SDHC_PROCTL_DTW(x) (HW_SDHC_PROCTL(x).B.DTW)
Kojto	90:cb3d968589d8	1585
Kojto	90:cb3d968589d8	1586	/! @brief Format value for bitfield SDHC_PROCTL_DTW. /
Kojto	90:cb3d968589d8	1587	#define BF_SDHC_PROCTL_DTW(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_DTW) & BM_SDHC_PROCTL_DTW)
Kojto	90:cb3d968589d8	1588
Kojto	90:cb3d968589d8	1589	/! @brief Set the DTW field to a new value. /
Kojto	90:cb3d968589d8	1590	#define BW_SDHC_PROCTL_DTW(x, v) (HW_SDHC_PROCTL_WR(x, (HW_SDHC_PROCTL_RD(x) & ~BM_SDHC_PROCTL_DTW) \| BF_SDHC_PROCTL_DTW(v)))
Kojto	90:cb3d968589d8	1591	/@}/
Kojto	90:cb3d968589d8	1592
Kojto	90:cb3d968589d8	1593	/*!
Kojto	90:cb3d968589d8	1594	* @name Register SDHC_PROCTL, field D3CD[3] (RW)
Kojto	90:cb3d968589d8	1595	*
Kojto	90:cb3d968589d8	1596	* If this bit is set, DAT3 should be pulled down to act as a card detection
Kojto	90:cb3d968589d8	1597	* pin. Be cautious when using this feature, because DAT3 is also a chip-select for
Kojto	90:cb3d968589d8	1598	* the SPI mode. A pulldown on this pin and CMD0 may set the card into the SPI
Kojto	90:cb3d968589d8	1599	* mode, which the SDHC does not support. Note: Keep this bit set if SDIO interrupt
Kojto	90:cb3d968589d8	1600	* is used.
Kojto	90:cb3d968589d8	1601	*
Kojto	90:cb3d968589d8	1602	* Values:
Kojto	90:cb3d968589d8	1603	* - 0 - DAT3 does not monitor card Insertion.
Kojto	90:cb3d968589d8	1604	* - 1 - DAT3 as card detection pin.
Kojto	90:cb3d968589d8	1605	*/
Kojto	90:cb3d968589d8	1606	/@{/
Kojto	90:cb3d968589d8	1607	#define BP_SDHC_PROCTL_D3CD (3U) /!< Bit position for SDHC_PROCTL_D3CD. /
Kojto	90:cb3d968589d8	1608	#define BM_SDHC_PROCTL_D3CD (0x00000008U) /!< Bit mask for SDHC_PROCTL_D3CD. /
Kojto	90:cb3d968589d8	1609	#define BS_SDHC_PROCTL_D3CD (1U) /!< Bit field size in bits for SDHC_PROCTL_D3CD. /
Kojto	90:cb3d968589d8	1610
Kojto	90:cb3d968589d8	1611	/! @brief Read current value of the SDHC_PROCTL_D3CD field. /
Kojto	90:cb3d968589d8	1612	#define BR_SDHC_PROCTL_D3CD(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_D3CD))
Kojto	90:cb3d968589d8	1613
Kojto	90:cb3d968589d8	1614	/! @brief Format value for bitfield SDHC_PROCTL_D3CD. /
Kojto	90:cb3d968589d8	1615	#define BF_SDHC_PROCTL_D3CD(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_D3CD) & BM_SDHC_PROCTL_D3CD)
Kojto	90:cb3d968589d8	1616
Kojto	90:cb3d968589d8	1617	/! @brief Set the D3CD field to a new value. /
Kojto	90:cb3d968589d8	1618	#define BW_SDHC_PROCTL_D3CD(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_D3CD) = (v))
Kojto	90:cb3d968589d8	1619	/@}/
Kojto	90:cb3d968589d8	1620
Kojto	90:cb3d968589d8	1621	/*!
Kojto	90:cb3d968589d8	1622	* @name Register SDHC_PROCTL, field EMODE[5:4] (RW)
Kojto	90:cb3d968589d8	1623	*
Kojto	90:cb3d968589d8	1624	* The SDHC supports all four endian modes in data transfer.
Kojto	90:cb3d968589d8	1625	*
Kojto	90:cb3d968589d8	1626	* Values:
Kojto	90:cb3d968589d8	1627	* - 00 - Big endian mode
Kojto	90:cb3d968589d8	1628	* - 01 - Half word big endian mode
Kojto	90:cb3d968589d8	1629	* - 10 - Little endian mode
Kojto	90:cb3d968589d8	1630	* - 11 - Reserved
Kojto	90:cb3d968589d8	1631	*/
Kojto	90:cb3d968589d8	1632	/@{/
Kojto	90:cb3d968589d8	1633	#define BP_SDHC_PROCTL_EMODE (4U) /!< Bit position for SDHC_PROCTL_EMODE. /
Kojto	90:cb3d968589d8	1634	#define BM_SDHC_PROCTL_EMODE (0x00000030U) /!< Bit mask for SDHC_PROCTL_EMODE. /
Kojto	90:cb3d968589d8	1635	#define BS_SDHC_PROCTL_EMODE (2U) /!< Bit field size in bits for SDHC_PROCTL_EMODE. /
Kojto	90:cb3d968589d8	1636
Kojto	90:cb3d968589d8	1637	/! @brief Read current value of the SDHC_PROCTL_EMODE field. /
Kojto	90:cb3d968589d8	1638	#define BR_SDHC_PROCTL_EMODE(x) (HW_SDHC_PROCTL(x).B.EMODE)
Kojto	90:cb3d968589d8	1639
Kojto	90:cb3d968589d8	1640	/! @brief Format value for bitfield SDHC_PROCTL_EMODE. /
Kojto	90:cb3d968589d8	1641	#define BF_SDHC_PROCTL_EMODE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_EMODE) & BM_SDHC_PROCTL_EMODE)
Kojto	90:cb3d968589d8	1642
Kojto	90:cb3d968589d8	1643	/! @brief Set the EMODE field to a new value. /
Kojto	90:cb3d968589d8	1644	#define BW_SDHC_PROCTL_EMODE(x, v) (HW_SDHC_PROCTL_WR(x, (HW_SDHC_PROCTL_RD(x) & ~BM_SDHC_PROCTL_EMODE) \| BF_SDHC_PROCTL_EMODE(v)))
Kojto	90:cb3d968589d8	1645	/@}/
Kojto	90:cb3d968589d8	1646
Kojto	90:cb3d968589d8	1647	/*!
Kojto	90:cb3d968589d8	1648	* @name Register SDHC_PROCTL, field CDTL[6] (RW)
Kojto	90:cb3d968589d8	1649	*
Kojto	90:cb3d968589d8	1650	* Enabled while the CDSS is set to 1 and it indicates card insertion.
Kojto	90:cb3d968589d8	1651	*
Kojto	90:cb3d968589d8	1652	* Values:
Kojto	90:cb3d968589d8	1653	* - 0 - Card detect test level is 0, no card inserted.
Kojto	90:cb3d968589d8	1654	* - 1 - Card detect test level is 1, card inserted.
Kojto	90:cb3d968589d8	1655	*/
Kojto	90:cb3d968589d8	1656	/@{/
Kojto	90:cb3d968589d8	1657	#define BP_SDHC_PROCTL_CDTL (6U) /!< Bit position for SDHC_PROCTL_CDTL. /
Kojto	90:cb3d968589d8	1658	#define BM_SDHC_PROCTL_CDTL (0x00000040U) /!< Bit mask for SDHC_PROCTL_CDTL. /
Kojto	90:cb3d968589d8	1659	#define BS_SDHC_PROCTL_CDTL (1U) /!< Bit field size in bits for SDHC_PROCTL_CDTL. /
Kojto	90:cb3d968589d8	1660
Kojto	90:cb3d968589d8	1661	/! @brief Read current value of the SDHC_PROCTL_CDTL field. /
Kojto	90:cb3d968589d8	1662	#define BR_SDHC_PROCTL_CDTL(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CDTL))
Kojto	90:cb3d968589d8	1663
Kojto	90:cb3d968589d8	1664	/! @brief Format value for bitfield SDHC_PROCTL_CDTL. /
Kojto	90:cb3d968589d8	1665	#define BF_SDHC_PROCTL_CDTL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_CDTL) & BM_SDHC_PROCTL_CDTL)
Kojto	90:cb3d968589d8	1666
Kojto	90:cb3d968589d8	1667	/! @brief Set the CDTL field to a new value. /
Kojto	90:cb3d968589d8	1668	#define BW_SDHC_PROCTL_CDTL(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CDTL) = (v))
Kojto	90:cb3d968589d8	1669	/@}/
Kojto	90:cb3d968589d8	1670
Kojto	90:cb3d968589d8	1671	/*!
Kojto	90:cb3d968589d8	1672	* @name Register SDHC_PROCTL, field CDSS[7] (RW)
Kojto	90:cb3d968589d8	1673	*
Kojto	90:cb3d968589d8	1674	* Selects the source for the card detection.
Kojto	90:cb3d968589d8	1675	*
Kojto	90:cb3d968589d8	1676	* Values:
Kojto	90:cb3d968589d8	1677	* - 0 - Card detection level is selected for normal purpose.
Kojto	90:cb3d968589d8	1678	* - 1 - Card detection test level is selected for test purpose.
Kojto	90:cb3d968589d8	1679	*/
Kojto	90:cb3d968589d8	1680	/@{/
Kojto	90:cb3d968589d8	1681	#define BP_SDHC_PROCTL_CDSS (7U) /!< Bit position for SDHC_PROCTL_CDSS. /
Kojto	90:cb3d968589d8	1682	#define BM_SDHC_PROCTL_CDSS (0x00000080U) /!< Bit mask for SDHC_PROCTL_CDSS. /
Kojto	90:cb3d968589d8	1683	#define BS_SDHC_PROCTL_CDSS (1U) /!< Bit field size in bits for SDHC_PROCTL_CDSS. /
Kojto	90:cb3d968589d8	1684
Kojto	90:cb3d968589d8	1685	/! @brief Read current value of the SDHC_PROCTL_CDSS field. /
Kojto	90:cb3d968589d8	1686	#define BR_SDHC_PROCTL_CDSS(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CDSS))
Kojto	90:cb3d968589d8	1687
Kojto	90:cb3d968589d8	1688	/! @brief Format value for bitfield SDHC_PROCTL_CDSS. /
Kojto	90:cb3d968589d8	1689	#define BF_SDHC_PROCTL_CDSS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_CDSS) & BM_SDHC_PROCTL_CDSS)
Kojto	90:cb3d968589d8	1690
Kojto	90:cb3d968589d8	1691	/! @brief Set the CDSS field to a new value. /
Kojto	90:cb3d968589d8	1692	#define BW_SDHC_PROCTL_CDSS(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CDSS) = (v))
Kojto	90:cb3d968589d8	1693	/@}/
Kojto	90:cb3d968589d8	1694
Kojto	90:cb3d968589d8	1695	/*!
Kojto	90:cb3d968589d8	1696	* @name Register SDHC_PROCTL, field DMAS[9:8] (RW)
Kojto	90:cb3d968589d8	1697	*
Kojto	90:cb3d968589d8	1698	* This field is valid while DMA (SDMA or ADMA) is enabled and selects the DMA
Kojto	90:cb3d968589d8	1699	* operation.
Kojto	90:cb3d968589d8	1700	*
Kojto	90:cb3d968589d8	1701	* Values:
Kojto	90:cb3d968589d8	1702	* - 00 - No DMA or simple DMA is selected.
Kojto	90:cb3d968589d8	1703	* - 01 - ADMA1 is selected.
Kojto	90:cb3d968589d8	1704	* - 10 - ADMA2 is selected.
Kojto	90:cb3d968589d8	1705	* - 11 - Reserved
Kojto	90:cb3d968589d8	1706	*/
Kojto	90:cb3d968589d8	1707	/@{/
Kojto	90:cb3d968589d8	1708	#define BP_SDHC_PROCTL_DMAS (8U) /!< Bit position for SDHC_PROCTL_DMAS. /
Kojto	90:cb3d968589d8	1709	#define BM_SDHC_PROCTL_DMAS (0x00000300U) /!< Bit mask for SDHC_PROCTL_DMAS. /
Kojto	90:cb3d968589d8	1710	#define BS_SDHC_PROCTL_DMAS (2U) /!< Bit field size in bits for SDHC_PROCTL_DMAS. /
Kojto	90:cb3d968589d8	1711
Kojto	90:cb3d968589d8	1712	/! @brief Read current value of the SDHC_PROCTL_DMAS field. /
Kojto	90:cb3d968589d8	1713	#define BR_SDHC_PROCTL_DMAS(x) (HW_SDHC_PROCTL(x).B.DMAS)
Kojto	90:cb3d968589d8	1714
Kojto	90:cb3d968589d8	1715	/! @brief Format value for bitfield SDHC_PROCTL_DMAS. /
Kojto	90:cb3d968589d8	1716	#define BF_SDHC_PROCTL_DMAS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_DMAS) & BM_SDHC_PROCTL_DMAS)
Kojto	90:cb3d968589d8	1717
Kojto	90:cb3d968589d8	1718	/! @brief Set the DMAS field to a new value. /
Kojto	90:cb3d968589d8	1719	#define BW_SDHC_PROCTL_DMAS(x, v) (HW_SDHC_PROCTL_WR(x, (HW_SDHC_PROCTL_RD(x) & ~BM_SDHC_PROCTL_DMAS) \| BF_SDHC_PROCTL_DMAS(v)))
Kojto	90:cb3d968589d8	1720	/@}/
Kojto	90:cb3d968589d8	1721
Kojto	90:cb3d968589d8	1722	/*!
Kojto	90:cb3d968589d8	1723	* @name Register SDHC_PROCTL, field SABGREQ[16] (RW)
Kojto	90:cb3d968589d8	1724	*
Kojto	90:cb3d968589d8	1725	* Used to stop executing a transaction at the next block gap for both DMA and
Kojto	90:cb3d968589d8	1726	* non-DMA transfers. Until the IRQSTATEN[TCSEN] is set to 1, indicating a
Kojto	90:cb3d968589d8	1727	* transfer completion, the host driver shall leave this bit set to 1. Clearing both
Kojto	90:cb3d968589d8	1728	* PROCTL[SABGREQ] and PROCTL[CREQ] does not cause the transaction to restart. Read
Kojto	90:cb3d968589d8	1729	* Wait is used to stop the read transaction at the block gap. The SDHC will
Kojto	90:cb3d968589d8	1730	* honor the PROCTL[SABGREQ] for write transfers, but for read transfers it requires
Kojto	90:cb3d968589d8	1731	* that SDIO card support read wait. Therefore, the host driver shall not set
Kojto	90:cb3d968589d8	1732	* this bit during read transfers unless the SDIO card supports read wait and has
Kojto	90:cb3d968589d8	1733	* set PROCTL[RWCTL] to 1, otherwise the SDHC will stop the SD bus clock to pause
Kojto	90:cb3d968589d8	1734	* the read operation during block gap. In the case of write transfers in which
Kojto	90:cb3d968589d8	1735	* the host driver writes data to the data port register, the host driver shall set
Kojto	90:cb3d968589d8	1736	* this bit after all block data is written. If this bit is set to 1, the host
Kojto	90:cb3d968589d8	1737	* driver shall not write data to the Data Port register after a block is sent.
Kojto	90:cb3d968589d8	1738	* Once this bit is set, the host driver shall not clear this bit before
Kojto	90:cb3d968589d8	1739	* IRQSTATEN[TCSEN] is set, otherwise the SDHC's behavior is undefined. This bit effects
Kojto	90:cb3d968589d8	1740	* PRSSTAT[RTA], PRSSTAT[WTA], and PRSSTAT[CDIHB].
Kojto	90:cb3d968589d8	1741	*
Kojto	90:cb3d968589d8	1742	* Values:
Kojto	90:cb3d968589d8	1743	* - 0 - Transfer
Kojto	90:cb3d968589d8	1744	* - 1 - Stop
Kojto	90:cb3d968589d8	1745	*/
Kojto	90:cb3d968589d8	1746	/@{/
Kojto	90:cb3d968589d8	1747	#define BP_SDHC_PROCTL_SABGREQ (16U) /!< Bit position for SDHC_PROCTL_SABGREQ. /
Kojto	90:cb3d968589d8	1748	#define BM_SDHC_PROCTL_SABGREQ (0x00010000U) /!< Bit mask for SDHC_PROCTL_SABGREQ. /
Kojto	90:cb3d968589d8	1749	#define BS_SDHC_PROCTL_SABGREQ (1U) /!< Bit field size in bits for SDHC_PROCTL_SABGREQ. /
Kojto	90:cb3d968589d8	1750
Kojto	90:cb3d968589d8	1751	/! @brief Read current value of the SDHC_PROCTL_SABGREQ field. /
Kojto	90:cb3d968589d8	1752	#define BR_SDHC_PROCTL_SABGREQ(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_SABGREQ))
Kojto	90:cb3d968589d8	1753
Kojto	90:cb3d968589d8	1754	/! @brief Format value for bitfield SDHC_PROCTL_SABGREQ. /
Kojto	90:cb3d968589d8	1755	#define BF_SDHC_PROCTL_SABGREQ(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_SABGREQ) & BM_SDHC_PROCTL_SABGREQ)
Kojto	90:cb3d968589d8	1756
Kojto	90:cb3d968589d8	1757	/! @brief Set the SABGREQ field to a new value. /
Kojto	90:cb3d968589d8	1758	#define BW_SDHC_PROCTL_SABGREQ(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_SABGREQ) = (v))
Kojto	90:cb3d968589d8	1759	/@}/
Kojto	90:cb3d968589d8	1760
Kojto	90:cb3d968589d8	1761	/*!
Kojto	90:cb3d968589d8	1762	* @name Register SDHC_PROCTL, field CREQ[17] (RW)
Kojto	90:cb3d968589d8	1763	*
Kojto	90:cb3d968589d8	1764	* Used to restart a transaction which was stopped using the PROCTL[SABGREQ].
Kojto	90:cb3d968589d8	1765	* When a suspend operation is not accepted by the card, it is also by setting this
Kojto	90:cb3d968589d8	1766	* bit to restart the paused transfer. To cancel stop at the block gap, set
Kojto	90:cb3d968589d8	1767	* PROCTL[SABGREQ] to 0 and set this bit to 1 to restart the transfer. The SDHC
Kojto	90:cb3d968589d8	1768	* automatically clears this bit, therefore it is not necessary for the host driver to
Kojto	90:cb3d968589d8	1769	* set this bit to 0. If both PROCTL[SABGREQ] and this bit are 1, the continue
Kojto	90:cb3d968589d8	1770	* request is ignored.
Kojto	90:cb3d968589d8	1771	*
Kojto	90:cb3d968589d8	1772	* Values:
Kojto	90:cb3d968589d8	1773	* - 0 - No effect.
Kojto	90:cb3d968589d8	1774	* - 1 - Restart
Kojto	90:cb3d968589d8	1775	*/
Kojto	90:cb3d968589d8	1776	/@{/
Kojto	90:cb3d968589d8	1777	#define BP_SDHC_PROCTL_CREQ (17U) /!< Bit position for SDHC_PROCTL_CREQ. /
Kojto	90:cb3d968589d8	1778	#define BM_SDHC_PROCTL_CREQ (0x00020000U) /!< Bit mask for SDHC_PROCTL_CREQ. /
Kojto	90:cb3d968589d8	1779	#define BS_SDHC_PROCTL_CREQ (1U) /!< Bit field size in bits for SDHC_PROCTL_CREQ. /
Kojto	90:cb3d968589d8	1780
Kojto	90:cb3d968589d8	1781	/! @brief Read current value of the SDHC_PROCTL_CREQ field. /
Kojto	90:cb3d968589d8	1782	#define BR_SDHC_PROCTL_CREQ(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CREQ))
Kojto	90:cb3d968589d8	1783
Kojto	90:cb3d968589d8	1784	/! @brief Format value for bitfield SDHC_PROCTL_CREQ. /
Kojto	90:cb3d968589d8	1785	#define BF_SDHC_PROCTL_CREQ(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_CREQ) & BM_SDHC_PROCTL_CREQ)
Kojto	90:cb3d968589d8	1786
Kojto	90:cb3d968589d8	1787	/! @brief Set the CREQ field to a new value. /
Kojto	90:cb3d968589d8	1788	#define BW_SDHC_PROCTL_CREQ(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CREQ) = (v))
Kojto	90:cb3d968589d8	1789	/@}/
Kojto	90:cb3d968589d8	1790
Kojto	90:cb3d968589d8	1791	/*!
Kojto	90:cb3d968589d8	1792	* @name Register SDHC_PROCTL, field RWCTL[18] (RW)
Kojto	90:cb3d968589d8	1793	*
Kojto	90:cb3d968589d8	1794	* The read wait function is optional for SDIO cards. If the card supports read
Kojto	90:cb3d968589d8	1795	* wait, set this bit to enable use of the read wait protocol to stop read data
Kojto	90:cb3d968589d8	1796	* using the DAT[2] line. Otherwise, the SDHC has to stop the SD Clock to hold
Kojto	90:cb3d968589d8	1797	* read data, which restricts commands generation. When the host driver detects an
Kojto	90:cb3d968589d8	1798	* SDIO card insertion, it shall set this bit according to the CCCR of the card.
Kojto	90:cb3d968589d8	1799	* If the card does not support read wait, this bit shall never be set to 1,
Kojto	90:cb3d968589d8	1800	* otherwise DAT line conflicts may occur. If this bit is set to 0, stop at block gap
Kojto	90:cb3d968589d8	1801	* during read operation is also supported, but the SDHC will stop the SD Clock
Kojto	90:cb3d968589d8	1802	* to pause reading operation.
Kojto	90:cb3d968589d8	1803	*
Kojto	90:cb3d968589d8	1804	* Values:
Kojto	90:cb3d968589d8	1805	* - 0 - Disable read wait control, and stop SD clock at block gap when SABGREQ
Kojto	90:cb3d968589d8	1806	* is set.
Kojto	90:cb3d968589d8	1807	* - 1 - Enable read wait control, and assert read wait without stopping SD
Kojto	90:cb3d968589d8	1808	* clock at block gap when SABGREQ bit is set.
Kojto	90:cb3d968589d8	1809	*/
Kojto	90:cb3d968589d8	1810	/@{/
Kojto	90:cb3d968589d8	1811	#define BP_SDHC_PROCTL_RWCTL (18U) /!< Bit position for SDHC_PROCTL_RWCTL. /
Kojto	90:cb3d968589d8	1812	#define BM_SDHC_PROCTL_RWCTL (0x00040000U) /!< Bit mask for SDHC_PROCTL_RWCTL. /
Kojto	90:cb3d968589d8	1813	#define BS_SDHC_PROCTL_RWCTL (1U) /!< Bit field size in bits for SDHC_PROCTL_RWCTL. /
Kojto	90:cb3d968589d8	1814
Kojto	90:cb3d968589d8	1815	/! @brief Read current value of the SDHC_PROCTL_RWCTL field. /
Kojto	90:cb3d968589d8	1816	#define BR_SDHC_PROCTL_RWCTL(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_RWCTL))
Kojto	90:cb3d968589d8	1817
Kojto	90:cb3d968589d8	1818	/! @brief Format value for bitfield SDHC_PROCTL_RWCTL. /
Kojto	90:cb3d968589d8	1819	#define BF_SDHC_PROCTL_RWCTL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_RWCTL) & BM_SDHC_PROCTL_RWCTL)
Kojto	90:cb3d968589d8	1820
Kojto	90:cb3d968589d8	1821	/! @brief Set the RWCTL field to a new value. /
Kojto	90:cb3d968589d8	1822	#define BW_SDHC_PROCTL_RWCTL(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_RWCTL) = (v))
Kojto	90:cb3d968589d8	1823	/@}/
Kojto	90:cb3d968589d8	1824
Kojto	90:cb3d968589d8	1825	/*!
Kojto	90:cb3d968589d8	1826	* @name Register SDHC_PROCTL, field IABG[19] (RW)
Kojto	90:cb3d968589d8	1827	*
Kojto	90:cb3d968589d8	1828	* Valid only in 4-bit mode, of the SDIO card, and selects a sample point in the
Kojto	90:cb3d968589d8	1829	* interrupt cycle. Setting to 1 enables interrupt detection at the block gap
Kojto	90:cb3d968589d8	1830	* for a multiple block transfer. Setting to 0 disables interrupt detection during
Kojto	90:cb3d968589d8	1831	* a multiple block transfer. If the SDIO card can't signal an interrupt during a
Kojto	90:cb3d968589d8	1832	* multiple block transfer, this bit must be set to 0 to avoid an inadvertent
Kojto	90:cb3d968589d8	1833	* interrupt. When the host driver detects an SDIO card insertion, it shall set
Kojto	90:cb3d968589d8	1834	* this bit according to the CCCR of the card.
Kojto	90:cb3d968589d8	1835	*
Kojto	90:cb3d968589d8	1836	* Values:
Kojto	90:cb3d968589d8	1837	* - 0 - Disabled
Kojto	90:cb3d968589d8	1838	* - 1 - Enabled
Kojto	90:cb3d968589d8	1839	*/
Kojto	90:cb3d968589d8	1840	/@{/
Kojto	90:cb3d968589d8	1841	#define BP_SDHC_PROCTL_IABG (19U) /!< Bit position for SDHC_PROCTL_IABG. /
Kojto	90:cb3d968589d8	1842	#define BM_SDHC_PROCTL_IABG (0x00080000U) /!< Bit mask for SDHC_PROCTL_IABG. /
Kojto	90:cb3d968589d8	1843	#define BS_SDHC_PROCTL_IABG (1U) /!< Bit field size in bits for SDHC_PROCTL_IABG. /
Kojto	90:cb3d968589d8	1844
Kojto	90:cb3d968589d8	1845	/! @brief Read current value of the SDHC_PROCTL_IABG field. /
Kojto	90:cb3d968589d8	1846	#define BR_SDHC_PROCTL_IABG(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_IABG))
Kojto	90:cb3d968589d8	1847
Kojto	90:cb3d968589d8	1848	/! @brief Format value for bitfield SDHC_PROCTL_IABG. /
Kojto	90:cb3d968589d8	1849	#define BF_SDHC_PROCTL_IABG(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_IABG) & BM_SDHC_PROCTL_IABG)
Kojto	90:cb3d968589d8	1850
Kojto	90:cb3d968589d8	1851	/! @brief Set the IABG field to a new value. /
Kojto	90:cb3d968589d8	1852	#define BW_SDHC_PROCTL_IABG(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_IABG) = (v))
Kojto	90:cb3d968589d8	1853	/@}/
Kojto	90:cb3d968589d8	1854
Kojto	90:cb3d968589d8	1855	/*!
Kojto	90:cb3d968589d8	1856	* @name Register SDHC_PROCTL, field WECINT[24] (RW)
Kojto	90:cb3d968589d8	1857	*
Kojto	90:cb3d968589d8	1858	* Enables a wakeup event, via IRQSTAT[CINT]. This bit can be set to 1 if FN_WUS
Kojto	90:cb3d968589d8	1859	* (Wake Up Support) in CIS is set to 1. When this bit is set, the card
Kojto	90:cb3d968589d8	1860	* interrupt status and the SDHC interrupt can be asserted without SD_CLK toggling. When
Kojto	90:cb3d968589d8	1861	* the wakeup feature is not enabled, the SD_CLK must be active to assert the
Kojto	90:cb3d968589d8	1862	* card interrupt status and the SDHC interrupt.
Kojto	90:cb3d968589d8	1863	*
Kojto	90:cb3d968589d8	1864	* Values:
Kojto	90:cb3d968589d8	1865	* - 0 - Disabled
Kojto	90:cb3d968589d8	1866	* - 1 - Enabled
Kojto	90:cb3d968589d8	1867	*/
Kojto	90:cb3d968589d8	1868	/@{/
Kojto	90:cb3d968589d8	1869	#define BP_SDHC_PROCTL_WECINT (24U) /!< Bit position for SDHC_PROCTL_WECINT. /
Kojto	90:cb3d968589d8	1870	#define BM_SDHC_PROCTL_WECINT (0x01000000U) /!< Bit mask for SDHC_PROCTL_WECINT. /
Kojto	90:cb3d968589d8	1871	#define BS_SDHC_PROCTL_WECINT (1U) /!< Bit field size in bits for SDHC_PROCTL_WECINT. /
Kojto	90:cb3d968589d8	1872
Kojto	90:cb3d968589d8	1873	/! @brief Read current value of the SDHC_PROCTL_WECINT field. /
Kojto	90:cb3d968589d8	1874	#define BR_SDHC_PROCTL_WECINT(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECINT))
Kojto	90:cb3d968589d8	1875
Kojto	90:cb3d968589d8	1876	/! @brief Format value for bitfield SDHC_PROCTL_WECINT. /
Kojto	90:cb3d968589d8	1877	#define BF_SDHC_PROCTL_WECINT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_WECINT) & BM_SDHC_PROCTL_WECINT)
Kojto	90:cb3d968589d8	1878
Kojto	90:cb3d968589d8	1879	/! @brief Set the WECINT field to a new value. /
Kojto	90:cb3d968589d8	1880	#define BW_SDHC_PROCTL_WECINT(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECINT) = (v))
Kojto	90:cb3d968589d8	1881	/@}/
Kojto	90:cb3d968589d8	1882
Kojto	90:cb3d968589d8	1883	/*!
Kojto	90:cb3d968589d8	1884	* @name Register SDHC_PROCTL, field WECINS[25] (RW)
Kojto	90:cb3d968589d8	1885	*
Kojto	90:cb3d968589d8	1886	* Enables a wakeup event, via IRQSTAT[CINS]. FN_WUS (Wake Up Support) in CIS
Kojto	90:cb3d968589d8	1887	* does not effect this bit. When this bit is set, IRQSTATEN[CINSEN] and the SDHC
Kojto	90:cb3d968589d8	1888	* interrupt can be asserted without SD_CLK toggling. When the wakeup feature is
Kojto	90:cb3d968589d8	1889	* not enabled, the SD_CLK must be active to assert IRQSTATEN[CINSEN] and the SDHC
Kojto	90:cb3d968589d8	1890	* interrupt.
Kojto	90:cb3d968589d8	1891	*
Kojto	90:cb3d968589d8	1892	* Values:
Kojto	90:cb3d968589d8	1893	* - 0 - Disabled
Kojto	90:cb3d968589d8	1894	* - 1 - Enabled
Kojto	90:cb3d968589d8	1895	*/
Kojto	90:cb3d968589d8	1896	/@{/
Kojto	90:cb3d968589d8	1897	#define BP_SDHC_PROCTL_WECINS (25U) /!< Bit position for SDHC_PROCTL_WECINS. /
Kojto	90:cb3d968589d8	1898	#define BM_SDHC_PROCTL_WECINS (0x02000000U) /!< Bit mask for SDHC_PROCTL_WECINS. /
Kojto	90:cb3d968589d8	1899	#define BS_SDHC_PROCTL_WECINS (1U) /!< Bit field size in bits for SDHC_PROCTL_WECINS. /
Kojto	90:cb3d968589d8	1900
Kojto	90:cb3d968589d8	1901	/! @brief Read current value of the SDHC_PROCTL_WECINS field. /
Kojto	90:cb3d968589d8	1902	#define BR_SDHC_PROCTL_WECINS(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECINS))
Kojto	90:cb3d968589d8	1903
Kojto	90:cb3d968589d8	1904	/! @brief Format value for bitfield SDHC_PROCTL_WECINS. /
Kojto	90:cb3d968589d8	1905	#define BF_SDHC_PROCTL_WECINS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_WECINS) & BM_SDHC_PROCTL_WECINS)
Kojto	90:cb3d968589d8	1906
Kojto	90:cb3d968589d8	1907	/! @brief Set the WECINS field to a new value. /
Kojto	90:cb3d968589d8	1908	#define BW_SDHC_PROCTL_WECINS(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECINS) = (v))
Kojto	90:cb3d968589d8	1909	/@}/
Kojto	90:cb3d968589d8	1910
Kojto	90:cb3d968589d8	1911	/*!
Kojto	90:cb3d968589d8	1912	* @name Register SDHC_PROCTL, field WECRM[26] (RW)
Kojto	90:cb3d968589d8	1913	*
Kojto	90:cb3d968589d8	1914	* Enables a wakeup event, via IRQSTAT[CRM]. FN_WUS (Wake Up Support) in CIS
Kojto	90:cb3d968589d8	1915	* does not effect this bit. When this bit is set, IRQSTAT[CRM] and the SDHC
Kojto	90:cb3d968589d8	1916	* interrupt can be asserted without SD_CLK toggling. When the wakeup feature is not
Kojto	90:cb3d968589d8	1917	* enabled, the SD_CLK must be active to assert IRQSTAT[CRM] and the SDHC interrupt.
Kojto	90:cb3d968589d8	1918	*
Kojto	90:cb3d968589d8	1919	* Values:
Kojto	90:cb3d968589d8	1920	* - 0 - Disabled
Kojto	90:cb3d968589d8	1921	* - 1 - Enabled
Kojto	90:cb3d968589d8	1922	*/
Kojto	90:cb3d968589d8	1923	/@{/
Kojto	90:cb3d968589d8	1924	#define BP_SDHC_PROCTL_WECRM (26U) /!< Bit position for SDHC_PROCTL_WECRM. /
Kojto	90:cb3d968589d8	1925	#define BM_SDHC_PROCTL_WECRM (0x04000000U) /!< Bit mask for SDHC_PROCTL_WECRM. /
Kojto	90:cb3d968589d8	1926	#define BS_SDHC_PROCTL_WECRM (1U) /!< Bit field size in bits for SDHC_PROCTL_WECRM. /
Kojto	90:cb3d968589d8	1927
Kojto	90:cb3d968589d8	1928	/! @brief Read current value of the SDHC_PROCTL_WECRM field. /
Kojto	90:cb3d968589d8	1929	#define BR_SDHC_PROCTL_WECRM(x) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECRM))
Kojto	90:cb3d968589d8	1930
Kojto	90:cb3d968589d8	1931	/! @brief Format value for bitfield SDHC_PROCTL_WECRM. /
Kojto	90:cb3d968589d8	1932	#define BF_SDHC_PROCTL_WECRM(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_WECRM) & BM_SDHC_PROCTL_WECRM)
Kojto	90:cb3d968589d8	1933
Kojto	90:cb3d968589d8	1934	/! @brief Set the WECRM field to a new value. /
Kojto	90:cb3d968589d8	1935	#define BW_SDHC_PROCTL_WECRM(x, v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECRM) = (v))
Kojto	90:cb3d968589d8	1936	/@}/
Kojto	90:cb3d968589d8	1937
Kojto	90:cb3d968589d8	1938	/*******************************************************************************
Kojto	90:cb3d968589d8	1939	* HW_SDHC_SYSCTL - System Control register
Kojto	90:cb3d968589d8	1940	******************************************************************************/
Kojto	90:cb3d968589d8	1941
Kojto	90:cb3d968589d8	1942	/*!
Kojto	90:cb3d968589d8	1943	* @brief HW_SDHC_SYSCTL - System Control register (RW)
Kojto	90:cb3d968589d8	1944	*
Kojto	90:cb3d968589d8	1945	* Reset value: 0x00008008U
Kojto	90:cb3d968589d8	1946	*/
Kojto	90:cb3d968589d8	1947	typedef union _hw_sdhc_sysctl
Kojto	90:cb3d968589d8	1948	{
Kojto	90:cb3d968589d8	1949	uint32_t U;
Kojto	90:cb3d968589d8	1950	struct _hw_sdhc_sysctl_bitfields
Kojto	90:cb3d968589d8	1951	{
Kojto	90:cb3d968589d8	1952	uint32_t IPGEN : 1; /!< [0] IPG Clock Enable /
Kojto	90:cb3d968589d8	1953	uint32_t HCKEN : 1; /!< [1] System Clock Enable /
Kojto	90:cb3d968589d8	1954	uint32_t PEREN : 1; /!< [2] Peripheral Clock Enable /
Kojto	90:cb3d968589d8	1955	uint32_t SDCLKEN : 1; /!< [3] SD Clock Enable /
Kojto	90:cb3d968589d8	1956	uint32_t DVS : 4; /!< [7:4] Divisor /
Kojto	90:cb3d968589d8	1957	uint32_t SDCLKFS : 8; /!< [15:8] SDCLK Frequency Select /
Kojto	90:cb3d968589d8	1958	uint32_t DTOCV : 4; /!< [19:16] Data Timeout Counter Value /
Kojto	90:cb3d968589d8	1959	uint32_t RESERVED0 : 4; /!< [23:20] /
Kojto	90:cb3d968589d8	1960	uint32_t RSTA : 1; /!< [24] Software Reset For ALL /
Kojto	90:cb3d968589d8	1961	uint32_t RSTC : 1; /!< [25] Software Reset For CMD Line /
Kojto	90:cb3d968589d8	1962	uint32_t RSTD : 1; /!< [26] Software Reset For DAT Line /
Kojto	90:cb3d968589d8	1963	uint32_t INITA : 1; /!< [27] Initialization Active /
Kojto	90:cb3d968589d8	1964	uint32_t RESERVED1 : 4; /!< [31:28] /
Kojto	90:cb3d968589d8	1965	} B;
Kojto	90:cb3d968589d8	1966	} hw_sdhc_sysctl_t;
Kojto	90:cb3d968589d8	1967
Kojto	90:cb3d968589d8	1968	/*!
Kojto	90:cb3d968589d8	1969	* @name Constants and macros for entire SDHC_SYSCTL register
Kojto	90:cb3d968589d8	1970	*/
Kojto	90:cb3d968589d8	1971	/@{/
Kojto	90:cb3d968589d8	1972	#define HW_SDHC_SYSCTL_ADDR(x) ((x) + 0x2CU)
Kojto	90:cb3d968589d8	1973
Kojto	90:cb3d968589d8	1974	#define HW_SDHC_SYSCTL(x) ((__IO hw_sdhc_sysctl_t ) HW_SDHC_SYSCTL_ADDR(x))
Kojto	90:cb3d968589d8	1975	#define HW_SDHC_SYSCTL_RD(x) (HW_SDHC_SYSCTL(x).U)
Kojto	90:cb3d968589d8	1976	#define HW_SDHC_SYSCTL_WR(x, v) (HW_SDHC_SYSCTL(x).U = (v))
Kojto	90:cb3d968589d8	1977	#define HW_SDHC_SYSCTL_SET(x, v) (HW_SDHC_SYSCTL_WR(x, HW_SDHC_SYSCTL_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1978	#define HW_SDHC_SYSCTL_CLR(x, v) (HW_SDHC_SYSCTL_WR(x, HW_SDHC_SYSCTL_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1979	#define HW_SDHC_SYSCTL_TOG(x, v) (HW_SDHC_SYSCTL_WR(x, HW_SDHC_SYSCTL_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1980	/@}/
Kojto	90:cb3d968589d8	1981
Kojto	90:cb3d968589d8	1982	/*
Kojto	90:cb3d968589d8	1983	* Constants & macros for individual SDHC_SYSCTL bitfields
Kojto	90:cb3d968589d8	1984	*/
Kojto	90:cb3d968589d8	1985
Kojto	90:cb3d968589d8	1986	/*!
Kojto	90:cb3d968589d8	1987	* @name Register SDHC_SYSCTL, field IPGEN[0] (RW)
Kojto	90:cb3d968589d8	1988	*
Kojto	90:cb3d968589d8	1989	* If this bit is set, bus clock will always be active and no automatic gating
Kojto	90:cb3d968589d8	1990	* is applied. The bus clock will be internally gated off, if none of the
Kojto	90:cb3d968589d8	1991	* following factors are met: The cmd part is reset, or Data part is reset, or Soft
Kojto	90:cb3d968589d8	1992	* reset, or The cmd is about to send, or Clock divisor is just updated, or Continue
Kojto	90:cb3d968589d8	1993	* request is just set, or This bit is set, or Card insertion is detected, or Card
Kojto	90:cb3d968589d8	1994	* removal is detected, or Card external interrupt is detected, or The SDHC
Kojto	90:cb3d968589d8	1995	* clock is not gated off The bus clock will not be auto gated off if the SDHC clock
Kojto	90:cb3d968589d8	1996	* is not gated off. So clearing only this bit has no effect unless the PEREN bit
Kojto	90:cb3d968589d8	1997	* is also cleared.
Kojto	90:cb3d968589d8	1998	*
Kojto	90:cb3d968589d8	1999	* Values:
Kojto	90:cb3d968589d8	2000	* - 0 - Bus clock will be internally gated off.
Kojto	90:cb3d968589d8	2001	* - 1 - Bus clock will not be automatically gated off.
Kojto	90:cb3d968589d8	2002	*/
Kojto	90:cb3d968589d8	2003	/@{/
Kojto	90:cb3d968589d8	2004	#define BP_SDHC_SYSCTL_IPGEN (0U) /!< Bit position for SDHC_SYSCTL_IPGEN. /
Kojto	90:cb3d968589d8	2005	#define BM_SDHC_SYSCTL_IPGEN (0x00000001U) /!< Bit mask for SDHC_SYSCTL_IPGEN. /
Kojto	90:cb3d968589d8	2006	#define BS_SDHC_SYSCTL_IPGEN (1U) /!< Bit field size in bits for SDHC_SYSCTL_IPGEN. /
Kojto	90:cb3d968589d8	2007
Kojto	90:cb3d968589d8	2008	/! @brief Read current value of the SDHC_SYSCTL_IPGEN field. /
Kojto	90:cb3d968589d8	2009	#define BR_SDHC_SYSCTL_IPGEN(x) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_IPGEN))
Kojto	90:cb3d968589d8	2010
Kojto	90:cb3d968589d8	2011	/! @brief Format value for bitfield SDHC_SYSCTL_IPGEN. /
Kojto	90:cb3d968589d8	2012	#define BF_SDHC_SYSCTL_IPGEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_IPGEN) & BM_SDHC_SYSCTL_IPGEN)
Kojto	90:cb3d968589d8	2013
Kojto	90:cb3d968589d8	2014	/! @brief Set the IPGEN field to a new value. /
Kojto	90:cb3d968589d8	2015	#define BW_SDHC_SYSCTL_IPGEN(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_IPGEN) = (v))
Kojto	90:cb3d968589d8	2016	/@}/
Kojto	90:cb3d968589d8	2017
Kojto	90:cb3d968589d8	2018	/*!
Kojto	90:cb3d968589d8	2019	* @name Register SDHC_SYSCTL, field HCKEN[1] (RW)
Kojto	90:cb3d968589d8	2020	*
Kojto	90:cb3d968589d8	2021	* If this bit is set, system clock will always be active and no automatic
Kojto	90:cb3d968589d8	2022	* gating is applied. When this bit is cleared, system clock will be automatically off
Kojto	90:cb3d968589d8	2023	* when no data transfer is on the SD bus.
Kojto	90:cb3d968589d8	2024	*
Kojto	90:cb3d968589d8	2025	* Values:
Kojto	90:cb3d968589d8	2026	* - 0 - System clock will be internally gated off.
Kojto	90:cb3d968589d8	2027	* - 1 - System clock will not be automatically gated off.
Kojto	90:cb3d968589d8	2028	*/
Kojto	90:cb3d968589d8	2029	/@{/
Kojto	90:cb3d968589d8	2030	#define BP_SDHC_SYSCTL_HCKEN (1U) /!< Bit position for SDHC_SYSCTL_HCKEN. /
Kojto	90:cb3d968589d8	2031	#define BM_SDHC_SYSCTL_HCKEN (0x00000002U) /!< Bit mask for SDHC_SYSCTL_HCKEN. /
Kojto	90:cb3d968589d8	2032	#define BS_SDHC_SYSCTL_HCKEN (1U) /!< Bit field size in bits for SDHC_SYSCTL_HCKEN. /
Kojto	90:cb3d968589d8	2033
Kojto	90:cb3d968589d8	2034	/! @brief Read current value of the SDHC_SYSCTL_HCKEN field. /
Kojto	90:cb3d968589d8	2035	#define BR_SDHC_SYSCTL_HCKEN(x) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_HCKEN))
Kojto	90:cb3d968589d8	2036
Kojto	90:cb3d968589d8	2037	/! @brief Format value for bitfield SDHC_SYSCTL_HCKEN. /
Kojto	90:cb3d968589d8	2038	#define BF_SDHC_SYSCTL_HCKEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_HCKEN) & BM_SDHC_SYSCTL_HCKEN)
Kojto	90:cb3d968589d8	2039
Kojto	90:cb3d968589d8	2040	/! @brief Set the HCKEN field to a new value. /
Kojto	90:cb3d968589d8	2041	#define BW_SDHC_SYSCTL_HCKEN(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_HCKEN) = (v))
Kojto	90:cb3d968589d8	2042	/@}/
Kojto	90:cb3d968589d8	2043
Kojto	90:cb3d968589d8	2044	/*!
Kojto	90:cb3d968589d8	2045	* @name Register SDHC_SYSCTL, field PEREN[2] (RW)
Kojto	90:cb3d968589d8	2046	*
Kojto	90:cb3d968589d8	2047	* If this bit is set, SDHC clock will always be active and no automatic gating
Kojto	90:cb3d968589d8	2048	* is applied. Thus the SDCLK is active except for when auto gating-off during
Kojto	90:cb3d968589d8	2049	* buffer danger (buffer about to over-run or under-run). When this bit is cleared,
Kojto	90:cb3d968589d8	2050	* the SDHC clock will be automatically off whenever there is no transaction on
Kojto	90:cb3d968589d8	2051	* the SD bus. Because this bit is only a feature enabling bit, clearing this bit
Kojto	90:cb3d968589d8	2052	* does not stop SDCLK immediately. The SDHC clock will be internally gated off,
Kojto	90:cb3d968589d8	2053	* if none of the following factors are met: The cmd part is reset, or Data part
Kojto	90:cb3d968589d8	2054	* is reset, or A soft reset, or The cmd is about to send, or Clock divisor is
Kojto	90:cb3d968589d8	2055	* just updated, or Continue request is just set, or This bit is set, or Card
Kojto	90:cb3d968589d8	2056	* insertion is detected, or Card removal is detected, or Card external interrupt is
Kojto	90:cb3d968589d8	2057	* detected, or 80 clocks for initialization phase is ongoing
Kojto	90:cb3d968589d8	2058	*
Kojto	90:cb3d968589d8	2059	* Values:
Kojto	90:cb3d968589d8	2060	* - 0 - SDHC clock will be internally gated off.
Kojto	90:cb3d968589d8	2061	* - 1 - SDHC clock will not be automatically gated off.
Kojto	90:cb3d968589d8	2062	*/
Kojto	90:cb3d968589d8	2063	/@{/
Kojto	90:cb3d968589d8	2064	#define BP_SDHC_SYSCTL_PEREN (2U) /!< Bit position for SDHC_SYSCTL_PEREN. /
Kojto	90:cb3d968589d8	2065	#define BM_SDHC_SYSCTL_PEREN (0x00000004U) /!< Bit mask for SDHC_SYSCTL_PEREN. /
Kojto	90:cb3d968589d8	2066	#define BS_SDHC_SYSCTL_PEREN (1U) /!< Bit field size in bits for SDHC_SYSCTL_PEREN. /
Kojto	90:cb3d968589d8	2067
Kojto	90:cb3d968589d8	2068	/! @brief Read current value of the SDHC_SYSCTL_PEREN field. /
Kojto	90:cb3d968589d8	2069	#define BR_SDHC_SYSCTL_PEREN(x) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_PEREN))
Kojto	90:cb3d968589d8	2070
Kojto	90:cb3d968589d8	2071	/! @brief Format value for bitfield SDHC_SYSCTL_PEREN. /
Kojto	90:cb3d968589d8	2072	#define BF_SDHC_SYSCTL_PEREN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_PEREN) & BM_SDHC_SYSCTL_PEREN)
Kojto	90:cb3d968589d8	2073
Kojto	90:cb3d968589d8	2074	/! @brief Set the PEREN field to a new value. /
Kojto	90:cb3d968589d8	2075	#define BW_SDHC_SYSCTL_PEREN(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_PEREN) = (v))
Kojto	90:cb3d968589d8	2076	/@}/
Kojto	90:cb3d968589d8	2077
Kojto	90:cb3d968589d8	2078	/*!
Kojto	90:cb3d968589d8	2079	* @name Register SDHC_SYSCTL, field SDCLKEN[3] (RW)
Kojto	90:cb3d968589d8	2080	*
Kojto	90:cb3d968589d8	2081	* The host controller shall stop SDCLK when writing this bit to 0. SDCLK
Kojto	90:cb3d968589d8	2082	* frequency can be changed when this bit is 0. Then, the host controller shall
Kojto	90:cb3d968589d8	2083	* maintain the same clock frequency until SDCLK is stopped (stop at SDCLK = 0). If the
Kojto	90:cb3d968589d8	2084	* IRQSTAT[CINS] is cleared, this bit must be cleared by the host driver to save
Kojto	90:cb3d968589d8	2085	* power.
Kojto	90:cb3d968589d8	2086	*/
Kojto	90:cb3d968589d8	2087	/@{/
Kojto	90:cb3d968589d8	2088	#define BP_SDHC_SYSCTL_SDCLKEN (3U) /!< Bit position for SDHC_SYSCTL_SDCLKEN. /
Kojto	90:cb3d968589d8	2089	#define BM_SDHC_SYSCTL_SDCLKEN (0x00000008U) /!< Bit mask for SDHC_SYSCTL_SDCLKEN. /
Kojto	90:cb3d968589d8	2090	#define BS_SDHC_SYSCTL_SDCLKEN (1U) /!< Bit field size in bits for SDHC_SYSCTL_SDCLKEN. /
Kojto	90:cb3d968589d8	2091
Kojto	90:cb3d968589d8	2092	/! @brief Read current value of the SDHC_SYSCTL_SDCLKEN field. /
Kojto	90:cb3d968589d8	2093	#define BR_SDHC_SYSCTL_SDCLKEN(x) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_SDCLKEN))
Kojto	90:cb3d968589d8	2094
Kojto	90:cb3d968589d8	2095	/! @brief Format value for bitfield SDHC_SYSCTL_SDCLKEN. /
Kojto	90:cb3d968589d8	2096	#define BF_SDHC_SYSCTL_SDCLKEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_SDCLKEN) & BM_SDHC_SYSCTL_SDCLKEN)
Kojto	90:cb3d968589d8	2097
Kojto	90:cb3d968589d8	2098	/! @brief Set the SDCLKEN field to a new value. /
Kojto	90:cb3d968589d8	2099	#define BW_SDHC_SYSCTL_SDCLKEN(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_SDCLKEN) = (v))
Kojto	90:cb3d968589d8	2100	/@}/
Kojto	90:cb3d968589d8	2101
Kojto	90:cb3d968589d8	2102	/*!
Kojto	90:cb3d968589d8	2103	* @name Register SDHC_SYSCTL, field DVS[7:4] (RW)
Kojto	90:cb3d968589d8	2104	*
Kojto	90:cb3d968589d8	2105	* Used to provide a more exact divisor to generate the desired SD clock
Kojto	90:cb3d968589d8	2106	* frequency. Note the divider can even support odd divisor without deterioration of
Kojto	90:cb3d968589d8	2107	* duty cycle. The setting are as following:
Kojto	90:cb3d968589d8	2108	*
Kojto	90:cb3d968589d8	2109	* Values:
Kojto	90:cb3d968589d8	2110	* - 0 - Divisor by 1.
Kojto	90:cb3d968589d8	2111	* - 1 - Divisor by 2.
Kojto	90:cb3d968589d8	2112	* - 1110 - Divisor by 15.
Kojto	90:cb3d968589d8	2113	* - 1111 - Divisor by 16.
Kojto	90:cb3d968589d8	2114	*/
Kojto	90:cb3d968589d8	2115	/@{/
Kojto	90:cb3d968589d8	2116	#define BP_SDHC_SYSCTL_DVS (4U) /!< Bit position for SDHC_SYSCTL_DVS. /
Kojto	90:cb3d968589d8	2117	#define BM_SDHC_SYSCTL_DVS (0x000000F0U) /!< Bit mask for SDHC_SYSCTL_DVS. /
Kojto	90:cb3d968589d8	2118	#define BS_SDHC_SYSCTL_DVS (4U) /!< Bit field size in bits for SDHC_SYSCTL_DVS. /
Kojto	90:cb3d968589d8	2119
Kojto	90:cb3d968589d8	2120	/! @brief Read current value of the SDHC_SYSCTL_DVS field. /
Kojto	90:cb3d968589d8	2121	#define BR_SDHC_SYSCTL_DVS(x) (HW_SDHC_SYSCTL(x).B.DVS)
Kojto	90:cb3d968589d8	2122
Kojto	90:cb3d968589d8	2123	/! @brief Format value for bitfield SDHC_SYSCTL_DVS. /
Kojto	90:cb3d968589d8	2124	#define BF_SDHC_SYSCTL_DVS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_DVS) & BM_SDHC_SYSCTL_DVS)
Kojto	90:cb3d968589d8	2125
Kojto	90:cb3d968589d8	2126	/! @brief Set the DVS field to a new value. /
Kojto	90:cb3d968589d8	2127	#define BW_SDHC_SYSCTL_DVS(x, v) (HW_SDHC_SYSCTL_WR(x, (HW_SDHC_SYSCTL_RD(x) & ~BM_SDHC_SYSCTL_DVS) \| BF_SDHC_SYSCTL_DVS(v)))
Kojto	90:cb3d968589d8	2128	/@}/
Kojto	90:cb3d968589d8	2129
Kojto	90:cb3d968589d8	2130	/*!
Kojto	90:cb3d968589d8	2131	* @name Register SDHC_SYSCTL, field SDCLKFS[15:8] (RW)
Kojto	90:cb3d968589d8	2132	*
Kojto	90:cb3d968589d8	2133	* Used to select the frequency of the SDCLK pin. The frequency is not
Kojto	90:cb3d968589d8	2134	* programmed directly. Rather this register holds the prescaler (this register) and
Kojto	90:cb3d968589d8	2135	* divisor (next register) of the base clock frequency register. Setting 00h bypasses
Kojto	90:cb3d968589d8	2136	* the frequency prescaler of the SD Clock. Multiple bits must not be set, or the
Kojto	90:cb3d968589d8	2137	* behavior of this prescaler is undefined. The two default divider values can
Kojto	90:cb3d968589d8	2138	* be calculated by the frequency of SDHC clock and the following divisor bits.
Kojto	90:cb3d968589d8	2139	* The frequency of SDCLK is set by the following formula: Clock frequency = (Base
Kojto	90:cb3d968589d8	2140	* clock) / (prescaler x divisor) For example, if the base clock frequency is 96
Kojto	90:cb3d968589d8	2141	* MHz, and the target frequency is 25 MHz, then choosing the prescaler value of
Kojto	90:cb3d968589d8	2142	* 01h and divisor value of 1h will yield 24 MHz, which is the nearest frequency
Kojto	90:cb3d968589d8	2143	* less than or equal to the target. Similarly, to approach a clock value of 400
Kojto	90:cb3d968589d8	2144	* kHz, the prescaler value of 08h and divisor value of eh yields the exact clock
Kojto	90:cb3d968589d8	2145	* value of 400 kHz. The reset value of this field is 80h, so if the input base
Kojto	90:cb3d968589d8	2146	* clock ( SDHC clock ) is about 96 MHz, the default SD clock after reset is 375
Kojto	90:cb3d968589d8	2147	* kHz. According to the SD Physical Specification Version 1.1 and the SDIO Card
Kojto	90:cb3d968589d8	2148	* Specification Version 1.2, the maximum SD clock frequency is 50 MHz and shall
Kojto	90:cb3d968589d8	2149	* never exceed this limit. Only the following settings are allowed:
Kojto	90:cb3d968589d8	2150	*
Kojto	90:cb3d968589d8	2151	* Values:
Kojto	90:cb3d968589d8	2152	* - 1 - Base clock divided by 2.
Kojto	90:cb3d968589d8	2153	* - 10 - Base clock divided by 4.
Kojto	90:cb3d968589d8	2154	* - 100 - Base clock divided by 8.
Kojto	90:cb3d968589d8	2155	* - 1000 - Base clock divided by 16.
Kojto	90:cb3d968589d8	2156	* - 10000 - Base clock divided by 32.
Kojto	90:cb3d968589d8	2157	* - 100000 - Base clock divided by 64.
Kojto	90:cb3d968589d8	2158	* - 1000000 - Base clock divided by 128.
Kojto	90:cb3d968589d8	2159	* - 10000000 - Base clock divided by 256.
Kojto	90:cb3d968589d8	2160	*/
Kojto	90:cb3d968589d8	2161	/@{/
Kojto	90:cb3d968589d8	2162	#define BP_SDHC_SYSCTL_SDCLKFS (8U) /!< Bit position for SDHC_SYSCTL_SDCLKFS. /
Kojto	90:cb3d968589d8	2163	#define BM_SDHC_SYSCTL_SDCLKFS (0x0000FF00U) /!< Bit mask for SDHC_SYSCTL_SDCLKFS. /
Kojto	90:cb3d968589d8	2164	#define BS_SDHC_SYSCTL_SDCLKFS (8U) /!< Bit field size in bits for SDHC_SYSCTL_SDCLKFS. /
Kojto	90:cb3d968589d8	2165
Kojto	90:cb3d968589d8	2166	/! @brief Read current value of the SDHC_SYSCTL_SDCLKFS field. /
Kojto	90:cb3d968589d8	2167	#define BR_SDHC_SYSCTL_SDCLKFS(x) (HW_SDHC_SYSCTL(x).B.SDCLKFS)
Kojto	90:cb3d968589d8	2168
Kojto	90:cb3d968589d8	2169	/! @brief Format value for bitfield SDHC_SYSCTL_SDCLKFS. /
Kojto	90:cb3d968589d8	2170	#define BF_SDHC_SYSCTL_SDCLKFS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_SDCLKFS) & BM_SDHC_SYSCTL_SDCLKFS)
Kojto	90:cb3d968589d8	2171
Kojto	90:cb3d968589d8	2172	/! @brief Set the SDCLKFS field to a new value. /
Kojto	90:cb3d968589d8	2173	#define BW_SDHC_SYSCTL_SDCLKFS(x, v) (HW_SDHC_SYSCTL_WR(x, (HW_SDHC_SYSCTL_RD(x) & ~BM_SDHC_SYSCTL_SDCLKFS) \| BF_SDHC_SYSCTL_SDCLKFS(v)))
Kojto	90:cb3d968589d8	2174	/@}/
Kojto	90:cb3d968589d8	2175
Kojto	90:cb3d968589d8	2176	/*!
Kojto	90:cb3d968589d8	2177	* @name Register SDHC_SYSCTL, field DTOCV[19:16] (RW)
Kojto	90:cb3d968589d8	2178	*
Kojto	90:cb3d968589d8	2179	* Determines the interval by which DAT line timeouts are detected. See
Kojto	90:cb3d968589d8	2180	* IRQSTAT[DTOE] for information on factors that dictate time-out generation. Time-out
Kojto	90:cb3d968589d8	2181	* clock frequency will be generated by dividing the base clock SDCLK value by this
Kojto	90:cb3d968589d8	2182	* value. The host driver can clear IRQSTATEN[DTOESEN] to prevent inadvertent
Kojto	90:cb3d968589d8	2183	* time-out events.
Kojto	90:cb3d968589d8	2184	*
Kojto	90:cb3d968589d8	2185	* Values:
Kojto	90:cb3d968589d8	2186	* - 0000 - SDCLK x 2 13
Kojto	90:cb3d968589d8	2187	* - 0001 - SDCLK x 2 14
Kojto	90:cb3d968589d8	2188	* - 1110 - SDCLK x 2 27
Kojto	90:cb3d968589d8	2189	* - 1111 - Reserved
Kojto	90:cb3d968589d8	2190	*/
Kojto	90:cb3d968589d8	2191	/@{/
Kojto	90:cb3d968589d8	2192	#define BP_SDHC_SYSCTL_DTOCV (16U) /!< Bit position for SDHC_SYSCTL_DTOCV. /
Kojto	90:cb3d968589d8	2193	#define BM_SDHC_SYSCTL_DTOCV (0x000F0000U) /!< Bit mask for SDHC_SYSCTL_DTOCV. /
Kojto	90:cb3d968589d8	2194	#define BS_SDHC_SYSCTL_DTOCV (4U) /!< Bit field size in bits for SDHC_SYSCTL_DTOCV. /
Kojto	90:cb3d968589d8	2195
Kojto	90:cb3d968589d8	2196	/! @brief Read current value of the SDHC_SYSCTL_DTOCV field. /
Kojto	90:cb3d968589d8	2197	#define BR_SDHC_SYSCTL_DTOCV(x) (HW_SDHC_SYSCTL(x).B.DTOCV)
Kojto	90:cb3d968589d8	2198
Kojto	90:cb3d968589d8	2199	/! @brief Format value for bitfield SDHC_SYSCTL_DTOCV. /
Kojto	90:cb3d968589d8	2200	#define BF_SDHC_SYSCTL_DTOCV(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_DTOCV) & BM_SDHC_SYSCTL_DTOCV)
Kojto	90:cb3d968589d8	2201
Kojto	90:cb3d968589d8	2202	/! @brief Set the DTOCV field to a new value. /
Kojto	90:cb3d968589d8	2203	#define BW_SDHC_SYSCTL_DTOCV(x, v) (HW_SDHC_SYSCTL_WR(x, (HW_SDHC_SYSCTL_RD(x) & ~BM_SDHC_SYSCTL_DTOCV) \| BF_SDHC_SYSCTL_DTOCV(v)))
Kojto	90:cb3d968589d8	2204	/@}/
Kojto	90:cb3d968589d8	2205
Kojto	90:cb3d968589d8	2206	/*!
Kojto	90:cb3d968589d8	2207	* @name Register SDHC_SYSCTL, field RSTA[24] (WORZ)
Kojto	90:cb3d968589d8	2208	*
Kojto	90:cb3d968589d8	2209	* Effects the entire host controller except for the card detection circuit.
Kojto	90:cb3d968589d8	2210	* Register bits of type ROC, RW, RW1C, RWAC are cleared. During its initialization,
Kojto	90:cb3d968589d8	2211	* the host driver shall set this bit to 1 to reset the SDHC. The SDHC shall
Kojto	90:cb3d968589d8	2212	* reset this bit to 0 when the capabilities registers are valid and the host driver
Kojto	90:cb3d968589d8	2213	* can read them. Additional use of software reset for all does not affect the
Kojto	90:cb3d968589d8	2214	* value of the capabilities registers. After this bit is set, it is recommended
Kojto	90:cb3d968589d8	2215	* that the host driver reset the external card and reinitialize it.
Kojto	90:cb3d968589d8	2216	*
Kojto	90:cb3d968589d8	2217	* Values:
Kojto	90:cb3d968589d8	2218	* - 0 - No reset.
Kojto	90:cb3d968589d8	2219	* - 1 - Reset.
Kojto	90:cb3d968589d8	2220	*/
Kojto	90:cb3d968589d8	2221	/@{/
Kojto	90:cb3d968589d8	2222	#define BP_SDHC_SYSCTL_RSTA (24U) /!< Bit position for SDHC_SYSCTL_RSTA. /
Kojto	90:cb3d968589d8	2223	#define BM_SDHC_SYSCTL_RSTA (0x01000000U) /!< Bit mask for SDHC_SYSCTL_RSTA. /
Kojto	90:cb3d968589d8	2224	#define BS_SDHC_SYSCTL_RSTA (1U) /!< Bit field size in bits for SDHC_SYSCTL_RSTA. /
Kojto	90:cb3d968589d8	2225
Kojto	90:cb3d968589d8	2226	/! @brief Format value for bitfield SDHC_SYSCTL_RSTA. /
Kojto	90:cb3d968589d8	2227	#define BF_SDHC_SYSCTL_RSTA(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_RSTA) & BM_SDHC_SYSCTL_RSTA)
Kojto	90:cb3d968589d8	2228
Kojto	90:cb3d968589d8	2229	/! @brief Set the RSTA field to a new value. /
Kojto	90:cb3d968589d8	2230	#define BW_SDHC_SYSCTL_RSTA(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_RSTA) = (v))
Kojto	90:cb3d968589d8	2231	/@}/
Kojto	90:cb3d968589d8	2232
Kojto	90:cb3d968589d8	2233	/*!
Kojto	90:cb3d968589d8	2234	* @name Register SDHC_SYSCTL, field RSTC[25] (WORZ)
Kojto	90:cb3d968589d8	2235	*
Kojto	90:cb3d968589d8	2236	* Only part of the command circuit is reset. The following registers and bits
Kojto	90:cb3d968589d8	2237	* are cleared by this bit: PRSSTAT[CIHB] IRQSTAT[CC]
Kojto	90:cb3d968589d8	2238	*
Kojto	90:cb3d968589d8	2239	* Values:
Kojto	90:cb3d968589d8	2240	* - 0 - No reset.
Kojto	90:cb3d968589d8	2241	* - 1 - Reset.
Kojto	90:cb3d968589d8	2242	*/
Kojto	90:cb3d968589d8	2243	/@{/
Kojto	90:cb3d968589d8	2244	#define BP_SDHC_SYSCTL_RSTC (25U) /!< Bit position for SDHC_SYSCTL_RSTC. /
Kojto	90:cb3d968589d8	2245	#define BM_SDHC_SYSCTL_RSTC (0x02000000U) /!< Bit mask for SDHC_SYSCTL_RSTC. /
Kojto	90:cb3d968589d8	2246	#define BS_SDHC_SYSCTL_RSTC (1U) /!< Bit field size in bits for SDHC_SYSCTL_RSTC. /
Kojto	90:cb3d968589d8	2247
Kojto	90:cb3d968589d8	2248	/! @brief Format value for bitfield SDHC_SYSCTL_RSTC. /
Kojto	90:cb3d968589d8	2249	#define BF_SDHC_SYSCTL_RSTC(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_RSTC) & BM_SDHC_SYSCTL_RSTC)
Kojto	90:cb3d968589d8	2250
Kojto	90:cb3d968589d8	2251	/! @brief Set the RSTC field to a new value. /
Kojto	90:cb3d968589d8	2252	#define BW_SDHC_SYSCTL_RSTC(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_RSTC) = (v))
Kojto	90:cb3d968589d8	2253	/@}/
Kojto	90:cb3d968589d8	2254
Kojto	90:cb3d968589d8	2255	/*!
Kojto	90:cb3d968589d8	2256	* @name Register SDHC_SYSCTL, field RSTD[26] (WORZ)
Kojto	90:cb3d968589d8	2257	*
Kojto	90:cb3d968589d8	2258	* Only part of the data circuit is reset. DMA circuit is also reset. The
Kojto	90:cb3d968589d8	2259	* following registers and bits are cleared by this bit: Data Port register Buffer Is
Kojto	90:cb3d968589d8	2260	* Cleared And Initialized.Present State register Buffer Read Enable Buffer Write
Kojto	90:cb3d968589d8	2261	* Enable Read Transfer Active Write Transfer Active DAT Line Active Command
Kojto	90:cb3d968589d8	2262	* Inhibit (DAT) Protocol Control register Continue Request Stop At Block Gap Request
Kojto	90:cb3d968589d8	2263	* Interrupt Status register Buffer Read Ready Buffer Write Ready DMA Interrupt
Kojto	90:cb3d968589d8	2264	* Block Gap Event Transfer Complete
Kojto	90:cb3d968589d8	2265	*
Kojto	90:cb3d968589d8	2266	* Values:
Kojto	90:cb3d968589d8	2267	* - 0 - No reset.
Kojto	90:cb3d968589d8	2268	* - 1 - Reset.
Kojto	90:cb3d968589d8	2269	*/
Kojto	90:cb3d968589d8	2270	/@{/
Kojto	90:cb3d968589d8	2271	#define BP_SDHC_SYSCTL_RSTD (26U) /!< Bit position for SDHC_SYSCTL_RSTD. /
Kojto	90:cb3d968589d8	2272	#define BM_SDHC_SYSCTL_RSTD (0x04000000U) /!< Bit mask for SDHC_SYSCTL_RSTD. /
Kojto	90:cb3d968589d8	2273	#define BS_SDHC_SYSCTL_RSTD (1U) /!< Bit field size in bits for SDHC_SYSCTL_RSTD. /
Kojto	90:cb3d968589d8	2274
Kojto	90:cb3d968589d8	2275	/! @brief Format value for bitfield SDHC_SYSCTL_RSTD. /
Kojto	90:cb3d968589d8	2276	#define BF_SDHC_SYSCTL_RSTD(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_RSTD) & BM_SDHC_SYSCTL_RSTD)
Kojto	90:cb3d968589d8	2277
Kojto	90:cb3d968589d8	2278	/! @brief Set the RSTD field to a new value. /
Kojto	90:cb3d968589d8	2279	#define BW_SDHC_SYSCTL_RSTD(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_RSTD) = (v))
Kojto	90:cb3d968589d8	2280	/@}/
Kojto	90:cb3d968589d8	2281
Kojto	90:cb3d968589d8	2282	/*!
Kojto	90:cb3d968589d8	2283	* @name Register SDHC_SYSCTL, field INITA[27] (RW)
Kojto	90:cb3d968589d8	2284	*
Kojto	90:cb3d968589d8	2285	* When this bit is set, 80 SD-clocks are sent to the card. After the 80 clocks
Kojto	90:cb3d968589d8	2286	* are sent, this bit is self-cleared. This bit is very useful during the card
Kojto	90:cb3d968589d8	2287	* power-up period when 74 SD-clocks are needed and the clock auto gating feature
Kojto	90:cb3d968589d8	2288	* is enabled. Writing 1 to this bit when this bit is already 1 has no effect.
Kojto	90:cb3d968589d8	2289	* Writing 0 to this bit at any time has no effect. When either of the PRSSTAT[CIHB]
Kojto	90:cb3d968589d8	2290	* and PRSSTAT[CDIHB] bits are set, writing 1 to this bit is ignored, that is,
Kojto	90:cb3d968589d8	2291	* when command line or data lines are active, write to this bit is not allowed.
Kojto	90:cb3d968589d8	2292	* On the otherhand, when this bit is set, that is, during intialization active
Kojto	90:cb3d968589d8	2293	* period, it is allowed to issue command, and the command bit stream will appear
Kojto	90:cb3d968589d8	2294	* on the CMD pad after all 80 clock cycles are done. So when this command ends,
Kojto	90:cb3d968589d8	2295	* the driver can make sure the 80 clock cycles are sent out. This is very useful
Kojto	90:cb3d968589d8	2296	* when the driver needs send 80 cycles to the card and does not want to wait
Kojto	90:cb3d968589d8	2297	* till this bit is self-cleared.
Kojto	90:cb3d968589d8	2298	*/
Kojto	90:cb3d968589d8	2299	/@{/
Kojto	90:cb3d968589d8	2300	#define BP_SDHC_SYSCTL_INITA (27U) /!< Bit position for SDHC_SYSCTL_INITA. /
Kojto	90:cb3d968589d8	2301	#define BM_SDHC_SYSCTL_INITA (0x08000000U) /!< Bit mask for SDHC_SYSCTL_INITA. /
Kojto	90:cb3d968589d8	2302	#define BS_SDHC_SYSCTL_INITA (1U) /!< Bit field size in bits for SDHC_SYSCTL_INITA. /
Kojto	90:cb3d968589d8	2303
Kojto	90:cb3d968589d8	2304	/! @brief Read current value of the SDHC_SYSCTL_INITA field. /
Kojto	90:cb3d968589d8	2305	#define BR_SDHC_SYSCTL_INITA(x) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_INITA))
Kojto	90:cb3d968589d8	2306
Kojto	90:cb3d968589d8	2307	/! @brief Format value for bitfield SDHC_SYSCTL_INITA. /
Kojto	90:cb3d968589d8	2308	#define BF_SDHC_SYSCTL_INITA(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_INITA) & BM_SDHC_SYSCTL_INITA)
Kojto	90:cb3d968589d8	2309
Kojto	90:cb3d968589d8	2310	/! @brief Set the INITA field to a new value. /
Kojto	90:cb3d968589d8	2311	#define BW_SDHC_SYSCTL_INITA(x, v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_INITA) = (v))
Kojto	90:cb3d968589d8	2312	/@}/
Kojto	90:cb3d968589d8	2313
Kojto	90:cb3d968589d8	2314	/*******************************************************************************
Kojto	90:cb3d968589d8	2315	* HW_SDHC_IRQSTAT - Interrupt Status register
Kojto	90:cb3d968589d8	2316	******************************************************************************/
Kojto	90:cb3d968589d8	2317
Kojto	90:cb3d968589d8	2318	/*!
Kojto	90:cb3d968589d8	2319	* @brief HW_SDHC_IRQSTAT - Interrupt Status register (RW)
Kojto	90:cb3d968589d8	2320	*
Kojto	90:cb3d968589d8	2321	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2322	*
Kojto	90:cb3d968589d8	2323	* An interrupt is generated when the Normal Interrupt Signal Enable is enabled
Kojto	90:cb3d968589d8	2324	* and at least one of the status bits is set to 1. For all bits, writing 1 to a
Kojto	90:cb3d968589d8	2325	* bit clears it; writing to 0 keeps the bit unchanged. More than one status can
Kojto	90:cb3d968589d8	2326	* be cleared with a single register write. For Card Interrupt, before writing 1
Kojto	90:cb3d968589d8	2327	* to clear, it is required that the card stops asserting the interrupt, meaning
Kojto	90:cb3d968589d8	2328	* that when the Card Driver services the interrupt condition, otherwise the CINT
Kojto	90:cb3d968589d8	2329	* bit will be asserted again. The table below shows the relationship between
Kojto	90:cb3d968589d8	2330	* the CTOE and the CC bits. SDHC status for CTOE/CC bit combinations Command
Kojto	90:cb3d968589d8	2331	* complete Command timeout error Meaning of the status 0 0 X X 1 Response not
Kojto	90:cb3d968589d8	2332	* received within 64 SDCLK cycles 1 0 Response received The table below shows the
Kojto	90:cb3d968589d8	2333	* relationship between the Transfer Complete and the Data Timeout Error. SDHC status
Kojto	90:cb3d968589d8	2334	* for data timeout error/transfer complete bit combinations Transfer complete
Kojto	90:cb3d968589d8	2335	* Data timeout error Meaning of the status 0 0 X 0 1 Timeout occurred during
Kojto	90:cb3d968589d8	2336	* transfer 1 X Data transfer complete The table below shows the relationship between
Kojto	90:cb3d968589d8	2337	* the command CRC Error (CCE) and Command Timeout Error (CTOE). SDHC status for
Kojto	90:cb3d968589d8	2338	* CCE/CTOE Bit Combinations Command complete Command timeout error Meaning of
Kojto	90:cb3d968589d8	2339	* the status 0 0 No error 0 1 Response timeout error 1 0 Response CRC error 1 1
Kojto	90:cb3d968589d8	2340	* CMD line conflict
Kojto	90:cb3d968589d8	2341	*/
Kojto	90:cb3d968589d8	2342	typedef union _hw_sdhc_irqstat
Kojto	90:cb3d968589d8	2343	{
Kojto	90:cb3d968589d8	2344	uint32_t U;
Kojto	90:cb3d968589d8	2345	struct _hw_sdhc_irqstat_bitfields
Kojto	90:cb3d968589d8	2346	{
Kojto	90:cb3d968589d8	2347	uint32_t CC : 1; /!< [0] Command Complete /
Kojto	90:cb3d968589d8	2348	uint32_t TC : 1; /!< [1] Transfer Complete /
Kojto	90:cb3d968589d8	2349	uint32_t BGE : 1; /!< [2] Block Gap Event /
Kojto	90:cb3d968589d8	2350	uint32_t DINT : 1; /!< [3] DMA Interrupt /
Kojto	90:cb3d968589d8	2351	uint32_t BWR : 1; /!< [4] Buffer Write Ready /
Kojto	90:cb3d968589d8	2352	uint32_t BRR : 1; /!< [5] Buffer Read Ready /
Kojto	90:cb3d968589d8	2353	uint32_t CINS : 1; /!< [6] Card Insertion /
Kojto	90:cb3d968589d8	2354	uint32_t CRM : 1; /!< [7] Card Removal /
Kojto	90:cb3d968589d8	2355	uint32_t CINT : 1; /!< [8] Card Interrupt /
Kojto	90:cb3d968589d8	2356	uint32_t RESERVED0 : 7; /!< [15:9] /
Kojto	90:cb3d968589d8	2357	uint32_t CTOE : 1; /!< [16] Command Timeout Error /
Kojto	90:cb3d968589d8	2358	uint32_t CCE : 1; /!< [17] Command CRC Error /
Kojto	90:cb3d968589d8	2359	uint32_t CEBE : 1; /!< [18] Command End Bit Error /
Kojto	90:cb3d968589d8	2360	uint32_t CIE : 1; /!< [19] Command Index Error /
Kojto	90:cb3d968589d8	2361	uint32_t DTOE : 1; /!< [20] Data Timeout Error /
Kojto	90:cb3d968589d8	2362	uint32_t DCE : 1; /!< [21] Data CRC Error /
Kojto	90:cb3d968589d8	2363	uint32_t DEBE : 1; /!< [22] Data End Bit Error /
Kojto	90:cb3d968589d8	2364	uint32_t RESERVED1 : 1; /!< [23] /
Kojto	90:cb3d968589d8	2365	uint32_t AC12E : 1; /!< [24] Auto CMD12 Error /
Kojto	90:cb3d968589d8	2366	uint32_t RESERVED2 : 3; /!< [27:25] /
Kojto	90:cb3d968589d8	2367	uint32_t DMAE : 1; /!< [28] DMA Error /
Kojto	90:cb3d968589d8	2368	uint32_t RESERVED3 : 3; /!< [31:29] /
Kojto	90:cb3d968589d8	2369	} B;
Kojto	90:cb3d968589d8	2370	} hw_sdhc_irqstat_t;
Kojto	90:cb3d968589d8	2371
Kojto	90:cb3d968589d8	2372	/*!
Kojto	90:cb3d968589d8	2373	* @name Constants and macros for entire SDHC_IRQSTAT register
Kojto	90:cb3d968589d8	2374	*/
Kojto	90:cb3d968589d8	2375	/@{/
Kojto	90:cb3d968589d8	2376	#define HW_SDHC_IRQSTAT_ADDR(x) ((x) + 0x30U)
Kojto	90:cb3d968589d8	2377
Kojto	90:cb3d968589d8	2378	#define HW_SDHC_IRQSTAT(x) ((__IO hw_sdhc_irqstat_t ) HW_SDHC_IRQSTAT_ADDR(x))
Kojto	90:cb3d968589d8	2379	#define HW_SDHC_IRQSTAT_RD(x) (HW_SDHC_IRQSTAT(x).U)
Kojto	90:cb3d968589d8	2380	#define HW_SDHC_IRQSTAT_WR(x, v) (HW_SDHC_IRQSTAT(x).U = (v))
Kojto	90:cb3d968589d8	2381	#define HW_SDHC_IRQSTAT_SET(x, v) (HW_SDHC_IRQSTAT_WR(x, HW_SDHC_IRQSTAT_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2382	#define HW_SDHC_IRQSTAT_CLR(x, v) (HW_SDHC_IRQSTAT_WR(x, HW_SDHC_IRQSTAT_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2383	#define HW_SDHC_IRQSTAT_TOG(x, v) (HW_SDHC_IRQSTAT_WR(x, HW_SDHC_IRQSTAT_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2384	/@}/
Kojto	90:cb3d968589d8	2385
Kojto	90:cb3d968589d8	2386	/*
Kojto	90:cb3d968589d8	2387	* Constants & macros for individual SDHC_IRQSTAT bitfields
Kojto	90:cb3d968589d8	2388	*/
Kojto	90:cb3d968589d8	2389
Kojto	90:cb3d968589d8	2390	/*!
Kojto	90:cb3d968589d8	2391	* @name Register SDHC_IRQSTAT, field CC[0] (W1C)
Kojto	90:cb3d968589d8	2392	*
Kojto	90:cb3d968589d8	2393	* This bit is set when you receive the end bit of the command response, except
Kojto	90:cb3d968589d8	2394	* Auto CMD12. See PRSSTAT[CIHB].
Kojto	90:cb3d968589d8	2395	*
Kojto	90:cb3d968589d8	2396	* Values:
Kojto	90:cb3d968589d8	2397	* - 0 - Command not complete.
Kojto	90:cb3d968589d8	2398	* - 1 - Command complete.
Kojto	90:cb3d968589d8	2399	*/
Kojto	90:cb3d968589d8	2400	/@{/
Kojto	90:cb3d968589d8	2401	#define BP_SDHC_IRQSTAT_CC (0U) /!< Bit position for SDHC_IRQSTAT_CC. /
Kojto	90:cb3d968589d8	2402	#define BM_SDHC_IRQSTAT_CC (0x00000001U) /!< Bit mask for SDHC_IRQSTAT_CC. /
Kojto	90:cb3d968589d8	2403	#define BS_SDHC_IRQSTAT_CC (1U) /!< Bit field size in bits for SDHC_IRQSTAT_CC. /
Kojto	90:cb3d968589d8	2404
Kojto	90:cb3d968589d8	2405	/! @brief Read current value of the SDHC_IRQSTAT_CC field. /
Kojto	90:cb3d968589d8	2406	#define BR_SDHC_IRQSTAT_CC(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CC))
Kojto	90:cb3d968589d8	2407
Kojto	90:cb3d968589d8	2408	/! @brief Format value for bitfield SDHC_IRQSTAT_CC. /
Kojto	90:cb3d968589d8	2409	#define BF_SDHC_IRQSTAT_CC(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CC) & BM_SDHC_IRQSTAT_CC)
Kojto	90:cb3d968589d8	2410
Kojto	90:cb3d968589d8	2411	/! @brief Set the CC field to a new value. /
Kojto	90:cb3d968589d8	2412	#define BW_SDHC_IRQSTAT_CC(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CC) = (v))
Kojto	90:cb3d968589d8	2413	/@}/
Kojto	90:cb3d968589d8	2414
Kojto	90:cb3d968589d8	2415	/*!
Kojto	90:cb3d968589d8	2416	* @name Register SDHC_IRQSTAT, field TC[1] (W1C)
Kojto	90:cb3d968589d8	2417	*
Kojto	90:cb3d968589d8	2418	* This bit is set when a read or write transfer is completed. In the case of a
Kojto	90:cb3d968589d8	2419	* read transaction: This bit is set at the falling edge of the read transfer
Kojto	90:cb3d968589d8	2420	* active status. There are two cases in which this interrupt is generated. The
Kojto	90:cb3d968589d8	2421	* first is when a data transfer is completed as specified by the data length, after
Kojto	90:cb3d968589d8	2422	* the last data has been read to the host system. The second is when data has
Kojto	90:cb3d968589d8	2423	* stopped at the block gap and completed the data transfer by setting
Kojto	90:cb3d968589d8	2424	* PROCTL[SABGREQ], after valid data has been read to the host system. In the case of a write
Kojto	90:cb3d968589d8	2425	* transaction: This bit is set at the falling edge of the DAT line active
Kojto	90:cb3d968589d8	2426	* status. There are two cases in which this interrupt is generated. The first is when
Kojto	90:cb3d968589d8	2427	* the last data is written to the SD card as specified by the data length and
Kojto	90:cb3d968589d8	2428	* the busy signal is released. The second is when data transfers are stopped at
Kojto	90:cb3d968589d8	2429	* the block gap, by setting PROCTL[SABGREQ], and the data transfers are
Kojto	90:cb3d968589d8	2430	* completed,after valid data is written to the SD card and the busy signal released.
Kojto	90:cb3d968589d8	2431	*
Kojto	90:cb3d968589d8	2432	* Values:
Kojto	90:cb3d968589d8	2433	* - 0 - Transfer not complete.
Kojto	90:cb3d968589d8	2434	* - 1 - Transfer complete.
Kojto	90:cb3d968589d8	2435	*/
Kojto	90:cb3d968589d8	2436	/@{/
Kojto	90:cb3d968589d8	2437	#define BP_SDHC_IRQSTAT_TC (1U) /!< Bit position for SDHC_IRQSTAT_TC. /
Kojto	90:cb3d968589d8	2438	#define BM_SDHC_IRQSTAT_TC (0x00000002U) /!< Bit mask for SDHC_IRQSTAT_TC. /
Kojto	90:cb3d968589d8	2439	#define BS_SDHC_IRQSTAT_TC (1U) /!< Bit field size in bits for SDHC_IRQSTAT_TC. /
Kojto	90:cb3d968589d8	2440
Kojto	90:cb3d968589d8	2441	/! @brief Read current value of the SDHC_IRQSTAT_TC field. /
Kojto	90:cb3d968589d8	2442	#define BR_SDHC_IRQSTAT_TC(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_TC))
Kojto	90:cb3d968589d8	2443
Kojto	90:cb3d968589d8	2444	/! @brief Format value for bitfield SDHC_IRQSTAT_TC. /
Kojto	90:cb3d968589d8	2445	#define BF_SDHC_IRQSTAT_TC(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_TC) & BM_SDHC_IRQSTAT_TC)
Kojto	90:cb3d968589d8	2446
Kojto	90:cb3d968589d8	2447	/! @brief Set the TC field to a new value. /
Kojto	90:cb3d968589d8	2448	#define BW_SDHC_IRQSTAT_TC(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_TC) = (v))
Kojto	90:cb3d968589d8	2449	/@}/
Kojto	90:cb3d968589d8	2450
Kojto	90:cb3d968589d8	2451	/*!
Kojto	90:cb3d968589d8	2452	* @name Register SDHC_IRQSTAT, field BGE[2] (W1C)
Kojto	90:cb3d968589d8	2453	*
Kojto	90:cb3d968589d8	2454	* If PROCTL[SABGREQ] is set, this bit is set when a read or write transaction
Kojto	90:cb3d968589d8	2455	* is stopped at a block gap. If PROCTL[SABGREQ] is not set to 1, this bit is not
Kojto	90:cb3d968589d8	2456	* set to 1. In the case of a read transaction: This bit is set at the falling
Kojto	90:cb3d968589d8	2457	* edge of the DAT line active status, when the transaction is stopped at SD Bus
Kojto	90:cb3d968589d8	2458	* timing. The read wait must be supported in order to use this function. In the
Kojto	90:cb3d968589d8	2459	* case of write transaction: This bit is set at the falling edge of write transfer
Kojto	90:cb3d968589d8	2460	* active status, after getting CRC status at SD bus timing.
Kojto	90:cb3d968589d8	2461	*
Kojto	90:cb3d968589d8	2462	* Values:
Kojto	90:cb3d968589d8	2463	* - 0 - No block gap event.
Kojto	90:cb3d968589d8	2464	* - 1 - Transaction stopped at block gap.
Kojto	90:cb3d968589d8	2465	*/
Kojto	90:cb3d968589d8	2466	/@{/
Kojto	90:cb3d968589d8	2467	#define BP_SDHC_IRQSTAT_BGE (2U) /!< Bit position for SDHC_IRQSTAT_BGE. /
Kojto	90:cb3d968589d8	2468	#define BM_SDHC_IRQSTAT_BGE (0x00000004U) /!< Bit mask for SDHC_IRQSTAT_BGE. /
Kojto	90:cb3d968589d8	2469	#define BS_SDHC_IRQSTAT_BGE (1U) /!< Bit field size in bits for SDHC_IRQSTAT_BGE. /
Kojto	90:cb3d968589d8	2470
Kojto	90:cb3d968589d8	2471	/! @brief Read current value of the SDHC_IRQSTAT_BGE field. /
Kojto	90:cb3d968589d8	2472	#define BR_SDHC_IRQSTAT_BGE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BGE))
Kojto	90:cb3d968589d8	2473
Kojto	90:cb3d968589d8	2474	/! @brief Format value for bitfield SDHC_IRQSTAT_BGE. /
Kojto	90:cb3d968589d8	2475	#define BF_SDHC_IRQSTAT_BGE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_BGE) & BM_SDHC_IRQSTAT_BGE)
Kojto	90:cb3d968589d8	2476
Kojto	90:cb3d968589d8	2477	/! @brief Set the BGE field to a new value. /
Kojto	90:cb3d968589d8	2478	#define BW_SDHC_IRQSTAT_BGE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BGE) = (v))
Kojto	90:cb3d968589d8	2479	/@}/
Kojto	90:cb3d968589d8	2480
Kojto	90:cb3d968589d8	2481	/*!
Kojto	90:cb3d968589d8	2482	* @name Register SDHC_IRQSTAT, field DINT[3] (W1C)
Kojto	90:cb3d968589d8	2483	*
Kojto	90:cb3d968589d8	2484	* Occurs only when the internal DMA finishes the data transfer successfully.
Kojto	90:cb3d968589d8	2485	* Whenever errors occur during data transfer, this bit will not be set. Instead,
Kojto	90:cb3d968589d8	2486	* the DMAE bit will be set. Either Simple DMA or ADMA finishes data transferring,
Kojto	90:cb3d968589d8	2487	* this bit will be set.
Kojto	90:cb3d968589d8	2488	*
Kojto	90:cb3d968589d8	2489	* Values:
Kojto	90:cb3d968589d8	2490	* - 0 - No DMA Interrupt.
Kojto	90:cb3d968589d8	2491	* - 1 - DMA Interrupt is generated.
Kojto	90:cb3d968589d8	2492	*/
Kojto	90:cb3d968589d8	2493	/@{/
Kojto	90:cb3d968589d8	2494	#define BP_SDHC_IRQSTAT_DINT (3U) /!< Bit position for SDHC_IRQSTAT_DINT. /
Kojto	90:cb3d968589d8	2495	#define BM_SDHC_IRQSTAT_DINT (0x00000008U) /!< Bit mask for SDHC_IRQSTAT_DINT. /
Kojto	90:cb3d968589d8	2496	#define BS_SDHC_IRQSTAT_DINT (1U) /!< Bit field size in bits for SDHC_IRQSTAT_DINT. /
Kojto	90:cb3d968589d8	2497
Kojto	90:cb3d968589d8	2498	/! @brief Read current value of the SDHC_IRQSTAT_DINT field. /
Kojto	90:cb3d968589d8	2499	#define BR_SDHC_IRQSTAT_DINT(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DINT))
Kojto	90:cb3d968589d8	2500
Kojto	90:cb3d968589d8	2501	/! @brief Format value for bitfield SDHC_IRQSTAT_DINT. /
Kojto	90:cb3d968589d8	2502	#define BF_SDHC_IRQSTAT_DINT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_DINT) & BM_SDHC_IRQSTAT_DINT)
Kojto	90:cb3d968589d8	2503
Kojto	90:cb3d968589d8	2504	/! @brief Set the DINT field to a new value. /
Kojto	90:cb3d968589d8	2505	#define BW_SDHC_IRQSTAT_DINT(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DINT) = (v))
Kojto	90:cb3d968589d8	2506	/@}/
Kojto	90:cb3d968589d8	2507
Kojto	90:cb3d968589d8	2508	/*!
Kojto	90:cb3d968589d8	2509	* @name Register SDHC_IRQSTAT, field BWR[4] (W1C)
Kojto	90:cb3d968589d8	2510	*
Kojto	90:cb3d968589d8	2511	* This status bit is set if the Buffer Write Enable bit, in the Present State
Kojto	90:cb3d968589d8	2512	* register, changes from 0 to 1. See the Buffer Write Enable bit in the Present
Kojto	90:cb3d968589d8	2513	* State register for additional information.
Kojto	90:cb3d968589d8	2514	*
Kojto	90:cb3d968589d8	2515	* Values:
Kojto	90:cb3d968589d8	2516	* - 0 - Not ready to write buffer.
Kojto	90:cb3d968589d8	2517	* - 1 - Ready to write buffer.
Kojto	90:cb3d968589d8	2518	*/
Kojto	90:cb3d968589d8	2519	/@{/
Kojto	90:cb3d968589d8	2520	#define BP_SDHC_IRQSTAT_BWR (4U) /!< Bit position for SDHC_IRQSTAT_BWR. /
Kojto	90:cb3d968589d8	2521	#define BM_SDHC_IRQSTAT_BWR (0x00000010U) /!< Bit mask for SDHC_IRQSTAT_BWR. /
Kojto	90:cb3d968589d8	2522	#define BS_SDHC_IRQSTAT_BWR (1U) /!< Bit field size in bits for SDHC_IRQSTAT_BWR. /
Kojto	90:cb3d968589d8	2523
Kojto	90:cb3d968589d8	2524	/! @brief Read current value of the SDHC_IRQSTAT_BWR field. /
Kojto	90:cb3d968589d8	2525	#define BR_SDHC_IRQSTAT_BWR(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BWR))
Kojto	90:cb3d968589d8	2526
Kojto	90:cb3d968589d8	2527	/! @brief Format value for bitfield SDHC_IRQSTAT_BWR. /
Kojto	90:cb3d968589d8	2528	#define BF_SDHC_IRQSTAT_BWR(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_BWR) & BM_SDHC_IRQSTAT_BWR)
Kojto	90:cb3d968589d8	2529
Kojto	90:cb3d968589d8	2530	/! @brief Set the BWR field to a new value. /
Kojto	90:cb3d968589d8	2531	#define BW_SDHC_IRQSTAT_BWR(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BWR) = (v))
Kojto	90:cb3d968589d8	2532	/@}/
Kojto	90:cb3d968589d8	2533
Kojto	90:cb3d968589d8	2534	/*!
Kojto	90:cb3d968589d8	2535	* @name Register SDHC_IRQSTAT, field BRR[5] (W1C)
Kojto	90:cb3d968589d8	2536	*
Kojto	90:cb3d968589d8	2537	* This status bit is set if the Buffer Read Enable bit, in the Present State
Kojto	90:cb3d968589d8	2538	* register, changes from 0 to 1. See the Buffer Read Enable bit in the Present
Kojto	90:cb3d968589d8	2539	* State register for additional information.
Kojto	90:cb3d968589d8	2540	*
Kojto	90:cb3d968589d8	2541	* Values:
Kojto	90:cb3d968589d8	2542	* - 0 - Not ready to read buffer.
Kojto	90:cb3d968589d8	2543	* - 1 - Ready to read buffer.
Kojto	90:cb3d968589d8	2544	*/
Kojto	90:cb3d968589d8	2545	/@{/
Kojto	90:cb3d968589d8	2546	#define BP_SDHC_IRQSTAT_BRR (5U) /!< Bit position for SDHC_IRQSTAT_BRR. /
Kojto	90:cb3d968589d8	2547	#define BM_SDHC_IRQSTAT_BRR (0x00000020U) /!< Bit mask for SDHC_IRQSTAT_BRR. /
Kojto	90:cb3d968589d8	2548	#define BS_SDHC_IRQSTAT_BRR (1U) /!< Bit field size in bits for SDHC_IRQSTAT_BRR. /
Kojto	90:cb3d968589d8	2549
Kojto	90:cb3d968589d8	2550	/! @brief Read current value of the SDHC_IRQSTAT_BRR field. /
Kojto	90:cb3d968589d8	2551	#define BR_SDHC_IRQSTAT_BRR(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BRR))
Kojto	90:cb3d968589d8	2552
Kojto	90:cb3d968589d8	2553	/! @brief Format value for bitfield SDHC_IRQSTAT_BRR. /
Kojto	90:cb3d968589d8	2554	#define BF_SDHC_IRQSTAT_BRR(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_BRR) & BM_SDHC_IRQSTAT_BRR)
Kojto	90:cb3d968589d8	2555
Kojto	90:cb3d968589d8	2556	/! @brief Set the BRR field to a new value. /
Kojto	90:cb3d968589d8	2557	#define BW_SDHC_IRQSTAT_BRR(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BRR) = (v))
Kojto	90:cb3d968589d8	2558	/@}/
Kojto	90:cb3d968589d8	2559
Kojto	90:cb3d968589d8	2560	/*!
Kojto	90:cb3d968589d8	2561	* @name Register SDHC_IRQSTAT, field CINS[6] (W1C)
Kojto	90:cb3d968589d8	2562	*
Kojto	90:cb3d968589d8	2563	* This status bit is set if the Card Inserted bit in the Present State register
Kojto	90:cb3d968589d8	2564	* changes from 0 to 1. When the host driver writes this bit to 1 to clear this
Kojto	90:cb3d968589d8	2565	* status, the status of the Card Inserted in the Present State register must be
Kojto	90:cb3d968589d8	2566	* confirmed. Because the card state may possibly be changed when the host driver
Kojto	90:cb3d968589d8	2567	* clears this bit and the interrupt event may not be generated. When this bit
Kojto	90:cb3d968589d8	2568	* is cleared, it will be set again if a card is inserted. To leave it cleared,
Kojto	90:cb3d968589d8	2569	* clear the Card Inserted Status Enable bit in Interrupt Status Enable register.
Kojto	90:cb3d968589d8	2570	*
Kojto	90:cb3d968589d8	2571	* Values:
Kojto	90:cb3d968589d8	2572	* - 0 - Card state unstable or removed.
Kojto	90:cb3d968589d8	2573	* - 1 - Card inserted.
Kojto	90:cb3d968589d8	2574	*/
Kojto	90:cb3d968589d8	2575	/@{/
Kojto	90:cb3d968589d8	2576	#define BP_SDHC_IRQSTAT_CINS (6U) /!< Bit position for SDHC_IRQSTAT_CINS. /
Kojto	90:cb3d968589d8	2577	#define BM_SDHC_IRQSTAT_CINS (0x00000040U) /!< Bit mask for SDHC_IRQSTAT_CINS. /
Kojto	90:cb3d968589d8	2578	#define BS_SDHC_IRQSTAT_CINS (1U) /!< Bit field size in bits for SDHC_IRQSTAT_CINS. /
Kojto	90:cb3d968589d8	2579
Kojto	90:cb3d968589d8	2580	/! @brief Read current value of the SDHC_IRQSTAT_CINS field. /
Kojto	90:cb3d968589d8	2581	#define BR_SDHC_IRQSTAT_CINS(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CINS))
Kojto	90:cb3d968589d8	2582
Kojto	90:cb3d968589d8	2583	/! @brief Format value for bitfield SDHC_IRQSTAT_CINS. /
Kojto	90:cb3d968589d8	2584	#define BF_SDHC_IRQSTAT_CINS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CINS) & BM_SDHC_IRQSTAT_CINS)
Kojto	90:cb3d968589d8	2585
Kojto	90:cb3d968589d8	2586	/! @brief Set the CINS field to a new value. /
Kojto	90:cb3d968589d8	2587	#define BW_SDHC_IRQSTAT_CINS(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CINS) = (v))
Kojto	90:cb3d968589d8	2588	/@}/
Kojto	90:cb3d968589d8	2589
Kojto	90:cb3d968589d8	2590	/*!
Kojto	90:cb3d968589d8	2591	* @name Register SDHC_IRQSTAT, field CRM[7] (W1C)
Kojto	90:cb3d968589d8	2592	*
Kojto	90:cb3d968589d8	2593	* This status bit is set if the Card Inserted bit in the Present State register
Kojto	90:cb3d968589d8	2594	* changes from 1 to 0. When the host driver writes this bit to 1 to clear this
Kojto	90:cb3d968589d8	2595	* status, the status of the Card Inserted in the Present State register must be
Kojto	90:cb3d968589d8	2596	* confirmed. Because the card state may possibly be changed when the host driver
Kojto	90:cb3d968589d8	2597	* clears this bit and the interrupt event may not be generated. When this bit
Kojto	90:cb3d968589d8	2598	* is cleared, it will be set again if no card is inserted. To leave it cleared,
Kojto	90:cb3d968589d8	2599	* clear the Card Removal Status Enable bit in Interrupt Status Enable register.
Kojto	90:cb3d968589d8	2600	*
Kojto	90:cb3d968589d8	2601	* Values:
Kojto	90:cb3d968589d8	2602	* - 0 - Card state unstable or inserted.
Kojto	90:cb3d968589d8	2603	* - 1 - Card removed.
Kojto	90:cb3d968589d8	2604	*/
Kojto	90:cb3d968589d8	2605	/@{/
Kojto	90:cb3d968589d8	2606	#define BP_SDHC_IRQSTAT_CRM (7U) /!< Bit position for SDHC_IRQSTAT_CRM. /
Kojto	90:cb3d968589d8	2607	#define BM_SDHC_IRQSTAT_CRM (0x00000080U) /!< Bit mask for SDHC_IRQSTAT_CRM. /
Kojto	90:cb3d968589d8	2608	#define BS_SDHC_IRQSTAT_CRM (1U) /!< Bit field size in bits for SDHC_IRQSTAT_CRM. /
Kojto	90:cb3d968589d8	2609
Kojto	90:cb3d968589d8	2610	/! @brief Read current value of the SDHC_IRQSTAT_CRM field. /
Kojto	90:cb3d968589d8	2611	#define BR_SDHC_IRQSTAT_CRM(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CRM))
Kojto	90:cb3d968589d8	2612
Kojto	90:cb3d968589d8	2613	/! @brief Format value for bitfield SDHC_IRQSTAT_CRM. /
Kojto	90:cb3d968589d8	2614	#define BF_SDHC_IRQSTAT_CRM(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CRM) & BM_SDHC_IRQSTAT_CRM)
Kojto	90:cb3d968589d8	2615
Kojto	90:cb3d968589d8	2616	/! @brief Set the CRM field to a new value. /
Kojto	90:cb3d968589d8	2617	#define BW_SDHC_IRQSTAT_CRM(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CRM) = (v))
Kojto	90:cb3d968589d8	2618	/@}/
Kojto	90:cb3d968589d8	2619
Kojto	90:cb3d968589d8	2620	/*!
Kojto	90:cb3d968589d8	2621	* @name Register SDHC_IRQSTAT, field CINT[8] (W1C)
Kojto	90:cb3d968589d8	2622	*
Kojto	90:cb3d968589d8	2623	* This status bit is set when an interrupt signal is detected from the external
Kojto	90:cb3d968589d8	2624	* card. In 1-bit mode, the SDHC will detect the Card Interrupt without the SD
Kojto	90:cb3d968589d8	2625	* Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled
Kojto	90:cb3d968589d8	2626	* during the interrupt cycle, so the interrupt from card can only be sampled
Kojto	90:cb3d968589d8	2627	* during interrupt cycle, introducing some delay between the interrupt signal from
Kojto	90:cb3d968589d8	2628	* the SDIO card and the interrupt to the host system. Writing this bit to 1 can
Kojto	90:cb3d968589d8	2629	* clear this bit, but as the interrupt factor from the SDIO card does not clear,
Kojto	90:cb3d968589d8	2630	* this bit is set again. To clear this bit, it is required to reset the interrupt
Kojto	90:cb3d968589d8	2631	* factor from the external card followed by a writing 1 to this bit. When this
Kojto	90:cb3d968589d8	2632	* status has been set, and the host driver needs to service this interrupt, the
Kojto	90:cb3d968589d8	2633	* Card Interrupt Signal Enable in the Interrupt Signal Enable register should be
Kojto	90:cb3d968589d8	2634	* 0 to stop driving the interrupt signal to the host system. After completion
Kojto	90:cb3d968589d8	2635	* of the card interrupt service (it must reset the interrupt factors in the SDIO
Kojto	90:cb3d968589d8	2636	* card and the interrupt signal may not be asserted), write 1 to clear this bit,
Kojto	90:cb3d968589d8	2637	* set the Card Interrupt Signal Enable to 1, and start sampling the interrupt
Kojto	90:cb3d968589d8	2638	* signal again.
Kojto	90:cb3d968589d8	2639	*
Kojto	90:cb3d968589d8	2640	* Values:
Kojto	90:cb3d968589d8	2641	* - 0 - No Card Interrupt.
Kojto	90:cb3d968589d8	2642	* - 1 - Generate Card Interrupt.
Kojto	90:cb3d968589d8	2643	*/
Kojto	90:cb3d968589d8	2644	/@{/
Kojto	90:cb3d968589d8	2645	#define BP_SDHC_IRQSTAT_CINT (8U) /!< Bit position for SDHC_IRQSTAT_CINT. /
Kojto	90:cb3d968589d8	2646	#define BM_SDHC_IRQSTAT_CINT (0x00000100U) /!< Bit mask for SDHC_IRQSTAT_CINT. /
Kojto	90:cb3d968589d8	2647	#define BS_SDHC_IRQSTAT_CINT (1U) /!< Bit field size in bits for SDHC_IRQSTAT_CINT. /
Kojto	90:cb3d968589d8	2648
Kojto	90:cb3d968589d8	2649	/! @brief Read current value of the SDHC_IRQSTAT_CINT field. /
Kojto	90:cb3d968589d8	2650	#define BR_SDHC_IRQSTAT_CINT(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CINT))
Kojto	90:cb3d968589d8	2651
Kojto	90:cb3d968589d8	2652	/! @brief Format value for bitfield SDHC_IRQSTAT_CINT. /
Kojto	90:cb3d968589d8	2653	#define BF_SDHC_IRQSTAT_CINT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CINT) & BM_SDHC_IRQSTAT_CINT)
Kojto	90:cb3d968589d8	2654
Kojto	90:cb3d968589d8	2655	/! @brief Set the CINT field to a new value. /
Kojto	90:cb3d968589d8	2656	#define BW_SDHC_IRQSTAT_CINT(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CINT) = (v))
Kojto	90:cb3d968589d8	2657	/@}/
Kojto	90:cb3d968589d8	2658
Kojto	90:cb3d968589d8	2659	/*!
Kojto	90:cb3d968589d8	2660	* @name Register SDHC_IRQSTAT, field CTOE[16] (W1C)
Kojto	90:cb3d968589d8	2661	*
Kojto	90:cb3d968589d8	2662	* Occurs only if no response is returned within 64 SDCLK cycles from the end
Kojto	90:cb3d968589d8	2663	* bit of the command. If the SDHC detects a CMD line conflict, in which case a
Kojto	90:cb3d968589d8	2664	* Command CRC Error shall also be set, this bit shall be set without waiting for 64
Kojto	90:cb3d968589d8	2665	* SDCLK cycles. This is because the command will be aborted by the SDHC.
Kojto	90:cb3d968589d8	2666	*
Kojto	90:cb3d968589d8	2667	* Values:
Kojto	90:cb3d968589d8	2668	* - 0 - No error.
Kojto	90:cb3d968589d8	2669	* - 1 - Time out.
Kojto	90:cb3d968589d8	2670	*/
Kojto	90:cb3d968589d8	2671	/@{/
Kojto	90:cb3d968589d8	2672	#define BP_SDHC_IRQSTAT_CTOE (16U) /!< Bit position for SDHC_IRQSTAT_CTOE. /
Kojto	90:cb3d968589d8	2673	#define BM_SDHC_IRQSTAT_CTOE (0x00010000U) /!< Bit mask for SDHC_IRQSTAT_CTOE. /
Kojto	90:cb3d968589d8	2674	#define BS_SDHC_IRQSTAT_CTOE (1U) /!< Bit field size in bits for SDHC_IRQSTAT_CTOE. /
Kojto	90:cb3d968589d8	2675
Kojto	90:cb3d968589d8	2676	/! @brief Read current value of the SDHC_IRQSTAT_CTOE field. /
Kojto	90:cb3d968589d8	2677	#define BR_SDHC_IRQSTAT_CTOE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CTOE))
Kojto	90:cb3d968589d8	2678
Kojto	90:cb3d968589d8	2679	/! @brief Format value for bitfield SDHC_IRQSTAT_CTOE. /
Kojto	90:cb3d968589d8	2680	#define BF_SDHC_IRQSTAT_CTOE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CTOE) & BM_SDHC_IRQSTAT_CTOE)
Kojto	90:cb3d968589d8	2681
Kojto	90:cb3d968589d8	2682	/! @brief Set the CTOE field to a new value. /
Kojto	90:cb3d968589d8	2683	#define BW_SDHC_IRQSTAT_CTOE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CTOE) = (v))
Kojto	90:cb3d968589d8	2684	/@}/
Kojto	90:cb3d968589d8	2685
Kojto	90:cb3d968589d8	2686	/*!
Kojto	90:cb3d968589d8	2687	* @name Register SDHC_IRQSTAT, field CCE[17] (W1C)
Kojto	90:cb3d968589d8	2688	*
Kojto	90:cb3d968589d8	2689	* Command CRC Error is generated in two cases. If a response is returned and
Kojto	90:cb3d968589d8	2690	* the Command Timeout Error is set to 0, indicating no time-out, this bit is set
Kojto	90:cb3d968589d8	2691	* when detecting a CRC error in the command response. The SDHC detects a CMD line
Kojto	90:cb3d968589d8	2692	* conflict by monitoring the CMD line when a command is issued. If the SDHC
Kojto	90:cb3d968589d8	2693	* drives the CMD line to 1, but detects 0 on the CMD line at the next SDCLK edge,
Kojto	90:cb3d968589d8	2694	* then the SDHC shall abort the command (Stop driving CMD line) and set this bit
Kojto	90:cb3d968589d8	2695	* to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line
Kojto	90:cb3d968589d8	2696	* conflict.
Kojto	90:cb3d968589d8	2697	*
Kojto	90:cb3d968589d8	2698	* Values:
Kojto	90:cb3d968589d8	2699	* - 0 - No error.
Kojto	90:cb3d968589d8	2700	* - 1 - CRC Error generated.
Kojto	90:cb3d968589d8	2701	*/
Kojto	90:cb3d968589d8	2702	/@{/
Kojto	90:cb3d968589d8	2703	#define BP_SDHC_IRQSTAT_CCE (17U) /!< Bit position for SDHC_IRQSTAT_CCE. /
Kojto	90:cb3d968589d8	2704	#define BM_SDHC_IRQSTAT_CCE (0x00020000U) /!< Bit mask for SDHC_IRQSTAT_CCE. /
Kojto	90:cb3d968589d8	2705	#define BS_SDHC_IRQSTAT_CCE (1U) /!< Bit field size in bits for SDHC_IRQSTAT_CCE. /
Kojto	90:cb3d968589d8	2706
Kojto	90:cb3d968589d8	2707	/! @brief Read current value of the SDHC_IRQSTAT_CCE field. /
Kojto	90:cb3d968589d8	2708	#define BR_SDHC_IRQSTAT_CCE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CCE))
Kojto	90:cb3d968589d8	2709
Kojto	90:cb3d968589d8	2710	/! @brief Format value for bitfield SDHC_IRQSTAT_CCE. /
Kojto	90:cb3d968589d8	2711	#define BF_SDHC_IRQSTAT_CCE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CCE) & BM_SDHC_IRQSTAT_CCE)
Kojto	90:cb3d968589d8	2712
Kojto	90:cb3d968589d8	2713	/! @brief Set the CCE field to a new value. /
Kojto	90:cb3d968589d8	2714	#define BW_SDHC_IRQSTAT_CCE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CCE) = (v))
Kojto	90:cb3d968589d8	2715	/@}/
Kojto	90:cb3d968589d8	2716
Kojto	90:cb3d968589d8	2717	/*!
Kojto	90:cb3d968589d8	2718	* @name Register SDHC_IRQSTAT, field CEBE[18] (W1C)
Kojto	90:cb3d968589d8	2719	*
Kojto	90:cb3d968589d8	2720	* Occurs when detecting that the end bit of a command response is 0.
Kojto	90:cb3d968589d8	2721	*
Kojto	90:cb3d968589d8	2722	* Values:
Kojto	90:cb3d968589d8	2723	* - 0 - No error.
Kojto	90:cb3d968589d8	2724	* - 1 - End Bit Error generated.
Kojto	90:cb3d968589d8	2725	*/
Kojto	90:cb3d968589d8	2726	/@{/
Kojto	90:cb3d968589d8	2727	#define BP_SDHC_IRQSTAT_CEBE (18U) /!< Bit position for SDHC_IRQSTAT_CEBE. /
Kojto	90:cb3d968589d8	2728	#define BM_SDHC_IRQSTAT_CEBE (0x00040000U) /!< Bit mask for SDHC_IRQSTAT_CEBE. /
Kojto	90:cb3d968589d8	2729	#define BS_SDHC_IRQSTAT_CEBE (1U) /!< Bit field size in bits for SDHC_IRQSTAT_CEBE. /
Kojto	90:cb3d968589d8	2730
Kojto	90:cb3d968589d8	2731	/! @brief Read current value of the SDHC_IRQSTAT_CEBE field. /
Kojto	90:cb3d968589d8	2732	#define BR_SDHC_IRQSTAT_CEBE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CEBE))
Kojto	90:cb3d968589d8	2733
Kojto	90:cb3d968589d8	2734	/! @brief Format value for bitfield SDHC_IRQSTAT_CEBE. /
Kojto	90:cb3d968589d8	2735	#define BF_SDHC_IRQSTAT_CEBE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CEBE) & BM_SDHC_IRQSTAT_CEBE)
Kojto	90:cb3d968589d8	2736
Kojto	90:cb3d968589d8	2737	/! @brief Set the CEBE field to a new value. /
Kojto	90:cb3d968589d8	2738	#define BW_SDHC_IRQSTAT_CEBE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CEBE) = (v))
Kojto	90:cb3d968589d8	2739	/@}/
Kojto	90:cb3d968589d8	2740
Kojto	90:cb3d968589d8	2741	/*!
Kojto	90:cb3d968589d8	2742	* @name Register SDHC_IRQSTAT, field CIE[19] (W1C)
Kojto	90:cb3d968589d8	2743	*
Kojto	90:cb3d968589d8	2744	* Occurs if a Command Index error occurs in the command response.
Kojto	90:cb3d968589d8	2745	*
Kojto	90:cb3d968589d8	2746	* Values:
Kojto	90:cb3d968589d8	2747	* - 0 - No error.
Kojto	90:cb3d968589d8	2748	* - 1 - Error.
Kojto	90:cb3d968589d8	2749	*/
Kojto	90:cb3d968589d8	2750	/@{/
Kojto	90:cb3d968589d8	2751	#define BP_SDHC_IRQSTAT_CIE (19U) /!< Bit position for SDHC_IRQSTAT_CIE. /
Kojto	90:cb3d968589d8	2752	#define BM_SDHC_IRQSTAT_CIE (0x00080000U) /!< Bit mask for SDHC_IRQSTAT_CIE. /
Kojto	90:cb3d968589d8	2753	#define BS_SDHC_IRQSTAT_CIE (1U) /!< Bit field size in bits for SDHC_IRQSTAT_CIE. /
Kojto	90:cb3d968589d8	2754
Kojto	90:cb3d968589d8	2755	/! @brief Read current value of the SDHC_IRQSTAT_CIE field. /
Kojto	90:cb3d968589d8	2756	#define BR_SDHC_IRQSTAT_CIE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CIE))
Kojto	90:cb3d968589d8	2757
Kojto	90:cb3d968589d8	2758	/! @brief Format value for bitfield SDHC_IRQSTAT_CIE. /
Kojto	90:cb3d968589d8	2759	#define BF_SDHC_IRQSTAT_CIE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CIE) & BM_SDHC_IRQSTAT_CIE)
Kojto	90:cb3d968589d8	2760
Kojto	90:cb3d968589d8	2761	/! @brief Set the CIE field to a new value. /
Kojto	90:cb3d968589d8	2762	#define BW_SDHC_IRQSTAT_CIE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CIE) = (v))
Kojto	90:cb3d968589d8	2763	/@}/
Kojto	90:cb3d968589d8	2764
Kojto	90:cb3d968589d8	2765	/*!
Kojto	90:cb3d968589d8	2766	* @name Register SDHC_IRQSTAT, field DTOE[20] (W1C)
Kojto	90:cb3d968589d8	2767	*
Kojto	90:cb3d968589d8	2768	* Occurs when detecting one of following time-out conditions. Busy time-out for
Kojto	90:cb3d968589d8	2769	* R1b,R5b type Busy time-out after Write CRC status Read Data time-out
Kojto	90:cb3d968589d8	2770	*
Kojto	90:cb3d968589d8	2771	* Values:
Kojto	90:cb3d968589d8	2772	* - 0 - No error.
Kojto	90:cb3d968589d8	2773	* - 1 - Time out.
Kojto	90:cb3d968589d8	2774	*/
Kojto	90:cb3d968589d8	2775	/@{/
Kojto	90:cb3d968589d8	2776	#define BP_SDHC_IRQSTAT_DTOE (20U) /!< Bit position for SDHC_IRQSTAT_DTOE. /
Kojto	90:cb3d968589d8	2777	#define BM_SDHC_IRQSTAT_DTOE (0x00100000U) /!< Bit mask for SDHC_IRQSTAT_DTOE. /
Kojto	90:cb3d968589d8	2778	#define BS_SDHC_IRQSTAT_DTOE (1U) /!< Bit field size in bits for SDHC_IRQSTAT_DTOE. /
Kojto	90:cb3d968589d8	2779
Kojto	90:cb3d968589d8	2780	/! @brief Read current value of the SDHC_IRQSTAT_DTOE field. /
Kojto	90:cb3d968589d8	2781	#define BR_SDHC_IRQSTAT_DTOE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DTOE))
Kojto	90:cb3d968589d8	2782
Kojto	90:cb3d968589d8	2783	/! @brief Format value for bitfield SDHC_IRQSTAT_DTOE. /
Kojto	90:cb3d968589d8	2784	#define BF_SDHC_IRQSTAT_DTOE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_DTOE) & BM_SDHC_IRQSTAT_DTOE)
Kojto	90:cb3d968589d8	2785
Kojto	90:cb3d968589d8	2786	/! @brief Set the DTOE field to a new value. /
Kojto	90:cb3d968589d8	2787	#define BW_SDHC_IRQSTAT_DTOE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DTOE) = (v))
Kojto	90:cb3d968589d8	2788	/@}/
Kojto	90:cb3d968589d8	2789
Kojto	90:cb3d968589d8	2790	/*!
Kojto	90:cb3d968589d8	2791	* @name Register SDHC_IRQSTAT, field DCE[21] (W1C)
Kojto	90:cb3d968589d8	2792	*
Kojto	90:cb3d968589d8	2793	* Occurs when detecting a CRC error when transferring read data, which uses the
Kojto	90:cb3d968589d8	2794	* DAT line, or when detecting the Write CRC status having a value other than
Kojto	90:cb3d968589d8	2795	* 010.
Kojto	90:cb3d968589d8	2796	*
Kojto	90:cb3d968589d8	2797	* Values:
Kojto	90:cb3d968589d8	2798	* - 0 - No error.
Kojto	90:cb3d968589d8	2799	* - 1 - Error.
Kojto	90:cb3d968589d8	2800	*/
Kojto	90:cb3d968589d8	2801	/@{/
Kojto	90:cb3d968589d8	2802	#define BP_SDHC_IRQSTAT_DCE (21U) /!< Bit position for SDHC_IRQSTAT_DCE. /
Kojto	90:cb3d968589d8	2803	#define BM_SDHC_IRQSTAT_DCE (0x00200000U) /!< Bit mask for SDHC_IRQSTAT_DCE. /
Kojto	90:cb3d968589d8	2804	#define BS_SDHC_IRQSTAT_DCE (1U) /!< Bit field size in bits for SDHC_IRQSTAT_DCE. /
Kojto	90:cb3d968589d8	2805
Kojto	90:cb3d968589d8	2806	/! @brief Read current value of the SDHC_IRQSTAT_DCE field. /
Kojto	90:cb3d968589d8	2807	#define BR_SDHC_IRQSTAT_DCE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DCE))
Kojto	90:cb3d968589d8	2808
Kojto	90:cb3d968589d8	2809	/! @brief Format value for bitfield SDHC_IRQSTAT_DCE. /
Kojto	90:cb3d968589d8	2810	#define BF_SDHC_IRQSTAT_DCE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_DCE) & BM_SDHC_IRQSTAT_DCE)
Kojto	90:cb3d968589d8	2811
Kojto	90:cb3d968589d8	2812	/! @brief Set the DCE field to a new value. /
Kojto	90:cb3d968589d8	2813	#define BW_SDHC_IRQSTAT_DCE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DCE) = (v))
Kojto	90:cb3d968589d8	2814	/@}/
Kojto	90:cb3d968589d8	2815
Kojto	90:cb3d968589d8	2816	/*!
Kojto	90:cb3d968589d8	2817	* @name Register SDHC_IRQSTAT, field DEBE[22] (W1C)
Kojto	90:cb3d968589d8	2818	*
Kojto	90:cb3d968589d8	2819	* Occurs either when detecting 0 at the end bit position of read data, which
Kojto	90:cb3d968589d8	2820	* uses the DAT line, or at the end bit position of the CRC.
Kojto	90:cb3d968589d8	2821	*
Kojto	90:cb3d968589d8	2822	* Values:
Kojto	90:cb3d968589d8	2823	* - 0 - No error.
Kojto	90:cb3d968589d8	2824	* - 1 - Error.
Kojto	90:cb3d968589d8	2825	*/
Kojto	90:cb3d968589d8	2826	/@{/
Kojto	90:cb3d968589d8	2827	#define BP_SDHC_IRQSTAT_DEBE (22U) /!< Bit position for SDHC_IRQSTAT_DEBE. /
Kojto	90:cb3d968589d8	2828	#define BM_SDHC_IRQSTAT_DEBE (0x00400000U) /!< Bit mask for SDHC_IRQSTAT_DEBE. /
Kojto	90:cb3d968589d8	2829	#define BS_SDHC_IRQSTAT_DEBE (1U) /!< Bit field size in bits for SDHC_IRQSTAT_DEBE. /
Kojto	90:cb3d968589d8	2830
Kojto	90:cb3d968589d8	2831	/! @brief Read current value of the SDHC_IRQSTAT_DEBE field. /
Kojto	90:cb3d968589d8	2832	#define BR_SDHC_IRQSTAT_DEBE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DEBE))
Kojto	90:cb3d968589d8	2833
Kojto	90:cb3d968589d8	2834	/! @brief Format value for bitfield SDHC_IRQSTAT_DEBE. /
Kojto	90:cb3d968589d8	2835	#define BF_SDHC_IRQSTAT_DEBE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_DEBE) & BM_SDHC_IRQSTAT_DEBE)
Kojto	90:cb3d968589d8	2836
Kojto	90:cb3d968589d8	2837	/! @brief Set the DEBE field to a new value. /
Kojto	90:cb3d968589d8	2838	#define BW_SDHC_IRQSTAT_DEBE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DEBE) = (v))
Kojto	90:cb3d968589d8	2839	/@}/
Kojto	90:cb3d968589d8	2840
Kojto	90:cb3d968589d8	2841	/*!
Kojto	90:cb3d968589d8	2842	* @name Register SDHC_IRQSTAT, field AC12E[24] (W1C)
Kojto	90:cb3d968589d8	2843	*
Kojto	90:cb3d968589d8	2844	* Occurs when detecting that one of the bits in the Auto CMD12 Error Status
Kojto	90:cb3d968589d8	2845	* register has changed from 0 to 1. This bit is set to 1, not only when the errors
Kojto	90:cb3d968589d8	2846	* in Auto CMD12 occur, but also when the Auto CMD12 is not executed due to the
Kojto	90:cb3d968589d8	2847	* previous command error.
Kojto	90:cb3d968589d8	2848	*
Kojto	90:cb3d968589d8	2849	* Values:
Kojto	90:cb3d968589d8	2850	* - 0 - No error.
Kojto	90:cb3d968589d8	2851	* - 1 - Error.
Kojto	90:cb3d968589d8	2852	*/
Kojto	90:cb3d968589d8	2853	/@{/
Kojto	90:cb3d968589d8	2854	#define BP_SDHC_IRQSTAT_AC12E (24U) /!< Bit position for SDHC_IRQSTAT_AC12E. /
Kojto	90:cb3d968589d8	2855	#define BM_SDHC_IRQSTAT_AC12E (0x01000000U) /!< Bit mask for SDHC_IRQSTAT_AC12E. /
Kojto	90:cb3d968589d8	2856	#define BS_SDHC_IRQSTAT_AC12E (1U) /!< Bit field size in bits for SDHC_IRQSTAT_AC12E. /
Kojto	90:cb3d968589d8	2857
Kojto	90:cb3d968589d8	2858	/! @brief Read current value of the SDHC_IRQSTAT_AC12E field. /
Kojto	90:cb3d968589d8	2859	#define BR_SDHC_IRQSTAT_AC12E(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_AC12E))
Kojto	90:cb3d968589d8	2860
Kojto	90:cb3d968589d8	2861	/! @brief Format value for bitfield SDHC_IRQSTAT_AC12E. /
Kojto	90:cb3d968589d8	2862	#define BF_SDHC_IRQSTAT_AC12E(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_AC12E) & BM_SDHC_IRQSTAT_AC12E)
Kojto	90:cb3d968589d8	2863
Kojto	90:cb3d968589d8	2864	/! @brief Set the AC12E field to a new value. /
Kojto	90:cb3d968589d8	2865	#define BW_SDHC_IRQSTAT_AC12E(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_AC12E) = (v))
Kojto	90:cb3d968589d8	2866	/@}/
Kojto	90:cb3d968589d8	2867
Kojto	90:cb3d968589d8	2868	/*!
Kojto	90:cb3d968589d8	2869	* @name Register SDHC_IRQSTAT, field DMAE[28] (W1C)
Kojto	90:cb3d968589d8	2870	*
Kojto	90:cb3d968589d8	2871	* Occurs when an Internal DMA transfer has failed. This bit is set to 1, when
Kojto	90:cb3d968589d8	2872	* some error occurs in the data transfer. This error can be caused by either
Kojto	90:cb3d968589d8	2873	* Simple DMA or ADMA, depending on which DMA is in use. The value in DMA System
Kojto	90:cb3d968589d8	2874	* Address register is the next fetch address where the error occurs. Because any
Kojto	90:cb3d968589d8	2875	* error corrupts the whole data block, the host driver shall restart the transfer
Kojto	90:cb3d968589d8	2876	* from the corrupted block boundary. The address of the block boundary can be
Kojto	90:cb3d968589d8	2877	* calculated either from the current DSADDR value or from the remaining number of
Kojto	90:cb3d968589d8	2878	* blocks and the block size.
Kojto	90:cb3d968589d8	2879	*
Kojto	90:cb3d968589d8	2880	* Values:
Kojto	90:cb3d968589d8	2881	* - 0 - No error.
Kojto	90:cb3d968589d8	2882	* - 1 - Error.
Kojto	90:cb3d968589d8	2883	*/
Kojto	90:cb3d968589d8	2884	/@{/
Kojto	90:cb3d968589d8	2885	#define BP_SDHC_IRQSTAT_DMAE (28U) /!< Bit position for SDHC_IRQSTAT_DMAE. /
Kojto	90:cb3d968589d8	2886	#define BM_SDHC_IRQSTAT_DMAE (0x10000000U) /!< Bit mask for SDHC_IRQSTAT_DMAE. /
Kojto	90:cb3d968589d8	2887	#define BS_SDHC_IRQSTAT_DMAE (1U) /!< Bit field size in bits for SDHC_IRQSTAT_DMAE. /
Kojto	90:cb3d968589d8	2888
Kojto	90:cb3d968589d8	2889	/! @brief Read current value of the SDHC_IRQSTAT_DMAE field. /
Kojto	90:cb3d968589d8	2890	#define BR_SDHC_IRQSTAT_DMAE(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DMAE))
Kojto	90:cb3d968589d8	2891
Kojto	90:cb3d968589d8	2892	/! @brief Format value for bitfield SDHC_IRQSTAT_DMAE. /
Kojto	90:cb3d968589d8	2893	#define BF_SDHC_IRQSTAT_DMAE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_DMAE) & BM_SDHC_IRQSTAT_DMAE)
Kojto	90:cb3d968589d8	2894
Kojto	90:cb3d968589d8	2895	/! @brief Set the DMAE field to a new value. /
Kojto	90:cb3d968589d8	2896	#define BW_SDHC_IRQSTAT_DMAE(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DMAE) = (v))
Kojto	90:cb3d968589d8	2897	/@}/
Kojto	90:cb3d968589d8	2898
Kojto	90:cb3d968589d8	2899	/*******************************************************************************
Kojto	90:cb3d968589d8	2900	* HW_SDHC_IRQSTATEN - Interrupt Status Enable register
Kojto	90:cb3d968589d8	2901	******************************************************************************/
Kojto	90:cb3d968589d8	2902
Kojto	90:cb3d968589d8	2903	/*!
Kojto	90:cb3d968589d8	2904	* @brief HW_SDHC_IRQSTATEN - Interrupt Status Enable register (RW)
Kojto	90:cb3d968589d8	2905	*
Kojto	90:cb3d968589d8	2906	* Reset value: 0x117F013FU
Kojto	90:cb3d968589d8	2907	*
Kojto	90:cb3d968589d8	2908	* Setting the bits in this register to 1 enables the corresponding interrupt
Kojto	90:cb3d968589d8	2909	* status to be set by the specified event. If any bit is cleared, the
Kojto	90:cb3d968589d8	2910	* corresponding interrupt status bit is also cleared, that is, when the bit in this register
Kojto	90:cb3d968589d8	2911	* is cleared, the corresponding bit in interrupt status register is always 0.
Kojto	90:cb3d968589d8	2912	* Depending on PROCTL[IABG] bit setting, SDHC may be programmed to sample the
Kojto	90:cb3d968589d8	2913	* card interrupt signal during the interrupt period and hold its value in the
Kojto	90:cb3d968589d8	2914	* flip-flop. There will be some delays on the card interrupt, asserted from the card,
Kojto	90:cb3d968589d8	2915	* to the time the host system is informed. To detect a CMD line conflict, the
Kojto	90:cb3d968589d8	2916	* host driver must set both IRQSTATEN[CTOESEN] and IRQSTATEN[CCESEN] to 1.
Kojto	90:cb3d968589d8	2917	*/
Kojto	90:cb3d968589d8	2918	typedef union _hw_sdhc_irqstaten
Kojto	90:cb3d968589d8	2919	{
Kojto	90:cb3d968589d8	2920	uint32_t U;
Kojto	90:cb3d968589d8	2921	struct _hw_sdhc_irqstaten_bitfields
Kojto	90:cb3d968589d8	2922	{
Kojto	90:cb3d968589d8	2923	uint32_t CCSEN : 1; /!< [0] Command Complete Status Enable /
Kojto	90:cb3d968589d8	2924	uint32_t TCSEN : 1; /!< [1] Transfer Complete Status Enable /
Kojto	90:cb3d968589d8	2925	uint32_t BGESEN : 1; /!< [2] Block Gap Event Status Enable /
Kojto	90:cb3d968589d8	2926	uint32_t DINTSEN : 1; /!< [3] DMA Interrupt Status Enable /
Kojto	90:cb3d968589d8	2927	uint32_t BWRSEN : 1; /!< [4] Buffer Write Ready Status Enable /
Kojto	90:cb3d968589d8	2928	uint32_t BRRSEN : 1; /!< [5] Buffer Read Ready Status Enable /
Kojto	90:cb3d968589d8	2929	uint32_t CINSEN : 1; /!< [6] Card Insertion Status Enable /
Kojto	90:cb3d968589d8	2930	uint32_t CRMSEN : 1; /!< [7] Card Removal Status Enable /
Kojto	90:cb3d968589d8	2931	uint32_t CINTSEN : 1; /!< [8] Card Interrupt Status Enable /
Kojto	90:cb3d968589d8	2932	uint32_t RESERVED0 : 7; /!< [15:9] /
Kojto	90:cb3d968589d8	2933	uint32_t CTOESEN : 1; /!< [16] Command Timeout Error Status Enable /
Kojto	90:cb3d968589d8	2934	uint32_t CCESEN : 1; /!< [17] Command CRC Error Status Enable /
Kojto	90:cb3d968589d8	2935	uint32_t CEBESEN : 1; /!< [18] Command End Bit Error Status Enable /
Kojto	90:cb3d968589d8	2936	uint32_t CIESEN : 1; /!< [19] Command Index Error Status Enable /
Kojto	90:cb3d968589d8	2937	uint32_t DTOESEN : 1; /!< [20] Data Timeout Error Status Enable /
Kojto	90:cb3d968589d8	2938	uint32_t DCESEN : 1; /!< [21] Data CRC Error Status Enable /
Kojto	90:cb3d968589d8	2939	uint32_t DEBESEN : 1; /!< [22] Data End Bit Error Status Enable /
Kojto	90:cb3d968589d8	2940	uint32_t RESERVED1 : 1; /!< [23] /
Kojto	90:cb3d968589d8	2941	uint32_t AC12ESEN : 1; /!< [24] Auto CMD12 Error Status Enable /
Kojto	90:cb3d968589d8	2942	uint32_t RESERVED2 : 3; /!< [27:25] /
Kojto	90:cb3d968589d8	2943	uint32_t DMAESEN : 1; /!< [28] DMA Error Status Enable /
Kojto	90:cb3d968589d8	2944	uint32_t RESERVED3 : 3; /!< [31:29] /
Kojto	90:cb3d968589d8	2945	} B;
Kojto	90:cb3d968589d8	2946	} hw_sdhc_irqstaten_t;
Kojto	90:cb3d968589d8	2947
Kojto	90:cb3d968589d8	2948	/*!
Kojto	90:cb3d968589d8	2949	* @name Constants and macros for entire SDHC_IRQSTATEN register
Kojto	90:cb3d968589d8	2950	*/
Kojto	90:cb3d968589d8	2951	/@{/
Kojto	90:cb3d968589d8	2952	#define HW_SDHC_IRQSTATEN_ADDR(x) ((x) + 0x34U)
Kojto	90:cb3d968589d8	2953
Kojto	90:cb3d968589d8	2954	#define HW_SDHC_IRQSTATEN(x) ((__IO hw_sdhc_irqstaten_t ) HW_SDHC_IRQSTATEN_ADDR(x))
Kojto	90:cb3d968589d8	2955	#define HW_SDHC_IRQSTATEN_RD(x) (HW_SDHC_IRQSTATEN(x).U)
Kojto	90:cb3d968589d8	2956	#define HW_SDHC_IRQSTATEN_WR(x, v) (HW_SDHC_IRQSTATEN(x).U = (v))
Kojto	90:cb3d968589d8	2957	#define HW_SDHC_IRQSTATEN_SET(x, v) (HW_SDHC_IRQSTATEN_WR(x, HW_SDHC_IRQSTATEN_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2958	#define HW_SDHC_IRQSTATEN_CLR(x, v) (HW_SDHC_IRQSTATEN_WR(x, HW_SDHC_IRQSTATEN_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2959	#define HW_SDHC_IRQSTATEN_TOG(x, v) (HW_SDHC_IRQSTATEN_WR(x, HW_SDHC_IRQSTATEN_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2960	/@}/
Kojto	90:cb3d968589d8	2961
Kojto	90:cb3d968589d8	2962	/*
Kojto	90:cb3d968589d8	2963	* Constants & macros for individual SDHC_IRQSTATEN bitfields
Kojto	90:cb3d968589d8	2964	*/
Kojto	90:cb3d968589d8	2965
Kojto	90:cb3d968589d8	2966	/*!
Kojto	90:cb3d968589d8	2967	* @name Register SDHC_IRQSTATEN, field CCSEN[0] (RW)
Kojto	90:cb3d968589d8	2968	*
Kojto	90:cb3d968589d8	2969	* Values:
Kojto	90:cb3d968589d8	2970	* - 0 - Masked
Kojto	90:cb3d968589d8	2971	* - 1 - Enabled
Kojto	90:cb3d968589d8	2972	*/
Kojto	90:cb3d968589d8	2973	/@{/
Kojto	90:cb3d968589d8	2974	#define BP_SDHC_IRQSTATEN_CCSEN (0U) /!< Bit position for SDHC_IRQSTATEN_CCSEN. /
Kojto	90:cb3d968589d8	2975	#define BM_SDHC_IRQSTATEN_CCSEN (0x00000001U) /!< Bit mask for SDHC_IRQSTATEN_CCSEN. /
Kojto	90:cb3d968589d8	2976	#define BS_SDHC_IRQSTATEN_CCSEN (1U) /!< Bit field size in bits for SDHC_IRQSTATEN_CCSEN. /
Kojto	90:cb3d968589d8	2977
Kojto	90:cb3d968589d8	2978	/! @brief Read current value of the SDHC_IRQSTATEN_CCSEN field. /
Kojto	90:cb3d968589d8	2979	#define BR_SDHC_IRQSTATEN_CCSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CCSEN))
Kojto	90:cb3d968589d8	2980
Kojto	90:cb3d968589d8	2981	/! @brief Format value for bitfield SDHC_IRQSTATEN_CCSEN. /
Kojto	90:cb3d968589d8	2982	#define BF_SDHC_IRQSTATEN_CCSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CCSEN) & BM_SDHC_IRQSTATEN_CCSEN)
Kojto	90:cb3d968589d8	2983
Kojto	90:cb3d968589d8	2984	/! @brief Set the CCSEN field to a new value. /
Kojto	90:cb3d968589d8	2985	#define BW_SDHC_IRQSTATEN_CCSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CCSEN) = (v))
Kojto	90:cb3d968589d8	2986	/@}/
Kojto	90:cb3d968589d8	2987
Kojto	90:cb3d968589d8	2988	/*!
Kojto	90:cb3d968589d8	2989	* @name Register SDHC_IRQSTATEN, field TCSEN[1] (RW)
Kojto	90:cb3d968589d8	2990	*
Kojto	90:cb3d968589d8	2991	* Values:
Kojto	90:cb3d968589d8	2992	* - 0 - Masked
Kojto	90:cb3d968589d8	2993	* - 1 - Enabled
Kojto	90:cb3d968589d8	2994	*/
Kojto	90:cb3d968589d8	2995	/@{/
Kojto	90:cb3d968589d8	2996	#define BP_SDHC_IRQSTATEN_TCSEN (1U) /!< Bit position for SDHC_IRQSTATEN_TCSEN. /
Kojto	90:cb3d968589d8	2997	#define BM_SDHC_IRQSTATEN_TCSEN (0x00000002U) /!< Bit mask for SDHC_IRQSTATEN_TCSEN. /
Kojto	90:cb3d968589d8	2998	#define BS_SDHC_IRQSTATEN_TCSEN (1U) /!< Bit field size in bits for SDHC_IRQSTATEN_TCSEN. /
Kojto	90:cb3d968589d8	2999
Kojto	90:cb3d968589d8	3000	/! @brief Read current value of the SDHC_IRQSTATEN_TCSEN field. /
Kojto	90:cb3d968589d8	3001	#define BR_SDHC_IRQSTATEN_TCSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_TCSEN))
Kojto	90:cb3d968589d8	3002
Kojto	90:cb3d968589d8	3003	/! @brief Format value for bitfield SDHC_IRQSTATEN_TCSEN. /
Kojto	90:cb3d968589d8	3004	#define BF_SDHC_IRQSTATEN_TCSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_TCSEN) & BM_SDHC_IRQSTATEN_TCSEN)
Kojto	90:cb3d968589d8	3005
Kojto	90:cb3d968589d8	3006	/! @brief Set the TCSEN field to a new value. /
Kojto	90:cb3d968589d8	3007	#define BW_SDHC_IRQSTATEN_TCSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_TCSEN) = (v))
Kojto	90:cb3d968589d8	3008	/@}/
Kojto	90:cb3d968589d8	3009
Kojto	90:cb3d968589d8	3010	/*!
Kojto	90:cb3d968589d8	3011	* @name Register SDHC_IRQSTATEN, field BGESEN[2] (RW)
Kojto	90:cb3d968589d8	3012	*
Kojto	90:cb3d968589d8	3013	* Values:
Kojto	90:cb3d968589d8	3014	* - 0 - Masked
Kojto	90:cb3d968589d8	3015	* - 1 - Enabled
Kojto	90:cb3d968589d8	3016	*/
Kojto	90:cb3d968589d8	3017	/@{/
Kojto	90:cb3d968589d8	3018	#define BP_SDHC_IRQSTATEN_BGESEN (2U) /!< Bit position for SDHC_IRQSTATEN_BGESEN. /
Kojto	90:cb3d968589d8	3019	#define BM_SDHC_IRQSTATEN_BGESEN (0x00000004U) /!< Bit mask for SDHC_IRQSTATEN_BGESEN. /
Kojto	90:cb3d968589d8	3020	#define BS_SDHC_IRQSTATEN_BGESEN (1U) /!< Bit field size in bits for SDHC_IRQSTATEN_BGESEN. /
Kojto	90:cb3d968589d8	3021
Kojto	90:cb3d968589d8	3022	/! @brief Read current value of the SDHC_IRQSTATEN_BGESEN field. /
Kojto	90:cb3d968589d8	3023	#define BR_SDHC_IRQSTATEN_BGESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BGESEN))
Kojto	90:cb3d968589d8	3024
Kojto	90:cb3d968589d8	3025	/! @brief Format value for bitfield SDHC_IRQSTATEN_BGESEN. /
Kojto	90:cb3d968589d8	3026	#define BF_SDHC_IRQSTATEN_BGESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_BGESEN) & BM_SDHC_IRQSTATEN_BGESEN)
Kojto	90:cb3d968589d8	3027
Kojto	90:cb3d968589d8	3028	/! @brief Set the BGESEN field to a new value. /
Kojto	90:cb3d968589d8	3029	#define BW_SDHC_IRQSTATEN_BGESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BGESEN) = (v))
Kojto	90:cb3d968589d8	3030	/@}/
Kojto	90:cb3d968589d8	3031
Kojto	90:cb3d968589d8	3032	/*!
Kojto	90:cb3d968589d8	3033	* @name Register SDHC_IRQSTATEN, field DINTSEN[3] (RW)
Kojto	90:cb3d968589d8	3034	*
Kojto	90:cb3d968589d8	3035	* Values:
Kojto	90:cb3d968589d8	3036	* - 0 - Masked
Kojto	90:cb3d968589d8	3037	* - 1 - Enabled
Kojto	90:cb3d968589d8	3038	*/
Kojto	90:cb3d968589d8	3039	/@{/
Kojto	90:cb3d968589d8	3040	#define BP_SDHC_IRQSTATEN_DINTSEN (3U) /!< Bit position for SDHC_IRQSTATEN_DINTSEN. /
Kojto	90:cb3d968589d8	3041	#define BM_SDHC_IRQSTATEN_DINTSEN (0x00000008U) /!< Bit mask for SDHC_IRQSTATEN_DINTSEN. /
Kojto	90:cb3d968589d8	3042	#define BS_SDHC_IRQSTATEN_DINTSEN (1U) /!< Bit field size in bits for SDHC_IRQSTATEN_DINTSEN. /
Kojto	90:cb3d968589d8	3043
Kojto	90:cb3d968589d8	3044	/! @brief Read current value of the SDHC_IRQSTATEN_DINTSEN field. /
Kojto	90:cb3d968589d8	3045	#define BR_SDHC_IRQSTATEN_DINTSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DINTSEN))
Kojto	90:cb3d968589d8	3046
Kojto	90:cb3d968589d8	3047	/! @brief Format value for bitfield SDHC_IRQSTATEN_DINTSEN. /
Kojto	90:cb3d968589d8	3048	#define BF_SDHC_IRQSTATEN_DINTSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_DINTSEN) & BM_SDHC_IRQSTATEN_DINTSEN)
Kojto	90:cb3d968589d8	3049
Kojto	90:cb3d968589d8	3050	/! @brief Set the DINTSEN field to a new value. /
Kojto	90:cb3d968589d8	3051	#define BW_SDHC_IRQSTATEN_DINTSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DINTSEN) = (v))
Kojto	90:cb3d968589d8	3052	/@}/
Kojto	90:cb3d968589d8	3053
Kojto	90:cb3d968589d8	3054	/*!
Kojto	90:cb3d968589d8	3055	* @name Register SDHC_IRQSTATEN, field BWRSEN[4] (RW)
Kojto	90:cb3d968589d8	3056	*
Kojto	90:cb3d968589d8	3057	* Values:
Kojto	90:cb3d968589d8	3058	* - 0 - Masked
Kojto	90:cb3d968589d8	3059	* - 1 - Enabled
Kojto	90:cb3d968589d8	3060	*/
Kojto	90:cb3d968589d8	3061	/@{/
Kojto	90:cb3d968589d8	3062	#define BP_SDHC_IRQSTATEN_BWRSEN (4U) /!< Bit position for SDHC_IRQSTATEN_BWRSEN. /
Kojto	90:cb3d968589d8	3063	#define BM_SDHC_IRQSTATEN_BWRSEN (0x00000010U) /!< Bit mask for SDHC_IRQSTATEN_BWRSEN. /
Kojto	90:cb3d968589d8	3064	#define BS_SDHC_IRQSTATEN_BWRSEN (1U) /!< Bit field size in bits for SDHC_IRQSTATEN_BWRSEN. /
Kojto	90:cb3d968589d8	3065
Kojto	90:cb3d968589d8	3066	/! @brief Read current value of the SDHC_IRQSTATEN_BWRSEN field. /
Kojto	90:cb3d968589d8	3067	#define BR_SDHC_IRQSTATEN_BWRSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BWRSEN))
Kojto	90:cb3d968589d8	3068
Kojto	90:cb3d968589d8	3069	/! @brief Format value for bitfield SDHC_IRQSTATEN_BWRSEN. /
Kojto	90:cb3d968589d8	3070	#define BF_SDHC_IRQSTATEN_BWRSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_BWRSEN) & BM_SDHC_IRQSTATEN_BWRSEN)
Kojto	90:cb3d968589d8	3071
Kojto	90:cb3d968589d8	3072	/! @brief Set the BWRSEN field to a new value. /
Kojto	90:cb3d968589d8	3073	#define BW_SDHC_IRQSTATEN_BWRSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BWRSEN) = (v))
Kojto	90:cb3d968589d8	3074	/@}/
Kojto	90:cb3d968589d8	3075
Kojto	90:cb3d968589d8	3076	/*!
Kojto	90:cb3d968589d8	3077	* @name Register SDHC_IRQSTATEN, field BRRSEN[5] (RW)
Kojto	90:cb3d968589d8	3078	*
Kojto	90:cb3d968589d8	3079	* Values:
Kojto	90:cb3d968589d8	3080	* - 0 - Masked
Kojto	90:cb3d968589d8	3081	* - 1 - Enabled
Kojto	90:cb3d968589d8	3082	*/
Kojto	90:cb3d968589d8	3083	/@{/
Kojto	90:cb3d968589d8	3084	#define BP_SDHC_IRQSTATEN_BRRSEN (5U) /!< Bit position for SDHC_IRQSTATEN_BRRSEN. /
Kojto	90:cb3d968589d8	3085	#define BM_SDHC_IRQSTATEN_BRRSEN (0x00000020U) /!< Bit mask for SDHC_IRQSTATEN_BRRSEN. /
Kojto	90:cb3d968589d8	3086	#define BS_SDHC_IRQSTATEN_BRRSEN (1U) /!< Bit field size in bits for SDHC_IRQSTATEN_BRRSEN. /
Kojto	90:cb3d968589d8	3087
Kojto	90:cb3d968589d8	3088	/! @brief Read current value of the SDHC_IRQSTATEN_BRRSEN field. /
Kojto	90:cb3d968589d8	3089	#define BR_SDHC_IRQSTATEN_BRRSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BRRSEN))
Kojto	90:cb3d968589d8	3090
Kojto	90:cb3d968589d8	3091	/! @brief Format value for bitfield SDHC_IRQSTATEN_BRRSEN. /
Kojto	90:cb3d968589d8	3092	#define BF_SDHC_IRQSTATEN_BRRSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_BRRSEN) & BM_SDHC_IRQSTATEN_BRRSEN)
Kojto	90:cb3d968589d8	3093
Kojto	90:cb3d968589d8	3094	/! @brief Set the BRRSEN field to a new value. /
Kojto	90:cb3d968589d8	3095	#define BW_SDHC_IRQSTATEN_BRRSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BRRSEN) = (v))
Kojto	90:cb3d968589d8	3096	/@}/
Kojto	90:cb3d968589d8	3097
Kojto	90:cb3d968589d8	3098	/*!
Kojto	90:cb3d968589d8	3099	* @name Register SDHC_IRQSTATEN, field CINSEN[6] (RW)
Kojto	90:cb3d968589d8	3100	*
Kojto	90:cb3d968589d8	3101	* Values:
Kojto	90:cb3d968589d8	3102	* - 0 - Masked
Kojto	90:cb3d968589d8	3103	* - 1 - Enabled
Kojto	90:cb3d968589d8	3104	*/
Kojto	90:cb3d968589d8	3105	/@{/
Kojto	90:cb3d968589d8	3106	#define BP_SDHC_IRQSTATEN_CINSEN (6U) /!< Bit position for SDHC_IRQSTATEN_CINSEN. /
Kojto	90:cb3d968589d8	3107	#define BM_SDHC_IRQSTATEN_CINSEN (0x00000040U) /!< Bit mask for SDHC_IRQSTATEN_CINSEN. /
Kojto	90:cb3d968589d8	3108	#define BS_SDHC_IRQSTATEN_CINSEN (1U) /!< Bit field size in bits for SDHC_IRQSTATEN_CINSEN. /
Kojto	90:cb3d968589d8	3109
Kojto	90:cb3d968589d8	3110	/! @brief Read current value of the SDHC_IRQSTATEN_CINSEN field. /
Kojto	90:cb3d968589d8	3111	#define BR_SDHC_IRQSTATEN_CINSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CINSEN))
Kojto	90:cb3d968589d8	3112
Kojto	90:cb3d968589d8	3113	/! @brief Format value for bitfield SDHC_IRQSTATEN_CINSEN. /
Kojto	90:cb3d968589d8	3114	#define BF_SDHC_IRQSTATEN_CINSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CINSEN) & BM_SDHC_IRQSTATEN_CINSEN)
Kojto	90:cb3d968589d8	3115
Kojto	90:cb3d968589d8	3116	/! @brief Set the CINSEN field to a new value. /
Kojto	90:cb3d968589d8	3117	#define BW_SDHC_IRQSTATEN_CINSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CINSEN) = (v))
Kojto	90:cb3d968589d8	3118	/@}/
Kojto	90:cb3d968589d8	3119
Kojto	90:cb3d968589d8	3120	/*!
Kojto	90:cb3d968589d8	3121	* @name Register SDHC_IRQSTATEN, field CRMSEN[7] (RW)
Kojto	90:cb3d968589d8	3122	*
Kojto	90:cb3d968589d8	3123	* Values:
Kojto	90:cb3d968589d8	3124	* - 0 - Masked
Kojto	90:cb3d968589d8	3125	* - 1 - Enabled
Kojto	90:cb3d968589d8	3126	*/
Kojto	90:cb3d968589d8	3127	/@{/
Kojto	90:cb3d968589d8	3128	#define BP_SDHC_IRQSTATEN_CRMSEN (7U) /!< Bit position for SDHC_IRQSTATEN_CRMSEN. /
Kojto	90:cb3d968589d8	3129	#define BM_SDHC_IRQSTATEN_CRMSEN (0x00000080U) /!< Bit mask for SDHC_IRQSTATEN_CRMSEN. /
Kojto	90:cb3d968589d8	3130	#define BS_SDHC_IRQSTATEN_CRMSEN (1U) /!< Bit field size in bits for SDHC_IRQSTATEN_CRMSEN. /
Kojto	90:cb3d968589d8	3131
Kojto	90:cb3d968589d8	3132	/! @brief Read current value of the SDHC_IRQSTATEN_CRMSEN field. /
Kojto	90:cb3d968589d8	3133	#define BR_SDHC_IRQSTATEN_CRMSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CRMSEN))
Kojto	90:cb3d968589d8	3134
Kojto	90:cb3d968589d8	3135	/! @brief Format value for bitfield SDHC_IRQSTATEN_CRMSEN. /
Kojto	90:cb3d968589d8	3136	#define BF_SDHC_IRQSTATEN_CRMSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CRMSEN) & BM_SDHC_IRQSTATEN_CRMSEN)
Kojto	90:cb3d968589d8	3137
Kojto	90:cb3d968589d8	3138	/! @brief Set the CRMSEN field to a new value. /
Kojto	90:cb3d968589d8	3139	#define BW_SDHC_IRQSTATEN_CRMSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CRMSEN) = (v))
Kojto	90:cb3d968589d8	3140	/@}/
Kojto	90:cb3d968589d8	3141
Kojto	90:cb3d968589d8	3142	/*!
Kojto	90:cb3d968589d8	3143	* @name Register SDHC_IRQSTATEN, field CINTSEN[8] (RW)
Kojto	90:cb3d968589d8	3144	*
Kojto	90:cb3d968589d8	3145	* If this bit is set to 0, the SDHC will clear the interrupt request to the
Kojto	90:cb3d968589d8	3146	* system. The card interrupt detection is stopped when this bit is cleared and
Kojto	90:cb3d968589d8	3147	* restarted when this bit is set to 1. The host driver must clear the this bit
Kojto	90:cb3d968589d8	3148	* before servicing the card interrupt and must set this bit again after all interrupt
Kojto	90:cb3d968589d8	3149	* requests from the card are cleared to prevent inadvertent interrupts.
Kojto	90:cb3d968589d8	3150	*
Kojto	90:cb3d968589d8	3151	* Values:
Kojto	90:cb3d968589d8	3152	* - 0 - Masked
Kojto	90:cb3d968589d8	3153	* - 1 - Enabled
Kojto	90:cb3d968589d8	3154	*/
Kojto	90:cb3d968589d8	3155	/@{/
Kojto	90:cb3d968589d8	3156	#define BP_SDHC_IRQSTATEN_CINTSEN (8U) /!< Bit position for SDHC_IRQSTATEN_CINTSEN. /
Kojto	90:cb3d968589d8	3157	#define BM_SDHC_IRQSTATEN_CINTSEN (0x00000100U) /!< Bit mask for SDHC_IRQSTATEN_CINTSEN. /
Kojto	90:cb3d968589d8	3158	#define BS_SDHC_IRQSTATEN_CINTSEN (1U) /!< Bit field size in bits for SDHC_IRQSTATEN_CINTSEN. /
Kojto	90:cb3d968589d8	3159
Kojto	90:cb3d968589d8	3160	/! @brief Read current value of the SDHC_IRQSTATEN_CINTSEN field. /
Kojto	90:cb3d968589d8	3161	#define BR_SDHC_IRQSTATEN_CINTSEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CINTSEN))
Kojto	90:cb3d968589d8	3162
Kojto	90:cb3d968589d8	3163	/! @brief Format value for bitfield SDHC_IRQSTATEN_CINTSEN. /
Kojto	90:cb3d968589d8	3164	#define BF_SDHC_IRQSTATEN_CINTSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CINTSEN) & BM_SDHC_IRQSTATEN_CINTSEN)
Kojto	90:cb3d968589d8	3165
Kojto	90:cb3d968589d8	3166	/! @brief Set the CINTSEN field to a new value. /
Kojto	90:cb3d968589d8	3167	#define BW_SDHC_IRQSTATEN_CINTSEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CINTSEN) = (v))
Kojto	90:cb3d968589d8	3168	/@}/
Kojto	90:cb3d968589d8	3169
Kojto	90:cb3d968589d8	3170	/*!
Kojto	90:cb3d968589d8	3171	* @name Register SDHC_IRQSTATEN, field CTOESEN[16] (RW)
Kojto	90:cb3d968589d8	3172	*
Kojto	90:cb3d968589d8	3173	* Values:
Kojto	90:cb3d968589d8	3174	* - 0 - Masked
Kojto	90:cb3d968589d8	3175	* - 1 - Enabled
Kojto	90:cb3d968589d8	3176	*/
Kojto	90:cb3d968589d8	3177	/@{/
Kojto	90:cb3d968589d8	3178	#define BP_SDHC_IRQSTATEN_CTOESEN (16U) /!< Bit position for SDHC_IRQSTATEN_CTOESEN. /
Kojto	90:cb3d968589d8	3179	#define BM_SDHC_IRQSTATEN_CTOESEN (0x00010000U) /!< Bit mask for SDHC_IRQSTATEN_CTOESEN. /
Kojto	90:cb3d968589d8	3180	#define BS_SDHC_IRQSTATEN_CTOESEN (1U) /!< Bit field size in bits for SDHC_IRQSTATEN_CTOESEN. /
Kojto	90:cb3d968589d8	3181
Kojto	90:cb3d968589d8	3182	/! @brief Read current value of the SDHC_IRQSTATEN_CTOESEN field. /
Kojto	90:cb3d968589d8	3183	#define BR_SDHC_IRQSTATEN_CTOESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CTOESEN))
Kojto	90:cb3d968589d8	3184
Kojto	90:cb3d968589d8	3185	/! @brief Format value for bitfield SDHC_IRQSTATEN_CTOESEN. /
Kojto	90:cb3d968589d8	3186	#define BF_SDHC_IRQSTATEN_CTOESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CTOESEN) & BM_SDHC_IRQSTATEN_CTOESEN)
Kojto	90:cb3d968589d8	3187
Kojto	90:cb3d968589d8	3188	/! @brief Set the CTOESEN field to a new value. /
Kojto	90:cb3d968589d8	3189	#define BW_SDHC_IRQSTATEN_CTOESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CTOESEN) = (v))
Kojto	90:cb3d968589d8	3190	/@}/
Kojto	90:cb3d968589d8	3191
Kojto	90:cb3d968589d8	3192	/*!
Kojto	90:cb3d968589d8	3193	* @name Register SDHC_IRQSTATEN, field CCESEN[17] (RW)
Kojto	90:cb3d968589d8	3194	*
Kojto	90:cb3d968589d8	3195	* Values:
Kojto	90:cb3d968589d8	3196	* - 0 - Masked
Kojto	90:cb3d968589d8	3197	* - 1 - Enabled
Kojto	90:cb3d968589d8	3198	*/
Kojto	90:cb3d968589d8	3199	/@{/
Kojto	90:cb3d968589d8	3200	#define BP_SDHC_IRQSTATEN_CCESEN (17U) /!< Bit position for SDHC_IRQSTATEN_CCESEN. /
Kojto	90:cb3d968589d8	3201	#define BM_SDHC_IRQSTATEN_CCESEN (0x00020000U) /!< Bit mask for SDHC_IRQSTATEN_CCESEN. /
Kojto	90:cb3d968589d8	3202	#define BS_SDHC_IRQSTATEN_CCESEN (1U) /!< Bit field size in bits for SDHC_IRQSTATEN_CCESEN. /
Kojto	90:cb3d968589d8	3203
Kojto	90:cb3d968589d8	3204	/! @brief Read current value of the SDHC_IRQSTATEN_CCESEN field. /
Kojto	90:cb3d968589d8	3205	#define BR_SDHC_IRQSTATEN_CCESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CCESEN))
Kojto	90:cb3d968589d8	3206
Kojto	90:cb3d968589d8	3207	/! @brief Format value for bitfield SDHC_IRQSTATEN_CCESEN. /
Kojto	90:cb3d968589d8	3208	#define BF_SDHC_IRQSTATEN_CCESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CCESEN) & BM_SDHC_IRQSTATEN_CCESEN)
Kojto	90:cb3d968589d8	3209
Kojto	90:cb3d968589d8	3210	/! @brief Set the CCESEN field to a new value. /
Kojto	90:cb3d968589d8	3211	#define BW_SDHC_IRQSTATEN_CCESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CCESEN) = (v))
Kojto	90:cb3d968589d8	3212	/@}/
Kojto	90:cb3d968589d8	3213
Kojto	90:cb3d968589d8	3214	/*!
Kojto	90:cb3d968589d8	3215	* @name Register SDHC_IRQSTATEN, field CEBESEN[18] (RW)
Kojto	90:cb3d968589d8	3216	*
Kojto	90:cb3d968589d8	3217	* Values:
Kojto	90:cb3d968589d8	3218	* - 0 - Masked
Kojto	90:cb3d968589d8	3219	* - 1 - Enabled
Kojto	90:cb3d968589d8	3220	*/
Kojto	90:cb3d968589d8	3221	/@{/
Kojto	90:cb3d968589d8	3222	#define BP_SDHC_IRQSTATEN_CEBESEN (18U) /!< Bit position for SDHC_IRQSTATEN_CEBESEN. /
Kojto	90:cb3d968589d8	3223	#define BM_SDHC_IRQSTATEN_CEBESEN (0x00040000U) /!< Bit mask for SDHC_IRQSTATEN_CEBESEN. /
Kojto	90:cb3d968589d8	3224	#define BS_SDHC_IRQSTATEN_CEBESEN (1U) /!< Bit field size in bits for SDHC_IRQSTATEN_CEBESEN. /
Kojto	90:cb3d968589d8	3225
Kojto	90:cb3d968589d8	3226	/! @brief Read current value of the SDHC_IRQSTATEN_CEBESEN field. /
Kojto	90:cb3d968589d8	3227	#define BR_SDHC_IRQSTATEN_CEBESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CEBESEN))
Kojto	90:cb3d968589d8	3228
Kojto	90:cb3d968589d8	3229	/! @brief Format value for bitfield SDHC_IRQSTATEN_CEBESEN. /
Kojto	90:cb3d968589d8	3230	#define BF_SDHC_IRQSTATEN_CEBESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CEBESEN) & BM_SDHC_IRQSTATEN_CEBESEN)
Kojto	90:cb3d968589d8	3231
Kojto	90:cb3d968589d8	3232	/! @brief Set the CEBESEN field to a new value. /
Kojto	90:cb3d968589d8	3233	#define BW_SDHC_IRQSTATEN_CEBESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CEBESEN) = (v))
Kojto	90:cb3d968589d8	3234	/@}/
Kojto	90:cb3d968589d8	3235
Kojto	90:cb3d968589d8	3236	/*!
Kojto	90:cb3d968589d8	3237	* @name Register SDHC_IRQSTATEN, field CIESEN[19] (RW)
Kojto	90:cb3d968589d8	3238	*
Kojto	90:cb3d968589d8	3239	* Values:
Kojto	90:cb3d968589d8	3240	* - 0 - Masked
Kojto	90:cb3d968589d8	3241	* - 1 - Enabled
Kojto	90:cb3d968589d8	3242	*/
Kojto	90:cb3d968589d8	3243	/@{/
Kojto	90:cb3d968589d8	3244	#define BP_SDHC_IRQSTATEN_CIESEN (19U) /!< Bit position for SDHC_IRQSTATEN_CIESEN. /
Kojto	90:cb3d968589d8	3245	#define BM_SDHC_IRQSTATEN_CIESEN (0x00080000U) /!< Bit mask for SDHC_IRQSTATEN_CIESEN. /
Kojto	90:cb3d968589d8	3246	#define BS_SDHC_IRQSTATEN_CIESEN (1U) /!< Bit field size in bits for SDHC_IRQSTATEN_CIESEN. /
Kojto	90:cb3d968589d8	3247
Kojto	90:cb3d968589d8	3248	/! @brief Read current value of the SDHC_IRQSTATEN_CIESEN field. /
Kojto	90:cb3d968589d8	3249	#define BR_SDHC_IRQSTATEN_CIESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CIESEN))
Kojto	90:cb3d968589d8	3250
Kojto	90:cb3d968589d8	3251	/! @brief Format value for bitfield SDHC_IRQSTATEN_CIESEN. /
Kojto	90:cb3d968589d8	3252	#define BF_SDHC_IRQSTATEN_CIESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CIESEN) & BM_SDHC_IRQSTATEN_CIESEN)
Kojto	90:cb3d968589d8	3253
Kojto	90:cb3d968589d8	3254	/! @brief Set the CIESEN field to a new value. /
Kojto	90:cb3d968589d8	3255	#define BW_SDHC_IRQSTATEN_CIESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CIESEN) = (v))
Kojto	90:cb3d968589d8	3256	/@}/
Kojto	90:cb3d968589d8	3257
Kojto	90:cb3d968589d8	3258	/*!
Kojto	90:cb3d968589d8	3259	* @name Register SDHC_IRQSTATEN, field DTOESEN[20] (RW)
Kojto	90:cb3d968589d8	3260	*
Kojto	90:cb3d968589d8	3261	* Values:
Kojto	90:cb3d968589d8	3262	* - 0 - Masked
Kojto	90:cb3d968589d8	3263	* - 1 - Enabled
Kojto	90:cb3d968589d8	3264	*/
Kojto	90:cb3d968589d8	3265	/@{/
Kojto	90:cb3d968589d8	3266	#define BP_SDHC_IRQSTATEN_DTOESEN (20U) /!< Bit position for SDHC_IRQSTATEN_DTOESEN. /
Kojto	90:cb3d968589d8	3267	#define BM_SDHC_IRQSTATEN_DTOESEN (0x00100000U) /!< Bit mask for SDHC_IRQSTATEN_DTOESEN. /
Kojto	90:cb3d968589d8	3268	#define BS_SDHC_IRQSTATEN_DTOESEN (1U) /!< Bit field size in bits for SDHC_IRQSTATEN_DTOESEN. /
Kojto	90:cb3d968589d8	3269
Kojto	90:cb3d968589d8	3270	/! @brief Read current value of the SDHC_IRQSTATEN_DTOESEN field. /
Kojto	90:cb3d968589d8	3271	#define BR_SDHC_IRQSTATEN_DTOESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DTOESEN))
Kojto	90:cb3d968589d8	3272
Kojto	90:cb3d968589d8	3273	/! @brief Format value for bitfield SDHC_IRQSTATEN_DTOESEN. /
Kojto	90:cb3d968589d8	3274	#define BF_SDHC_IRQSTATEN_DTOESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_DTOESEN) & BM_SDHC_IRQSTATEN_DTOESEN)
Kojto	90:cb3d968589d8	3275
Kojto	90:cb3d968589d8	3276	/! @brief Set the DTOESEN field to a new value. /
Kojto	90:cb3d968589d8	3277	#define BW_SDHC_IRQSTATEN_DTOESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DTOESEN) = (v))
Kojto	90:cb3d968589d8	3278	/@}/
Kojto	90:cb3d968589d8	3279
Kojto	90:cb3d968589d8	3280	/*!
Kojto	90:cb3d968589d8	3281	* @name Register SDHC_IRQSTATEN, field DCESEN[21] (RW)
Kojto	90:cb3d968589d8	3282	*
Kojto	90:cb3d968589d8	3283	* Values:
Kojto	90:cb3d968589d8	3284	* - 0 - Masked
Kojto	90:cb3d968589d8	3285	* - 1 - Enabled
Kojto	90:cb3d968589d8	3286	*/
Kojto	90:cb3d968589d8	3287	/@{/
Kojto	90:cb3d968589d8	3288	#define BP_SDHC_IRQSTATEN_DCESEN (21U) /!< Bit position for SDHC_IRQSTATEN_DCESEN. /
Kojto	90:cb3d968589d8	3289	#define BM_SDHC_IRQSTATEN_DCESEN (0x00200000U) /!< Bit mask for SDHC_IRQSTATEN_DCESEN. /
Kojto	90:cb3d968589d8	3290	#define BS_SDHC_IRQSTATEN_DCESEN (1U) /!< Bit field size in bits for SDHC_IRQSTATEN_DCESEN. /
Kojto	90:cb3d968589d8	3291
Kojto	90:cb3d968589d8	3292	/! @brief Read current value of the SDHC_IRQSTATEN_DCESEN field. /
Kojto	90:cb3d968589d8	3293	#define BR_SDHC_IRQSTATEN_DCESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DCESEN))
Kojto	90:cb3d968589d8	3294
Kojto	90:cb3d968589d8	3295	/! @brief Format value for bitfield SDHC_IRQSTATEN_DCESEN. /
Kojto	90:cb3d968589d8	3296	#define BF_SDHC_IRQSTATEN_DCESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_DCESEN) & BM_SDHC_IRQSTATEN_DCESEN)
Kojto	90:cb3d968589d8	3297
Kojto	90:cb3d968589d8	3298	/! @brief Set the DCESEN field to a new value. /
Kojto	90:cb3d968589d8	3299	#define BW_SDHC_IRQSTATEN_DCESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DCESEN) = (v))
Kojto	90:cb3d968589d8	3300	/@}/
Kojto	90:cb3d968589d8	3301
Kojto	90:cb3d968589d8	3302	/*!
Kojto	90:cb3d968589d8	3303	* @name Register SDHC_IRQSTATEN, field DEBESEN[22] (RW)
Kojto	90:cb3d968589d8	3304	*
Kojto	90:cb3d968589d8	3305	* Values:
Kojto	90:cb3d968589d8	3306	* - 0 - Masked
Kojto	90:cb3d968589d8	3307	* - 1 - Enabled
Kojto	90:cb3d968589d8	3308	*/
Kojto	90:cb3d968589d8	3309	/@{/
Kojto	90:cb3d968589d8	3310	#define BP_SDHC_IRQSTATEN_DEBESEN (22U) /!< Bit position for SDHC_IRQSTATEN_DEBESEN. /
Kojto	90:cb3d968589d8	3311	#define BM_SDHC_IRQSTATEN_DEBESEN (0x00400000U) /!< Bit mask for SDHC_IRQSTATEN_DEBESEN. /
Kojto	90:cb3d968589d8	3312	#define BS_SDHC_IRQSTATEN_DEBESEN (1U) /!< Bit field size in bits for SDHC_IRQSTATEN_DEBESEN. /
Kojto	90:cb3d968589d8	3313
Kojto	90:cb3d968589d8	3314	/! @brief Read current value of the SDHC_IRQSTATEN_DEBESEN field. /
Kojto	90:cb3d968589d8	3315	#define BR_SDHC_IRQSTATEN_DEBESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DEBESEN))
Kojto	90:cb3d968589d8	3316
Kojto	90:cb3d968589d8	3317	/! @brief Format value for bitfield SDHC_IRQSTATEN_DEBESEN. /
Kojto	90:cb3d968589d8	3318	#define BF_SDHC_IRQSTATEN_DEBESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_DEBESEN) & BM_SDHC_IRQSTATEN_DEBESEN)
Kojto	90:cb3d968589d8	3319
Kojto	90:cb3d968589d8	3320	/! @brief Set the DEBESEN field to a new value. /
Kojto	90:cb3d968589d8	3321	#define BW_SDHC_IRQSTATEN_DEBESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DEBESEN) = (v))
Kojto	90:cb3d968589d8	3322	/@}/
Kojto	90:cb3d968589d8	3323
Kojto	90:cb3d968589d8	3324	/*!
Kojto	90:cb3d968589d8	3325	* @name Register SDHC_IRQSTATEN, field AC12ESEN[24] (RW)
Kojto	90:cb3d968589d8	3326	*
Kojto	90:cb3d968589d8	3327	* Values:
Kojto	90:cb3d968589d8	3328	* - 0 - Masked
Kojto	90:cb3d968589d8	3329	* - 1 - Enabled
Kojto	90:cb3d968589d8	3330	*/
Kojto	90:cb3d968589d8	3331	/@{/
Kojto	90:cb3d968589d8	3332	#define BP_SDHC_IRQSTATEN_AC12ESEN (24U) /!< Bit position for SDHC_IRQSTATEN_AC12ESEN. /
Kojto	90:cb3d968589d8	3333	#define BM_SDHC_IRQSTATEN_AC12ESEN (0x01000000U) /!< Bit mask for SDHC_IRQSTATEN_AC12ESEN. /
Kojto	90:cb3d968589d8	3334	#define BS_SDHC_IRQSTATEN_AC12ESEN (1U) /!< Bit field size in bits for SDHC_IRQSTATEN_AC12ESEN. /
Kojto	90:cb3d968589d8	3335
Kojto	90:cb3d968589d8	3336	/! @brief Read current value of the SDHC_IRQSTATEN_AC12ESEN field. /
Kojto	90:cb3d968589d8	3337	#define BR_SDHC_IRQSTATEN_AC12ESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_AC12ESEN))
Kojto	90:cb3d968589d8	3338
Kojto	90:cb3d968589d8	3339	/! @brief Format value for bitfield SDHC_IRQSTATEN_AC12ESEN. /
Kojto	90:cb3d968589d8	3340	#define BF_SDHC_IRQSTATEN_AC12ESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_AC12ESEN) & BM_SDHC_IRQSTATEN_AC12ESEN)
Kojto	90:cb3d968589d8	3341
Kojto	90:cb3d968589d8	3342	/! @brief Set the AC12ESEN field to a new value. /
Kojto	90:cb3d968589d8	3343	#define BW_SDHC_IRQSTATEN_AC12ESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_AC12ESEN) = (v))
Kojto	90:cb3d968589d8	3344	/@}/
Kojto	90:cb3d968589d8	3345
Kojto	90:cb3d968589d8	3346	/*!
Kojto	90:cb3d968589d8	3347	* @name Register SDHC_IRQSTATEN, field DMAESEN[28] (RW)
Kojto	90:cb3d968589d8	3348	*
Kojto	90:cb3d968589d8	3349	* Values:
Kojto	90:cb3d968589d8	3350	* - 0 - Masked
Kojto	90:cb3d968589d8	3351	* - 1 - Enabled
Kojto	90:cb3d968589d8	3352	*/
Kojto	90:cb3d968589d8	3353	/@{/
Kojto	90:cb3d968589d8	3354	#define BP_SDHC_IRQSTATEN_DMAESEN (28U) /!< Bit position for SDHC_IRQSTATEN_DMAESEN. /
Kojto	90:cb3d968589d8	3355	#define BM_SDHC_IRQSTATEN_DMAESEN (0x10000000U) /!< Bit mask for SDHC_IRQSTATEN_DMAESEN. /
Kojto	90:cb3d968589d8	3356	#define BS_SDHC_IRQSTATEN_DMAESEN (1U) /!< Bit field size in bits for SDHC_IRQSTATEN_DMAESEN. /
Kojto	90:cb3d968589d8	3357
Kojto	90:cb3d968589d8	3358	/! @brief Read current value of the SDHC_IRQSTATEN_DMAESEN field. /
Kojto	90:cb3d968589d8	3359	#define BR_SDHC_IRQSTATEN_DMAESEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DMAESEN))
Kojto	90:cb3d968589d8	3360
Kojto	90:cb3d968589d8	3361	/! @brief Format value for bitfield SDHC_IRQSTATEN_DMAESEN. /
Kojto	90:cb3d968589d8	3362	#define BF_SDHC_IRQSTATEN_DMAESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_DMAESEN) & BM_SDHC_IRQSTATEN_DMAESEN)
Kojto	90:cb3d968589d8	3363
Kojto	90:cb3d968589d8	3364	/! @brief Set the DMAESEN field to a new value. /
Kojto	90:cb3d968589d8	3365	#define BW_SDHC_IRQSTATEN_DMAESEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DMAESEN) = (v))
Kojto	90:cb3d968589d8	3366	/@}/
Kojto	90:cb3d968589d8	3367
Kojto	90:cb3d968589d8	3368	/*******************************************************************************
Kojto	90:cb3d968589d8	3369	* HW_SDHC_IRQSIGEN - Interrupt Signal Enable register
Kojto	90:cb3d968589d8	3370	******************************************************************************/
Kojto	90:cb3d968589d8	3371
Kojto	90:cb3d968589d8	3372	/*!
Kojto	90:cb3d968589d8	3373	* @brief HW_SDHC_IRQSIGEN - Interrupt Signal Enable register (RW)
Kojto	90:cb3d968589d8	3374	*
Kojto	90:cb3d968589d8	3375	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	3376	*
Kojto	90:cb3d968589d8	3377	* This register is used to select which interrupt status is indicated to the
Kojto	90:cb3d968589d8	3378	* host system as the interrupt. All of these status bits share the same interrupt
Kojto	90:cb3d968589d8	3379	* line. Setting any of these bits to 1 enables interrupt generation. The
Kojto	90:cb3d968589d8	3380	* corresponding status register bit will generate an interrupt when the corresponding
Kojto	90:cb3d968589d8	3381	* interrupt signal enable bit is set.
Kojto	90:cb3d968589d8	3382	*/
Kojto	90:cb3d968589d8	3383	typedef union _hw_sdhc_irqsigen
Kojto	90:cb3d968589d8	3384	{
Kojto	90:cb3d968589d8	3385	uint32_t U;
Kojto	90:cb3d968589d8	3386	struct _hw_sdhc_irqsigen_bitfields
Kojto	90:cb3d968589d8	3387	{
Kojto	90:cb3d968589d8	3388	uint32_t CCIEN : 1; /!< [0] Command Complete Interrupt Enable /
Kojto	90:cb3d968589d8	3389	uint32_t TCIEN : 1; /!< [1] Transfer Complete Interrupt Enable /
Kojto	90:cb3d968589d8	3390	uint32_t BGEIEN : 1; /!< [2] Block Gap Event Interrupt Enable /
Kojto	90:cb3d968589d8	3391	uint32_t DINTIEN : 1; /!< [3] DMA Interrupt Enable /
Kojto	90:cb3d968589d8	3392	uint32_t BWRIEN : 1; /!< [4] Buffer Write Ready Interrupt Enable /
Kojto	90:cb3d968589d8	3393	uint32_t BRRIEN : 1; /!< [5] Buffer Read Ready Interrupt Enable /
Kojto	90:cb3d968589d8	3394	uint32_t CINSIEN : 1; /!< [6] Card Insertion Interrupt Enable /
Kojto	90:cb3d968589d8	3395	uint32_t CRMIEN : 1; /!< [7] Card Removal Interrupt Enable /
Kojto	90:cb3d968589d8	3396	uint32_t CINTIEN : 1; /!< [8] Card Interrupt Enable /
Kojto	90:cb3d968589d8	3397	uint32_t RESERVED0 : 7; /!< [15:9] /
Kojto	90:cb3d968589d8	3398	uint32_t CTOEIEN : 1; /*!< [16] Command Timeout Error Interrupt
Kojto	90:cb3d968589d8	3399	* Enable */
Kojto	90:cb3d968589d8	3400	uint32_t CCEIEN : 1; /!< [17] Command CRC Error Interrupt Enable /
Kojto	90:cb3d968589d8	3401	uint32_t CEBEIEN : 1; /*!< [18] Command End Bit Error Interrupt
Kojto	90:cb3d968589d8	3402	* Enable */
Kojto	90:cb3d968589d8	3403	uint32_t CIEIEN : 1; /!< [19] Command Index Error Interrupt Enable /
Kojto	90:cb3d968589d8	3404	uint32_t DTOEIEN : 1; /!< [20] Data Timeout Error Interrupt Enable /
Kojto	90:cb3d968589d8	3405	uint32_t DCEIEN : 1; /!< [21] Data CRC Error Interrupt Enable /
Kojto	90:cb3d968589d8	3406	uint32_t DEBEIEN : 1; /!< [22] Data End Bit Error Interrupt Enable /
Kojto	90:cb3d968589d8	3407	uint32_t RESERVED1 : 1; /!< [23] /
Kojto	90:cb3d968589d8	3408	uint32_t AC12EIEN : 1; /!< [24] Auto CMD12 Error Interrupt Enable /
Kojto	90:cb3d968589d8	3409	uint32_t RESERVED2 : 3; /!< [27:25] /
Kojto	90:cb3d968589d8	3410	uint32_t DMAEIEN : 1; /!< [28] DMA Error Interrupt Enable /
Kojto	90:cb3d968589d8	3411	uint32_t RESERVED3 : 3; /!< [31:29] /
Kojto	90:cb3d968589d8	3412	} B;
Kojto	90:cb3d968589d8	3413	} hw_sdhc_irqsigen_t;
Kojto	90:cb3d968589d8	3414
Kojto	90:cb3d968589d8	3415	/*!
Kojto	90:cb3d968589d8	3416	* @name Constants and macros for entire SDHC_IRQSIGEN register
Kojto	90:cb3d968589d8	3417	*/
Kojto	90:cb3d968589d8	3418	/@{/
Kojto	90:cb3d968589d8	3419	#define HW_SDHC_IRQSIGEN_ADDR(x) ((x) + 0x38U)
Kojto	90:cb3d968589d8	3420
Kojto	90:cb3d968589d8	3421	#define HW_SDHC_IRQSIGEN(x) ((__IO hw_sdhc_irqsigen_t ) HW_SDHC_IRQSIGEN_ADDR(x))
Kojto	90:cb3d968589d8	3422	#define HW_SDHC_IRQSIGEN_RD(x) (HW_SDHC_IRQSIGEN(x).U)
Kojto	90:cb3d968589d8	3423	#define HW_SDHC_IRQSIGEN_WR(x, v) (HW_SDHC_IRQSIGEN(x).U = (v))
Kojto	90:cb3d968589d8	3424	#define HW_SDHC_IRQSIGEN_SET(x, v) (HW_SDHC_IRQSIGEN_WR(x, HW_SDHC_IRQSIGEN_RD(x) \| (v)))
Kojto	90:cb3d968589d8	3425	#define HW_SDHC_IRQSIGEN_CLR(x, v) (HW_SDHC_IRQSIGEN_WR(x, HW_SDHC_IRQSIGEN_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	3426	#define HW_SDHC_IRQSIGEN_TOG(x, v) (HW_SDHC_IRQSIGEN_WR(x, HW_SDHC_IRQSIGEN_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	3427	/@}/
Kojto	90:cb3d968589d8	3428
Kojto	90:cb3d968589d8	3429	/*
Kojto	90:cb3d968589d8	3430	* Constants & macros for individual SDHC_IRQSIGEN bitfields
Kojto	90:cb3d968589d8	3431	*/
Kojto	90:cb3d968589d8	3432
Kojto	90:cb3d968589d8	3433	/*!
Kojto	90:cb3d968589d8	3434	* @name Register SDHC_IRQSIGEN, field CCIEN[0] (RW)
Kojto	90:cb3d968589d8	3435	*
Kojto	90:cb3d968589d8	3436	* Values:
Kojto	90:cb3d968589d8	3437	* - 0 - Masked
Kojto	90:cb3d968589d8	3438	* - 1 - Enabled
Kojto	90:cb3d968589d8	3439	*/
Kojto	90:cb3d968589d8	3440	/@{/
Kojto	90:cb3d968589d8	3441	#define BP_SDHC_IRQSIGEN_CCIEN (0U) /!< Bit position for SDHC_IRQSIGEN_CCIEN. /
Kojto	90:cb3d968589d8	3442	#define BM_SDHC_IRQSIGEN_CCIEN (0x00000001U) /!< Bit mask for SDHC_IRQSIGEN_CCIEN. /
Kojto	90:cb3d968589d8	3443	#define BS_SDHC_IRQSIGEN_CCIEN (1U) /!< Bit field size in bits for SDHC_IRQSIGEN_CCIEN. /
Kojto	90:cb3d968589d8	3444
Kojto	90:cb3d968589d8	3445	/! @brief Read current value of the SDHC_IRQSIGEN_CCIEN field. /
Kojto	90:cb3d968589d8	3446	#define BR_SDHC_IRQSIGEN_CCIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CCIEN))
Kojto	90:cb3d968589d8	3447
Kojto	90:cb3d968589d8	3448	/! @brief Format value for bitfield SDHC_IRQSIGEN_CCIEN. /
Kojto	90:cb3d968589d8	3449	#define BF_SDHC_IRQSIGEN_CCIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CCIEN) & BM_SDHC_IRQSIGEN_CCIEN)
Kojto	90:cb3d968589d8	3450
Kojto	90:cb3d968589d8	3451	/! @brief Set the CCIEN field to a new value. /
Kojto	90:cb3d968589d8	3452	#define BW_SDHC_IRQSIGEN_CCIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CCIEN) = (v))
Kojto	90:cb3d968589d8	3453	/@}/
Kojto	90:cb3d968589d8	3454
Kojto	90:cb3d968589d8	3455	/*!
Kojto	90:cb3d968589d8	3456	* @name Register SDHC_IRQSIGEN, field TCIEN[1] (RW)
Kojto	90:cb3d968589d8	3457	*
Kojto	90:cb3d968589d8	3458	* Values:
Kojto	90:cb3d968589d8	3459	* - 0 - Masked
Kojto	90:cb3d968589d8	3460	* - 1 - Enabled
Kojto	90:cb3d968589d8	3461	*/
Kojto	90:cb3d968589d8	3462	/@{/
Kojto	90:cb3d968589d8	3463	#define BP_SDHC_IRQSIGEN_TCIEN (1U) /!< Bit position for SDHC_IRQSIGEN_TCIEN. /
Kojto	90:cb3d968589d8	3464	#define BM_SDHC_IRQSIGEN_TCIEN (0x00000002U) /!< Bit mask for SDHC_IRQSIGEN_TCIEN. /
Kojto	90:cb3d968589d8	3465	#define BS_SDHC_IRQSIGEN_TCIEN (1U) /!< Bit field size in bits for SDHC_IRQSIGEN_TCIEN. /
Kojto	90:cb3d968589d8	3466
Kojto	90:cb3d968589d8	3467	/! @brief Read current value of the SDHC_IRQSIGEN_TCIEN field. /
Kojto	90:cb3d968589d8	3468	#define BR_SDHC_IRQSIGEN_TCIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_TCIEN))
Kojto	90:cb3d968589d8	3469
Kojto	90:cb3d968589d8	3470	/! @brief Format value for bitfield SDHC_IRQSIGEN_TCIEN. /
Kojto	90:cb3d968589d8	3471	#define BF_SDHC_IRQSIGEN_TCIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_TCIEN) & BM_SDHC_IRQSIGEN_TCIEN)
Kojto	90:cb3d968589d8	3472
Kojto	90:cb3d968589d8	3473	/! @brief Set the TCIEN field to a new value. /
Kojto	90:cb3d968589d8	3474	#define BW_SDHC_IRQSIGEN_TCIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_TCIEN) = (v))
Kojto	90:cb3d968589d8	3475	/@}/
Kojto	90:cb3d968589d8	3476
Kojto	90:cb3d968589d8	3477	/*!
Kojto	90:cb3d968589d8	3478	* @name Register SDHC_IRQSIGEN, field BGEIEN[2] (RW)
Kojto	90:cb3d968589d8	3479	*
Kojto	90:cb3d968589d8	3480	* Values:
Kojto	90:cb3d968589d8	3481	* - 0 - Masked
Kojto	90:cb3d968589d8	3482	* - 1 - Enabled
Kojto	90:cb3d968589d8	3483	*/
Kojto	90:cb3d968589d8	3484	/@{/
Kojto	90:cb3d968589d8	3485	#define BP_SDHC_IRQSIGEN_BGEIEN (2U) /!< Bit position for SDHC_IRQSIGEN_BGEIEN. /
Kojto	90:cb3d968589d8	3486	#define BM_SDHC_IRQSIGEN_BGEIEN (0x00000004U) /!< Bit mask for SDHC_IRQSIGEN_BGEIEN. /
Kojto	90:cb3d968589d8	3487	#define BS_SDHC_IRQSIGEN_BGEIEN (1U) /!< Bit field size in bits for SDHC_IRQSIGEN_BGEIEN. /
Kojto	90:cb3d968589d8	3488
Kojto	90:cb3d968589d8	3489	/! @brief Read current value of the SDHC_IRQSIGEN_BGEIEN field. /
Kojto	90:cb3d968589d8	3490	#define BR_SDHC_IRQSIGEN_BGEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BGEIEN))
Kojto	90:cb3d968589d8	3491
Kojto	90:cb3d968589d8	3492	/! @brief Format value for bitfield SDHC_IRQSIGEN_BGEIEN. /
Kojto	90:cb3d968589d8	3493	#define BF_SDHC_IRQSIGEN_BGEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_BGEIEN) & BM_SDHC_IRQSIGEN_BGEIEN)
Kojto	90:cb3d968589d8	3494
Kojto	90:cb3d968589d8	3495	/! @brief Set the BGEIEN field to a new value. /
Kojto	90:cb3d968589d8	3496	#define BW_SDHC_IRQSIGEN_BGEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BGEIEN) = (v))
Kojto	90:cb3d968589d8	3497	/@}/
Kojto	90:cb3d968589d8	3498
Kojto	90:cb3d968589d8	3499	/*!
Kojto	90:cb3d968589d8	3500	* @name Register SDHC_IRQSIGEN, field DINTIEN[3] (RW)
Kojto	90:cb3d968589d8	3501	*
Kojto	90:cb3d968589d8	3502	* Values:
Kojto	90:cb3d968589d8	3503	* - 0 - Masked
Kojto	90:cb3d968589d8	3504	* - 1 - Enabled
Kojto	90:cb3d968589d8	3505	*/
Kojto	90:cb3d968589d8	3506	/@{/
Kojto	90:cb3d968589d8	3507	#define BP_SDHC_IRQSIGEN_DINTIEN (3U) /!< Bit position for SDHC_IRQSIGEN_DINTIEN. /
Kojto	90:cb3d968589d8	3508	#define BM_SDHC_IRQSIGEN_DINTIEN (0x00000008U) /!< Bit mask for SDHC_IRQSIGEN_DINTIEN. /
Kojto	90:cb3d968589d8	3509	#define BS_SDHC_IRQSIGEN_DINTIEN (1U) /!< Bit field size in bits for SDHC_IRQSIGEN_DINTIEN. /
Kojto	90:cb3d968589d8	3510
Kojto	90:cb3d968589d8	3511	/! @brief Read current value of the SDHC_IRQSIGEN_DINTIEN field. /
Kojto	90:cb3d968589d8	3512	#define BR_SDHC_IRQSIGEN_DINTIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DINTIEN))
Kojto	90:cb3d968589d8	3513
Kojto	90:cb3d968589d8	3514	/! @brief Format value for bitfield SDHC_IRQSIGEN_DINTIEN. /
Kojto	90:cb3d968589d8	3515	#define BF_SDHC_IRQSIGEN_DINTIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_DINTIEN) & BM_SDHC_IRQSIGEN_DINTIEN)
Kojto	90:cb3d968589d8	3516
Kojto	90:cb3d968589d8	3517	/! @brief Set the DINTIEN field to a new value. /
Kojto	90:cb3d968589d8	3518	#define BW_SDHC_IRQSIGEN_DINTIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DINTIEN) = (v))
Kojto	90:cb3d968589d8	3519	/@}/
Kojto	90:cb3d968589d8	3520
Kojto	90:cb3d968589d8	3521	/*!
Kojto	90:cb3d968589d8	3522	* @name Register SDHC_IRQSIGEN, field BWRIEN[4] (RW)
Kojto	90:cb3d968589d8	3523	*
Kojto	90:cb3d968589d8	3524	* Values:
Kojto	90:cb3d968589d8	3525	* - 0 - Masked
Kojto	90:cb3d968589d8	3526	* - 1 - Enabled
Kojto	90:cb3d968589d8	3527	*/
Kojto	90:cb3d968589d8	3528	/@{/
Kojto	90:cb3d968589d8	3529	#define BP_SDHC_IRQSIGEN_BWRIEN (4U) /!< Bit position for SDHC_IRQSIGEN_BWRIEN. /
Kojto	90:cb3d968589d8	3530	#define BM_SDHC_IRQSIGEN_BWRIEN (0x00000010U) /!< Bit mask for SDHC_IRQSIGEN_BWRIEN. /
Kojto	90:cb3d968589d8	3531	#define BS_SDHC_IRQSIGEN_BWRIEN (1U) /!< Bit field size in bits for SDHC_IRQSIGEN_BWRIEN. /
Kojto	90:cb3d968589d8	3532
Kojto	90:cb3d968589d8	3533	/! @brief Read current value of the SDHC_IRQSIGEN_BWRIEN field. /
Kojto	90:cb3d968589d8	3534	#define BR_SDHC_IRQSIGEN_BWRIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BWRIEN))
Kojto	90:cb3d968589d8	3535
Kojto	90:cb3d968589d8	3536	/! @brief Format value for bitfield SDHC_IRQSIGEN_BWRIEN. /
Kojto	90:cb3d968589d8	3537	#define BF_SDHC_IRQSIGEN_BWRIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_BWRIEN) & BM_SDHC_IRQSIGEN_BWRIEN)
Kojto	90:cb3d968589d8	3538
Kojto	90:cb3d968589d8	3539	/! @brief Set the BWRIEN field to a new value. /
Kojto	90:cb3d968589d8	3540	#define BW_SDHC_IRQSIGEN_BWRIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BWRIEN) = (v))
Kojto	90:cb3d968589d8	3541	/@}/
Kojto	90:cb3d968589d8	3542
Kojto	90:cb3d968589d8	3543	/*!
Kojto	90:cb3d968589d8	3544	* @name Register SDHC_IRQSIGEN, field BRRIEN[5] (RW)
Kojto	90:cb3d968589d8	3545	*
Kojto	90:cb3d968589d8	3546	* Values:
Kojto	90:cb3d968589d8	3547	* - 0 - Masked
Kojto	90:cb3d968589d8	3548	* - 1 - Enabled
Kojto	90:cb3d968589d8	3549	*/
Kojto	90:cb3d968589d8	3550	/@{/
Kojto	90:cb3d968589d8	3551	#define BP_SDHC_IRQSIGEN_BRRIEN (5U) /!< Bit position for SDHC_IRQSIGEN_BRRIEN. /
Kojto	90:cb3d968589d8	3552	#define BM_SDHC_IRQSIGEN_BRRIEN (0x00000020U) /!< Bit mask for SDHC_IRQSIGEN_BRRIEN. /
Kojto	90:cb3d968589d8	3553	#define BS_SDHC_IRQSIGEN_BRRIEN (1U) /!< Bit field size in bits for SDHC_IRQSIGEN_BRRIEN. /
Kojto	90:cb3d968589d8	3554
Kojto	90:cb3d968589d8	3555	/! @brief Read current value of the SDHC_IRQSIGEN_BRRIEN field. /
Kojto	90:cb3d968589d8	3556	#define BR_SDHC_IRQSIGEN_BRRIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BRRIEN))
Kojto	90:cb3d968589d8	3557
Kojto	90:cb3d968589d8	3558	/! @brief Format value for bitfield SDHC_IRQSIGEN_BRRIEN. /
Kojto	90:cb3d968589d8	3559	#define BF_SDHC_IRQSIGEN_BRRIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_BRRIEN) & BM_SDHC_IRQSIGEN_BRRIEN)
Kojto	90:cb3d968589d8	3560
Kojto	90:cb3d968589d8	3561	/! @brief Set the BRRIEN field to a new value. /
Kojto	90:cb3d968589d8	3562	#define BW_SDHC_IRQSIGEN_BRRIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BRRIEN) = (v))
Kojto	90:cb3d968589d8	3563	/@}/
Kojto	90:cb3d968589d8	3564
Kojto	90:cb3d968589d8	3565	/*!
Kojto	90:cb3d968589d8	3566	* @name Register SDHC_IRQSIGEN, field CINSIEN[6] (RW)
Kojto	90:cb3d968589d8	3567	*
Kojto	90:cb3d968589d8	3568	* Values:
Kojto	90:cb3d968589d8	3569	* - 0 - Masked
Kojto	90:cb3d968589d8	3570	* - 1 - Enabled
Kojto	90:cb3d968589d8	3571	*/
Kojto	90:cb3d968589d8	3572	/@{/
Kojto	90:cb3d968589d8	3573	#define BP_SDHC_IRQSIGEN_CINSIEN (6U) /!< Bit position for SDHC_IRQSIGEN_CINSIEN. /
Kojto	90:cb3d968589d8	3574	#define BM_SDHC_IRQSIGEN_CINSIEN (0x00000040U) /!< Bit mask for SDHC_IRQSIGEN_CINSIEN. /
Kojto	90:cb3d968589d8	3575	#define BS_SDHC_IRQSIGEN_CINSIEN (1U) /!< Bit field size in bits for SDHC_IRQSIGEN_CINSIEN. /
Kojto	90:cb3d968589d8	3576
Kojto	90:cb3d968589d8	3577	/! @brief Read current value of the SDHC_IRQSIGEN_CINSIEN field. /
Kojto	90:cb3d968589d8	3578	#define BR_SDHC_IRQSIGEN_CINSIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CINSIEN))
Kojto	90:cb3d968589d8	3579
Kojto	90:cb3d968589d8	3580	/! @brief Format value for bitfield SDHC_IRQSIGEN_CINSIEN. /
Kojto	90:cb3d968589d8	3581	#define BF_SDHC_IRQSIGEN_CINSIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CINSIEN) & BM_SDHC_IRQSIGEN_CINSIEN)
Kojto	90:cb3d968589d8	3582
Kojto	90:cb3d968589d8	3583	/! @brief Set the CINSIEN field to a new value. /
Kojto	90:cb3d968589d8	3584	#define BW_SDHC_IRQSIGEN_CINSIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CINSIEN) = (v))
Kojto	90:cb3d968589d8	3585	/@}/
Kojto	90:cb3d968589d8	3586
Kojto	90:cb3d968589d8	3587	/*!
Kojto	90:cb3d968589d8	3588	* @name Register SDHC_IRQSIGEN, field CRMIEN[7] (RW)
Kojto	90:cb3d968589d8	3589	*
Kojto	90:cb3d968589d8	3590	* Values:
Kojto	90:cb3d968589d8	3591	* - 0 - Masked
Kojto	90:cb3d968589d8	3592	* - 1 - Enabled
Kojto	90:cb3d968589d8	3593	*/
Kojto	90:cb3d968589d8	3594	/@{/
Kojto	90:cb3d968589d8	3595	#define BP_SDHC_IRQSIGEN_CRMIEN (7U) /!< Bit position for SDHC_IRQSIGEN_CRMIEN. /
Kojto	90:cb3d968589d8	3596	#define BM_SDHC_IRQSIGEN_CRMIEN (0x00000080U) /!< Bit mask for SDHC_IRQSIGEN_CRMIEN. /
Kojto	90:cb3d968589d8	3597	#define BS_SDHC_IRQSIGEN_CRMIEN (1U) /!< Bit field size in bits for SDHC_IRQSIGEN_CRMIEN. /
Kojto	90:cb3d968589d8	3598
Kojto	90:cb3d968589d8	3599	/! @brief Read current value of the SDHC_IRQSIGEN_CRMIEN field. /
Kojto	90:cb3d968589d8	3600	#define BR_SDHC_IRQSIGEN_CRMIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CRMIEN))
Kojto	90:cb3d968589d8	3601
Kojto	90:cb3d968589d8	3602	/! @brief Format value for bitfield SDHC_IRQSIGEN_CRMIEN. /
Kojto	90:cb3d968589d8	3603	#define BF_SDHC_IRQSIGEN_CRMIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CRMIEN) & BM_SDHC_IRQSIGEN_CRMIEN)
Kojto	90:cb3d968589d8	3604
Kojto	90:cb3d968589d8	3605	/! @brief Set the CRMIEN field to a new value. /
Kojto	90:cb3d968589d8	3606	#define BW_SDHC_IRQSIGEN_CRMIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CRMIEN) = (v))
Kojto	90:cb3d968589d8	3607	/@}/
Kojto	90:cb3d968589d8	3608
Kojto	90:cb3d968589d8	3609	/*!
Kojto	90:cb3d968589d8	3610	* @name Register SDHC_IRQSIGEN, field CINTIEN[8] (RW)
Kojto	90:cb3d968589d8	3611	*
Kojto	90:cb3d968589d8	3612	* Values:
Kojto	90:cb3d968589d8	3613	* - 0 - Masked
Kojto	90:cb3d968589d8	3614	* - 1 - Enabled
Kojto	90:cb3d968589d8	3615	*/
Kojto	90:cb3d968589d8	3616	/@{/
Kojto	90:cb3d968589d8	3617	#define BP_SDHC_IRQSIGEN_CINTIEN (8U) /!< Bit position for SDHC_IRQSIGEN_CINTIEN. /
Kojto	90:cb3d968589d8	3618	#define BM_SDHC_IRQSIGEN_CINTIEN (0x00000100U) /!< Bit mask for SDHC_IRQSIGEN_CINTIEN. /
Kojto	90:cb3d968589d8	3619	#define BS_SDHC_IRQSIGEN_CINTIEN (1U) /!< Bit field size in bits for SDHC_IRQSIGEN_CINTIEN. /
Kojto	90:cb3d968589d8	3620
Kojto	90:cb3d968589d8	3621	/! @brief Read current value of the SDHC_IRQSIGEN_CINTIEN field. /
Kojto	90:cb3d968589d8	3622	#define BR_SDHC_IRQSIGEN_CINTIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CINTIEN))
Kojto	90:cb3d968589d8	3623
Kojto	90:cb3d968589d8	3624	/! @brief Format value for bitfield SDHC_IRQSIGEN_CINTIEN. /
Kojto	90:cb3d968589d8	3625	#define BF_SDHC_IRQSIGEN_CINTIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CINTIEN) & BM_SDHC_IRQSIGEN_CINTIEN)
Kojto	90:cb3d968589d8	3626
Kojto	90:cb3d968589d8	3627	/! @brief Set the CINTIEN field to a new value. /
Kojto	90:cb3d968589d8	3628	#define BW_SDHC_IRQSIGEN_CINTIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CINTIEN) = (v))
Kojto	90:cb3d968589d8	3629	/@}/
Kojto	90:cb3d968589d8	3630
Kojto	90:cb3d968589d8	3631	/*!
Kojto	90:cb3d968589d8	3632	* @name Register SDHC_IRQSIGEN, field CTOEIEN[16] (RW)
Kojto	90:cb3d968589d8	3633	*
Kojto	90:cb3d968589d8	3634	* Values:
Kojto	90:cb3d968589d8	3635	* - 0 - Masked
Kojto	90:cb3d968589d8	3636	* - 1 - Enabled
Kojto	90:cb3d968589d8	3637	*/
Kojto	90:cb3d968589d8	3638	/@{/
Kojto	90:cb3d968589d8	3639	#define BP_SDHC_IRQSIGEN_CTOEIEN (16U) /!< Bit position for SDHC_IRQSIGEN_CTOEIEN. /
Kojto	90:cb3d968589d8	3640	#define BM_SDHC_IRQSIGEN_CTOEIEN (0x00010000U) /!< Bit mask for SDHC_IRQSIGEN_CTOEIEN. /
Kojto	90:cb3d968589d8	3641	#define BS_SDHC_IRQSIGEN_CTOEIEN (1U) /!< Bit field size in bits for SDHC_IRQSIGEN_CTOEIEN. /
Kojto	90:cb3d968589d8	3642
Kojto	90:cb3d968589d8	3643	/! @brief Read current value of the SDHC_IRQSIGEN_CTOEIEN field. /
Kojto	90:cb3d968589d8	3644	#define BR_SDHC_IRQSIGEN_CTOEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CTOEIEN))
Kojto	90:cb3d968589d8	3645
Kojto	90:cb3d968589d8	3646	/! @brief Format value for bitfield SDHC_IRQSIGEN_CTOEIEN. /
Kojto	90:cb3d968589d8	3647	#define BF_SDHC_IRQSIGEN_CTOEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CTOEIEN) & BM_SDHC_IRQSIGEN_CTOEIEN)
Kojto	90:cb3d968589d8	3648
Kojto	90:cb3d968589d8	3649	/! @brief Set the CTOEIEN field to a new value. /
Kojto	90:cb3d968589d8	3650	#define BW_SDHC_IRQSIGEN_CTOEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CTOEIEN) = (v))
Kojto	90:cb3d968589d8	3651	/@}/
Kojto	90:cb3d968589d8	3652
Kojto	90:cb3d968589d8	3653	/*!
Kojto	90:cb3d968589d8	3654	* @name Register SDHC_IRQSIGEN, field CCEIEN[17] (RW)
Kojto	90:cb3d968589d8	3655	*
Kojto	90:cb3d968589d8	3656	* Values:
Kojto	90:cb3d968589d8	3657	* - 0 - Masked
Kojto	90:cb3d968589d8	3658	* - 1 - Enabled
Kojto	90:cb3d968589d8	3659	*/
Kojto	90:cb3d968589d8	3660	/@{/
Kojto	90:cb3d968589d8	3661	#define BP_SDHC_IRQSIGEN_CCEIEN (17U) /!< Bit position for SDHC_IRQSIGEN_CCEIEN. /
Kojto	90:cb3d968589d8	3662	#define BM_SDHC_IRQSIGEN_CCEIEN (0x00020000U) /!< Bit mask for SDHC_IRQSIGEN_CCEIEN. /
Kojto	90:cb3d968589d8	3663	#define BS_SDHC_IRQSIGEN_CCEIEN (1U) /!< Bit field size in bits for SDHC_IRQSIGEN_CCEIEN. /
Kojto	90:cb3d968589d8	3664
Kojto	90:cb3d968589d8	3665	/! @brief Read current value of the SDHC_IRQSIGEN_CCEIEN field. /
Kojto	90:cb3d968589d8	3666	#define BR_SDHC_IRQSIGEN_CCEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CCEIEN))
Kojto	90:cb3d968589d8	3667
Kojto	90:cb3d968589d8	3668	/! @brief Format value for bitfield SDHC_IRQSIGEN_CCEIEN. /
Kojto	90:cb3d968589d8	3669	#define BF_SDHC_IRQSIGEN_CCEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CCEIEN) & BM_SDHC_IRQSIGEN_CCEIEN)
Kojto	90:cb3d968589d8	3670
Kojto	90:cb3d968589d8	3671	/! @brief Set the CCEIEN field to a new value. /
Kojto	90:cb3d968589d8	3672	#define BW_SDHC_IRQSIGEN_CCEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CCEIEN) = (v))
Kojto	90:cb3d968589d8	3673	/@}/
Kojto	90:cb3d968589d8	3674
Kojto	90:cb3d968589d8	3675	/*!
Kojto	90:cb3d968589d8	3676	* @name Register SDHC_IRQSIGEN, field CEBEIEN[18] (RW)
Kojto	90:cb3d968589d8	3677	*
Kojto	90:cb3d968589d8	3678	* Values:
Kojto	90:cb3d968589d8	3679	* - 0 - Masked
Kojto	90:cb3d968589d8	3680	* - 1 - Enabled
Kojto	90:cb3d968589d8	3681	*/
Kojto	90:cb3d968589d8	3682	/@{/
Kojto	90:cb3d968589d8	3683	#define BP_SDHC_IRQSIGEN_CEBEIEN (18U) /!< Bit position for SDHC_IRQSIGEN_CEBEIEN. /
Kojto	90:cb3d968589d8	3684	#define BM_SDHC_IRQSIGEN_CEBEIEN (0x00040000U) /!< Bit mask for SDHC_IRQSIGEN_CEBEIEN. /
Kojto	90:cb3d968589d8	3685	#define BS_SDHC_IRQSIGEN_CEBEIEN (1U) /!< Bit field size in bits for SDHC_IRQSIGEN_CEBEIEN. /
Kojto	90:cb3d968589d8	3686
Kojto	90:cb3d968589d8	3687	/! @brief Read current value of the SDHC_IRQSIGEN_CEBEIEN field. /
Kojto	90:cb3d968589d8	3688	#define BR_SDHC_IRQSIGEN_CEBEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CEBEIEN))
Kojto	90:cb3d968589d8	3689
Kojto	90:cb3d968589d8	3690	/! @brief Format value for bitfield SDHC_IRQSIGEN_CEBEIEN. /
Kojto	90:cb3d968589d8	3691	#define BF_SDHC_IRQSIGEN_CEBEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CEBEIEN) & BM_SDHC_IRQSIGEN_CEBEIEN)
Kojto	90:cb3d968589d8	3692
Kojto	90:cb3d968589d8	3693	/! @brief Set the CEBEIEN field to a new value. /
Kojto	90:cb3d968589d8	3694	#define BW_SDHC_IRQSIGEN_CEBEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CEBEIEN) = (v))
Kojto	90:cb3d968589d8	3695	/@}/
Kojto	90:cb3d968589d8	3696
Kojto	90:cb3d968589d8	3697	/*!
Kojto	90:cb3d968589d8	3698	* @name Register SDHC_IRQSIGEN, field CIEIEN[19] (RW)
Kojto	90:cb3d968589d8	3699	*
Kojto	90:cb3d968589d8	3700	* Values:
Kojto	90:cb3d968589d8	3701	* - 0 - Masked
Kojto	90:cb3d968589d8	3702	* - 1 - Enabled
Kojto	90:cb3d968589d8	3703	*/
Kojto	90:cb3d968589d8	3704	/@{/
Kojto	90:cb3d968589d8	3705	#define BP_SDHC_IRQSIGEN_CIEIEN (19U) /!< Bit position for SDHC_IRQSIGEN_CIEIEN. /
Kojto	90:cb3d968589d8	3706	#define BM_SDHC_IRQSIGEN_CIEIEN (0x00080000U) /!< Bit mask for SDHC_IRQSIGEN_CIEIEN. /
Kojto	90:cb3d968589d8	3707	#define BS_SDHC_IRQSIGEN_CIEIEN (1U) /!< Bit field size in bits for SDHC_IRQSIGEN_CIEIEN. /
Kojto	90:cb3d968589d8	3708
Kojto	90:cb3d968589d8	3709	/! @brief Read current value of the SDHC_IRQSIGEN_CIEIEN field. /
Kojto	90:cb3d968589d8	3710	#define BR_SDHC_IRQSIGEN_CIEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CIEIEN))
Kojto	90:cb3d968589d8	3711
Kojto	90:cb3d968589d8	3712	/! @brief Format value for bitfield SDHC_IRQSIGEN_CIEIEN. /
Kojto	90:cb3d968589d8	3713	#define BF_SDHC_IRQSIGEN_CIEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CIEIEN) & BM_SDHC_IRQSIGEN_CIEIEN)
Kojto	90:cb3d968589d8	3714
Kojto	90:cb3d968589d8	3715	/! @brief Set the CIEIEN field to a new value. /
Kojto	90:cb3d968589d8	3716	#define BW_SDHC_IRQSIGEN_CIEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CIEIEN) = (v))
Kojto	90:cb3d968589d8	3717	/@}/
Kojto	90:cb3d968589d8	3718
Kojto	90:cb3d968589d8	3719	/*!
Kojto	90:cb3d968589d8	3720	* @name Register SDHC_IRQSIGEN, field DTOEIEN[20] (RW)
Kojto	90:cb3d968589d8	3721	*
Kojto	90:cb3d968589d8	3722	* Values:
Kojto	90:cb3d968589d8	3723	* - 0 - Masked
Kojto	90:cb3d968589d8	3724	* - 1 - Enabled
Kojto	90:cb3d968589d8	3725	*/
Kojto	90:cb3d968589d8	3726	/@{/
Kojto	90:cb3d968589d8	3727	#define BP_SDHC_IRQSIGEN_DTOEIEN (20U) /!< Bit position for SDHC_IRQSIGEN_DTOEIEN. /
Kojto	90:cb3d968589d8	3728	#define BM_SDHC_IRQSIGEN_DTOEIEN (0x00100000U) /!< Bit mask for SDHC_IRQSIGEN_DTOEIEN. /
Kojto	90:cb3d968589d8	3729	#define BS_SDHC_IRQSIGEN_DTOEIEN (1U) /!< Bit field size in bits for SDHC_IRQSIGEN_DTOEIEN. /
Kojto	90:cb3d968589d8	3730
Kojto	90:cb3d968589d8	3731	/! @brief Read current value of the SDHC_IRQSIGEN_DTOEIEN field. /
Kojto	90:cb3d968589d8	3732	#define BR_SDHC_IRQSIGEN_DTOEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DTOEIEN))
Kojto	90:cb3d968589d8	3733
Kojto	90:cb3d968589d8	3734	/! @brief Format value for bitfield SDHC_IRQSIGEN_DTOEIEN. /
Kojto	90:cb3d968589d8	3735	#define BF_SDHC_IRQSIGEN_DTOEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_DTOEIEN) & BM_SDHC_IRQSIGEN_DTOEIEN)
Kojto	90:cb3d968589d8	3736
Kojto	90:cb3d968589d8	3737	/! @brief Set the DTOEIEN field to a new value. /
Kojto	90:cb3d968589d8	3738	#define BW_SDHC_IRQSIGEN_DTOEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DTOEIEN) = (v))
Kojto	90:cb3d968589d8	3739	/@}/
Kojto	90:cb3d968589d8	3740
Kojto	90:cb3d968589d8	3741	/*!
Kojto	90:cb3d968589d8	3742	* @name Register SDHC_IRQSIGEN, field DCEIEN[21] (RW)
Kojto	90:cb3d968589d8	3743	*
Kojto	90:cb3d968589d8	3744	* Values:
Kojto	90:cb3d968589d8	3745	* - 0 - Masked
Kojto	90:cb3d968589d8	3746	* - 1 - Enabled
Kojto	90:cb3d968589d8	3747	*/
Kojto	90:cb3d968589d8	3748	/@{/
Kojto	90:cb3d968589d8	3749	#define BP_SDHC_IRQSIGEN_DCEIEN (21U) /!< Bit position for SDHC_IRQSIGEN_DCEIEN. /
Kojto	90:cb3d968589d8	3750	#define BM_SDHC_IRQSIGEN_DCEIEN (0x00200000U) /!< Bit mask for SDHC_IRQSIGEN_DCEIEN. /
Kojto	90:cb3d968589d8	3751	#define BS_SDHC_IRQSIGEN_DCEIEN (1U) /!< Bit field size in bits for SDHC_IRQSIGEN_DCEIEN. /
Kojto	90:cb3d968589d8	3752
Kojto	90:cb3d968589d8	3753	/! @brief Read current value of the SDHC_IRQSIGEN_DCEIEN field. /
Kojto	90:cb3d968589d8	3754	#define BR_SDHC_IRQSIGEN_DCEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DCEIEN))
Kojto	90:cb3d968589d8	3755
Kojto	90:cb3d968589d8	3756	/! @brief Format value for bitfield SDHC_IRQSIGEN_DCEIEN. /
Kojto	90:cb3d968589d8	3757	#define BF_SDHC_IRQSIGEN_DCEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_DCEIEN) & BM_SDHC_IRQSIGEN_DCEIEN)
Kojto	90:cb3d968589d8	3758
Kojto	90:cb3d968589d8	3759	/! @brief Set the DCEIEN field to a new value. /
Kojto	90:cb3d968589d8	3760	#define BW_SDHC_IRQSIGEN_DCEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DCEIEN) = (v))
Kojto	90:cb3d968589d8	3761	/@}/
Kojto	90:cb3d968589d8	3762
Kojto	90:cb3d968589d8	3763	/*!
Kojto	90:cb3d968589d8	3764	* @name Register SDHC_IRQSIGEN, field DEBEIEN[22] (RW)
Kojto	90:cb3d968589d8	3765	*
Kojto	90:cb3d968589d8	3766	* Values:
Kojto	90:cb3d968589d8	3767	* - 0 - Masked
Kojto	90:cb3d968589d8	3768	* - 1 - Enabled
Kojto	90:cb3d968589d8	3769	*/
Kojto	90:cb3d968589d8	3770	/@{/
Kojto	90:cb3d968589d8	3771	#define BP_SDHC_IRQSIGEN_DEBEIEN (22U) /!< Bit position for SDHC_IRQSIGEN_DEBEIEN. /
Kojto	90:cb3d968589d8	3772	#define BM_SDHC_IRQSIGEN_DEBEIEN (0x00400000U) /!< Bit mask for SDHC_IRQSIGEN_DEBEIEN. /
Kojto	90:cb3d968589d8	3773	#define BS_SDHC_IRQSIGEN_DEBEIEN (1U) /!< Bit field size in bits for SDHC_IRQSIGEN_DEBEIEN. /
Kojto	90:cb3d968589d8	3774
Kojto	90:cb3d968589d8	3775	/! @brief Read current value of the SDHC_IRQSIGEN_DEBEIEN field. /
Kojto	90:cb3d968589d8	3776	#define BR_SDHC_IRQSIGEN_DEBEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DEBEIEN))
Kojto	90:cb3d968589d8	3777
Kojto	90:cb3d968589d8	3778	/! @brief Format value for bitfield SDHC_IRQSIGEN_DEBEIEN. /
Kojto	90:cb3d968589d8	3779	#define BF_SDHC_IRQSIGEN_DEBEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_DEBEIEN) & BM_SDHC_IRQSIGEN_DEBEIEN)
Kojto	90:cb3d968589d8	3780
Kojto	90:cb3d968589d8	3781	/! @brief Set the DEBEIEN field to a new value. /
Kojto	90:cb3d968589d8	3782	#define BW_SDHC_IRQSIGEN_DEBEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DEBEIEN) = (v))
Kojto	90:cb3d968589d8	3783	/@}/
Kojto	90:cb3d968589d8	3784
Kojto	90:cb3d968589d8	3785	/*!
Kojto	90:cb3d968589d8	3786	* @name Register SDHC_IRQSIGEN, field AC12EIEN[24] (RW)
Kojto	90:cb3d968589d8	3787	*
Kojto	90:cb3d968589d8	3788	* Values:
Kojto	90:cb3d968589d8	3789	* - 0 - Masked
Kojto	90:cb3d968589d8	3790	* - 1 - Enabled
Kojto	90:cb3d968589d8	3791	*/
Kojto	90:cb3d968589d8	3792	/@{/
Kojto	90:cb3d968589d8	3793	#define BP_SDHC_IRQSIGEN_AC12EIEN (24U) /!< Bit position for SDHC_IRQSIGEN_AC12EIEN. /
Kojto	90:cb3d968589d8	3794	#define BM_SDHC_IRQSIGEN_AC12EIEN (0x01000000U) /!< Bit mask for SDHC_IRQSIGEN_AC12EIEN. /
Kojto	90:cb3d968589d8	3795	#define BS_SDHC_IRQSIGEN_AC12EIEN (1U) /!< Bit field size in bits for SDHC_IRQSIGEN_AC12EIEN. /
Kojto	90:cb3d968589d8	3796
Kojto	90:cb3d968589d8	3797	/! @brief Read current value of the SDHC_IRQSIGEN_AC12EIEN field. /
Kojto	90:cb3d968589d8	3798	#define BR_SDHC_IRQSIGEN_AC12EIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_AC12EIEN))
Kojto	90:cb3d968589d8	3799
Kojto	90:cb3d968589d8	3800	/! @brief Format value for bitfield SDHC_IRQSIGEN_AC12EIEN. /
Kojto	90:cb3d968589d8	3801	#define BF_SDHC_IRQSIGEN_AC12EIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_AC12EIEN) & BM_SDHC_IRQSIGEN_AC12EIEN)
Kojto	90:cb3d968589d8	3802
Kojto	90:cb3d968589d8	3803	/! @brief Set the AC12EIEN field to a new value. /
Kojto	90:cb3d968589d8	3804	#define BW_SDHC_IRQSIGEN_AC12EIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_AC12EIEN) = (v))
Kojto	90:cb3d968589d8	3805	/@}/
Kojto	90:cb3d968589d8	3806
Kojto	90:cb3d968589d8	3807	/*!
Kojto	90:cb3d968589d8	3808	* @name Register SDHC_IRQSIGEN, field DMAEIEN[28] (RW)
Kojto	90:cb3d968589d8	3809	*
Kojto	90:cb3d968589d8	3810	* Values:
Kojto	90:cb3d968589d8	3811	* - 0 - Masked
Kojto	90:cb3d968589d8	3812	* - 1 - Enabled
Kojto	90:cb3d968589d8	3813	*/
Kojto	90:cb3d968589d8	3814	/@{/
Kojto	90:cb3d968589d8	3815	#define BP_SDHC_IRQSIGEN_DMAEIEN (28U) /!< Bit position for SDHC_IRQSIGEN_DMAEIEN. /
Kojto	90:cb3d968589d8	3816	#define BM_SDHC_IRQSIGEN_DMAEIEN (0x10000000U) /!< Bit mask for SDHC_IRQSIGEN_DMAEIEN. /
Kojto	90:cb3d968589d8	3817	#define BS_SDHC_IRQSIGEN_DMAEIEN (1U) /!< Bit field size in bits for SDHC_IRQSIGEN_DMAEIEN. /
Kojto	90:cb3d968589d8	3818
Kojto	90:cb3d968589d8	3819	/! @brief Read current value of the SDHC_IRQSIGEN_DMAEIEN field. /
Kojto	90:cb3d968589d8	3820	#define BR_SDHC_IRQSIGEN_DMAEIEN(x) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DMAEIEN))
Kojto	90:cb3d968589d8	3821
Kojto	90:cb3d968589d8	3822	/! @brief Format value for bitfield SDHC_IRQSIGEN_DMAEIEN. /
Kojto	90:cb3d968589d8	3823	#define BF_SDHC_IRQSIGEN_DMAEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_DMAEIEN) & BM_SDHC_IRQSIGEN_DMAEIEN)
Kojto	90:cb3d968589d8	3824
Kojto	90:cb3d968589d8	3825	/! @brief Set the DMAEIEN field to a new value. /
Kojto	90:cb3d968589d8	3826	#define BW_SDHC_IRQSIGEN_DMAEIEN(x, v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DMAEIEN) = (v))
Kojto	90:cb3d968589d8	3827	/@}/
Kojto	90:cb3d968589d8	3828
Kojto	90:cb3d968589d8	3829	/*******************************************************************************
Kojto	90:cb3d968589d8	3830	* HW_SDHC_AC12ERR - Auto CMD12 Error Status Register
Kojto	90:cb3d968589d8	3831	******************************************************************************/
Kojto	90:cb3d968589d8	3832
Kojto	90:cb3d968589d8	3833	/*!
Kojto	90:cb3d968589d8	3834	* @brief HW_SDHC_AC12ERR - Auto CMD12 Error Status Register (RO)
Kojto	90:cb3d968589d8	3835	*
Kojto	90:cb3d968589d8	3836	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	3837	*
Kojto	90:cb3d968589d8	3838	* When the AC12ESEN bit in the Status register is set, the host driver shall
Kojto	90:cb3d968589d8	3839	* check this register to identify what kind of error the Auto CMD12 indicated.
Kojto	90:cb3d968589d8	3840	* This register is valid only when the Auto CMD12 Error status bit is set. The
Kojto	90:cb3d968589d8	3841	* following table shows the relationship between the Auto CMGD12 CRC error and the
Kojto	90:cb3d968589d8	3842	* Auto CMD12 command timeout error. Relationship between Command CRC Error and
Kojto	90:cb3d968589d8	3843	* Command Timeout Error For Auto CMD12 Auto CMD12 CRC error Auto CMD12 timeout
Kojto	90:cb3d968589d8	3844	* error Type of error 0 0 No error 0 1 Response timeout error 1 0 Response CRC
Kojto	90:cb3d968589d8	3845	* error 1 1 CMD line conflict Changes in Auto CMD12 Error Status register can be
Kojto	90:cb3d968589d8	3846	* classified in three scenarios: When the SDHC is going to issue an Auto CMD12: Set
Kojto	90:cb3d968589d8	3847	* bit 0 to 1 if the Auto CMD12 can't be issued due to an error in the previous
Kojto	90:cb3d968589d8	3848	* command. Set bit 0 to 0 if the auto CMD12 is issued. At the end bit of an auto
Kojto	90:cb3d968589d8	3849	* CMD12 response: Check errors corresponding to bits 1-4. Set bits 1-4
Kojto	90:cb3d968589d8	3850	* corresponding to detected errors. Clear bits 1-4 corresponding to detected errors.
Kojto	90:cb3d968589d8	3851	* Before reading the Auto CMD12 error status bit 7: Set bit 7 to 1 if there is a
Kojto	90:cb3d968589d8	3852	* command that can't be issued. Clear bit 7 if there is no command to issue. The
Kojto	90:cb3d968589d8	3853	* timing for generating the auto CMD12 error and writing to the command register
Kojto	90:cb3d968589d8	3854	* are asynchronous. After that, bit 7 shall be sampled when the driver is not
Kojto	90:cb3d968589d8	3855	* writing to the command register. So it is suggested to read this register only
Kojto	90:cb3d968589d8	3856	* when IRQSTAT[AC12E] is set. An Auto CMD12 error interrupt is generated when one
Kojto	90:cb3d968589d8	3857	* of the error bits (0-4) is set to 1. The command not issued by auto CMD12
Kojto	90:cb3d968589d8	3858	* error does not generate an interrupt.
Kojto	90:cb3d968589d8	3859	*/
Kojto	90:cb3d968589d8	3860	typedef union _hw_sdhc_ac12err
Kojto	90:cb3d968589d8	3861	{
Kojto	90:cb3d968589d8	3862	uint32_t U;
Kojto	90:cb3d968589d8	3863	struct _hw_sdhc_ac12err_bitfields
Kojto	90:cb3d968589d8	3864	{
Kojto	90:cb3d968589d8	3865	uint32_t AC12NE : 1; /!< [0] Auto CMD12 Not Executed /
Kojto	90:cb3d968589d8	3866	uint32_t AC12TOE : 1; /!< [1] Auto CMD12 Timeout Error /
Kojto	90:cb3d968589d8	3867	uint32_t AC12EBE : 1; /!< [2] Auto CMD12 End Bit Error /
Kojto	90:cb3d968589d8	3868	uint32_t AC12CE : 1; /!< [3] Auto CMD12 CRC Error /
Kojto	90:cb3d968589d8	3869	uint32_t AC12IE : 1; /!< [4] Auto CMD12 Index Error /
Kojto	90:cb3d968589d8	3870	uint32_t RESERVED0 : 2; /!< [6:5] /
Kojto	90:cb3d968589d8	3871	uint32_t CNIBAC12E : 1; /*!< [7] Command Not Issued By Auto CMD12
Kojto	90:cb3d968589d8	3872	* Error */
Kojto	90:cb3d968589d8	3873	uint32_t RESERVED1 : 24; /!< [31:8] /
Kojto	90:cb3d968589d8	3874	} B;
Kojto	90:cb3d968589d8	3875	} hw_sdhc_ac12err_t;
Kojto	90:cb3d968589d8	3876
Kojto	90:cb3d968589d8	3877	/*!
Kojto	90:cb3d968589d8	3878	* @name Constants and macros for entire SDHC_AC12ERR register
Kojto	90:cb3d968589d8	3879	*/
Kojto	90:cb3d968589d8	3880	/@{/
Kojto	90:cb3d968589d8	3881	#define HW_SDHC_AC12ERR_ADDR(x) ((x) + 0x3CU)
Kojto	90:cb3d968589d8	3882
Kojto	90:cb3d968589d8	3883	#define HW_SDHC_AC12ERR(x) ((__I hw_sdhc_ac12err_t ) HW_SDHC_AC12ERR_ADDR(x))
Kojto	90:cb3d968589d8	3884	#define HW_SDHC_AC12ERR_RD(x) (HW_SDHC_AC12ERR(x).U)
Kojto	90:cb3d968589d8	3885	/@}/
Kojto	90:cb3d968589d8	3886
Kojto	90:cb3d968589d8	3887	/*
Kojto	90:cb3d968589d8	3888	* Constants & macros for individual SDHC_AC12ERR bitfields
Kojto	90:cb3d968589d8	3889	*/
Kojto	90:cb3d968589d8	3890
Kojto	90:cb3d968589d8	3891	/*!
Kojto	90:cb3d968589d8	3892	* @name Register SDHC_AC12ERR, field AC12NE[0] (RO)
Kojto	90:cb3d968589d8	3893	*
Kojto	90:cb3d968589d8	3894	* If memory multiple block data transfer is not started, due to a command
Kojto	90:cb3d968589d8	3895	* error, this bit is not set because it is not necessary to issue an auto CMD12.
Kojto	90:cb3d968589d8	3896	* Setting this bit to 1 means the SDHC cannot issue the auto CMD12 to stop a memory
Kojto	90:cb3d968589d8	3897	* multiple block data transfer due to some error. If this bit is set to 1, other
Kojto	90:cb3d968589d8	3898	* error status bits (1-4) have no meaning.
Kojto	90:cb3d968589d8	3899	*
Kojto	90:cb3d968589d8	3900	* Values:
Kojto	90:cb3d968589d8	3901	* - 0 - Executed.
Kojto	90:cb3d968589d8	3902	* - 1 - Not executed.
Kojto	90:cb3d968589d8	3903	*/
Kojto	90:cb3d968589d8	3904	/@{/
Kojto	90:cb3d968589d8	3905	#define BP_SDHC_AC12ERR_AC12NE (0U) /!< Bit position for SDHC_AC12ERR_AC12NE. /
Kojto	90:cb3d968589d8	3906	#define BM_SDHC_AC12ERR_AC12NE (0x00000001U) /!< Bit mask for SDHC_AC12ERR_AC12NE. /
Kojto	90:cb3d968589d8	3907	#define BS_SDHC_AC12ERR_AC12NE (1U) /!< Bit field size in bits for SDHC_AC12ERR_AC12NE. /
Kojto	90:cb3d968589d8	3908
Kojto	90:cb3d968589d8	3909	/! @brief Read current value of the SDHC_AC12ERR_AC12NE field. /
Kojto	90:cb3d968589d8	3910	#define BR_SDHC_AC12ERR_AC12NE(x) (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_AC12NE))
Kojto	90:cb3d968589d8	3911	/@}/
Kojto	90:cb3d968589d8	3912
Kojto	90:cb3d968589d8	3913	/*!
Kojto	90:cb3d968589d8	3914	* @name Register SDHC_AC12ERR, field AC12TOE[1] (RO)
Kojto	90:cb3d968589d8	3915	*
Kojto	90:cb3d968589d8	3916	* Occurs if no response is returned within 64 SDCLK cycles from the end bit of
Kojto	90:cb3d968589d8	3917	* the command. If this bit is set to 1, the other error status bits (2-4) have
Kojto	90:cb3d968589d8	3918	* no meaning.
Kojto	90:cb3d968589d8	3919	*
Kojto	90:cb3d968589d8	3920	* Values:
Kojto	90:cb3d968589d8	3921	* - 0 - No error.
Kojto	90:cb3d968589d8	3922	* - 1 - Time out.
Kojto	90:cb3d968589d8	3923	*/
Kojto	90:cb3d968589d8	3924	/@{/
Kojto	90:cb3d968589d8	3925	#define BP_SDHC_AC12ERR_AC12TOE (1U) /!< Bit position for SDHC_AC12ERR_AC12TOE. /
Kojto	90:cb3d968589d8	3926	#define BM_SDHC_AC12ERR_AC12TOE (0x00000002U) /!< Bit mask for SDHC_AC12ERR_AC12TOE. /
Kojto	90:cb3d968589d8	3927	#define BS_SDHC_AC12ERR_AC12TOE (1U) /!< Bit field size in bits for SDHC_AC12ERR_AC12TOE. /
Kojto	90:cb3d968589d8	3928
Kojto	90:cb3d968589d8	3929	/! @brief Read current value of the SDHC_AC12ERR_AC12TOE field. /
Kojto	90:cb3d968589d8	3930	#define BR_SDHC_AC12ERR_AC12TOE(x) (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_AC12TOE))
Kojto	90:cb3d968589d8	3931	/@}/
Kojto	90:cb3d968589d8	3932
Kojto	90:cb3d968589d8	3933	/*!
Kojto	90:cb3d968589d8	3934	* @name Register SDHC_AC12ERR, field AC12EBE[2] (RO)
Kojto	90:cb3d968589d8	3935	*
Kojto	90:cb3d968589d8	3936	* Occurs when detecting that the end bit of command response is 0 which must be
Kojto	90:cb3d968589d8	3937	* 1.
Kojto	90:cb3d968589d8	3938	*
Kojto	90:cb3d968589d8	3939	* Values:
Kojto	90:cb3d968589d8	3940	* - 0 - No error.
Kojto	90:cb3d968589d8	3941	* - 1 - End bit error generated.
Kojto	90:cb3d968589d8	3942	*/
Kojto	90:cb3d968589d8	3943	/@{/
Kojto	90:cb3d968589d8	3944	#define BP_SDHC_AC12ERR_AC12EBE (2U) /!< Bit position for SDHC_AC12ERR_AC12EBE. /
Kojto	90:cb3d968589d8	3945	#define BM_SDHC_AC12ERR_AC12EBE (0x00000004U) /!< Bit mask for SDHC_AC12ERR_AC12EBE. /
Kojto	90:cb3d968589d8	3946	#define BS_SDHC_AC12ERR_AC12EBE (1U) /!< Bit field size in bits for SDHC_AC12ERR_AC12EBE. /
Kojto	90:cb3d968589d8	3947
Kojto	90:cb3d968589d8	3948	/! @brief Read current value of the SDHC_AC12ERR_AC12EBE field. /
Kojto	90:cb3d968589d8	3949	#define BR_SDHC_AC12ERR_AC12EBE(x) (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_AC12EBE))
Kojto	90:cb3d968589d8	3950	/@}/
Kojto	90:cb3d968589d8	3951
Kojto	90:cb3d968589d8	3952	/*!
Kojto	90:cb3d968589d8	3953	* @name Register SDHC_AC12ERR, field AC12CE[3] (RO)
Kojto	90:cb3d968589d8	3954	*
Kojto	90:cb3d968589d8	3955	* Occurs when detecting a CRC error in the command response.
Kojto	90:cb3d968589d8	3956	*
Kojto	90:cb3d968589d8	3957	* Values:
Kojto	90:cb3d968589d8	3958	* - 0 - No CRC error.
Kojto	90:cb3d968589d8	3959	* - 1 - CRC error met in Auto CMD12 response.
Kojto	90:cb3d968589d8	3960	*/
Kojto	90:cb3d968589d8	3961	/@{/
Kojto	90:cb3d968589d8	3962	#define BP_SDHC_AC12ERR_AC12CE (3U) /!< Bit position for SDHC_AC12ERR_AC12CE. /
Kojto	90:cb3d968589d8	3963	#define BM_SDHC_AC12ERR_AC12CE (0x00000008U) /!< Bit mask for SDHC_AC12ERR_AC12CE. /
Kojto	90:cb3d968589d8	3964	#define BS_SDHC_AC12ERR_AC12CE (1U) /!< Bit field size in bits for SDHC_AC12ERR_AC12CE. /
Kojto	90:cb3d968589d8	3965
Kojto	90:cb3d968589d8	3966	/! @brief Read current value of the SDHC_AC12ERR_AC12CE field. /
Kojto	90:cb3d968589d8	3967	#define BR_SDHC_AC12ERR_AC12CE(x) (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_AC12CE))
Kojto	90:cb3d968589d8	3968	/@}/
Kojto	90:cb3d968589d8	3969
Kojto	90:cb3d968589d8	3970	/*!
Kojto	90:cb3d968589d8	3971	* @name Register SDHC_AC12ERR, field AC12IE[4] (RO)
Kojto	90:cb3d968589d8	3972	*
Kojto	90:cb3d968589d8	3973	* Occurs if the command index error occurs in response to a command.
Kojto	90:cb3d968589d8	3974	*
Kojto	90:cb3d968589d8	3975	* Values:
Kojto	90:cb3d968589d8	3976	* - 0 - No error.
Kojto	90:cb3d968589d8	3977	* - 1 - Error, the CMD index in response is not CMD12.
Kojto	90:cb3d968589d8	3978	*/
Kojto	90:cb3d968589d8	3979	/@{/
Kojto	90:cb3d968589d8	3980	#define BP_SDHC_AC12ERR_AC12IE (4U) /!< Bit position for SDHC_AC12ERR_AC12IE. /
Kojto	90:cb3d968589d8	3981	#define BM_SDHC_AC12ERR_AC12IE (0x00000010U) /!< Bit mask for SDHC_AC12ERR_AC12IE. /
Kojto	90:cb3d968589d8	3982	#define BS_SDHC_AC12ERR_AC12IE (1U) /!< Bit field size in bits for SDHC_AC12ERR_AC12IE. /
Kojto	90:cb3d968589d8	3983
Kojto	90:cb3d968589d8	3984	/! @brief Read current value of the SDHC_AC12ERR_AC12IE field. /
Kojto	90:cb3d968589d8	3985	#define BR_SDHC_AC12ERR_AC12IE(x) (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_AC12IE))
Kojto	90:cb3d968589d8	3986	/@}/
Kojto	90:cb3d968589d8	3987
Kojto	90:cb3d968589d8	3988	/*!
Kojto	90:cb3d968589d8	3989	* @name Register SDHC_AC12ERR, field CNIBAC12E[7] (RO)
Kojto	90:cb3d968589d8	3990	*
Kojto	90:cb3d968589d8	3991	* Setting this bit to 1 means CMD_wo_DAT is not executed due to an auto CMD12
Kojto	90:cb3d968589d8	3992	* error (D04-D01) in this register.
Kojto	90:cb3d968589d8	3993	*
Kojto	90:cb3d968589d8	3994	* Values:
Kojto	90:cb3d968589d8	3995	* - 0 - No error.
Kojto	90:cb3d968589d8	3996	* - 1 - Not issued.
Kojto	90:cb3d968589d8	3997	*/
Kojto	90:cb3d968589d8	3998	/@{/
Kojto	90:cb3d968589d8	3999	#define BP_SDHC_AC12ERR_CNIBAC12E (7U) /!< Bit position for SDHC_AC12ERR_CNIBAC12E. /
Kojto	90:cb3d968589d8	4000	#define BM_SDHC_AC12ERR_CNIBAC12E (0x00000080U) /!< Bit mask for SDHC_AC12ERR_CNIBAC12E. /
Kojto	90:cb3d968589d8	4001	#define BS_SDHC_AC12ERR_CNIBAC12E (1U) /!< Bit field size in bits for SDHC_AC12ERR_CNIBAC12E. /
Kojto	90:cb3d968589d8	4002
Kojto	90:cb3d968589d8	4003	/! @brief Read current value of the SDHC_AC12ERR_CNIBAC12E field. /
Kojto	90:cb3d968589d8	4004	#define BR_SDHC_AC12ERR_CNIBAC12E(x) (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_CNIBAC12E))
Kojto	90:cb3d968589d8	4005	/@}/
Kojto	90:cb3d968589d8	4006
Kojto	90:cb3d968589d8	4007	/*******************************************************************************
Kojto	90:cb3d968589d8	4008	* HW_SDHC_HTCAPBLT - Host Controller Capabilities
Kojto	90:cb3d968589d8	4009	******************************************************************************/
Kojto	90:cb3d968589d8	4010
Kojto	90:cb3d968589d8	4011	/*!
Kojto	90:cb3d968589d8	4012	* @brief HW_SDHC_HTCAPBLT - Host Controller Capabilities (RO)
Kojto	90:cb3d968589d8	4013	*
Kojto	90:cb3d968589d8	4014	* Reset value: 0x07F30000U
Kojto	90:cb3d968589d8	4015	*
Kojto	90:cb3d968589d8	4016	* This register provides the host driver with information specific to the SDHC
Kojto	90:cb3d968589d8	4017	* implementation. The value in this register is the power-on-reset value, and
Kojto	90:cb3d968589d8	4018	* does not change with a software reset. Any write to this register is ignored.
Kojto	90:cb3d968589d8	4019	*/
Kojto	90:cb3d968589d8	4020	typedef union _hw_sdhc_htcapblt
Kojto	90:cb3d968589d8	4021	{
Kojto	90:cb3d968589d8	4022	uint32_t U;
Kojto	90:cb3d968589d8	4023	struct _hw_sdhc_htcapblt_bitfields
Kojto	90:cb3d968589d8	4024	{
Kojto	90:cb3d968589d8	4025	uint32_t RESERVED0 : 16; /!< [15:0] /
Kojto	90:cb3d968589d8	4026	uint32_t MBL : 3; /!< [18:16] Max Block Length /
Kojto	90:cb3d968589d8	4027	uint32_t RESERVED1 : 1; /!< [19] /
Kojto	90:cb3d968589d8	4028	uint32_t ADMAS : 1; /!< [20] ADMA Support /
Kojto	90:cb3d968589d8	4029	uint32_t HSS : 1; /!< [21] High Speed Support /
Kojto	90:cb3d968589d8	4030	uint32_t DMAS : 1; /!< [22] DMA Support /
Kojto	90:cb3d968589d8	4031	uint32_t SRS : 1; /!< [23] Suspend/Resume Support /
Kojto	90:cb3d968589d8	4032	uint32_t VS33 : 1; /!< [24] Voltage Support 3.3 V /
Kojto	90:cb3d968589d8	4033	uint32_t RESERVED2 : 7; /!< [31:25] /
Kojto	90:cb3d968589d8	4034	} B;
Kojto	90:cb3d968589d8	4035	} hw_sdhc_htcapblt_t;
Kojto	90:cb3d968589d8	4036
Kojto	90:cb3d968589d8	4037	/*!
Kojto	90:cb3d968589d8	4038	* @name Constants and macros for entire SDHC_HTCAPBLT register
Kojto	90:cb3d968589d8	4039	*/
Kojto	90:cb3d968589d8	4040	/@{/
Kojto	90:cb3d968589d8	4041	#define HW_SDHC_HTCAPBLT_ADDR(x) ((x) + 0x40U)
Kojto	90:cb3d968589d8	4042
Kojto	90:cb3d968589d8	4043	#define HW_SDHC_HTCAPBLT(x) ((__I hw_sdhc_htcapblt_t ) HW_SDHC_HTCAPBLT_ADDR(x))
Kojto	90:cb3d968589d8	4044	#define HW_SDHC_HTCAPBLT_RD(x) (HW_SDHC_HTCAPBLT(x).U)
Kojto	90:cb3d968589d8	4045	/@}/
Kojto	90:cb3d968589d8	4046
Kojto	90:cb3d968589d8	4047	/*
Kojto	90:cb3d968589d8	4048	* Constants & macros for individual SDHC_HTCAPBLT bitfields
Kojto	90:cb3d968589d8	4049	*/
Kojto	90:cb3d968589d8	4050
Kojto	90:cb3d968589d8	4051	/*!
Kojto	90:cb3d968589d8	4052	* @name Register SDHC_HTCAPBLT, field MBL[18:16] (RO)
Kojto	90:cb3d968589d8	4053	*
Kojto	90:cb3d968589d8	4054	* This value indicates the maximum block size that the host driver can read and
Kojto	90:cb3d968589d8	4055	* write to the buffer in the SDHC. The buffer shall transfer block size without
Kojto	90:cb3d968589d8	4056	* wait cycles.
Kojto	90:cb3d968589d8	4057	*
Kojto	90:cb3d968589d8	4058	* Values:
Kojto	90:cb3d968589d8	4059	* - 000 - 512 bytes
Kojto	90:cb3d968589d8	4060	* - 001 - 1024 bytes
Kojto	90:cb3d968589d8	4061	* - 010 - 2048 bytes
Kojto	90:cb3d968589d8	4062	* - 011 - 4096 bytes
Kojto	90:cb3d968589d8	4063	*/
Kojto	90:cb3d968589d8	4064	/@{/
Kojto	90:cb3d968589d8	4065	#define BP_SDHC_HTCAPBLT_MBL (16U) /!< Bit position for SDHC_HTCAPBLT_MBL. /
Kojto	90:cb3d968589d8	4066	#define BM_SDHC_HTCAPBLT_MBL (0x00070000U) /!< Bit mask for SDHC_HTCAPBLT_MBL. /
Kojto	90:cb3d968589d8	4067	#define BS_SDHC_HTCAPBLT_MBL (3U) /!< Bit field size in bits for SDHC_HTCAPBLT_MBL. /
Kojto	90:cb3d968589d8	4068
Kojto	90:cb3d968589d8	4069	/! @brief Read current value of the SDHC_HTCAPBLT_MBL field. /
Kojto	90:cb3d968589d8	4070	#define BR_SDHC_HTCAPBLT_MBL(x) (HW_SDHC_HTCAPBLT(x).B.MBL)
Kojto	90:cb3d968589d8	4071	/@}/
Kojto	90:cb3d968589d8	4072
Kojto	90:cb3d968589d8	4073	/*!
Kojto	90:cb3d968589d8	4074	* @name Register SDHC_HTCAPBLT, field ADMAS[20] (RO)
Kojto	90:cb3d968589d8	4075	*
Kojto	90:cb3d968589d8	4076	* This bit indicates whether the SDHC supports the ADMA feature.
Kojto	90:cb3d968589d8	4077	*
Kojto	90:cb3d968589d8	4078	* Values:
Kojto	90:cb3d968589d8	4079	* - 0 - Advanced DMA not supported.
Kojto	90:cb3d968589d8	4080	* - 1 - Advanced DMA supported.
Kojto	90:cb3d968589d8	4081	*/
Kojto	90:cb3d968589d8	4082	/@{/
Kojto	90:cb3d968589d8	4083	#define BP_SDHC_HTCAPBLT_ADMAS (20U) /!< Bit position for SDHC_HTCAPBLT_ADMAS. /
Kojto	90:cb3d968589d8	4084	#define BM_SDHC_HTCAPBLT_ADMAS (0x00100000U) /!< Bit mask for SDHC_HTCAPBLT_ADMAS. /
Kojto	90:cb3d968589d8	4085	#define BS_SDHC_HTCAPBLT_ADMAS (1U) /!< Bit field size in bits for SDHC_HTCAPBLT_ADMAS. /
Kojto	90:cb3d968589d8	4086
Kojto	90:cb3d968589d8	4087	/! @brief Read current value of the SDHC_HTCAPBLT_ADMAS field. /
Kojto	90:cb3d968589d8	4088	#define BR_SDHC_HTCAPBLT_ADMAS(x) (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR(x), BP_SDHC_HTCAPBLT_ADMAS))
Kojto	90:cb3d968589d8	4089	/@}/
Kojto	90:cb3d968589d8	4090
Kojto	90:cb3d968589d8	4091	/*!
Kojto	90:cb3d968589d8	4092	* @name Register SDHC_HTCAPBLT, field HSS[21] (RO)
Kojto	90:cb3d968589d8	4093	*
Kojto	90:cb3d968589d8	4094	* This bit indicates whether the SDHC supports high speed mode and the host
Kojto	90:cb3d968589d8	4095	* system can supply a SD Clock frequency from 25 MHz to 50 MHz.
Kojto	90:cb3d968589d8	4096	*
Kojto	90:cb3d968589d8	4097	* Values:
Kojto	90:cb3d968589d8	4098	* - 0 - High speed not supported.
Kojto	90:cb3d968589d8	4099	* - 1 - High speed supported.
Kojto	90:cb3d968589d8	4100	*/
Kojto	90:cb3d968589d8	4101	/@{/
Kojto	90:cb3d968589d8	4102	#define BP_SDHC_HTCAPBLT_HSS (21U) /!< Bit position for SDHC_HTCAPBLT_HSS. /
Kojto	90:cb3d968589d8	4103	#define BM_SDHC_HTCAPBLT_HSS (0x00200000U) /!< Bit mask for SDHC_HTCAPBLT_HSS. /
Kojto	90:cb3d968589d8	4104	#define BS_SDHC_HTCAPBLT_HSS (1U) /!< Bit field size in bits for SDHC_HTCAPBLT_HSS. /
Kojto	90:cb3d968589d8	4105
Kojto	90:cb3d968589d8	4106	/! @brief Read current value of the SDHC_HTCAPBLT_HSS field. /
Kojto	90:cb3d968589d8	4107	#define BR_SDHC_HTCAPBLT_HSS(x) (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR(x), BP_SDHC_HTCAPBLT_HSS))
Kojto	90:cb3d968589d8	4108	/@}/
Kojto	90:cb3d968589d8	4109
Kojto	90:cb3d968589d8	4110	/*!
Kojto	90:cb3d968589d8	4111	* @name Register SDHC_HTCAPBLT, field DMAS[22] (RO)
Kojto	90:cb3d968589d8	4112	*
Kojto	90:cb3d968589d8	4113	* This bit indicates whether the SDHC is capable of using the internal DMA to
Kojto	90:cb3d968589d8	4114	* transfer data between system memory and the data buffer directly.
Kojto	90:cb3d968589d8	4115	*
Kojto	90:cb3d968589d8	4116	* Values:
Kojto	90:cb3d968589d8	4117	* - 0 - DMA not supported.
Kojto	90:cb3d968589d8	4118	* - 1 - DMA supported.
Kojto	90:cb3d968589d8	4119	*/
Kojto	90:cb3d968589d8	4120	/@{/
Kojto	90:cb3d968589d8	4121	#define BP_SDHC_HTCAPBLT_DMAS (22U) /!< Bit position for SDHC_HTCAPBLT_DMAS. /
Kojto	90:cb3d968589d8	4122	#define BM_SDHC_HTCAPBLT_DMAS (0x00400000U) /!< Bit mask for SDHC_HTCAPBLT_DMAS. /
Kojto	90:cb3d968589d8	4123	#define BS_SDHC_HTCAPBLT_DMAS (1U) /!< Bit field size in bits for SDHC_HTCAPBLT_DMAS. /
Kojto	90:cb3d968589d8	4124
Kojto	90:cb3d968589d8	4125	/! @brief Read current value of the SDHC_HTCAPBLT_DMAS field. /
Kojto	90:cb3d968589d8	4126	#define BR_SDHC_HTCAPBLT_DMAS(x) (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR(x), BP_SDHC_HTCAPBLT_DMAS))
Kojto	90:cb3d968589d8	4127	/@}/
Kojto	90:cb3d968589d8	4128
Kojto	90:cb3d968589d8	4129	/*!
Kojto	90:cb3d968589d8	4130	* @name Register SDHC_HTCAPBLT, field SRS[23] (RO)
Kojto	90:cb3d968589d8	4131	*
Kojto	90:cb3d968589d8	4132	* This bit indicates whether the SDHC supports suspend / resume functionality.
Kojto	90:cb3d968589d8	4133	* If this bit is 0, the suspend and resume mechanism, as well as the read Wwait,
Kojto	90:cb3d968589d8	4134	* are not supported, and the host driver shall not issue either suspend or
Kojto	90:cb3d968589d8	4135	* resume commands.
Kojto	90:cb3d968589d8	4136	*
Kojto	90:cb3d968589d8	4137	* Values:
Kojto	90:cb3d968589d8	4138	* - 0 - Not supported.
Kojto	90:cb3d968589d8	4139	* - 1 - Supported.
Kojto	90:cb3d968589d8	4140	*/
Kojto	90:cb3d968589d8	4141	/@{/
Kojto	90:cb3d968589d8	4142	#define BP_SDHC_HTCAPBLT_SRS (23U) /!< Bit position for SDHC_HTCAPBLT_SRS. /
Kojto	90:cb3d968589d8	4143	#define BM_SDHC_HTCAPBLT_SRS (0x00800000U) /!< Bit mask for SDHC_HTCAPBLT_SRS. /
Kojto	90:cb3d968589d8	4144	#define BS_SDHC_HTCAPBLT_SRS (1U) /!< Bit field size in bits for SDHC_HTCAPBLT_SRS. /
Kojto	90:cb3d968589d8	4145
Kojto	90:cb3d968589d8	4146	/! @brief Read current value of the SDHC_HTCAPBLT_SRS field. /
Kojto	90:cb3d968589d8	4147	#define BR_SDHC_HTCAPBLT_SRS(x) (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR(x), BP_SDHC_HTCAPBLT_SRS))
Kojto	90:cb3d968589d8	4148	/@}/
Kojto	90:cb3d968589d8	4149
Kojto	90:cb3d968589d8	4150	/*!
Kojto	90:cb3d968589d8	4151	* @name Register SDHC_HTCAPBLT, field VS33[24] (RO)
Kojto	90:cb3d968589d8	4152	*
Kojto	90:cb3d968589d8	4153	* This bit shall depend on the host system ability.
Kojto	90:cb3d968589d8	4154	*
Kojto	90:cb3d968589d8	4155	* Values:
Kojto	90:cb3d968589d8	4156	* - 0 - 3.3 V not supported.
Kojto	90:cb3d968589d8	4157	* - 1 - 3.3 V supported.
Kojto	90:cb3d968589d8	4158	*/
Kojto	90:cb3d968589d8	4159	/@{/
Kojto	90:cb3d968589d8	4160	#define BP_SDHC_HTCAPBLT_VS33 (24U) /!< Bit position for SDHC_HTCAPBLT_VS33. /
Kojto	90:cb3d968589d8	4161	#define BM_SDHC_HTCAPBLT_VS33 (0x01000000U) /!< Bit mask for SDHC_HTCAPBLT_VS33. /
Kojto	90:cb3d968589d8	4162	#define BS_SDHC_HTCAPBLT_VS33 (1U) /!< Bit field size in bits for SDHC_HTCAPBLT_VS33. /
Kojto	90:cb3d968589d8	4163
Kojto	90:cb3d968589d8	4164	/! @brief Read current value of the SDHC_HTCAPBLT_VS33 field. /
Kojto	90:cb3d968589d8	4165	#define BR_SDHC_HTCAPBLT_VS33(x) (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR(x), BP_SDHC_HTCAPBLT_VS33))
Kojto	90:cb3d968589d8	4166	/@}/
Kojto	90:cb3d968589d8	4167
Kojto	90:cb3d968589d8	4168	/*******************************************************************************
Kojto	90:cb3d968589d8	4169	* HW_SDHC_WML - Watermark Level Register
Kojto	90:cb3d968589d8	4170	******************************************************************************/
Kojto	90:cb3d968589d8	4171
Kojto	90:cb3d968589d8	4172	/*!
Kojto	90:cb3d968589d8	4173	* @brief HW_SDHC_WML - Watermark Level Register (RW)
Kojto	90:cb3d968589d8	4174	*
Kojto	90:cb3d968589d8	4175	* Reset value: 0x00100010U
Kojto	90:cb3d968589d8	4176	*
Kojto	90:cb3d968589d8	4177	* Both write and read watermark levels (FIFO threshold) are configurable. There
Kojto	90:cb3d968589d8	4178	* value can range from 1 to 128 words. Both write and read burst lengths are
Kojto	90:cb3d968589d8	4179	* also configurable. There value can range from 1 to 31 words.
Kojto	90:cb3d968589d8	4180	*/
Kojto	90:cb3d968589d8	4181	typedef union _hw_sdhc_wml
Kojto	90:cb3d968589d8	4182	{
Kojto	90:cb3d968589d8	4183	uint32_t U;
Kojto	90:cb3d968589d8	4184	struct _hw_sdhc_wml_bitfields
Kojto	90:cb3d968589d8	4185	{
Kojto	90:cb3d968589d8	4186	uint32_t RDWML : 8; /!< [7:0] Read Watermark Level /
Kojto	90:cb3d968589d8	4187	uint32_t RESERVED0 : 8; /!< [15:8] /
Kojto	90:cb3d968589d8	4188	uint32_t WRWML : 8; /!< [23:16] Write Watermark Level /
Kojto	90:cb3d968589d8	4189	uint32_t RESERVED1 : 8; /!< [31:24] /
Kojto	90:cb3d968589d8	4190	} B;
Kojto	90:cb3d968589d8	4191	} hw_sdhc_wml_t;
Kojto	90:cb3d968589d8	4192
Kojto	90:cb3d968589d8	4193	/*!
Kojto	90:cb3d968589d8	4194	* @name Constants and macros for entire SDHC_WML register
Kojto	90:cb3d968589d8	4195	*/
Kojto	90:cb3d968589d8	4196	/@{/
Kojto	90:cb3d968589d8	4197	#define HW_SDHC_WML_ADDR(x) ((x) + 0x44U)
Kojto	90:cb3d968589d8	4198
Kojto	90:cb3d968589d8	4199	#define HW_SDHC_WML(x) ((__IO hw_sdhc_wml_t ) HW_SDHC_WML_ADDR(x))
Kojto	90:cb3d968589d8	4200	#define HW_SDHC_WML_RD(x) (HW_SDHC_WML(x).U)
Kojto	90:cb3d968589d8	4201	#define HW_SDHC_WML_WR(x, v) (HW_SDHC_WML(x).U = (v))
Kojto	90:cb3d968589d8	4202	#define HW_SDHC_WML_SET(x, v) (HW_SDHC_WML_WR(x, HW_SDHC_WML_RD(x) \| (v)))
Kojto	90:cb3d968589d8	4203	#define HW_SDHC_WML_CLR(x, v) (HW_SDHC_WML_WR(x, HW_SDHC_WML_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	4204	#define HW_SDHC_WML_TOG(x, v) (HW_SDHC_WML_WR(x, HW_SDHC_WML_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	4205	/@}/
Kojto	90:cb3d968589d8	4206
Kojto	90:cb3d968589d8	4207	/*
Kojto	90:cb3d968589d8	4208	* Constants & macros for individual SDHC_WML bitfields
Kojto	90:cb3d968589d8	4209	*/
Kojto	90:cb3d968589d8	4210
Kojto	90:cb3d968589d8	4211	/*!
Kojto	90:cb3d968589d8	4212	* @name Register SDHC_WML, field RDWML[7:0] (RW)
Kojto	90:cb3d968589d8	4213	*
Kojto	90:cb3d968589d8	4214	* The number of words used as the watermark level (FIFO threshold) in a DMA
Kojto	90:cb3d968589d8	4215	* read operation. Also the number of words as a sequence of read bursts in
Kojto	90:cb3d968589d8	4216	* back-to-back mode. The maximum legal value for the read water mark level is 128.
Kojto	90:cb3d968589d8	4217	*/
Kojto	90:cb3d968589d8	4218	/@{/
Kojto	90:cb3d968589d8	4219	#define BP_SDHC_WML_RDWML (0U) /!< Bit position for SDHC_WML_RDWML. /
Kojto	90:cb3d968589d8	4220	#define BM_SDHC_WML_RDWML (0x000000FFU) /!< Bit mask for SDHC_WML_RDWML. /
Kojto	90:cb3d968589d8	4221	#define BS_SDHC_WML_RDWML (8U) /!< Bit field size in bits for SDHC_WML_RDWML. /
Kojto	90:cb3d968589d8	4222
Kojto	90:cb3d968589d8	4223	/! @brief Read current value of the SDHC_WML_RDWML field. /
Kojto	90:cb3d968589d8	4224	#define BR_SDHC_WML_RDWML(x) (HW_SDHC_WML(x).B.RDWML)
Kojto	90:cb3d968589d8	4225
Kojto	90:cb3d968589d8	4226	/! @brief Format value for bitfield SDHC_WML_RDWML. /
Kojto	90:cb3d968589d8	4227	#define BF_SDHC_WML_RDWML(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_WML_RDWML) & BM_SDHC_WML_RDWML)
Kojto	90:cb3d968589d8	4228
Kojto	90:cb3d968589d8	4229	/! @brief Set the RDWML field to a new value. /
Kojto	90:cb3d968589d8	4230	#define BW_SDHC_WML_RDWML(x, v) (HW_SDHC_WML_WR(x, (HW_SDHC_WML_RD(x) & ~BM_SDHC_WML_RDWML) \| BF_SDHC_WML_RDWML(v)))
Kojto	90:cb3d968589d8	4231	/@}/
Kojto	90:cb3d968589d8	4232
Kojto	90:cb3d968589d8	4233	/*!
Kojto	90:cb3d968589d8	4234	* @name Register SDHC_WML, field WRWML[23:16] (RW)
Kojto	90:cb3d968589d8	4235	*
Kojto	90:cb3d968589d8	4236	* The number of words used as the watermark level (FIFO threshold) in a DMA
Kojto	90:cb3d968589d8	4237	* write operation. Also the number of words as a sequence of write bursts in
Kojto	90:cb3d968589d8	4238	* back-to-back mode. The maximum legal value for the write watermark level is 128.
Kojto	90:cb3d968589d8	4239	*/
Kojto	90:cb3d968589d8	4240	/@{/
Kojto	90:cb3d968589d8	4241	#define BP_SDHC_WML_WRWML (16U) /!< Bit position for SDHC_WML_WRWML. /
Kojto	90:cb3d968589d8	4242	#define BM_SDHC_WML_WRWML (0x00FF0000U) /!< Bit mask for SDHC_WML_WRWML. /
Kojto	90:cb3d968589d8	4243	#define BS_SDHC_WML_WRWML (8U) /!< Bit field size in bits for SDHC_WML_WRWML. /
Kojto	90:cb3d968589d8	4244
Kojto	90:cb3d968589d8	4245	/! @brief Read current value of the SDHC_WML_WRWML field. /
Kojto	90:cb3d968589d8	4246	#define BR_SDHC_WML_WRWML(x) (HW_SDHC_WML(x).B.WRWML)
Kojto	90:cb3d968589d8	4247
Kojto	90:cb3d968589d8	4248	/! @brief Format value for bitfield SDHC_WML_WRWML. /
Kojto	90:cb3d968589d8	4249	#define BF_SDHC_WML_WRWML(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_WML_WRWML) & BM_SDHC_WML_WRWML)
Kojto	90:cb3d968589d8	4250
Kojto	90:cb3d968589d8	4251	/! @brief Set the WRWML field to a new value. /
Kojto	90:cb3d968589d8	4252	#define BW_SDHC_WML_WRWML(x, v) (HW_SDHC_WML_WR(x, (HW_SDHC_WML_RD(x) & ~BM_SDHC_WML_WRWML) \| BF_SDHC_WML_WRWML(v)))
Kojto	90:cb3d968589d8	4253	/@}/
Kojto	90:cb3d968589d8	4254
Kojto	90:cb3d968589d8	4255	/*******************************************************************************
Kojto	90:cb3d968589d8	4256	* HW_SDHC_FEVT - Force Event register
Kojto	90:cb3d968589d8	4257	******************************************************************************/
Kojto	90:cb3d968589d8	4258
Kojto	90:cb3d968589d8	4259	/*!
Kojto	90:cb3d968589d8	4260	* @brief HW_SDHC_FEVT - Force Event register (WO)
Kojto	90:cb3d968589d8	4261	*
Kojto	90:cb3d968589d8	4262	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4263	*
Kojto	90:cb3d968589d8	4264	* The Force Event (FEVT) register is not a physically implemented register.
Kojto	90:cb3d968589d8	4265	* Rather, it is an address at which the Interrupt Status register can be written if
Kojto	90:cb3d968589d8	4266	* the corresponding bit of the Interrupt Status Enable register is set. This
Kojto	90:cb3d968589d8	4267	* register is a write only register and writing 0 to it has no effect. Writing 1
Kojto	90:cb3d968589d8	4268	* to this register actually sets the corresponding bit of Interrupt Status
Kojto	90:cb3d968589d8	4269	* register. A read from this register always results in 0's. To change the
Kojto	90:cb3d968589d8	4270	* corresponding status bits in the interrupt status register, make sure to set
Kojto	90:cb3d968589d8	4271	* SYSCTL[IPGEN] so that bus clock is always active. Forcing a card interrupt will generate a
Kojto	90:cb3d968589d8	4272	* short pulse on the DAT[1] line, and the driver may treat this interrupt as a
Kojto	90:cb3d968589d8	4273	* normal interrupt. The interrupt service routine may skip polling the card
Kojto	90:cb3d968589d8	4274	* interrupt factor as the interrupt is selfcleared.
Kojto	90:cb3d968589d8	4275	*/
Kojto	90:cb3d968589d8	4276	typedef union _hw_sdhc_fevt
Kojto	90:cb3d968589d8	4277	{
Kojto	90:cb3d968589d8	4278	uint32_t U;
Kojto	90:cb3d968589d8	4279	struct _hw_sdhc_fevt_bitfields
Kojto	90:cb3d968589d8	4280	{
Kojto	90:cb3d968589d8	4281	uint32_t AC12NE : 1; /*!< [0] Force Event Auto Command 12 Not
Kojto	90:cb3d968589d8	4282	* Executed */
Kojto	90:cb3d968589d8	4283	uint32_t AC12TOE : 1; /*!< [1] Force Event Auto Command 12 Time Out
Kojto	90:cb3d968589d8	4284	* Error */
Kojto	90:cb3d968589d8	4285	uint32_t AC12CE : 1; /!< [2] Force Event Auto Command 12 CRC Error /
Kojto	90:cb3d968589d8	4286	uint32_t AC12EBE : 1; /*!< [3] Force Event Auto Command 12 End Bit
Kojto	90:cb3d968589d8	4287	* Error */
Kojto	90:cb3d968589d8	4288	uint32_t AC12IE : 1; /*!< [4] Force Event Auto Command 12 Index Error
Kojto	90:cb3d968589d8	4289	* */
Kojto	90:cb3d968589d8	4290	uint32_t RESERVED0 : 2; /!< [6:5] /
Kojto	90:cb3d968589d8	4291	uint32_t CNIBAC12E : 1; /*!< [7] Force Event Command Not Executed By
Kojto	90:cb3d968589d8	4292	* Auto Command 12 Error */
Kojto	90:cb3d968589d8	4293	uint32_t RESERVED1 : 8; /!< [15:8] /
Kojto	90:cb3d968589d8	4294	uint32_t CTOE : 1; /!< [16] Force Event Command Time Out Error /
Kojto	90:cb3d968589d8	4295	uint32_t CCE : 1; /!< [17] Force Event Command CRC Error /
Kojto	90:cb3d968589d8	4296	uint32_t CEBE : 1; /!< [18] Force Event Command End Bit Error /
Kojto	90:cb3d968589d8	4297	uint32_t CIE : 1; /!< [19] Force Event Command Index Error /
Kojto	90:cb3d968589d8	4298	uint32_t DTOE : 1; /!< [20] Force Event Data Time Out Error /
Kojto	90:cb3d968589d8	4299	uint32_t DCE : 1; /!< [21] Force Event Data CRC Error /
Kojto	90:cb3d968589d8	4300	uint32_t DEBE : 1; /!< [22] Force Event Data End Bit Error /
Kojto	90:cb3d968589d8	4301	uint32_t RESERVED2 : 1; /!< [23] /
Kojto	90:cb3d968589d8	4302	uint32_t AC12E : 1; /!< [24] Force Event Auto Command 12 Error /
Kojto	90:cb3d968589d8	4303	uint32_t RESERVED3 : 3; /!< [27:25] /
Kojto	90:cb3d968589d8	4304	uint32_t DMAE : 1; /!< [28] Force Event DMA Error /
Kojto	90:cb3d968589d8	4305	uint32_t RESERVED4 : 2; /!< [30:29] /
Kojto	90:cb3d968589d8	4306	uint32_t CINT : 1; /!< [31] Force Event Card Interrupt /
Kojto	90:cb3d968589d8	4307	} B;
Kojto	90:cb3d968589d8	4308	} hw_sdhc_fevt_t;
Kojto	90:cb3d968589d8	4309
Kojto	90:cb3d968589d8	4310	/*!
Kojto	90:cb3d968589d8	4311	* @name Constants and macros for entire SDHC_FEVT register
Kojto	90:cb3d968589d8	4312	*/
Kojto	90:cb3d968589d8	4313	/@{/
Kojto	90:cb3d968589d8	4314	#define HW_SDHC_FEVT_ADDR(x) ((x) + 0x50U)
Kojto	90:cb3d968589d8	4315
Kojto	90:cb3d968589d8	4316	#define HW_SDHC_FEVT(x) ((__O hw_sdhc_fevt_t ) HW_SDHC_FEVT_ADDR(x))
Kojto	90:cb3d968589d8	4317	#define HW_SDHC_FEVT_RD(x) (HW_SDHC_FEVT(x).U)
Kojto	90:cb3d968589d8	4318	#define HW_SDHC_FEVT_WR(x, v) (HW_SDHC_FEVT(x).U = (v))
Kojto	90:cb3d968589d8	4319	/@}/
Kojto	90:cb3d968589d8	4320
Kojto	90:cb3d968589d8	4321	/*
Kojto	90:cb3d968589d8	4322	* Constants & macros for individual SDHC_FEVT bitfields
Kojto	90:cb3d968589d8	4323	*/
Kojto	90:cb3d968589d8	4324
Kojto	90:cb3d968589d8	4325	/*!
Kojto	90:cb3d968589d8	4326	* @name Register SDHC_FEVT, field AC12NE[0] (WORZ)
Kojto	90:cb3d968589d8	4327	*
Kojto	90:cb3d968589d8	4328	* Forces AC12ERR[AC12NE] to be set.
Kojto	90:cb3d968589d8	4329	*/
Kojto	90:cb3d968589d8	4330	/@{/
Kojto	90:cb3d968589d8	4331	#define BP_SDHC_FEVT_AC12NE (0U) /!< Bit position for SDHC_FEVT_AC12NE. /
Kojto	90:cb3d968589d8	4332	#define BM_SDHC_FEVT_AC12NE (0x00000001U) /!< Bit mask for SDHC_FEVT_AC12NE. /
Kojto	90:cb3d968589d8	4333	#define BS_SDHC_FEVT_AC12NE (1U) /!< Bit field size in bits for SDHC_FEVT_AC12NE. /
Kojto	90:cb3d968589d8	4334
Kojto	90:cb3d968589d8	4335	/! @brief Format value for bitfield SDHC_FEVT_AC12NE. /
Kojto	90:cb3d968589d8	4336	#define BF_SDHC_FEVT_AC12NE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12NE) & BM_SDHC_FEVT_AC12NE)
Kojto	90:cb3d968589d8	4337
Kojto	90:cb3d968589d8	4338	/! @brief Set the AC12NE field to a new value. /
Kojto	90:cb3d968589d8	4339	#define BW_SDHC_FEVT_AC12NE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12NE) = (v))
Kojto	90:cb3d968589d8	4340	/@}/
Kojto	90:cb3d968589d8	4341
Kojto	90:cb3d968589d8	4342	/*!
Kojto	90:cb3d968589d8	4343	* @name Register SDHC_FEVT, field AC12TOE[1] (WORZ)
Kojto	90:cb3d968589d8	4344	*
Kojto	90:cb3d968589d8	4345	* Forces AC12ERR[AC12TOE] to be set.
Kojto	90:cb3d968589d8	4346	*/
Kojto	90:cb3d968589d8	4347	/@{/
Kojto	90:cb3d968589d8	4348	#define BP_SDHC_FEVT_AC12TOE (1U) /!< Bit position for SDHC_FEVT_AC12TOE. /
Kojto	90:cb3d968589d8	4349	#define BM_SDHC_FEVT_AC12TOE (0x00000002U) /!< Bit mask for SDHC_FEVT_AC12TOE. /
Kojto	90:cb3d968589d8	4350	#define BS_SDHC_FEVT_AC12TOE (1U) /!< Bit field size in bits for SDHC_FEVT_AC12TOE. /
Kojto	90:cb3d968589d8	4351
Kojto	90:cb3d968589d8	4352	/! @brief Format value for bitfield SDHC_FEVT_AC12TOE. /
Kojto	90:cb3d968589d8	4353	#define BF_SDHC_FEVT_AC12TOE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12TOE) & BM_SDHC_FEVT_AC12TOE)
Kojto	90:cb3d968589d8	4354
Kojto	90:cb3d968589d8	4355	/! @brief Set the AC12TOE field to a new value. /
Kojto	90:cb3d968589d8	4356	#define BW_SDHC_FEVT_AC12TOE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12TOE) = (v))
Kojto	90:cb3d968589d8	4357	/@}/
Kojto	90:cb3d968589d8	4358
Kojto	90:cb3d968589d8	4359	/*!
Kojto	90:cb3d968589d8	4360	* @name Register SDHC_FEVT, field AC12CE[2] (WORZ)
Kojto	90:cb3d968589d8	4361	*
Kojto	90:cb3d968589d8	4362	* Forces AC12ERR[AC12CE] to be set.
Kojto	90:cb3d968589d8	4363	*/
Kojto	90:cb3d968589d8	4364	/@{/
Kojto	90:cb3d968589d8	4365	#define BP_SDHC_FEVT_AC12CE (2U) /!< Bit position for SDHC_FEVT_AC12CE. /
Kojto	90:cb3d968589d8	4366	#define BM_SDHC_FEVT_AC12CE (0x00000004U) /!< Bit mask for SDHC_FEVT_AC12CE. /
Kojto	90:cb3d968589d8	4367	#define BS_SDHC_FEVT_AC12CE (1U) /!< Bit field size in bits for SDHC_FEVT_AC12CE. /
Kojto	90:cb3d968589d8	4368
Kojto	90:cb3d968589d8	4369	/! @brief Format value for bitfield SDHC_FEVT_AC12CE. /
Kojto	90:cb3d968589d8	4370	#define BF_SDHC_FEVT_AC12CE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12CE) & BM_SDHC_FEVT_AC12CE)
Kojto	90:cb3d968589d8	4371
Kojto	90:cb3d968589d8	4372	/! @brief Set the AC12CE field to a new value. /
Kojto	90:cb3d968589d8	4373	#define BW_SDHC_FEVT_AC12CE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12CE) = (v))
Kojto	90:cb3d968589d8	4374	/@}/
Kojto	90:cb3d968589d8	4375
Kojto	90:cb3d968589d8	4376	/*!
Kojto	90:cb3d968589d8	4377	* @name Register SDHC_FEVT, field AC12EBE[3] (WORZ)
Kojto	90:cb3d968589d8	4378	*
Kojto	90:cb3d968589d8	4379	* Forces AC12ERR[AC12EBE] to be set.
Kojto	90:cb3d968589d8	4380	*/
Kojto	90:cb3d968589d8	4381	/@{/
Kojto	90:cb3d968589d8	4382	#define BP_SDHC_FEVT_AC12EBE (3U) /!< Bit position for SDHC_FEVT_AC12EBE. /
Kojto	90:cb3d968589d8	4383	#define BM_SDHC_FEVT_AC12EBE (0x00000008U) /!< Bit mask for SDHC_FEVT_AC12EBE. /
Kojto	90:cb3d968589d8	4384	#define BS_SDHC_FEVT_AC12EBE (1U) /!< Bit field size in bits for SDHC_FEVT_AC12EBE. /
Kojto	90:cb3d968589d8	4385
Kojto	90:cb3d968589d8	4386	/! @brief Format value for bitfield SDHC_FEVT_AC12EBE. /
Kojto	90:cb3d968589d8	4387	#define BF_SDHC_FEVT_AC12EBE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12EBE) & BM_SDHC_FEVT_AC12EBE)
Kojto	90:cb3d968589d8	4388
Kojto	90:cb3d968589d8	4389	/! @brief Set the AC12EBE field to a new value. /
Kojto	90:cb3d968589d8	4390	#define BW_SDHC_FEVT_AC12EBE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12EBE) = (v))
Kojto	90:cb3d968589d8	4391	/@}/
Kojto	90:cb3d968589d8	4392
Kojto	90:cb3d968589d8	4393	/*!
Kojto	90:cb3d968589d8	4394	* @name Register SDHC_FEVT, field AC12IE[4] (WORZ)
Kojto	90:cb3d968589d8	4395	*
Kojto	90:cb3d968589d8	4396	* Forces AC12ERR[AC12IE] to be set.
Kojto	90:cb3d968589d8	4397	*/
Kojto	90:cb3d968589d8	4398	/@{/
Kojto	90:cb3d968589d8	4399	#define BP_SDHC_FEVT_AC12IE (4U) /!< Bit position for SDHC_FEVT_AC12IE. /
Kojto	90:cb3d968589d8	4400	#define BM_SDHC_FEVT_AC12IE (0x00000010U) /!< Bit mask for SDHC_FEVT_AC12IE. /
Kojto	90:cb3d968589d8	4401	#define BS_SDHC_FEVT_AC12IE (1U) /!< Bit field size in bits for SDHC_FEVT_AC12IE. /
Kojto	90:cb3d968589d8	4402
Kojto	90:cb3d968589d8	4403	/! @brief Format value for bitfield SDHC_FEVT_AC12IE. /
Kojto	90:cb3d968589d8	4404	#define BF_SDHC_FEVT_AC12IE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12IE) & BM_SDHC_FEVT_AC12IE)
Kojto	90:cb3d968589d8	4405
Kojto	90:cb3d968589d8	4406	/! @brief Set the AC12IE field to a new value. /
Kojto	90:cb3d968589d8	4407	#define BW_SDHC_FEVT_AC12IE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12IE) = (v))
Kojto	90:cb3d968589d8	4408	/@}/
Kojto	90:cb3d968589d8	4409
Kojto	90:cb3d968589d8	4410	/*!
Kojto	90:cb3d968589d8	4411	* @name Register SDHC_FEVT, field CNIBAC12E[7] (WORZ)
Kojto	90:cb3d968589d8	4412	*
Kojto	90:cb3d968589d8	4413	* Forces AC12ERR[CNIBAC12E] to be set.
Kojto	90:cb3d968589d8	4414	*/
Kojto	90:cb3d968589d8	4415	/@{/
Kojto	90:cb3d968589d8	4416	#define BP_SDHC_FEVT_CNIBAC12E (7U) /!< Bit position for SDHC_FEVT_CNIBAC12E. /
Kojto	90:cb3d968589d8	4417	#define BM_SDHC_FEVT_CNIBAC12E (0x00000080U) /!< Bit mask for SDHC_FEVT_CNIBAC12E. /
Kojto	90:cb3d968589d8	4418	#define BS_SDHC_FEVT_CNIBAC12E (1U) /!< Bit field size in bits for SDHC_FEVT_CNIBAC12E. /
Kojto	90:cb3d968589d8	4419
Kojto	90:cb3d968589d8	4420	/! @brief Format value for bitfield SDHC_FEVT_CNIBAC12E. /
Kojto	90:cb3d968589d8	4421	#define BF_SDHC_FEVT_CNIBAC12E(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CNIBAC12E) & BM_SDHC_FEVT_CNIBAC12E)
Kojto	90:cb3d968589d8	4422
Kojto	90:cb3d968589d8	4423	/! @brief Set the CNIBAC12E field to a new value. /
Kojto	90:cb3d968589d8	4424	#define BW_SDHC_FEVT_CNIBAC12E(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CNIBAC12E) = (v))
Kojto	90:cb3d968589d8	4425	/@}/
Kojto	90:cb3d968589d8	4426
Kojto	90:cb3d968589d8	4427	/*!
Kojto	90:cb3d968589d8	4428	* @name Register SDHC_FEVT, field CTOE[16] (WORZ)
Kojto	90:cb3d968589d8	4429	*
Kojto	90:cb3d968589d8	4430	* Forces IRQSTAT[CTOE] to be set.
Kojto	90:cb3d968589d8	4431	*/
Kojto	90:cb3d968589d8	4432	/@{/
Kojto	90:cb3d968589d8	4433	#define BP_SDHC_FEVT_CTOE (16U) /!< Bit position for SDHC_FEVT_CTOE. /
Kojto	90:cb3d968589d8	4434	#define BM_SDHC_FEVT_CTOE (0x00010000U) /!< Bit mask for SDHC_FEVT_CTOE. /
Kojto	90:cb3d968589d8	4435	#define BS_SDHC_FEVT_CTOE (1U) /!< Bit field size in bits for SDHC_FEVT_CTOE. /
Kojto	90:cb3d968589d8	4436
Kojto	90:cb3d968589d8	4437	/! @brief Format value for bitfield SDHC_FEVT_CTOE. /
Kojto	90:cb3d968589d8	4438	#define BF_SDHC_FEVT_CTOE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CTOE) & BM_SDHC_FEVT_CTOE)
Kojto	90:cb3d968589d8	4439
Kojto	90:cb3d968589d8	4440	/! @brief Set the CTOE field to a new value. /
Kojto	90:cb3d968589d8	4441	#define BW_SDHC_FEVT_CTOE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CTOE) = (v))
Kojto	90:cb3d968589d8	4442	/@}/
Kojto	90:cb3d968589d8	4443
Kojto	90:cb3d968589d8	4444	/*!
Kojto	90:cb3d968589d8	4445	* @name Register SDHC_FEVT, field CCE[17] (WORZ)
Kojto	90:cb3d968589d8	4446	*
Kojto	90:cb3d968589d8	4447	* Forces IRQSTAT[CCE] to be set.
Kojto	90:cb3d968589d8	4448	*/
Kojto	90:cb3d968589d8	4449	/@{/
Kojto	90:cb3d968589d8	4450	#define BP_SDHC_FEVT_CCE (17U) /!< Bit position for SDHC_FEVT_CCE. /
Kojto	90:cb3d968589d8	4451	#define BM_SDHC_FEVT_CCE (0x00020000U) /!< Bit mask for SDHC_FEVT_CCE. /
Kojto	90:cb3d968589d8	4452	#define BS_SDHC_FEVT_CCE (1U) /!< Bit field size in bits for SDHC_FEVT_CCE. /
Kojto	90:cb3d968589d8	4453
Kojto	90:cb3d968589d8	4454	/! @brief Format value for bitfield SDHC_FEVT_CCE. /
Kojto	90:cb3d968589d8	4455	#define BF_SDHC_FEVT_CCE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CCE) & BM_SDHC_FEVT_CCE)
Kojto	90:cb3d968589d8	4456
Kojto	90:cb3d968589d8	4457	/! @brief Set the CCE field to a new value. /
Kojto	90:cb3d968589d8	4458	#define BW_SDHC_FEVT_CCE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CCE) = (v))
Kojto	90:cb3d968589d8	4459	/@}/
Kojto	90:cb3d968589d8	4460
Kojto	90:cb3d968589d8	4461	/*!
Kojto	90:cb3d968589d8	4462	* @name Register SDHC_FEVT, field CEBE[18] (WORZ)
Kojto	90:cb3d968589d8	4463	*
Kojto	90:cb3d968589d8	4464	* Forces IRQSTAT[CEBE] to be set.
Kojto	90:cb3d968589d8	4465	*/
Kojto	90:cb3d968589d8	4466	/@{/
Kojto	90:cb3d968589d8	4467	#define BP_SDHC_FEVT_CEBE (18U) /!< Bit position for SDHC_FEVT_CEBE. /
Kojto	90:cb3d968589d8	4468	#define BM_SDHC_FEVT_CEBE (0x00040000U) /!< Bit mask for SDHC_FEVT_CEBE. /
Kojto	90:cb3d968589d8	4469	#define BS_SDHC_FEVT_CEBE (1U) /!< Bit field size in bits for SDHC_FEVT_CEBE. /
Kojto	90:cb3d968589d8	4470
Kojto	90:cb3d968589d8	4471	/! @brief Format value for bitfield SDHC_FEVT_CEBE. /
Kojto	90:cb3d968589d8	4472	#define BF_SDHC_FEVT_CEBE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CEBE) & BM_SDHC_FEVT_CEBE)
Kojto	90:cb3d968589d8	4473
Kojto	90:cb3d968589d8	4474	/! @brief Set the CEBE field to a new value. /
Kojto	90:cb3d968589d8	4475	#define BW_SDHC_FEVT_CEBE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CEBE) = (v))
Kojto	90:cb3d968589d8	4476	/@}/
Kojto	90:cb3d968589d8	4477
Kojto	90:cb3d968589d8	4478	/*!
Kojto	90:cb3d968589d8	4479	* @name Register SDHC_FEVT, field CIE[19] (WORZ)
Kojto	90:cb3d968589d8	4480	*
Kojto	90:cb3d968589d8	4481	* Forces IRQSTAT[CCE] to be set.
Kojto	90:cb3d968589d8	4482	*/
Kojto	90:cb3d968589d8	4483	/@{/
Kojto	90:cb3d968589d8	4484	#define BP_SDHC_FEVT_CIE (19U) /!< Bit position for SDHC_FEVT_CIE. /
Kojto	90:cb3d968589d8	4485	#define BM_SDHC_FEVT_CIE (0x00080000U) /!< Bit mask for SDHC_FEVT_CIE. /
Kojto	90:cb3d968589d8	4486	#define BS_SDHC_FEVT_CIE (1U) /!< Bit field size in bits for SDHC_FEVT_CIE. /
Kojto	90:cb3d968589d8	4487
Kojto	90:cb3d968589d8	4488	/! @brief Format value for bitfield SDHC_FEVT_CIE. /
Kojto	90:cb3d968589d8	4489	#define BF_SDHC_FEVT_CIE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CIE) & BM_SDHC_FEVT_CIE)
Kojto	90:cb3d968589d8	4490
Kojto	90:cb3d968589d8	4491	/! @brief Set the CIE field to a new value. /
Kojto	90:cb3d968589d8	4492	#define BW_SDHC_FEVT_CIE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CIE) = (v))
Kojto	90:cb3d968589d8	4493	/@}/
Kojto	90:cb3d968589d8	4494
Kojto	90:cb3d968589d8	4495	/*!
Kojto	90:cb3d968589d8	4496	* @name Register SDHC_FEVT, field DTOE[20] (WORZ)
Kojto	90:cb3d968589d8	4497	*
Kojto	90:cb3d968589d8	4498	* Forces IRQSTAT[DTOE] to be set.
Kojto	90:cb3d968589d8	4499	*/
Kojto	90:cb3d968589d8	4500	/@{/
Kojto	90:cb3d968589d8	4501	#define BP_SDHC_FEVT_DTOE (20U) /!< Bit position for SDHC_FEVT_DTOE. /
Kojto	90:cb3d968589d8	4502	#define BM_SDHC_FEVT_DTOE (0x00100000U) /!< Bit mask for SDHC_FEVT_DTOE. /
Kojto	90:cb3d968589d8	4503	#define BS_SDHC_FEVT_DTOE (1U) /!< Bit field size in bits for SDHC_FEVT_DTOE. /
Kojto	90:cb3d968589d8	4504
Kojto	90:cb3d968589d8	4505	/! @brief Format value for bitfield SDHC_FEVT_DTOE. /
Kojto	90:cb3d968589d8	4506	#define BF_SDHC_FEVT_DTOE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_DTOE) & BM_SDHC_FEVT_DTOE)
Kojto	90:cb3d968589d8	4507
Kojto	90:cb3d968589d8	4508	/! @brief Set the DTOE field to a new value. /
Kojto	90:cb3d968589d8	4509	#define BW_SDHC_FEVT_DTOE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_DTOE) = (v))
Kojto	90:cb3d968589d8	4510	/@}/
Kojto	90:cb3d968589d8	4511
Kojto	90:cb3d968589d8	4512	/*!
Kojto	90:cb3d968589d8	4513	* @name Register SDHC_FEVT, field DCE[21] (WORZ)
Kojto	90:cb3d968589d8	4514	*
Kojto	90:cb3d968589d8	4515	* Forces IRQSTAT[DCE] to be set.
Kojto	90:cb3d968589d8	4516	*/
Kojto	90:cb3d968589d8	4517	/@{/
Kojto	90:cb3d968589d8	4518	#define BP_SDHC_FEVT_DCE (21U) /!< Bit position for SDHC_FEVT_DCE. /
Kojto	90:cb3d968589d8	4519	#define BM_SDHC_FEVT_DCE (0x00200000U) /!< Bit mask for SDHC_FEVT_DCE. /
Kojto	90:cb3d968589d8	4520	#define BS_SDHC_FEVT_DCE (1U) /!< Bit field size in bits for SDHC_FEVT_DCE. /
Kojto	90:cb3d968589d8	4521
Kojto	90:cb3d968589d8	4522	/! @brief Format value for bitfield SDHC_FEVT_DCE. /
Kojto	90:cb3d968589d8	4523	#define BF_SDHC_FEVT_DCE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_DCE) & BM_SDHC_FEVT_DCE)
Kojto	90:cb3d968589d8	4524
Kojto	90:cb3d968589d8	4525	/! @brief Set the DCE field to a new value. /
Kojto	90:cb3d968589d8	4526	#define BW_SDHC_FEVT_DCE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_DCE) = (v))
Kojto	90:cb3d968589d8	4527	/@}/
Kojto	90:cb3d968589d8	4528
Kojto	90:cb3d968589d8	4529	/*!
Kojto	90:cb3d968589d8	4530	* @name Register SDHC_FEVT, field DEBE[22] (WORZ)
Kojto	90:cb3d968589d8	4531	*
Kojto	90:cb3d968589d8	4532	* Forces IRQSTAT[DEBE] to be set.
Kojto	90:cb3d968589d8	4533	*/
Kojto	90:cb3d968589d8	4534	/@{/
Kojto	90:cb3d968589d8	4535	#define BP_SDHC_FEVT_DEBE (22U) /!< Bit position for SDHC_FEVT_DEBE. /
Kojto	90:cb3d968589d8	4536	#define BM_SDHC_FEVT_DEBE (0x00400000U) /!< Bit mask for SDHC_FEVT_DEBE. /
Kojto	90:cb3d968589d8	4537	#define BS_SDHC_FEVT_DEBE (1U) /!< Bit field size in bits for SDHC_FEVT_DEBE. /
Kojto	90:cb3d968589d8	4538
Kojto	90:cb3d968589d8	4539	/! @brief Format value for bitfield SDHC_FEVT_DEBE. /
Kojto	90:cb3d968589d8	4540	#define BF_SDHC_FEVT_DEBE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_DEBE) & BM_SDHC_FEVT_DEBE)
Kojto	90:cb3d968589d8	4541
Kojto	90:cb3d968589d8	4542	/! @brief Set the DEBE field to a new value. /
Kojto	90:cb3d968589d8	4543	#define BW_SDHC_FEVT_DEBE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_DEBE) = (v))
Kojto	90:cb3d968589d8	4544	/@}/
Kojto	90:cb3d968589d8	4545
Kojto	90:cb3d968589d8	4546	/*!
Kojto	90:cb3d968589d8	4547	* @name Register SDHC_FEVT, field AC12E[24] (WORZ)
Kojto	90:cb3d968589d8	4548	*
Kojto	90:cb3d968589d8	4549	* Forces IRQSTAT[AC12E] to be set.
Kojto	90:cb3d968589d8	4550	*/
Kojto	90:cb3d968589d8	4551	/@{/
Kojto	90:cb3d968589d8	4552	#define BP_SDHC_FEVT_AC12E (24U) /!< Bit position for SDHC_FEVT_AC12E. /
Kojto	90:cb3d968589d8	4553	#define BM_SDHC_FEVT_AC12E (0x01000000U) /!< Bit mask for SDHC_FEVT_AC12E. /
Kojto	90:cb3d968589d8	4554	#define BS_SDHC_FEVT_AC12E (1U) /!< Bit field size in bits for SDHC_FEVT_AC12E. /
Kojto	90:cb3d968589d8	4555
Kojto	90:cb3d968589d8	4556	/! @brief Format value for bitfield SDHC_FEVT_AC12E. /
Kojto	90:cb3d968589d8	4557	#define BF_SDHC_FEVT_AC12E(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12E) & BM_SDHC_FEVT_AC12E)
Kojto	90:cb3d968589d8	4558
Kojto	90:cb3d968589d8	4559	/! @brief Set the AC12E field to a new value. /
Kojto	90:cb3d968589d8	4560	#define BW_SDHC_FEVT_AC12E(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12E) = (v))
Kojto	90:cb3d968589d8	4561	/@}/
Kojto	90:cb3d968589d8	4562
Kojto	90:cb3d968589d8	4563	/*!
Kojto	90:cb3d968589d8	4564	* @name Register SDHC_FEVT, field DMAE[28] (WORZ)
Kojto	90:cb3d968589d8	4565	*
Kojto	90:cb3d968589d8	4566	* Forces the DMAE bit of Interrupt Status Register to be set.
Kojto	90:cb3d968589d8	4567	*/
Kojto	90:cb3d968589d8	4568	/@{/
Kojto	90:cb3d968589d8	4569	#define BP_SDHC_FEVT_DMAE (28U) /!< Bit position for SDHC_FEVT_DMAE. /
Kojto	90:cb3d968589d8	4570	#define BM_SDHC_FEVT_DMAE (0x10000000U) /!< Bit mask for SDHC_FEVT_DMAE. /
Kojto	90:cb3d968589d8	4571	#define BS_SDHC_FEVT_DMAE (1U) /!< Bit field size in bits for SDHC_FEVT_DMAE. /
Kojto	90:cb3d968589d8	4572
Kojto	90:cb3d968589d8	4573	/! @brief Format value for bitfield SDHC_FEVT_DMAE. /
Kojto	90:cb3d968589d8	4574	#define BF_SDHC_FEVT_DMAE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_DMAE) & BM_SDHC_FEVT_DMAE)
Kojto	90:cb3d968589d8	4575
Kojto	90:cb3d968589d8	4576	/! @brief Set the DMAE field to a new value. /
Kojto	90:cb3d968589d8	4577	#define BW_SDHC_FEVT_DMAE(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_DMAE) = (v))
Kojto	90:cb3d968589d8	4578	/@}/
Kojto	90:cb3d968589d8	4579
Kojto	90:cb3d968589d8	4580	/*!
Kojto	90:cb3d968589d8	4581	* @name Register SDHC_FEVT, field CINT[31] (WORZ)
Kojto	90:cb3d968589d8	4582	*
Kojto	90:cb3d968589d8	4583	* Writing 1 to this bit generates a short low-level pulse on the internal
Kojto	90:cb3d968589d8	4584	* DAT[1] line, as if a self-clearing interrupt was received from the external card.
Kojto	90:cb3d968589d8	4585	* If enabled, the CINT bit will be set and the interrupt service routine may
Kojto	90:cb3d968589d8	4586	* treat this interrupt as a normal interrupt from the external card.
Kojto	90:cb3d968589d8	4587	*/
Kojto	90:cb3d968589d8	4588	/@{/
Kojto	90:cb3d968589d8	4589	#define BP_SDHC_FEVT_CINT (31U) /!< Bit position for SDHC_FEVT_CINT. /
Kojto	90:cb3d968589d8	4590	#define BM_SDHC_FEVT_CINT (0x80000000U) /!< Bit mask for SDHC_FEVT_CINT. /
Kojto	90:cb3d968589d8	4591	#define BS_SDHC_FEVT_CINT (1U) /!< Bit field size in bits for SDHC_FEVT_CINT. /
Kojto	90:cb3d968589d8	4592
Kojto	90:cb3d968589d8	4593	/! @brief Format value for bitfield SDHC_FEVT_CINT. /
Kojto	90:cb3d968589d8	4594	#define BF_SDHC_FEVT_CINT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CINT) & BM_SDHC_FEVT_CINT)
Kojto	90:cb3d968589d8	4595
Kojto	90:cb3d968589d8	4596	/! @brief Set the CINT field to a new value. /
Kojto	90:cb3d968589d8	4597	#define BW_SDHC_FEVT_CINT(x, v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CINT) = (v))
Kojto	90:cb3d968589d8	4598	/@}/
Kojto	90:cb3d968589d8	4599
Kojto	90:cb3d968589d8	4600	/*******************************************************************************
Kojto	90:cb3d968589d8	4601	* HW_SDHC_ADMAES - ADMA Error Status register
Kojto	90:cb3d968589d8	4602	******************************************************************************/
Kojto	90:cb3d968589d8	4603
Kojto	90:cb3d968589d8	4604	/*!
Kojto	90:cb3d968589d8	4605	* @brief HW_SDHC_ADMAES - ADMA Error Status register (RO)
Kojto	90:cb3d968589d8	4606	*
Kojto	90:cb3d968589d8	4607	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4608	*
Kojto	90:cb3d968589d8	4609	* When an ADMA error interrupt has occurred, the ADMA Error States field in
Kojto	90:cb3d968589d8	4610	* this register holds the ADMA state and the ADMA System Address register holds the
Kojto	90:cb3d968589d8	4611	* address around the error descriptor. For recovering from this error, the host
Kojto	90:cb3d968589d8	4612	* driver requires the ADMA state to identify the error descriptor address as
Kojto	90:cb3d968589d8	4613	* follows: ST_STOP: Previous location set in the ADMA System Address register is
Kojto	90:cb3d968589d8	4614	* the error descriptor address. ST_FDS: Current location set in the ADMA System
Kojto	90:cb3d968589d8	4615	* Address register is the error descriptor address. ST_CADR: This state is never
Kojto	90:cb3d968589d8	4616	* set because it only increments the descriptor pointer and doesn't generate an
Kojto	90:cb3d968589d8	4617	* ADMA error. ST_TFR: Previous location set in the ADMA System Address register
Kojto	90:cb3d968589d8	4618	* is the error descriptor address. In case of a write operation, the host driver
Kojto	90:cb3d968589d8	4619	* must use the ACMD22 to get the number of the written block, rather than using
Kojto	90:cb3d968589d8	4620	* this information, because unwritten data may exist in the host controller.
Kojto	90:cb3d968589d8	4621	* The host controller generates the ADMA error interrupt when it detects invalid
Kojto	90:cb3d968589d8	4622	* descriptor data (valid = 0) in the ST_FDS state. The host driver can
Kojto	90:cb3d968589d8	4623	* distinguish this error by reading the valid bit of the error descriptor. ADMA Error
Kojto	90:cb3d968589d8	4624	* State coding D01-D00 ADMA Error State when error has occurred Contents of ADMA
Kojto	90:cb3d968589d8	4625	* System Address register 00 ST_STOP (Stop DMA) Holds the address of the next
Kojto	90:cb3d968589d8	4626	* executable descriptor command 01 ST_FDS (fetch descriptor) Holds the valid
Kojto	90:cb3d968589d8	4627	* descriptor address 10 ST_CADR (change address) No ADMA error is generated 11 ST_TFR
Kojto	90:cb3d968589d8	4628	* (Transfer Data) Holds the address of the next executable descriptor command
Kojto	90:cb3d968589d8	4629	*/
Kojto	90:cb3d968589d8	4630	typedef union _hw_sdhc_admaes
Kojto	90:cb3d968589d8	4631	{
Kojto	90:cb3d968589d8	4632	uint32_t U;
Kojto	90:cb3d968589d8	4633	struct _hw_sdhc_admaes_bitfields
Kojto	90:cb3d968589d8	4634	{
Kojto	90:cb3d968589d8	4635	uint32_t ADMAES : 2; /*!< [1:0] ADMA Error State (When ADMA Error Is
Kojto	90:cb3d968589d8	4636	* Occurred.) */
Kojto	90:cb3d968589d8	4637	uint32_t ADMALME : 1; /!< [2] ADMA Length Mismatch Error /
Kojto	90:cb3d968589d8	4638	uint32_t ADMADCE : 1; /!< [3] ADMA Descriptor Error /
Kojto	90:cb3d968589d8	4639	uint32_t RESERVED0 : 28; /!< [31:4] /
Kojto	90:cb3d968589d8	4640	} B;
Kojto	90:cb3d968589d8	4641	} hw_sdhc_admaes_t;
Kojto	90:cb3d968589d8	4642
Kojto	90:cb3d968589d8	4643	/*!
Kojto	90:cb3d968589d8	4644	* @name Constants and macros for entire SDHC_ADMAES register
Kojto	90:cb3d968589d8	4645	*/
Kojto	90:cb3d968589d8	4646	/@{/
Kojto	90:cb3d968589d8	4647	#define HW_SDHC_ADMAES_ADDR(x) ((x) + 0x54U)
Kojto	90:cb3d968589d8	4648
Kojto	90:cb3d968589d8	4649	#define HW_SDHC_ADMAES(x) ((__I hw_sdhc_admaes_t ) HW_SDHC_ADMAES_ADDR(x))
Kojto	90:cb3d968589d8	4650	#define HW_SDHC_ADMAES_RD(x) (HW_SDHC_ADMAES(x).U)
Kojto	90:cb3d968589d8	4651	/@}/
Kojto	90:cb3d968589d8	4652
Kojto	90:cb3d968589d8	4653	/*
Kojto	90:cb3d968589d8	4654	* Constants & macros for individual SDHC_ADMAES bitfields
Kojto	90:cb3d968589d8	4655	*/
Kojto	90:cb3d968589d8	4656
Kojto	90:cb3d968589d8	4657	/*!
Kojto	90:cb3d968589d8	4658	* @name Register SDHC_ADMAES, field ADMAES[1:0] (RO)
Kojto	90:cb3d968589d8	4659	*
Kojto	90:cb3d968589d8	4660	* Indicates the state of the ADMA when an error has occurred during an ADMA
Kojto	90:cb3d968589d8	4661	* data transfer.
Kojto	90:cb3d968589d8	4662	*/
Kojto	90:cb3d968589d8	4663	/@{/
Kojto	90:cb3d968589d8	4664	#define BP_SDHC_ADMAES_ADMAES (0U) /!< Bit position for SDHC_ADMAES_ADMAES. /
Kojto	90:cb3d968589d8	4665	#define BM_SDHC_ADMAES_ADMAES (0x00000003U) /!< Bit mask for SDHC_ADMAES_ADMAES. /
Kojto	90:cb3d968589d8	4666	#define BS_SDHC_ADMAES_ADMAES (2U) /!< Bit field size in bits for SDHC_ADMAES_ADMAES. /
Kojto	90:cb3d968589d8	4667
Kojto	90:cb3d968589d8	4668	/! @brief Read current value of the SDHC_ADMAES_ADMAES field. /
Kojto	90:cb3d968589d8	4669	#define BR_SDHC_ADMAES_ADMAES(x) (HW_SDHC_ADMAES(x).B.ADMAES)
Kojto	90:cb3d968589d8	4670	/@}/
Kojto	90:cb3d968589d8	4671
Kojto	90:cb3d968589d8	4672	/*!
Kojto	90:cb3d968589d8	4673	* @name Register SDHC_ADMAES, field ADMALME[2] (RO)
Kojto	90:cb3d968589d8	4674	*
Kojto	90:cb3d968589d8	4675	* This error occurs in the following 2 cases: While the block count enable is
Kojto	90:cb3d968589d8	4676	* being set, the total data length specified by the descriptor table is different
Kojto	90:cb3d968589d8	4677	* from that specified by the block count and block length. Total data length
Kojto	90:cb3d968589d8	4678	* can not be divided by the block length.
Kojto	90:cb3d968589d8	4679	*
Kojto	90:cb3d968589d8	4680	* Values:
Kojto	90:cb3d968589d8	4681	* - 0 - No error.
Kojto	90:cb3d968589d8	4682	* - 1 - Error.
Kojto	90:cb3d968589d8	4683	*/
Kojto	90:cb3d968589d8	4684	/@{/
Kojto	90:cb3d968589d8	4685	#define BP_SDHC_ADMAES_ADMALME (2U) /!< Bit position for SDHC_ADMAES_ADMALME. /
Kojto	90:cb3d968589d8	4686	#define BM_SDHC_ADMAES_ADMALME (0x00000004U) /!< Bit mask for SDHC_ADMAES_ADMALME. /
Kojto	90:cb3d968589d8	4687	#define BS_SDHC_ADMAES_ADMALME (1U) /!< Bit field size in bits for SDHC_ADMAES_ADMALME. /
Kojto	90:cb3d968589d8	4688
Kojto	90:cb3d968589d8	4689	/! @brief Read current value of the SDHC_ADMAES_ADMALME field. /
Kojto	90:cb3d968589d8	4690	#define BR_SDHC_ADMAES_ADMALME(x) (BITBAND_ACCESS32(HW_SDHC_ADMAES_ADDR(x), BP_SDHC_ADMAES_ADMALME))
Kojto	90:cb3d968589d8	4691	/@}/
Kojto	90:cb3d968589d8	4692
Kojto	90:cb3d968589d8	4693	/*!
Kojto	90:cb3d968589d8	4694	* @name Register SDHC_ADMAES, field ADMADCE[3] (RO)
Kojto	90:cb3d968589d8	4695	*
Kojto	90:cb3d968589d8	4696	* This error occurs when an invalid descriptor is fetched by ADMA.
Kojto	90:cb3d968589d8	4697	*
Kojto	90:cb3d968589d8	4698	* Values:
Kojto	90:cb3d968589d8	4699	* - 0 - No error.
Kojto	90:cb3d968589d8	4700	* - 1 - Error.
Kojto	90:cb3d968589d8	4701	*/
Kojto	90:cb3d968589d8	4702	/@{/
Kojto	90:cb3d968589d8	4703	#define BP_SDHC_ADMAES_ADMADCE (3U) /!< Bit position for SDHC_ADMAES_ADMADCE. /
Kojto	90:cb3d968589d8	4704	#define BM_SDHC_ADMAES_ADMADCE (0x00000008U) /!< Bit mask for SDHC_ADMAES_ADMADCE. /
Kojto	90:cb3d968589d8	4705	#define BS_SDHC_ADMAES_ADMADCE (1U) /!< Bit field size in bits for SDHC_ADMAES_ADMADCE. /
Kojto	90:cb3d968589d8	4706
Kojto	90:cb3d968589d8	4707	/! @brief Read current value of the SDHC_ADMAES_ADMADCE field. /
Kojto	90:cb3d968589d8	4708	#define BR_SDHC_ADMAES_ADMADCE(x) (BITBAND_ACCESS32(HW_SDHC_ADMAES_ADDR(x), BP_SDHC_ADMAES_ADMADCE))
Kojto	90:cb3d968589d8	4709	/@}/
Kojto	90:cb3d968589d8	4710
Kojto	90:cb3d968589d8	4711	/*******************************************************************************
Kojto	90:cb3d968589d8	4712	* HW_SDHC_ADSADDR - ADMA System Addressregister
Kojto	90:cb3d968589d8	4713	******************************************************************************/
Kojto	90:cb3d968589d8	4714
Kojto	90:cb3d968589d8	4715	/*!
Kojto	90:cb3d968589d8	4716	* @brief HW_SDHC_ADSADDR - ADMA System Addressregister (RW)
Kojto	90:cb3d968589d8	4717	*
Kojto	90:cb3d968589d8	4718	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4719	*
Kojto	90:cb3d968589d8	4720	* This register contains the physical system memory address used for ADMA
Kojto	90:cb3d968589d8	4721	* transfers.
Kojto	90:cb3d968589d8	4722	*/
Kojto	90:cb3d968589d8	4723	typedef union _hw_sdhc_adsaddr
Kojto	90:cb3d968589d8	4724	{
Kojto	90:cb3d968589d8	4725	uint32_t U;
Kojto	90:cb3d968589d8	4726	struct _hw_sdhc_adsaddr_bitfields
Kojto	90:cb3d968589d8	4727	{
Kojto	90:cb3d968589d8	4728	uint32_t RESERVED0 : 2; /!< [1:0] /
Kojto	90:cb3d968589d8	4729	uint32_t ADSADDR : 30; /!< [31:2] ADMA System Address /
Kojto	90:cb3d968589d8	4730	} B;
Kojto	90:cb3d968589d8	4731	} hw_sdhc_adsaddr_t;
Kojto	90:cb3d968589d8	4732
Kojto	90:cb3d968589d8	4733	/*!
Kojto	90:cb3d968589d8	4734	* @name Constants and macros for entire SDHC_ADSADDR register
Kojto	90:cb3d968589d8	4735	*/
Kojto	90:cb3d968589d8	4736	/@{/
Kojto	90:cb3d968589d8	4737	#define HW_SDHC_ADSADDR_ADDR(x) ((x) + 0x58U)
Kojto	90:cb3d968589d8	4738
Kojto	90:cb3d968589d8	4739	#define HW_SDHC_ADSADDR(x) ((__IO hw_sdhc_adsaddr_t ) HW_SDHC_ADSADDR_ADDR(x))
Kojto	90:cb3d968589d8	4740	#define HW_SDHC_ADSADDR_RD(x) (HW_SDHC_ADSADDR(x).U)
Kojto	90:cb3d968589d8	4741	#define HW_SDHC_ADSADDR_WR(x, v) (HW_SDHC_ADSADDR(x).U = (v))
Kojto	90:cb3d968589d8	4742	#define HW_SDHC_ADSADDR_SET(x, v) (HW_SDHC_ADSADDR_WR(x, HW_SDHC_ADSADDR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	4743	#define HW_SDHC_ADSADDR_CLR(x, v) (HW_SDHC_ADSADDR_WR(x, HW_SDHC_ADSADDR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	4744	#define HW_SDHC_ADSADDR_TOG(x, v) (HW_SDHC_ADSADDR_WR(x, HW_SDHC_ADSADDR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	4745	/@}/
Kojto	90:cb3d968589d8	4746
Kojto	90:cb3d968589d8	4747	/*
Kojto	90:cb3d968589d8	4748	* Constants & macros for individual SDHC_ADSADDR bitfields
Kojto	90:cb3d968589d8	4749	*/
Kojto	90:cb3d968589d8	4750
Kojto	90:cb3d968589d8	4751	/*!
Kojto	90:cb3d968589d8	4752	* @name Register SDHC_ADSADDR, field ADSADDR[31:2] (RW)
Kojto	90:cb3d968589d8	4753	*
Kojto	90:cb3d968589d8	4754	* Holds the word address of the executing command in the descriptor table. At
Kojto	90:cb3d968589d8	4755	* the start of ADMA, the host driver shall set the start address of the
Kojto	90:cb3d968589d8	4756	* Descriptor table. The ADMA engine increments this register address whenever fetching a
Kojto	90:cb3d968589d8	4757	* descriptor command. When the ADMA is stopped at the block gap, this register
Kojto	90:cb3d968589d8	4758	* indicates the address of the next executable descriptor command. When the ADMA
Kojto	90:cb3d968589d8	4759	* error interrupt is generated, this register shall hold the valid descriptor
Kojto	90:cb3d968589d8	4760	* address depending on the ADMA state. The lower 2 bits of this register is tied
Kojto	90:cb3d968589d8	4761	* to '0' so the ADMA address is always word-aligned. Because this register
Kojto	90:cb3d968589d8	4762	* supports dynamic address reflecting, when TC bit is set, it automatically alters the
Kojto	90:cb3d968589d8	4763	* value of internal address counter, so SW cannot change this register when TC
Kojto	90:cb3d968589d8	4764	* bit is set.
Kojto	90:cb3d968589d8	4765	*/
Kojto	90:cb3d968589d8	4766	/@{/
Kojto	90:cb3d968589d8	4767	#define BP_SDHC_ADSADDR_ADSADDR (2U) /!< Bit position for SDHC_ADSADDR_ADSADDR. /
Kojto	90:cb3d968589d8	4768	#define BM_SDHC_ADSADDR_ADSADDR (0xFFFFFFFCU) /!< Bit mask for SDHC_ADSADDR_ADSADDR. /
Kojto	90:cb3d968589d8	4769	#define BS_SDHC_ADSADDR_ADSADDR (30U) /!< Bit field size in bits for SDHC_ADSADDR_ADSADDR. /
Kojto	90:cb3d968589d8	4770
Kojto	90:cb3d968589d8	4771	/! @brief Read current value of the SDHC_ADSADDR_ADSADDR field. /
Kojto	90:cb3d968589d8	4772	#define BR_SDHC_ADSADDR_ADSADDR(x) (HW_SDHC_ADSADDR(x).B.ADSADDR)
Kojto	90:cb3d968589d8	4773
Kojto	90:cb3d968589d8	4774	/! @brief Format value for bitfield SDHC_ADSADDR_ADSADDR. /
Kojto	90:cb3d968589d8	4775	#define BF_SDHC_ADSADDR_ADSADDR(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_ADSADDR_ADSADDR) & BM_SDHC_ADSADDR_ADSADDR)
Kojto	90:cb3d968589d8	4776
Kojto	90:cb3d968589d8	4777	/! @brief Set the ADSADDR field to a new value. /
Kojto	90:cb3d968589d8	4778	#define BW_SDHC_ADSADDR_ADSADDR(x, v) (HW_SDHC_ADSADDR_WR(x, (HW_SDHC_ADSADDR_RD(x) & ~BM_SDHC_ADSADDR_ADSADDR) \| BF_SDHC_ADSADDR_ADSADDR(v)))
Kojto	90:cb3d968589d8	4779	/@}/
Kojto	90:cb3d968589d8	4780
Kojto	90:cb3d968589d8	4781	/*******************************************************************************
Kojto	90:cb3d968589d8	4782	* HW_SDHC_VENDOR - Vendor Specific register
Kojto	90:cb3d968589d8	4783	******************************************************************************/
Kojto	90:cb3d968589d8	4784
Kojto	90:cb3d968589d8	4785	/*!
Kojto	90:cb3d968589d8	4786	* @brief HW_SDHC_VENDOR - Vendor Specific register (RW)
Kojto	90:cb3d968589d8	4787	*
Kojto	90:cb3d968589d8	4788	* Reset value: 0x00000001U
Kojto	90:cb3d968589d8	4789	*
Kojto	90:cb3d968589d8	4790	* This register contains the vendor-specific control/status register.
Kojto	90:cb3d968589d8	4791	*/
Kojto	90:cb3d968589d8	4792	typedef union _hw_sdhc_vendor
Kojto	90:cb3d968589d8	4793	{
Kojto	90:cb3d968589d8	4794	uint32_t U;
Kojto	90:cb3d968589d8	4795	struct _hw_sdhc_vendor_bitfields
Kojto	90:cb3d968589d8	4796	{
Kojto	90:cb3d968589d8	4797	uint32_t EXTDMAEN : 1; /!< [0] External DMA Request Enable /
Kojto	90:cb3d968589d8	4798	uint32_t EXBLKNU : 1; /*!< [1] Exact Block Number Block Read Enable
Kojto	90:cb3d968589d8	4799	* For SDIO CMD53 */
Kojto	90:cb3d968589d8	4800	uint32_t RESERVED0 : 14; /!< [15:2] /
Kojto	90:cb3d968589d8	4801	uint32_t INTSTVAL : 8; /!< [23:16] Internal State Value /
Kojto	90:cb3d968589d8	4802	uint32_t RESERVED1 : 8; /!< [31:24] /
Kojto	90:cb3d968589d8	4803	} B;
Kojto	90:cb3d968589d8	4804	} hw_sdhc_vendor_t;
Kojto	90:cb3d968589d8	4805
Kojto	90:cb3d968589d8	4806	/*!
Kojto	90:cb3d968589d8	4807	* @name Constants and macros for entire SDHC_VENDOR register
Kojto	90:cb3d968589d8	4808	*/
Kojto	90:cb3d968589d8	4809	/@{/
Kojto	90:cb3d968589d8	4810	#define HW_SDHC_VENDOR_ADDR(x) ((x) + 0xC0U)
Kojto	90:cb3d968589d8	4811
Kojto	90:cb3d968589d8	4812	#define HW_SDHC_VENDOR(x) ((__IO hw_sdhc_vendor_t ) HW_SDHC_VENDOR_ADDR(x))
Kojto	90:cb3d968589d8	4813	#define HW_SDHC_VENDOR_RD(x) (HW_SDHC_VENDOR(x).U)
Kojto	90:cb3d968589d8	4814	#define HW_SDHC_VENDOR_WR(x, v) (HW_SDHC_VENDOR(x).U = (v))
Kojto	90:cb3d968589d8	4815	#define HW_SDHC_VENDOR_SET(x, v) (HW_SDHC_VENDOR_WR(x, HW_SDHC_VENDOR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	4816	#define HW_SDHC_VENDOR_CLR(x, v) (HW_SDHC_VENDOR_WR(x, HW_SDHC_VENDOR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	4817	#define HW_SDHC_VENDOR_TOG(x, v) (HW_SDHC_VENDOR_WR(x, HW_SDHC_VENDOR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	4818	/@}/
Kojto	90:cb3d968589d8	4819
Kojto	90:cb3d968589d8	4820	/*
Kojto	90:cb3d968589d8	4821	* Constants & macros for individual SDHC_VENDOR bitfields
Kojto	90:cb3d968589d8	4822	*/
Kojto	90:cb3d968589d8	4823
Kojto	90:cb3d968589d8	4824	/*!
Kojto	90:cb3d968589d8	4825	* @name Register SDHC_VENDOR, field EXTDMAEN[0] (RW)
Kojto	90:cb3d968589d8	4826	*
Kojto	90:cb3d968589d8	4827	* Enables the request to external DMA. When the internal DMA (either simple DMA
Kojto	90:cb3d968589d8	4828	* or advanced DMA) is not in use, and this bit is set, SDHC will send out DMA
Kojto	90:cb3d968589d8	4829	* request when the internal buffer is ready. This bit is particularly useful when
Kojto	90:cb3d968589d8	4830	* transferring data by CPU polling mode, and it is not allowed to send out the
Kojto	90:cb3d968589d8	4831	* external DMA request. By default, this bit is set.
Kojto	90:cb3d968589d8	4832	*
Kojto	90:cb3d968589d8	4833	* Values:
Kojto	90:cb3d968589d8	4834	* - 0 - In any scenario, SDHC does not send out the external DMA request.
Kojto	90:cb3d968589d8	4835	* - 1 - When internal DMA is not active, the external DMA request will be sent
Kojto	90:cb3d968589d8	4836	* out.
Kojto	90:cb3d968589d8	4837	*/
Kojto	90:cb3d968589d8	4838	/@{/
Kojto	90:cb3d968589d8	4839	#define BP_SDHC_VENDOR_EXTDMAEN (0U) /!< Bit position for SDHC_VENDOR_EXTDMAEN. /
Kojto	90:cb3d968589d8	4840	#define BM_SDHC_VENDOR_EXTDMAEN (0x00000001U) /!< Bit mask for SDHC_VENDOR_EXTDMAEN. /
Kojto	90:cb3d968589d8	4841	#define BS_SDHC_VENDOR_EXTDMAEN (1U) /!< Bit field size in bits for SDHC_VENDOR_EXTDMAEN. /
Kojto	90:cb3d968589d8	4842
Kojto	90:cb3d968589d8	4843	/! @brief Read current value of the SDHC_VENDOR_EXTDMAEN field. /
Kojto	90:cb3d968589d8	4844	#define BR_SDHC_VENDOR_EXTDMAEN(x) (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR(x), BP_SDHC_VENDOR_EXTDMAEN))
Kojto	90:cb3d968589d8	4845
Kojto	90:cb3d968589d8	4846	/! @brief Format value for bitfield SDHC_VENDOR_EXTDMAEN. /
Kojto	90:cb3d968589d8	4847	#define BF_SDHC_VENDOR_EXTDMAEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_VENDOR_EXTDMAEN) & BM_SDHC_VENDOR_EXTDMAEN)
Kojto	90:cb3d968589d8	4848
Kojto	90:cb3d968589d8	4849	/! @brief Set the EXTDMAEN field to a new value. /
Kojto	90:cb3d968589d8	4850	#define BW_SDHC_VENDOR_EXTDMAEN(x, v) (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR(x), BP_SDHC_VENDOR_EXTDMAEN) = (v))
Kojto	90:cb3d968589d8	4851	/@}/
Kojto	90:cb3d968589d8	4852
Kojto	90:cb3d968589d8	4853	/*!
Kojto	90:cb3d968589d8	4854	* @name Register SDHC_VENDOR, field EXBLKNU[1] (RW)
Kojto	90:cb3d968589d8	4855	*
Kojto	90:cb3d968589d8	4856	* This bit must be set before S/W issues CMD53 multi-block read with exact
Kojto	90:cb3d968589d8	4857	* block number. This bit must not be set if the CMD53 multi-block read is not exact
Kojto	90:cb3d968589d8	4858	* block number.
Kojto	90:cb3d968589d8	4859	*
Kojto	90:cb3d968589d8	4860	* Values:
Kojto	90:cb3d968589d8	4861	* - 0 - None exact block read.
Kojto	90:cb3d968589d8	4862	* - 1 - Exact block read for SDIO CMD53.
Kojto	90:cb3d968589d8	4863	*/
Kojto	90:cb3d968589d8	4864	/@{/
Kojto	90:cb3d968589d8	4865	#define BP_SDHC_VENDOR_EXBLKNU (1U) /!< Bit position for SDHC_VENDOR_EXBLKNU. /
Kojto	90:cb3d968589d8	4866	#define BM_SDHC_VENDOR_EXBLKNU (0x00000002U) /!< Bit mask for SDHC_VENDOR_EXBLKNU. /
Kojto	90:cb3d968589d8	4867	#define BS_SDHC_VENDOR_EXBLKNU (1U) /!< Bit field size in bits for SDHC_VENDOR_EXBLKNU. /
Kojto	90:cb3d968589d8	4868
Kojto	90:cb3d968589d8	4869	/! @brief Read current value of the SDHC_VENDOR_EXBLKNU field. /
Kojto	90:cb3d968589d8	4870	#define BR_SDHC_VENDOR_EXBLKNU(x) (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR(x), BP_SDHC_VENDOR_EXBLKNU))
Kojto	90:cb3d968589d8	4871
Kojto	90:cb3d968589d8	4872	/! @brief Format value for bitfield SDHC_VENDOR_EXBLKNU. /
Kojto	90:cb3d968589d8	4873	#define BF_SDHC_VENDOR_EXBLKNU(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_VENDOR_EXBLKNU) & BM_SDHC_VENDOR_EXBLKNU)
Kojto	90:cb3d968589d8	4874
Kojto	90:cb3d968589d8	4875	/! @brief Set the EXBLKNU field to a new value. /
Kojto	90:cb3d968589d8	4876	#define BW_SDHC_VENDOR_EXBLKNU(x, v) (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR(x), BP_SDHC_VENDOR_EXBLKNU) = (v))
Kojto	90:cb3d968589d8	4877	/@}/
Kojto	90:cb3d968589d8	4878
Kojto	90:cb3d968589d8	4879	/*!
Kojto	90:cb3d968589d8	4880	* @name Register SDHC_VENDOR, field INTSTVAL[23:16] (RO)
Kojto	90:cb3d968589d8	4881	*
Kojto	90:cb3d968589d8	4882	* Internal state value, reflecting the corresponding state value selected by
Kojto	90:cb3d968589d8	4883	* Debug Select field. This field is read-only and write to this field does not
Kojto	90:cb3d968589d8	4884	* have effect.
Kojto	90:cb3d968589d8	4885	*/
Kojto	90:cb3d968589d8	4886	/@{/
Kojto	90:cb3d968589d8	4887	#define BP_SDHC_VENDOR_INTSTVAL (16U) /!< Bit position for SDHC_VENDOR_INTSTVAL. /
Kojto	90:cb3d968589d8	4888	#define BM_SDHC_VENDOR_INTSTVAL (0x00FF0000U) /!< Bit mask for SDHC_VENDOR_INTSTVAL. /
Kojto	90:cb3d968589d8	4889	#define BS_SDHC_VENDOR_INTSTVAL (8U) /!< Bit field size in bits for SDHC_VENDOR_INTSTVAL. /
Kojto	90:cb3d968589d8	4890
Kojto	90:cb3d968589d8	4891	/! @brief Read current value of the SDHC_VENDOR_INTSTVAL field. /
Kojto	90:cb3d968589d8	4892	#define BR_SDHC_VENDOR_INTSTVAL(x) (HW_SDHC_VENDOR(x).B.INTSTVAL)
Kojto	90:cb3d968589d8	4893	/@}/
Kojto	90:cb3d968589d8	4894
Kojto	90:cb3d968589d8	4895	/*******************************************************************************
Kojto	90:cb3d968589d8	4896	* HW_SDHC_MMCBOOT - MMC Boot register
Kojto	90:cb3d968589d8	4897	******************************************************************************/
Kojto	90:cb3d968589d8	4898
Kojto	90:cb3d968589d8	4899	/*!
Kojto	90:cb3d968589d8	4900	* @brief HW_SDHC_MMCBOOT - MMC Boot register (RW)
Kojto	90:cb3d968589d8	4901	*
Kojto	90:cb3d968589d8	4902	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	4903	*
Kojto	90:cb3d968589d8	4904	* This register contains the MMC fast boot control register.
Kojto	90:cb3d968589d8	4905	*/
Kojto	90:cb3d968589d8	4906	typedef union _hw_sdhc_mmcboot
Kojto	90:cb3d968589d8	4907	{
Kojto	90:cb3d968589d8	4908	uint32_t U;
Kojto	90:cb3d968589d8	4909	struct _hw_sdhc_mmcboot_bitfields
Kojto	90:cb3d968589d8	4910	{
Kojto	90:cb3d968589d8	4911	uint32_t DTOCVACK : 4; /!< [3:0] Boot ACK Time Out Counter Value /
Kojto	90:cb3d968589d8	4912	uint32_t BOOTACK : 1; /!< [4] Boot Ack Mode Select /
Kojto	90:cb3d968589d8	4913	uint32_t BOOTMODE : 1; /!< [5] Boot Mode Select /
Kojto	90:cb3d968589d8	4914	uint32_t BOOTEN : 1; /!< [6] Boot Mode Enable /
Kojto	90:cb3d968589d8	4915	uint32_t AUTOSABGEN : 1; /!< [7] /
Kojto	90:cb3d968589d8	4916	uint32_t RESERVED0 : 8; /!< [15:8] /
Kojto	90:cb3d968589d8	4917	uint32_t BOOTBLKCNT : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	4918	} B;
Kojto	90:cb3d968589d8	4919	} hw_sdhc_mmcboot_t;
Kojto	90:cb3d968589d8	4920
Kojto	90:cb3d968589d8	4921	/*!
Kojto	90:cb3d968589d8	4922	* @name Constants and macros for entire SDHC_MMCBOOT register
Kojto	90:cb3d968589d8	4923	*/
Kojto	90:cb3d968589d8	4924	/@{/
Kojto	90:cb3d968589d8	4925	#define HW_SDHC_MMCBOOT_ADDR(x) ((x) + 0xC4U)
Kojto	90:cb3d968589d8	4926
Kojto	90:cb3d968589d8	4927	#define HW_SDHC_MMCBOOT(x) ((__IO hw_sdhc_mmcboot_t ) HW_SDHC_MMCBOOT_ADDR(x))
Kojto	90:cb3d968589d8	4928	#define HW_SDHC_MMCBOOT_RD(x) (HW_SDHC_MMCBOOT(x).U)
Kojto	90:cb3d968589d8	4929	#define HW_SDHC_MMCBOOT_WR(x, v) (HW_SDHC_MMCBOOT(x).U = (v))
Kojto	90:cb3d968589d8	4930	#define HW_SDHC_MMCBOOT_SET(x, v) (HW_SDHC_MMCBOOT_WR(x, HW_SDHC_MMCBOOT_RD(x) \| (v)))
Kojto	90:cb3d968589d8	4931	#define HW_SDHC_MMCBOOT_CLR(x, v) (HW_SDHC_MMCBOOT_WR(x, HW_SDHC_MMCBOOT_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	4932	#define HW_SDHC_MMCBOOT_TOG(x, v) (HW_SDHC_MMCBOOT_WR(x, HW_SDHC_MMCBOOT_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	4933	/@}/
Kojto	90:cb3d968589d8	4934
Kojto	90:cb3d968589d8	4935	/*
Kojto	90:cb3d968589d8	4936	* Constants & macros for individual SDHC_MMCBOOT bitfields
Kojto	90:cb3d968589d8	4937	*/
Kojto	90:cb3d968589d8	4938
Kojto	90:cb3d968589d8	4939	/*!
Kojto	90:cb3d968589d8	4940	* @name Register SDHC_MMCBOOT, field DTOCVACK[3:0] (RW)
Kojto	90:cb3d968589d8	4941	*
Kojto	90:cb3d968589d8	4942	* Values:
Kojto	90:cb3d968589d8	4943	* - 0000 - SDCLK x 2^8
Kojto	90:cb3d968589d8	4944	* - 0001 - SDCLK x 2^9
Kojto	90:cb3d968589d8	4945	* - 0010 - SDCLK x 2^10
Kojto	90:cb3d968589d8	4946	* - 0011 - SDCLK x 2^11
Kojto	90:cb3d968589d8	4947	* - 0100 - SDCLK x 2^12
Kojto	90:cb3d968589d8	4948	* - 0101 - SDCLK x 2^13
Kojto	90:cb3d968589d8	4949	* - 0110 - SDCLK x 2^14
Kojto	90:cb3d968589d8	4950	* - 0111 - SDCLK x 2^15
Kojto	90:cb3d968589d8	4951	* - 1110 - SDCLK x 2^22
Kojto	90:cb3d968589d8	4952	* - 1111 - Reserved
Kojto	90:cb3d968589d8	4953	*/
Kojto	90:cb3d968589d8	4954	/@{/
Kojto	90:cb3d968589d8	4955	#define BP_SDHC_MMCBOOT_DTOCVACK (0U) /!< Bit position for SDHC_MMCBOOT_DTOCVACK. /
Kojto	90:cb3d968589d8	4956	#define BM_SDHC_MMCBOOT_DTOCVACK (0x0000000FU) /!< Bit mask for SDHC_MMCBOOT_DTOCVACK. /
Kojto	90:cb3d968589d8	4957	#define BS_SDHC_MMCBOOT_DTOCVACK (4U) /!< Bit field size in bits for SDHC_MMCBOOT_DTOCVACK. /
Kojto	90:cb3d968589d8	4958
Kojto	90:cb3d968589d8	4959	/! @brief Read current value of the SDHC_MMCBOOT_DTOCVACK field. /
Kojto	90:cb3d968589d8	4960	#define BR_SDHC_MMCBOOT_DTOCVACK(x) (HW_SDHC_MMCBOOT(x).B.DTOCVACK)
Kojto	90:cb3d968589d8	4961
Kojto	90:cb3d968589d8	4962	/! @brief Format value for bitfield SDHC_MMCBOOT_DTOCVACK. /
Kojto	90:cb3d968589d8	4963	#define BF_SDHC_MMCBOOT_DTOCVACK(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_DTOCVACK) & BM_SDHC_MMCBOOT_DTOCVACK)
Kojto	90:cb3d968589d8	4964
Kojto	90:cb3d968589d8	4965	/! @brief Set the DTOCVACK field to a new value. /
Kojto	90:cb3d968589d8	4966	#define BW_SDHC_MMCBOOT_DTOCVACK(x, v) (HW_SDHC_MMCBOOT_WR(x, (HW_SDHC_MMCBOOT_RD(x) & ~BM_SDHC_MMCBOOT_DTOCVACK) \| BF_SDHC_MMCBOOT_DTOCVACK(v)))
Kojto	90:cb3d968589d8	4967	/@}/
Kojto	90:cb3d968589d8	4968
Kojto	90:cb3d968589d8	4969	/*!
Kojto	90:cb3d968589d8	4970	* @name Register SDHC_MMCBOOT, field BOOTACK[4] (RW)
Kojto	90:cb3d968589d8	4971	*
Kojto	90:cb3d968589d8	4972	* Values:
Kojto	90:cb3d968589d8	4973	* - 0 - No ack.
Kojto	90:cb3d968589d8	4974	* - 1 - Ack.
Kojto	90:cb3d968589d8	4975	*/
Kojto	90:cb3d968589d8	4976	/@{/
Kojto	90:cb3d968589d8	4977	#define BP_SDHC_MMCBOOT_BOOTACK (4U) /!< Bit position for SDHC_MMCBOOT_BOOTACK. /
Kojto	90:cb3d968589d8	4978	#define BM_SDHC_MMCBOOT_BOOTACK (0x00000010U) /!< Bit mask for SDHC_MMCBOOT_BOOTACK. /
Kojto	90:cb3d968589d8	4979	#define BS_SDHC_MMCBOOT_BOOTACK (1U) /!< Bit field size in bits for SDHC_MMCBOOT_BOOTACK. /
Kojto	90:cb3d968589d8	4980
Kojto	90:cb3d968589d8	4981	/! @brief Read current value of the SDHC_MMCBOOT_BOOTACK field. /
Kojto	90:cb3d968589d8	4982	#define BR_SDHC_MMCBOOT_BOOTACK(x) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTACK))
Kojto	90:cb3d968589d8	4983
Kojto	90:cb3d968589d8	4984	/! @brief Format value for bitfield SDHC_MMCBOOT_BOOTACK. /
Kojto	90:cb3d968589d8	4985	#define BF_SDHC_MMCBOOT_BOOTACK(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_BOOTACK) & BM_SDHC_MMCBOOT_BOOTACK)
Kojto	90:cb3d968589d8	4986
Kojto	90:cb3d968589d8	4987	/! @brief Set the BOOTACK field to a new value. /
Kojto	90:cb3d968589d8	4988	#define BW_SDHC_MMCBOOT_BOOTACK(x, v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTACK) = (v))
Kojto	90:cb3d968589d8	4989	/@}/
Kojto	90:cb3d968589d8	4990
Kojto	90:cb3d968589d8	4991	/*!
Kojto	90:cb3d968589d8	4992	* @name Register SDHC_MMCBOOT, field BOOTMODE[5] (RW)
Kojto	90:cb3d968589d8	4993	*
Kojto	90:cb3d968589d8	4994	* Values:
Kojto	90:cb3d968589d8	4995	* - 0 - Normal boot.
Kojto	90:cb3d968589d8	4996	* - 1 - Alternative boot.
Kojto	90:cb3d968589d8	4997	*/
Kojto	90:cb3d968589d8	4998	/@{/
Kojto	90:cb3d968589d8	4999	#define BP_SDHC_MMCBOOT_BOOTMODE (5U) /!< Bit position for SDHC_MMCBOOT_BOOTMODE. /
Kojto	90:cb3d968589d8	5000	#define BM_SDHC_MMCBOOT_BOOTMODE (0x00000020U) /!< Bit mask for SDHC_MMCBOOT_BOOTMODE. /
Kojto	90:cb3d968589d8	5001	#define BS_SDHC_MMCBOOT_BOOTMODE (1U) /!< Bit field size in bits for SDHC_MMCBOOT_BOOTMODE. /
Kojto	90:cb3d968589d8	5002
Kojto	90:cb3d968589d8	5003	/! @brief Read current value of the SDHC_MMCBOOT_BOOTMODE field. /
Kojto	90:cb3d968589d8	5004	#define BR_SDHC_MMCBOOT_BOOTMODE(x) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTMODE))
Kojto	90:cb3d968589d8	5005
Kojto	90:cb3d968589d8	5006	/! @brief Format value for bitfield SDHC_MMCBOOT_BOOTMODE. /
Kojto	90:cb3d968589d8	5007	#define BF_SDHC_MMCBOOT_BOOTMODE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_BOOTMODE) & BM_SDHC_MMCBOOT_BOOTMODE)
Kojto	90:cb3d968589d8	5008
Kojto	90:cb3d968589d8	5009	/! @brief Set the BOOTMODE field to a new value. /
Kojto	90:cb3d968589d8	5010	#define BW_SDHC_MMCBOOT_BOOTMODE(x, v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTMODE) = (v))
Kojto	90:cb3d968589d8	5011	/@}/
Kojto	90:cb3d968589d8	5012
Kojto	90:cb3d968589d8	5013	/*!
Kojto	90:cb3d968589d8	5014	* @name Register SDHC_MMCBOOT, field BOOTEN[6] (RW)
Kojto	90:cb3d968589d8	5015	*
Kojto	90:cb3d968589d8	5016	* Values:
Kojto	90:cb3d968589d8	5017	* - 0 - Fast boot disable.
Kojto	90:cb3d968589d8	5018	* - 1 - Fast boot enable.
Kojto	90:cb3d968589d8	5019	*/
Kojto	90:cb3d968589d8	5020	/@{/
Kojto	90:cb3d968589d8	5021	#define BP_SDHC_MMCBOOT_BOOTEN (6U) /!< Bit position for SDHC_MMCBOOT_BOOTEN. /
Kojto	90:cb3d968589d8	5022	#define BM_SDHC_MMCBOOT_BOOTEN (0x00000040U) /!< Bit mask for SDHC_MMCBOOT_BOOTEN. /
Kojto	90:cb3d968589d8	5023	#define BS_SDHC_MMCBOOT_BOOTEN (1U) /!< Bit field size in bits for SDHC_MMCBOOT_BOOTEN. /
Kojto	90:cb3d968589d8	5024
Kojto	90:cb3d968589d8	5025	/! @brief Read current value of the SDHC_MMCBOOT_BOOTEN field. /
Kojto	90:cb3d968589d8	5026	#define BR_SDHC_MMCBOOT_BOOTEN(x) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTEN))
Kojto	90:cb3d968589d8	5027
Kojto	90:cb3d968589d8	5028	/! @brief Format value for bitfield SDHC_MMCBOOT_BOOTEN. /
Kojto	90:cb3d968589d8	5029	#define BF_SDHC_MMCBOOT_BOOTEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_BOOTEN) & BM_SDHC_MMCBOOT_BOOTEN)
Kojto	90:cb3d968589d8	5030
Kojto	90:cb3d968589d8	5031	/! @brief Set the BOOTEN field to a new value. /
Kojto	90:cb3d968589d8	5032	#define BW_SDHC_MMCBOOT_BOOTEN(x, v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTEN) = (v))
Kojto	90:cb3d968589d8	5033	/@}/
Kojto	90:cb3d968589d8	5034
Kojto	90:cb3d968589d8	5035	/*!
Kojto	90:cb3d968589d8	5036	* @name Register SDHC_MMCBOOT, field AUTOSABGEN[7] (RW)
Kojto	90:cb3d968589d8	5037	*
Kojto	90:cb3d968589d8	5038	* When boot, enable auto stop at block gap function. This function will be
Kojto	90:cb3d968589d8	5039	* triggered, and host will stop at block gap when received card block cnt is equal
Kojto	90:cb3d968589d8	5040	* to BOOTBLKCNT.
Kojto	90:cb3d968589d8	5041	*/
Kojto	90:cb3d968589d8	5042	/@{/
Kojto	90:cb3d968589d8	5043	#define BP_SDHC_MMCBOOT_AUTOSABGEN (7U) /!< Bit position for SDHC_MMCBOOT_AUTOSABGEN. /
Kojto	90:cb3d968589d8	5044	#define BM_SDHC_MMCBOOT_AUTOSABGEN (0x00000080U) /!< Bit mask for SDHC_MMCBOOT_AUTOSABGEN. /
Kojto	90:cb3d968589d8	5045	#define BS_SDHC_MMCBOOT_AUTOSABGEN (1U) /!< Bit field size in bits for SDHC_MMCBOOT_AUTOSABGEN. /
Kojto	90:cb3d968589d8	5046
Kojto	90:cb3d968589d8	5047	/! @brief Read current value of the SDHC_MMCBOOT_AUTOSABGEN field. /
Kojto	90:cb3d968589d8	5048	#define BR_SDHC_MMCBOOT_AUTOSABGEN(x) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_AUTOSABGEN))
Kojto	90:cb3d968589d8	5049
Kojto	90:cb3d968589d8	5050	/! @brief Format value for bitfield SDHC_MMCBOOT_AUTOSABGEN. /
Kojto	90:cb3d968589d8	5051	#define BF_SDHC_MMCBOOT_AUTOSABGEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_AUTOSABGEN) & BM_SDHC_MMCBOOT_AUTOSABGEN)
Kojto	90:cb3d968589d8	5052
Kojto	90:cb3d968589d8	5053	/! @brief Set the AUTOSABGEN field to a new value. /
Kojto	90:cb3d968589d8	5054	#define BW_SDHC_MMCBOOT_AUTOSABGEN(x, v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_AUTOSABGEN) = (v))
Kojto	90:cb3d968589d8	5055	/@}/
Kojto	90:cb3d968589d8	5056
Kojto	90:cb3d968589d8	5057	/*!
Kojto	90:cb3d968589d8	5058	* @name Register SDHC_MMCBOOT, field BOOTBLKCNT[31:16] (RW)
Kojto	90:cb3d968589d8	5059	*
Kojto	90:cb3d968589d8	5060	* Defines the stop at block gap value of automatic mode. When received card
Kojto	90:cb3d968589d8	5061	* block cnt is equal to BOOTBLKCNT and AUTOSABGEN is 1, then stop at block gap.
Kojto	90:cb3d968589d8	5062	*/
Kojto	90:cb3d968589d8	5063	/@{/
Kojto	90:cb3d968589d8	5064	#define BP_SDHC_MMCBOOT_BOOTBLKCNT (16U) /!< Bit position for SDHC_MMCBOOT_BOOTBLKCNT. /
Kojto	90:cb3d968589d8	5065	#define BM_SDHC_MMCBOOT_BOOTBLKCNT (0xFFFF0000U) /!< Bit mask for SDHC_MMCBOOT_BOOTBLKCNT. /
Kojto	90:cb3d968589d8	5066	#define BS_SDHC_MMCBOOT_BOOTBLKCNT (16U) /!< Bit field size in bits for SDHC_MMCBOOT_BOOTBLKCNT. /
Kojto	90:cb3d968589d8	5067
Kojto	90:cb3d968589d8	5068	/! @brief Read current value of the SDHC_MMCBOOT_BOOTBLKCNT field. /
Kojto	90:cb3d968589d8	5069	#define BR_SDHC_MMCBOOT_BOOTBLKCNT(x) (HW_SDHC_MMCBOOT(x).B.BOOTBLKCNT)
Kojto	90:cb3d968589d8	5070
Kojto	90:cb3d968589d8	5071	/! @brief Format value for bitfield SDHC_MMCBOOT_BOOTBLKCNT. /
Kojto	90:cb3d968589d8	5072	#define BF_SDHC_MMCBOOT_BOOTBLKCNT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_BOOTBLKCNT) & BM_SDHC_MMCBOOT_BOOTBLKCNT)
Kojto	90:cb3d968589d8	5073
Kojto	90:cb3d968589d8	5074	/! @brief Set the BOOTBLKCNT field to a new value. /
Kojto	90:cb3d968589d8	5075	#define BW_SDHC_MMCBOOT_BOOTBLKCNT(x, v) (HW_SDHC_MMCBOOT_WR(x, (HW_SDHC_MMCBOOT_RD(x) & ~BM_SDHC_MMCBOOT_BOOTBLKCNT) \| BF_SDHC_MMCBOOT_BOOTBLKCNT(v)))
Kojto	90:cb3d968589d8	5076	/@}/
Kojto	90:cb3d968589d8	5077
Kojto	90:cb3d968589d8	5078	/*******************************************************************************
Kojto	90:cb3d968589d8	5079	* HW_SDHC_HOSTVER - Host Controller Version
Kojto	90:cb3d968589d8	5080	******************************************************************************/
Kojto	90:cb3d968589d8	5081
Kojto	90:cb3d968589d8	5082	/*!
Kojto	90:cb3d968589d8	5083	* @brief HW_SDHC_HOSTVER - Host Controller Version (RO)
Kojto	90:cb3d968589d8	5084	*
Kojto	90:cb3d968589d8	5085	* Reset value: 0x00001201U
Kojto	90:cb3d968589d8	5086	*
Kojto	90:cb3d968589d8	5087	* This register contains the vendor host controller version information. All
Kojto	90:cb3d968589d8	5088	* bits are read only and will read the same as the power-reset value.
Kojto	90:cb3d968589d8	5089	*/
Kojto	90:cb3d968589d8	5090	typedef union _hw_sdhc_hostver
Kojto	90:cb3d968589d8	5091	{
Kojto	90:cb3d968589d8	5092	uint32_t U;
Kojto	90:cb3d968589d8	5093	struct _hw_sdhc_hostver_bitfields
Kojto	90:cb3d968589d8	5094	{
Kojto	90:cb3d968589d8	5095	uint32_t SVN : 8; /!< [7:0] Specification Version Number /
Kojto	90:cb3d968589d8	5096	uint32_t VVN : 8; /!< [15:8] Vendor Version Number /
Kojto	90:cb3d968589d8	5097	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	5098	} B;
Kojto	90:cb3d968589d8	5099	} hw_sdhc_hostver_t;
Kojto	90:cb3d968589d8	5100
Kojto	90:cb3d968589d8	5101	/*!
Kojto	90:cb3d968589d8	5102	* @name Constants and macros for entire SDHC_HOSTVER register
Kojto	90:cb3d968589d8	5103	*/
Kojto	90:cb3d968589d8	5104	/@{/
Kojto	90:cb3d968589d8	5105	#define HW_SDHC_HOSTVER_ADDR(x) ((x) + 0xFCU)
Kojto	90:cb3d968589d8	5106
Kojto	90:cb3d968589d8	5107	#define HW_SDHC_HOSTVER(x) ((__I hw_sdhc_hostver_t ) HW_SDHC_HOSTVER_ADDR(x))
Kojto	90:cb3d968589d8	5108	#define HW_SDHC_HOSTVER_RD(x) (HW_SDHC_HOSTVER(x).U)
Kojto	90:cb3d968589d8	5109	/@}/
Kojto	90:cb3d968589d8	5110
Kojto	90:cb3d968589d8	5111	/*
Kojto	90:cb3d968589d8	5112	* Constants & macros for individual SDHC_HOSTVER bitfields
Kojto	90:cb3d968589d8	5113	*/
Kojto	90:cb3d968589d8	5114
Kojto	90:cb3d968589d8	5115	/*!
Kojto	90:cb3d968589d8	5116	* @name Register SDHC_HOSTVER, field SVN[7:0] (RO)
Kojto	90:cb3d968589d8	5117	*
Kojto	90:cb3d968589d8	5118	* These status bits indicate the host controller specification version.
Kojto	90:cb3d968589d8	5119	*
Kojto	90:cb3d968589d8	5120	* Values:
Kojto	90:cb3d968589d8	5121	* - 1 - SD host specification version 2.0, supports test event register and
Kojto	90:cb3d968589d8	5122	* ADMA.
Kojto	90:cb3d968589d8	5123	*/
Kojto	90:cb3d968589d8	5124	/@{/
Kojto	90:cb3d968589d8	5125	#define BP_SDHC_HOSTVER_SVN (0U) /!< Bit position for SDHC_HOSTVER_SVN. /
Kojto	90:cb3d968589d8	5126	#define BM_SDHC_HOSTVER_SVN (0x000000FFU) /!< Bit mask for SDHC_HOSTVER_SVN. /
Kojto	90:cb3d968589d8	5127	#define BS_SDHC_HOSTVER_SVN (8U) /!< Bit field size in bits for SDHC_HOSTVER_SVN. /
Kojto	90:cb3d968589d8	5128
Kojto	90:cb3d968589d8	5129	/! @brief Read current value of the SDHC_HOSTVER_SVN field. /
Kojto	90:cb3d968589d8	5130	#define BR_SDHC_HOSTVER_SVN(x) (HW_SDHC_HOSTVER(x).B.SVN)
Kojto	90:cb3d968589d8	5131	/@}/
Kojto	90:cb3d968589d8	5132
Kojto	90:cb3d968589d8	5133	/*!
Kojto	90:cb3d968589d8	5134	* @name Register SDHC_HOSTVER, field VVN[15:8] (RO)
Kojto	90:cb3d968589d8	5135	*
Kojto	90:cb3d968589d8	5136	* These status bits are reserved for the vendor version number. The host driver
Kojto	90:cb3d968589d8	5137	* shall not use this status.
Kojto	90:cb3d968589d8	5138	*
Kojto	90:cb3d968589d8	5139	* Values:
Kojto	90:cb3d968589d8	5140	* - 0 - Freescale SDHC version 1.0
Kojto	90:cb3d968589d8	5141	* - 10000 - Freescale SDHC version 2.0
Kojto	90:cb3d968589d8	5142	* - 10001 - Freescale SDHC version 2.1
Kojto	90:cb3d968589d8	5143	* - 10010 - Freescale SDHC version 2.2
Kojto	90:cb3d968589d8	5144	*/
Kojto	90:cb3d968589d8	5145	/@{/
Kojto	90:cb3d968589d8	5146	#define BP_SDHC_HOSTVER_VVN (8U) /!< Bit position for SDHC_HOSTVER_VVN. /
Kojto	90:cb3d968589d8	5147	#define BM_SDHC_HOSTVER_VVN (0x0000FF00U) /!< Bit mask for SDHC_HOSTVER_VVN. /
Kojto	90:cb3d968589d8	5148	#define BS_SDHC_HOSTVER_VVN (8U) /!< Bit field size in bits for SDHC_HOSTVER_VVN. /
Kojto	90:cb3d968589d8	5149
Kojto	90:cb3d968589d8	5150	/! @brief Read current value of the SDHC_HOSTVER_VVN field. /
Kojto	90:cb3d968589d8	5151	#define BR_SDHC_HOSTVER_VVN(x) (HW_SDHC_HOSTVER(x).B.VVN)
Kojto	90:cb3d968589d8	5152	/@}/
Kojto	90:cb3d968589d8	5153
Kojto	90:cb3d968589d8	5154	/*******************************************************************************
Kojto	90:cb3d968589d8	5155	* hw_sdhc_t - module struct
Kojto	90:cb3d968589d8	5156	******************************************************************************/
Kojto	90:cb3d968589d8	5157	/*!
Kojto	90:cb3d968589d8	5158	* @brief All SDHC module registers.
Kojto	90:cb3d968589d8	5159	*/
Kojto	90:cb3d968589d8	5160	#pragma pack(1)
Kojto	90:cb3d968589d8	5161	typedef struct _hw_sdhc
Kojto	90:cb3d968589d8	5162	{
Kojto	90:cb3d968589d8	5163	__IO hw_sdhc_dsaddr_t DSADDR; /!< [0x0] DMA System Address register /
Kojto	90:cb3d968589d8	5164	__IO hw_sdhc_blkattr_t BLKATTR; /!< [0x4] Block Attributes register /
Kojto	90:cb3d968589d8	5165	__IO hw_sdhc_cmdarg_t CMDARG; /!< [0x8] Command Argument register /
Kojto	90:cb3d968589d8	5166	__IO hw_sdhc_xfertyp_t XFERTYP; /!< [0xC] Transfer Type register /
Kojto	90:cb3d968589d8	5167	__I hw_sdhc_cmdrsp0_t CMDRSP0; /!< [0x10] Command Response 0 /
Kojto	90:cb3d968589d8	5168	__I hw_sdhc_cmdrsp1_t CMDRSP1; /!< [0x14] Command Response 1 /
Kojto	90:cb3d968589d8	5169	__I hw_sdhc_cmdrsp2_t CMDRSP2; /!< [0x18] Command Response 2 /
Kojto	90:cb3d968589d8	5170	__I hw_sdhc_cmdrsp3_t CMDRSP3; /!< [0x1C] Command Response 3 /
Kojto	90:cb3d968589d8	5171	__IO hw_sdhc_datport_t DATPORT; /!< [0x20] Buffer Data Port register /
Kojto	90:cb3d968589d8	5172	__I hw_sdhc_prsstat_t PRSSTAT; /!< [0x24] Present State register /
Kojto	90:cb3d968589d8	5173	__IO hw_sdhc_proctl_t PROCTL; /!< [0x28] Protocol Control register /
Kojto	90:cb3d968589d8	5174	__IO hw_sdhc_sysctl_t SYSCTL; /!< [0x2C] System Control register /
Kojto	90:cb3d968589d8	5175	__IO hw_sdhc_irqstat_t IRQSTAT; /!< [0x30] Interrupt Status register /
Kojto	90:cb3d968589d8	5176	__IO hw_sdhc_irqstaten_t IRQSTATEN; /!< [0x34] Interrupt Status Enable register /
Kojto	90:cb3d968589d8	5177	__IO hw_sdhc_irqsigen_t IRQSIGEN; /!< [0x38] Interrupt Signal Enable register /
Kojto	90:cb3d968589d8	5178	__I hw_sdhc_ac12err_t AC12ERR; /!< [0x3C] Auto CMD12 Error Status Register /
Kojto	90:cb3d968589d8	5179	__I hw_sdhc_htcapblt_t HTCAPBLT; /!< [0x40] Host Controller Capabilities /
Kojto	90:cb3d968589d8	5180	__IO hw_sdhc_wml_t WML; /!< [0x44] Watermark Level Register /
Kojto	90:cb3d968589d8	5181	uint8_t _reserved0[8];
Kojto	90:cb3d968589d8	5182	__O hw_sdhc_fevt_t FEVT; /!< [0x50] Force Event register /
Kojto	90:cb3d968589d8	5183	__I hw_sdhc_admaes_t ADMAES; /!< [0x54] ADMA Error Status register /
Kojto	90:cb3d968589d8	5184	__IO hw_sdhc_adsaddr_t ADSADDR; /!< [0x58] ADMA System Addressregister /
Kojto	90:cb3d968589d8	5185	uint8_t _reserved1[100];
Kojto	90:cb3d968589d8	5186	__IO hw_sdhc_vendor_t VENDOR; /!< [0xC0] Vendor Specific register /
Kojto	90:cb3d968589d8	5187	__IO hw_sdhc_mmcboot_t MMCBOOT; /!< [0xC4] MMC Boot register /
Kojto	90:cb3d968589d8	5188	uint8_t _reserved2[52];
Kojto	90:cb3d968589d8	5189	__I hw_sdhc_hostver_t HOSTVER; /!< [0xFC] Host Controller Version /
Kojto	90:cb3d968589d8	5190	} hw_sdhc_t;
Kojto	90:cb3d968589d8	5191	#pragma pack()
Kojto	90:cb3d968589d8	5192
Kojto	90:cb3d968589d8	5193	/! @brief Macro to access all SDHC registers. /
Kojto	90:cb3d968589d8	5194	/! @param x SDHC module instance base address. /
Kojto	90:cb3d968589d8	5195	/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto	90:cb3d968589d8	5196	* use the '&' operator, like <code>&HW_SDHC(SDHC_BASE)</code>. */
Kojto	90:cb3d968589d8	5197	#define HW_SDHC(x) ((hw_sdhc_t )(x))
Kojto	90:cb3d968589d8	5198
Kojto	90:cb3d968589d8	5199	#endif /* __HW_SDHC_REGISTERS_H__ */
Kojto	90:cb3d968589d8	5200	/* EOF */