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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rng.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:
Kojto
Date:
Wed Aug 05 13:16:35 2015 +0100
Revision:
104:b9ad9a133dc7
Parent:
90:cb3d968589d8 
Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /*
Kojto 90:cb3d968589d8 2 ** ###################################################################
Kojto 90:cb3d968589d8 3 ** Compilers: Keil ARM C/C++ Compiler
Kojto 90:cb3d968589d8 4 ** Freescale C/C++ for Embedded ARM
Kojto 90:cb3d968589d8 5 ** GNU C Compiler
Kojto 90:cb3d968589d8 6 ** IAR ANSI C/C++ Compiler for ARM
Kojto 90:cb3d968589d8 7 **
Kojto 90:cb3d968589d8 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto 90:cb3d968589d8 9 ** Version: rev. 2.5, 2014-02-10
Kojto 90:cb3d968589d8 10 ** Build: b140604
Kojto 90:cb3d968589d8 11 **
Kojto 90:cb3d968589d8 12 ** Abstract:
Kojto 90:cb3d968589d8 13 ** Extension to the CMSIS register access layer header.
Kojto 90:cb3d968589d8 14 **
Kojto 90:cb3d968589d8 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto 90:cb3d968589d8 16 ** All rights reserved.
Kojto 90:cb3d968589d8 17 **
Kojto 90:cb3d968589d8 18 ** Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 19 ** are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 20 **
Kojto 90:cb3d968589d8 21 ** o Redistributions of source code must retain the above copyright notice, this list
Kojto 90:cb3d968589d8 22 ** of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 23 **
Kojto 90:cb3d968589d8 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto 90:cb3d968589d8 25 ** list of conditions and the following disclaimer in the documentation and/or
Kojto 90:cb3d968589d8 26 ** other materials provided with the distribution.
Kojto 90:cb3d968589d8 27 **
Kojto 90:cb3d968589d8 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto 90:cb3d968589d8 29 ** contributors may be used to endorse or promote products derived from this
Kojto 90:cb3d968589d8 30 ** software without specific prior written permission.
Kojto 90:cb3d968589d8 31 **
Kojto 90:cb3d968589d8 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 90:cb3d968589d8 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 90:cb3d968589d8 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 90:cb3d968589d8 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 90:cb3d968589d8 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 90:cb3d968589d8 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 90:cb3d968589d8 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 90:cb3d968589d8 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 90:cb3d968589d8 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 42 **
Kojto 90:cb3d968589d8 43 ** http: www.freescale.com
Kojto 90:cb3d968589d8 44 ** mail: support@freescale.com
Kojto 90:cb3d968589d8 45 **
Kojto 90:cb3d968589d8 46 ** Revisions:
Kojto 90:cb3d968589d8 47 ** - rev. 1.0 (2013-08-12)
Kojto 90:cb3d968589d8 48 ** Initial version.
Kojto 90:cb3d968589d8 49 ** - rev. 2.0 (2013-10-29)
Kojto 90:cb3d968589d8 50 ** Register accessor macros added to the memory map.
Kojto 90:cb3d968589d8 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto 90:cb3d968589d8 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto 90:cb3d968589d8 53 ** System initialization updated.
Kojto 90:cb3d968589d8 54 ** MCG - registers updated.
Kojto 90:cb3d968589d8 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto 90:cb3d968589d8 56 ** - rev. 2.1 (2013-10-30)
Kojto 90:cb3d968589d8 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto 90:cb3d968589d8 58 ** - rev. 2.2 (2013-12-09)
Kojto 90:cb3d968589d8 59 ** DMA - EARS register removed.
Kojto 90:cb3d968589d8 60 ** AIPS0, AIPS1 - MPRA register updated.
Kojto 90:cb3d968589d8 61 ** - rev. 2.3 (2014-01-24)
Kojto 90:cb3d968589d8 62 ** Update according to reference manual rev. 2
Kojto 90:cb3d968589d8 63 ** ENET, MCG, MCM, SIM, USB - registers updated
Kojto 90:cb3d968589d8 64 ** - rev. 2.4 (2014-02-10)
Kojto 90:cb3d968589d8 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 67 ** - rev. 2.5 (2014-02-10)
Kojto 90:cb3d968589d8 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto 90:cb3d968589d8 71 **
Kojto 90:cb3d968589d8 72 ** ###################################################################
Kojto 90:cb3d968589d8 73 */
Kojto 90:cb3d968589d8 74
Kojto 90:cb3d968589d8 75 /*
Kojto 90:cb3d968589d8 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto 90:cb3d968589d8 77 *
Kojto 90:cb3d968589d8 78 * This file was generated automatically and any changes may be lost.
Kojto 90:cb3d968589d8 79 */
Kojto 90:cb3d968589d8 80 #ifndef __HW_RNG_REGISTERS_H__
Kojto 90:cb3d968589d8 81 #define __HW_RNG_REGISTERS_H__
Kojto 90:cb3d968589d8 82
Kojto 90:cb3d968589d8 83 #include "MK64F12.h"
Kojto 90:cb3d968589d8 84 #include "fsl_bitaccess.h"
Kojto 90:cb3d968589d8 85
Kojto 90:cb3d968589d8 86 /*
Kojto 90:cb3d968589d8 87 * MK64F12 RNG
Kojto 90:cb3d968589d8 88 *
Kojto 90:cb3d968589d8 89 * Random Number Generator Accelerator
Kojto 90:cb3d968589d8 90 *
Kojto 90:cb3d968589d8 91 * Registers defined in this header file:
Kojto 90:cb3d968589d8 92 * - HW_RNG_CR - RNGA Control Register
Kojto 90:cb3d968589d8 93 * - HW_RNG_SR - RNGA Status Register
Kojto 90:cb3d968589d8 94 * - HW_RNG_ER - RNGA Entropy Register
Kojto 90:cb3d968589d8 95 * - HW_RNG_OR - RNGA Output Register
Kojto 90:cb3d968589d8 96 *
Kojto 90:cb3d968589d8 97 * - hw_rng_t - Struct containing all module registers.
Kojto 90:cb3d968589d8 98 */
Kojto 90:cb3d968589d8 99
Kojto 90:cb3d968589d8 100 #define HW_RNG_INSTANCE_COUNT (1U) /*!< Number of instances of the RNG module. */
Kojto 90:cb3d968589d8 101
Kojto 90:cb3d968589d8 102 /*******************************************************************************
Kojto 90:cb3d968589d8 103 * HW_RNG_CR - RNGA Control Register
Kojto 90:cb3d968589d8 104 ******************************************************************************/
Kojto 90:cb3d968589d8 105
Kojto 90:cb3d968589d8 106 /*!
Kojto 90:cb3d968589d8 107 * @brief HW_RNG_CR - RNGA Control Register (RW)
Kojto 90:cb3d968589d8 108 *
Kojto 90:cb3d968589d8 109 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 110 *
Kojto 90:cb3d968589d8 111 * Controls the operation of RNGA.
Kojto 90:cb3d968589d8 112 */
Kojto 90:cb3d968589d8 113 typedef union _hw_rng_cr
Kojto 90:cb3d968589d8 114 {
Kojto 90:cb3d968589d8 115 uint32_t U;
Kojto 90:cb3d968589d8 116 struct _hw_rng_cr_bitfields
Kojto 90:cb3d968589d8 117 {
Kojto 90:cb3d968589d8 118 uint32_t GO : 1; /*!< [0] Go */
Kojto 90:cb3d968589d8 119 uint32_t HA : 1; /*!< [1] High Assurance */
Kojto 90:cb3d968589d8 120 uint32_t INTM : 1; /*!< [2] Interrupt Mask */
Kojto 90:cb3d968589d8 121 uint32_t CLRI : 1; /*!< [3] Clear Interrupt */
Kojto 90:cb3d968589d8 122 uint32_t SLP : 1; /*!< [4] Sleep */
Kojto 90:cb3d968589d8 123 uint32_t RESERVED0 : 27; /*!< [31:5] */
Kojto 90:cb3d968589d8 124 } B;
Kojto 90:cb3d968589d8 125 } hw_rng_cr_t;
Kojto 90:cb3d968589d8 126
Kojto 90:cb3d968589d8 127 /*!
Kojto 90:cb3d968589d8 128 * @name Constants and macros for entire RNG_CR register
Kojto 90:cb3d968589d8 129 */
Kojto 90:cb3d968589d8 130 /*@{*/
Kojto 90:cb3d968589d8 131 #define HW_RNG_CR_ADDR(x) ((x) + 0x0U)
Kojto 90:cb3d968589d8 132
Kojto 90:cb3d968589d8 133 #define HW_RNG_CR(x) (*(__IO hw_rng_cr_t *) HW_RNG_CR_ADDR(x))
Kojto 90:cb3d968589d8 134 #define HW_RNG_CR_RD(x) (HW_RNG_CR(x).U)
Kojto 90:cb3d968589d8 135 #define HW_RNG_CR_WR(x, v) (HW_RNG_CR(x).U = (v))
Kojto 90:cb3d968589d8 136 #define HW_RNG_CR_SET(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) | (v)))
Kojto 90:cb3d968589d8 137 #define HW_RNG_CR_CLR(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 138 #define HW_RNG_CR_TOG(x, v) (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 139 /*@}*/
Kojto 90:cb3d968589d8 140
Kojto 90:cb3d968589d8 141 /*
Kojto 90:cb3d968589d8 142 * Constants & macros for individual RNG_CR bitfields
Kojto 90:cb3d968589d8 143 */
Kojto 90:cb3d968589d8 144
Kojto 90:cb3d968589d8 145 /*!
Kojto 90:cb3d968589d8 146 * @name Register RNG_CR, field GO[0] (RW)
Kojto 90:cb3d968589d8 147 *
Kojto 90:cb3d968589d8 148 * Specifies whether random-data generation and loading (into OR[RANDOUT]) is
Kojto 90:cb3d968589d8 149 * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
Kojto 90:cb3d968589d8 150 * OR[RANDOUT] with data.
Kojto 90:cb3d968589d8 151 *
Kojto 90:cb3d968589d8 152 * Values:
Kojto 90:cb3d968589d8 153 * - 0 - Disabled
Kojto 90:cb3d968589d8 154 * - 1 - Enabled
Kojto 90:cb3d968589d8 155 */
Kojto 90:cb3d968589d8 156 /*@{*/
Kojto 90:cb3d968589d8 157 #define BP_RNG_CR_GO (0U) /*!< Bit position for RNG_CR_GO. */
Kojto 90:cb3d968589d8 158 #define BM_RNG_CR_GO (0x00000001U) /*!< Bit mask for RNG_CR_GO. */
Kojto 90:cb3d968589d8 159 #define BS_RNG_CR_GO (1U) /*!< Bit field size in bits for RNG_CR_GO. */
Kojto 90:cb3d968589d8 160
Kojto 90:cb3d968589d8 161 /*! @brief Read current value of the RNG_CR_GO field. */
Kojto 90:cb3d968589d8 162 #define BR_RNG_CR_GO(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_GO))
Kojto 90:cb3d968589d8 163
Kojto 90:cb3d968589d8 164 /*! @brief Format value for bitfield RNG_CR_GO. */
Kojto 90:cb3d968589d8 165 #define BF_RNG_CR_GO(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_GO) & BM_RNG_CR_GO)
Kojto 90:cb3d968589d8 166
Kojto 90:cb3d968589d8 167 /*! @brief Set the GO field to a new value. */
Kojto 90:cb3d968589d8 168 #define BW_RNG_CR_GO(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_GO) = (v))
Kojto 90:cb3d968589d8 169 /*@}*/
Kojto 90:cb3d968589d8 170
Kojto 90:cb3d968589d8 171 /*!
Kojto 90:cb3d968589d8 172 * @name Register RNG_CR, field HA[1] (RW)
Kojto 90:cb3d968589d8 173 *
Kojto 90:cb3d968589d8 174 * Enables notification of security violations (via SR[SECV]). A security
Kojto 90:cb3d968589d8 175 * violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky.
Kojto 90:cb3d968589d8 176 * After enabling notification of security violations, you must reset RNGA to
Kojto 90:cb3d968589d8 177 * disable them again.
Kojto 90:cb3d968589d8 178 *
Kojto 90:cb3d968589d8 179 * Values:
Kojto 90:cb3d968589d8 180 * - 0 - Disabled
Kojto 90:cb3d968589d8 181 * - 1 - Enabled
Kojto 90:cb3d968589d8 182 */
Kojto 90:cb3d968589d8 183 /*@{*/
Kojto 90:cb3d968589d8 184 #define BP_RNG_CR_HA (1U) /*!< Bit position for RNG_CR_HA. */
Kojto 90:cb3d968589d8 185 #define BM_RNG_CR_HA (0x00000002U) /*!< Bit mask for RNG_CR_HA. */
Kojto 90:cb3d968589d8 186 #define BS_RNG_CR_HA (1U) /*!< Bit field size in bits for RNG_CR_HA. */
Kojto 90:cb3d968589d8 187
Kojto 90:cb3d968589d8 188 /*! @brief Read current value of the RNG_CR_HA field. */
Kojto 90:cb3d968589d8 189 #define BR_RNG_CR_HA(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_HA))
Kojto 90:cb3d968589d8 190
Kojto 90:cb3d968589d8 191 /*! @brief Format value for bitfield RNG_CR_HA. */
Kojto 90:cb3d968589d8 192 #define BF_RNG_CR_HA(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_HA) & BM_RNG_CR_HA)
Kojto 90:cb3d968589d8 193
Kojto 90:cb3d968589d8 194 /*! @brief Set the HA field to a new value. */
Kojto 90:cb3d968589d8 195 #define BW_RNG_CR_HA(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_HA) = (v))
Kojto 90:cb3d968589d8 196 /*@}*/
Kojto 90:cb3d968589d8 197
Kojto 90:cb3d968589d8 198 /*!
Kojto 90:cb3d968589d8 199 * @name Register RNG_CR, field INTM[2] (RW)
Kojto 90:cb3d968589d8 200 *
Kojto 90:cb3d968589d8 201 * Masks the triggering of an error interrupt to the interrupt controller when
Kojto 90:cb3d968589d8 202 * an OR underflow condition occurs. An OR underflow condition occurs when you
Kojto 90:cb3d968589d8 203 * read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description.
Kojto 90:cb3d968589d8 204 *
Kojto 90:cb3d968589d8 205 * Values:
Kojto 90:cb3d968589d8 206 * - 0 - Not masked
Kojto 90:cb3d968589d8 207 * - 1 - Masked
Kojto 90:cb3d968589d8 208 */
Kojto 90:cb3d968589d8 209 /*@{*/
Kojto 90:cb3d968589d8 210 #define BP_RNG_CR_INTM (2U) /*!< Bit position for RNG_CR_INTM. */
Kojto 90:cb3d968589d8 211 #define BM_RNG_CR_INTM (0x00000004U) /*!< Bit mask for RNG_CR_INTM. */
Kojto 90:cb3d968589d8 212 #define BS_RNG_CR_INTM (1U) /*!< Bit field size in bits for RNG_CR_INTM. */
Kojto 90:cb3d968589d8 213
Kojto 90:cb3d968589d8 214 /*! @brief Read current value of the RNG_CR_INTM field. */
Kojto 90:cb3d968589d8 215 #define BR_RNG_CR_INTM(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_INTM))
Kojto 90:cb3d968589d8 216
Kojto 90:cb3d968589d8 217 /*! @brief Format value for bitfield RNG_CR_INTM. */
Kojto 90:cb3d968589d8 218 #define BF_RNG_CR_INTM(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_INTM) & BM_RNG_CR_INTM)
Kojto 90:cb3d968589d8 219
Kojto 90:cb3d968589d8 220 /*! @brief Set the INTM field to a new value. */
Kojto 90:cb3d968589d8 221 #define BW_RNG_CR_INTM(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_INTM) = (v))
Kojto 90:cb3d968589d8 222 /*@}*/
Kojto 90:cb3d968589d8 223
Kojto 90:cb3d968589d8 224 /*!
Kojto 90:cb3d968589d8 225 * @name Register RNG_CR, field CLRI[3] (WORZ)
Kojto 90:cb3d968589d8 226 *
Kojto 90:cb3d968589d8 227 * Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]).
Kojto 90:cb3d968589d8 228 *
Kojto 90:cb3d968589d8 229 * Values:
Kojto 90:cb3d968589d8 230 * - 0 - Do not clear the interrupt.
Kojto 90:cb3d968589d8 231 * - 1 - Clear the interrupt. When you write 1 to this field, RNGA then resets
Kojto 90:cb3d968589d8 232 * the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
Kojto 90:cb3d968589d8 233 */
Kojto 90:cb3d968589d8 234 /*@{*/
Kojto 90:cb3d968589d8 235 #define BP_RNG_CR_CLRI (3U) /*!< Bit position for RNG_CR_CLRI. */
Kojto 90:cb3d968589d8 236 #define BM_RNG_CR_CLRI (0x00000008U) /*!< Bit mask for RNG_CR_CLRI. */
Kojto 90:cb3d968589d8 237 #define BS_RNG_CR_CLRI (1U) /*!< Bit field size in bits for RNG_CR_CLRI. */
Kojto 90:cb3d968589d8 238
Kojto 90:cb3d968589d8 239 /*! @brief Format value for bitfield RNG_CR_CLRI. */
Kojto 90:cb3d968589d8 240 #define BF_RNG_CR_CLRI(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_CLRI) & BM_RNG_CR_CLRI)
Kojto 90:cb3d968589d8 241
Kojto 90:cb3d968589d8 242 /*! @brief Set the CLRI field to a new value. */
Kojto 90:cb3d968589d8 243 #define BW_RNG_CR_CLRI(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_CLRI) = (v))
Kojto 90:cb3d968589d8 244 /*@}*/
Kojto 90:cb3d968589d8 245
Kojto 90:cb3d968589d8 246 /*!
Kojto 90:cb3d968589d8 247 * @name Register RNG_CR, field SLP[4] (RW)
Kojto 90:cb3d968589d8 248 *
Kojto 90:cb3d968589d8 249 * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
Kojto 90:cb3d968589d8 250 * mode by asserting the DOZE signal.
Kojto 90:cb3d968589d8 251 *
Kojto 90:cb3d968589d8 252 * Values:
Kojto 90:cb3d968589d8 253 * - 0 - Normal mode
Kojto 90:cb3d968589d8 254 * - 1 - Sleep (low-power) mode
Kojto 90:cb3d968589d8 255 */
Kojto 90:cb3d968589d8 256 /*@{*/
Kojto 90:cb3d968589d8 257 #define BP_RNG_CR_SLP (4U) /*!< Bit position for RNG_CR_SLP. */
Kojto 90:cb3d968589d8 258 #define BM_RNG_CR_SLP (0x00000010U) /*!< Bit mask for RNG_CR_SLP. */
Kojto 90:cb3d968589d8 259 #define BS_RNG_CR_SLP (1U) /*!< Bit field size in bits for RNG_CR_SLP. */
Kojto 90:cb3d968589d8 260
Kojto 90:cb3d968589d8 261 /*! @brief Read current value of the RNG_CR_SLP field. */
Kojto 90:cb3d968589d8 262 #define BR_RNG_CR_SLP(x) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_SLP))
Kojto 90:cb3d968589d8 263
Kojto 90:cb3d968589d8 264 /*! @brief Format value for bitfield RNG_CR_SLP. */
Kojto 90:cb3d968589d8 265 #define BF_RNG_CR_SLP(v) ((uint32_t)((uint32_t)(v) << BP_RNG_CR_SLP) & BM_RNG_CR_SLP)
Kojto 90:cb3d968589d8 266
Kojto 90:cb3d968589d8 267 /*! @brief Set the SLP field to a new value. */
Kojto 90:cb3d968589d8 268 #define BW_RNG_CR_SLP(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_SLP) = (v))
Kojto 90:cb3d968589d8 269 /*@}*/
Kojto 90:cb3d968589d8 270
Kojto 90:cb3d968589d8 271 /*******************************************************************************
Kojto 90:cb3d968589d8 272 * HW_RNG_SR - RNGA Status Register
Kojto 90:cb3d968589d8 273 ******************************************************************************/
Kojto 90:cb3d968589d8 274
Kojto 90:cb3d968589d8 275 /*!
Kojto 90:cb3d968589d8 276 * @brief HW_RNG_SR - RNGA Status Register (RO)
Kojto 90:cb3d968589d8 277 *
Kojto 90:cb3d968589d8 278 * Reset value: 0x00010000U
Kojto 90:cb3d968589d8 279 *
Kojto 90:cb3d968589d8 280 * Indicates the status of RNGA. This register is read-only.
Kojto 90:cb3d968589d8 281 */
Kojto 90:cb3d968589d8 282 typedef union _hw_rng_sr
Kojto 90:cb3d968589d8 283 {
Kojto 90:cb3d968589d8 284 uint32_t U;
Kojto 90:cb3d968589d8 285 struct _hw_rng_sr_bitfields
Kojto 90:cb3d968589d8 286 {
Kojto 90:cb3d968589d8 287 uint32_t SECV : 1; /*!< [0] Security Violation */
Kojto 90:cb3d968589d8 288 uint32_t LRS : 1; /*!< [1] Last Read Status */
Kojto 90:cb3d968589d8 289 uint32_t ORU : 1; /*!< [2] Output Register Underflow */
Kojto 90:cb3d968589d8 290 uint32_t ERRI : 1; /*!< [3] Error Interrupt */
Kojto 90:cb3d968589d8 291 uint32_t SLP : 1; /*!< [4] Sleep */
Kojto 90:cb3d968589d8 292 uint32_t RESERVED0 : 3; /*!< [7:5] */
Kojto 90:cb3d968589d8 293 uint32_t OREG_LVL : 8; /*!< [15:8] Output Register Level */
Kojto 90:cb3d968589d8 294 uint32_t OREG_SIZE : 8; /*!< [23:16] Output Register Size */
Kojto 90:cb3d968589d8 295 uint32_t RESERVED1 : 8; /*!< [31:24] */
Kojto 90:cb3d968589d8 296 } B;
Kojto 90:cb3d968589d8 297 } hw_rng_sr_t;
Kojto 90:cb3d968589d8 298
Kojto 90:cb3d968589d8 299 /*!
Kojto 90:cb3d968589d8 300 * @name Constants and macros for entire RNG_SR register
Kojto 90:cb3d968589d8 301 */
Kojto 90:cb3d968589d8 302 /*@{*/
Kojto 90:cb3d968589d8 303 #define HW_RNG_SR_ADDR(x) ((x) + 0x4U)
Kojto 90:cb3d968589d8 304
Kojto 90:cb3d968589d8 305 #define HW_RNG_SR(x) (*(__I hw_rng_sr_t *) HW_RNG_SR_ADDR(x))
Kojto 90:cb3d968589d8 306 #define HW_RNG_SR_RD(x) (HW_RNG_SR(x).U)
Kojto 90:cb3d968589d8 307 /*@}*/
Kojto 90:cb3d968589d8 308
Kojto 90:cb3d968589d8 309 /*
Kojto 90:cb3d968589d8 310 * Constants & macros for individual RNG_SR bitfields
Kojto 90:cb3d968589d8 311 */
Kojto 90:cb3d968589d8 312
Kojto 90:cb3d968589d8 313 /*!
Kojto 90:cb3d968589d8 314 * @name Register RNG_SR, field SECV[0] (RO)
Kojto 90:cb3d968589d8 315 *
Kojto 90:cb3d968589d8 316 * Used only when high assurance is enabled (CR[HA]). Indicates that a security
Kojto 90:cb3d968589d8 317 * violation has occurred.This field is sticky. To clear SR[SECV], you must reset
Kojto 90:cb3d968589d8 318 * RNGA.
Kojto 90:cb3d968589d8 319 *
Kojto 90:cb3d968589d8 320 * Values:
Kojto 90:cb3d968589d8 321 * - 0 - No security violation
Kojto 90:cb3d968589d8 322 * - 1 - Security violation
Kojto 90:cb3d968589d8 323 */
Kojto 90:cb3d968589d8 324 /*@{*/
Kojto 90:cb3d968589d8 325 #define BP_RNG_SR_SECV (0U) /*!< Bit position for RNG_SR_SECV. */
Kojto 90:cb3d968589d8 326 #define BM_RNG_SR_SECV (0x00000001U) /*!< Bit mask for RNG_SR_SECV. */
Kojto 90:cb3d968589d8 327 #define BS_RNG_SR_SECV (1U) /*!< Bit field size in bits for RNG_SR_SECV. */
Kojto 90:cb3d968589d8 328
Kojto 90:cb3d968589d8 329 /*! @brief Read current value of the RNG_SR_SECV field. */
Kojto 90:cb3d968589d8 330 #define BR_RNG_SR_SECV(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_SECV))
Kojto 90:cb3d968589d8 331 /*@}*/
Kojto 90:cb3d968589d8 332
Kojto 90:cb3d968589d8 333 /*!
Kojto 90:cb3d968589d8 334 * @name Register RNG_SR, field LRS[1] (RO)
Kojto 90:cb3d968589d8 335 *
Kojto 90:cb3d968589d8 336 * Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow
Kojto 90:cb3d968589d8 337 * condition, regardless of whether the error interrupt is masked (CR[INTM]). An
Kojto 90:cb3d968589d8 338 * OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0.
Kojto 90:cb3d968589d8 339 * After you read this register, RNGA writes 0 to this field.
Kojto 90:cb3d968589d8 340 *
Kojto 90:cb3d968589d8 341 * Values:
Kojto 90:cb3d968589d8 342 * - 0 - No underflow
Kojto 90:cb3d968589d8 343 * - 1 - Underflow
Kojto 90:cb3d968589d8 344 */
Kojto 90:cb3d968589d8 345 /*@{*/
Kojto 90:cb3d968589d8 346 #define BP_RNG_SR_LRS (1U) /*!< Bit position for RNG_SR_LRS. */
Kojto 90:cb3d968589d8 347 #define BM_RNG_SR_LRS (0x00000002U) /*!< Bit mask for RNG_SR_LRS. */
Kojto 90:cb3d968589d8 348 #define BS_RNG_SR_LRS (1U) /*!< Bit field size in bits for RNG_SR_LRS. */
Kojto 90:cb3d968589d8 349
Kojto 90:cb3d968589d8 350 /*! @brief Read current value of the RNG_SR_LRS field. */
Kojto 90:cb3d968589d8 351 #define BR_RNG_SR_LRS(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_LRS))
Kojto 90:cb3d968589d8 352 /*@}*/
Kojto 90:cb3d968589d8 353
Kojto 90:cb3d968589d8 354 /*!
Kojto 90:cb3d968589d8 355 * @name Register RNG_SR, field ORU[2] (RO)
Kojto 90:cb3d968589d8 356 *
Kojto 90:cb3d968589d8 357 * Indicates whether an OR underflow condition has occurred since you last read
Kojto 90:cb3d968589d8 358 * this register (SR) or RNGA was reset, regardless of whether the error
Kojto 90:cb3d968589d8 359 * interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read
Kojto 90:cb3d968589d8 360 * OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this
Kojto 90:cb3d968589d8 361 * field.
Kojto 90:cb3d968589d8 362 *
Kojto 90:cb3d968589d8 363 * Values:
Kojto 90:cb3d968589d8 364 * - 0 - No underflow
Kojto 90:cb3d968589d8 365 * - 1 - Underflow
Kojto 90:cb3d968589d8 366 */
Kojto 90:cb3d968589d8 367 /*@{*/
Kojto 90:cb3d968589d8 368 #define BP_RNG_SR_ORU (2U) /*!< Bit position for RNG_SR_ORU. */
Kojto 90:cb3d968589d8 369 #define BM_RNG_SR_ORU (0x00000004U) /*!< Bit mask for RNG_SR_ORU. */
Kojto 90:cb3d968589d8 370 #define BS_RNG_SR_ORU (1U) /*!< Bit field size in bits for RNG_SR_ORU. */
Kojto 90:cb3d968589d8 371
Kojto 90:cb3d968589d8 372 /*! @brief Read current value of the RNG_SR_ORU field. */
Kojto 90:cb3d968589d8 373 #define BR_RNG_SR_ORU(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_ORU))
Kojto 90:cb3d968589d8 374 /*@}*/
Kojto 90:cb3d968589d8 375
Kojto 90:cb3d968589d8 376 /*!
Kojto 90:cb3d968589d8 377 * @name Register RNG_SR, field ERRI[3] (RO)
Kojto 90:cb3d968589d8 378 *
Kojto 90:cb3d968589d8 379 * Indicates whether an OR underflow condition has occurred since you last
Kojto 90:cb3d968589d8 380 * cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the
Kojto 90:cb3d968589d8 381 * error interrupt is masked (CR[INTM]). An OR underflow condition occurs when
Kojto 90:cb3d968589d8 382 * you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt
Kojto 90:cb3d968589d8 383 * indicator (via CR[CLRI]), RNGA writes 0 to this field.
Kojto 90:cb3d968589d8 384 *
Kojto 90:cb3d968589d8 385 * Values:
Kojto 90:cb3d968589d8 386 * - 0 - No underflow
Kojto 90:cb3d968589d8 387 * - 1 - Underflow
Kojto 90:cb3d968589d8 388 */
Kojto 90:cb3d968589d8 389 /*@{*/
Kojto 90:cb3d968589d8 390 #define BP_RNG_SR_ERRI (3U) /*!< Bit position for RNG_SR_ERRI. */
Kojto 90:cb3d968589d8 391 #define BM_RNG_SR_ERRI (0x00000008U) /*!< Bit mask for RNG_SR_ERRI. */
Kojto 90:cb3d968589d8 392 #define BS_RNG_SR_ERRI (1U) /*!< Bit field size in bits for RNG_SR_ERRI. */
Kojto 90:cb3d968589d8 393
Kojto 90:cb3d968589d8 394 /*! @brief Read current value of the RNG_SR_ERRI field. */
Kojto 90:cb3d968589d8 395 #define BR_RNG_SR_ERRI(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_ERRI))
Kojto 90:cb3d968589d8 396 /*@}*/
Kojto 90:cb3d968589d8 397
Kojto 90:cb3d968589d8 398 /*!
Kojto 90:cb3d968589d8 399 * @name Register RNG_SR, field SLP[4] (RO)
Kojto 90:cb3d968589d8 400 *
Kojto 90:cb3d968589d8 401 * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
Kojto 90:cb3d968589d8 402 * mode by asserting the DOZE signal.
Kojto 90:cb3d968589d8 403 *
Kojto 90:cb3d968589d8 404 * Values:
Kojto 90:cb3d968589d8 405 * - 0 - Normal mode
Kojto 90:cb3d968589d8 406 * - 1 - Sleep (low-power) mode
Kojto 90:cb3d968589d8 407 */
Kojto 90:cb3d968589d8 408 /*@{*/
Kojto 90:cb3d968589d8 409 #define BP_RNG_SR_SLP (4U) /*!< Bit position for RNG_SR_SLP. */
Kojto 90:cb3d968589d8 410 #define BM_RNG_SR_SLP (0x00000010U) /*!< Bit mask for RNG_SR_SLP. */
Kojto 90:cb3d968589d8 411 #define BS_RNG_SR_SLP (1U) /*!< Bit field size in bits for RNG_SR_SLP. */
Kojto 90:cb3d968589d8 412
Kojto 90:cb3d968589d8 413 /*! @brief Read current value of the RNG_SR_SLP field. */
Kojto 90:cb3d968589d8 414 #define BR_RNG_SR_SLP(x) (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_SLP))
Kojto 90:cb3d968589d8 415 /*@}*/
Kojto 90:cb3d968589d8 416
Kojto 90:cb3d968589d8 417 /*!
Kojto 90:cb3d968589d8 418 * @name Register RNG_SR, field OREG_LVL[15:8] (RO)
Kojto 90:cb3d968589d8 419 *
Kojto 90:cb3d968589d8 420 * Indicates the number of random-data words that are in OR[RANDOUT], which
Kojto 90:cb3d968589d8 421 * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
Kojto 90:cb3d968589d8 422 * is not 0, then the contents of a random number contained in OR[RANDOUT] are
Kojto 90:cb3d968589d8 423 * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
Kojto 90:cb3d968589d8 424 *
Kojto 90:cb3d968589d8 425 * Values:
Kojto 90:cb3d968589d8 426 * - 0 - No words (empty)
Kojto 90:cb3d968589d8 427 * - 1 - One word (valid)
Kojto 90:cb3d968589d8 428 */
Kojto 90:cb3d968589d8 429 /*@{*/
Kojto 90:cb3d968589d8 430 #define BP_RNG_SR_OREG_LVL (8U) /*!< Bit position for RNG_SR_OREG_LVL. */
Kojto 90:cb3d968589d8 431 #define BM_RNG_SR_OREG_LVL (0x0000FF00U) /*!< Bit mask for RNG_SR_OREG_LVL. */
Kojto 90:cb3d968589d8 432 #define BS_RNG_SR_OREG_LVL (8U) /*!< Bit field size in bits for RNG_SR_OREG_LVL. */
Kojto 90:cb3d968589d8 433
Kojto 90:cb3d968589d8 434 /*! @brief Read current value of the RNG_SR_OREG_LVL field. */
Kojto 90:cb3d968589d8 435 #define BR_RNG_SR_OREG_LVL(x) (HW_RNG_SR(x).B.OREG_LVL)
Kojto 90:cb3d968589d8 436 /*@}*/
Kojto 90:cb3d968589d8 437
Kojto 90:cb3d968589d8 438 /*!
Kojto 90:cb3d968589d8 439 * @name Register RNG_SR, field OREG_SIZE[23:16] (RO)
Kojto 90:cb3d968589d8 440 *
Kojto 90:cb3d968589d8 441 * Indicates the size of the Output (OR) register in terms of the number of
Kojto 90:cb3d968589d8 442 * 32-bit random-data words it can hold.
Kojto 90:cb3d968589d8 443 *
Kojto 90:cb3d968589d8 444 * Values:
Kojto 90:cb3d968589d8 445 * - 1 - One word (this value is fixed)
Kojto 90:cb3d968589d8 446 */
Kojto 90:cb3d968589d8 447 /*@{*/
Kojto 90:cb3d968589d8 448 #define BP_RNG_SR_OREG_SIZE (16U) /*!< Bit position for RNG_SR_OREG_SIZE. */
Kojto 90:cb3d968589d8 449 #define BM_RNG_SR_OREG_SIZE (0x00FF0000U) /*!< Bit mask for RNG_SR_OREG_SIZE. */
Kojto 90:cb3d968589d8 450 #define BS_RNG_SR_OREG_SIZE (8U) /*!< Bit field size in bits for RNG_SR_OREG_SIZE. */
Kojto 90:cb3d968589d8 451
Kojto 90:cb3d968589d8 452 /*! @brief Read current value of the RNG_SR_OREG_SIZE field. */
Kojto 90:cb3d968589d8 453 #define BR_RNG_SR_OREG_SIZE(x) (HW_RNG_SR(x).B.OREG_SIZE)
Kojto 90:cb3d968589d8 454 /*@}*/
Kojto 90:cb3d968589d8 455
Kojto 90:cb3d968589d8 456 /*******************************************************************************
Kojto 90:cb3d968589d8 457 * HW_RNG_ER - RNGA Entropy Register
Kojto 90:cb3d968589d8 458 ******************************************************************************/
Kojto 90:cb3d968589d8 459
Kojto 90:cb3d968589d8 460 /*!
Kojto 90:cb3d968589d8 461 * @brief HW_RNG_ER - RNGA Entropy Register (WORZ)
Kojto 90:cb3d968589d8 462 *
Kojto 90:cb3d968589d8 463 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 464 *
Kojto 90:cb3d968589d8 465 * Specifies an entropy value that RNGA uses in addition to its ring oscillators
Kojto 90:cb3d968589d8 466 * to seed its pseudorandom algorithm. This is a write-only register; reads
Kojto 90:cb3d968589d8 467 * return all zeros.
Kojto 90:cb3d968589d8 468 */
Kojto 90:cb3d968589d8 469 typedef union _hw_rng_er
Kojto 90:cb3d968589d8 470 {
Kojto 90:cb3d968589d8 471 uint32_t U;
Kojto 90:cb3d968589d8 472 struct _hw_rng_er_bitfields
Kojto 90:cb3d968589d8 473 {
Kojto 90:cb3d968589d8 474 uint32_t EXT_ENT : 32; /*!< [31:0] External Entropy */
Kojto 90:cb3d968589d8 475 } B;
Kojto 90:cb3d968589d8 476 } hw_rng_er_t;
Kojto 90:cb3d968589d8 477
Kojto 90:cb3d968589d8 478 /*!
Kojto 90:cb3d968589d8 479 * @name Constants and macros for entire RNG_ER register
Kojto 90:cb3d968589d8 480 */
Kojto 90:cb3d968589d8 481 /*@{*/
Kojto 90:cb3d968589d8 482 #define HW_RNG_ER_ADDR(x) ((x) + 0x8U)
Kojto 90:cb3d968589d8 483
Kojto 90:cb3d968589d8 484 #define HW_RNG_ER(x) (*(__O hw_rng_er_t *) HW_RNG_ER_ADDR(x))
Kojto 90:cb3d968589d8 485 #define HW_RNG_ER_RD(x) (HW_RNG_ER(x).U)
Kojto 90:cb3d968589d8 486 #define HW_RNG_ER_WR(x, v) (HW_RNG_ER(x).U = (v))
Kojto 90:cb3d968589d8 487 /*@}*/
Kojto 90:cb3d968589d8 488
Kojto 90:cb3d968589d8 489 /*
Kojto 90:cb3d968589d8 490 * Constants & macros for individual RNG_ER bitfields
Kojto 90:cb3d968589d8 491 */
Kojto 90:cb3d968589d8 492
Kojto 90:cb3d968589d8 493 /*!
Kojto 90:cb3d968589d8 494 * @name Register RNG_ER, field EXT_ENT[31:0] (WORZ)
Kojto 90:cb3d968589d8 495 *
Kojto 90:cb3d968589d8 496 * Specifies an entropy value that RNGA uses in addition to its ring oscillators
Kojto 90:cb3d968589d8 497 * to seed its pseudorandom algorithm.Specifying a value for this field is
Kojto 90:cb3d968589d8 498 * optional but recommended. You can write to this field at any time during operation.
Kojto 90:cb3d968589d8 499 */
Kojto 90:cb3d968589d8 500 /*@{*/
Kojto 90:cb3d968589d8 501 #define BP_RNG_ER_EXT_ENT (0U) /*!< Bit position for RNG_ER_EXT_ENT. */
Kojto 90:cb3d968589d8 502 #define BM_RNG_ER_EXT_ENT (0xFFFFFFFFU) /*!< Bit mask for RNG_ER_EXT_ENT. */
Kojto 90:cb3d968589d8 503 #define BS_RNG_ER_EXT_ENT (32U) /*!< Bit field size in bits for RNG_ER_EXT_ENT. */
Kojto 90:cb3d968589d8 504
Kojto 90:cb3d968589d8 505 /*! @brief Format value for bitfield RNG_ER_EXT_ENT. */
Kojto 90:cb3d968589d8 506 #define BF_RNG_ER_EXT_ENT(v) ((uint32_t)((uint32_t)(v) << BP_RNG_ER_EXT_ENT) & BM_RNG_ER_EXT_ENT)
Kojto 90:cb3d968589d8 507
Kojto 90:cb3d968589d8 508 /*! @brief Set the EXT_ENT field to a new value. */
Kojto 90:cb3d968589d8 509 #define BW_RNG_ER_EXT_ENT(x, v) (HW_RNG_ER_WR(x, v))
Kojto 90:cb3d968589d8 510 /*@}*/
Kojto 90:cb3d968589d8 511
Kojto 90:cb3d968589d8 512 /*******************************************************************************
Kojto 90:cb3d968589d8 513 * HW_RNG_OR - RNGA Output Register
Kojto 90:cb3d968589d8 514 ******************************************************************************/
Kojto 90:cb3d968589d8 515
Kojto 90:cb3d968589d8 516 /*!
Kojto 90:cb3d968589d8 517 * @brief HW_RNG_OR - RNGA Output Register (RO)
Kojto 90:cb3d968589d8 518 *
Kojto 90:cb3d968589d8 519 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 520 *
Kojto 90:cb3d968589d8 521 * Stores a random-data word generated by RNGA.
Kojto 90:cb3d968589d8 522 */
Kojto 90:cb3d968589d8 523 typedef union _hw_rng_or
Kojto 90:cb3d968589d8 524 {
Kojto 90:cb3d968589d8 525 uint32_t U;
Kojto 90:cb3d968589d8 526 struct _hw_rng_or_bitfields
Kojto 90:cb3d968589d8 527 {
Kojto 90:cb3d968589d8 528 uint32_t RANDOUT : 32; /*!< [31:0] Random Output */
Kojto 90:cb3d968589d8 529 } B;
Kojto 90:cb3d968589d8 530 } hw_rng_or_t;
Kojto 90:cb3d968589d8 531
Kojto 90:cb3d968589d8 532 /*!
Kojto 90:cb3d968589d8 533 * @name Constants and macros for entire RNG_OR register
Kojto 90:cb3d968589d8 534 */
Kojto 90:cb3d968589d8 535 /*@{*/
Kojto 90:cb3d968589d8 536 #define HW_RNG_OR_ADDR(x) ((x) + 0xCU)
Kojto 90:cb3d968589d8 537
Kojto 90:cb3d968589d8 538 #define HW_RNG_OR(x) (*(__I hw_rng_or_t *) HW_RNG_OR_ADDR(x))
Kojto 90:cb3d968589d8 539 #define HW_RNG_OR_RD(x) (HW_RNG_OR(x).U)
Kojto 90:cb3d968589d8 540 /*@}*/
Kojto 90:cb3d968589d8 541
Kojto 90:cb3d968589d8 542 /*
Kojto 90:cb3d968589d8 543 * Constants & macros for individual RNG_OR bitfields
Kojto 90:cb3d968589d8 544 */
Kojto 90:cb3d968589d8 545
Kojto 90:cb3d968589d8 546 /*!
Kojto 90:cb3d968589d8 547 * @name Register RNG_OR, field RANDOUT[31:0] (RO)
Kojto 90:cb3d968589d8 548 *
Kojto 90:cb3d968589d8 549 * Stores a random-data word generated by RNGA. This is a read-only field.Before
Kojto 90:cb3d968589d8 550 * reading RANDOUT, be sure it is valid (SR[OREG_LVL]=1).
Kojto 90:cb3d968589d8 551 *
Kojto 90:cb3d968589d8 552 * Values:
Kojto 90:cb3d968589d8 553 * - 0 - Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is
Kojto 90:cb3d968589d8 554 * 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error
Kojto 90:cb3d968589d8 555 * interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt
Kojto 90:cb3d968589d8 556 * request to the interrupt controller).
Kojto 90:cb3d968589d8 557 */
Kojto 90:cb3d968589d8 558 /*@{*/
Kojto 90:cb3d968589d8 559 #define BP_RNG_OR_RANDOUT (0U) /*!< Bit position for RNG_OR_RANDOUT. */
Kojto 90:cb3d968589d8 560 #define BM_RNG_OR_RANDOUT (0xFFFFFFFFU) /*!< Bit mask for RNG_OR_RANDOUT. */
Kojto 90:cb3d968589d8 561 #define BS_RNG_OR_RANDOUT (32U) /*!< Bit field size in bits for RNG_OR_RANDOUT. */
Kojto 90:cb3d968589d8 562
Kojto 90:cb3d968589d8 563 /*! @brief Read current value of the RNG_OR_RANDOUT field. */
Kojto 90:cb3d968589d8 564 #define BR_RNG_OR_RANDOUT(x) (HW_RNG_OR(x).U)
Kojto 90:cb3d968589d8 565 /*@}*/
Kojto 90:cb3d968589d8 566
Kojto 90:cb3d968589d8 567 /*******************************************************************************
Kojto 90:cb3d968589d8 568 * hw_rng_t - module struct
Kojto 90:cb3d968589d8 569 ******************************************************************************/
Kojto 90:cb3d968589d8 570 /*!
Kojto 90:cb3d968589d8 571 * @brief All RNG module registers.
Kojto 90:cb3d968589d8 572 */
Kojto 90:cb3d968589d8 573 #pragma pack(1)
Kojto 90:cb3d968589d8 574 typedef struct _hw_rng
Kojto 90:cb3d968589d8 575 {
Kojto 90:cb3d968589d8 576 __IO hw_rng_cr_t CR; /*!< [0x0] RNGA Control Register */
Kojto 90:cb3d968589d8 577 __I hw_rng_sr_t SR; /*!< [0x4] RNGA Status Register */
Kojto 90:cb3d968589d8 578 __O hw_rng_er_t ER; /*!< [0x8] RNGA Entropy Register */
Kojto 90:cb3d968589d8 579 __I hw_rng_or_t OR; /*!< [0xC] RNGA Output Register */
Kojto 90:cb3d968589d8 580 } hw_rng_t;
Kojto 90:cb3d968589d8 581 #pragma pack()
Kojto 90:cb3d968589d8 582
Kojto 90:cb3d968589d8 583 /*! @brief Macro to access all RNG registers. */
Kojto 90:cb3d968589d8 584 /*! @param x RNG module instance base address. */
Kojto 90:cb3d968589d8 585 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto 90:cb3d968589d8 586 * use the '&' operator, like <code>&HW_RNG(RNG_BASE)</code>. */
Kojto 90:cb3d968589d8 587 #define HW_RNG(x) (*(hw_rng_t *)(x))
Kojto 90:cb3d968589d8 588
Kojto 90:cb3d968589d8 589 #endif /* __HW_RNG_REGISTERS_H__ */
Kojto 90:cb3d968589d8 590 /* EOF */