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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rcm.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:
Kojto
Date:
Wed Aug 05 13:16:35 2015 +0100
Revision:
104:b9ad9a133dc7
Parent:
90:cb3d968589d8 
Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /*
Kojto 90:cb3d968589d8 2 ** ###################################################################
Kojto 90:cb3d968589d8 3 ** Compilers: Keil ARM C/C++ Compiler
Kojto 90:cb3d968589d8 4 ** Freescale C/C++ for Embedded ARM
Kojto 90:cb3d968589d8 5 ** GNU C Compiler
Kojto 90:cb3d968589d8 6 ** IAR ANSI C/C++ Compiler for ARM
Kojto 90:cb3d968589d8 7 **
Kojto 90:cb3d968589d8 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto 90:cb3d968589d8 9 ** Version: rev. 2.5, 2014-02-10
Kojto 90:cb3d968589d8 10 ** Build: b140604
Kojto 90:cb3d968589d8 11 **
Kojto 90:cb3d968589d8 12 ** Abstract:
Kojto 90:cb3d968589d8 13 ** Extension to the CMSIS register access layer header.
Kojto 90:cb3d968589d8 14 **
Kojto 90:cb3d968589d8 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto 90:cb3d968589d8 16 ** All rights reserved.
Kojto 90:cb3d968589d8 17 **
Kojto 90:cb3d968589d8 18 ** Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 19 ** are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 20 **
Kojto 90:cb3d968589d8 21 ** o Redistributions of source code must retain the above copyright notice, this list
Kojto 90:cb3d968589d8 22 ** of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 23 **
Kojto 90:cb3d968589d8 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto 90:cb3d968589d8 25 ** list of conditions and the following disclaimer in the documentation and/or
Kojto 90:cb3d968589d8 26 ** other materials provided with the distribution.
Kojto 90:cb3d968589d8 27 **
Kojto 90:cb3d968589d8 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto 90:cb3d968589d8 29 ** contributors may be used to endorse or promote products derived from this
Kojto 90:cb3d968589d8 30 ** software without specific prior written permission.
Kojto 90:cb3d968589d8 31 **
Kojto 90:cb3d968589d8 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 90:cb3d968589d8 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 90:cb3d968589d8 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 90:cb3d968589d8 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 90:cb3d968589d8 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 90:cb3d968589d8 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 90:cb3d968589d8 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 90:cb3d968589d8 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 90:cb3d968589d8 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 42 **
Kojto 90:cb3d968589d8 43 ** http: www.freescale.com
Kojto 90:cb3d968589d8 44 ** mail: support@freescale.com
Kojto 90:cb3d968589d8 45 **
Kojto 90:cb3d968589d8 46 ** Revisions:
Kojto 90:cb3d968589d8 47 ** - rev. 1.0 (2013-08-12)
Kojto 90:cb3d968589d8 48 ** Initial version.
Kojto 90:cb3d968589d8 49 ** - rev. 2.0 (2013-10-29)
Kojto 90:cb3d968589d8 50 ** Register accessor macros added to the memory map.
Kojto 90:cb3d968589d8 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto 90:cb3d968589d8 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto 90:cb3d968589d8 53 ** System initialization updated.
Kojto 90:cb3d968589d8 54 ** MCG - registers updated.
Kojto 90:cb3d968589d8 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto 90:cb3d968589d8 56 ** - rev. 2.1 (2013-10-30)
Kojto 90:cb3d968589d8 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto 90:cb3d968589d8 58 ** - rev. 2.2 (2013-12-09)
Kojto 90:cb3d968589d8 59 ** DMA - EARS register removed.
Kojto 90:cb3d968589d8 60 ** AIPS0, AIPS1 - MPRA register updated.
Kojto 90:cb3d968589d8 61 ** - rev. 2.3 (2014-01-24)
Kojto 90:cb3d968589d8 62 ** Update according to reference manual rev. 2
Kojto 90:cb3d968589d8 63 ** ENET, MCG, MCM, SIM, USB - registers updated
Kojto 90:cb3d968589d8 64 ** - rev. 2.4 (2014-02-10)
Kojto 90:cb3d968589d8 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 67 ** - rev. 2.5 (2014-02-10)
Kojto 90:cb3d968589d8 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto 90:cb3d968589d8 71 **
Kojto 90:cb3d968589d8 72 ** ###################################################################
Kojto 90:cb3d968589d8 73 */
Kojto 90:cb3d968589d8 74
Kojto 90:cb3d968589d8 75 /*
Kojto 90:cb3d968589d8 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto 90:cb3d968589d8 77 *
Kojto 90:cb3d968589d8 78 * This file was generated automatically and any changes may be lost.
Kojto 90:cb3d968589d8 79 */
Kojto 90:cb3d968589d8 80 #ifndef __HW_RCM_REGISTERS_H__
Kojto 90:cb3d968589d8 81 #define __HW_RCM_REGISTERS_H__
Kojto 90:cb3d968589d8 82
Kojto 90:cb3d968589d8 83 #include "MK64F12.h"
Kojto 90:cb3d968589d8 84 #include "fsl_bitaccess.h"
Kojto 90:cb3d968589d8 85
Kojto 90:cb3d968589d8 86 /*
Kojto 90:cb3d968589d8 87 * MK64F12 RCM
Kojto 90:cb3d968589d8 88 *
Kojto 90:cb3d968589d8 89 * Reset Control Module
Kojto 90:cb3d968589d8 90 *
Kojto 90:cb3d968589d8 91 * Registers defined in this header file:
Kojto 90:cb3d968589d8 92 * - HW_RCM_SRS0 - System Reset Status Register 0
Kojto 90:cb3d968589d8 93 * - HW_RCM_SRS1 - System Reset Status Register 1
Kojto 90:cb3d968589d8 94 * - HW_RCM_RPFC - Reset Pin Filter Control register
Kojto 90:cb3d968589d8 95 * - HW_RCM_RPFW - Reset Pin Filter Width register
Kojto 90:cb3d968589d8 96 * - HW_RCM_MR - Mode Register
Kojto 90:cb3d968589d8 97 *
Kojto 90:cb3d968589d8 98 * - hw_rcm_t - Struct containing all module registers.
Kojto 90:cb3d968589d8 99 */
Kojto 90:cb3d968589d8 100
Kojto 90:cb3d968589d8 101 #define HW_RCM_INSTANCE_COUNT (1U) /*!< Number of instances of the RCM module. */
Kojto 90:cb3d968589d8 102
Kojto 90:cb3d968589d8 103 /*******************************************************************************
Kojto 90:cb3d968589d8 104 * HW_RCM_SRS0 - System Reset Status Register 0
Kojto 90:cb3d968589d8 105 ******************************************************************************/
Kojto 90:cb3d968589d8 106
Kojto 90:cb3d968589d8 107 /*!
Kojto 90:cb3d968589d8 108 * @brief HW_RCM_SRS0 - System Reset Status Register 0 (RO)
Kojto 90:cb3d968589d8 109 *
Kojto 90:cb3d968589d8 110 * Reset value: 0x82U
Kojto 90:cb3d968589d8 111 *
Kojto 90:cb3d968589d8 112 * This register includes read-only status flags to indicate the source of the
Kojto 90:cb3d968589d8 113 * most recent reset. The reset state of these bits depends on what caused the MCU
Kojto 90:cb3d968589d8 114 * to reset. The reset value of this register depends on the reset source: POR
Kojto 90:cb3d968589d8 115 * (including LVD) - 0x82 LVD (without POR) - 0x02 VLLS mode wakeup due to RESET
Kojto 90:cb3d968589d8 116 * pin assertion - 0x41 VLLS mode wakeup due to other wakeup sources - 0x01 Other
Kojto 90:cb3d968589d8 117 * reset - a bit is set if its corresponding reset source caused the reset
Kojto 90:cb3d968589d8 118 */
Kojto 90:cb3d968589d8 119 typedef union _hw_rcm_srs0
Kojto 90:cb3d968589d8 120 {
Kojto 90:cb3d968589d8 121 uint8_t U;
Kojto 90:cb3d968589d8 122 struct _hw_rcm_srs0_bitfields
Kojto 90:cb3d968589d8 123 {
Kojto 90:cb3d968589d8 124 uint8_t WAKEUP : 1; /*!< [0] Low Leakage Wakeup Reset */
Kojto 90:cb3d968589d8 125 uint8_t LVD : 1; /*!< [1] Low-Voltage Detect Reset */
Kojto 90:cb3d968589d8 126 uint8_t LOC : 1; /*!< [2] Loss-of-Clock Reset */
Kojto 90:cb3d968589d8 127 uint8_t LOL : 1; /*!< [3] Loss-of-Lock Reset */
Kojto 90:cb3d968589d8 128 uint8_t RESERVED0 : 1; /*!< [4] */
Kojto 90:cb3d968589d8 129 uint8_t WDOGb : 1; /*!< [5] Watchdog */
Kojto 90:cb3d968589d8 130 uint8_t PIN : 1; /*!< [6] External Reset Pin */
Kojto 90:cb3d968589d8 131 uint8_t POR : 1; /*!< [7] Power-On Reset */
Kojto 90:cb3d968589d8 132 } B;
Kojto 90:cb3d968589d8 133 } hw_rcm_srs0_t;
Kojto 90:cb3d968589d8 134
Kojto 90:cb3d968589d8 135 /*!
Kojto 90:cb3d968589d8 136 * @name Constants and macros for entire RCM_SRS0 register
Kojto 90:cb3d968589d8 137 */
Kojto 90:cb3d968589d8 138 /*@{*/
Kojto 90:cb3d968589d8 139 #define HW_RCM_SRS0_ADDR(x) ((x) + 0x0U)
Kojto 90:cb3d968589d8 140
Kojto 90:cb3d968589d8 141 #define HW_RCM_SRS0(x) (*(__I hw_rcm_srs0_t *) HW_RCM_SRS0_ADDR(x))
Kojto 90:cb3d968589d8 142 #define HW_RCM_SRS0_RD(x) (HW_RCM_SRS0(x).U)
Kojto 90:cb3d968589d8 143 /*@}*/
Kojto 90:cb3d968589d8 144
Kojto 90:cb3d968589d8 145 /*
Kojto 90:cb3d968589d8 146 * Constants & macros for individual RCM_SRS0 bitfields
Kojto 90:cb3d968589d8 147 */
Kojto 90:cb3d968589d8 148
Kojto 90:cb3d968589d8 149 /*!
Kojto 90:cb3d968589d8 150 * @name Register RCM_SRS0, field WAKEUP[0] (RO)
Kojto 90:cb3d968589d8 151 *
Kojto 90:cb3d968589d8 152 * Indicates a reset has been caused by an enabled LLWU module wakeup source
Kojto 90:cb3d968589d8 153 * while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only
Kojto 90:cb3d968589d8 154 * wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx
Kojto 90:cb3d968589d8 155 * mode causes a reset. This bit is cleared by any reset except WAKEUP.
Kojto 90:cb3d968589d8 156 *
Kojto 90:cb3d968589d8 157 * Values:
Kojto 90:cb3d968589d8 158 * - 0 - Reset not caused by LLWU module wakeup source
Kojto 90:cb3d968589d8 159 * - 1 - Reset caused by LLWU module wakeup source
Kojto 90:cb3d968589d8 160 */
Kojto 90:cb3d968589d8 161 /*@{*/
Kojto 90:cb3d968589d8 162 #define BP_RCM_SRS0_WAKEUP (0U) /*!< Bit position for RCM_SRS0_WAKEUP. */
Kojto 90:cb3d968589d8 163 #define BM_RCM_SRS0_WAKEUP (0x01U) /*!< Bit mask for RCM_SRS0_WAKEUP. */
Kojto 90:cb3d968589d8 164 #define BS_RCM_SRS0_WAKEUP (1U) /*!< Bit field size in bits for RCM_SRS0_WAKEUP. */
Kojto 90:cb3d968589d8 165
Kojto 90:cb3d968589d8 166 /*! @brief Read current value of the RCM_SRS0_WAKEUP field. */
Kojto 90:cb3d968589d8 167 #define BR_RCM_SRS0_WAKEUP(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_WAKEUP))
Kojto 90:cb3d968589d8 168 /*@}*/
Kojto 90:cb3d968589d8 169
Kojto 90:cb3d968589d8 170 /*!
Kojto 90:cb3d968589d8 171 * @name Register RCM_SRS0, field LVD[1] (RO)
Kojto 90:cb3d968589d8 172 *
Kojto 90:cb3d968589d8 173 * If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage,
Kojto 90:cb3d968589d8 174 * an LVD reset occurs. This field is also set by POR.
Kojto 90:cb3d968589d8 175 *
Kojto 90:cb3d968589d8 176 * Values:
Kojto 90:cb3d968589d8 177 * - 0 - Reset not caused by LVD trip or POR
Kojto 90:cb3d968589d8 178 * - 1 - Reset caused by LVD trip or POR
Kojto 90:cb3d968589d8 179 */
Kojto 90:cb3d968589d8 180 /*@{*/
Kojto 90:cb3d968589d8 181 #define BP_RCM_SRS0_LVD (1U) /*!< Bit position for RCM_SRS0_LVD. */
Kojto 90:cb3d968589d8 182 #define BM_RCM_SRS0_LVD (0x02U) /*!< Bit mask for RCM_SRS0_LVD. */
Kojto 90:cb3d968589d8 183 #define BS_RCM_SRS0_LVD (1U) /*!< Bit field size in bits for RCM_SRS0_LVD. */
Kojto 90:cb3d968589d8 184
Kojto 90:cb3d968589d8 185 /*! @brief Read current value of the RCM_SRS0_LVD field. */
Kojto 90:cb3d968589d8 186 #define BR_RCM_SRS0_LVD(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LVD))
Kojto 90:cb3d968589d8 187 /*@}*/
Kojto 90:cb3d968589d8 188
Kojto 90:cb3d968589d8 189 /*!
Kojto 90:cb3d968589d8 190 * @name Register RCM_SRS0, field LOC[2] (RO)
Kojto 90:cb3d968589d8 191 *
Kojto 90:cb3d968589d8 192 * Indicates a reset has been caused by a loss of external clock. The MCG clock
Kojto 90:cb3d968589d8 193 * monitor must be enabled for a loss of clock to be detected. Refer to the
Kojto 90:cb3d968589d8 194 * detailed MCG description for information on enabling the clock monitor.
Kojto 90:cb3d968589d8 195 *
Kojto 90:cb3d968589d8 196 * Values:
Kojto 90:cb3d968589d8 197 * - 0 - Reset not caused by a loss of external clock.
Kojto 90:cb3d968589d8 198 * - 1 - Reset caused by a loss of external clock.
Kojto 90:cb3d968589d8 199 */
Kojto 90:cb3d968589d8 200 /*@{*/
Kojto 90:cb3d968589d8 201 #define BP_RCM_SRS0_LOC (2U) /*!< Bit position for RCM_SRS0_LOC. */
Kojto 90:cb3d968589d8 202 #define BM_RCM_SRS0_LOC (0x04U) /*!< Bit mask for RCM_SRS0_LOC. */
Kojto 90:cb3d968589d8 203 #define BS_RCM_SRS0_LOC (1U) /*!< Bit field size in bits for RCM_SRS0_LOC. */
Kojto 90:cb3d968589d8 204
Kojto 90:cb3d968589d8 205 /*! @brief Read current value of the RCM_SRS0_LOC field. */
Kojto 90:cb3d968589d8 206 #define BR_RCM_SRS0_LOC(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LOC))
Kojto 90:cb3d968589d8 207 /*@}*/
Kojto 90:cb3d968589d8 208
Kojto 90:cb3d968589d8 209 /*!
Kojto 90:cb3d968589d8 210 * @name Register RCM_SRS0, field LOL[3] (RO)
Kojto 90:cb3d968589d8 211 *
Kojto 90:cb3d968589d8 212 * Indicates a reset has been caused by a loss of lock in the MCG PLL. See the
Kojto 90:cb3d968589d8 213 * MCG description for information on the loss-of-clock event.
Kojto 90:cb3d968589d8 214 *
Kojto 90:cb3d968589d8 215 * Values:
Kojto 90:cb3d968589d8 216 * - 0 - Reset not caused by a loss of lock in the PLL
Kojto 90:cb3d968589d8 217 * - 1 - Reset caused by a loss of lock in the PLL
Kojto 90:cb3d968589d8 218 */
Kojto 90:cb3d968589d8 219 /*@{*/
Kojto 90:cb3d968589d8 220 #define BP_RCM_SRS0_LOL (3U) /*!< Bit position for RCM_SRS0_LOL. */
Kojto 90:cb3d968589d8 221 #define BM_RCM_SRS0_LOL (0x08U) /*!< Bit mask for RCM_SRS0_LOL. */
Kojto 90:cb3d968589d8 222 #define BS_RCM_SRS0_LOL (1U) /*!< Bit field size in bits for RCM_SRS0_LOL. */
Kojto 90:cb3d968589d8 223
Kojto 90:cb3d968589d8 224 /*! @brief Read current value of the RCM_SRS0_LOL field. */
Kojto 90:cb3d968589d8 225 #define BR_RCM_SRS0_LOL(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LOL))
Kojto 90:cb3d968589d8 226 /*@}*/
Kojto 90:cb3d968589d8 227
Kojto 90:cb3d968589d8 228 /*!
Kojto 90:cb3d968589d8 229 * @name Register RCM_SRS0, field WDOG[5] (RO)
Kojto 90:cb3d968589d8 230 *
Kojto 90:cb3d968589d8 231 * Indicates a reset has been caused by the watchdog timer Computer Operating
Kojto 90:cb3d968589d8 232 * Properly (COP) timing out. This reset source can be blocked by disabling the COP
Kojto 90:cb3d968589d8 233 * watchdog: write 00 to SIM_COPCTRL[COPT].
Kojto 90:cb3d968589d8 234 *
Kojto 90:cb3d968589d8 235 * Values:
Kojto 90:cb3d968589d8 236 * - 0 - Reset not caused by watchdog timeout
Kojto 90:cb3d968589d8 237 * - 1 - Reset caused by watchdog timeout
Kojto 90:cb3d968589d8 238 */
Kojto 90:cb3d968589d8 239 /*@{*/
Kojto 90:cb3d968589d8 240 #define BP_RCM_SRS0_WDOG (5U) /*!< Bit position for RCM_SRS0_WDOG. */
Kojto 90:cb3d968589d8 241 #define BM_RCM_SRS0_WDOG (0x20U) /*!< Bit mask for RCM_SRS0_WDOG. */
Kojto 90:cb3d968589d8 242 #define BS_RCM_SRS0_WDOG (1U) /*!< Bit field size in bits for RCM_SRS0_WDOG. */
Kojto 90:cb3d968589d8 243
Kojto 90:cb3d968589d8 244 /*! @brief Read current value of the RCM_SRS0_WDOG field. */
Kojto 90:cb3d968589d8 245 #define BR_RCM_SRS0_WDOG(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_WDOG))
Kojto 90:cb3d968589d8 246 /*@}*/
Kojto 90:cb3d968589d8 247
Kojto 90:cb3d968589d8 248 /*!
Kojto 90:cb3d968589d8 249 * @name Register RCM_SRS0, field PIN[6] (RO)
Kojto 90:cb3d968589d8 250 *
Kojto 90:cb3d968589d8 251 * Indicates a reset has been caused by an active-low level on the external
Kojto 90:cb3d968589d8 252 * RESET pin.
Kojto 90:cb3d968589d8 253 *
Kojto 90:cb3d968589d8 254 * Values:
Kojto 90:cb3d968589d8 255 * - 0 - Reset not caused by external reset pin
Kojto 90:cb3d968589d8 256 * - 1 - Reset caused by external reset pin
Kojto 90:cb3d968589d8 257 */
Kojto 90:cb3d968589d8 258 /*@{*/
Kojto 90:cb3d968589d8 259 #define BP_RCM_SRS0_PIN (6U) /*!< Bit position for RCM_SRS0_PIN. */
Kojto 90:cb3d968589d8 260 #define BM_RCM_SRS0_PIN (0x40U) /*!< Bit mask for RCM_SRS0_PIN. */
Kojto 90:cb3d968589d8 261 #define BS_RCM_SRS0_PIN (1U) /*!< Bit field size in bits for RCM_SRS0_PIN. */
Kojto 90:cb3d968589d8 262
Kojto 90:cb3d968589d8 263 /*! @brief Read current value of the RCM_SRS0_PIN field. */
Kojto 90:cb3d968589d8 264 #define BR_RCM_SRS0_PIN(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_PIN))
Kojto 90:cb3d968589d8 265 /*@}*/
Kojto 90:cb3d968589d8 266
Kojto 90:cb3d968589d8 267 /*!
Kojto 90:cb3d968589d8 268 * @name Register RCM_SRS0, field POR[7] (RO)
Kojto 90:cb3d968589d8 269 *
Kojto 90:cb3d968589d8 270 * Indicates a reset has been caused by the power-on detection logic. Because
Kojto 90:cb3d968589d8 271 * the internal supply voltage was ramping up at the time, the low-voltage reset
Kojto 90:cb3d968589d8 272 * (LVD) status bit is also set to indicate that the reset occurred while the
Kojto 90:cb3d968589d8 273 * internal supply was below the LVD threshold.
Kojto 90:cb3d968589d8 274 *
Kojto 90:cb3d968589d8 275 * Values:
Kojto 90:cb3d968589d8 276 * - 0 - Reset not caused by POR
Kojto 90:cb3d968589d8 277 * - 1 - Reset caused by POR
Kojto 90:cb3d968589d8 278 */
Kojto 90:cb3d968589d8 279 /*@{*/
Kojto 90:cb3d968589d8 280 #define BP_RCM_SRS0_POR (7U) /*!< Bit position for RCM_SRS0_POR. */
Kojto 90:cb3d968589d8 281 #define BM_RCM_SRS0_POR (0x80U) /*!< Bit mask for RCM_SRS0_POR. */
Kojto 90:cb3d968589d8 282 #define BS_RCM_SRS0_POR (1U) /*!< Bit field size in bits for RCM_SRS0_POR. */
Kojto 90:cb3d968589d8 283
Kojto 90:cb3d968589d8 284 /*! @brief Read current value of the RCM_SRS0_POR field. */
Kojto 90:cb3d968589d8 285 #define BR_RCM_SRS0_POR(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_POR))
Kojto 90:cb3d968589d8 286 /*@}*/
Kojto 90:cb3d968589d8 287
Kojto 90:cb3d968589d8 288 /*******************************************************************************
Kojto 90:cb3d968589d8 289 * HW_RCM_SRS1 - System Reset Status Register 1
Kojto 90:cb3d968589d8 290 ******************************************************************************/
Kojto 90:cb3d968589d8 291
Kojto 90:cb3d968589d8 292 /*!
Kojto 90:cb3d968589d8 293 * @brief HW_RCM_SRS1 - System Reset Status Register 1 (RO)
Kojto 90:cb3d968589d8 294 *
Kojto 90:cb3d968589d8 295 * Reset value: 0x00U
Kojto 90:cb3d968589d8 296 *
Kojto 90:cb3d968589d8 297 * This register includes read-only status flags to indicate the source of the
Kojto 90:cb3d968589d8 298 * most recent reset. The reset state of these bits depends on what caused the MCU
Kojto 90:cb3d968589d8 299 * to reset. The reset value of this register depends on the reset source: POR
Kojto 90:cb3d968589d8 300 * (including LVD) - 0x00 LVD (without POR) - 0x00 VLLS mode wakeup - 0x00 Other
Kojto 90:cb3d968589d8 301 * reset - a bit is set if its corresponding reset source caused the reset
Kojto 90:cb3d968589d8 302 */
Kojto 90:cb3d968589d8 303 typedef union _hw_rcm_srs1
Kojto 90:cb3d968589d8 304 {
Kojto 90:cb3d968589d8 305 uint8_t U;
Kojto 90:cb3d968589d8 306 struct _hw_rcm_srs1_bitfields
Kojto 90:cb3d968589d8 307 {
Kojto 90:cb3d968589d8 308 uint8_t JTAG : 1; /*!< [0] JTAG Generated Reset */
Kojto 90:cb3d968589d8 309 uint8_t LOCKUP : 1; /*!< [1] Core Lockup */
Kojto 90:cb3d968589d8 310 uint8_t SW : 1; /*!< [2] Software */
Kojto 90:cb3d968589d8 311 uint8_t MDM_AP : 1; /*!< [3] MDM-AP System Reset Request */
Kojto 90:cb3d968589d8 312 uint8_t EZPT : 1; /*!< [4] EzPort Reset */
Kojto 90:cb3d968589d8 313 uint8_t SACKERR : 1; /*!< [5] Stop Mode Acknowledge Error Reset */
Kojto 90:cb3d968589d8 314 uint8_t RESERVED0 : 2; /*!< [7:6] */
Kojto 90:cb3d968589d8 315 } B;
Kojto 90:cb3d968589d8 316 } hw_rcm_srs1_t;
Kojto 90:cb3d968589d8 317
Kojto 90:cb3d968589d8 318 /*!
Kojto 90:cb3d968589d8 319 * @name Constants and macros for entire RCM_SRS1 register
Kojto 90:cb3d968589d8 320 */
Kojto 90:cb3d968589d8 321 /*@{*/
Kojto 90:cb3d968589d8 322 #define HW_RCM_SRS1_ADDR(x) ((x) + 0x1U)
Kojto 90:cb3d968589d8 323
Kojto 90:cb3d968589d8 324 #define HW_RCM_SRS1(x) (*(__I hw_rcm_srs1_t *) HW_RCM_SRS1_ADDR(x))
Kojto 90:cb3d968589d8 325 #define HW_RCM_SRS1_RD(x) (HW_RCM_SRS1(x).U)
Kojto 90:cb3d968589d8 326 /*@}*/
Kojto 90:cb3d968589d8 327
Kojto 90:cb3d968589d8 328 /*
Kojto 90:cb3d968589d8 329 * Constants & macros for individual RCM_SRS1 bitfields
Kojto 90:cb3d968589d8 330 */
Kojto 90:cb3d968589d8 331
Kojto 90:cb3d968589d8 332 /*!
Kojto 90:cb3d968589d8 333 * @name Register RCM_SRS1, field JTAG[0] (RO)
Kojto 90:cb3d968589d8 334 *
Kojto 90:cb3d968589d8 335 * Indicates a reset has been caused by JTAG selection of certain IR codes:
Kojto 90:cb3d968589d8 336 * EZPORT, EXTEST, HIGHZ, and CLAMP.
Kojto 90:cb3d968589d8 337 *
Kojto 90:cb3d968589d8 338 * Values:
Kojto 90:cb3d968589d8 339 * - 0 - Reset not caused by JTAG
Kojto 90:cb3d968589d8 340 * - 1 - Reset caused by JTAG
Kojto 90:cb3d968589d8 341 */
Kojto 90:cb3d968589d8 342 /*@{*/
Kojto 90:cb3d968589d8 343 #define BP_RCM_SRS1_JTAG (0U) /*!< Bit position for RCM_SRS1_JTAG. */
Kojto 90:cb3d968589d8 344 #define BM_RCM_SRS1_JTAG (0x01U) /*!< Bit mask for RCM_SRS1_JTAG. */
Kojto 90:cb3d968589d8 345 #define BS_RCM_SRS1_JTAG (1U) /*!< Bit field size in bits for RCM_SRS1_JTAG. */
Kojto 90:cb3d968589d8 346
Kojto 90:cb3d968589d8 347 /*! @brief Read current value of the RCM_SRS1_JTAG field. */
Kojto 90:cb3d968589d8 348 #define BR_RCM_SRS1_JTAG(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_JTAG))
Kojto 90:cb3d968589d8 349 /*@}*/
Kojto 90:cb3d968589d8 350
Kojto 90:cb3d968589d8 351 /*!
Kojto 90:cb3d968589d8 352 * @name Register RCM_SRS1, field LOCKUP[1] (RO)
Kojto 90:cb3d968589d8 353 *
Kojto 90:cb3d968589d8 354 * Indicates a reset has been caused by the ARM core indication of a LOCKUP
Kojto 90:cb3d968589d8 355 * event.
Kojto 90:cb3d968589d8 356 *
Kojto 90:cb3d968589d8 357 * Values:
Kojto 90:cb3d968589d8 358 * - 0 - Reset not caused by core LOCKUP event
Kojto 90:cb3d968589d8 359 * - 1 - Reset caused by core LOCKUP event
Kojto 90:cb3d968589d8 360 */
Kojto 90:cb3d968589d8 361 /*@{*/
Kojto 90:cb3d968589d8 362 #define BP_RCM_SRS1_LOCKUP (1U) /*!< Bit position for RCM_SRS1_LOCKUP. */
Kojto 90:cb3d968589d8 363 #define BM_RCM_SRS1_LOCKUP (0x02U) /*!< Bit mask for RCM_SRS1_LOCKUP. */
Kojto 90:cb3d968589d8 364 #define BS_RCM_SRS1_LOCKUP (1U) /*!< Bit field size in bits for RCM_SRS1_LOCKUP. */
Kojto 90:cb3d968589d8 365
Kojto 90:cb3d968589d8 366 /*! @brief Read current value of the RCM_SRS1_LOCKUP field. */
Kojto 90:cb3d968589d8 367 #define BR_RCM_SRS1_LOCKUP(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_LOCKUP))
Kojto 90:cb3d968589d8 368 /*@}*/
Kojto 90:cb3d968589d8 369
Kojto 90:cb3d968589d8 370 /*!
Kojto 90:cb3d968589d8 371 * @name Register RCM_SRS1, field SW[2] (RO)
Kojto 90:cb3d968589d8 372 *
Kojto 90:cb3d968589d8 373 * Indicates a reset has been caused by software setting of SYSRESETREQ bit in
Kojto 90:cb3d968589d8 374 * Application Interrupt and Reset Control Register in the ARM core.
Kojto 90:cb3d968589d8 375 *
Kojto 90:cb3d968589d8 376 * Values:
Kojto 90:cb3d968589d8 377 * - 0 - Reset not caused by software setting of SYSRESETREQ bit
Kojto 90:cb3d968589d8 378 * - 1 - Reset caused by software setting of SYSRESETREQ bit
Kojto 90:cb3d968589d8 379 */
Kojto 90:cb3d968589d8 380 /*@{*/
Kojto 90:cb3d968589d8 381 #define BP_RCM_SRS1_SW (2U) /*!< Bit position for RCM_SRS1_SW. */
Kojto 90:cb3d968589d8 382 #define BM_RCM_SRS1_SW (0x04U) /*!< Bit mask for RCM_SRS1_SW. */
Kojto 90:cb3d968589d8 383 #define BS_RCM_SRS1_SW (1U) /*!< Bit field size in bits for RCM_SRS1_SW. */
Kojto 90:cb3d968589d8 384
Kojto 90:cb3d968589d8 385 /*! @brief Read current value of the RCM_SRS1_SW field. */
Kojto 90:cb3d968589d8 386 #define BR_RCM_SRS1_SW(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_SW))
Kojto 90:cb3d968589d8 387 /*@}*/
Kojto 90:cb3d968589d8 388
Kojto 90:cb3d968589d8 389 /*!
Kojto 90:cb3d968589d8 390 * @name Register RCM_SRS1, field MDM_AP[3] (RO)
Kojto 90:cb3d968589d8 391 *
Kojto 90:cb3d968589d8 392 * Indicates a reset has been caused by the host debugger system setting of the
Kojto 90:cb3d968589d8 393 * System Reset Request bit in the MDM-AP Control Register.
Kojto 90:cb3d968589d8 394 *
Kojto 90:cb3d968589d8 395 * Values:
Kojto 90:cb3d968589d8 396 * - 0 - Reset not caused by host debugger system setting of the System Reset
Kojto 90:cb3d968589d8 397 * Request bit
Kojto 90:cb3d968589d8 398 * - 1 - Reset caused by host debugger system setting of the System Reset
Kojto 90:cb3d968589d8 399 * Request bit
Kojto 90:cb3d968589d8 400 */
Kojto 90:cb3d968589d8 401 /*@{*/
Kojto 90:cb3d968589d8 402 #define BP_RCM_SRS1_MDM_AP (3U) /*!< Bit position for RCM_SRS1_MDM_AP. */
Kojto 90:cb3d968589d8 403 #define BM_RCM_SRS1_MDM_AP (0x08U) /*!< Bit mask for RCM_SRS1_MDM_AP. */
Kojto 90:cb3d968589d8 404 #define BS_RCM_SRS1_MDM_AP (1U) /*!< Bit field size in bits for RCM_SRS1_MDM_AP. */
Kojto 90:cb3d968589d8 405
Kojto 90:cb3d968589d8 406 /*! @brief Read current value of the RCM_SRS1_MDM_AP field. */
Kojto 90:cb3d968589d8 407 #define BR_RCM_SRS1_MDM_AP(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_MDM_AP))
Kojto 90:cb3d968589d8 408 /*@}*/
Kojto 90:cb3d968589d8 409
Kojto 90:cb3d968589d8 410 /*!
Kojto 90:cb3d968589d8 411 * @name Register RCM_SRS1, field EZPT[4] (RO)
Kojto 90:cb3d968589d8 412 *
Kojto 90:cb3d968589d8 413 * Indicates a reset has been caused by EzPort receiving the RESET command while
Kojto 90:cb3d968589d8 414 * the device is in EzPort mode.
Kojto 90:cb3d968589d8 415 *
Kojto 90:cb3d968589d8 416 * Values:
Kojto 90:cb3d968589d8 417 * - 0 - Reset not caused by EzPort receiving the RESET command while the device
Kojto 90:cb3d968589d8 418 * is in EzPort mode
Kojto 90:cb3d968589d8 419 * - 1 - Reset caused by EzPort receiving the RESET command while the device is
Kojto 90:cb3d968589d8 420 * in EzPort mode
Kojto 90:cb3d968589d8 421 */
Kojto 90:cb3d968589d8 422 /*@{*/
Kojto 90:cb3d968589d8 423 #define BP_RCM_SRS1_EZPT (4U) /*!< Bit position for RCM_SRS1_EZPT. */
Kojto 90:cb3d968589d8 424 #define BM_RCM_SRS1_EZPT (0x10U) /*!< Bit mask for RCM_SRS1_EZPT. */
Kojto 90:cb3d968589d8 425 #define BS_RCM_SRS1_EZPT (1U) /*!< Bit field size in bits for RCM_SRS1_EZPT. */
Kojto 90:cb3d968589d8 426
Kojto 90:cb3d968589d8 427 /*! @brief Read current value of the RCM_SRS1_EZPT field. */
Kojto 90:cb3d968589d8 428 #define BR_RCM_SRS1_EZPT(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_EZPT))
Kojto 90:cb3d968589d8 429 /*@}*/
Kojto 90:cb3d968589d8 430
Kojto 90:cb3d968589d8 431 /*!
Kojto 90:cb3d968589d8 432 * @name Register RCM_SRS1, field SACKERR[5] (RO)
Kojto 90:cb3d968589d8 433 *
Kojto 90:cb3d968589d8 434 * Indicates that after an attempt to enter Stop mode, a reset has been caused
Kojto 90:cb3d968589d8 435 * by a failure of one or more peripherals to acknowledge within approximately one
Kojto 90:cb3d968589d8 436 * second to enter stop mode.
Kojto 90:cb3d968589d8 437 *
Kojto 90:cb3d968589d8 438 * Values:
Kojto 90:cb3d968589d8 439 * - 0 - Reset not caused by peripheral failure to acknowledge attempt to enter
Kojto 90:cb3d968589d8 440 * stop mode
Kojto 90:cb3d968589d8 441 * - 1 - Reset caused by peripheral failure to acknowledge attempt to enter stop
Kojto 90:cb3d968589d8 442 * mode
Kojto 90:cb3d968589d8 443 */
Kojto 90:cb3d968589d8 444 /*@{*/
Kojto 90:cb3d968589d8 445 #define BP_RCM_SRS1_SACKERR (5U) /*!< Bit position for RCM_SRS1_SACKERR. */
Kojto 90:cb3d968589d8 446 #define BM_RCM_SRS1_SACKERR (0x20U) /*!< Bit mask for RCM_SRS1_SACKERR. */
Kojto 90:cb3d968589d8 447 #define BS_RCM_SRS1_SACKERR (1U) /*!< Bit field size in bits for RCM_SRS1_SACKERR. */
Kojto 90:cb3d968589d8 448
Kojto 90:cb3d968589d8 449 /*! @brief Read current value of the RCM_SRS1_SACKERR field. */
Kojto 90:cb3d968589d8 450 #define BR_RCM_SRS1_SACKERR(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_SACKERR))
Kojto 90:cb3d968589d8 451 /*@}*/
Kojto 90:cb3d968589d8 452
Kojto 90:cb3d968589d8 453 /*******************************************************************************
Kojto 90:cb3d968589d8 454 * HW_RCM_RPFC - Reset Pin Filter Control register
Kojto 90:cb3d968589d8 455 ******************************************************************************/
Kojto 90:cb3d968589d8 456
Kojto 90:cb3d968589d8 457 /*!
Kojto 90:cb3d968589d8 458 * @brief HW_RCM_RPFC - Reset Pin Filter Control register (RW)
Kojto 90:cb3d968589d8 459 *
Kojto 90:cb3d968589d8 460 * Reset value: 0x00U
Kojto 90:cb3d968589d8 461 *
Kojto 90:cb3d968589d8 462 * The reset values of bits 2-0 are for Chip POR only. They are unaffected by
Kojto 90:cb3d968589d8 463 * other reset types. The bus clock filter is reset when disabled or when entering
Kojto 90:cb3d968589d8 464 * stop mode. The LPO filter is reset when disabled or when entering any low
Kojto 90:cb3d968589d8 465 * leakage stop mode .
Kojto 90:cb3d968589d8 466 */
Kojto 90:cb3d968589d8 467 typedef union _hw_rcm_rpfc
Kojto 90:cb3d968589d8 468 {
Kojto 90:cb3d968589d8 469 uint8_t U;
Kojto 90:cb3d968589d8 470 struct _hw_rcm_rpfc_bitfields
Kojto 90:cb3d968589d8 471 {
Kojto 90:cb3d968589d8 472 uint8_t RSTFLTSRW : 2; /*!< [1:0] Reset Pin Filter Select in Run and
Kojto 90:cb3d968589d8 473 * Wait Modes */
Kojto 90:cb3d968589d8 474 uint8_t RSTFLTSS : 1; /*!< [2] Reset Pin Filter Select in Stop Mode */
Kojto 90:cb3d968589d8 475 uint8_t RESERVED0 : 5; /*!< [7:3] */
Kojto 90:cb3d968589d8 476 } B;
Kojto 90:cb3d968589d8 477 } hw_rcm_rpfc_t;
Kojto 90:cb3d968589d8 478
Kojto 90:cb3d968589d8 479 /*!
Kojto 90:cb3d968589d8 480 * @name Constants and macros for entire RCM_RPFC register
Kojto 90:cb3d968589d8 481 */
Kojto 90:cb3d968589d8 482 /*@{*/
Kojto 90:cb3d968589d8 483 #define HW_RCM_RPFC_ADDR(x) ((x) + 0x4U)
Kojto 90:cb3d968589d8 484
Kojto 90:cb3d968589d8 485 #define HW_RCM_RPFC(x) (*(__IO hw_rcm_rpfc_t *) HW_RCM_RPFC_ADDR(x))
Kojto 90:cb3d968589d8 486 #define HW_RCM_RPFC_RD(x) (HW_RCM_RPFC(x).U)
Kojto 90:cb3d968589d8 487 #define HW_RCM_RPFC_WR(x, v) (HW_RCM_RPFC(x).U = (v))
Kojto 90:cb3d968589d8 488 #define HW_RCM_RPFC_SET(x, v) (HW_RCM_RPFC_WR(x, HW_RCM_RPFC_RD(x) | (v)))
Kojto 90:cb3d968589d8 489 #define HW_RCM_RPFC_CLR(x, v) (HW_RCM_RPFC_WR(x, HW_RCM_RPFC_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 490 #define HW_RCM_RPFC_TOG(x, v) (HW_RCM_RPFC_WR(x, HW_RCM_RPFC_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 491 /*@}*/
Kojto 90:cb3d968589d8 492
Kojto 90:cb3d968589d8 493 /*
Kojto 90:cb3d968589d8 494 * Constants & macros for individual RCM_RPFC bitfields
Kojto 90:cb3d968589d8 495 */
Kojto 90:cb3d968589d8 496
Kojto 90:cb3d968589d8 497 /*!
Kojto 90:cb3d968589d8 498 * @name Register RCM_RPFC, field RSTFLTSRW[1:0] (RW)
Kojto 90:cb3d968589d8 499 *
Kojto 90:cb3d968589d8 500 * Selects how the reset pin filter is enabled in run and wait modes.
Kojto 90:cb3d968589d8 501 *
Kojto 90:cb3d968589d8 502 * Values:
Kojto 90:cb3d968589d8 503 * - 00 - All filtering disabled
Kojto 90:cb3d968589d8 504 * - 01 - Bus clock filter enabled for normal operation
Kojto 90:cb3d968589d8 505 * - 10 - LPO clock filter enabled for normal operation
Kojto 90:cb3d968589d8 506 * - 11 - Reserved
Kojto 90:cb3d968589d8 507 */
Kojto 90:cb3d968589d8 508 /*@{*/
Kojto 90:cb3d968589d8 509 #define BP_RCM_RPFC_RSTFLTSRW (0U) /*!< Bit position for RCM_RPFC_RSTFLTSRW. */
Kojto 90:cb3d968589d8 510 #define BM_RCM_RPFC_RSTFLTSRW (0x03U) /*!< Bit mask for RCM_RPFC_RSTFLTSRW. */
Kojto 90:cb3d968589d8 511 #define BS_RCM_RPFC_RSTFLTSRW (2U) /*!< Bit field size in bits for RCM_RPFC_RSTFLTSRW. */
Kojto 90:cb3d968589d8 512
Kojto 90:cb3d968589d8 513 /*! @brief Read current value of the RCM_RPFC_RSTFLTSRW field. */
Kojto 90:cb3d968589d8 514 #define BR_RCM_RPFC_RSTFLTSRW(x) (HW_RCM_RPFC(x).B.RSTFLTSRW)
Kojto 90:cb3d968589d8 515
Kojto 90:cb3d968589d8 516 /*! @brief Format value for bitfield RCM_RPFC_RSTFLTSRW. */
Kojto 90:cb3d968589d8 517 #define BF_RCM_RPFC_RSTFLTSRW(v) ((uint8_t)((uint8_t)(v) << BP_RCM_RPFC_RSTFLTSRW) & BM_RCM_RPFC_RSTFLTSRW)
Kojto 90:cb3d968589d8 518
Kojto 90:cb3d968589d8 519 /*! @brief Set the RSTFLTSRW field to a new value. */
Kojto 90:cb3d968589d8 520 #define BW_RCM_RPFC_RSTFLTSRW(x, v) (HW_RCM_RPFC_WR(x, (HW_RCM_RPFC_RD(x) & ~BM_RCM_RPFC_RSTFLTSRW) | BF_RCM_RPFC_RSTFLTSRW(v)))
Kojto 90:cb3d968589d8 521 /*@}*/
Kojto 90:cb3d968589d8 522
Kojto 90:cb3d968589d8 523 /*!
Kojto 90:cb3d968589d8 524 * @name Register RCM_RPFC, field RSTFLTSS[2] (RW)
Kojto 90:cb3d968589d8 525 *
Kojto 90:cb3d968589d8 526 * Selects how the reset pin filter is enabled in Stop and VLPS modes
Kojto 90:cb3d968589d8 527 *
Kojto 90:cb3d968589d8 528 * Values:
Kojto 90:cb3d968589d8 529 * - 0 - All filtering disabled
Kojto 90:cb3d968589d8 530 * - 1 - LPO clock filter enabled
Kojto 90:cb3d968589d8 531 */
Kojto 90:cb3d968589d8 532 /*@{*/
Kojto 90:cb3d968589d8 533 #define BP_RCM_RPFC_RSTFLTSS (2U) /*!< Bit position for RCM_RPFC_RSTFLTSS. */
Kojto 90:cb3d968589d8 534 #define BM_RCM_RPFC_RSTFLTSS (0x04U) /*!< Bit mask for RCM_RPFC_RSTFLTSS. */
Kojto 90:cb3d968589d8 535 #define BS_RCM_RPFC_RSTFLTSS (1U) /*!< Bit field size in bits for RCM_RPFC_RSTFLTSS. */
Kojto 90:cb3d968589d8 536
Kojto 90:cb3d968589d8 537 /*! @brief Read current value of the RCM_RPFC_RSTFLTSS field. */
Kojto 90:cb3d968589d8 538 #define BR_RCM_RPFC_RSTFLTSS(x) (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR(x), BP_RCM_RPFC_RSTFLTSS))
Kojto 90:cb3d968589d8 539
Kojto 90:cb3d968589d8 540 /*! @brief Format value for bitfield RCM_RPFC_RSTFLTSS. */
Kojto 90:cb3d968589d8 541 #define BF_RCM_RPFC_RSTFLTSS(v) ((uint8_t)((uint8_t)(v) << BP_RCM_RPFC_RSTFLTSS) & BM_RCM_RPFC_RSTFLTSS)
Kojto 90:cb3d968589d8 542
Kojto 90:cb3d968589d8 543 /*! @brief Set the RSTFLTSS field to a new value. */
Kojto 90:cb3d968589d8 544 #define BW_RCM_RPFC_RSTFLTSS(x, v) (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR(x), BP_RCM_RPFC_RSTFLTSS) = (v))
Kojto 90:cb3d968589d8 545 /*@}*/
Kojto 90:cb3d968589d8 546
Kojto 90:cb3d968589d8 547 /*******************************************************************************
Kojto 90:cb3d968589d8 548 * HW_RCM_RPFW - Reset Pin Filter Width register
Kojto 90:cb3d968589d8 549 ******************************************************************************/
Kojto 90:cb3d968589d8 550
Kojto 90:cb3d968589d8 551 /*!
Kojto 90:cb3d968589d8 552 * @brief HW_RCM_RPFW - Reset Pin Filter Width register (RW)
Kojto 90:cb3d968589d8 553 *
Kojto 90:cb3d968589d8 554 * Reset value: 0x00U
Kojto 90:cb3d968589d8 555 *
Kojto 90:cb3d968589d8 556 * The reset values of the bits in the RSTFLTSEL field are for Chip POR only.
Kojto 90:cb3d968589d8 557 * They are unaffected by other reset types.
Kojto 90:cb3d968589d8 558 */
Kojto 90:cb3d968589d8 559 typedef union _hw_rcm_rpfw
Kojto 90:cb3d968589d8 560 {
Kojto 90:cb3d968589d8 561 uint8_t U;
Kojto 90:cb3d968589d8 562 struct _hw_rcm_rpfw_bitfields
Kojto 90:cb3d968589d8 563 {
Kojto 90:cb3d968589d8 564 uint8_t RSTFLTSEL : 5; /*!< [4:0] Reset Pin Filter Bus Clock Select */
Kojto 90:cb3d968589d8 565 uint8_t RESERVED0 : 3; /*!< [7:5] */
Kojto 90:cb3d968589d8 566 } B;
Kojto 90:cb3d968589d8 567 } hw_rcm_rpfw_t;
Kojto 90:cb3d968589d8 568
Kojto 90:cb3d968589d8 569 /*!
Kojto 90:cb3d968589d8 570 * @name Constants and macros for entire RCM_RPFW register
Kojto 90:cb3d968589d8 571 */
Kojto 90:cb3d968589d8 572 /*@{*/
Kojto 90:cb3d968589d8 573 #define HW_RCM_RPFW_ADDR(x) ((x) + 0x5U)
Kojto 90:cb3d968589d8 574
Kojto 90:cb3d968589d8 575 #define HW_RCM_RPFW(x) (*(__IO hw_rcm_rpfw_t *) HW_RCM_RPFW_ADDR(x))
Kojto 90:cb3d968589d8 576 #define HW_RCM_RPFW_RD(x) (HW_RCM_RPFW(x).U)
Kojto 90:cb3d968589d8 577 #define HW_RCM_RPFW_WR(x, v) (HW_RCM_RPFW(x).U = (v))
Kojto 90:cb3d968589d8 578 #define HW_RCM_RPFW_SET(x, v) (HW_RCM_RPFW_WR(x, HW_RCM_RPFW_RD(x) | (v)))
Kojto 90:cb3d968589d8 579 #define HW_RCM_RPFW_CLR(x, v) (HW_RCM_RPFW_WR(x, HW_RCM_RPFW_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 580 #define HW_RCM_RPFW_TOG(x, v) (HW_RCM_RPFW_WR(x, HW_RCM_RPFW_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 581 /*@}*/
Kojto 90:cb3d968589d8 582
Kojto 90:cb3d968589d8 583 /*
Kojto 90:cb3d968589d8 584 * Constants & macros for individual RCM_RPFW bitfields
Kojto 90:cb3d968589d8 585 */
Kojto 90:cb3d968589d8 586
Kojto 90:cb3d968589d8 587 /*!
Kojto 90:cb3d968589d8 588 * @name Register RCM_RPFW, field RSTFLTSEL[4:0] (RW)
Kojto 90:cb3d968589d8 589 *
Kojto 90:cb3d968589d8 590 * Selects the reset pin bus clock filter width.
Kojto 90:cb3d968589d8 591 *
Kojto 90:cb3d968589d8 592 * Values:
Kojto 90:cb3d968589d8 593 * - 00000 - Bus clock filter count is 1
Kojto 90:cb3d968589d8 594 * - 00001 - Bus clock filter count is 2
Kojto 90:cb3d968589d8 595 * - 00010 - Bus clock filter count is 3
Kojto 90:cb3d968589d8 596 * - 00011 - Bus clock filter count is 4
Kojto 90:cb3d968589d8 597 * - 00100 - Bus clock filter count is 5
Kojto 90:cb3d968589d8 598 * - 00101 - Bus clock filter count is 6
Kojto 90:cb3d968589d8 599 * - 00110 - Bus clock filter count is 7
Kojto 90:cb3d968589d8 600 * - 00111 - Bus clock filter count is 8
Kojto 90:cb3d968589d8 601 * - 01000 - Bus clock filter count is 9
Kojto 90:cb3d968589d8 602 * - 01001 - Bus clock filter count is 10
Kojto 90:cb3d968589d8 603 * - 01010 - Bus clock filter count is 11
Kojto 90:cb3d968589d8 604 * - 01011 - Bus clock filter count is 12
Kojto 90:cb3d968589d8 605 * - 01100 - Bus clock filter count is 13
Kojto 90:cb3d968589d8 606 * - 01101 - Bus clock filter count is 14
Kojto 90:cb3d968589d8 607 * - 01110 - Bus clock filter count is 15
Kojto 90:cb3d968589d8 608 * - 01111 - Bus clock filter count is 16
Kojto 90:cb3d968589d8 609 * - 10000 - Bus clock filter count is 17
Kojto 90:cb3d968589d8 610 * - 10001 - Bus clock filter count is 18
Kojto 90:cb3d968589d8 611 * - 10010 - Bus clock filter count is 19
Kojto 90:cb3d968589d8 612 * - 10011 - Bus clock filter count is 20
Kojto 90:cb3d968589d8 613 * - 10100 - Bus clock filter count is 21
Kojto 90:cb3d968589d8 614 * - 10101 - Bus clock filter count is 22
Kojto 90:cb3d968589d8 615 * - 10110 - Bus clock filter count is 23
Kojto 90:cb3d968589d8 616 * - 10111 - Bus clock filter count is 24
Kojto 90:cb3d968589d8 617 * - 11000 - Bus clock filter count is 25
Kojto 90:cb3d968589d8 618 * - 11001 - Bus clock filter count is 26
Kojto 90:cb3d968589d8 619 * - 11010 - Bus clock filter count is 27
Kojto 90:cb3d968589d8 620 * - 11011 - Bus clock filter count is 28
Kojto 90:cb3d968589d8 621 * - 11100 - Bus clock filter count is 29
Kojto 90:cb3d968589d8 622 * - 11101 - Bus clock filter count is 30
Kojto 90:cb3d968589d8 623 * - 11110 - Bus clock filter count is 31
Kojto 90:cb3d968589d8 624 * - 11111 - Bus clock filter count is 32
Kojto 90:cb3d968589d8 625 */
Kojto 90:cb3d968589d8 626 /*@{*/
Kojto 90:cb3d968589d8 627 #define BP_RCM_RPFW_RSTFLTSEL (0U) /*!< Bit position for RCM_RPFW_RSTFLTSEL. */
Kojto 90:cb3d968589d8 628 #define BM_RCM_RPFW_RSTFLTSEL (0x1FU) /*!< Bit mask for RCM_RPFW_RSTFLTSEL. */
Kojto 90:cb3d968589d8 629 #define BS_RCM_RPFW_RSTFLTSEL (5U) /*!< Bit field size in bits for RCM_RPFW_RSTFLTSEL. */
Kojto 90:cb3d968589d8 630
Kojto 90:cb3d968589d8 631 /*! @brief Read current value of the RCM_RPFW_RSTFLTSEL field. */
Kojto 90:cb3d968589d8 632 #define BR_RCM_RPFW_RSTFLTSEL(x) (HW_RCM_RPFW(x).B.RSTFLTSEL)
Kojto 90:cb3d968589d8 633
Kojto 90:cb3d968589d8 634 /*! @brief Format value for bitfield RCM_RPFW_RSTFLTSEL. */
Kojto 90:cb3d968589d8 635 #define BF_RCM_RPFW_RSTFLTSEL(v) ((uint8_t)((uint8_t)(v) << BP_RCM_RPFW_RSTFLTSEL) & BM_RCM_RPFW_RSTFLTSEL)
Kojto 90:cb3d968589d8 636
Kojto 90:cb3d968589d8 637 /*! @brief Set the RSTFLTSEL field to a new value. */
Kojto 90:cb3d968589d8 638 #define BW_RCM_RPFW_RSTFLTSEL(x, v) (HW_RCM_RPFW_WR(x, (HW_RCM_RPFW_RD(x) & ~BM_RCM_RPFW_RSTFLTSEL) | BF_RCM_RPFW_RSTFLTSEL(v)))
Kojto 90:cb3d968589d8 639 /*@}*/
Kojto 90:cb3d968589d8 640
Kojto 90:cb3d968589d8 641 /*******************************************************************************
Kojto 90:cb3d968589d8 642 * HW_RCM_MR - Mode Register
Kojto 90:cb3d968589d8 643 ******************************************************************************/
Kojto 90:cb3d968589d8 644
Kojto 90:cb3d968589d8 645 /*!
Kojto 90:cb3d968589d8 646 * @brief HW_RCM_MR - Mode Register (RO)
Kojto 90:cb3d968589d8 647 *
Kojto 90:cb3d968589d8 648 * Reset value: 0x00U
Kojto 90:cb3d968589d8 649 *
Kojto 90:cb3d968589d8 650 * This register includes read-only status flags to indicate the state of the
Kojto 90:cb3d968589d8 651 * mode pins during the last Chip Reset.
Kojto 90:cb3d968589d8 652 */
Kojto 90:cb3d968589d8 653 typedef union _hw_rcm_mr
Kojto 90:cb3d968589d8 654 {
Kojto 90:cb3d968589d8 655 uint8_t U;
Kojto 90:cb3d968589d8 656 struct _hw_rcm_mr_bitfields
Kojto 90:cb3d968589d8 657 {
Kojto 90:cb3d968589d8 658 uint8_t RESERVED0 : 1; /*!< [0] */
Kojto 90:cb3d968589d8 659 uint8_t EZP_MS : 1; /*!< [1] EZP_MS_B pin state */
Kojto 90:cb3d968589d8 660 uint8_t RESERVED1 : 6; /*!< [7:2] */
Kojto 90:cb3d968589d8 661 } B;
Kojto 90:cb3d968589d8 662 } hw_rcm_mr_t;
Kojto 90:cb3d968589d8 663
Kojto 90:cb3d968589d8 664 /*!
Kojto 90:cb3d968589d8 665 * @name Constants and macros for entire RCM_MR register
Kojto 90:cb3d968589d8 666 */
Kojto 90:cb3d968589d8 667 /*@{*/
Kojto 90:cb3d968589d8 668 #define HW_RCM_MR_ADDR(x) ((x) + 0x7U)
Kojto 90:cb3d968589d8 669
Kojto 90:cb3d968589d8 670 #define HW_RCM_MR(x) (*(__I hw_rcm_mr_t *) HW_RCM_MR_ADDR(x))
Kojto 90:cb3d968589d8 671 #define HW_RCM_MR_RD(x) (HW_RCM_MR(x).U)
Kojto 90:cb3d968589d8 672 /*@}*/
Kojto 90:cb3d968589d8 673
Kojto 90:cb3d968589d8 674 /*
Kojto 90:cb3d968589d8 675 * Constants & macros for individual RCM_MR bitfields
Kojto 90:cb3d968589d8 676 */
Kojto 90:cb3d968589d8 677
Kojto 90:cb3d968589d8 678 /*!
Kojto 90:cb3d968589d8 679 * @name Register RCM_MR, field EZP_MS[1] (RO)
Kojto 90:cb3d968589d8 680 *
Kojto 90:cb3d968589d8 681 * Reflects the state of the EZP_MS pin during the last Chip Reset
Kojto 90:cb3d968589d8 682 *
Kojto 90:cb3d968589d8 683 * Values:
Kojto 90:cb3d968589d8 684 * - 0 - Pin deasserted (logic 1)
Kojto 90:cb3d968589d8 685 * - 1 - Pin asserted (logic 0)
Kojto 90:cb3d968589d8 686 */
Kojto 90:cb3d968589d8 687 /*@{*/
Kojto 90:cb3d968589d8 688 #define BP_RCM_MR_EZP_MS (1U) /*!< Bit position for RCM_MR_EZP_MS. */
Kojto 90:cb3d968589d8 689 #define BM_RCM_MR_EZP_MS (0x02U) /*!< Bit mask for RCM_MR_EZP_MS. */
Kojto 90:cb3d968589d8 690 #define BS_RCM_MR_EZP_MS (1U) /*!< Bit field size in bits for RCM_MR_EZP_MS. */
Kojto 90:cb3d968589d8 691
Kojto 90:cb3d968589d8 692 /*! @brief Read current value of the RCM_MR_EZP_MS field. */
Kojto 90:cb3d968589d8 693 #define BR_RCM_MR_EZP_MS(x) (BITBAND_ACCESS8(HW_RCM_MR_ADDR(x), BP_RCM_MR_EZP_MS))
Kojto 90:cb3d968589d8 694 /*@}*/
Kojto 90:cb3d968589d8 695
Kojto 90:cb3d968589d8 696 /*******************************************************************************
Kojto 90:cb3d968589d8 697 * hw_rcm_t - module struct
Kojto 90:cb3d968589d8 698 ******************************************************************************/
Kojto 90:cb3d968589d8 699 /*!
Kojto 90:cb3d968589d8 700 * @brief All RCM module registers.
Kojto 90:cb3d968589d8 701 */
Kojto 90:cb3d968589d8 702 #pragma pack(1)
Kojto 90:cb3d968589d8 703 typedef struct _hw_rcm
Kojto 90:cb3d968589d8 704 {
Kojto 90:cb3d968589d8 705 __I hw_rcm_srs0_t SRS0; /*!< [0x0] System Reset Status Register 0 */
Kojto 90:cb3d968589d8 706 __I hw_rcm_srs1_t SRS1; /*!< [0x1] System Reset Status Register 1 */
Kojto 90:cb3d968589d8 707 uint8_t _reserved0[2];
Kojto 90:cb3d968589d8 708 __IO hw_rcm_rpfc_t RPFC; /*!< [0x4] Reset Pin Filter Control register */
Kojto 90:cb3d968589d8 709 __IO hw_rcm_rpfw_t RPFW; /*!< [0x5] Reset Pin Filter Width register */
Kojto 90:cb3d968589d8 710 uint8_t _reserved1[1];
Kojto 90:cb3d968589d8 711 __I hw_rcm_mr_t MR; /*!< [0x7] Mode Register */
Kojto 90:cb3d968589d8 712 } hw_rcm_t;
Kojto 90:cb3d968589d8 713 #pragma pack()
Kojto 90:cb3d968589d8 714
Kojto 90:cb3d968589d8 715 /*! @brief Macro to access all RCM registers. */
Kojto 90:cb3d968589d8 716 /*! @param x RCM module instance base address. */
Kojto 90:cb3d968589d8 717 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto 90:cb3d968589d8 718 * use the '&' operator, like <code>&HW_RCM(RCM_BASE)</code>. */
Kojto 90:cb3d968589d8 719 #define HW_RCM(x) (*(hw_rcm_t *)(x))
Kojto 90:cb3d968589d8 720
Kojto 90:cb3d968589d8 721 #endif /* __HW_RCM_REGISTERS_H__ */
Kojto 90:cb3d968589d8 722 /* EOF */