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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_pmc.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:
Kojto
Date:
Wed Aug 05 13:16:35 2015 +0100
Revision:
104:b9ad9a133dc7
Parent:
90:cb3d968589d8 
Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /*
Kojto 90:cb3d968589d8 2 ** ###################################################################
Kojto 90:cb3d968589d8 3 ** Compilers: Keil ARM C/C++ Compiler
Kojto 90:cb3d968589d8 4 ** Freescale C/C++ for Embedded ARM
Kojto 90:cb3d968589d8 5 ** GNU C Compiler
Kojto 90:cb3d968589d8 6 ** IAR ANSI C/C++ Compiler for ARM
Kojto 90:cb3d968589d8 7 **
Kojto 90:cb3d968589d8 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto 90:cb3d968589d8 9 ** Version: rev. 2.5, 2014-02-10
Kojto 90:cb3d968589d8 10 ** Build: b140604
Kojto 90:cb3d968589d8 11 **
Kojto 90:cb3d968589d8 12 ** Abstract:
Kojto 90:cb3d968589d8 13 ** Extension to the CMSIS register access layer header.
Kojto 90:cb3d968589d8 14 **
Kojto 90:cb3d968589d8 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto 90:cb3d968589d8 16 ** All rights reserved.
Kojto 90:cb3d968589d8 17 **
Kojto 90:cb3d968589d8 18 ** Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 19 ** are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 20 **
Kojto 90:cb3d968589d8 21 ** o Redistributions of source code must retain the above copyright notice, this list
Kojto 90:cb3d968589d8 22 ** of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 23 **
Kojto 90:cb3d968589d8 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto 90:cb3d968589d8 25 ** list of conditions and the following disclaimer in the documentation and/or
Kojto 90:cb3d968589d8 26 ** other materials provided with the distribution.
Kojto 90:cb3d968589d8 27 **
Kojto 90:cb3d968589d8 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto 90:cb3d968589d8 29 ** contributors may be used to endorse or promote products derived from this
Kojto 90:cb3d968589d8 30 ** software without specific prior written permission.
Kojto 90:cb3d968589d8 31 **
Kojto 90:cb3d968589d8 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 90:cb3d968589d8 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 90:cb3d968589d8 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 90:cb3d968589d8 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 90:cb3d968589d8 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 90:cb3d968589d8 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 90:cb3d968589d8 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 90:cb3d968589d8 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 90:cb3d968589d8 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 42 **
Kojto 90:cb3d968589d8 43 ** http: www.freescale.com
Kojto 90:cb3d968589d8 44 ** mail: support@freescale.com
Kojto 90:cb3d968589d8 45 **
Kojto 90:cb3d968589d8 46 ** Revisions:
Kojto 90:cb3d968589d8 47 ** - rev. 1.0 (2013-08-12)
Kojto 90:cb3d968589d8 48 ** Initial version.
Kojto 90:cb3d968589d8 49 ** - rev. 2.0 (2013-10-29)
Kojto 90:cb3d968589d8 50 ** Register accessor macros added to the memory map.
Kojto 90:cb3d968589d8 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto 90:cb3d968589d8 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto 90:cb3d968589d8 53 ** System initialization updated.
Kojto 90:cb3d968589d8 54 ** MCG - registers updated.
Kojto 90:cb3d968589d8 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto 90:cb3d968589d8 56 ** - rev. 2.1 (2013-10-30)
Kojto 90:cb3d968589d8 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto 90:cb3d968589d8 58 ** - rev. 2.2 (2013-12-09)
Kojto 90:cb3d968589d8 59 ** DMA - EARS register removed.
Kojto 90:cb3d968589d8 60 ** AIPS0, AIPS1 - MPRA register updated.
Kojto 90:cb3d968589d8 61 ** - rev. 2.3 (2014-01-24)
Kojto 90:cb3d968589d8 62 ** Update according to reference manual rev. 2
Kojto 90:cb3d968589d8 63 ** ENET, MCG, MCM, SIM, USB - registers updated
Kojto 90:cb3d968589d8 64 ** - rev. 2.4 (2014-02-10)
Kojto 90:cb3d968589d8 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 67 ** - rev. 2.5 (2014-02-10)
Kojto 90:cb3d968589d8 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto 90:cb3d968589d8 71 **
Kojto 90:cb3d968589d8 72 ** ###################################################################
Kojto 90:cb3d968589d8 73 */
Kojto 90:cb3d968589d8 74
Kojto 90:cb3d968589d8 75 /*
Kojto 90:cb3d968589d8 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto 90:cb3d968589d8 77 *
Kojto 90:cb3d968589d8 78 * This file was generated automatically and any changes may be lost.
Kojto 90:cb3d968589d8 79 */
Kojto 90:cb3d968589d8 80 #ifndef __HW_PMC_REGISTERS_H__
Kojto 90:cb3d968589d8 81 #define __HW_PMC_REGISTERS_H__
Kojto 90:cb3d968589d8 82
Kojto 90:cb3d968589d8 83 #include "MK64F12.h"
Kojto 90:cb3d968589d8 84 #include "fsl_bitaccess.h"
Kojto 90:cb3d968589d8 85
Kojto 90:cb3d968589d8 86 /*
Kojto 90:cb3d968589d8 87 * MK64F12 PMC
Kojto 90:cb3d968589d8 88 *
Kojto 90:cb3d968589d8 89 * Power Management Controller
Kojto 90:cb3d968589d8 90 *
Kojto 90:cb3d968589d8 91 * Registers defined in this header file:
Kojto 90:cb3d968589d8 92 * - HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
Kojto 90:cb3d968589d8 93 * - HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
Kojto 90:cb3d968589d8 94 * - HW_PMC_REGSC - Regulator Status And Control register
Kojto 90:cb3d968589d8 95 *
Kojto 90:cb3d968589d8 96 * - hw_pmc_t - Struct containing all module registers.
Kojto 90:cb3d968589d8 97 */
Kojto 90:cb3d968589d8 98
Kojto 90:cb3d968589d8 99 #define HW_PMC_INSTANCE_COUNT (1U) /*!< Number of instances of the PMC module. */
Kojto 90:cb3d968589d8 100
Kojto 90:cb3d968589d8 101 /*******************************************************************************
Kojto 90:cb3d968589d8 102 * HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
Kojto 90:cb3d968589d8 103 ******************************************************************************/
Kojto 90:cb3d968589d8 104
Kojto 90:cb3d968589d8 105 /*!
Kojto 90:cb3d968589d8 106 * @brief HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW)
Kojto 90:cb3d968589d8 107 *
Kojto 90:cb3d968589d8 108 * Reset value: 0x10U
Kojto 90:cb3d968589d8 109 *
Kojto 90:cb3d968589d8 110 * This register contains status and control bits to support the low voltage
Kojto 90:cb3d968589d8 111 * detect function. This register should be written during the reset initialization
Kojto 90:cb3d968589d8 112 * program to set the desired controls even if the desired settings are the same
Kojto 90:cb3d968589d8 113 * as the reset settings. While the device is in the very low power or low
Kojto 90:cb3d968589d8 114 * leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect
Kojto 90:cb3d968589d8 115 * systems that must have LVD always on, configure the Power Mode Protection
Kojto 90:cb3d968589d8 116 * (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or
Kojto 90:cb3d968589d8 117 * low leakage modes from being enabled. See the device's data sheet for the
Kojto 90:cb3d968589d8 118 * exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The
Kojto 90:cb3d968589d8 119 * register's other bits are reset on Chip Reset Not VLLS. For more information
Kojto 90:cb3d968589d8 120 * about these reset types, refer to the Reset section details.
Kojto 90:cb3d968589d8 121 */
Kojto 90:cb3d968589d8 122 typedef union _hw_pmc_lvdsc1
Kojto 90:cb3d968589d8 123 {
Kojto 90:cb3d968589d8 124 uint8_t U;
Kojto 90:cb3d968589d8 125 struct _hw_pmc_lvdsc1_bitfields
Kojto 90:cb3d968589d8 126 {
Kojto 90:cb3d968589d8 127 uint8_t LVDV : 2; /*!< [1:0] Low-Voltage Detect Voltage Select */
Kojto 90:cb3d968589d8 128 uint8_t RESERVED0 : 2; /*!< [3:2] */
Kojto 90:cb3d968589d8 129 uint8_t LVDRE : 1; /*!< [4] Low-Voltage Detect Reset Enable */
Kojto 90:cb3d968589d8 130 uint8_t LVDIE : 1; /*!< [5] Low-Voltage Detect Interrupt Enable */
Kojto 90:cb3d968589d8 131 uint8_t LVDACK : 1; /*!< [6] Low-Voltage Detect Acknowledge */
Kojto 90:cb3d968589d8 132 uint8_t LVDF : 1; /*!< [7] Low-Voltage Detect Flag */
Kojto 90:cb3d968589d8 133 } B;
Kojto 90:cb3d968589d8 134 } hw_pmc_lvdsc1_t;
Kojto 90:cb3d968589d8 135
Kojto 90:cb3d968589d8 136 /*!
Kojto 90:cb3d968589d8 137 * @name Constants and macros for entire PMC_LVDSC1 register
Kojto 90:cb3d968589d8 138 */
Kojto 90:cb3d968589d8 139 /*@{*/
Kojto 90:cb3d968589d8 140 #define HW_PMC_LVDSC1_ADDR(x) ((x) + 0x0U)
Kojto 90:cb3d968589d8 141
Kojto 90:cb3d968589d8 142 #define HW_PMC_LVDSC1(x) (*(__IO hw_pmc_lvdsc1_t *) HW_PMC_LVDSC1_ADDR(x))
Kojto 90:cb3d968589d8 143 #define HW_PMC_LVDSC1_RD(x) (HW_PMC_LVDSC1(x).U)
Kojto 90:cb3d968589d8 144 #define HW_PMC_LVDSC1_WR(x, v) (HW_PMC_LVDSC1(x).U = (v))
Kojto 90:cb3d968589d8 145 #define HW_PMC_LVDSC1_SET(x, v) (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) | (v)))
Kojto 90:cb3d968589d8 146 #define HW_PMC_LVDSC1_CLR(x, v) (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 147 #define HW_PMC_LVDSC1_TOG(x, v) (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 148 /*@}*/
Kojto 90:cb3d968589d8 149
Kojto 90:cb3d968589d8 150 /*
Kojto 90:cb3d968589d8 151 * Constants & macros for individual PMC_LVDSC1 bitfields
Kojto 90:cb3d968589d8 152 */
Kojto 90:cb3d968589d8 153
Kojto 90:cb3d968589d8 154 /*!
Kojto 90:cb3d968589d8 155 * @name Register PMC_LVDSC1, field LVDV[1:0] (RW)
Kojto 90:cb3d968589d8 156 *
Kojto 90:cb3d968589d8 157 * Selects the LVD trip point voltage (V LVD ).
Kojto 90:cb3d968589d8 158 *
Kojto 90:cb3d968589d8 159 * Values:
Kojto 90:cb3d968589d8 160 * - 00 - Low trip point selected (V LVD = V LVDL )
Kojto 90:cb3d968589d8 161 * - 01 - High trip point selected (V LVD = V LVDH )
Kojto 90:cb3d968589d8 162 * - 10 - Reserved
Kojto 90:cb3d968589d8 163 * - 11 - Reserved
Kojto 90:cb3d968589d8 164 */
Kojto 90:cb3d968589d8 165 /*@{*/
Kojto 90:cb3d968589d8 166 #define BP_PMC_LVDSC1_LVDV (0U) /*!< Bit position for PMC_LVDSC1_LVDV. */
Kojto 90:cb3d968589d8 167 #define BM_PMC_LVDSC1_LVDV (0x03U) /*!< Bit mask for PMC_LVDSC1_LVDV. */
Kojto 90:cb3d968589d8 168 #define BS_PMC_LVDSC1_LVDV (2U) /*!< Bit field size in bits for PMC_LVDSC1_LVDV. */
Kojto 90:cb3d968589d8 169
Kojto 90:cb3d968589d8 170 /*! @brief Read current value of the PMC_LVDSC1_LVDV field. */
Kojto 90:cb3d968589d8 171 #define BR_PMC_LVDSC1_LVDV(x) (HW_PMC_LVDSC1(x).B.LVDV)
Kojto 90:cb3d968589d8 172
Kojto 90:cb3d968589d8 173 /*! @brief Format value for bitfield PMC_LVDSC1_LVDV. */
Kojto 90:cb3d968589d8 174 #define BF_PMC_LVDSC1_LVDV(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDV) & BM_PMC_LVDSC1_LVDV)
Kojto 90:cb3d968589d8 175
Kojto 90:cb3d968589d8 176 /*! @brief Set the LVDV field to a new value. */
Kojto 90:cb3d968589d8 177 #define BW_PMC_LVDSC1_LVDV(x, v) (HW_PMC_LVDSC1_WR(x, (HW_PMC_LVDSC1_RD(x) & ~BM_PMC_LVDSC1_LVDV) | BF_PMC_LVDSC1_LVDV(v)))
Kojto 90:cb3d968589d8 178 /*@}*/
Kojto 90:cb3d968589d8 179
Kojto 90:cb3d968589d8 180 /*!
Kojto 90:cb3d968589d8 181 * @name Register PMC_LVDSC1, field LVDRE[4] (RW)
Kojto 90:cb3d968589d8 182 *
Kojto 90:cb3d968589d8 183 * This write-once bit enables LVDF events to generate a hardware reset.
Kojto 90:cb3d968589d8 184 * Additional writes are ignored.
Kojto 90:cb3d968589d8 185 *
Kojto 90:cb3d968589d8 186 * Values:
Kojto 90:cb3d968589d8 187 * - 0 - LVDF does not generate hardware resets
Kojto 90:cb3d968589d8 188 * - 1 - Force an MCU reset when LVDF = 1
Kojto 90:cb3d968589d8 189 */
Kojto 90:cb3d968589d8 190 /*@{*/
Kojto 90:cb3d968589d8 191 #define BP_PMC_LVDSC1_LVDRE (4U) /*!< Bit position for PMC_LVDSC1_LVDRE. */
Kojto 90:cb3d968589d8 192 #define BM_PMC_LVDSC1_LVDRE (0x10U) /*!< Bit mask for PMC_LVDSC1_LVDRE. */
Kojto 90:cb3d968589d8 193 #define BS_PMC_LVDSC1_LVDRE (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDRE. */
Kojto 90:cb3d968589d8 194
Kojto 90:cb3d968589d8 195 /*! @brief Read current value of the PMC_LVDSC1_LVDRE field. */
Kojto 90:cb3d968589d8 196 #define BR_PMC_LVDSC1_LVDRE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDRE))
Kojto 90:cb3d968589d8 197
Kojto 90:cb3d968589d8 198 /*! @brief Format value for bitfield PMC_LVDSC1_LVDRE. */
Kojto 90:cb3d968589d8 199 #define BF_PMC_LVDSC1_LVDRE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDRE) & BM_PMC_LVDSC1_LVDRE)
Kojto 90:cb3d968589d8 200
Kojto 90:cb3d968589d8 201 /*! @brief Set the LVDRE field to a new value. */
Kojto 90:cb3d968589d8 202 #define BW_PMC_LVDSC1_LVDRE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDRE) = (v))
Kojto 90:cb3d968589d8 203 /*@}*/
Kojto 90:cb3d968589d8 204
Kojto 90:cb3d968589d8 205 /*!
Kojto 90:cb3d968589d8 206 * @name Register PMC_LVDSC1, field LVDIE[5] (RW)
Kojto 90:cb3d968589d8 207 *
Kojto 90:cb3d968589d8 208 * Enables hardware interrupt requests for LVDF.
Kojto 90:cb3d968589d8 209 *
Kojto 90:cb3d968589d8 210 * Values:
Kojto 90:cb3d968589d8 211 * - 0 - Hardware interrupt disabled (use polling)
Kojto 90:cb3d968589d8 212 * - 1 - Request a hardware interrupt when LVDF = 1
Kojto 90:cb3d968589d8 213 */
Kojto 90:cb3d968589d8 214 /*@{*/
Kojto 90:cb3d968589d8 215 #define BP_PMC_LVDSC1_LVDIE (5U) /*!< Bit position for PMC_LVDSC1_LVDIE. */
Kojto 90:cb3d968589d8 216 #define BM_PMC_LVDSC1_LVDIE (0x20U) /*!< Bit mask for PMC_LVDSC1_LVDIE. */
Kojto 90:cb3d968589d8 217 #define BS_PMC_LVDSC1_LVDIE (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDIE. */
Kojto 90:cb3d968589d8 218
Kojto 90:cb3d968589d8 219 /*! @brief Read current value of the PMC_LVDSC1_LVDIE field. */
Kojto 90:cb3d968589d8 220 #define BR_PMC_LVDSC1_LVDIE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDIE))
Kojto 90:cb3d968589d8 221
Kojto 90:cb3d968589d8 222 /*! @brief Format value for bitfield PMC_LVDSC1_LVDIE. */
Kojto 90:cb3d968589d8 223 #define BF_PMC_LVDSC1_LVDIE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDIE) & BM_PMC_LVDSC1_LVDIE)
Kojto 90:cb3d968589d8 224
Kojto 90:cb3d968589d8 225 /*! @brief Set the LVDIE field to a new value. */
Kojto 90:cb3d968589d8 226 #define BW_PMC_LVDSC1_LVDIE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDIE) = (v))
Kojto 90:cb3d968589d8 227 /*@}*/
Kojto 90:cb3d968589d8 228
Kojto 90:cb3d968589d8 229 /*!
Kojto 90:cb3d968589d8 230 * @name Register PMC_LVDSC1, field LVDACK[6] (WORZ)
Kojto 90:cb3d968589d8 231 *
Kojto 90:cb3d968589d8 232 * This write-only field is used to acknowledge low voltage detection errors.
Kojto 90:cb3d968589d8 233 * Write 1 to clear LVDF. Reads always return 0.
Kojto 90:cb3d968589d8 234 */
Kojto 90:cb3d968589d8 235 /*@{*/
Kojto 90:cb3d968589d8 236 #define BP_PMC_LVDSC1_LVDACK (6U) /*!< Bit position for PMC_LVDSC1_LVDACK. */
Kojto 90:cb3d968589d8 237 #define BM_PMC_LVDSC1_LVDACK (0x40U) /*!< Bit mask for PMC_LVDSC1_LVDACK. */
Kojto 90:cb3d968589d8 238 #define BS_PMC_LVDSC1_LVDACK (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDACK. */
Kojto 90:cb3d968589d8 239
Kojto 90:cb3d968589d8 240 /*! @brief Format value for bitfield PMC_LVDSC1_LVDACK. */
Kojto 90:cb3d968589d8 241 #define BF_PMC_LVDSC1_LVDACK(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDACK) & BM_PMC_LVDSC1_LVDACK)
Kojto 90:cb3d968589d8 242
Kojto 90:cb3d968589d8 243 /*! @brief Set the LVDACK field to a new value. */
Kojto 90:cb3d968589d8 244 #define BW_PMC_LVDSC1_LVDACK(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDACK) = (v))
Kojto 90:cb3d968589d8 245 /*@}*/
Kojto 90:cb3d968589d8 246
Kojto 90:cb3d968589d8 247 /*!
Kojto 90:cb3d968589d8 248 * @name Register PMC_LVDSC1, field LVDF[7] (RO)
Kojto 90:cb3d968589d8 249 *
Kojto 90:cb3d968589d8 250 * This read-only status field indicates a low-voltage detect event.
Kojto 90:cb3d968589d8 251 *
Kojto 90:cb3d968589d8 252 * Values:
Kojto 90:cb3d968589d8 253 * - 0 - Low-voltage event not detected
Kojto 90:cb3d968589d8 254 * - 1 - Low-voltage event detected
Kojto 90:cb3d968589d8 255 */
Kojto 90:cb3d968589d8 256 /*@{*/
Kojto 90:cb3d968589d8 257 #define BP_PMC_LVDSC1_LVDF (7U) /*!< Bit position for PMC_LVDSC1_LVDF. */
Kojto 90:cb3d968589d8 258 #define BM_PMC_LVDSC1_LVDF (0x80U) /*!< Bit mask for PMC_LVDSC1_LVDF. */
Kojto 90:cb3d968589d8 259 #define BS_PMC_LVDSC1_LVDF (1U) /*!< Bit field size in bits for PMC_LVDSC1_LVDF. */
Kojto 90:cb3d968589d8 260
Kojto 90:cb3d968589d8 261 /*! @brief Read current value of the PMC_LVDSC1_LVDF field. */
Kojto 90:cb3d968589d8 262 #define BR_PMC_LVDSC1_LVDF(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDF))
Kojto 90:cb3d968589d8 263 /*@}*/
Kojto 90:cb3d968589d8 264
Kojto 90:cb3d968589d8 265 /*******************************************************************************
Kojto 90:cb3d968589d8 266 * HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
Kojto 90:cb3d968589d8 267 ******************************************************************************/
Kojto 90:cb3d968589d8 268
Kojto 90:cb3d968589d8 269 /*!
Kojto 90:cb3d968589d8 270 * @brief HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW)
Kojto 90:cb3d968589d8 271 *
Kojto 90:cb3d968589d8 272 * Reset value: 0x00U
Kojto 90:cb3d968589d8 273 *
Kojto 90:cb3d968589d8 274 * This register contains status and control bits to support the low voltage
Kojto 90:cb3d968589d8 275 * warning function. While the device is in the very low power or low leakage modes,
Kojto 90:cb3d968589d8 276 * the LVD system is disabled regardless of LVDSC2 settings. See the device's
Kojto 90:cb3d968589d8 277 * data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV
Kojto 90:cb3d968589d8 278 * and LVDV. LVWV is reset solely on a POR Only event. The other fields of the
Kojto 90:cb3d968589d8 279 * register are reset on Chip Reset Not VLLS. For more information about these
Kojto 90:cb3d968589d8 280 * reset types, refer to the Reset section details.
Kojto 90:cb3d968589d8 281 */
Kojto 90:cb3d968589d8 282 typedef union _hw_pmc_lvdsc2
Kojto 90:cb3d968589d8 283 {
Kojto 90:cb3d968589d8 284 uint8_t U;
Kojto 90:cb3d968589d8 285 struct _hw_pmc_lvdsc2_bitfields
Kojto 90:cb3d968589d8 286 {
Kojto 90:cb3d968589d8 287 uint8_t LVWV : 2; /*!< [1:0] Low-Voltage Warning Voltage Select */
Kojto 90:cb3d968589d8 288 uint8_t RESERVED0 : 3; /*!< [4:2] */
Kojto 90:cb3d968589d8 289 uint8_t LVWIE : 1; /*!< [5] Low-Voltage Warning Interrupt Enable */
Kojto 90:cb3d968589d8 290 uint8_t LVWACK : 1; /*!< [6] Low-Voltage Warning Acknowledge */
Kojto 90:cb3d968589d8 291 uint8_t LVWF : 1; /*!< [7] Low-Voltage Warning Flag */
Kojto 90:cb3d968589d8 292 } B;
Kojto 90:cb3d968589d8 293 } hw_pmc_lvdsc2_t;
Kojto 90:cb3d968589d8 294
Kojto 90:cb3d968589d8 295 /*!
Kojto 90:cb3d968589d8 296 * @name Constants and macros for entire PMC_LVDSC2 register
Kojto 90:cb3d968589d8 297 */
Kojto 90:cb3d968589d8 298 /*@{*/
Kojto 90:cb3d968589d8 299 #define HW_PMC_LVDSC2_ADDR(x) ((x) + 0x1U)
Kojto 90:cb3d968589d8 300
Kojto 90:cb3d968589d8 301 #define HW_PMC_LVDSC2(x) (*(__IO hw_pmc_lvdsc2_t *) HW_PMC_LVDSC2_ADDR(x))
Kojto 90:cb3d968589d8 302 #define HW_PMC_LVDSC2_RD(x) (HW_PMC_LVDSC2(x).U)
Kojto 90:cb3d968589d8 303 #define HW_PMC_LVDSC2_WR(x, v) (HW_PMC_LVDSC2(x).U = (v))
Kojto 90:cb3d968589d8 304 #define HW_PMC_LVDSC2_SET(x, v) (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) | (v)))
Kojto 90:cb3d968589d8 305 #define HW_PMC_LVDSC2_CLR(x, v) (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 306 #define HW_PMC_LVDSC2_TOG(x, v) (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 307 /*@}*/
Kojto 90:cb3d968589d8 308
Kojto 90:cb3d968589d8 309 /*
Kojto 90:cb3d968589d8 310 * Constants & macros for individual PMC_LVDSC2 bitfields
Kojto 90:cb3d968589d8 311 */
Kojto 90:cb3d968589d8 312
Kojto 90:cb3d968589d8 313 /*!
Kojto 90:cb3d968589d8 314 * @name Register PMC_LVDSC2, field LVWV[1:0] (RW)
Kojto 90:cb3d968589d8 315 *
Kojto 90:cb3d968589d8 316 * Selects the LVW trip point voltage (VLVW). The actual voltage for the warning
Kojto 90:cb3d968589d8 317 * depends on LVDSC1[LVDV].
Kojto 90:cb3d968589d8 318 *
Kojto 90:cb3d968589d8 319 * Values:
Kojto 90:cb3d968589d8 320 * - 00 - Low trip point selected (VLVW = VLVW1)
Kojto 90:cb3d968589d8 321 * - 01 - Mid 1 trip point selected (VLVW = VLVW2)
Kojto 90:cb3d968589d8 322 * - 10 - Mid 2 trip point selected (VLVW = VLVW3)
Kojto 90:cb3d968589d8 323 * - 11 - High trip point selected (VLVW = VLVW4)
Kojto 90:cb3d968589d8 324 */
Kojto 90:cb3d968589d8 325 /*@{*/
Kojto 90:cb3d968589d8 326 #define BP_PMC_LVDSC2_LVWV (0U) /*!< Bit position for PMC_LVDSC2_LVWV. */
Kojto 90:cb3d968589d8 327 #define BM_PMC_LVDSC2_LVWV (0x03U) /*!< Bit mask for PMC_LVDSC2_LVWV. */
Kojto 90:cb3d968589d8 328 #define BS_PMC_LVDSC2_LVWV (2U) /*!< Bit field size in bits for PMC_LVDSC2_LVWV. */
Kojto 90:cb3d968589d8 329
Kojto 90:cb3d968589d8 330 /*! @brief Read current value of the PMC_LVDSC2_LVWV field. */
Kojto 90:cb3d968589d8 331 #define BR_PMC_LVDSC2_LVWV(x) (HW_PMC_LVDSC2(x).B.LVWV)
Kojto 90:cb3d968589d8 332
Kojto 90:cb3d968589d8 333 /*! @brief Format value for bitfield PMC_LVDSC2_LVWV. */
Kojto 90:cb3d968589d8 334 #define BF_PMC_LVDSC2_LVWV(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWV) & BM_PMC_LVDSC2_LVWV)
Kojto 90:cb3d968589d8 335
Kojto 90:cb3d968589d8 336 /*! @brief Set the LVWV field to a new value. */
Kojto 90:cb3d968589d8 337 #define BW_PMC_LVDSC2_LVWV(x, v) (HW_PMC_LVDSC2_WR(x, (HW_PMC_LVDSC2_RD(x) & ~BM_PMC_LVDSC2_LVWV) | BF_PMC_LVDSC2_LVWV(v)))
Kojto 90:cb3d968589d8 338 /*@}*/
Kojto 90:cb3d968589d8 339
Kojto 90:cb3d968589d8 340 /*!
Kojto 90:cb3d968589d8 341 * @name Register PMC_LVDSC2, field LVWIE[5] (RW)
Kojto 90:cb3d968589d8 342 *
Kojto 90:cb3d968589d8 343 * Enables hardware interrupt requests for LVWF.
Kojto 90:cb3d968589d8 344 *
Kojto 90:cb3d968589d8 345 * Values:
Kojto 90:cb3d968589d8 346 * - 0 - Hardware interrupt disabled (use polling)
Kojto 90:cb3d968589d8 347 * - 1 - Request a hardware interrupt when LVWF = 1
Kojto 90:cb3d968589d8 348 */
Kojto 90:cb3d968589d8 349 /*@{*/
Kojto 90:cb3d968589d8 350 #define BP_PMC_LVDSC2_LVWIE (5U) /*!< Bit position for PMC_LVDSC2_LVWIE. */
Kojto 90:cb3d968589d8 351 #define BM_PMC_LVDSC2_LVWIE (0x20U) /*!< Bit mask for PMC_LVDSC2_LVWIE. */
Kojto 90:cb3d968589d8 352 #define BS_PMC_LVDSC2_LVWIE (1U) /*!< Bit field size in bits for PMC_LVDSC2_LVWIE. */
Kojto 90:cb3d968589d8 353
Kojto 90:cb3d968589d8 354 /*! @brief Read current value of the PMC_LVDSC2_LVWIE field. */
Kojto 90:cb3d968589d8 355 #define BR_PMC_LVDSC2_LVWIE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWIE))
Kojto 90:cb3d968589d8 356
Kojto 90:cb3d968589d8 357 /*! @brief Format value for bitfield PMC_LVDSC2_LVWIE. */
Kojto 90:cb3d968589d8 358 #define BF_PMC_LVDSC2_LVWIE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWIE) & BM_PMC_LVDSC2_LVWIE)
Kojto 90:cb3d968589d8 359
Kojto 90:cb3d968589d8 360 /*! @brief Set the LVWIE field to a new value. */
Kojto 90:cb3d968589d8 361 #define BW_PMC_LVDSC2_LVWIE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWIE) = (v))
Kojto 90:cb3d968589d8 362 /*@}*/
Kojto 90:cb3d968589d8 363
Kojto 90:cb3d968589d8 364 /*!
Kojto 90:cb3d968589d8 365 * @name Register PMC_LVDSC2, field LVWACK[6] (WORZ)
Kojto 90:cb3d968589d8 366 *
Kojto 90:cb3d968589d8 367 * This write-only field is used to acknowledge low voltage warning errors.
Kojto 90:cb3d968589d8 368 * Write 1 to clear LVWF. Reads always return 0.
Kojto 90:cb3d968589d8 369 */
Kojto 90:cb3d968589d8 370 /*@{*/
Kojto 90:cb3d968589d8 371 #define BP_PMC_LVDSC2_LVWACK (6U) /*!< Bit position for PMC_LVDSC2_LVWACK. */
Kojto 90:cb3d968589d8 372 #define BM_PMC_LVDSC2_LVWACK (0x40U) /*!< Bit mask for PMC_LVDSC2_LVWACK. */
Kojto 90:cb3d968589d8 373 #define BS_PMC_LVDSC2_LVWACK (1U) /*!< Bit field size in bits for PMC_LVDSC2_LVWACK. */
Kojto 90:cb3d968589d8 374
Kojto 90:cb3d968589d8 375 /*! @brief Format value for bitfield PMC_LVDSC2_LVWACK. */
Kojto 90:cb3d968589d8 376 #define BF_PMC_LVDSC2_LVWACK(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWACK) & BM_PMC_LVDSC2_LVWACK)
Kojto 90:cb3d968589d8 377
Kojto 90:cb3d968589d8 378 /*! @brief Set the LVWACK field to a new value. */
Kojto 90:cb3d968589d8 379 #define BW_PMC_LVDSC2_LVWACK(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWACK) = (v))
Kojto 90:cb3d968589d8 380 /*@}*/
Kojto 90:cb3d968589d8 381
Kojto 90:cb3d968589d8 382 /*!
Kojto 90:cb3d968589d8 383 * @name Register PMC_LVDSC2, field LVWF[7] (RO)
Kojto 90:cb3d968589d8 384 *
Kojto 90:cb3d968589d8 385 * This read-only status field indicates a low-voltage warning event. LVWF is
Kojto 90:cb3d968589d8 386 * set when VSupply transitions below the trip point, or after reset and VSupply is
Kojto 90:cb3d968589d8 387 * already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW
Kojto 90:cb3d968589d8 388 * interrupt function, before enabling LVWIE, LVWF must be cleared by writing
Kojto 90:cb3d968589d8 389 * LVWACK first.
Kojto 90:cb3d968589d8 390 *
Kojto 90:cb3d968589d8 391 * Values:
Kojto 90:cb3d968589d8 392 * - 0 - Low-voltage warning event not detected
Kojto 90:cb3d968589d8 393 * - 1 - Low-voltage warning event detected
Kojto 90:cb3d968589d8 394 */
Kojto 90:cb3d968589d8 395 /*@{*/
Kojto 90:cb3d968589d8 396 #define BP_PMC_LVDSC2_LVWF (7U) /*!< Bit position for PMC_LVDSC2_LVWF. */
Kojto 90:cb3d968589d8 397 #define BM_PMC_LVDSC2_LVWF (0x80U) /*!< Bit mask for PMC_LVDSC2_LVWF. */
Kojto 90:cb3d968589d8 398 #define BS_PMC_LVDSC2_LVWF (1U) /*!< Bit field size in bits for PMC_LVDSC2_LVWF. */
Kojto 90:cb3d968589d8 399
Kojto 90:cb3d968589d8 400 /*! @brief Read current value of the PMC_LVDSC2_LVWF field. */
Kojto 90:cb3d968589d8 401 #define BR_PMC_LVDSC2_LVWF(x) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWF))
Kojto 90:cb3d968589d8 402 /*@}*/
Kojto 90:cb3d968589d8 403
Kojto 90:cb3d968589d8 404 /*******************************************************************************
Kojto 90:cb3d968589d8 405 * HW_PMC_REGSC - Regulator Status And Control register
Kojto 90:cb3d968589d8 406 ******************************************************************************/
Kojto 90:cb3d968589d8 407
Kojto 90:cb3d968589d8 408 /*!
Kojto 90:cb3d968589d8 409 * @brief HW_PMC_REGSC - Regulator Status And Control register (RW)
Kojto 90:cb3d968589d8 410 *
Kojto 90:cb3d968589d8 411 * Reset value: 0x04U
Kojto 90:cb3d968589d8 412 *
Kojto 90:cb3d968589d8 413 * The PMC contains an internal voltage regulator. The voltage regulator design
Kojto 90:cb3d968589d8 414 * uses a bandgap reference that is also available through a buffer as input to
Kojto 90:cb3d968589d8 415 * certain internal peripherals, such as the CMP and ADC. The internal regulator
Kojto 90:cb3d968589d8 416 * provides a status bit (REGONS) indicating the regulator is in run regulation.
Kojto 90:cb3d968589d8 417 * This register is reset on Chip Reset Not VLLS and by reset types that trigger
Kojto 90:cb3d968589d8 418 * Chip Reset not VLLS. See the Reset section details for more information.
Kojto 90:cb3d968589d8 419 */
Kojto 90:cb3d968589d8 420 typedef union _hw_pmc_regsc
Kojto 90:cb3d968589d8 421 {
Kojto 90:cb3d968589d8 422 uint8_t U;
Kojto 90:cb3d968589d8 423 struct _hw_pmc_regsc_bitfields
Kojto 90:cb3d968589d8 424 {
Kojto 90:cb3d968589d8 425 uint8_t BGBE : 1; /*!< [0] Bandgap Buffer Enable */
Kojto 90:cb3d968589d8 426 uint8_t RESERVED0 : 1; /*!< [1] */
Kojto 90:cb3d968589d8 427 uint8_t REGONS : 1; /*!< [2] Regulator In Run Regulation Status */
Kojto 90:cb3d968589d8 428 uint8_t ACKISO : 1; /*!< [3] Acknowledge Isolation */
Kojto 90:cb3d968589d8 429 uint8_t BGEN : 1; /*!< [4] Bandgap Enable In VLPx Operation */
Kojto 90:cb3d968589d8 430 uint8_t RESERVED1 : 3; /*!< [7:5] */
Kojto 90:cb3d968589d8 431 } B;
Kojto 90:cb3d968589d8 432 } hw_pmc_regsc_t;
Kojto 90:cb3d968589d8 433
Kojto 90:cb3d968589d8 434 /*!
Kojto 90:cb3d968589d8 435 * @name Constants and macros for entire PMC_REGSC register
Kojto 90:cb3d968589d8 436 */
Kojto 90:cb3d968589d8 437 /*@{*/
Kojto 90:cb3d968589d8 438 #define HW_PMC_REGSC_ADDR(x) ((x) + 0x2U)
Kojto 90:cb3d968589d8 439
Kojto 90:cb3d968589d8 440 #define HW_PMC_REGSC(x) (*(__IO hw_pmc_regsc_t *) HW_PMC_REGSC_ADDR(x))
Kojto 90:cb3d968589d8 441 #define HW_PMC_REGSC_RD(x) (HW_PMC_REGSC(x).U)
Kojto 90:cb3d968589d8 442 #define HW_PMC_REGSC_WR(x, v) (HW_PMC_REGSC(x).U = (v))
Kojto 90:cb3d968589d8 443 #define HW_PMC_REGSC_SET(x, v) (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) | (v)))
Kojto 90:cb3d968589d8 444 #define HW_PMC_REGSC_CLR(x, v) (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 445 #define HW_PMC_REGSC_TOG(x, v) (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 446 /*@}*/
Kojto 90:cb3d968589d8 447
Kojto 90:cb3d968589d8 448 /*
Kojto 90:cb3d968589d8 449 * Constants & macros for individual PMC_REGSC bitfields
Kojto 90:cb3d968589d8 450 */
Kojto 90:cb3d968589d8 451
Kojto 90:cb3d968589d8 452 /*!
Kojto 90:cb3d968589d8 453 * @name Register PMC_REGSC, field BGBE[0] (RW)
Kojto 90:cb3d968589d8 454 *
Kojto 90:cb3d968589d8 455 * Enables the bandgap buffer.
Kojto 90:cb3d968589d8 456 *
Kojto 90:cb3d968589d8 457 * Values:
Kojto 90:cb3d968589d8 458 * - 0 - Bandgap buffer not enabled
Kojto 90:cb3d968589d8 459 * - 1 - Bandgap buffer enabled
Kojto 90:cb3d968589d8 460 */
Kojto 90:cb3d968589d8 461 /*@{*/
Kojto 90:cb3d968589d8 462 #define BP_PMC_REGSC_BGBE (0U) /*!< Bit position for PMC_REGSC_BGBE. */
Kojto 90:cb3d968589d8 463 #define BM_PMC_REGSC_BGBE (0x01U) /*!< Bit mask for PMC_REGSC_BGBE. */
Kojto 90:cb3d968589d8 464 #define BS_PMC_REGSC_BGBE (1U) /*!< Bit field size in bits for PMC_REGSC_BGBE. */
Kojto 90:cb3d968589d8 465
Kojto 90:cb3d968589d8 466 /*! @brief Read current value of the PMC_REGSC_BGBE field. */
Kojto 90:cb3d968589d8 467 #define BR_PMC_REGSC_BGBE(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGBE))
Kojto 90:cb3d968589d8 468
Kojto 90:cb3d968589d8 469 /*! @brief Format value for bitfield PMC_REGSC_BGBE. */
Kojto 90:cb3d968589d8 470 #define BF_PMC_REGSC_BGBE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_BGBE) & BM_PMC_REGSC_BGBE)
Kojto 90:cb3d968589d8 471
Kojto 90:cb3d968589d8 472 /*! @brief Set the BGBE field to a new value. */
Kojto 90:cb3d968589d8 473 #define BW_PMC_REGSC_BGBE(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGBE) = (v))
Kojto 90:cb3d968589d8 474 /*@}*/
Kojto 90:cb3d968589d8 475
Kojto 90:cb3d968589d8 476 /*!
Kojto 90:cb3d968589d8 477 * @name Register PMC_REGSC, field REGONS[2] (RO)
Kojto 90:cb3d968589d8 478 *
Kojto 90:cb3d968589d8 479 * This read-only field provides the current status of the internal voltage
Kojto 90:cb3d968589d8 480 * regulator.
Kojto 90:cb3d968589d8 481 *
Kojto 90:cb3d968589d8 482 * Values:
Kojto 90:cb3d968589d8 483 * - 0 - Regulator is in stop regulation or in transition to/from it
Kojto 90:cb3d968589d8 484 * - 1 - Regulator is in run regulation
Kojto 90:cb3d968589d8 485 */
Kojto 90:cb3d968589d8 486 /*@{*/
Kojto 90:cb3d968589d8 487 #define BP_PMC_REGSC_REGONS (2U) /*!< Bit position for PMC_REGSC_REGONS. */
Kojto 90:cb3d968589d8 488 #define BM_PMC_REGSC_REGONS (0x04U) /*!< Bit mask for PMC_REGSC_REGONS. */
Kojto 90:cb3d968589d8 489 #define BS_PMC_REGSC_REGONS (1U) /*!< Bit field size in bits for PMC_REGSC_REGONS. */
Kojto 90:cb3d968589d8 490
Kojto 90:cb3d968589d8 491 /*! @brief Read current value of the PMC_REGSC_REGONS field. */
Kojto 90:cb3d968589d8 492 #define BR_PMC_REGSC_REGONS(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_REGONS))
Kojto 90:cb3d968589d8 493 /*@}*/
Kojto 90:cb3d968589d8 494
Kojto 90:cb3d968589d8 495 /*!
Kojto 90:cb3d968589d8 496 * @name Register PMC_REGSC, field ACKISO[3] (W1C)
Kojto 90:cb3d968589d8 497 *
Kojto 90:cb3d968589d8 498 * Reading this field indicates whether certain peripherals and the I/O pads are
Kojto 90:cb3d968589d8 499 * in a latched state as a result of having been in a VLLS mode. Writing 1 to
Kojto 90:cb3d968589d8 500 * this field when it is set releases the I/O pads and certain peripherals to their
Kojto 90:cb3d968589d8 501 * normal run mode state. After recovering from a VLLS mode, user should restore
Kojto 90:cb3d968589d8 502 * chip configuration before clearing ACKISO. In particular, pin configuration
Kojto 90:cb3d968589d8 503 * for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from
Kojto 90:cb3d968589d8 504 * being falsely set when ACKISO is cleared.
Kojto 90:cb3d968589d8 505 *
Kojto 90:cb3d968589d8 506 * Values:
Kojto 90:cb3d968589d8 507 * - 0 - Peripherals and I/O pads are in normal run state.
Kojto 90:cb3d968589d8 508 * - 1 - Certain peripherals and I/O pads are in an isolated and latched state.
Kojto 90:cb3d968589d8 509 */
Kojto 90:cb3d968589d8 510 /*@{*/
Kojto 90:cb3d968589d8 511 #define BP_PMC_REGSC_ACKISO (3U) /*!< Bit position for PMC_REGSC_ACKISO. */
Kojto 90:cb3d968589d8 512 #define BM_PMC_REGSC_ACKISO (0x08U) /*!< Bit mask for PMC_REGSC_ACKISO. */
Kojto 90:cb3d968589d8 513 #define BS_PMC_REGSC_ACKISO (1U) /*!< Bit field size in bits for PMC_REGSC_ACKISO. */
Kojto 90:cb3d968589d8 514
Kojto 90:cb3d968589d8 515 /*! @brief Read current value of the PMC_REGSC_ACKISO field. */
Kojto 90:cb3d968589d8 516 #define BR_PMC_REGSC_ACKISO(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_ACKISO))
Kojto 90:cb3d968589d8 517
Kojto 90:cb3d968589d8 518 /*! @brief Format value for bitfield PMC_REGSC_ACKISO. */
Kojto 90:cb3d968589d8 519 #define BF_PMC_REGSC_ACKISO(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_ACKISO) & BM_PMC_REGSC_ACKISO)
Kojto 90:cb3d968589d8 520
Kojto 90:cb3d968589d8 521 /*! @brief Set the ACKISO field to a new value. */
Kojto 90:cb3d968589d8 522 #define BW_PMC_REGSC_ACKISO(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_ACKISO) = (v))
Kojto 90:cb3d968589d8 523 /*@}*/
Kojto 90:cb3d968589d8 524
Kojto 90:cb3d968589d8 525 /*!
Kojto 90:cb3d968589d8 526 * @name Register PMC_REGSC, field BGEN[4] (RW)
Kojto 90:cb3d968589d8 527 *
Kojto 90:cb3d968589d8 528 * BGEN controls whether the bandgap is enabled in lower power modes of
Kojto 90:cb3d968589d8 529 * operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage
Kojto 90:cb3d968589d8 530 * reference in low power modes of operation, set BGEN to continue to enable the
Kojto 90:cb3d968589d8 531 * bandgap operation. When the bandgap voltage reference is not needed in low
Kojto 90:cb3d968589d8 532 * power modes, clear BGEN to avoid excess power consumption.
Kojto 90:cb3d968589d8 533 *
Kojto 90:cb3d968589d8 534 * Values:
Kojto 90:cb3d968589d8 535 * - 0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
Kojto 90:cb3d968589d8 536 * - 1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
Kojto 90:cb3d968589d8 537 */
Kojto 90:cb3d968589d8 538 /*@{*/
Kojto 90:cb3d968589d8 539 #define BP_PMC_REGSC_BGEN (4U) /*!< Bit position for PMC_REGSC_BGEN. */
Kojto 90:cb3d968589d8 540 #define BM_PMC_REGSC_BGEN (0x10U) /*!< Bit mask for PMC_REGSC_BGEN. */
Kojto 90:cb3d968589d8 541 #define BS_PMC_REGSC_BGEN (1U) /*!< Bit field size in bits for PMC_REGSC_BGEN. */
Kojto 90:cb3d968589d8 542
Kojto 90:cb3d968589d8 543 /*! @brief Read current value of the PMC_REGSC_BGEN field. */
Kojto 90:cb3d968589d8 544 #define BR_PMC_REGSC_BGEN(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGEN))
Kojto 90:cb3d968589d8 545
Kojto 90:cb3d968589d8 546 /*! @brief Format value for bitfield PMC_REGSC_BGEN. */
Kojto 90:cb3d968589d8 547 #define BF_PMC_REGSC_BGEN(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_BGEN) & BM_PMC_REGSC_BGEN)
Kojto 90:cb3d968589d8 548
Kojto 90:cb3d968589d8 549 /*! @brief Set the BGEN field to a new value. */
Kojto 90:cb3d968589d8 550 #define BW_PMC_REGSC_BGEN(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGEN) = (v))
Kojto 90:cb3d968589d8 551 /*@}*/
Kojto 90:cb3d968589d8 552
Kojto 90:cb3d968589d8 553 /*******************************************************************************
Kojto 90:cb3d968589d8 554 * hw_pmc_t - module struct
Kojto 90:cb3d968589d8 555 ******************************************************************************/
Kojto 90:cb3d968589d8 556 /*!
Kojto 90:cb3d968589d8 557 * @brief All PMC module registers.
Kojto 90:cb3d968589d8 558 */
Kojto 90:cb3d968589d8 559 #pragma pack(1)
Kojto 90:cb3d968589d8 560 typedef struct _hw_pmc
Kojto 90:cb3d968589d8 561 {
Kojto 90:cb3d968589d8 562 __IO hw_pmc_lvdsc1_t LVDSC1; /*!< [0x0] Low Voltage Detect Status And Control 1 register */
Kojto 90:cb3d968589d8 563 __IO hw_pmc_lvdsc2_t LVDSC2; /*!< [0x1] Low Voltage Detect Status And Control 2 register */
Kojto 90:cb3d968589d8 564 __IO hw_pmc_regsc_t REGSC; /*!< [0x2] Regulator Status And Control register */
Kojto 90:cb3d968589d8 565 } hw_pmc_t;
Kojto 90:cb3d968589d8 566 #pragma pack()
Kojto 90:cb3d968589d8 567
Kojto 90:cb3d968589d8 568 /*! @brief Macro to access all PMC registers. */
Kojto 90:cb3d968589d8 569 /*! @param x PMC module instance base address. */
Kojto 90:cb3d968589d8 570 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto 90:cb3d968589d8 571 * use the '&' operator, like <code>&HW_PMC(PMC_BASE)</code>. */
Kojto 90:cb3d968589d8 572 #define HW_PMC(x) (*(hw_pmc_t *)(x))
Kojto 90:cb3d968589d8 573
Kojto 90:cb3d968589d8 574 #endif /* __HW_PMC_REGISTERS_H__ */
Kojto 90:cb3d968589d8 575 /* EOF */