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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_mpu.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:: Kojto
Date:: Wed Aug 05 13:16:35 2015 +0100
Revision:: 104:b9ad9a133dc7
Parent:: 90:cb3d968589d8

Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	90:cb3d968589d8	1	/*
Kojto	90:cb3d968589d8	2	** ###################################################################
Kojto	90:cb3d968589d8	3	** Compilers: Keil ARM C/C++ Compiler
Kojto	90:cb3d968589d8	4	** Freescale C/C++ for Embedded ARM
Kojto	90:cb3d968589d8	5	** GNU C Compiler
Kojto	90:cb3d968589d8	6	** IAR ANSI C/C++ Compiler for ARM
Kojto	90:cb3d968589d8	7	**
Kojto	90:cb3d968589d8	8	** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto	90:cb3d968589d8	9	** Version: rev. 2.5, 2014-02-10
Kojto	90:cb3d968589d8	10	** Build: b140604
Kojto	90:cb3d968589d8	11	**
Kojto	90:cb3d968589d8	12	** Abstract:
Kojto	90:cb3d968589d8	13	** Extension to the CMSIS register access layer header.
Kojto	90:cb3d968589d8	14	**
Kojto	90:cb3d968589d8	15	** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto	90:cb3d968589d8	16	** All rights reserved.
Kojto	90:cb3d968589d8	17	**
Kojto	90:cb3d968589d8	18	** Redistribution and use in source and binary forms, with or without modification,
Kojto	90:cb3d968589d8	19	** are permitted provided that the following conditions are met:
Kojto	90:cb3d968589d8	20	**
Kojto	90:cb3d968589d8	21	** o Redistributions of source code must retain the above copyright notice, this list
Kojto	90:cb3d968589d8	22	** of conditions and the following disclaimer.
Kojto	90:cb3d968589d8	23	**
Kojto	90:cb3d968589d8	24	** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto	90:cb3d968589d8	25	** list of conditions and the following disclaimer in the documentation and/or
Kojto	90:cb3d968589d8	26	** other materials provided with the distribution.
Kojto	90:cb3d968589d8	27	**
Kojto	90:cb3d968589d8	28	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto	90:cb3d968589d8	29	** contributors may be used to endorse or promote products derived from this
Kojto	90:cb3d968589d8	30	** software without specific prior written permission.
Kojto	90:cb3d968589d8	31	**
Kojto	90:cb3d968589d8	32	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto	90:cb3d968589d8	33	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto	90:cb3d968589d8	34	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	90:cb3d968589d8	35	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto	90:cb3d968589d8	36	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto	90:cb3d968589d8	37	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto	90:cb3d968589d8	38	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto	90:cb3d968589d8	39	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto	90:cb3d968589d8	40	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto	90:cb3d968589d8	41	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	90:cb3d968589d8	42	**
Kojto	90:cb3d968589d8	43	** http: www.freescale.com
Kojto	90:cb3d968589d8	44	** mail: support@freescale.com
Kojto	90:cb3d968589d8	45	**
Kojto	90:cb3d968589d8	46	** Revisions:
Kojto	90:cb3d968589d8	47	** - rev. 1.0 (2013-08-12)
Kojto	90:cb3d968589d8	48	** Initial version.
Kojto	90:cb3d968589d8	49	** - rev. 2.0 (2013-10-29)
Kojto	90:cb3d968589d8	50	** Register accessor macros added to the memory map.
Kojto	90:cb3d968589d8	51	** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto	90:cb3d968589d8	52	** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto	90:cb3d968589d8	53	** System initialization updated.
Kojto	90:cb3d968589d8	54	** MCG - registers updated.
Kojto	90:cb3d968589d8	55	** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto	90:cb3d968589d8	56	** - rev. 2.1 (2013-10-30)
Kojto	90:cb3d968589d8	57	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto	90:cb3d968589d8	58	** - rev. 2.2 (2013-12-09)
Kojto	90:cb3d968589d8	59	** DMA - EARS register removed.
Kojto	90:cb3d968589d8	60	** AIPS0, AIPS1 - MPRA register updated.
Kojto	90:cb3d968589d8	61	** - rev. 2.3 (2014-01-24)
Kojto	90:cb3d968589d8	62	** Update according to reference manual rev. 2
Kojto	90:cb3d968589d8	63	** ENET, MCG, MCM, SIM, USB - registers updated
Kojto	90:cb3d968589d8	64	** - rev. 2.4 (2014-02-10)
Kojto	90:cb3d968589d8	65	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	66	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	67	** - rev. 2.5 (2014-02-10)
Kojto	90:cb3d968589d8	68	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	69	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	70	** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto	90:cb3d968589d8	71	**
Kojto	90:cb3d968589d8	72	** ###################################################################
Kojto	90:cb3d968589d8	73	*/
Kojto	90:cb3d968589d8	74
Kojto	90:cb3d968589d8	75	/*
Kojto	90:cb3d968589d8	76	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto	90:cb3d968589d8	77	*
Kojto	90:cb3d968589d8	78	* This file was generated automatically and any changes may be lost.
Kojto	90:cb3d968589d8	79	*/
Kojto	90:cb3d968589d8	80	#ifndef __HW_MPU_REGISTERS_H__
Kojto	90:cb3d968589d8	81	#define __HW_MPU_REGISTERS_H__
Kojto	90:cb3d968589d8	82
Kojto	90:cb3d968589d8	83	#include "MK64F12.h"
Kojto	90:cb3d968589d8	84	#include "fsl_bitaccess.h"
Kojto	90:cb3d968589d8	85
Kojto	90:cb3d968589d8	86	/*
Kojto	90:cb3d968589d8	87	* MK64F12 MPU
Kojto	90:cb3d968589d8	88	*
Kojto	90:cb3d968589d8	89	* Memory protection unit
Kojto	90:cb3d968589d8	90	*
Kojto	90:cb3d968589d8	91	* Registers defined in this header file:
Kojto	90:cb3d968589d8	92	* - HW_MPU_CESR - Control/Error Status Register
Kojto	90:cb3d968589d8	93	* - HW_MPU_EARn - Error Address Register, slave port n
Kojto	90:cb3d968589d8	94	* - HW_MPU_EDRn - Error Detail Register, slave port n
Kojto	90:cb3d968589d8	95	* - HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0
Kojto	90:cb3d968589d8	96	* - HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1
Kojto	90:cb3d968589d8	97	* - HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2
Kojto	90:cb3d968589d8	98	* - HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3
Kojto	90:cb3d968589d8	99	* - HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n
Kojto	90:cb3d968589d8	100	*
Kojto	90:cb3d968589d8	101	* - hw_mpu_t - Struct containing all module registers.
Kojto	90:cb3d968589d8	102	*/
Kojto	90:cb3d968589d8	103
Kojto	90:cb3d968589d8	104	#define HW_MPU_INSTANCE_COUNT (1U) /!< Number of instances of the MPU module. /
Kojto	90:cb3d968589d8	105
Kojto	90:cb3d968589d8	106	/*******************************************************************************
Kojto	90:cb3d968589d8	107	* HW_MPU_CESR - Control/Error Status Register
Kojto	90:cb3d968589d8	108	******************************************************************************/
Kojto	90:cb3d968589d8	109
Kojto	90:cb3d968589d8	110	/*!
Kojto	90:cb3d968589d8	111	* @brief HW_MPU_CESR - Control/Error Status Register (RW)
Kojto	90:cb3d968589d8	112	*
Kojto	90:cb3d968589d8	113	* Reset value: 0x00815101U
Kojto	90:cb3d968589d8	114	*/
Kojto	90:cb3d968589d8	115	typedef union _hw_mpu_cesr
Kojto	90:cb3d968589d8	116	{
Kojto	90:cb3d968589d8	117	uint32_t U;
Kojto	90:cb3d968589d8	118	struct _hw_mpu_cesr_bitfields
Kojto	90:cb3d968589d8	119	{
Kojto	90:cb3d968589d8	120	uint32_t VLD : 1; /!< [0] Valid /
Kojto	90:cb3d968589d8	121	uint32_t RESERVED0 : 7; /!< [7:1] /
Kojto	90:cb3d968589d8	122	uint32_t NRGD : 4; /!< [11:8] Number Of Region Descriptors /
Kojto	90:cb3d968589d8	123	uint32_t NSP : 4; /!< [15:12] Number Of Slave Ports /
Kojto	90:cb3d968589d8	124	uint32_t HRL : 4; /!< [19:16] Hardware Revision Level /
Kojto	90:cb3d968589d8	125	uint32_t RESERVED1 : 7; /!< [26:20] /
Kojto	90:cb3d968589d8	126	uint32_t SPERR : 5; /!< [31:27] Slave Port n Error /
Kojto	90:cb3d968589d8	127	} B;
Kojto	90:cb3d968589d8	128	} hw_mpu_cesr_t;
Kojto	90:cb3d968589d8	129
Kojto	90:cb3d968589d8	130	/*!
Kojto	90:cb3d968589d8	131	* @name Constants and macros for entire MPU_CESR register
Kojto	90:cb3d968589d8	132	*/
Kojto	90:cb3d968589d8	133	/@{/
Kojto	90:cb3d968589d8	134	#define HW_MPU_CESR_ADDR(x) ((x) + 0x0U)
Kojto	90:cb3d968589d8	135
Kojto	90:cb3d968589d8	136	#define HW_MPU_CESR(x) ((__IO hw_mpu_cesr_t ) HW_MPU_CESR_ADDR(x))
Kojto	90:cb3d968589d8	137	#define HW_MPU_CESR_RD(x) (HW_MPU_CESR(x).U)
Kojto	90:cb3d968589d8	138	#define HW_MPU_CESR_WR(x, v) (HW_MPU_CESR(x).U = (v))
Kojto	90:cb3d968589d8	139	#define HW_MPU_CESR_SET(x, v) (HW_MPU_CESR_WR(x, HW_MPU_CESR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	140	#define HW_MPU_CESR_CLR(x, v) (HW_MPU_CESR_WR(x, HW_MPU_CESR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	141	#define HW_MPU_CESR_TOG(x, v) (HW_MPU_CESR_WR(x, HW_MPU_CESR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	142	/@}/
Kojto	90:cb3d968589d8	143
Kojto	90:cb3d968589d8	144	/*
Kojto	90:cb3d968589d8	145	* Constants & macros for individual MPU_CESR bitfields
Kojto	90:cb3d968589d8	146	*/
Kojto	90:cb3d968589d8	147
Kojto	90:cb3d968589d8	148	/*!
Kojto	90:cb3d968589d8	149	* @name Register MPU_CESR, field VLD[0] (RW)
Kojto	90:cb3d968589d8	150	*
Kojto	90:cb3d968589d8	151	* Global enable/disable for the MPU.
Kojto	90:cb3d968589d8	152	*
Kojto	90:cb3d968589d8	153	* Values:
Kojto	90:cb3d968589d8	154	* - 0 - MPU is disabled. All accesses from all bus masters are allowed.
Kojto	90:cb3d968589d8	155	* - 1 - MPU is enabled
Kojto	90:cb3d968589d8	156	*/
Kojto	90:cb3d968589d8	157	/@{/
Kojto	90:cb3d968589d8	158	#define BP_MPU_CESR_VLD (0U) /!< Bit position for MPU_CESR_VLD. /
Kojto	90:cb3d968589d8	159	#define BM_MPU_CESR_VLD (0x00000001U) /!< Bit mask for MPU_CESR_VLD. /
Kojto	90:cb3d968589d8	160	#define BS_MPU_CESR_VLD (1U) /!< Bit field size in bits for MPU_CESR_VLD. /
Kojto	90:cb3d968589d8	161
Kojto	90:cb3d968589d8	162	/! @brief Read current value of the MPU_CESR_VLD field. /
Kojto	90:cb3d968589d8	163	#define BR_MPU_CESR_VLD(x) (BITBAND_ACCESS32(HW_MPU_CESR_ADDR(x), BP_MPU_CESR_VLD))
Kojto	90:cb3d968589d8	164
Kojto	90:cb3d968589d8	165	/! @brief Format value for bitfield MPU_CESR_VLD. /
Kojto	90:cb3d968589d8	166	#define BF_MPU_CESR_VLD(v) ((uint32_t)((uint32_t)(v) << BP_MPU_CESR_VLD) & BM_MPU_CESR_VLD)
Kojto	90:cb3d968589d8	167
Kojto	90:cb3d968589d8	168	/! @brief Set the VLD field to a new value. /
Kojto	90:cb3d968589d8	169	#define BW_MPU_CESR_VLD(x, v) (BITBAND_ACCESS32(HW_MPU_CESR_ADDR(x), BP_MPU_CESR_VLD) = (v))
Kojto	90:cb3d968589d8	170	/@}/
Kojto	90:cb3d968589d8	171
Kojto	90:cb3d968589d8	172	/*!
Kojto	90:cb3d968589d8	173	* @name Register MPU_CESR, field NRGD[11:8] (RO)
Kojto	90:cb3d968589d8	174	*
Kojto	90:cb3d968589d8	175	* Indicates the number of region descriptors implemented in the MPU.
Kojto	90:cb3d968589d8	176	*
Kojto	90:cb3d968589d8	177	* Values:
Kojto	90:cb3d968589d8	178	* - 0000 - 8 region descriptors
Kojto	90:cb3d968589d8	179	* - 0001 - 12 region descriptors
Kojto	90:cb3d968589d8	180	* - 0010 - 16 region descriptors
Kojto	90:cb3d968589d8	181	*/
Kojto	90:cb3d968589d8	182	/@{/
Kojto	90:cb3d968589d8	183	#define BP_MPU_CESR_NRGD (8U) /!< Bit position for MPU_CESR_NRGD. /
Kojto	90:cb3d968589d8	184	#define BM_MPU_CESR_NRGD (0x00000F00U) /!< Bit mask for MPU_CESR_NRGD. /
Kojto	90:cb3d968589d8	185	#define BS_MPU_CESR_NRGD (4U) /!< Bit field size in bits for MPU_CESR_NRGD. /
Kojto	90:cb3d968589d8	186
Kojto	90:cb3d968589d8	187	/! @brief Read current value of the MPU_CESR_NRGD field. /
Kojto	90:cb3d968589d8	188	#define BR_MPU_CESR_NRGD(x) (HW_MPU_CESR(x).B.NRGD)
Kojto	90:cb3d968589d8	189	/@}/
Kojto	90:cb3d968589d8	190
Kojto	90:cb3d968589d8	191	/*!
Kojto	90:cb3d968589d8	192	* @name Register MPU_CESR, field NSP[15:12] (RO)
Kojto	90:cb3d968589d8	193	*
Kojto	90:cb3d968589d8	194	* Specifies the number of slave ports connected to the MPU.
Kojto	90:cb3d968589d8	195	*/
Kojto	90:cb3d968589d8	196	/@{/
Kojto	90:cb3d968589d8	197	#define BP_MPU_CESR_NSP (12U) /!< Bit position for MPU_CESR_NSP. /
Kojto	90:cb3d968589d8	198	#define BM_MPU_CESR_NSP (0x0000F000U) /!< Bit mask for MPU_CESR_NSP. /
Kojto	90:cb3d968589d8	199	#define BS_MPU_CESR_NSP (4U) /!< Bit field size in bits for MPU_CESR_NSP. /
Kojto	90:cb3d968589d8	200
Kojto	90:cb3d968589d8	201	/! @brief Read current value of the MPU_CESR_NSP field. /
Kojto	90:cb3d968589d8	202	#define BR_MPU_CESR_NSP(x) (HW_MPU_CESR(x).B.NSP)
Kojto	90:cb3d968589d8	203	/@}/
Kojto	90:cb3d968589d8	204
Kojto	90:cb3d968589d8	205	/*!
Kojto	90:cb3d968589d8	206	* @name Register MPU_CESR, field HRL[19:16] (RO)
Kojto	90:cb3d968589d8	207	*
Kojto	90:cb3d968589d8	208	* Specifies the MPU's hardware and definition revision level. It can be read by
Kojto	90:cb3d968589d8	209	* software to determine the functional definition of the module.
Kojto	90:cb3d968589d8	210	*/
Kojto	90:cb3d968589d8	211	/@{/
Kojto	90:cb3d968589d8	212	#define BP_MPU_CESR_HRL (16U) /!< Bit position for MPU_CESR_HRL. /
Kojto	90:cb3d968589d8	213	#define BM_MPU_CESR_HRL (0x000F0000U) /!< Bit mask for MPU_CESR_HRL. /
Kojto	90:cb3d968589d8	214	#define BS_MPU_CESR_HRL (4U) /!< Bit field size in bits for MPU_CESR_HRL. /
Kojto	90:cb3d968589d8	215
Kojto	90:cb3d968589d8	216	/! @brief Read current value of the MPU_CESR_HRL field. /
Kojto	90:cb3d968589d8	217	#define BR_MPU_CESR_HRL(x) (HW_MPU_CESR(x).B.HRL)
Kojto	90:cb3d968589d8	218	/@}/
Kojto	90:cb3d968589d8	219
Kojto	90:cb3d968589d8	220	/*!
Kojto	90:cb3d968589d8	221	* @name Register MPU_CESR, field SPERR[31:27] (W1C)
Kojto	90:cb3d968589d8	222	*
Kojto	90:cb3d968589d8	223	* Indicates a captured error in EARn and EDRn. This bit is set when the
Kojto	90:cb3d968589d8	224	* hardware detects an error and records the faulting address and attributes. It is
Kojto	90:cb3d968589d8	225	* cleared by writing one to it. If another error is captured at the exact same cycle
Kojto	90:cb3d968589d8	226	* as the write, the flag remains set. A find-first-one instruction or
Kojto	90:cb3d968589d8	227	* equivalent can detect the presence of a captured error. The following shows the
Kojto	90:cb3d968589d8	228	* correspondence between the bit number and slave port number: Bit 31 corresponds to
Kojto	90:cb3d968589d8	229	* slave port 0. Bit 30 corresponds to slave port 1. Bit 29 corresponds to slave
Kojto	90:cb3d968589d8	230	* port 2. Bit 28 corresponds to slave port 3. Bit 27 corresponds to slave port 4.
Kojto	90:cb3d968589d8	231	*
Kojto	90:cb3d968589d8	232	* Values:
Kojto	90:cb3d968589d8	233	* - 0 - No error has occurred for slave port n.
Kojto	90:cb3d968589d8	234	* - 1 - An error has occurred for slave port n.
Kojto	90:cb3d968589d8	235	*/
Kojto	90:cb3d968589d8	236	/@{/
Kojto	90:cb3d968589d8	237	#define BP_MPU_CESR_SPERR (27U) /!< Bit position for MPU_CESR_SPERR. /
Kojto	90:cb3d968589d8	238	#define BM_MPU_CESR_SPERR (0xF8000000U) /!< Bit mask for MPU_CESR_SPERR. /
Kojto	90:cb3d968589d8	239	#define BS_MPU_CESR_SPERR (5U) /!< Bit field size in bits for MPU_CESR_SPERR. /
Kojto	90:cb3d968589d8	240
Kojto	90:cb3d968589d8	241	/! @brief Read current value of the MPU_CESR_SPERR field. /
Kojto	90:cb3d968589d8	242	#define BR_MPU_CESR_SPERR(x) (HW_MPU_CESR(x).B.SPERR)
Kojto	90:cb3d968589d8	243
Kojto	90:cb3d968589d8	244	/! @brief Format value for bitfield MPU_CESR_SPERR. /
Kojto	90:cb3d968589d8	245	#define BF_MPU_CESR_SPERR(v) ((uint32_t)((uint32_t)(v) << BP_MPU_CESR_SPERR) & BM_MPU_CESR_SPERR)
Kojto	90:cb3d968589d8	246
Kojto	90:cb3d968589d8	247	/! @brief Set the SPERR field to a new value. /
Kojto	90:cb3d968589d8	248	#define BW_MPU_CESR_SPERR(x, v) (HW_MPU_CESR_WR(x, (HW_MPU_CESR_RD(x) & ~BM_MPU_CESR_SPERR) \| BF_MPU_CESR_SPERR(v)))
Kojto	90:cb3d968589d8	249	/@}/
Kojto	90:cb3d968589d8	250
Kojto	90:cb3d968589d8	251	/*******************************************************************************
Kojto	90:cb3d968589d8	252	* HW_MPU_EARn - Error Address Register, slave port n
Kojto	90:cb3d968589d8	253	******************************************************************************/
Kojto	90:cb3d968589d8	254
Kojto	90:cb3d968589d8	255	/*!
Kojto	90:cb3d968589d8	256	* @brief HW_MPU_EARn - Error Address Register, slave port n (RO)
Kojto	90:cb3d968589d8	257	*
Kojto	90:cb3d968589d8	258	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	259	*
Kojto	90:cb3d968589d8	260	* When the MPU detects an access error on slave port n, the 32-bit reference
Kojto	90:cb3d968589d8	261	* address is captured in this read-only register and the corresponding bit in
Kojto	90:cb3d968589d8	262	* CESR[SPERR] set. Additional information about the faulting access is captured in
Kojto	90:cb3d968589d8	263	* the corresponding EDRn at the same time. This register and the corresponding
Kojto	90:cb3d968589d8	264	* EDRn contain the most recent access error; there are no hardware interlocks with
Kojto	90:cb3d968589d8	265	* CESR[SPERR], as the error registers are always loaded upon the occurrence of
Kojto	90:cb3d968589d8	266	* each protection violation.
Kojto	90:cb3d968589d8	267	*/
Kojto	90:cb3d968589d8	268	typedef union _hw_mpu_earn
Kojto	90:cb3d968589d8	269	{
Kojto	90:cb3d968589d8	270	uint32_t U;
Kojto	90:cb3d968589d8	271	struct _hw_mpu_earn_bitfields
Kojto	90:cb3d968589d8	272	{
Kojto	90:cb3d968589d8	273	uint32_t EADDR : 32; /!< [31:0] Error Address /
Kojto	90:cb3d968589d8	274	} B;
Kojto	90:cb3d968589d8	275	} hw_mpu_earn_t;
Kojto	90:cb3d968589d8	276
Kojto	90:cb3d968589d8	277	/*!
Kojto	90:cb3d968589d8	278	* @name Constants and macros for entire MPU_EARn register
Kojto	90:cb3d968589d8	279	*/
Kojto	90:cb3d968589d8	280	/@{/
Kojto	90:cb3d968589d8	281	#define HW_MPU_EARn_COUNT (5U)
Kojto	90:cb3d968589d8	282
Kojto	90:cb3d968589d8	283	#define HW_MPU_EARn_ADDR(x, n) ((x) + 0x10U + (0x8U * (n)))
Kojto	90:cb3d968589d8	284
Kojto	90:cb3d968589d8	285	#define HW_MPU_EARn(x, n) ((__I hw_mpu_earn_t ) HW_MPU_EARn_ADDR(x, n))
Kojto	90:cb3d968589d8	286	#define HW_MPU_EARn_RD(x, n) (HW_MPU_EARn(x, n).U)
Kojto	90:cb3d968589d8	287	/@}/
Kojto	90:cb3d968589d8	288
Kojto	90:cb3d968589d8	289	/*
Kojto	90:cb3d968589d8	290	* Constants & macros for individual MPU_EARn bitfields
Kojto	90:cb3d968589d8	291	*/
Kojto	90:cb3d968589d8	292
Kojto	90:cb3d968589d8	293	/*!
Kojto	90:cb3d968589d8	294	* @name Register MPU_EARn, field EADDR[31:0] (RO)
Kojto	90:cb3d968589d8	295	*
Kojto	90:cb3d968589d8	296	* Indicates the reference address from slave port n that generated the access
Kojto	90:cb3d968589d8	297	* error
Kojto	90:cb3d968589d8	298	*/
Kojto	90:cb3d968589d8	299	/@{/
Kojto	90:cb3d968589d8	300	#define BP_MPU_EARn_EADDR (0U) /!< Bit position for MPU_EARn_EADDR. /
Kojto	90:cb3d968589d8	301	#define BM_MPU_EARn_EADDR (0xFFFFFFFFU) /!< Bit mask for MPU_EARn_EADDR. /
Kojto	90:cb3d968589d8	302	#define BS_MPU_EARn_EADDR (32U) /!< Bit field size in bits for MPU_EARn_EADDR. /
Kojto	90:cb3d968589d8	303
Kojto	90:cb3d968589d8	304	/! @brief Read current value of the MPU_EARn_EADDR field. /
Kojto	90:cb3d968589d8	305	#define BR_MPU_EARn_EADDR(x, n) (HW_MPU_EARn(x, n).U)
Kojto	90:cb3d968589d8	306	/@}/
Kojto	90:cb3d968589d8	307	/*******************************************************************************
Kojto	90:cb3d968589d8	308	* HW_MPU_EDRn - Error Detail Register, slave port n
Kojto	90:cb3d968589d8	309	******************************************************************************/
Kojto	90:cb3d968589d8	310
Kojto	90:cb3d968589d8	311	/*!
Kojto	90:cb3d968589d8	312	* @brief HW_MPU_EDRn - Error Detail Register, slave port n (RO)
Kojto	90:cb3d968589d8	313	*
Kojto	90:cb3d968589d8	314	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	315	*
Kojto	90:cb3d968589d8	316	* When the MPU detects an access error on slave port n, 32 bits of error detail
Kojto	90:cb3d968589d8	317	* are captured in this read-only register and the corresponding bit in
Kojto	90:cb3d968589d8	318	* CESR[SPERR] is set. Information on the faulting address is captured in the
Kojto	90:cb3d968589d8	319	* corresponding EARn register at the same time. This register and the corresponding EARn
Kojto	90:cb3d968589d8	320	* register contain the most recent access error; there are no hardware interlocks
Kojto	90:cb3d968589d8	321	* with CESR[SPERR] as the error registers are always loaded upon the occurrence
Kojto	90:cb3d968589d8	322	* of each protection violation.
Kojto	90:cb3d968589d8	323	*/
Kojto	90:cb3d968589d8	324	typedef union _hw_mpu_edrn
Kojto	90:cb3d968589d8	325	{
Kojto	90:cb3d968589d8	326	uint32_t U;
Kojto	90:cb3d968589d8	327	struct _hw_mpu_edrn_bitfields
Kojto	90:cb3d968589d8	328	{
Kojto	90:cb3d968589d8	329	uint32_t ERW : 1; /!< [0] Error Read/Write /
Kojto	90:cb3d968589d8	330	uint32_t EATTR : 3; /!< [3:1] Error Attributes /
Kojto	90:cb3d968589d8	331	uint32_t EMN : 4; /!< [7:4] Error Master Number /
Kojto	90:cb3d968589d8	332	uint32_t EPID : 8; /!< [15:8] Error Process Identification /
Kojto	90:cb3d968589d8	333	uint32_t EACD : 16; /!< [31:16] Error Access Control Detail /
Kojto	90:cb3d968589d8	334	} B;
Kojto	90:cb3d968589d8	335	} hw_mpu_edrn_t;
Kojto	90:cb3d968589d8	336
Kojto	90:cb3d968589d8	337	/*!
Kojto	90:cb3d968589d8	338	* @name Constants and macros for entire MPU_EDRn register
Kojto	90:cb3d968589d8	339	*/
Kojto	90:cb3d968589d8	340	/@{/
Kojto	90:cb3d968589d8	341	#define HW_MPU_EDRn_COUNT (5U)
Kojto	90:cb3d968589d8	342
Kojto	90:cb3d968589d8	343	#define HW_MPU_EDRn_ADDR(x, n) ((x) + 0x14U + (0x8U * (n)))
Kojto	90:cb3d968589d8	344
Kojto	90:cb3d968589d8	345	#define HW_MPU_EDRn(x, n) ((__I hw_mpu_edrn_t ) HW_MPU_EDRn_ADDR(x, n))
Kojto	90:cb3d968589d8	346	#define HW_MPU_EDRn_RD(x, n) (HW_MPU_EDRn(x, n).U)
Kojto	90:cb3d968589d8	347	/@}/
Kojto	90:cb3d968589d8	348
Kojto	90:cb3d968589d8	349	/*
Kojto	90:cb3d968589d8	350	* Constants & macros for individual MPU_EDRn bitfields
Kojto	90:cb3d968589d8	351	*/
Kojto	90:cb3d968589d8	352
Kojto	90:cb3d968589d8	353	/*!
Kojto	90:cb3d968589d8	354	* @name Register MPU_EDRn, field ERW[0] (RO)
Kojto	90:cb3d968589d8	355	*
Kojto	90:cb3d968589d8	356	* Indicates the access type of the faulting reference.
Kojto	90:cb3d968589d8	357	*
Kojto	90:cb3d968589d8	358	* Values:
Kojto	90:cb3d968589d8	359	* - 0 - Read
Kojto	90:cb3d968589d8	360	* - 1 - Write
Kojto	90:cb3d968589d8	361	*/
Kojto	90:cb3d968589d8	362	/@{/
Kojto	90:cb3d968589d8	363	#define BP_MPU_EDRn_ERW (0U) /!< Bit position for MPU_EDRn_ERW. /
Kojto	90:cb3d968589d8	364	#define BM_MPU_EDRn_ERW (0x00000001U) /!< Bit mask for MPU_EDRn_ERW. /
Kojto	90:cb3d968589d8	365	#define BS_MPU_EDRn_ERW (1U) /!< Bit field size in bits for MPU_EDRn_ERW. /
Kojto	90:cb3d968589d8	366
Kojto	90:cb3d968589d8	367	/! @brief Read current value of the MPU_EDRn_ERW field. /
Kojto	90:cb3d968589d8	368	#define BR_MPU_EDRn_ERW(x, n) (BITBAND_ACCESS32(HW_MPU_EDRn_ADDR(x, n), BP_MPU_EDRn_ERW))
Kojto	90:cb3d968589d8	369	/@}/
Kojto	90:cb3d968589d8	370
Kojto	90:cb3d968589d8	371	/*!
Kojto	90:cb3d968589d8	372	* @name Register MPU_EDRn, field EATTR[3:1] (RO)
Kojto	90:cb3d968589d8	373	*
Kojto	90:cb3d968589d8	374	* Indicates attribute information about the faulting reference. All other
Kojto	90:cb3d968589d8	375	* encodings are reserved.
Kojto	90:cb3d968589d8	376	*
Kojto	90:cb3d968589d8	377	* Values:
Kojto	90:cb3d968589d8	378	* - 000 - User mode, instruction access
Kojto	90:cb3d968589d8	379	* - 001 - User mode, data access
Kojto	90:cb3d968589d8	380	* - 010 - Supervisor mode, instruction access
Kojto	90:cb3d968589d8	381	* - 011 - Supervisor mode, data access
Kojto	90:cb3d968589d8	382	*/
Kojto	90:cb3d968589d8	383	/@{/
Kojto	90:cb3d968589d8	384	#define BP_MPU_EDRn_EATTR (1U) /!< Bit position for MPU_EDRn_EATTR. /
Kojto	90:cb3d968589d8	385	#define BM_MPU_EDRn_EATTR (0x0000000EU) /!< Bit mask for MPU_EDRn_EATTR. /
Kojto	90:cb3d968589d8	386	#define BS_MPU_EDRn_EATTR (3U) /!< Bit field size in bits for MPU_EDRn_EATTR. /
Kojto	90:cb3d968589d8	387
Kojto	90:cb3d968589d8	388	/! @brief Read current value of the MPU_EDRn_EATTR field. /
Kojto	90:cb3d968589d8	389	#define BR_MPU_EDRn_EATTR(x, n) (HW_MPU_EDRn(x, n).B.EATTR)
Kojto	90:cb3d968589d8	390	/@}/
Kojto	90:cb3d968589d8	391
Kojto	90:cb3d968589d8	392	/*!
Kojto	90:cb3d968589d8	393	* @name Register MPU_EDRn, field EMN[7:4] (RO)
Kojto	90:cb3d968589d8	394	*
Kojto	90:cb3d968589d8	395	* Indicates the bus master that generated the access error.
Kojto	90:cb3d968589d8	396	*/
Kojto	90:cb3d968589d8	397	/@{/
Kojto	90:cb3d968589d8	398	#define BP_MPU_EDRn_EMN (4U) /!< Bit position for MPU_EDRn_EMN. /
Kojto	90:cb3d968589d8	399	#define BM_MPU_EDRn_EMN (0x000000F0U) /!< Bit mask for MPU_EDRn_EMN. /
Kojto	90:cb3d968589d8	400	#define BS_MPU_EDRn_EMN (4U) /!< Bit field size in bits for MPU_EDRn_EMN. /
Kojto	90:cb3d968589d8	401
Kojto	90:cb3d968589d8	402	/! @brief Read current value of the MPU_EDRn_EMN field. /
Kojto	90:cb3d968589d8	403	#define BR_MPU_EDRn_EMN(x, n) (HW_MPU_EDRn(x, n).B.EMN)
Kojto	90:cb3d968589d8	404	/@}/
Kojto	90:cb3d968589d8	405
Kojto	90:cb3d968589d8	406	/*!
Kojto	90:cb3d968589d8	407	* @name Register MPU_EDRn, field EPID[15:8] (RO)
Kojto	90:cb3d968589d8	408	*
Kojto	90:cb3d968589d8	409	* Records the process identifier of the faulting reference. The process
Kojto	90:cb3d968589d8	410	* identifier is typically driven only by processor cores; for other bus masters, this
Kojto	90:cb3d968589d8	411	* field is cleared.
Kojto	90:cb3d968589d8	412	*/
Kojto	90:cb3d968589d8	413	/@{/
Kojto	90:cb3d968589d8	414	#define BP_MPU_EDRn_EPID (8U) /!< Bit position for MPU_EDRn_EPID. /
Kojto	90:cb3d968589d8	415	#define BM_MPU_EDRn_EPID (0x0000FF00U) /!< Bit mask for MPU_EDRn_EPID. /
Kojto	90:cb3d968589d8	416	#define BS_MPU_EDRn_EPID (8U) /!< Bit field size in bits for MPU_EDRn_EPID. /
Kojto	90:cb3d968589d8	417
Kojto	90:cb3d968589d8	418	/! @brief Read current value of the MPU_EDRn_EPID field. /
Kojto	90:cb3d968589d8	419	#define BR_MPU_EDRn_EPID(x, n) (HW_MPU_EDRn(x, n).B.EPID)
Kojto	90:cb3d968589d8	420	/@}/
Kojto	90:cb3d968589d8	421
Kojto	90:cb3d968589d8	422	/*!
Kojto	90:cb3d968589d8	423	* @name Register MPU_EDRn, field EACD[31:16] (RO)
Kojto	90:cb3d968589d8	424	*
Kojto	90:cb3d968589d8	425	* Indicates the region descriptor with the access error. If EDRn contains a
Kojto	90:cb3d968589d8	426	* captured error and EACD is cleared, an access did not hit in any region
Kojto	90:cb3d968589d8	427	* descriptor. If only a single EACD bit is set, the protection error was caused by a
Kojto	90:cb3d968589d8	428	* single non-overlapping region descriptor. If two or more EACD bits are set, the
Kojto	90:cb3d968589d8	429	* protection error was caused by an overlapping set of region descriptors.
Kojto	90:cb3d968589d8	430	*/
Kojto	90:cb3d968589d8	431	/@{/
Kojto	90:cb3d968589d8	432	#define BP_MPU_EDRn_EACD (16U) /!< Bit position for MPU_EDRn_EACD. /
Kojto	90:cb3d968589d8	433	#define BM_MPU_EDRn_EACD (0xFFFF0000U) /!< Bit mask for MPU_EDRn_EACD. /
Kojto	90:cb3d968589d8	434	#define BS_MPU_EDRn_EACD (16U) /!< Bit field size in bits for MPU_EDRn_EACD. /
Kojto	90:cb3d968589d8	435
Kojto	90:cb3d968589d8	436	/! @brief Read current value of the MPU_EDRn_EACD field. /
Kojto	90:cb3d968589d8	437	#define BR_MPU_EDRn_EACD(x, n) (HW_MPU_EDRn(x, n).B.EACD)
Kojto	90:cb3d968589d8	438	/@}/
Kojto	90:cb3d968589d8	439
Kojto	90:cb3d968589d8	440	/*******************************************************************************
Kojto	90:cb3d968589d8	441	* HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0
Kojto	90:cb3d968589d8	442	******************************************************************************/
Kojto	90:cb3d968589d8	443
Kojto	90:cb3d968589d8	444	/*!
Kojto	90:cb3d968589d8	445	* @brief HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0 (RW)
Kojto	90:cb3d968589d8	446	*
Kojto	90:cb3d968589d8	447	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	448	*
Kojto	90:cb3d968589d8	449	* The first word of the region descriptor defines the 0-modulo-32 byte start
Kojto	90:cb3d968589d8	450	* address of the memory region. Writes to this register clear the region
Kojto	90:cb3d968589d8	451	* descriptor's valid bit (RGDn_WORD3[VLD]).
Kojto	90:cb3d968589d8	452	*/
Kojto	90:cb3d968589d8	453	typedef union _hw_mpu_rgdn_word0
Kojto	90:cb3d968589d8	454	{
Kojto	90:cb3d968589d8	455	uint32_t U;
Kojto	90:cb3d968589d8	456	struct _hw_mpu_rgdn_word0_bitfields
Kojto	90:cb3d968589d8	457	{
Kojto	90:cb3d968589d8	458	uint32_t RESERVED0 : 5; /!< [4:0] /
Kojto	90:cb3d968589d8	459	uint32_t SRTADDR : 27; /!< [31:5] Start Address /
Kojto	90:cb3d968589d8	460	} B;
Kojto	90:cb3d968589d8	461	} hw_mpu_rgdn_word0_t;
Kojto	90:cb3d968589d8	462
Kojto	90:cb3d968589d8	463	/*!
Kojto	90:cb3d968589d8	464	* @name Constants and macros for entire MPU_RGDn_WORD0 register
Kojto	90:cb3d968589d8	465	*/
Kojto	90:cb3d968589d8	466	/@{/
Kojto	90:cb3d968589d8	467	#define HW_MPU_RGDn_WORD0_COUNT (12U)
Kojto	90:cb3d968589d8	468
Kojto	90:cb3d968589d8	469	#define HW_MPU_RGDn_WORD0_ADDR(x, n) ((x) + 0x400U + (0x10U * (n)))
Kojto	90:cb3d968589d8	470
Kojto	90:cb3d968589d8	471	#define HW_MPU_RGDn_WORD0(x, n) ((__IO hw_mpu_rgdn_word0_t ) HW_MPU_RGDn_WORD0_ADDR(x, n))
Kojto	90:cb3d968589d8	472	#define HW_MPU_RGDn_WORD0_RD(x, n) (HW_MPU_RGDn_WORD0(x, n).U)
Kojto	90:cb3d968589d8	473	#define HW_MPU_RGDn_WORD0_WR(x, n, v) (HW_MPU_RGDn_WORD0(x, n).U = (v))
Kojto	90:cb3d968589d8	474	#define HW_MPU_RGDn_WORD0_SET(x, n, v) (HW_MPU_RGDn_WORD0_WR(x, n, HW_MPU_RGDn_WORD0_RD(x, n) \| (v)))
Kojto	90:cb3d968589d8	475	#define HW_MPU_RGDn_WORD0_CLR(x, n, v) (HW_MPU_RGDn_WORD0_WR(x, n, HW_MPU_RGDn_WORD0_RD(x, n) & ~(v)))
Kojto	90:cb3d968589d8	476	#define HW_MPU_RGDn_WORD0_TOG(x, n, v) (HW_MPU_RGDn_WORD0_WR(x, n, HW_MPU_RGDn_WORD0_RD(x, n) ^ (v)))
Kojto	90:cb3d968589d8	477	/@}/
Kojto	90:cb3d968589d8	478
Kojto	90:cb3d968589d8	479	/*
Kojto	90:cb3d968589d8	480	* Constants & macros for individual MPU_RGDn_WORD0 bitfields
Kojto	90:cb3d968589d8	481	*/
Kojto	90:cb3d968589d8	482
Kojto	90:cb3d968589d8	483	/*!
Kojto	90:cb3d968589d8	484	* @name Register MPU_RGDn_WORD0, field SRTADDR[31:5] (RW)
Kojto	90:cb3d968589d8	485	*
Kojto	90:cb3d968589d8	486	* Defines the most significant bits of the 0-modulo-32 byte start address of
Kojto	90:cb3d968589d8	487	* the memory region.
Kojto	90:cb3d968589d8	488	*/
Kojto	90:cb3d968589d8	489	/@{/
Kojto	90:cb3d968589d8	490	#define BP_MPU_RGDn_WORD0_SRTADDR (5U) /!< Bit position for MPU_RGDn_WORD0_SRTADDR. /
Kojto	90:cb3d968589d8	491	#define BM_MPU_RGDn_WORD0_SRTADDR (0xFFFFFFE0U) /!< Bit mask for MPU_RGDn_WORD0_SRTADDR. /
Kojto	90:cb3d968589d8	492	#define BS_MPU_RGDn_WORD0_SRTADDR (27U) /!< Bit field size in bits for MPU_RGDn_WORD0_SRTADDR. /
Kojto	90:cb3d968589d8	493
Kojto	90:cb3d968589d8	494	/! @brief Read current value of the MPU_RGDn_WORD0_SRTADDR field. /
Kojto	90:cb3d968589d8	495	#define BR_MPU_RGDn_WORD0_SRTADDR(x, n) (HW_MPU_RGDn_WORD0(x, n).B.SRTADDR)
Kojto	90:cb3d968589d8	496
Kojto	90:cb3d968589d8	497	/! @brief Format value for bitfield MPU_RGDn_WORD0_SRTADDR. /
Kojto	90:cb3d968589d8	498	#define BF_MPU_RGDn_WORD0_SRTADDR(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD0_SRTADDR) & BM_MPU_RGDn_WORD0_SRTADDR)
Kojto	90:cb3d968589d8	499
Kojto	90:cb3d968589d8	500	/! @brief Set the SRTADDR field to a new value. /
Kojto	90:cb3d968589d8	501	#define BW_MPU_RGDn_WORD0_SRTADDR(x, n, v) (HW_MPU_RGDn_WORD0_WR(x, n, (HW_MPU_RGDn_WORD0_RD(x, n) & ~BM_MPU_RGDn_WORD0_SRTADDR) \| BF_MPU_RGDn_WORD0_SRTADDR(v)))
Kojto	90:cb3d968589d8	502	/@}/
Kojto	90:cb3d968589d8	503	/*******************************************************************************
Kojto	90:cb3d968589d8	504	* HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1
Kojto	90:cb3d968589d8	505	******************************************************************************/
Kojto	90:cb3d968589d8	506
Kojto	90:cb3d968589d8	507	/*!
Kojto	90:cb3d968589d8	508	* @brief HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1 (RW)
Kojto	90:cb3d968589d8	509	*
Kojto	90:cb3d968589d8	510	* Reset value: 0xFFFFFFFFU
Kojto	90:cb3d968589d8	511	*
Kojto	90:cb3d968589d8	512	* The second word of the region descriptor defines the 31-modulo-32 byte end
Kojto	90:cb3d968589d8	513	* address of the memory region. Writes to this register clear the region
Kojto	90:cb3d968589d8	514	* descriptor's valid bit (RGDn_WORD3[VLD]).
Kojto	90:cb3d968589d8	515	*/
Kojto	90:cb3d968589d8	516	typedef union _hw_mpu_rgdn_word1
Kojto	90:cb3d968589d8	517	{
Kojto	90:cb3d968589d8	518	uint32_t U;
Kojto	90:cb3d968589d8	519	struct _hw_mpu_rgdn_word1_bitfields
Kojto	90:cb3d968589d8	520	{
Kojto	90:cb3d968589d8	521	uint32_t RESERVED0 : 5; /!< [4:0] /
Kojto	90:cb3d968589d8	522	uint32_t ENDADDR : 27; /!< [31:5] End Address /
Kojto	90:cb3d968589d8	523	} B;
Kojto	90:cb3d968589d8	524	} hw_mpu_rgdn_word1_t;
Kojto	90:cb3d968589d8	525
Kojto	90:cb3d968589d8	526	/*!
Kojto	90:cb3d968589d8	527	* @name Constants and macros for entire MPU_RGDn_WORD1 register
Kojto	90:cb3d968589d8	528	*/
Kojto	90:cb3d968589d8	529	/@{/
Kojto	90:cb3d968589d8	530	#define HW_MPU_RGDn_WORD1_COUNT (12U)
Kojto	90:cb3d968589d8	531
Kojto	90:cb3d968589d8	532	#define HW_MPU_RGDn_WORD1_ADDR(x, n) ((x) + 0x404U + (0x10U * (n)))
Kojto	90:cb3d968589d8	533
Kojto	90:cb3d968589d8	534	#define HW_MPU_RGDn_WORD1(x, n) ((__IO hw_mpu_rgdn_word1_t ) HW_MPU_RGDn_WORD1_ADDR(x, n))
Kojto	90:cb3d968589d8	535	#define HW_MPU_RGDn_WORD1_RD(x, n) (HW_MPU_RGDn_WORD1(x, n).U)
Kojto	90:cb3d968589d8	536	#define HW_MPU_RGDn_WORD1_WR(x, n, v) (HW_MPU_RGDn_WORD1(x, n).U = (v))
Kojto	90:cb3d968589d8	537	#define HW_MPU_RGDn_WORD1_SET(x, n, v) (HW_MPU_RGDn_WORD1_WR(x, n, HW_MPU_RGDn_WORD1_RD(x, n) \| (v)))
Kojto	90:cb3d968589d8	538	#define HW_MPU_RGDn_WORD1_CLR(x, n, v) (HW_MPU_RGDn_WORD1_WR(x, n, HW_MPU_RGDn_WORD1_RD(x, n) & ~(v)))
Kojto	90:cb3d968589d8	539	#define HW_MPU_RGDn_WORD1_TOG(x, n, v) (HW_MPU_RGDn_WORD1_WR(x, n, HW_MPU_RGDn_WORD1_RD(x, n) ^ (v)))
Kojto	90:cb3d968589d8	540	/@}/
Kojto	90:cb3d968589d8	541
Kojto	90:cb3d968589d8	542	/*
Kojto	90:cb3d968589d8	543	* Constants & macros for individual MPU_RGDn_WORD1 bitfields
Kojto	90:cb3d968589d8	544	*/
Kojto	90:cb3d968589d8	545
Kojto	90:cb3d968589d8	546	/*!
Kojto	90:cb3d968589d8	547	* @name Register MPU_RGDn_WORD1, field ENDADDR[31:5] (RW)
Kojto	90:cb3d968589d8	548	*
Kojto	90:cb3d968589d8	549	* Defines the most significant bits of the 31-modulo-32 byte end address of the
Kojto	90:cb3d968589d8	550	* memory region. The MPU does not verify that ENDADDR >= SRTADDR.
Kojto	90:cb3d968589d8	551	*/
Kojto	90:cb3d968589d8	552	/@{/
Kojto	90:cb3d968589d8	553	#define BP_MPU_RGDn_WORD1_ENDADDR (5U) /!< Bit position for MPU_RGDn_WORD1_ENDADDR. /
Kojto	90:cb3d968589d8	554	#define BM_MPU_RGDn_WORD1_ENDADDR (0xFFFFFFE0U) /!< Bit mask for MPU_RGDn_WORD1_ENDADDR. /
Kojto	90:cb3d968589d8	555	#define BS_MPU_RGDn_WORD1_ENDADDR (27U) /!< Bit field size in bits for MPU_RGDn_WORD1_ENDADDR. /
Kojto	90:cb3d968589d8	556
Kojto	90:cb3d968589d8	557	/! @brief Read current value of the MPU_RGDn_WORD1_ENDADDR field. /
Kojto	90:cb3d968589d8	558	#define BR_MPU_RGDn_WORD1_ENDADDR(x, n) (HW_MPU_RGDn_WORD1(x, n).B.ENDADDR)
Kojto	90:cb3d968589d8	559
Kojto	90:cb3d968589d8	560	/! @brief Format value for bitfield MPU_RGDn_WORD1_ENDADDR. /
Kojto	90:cb3d968589d8	561	#define BF_MPU_RGDn_WORD1_ENDADDR(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD1_ENDADDR) & BM_MPU_RGDn_WORD1_ENDADDR)
Kojto	90:cb3d968589d8	562
Kojto	90:cb3d968589d8	563	/! @brief Set the ENDADDR field to a new value. /
Kojto	90:cb3d968589d8	564	#define BW_MPU_RGDn_WORD1_ENDADDR(x, n, v) (HW_MPU_RGDn_WORD1_WR(x, n, (HW_MPU_RGDn_WORD1_RD(x, n) & ~BM_MPU_RGDn_WORD1_ENDADDR) \| BF_MPU_RGDn_WORD1_ENDADDR(v)))
Kojto	90:cb3d968589d8	565	/@}/
Kojto	90:cb3d968589d8	566	/*******************************************************************************
Kojto	90:cb3d968589d8	567	* HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2
Kojto	90:cb3d968589d8	568	******************************************************************************/
Kojto	90:cb3d968589d8	569
Kojto	90:cb3d968589d8	570	/*!
Kojto	90:cb3d968589d8	571	* @brief HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2 (RW)
Kojto	90:cb3d968589d8	572	*
Kojto	90:cb3d968589d8	573	* Reset value: 0x0061F7DFU
Kojto	90:cb3d968589d8	574	*
Kojto	90:cb3d968589d8	575	* The third word of the region descriptor defines the access control rights of
Kojto	90:cb3d968589d8	576	* the memory region. The access control privileges depend on two broad
Kojto	90:cb3d968589d8	577	* classifications of bus masters: Bus masters 0-3 have a 5-bit field defining separate
Kojto	90:cb3d968589d8	578	* privilege rights for user and supervisor mode accesses, as well as the optional
Kojto	90:cb3d968589d8	579	* inclusion of a process identification field within the definition. Bus masters
Kojto	90:cb3d968589d8	580	* 4-7 are limited to separate read and write permissions. For the privilege
Kojto	90:cb3d968589d8	581	* rights of bus masters 0-3, there are three flags associated with this function:
Kojto	90:cb3d968589d8	582	* Read (r) refers to accessing the referenced memory address using an operand
Kojto	90:cb3d968589d8	583	* (data) fetch Write (w) refers to updating the referenced memory address using a
Kojto	90:cb3d968589d8	584	* store (data) instruction Execute (x) refers to reading the referenced memory
Kojto	90:cb3d968589d8	585	* address using an instruction fetch Writes to RGDn_WORD2 clear the region
Kojto	90:cb3d968589d8	586	* descriptor's valid bit (RGDn_WORD3[VLD]). If only updating the access controls, write
Kojto	90:cb3d968589d8	587	* to RGDAACn instead because stores to these locations do not affect the
Kojto	90:cb3d968589d8	588	* descriptor's valid bit.
Kojto	90:cb3d968589d8	589	*/
Kojto	90:cb3d968589d8	590	typedef union _hw_mpu_rgdn_word2
Kojto	90:cb3d968589d8	591	{
Kojto	90:cb3d968589d8	592	uint32_t U;
Kojto	90:cb3d968589d8	593	struct _hw_mpu_rgdn_word2_bitfields
Kojto	90:cb3d968589d8	594	{
Kojto	90:cb3d968589d8	595	uint32_t M0UM : 3; /!< [2:0] Bus Master 0 User Mode Access Control /
Kojto	90:cb3d968589d8	596	uint32_t M0SM : 2; /*!< [4:3] Bus Master 0 Supervisor Mode Access
Kojto	90:cb3d968589d8	597	* Control */
Kojto	90:cb3d968589d8	598	uint32_t M0PE : 1; /!< [5] Bus Master 0 Process Identifier enable /
Kojto	90:cb3d968589d8	599	uint32_t M1UM : 3; /!< [8:6] Bus Master 1 User Mode Access Control /
Kojto	90:cb3d968589d8	600	uint32_t M1SM : 2; /*!< [10:9] Bus Master 1 Supervisor Mode Access
Kojto	90:cb3d968589d8	601	* Control */
Kojto	90:cb3d968589d8	602	uint32_t M1PE : 1; /!< [11] Bus Master 1 Process Identifier enable /
Kojto	90:cb3d968589d8	603	uint32_t M2UM : 3; /*!< [14:12] Bus Master 2 User Mode Access control
Kojto	90:cb3d968589d8	604	* */
Kojto	90:cb3d968589d8	605	uint32_t M2SM : 2; /*!< [16:15] Bus Master 2 Supervisor Mode Access
Kojto	90:cb3d968589d8	606	* Control */
Kojto	90:cb3d968589d8	607	uint32_t M2PE : 1; /!< [17] Bus Master 2 Process Identifier Enable /
Kojto	90:cb3d968589d8	608	uint32_t M3UM : 3; /*!< [20:18] Bus Master 3 User Mode Access Control
Kojto	90:cb3d968589d8	609	* */
Kojto	90:cb3d968589d8	610	uint32_t M3SM : 2; /*!< [22:21] Bus Master 3 Supervisor Mode Access
Kojto	90:cb3d968589d8	611	* Control */
Kojto	90:cb3d968589d8	612	uint32_t M3PE : 1; /!< [23] Bus Master 3 Process Identifier Enable /
Kojto	90:cb3d968589d8	613	uint32_t M4WE : 1; /!< [24] Bus Master 4 Write Enable /
Kojto	90:cb3d968589d8	614	uint32_t M4RE : 1; /!< [25] Bus Master 4 Read Enable /
Kojto	90:cb3d968589d8	615	uint32_t M5WE : 1; /!< [26] Bus Master 5 Write Enable /
Kojto	90:cb3d968589d8	616	uint32_t M5RE : 1; /!< [27] Bus Master 5 Read Enable /
Kojto	90:cb3d968589d8	617	uint32_t M6WE : 1; /!< [28] Bus Master 6 Write Enable /
Kojto	90:cb3d968589d8	618	uint32_t M6RE : 1; /!< [29] Bus Master 6 Read Enable /
Kojto	90:cb3d968589d8	619	uint32_t M7WE : 1; /!< [30] Bus Master 7 Write Enable /
Kojto	90:cb3d968589d8	620	uint32_t M7RE : 1; /!< [31] Bus Master 7 Read Enable /
Kojto	90:cb3d968589d8	621	} B;
Kojto	90:cb3d968589d8	622	} hw_mpu_rgdn_word2_t;
Kojto	90:cb3d968589d8	623
Kojto	90:cb3d968589d8	624	/*!
Kojto	90:cb3d968589d8	625	* @name Constants and macros for entire MPU_RGDn_WORD2 register
Kojto	90:cb3d968589d8	626	*/
Kojto	90:cb3d968589d8	627	/@{/
Kojto	90:cb3d968589d8	628	#define HW_MPU_RGDn_WORD2_COUNT (12U)
Kojto	90:cb3d968589d8	629
Kojto	90:cb3d968589d8	630	#define HW_MPU_RGDn_WORD2_ADDR(x, n) ((x) + 0x408U + (0x10U * (n)))
Kojto	90:cb3d968589d8	631
Kojto	90:cb3d968589d8	632	#define HW_MPU_RGDn_WORD2(x, n) ((__IO hw_mpu_rgdn_word2_t ) HW_MPU_RGDn_WORD2_ADDR(x, n))
Kojto	90:cb3d968589d8	633	#define HW_MPU_RGDn_WORD2_RD(x, n) (HW_MPU_RGDn_WORD2(x, n).U)
Kojto	90:cb3d968589d8	634	#define HW_MPU_RGDn_WORD2_WR(x, n, v) (HW_MPU_RGDn_WORD2(x, n).U = (v))
Kojto	90:cb3d968589d8	635	#define HW_MPU_RGDn_WORD2_SET(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, HW_MPU_RGDn_WORD2_RD(x, n) \| (v)))
Kojto	90:cb3d968589d8	636	#define HW_MPU_RGDn_WORD2_CLR(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, HW_MPU_RGDn_WORD2_RD(x, n) & ~(v)))
Kojto	90:cb3d968589d8	637	#define HW_MPU_RGDn_WORD2_TOG(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, HW_MPU_RGDn_WORD2_RD(x, n) ^ (v)))
Kojto	90:cb3d968589d8	638	/@}/
Kojto	90:cb3d968589d8	639
Kojto	90:cb3d968589d8	640	/*
Kojto	90:cb3d968589d8	641	* Constants & macros for individual MPU_RGDn_WORD2 bitfields
Kojto	90:cb3d968589d8	642	*/
Kojto	90:cb3d968589d8	643
Kojto	90:cb3d968589d8	644	/*!
Kojto	90:cb3d968589d8	645	* @name Register MPU_RGDn_WORD2, field M0UM[2:0] (RW)
Kojto	90:cb3d968589d8	646	*
Kojto	90:cb3d968589d8	647	* See M3UM description.
Kojto	90:cb3d968589d8	648	*/
Kojto	90:cb3d968589d8	649	/@{/
Kojto	90:cb3d968589d8	650	#define BP_MPU_RGDn_WORD2_M0UM (0U) /!< Bit position for MPU_RGDn_WORD2_M0UM. /
Kojto	90:cb3d968589d8	651	#define BM_MPU_RGDn_WORD2_M0UM (0x00000007U) /!< Bit mask for MPU_RGDn_WORD2_M0UM. /
Kojto	90:cb3d968589d8	652	#define BS_MPU_RGDn_WORD2_M0UM (3U) /!< Bit field size in bits for MPU_RGDn_WORD2_M0UM. /
Kojto	90:cb3d968589d8	653
Kojto	90:cb3d968589d8	654	/! @brief Read current value of the MPU_RGDn_WORD2_M0UM field. /
Kojto	90:cb3d968589d8	655	#define BR_MPU_RGDn_WORD2_M0UM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M0UM)
Kojto	90:cb3d968589d8	656
Kojto	90:cb3d968589d8	657	/! @brief Format value for bitfield MPU_RGDn_WORD2_M0UM. /
Kojto	90:cb3d968589d8	658	#define BF_MPU_RGDn_WORD2_M0UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M0UM) & BM_MPU_RGDn_WORD2_M0UM)
Kojto	90:cb3d968589d8	659
Kojto	90:cb3d968589d8	660	/! @brief Set the M0UM field to a new value. /
Kojto	90:cb3d968589d8	661	#define BW_MPU_RGDn_WORD2_M0UM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M0UM) \| BF_MPU_RGDn_WORD2_M0UM(v)))
Kojto	90:cb3d968589d8	662	/@}/
Kojto	90:cb3d968589d8	663
Kojto	90:cb3d968589d8	664	/*!
Kojto	90:cb3d968589d8	665	* @name Register MPU_RGDn_WORD2, field M0SM[4:3] (RW)
Kojto	90:cb3d968589d8	666	*
Kojto	90:cb3d968589d8	667	* See M3SM description.
Kojto	90:cb3d968589d8	668	*/
Kojto	90:cb3d968589d8	669	/@{/
Kojto	90:cb3d968589d8	670	#define BP_MPU_RGDn_WORD2_M0SM (3U) /!< Bit position for MPU_RGDn_WORD2_M0SM. /
Kojto	90:cb3d968589d8	671	#define BM_MPU_RGDn_WORD2_M0SM (0x00000018U) /!< Bit mask for MPU_RGDn_WORD2_M0SM. /
Kojto	90:cb3d968589d8	672	#define BS_MPU_RGDn_WORD2_M0SM (2U) /!< Bit field size in bits for MPU_RGDn_WORD2_M0SM. /
Kojto	90:cb3d968589d8	673
Kojto	90:cb3d968589d8	674	/! @brief Read current value of the MPU_RGDn_WORD2_M0SM field. /
Kojto	90:cb3d968589d8	675	#define BR_MPU_RGDn_WORD2_M0SM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M0SM)
Kojto	90:cb3d968589d8	676
Kojto	90:cb3d968589d8	677	/! @brief Format value for bitfield MPU_RGDn_WORD2_M0SM. /
Kojto	90:cb3d968589d8	678	#define BF_MPU_RGDn_WORD2_M0SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M0SM) & BM_MPU_RGDn_WORD2_M0SM)
Kojto	90:cb3d968589d8	679
Kojto	90:cb3d968589d8	680	/! @brief Set the M0SM field to a new value. /
Kojto	90:cb3d968589d8	681	#define BW_MPU_RGDn_WORD2_M0SM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M0SM) \| BF_MPU_RGDn_WORD2_M0SM(v)))
Kojto	90:cb3d968589d8	682	/@}/
Kojto	90:cb3d968589d8	683
Kojto	90:cb3d968589d8	684	/*!
Kojto	90:cb3d968589d8	685	* @name Register MPU_RGDn_WORD2, field M0PE[5] (RW)
Kojto	90:cb3d968589d8	686	*
Kojto	90:cb3d968589d8	687	* See M0PE description.
Kojto	90:cb3d968589d8	688	*/
Kojto	90:cb3d968589d8	689	/@{/
Kojto	90:cb3d968589d8	690	#define BP_MPU_RGDn_WORD2_M0PE (5U) /!< Bit position for MPU_RGDn_WORD2_M0PE. /
Kojto	90:cb3d968589d8	691	#define BM_MPU_RGDn_WORD2_M0PE (0x00000020U) /!< Bit mask for MPU_RGDn_WORD2_M0PE. /
Kojto	90:cb3d968589d8	692	#define BS_MPU_RGDn_WORD2_M0PE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M0PE. /
Kojto	90:cb3d968589d8	693
Kojto	90:cb3d968589d8	694	/! @brief Read current value of the MPU_RGDn_WORD2_M0PE field. /
Kojto	90:cb3d968589d8	695	#define BR_MPU_RGDn_WORD2_M0PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M0PE))
Kojto	90:cb3d968589d8	696
Kojto	90:cb3d968589d8	697	/! @brief Format value for bitfield MPU_RGDn_WORD2_M0PE. /
Kojto	90:cb3d968589d8	698	#define BF_MPU_RGDn_WORD2_M0PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M0PE) & BM_MPU_RGDn_WORD2_M0PE)
Kojto	90:cb3d968589d8	699
Kojto	90:cb3d968589d8	700	/! @brief Set the M0PE field to a new value. /
Kojto	90:cb3d968589d8	701	#define BW_MPU_RGDn_WORD2_M0PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M0PE) = (v))
Kojto	90:cb3d968589d8	702	/@}/
Kojto	90:cb3d968589d8	703
Kojto	90:cb3d968589d8	704	/*!
Kojto	90:cb3d968589d8	705	* @name Register MPU_RGDn_WORD2, field M1UM[8:6] (RW)
Kojto	90:cb3d968589d8	706	*
Kojto	90:cb3d968589d8	707	* See M3UM description.
Kojto	90:cb3d968589d8	708	*/
Kojto	90:cb3d968589d8	709	/@{/
Kojto	90:cb3d968589d8	710	#define BP_MPU_RGDn_WORD2_M1UM (6U) /!< Bit position for MPU_RGDn_WORD2_M1UM. /
Kojto	90:cb3d968589d8	711	#define BM_MPU_RGDn_WORD2_M1UM (0x000001C0U) /!< Bit mask for MPU_RGDn_WORD2_M1UM. /
Kojto	90:cb3d968589d8	712	#define BS_MPU_RGDn_WORD2_M1UM (3U) /!< Bit field size in bits for MPU_RGDn_WORD2_M1UM. /
Kojto	90:cb3d968589d8	713
Kojto	90:cb3d968589d8	714	/! @brief Read current value of the MPU_RGDn_WORD2_M1UM field. /
Kojto	90:cb3d968589d8	715	#define BR_MPU_RGDn_WORD2_M1UM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M1UM)
Kojto	90:cb3d968589d8	716
Kojto	90:cb3d968589d8	717	/! @brief Format value for bitfield MPU_RGDn_WORD2_M1UM. /
Kojto	90:cb3d968589d8	718	#define BF_MPU_RGDn_WORD2_M1UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M1UM) & BM_MPU_RGDn_WORD2_M1UM)
Kojto	90:cb3d968589d8	719
Kojto	90:cb3d968589d8	720	/! @brief Set the M1UM field to a new value. /
Kojto	90:cb3d968589d8	721	#define BW_MPU_RGDn_WORD2_M1UM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M1UM) \| BF_MPU_RGDn_WORD2_M1UM(v)))
Kojto	90:cb3d968589d8	722	/@}/
Kojto	90:cb3d968589d8	723
Kojto	90:cb3d968589d8	724	/*!
Kojto	90:cb3d968589d8	725	* @name Register MPU_RGDn_WORD2, field M1SM[10:9] (RW)
Kojto	90:cb3d968589d8	726	*
Kojto	90:cb3d968589d8	727	* See M3SM description.
Kojto	90:cb3d968589d8	728	*/
Kojto	90:cb3d968589d8	729	/@{/
Kojto	90:cb3d968589d8	730	#define BP_MPU_RGDn_WORD2_M1SM (9U) /!< Bit position for MPU_RGDn_WORD2_M1SM. /
Kojto	90:cb3d968589d8	731	#define BM_MPU_RGDn_WORD2_M1SM (0x00000600U) /!< Bit mask for MPU_RGDn_WORD2_M1SM. /
Kojto	90:cb3d968589d8	732	#define BS_MPU_RGDn_WORD2_M1SM (2U) /!< Bit field size in bits for MPU_RGDn_WORD2_M1SM. /
Kojto	90:cb3d968589d8	733
Kojto	90:cb3d968589d8	734	/! @brief Read current value of the MPU_RGDn_WORD2_M1SM field. /
Kojto	90:cb3d968589d8	735	#define BR_MPU_RGDn_WORD2_M1SM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M1SM)
Kojto	90:cb3d968589d8	736
Kojto	90:cb3d968589d8	737	/! @brief Format value for bitfield MPU_RGDn_WORD2_M1SM. /
Kojto	90:cb3d968589d8	738	#define BF_MPU_RGDn_WORD2_M1SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M1SM) & BM_MPU_RGDn_WORD2_M1SM)
Kojto	90:cb3d968589d8	739
Kojto	90:cb3d968589d8	740	/! @brief Set the M1SM field to a new value. /
Kojto	90:cb3d968589d8	741	#define BW_MPU_RGDn_WORD2_M1SM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M1SM) \| BF_MPU_RGDn_WORD2_M1SM(v)))
Kojto	90:cb3d968589d8	742	/@}/
Kojto	90:cb3d968589d8	743
Kojto	90:cb3d968589d8	744	/*!
Kojto	90:cb3d968589d8	745	* @name Register MPU_RGDn_WORD2, field M1PE[11] (RW)
Kojto	90:cb3d968589d8	746	*
Kojto	90:cb3d968589d8	747	* See M3PE description.
Kojto	90:cb3d968589d8	748	*/
Kojto	90:cb3d968589d8	749	/@{/
Kojto	90:cb3d968589d8	750	#define BP_MPU_RGDn_WORD2_M1PE (11U) /!< Bit position for MPU_RGDn_WORD2_M1PE. /
Kojto	90:cb3d968589d8	751	#define BM_MPU_RGDn_WORD2_M1PE (0x00000800U) /!< Bit mask for MPU_RGDn_WORD2_M1PE. /
Kojto	90:cb3d968589d8	752	#define BS_MPU_RGDn_WORD2_M1PE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M1PE. /
Kojto	90:cb3d968589d8	753
Kojto	90:cb3d968589d8	754	/! @brief Read current value of the MPU_RGDn_WORD2_M1PE field. /
Kojto	90:cb3d968589d8	755	#define BR_MPU_RGDn_WORD2_M1PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M1PE))
Kojto	90:cb3d968589d8	756
Kojto	90:cb3d968589d8	757	/! @brief Format value for bitfield MPU_RGDn_WORD2_M1PE. /
Kojto	90:cb3d968589d8	758	#define BF_MPU_RGDn_WORD2_M1PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M1PE) & BM_MPU_RGDn_WORD2_M1PE)
Kojto	90:cb3d968589d8	759
Kojto	90:cb3d968589d8	760	/! @brief Set the M1PE field to a new value. /
Kojto	90:cb3d968589d8	761	#define BW_MPU_RGDn_WORD2_M1PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M1PE) = (v))
Kojto	90:cb3d968589d8	762	/@}/
Kojto	90:cb3d968589d8	763
Kojto	90:cb3d968589d8	764	/*!
Kojto	90:cb3d968589d8	765	* @name Register MPU_RGDn_WORD2, field M2UM[14:12] (RW)
Kojto	90:cb3d968589d8	766	*
Kojto	90:cb3d968589d8	767	* See M3UM description.
Kojto	90:cb3d968589d8	768	*/
Kojto	90:cb3d968589d8	769	/@{/
Kojto	90:cb3d968589d8	770	#define BP_MPU_RGDn_WORD2_M2UM (12U) /!< Bit position for MPU_RGDn_WORD2_M2UM. /
Kojto	90:cb3d968589d8	771	#define BM_MPU_RGDn_WORD2_M2UM (0x00007000U) /!< Bit mask for MPU_RGDn_WORD2_M2UM. /
Kojto	90:cb3d968589d8	772	#define BS_MPU_RGDn_WORD2_M2UM (3U) /!< Bit field size in bits for MPU_RGDn_WORD2_M2UM. /
Kojto	90:cb3d968589d8	773
Kojto	90:cb3d968589d8	774	/! @brief Read current value of the MPU_RGDn_WORD2_M2UM field. /
Kojto	90:cb3d968589d8	775	#define BR_MPU_RGDn_WORD2_M2UM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M2UM)
Kojto	90:cb3d968589d8	776
Kojto	90:cb3d968589d8	777	/! @brief Format value for bitfield MPU_RGDn_WORD2_M2UM. /
Kojto	90:cb3d968589d8	778	#define BF_MPU_RGDn_WORD2_M2UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M2UM) & BM_MPU_RGDn_WORD2_M2UM)
Kojto	90:cb3d968589d8	779
Kojto	90:cb3d968589d8	780	/! @brief Set the M2UM field to a new value. /
Kojto	90:cb3d968589d8	781	#define BW_MPU_RGDn_WORD2_M2UM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M2UM) \| BF_MPU_RGDn_WORD2_M2UM(v)))
Kojto	90:cb3d968589d8	782	/@}/
Kojto	90:cb3d968589d8	783
Kojto	90:cb3d968589d8	784	/*!
Kojto	90:cb3d968589d8	785	* @name Register MPU_RGDn_WORD2, field M2SM[16:15] (RW)
Kojto	90:cb3d968589d8	786	*
Kojto	90:cb3d968589d8	787	* See M3SM description.
Kojto	90:cb3d968589d8	788	*/
Kojto	90:cb3d968589d8	789	/@{/
Kojto	90:cb3d968589d8	790	#define BP_MPU_RGDn_WORD2_M2SM (15U) /!< Bit position for MPU_RGDn_WORD2_M2SM. /
Kojto	90:cb3d968589d8	791	#define BM_MPU_RGDn_WORD2_M2SM (0x00018000U) /!< Bit mask for MPU_RGDn_WORD2_M2SM. /
Kojto	90:cb3d968589d8	792	#define BS_MPU_RGDn_WORD2_M2SM (2U) /!< Bit field size in bits for MPU_RGDn_WORD2_M2SM. /
Kojto	90:cb3d968589d8	793
Kojto	90:cb3d968589d8	794	/! @brief Read current value of the MPU_RGDn_WORD2_M2SM field. /
Kojto	90:cb3d968589d8	795	#define BR_MPU_RGDn_WORD2_M2SM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M2SM)
Kojto	90:cb3d968589d8	796
Kojto	90:cb3d968589d8	797	/! @brief Format value for bitfield MPU_RGDn_WORD2_M2SM. /
Kojto	90:cb3d968589d8	798	#define BF_MPU_RGDn_WORD2_M2SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M2SM) & BM_MPU_RGDn_WORD2_M2SM)
Kojto	90:cb3d968589d8	799
Kojto	90:cb3d968589d8	800	/! @brief Set the M2SM field to a new value. /
Kojto	90:cb3d968589d8	801	#define BW_MPU_RGDn_WORD2_M2SM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M2SM) \| BF_MPU_RGDn_WORD2_M2SM(v)))
Kojto	90:cb3d968589d8	802	/@}/
Kojto	90:cb3d968589d8	803
Kojto	90:cb3d968589d8	804	/*!
Kojto	90:cb3d968589d8	805	* @name Register MPU_RGDn_WORD2, field M2PE[17] (RW)
Kojto	90:cb3d968589d8	806	*
Kojto	90:cb3d968589d8	807	* See M3PE description.
Kojto	90:cb3d968589d8	808	*/
Kojto	90:cb3d968589d8	809	/@{/
Kojto	90:cb3d968589d8	810	#define BP_MPU_RGDn_WORD2_M2PE (17U) /!< Bit position for MPU_RGDn_WORD2_M2PE. /
Kojto	90:cb3d968589d8	811	#define BM_MPU_RGDn_WORD2_M2PE (0x00020000U) /!< Bit mask for MPU_RGDn_WORD2_M2PE. /
Kojto	90:cb3d968589d8	812	#define BS_MPU_RGDn_WORD2_M2PE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M2PE. /
Kojto	90:cb3d968589d8	813
Kojto	90:cb3d968589d8	814	/! @brief Read current value of the MPU_RGDn_WORD2_M2PE field. /
Kojto	90:cb3d968589d8	815	#define BR_MPU_RGDn_WORD2_M2PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M2PE))
Kojto	90:cb3d968589d8	816
Kojto	90:cb3d968589d8	817	/! @brief Format value for bitfield MPU_RGDn_WORD2_M2PE. /
Kojto	90:cb3d968589d8	818	#define BF_MPU_RGDn_WORD2_M2PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M2PE) & BM_MPU_RGDn_WORD2_M2PE)
Kojto	90:cb3d968589d8	819
Kojto	90:cb3d968589d8	820	/! @brief Set the M2PE field to a new value. /
Kojto	90:cb3d968589d8	821	#define BW_MPU_RGDn_WORD2_M2PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M2PE) = (v))
Kojto	90:cb3d968589d8	822	/@}/
Kojto	90:cb3d968589d8	823
Kojto	90:cb3d968589d8	824	/*!
Kojto	90:cb3d968589d8	825	* @name Register MPU_RGDn_WORD2, field M3UM[20:18] (RW)
Kojto	90:cb3d968589d8	826	*
Kojto	90:cb3d968589d8	827	* Defines the access controls for bus master 3 in User mode. M3UM consists of
Kojto	90:cb3d968589d8	828	* three independent bits, enabling read (r), write (w), and execute (x)
Kojto	90:cb3d968589d8	829	* permissions.
Kojto	90:cb3d968589d8	830	*
Kojto	90:cb3d968589d8	831	* Values:
Kojto	90:cb3d968589d8	832	* - 0 - An attempted access of that mode may be terminated with an access error
Kojto	90:cb3d968589d8	833	* (if not allowed by another descriptor) and the access not performed.
Kojto	90:cb3d968589d8	834	* - 1 - Allows the given access type to occur
Kojto	90:cb3d968589d8	835	*/
Kojto	90:cb3d968589d8	836	/@{/
Kojto	90:cb3d968589d8	837	#define BP_MPU_RGDn_WORD2_M3UM (18U) /!< Bit position for MPU_RGDn_WORD2_M3UM. /
Kojto	90:cb3d968589d8	838	#define BM_MPU_RGDn_WORD2_M3UM (0x001C0000U) /!< Bit mask for MPU_RGDn_WORD2_M3UM. /
Kojto	90:cb3d968589d8	839	#define BS_MPU_RGDn_WORD2_M3UM (3U) /!< Bit field size in bits for MPU_RGDn_WORD2_M3UM. /
Kojto	90:cb3d968589d8	840
Kojto	90:cb3d968589d8	841	/! @brief Read current value of the MPU_RGDn_WORD2_M3UM field. /
Kojto	90:cb3d968589d8	842	#define BR_MPU_RGDn_WORD2_M3UM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M3UM)
Kojto	90:cb3d968589d8	843
Kojto	90:cb3d968589d8	844	/! @brief Format value for bitfield MPU_RGDn_WORD2_M3UM. /
Kojto	90:cb3d968589d8	845	#define BF_MPU_RGDn_WORD2_M3UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M3UM) & BM_MPU_RGDn_WORD2_M3UM)
Kojto	90:cb3d968589d8	846
Kojto	90:cb3d968589d8	847	/! @brief Set the M3UM field to a new value. /
Kojto	90:cb3d968589d8	848	#define BW_MPU_RGDn_WORD2_M3UM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M3UM) \| BF_MPU_RGDn_WORD2_M3UM(v)))
Kojto	90:cb3d968589d8	849	/@}/
Kojto	90:cb3d968589d8	850
Kojto	90:cb3d968589d8	851	/*!
Kojto	90:cb3d968589d8	852	* @name Register MPU_RGDn_WORD2, field M3SM[22:21] (RW)
Kojto	90:cb3d968589d8	853	*
Kojto	90:cb3d968589d8	854	* Defines the access controls for bus master 3 in Supervisor mode.
Kojto	90:cb3d968589d8	855	*
Kojto	90:cb3d968589d8	856	* Values:
Kojto	90:cb3d968589d8	857	* - 00 - r/w/x; read, write and execute allowed
Kojto	90:cb3d968589d8	858	* - 01 - r/x; read and execute allowed, but no write
Kojto	90:cb3d968589d8	859	* - 10 - r/w; read and write allowed, but no execute
Kojto	90:cb3d968589d8	860	* - 11 - Same as User mode defined in M3UM
Kojto	90:cb3d968589d8	861	*/
Kojto	90:cb3d968589d8	862	/@{/
Kojto	90:cb3d968589d8	863	#define BP_MPU_RGDn_WORD2_M3SM (21U) /!< Bit position for MPU_RGDn_WORD2_M3SM. /
Kojto	90:cb3d968589d8	864	#define BM_MPU_RGDn_WORD2_M3SM (0x00600000U) /!< Bit mask for MPU_RGDn_WORD2_M3SM. /
Kojto	90:cb3d968589d8	865	#define BS_MPU_RGDn_WORD2_M3SM (2U) /!< Bit field size in bits for MPU_RGDn_WORD2_M3SM. /
Kojto	90:cb3d968589d8	866
Kojto	90:cb3d968589d8	867	/! @brief Read current value of the MPU_RGDn_WORD2_M3SM field. /
Kojto	90:cb3d968589d8	868	#define BR_MPU_RGDn_WORD2_M3SM(x, n) (HW_MPU_RGDn_WORD2(x, n).B.M3SM)
Kojto	90:cb3d968589d8	869
Kojto	90:cb3d968589d8	870	/! @brief Format value for bitfield MPU_RGDn_WORD2_M3SM. /
Kojto	90:cb3d968589d8	871	#define BF_MPU_RGDn_WORD2_M3SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M3SM) & BM_MPU_RGDn_WORD2_M3SM)
Kojto	90:cb3d968589d8	872
Kojto	90:cb3d968589d8	873	/! @brief Set the M3SM field to a new value. /
Kojto	90:cb3d968589d8	874	#define BW_MPU_RGDn_WORD2_M3SM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M3SM) \| BF_MPU_RGDn_WORD2_M3SM(v)))
Kojto	90:cb3d968589d8	875	/@}/
Kojto	90:cb3d968589d8	876
Kojto	90:cb3d968589d8	877	/*!
Kojto	90:cb3d968589d8	878	* @name Register MPU_RGDn_WORD2, field M3PE[23] (RW)
Kojto	90:cb3d968589d8	879	*
Kojto	90:cb3d968589d8	880	* Values:
Kojto	90:cb3d968589d8	881	* - 0 - Do not include the process identifier in the evaluation
Kojto	90:cb3d968589d8	882	* - 1 - Include the process identifier and mask (RGDn_WORD3) in the region hit
Kojto	90:cb3d968589d8	883	* evaluation
Kojto	90:cb3d968589d8	884	*/
Kojto	90:cb3d968589d8	885	/@{/
Kojto	90:cb3d968589d8	886	#define BP_MPU_RGDn_WORD2_M3PE (23U) /!< Bit position for MPU_RGDn_WORD2_M3PE. /
Kojto	90:cb3d968589d8	887	#define BM_MPU_RGDn_WORD2_M3PE (0x00800000U) /!< Bit mask for MPU_RGDn_WORD2_M3PE. /
Kojto	90:cb3d968589d8	888	#define BS_MPU_RGDn_WORD2_M3PE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M3PE. /
Kojto	90:cb3d968589d8	889
Kojto	90:cb3d968589d8	890	/! @brief Read current value of the MPU_RGDn_WORD2_M3PE field. /
Kojto	90:cb3d968589d8	891	#define BR_MPU_RGDn_WORD2_M3PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M3PE))
Kojto	90:cb3d968589d8	892
Kojto	90:cb3d968589d8	893	/! @brief Format value for bitfield MPU_RGDn_WORD2_M3PE. /
Kojto	90:cb3d968589d8	894	#define BF_MPU_RGDn_WORD2_M3PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M3PE) & BM_MPU_RGDn_WORD2_M3PE)
Kojto	90:cb3d968589d8	895
Kojto	90:cb3d968589d8	896	/! @brief Set the M3PE field to a new value. /
Kojto	90:cb3d968589d8	897	#define BW_MPU_RGDn_WORD2_M3PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M3PE) = (v))
Kojto	90:cb3d968589d8	898	/@}/
Kojto	90:cb3d968589d8	899
Kojto	90:cb3d968589d8	900	/*!
Kojto	90:cb3d968589d8	901	* @name Register MPU_RGDn_WORD2, field M4WE[24] (RW)
Kojto	90:cb3d968589d8	902	*
Kojto	90:cb3d968589d8	903	* Values:
Kojto	90:cb3d968589d8	904	* - 0 - Bus master 4 writes terminate with an access error and the write is not
Kojto	90:cb3d968589d8	905	* performed
Kojto	90:cb3d968589d8	906	* - 1 - Bus master 4 writes allowed
Kojto	90:cb3d968589d8	907	*/
Kojto	90:cb3d968589d8	908	/@{/
Kojto	90:cb3d968589d8	909	#define BP_MPU_RGDn_WORD2_M4WE (24U) /!< Bit position for MPU_RGDn_WORD2_M4WE. /
Kojto	90:cb3d968589d8	910	#define BM_MPU_RGDn_WORD2_M4WE (0x01000000U) /!< Bit mask for MPU_RGDn_WORD2_M4WE. /
Kojto	90:cb3d968589d8	911	#define BS_MPU_RGDn_WORD2_M4WE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M4WE. /
Kojto	90:cb3d968589d8	912
Kojto	90:cb3d968589d8	913	/! @brief Read current value of the MPU_RGDn_WORD2_M4WE field. /
Kojto	90:cb3d968589d8	914	#define BR_MPU_RGDn_WORD2_M4WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M4WE))
Kojto	90:cb3d968589d8	915
Kojto	90:cb3d968589d8	916	/! @brief Format value for bitfield MPU_RGDn_WORD2_M4WE. /
Kojto	90:cb3d968589d8	917	#define BF_MPU_RGDn_WORD2_M4WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M4WE) & BM_MPU_RGDn_WORD2_M4WE)
Kojto	90:cb3d968589d8	918
Kojto	90:cb3d968589d8	919	/! @brief Set the M4WE field to a new value. /
Kojto	90:cb3d968589d8	920	#define BW_MPU_RGDn_WORD2_M4WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M4WE) = (v))
Kojto	90:cb3d968589d8	921	/@}/
Kojto	90:cb3d968589d8	922
Kojto	90:cb3d968589d8	923	/*!
Kojto	90:cb3d968589d8	924	* @name Register MPU_RGDn_WORD2, field M4RE[25] (RW)
Kojto	90:cb3d968589d8	925	*
Kojto	90:cb3d968589d8	926	* Values:
Kojto	90:cb3d968589d8	927	* - 0 - Bus master 4 reads terminate with an access error and the read is not
Kojto	90:cb3d968589d8	928	* performed
Kojto	90:cb3d968589d8	929	* - 1 - Bus master 4 reads allowed
Kojto	90:cb3d968589d8	930	*/
Kojto	90:cb3d968589d8	931	/@{/
Kojto	90:cb3d968589d8	932	#define BP_MPU_RGDn_WORD2_M4RE (25U) /!< Bit position for MPU_RGDn_WORD2_M4RE. /
Kojto	90:cb3d968589d8	933	#define BM_MPU_RGDn_WORD2_M4RE (0x02000000U) /!< Bit mask for MPU_RGDn_WORD2_M4RE. /
Kojto	90:cb3d968589d8	934	#define BS_MPU_RGDn_WORD2_M4RE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M4RE. /
Kojto	90:cb3d968589d8	935
Kojto	90:cb3d968589d8	936	/! @brief Read current value of the MPU_RGDn_WORD2_M4RE field. /
Kojto	90:cb3d968589d8	937	#define BR_MPU_RGDn_WORD2_M4RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M4RE))
Kojto	90:cb3d968589d8	938
Kojto	90:cb3d968589d8	939	/! @brief Format value for bitfield MPU_RGDn_WORD2_M4RE. /
Kojto	90:cb3d968589d8	940	#define BF_MPU_RGDn_WORD2_M4RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M4RE) & BM_MPU_RGDn_WORD2_M4RE)
Kojto	90:cb3d968589d8	941
Kojto	90:cb3d968589d8	942	/! @brief Set the M4RE field to a new value. /
Kojto	90:cb3d968589d8	943	#define BW_MPU_RGDn_WORD2_M4RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M4RE) = (v))
Kojto	90:cb3d968589d8	944	/@}/
Kojto	90:cb3d968589d8	945
Kojto	90:cb3d968589d8	946	/*!
Kojto	90:cb3d968589d8	947	* @name Register MPU_RGDn_WORD2, field M5WE[26] (RW)
Kojto	90:cb3d968589d8	948	*
Kojto	90:cb3d968589d8	949	* Values:
Kojto	90:cb3d968589d8	950	* - 0 - Bus master 5 writes terminate with an access error and the write is not
Kojto	90:cb3d968589d8	951	* performed
Kojto	90:cb3d968589d8	952	* - 1 - Bus master 5 writes allowed
Kojto	90:cb3d968589d8	953	*/
Kojto	90:cb3d968589d8	954	/@{/
Kojto	90:cb3d968589d8	955	#define BP_MPU_RGDn_WORD2_M5WE (26U) /!< Bit position for MPU_RGDn_WORD2_M5WE. /
Kojto	90:cb3d968589d8	956	#define BM_MPU_RGDn_WORD2_M5WE (0x04000000U) /!< Bit mask for MPU_RGDn_WORD2_M5WE. /
Kojto	90:cb3d968589d8	957	#define BS_MPU_RGDn_WORD2_M5WE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M5WE. /
Kojto	90:cb3d968589d8	958
Kojto	90:cb3d968589d8	959	/! @brief Read current value of the MPU_RGDn_WORD2_M5WE field. /
Kojto	90:cb3d968589d8	960	#define BR_MPU_RGDn_WORD2_M5WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M5WE))
Kojto	90:cb3d968589d8	961
Kojto	90:cb3d968589d8	962	/! @brief Format value for bitfield MPU_RGDn_WORD2_M5WE. /
Kojto	90:cb3d968589d8	963	#define BF_MPU_RGDn_WORD2_M5WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M5WE) & BM_MPU_RGDn_WORD2_M5WE)
Kojto	90:cb3d968589d8	964
Kojto	90:cb3d968589d8	965	/! @brief Set the M5WE field to a new value. /
Kojto	90:cb3d968589d8	966	#define BW_MPU_RGDn_WORD2_M5WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M5WE) = (v))
Kojto	90:cb3d968589d8	967	/@}/
Kojto	90:cb3d968589d8	968
Kojto	90:cb3d968589d8	969	/*!
Kojto	90:cb3d968589d8	970	* @name Register MPU_RGDn_WORD2, field M5RE[27] (RW)
Kojto	90:cb3d968589d8	971	*
Kojto	90:cb3d968589d8	972	* Values:
Kojto	90:cb3d968589d8	973	* - 0 - Bus master 5 reads terminate with an access error and the read is not
Kojto	90:cb3d968589d8	974	* performed
Kojto	90:cb3d968589d8	975	* - 1 - Bus master 5 reads allowed
Kojto	90:cb3d968589d8	976	*/
Kojto	90:cb3d968589d8	977	/@{/
Kojto	90:cb3d968589d8	978	#define BP_MPU_RGDn_WORD2_M5RE (27U) /!< Bit position for MPU_RGDn_WORD2_M5RE. /
Kojto	90:cb3d968589d8	979	#define BM_MPU_RGDn_WORD2_M5RE (0x08000000U) /!< Bit mask for MPU_RGDn_WORD2_M5RE. /
Kojto	90:cb3d968589d8	980	#define BS_MPU_RGDn_WORD2_M5RE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M5RE. /
Kojto	90:cb3d968589d8	981
Kojto	90:cb3d968589d8	982	/! @brief Read current value of the MPU_RGDn_WORD2_M5RE field. /
Kojto	90:cb3d968589d8	983	#define BR_MPU_RGDn_WORD2_M5RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M5RE))
Kojto	90:cb3d968589d8	984
Kojto	90:cb3d968589d8	985	/! @brief Format value for bitfield MPU_RGDn_WORD2_M5RE. /
Kojto	90:cb3d968589d8	986	#define BF_MPU_RGDn_WORD2_M5RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M5RE) & BM_MPU_RGDn_WORD2_M5RE)
Kojto	90:cb3d968589d8	987
Kojto	90:cb3d968589d8	988	/! @brief Set the M5RE field to a new value. /
Kojto	90:cb3d968589d8	989	#define BW_MPU_RGDn_WORD2_M5RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M5RE) = (v))
Kojto	90:cb3d968589d8	990	/@}/
Kojto	90:cb3d968589d8	991
Kojto	90:cb3d968589d8	992	/*!
Kojto	90:cb3d968589d8	993	* @name Register MPU_RGDn_WORD2, field M6WE[28] (RW)
Kojto	90:cb3d968589d8	994	*
Kojto	90:cb3d968589d8	995	* Values:
Kojto	90:cb3d968589d8	996	* - 0 - Bus master 6 writes terminate with an access error and the write is not
Kojto	90:cb3d968589d8	997	* performed
Kojto	90:cb3d968589d8	998	* - 1 - Bus master 6 writes allowed
Kojto	90:cb3d968589d8	999	*/
Kojto	90:cb3d968589d8	1000	/@{/
Kojto	90:cb3d968589d8	1001	#define BP_MPU_RGDn_WORD2_M6WE (28U) /!< Bit position for MPU_RGDn_WORD2_M6WE. /
Kojto	90:cb3d968589d8	1002	#define BM_MPU_RGDn_WORD2_M6WE (0x10000000U) /!< Bit mask for MPU_RGDn_WORD2_M6WE. /
Kojto	90:cb3d968589d8	1003	#define BS_MPU_RGDn_WORD2_M6WE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M6WE. /
Kojto	90:cb3d968589d8	1004
Kojto	90:cb3d968589d8	1005	/! @brief Read current value of the MPU_RGDn_WORD2_M6WE field. /
Kojto	90:cb3d968589d8	1006	#define BR_MPU_RGDn_WORD2_M6WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M6WE))
Kojto	90:cb3d968589d8	1007
Kojto	90:cb3d968589d8	1008	/! @brief Format value for bitfield MPU_RGDn_WORD2_M6WE. /
Kojto	90:cb3d968589d8	1009	#define BF_MPU_RGDn_WORD2_M6WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M6WE) & BM_MPU_RGDn_WORD2_M6WE)
Kojto	90:cb3d968589d8	1010
Kojto	90:cb3d968589d8	1011	/! @brief Set the M6WE field to a new value. /
Kojto	90:cb3d968589d8	1012	#define BW_MPU_RGDn_WORD2_M6WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M6WE) = (v))
Kojto	90:cb3d968589d8	1013	/@}/
Kojto	90:cb3d968589d8	1014
Kojto	90:cb3d968589d8	1015	/*!
Kojto	90:cb3d968589d8	1016	* @name Register MPU_RGDn_WORD2, field M6RE[29] (RW)
Kojto	90:cb3d968589d8	1017	*
Kojto	90:cb3d968589d8	1018	* Values:
Kojto	90:cb3d968589d8	1019	* - 0 - Bus master 6 reads terminate with an access error and the read is not
Kojto	90:cb3d968589d8	1020	* performed
Kojto	90:cb3d968589d8	1021	* - 1 - Bus master 6 reads allowed
Kojto	90:cb3d968589d8	1022	*/
Kojto	90:cb3d968589d8	1023	/@{/
Kojto	90:cb3d968589d8	1024	#define BP_MPU_RGDn_WORD2_M6RE (29U) /!< Bit position for MPU_RGDn_WORD2_M6RE. /
Kojto	90:cb3d968589d8	1025	#define BM_MPU_RGDn_WORD2_M6RE (0x20000000U) /!< Bit mask for MPU_RGDn_WORD2_M6RE. /
Kojto	90:cb3d968589d8	1026	#define BS_MPU_RGDn_WORD2_M6RE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M6RE. /
Kojto	90:cb3d968589d8	1027
Kojto	90:cb3d968589d8	1028	/! @brief Read current value of the MPU_RGDn_WORD2_M6RE field. /
Kojto	90:cb3d968589d8	1029	#define BR_MPU_RGDn_WORD2_M6RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M6RE))
Kojto	90:cb3d968589d8	1030
Kojto	90:cb3d968589d8	1031	/! @brief Format value for bitfield MPU_RGDn_WORD2_M6RE. /
Kojto	90:cb3d968589d8	1032	#define BF_MPU_RGDn_WORD2_M6RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M6RE) & BM_MPU_RGDn_WORD2_M6RE)
Kojto	90:cb3d968589d8	1033
Kojto	90:cb3d968589d8	1034	/! @brief Set the M6RE field to a new value. /
Kojto	90:cb3d968589d8	1035	#define BW_MPU_RGDn_WORD2_M6RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M6RE) = (v))
Kojto	90:cb3d968589d8	1036	/@}/
Kojto	90:cb3d968589d8	1037
Kojto	90:cb3d968589d8	1038	/*!
Kojto	90:cb3d968589d8	1039	* @name Register MPU_RGDn_WORD2, field M7WE[30] (RW)
Kojto	90:cb3d968589d8	1040	*
Kojto	90:cb3d968589d8	1041	* Values:
Kojto	90:cb3d968589d8	1042	* - 0 - Bus master 7 writes terminate with an access error and the write is not
Kojto	90:cb3d968589d8	1043	* performed
Kojto	90:cb3d968589d8	1044	* - 1 - Bus master 7 writes allowed
Kojto	90:cb3d968589d8	1045	*/
Kojto	90:cb3d968589d8	1046	/@{/
Kojto	90:cb3d968589d8	1047	#define BP_MPU_RGDn_WORD2_M7WE (30U) /!< Bit position for MPU_RGDn_WORD2_M7WE. /
Kojto	90:cb3d968589d8	1048	#define BM_MPU_RGDn_WORD2_M7WE (0x40000000U) /!< Bit mask for MPU_RGDn_WORD2_M7WE. /
Kojto	90:cb3d968589d8	1049	#define BS_MPU_RGDn_WORD2_M7WE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M7WE. /
Kojto	90:cb3d968589d8	1050
Kojto	90:cb3d968589d8	1051	/! @brief Read current value of the MPU_RGDn_WORD2_M7WE field. /
Kojto	90:cb3d968589d8	1052	#define BR_MPU_RGDn_WORD2_M7WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M7WE))
Kojto	90:cb3d968589d8	1053
Kojto	90:cb3d968589d8	1054	/! @brief Format value for bitfield MPU_RGDn_WORD2_M7WE. /
Kojto	90:cb3d968589d8	1055	#define BF_MPU_RGDn_WORD2_M7WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M7WE) & BM_MPU_RGDn_WORD2_M7WE)
Kojto	90:cb3d968589d8	1056
Kojto	90:cb3d968589d8	1057	/! @brief Set the M7WE field to a new value. /
Kojto	90:cb3d968589d8	1058	#define BW_MPU_RGDn_WORD2_M7WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M7WE) = (v))
Kojto	90:cb3d968589d8	1059	/@}/
Kojto	90:cb3d968589d8	1060
Kojto	90:cb3d968589d8	1061	/*!
Kojto	90:cb3d968589d8	1062	* @name Register MPU_RGDn_WORD2, field M7RE[31] (RW)
Kojto	90:cb3d968589d8	1063	*
Kojto	90:cb3d968589d8	1064	* Values:
Kojto	90:cb3d968589d8	1065	* - 0 - Bus master 7 reads terminate with an access error and the read is not
Kojto	90:cb3d968589d8	1066	* performed
Kojto	90:cb3d968589d8	1067	* - 1 - Bus master 7 reads allowed
Kojto	90:cb3d968589d8	1068	*/
Kojto	90:cb3d968589d8	1069	/@{/
Kojto	90:cb3d968589d8	1070	#define BP_MPU_RGDn_WORD2_M7RE (31U) /!< Bit position for MPU_RGDn_WORD2_M7RE. /
Kojto	90:cb3d968589d8	1071	#define BM_MPU_RGDn_WORD2_M7RE (0x80000000U) /!< Bit mask for MPU_RGDn_WORD2_M7RE. /
Kojto	90:cb3d968589d8	1072	#define BS_MPU_RGDn_WORD2_M7RE (1U) /!< Bit field size in bits for MPU_RGDn_WORD2_M7RE. /
Kojto	90:cb3d968589d8	1073
Kojto	90:cb3d968589d8	1074	/! @brief Read current value of the MPU_RGDn_WORD2_M7RE field. /
Kojto	90:cb3d968589d8	1075	#define BR_MPU_RGDn_WORD2_M7RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M7RE))
Kojto	90:cb3d968589d8	1076
Kojto	90:cb3d968589d8	1077	/! @brief Format value for bitfield MPU_RGDn_WORD2_M7RE. /
Kojto	90:cb3d968589d8	1078	#define BF_MPU_RGDn_WORD2_M7RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M7RE) & BM_MPU_RGDn_WORD2_M7RE)
Kojto	90:cb3d968589d8	1079
Kojto	90:cb3d968589d8	1080	/! @brief Set the M7RE field to a new value. /
Kojto	90:cb3d968589d8	1081	#define BW_MPU_RGDn_WORD2_M7RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M7RE) = (v))
Kojto	90:cb3d968589d8	1082	/@}/
Kojto	90:cb3d968589d8	1083	/*******************************************************************************
Kojto	90:cb3d968589d8	1084	* HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3
Kojto	90:cb3d968589d8	1085	******************************************************************************/
Kojto	90:cb3d968589d8	1086
Kojto	90:cb3d968589d8	1087	/*!
Kojto	90:cb3d968589d8	1088	* @brief HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3 (RW)
Kojto	90:cb3d968589d8	1089	*
Kojto	90:cb3d968589d8	1090	* Reset value: 0x00000001U
Kojto	90:cb3d968589d8	1091	*
Kojto	90:cb3d968589d8	1092	* The fourth word of the region descriptor contains the optional process
Kojto	90:cb3d968589d8	1093	* identifier and mask, plus the region descriptor's valid bit.
Kojto	90:cb3d968589d8	1094	*/
Kojto	90:cb3d968589d8	1095	typedef union _hw_mpu_rgdn_word3
Kojto	90:cb3d968589d8	1096	{
Kojto	90:cb3d968589d8	1097	uint32_t U;
Kojto	90:cb3d968589d8	1098	struct _hw_mpu_rgdn_word3_bitfields
Kojto	90:cb3d968589d8	1099	{
Kojto	90:cb3d968589d8	1100	uint32_t VLD : 1; /!< [0] Valid /
Kojto	90:cb3d968589d8	1101	uint32_t RESERVED0 : 15; /!< [15:1] /
Kojto	90:cb3d968589d8	1102	uint32_t PIDMASK : 8; /!< [23:16] Process Identifier Mask /
Kojto	90:cb3d968589d8	1103	uint32_t PID : 8; /!< [31:24] Process Identifier /
Kojto	90:cb3d968589d8	1104	} B;
Kojto	90:cb3d968589d8	1105	} hw_mpu_rgdn_word3_t;
Kojto	90:cb3d968589d8	1106
Kojto	90:cb3d968589d8	1107	/*!
Kojto	90:cb3d968589d8	1108	* @name Constants and macros for entire MPU_RGDn_WORD3 register
Kojto	90:cb3d968589d8	1109	*/
Kojto	90:cb3d968589d8	1110	/@{/
Kojto	90:cb3d968589d8	1111	#define HW_MPU_RGDn_WORD3_COUNT (12U)
Kojto	90:cb3d968589d8	1112
Kojto	90:cb3d968589d8	1113	#define HW_MPU_RGDn_WORD3_ADDR(x, n) ((x) + 0x40CU + (0x10U * (n)))
Kojto	90:cb3d968589d8	1114
Kojto	90:cb3d968589d8	1115	#define HW_MPU_RGDn_WORD3(x, n) ((__IO hw_mpu_rgdn_word3_t ) HW_MPU_RGDn_WORD3_ADDR(x, n))
Kojto	90:cb3d968589d8	1116	#define HW_MPU_RGDn_WORD3_RD(x, n) (HW_MPU_RGDn_WORD3(x, n).U)
Kojto	90:cb3d968589d8	1117	#define HW_MPU_RGDn_WORD3_WR(x, n, v) (HW_MPU_RGDn_WORD3(x, n).U = (v))
Kojto	90:cb3d968589d8	1118	#define HW_MPU_RGDn_WORD3_SET(x, n, v) (HW_MPU_RGDn_WORD3_WR(x, n, HW_MPU_RGDn_WORD3_RD(x, n) \| (v)))
Kojto	90:cb3d968589d8	1119	#define HW_MPU_RGDn_WORD3_CLR(x, n, v) (HW_MPU_RGDn_WORD3_WR(x, n, HW_MPU_RGDn_WORD3_RD(x, n) & ~(v)))
Kojto	90:cb3d968589d8	1120	#define HW_MPU_RGDn_WORD3_TOG(x, n, v) (HW_MPU_RGDn_WORD3_WR(x, n, HW_MPU_RGDn_WORD3_RD(x, n) ^ (v)))
Kojto	90:cb3d968589d8	1121	/@}/
Kojto	90:cb3d968589d8	1122
Kojto	90:cb3d968589d8	1123	/*
Kojto	90:cb3d968589d8	1124	* Constants & macros for individual MPU_RGDn_WORD3 bitfields
Kojto	90:cb3d968589d8	1125	*/
Kojto	90:cb3d968589d8	1126
Kojto	90:cb3d968589d8	1127	/*!
Kojto	90:cb3d968589d8	1128	* @name Register MPU_RGDn_WORD3, field VLD[0] (RW)
Kojto	90:cb3d968589d8	1129	*
Kojto	90:cb3d968589d8	1130	* Signals the region descriptor is valid. Any write to RGDn_WORD0-2 clears this
Kojto	90:cb3d968589d8	1131	* bit.
Kojto	90:cb3d968589d8	1132	*
Kojto	90:cb3d968589d8	1133	* Values:
Kojto	90:cb3d968589d8	1134	* - 0 - Region descriptor is invalid
Kojto	90:cb3d968589d8	1135	* - 1 - Region descriptor is valid
Kojto	90:cb3d968589d8	1136	*/
Kojto	90:cb3d968589d8	1137	/@{/
Kojto	90:cb3d968589d8	1138	#define BP_MPU_RGDn_WORD3_VLD (0U) /!< Bit position for MPU_RGDn_WORD3_VLD. /
Kojto	90:cb3d968589d8	1139	#define BM_MPU_RGDn_WORD3_VLD (0x00000001U) /!< Bit mask for MPU_RGDn_WORD3_VLD. /
Kojto	90:cb3d968589d8	1140	#define BS_MPU_RGDn_WORD3_VLD (1U) /!< Bit field size in bits for MPU_RGDn_WORD3_VLD. /
Kojto	90:cb3d968589d8	1141
Kojto	90:cb3d968589d8	1142	/! @brief Read current value of the MPU_RGDn_WORD3_VLD field. /
Kojto	90:cb3d968589d8	1143	#define BR_MPU_RGDn_WORD3_VLD(x, n) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD3_ADDR(x, n), BP_MPU_RGDn_WORD3_VLD))
Kojto	90:cb3d968589d8	1144
Kojto	90:cb3d968589d8	1145	/! @brief Format value for bitfield MPU_RGDn_WORD3_VLD. /
Kojto	90:cb3d968589d8	1146	#define BF_MPU_RGDn_WORD3_VLD(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD3_VLD) & BM_MPU_RGDn_WORD3_VLD)
Kojto	90:cb3d968589d8	1147
Kojto	90:cb3d968589d8	1148	/! @brief Set the VLD field to a new value. /
Kojto	90:cb3d968589d8	1149	#define BW_MPU_RGDn_WORD3_VLD(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDn_WORD3_ADDR(x, n), BP_MPU_RGDn_WORD3_VLD) = (v))
Kojto	90:cb3d968589d8	1150	/@}/
Kojto	90:cb3d968589d8	1151
Kojto	90:cb3d968589d8	1152	/*!
Kojto	90:cb3d968589d8	1153	* @name Register MPU_RGDn_WORD3, field PIDMASK[23:16] (RW)
Kojto	90:cb3d968589d8	1154	*
Kojto	90:cb3d968589d8	1155	* Provides a masking capability so that multiple process identifiers can be
Kojto	90:cb3d968589d8	1156	* included as part of the region hit determination. If a bit in PIDMASK is set,
Kojto	90:cb3d968589d8	1157	* then the corresponding PID bit is ignored in the comparison. This field and PID
Kojto	90:cb3d968589d8	1158	* are included in the region hit determination if RGDn_WORD2[MxPE] is set. For
Kojto	90:cb3d968589d8	1159	* more information on the handling of the PID and PIDMASK, see "Access Evaluation
Kojto	90:cb3d968589d8	1160	* - Hit Determination."
Kojto	90:cb3d968589d8	1161	*/
Kojto	90:cb3d968589d8	1162	/@{/
Kojto	90:cb3d968589d8	1163	#define BP_MPU_RGDn_WORD3_PIDMASK (16U) /!< Bit position for MPU_RGDn_WORD3_PIDMASK. /
Kojto	90:cb3d968589d8	1164	#define BM_MPU_RGDn_WORD3_PIDMASK (0x00FF0000U) /!< Bit mask for MPU_RGDn_WORD3_PIDMASK. /
Kojto	90:cb3d968589d8	1165	#define BS_MPU_RGDn_WORD3_PIDMASK (8U) /!< Bit field size in bits for MPU_RGDn_WORD3_PIDMASK. /
Kojto	90:cb3d968589d8	1166
Kojto	90:cb3d968589d8	1167	/! @brief Read current value of the MPU_RGDn_WORD3_PIDMASK field. /
Kojto	90:cb3d968589d8	1168	#define BR_MPU_RGDn_WORD3_PIDMASK(x, n) (HW_MPU_RGDn_WORD3(x, n).B.PIDMASK)
Kojto	90:cb3d968589d8	1169
Kojto	90:cb3d968589d8	1170	/! @brief Format value for bitfield MPU_RGDn_WORD3_PIDMASK. /
Kojto	90:cb3d968589d8	1171	#define BF_MPU_RGDn_WORD3_PIDMASK(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD3_PIDMASK) & BM_MPU_RGDn_WORD3_PIDMASK)
Kojto	90:cb3d968589d8	1172
Kojto	90:cb3d968589d8	1173	/! @brief Set the PIDMASK field to a new value. /
Kojto	90:cb3d968589d8	1174	#define BW_MPU_RGDn_WORD3_PIDMASK(x, n, v) (HW_MPU_RGDn_WORD3_WR(x, n, (HW_MPU_RGDn_WORD3_RD(x, n) & ~BM_MPU_RGDn_WORD3_PIDMASK) \| BF_MPU_RGDn_WORD3_PIDMASK(v)))
Kojto	90:cb3d968589d8	1175	/@}/
Kojto	90:cb3d968589d8	1176
Kojto	90:cb3d968589d8	1177	/*!
Kojto	90:cb3d968589d8	1178	* @name Register MPU_RGDn_WORD3, field PID[31:24] (RW)
Kojto	90:cb3d968589d8	1179	*
Kojto	90:cb3d968589d8	1180	* Specifies the process identifier that is included in the region hit
Kojto	90:cb3d968589d8	1181	* determination if RGDn_WORD2[MxPE] is set. PIDMASK can mask individual bits in this
Kojto	90:cb3d968589d8	1182	* field.
Kojto	90:cb3d968589d8	1183	*/
Kojto	90:cb3d968589d8	1184	/@{/
Kojto	90:cb3d968589d8	1185	#define BP_MPU_RGDn_WORD3_PID (24U) /!< Bit position for MPU_RGDn_WORD3_PID. /
Kojto	90:cb3d968589d8	1186	#define BM_MPU_RGDn_WORD3_PID (0xFF000000U) /!< Bit mask for MPU_RGDn_WORD3_PID. /
Kojto	90:cb3d968589d8	1187	#define BS_MPU_RGDn_WORD3_PID (8U) /!< Bit field size in bits for MPU_RGDn_WORD3_PID. /
Kojto	90:cb3d968589d8	1188
Kojto	90:cb3d968589d8	1189	/! @brief Read current value of the MPU_RGDn_WORD3_PID field. /
Kojto	90:cb3d968589d8	1190	#define BR_MPU_RGDn_WORD3_PID(x, n) (HW_MPU_RGDn_WORD3(x, n).B.PID)
Kojto	90:cb3d968589d8	1191
Kojto	90:cb3d968589d8	1192	/! @brief Format value for bitfield MPU_RGDn_WORD3_PID. /
Kojto	90:cb3d968589d8	1193	#define BF_MPU_RGDn_WORD3_PID(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD3_PID) & BM_MPU_RGDn_WORD3_PID)
Kojto	90:cb3d968589d8	1194
Kojto	90:cb3d968589d8	1195	/! @brief Set the PID field to a new value. /
Kojto	90:cb3d968589d8	1196	#define BW_MPU_RGDn_WORD3_PID(x, n, v) (HW_MPU_RGDn_WORD3_WR(x, n, (HW_MPU_RGDn_WORD3_RD(x, n) & ~BM_MPU_RGDn_WORD3_PID) \| BF_MPU_RGDn_WORD3_PID(v)))
Kojto	90:cb3d968589d8	1197	/@}/
Kojto	90:cb3d968589d8	1198
Kojto	90:cb3d968589d8	1199	/*******************************************************************************
Kojto	90:cb3d968589d8	1200	* HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n
Kojto	90:cb3d968589d8	1201	******************************************************************************/
Kojto	90:cb3d968589d8	1202
Kojto	90:cb3d968589d8	1203	/*!
Kojto	90:cb3d968589d8	1204	* @brief HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n (RW)
Kojto	90:cb3d968589d8	1205	*
Kojto	90:cb3d968589d8	1206	* Reset value: 0x0061F7DFU
Kojto	90:cb3d968589d8	1207	*
Kojto	90:cb3d968589d8	1208	* Because software may adjust only the access controls within a region
Kojto	90:cb3d968589d8	1209	* descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of
Kojto	90:cb3d968589d8	1210	* this 32-bit entity is available. Writing to this register does not affect the
Kojto	90:cb3d968589d8	1211	* descriptor's valid bit.
Kojto	90:cb3d968589d8	1212	*/
Kojto	90:cb3d968589d8	1213	typedef union _hw_mpu_rgdaacn
Kojto	90:cb3d968589d8	1214	{
Kojto	90:cb3d968589d8	1215	uint32_t U;
Kojto	90:cb3d968589d8	1216	struct _hw_mpu_rgdaacn_bitfields
Kojto	90:cb3d968589d8	1217	{
Kojto	90:cb3d968589d8	1218	uint32_t M0UM : 3; /!< [2:0] Bus Master 0 User Mode Access Control /
Kojto	90:cb3d968589d8	1219	uint32_t M0SM : 2; /*!< [4:3] Bus Master 0 Supervisor Mode Access
Kojto	90:cb3d968589d8	1220	* Control */
Kojto	90:cb3d968589d8	1221	uint32_t M0PE : 1; /!< [5] Bus Master 0 Process Identifier Enable /
Kojto	90:cb3d968589d8	1222	uint32_t M1UM : 3; /!< [8:6] Bus Master 1 User Mode Access Control /
Kojto	90:cb3d968589d8	1223	uint32_t M1SM : 2; /*!< [10:9] Bus Master 1 Supervisor Mode Access
Kojto	90:cb3d968589d8	1224	* Control */
Kojto	90:cb3d968589d8	1225	uint32_t M1PE : 1; /!< [11] Bus Master 1 Process Identifier Enable /
Kojto	90:cb3d968589d8	1226	uint32_t M2UM : 3; /*!< [14:12] Bus Master 2 User Mode Access Control
Kojto	90:cb3d968589d8	1227	* */
Kojto	90:cb3d968589d8	1228	uint32_t M2SM : 2; /*!< [16:15] Bus Master 2 Supervisor Mode Access
Kojto	90:cb3d968589d8	1229	* Control */
Kojto	90:cb3d968589d8	1230	uint32_t M2PE : 1; /!< [17] Bus Master 2 Process Identifier Enable /
Kojto	90:cb3d968589d8	1231	uint32_t M3UM : 3; /*!< [20:18] Bus Master 3 User Mode Access Control
Kojto	90:cb3d968589d8	1232	* */
Kojto	90:cb3d968589d8	1233	uint32_t M3SM : 2; /*!< [22:21] Bus Master 3 Supervisor Mode Access
Kojto	90:cb3d968589d8	1234	* Control */
Kojto	90:cb3d968589d8	1235	uint32_t M3PE : 1; /!< [23] Bus Master 3 Process Identifier Enable /
Kojto	90:cb3d968589d8	1236	uint32_t M4WE : 1; /!< [24] Bus Master 4 Write Enable /
Kojto	90:cb3d968589d8	1237	uint32_t M4RE : 1; /!< [25] Bus Master 4 Read Enable /
Kojto	90:cb3d968589d8	1238	uint32_t M5WE : 1; /!< [26] Bus Master 5 Write Enable /
Kojto	90:cb3d968589d8	1239	uint32_t M5RE : 1; /!< [27] Bus Master 5 Read Enable /
Kojto	90:cb3d968589d8	1240	uint32_t M6WE : 1; /!< [28] Bus Master 6 Write Enable /
Kojto	90:cb3d968589d8	1241	uint32_t M6RE : 1; /!< [29] Bus Master 6 Read Enable /
Kojto	90:cb3d968589d8	1242	uint32_t M7WE : 1; /!< [30] Bus Master 7 Write Enable /
Kojto	90:cb3d968589d8	1243	uint32_t M7RE : 1; /!< [31] Bus Master 7 Read Enable /
Kojto	90:cb3d968589d8	1244	} B;
Kojto	90:cb3d968589d8	1245	} hw_mpu_rgdaacn_t;
Kojto	90:cb3d968589d8	1246
Kojto	90:cb3d968589d8	1247	/*!
Kojto	90:cb3d968589d8	1248	* @name Constants and macros for entire MPU_RGDAACn register
Kojto	90:cb3d968589d8	1249	*/
Kojto	90:cb3d968589d8	1250	/@{/
Kojto	90:cb3d968589d8	1251	#define HW_MPU_RGDAACn_COUNT (12U)
Kojto	90:cb3d968589d8	1252
Kojto	90:cb3d968589d8	1253	#define HW_MPU_RGDAACn_ADDR(x, n) ((x) + 0x800U + (0x4U * (n)))
Kojto	90:cb3d968589d8	1254
Kojto	90:cb3d968589d8	1255	#define HW_MPU_RGDAACn(x, n) ((__IO hw_mpu_rgdaacn_t ) HW_MPU_RGDAACn_ADDR(x, n))
Kojto	90:cb3d968589d8	1256	#define HW_MPU_RGDAACn_RD(x, n) (HW_MPU_RGDAACn(x, n).U)
Kojto	90:cb3d968589d8	1257	#define HW_MPU_RGDAACn_WR(x, n, v) (HW_MPU_RGDAACn(x, n).U = (v))
Kojto	90:cb3d968589d8	1258	#define HW_MPU_RGDAACn_SET(x, n, v) (HW_MPU_RGDAACn_WR(x, n, HW_MPU_RGDAACn_RD(x, n) \| (v)))
Kojto	90:cb3d968589d8	1259	#define HW_MPU_RGDAACn_CLR(x, n, v) (HW_MPU_RGDAACn_WR(x, n, HW_MPU_RGDAACn_RD(x, n) & ~(v)))
Kojto	90:cb3d968589d8	1260	#define HW_MPU_RGDAACn_TOG(x, n, v) (HW_MPU_RGDAACn_WR(x, n, HW_MPU_RGDAACn_RD(x, n) ^ (v)))
Kojto	90:cb3d968589d8	1261	/@}/
Kojto	90:cb3d968589d8	1262
Kojto	90:cb3d968589d8	1263	/*
Kojto	90:cb3d968589d8	1264	* Constants & macros for individual MPU_RGDAACn bitfields
Kojto	90:cb3d968589d8	1265	*/
Kojto	90:cb3d968589d8	1266
Kojto	90:cb3d968589d8	1267	/*!
Kojto	90:cb3d968589d8	1268	* @name Register MPU_RGDAACn, field M0UM[2:0] (RW)
Kojto	90:cb3d968589d8	1269	*
Kojto	90:cb3d968589d8	1270	* See M3UM description.
Kojto	90:cb3d968589d8	1271	*/
Kojto	90:cb3d968589d8	1272	/@{/
Kojto	90:cb3d968589d8	1273	#define BP_MPU_RGDAACn_M0UM (0U) /!< Bit position for MPU_RGDAACn_M0UM. /
Kojto	90:cb3d968589d8	1274	#define BM_MPU_RGDAACn_M0UM (0x00000007U) /!< Bit mask for MPU_RGDAACn_M0UM. /
Kojto	90:cb3d968589d8	1275	#define BS_MPU_RGDAACn_M0UM (3U) /!< Bit field size in bits for MPU_RGDAACn_M0UM. /
Kojto	90:cb3d968589d8	1276
Kojto	90:cb3d968589d8	1277	/! @brief Read current value of the MPU_RGDAACn_M0UM field. /
Kojto	90:cb3d968589d8	1278	#define BR_MPU_RGDAACn_M0UM(x, n) (HW_MPU_RGDAACn(x, n).B.M0UM)
Kojto	90:cb3d968589d8	1279
Kojto	90:cb3d968589d8	1280	/! @brief Format value for bitfield MPU_RGDAACn_M0UM. /
Kojto	90:cb3d968589d8	1281	#define BF_MPU_RGDAACn_M0UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M0UM) & BM_MPU_RGDAACn_M0UM)
Kojto	90:cb3d968589d8	1282
Kojto	90:cb3d968589d8	1283	/! @brief Set the M0UM field to a new value. /
Kojto	90:cb3d968589d8	1284	#define BW_MPU_RGDAACn_M0UM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M0UM) \| BF_MPU_RGDAACn_M0UM(v)))
Kojto	90:cb3d968589d8	1285	/@}/
Kojto	90:cb3d968589d8	1286
Kojto	90:cb3d968589d8	1287	/*!
Kojto	90:cb3d968589d8	1288	* @name Register MPU_RGDAACn, field M0SM[4:3] (RW)
Kojto	90:cb3d968589d8	1289	*
Kojto	90:cb3d968589d8	1290	* See M3SM description.
Kojto	90:cb3d968589d8	1291	*/
Kojto	90:cb3d968589d8	1292	/@{/
Kojto	90:cb3d968589d8	1293	#define BP_MPU_RGDAACn_M0SM (3U) /!< Bit position for MPU_RGDAACn_M0SM. /
Kojto	90:cb3d968589d8	1294	#define BM_MPU_RGDAACn_M0SM (0x00000018U) /!< Bit mask for MPU_RGDAACn_M0SM. /
Kojto	90:cb3d968589d8	1295	#define BS_MPU_RGDAACn_M0SM (2U) /!< Bit field size in bits for MPU_RGDAACn_M0SM. /
Kojto	90:cb3d968589d8	1296
Kojto	90:cb3d968589d8	1297	/! @brief Read current value of the MPU_RGDAACn_M0SM field. /
Kojto	90:cb3d968589d8	1298	#define BR_MPU_RGDAACn_M0SM(x, n) (HW_MPU_RGDAACn(x, n).B.M0SM)
Kojto	90:cb3d968589d8	1299
Kojto	90:cb3d968589d8	1300	/! @brief Format value for bitfield MPU_RGDAACn_M0SM. /
Kojto	90:cb3d968589d8	1301	#define BF_MPU_RGDAACn_M0SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M0SM) & BM_MPU_RGDAACn_M0SM)
Kojto	90:cb3d968589d8	1302
Kojto	90:cb3d968589d8	1303	/! @brief Set the M0SM field to a new value. /
Kojto	90:cb3d968589d8	1304	#define BW_MPU_RGDAACn_M0SM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M0SM) \| BF_MPU_RGDAACn_M0SM(v)))
Kojto	90:cb3d968589d8	1305	/@}/
Kojto	90:cb3d968589d8	1306
Kojto	90:cb3d968589d8	1307	/*!
Kojto	90:cb3d968589d8	1308	* @name Register MPU_RGDAACn, field M0PE[5] (RW)
Kojto	90:cb3d968589d8	1309	*
Kojto	90:cb3d968589d8	1310	* See M3PE description.
Kojto	90:cb3d968589d8	1311	*/
Kojto	90:cb3d968589d8	1312	/@{/
Kojto	90:cb3d968589d8	1313	#define BP_MPU_RGDAACn_M0PE (5U) /!< Bit position for MPU_RGDAACn_M0PE. /
Kojto	90:cb3d968589d8	1314	#define BM_MPU_RGDAACn_M0PE (0x00000020U) /!< Bit mask for MPU_RGDAACn_M0PE. /
Kojto	90:cb3d968589d8	1315	#define BS_MPU_RGDAACn_M0PE (1U) /!< Bit field size in bits for MPU_RGDAACn_M0PE. /
Kojto	90:cb3d968589d8	1316
Kojto	90:cb3d968589d8	1317	/! @brief Read current value of the MPU_RGDAACn_M0PE field. /
Kojto	90:cb3d968589d8	1318	#define BR_MPU_RGDAACn_M0PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M0PE))
Kojto	90:cb3d968589d8	1319
Kojto	90:cb3d968589d8	1320	/! @brief Format value for bitfield MPU_RGDAACn_M0PE. /
Kojto	90:cb3d968589d8	1321	#define BF_MPU_RGDAACn_M0PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M0PE) & BM_MPU_RGDAACn_M0PE)
Kojto	90:cb3d968589d8	1322
Kojto	90:cb3d968589d8	1323	/! @brief Set the M0PE field to a new value. /
Kojto	90:cb3d968589d8	1324	#define BW_MPU_RGDAACn_M0PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M0PE) = (v))
Kojto	90:cb3d968589d8	1325	/@}/
Kojto	90:cb3d968589d8	1326
Kojto	90:cb3d968589d8	1327	/*!
Kojto	90:cb3d968589d8	1328	* @name Register MPU_RGDAACn, field M1UM[8:6] (RW)
Kojto	90:cb3d968589d8	1329	*
Kojto	90:cb3d968589d8	1330	* See M3UM description.
Kojto	90:cb3d968589d8	1331	*/
Kojto	90:cb3d968589d8	1332	/@{/
Kojto	90:cb3d968589d8	1333	#define BP_MPU_RGDAACn_M1UM (6U) /!< Bit position for MPU_RGDAACn_M1UM. /
Kojto	90:cb3d968589d8	1334	#define BM_MPU_RGDAACn_M1UM (0x000001C0U) /!< Bit mask for MPU_RGDAACn_M1UM. /
Kojto	90:cb3d968589d8	1335	#define BS_MPU_RGDAACn_M1UM (3U) /!< Bit field size in bits for MPU_RGDAACn_M1UM. /
Kojto	90:cb3d968589d8	1336
Kojto	90:cb3d968589d8	1337	/! @brief Read current value of the MPU_RGDAACn_M1UM field. /
Kojto	90:cb3d968589d8	1338	#define BR_MPU_RGDAACn_M1UM(x, n) (HW_MPU_RGDAACn(x, n).B.M1UM)
Kojto	90:cb3d968589d8	1339
Kojto	90:cb3d968589d8	1340	/! @brief Format value for bitfield MPU_RGDAACn_M1UM. /
Kojto	90:cb3d968589d8	1341	#define BF_MPU_RGDAACn_M1UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M1UM) & BM_MPU_RGDAACn_M1UM)
Kojto	90:cb3d968589d8	1342
Kojto	90:cb3d968589d8	1343	/! @brief Set the M1UM field to a new value. /
Kojto	90:cb3d968589d8	1344	#define BW_MPU_RGDAACn_M1UM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M1UM) \| BF_MPU_RGDAACn_M1UM(v)))
Kojto	90:cb3d968589d8	1345	/@}/
Kojto	90:cb3d968589d8	1346
Kojto	90:cb3d968589d8	1347	/*!
Kojto	90:cb3d968589d8	1348	* @name Register MPU_RGDAACn, field M1SM[10:9] (RW)
Kojto	90:cb3d968589d8	1349	*
Kojto	90:cb3d968589d8	1350	* See M3SM description.
Kojto	90:cb3d968589d8	1351	*/
Kojto	90:cb3d968589d8	1352	/@{/
Kojto	90:cb3d968589d8	1353	#define BP_MPU_RGDAACn_M1SM (9U) /!< Bit position for MPU_RGDAACn_M1SM. /
Kojto	90:cb3d968589d8	1354	#define BM_MPU_RGDAACn_M1SM (0x00000600U) /!< Bit mask for MPU_RGDAACn_M1SM. /
Kojto	90:cb3d968589d8	1355	#define BS_MPU_RGDAACn_M1SM (2U) /!< Bit field size in bits for MPU_RGDAACn_M1SM. /
Kojto	90:cb3d968589d8	1356
Kojto	90:cb3d968589d8	1357	/! @brief Read current value of the MPU_RGDAACn_M1SM field. /
Kojto	90:cb3d968589d8	1358	#define BR_MPU_RGDAACn_M1SM(x, n) (HW_MPU_RGDAACn(x, n).B.M1SM)
Kojto	90:cb3d968589d8	1359
Kojto	90:cb3d968589d8	1360	/! @brief Format value for bitfield MPU_RGDAACn_M1SM. /
Kojto	90:cb3d968589d8	1361	#define BF_MPU_RGDAACn_M1SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M1SM) & BM_MPU_RGDAACn_M1SM)
Kojto	90:cb3d968589d8	1362
Kojto	90:cb3d968589d8	1363	/! @brief Set the M1SM field to a new value. /
Kojto	90:cb3d968589d8	1364	#define BW_MPU_RGDAACn_M1SM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M1SM) \| BF_MPU_RGDAACn_M1SM(v)))
Kojto	90:cb3d968589d8	1365	/@}/
Kojto	90:cb3d968589d8	1366
Kojto	90:cb3d968589d8	1367	/*!
Kojto	90:cb3d968589d8	1368	* @name Register MPU_RGDAACn, field M1PE[11] (RW)
Kojto	90:cb3d968589d8	1369	*
Kojto	90:cb3d968589d8	1370	* See M3PE description.
Kojto	90:cb3d968589d8	1371	*/
Kojto	90:cb3d968589d8	1372	/@{/
Kojto	90:cb3d968589d8	1373	#define BP_MPU_RGDAACn_M1PE (11U) /!< Bit position for MPU_RGDAACn_M1PE. /
Kojto	90:cb3d968589d8	1374	#define BM_MPU_RGDAACn_M1PE (0x00000800U) /!< Bit mask for MPU_RGDAACn_M1PE. /
Kojto	90:cb3d968589d8	1375	#define BS_MPU_RGDAACn_M1PE (1U) /!< Bit field size in bits for MPU_RGDAACn_M1PE. /
Kojto	90:cb3d968589d8	1376
Kojto	90:cb3d968589d8	1377	/! @brief Read current value of the MPU_RGDAACn_M1PE field. /
Kojto	90:cb3d968589d8	1378	#define BR_MPU_RGDAACn_M1PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M1PE))
Kojto	90:cb3d968589d8	1379
Kojto	90:cb3d968589d8	1380	/! @brief Format value for bitfield MPU_RGDAACn_M1PE. /
Kojto	90:cb3d968589d8	1381	#define BF_MPU_RGDAACn_M1PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M1PE) & BM_MPU_RGDAACn_M1PE)
Kojto	90:cb3d968589d8	1382
Kojto	90:cb3d968589d8	1383	/! @brief Set the M1PE field to a new value. /
Kojto	90:cb3d968589d8	1384	#define BW_MPU_RGDAACn_M1PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M1PE) = (v))
Kojto	90:cb3d968589d8	1385	/@}/
Kojto	90:cb3d968589d8	1386
Kojto	90:cb3d968589d8	1387	/*!
Kojto	90:cb3d968589d8	1388	* @name Register MPU_RGDAACn, field M2UM[14:12] (RW)
Kojto	90:cb3d968589d8	1389	*
Kojto	90:cb3d968589d8	1390	* See M3UM description.
Kojto	90:cb3d968589d8	1391	*/
Kojto	90:cb3d968589d8	1392	/@{/
Kojto	90:cb3d968589d8	1393	#define BP_MPU_RGDAACn_M2UM (12U) /!< Bit position for MPU_RGDAACn_M2UM. /
Kojto	90:cb3d968589d8	1394	#define BM_MPU_RGDAACn_M2UM (0x00007000U) /!< Bit mask for MPU_RGDAACn_M2UM. /
Kojto	90:cb3d968589d8	1395	#define BS_MPU_RGDAACn_M2UM (3U) /!< Bit field size in bits for MPU_RGDAACn_M2UM. /
Kojto	90:cb3d968589d8	1396
Kojto	90:cb3d968589d8	1397	/! @brief Read current value of the MPU_RGDAACn_M2UM field. /
Kojto	90:cb3d968589d8	1398	#define BR_MPU_RGDAACn_M2UM(x, n) (HW_MPU_RGDAACn(x, n).B.M2UM)
Kojto	90:cb3d968589d8	1399
Kojto	90:cb3d968589d8	1400	/! @brief Format value for bitfield MPU_RGDAACn_M2UM. /
Kojto	90:cb3d968589d8	1401	#define BF_MPU_RGDAACn_M2UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M2UM) & BM_MPU_RGDAACn_M2UM)
Kojto	90:cb3d968589d8	1402
Kojto	90:cb3d968589d8	1403	/! @brief Set the M2UM field to a new value. /
Kojto	90:cb3d968589d8	1404	#define BW_MPU_RGDAACn_M2UM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M2UM) \| BF_MPU_RGDAACn_M2UM(v)))
Kojto	90:cb3d968589d8	1405	/@}/
Kojto	90:cb3d968589d8	1406
Kojto	90:cb3d968589d8	1407	/*!
Kojto	90:cb3d968589d8	1408	* @name Register MPU_RGDAACn, field M2SM[16:15] (RW)
Kojto	90:cb3d968589d8	1409	*
Kojto	90:cb3d968589d8	1410	* See M3SM description.
Kojto	90:cb3d968589d8	1411	*/
Kojto	90:cb3d968589d8	1412	/@{/
Kojto	90:cb3d968589d8	1413	#define BP_MPU_RGDAACn_M2SM (15U) /!< Bit position for MPU_RGDAACn_M2SM. /
Kojto	90:cb3d968589d8	1414	#define BM_MPU_RGDAACn_M2SM (0x00018000U) /!< Bit mask for MPU_RGDAACn_M2SM. /
Kojto	90:cb3d968589d8	1415	#define BS_MPU_RGDAACn_M2SM (2U) /!< Bit field size in bits for MPU_RGDAACn_M2SM. /
Kojto	90:cb3d968589d8	1416
Kojto	90:cb3d968589d8	1417	/! @brief Read current value of the MPU_RGDAACn_M2SM field. /
Kojto	90:cb3d968589d8	1418	#define BR_MPU_RGDAACn_M2SM(x, n) (HW_MPU_RGDAACn(x, n).B.M2SM)
Kojto	90:cb3d968589d8	1419
Kojto	90:cb3d968589d8	1420	/! @brief Format value for bitfield MPU_RGDAACn_M2SM. /
Kojto	90:cb3d968589d8	1421	#define BF_MPU_RGDAACn_M2SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M2SM) & BM_MPU_RGDAACn_M2SM)
Kojto	90:cb3d968589d8	1422
Kojto	90:cb3d968589d8	1423	/! @brief Set the M2SM field to a new value. /
Kojto	90:cb3d968589d8	1424	#define BW_MPU_RGDAACn_M2SM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M2SM) \| BF_MPU_RGDAACn_M2SM(v)))
Kojto	90:cb3d968589d8	1425	/@}/
Kojto	90:cb3d968589d8	1426
Kojto	90:cb3d968589d8	1427	/*!
Kojto	90:cb3d968589d8	1428	* @name Register MPU_RGDAACn, field M2PE[17] (RW)
Kojto	90:cb3d968589d8	1429	*
Kojto	90:cb3d968589d8	1430	* See M3PE description.
Kojto	90:cb3d968589d8	1431	*/
Kojto	90:cb3d968589d8	1432	/@{/
Kojto	90:cb3d968589d8	1433	#define BP_MPU_RGDAACn_M2PE (17U) /!< Bit position for MPU_RGDAACn_M2PE. /
Kojto	90:cb3d968589d8	1434	#define BM_MPU_RGDAACn_M2PE (0x00020000U) /!< Bit mask for MPU_RGDAACn_M2PE. /
Kojto	90:cb3d968589d8	1435	#define BS_MPU_RGDAACn_M2PE (1U) /!< Bit field size in bits for MPU_RGDAACn_M2PE. /
Kojto	90:cb3d968589d8	1436
Kojto	90:cb3d968589d8	1437	/! @brief Read current value of the MPU_RGDAACn_M2PE field. /
Kojto	90:cb3d968589d8	1438	#define BR_MPU_RGDAACn_M2PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M2PE))
Kojto	90:cb3d968589d8	1439
Kojto	90:cb3d968589d8	1440	/! @brief Format value for bitfield MPU_RGDAACn_M2PE. /
Kojto	90:cb3d968589d8	1441	#define BF_MPU_RGDAACn_M2PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M2PE) & BM_MPU_RGDAACn_M2PE)
Kojto	90:cb3d968589d8	1442
Kojto	90:cb3d968589d8	1443	/! @brief Set the M2PE field to a new value. /
Kojto	90:cb3d968589d8	1444	#define BW_MPU_RGDAACn_M2PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M2PE) = (v))
Kojto	90:cb3d968589d8	1445	/@}/
Kojto	90:cb3d968589d8	1446
Kojto	90:cb3d968589d8	1447	/*!
Kojto	90:cb3d968589d8	1448	* @name Register MPU_RGDAACn, field M3UM[20:18] (RW)
Kojto	90:cb3d968589d8	1449	*
Kojto	90:cb3d968589d8	1450	* Defines the access controls for bus master 3 in user mode. M3UM consists of
Kojto	90:cb3d968589d8	1451	* three independent bits, enabling read (r), write (w), and execute (x)
Kojto	90:cb3d968589d8	1452	* permissions.
Kojto	90:cb3d968589d8	1453	*
Kojto	90:cb3d968589d8	1454	* Values:
Kojto	90:cb3d968589d8	1455	* - 0 - An attempted access of that mode may be terminated with an access error
Kojto	90:cb3d968589d8	1456	* (if not allowed by another descriptor) and the access not performed.
Kojto	90:cb3d968589d8	1457	* - 1 - Allows the given access type to occur
Kojto	90:cb3d968589d8	1458	*/
Kojto	90:cb3d968589d8	1459	/@{/
Kojto	90:cb3d968589d8	1460	#define BP_MPU_RGDAACn_M3UM (18U) /!< Bit position for MPU_RGDAACn_M3UM. /
Kojto	90:cb3d968589d8	1461	#define BM_MPU_RGDAACn_M3UM (0x001C0000U) /!< Bit mask for MPU_RGDAACn_M3UM. /
Kojto	90:cb3d968589d8	1462	#define BS_MPU_RGDAACn_M3UM (3U) /!< Bit field size in bits for MPU_RGDAACn_M3UM. /
Kojto	90:cb3d968589d8	1463
Kojto	90:cb3d968589d8	1464	/! @brief Read current value of the MPU_RGDAACn_M3UM field. /
Kojto	90:cb3d968589d8	1465	#define BR_MPU_RGDAACn_M3UM(x, n) (HW_MPU_RGDAACn(x, n).B.M3UM)
Kojto	90:cb3d968589d8	1466
Kojto	90:cb3d968589d8	1467	/! @brief Format value for bitfield MPU_RGDAACn_M3UM. /
Kojto	90:cb3d968589d8	1468	#define BF_MPU_RGDAACn_M3UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M3UM) & BM_MPU_RGDAACn_M3UM)
Kojto	90:cb3d968589d8	1469
Kojto	90:cb3d968589d8	1470	/! @brief Set the M3UM field to a new value. /
Kojto	90:cb3d968589d8	1471	#define BW_MPU_RGDAACn_M3UM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M3UM) \| BF_MPU_RGDAACn_M3UM(v)))
Kojto	90:cb3d968589d8	1472	/@}/
Kojto	90:cb3d968589d8	1473
Kojto	90:cb3d968589d8	1474	/*!
Kojto	90:cb3d968589d8	1475	* @name Register MPU_RGDAACn, field M3SM[22:21] (RW)
Kojto	90:cb3d968589d8	1476	*
Kojto	90:cb3d968589d8	1477	* Defines the access controls for bus master 3 in Supervisor mode.
Kojto	90:cb3d968589d8	1478	*
Kojto	90:cb3d968589d8	1479	* Values:
Kojto	90:cb3d968589d8	1480	* - 00 - r/w/x; read, write and execute allowed
Kojto	90:cb3d968589d8	1481	* - 01 - r/x; read and execute allowed, but no write
Kojto	90:cb3d968589d8	1482	* - 10 - r/w; read and write allowed, but no execute
Kojto	90:cb3d968589d8	1483	* - 11 - Same as User mode defined in M3UM
Kojto	90:cb3d968589d8	1484	*/
Kojto	90:cb3d968589d8	1485	/@{/
Kojto	90:cb3d968589d8	1486	#define BP_MPU_RGDAACn_M3SM (21U) /!< Bit position for MPU_RGDAACn_M3SM. /
Kojto	90:cb3d968589d8	1487	#define BM_MPU_RGDAACn_M3SM (0x00600000U) /!< Bit mask for MPU_RGDAACn_M3SM. /
Kojto	90:cb3d968589d8	1488	#define BS_MPU_RGDAACn_M3SM (2U) /!< Bit field size in bits for MPU_RGDAACn_M3SM. /
Kojto	90:cb3d968589d8	1489
Kojto	90:cb3d968589d8	1490	/! @brief Read current value of the MPU_RGDAACn_M3SM field. /
Kojto	90:cb3d968589d8	1491	#define BR_MPU_RGDAACn_M3SM(x, n) (HW_MPU_RGDAACn(x, n).B.M3SM)
Kojto	90:cb3d968589d8	1492
Kojto	90:cb3d968589d8	1493	/! @brief Format value for bitfield MPU_RGDAACn_M3SM. /
Kojto	90:cb3d968589d8	1494	#define BF_MPU_RGDAACn_M3SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M3SM) & BM_MPU_RGDAACn_M3SM)
Kojto	90:cb3d968589d8	1495
Kojto	90:cb3d968589d8	1496	/! @brief Set the M3SM field to a new value. /
Kojto	90:cb3d968589d8	1497	#define BW_MPU_RGDAACn_M3SM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M3SM) \| BF_MPU_RGDAACn_M3SM(v)))
Kojto	90:cb3d968589d8	1498	/@}/
Kojto	90:cb3d968589d8	1499
Kojto	90:cb3d968589d8	1500	/*!
Kojto	90:cb3d968589d8	1501	* @name Register MPU_RGDAACn, field M3PE[23] (RW)
Kojto	90:cb3d968589d8	1502	*
Kojto	90:cb3d968589d8	1503	* Values:
Kojto	90:cb3d968589d8	1504	* - 0 - Do not include the process identifier in the evaluation
Kojto	90:cb3d968589d8	1505	* - 1 - Include the process identifier and mask (RGDn.RGDAAC) in the region hit
Kojto	90:cb3d968589d8	1506	* evaluation
Kojto	90:cb3d968589d8	1507	*/
Kojto	90:cb3d968589d8	1508	/@{/
Kojto	90:cb3d968589d8	1509	#define BP_MPU_RGDAACn_M3PE (23U) /!< Bit position for MPU_RGDAACn_M3PE. /
Kojto	90:cb3d968589d8	1510	#define BM_MPU_RGDAACn_M3PE (0x00800000U) /!< Bit mask for MPU_RGDAACn_M3PE. /
Kojto	90:cb3d968589d8	1511	#define BS_MPU_RGDAACn_M3PE (1U) /!< Bit field size in bits for MPU_RGDAACn_M3PE. /
Kojto	90:cb3d968589d8	1512
Kojto	90:cb3d968589d8	1513	/! @brief Read current value of the MPU_RGDAACn_M3PE field. /
Kojto	90:cb3d968589d8	1514	#define BR_MPU_RGDAACn_M3PE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M3PE))
Kojto	90:cb3d968589d8	1515
Kojto	90:cb3d968589d8	1516	/! @brief Format value for bitfield MPU_RGDAACn_M3PE. /
Kojto	90:cb3d968589d8	1517	#define BF_MPU_RGDAACn_M3PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M3PE) & BM_MPU_RGDAACn_M3PE)
Kojto	90:cb3d968589d8	1518
Kojto	90:cb3d968589d8	1519	/! @brief Set the M3PE field to a new value. /
Kojto	90:cb3d968589d8	1520	#define BW_MPU_RGDAACn_M3PE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M3PE) = (v))
Kojto	90:cb3d968589d8	1521	/@}/
Kojto	90:cb3d968589d8	1522
Kojto	90:cb3d968589d8	1523	/*!
Kojto	90:cb3d968589d8	1524	* @name Register MPU_RGDAACn, field M4WE[24] (RW)
Kojto	90:cb3d968589d8	1525	*
Kojto	90:cb3d968589d8	1526	* Values:
Kojto	90:cb3d968589d8	1527	* - 0 - Bus master 4 writes terminate with an access error and the write is not
Kojto	90:cb3d968589d8	1528	* performed
Kojto	90:cb3d968589d8	1529	* - 1 - Bus master 4 writes allowed
Kojto	90:cb3d968589d8	1530	*/
Kojto	90:cb3d968589d8	1531	/@{/
Kojto	90:cb3d968589d8	1532	#define BP_MPU_RGDAACn_M4WE (24U) /!< Bit position for MPU_RGDAACn_M4WE. /
Kojto	90:cb3d968589d8	1533	#define BM_MPU_RGDAACn_M4WE (0x01000000U) /!< Bit mask for MPU_RGDAACn_M4WE. /
Kojto	90:cb3d968589d8	1534	#define BS_MPU_RGDAACn_M4WE (1U) /!< Bit field size in bits for MPU_RGDAACn_M4WE. /
Kojto	90:cb3d968589d8	1535
Kojto	90:cb3d968589d8	1536	/! @brief Read current value of the MPU_RGDAACn_M4WE field. /
Kojto	90:cb3d968589d8	1537	#define BR_MPU_RGDAACn_M4WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M4WE))
Kojto	90:cb3d968589d8	1538
Kojto	90:cb3d968589d8	1539	/! @brief Format value for bitfield MPU_RGDAACn_M4WE. /
Kojto	90:cb3d968589d8	1540	#define BF_MPU_RGDAACn_M4WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M4WE) & BM_MPU_RGDAACn_M4WE)
Kojto	90:cb3d968589d8	1541
Kojto	90:cb3d968589d8	1542	/! @brief Set the M4WE field to a new value. /
Kojto	90:cb3d968589d8	1543	#define BW_MPU_RGDAACn_M4WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M4WE) = (v))
Kojto	90:cb3d968589d8	1544	/@}/
Kojto	90:cb3d968589d8	1545
Kojto	90:cb3d968589d8	1546	/*!
Kojto	90:cb3d968589d8	1547	* @name Register MPU_RGDAACn, field M4RE[25] (RW)
Kojto	90:cb3d968589d8	1548	*
Kojto	90:cb3d968589d8	1549	* Values:
Kojto	90:cb3d968589d8	1550	* - 0 - Bus master 4 reads terminate with an access error and the read is not
Kojto	90:cb3d968589d8	1551	* performed
Kojto	90:cb3d968589d8	1552	* - 1 - Bus master 4 reads allowed
Kojto	90:cb3d968589d8	1553	*/
Kojto	90:cb3d968589d8	1554	/@{/
Kojto	90:cb3d968589d8	1555	#define BP_MPU_RGDAACn_M4RE (25U) /!< Bit position for MPU_RGDAACn_M4RE. /
Kojto	90:cb3d968589d8	1556	#define BM_MPU_RGDAACn_M4RE (0x02000000U) /!< Bit mask for MPU_RGDAACn_M4RE. /
Kojto	90:cb3d968589d8	1557	#define BS_MPU_RGDAACn_M4RE (1U) /!< Bit field size in bits for MPU_RGDAACn_M4RE. /
Kojto	90:cb3d968589d8	1558
Kojto	90:cb3d968589d8	1559	/! @brief Read current value of the MPU_RGDAACn_M4RE field. /
Kojto	90:cb3d968589d8	1560	#define BR_MPU_RGDAACn_M4RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M4RE))
Kojto	90:cb3d968589d8	1561
Kojto	90:cb3d968589d8	1562	/! @brief Format value for bitfield MPU_RGDAACn_M4RE. /
Kojto	90:cb3d968589d8	1563	#define BF_MPU_RGDAACn_M4RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M4RE) & BM_MPU_RGDAACn_M4RE)
Kojto	90:cb3d968589d8	1564
Kojto	90:cb3d968589d8	1565	/! @brief Set the M4RE field to a new value. /
Kojto	90:cb3d968589d8	1566	#define BW_MPU_RGDAACn_M4RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M4RE) = (v))
Kojto	90:cb3d968589d8	1567	/@}/
Kojto	90:cb3d968589d8	1568
Kojto	90:cb3d968589d8	1569	/*!
Kojto	90:cb3d968589d8	1570	* @name Register MPU_RGDAACn, field M5WE[26] (RW)
Kojto	90:cb3d968589d8	1571	*
Kojto	90:cb3d968589d8	1572	* Values:
Kojto	90:cb3d968589d8	1573	* - 0 - Bus master 5 writes terminate with an access error and the write is not
Kojto	90:cb3d968589d8	1574	* performed
Kojto	90:cb3d968589d8	1575	* - 1 - Bus master 5 writes allowed
Kojto	90:cb3d968589d8	1576	*/
Kojto	90:cb3d968589d8	1577	/@{/
Kojto	90:cb3d968589d8	1578	#define BP_MPU_RGDAACn_M5WE (26U) /!< Bit position for MPU_RGDAACn_M5WE. /
Kojto	90:cb3d968589d8	1579	#define BM_MPU_RGDAACn_M5WE (0x04000000U) /!< Bit mask for MPU_RGDAACn_M5WE. /
Kojto	90:cb3d968589d8	1580	#define BS_MPU_RGDAACn_M5WE (1U) /!< Bit field size in bits for MPU_RGDAACn_M5WE. /
Kojto	90:cb3d968589d8	1581
Kojto	90:cb3d968589d8	1582	/! @brief Read current value of the MPU_RGDAACn_M5WE field. /
Kojto	90:cb3d968589d8	1583	#define BR_MPU_RGDAACn_M5WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M5WE))
Kojto	90:cb3d968589d8	1584
Kojto	90:cb3d968589d8	1585	/! @brief Format value for bitfield MPU_RGDAACn_M5WE. /
Kojto	90:cb3d968589d8	1586	#define BF_MPU_RGDAACn_M5WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M5WE) & BM_MPU_RGDAACn_M5WE)
Kojto	90:cb3d968589d8	1587
Kojto	90:cb3d968589d8	1588	/! @brief Set the M5WE field to a new value. /
Kojto	90:cb3d968589d8	1589	#define BW_MPU_RGDAACn_M5WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M5WE) = (v))
Kojto	90:cb3d968589d8	1590	/@}/
Kojto	90:cb3d968589d8	1591
Kojto	90:cb3d968589d8	1592	/*!
Kojto	90:cb3d968589d8	1593	* @name Register MPU_RGDAACn, field M5RE[27] (RW)
Kojto	90:cb3d968589d8	1594	*
Kojto	90:cb3d968589d8	1595	* Values:
Kojto	90:cb3d968589d8	1596	* - 0 - Bus master 5 reads terminate with an access error and the read is not
Kojto	90:cb3d968589d8	1597	* performed
Kojto	90:cb3d968589d8	1598	* - 1 - Bus master 5 reads allowed
Kojto	90:cb3d968589d8	1599	*/
Kojto	90:cb3d968589d8	1600	/@{/
Kojto	90:cb3d968589d8	1601	#define BP_MPU_RGDAACn_M5RE (27U) /!< Bit position for MPU_RGDAACn_M5RE. /
Kojto	90:cb3d968589d8	1602	#define BM_MPU_RGDAACn_M5RE (0x08000000U) /!< Bit mask for MPU_RGDAACn_M5RE. /
Kojto	90:cb3d968589d8	1603	#define BS_MPU_RGDAACn_M5RE (1U) /!< Bit field size in bits for MPU_RGDAACn_M5RE. /
Kojto	90:cb3d968589d8	1604
Kojto	90:cb3d968589d8	1605	/! @brief Read current value of the MPU_RGDAACn_M5RE field. /
Kojto	90:cb3d968589d8	1606	#define BR_MPU_RGDAACn_M5RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M5RE))
Kojto	90:cb3d968589d8	1607
Kojto	90:cb3d968589d8	1608	/! @brief Format value for bitfield MPU_RGDAACn_M5RE. /
Kojto	90:cb3d968589d8	1609	#define BF_MPU_RGDAACn_M5RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M5RE) & BM_MPU_RGDAACn_M5RE)
Kojto	90:cb3d968589d8	1610
Kojto	90:cb3d968589d8	1611	/! @brief Set the M5RE field to a new value. /
Kojto	90:cb3d968589d8	1612	#define BW_MPU_RGDAACn_M5RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M5RE) = (v))
Kojto	90:cb3d968589d8	1613	/@}/
Kojto	90:cb3d968589d8	1614
Kojto	90:cb3d968589d8	1615	/*!
Kojto	90:cb3d968589d8	1616	* @name Register MPU_RGDAACn, field M6WE[28] (RW)
Kojto	90:cb3d968589d8	1617	*
Kojto	90:cb3d968589d8	1618	* Values:
Kojto	90:cb3d968589d8	1619	* - 0 - Bus master 6 writes terminate with an access error and the write is not
Kojto	90:cb3d968589d8	1620	* performed
Kojto	90:cb3d968589d8	1621	* - 1 - Bus master 6 writes allowed
Kojto	90:cb3d968589d8	1622	*/
Kojto	90:cb3d968589d8	1623	/@{/
Kojto	90:cb3d968589d8	1624	#define BP_MPU_RGDAACn_M6WE (28U) /!< Bit position for MPU_RGDAACn_M6WE. /
Kojto	90:cb3d968589d8	1625	#define BM_MPU_RGDAACn_M6WE (0x10000000U) /!< Bit mask for MPU_RGDAACn_M6WE. /
Kojto	90:cb3d968589d8	1626	#define BS_MPU_RGDAACn_M6WE (1U) /!< Bit field size in bits for MPU_RGDAACn_M6WE. /
Kojto	90:cb3d968589d8	1627
Kojto	90:cb3d968589d8	1628	/! @brief Read current value of the MPU_RGDAACn_M6WE field. /
Kojto	90:cb3d968589d8	1629	#define BR_MPU_RGDAACn_M6WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M6WE))
Kojto	90:cb3d968589d8	1630
Kojto	90:cb3d968589d8	1631	/! @brief Format value for bitfield MPU_RGDAACn_M6WE. /
Kojto	90:cb3d968589d8	1632	#define BF_MPU_RGDAACn_M6WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M6WE) & BM_MPU_RGDAACn_M6WE)
Kojto	90:cb3d968589d8	1633
Kojto	90:cb3d968589d8	1634	/! @brief Set the M6WE field to a new value. /
Kojto	90:cb3d968589d8	1635	#define BW_MPU_RGDAACn_M6WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M6WE) = (v))
Kojto	90:cb3d968589d8	1636	/@}/
Kojto	90:cb3d968589d8	1637
Kojto	90:cb3d968589d8	1638	/*!
Kojto	90:cb3d968589d8	1639	* @name Register MPU_RGDAACn, field M6RE[29] (RW)
Kojto	90:cb3d968589d8	1640	*
Kojto	90:cb3d968589d8	1641	* Values:
Kojto	90:cb3d968589d8	1642	* - 0 - Bus master 6 reads terminate with an access error and the read is not
Kojto	90:cb3d968589d8	1643	* performed
Kojto	90:cb3d968589d8	1644	* - 1 - Bus master 6 reads allowed
Kojto	90:cb3d968589d8	1645	*/
Kojto	90:cb3d968589d8	1646	/@{/
Kojto	90:cb3d968589d8	1647	#define BP_MPU_RGDAACn_M6RE (29U) /!< Bit position for MPU_RGDAACn_M6RE. /
Kojto	90:cb3d968589d8	1648	#define BM_MPU_RGDAACn_M6RE (0x20000000U) /!< Bit mask for MPU_RGDAACn_M6RE. /
Kojto	90:cb3d968589d8	1649	#define BS_MPU_RGDAACn_M6RE (1U) /!< Bit field size in bits for MPU_RGDAACn_M6RE. /
Kojto	90:cb3d968589d8	1650
Kojto	90:cb3d968589d8	1651	/! @brief Read current value of the MPU_RGDAACn_M6RE field. /
Kojto	90:cb3d968589d8	1652	#define BR_MPU_RGDAACn_M6RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M6RE))
Kojto	90:cb3d968589d8	1653
Kojto	90:cb3d968589d8	1654	/! @brief Format value for bitfield MPU_RGDAACn_M6RE. /
Kojto	90:cb3d968589d8	1655	#define BF_MPU_RGDAACn_M6RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M6RE) & BM_MPU_RGDAACn_M6RE)
Kojto	90:cb3d968589d8	1656
Kojto	90:cb3d968589d8	1657	/! @brief Set the M6RE field to a new value. /
Kojto	90:cb3d968589d8	1658	#define BW_MPU_RGDAACn_M6RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M6RE) = (v))
Kojto	90:cb3d968589d8	1659	/@}/
Kojto	90:cb3d968589d8	1660
Kojto	90:cb3d968589d8	1661	/*!
Kojto	90:cb3d968589d8	1662	* @name Register MPU_RGDAACn, field M7WE[30] (RW)
Kojto	90:cb3d968589d8	1663	*
Kojto	90:cb3d968589d8	1664	* Values:
Kojto	90:cb3d968589d8	1665	* - 0 - Bus master 7 writes terminate with an access error and the write is not
Kojto	90:cb3d968589d8	1666	* performed
Kojto	90:cb3d968589d8	1667	* - 1 - Bus master 7 writes allowed
Kojto	90:cb3d968589d8	1668	*/
Kojto	90:cb3d968589d8	1669	/@{/
Kojto	90:cb3d968589d8	1670	#define BP_MPU_RGDAACn_M7WE (30U) /!< Bit position for MPU_RGDAACn_M7WE. /
Kojto	90:cb3d968589d8	1671	#define BM_MPU_RGDAACn_M7WE (0x40000000U) /!< Bit mask for MPU_RGDAACn_M7WE. /
Kojto	90:cb3d968589d8	1672	#define BS_MPU_RGDAACn_M7WE (1U) /!< Bit field size in bits for MPU_RGDAACn_M7WE. /
Kojto	90:cb3d968589d8	1673
Kojto	90:cb3d968589d8	1674	/! @brief Read current value of the MPU_RGDAACn_M7WE field. /
Kojto	90:cb3d968589d8	1675	#define BR_MPU_RGDAACn_M7WE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M7WE))
Kojto	90:cb3d968589d8	1676
Kojto	90:cb3d968589d8	1677	/! @brief Format value for bitfield MPU_RGDAACn_M7WE. /
Kojto	90:cb3d968589d8	1678	#define BF_MPU_RGDAACn_M7WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M7WE) & BM_MPU_RGDAACn_M7WE)
Kojto	90:cb3d968589d8	1679
Kojto	90:cb3d968589d8	1680	/! @brief Set the M7WE field to a new value. /
Kojto	90:cb3d968589d8	1681	#define BW_MPU_RGDAACn_M7WE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M7WE) = (v))
Kojto	90:cb3d968589d8	1682	/@}/
Kojto	90:cb3d968589d8	1683
Kojto	90:cb3d968589d8	1684	/*!
Kojto	90:cb3d968589d8	1685	* @name Register MPU_RGDAACn, field M7RE[31] (RW)
Kojto	90:cb3d968589d8	1686	*
Kojto	90:cb3d968589d8	1687	* Values:
Kojto	90:cb3d968589d8	1688	* - 0 - Bus master 7 reads terminate with an access error and the read is not
Kojto	90:cb3d968589d8	1689	* performed
Kojto	90:cb3d968589d8	1690	* - 1 - Bus master 7 reads allowed
Kojto	90:cb3d968589d8	1691	*/
Kojto	90:cb3d968589d8	1692	/@{/
Kojto	90:cb3d968589d8	1693	#define BP_MPU_RGDAACn_M7RE (31U) /!< Bit position for MPU_RGDAACn_M7RE. /
Kojto	90:cb3d968589d8	1694	#define BM_MPU_RGDAACn_M7RE (0x80000000U) /!< Bit mask for MPU_RGDAACn_M7RE. /
Kojto	90:cb3d968589d8	1695	#define BS_MPU_RGDAACn_M7RE (1U) /!< Bit field size in bits for MPU_RGDAACn_M7RE. /
Kojto	90:cb3d968589d8	1696
Kojto	90:cb3d968589d8	1697	/! @brief Read current value of the MPU_RGDAACn_M7RE field. /
Kojto	90:cb3d968589d8	1698	#define BR_MPU_RGDAACn_M7RE(x, n) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M7RE))
Kojto	90:cb3d968589d8	1699
Kojto	90:cb3d968589d8	1700	/! @brief Format value for bitfield MPU_RGDAACn_M7RE. /
Kojto	90:cb3d968589d8	1701	#define BF_MPU_RGDAACn_M7RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M7RE) & BM_MPU_RGDAACn_M7RE)
Kojto	90:cb3d968589d8	1702
Kojto	90:cb3d968589d8	1703	/! @brief Set the M7RE field to a new value. /
Kojto	90:cb3d968589d8	1704	#define BW_MPU_RGDAACn_M7RE(x, n, v) (BITBAND_ACCESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M7RE) = (v))
Kojto	90:cb3d968589d8	1705	/@}/
Kojto	90:cb3d968589d8	1706
Kojto	90:cb3d968589d8	1707	/*******************************************************************************
Kojto	90:cb3d968589d8	1708	* hw_mpu_t - module struct
Kojto	90:cb3d968589d8	1709	******************************************************************************/
Kojto	90:cb3d968589d8	1710	/*!
Kojto	90:cb3d968589d8	1711	* @brief All MPU module registers.
Kojto	90:cb3d968589d8	1712	*/
Kojto	90:cb3d968589d8	1713	#pragma pack(1)
Kojto	90:cb3d968589d8	1714	typedef struct _hw_mpu
Kojto	90:cb3d968589d8	1715	{
Kojto	90:cb3d968589d8	1716	__IO hw_mpu_cesr_t CESR; /!< [0x0] Control/Error Status Register /
Kojto	90:cb3d968589d8	1717	uint8_t _reserved0[12];
Kojto	90:cb3d968589d8	1718	struct {
Kojto	90:cb3d968589d8	1719	__I hw_mpu_earn_t EARn; /!< [0x10] Error Address Register, slave port n /
Kojto	90:cb3d968589d8	1720	__I hw_mpu_edrn_t EDRn; /!< [0x14] Error Detail Register, slave port n /
Kojto	90:cb3d968589d8	1721	} SP[5];
Kojto	90:cb3d968589d8	1722	uint8_t _reserved1[968];
Kojto	90:cb3d968589d8	1723	struct {
Kojto	90:cb3d968589d8	1724	__IO hw_mpu_rgdn_word0_t RGDn_WORD0; /!< [0x400] Region Descriptor n, Word 0 /
Kojto	90:cb3d968589d8	1725	__IO hw_mpu_rgdn_word1_t RGDn_WORD1; /!< [0x404] Region Descriptor n, Word 1 /
Kojto	90:cb3d968589d8	1726	__IO hw_mpu_rgdn_word2_t RGDn_WORD2; /!< [0x408] Region Descriptor n, Word 2 /
Kojto	90:cb3d968589d8	1727	__IO hw_mpu_rgdn_word3_t RGDn_WORD3; /!< [0x40C] Region Descriptor n, Word 3 /
Kojto	90:cb3d968589d8	1728	} RGD[12];
Kojto	90:cb3d968589d8	1729	uint8_t _reserved2[832];
Kojto	90:cb3d968589d8	1730	__IO hw_mpu_rgdaacn_t RGDAACn[12]; /!< [0x800] Region Descriptor Alternate Access Control n /
Kojto	90:cb3d968589d8	1731	} hw_mpu_t;
Kojto	90:cb3d968589d8	1732	#pragma pack()
Kojto	90:cb3d968589d8	1733
Kojto	90:cb3d968589d8	1734	/! @brief Macro to access all MPU registers. /
Kojto	90:cb3d968589d8	1735	/! @param x MPU module instance base address. /
Kojto	90:cb3d968589d8	1736	/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto	90:cb3d968589d8	1737	* use the '&' operator, like <code>&HW_MPU(MPU_BASE)</code>. */
Kojto	90:cb3d968589d8	1738	#define HW_MPU(x) ((hw_mpu_t )(x))
Kojto	90:cb3d968589d8	1739
Kojto	90:cb3d968589d8	1740	#endif /* __HW_MPU_REGISTERS_H__ */
Kojto	90:cb3d968589d8	1741	/* EOF */