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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_mcm.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:
Kojto
Date:
Wed Aug 05 13:16:35 2015 +0100
Revision:
104:b9ad9a133dc7
Parent:
90:cb3d968589d8 
Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /*
Kojto 90:cb3d968589d8 2 ** ###################################################################
Kojto 90:cb3d968589d8 3 ** Compilers: Keil ARM C/C++ Compiler
Kojto 90:cb3d968589d8 4 ** Freescale C/C++ for Embedded ARM
Kojto 90:cb3d968589d8 5 ** GNU C Compiler
Kojto 90:cb3d968589d8 6 ** IAR ANSI C/C++ Compiler for ARM
Kojto 90:cb3d968589d8 7 **
Kojto 90:cb3d968589d8 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto 90:cb3d968589d8 9 ** Version: rev. 2.5, 2014-02-10
Kojto 90:cb3d968589d8 10 ** Build: b140604
Kojto 90:cb3d968589d8 11 **
Kojto 90:cb3d968589d8 12 ** Abstract:
Kojto 90:cb3d968589d8 13 ** Extension to the CMSIS register access layer header.
Kojto 90:cb3d968589d8 14 **
Kojto 90:cb3d968589d8 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto 90:cb3d968589d8 16 ** All rights reserved.
Kojto 90:cb3d968589d8 17 **
Kojto 90:cb3d968589d8 18 ** Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 19 ** are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 20 **
Kojto 90:cb3d968589d8 21 ** o Redistributions of source code must retain the above copyright notice, this list
Kojto 90:cb3d968589d8 22 ** of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 23 **
Kojto 90:cb3d968589d8 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto 90:cb3d968589d8 25 ** list of conditions and the following disclaimer in the documentation and/or
Kojto 90:cb3d968589d8 26 ** other materials provided with the distribution.
Kojto 90:cb3d968589d8 27 **
Kojto 90:cb3d968589d8 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto 90:cb3d968589d8 29 ** contributors may be used to endorse or promote products derived from this
Kojto 90:cb3d968589d8 30 ** software without specific prior written permission.
Kojto 90:cb3d968589d8 31 **
Kojto 90:cb3d968589d8 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 90:cb3d968589d8 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 90:cb3d968589d8 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 90:cb3d968589d8 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 90:cb3d968589d8 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 90:cb3d968589d8 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 90:cb3d968589d8 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 90:cb3d968589d8 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 90:cb3d968589d8 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 42 **
Kojto 90:cb3d968589d8 43 ** http: www.freescale.com
Kojto 90:cb3d968589d8 44 ** mail: support@freescale.com
Kojto 90:cb3d968589d8 45 **
Kojto 90:cb3d968589d8 46 ** Revisions:
Kojto 90:cb3d968589d8 47 ** - rev. 1.0 (2013-08-12)
Kojto 90:cb3d968589d8 48 ** Initial version.
Kojto 90:cb3d968589d8 49 ** - rev. 2.0 (2013-10-29)
Kojto 90:cb3d968589d8 50 ** Register accessor macros added to the memory map.
Kojto 90:cb3d968589d8 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto 90:cb3d968589d8 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto 90:cb3d968589d8 53 ** System initialization updated.
Kojto 90:cb3d968589d8 54 ** MCG - registers updated.
Kojto 90:cb3d968589d8 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto 90:cb3d968589d8 56 ** - rev. 2.1 (2013-10-30)
Kojto 90:cb3d968589d8 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto 90:cb3d968589d8 58 ** - rev. 2.2 (2013-12-09)
Kojto 90:cb3d968589d8 59 ** DMA - EARS register removed.
Kojto 90:cb3d968589d8 60 ** AIPS0, AIPS1 - MPRA register updated.
Kojto 90:cb3d968589d8 61 ** - rev. 2.3 (2014-01-24)
Kojto 90:cb3d968589d8 62 ** Update according to reference manual rev. 2
Kojto 90:cb3d968589d8 63 ** ENET, MCG, MCM, SIM, USB - registers updated
Kojto 90:cb3d968589d8 64 ** - rev. 2.4 (2014-02-10)
Kojto 90:cb3d968589d8 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 67 ** - rev. 2.5 (2014-02-10)
Kojto 90:cb3d968589d8 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto 90:cb3d968589d8 71 **
Kojto 90:cb3d968589d8 72 ** ###################################################################
Kojto 90:cb3d968589d8 73 */
Kojto 90:cb3d968589d8 74
Kojto 90:cb3d968589d8 75 /*
Kojto 90:cb3d968589d8 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto 90:cb3d968589d8 77 *
Kojto 90:cb3d968589d8 78 * This file was generated automatically and any changes may be lost.
Kojto 90:cb3d968589d8 79 */
Kojto 90:cb3d968589d8 80 #ifndef __HW_MCM_REGISTERS_H__
Kojto 90:cb3d968589d8 81 #define __HW_MCM_REGISTERS_H__
Kojto 90:cb3d968589d8 82
Kojto 90:cb3d968589d8 83 #include "MK64F12.h"
Kojto 90:cb3d968589d8 84 #include "fsl_bitaccess.h"
Kojto 90:cb3d968589d8 85
Kojto 90:cb3d968589d8 86 /*
Kojto 90:cb3d968589d8 87 * MK64F12 MCM
Kojto 90:cb3d968589d8 88 *
Kojto 90:cb3d968589d8 89 * Core Platform Miscellaneous Control Module
Kojto 90:cb3d968589d8 90 *
Kojto 90:cb3d968589d8 91 * Registers defined in this header file:
Kojto 90:cb3d968589d8 92 * - HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
Kojto 90:cb3d968589d8 93 * - HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
Kojto 90:cb3d968589d8 94 * - HW_MCM_CR - Control Register
Kojto 90:cb3d968589d8 95 * - HW_MCM_ISCR - Interrupt Status Register
Kojto 90:cb3d968589d8 96 * - HW_MCM_ETBCC - ETB Counter Control register
Kojto 90:cb3d968589d8 97 * - HW_MCM_ETBRL - ETB Reload register
Kojto 90:cb3d968589d8 98 * - HW_MCM_ETBCNT - ETB Counter Value register
Kojto 90:cb3d968589d8 99 * - HW_MCM_PID - Process ID register
Kojto 90:cb3d968589d8 100 *
Kojto 90:cb3d968589d8 101 * - hw_mcm_t - Struct containing all module registers.
Kojto 90:cb3d968589d8 102 */
Kojto 90:cb3d968589d8 103
Kojto 90:cb3d968589d8 104 #define HW_MCM_INSTANCE_COUNT (1U) /*!< Number of instances of the MCM module. */
Kojto 90:cb3d968589d8 105
Kojto 90:cb3d968589d8 106 /*******************************************************************************
Kojto 90:cb3d968589d8 107 * HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
Kojto 90:cb3d968589d8 108 ******************************************************************************/
Kojto 90:cb3d968589d8 109
Kojto 90:cb3d968589d8 110 /*!
Kojto 90:cb3d968589d8 111 * @brief HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO)
Kojto 90:cb3d968589d8 112 *
Kojto 90:cb3d968589d8 113 * Reset value: 0x001FU
Kojto 90:cb3d968589d8 114 *
Kojto 90:cb3d968589d8 115 * PLASC is a 16-bit read-only register identifying the presence/absence of bus
Kojto 90:cb3d968589d8 116 * slave connections to the device's crossbar switch.
Kojto 90:cb3d968589d8 117 */
Kojto 90:cb3d968589d8 118 typedef union _hw_mcm_plasc
Kojto 90:cb3d968589d8 119 {
Kojto 90:cb3d968589d8 120 uint16_t U;
Kojto 90:cb3d968589d8 121 struct _hw_mcm_plasc_bitfields
Kojto 90:cb3d968589d8 122 {
Kojto 90:cb3d968589d8 123 uint16_t ASC : 8; /*!< [7:0] Each bit in the ASC field indicates
Kojto 90:cb3d968589d8 124 * whether there is a corresponding connection to the crossbar switch's slave
Kojto 90:cb3d968589d8 125 * input port. */
Kojto 90:cb3d968589d8 126 uint16_t RESERVED0 : 8; /*!< [15:8] */
Kojto 90:cb3d968589d8 127 } B;
Kojto 90:cb3d968589d8 128 } hw_mcm_plasc_t;
Kojto 90:cb3d968589d8 129
Kojto 90:cb3d968589d8 130 /*!
Kojto 90:cb3d968589d8 131 * @name Constants and macros for entire MCM_PLASC register
Kojto 90:cb3d968589d8 132 */
Kojto 90:cb3d968589d8 133 /*@{*/
Kojto 90:cb3d968589d8 134 #define HW_MCM_PLASC_ADDR(x) ((x) + 0x8U)
Kojto 90:cb3d968589d8 135
Kojto 90:cb3d968589d8 136 #define HW_MCM_PLASC(x) (*(__I hw_mcm_plasc_t *) HW_MCM_PLASC_ADDR(x))
Kojto 90:cb3d968589d8 137 #define HW_MCM_PLASC_RD(x) (HW_MCM_PLASC(x).U)
Kojto 90:cb3d968589d8 138 /*@}*/
Kojto 90:cb3d968589d8 139
Kojto 90:cb3d968589d8 140 /*
Kojto 90:cb3d968589d8 141 * Constants & macros for individual MCM_PLASC bitfields
Kojto 90:cb3d968589d8 142 */
Kojto 90:cb3d968589d8 143
Kojto 90:cb3d968589d8 144 /*!
Kojto 90:cb3d968589d8 145 * @name Register MCM_PLASC, field ASC[7:0] (RO)
Kojto 90:cb3d968589d8 146 *
Kojto 90:cb3d968589d8 147 * Values:
Kojto 90:cb3d968589d8 148 * - 0 - A bus slave connection to AXBS input port n is absent
Kojto 90:cb3d968589d8 149 * - 1 - A bus slave connection to AXBS input port n is present
Kojto 90:cb3d968589d8 150 */
Kojto 90:cb3d968589d8 151 /*@{*/
Kojto 90:cb3d968589d8 152 #define BP_MCM_PLASC_ASC (0U) /*!< Bit position for MCM_PLASC_ASC. */
Kojto 90:cb3d968589d8 153 #define BM_MCM_PLASC_ASC (0x00FFU) /*!< Bit mask for MCM_PLASC_ASC. */
Kojto 90:cb3d968589d8 154 #define BS_MCM_PLASC_ASC (8U) /*!< Bit field size in bits for MCM_PLASC_ASC. */
Kojto 90:cb3d968589d8 155
Kojto 90:cb3d968589d8 156 /*! @brief Read current value of the MCM_PLASC_ASC field. */
Kojto 90:cb3d968589d8 157 #define BR_MCM_PLASC_ASC(x) (HW_MCM_PLASC(x).B.ASC)
Kojto 90:cb3d968589d8 158 /*@}*/
Kojto 90:cb3d968589d8 159
Kojto 90:cb3d968589d8 160 /*******************************************************************************
Kojto 90:cb3d968589d8 161 * HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
Kojto 90:cb3d968589d8 162 ******************************************************************************/
Kojto 90:cb3d968589d8 163
Kojto 90:cb3d968589d8 164 /*!
Kojto 90:cb3d968589d8 165 * @brief HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO)
Kojto 90:cb3d968589d8 166 *
Kojto 90:cb3d968589d8 167 * Reset value: 0x0037U
Kojto 90:cb3d968589d8 168 *
Kojto 90:cb3d968589d8 169 * PLAMC is a 16-bit read-only register identifying the presence/absence of bus
Kojto 90:cb3d968589d8 170 * master connections to the device's crossbar switch.
Kojto 90:cb3d968589d8 171 */
Kojto 90:cb3d968589d8 172 typedef union _hw_mcm_plamc
Kojto 90:cb3d968589d8 173 {
Kojto 90:cb3d968589d8 174 uint16_t U;
Kojto 90:cb3d968589d8 175 struct _hw_mcm_plamc_bitfields
Kojto 90:cb3d968589d8 176 {
Kojto 90:cb3d968589d8 177 uint16_t AMC : 8; /*!< [7:0] Each bit in the AMC field indicates
Kojto 90:cb3d968589d8 178 * whether there is a corresponding connection to the AXBS master input port. */
Kojto 90:cb3d968589d8 179 uint16_t RESERVED0 : 8; /*!< [15:8] */
Kojto 90:cb3d968589d8 180 } B;
Kojto 90:cb3d968589d8 181 } hw_mcm_plamc_t;
Kojto 90:cb3d968589d8 182
Kojto 90:cb3d968589d8 183 /*!
Kojto 90:cb3d968589d8 184 * @name Constants and macros for entire MCM_PLAMC register
Kojto 90:cb3d968589d8 185 */
Kojto 90:cb3d968589d8 186 /*@{*/
Kojto 90:cb3d968589d8 187 #define HW_MCM_PLAMC_ADDR(x) ((x) + 0xAU)
Kojto 90:cb3d968589d8 188
Kojto 90:cb3d968589d8 189 #define HW_MCM_PLAMC(x) (*(__I hw_mcm_plamc_t *) HW_MCM_PLAMC_ADDR(x))
Kojto 90:cb3d968589d8 190 #define HW_MCM_PLAMC_RD(x) (HW_MCM_PLAMC(x).U)
Kojto 90:cb3d968589d8 191 /*@}*/
Kojto 90:cb3d968589d8 192
Kojto 90:cb3d968589d8 193 /*
Kojto 90:cb3d968589d8 194 * Constants & macros for individual MCM_PLAMC bitfields
Kojto 90:cb3d968589d8 195 */
Kojto 90:cb3d968589d8 196
Kojto 90:cb3d968589d8 197 /*!
Kojto 90:cb3d968589d8 198 * @name Register MCM_PLAMC, field AMC[7:0] (RO)
Kojto 90:cb3d968589d8 199 *
Kojto 90:cb3d968589d8 200 * Values:
Kojto 90:cb3d968589d8 201 * - 0 - A bus master connection to AXBS input port n is absent
Kojto 90:cb3d968589d8 202 * - 1 - A bus master connection to AXBS input port n is present
Kojto 90:cb3d968589d8 203 */
Kojto 90:cb3d968589d8 204 /*@{*/
Kojto 90:cb3d968589d8 205 #define BP_MCM_PLAMC_AMC (0U) /*!< Bit position for MCM_PLAMC_AMC. */
Kojto 90:cb3d968589d8 206 #define BM_MCM_PLAMC_AMC (0x00FFU) /*!< Bit mask for MCM_PLAMC_AMC. */
Kojto 90:cb3d968589d8 207 #define BS_MCM_PLAMC_AMC (8U) /*!< Bit field size in bits for MCM_PLAMC_AMC. */
Kojto 90:cb3d968589d8 208
Kojto 90:cb3d968589d8 209 /*! @brief Read current value of the MCM_PLAMC_AMC field. */
Kojto 90:cb3d968589d8 210 #define BR_MCM_PLAMC_AMC(x) (HW_MCM_PLAMC(x).B.AMC)
Kojto 90:cb3d968589d8 211 /*@}*/
Kojto 90:cb3d968589d8 212
Kojto 90:cb3d968589d8 213 /*******************************************************************************
Kojto 90:cb3d968589d8 214 * HW_MCM_CR - Control Register
Kojto 90:cb3d968589d8 215 ******************************************************************************/
Kojto 90:cb3d968589d8 216
Kojto 90:cb3d968589d8 217 /*!
Kojto 90:cb3d968589d8 218 * @brief HW_MCM_CR - Control Register (RW)
Kojto 90:cb3d968589d8 219 *
Kojto 90:cb3d968589d8 220 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 221 *
Kojto 90:cb3d968589d8 222 * CR defines the arbitration and protection schemes for the two system RAM
Kojto 90:cb3d968589d8 223 * arrays.
Kojto 90:cb3d968589d8 224 */
Kojto 90:cb3d968589d8 225 typedef union _hw_mcm_cr
Kojto 90:cb3d968589d8 226 {
Kojto 90:cb3d968589d8 227 uint32_t U;
Kojto 90:cb3d968589d8 228 struct _hw_mcm_cr_bitfields
Kojto 90:cb3d968589d8 229 {
Kojto 90:cb3d968589d8 230 uint32_t RESERVED0 : 24; /*!< [23:0] */
Kojto 90:cb3d968589d8 231 uint32_t SRAMUAP : 2; /*!< [25:24] SRAM_U arbitration priority */
Kojto 90:cb3d968589d8 232 uint32_t SRAMUWP : 1; /*!< [26] SRAM_U write protect */
Kojto 90:cb3d968589d8 233 uint32_t RESERVED1 : 1; /*!< [27] */
Kojto 90:cb3d968589d8 234 uint32_t SRAMLAP : 2; /*!< [29:28] SRAM_L arbitration priority */
Kojto 90:cb3d968589d8 235 uint32_t SRAMLWP : 1; /*!< [30] SRAM_L Write Protect */
Kojto 90:cb3d968589d8 236 uint32_t RESERVED2 : 1; /*!< [31] */
Kojto 90:cb3d968589d8 237 } B;
Kojto 90:cb3d968589d8 238 } hw_mcm_cr_t;
Kojto 90:cb3d968589d8 239
Kojto 90:cb3d968589d8 240 /*!
Kojto 90:cb3d968589d8 241 * @name Constants and macros for entire MCM_CR register
Kojto 90:cb3d968589d8 242 */
Kojto 90:cb3d968589d8 243 /*@{*/
Kojto 90:cb3d968589d8 244 #define HW_MCM_CR_ADDR(x) ((x) + 0xCU)
Kojto 90:cb3d968589d8 245
Kojto 90:cb3d968589d8 246 #define HW_MCM_CR(x) (*(__IO hw_mcm_cr_t *) HW_MCM_CR_ADDR(x))
Kojto 90:cb3d968589d8 247 #define HW_MCM_CR_RD(x) (HW_MCM_CR(x).U)
Kojto 90:cb3d968589d8 248 #define HW_MCM_CR_WR(x, v) (HW_MCM_CR(x).U = (v))
Kojto 90:cb3d968589d8 249 #define HW_MCM_CR_SET(x, v) (HW_MCM_CR_WR(x, HW_MCM_CR_RD(x) | (v)))
Kojto 90:cb3d968589d8 250 #define HW_MCM_CR_CLR(x, v) (HW_MCM_CR_WR(x, HW_MCM_CR_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 251 #define HW_MCM_CR_TOG(x, v) (HW_MCM_CR_WR(x, HW_MCM_CR_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 252 /*@}*/
Kojto 90:cb3d968589d8 253
Kojto 90:cb3d968589d8 254 /*
Kojto 90:cb3d968589d8 255 * Constants & macros for individual MCM_CR bitfields
Kojto 90:cb3d968589d8 256 */
Kojto 90:cb3d968589d8 257
Kojto 90:cb3d968589d8 258 /*!
Kojto 90:cb3d968589d8 259 * @name Register MCM_CR, field SRAMUAP[25:24] (RW)
Kojto 90:cb3d968589d8 260 *
Kojto 90:cb3d968589d8 261 * Defines the arbitration scheme and priority for the processor and SRAM
Kojto 90:cb3d968589d8 262 * backdoor accesses to the SRAM_U array.
Kojto 90:cb3d968589d8 263 *
Kojto 90:cb3d968589d8 264 * Values:
Kojto 90:cb3d968589d8 265 * - 00 - Round robin
Kojto 90:cb3d968589d8 266 * - 01 - Special round robin (favors SRAM backoor accesses over the processor)
Kojto 90:cb3d968589d8 267 * - 10 - Fixed priority. Processor has highest, backdoor has lowest
Kojto 90:cb3d968589d8 268 * - 11 - Fixed priority. Backdoor has highest, processor has lowest
Kojto 90:cb3d968589d8 269 */
Kojto 90:cb3d968589d8 270 /*@{*/
Kojto 90:cb3d968589d8 271 #define BP_MCM_CR_SRAMUAP (24U) /*!< Bit position for MCM_CR_SRAMUAP. */
Kojto 90:cb3d968589d8 272 #define BM_MCM_CR_SRAMUAP (0x03000000U) /*!< Bit mask for MCM_CR_SRAMUAP. */
Kojto 90:cb3d968589d8 273 #define BS_MCM_CR_SRAMUAP (2U) /*!< Bit field size in bits for MCM_CR_SRAMUAP. */
Kojto 90:cb3d968589d8 274
Kojto 90:cb3d968589d8 275 /*! @brief Read current value of the MCM_CR_SRAMUAP field. */
Kojto 90:cb3d968589d8 276 #define BR_MCM_CR_SRAMUAP(x) (HW_MCM_CR(x).B.SRAMUAP)
Kojto 90:cb3d968589d8 277
Kojto 90:cb3d968589d8 278 /*! @brief Format value for bitfield MCM_CR_SRAMUAP. */
Kojto 90:cb3d968589d8 279 #define BF_MCM_CR_SRAMUAP(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CR_SRAMUAP) & BM_MCM_CR_SRAMUAP)
Kojto 90:cb3d968589d8 280
Kojto 90:cb3d968589d8 281 /*! @brief Set the SRAMUAP field to a new value. */
Kojto 90:cb3d968589d8 282 #define BW_MCM_CR_SRAMUAP(x, v) (HW_MCM_CR_WR(x, (HW_MCM_CR_RD(x) & ~BM_MCM_CR_SRAMUAP) | BF_MCM_CR_SRAMUAP(v)))
Kojto 90:cb3d968589d8 283 /*@}*/
Kojto 90:cb3d968589d8 284
Kojto 90:cb3d968589d8 285 /*!
Kojto 90:cb3d968589d8 286 * @name Register MCM_CR, field SRAMUWP[26] (RW)
Kojto 90:cb3d968589d8 287 *
Kojto 90:cb3d968589d8 288 * When this bit is set, writes to SRAM_U array generates a bus error.
Kojto 90:cb3d968589d8 289 */
Kojto 90:cb3d968589d8 290 /*@{*/
Kojto 90:cb3d968589d8 291 #define BP_MCM_CR_SRAMUWP (26U) /*!< Bit position for MCM_CR_SRAMUWP. */
Kojto 90:cb3d968589d8 292 #define BM_MCM_CR_SRAMUWP (0x04000000U) /*!< Bit mask for MCM_CR_SRAMUWP. */
Kojto 90:cb3d968589d8 293 #define BS_MCM_CR_SRAMUWP (1U) /*!< Bit field size in bits for MCM_CR_SRAMUWP. */
Kojto 90:cb3d968589d8 294
Kojto 90:cb3d968589d8 295 /*! @brief Read current value of the MCM_CR_SRAMUWP field. */
Kojto 90:cb3d968589d8 296 #define BR_MCM_CR_SRAMUWP(x) (HW_MCM_CR(x).B.SRAMUWP)
Kojto 90:cb3d968589d8 297
Kojto 90:cb3d968589d8 298 /*! @brief Format value for bitfield MCM_CR_SRAMUWP. */
Kojto 90:cb3d968589d8 299 #define BF_MCM_CR_SRAMUWP(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CR_SRAMUWP) & BM_MCM_CR_SRAMUWP)
Kojto 90:cb3d968589d8 300
Kojto 90:cb3d968589d8 301 /*! @brief Set the SRAMUWP field to a new value. */
Kojto 90:cb3d968589d8 302 #define BW_MCM_CR_SRAMUWP(x, v) (HW_MCM_CR_WR(x, (HW_MCM_CR_RD(x) & ~BM_MCM_CR_SRAMUWP) | BF_MCM_CR_SRAMUWP(v)))
Kojto 90:cb3d968589d8 303 /*@}*/
Kojto 90:cb3d968589d8 304
Kojto 90:cb3d968589d8 305 /*!
Kojto 90:cb3d968589d8 306 * @name Register MCM_CR, field SRAMLAP[29:28] (RW)
Kojto 90:cb3d968589d8 307 *
Kojto 90:cb3d968589d8 308 * Defines the arbitration scheme and priority for the processor and SRAM
Kojto 90:cb3d968589d8 309 * backdoor accesses to the SRAM_L array.
Kojto 90:cb3d968589d8 310 *
Kojto 90:cb3d968589d8 311 * Values:
Kojto 90:cb3d968589d8 312 * - 00 - Round robin
Kojto 90:cb3d968589d8 313 * - 01 - Special round robin (favors SRAM backoor accesses over the processor)
Kojto 90:cb3d968589d8 314 * - 10 - Fixed priority. Processor has highest, backdoor has lowest
Kojto 90:cb3d968589d8 315 * - 11 - Fixed priority. Backdoor has highest, processor has lowest
Kojto 90:cb3d968589d8 316 */
Kojto 90:cb3d968589d8 317 /*@{*/
Kojto 90:cb3d968589d8 318 #define BP_MCM_CR_SRAMLAP (28U) /*!< Bit position for MCM_CR_SRAMLAP. */
Kojto 90:cb3d968589d8 319 #define BM_MCM_CR_SRAMLAP (0x30000000U) /*!< Bit mask for MCM_CR_SRAMLAP. */
Kojto 90:cb3d968589d8 320 #define BS_MCM_CR_SRAMLAP (2U) /*!< Bit field size in bits for MCM_CR_SRAMLAP. */
Kojto 90:cb3d968589d8 321
Kojto 90:cb3d968589d8 322 /*! @brief Read current value of the MCM_CR_SRAMLAP field. */
Kojto 90:cb3d968589d8 323 #define BR_MCM_CR_SRAMLAP(x) (HW_MCM_CR(x).B.SRAMLAP)
Kojto 90:cb3d968589d8 324
Kojto 90:cb3d968589d8 325 /*! @brief Format value for bitfield MCM_CR_SRAMLAP. */
Kojto 90:cb3d968589d8 326 #define BF_MCM_CR_SRAMLAP(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CR_SRAMLAP) & BM_MCM_CR_SRAMLAP)
Kojto 90:cb3d968589d8 327
Kojto 90:cb3d968589d8 328 /*! @brief Set the SRAMLAP field to a new value. */
Kojto 90:cb3d968589d8 329 #define BW_MCM_CR_SRAMLAP(x, v) (HW_MCM_CR_WR(x, (HW_MCM_CR_RD(x) & ~BM_MCM_CR_SRAMLAP) | BF_MCM_CR_SRAMLAP(v)))
Kojto 90:cb3d968589d8 330 /*@}*/
Kojto 90:cb3d968589d8 331
Kojto 90:cb3d968589d8 332 /*!
Kojto 90:cb3d968589d8 333 * @name Register MCM_CR, field SRAMLWP[30] (RW)
Kojto 90:cb3d968589d8 334 *
Kojto 90:cb3d968589d8 335 * When this bit is set, writes to SRAM_L array generates a bus error.
Kojto 90:cb3d968589d8 336 */
Kojto 90:cb3d968589d8 337 /*@{*/
Kojto 90:cb3d968589d8 338 #define BP_MCM_CR_SRAMLWP (30U) /*!< Bit position for MCM_CR_SRAMLWP. */
Kojto 90:cb3d968589d8 339 #define BM_MCM_CR_SRAMLWP (0x40000000U) /*!< Bit mask for MCM_CR_SRAMLWP. */
Kojto 90:cb3d968589d8 340 #define BS_MCM_CR_SRAMLWP (1U) /*!< Bit field size in bits for MCM_CR_SRAMLWP. */
Kojto 90:cb3d968589d8 341
Kojto 90:cb3d968589d8 342 /*! @brief Read current value of the MCM_CR_SRAMLWP field. */
Kojto 90:cb3d968589d8 343 #define BR_MCM_CR_SRAMLWP(x) (HW_MCM_CR(x).B.SRAMLWP)
Kojto 90:cb3d968589d8 344
Kojto 90:cb3d968589d8 345 /*! @brief Format value for bitfield MCM_CR_SRAMLWP. */
Kojto 90:cb3d968589d8 346 #define BF_MCM_CR_SRAMLWP(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CR_SRAMLWP) & BM_MCM_CR_SRAMLWP)
Kojto 90:cb3d968589d8 347
Kojto 90:cb3d968589d8 348 /*! @brief Set the SRAMLWP field to a new value. */
Kojto 90:cb3d968589d8 349 #define BW_MCM_CR_SRAMLWP(x, v) (HW_MCM_CR_WR(x, (HW_MCM_CR_RD(x) & ~BM_MCM_CR_SRAMLWP) | BF_MCM_CR_SRAMLWP(v)))
Kojto 90:cb3d968589d8 350 /*@}*/
Kojto 90:cb3d968589d8 351
Kojto 90:cb3d968589d8 352 /*******************************************************************************
Kojto 90:cb3d968589d8 353 * HW_MCM_ISCR - Interrupt Status Register
Kojto 90:cb3d968589d8 354 ******************************************************************************/
Kojto 90:cb3d968589d8 355
Kojto 90:cb3d968589d8 356 /*!
Kojto 90:cb3d968589d8 357 * @brief HW_MCM_ISCR - Interrupt Status Register (RW)
Kojto 90:cb3d968589d8 358 *
Kojto 90:cb3d968589d8 359 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 360 */
Kojto 90:cb3d968589d8 361 typedef union _hw_mcm_iscr
Kojto 90:cb3d968589d8 362 {
Kojto 90:cb3d968589d8 363 uint32_t U;
Kojto 90:cb3d968589d8 364 struct _hw_mcm_iscr_bitfields
Kojto 90:cb3d968589d8 365 {
Kojto 90:cb3d968589d8 366 uint32_t RESERVED0 : 1; /*!< [0] */
Kojto 90:cb3d968589d8 367 uint32_t IRQ : 1; /*!< [1] Normal Interrupt Pending */
Kojto 90:cb3d968589d8 368 uint32_t NMI : 1; /*!< [2] Non-maskable Interrupt Pending */
Kojto 90:cb3d968589d8 369 uint32_t DHREQ : 1; /*!< [3] Debug Halt Request Indicator */
Kojto 90:cb3d968589d8 370 uint32_t RESERVED1 : 4; /*!< [7:4] */
Kojto 90:cb3d968589d8 371 uint32_t FIOC : 1; /*!< [8] FPU invalid operation interrupt status */
Kojto 90:cb3d968589d8 372 uint32_t FDZC : 1; /*!< [9] FPU divide-by-zero interrupt status */
Kojto 90:cb3d968589d8 373 uint32_t FOFC : 1; /*!< [10] FPU overflow interrupt status */
Kojto 90:cb3d968589d8 374 uint32_t FUFC : 1; /*!< [11] FPU underflow interrupt status */
Kojto 90:cb3d968589d8 375 uint32_t FIXC : 1; /*!< [12] FPU inexact interrupt status */
Kojto 90:cb3d968589d8 376 uint32_t RESERVED2 : 2; /*!< [14:13] */
Kojto 90:cb3d968589d8 377 uint32_t FIDC : 1; /*!< [15] FPU input denormal interrupt status */
Kojto 90:cb3d968589d8 378 uint32_t RESERVED3 : 8; /*!< [23:16] */
Kojto 90:cb3d968589d8 379 uint32_t FIOCE : 1; /*!< [24] FPU invalid operation interrupt enable
Kojto 90:cb3d968589d8 380 * */
Kojto 90:cb3d968589d8 381 uint32_t FDZCE : 1; /*!< [25] FPU divide-by-zero interrupt enable */
Kojto 90:cb3d968589d8 382 uint32_t FOFCE : 1; /*!< [26] FPU overflow interrupt enable */
Kojto 90:cb3d968589d8 383 uint32_t FUFCE : 1; /*!< [27] FPU underflow interrupt enable */
Kojto 90:cb3d968589d8 384 uint32_t FIXCE : 1; /*!< [28] FPU inexact interrupt enable */
Kojto 90:cb3d968589d8 385 uint32_t RESERVED4 : 2; /*!< [30:29] */
Kojto 90:cb3d968589d8 386 uint32_t FIDCE : 1; /*!< [31] FPU input denormal interrupt enable */
Kojto 90:cb3d968589d8 387 } B;
Kojto 90:cb3d968589d8 388 } hw_mcm_iscr_t;
Kojto 90:cb3d968589d8 389
Kojto 90:cb3d968589d8 390 /*!
Kojto 90:cb3d968589d8 391 * @name Constants and macros for entire MCM_ISCR register
Kojto 90:cb3d968589d8 392 */
Kojto 90:cb3d968589d8 393 /*@{*/
Kojto 90:cb3d968589d8 394 #define HW_MCM_ISCR_ADDR(x) ((x) + 0x10U)
Kojto 90:cb3d968589d8 395
Kojto 90:cb3d968589d8 396 #define HW_MCM_ISCR(x) (*(__IO hw_mcm_iscr_t *) HW_MCM_ISCR_ADDR(x))
Kojto 90:cb3d968589d8 397 #define HW_MCM_ISCR_RD(x) (HW_MCM_ISCR(x).U)
Kojto 90:cb3d968589d8 398 #define HW_MCM_ISCR_WR(x, v) (HW_MCM_ISCR(x).U = (v))
Kojto 90:cb3d968589d8 399 #define HW_MCM_ISCR_SET(x, v) (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) | (v)))
Kojto 90:cb3d968589d8 400 #define HW_MCM_ISCR_CLR(x, v) (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 401 #define HW_MCM_ISCR_TOG(x, v) (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 402 /*@}*/
Kojto 90:cb3d968589d8 403
Kojto 90:cb3d968589d8 404 /*
Kojto 90:cb3d968589d8 405 * Constants & macros for individual MCM_ISCR bitfields
Kojto 90:cb3d968589d8 406 */
Kojto 90:cb3d968589d8 407
Kojto 90:cb3d968589d8 408 /*!
Kojto 90:cb3d968589d8 409 * @name Register MCM_ISCR, field IRQ[1] (W1C)
Kojto 90:cb3d968589d8 410 *
Kojto 90:cb3d968589d8 411 * If ETBCC[RSPT] is set to 01b, this bit is set when the ETB counter expires.
Kojto 90:cb3d968589d8 412 *
Kojto 90:cb3d968589d8 413 * Values:
Kojto 90:cb3d968589d8 414 * - 0 - No pending interrupt
Kojto 90:cb3d968589d8 415 * - 1 - Due to the ETB counter expiring, a normal interrupt is pending
Kojto 90:cb3d968589d8 416 */
Kojto 90:cb3d968589d8 417 /*@{*/
Kojto 90:cb3d968589d8 418 #define BP_MCM_ISCR_IRQ (1U) /*!< Bit position for MCM_ISCR_IRQ. */
Kojto 90:cb3d968589d8 419 #define BM_MCM_ISCR_IRQ (0x00000002U) /*!< Bit mask for MCM_ISCR_IRQ. */
Kojto 90:cb3d968589d8 420 #define BS_MCM_ISCR_IRQ (1U) /*!< Bit field size in bits for MCM_ISCR_IRQ. */
Kojto 90:cb3d968589d8 421
Kojto 90:cb3d968589d8 422 /*! @brief Read current value of the MCM_ISCR_IRQ field. */
Kojto 90:cb3d968589d8 423 #define BR_MCM_ISCR_IRQ(x) (HW_MCM_ISCR(x).B.IRQ)
Kojto 90:cb3d968589d8 424
Kojto 90:cb3d968589d8 425 /*! @brief Format value for bitfield MCM_ISCR_IRQ. */
Kojto 90:cb3d968589d8 426 #define BF_MCM_ISCR_IRQ(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_IRQ) & BM_MCM_ISCR_IRQ)
Kojto 90:cb3d968589d8 427
Kojto 90:cb3d968589d8 428 /*! @brief Set the IRQ field to a new value. */
Kojto 90:cb3d968589d8 429 #define BW_MCM_ISCR_IRQ(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_IRQ) | BF_MCM_ISCR_IRQ(v)))
Kojto 90:cb3d968589d8 430 /*@}*/
Kojto 90:cb3d968589d8 431
Kojto 90:cb3d968589d8 432 /*!
Kojto 90:cb3d968589d8 433 * @name Register MCM_ISCR, field NMI[2] (W1C)
Kojto 90:cb3d968589d8 434 *
Kojto 90:cb3d968589d8 435 * If ETBCC[RSPT] is set to 10b, this bit is set when the ETB counter expires.
Kojto 90:cb3d968589d8 436 *
Kojto 90:cb3d968589d8 437 * Values:
Kojto 90:cb3d968589d8 438 * - 0 - No pending NMI
Kojto 90:cb3d968589d8 439 * - 1 - Due to the ETB counter expiring, an NMI is pending
Kojto 90:cb3d968589d8 440 */
Kojto 90:cb3d968589d8 441 /*@{*/
Kojto 90:cb3d968589d8 442 #define BP_MCM_ISCR_NMI (2U) /*!< Bit position for MCM_ISCR_NMI. */
Kojto 90:cb3d968589d8 443 #define BM_MCM_ISCR_NMI (0x00000004U) /*!< Bit mask for MCM_ISCR_NMI. */
Kojto 90:cb3d968589d8 444 #define BS_MCM_ISCR_NMI (1U) /*!< Bit field size in bits for MCM_ISCR_NMI. */
Kojto 90:cb3d968589d8 445
Kojto 90:cb3d968589d8 446 /*! @brief Read current value of the MCM_ISCR_NMI field. */
Kojto 90:cb3d968589d8 447 #define BR_MCM_ISCR_NMI(x) (HW_MCM_ISCR(x).B.NMI)
Kojto 90:cb3d968589d8 448
Kojto 90:cb3d968589d8 449 /*! @brief Format value for bitfield MCM_ISCR_NMI. */
Kojto 90:cb3d968589d8 450 #define BF_MCM_ISCR_NMI(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_NMI) & BM_MCM_ISCR_NMI)
Kojto 90:cb3d968589d8 451
Kojto 90:cb3d968589d8 452 /*! @brief Set the NMI field to a new value. */
Kojto 90:cb3d968589d8 453 #define BW_MCM_ISCR_NMI(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_NMI) | BF_MCM_ISCR_NMI(v)))
Kojto 90:cb3d968589d8 454 /*@}*/
Kojto 90:cb3d968589d8 455
Kojto 90:cb3d968589d8 456 /*!
Kojto 90:cb3d968589d8 457 * @name Register MCM_ISCR, field DHREQ[3] (RO)
Kojto 90:cb3d968589d8 458 *
Kojto 90:cb3d968589d8 459 * Indicates that a debug halt request is initiated due to a ETB counter
Kojto 90:cb3d968589d8 460 * expiration, ETBCC[2:0] = 3b111 & ETBCV[10:0] = 11h0. This bit is cleared when the
Kojto 90:cb3d968589d8 461 * counter is disabled or when the ETB counter is reloaded.
Kojto 90:cb3d968589d8 462 *
Kojto 90:cb3d968589d8 463 * Values:
Kojto 90:cb3d968589d8 464 * - 0 - No debug halt request
Kojto 90:cb3d968589d8 465 * - 1 - Debug halt request initiated
Kojto 90:cb3d968589d8 466 */
Kojto 90:cb3d968589d8 467 /*@{*/
Kojto 90:cb3d968589d8 468 #define BP_MCM_ISCR_DHREQ (3U) /*!< Bit position for MCM_ISCR_DHREQ. */
Kojto 90:cb3d968589d8 469 #define BM_MCM_ISCR_DHREQ (0x00000008U) /*!< Bit mask for MCM_ISCR_DHREQ. */
Kojto 90:cb3d968589d8 470 #define BS_MCM_ISCR_DHREQ (1U) /*!< Bit field size in bits for MCM_ISCR_DHREQ. */
Kojto 90:cb3d968589d8 471
Kojto 90:cb3d968589d8 472 /*! @brief Read current value of the MCM_ISCR_DHREQ field. */
Kojto 90:cb3d968589d8 473 #define BR_MCM_ISCR_DHREQ(x) (HW_MCM_ISCR(x).B.DHREQ)
Kojto 90:cb3d968589d8 474 /*@}*/
Kojto 90:cb3d968589d8 475
Kojto 90:cb3d968589d8 476 /*!
Kojto 90:cb3d968589d8 477 * @name Register MCM_ISCR, field FIOC[8] (RO)
Kojto 90:cb3d968589d8 478 *
Kojto 90:cb3d968589d8 479 * This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an
Kojto 90:cb3d968589d8 480 * illegal operation has been detected in the processor's FPU. Once set, this bit
Kojto 90:cb3d968589d8 481 * remains set until software clears the FPSCR[IOC] bit.
Kojto 90:cb3d968589d8 482 *
Kojto 90:cb3d968589d8 483 * Values:
Kojto 90:cb3d968589d8 484 * - 0 - No interrupt
Kojto 90:cb3d968589d8 485 * - 1 - Interrupt occurred
Kojto 90:cb3d968589d8 486 */
Kojto 90:cb3d968589d8 487 /*@{*/
Kojto 90:cb3d968589d8 488 #define BP_MCM_ISCR_FIOC (8U) /*!< Bit position for MCM_ISCR_FIOC. */
Kojto 90:cb3d968589d8 489 #define BM_MCM_ISCR_FIOC (0x00000100U) /*!< Bit mask for MCM_ISCR_FIOC. */
Kojto 90:cb3d968589d8 490 #define BS_MCM_ISCR_FIOC (1U) /*!< Bit field size in bits for MCM_ISCR_FIOC. */
Kojto 90:cb3d968589d8 491
Kojto 90:cb3d968589d8 492 /*! @brief Read current value of the MCM_ISCR_FIOC field. */
Kojto 90:cb3d968589d8 493 #define BR_MCM_ISCR_FIOC(x) (HW_MCM_ISCR(x).B.FIOC)
Kojto 90:cb3d968589d8 494 /*@}*/
Kojto 90:cb3d968589d8 495
Kojto 90:cb3d968589d8 496 /*!
Kojto 90:cb3d968589d8 497 * @name Register MCM_ISCR, field FDZC[9] (RO)
Kojto 90:cb3d968589d8 498 *
Kojto 90:cb3d968589d8 499 * This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a
Kojto 90:cb3d968589d8 500 * divide by zero has been detected in the processor's FPU. Once set, this bit remains
Kojto 90:cb3d968589d8 501 * set until software clears the FPSCR[DZC] bit.
Kojto 90:cb3d968589d8 502 *
Kojto 90:cb3d968589d8 503 * Values:
Kojto 90:cb3d968589d8 504 * - 0 - No interrupt
Kojto 90:cb3d968589d8 505 * - 1 - Interrupt occurred
Kojto 90:cb3d968589d8 506 */
Kojto 90:cb3d968589d8 507 /*@{*/
Kojto 90:cb3d968589d8 508 #define BP_MCM_ISCR_FDZC (9U) /*!< Bit position for MCM_ISCR_FDZC. */
Kojto 90:cb3d968589d8 509 #define BM_MCM_ISCR_FDZC (0x00000200U) /*!< Bit mask for MCM_ISCR_FDZC. */
Kojto 90:cb3d968589d8 510 #define BS_MCM_ISCR_FDZC (1U) /*!< Bit field size in bits for MCM_ISCR_FDZC. */
Kojto 90:cb3d968589d8 511
Kojto 90:cb3d968589d8 512 /*! @brief Read current value of the MCM_ISCR_FDZC field. */
Kojto 90:cb3d968589d8 513 #define BR_MCM_ISCR_FDZC(x) (HW_MCM_ISCR(x).B.FDZC)
Kojto 90:cb3d968589d8 514 /*@}*/
Kojto 90:cb3d968589d8 515
Kojto 90:cb3d968589d8 516 /*!
Kojto 90:cb3d968589d8 517 * @name Register MCM_ISCR, field FOFC[10] (RO)
Kojto 90:cb3d968589d8 518 *
Kojto 90:cb3d968589d8 519 * This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an
Kojto 90:cb3d968589d8 520 * overflow has been detected in the processor's FPU. Once set, this bit remains set
Kojto 90:cb3d968589d8 521 * until software clears the FPSCR[OFC] bit.
Kojto 90:cb3d968589d8 522 *
Kojto 90:cb3d968589d8 523 * Values:
Kojto 90:cb3d968589d8 524 * - 0 - No interrupt
Kojto 90:cb3d968589d8 525 * - 1 - Interrupt occurred
Kojto 90:cb3d968589d8 526 */
Kojto 90:cb3d968589d8 527 /*@{*/
Kojto 90:cb3d968589d8 528 #define BP_MCM_ISCR_FOFC (10U) /*!< Bit position for MCM_ISCR_FOFC. */
Kojto 90:cb3d968589d8 529 #define BM_MCM_ISCR_FOFC (0x00000400U) /*!< Bit mask for MCM_ISCR_FOFC. */
Kojto 90:cb3d968589d8 530 #define BS_MCM_ISCR_FOFC (1U) /*!< Bit field size in bits for MCM_ISCR_FOFC. */
Kojto 90:cb3d968589d8 531
Kojto 90:cb3d968589d8 532 /*! @brief Read current value of the MCM_ISCR_FOFC field. */
Kojto 90:cb3d968589d8 533 #define BR_MCM_ISCR_FOFC(x) (HW_MCM_ISCR(x).B.FOFC)
Kojto 90:cb3d968589d8 534 /*@}*/
Kojto 90:cb3d968589d8 535
Kojto 90:cb3d968589d8 536 /*!
Kojto 90:cb3d968589d8 537 * @name Register MCM_ISCR, field FUFC[11] (RO)
Kojto 90:cb3d968589d8 538 *
Kojto 90:cb3d968589d8 539 * This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an
Kojto 90:cb3d968589d8 540 * underflow has been detected in the processor's FPU. Once set, this bit remains set
Kojto 90:cb3d968589d8 541 * until software clears the FPSCR[UFC] bit.
Kojto 90:cb3d968589d8 542 *
Kojto 90:cb3d968589d8 543 * Values:
Kojto 90:cb3d968589d8 544 * - 0 - No interrupt
Kojto 90:cb3d968589d8 545 * - 1 - Interrupt occurred
Kojto 90:cb3d968589d8 546 */
Kojto 90:cb3d968589d8 547 /*@{*/
Kojto 90:cb3d968589d8 548 #define BP_MCM_ISCR_FUFC (11U) /*!< Bit position for MCM_ISCR_FUFC. */
Kojto 90:cb3d968589d8 549 #define BM_MCM_ISCR_FUFC (0x00000800U) /*!< Bit mask for MCM_ISCR_FUFC. */
Kojto 90:cb3d968589d8 550 #define BS_MCM_ISCR_FUFC (1U) /*!< Bit field size in bits for MCM_ISCR_FUFC. */
Kojto 90:cb3d968589d8 551
Kojto 90:cb3d968589d8 552 /*! @brief Read current value of the MCM_ISCR_FUFC field. */
Kojto 90:cb3d968589d8 553 #define BR_MCM_ISCR_FUFC(x) (HW_MCM_ISCR(x).B.FUFC)
Kojto 90:cb3d968589d8 554 /*@}*/
Kojto 90:cb3d968589d8 555
Kojto 90:cb3d968589d8 556 /*!
Kojto 90:cb3d968589d8 557 * @name Register MCM_ISCR, field FIXC[12] (RO)
Kojto 90:cb3d968589d8 558 *
Kojto 90:cb3d968589d8 559 * This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an
Kojto 90:cb3d968589d8 560 * inexact number has been detected in the processor's FPU. Once set, this bit
Kojto 90:cb3d968589d8 561 * remains set until software clears the FPSCR[IXC] bit.
Kojto 90:cb3d968589d8 562 *
Kojto 90:cb3d968589d8 563 * Values:
Kojto 90:cb3d968589d8 564 * - 0 - No interrupt
Kojto 90:cb3d968589d8 565 * - 1 - Interrupt occurred
Kojto 90:cb3d968589d8 566 */
Kojto 90:cb3d968589d8 567 /*@{*/
Kojto 90:cb3d968589d8 568 #define BP_MCM_ISCR_FIXC (12U) /*!< Bit position for MCM_ISCR_FIXC. */
Kojto 90:cb3d968589d8 569 #define BM_MCM_ISCR_FIXC (0x00001000U) /*!< Bit mask for MCM_ISCR_FIXC. */
Kojto 90:cb3d968589d8 570 #define BS_MCM_ISCR_FIXC (1U) /*!< Bit field size in bits for MCM_ISCR_FIXC. */
Kojto 90:cb3d968589d8 571
Kojto 90:cb3d968589d8 572 /*! @brief Read current value of the MCM_ISCR_FIXC field. */
Kojto 90:cb3d968589d8 573 #define BR_MCM_ISCR_FIXC(x) (HW_MCM_ISCR(x).B.FIXC)
Kojto 90:cb3d968589d8 574 /*@}*/
Kojto 90:cb3d968589d8 575
Kojto 90:cb3d968589d8 576 /*!
Kojto 90:cb3d968589d8 577 * @name Register MCM_ISCR, field FIDC[15] (RO)
Kojto 90:cb3d968589d8 578 *
Kojto 90:cb3d968589d8 579 * This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input
Kojto 90:cb3d968589d8 580 * denormalized number has been detected in the processor's FPU. Once set, this
Kojto 90:cb3d968589d8 581 * bit remains set until software clears the FPSCR[IDC] bit.
Kojto 90:cb3d968589d8 582 *
Kojto 90:cb3d968589d8 583 * Values:
Kojto 90:cb3d968589d8 584 * - 0 - No interrupt
Kojto 90:cb3d968589d8 585 * - 1 - Interrupt occurred
Kojto 90:cb3d968589d8 586 */
Kojto 90:cb3d968589d8 587 /*@{*/
Kojto 90:cb3d968589d8 588 #define BP_MCM_ISCR_FIDC (15U) /*!< Bit position for MCM_ISCR_FIDC. */
Kojto 90:cb3d968589d8 589 #define BM_MCM_ISCR_FIDC (0x00008000U) /*!< Bit mask for MCM_ISCR_FIDC. */
Kojto 90:cb3d968589d8 590 #define BS_MCM_ISCR_FIDC (1U) /*!< Bit field size in bits for MCM_ISCR_FIDC. */
Kojto 90:cb3d968589d8 591
Kojto 90:cb3d968589d8 592 /*! @brief Read current value of the MCM_ISCR_FIDC field. */
Kojto 90:cb3d968589d8 593 #define BR_MCM_ISCR_FIDC(x) (HW_MCM_ISCR(x).B.FIDC)
Kojto 90:cb3d968589d8 594 /*@}*/
Kojto 90:cb3d968589d8 595
Kojto 90:cb3d968589d8 596 /*!
Kojto 90:cb3d968589d8 597 * @name Register MCM_ISCR, field FIOCE[24] (RW)
Kojto 90:cb3d968589d8 598 *
Kojto 90:cb3d968589d8 599 * Values:
Kojto 90:cb3d968589d8 600 * - 0 - Disable interrupt
Kojto 90:cb3d968589d8 601 * - 1 - Enable interrupt
Kojto 90:cb3d968589d8 602 */
Kojto 90:cb3d968589d8 603 /*@{*/
Kojto 90:cb3d968589d8 604 #define BP_MCM_ISCR_FIOCE (24U) /*!< Bit position for MCM_ISCR_FIOCE. */
Kojto 90:cb3d968589d8 605 #define BM_MCM_ISCR_FIOCE (0x01000000U) /*!< Bit mask for MCM_ISCR_FIOCE. */
Kojto 90:cb3d968589d8 606 #define BS_MCM_ISCR_FIOCE (1U) /*!< Bit field size in bits for MCM_ISCR_FIOCE. */
Kojto 90:cb3d968589d8 607
Kojto 90:cb3d968589d8 608 /*! @brief Read current value of the MCM_ISCR_FIOCE field. */
Kojto 90:cb3d968589d8 609 #define BR_MCM_ISCR_FIOCE(x) (HW_MCM_ISCR(x).B.FIOCE)
Kojto 90:cb3d968589d8 610
Kojto 90:cb3d968589d8 611 /*! @brief Format value for bitfield MCM_ISCR_FIOCE. */
Kojto 90:cb3d968589d8 612 #define BF_MCM_ISCR_FIOCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIOCE) & BM_MCM_ISCR_FIOCE)
Kojto 90:cb3d968589d8 613
Kojto 90:cb3d968589d8 614 /*! @brief Set the FIOCE field to a new value. */
Kojto 90:cb3d968589d8 615 #define BW_MCM_ISCR_FIOCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIOCE) | BF_MCM_ISCR_FIOCE(v)))
Kojto 90:cb3d968589d8 616 /*@}*/
Kojto 90:cb3d968589d8 617
Kojto 90:cb3d968589d8 618 /*!
Kojto 90:cb3d968589d8 619 * @name Register MCM_ISCR, field FDZCE[25] (RW)
Kojto 90:cb3d968589d8 620 *
Kojto 90:cb3d968589d8 621 * Values:
Kojto 90:cb3d968589d8 622 * - 0 - Disable interrupt
Kojto 90:cb3d968589d8 623 * - 1 - Enable interrupt
Kojto 90:cb3d968589d8 624 */
Kojto 90:cb3d968589d8 625 /*@{*/
Kojto 90:cb3d968589d8 626 #define BP_MCM_ISCR_FDZCE (25U) /*!< Bit position for MCM_ISCR_FDZCE. */
Kojto 90:cb3d968589d8 627 #define BM_MCM_ISCR_FDZCE (0x02000000U) /*!< Bit mask for MCM_ISCR_FDZCE. */
Kojto 90:cb3d968589d8 628 #define BS_MCM_ISCR_FDZCE (1U) /*!< Bit field size in bits for MCM_ISCR_FDZCE. */
Kojto 90:cb3d968589d8 629
Kojto 90:cb3d968589d8 630 /*! @brief Read current value of the MCM_ISCR_FDZCE field. */
Kojto 90:cb3d968589d8 631 #define BR_MCM_ISCR_FDZCE(x) (HW_MCM_ISCR(x).B.FDZCE)
Kojto 90:cb3d968589d8 632
Kojto 90:cb3d968589d8 633 /*! @brief Format value for bitfield MCM_ISCR_FDZCE. */
Kojto 90:cb3d968589d8 634 #define BF_MCM_ISCR_FDZCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FDZCE) & BM_MCM_ISCR_FDZCE)
Kojto 90:cb3d968589d8 635
Kojto 90:cb3d968589d8 636 /*! @brief Set the FDZCE field to a new value. */
Kojto 90:cb3d968589d8 637 #define BW_MCM_ISCR_FDZCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FDZCE) | BF_MCM_ISCR_FDZCE(v)))
Kojto 90:cb3d968589d8 638 /*@}*/
Kojto 90:cb3d968589d8 639
Kojto 90:cb3d968589d8 640 /*!
Kojto 90:cb3d968589d8 641 * @name Register MCM_ISCR, field FOFCE[26] (RW)
Kojto 90:cb3d968589d8 642 *
Kojto 90:cb3d968589d8 643 * Values:
Kojto 90:cb3d968589d8 644 * - 0 - Disable interrupt
Kojto 90:cb3d968589d8 645 * - 1 - Enable interrupt
Kojto 90:cb3d968589d8 646 */
Kojto 90:cb3d968589d8 647 /*@{*/
Kojto 90:cb3d968589d8 648 #define BP_MCM_ISCR_FOFCE (26U) /*!< Bit position for MCM_ISCR_FOFCE. */
Kojto 90:cb3d968589d8 649 #define BM_MCM_ISCR_FOFCE (0x04000000U) /*!< Bit mask for MCM_ISCR_FOFCE. */
Kojto 90:cb3d968589d8 650 #define BS_MCM_ISCR_FOFCE (1U) /*!< Bit field size in bits for MCM_ISCR_FOFCE. */
Kojto 90:cb3d968589d8 651
Kojto 90:cb3d968589d8 652 /*! @brief Read current value of the MCM_ISCR_FOFCE field. */
Kojto 90:cb3d968589d8 653 #define BR_MCM_ISCR_FOFCE(x) (HW_MCM_ISCR(x).B.FOFCE)
Kojto 90:cb3d968589d8 654
Kojto 90:cb3d968589d8 655 /*! @brief Format value for bitfield MCM_ISCR_FOFCE. */
Kojto 90:cb3d968589d8 656 #define BF_MCM_ISCR_FOFCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FOFCE) & BM_MCM_ISCR_FOFCE)
Kojto 90:cb3d968589d8 657
Kojto 90:cb3d968589d8 658 /*! @brief Set the FOFCE field to a new value. */
Kojto 90:cb3d968589d8 659 #define BW_MCM_ISCR_FOFCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FOFCE) | BF_MCM_ISCR_FOFCE(v)))
Kojto 90:cb3d968589d8 660 /*@}*/
Kojto 90:cb3d968589d8 661
Kojto 90:cb3d968589d8 662 /*!
Kojto 90:cb3d968589d8 663 * @name Register MCM_ISCR, field FUFCE[27] (RW)
Kojto 90:cb3d968589d8 664 *
Kojto 90:cb3d968589d8 665 * Values:
Kojto 90:cb3d968589d8 666 * - 0 - Disable interrupt
Kojto 90:cb3d968589d8 667 * - 1 - Enable interrupt
Kojto 90:cb3d968589d8 668 */
Kojto 90:cb3d968589d8 669 /*@{*/
Kojto 90:cb3d968589d8 670 #define BP_MCM_ISCR_FUFCE (27U) /*!< Bit position for MCM_ISCR_FUFCE. */
Kojto 90:cb3d968589d8 671 #define BM_MCM_ISCR_FUFCE (0x08000000U) /*!< Bit mask for MCM_ISCR_FUFCE. */
Kojto 90:cb3d968589d8 672 #define BS_MCM_ISCR_FUFCE (1U) /*!< Bit field size in bits for MCM_ISCR_FUFCE. */
Kojto 90:cb3d968589d8 673
Kojto 90:cb3d968589d8 674 /*! @brief Read current value of the MCM_ISCR_FUFCE field. */
Kojto 90:cb3d968589d8 675 #define BR_MCM_ISCR_FUFCE(x) (HW_MCM_ISCR(x).B.FUFCE)
Kojto 90:cb3d968589d8 676
Kojto 90:cb3d968589d8 677 /*! @brief Format value for bitfield MCM_ISCR_FUFCE. */
Kojto 90:cb3d968589d8 678 #define BF_MCM_ISCR_FUFCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FUFCE) & BM_MCM_ISCR_FUFCE)
Kojto 90:cb3d968589d8 679
Kojto 90:cb3d968589d8 680 /*! @brief Set the FUFCE field to a new value. */
Kojto 90:cb3d968589d8 681 #define BW_MCM_ISCR_FUFCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FUFCE) | BF_MCM_ISCR_FUFCE(v)))
Kojto 90:cb3d968589d8 682 /*@}*/
Kojto 90:cb3d968589d8 683
Kojto 90:cb3d968589d8 684 /*!
Kojto 90:cb3d968589d8 685 * @name Register MCM_ISCR, field FIXCE[28] (RW)
Kojto 90:cb3d968589d8 686 *
Kojto 90:cb3d968589d8 687 * Values:
Kojto 90:cb3d968589d8 688 * - 0 - Disable interrupt
Kojto 90:cb3d968589d8 689 * - 1 - Enable interrupt
Kojto 90:cb3d968589d8 690 */
Kojto 90:cb3d968589d8 691 /*@{*/
Kojto 90:cb3d968589d8 692 #define BP_MCM_ISCR_FIXCE (28U) /*!< Bit position for MCM_ISCR_FIXCE. */
Kojto 90:cb3d968589d8 693 #define BM_MCM_ISCR_FIXCE (0x10000000U) /*!< Bit mask for MCM_ISCR_FIXCE. */
Kojto 90:cb3d968589d8 694 #define BS_MCM_ISCR_FIXCE (1U) /*!< Bit field size in bits for MCM_ISCR_FIXCE. */
Kojto 90:cb3d968589d8 695
Kojto 90:cb3d968589d8 696 /*! @brief Read current value of the MCM_ISCR_FIXCE field. */
Kojto 90:cb3d968589d8 697 #define BR_MCM_ISCR_FIXCE(x) (HW_MCM_ISCR(x).B.FIXCE)
Kojto 90:cb3d968589d8 698
Kojto 90:cb3d968589d8 699 /*! @brief Format value for bitfield MCM_ISCR_FIXCE. */
Kojto 90:cb3d968589d8 700 #define BF_MCM_ISCR_FIXCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIXCE) & BM_MCM_ISCR_FIXCE)
Kojto 90:cb3d968589d8 701
Kojto 90:cb3d968589d8 702 /*! @brief Set the FIXCE field to a new value. */
Kojto 90:cb3d968589d8 703 #define BW_MCM_ISCR_FIXCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIXCE) | BF_MCM_ISCR_FIXCE(v)))
Kojto 90:cb3d968589d8 704 /*@}*/
Kojto 90:cb3d968589d8 705
Kojto 90:cb3d968589d8 706 /*!
Kojto 90:cb3d968589d8 707 * @name Register MCM_ISCR, field FIDCE[31] (RW)
Kojto 90:cb3d968589d8 708 *
Kojto 90:cb3d968589d8 709 * Values:
Kojto 90:cb3d968589d8 710 * - 0 - Disable interrupt
Kojto 90:cb3d968589d8 711 * - 1 - Enable interrupt
Kojto 90:cb3d968589d8 712 */
Kojto 90:cb3d968589d8 713 /*@{*/
Kojto 90:cb3d968589d8 714 #define BP_MCM_ISCR_FIDCE (31U) /*!< Bit position for MCM_ISCR_FIDCE. */
Kojto 90:cb3d968589d8 715 #define BM_MCM_ISCR_FIDCE (0x80000000U) /*!< Bit mask for MCM_ISCR_FIDCE. */
Kojto 90:cb3d968589d8 716 #define BS_MCM_ISCR_FIDCE (1U) /*!< Bit field size in bits for MCM_ISCR_FIDCE. */
Kojto 90:cb3d968589d8 717
Kojto 90:cb3d968589d8 718 /*! @brief Read current value of the MCM_ISCR_FIDCE field. */
Kojto 90:cb3d968589d8 719 #define BR_MCM_ISCR_FIDCE(x) (HW_MCM_ISCR(x).B.FIDCE)
Kojto 90:cb3d968589d8 720
Kojto 90:cb3d968589d8 721 /*! @brief Format value for bitfield MCM_ISCR_FIDCE. */
Kojto 90:cb3d968589d8 722 #define BF_MCM_ISCR_FIDCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIDCE) & BM_MCM_ISCR_FIDCE)
Kojto 90:cb3d968589d8 723
Kojto 90:cb3d968589d8 724 /*! @brief Set the FIDCE field to a new value. */
Kojto 90:cb3d968589d8 725 #define BW_MCM_ISCR_FIDCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIDCE) | BF_MCM_ISCR_FIDCE(v)))
Kojto 90:cb3d968589d8 726 /*@}*/
Kojto 90:cb3d968589d8 727
Kojto 90:cb3d968589d8 728 /*******************************************************************************
Kojto 90:cb3d968589d8 729 * HW_MCM_ETBCC - ETB Counter Control register
Kojto 90:cb3d968589d8 730 ******************************************************************************/
Kojto 90:cb3d968589d8 731
Kojto 90:cb3d968589d8 732 /*!
Kojto 90:cb3d968589d8 733 * @brief HW_MCM_ETBCC - ETB Counter Control register (RW)
Kojto 90:cb3d968589d8 734 *
Kojto 90:cb3d968589d8 735 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 736 */
Kojto 90:cb3d968589d8 737 typedef union _hw_mcm_etbcc
Kojto 90:cb3d968589d8 738 {
Kojto 90:cb3d968589d8 739 uint32_t U;
Kojto 90:cb3d968589d8 740 struct _hw_mcm_etbcc_bitfields
Kojto 90:cb3d968589d8 741 {
Kojto 90:cb3d968589d8 742 uint32_t CNTEN : 1; /*!< [0] Counter Enable */
Kojto 90:cb3d968589d8 743 uint32_t RSPT : 2; /*!< [2:1] Response Type */
Kojto 90:cb3d968589d8 744 uint32_t RLRQ : 1; /*!< [3] Reload Request */
Kojto 90:cb3d968589d8 745 uint32_t ETDIS : 1; /*!< [4] ETM-To-TPIU Disable */
Kojto 90:cb3d968589d8 746 uint32_t ITDIS : 1; /*!< [5] ITM-To-TPIU Disable */
Kojto 90:cb3d968589d8 747 uint32_t RESERVED0 : 26; /*!< [31:6] */
Kojto 90:cb3d968589d8 748 } B;
Kojto 90:cb3d968589d8 749 } hw_mcm_etbcc_t;
Kojto 90:cb3d968589d8 750
Kojto 90:cb3d968589d8 751 /*!
Kojto 90:cb3d968589d8 752 * @name Constants and macros for entire MCM_ETBCC register
Kojto 90:cb3d968589d8 753 */
Kojto 90:cb3d968589d8 754 /*@{*/
Kojto 90:cb3d968589d8 755 #define HW_MCM_ETBCC_ADDR(x) ((x) + 0x14U)
Kojto 90:cb3d968589d8 756
Kojto 90:cb3d968589d8 757 #define HW_MCM_ETBCC(x) (*(__IO hw_mcm_etbcc_t *) HW_MCM_ETBCC_ADDR(x))
Kojto 90:cb3d968589d8 758 #define HW_MCM_ETBCC_RD(x) (HW_MCM_ETBCC(x).U)
Kojto 90:cb3d968589d8 759 #define HW_MCM_ETBCC_WR(x, v) (HW_MCM_ETBCC(x).U = (v))
Kojto 90:cb3d968589d8 760 #define HW_MCM_ETBCC_SET(x, v) (HW_MCM_ETBCC_WR(x, HW_MCM_ETBCC_RD(x) | (v)))
Kojto 90:cb3d968589d8 761 #define HW_MCM_ETBCC_CLR(x, v) (HW_MCM_ETBCC_WR(x, HW_MCM_ETBCC_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 762 #define HW_MCM_ETBCC_TOG(x, v) (HW_MCM_ETBCC_WR(x, HW_MCM_ETBCC_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 763 /*@}*/
Kojto 90:cb3d968589d8 764
Kojto 90:cb3d968589d8 765 /*
Kojto 90:cb3d968589d8 766 * Constants & macros for individual MCM_ETBCC bitfields
Kojto 90:cb3d968589d8 767 */
Kojto 90:cb3d968589d8 768
Kojto 90:cb3d968589d8 769 /*!
Kojto 90:cb3d968589d8 770 * @name Register MCM_ETBCC, field CNTEN[0] (RW)
Kojto 90:cb3d968589d8 771 *
Kojto 90:cb3d968589d8 772 * Enables the ETB counter.
Kojto 90:cb3d968589d8 773 *
Kojto 90:cb3d968589d8 774 * Values:
Kojto 90:cb3d968589d8 775 * - 0 - ETB counter disabled
Kojto 90:cb3d968589d8 776 * - 1 - ETB counter enabled
Kojto 90:cb3d968589d8 777 */
Kojto 90:cb3d968589d8 778 /*@{*/
Kojto 90:cb3d968589d8 779 #define BP_MCM_ETBCC_CNTEN (0U) /*!< Bit position for MCM_ETBCC_CNTEN. */
Kojto 90:cb3d968589d8 780 #define BM_MCM_ETBCC_CNTEN (0x00000001U) /*!< Bit mask for MCM_ETBCC_CNTEN. */
Kojto 90:cb3d968589d8 781 #define BS_MCM_ETBCC_CNTEN (1U) /*!< Bit field size in bits for MCM_ETBCC_CNTEN. */
Kojto 90:cb3d968589d8 782
Kojto 90:cb3d968589d8 783 /*! @brief Read current value of the MCM_ETBCC_CNTEN field. */
Kojto 90:cb3d968589d8 784 #define BR_MCM_ETBCC_CNTEN(x) (HW_MCM_ETBCC(x).B.CNTEN)
Kojto 90:cb3d968589d8 785
Kojto 90:cb3d968589d8 786 /*! @brief Format value for bitfield MCM_ETBCC_CNTEN. */
Kojto 90:cb3d968589d8 787 #define BF_MCM_ETBCC_CNTEN(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_CNTEN) & BM_MCM_ETBCC_CNTEN)
Kojto 90:cb3d968589d8 788
Kojto 90:cb3d968589d8 789 /*! @brief Set the CNTEN field to a new value. */
Kojto 90:cb3d968589d8 790 #define BW_MCM_ETBCC_CNTEN(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_CNTEN) | BF_MCM_ETBCC_CNTEN(v)))
Kojto 90:cb3d968589d8 791 /*@}*/
Kojto 90:cb3d968589d8 792
Kojto 90:cb3d968589d8 793 /*!
Kojto 90:cb3d968589d8 794 * @name Register MCM_ETBCC, field RSPT[2:1] (RW)
Kojto 90:cb3d968589d8 795 *
Kojto 90:cb3d968589d8 796 * Values:
Kojto 90:cb3d968589d8 797 * - 00 - No response when the ETB count expires
Kojto 90:cb3d968589d8 798 * - 01 - Generate a normal interrupt when the ETB count expires
Kojto 90:cb3d968589d8 799 * - 10 - Generate an NMI when the ETB count expires
Kojto 90:cb3d968589d8 800 * - 11 - Generate a debug halt when the ETB count expires
Kojto 90:cb3d968589d8 801 */
Kojto 90:cb3d968589d8 802 /*@{*/
Kojto 90:cb3d968589d8 803 #define BP_MCM_ETBCC_RSPT (1U) /*!< Bit position for MCM_ETBCC_RSPT. */
Kojto 90:cb3d968589d8 804 #define BM_MCM_ETBCC_RSPT (0x00000006U) /*!< Bit mask for MCM_ETBCC_RSPT. */
Kojto 90:cb3d968589d8 805 #define BS_MCM_ETBCC_RSPT (2U) /*!< Bit field size in bits for MCM_ETBCC_RSPT. */
Kojto 90:cb3d968589d8 806
Kojto 90:cb3d968589d8 807 /*! @brief Read current value of the MCM_ETBCC_RSPT field. */
Kojto 90:cb3d968589d8 808 #define BR_MCM_ETBCC_RSPT(x) (HW_MCM_ETBCC(x).B.RSPT)
Kojto 90:cb3d968589d8 809
Kojto 90:cb3d968589d8 810 /*! @brief Format value for bitfield MCM_ETBCC_RSPT. */
Kojto 90:cb3d968589d8 811 #define BF_MCM_ETBCC_RSPT(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_RSPT) & BM_MCM_ETBCC_RSPT)
Kojto 90:cb3d968589d8 812
Kojto 90:cb3d968589d8 813 /*! @brief Set the RSPT field to a new value. */
Kojto 90:cb3d968589d8 814 #define BW_MCM_ETBCC_RSPT(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_RSPT) | BF_MCM_ETBCC_RSPT(v)))
Kojto 90:cb3d968589d8 815 /*@}*/
Kojto 90:cb3d968589d8 816
Kojto 90:cb3d968589d8 817 /*!
Kojto 90:cb3d968589d8 818 * @name Register MCM_ETBCC, field RLRQ[3] (RW)
Kojto 90:cb3d968589d8 819 *
Kojto 90:cb3d968589d8 820 * Reloads the ETB packet counter with the MCM_ETBRL RELOAD value. If IRQ or NMI
Kojto 90:cb3d968589d8 821 * interrupts were enabled and an NMI or IRQ interrupt was generated on counter
Kojto 90:cb3d968589d8 822 * expiration, setting this bit clears the pending NMI or IRQ interrupt request.
Kojto 90:cb3d968589d8 823 * If debug halt was enabled and a debug halt request was asserted on counter
Kojto 90:cb3d968589d8 824 * expiration, setting this bit clears the debug halt request.
Kojto 90:cb3d968589d8 825 *
Kojto 90:cb3d968589d8 826 * Values:
Kojto 90:cb3d968589d8 827 * - 0 - No effect
Kojto 90:cb3d968589d8 828 * - 1 - Clears pending debug halt, NMI, or IRQ interrupt requests
Kojto 90:cb3d968589d8 829 */
Kojto 90:cb3d968589d8 830 /*@{*/
Kojto 90:cb3d968589d8 831 #define BP_MCM_ETBCC_RLRQ (3U) /*!< Bit position for MCM_ETBCC_RLRQ. */
Kojto 90:cb3d968589d8 832 #define BM_MCM_ETBCC_RLRQ (0x00000008U) /*!< Bit mask for MCM_ETBCC_RLRQ. */
Kojto 90:cb3d968589d8 833 #define BS_MCM_ETBCC_RLRQ (1U) /*!< Bit field size in bits for MCM_ETBCC_RLRQ. */
Kojto 90:cb3d968589d8 834
Kojto 90:cb3d968589d8 835 /*! @brief Read current value of the MCM_ETBCC_RLRQ field. */
Kojto 90:cb3d968589d8 836 #define BR_MCM_ETBCC_RLRQ(x) (HW_MCM_ETBCC(x).B.RLRQ)
Kojto 90:cb3d968589d8 837
Kojto 90:cb3d968589d8 838 /*! @brief Format value for bitfield MCM_ETBCC_RLRQ. */
Kojto 90:cb3d968589d8 839 #define BF_MCM_ETBCC_RLRQ(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_RLRQ) & BM_MCM_ETBCC_RLRQ)
Kojto 90:cb3d968589d8 840
Kojto 90:cb3d968589d8 841 /*! @brief Set the RLRQ field to a new value. */
Kojto 90:cb3d968589d8 842 #define BW_MCM_ETBCC_RLRQ(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_RLRQ) | BF_MCM_ETBCC_RLRQ(v)))
Kojto 90:cb3d968589d8 843 /*@}*/
Kojto 90:cb3d968589d8 844
Kojto 90:cb3d968589d8 845 /*!
Kojto 90:cb3d968589d8 846 * @name Register MCM_ETBCC, field ETDIS[4] (RW)
Kojto 90:cb3d968589d8 847 *
Kojto 90:cb3d968589d8 848 * Disables the trace path from ETM to TPIU.
Kojto 90:cb3d968589d8 849 *
Kojto 90:cb3d968589d8 850 * Values:
Kojto 90:cb3d968589d8 851 * - 0 - ETM-to-TPIU trace path enabled
Kojto 90:cb3d968589d8 852 * - 1 - ETM-to-TPIU trace path disabled
Kojto 90:cb3d968589d8 853 */
Kojto 90:cb3d968589d8 854 /*@{*/
Kojto 90:cb3d968589d8 855 #define BP_MCM_ETBCC_ETDIS (4U) /*!< Bit position for MCM_ETBCC_ETDIS. */
Kojto 90:cb3d968589d8 856 #define BM_MCM_ETBCC_ETDIS (0x00000010U) /*!< Bit mask for MCM_ETBCC_ETDIS. */
Kojto 90:cb3d968589d8 857 #define BS_MCM_ETBCC_ETDIS (1U) /*!< Bit field size in bits for MCM_ETBCC_ETDIS. */
Kojto 90:cb3d968589d8 858
Kojto 90:cb3d968589d8 859 /*! @brief Read current value of the MCM_ETBCC_ETDIS field. */
Kojto 90:cb3d968589d8 860 #define BR_MCM_ETBCC_ETDIS(x) (HW_MCM_ETBCC(x).B.ETDIS)
Kojto 90:cb3d968589d8 861
Kojto 90:cb3d968589d8 862 /*! @brief Format value for bitfield MCM_ETBCC_ETDIS. */
Kojto 90:cb3d968589d8 863 #define BF_MCM_ETBCC_ETDIS(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_ETDIS) & BM_MCM_ETBCC_ETDIS)
Kojto 90:cb3d968589d8 864
Kojto 90:cb3d968589d8 865 /*! @brief Set the ETDIS field to a new value. */
Kojto 90:cb3d968589d8 866 #define BW_MCM_ETBCC_ETDIS(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_ETDIS) | BF_MCM_ETBCC_ETDIS(v)))
Kojto 90:cb3d968589d8 867 /*@}*/
Kojto 90:cb3d968589d8 868
Kojto 90:cb3d968589d8 869 /*!
Kojto 90:cb3d968589d8 870 * @name Register MCM_ETBCC, field ITDIS[5] (RW)
Kojto 90:cb3d968589d8 871 *
Kojto 90:cb3d968589d8 872 * Disables the trace path from ITM to TPIU.
Kojto 90:cb3d968589d8 873 *
Kojto 90:cb3d968589d8 874 * Values:
Kojto 90:cb3d968589d8 875 * - 0 - ITM-to-TPIU trace path enabled
Kojto 90:cb3d968589d8 876 * - 1 - ITM-to-TPIU trace path disabled
Kojto 90:cb3d968589d8 877 */
Kojto 90:cb3d968589d8 878 /*@{*/
Kojto 90:cb3d968589d8 879 #define BP_MCM_ETBCC_ITDIS (5U) /*!< Bit position for MCM_ETBCC_ITDIS. */
Kojto 90:cb3d968589d8 880 #define BM_MCM_ETBCC_ITDIS (0x00000020U) /*!< Bit mask for MCM_ETBCC_ITDIS. */
Kojto 90:cb3d968589d8 881 #define BS_MCM_ETBCC_ITDIS (1U) /*!< Bit field size in bits for MCM_ETBCC_ITDIS. */
Kojto 90:cb3d968589d8 882
Kojto 90:cb3d968589d8 883 /*! @brief Read current value of the MCM_ETBCC_ITDIS field. */
Kojto 90:cb3d968589d8 884 #define BR_MCM_ETBCC_ITDIS(x) (HW_MCM_ETBCC(x).B.ITDIS)
Kojto 90:cb3d968589d8 885
Kojto 90:cb3d968589d8 886 /*! @brief Format value for bitfield MCM_ETBCC_ITDIS. */
Kojto 90:cb3d968589d8 887 #define BF_MCM_ETBCC_ITDIS(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_ITDIS) & BM_MCM_ETBCC_ITDIS)
Kojto 90:cb3d968589d8 888
Kojto 90:cb3d968589d8 889 /*! @brief Set the ITDIS field to a new value. */
Kojto 90:cb3d968589d8 890 #define BW_MCM_ETBCC_ITDIS(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_ITDIS) | BF_MCM_ETBCC_ITDIS(v)))
Kojto 90:cb3d968589d8 891 /*@}*/
Kojto 90:cb3d968589d8 892
Kojto 90:cb3d968589d8 893 /*******************************************************************************
Kojto 90:cb3d968589d8 894 * HW_MCM_ETBRL - ETB Reload register
Kojto 90:cb3d968589d8 895 ******************************************************************************/
Kojto 90:cb3d968589d8 896
Kojto 90:cb3d968589d8 897 /*!
Kojto 90:cb3d968589d8 898 * @brief HW_MCM_ETBRL - ETB Reload register (RW)
Kojto 90:cb3d968589d8 899 *
Kojto 90:cb3d968589d8 900 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 901 */
Kojto 90:cb3d968589d8 902 typedef union _hw_mcm_etbrl
Kojto 90:cb3d968589d8 903 {
Kojto 90:cb3d968589d8 904 uint32_t U;
Kojto 90:cb3d968589d8 905 struct _hw_mcm_etbrl_bitfields
Kojto 90:cb3d968589d8 906 {
Kojto 90:cb3d968589d8 907 uint32_t RELOAD : 11; /*!< [10:0] Byte Count Reload Value */
Kojto 90:cb3d968589d8 908 uint32_t RESERVED0 : 21; /*!< [31:11] */
Kojto 90:cb3d968589d8 909 } B;
Kojto 90:cb3d968589d8 910 } hw_mcm_etbrl_t;
Kojto 90:cb3d968589d8 911
Kojto 90:cb3d968589d8 912 /*!
Kojto 90:cb3d968589d8 913 * @name Constants and macros for entire MCM_ETBRL register
Kojto 90:cb3d968589d8 914 */
Kojto 90:cb3d968589d8 915 /*@{*/
Kojto 90:cb3d968589d8 916 #define HW_MCM_ETBRL_ADDR(x) ((x) + 0x18U)
Kojto 90:cb3d968589d8 917
Kojto 90:cb3d968589d8 918 #define HW_MCM_ETBRL(x) (*(__IO hw_mcm_etbrl_t *) HW_MCM_ETBRL_ADDR(x))
Kojto 90:cb3d968589d8 919 #define HW_MCM_ETBRL_RD(x) (HW_MCM_ETBRL(x).U)
Kojto 90:cb3d968589d8 920 #define HW_MCM_ETBRL_WR(x, v) (HW_MCM_ETBRL(x).U = (v))
Kojto 90:cb3d968589d8 921 #define HW_MCM_ETBRL_SET(x, v) (HW_MCM_ETBRL_WR(x, HW_MCM_ETBRL_RD(x) | (v)))
Kojto 90:cb3d968589d8 922 #define HW_MCM_ETBRL_CLR(x, v) (HW_MCM_ETBRL_WR(x, HW_MCM_ETBRL_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 923 #define HW_MCM_ETBRL_TOG(x, v) (HW_MCM_ETBRL_WR(x, HW_MCM_ETBRL_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 924 /*@}*/
Kojto 90:cb3d968589d8 925
Kojto 90:cb3d968589d8 926 /*
Kojto 90:cb3d968589d8 927 * Constants & macros for individual MCM_ETBRL bitfields
Kojto 90:cb3d968589d8 928 */
Kojto 90:cb3d968589d8 929
Kojto 90:cb3d968589d8 930 /*!
Kojto 90:cb3d968589d8 931 * @name Register MCM_ETBRL, field RELOAD[10:0] (RW)
Kojto 90:cb3d968589d8 932 *
Kojto 90:cb3d968589d8 933 * Indicates the 0-mod-4 value the counter reloads to. Writing a non-0-mod-4
Kojto 90:cb3d968589d8 934 * value to this field results in a bus error.
Kojto 90:cb3d968589d8 935 */
Kojto 90:cb3d968589d8 936 /*@{*/
Kojto 90:cb3d968589d8 937 #define BP_MCM_ETBRL_RELOAD (0U) /*!< Bit position for MCM_ETBRL_RELOAD. */
Kojto 90:cb3d968589d8 938 #define BM_MCM_ETBRL_RELOAD (0x000007FFU) /*!< Bit mask for MCM_ETBRL_RELOAD. */
Kojto 90:cb3d968589d8 939 #define BS_MCM_ETBRL_RELOAD (11U) /*!< Bit field size in bits for MCM_ETBRL_RELOAD. */
Kojto 90:cb3d968589d8 940
Kojto 90:cb3d968589d8 941 /*! @brief Read current value of the MCM_ETBRL_RELOAD field. */
Kojto 90:cb3d968589d8 942 #define BR_MCM_ETBRL_RELOAD(x) (HW_MCM_ETBRL(x).B.RELOAD)
Kojto 90:cb3d968589d8 943
Kojto 90:cb3d968589d8 944 /*! @brief Format value for bitfield MCM_ETBRL_RELOAD. */
Kojto 90:cb3d968589d8 945 #define BF_MCM_ETBRL_RELOAD(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBRL_RELOAD) & BM_MCM_ETBRL_RELOAD)
Kojto 90:cb3d968589d8 946
Kojto 90:cb3d968589d8 947 /*! @brief Set the RELOAD field to a new value. */
Kojto 90:cb3d968589d8 948 #define BW_MCM_ETBRL_RELOAD(x, v) (HW_MCM_ETBRL_WR(x, (HW_MCM_ETBRL_RD(x) & ~BM_MCM_ETBRL_RELOAD) | BF_MCM_ETBRL_RELOAD(v)))
Kojto 90:cb3d968589d8 949 /*@}*/
Kojto 90:cb3d968589d8 950
Kojto 90:cb3d968589d8 951 /*******************************************************************************
Kojto 90:cb3d968589d8 952 * HW_MCM_ETBCNT - ETB Counter Value register
Kojto 90:cb3d968589d8 953 ******************************************************************************/
Kojto 90:cb3d968589d8 954
Kojto 90:cb3d968589d8 955 /*!
Kojto 90:cb3d968589d8 956 * @brief HW_MCM_ETBCNT - ETB Counter Value register (RO)
Kojto 90:cb3d968589d8 957 *
Kojto 90:cb3d968589d8 958 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 959 */
Kojto 90:cb3d968589d8 960 typedef union _hw_mcm_etbcnt
Kojto 90:cb3d968589d8 961 {
Kojto 90:cb3d968589d8 962 uint32_t U;
Kojto 90:cb3d968589d8 963 struct _hw_mcm_etbcnt_bitfields
Kojto 90:cb3d968589d8 964 {
Kojto 90:cb3d968589d8 965 uint32_t COUNTER : 11; /*!< [10:0] Byte Count Counter Value */
Kojto 90:cb3d968589d8 966 uint32_t RESERVED0 : 21; /*!< [31:11] */
Kojto 90:cb3d968589d8 967 } B;
Kojto 90:cb3d968589d8 968 } hw_mcm_etbcnt_t;
Kojto 90:cb3d968589d8 969
Kojto 90:cb3d968589d8 970 /*!
Kojto 90:cb3d968589d8 971 * @name Constants and macros for entire MCM_ETBCNT register
Kojto 90:cb3d968589d8 972 */
Kojto 90:cb3d968589d8 973 /*@{*/
Kojto 90:cb3d968589d8 974 #define HW_MCM_ETBCNT_ADDR(x) ((x) + 0x1CU)
Kojto 90:cb3d968589d8 975
Kojto 90:cb3d968589d8 976 #define HW_MCM_ETBCNT(x) (*(__I hw_mcm_etbcnt_t *) HW_MCM_ETBCNT_ADDR(x))
Kojto 90:cb3d968589d8 977 #define HW_MCM_ETBCNT_RD(x) (HW_MCM_ETBCNT(x).U)
Kojto 90:cb3d968589d8 978 /*@}*/
Kojto 90:cb3d968589d8 979
Kojto 90:cb3d968589d8 980 /*
Kojto 90:cb3d968589d8 981 * Constants & macros for individual MCM_ETBCNT bitfields
Kojto 90:cb3d968589d8 982 */
Kojto 90:cb3d968589d8 983
Kojto 90:cb3d968589d8 984 /*!
Kojto 90:cb3d968589d8 985 * @name Register MCM_ETBCNT, field COUNTER[10:0] (RO)
Kojto 90:cb3d968589d8 986 *
Kojto 90:cb3d968589d8 987 * Indicates the current 0-mod-4 value of the counter.
Kojto 90:cb3d968589d8 988 */
Kojto 90:cb3d968589d8 989 /*@{*/
Kojto 90:cb3d968589d8 990 #define BP_MCM_ETBCNT_COUNTER (0U) /*!< Bit position for MCM_ETBCNT_COUNTER. */
Kojto 90:cb3d968589d8 991 #define BM_MCM_ETBCNT_COUNTER (0x000007FFU) /*!< Bit mask for MCM_ETBCNT_COUNTER. */
Kojto 90:cb3d968589d8 992 #define BS_MCM_ETBCNT_COUNTER (11U) /*!< Bit field size in bits for MCM_ETBCNT_COUNTER. */
Kojto 90:cb3d968589d8 993
Kojto 90:cb3d968589d8 994 /*! @brief Read current value of the MCM_ETBCNT_COUNTER field. */
Kojto 90:cb3d968589d8 995 #define BR_MCM_ETBCNT_COUNTER(x) (HW_MCM_ETBCNT(x).B.COUNTER)
Kojto 90:cb3d968589d8 996 /*@}*/
Kojto 90:cb3d968589d8 997
Kojto 90:cb3d968589d8 998 /*******************************************************************************
Kojto 90:cb3d968589d8 999 * HW_MCM_PID - Process ID register
Kojto 90:cb3d968589d8 1000 ******************************************************************************/
Kojto 90:cb3d968589d8 1001
Kojto 90:cb3d968589d8 1002 /*!
Kojto 90:cb3d968589d8 1003 * @brief HW_MCM_PID - Process ID register (RW)
Kojto 90:cb3d968589d8 1004 *
Kojto 90:cb3d968589d8 1005 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 1006 *
Kojto 90:cb3d968589d8 1007 * This register drives the M0_PID and M1_PID values in the Memory Protection
Kojto 90:cb3d968589d8 1008 * Unit(MPU). System software loads this register before passing control to a given
Kojto 90:cb3d968589d8 1009 * user mode process. If the PID of the process does not match the value in this
Kojto 90:cb3d968589d8 1010 * register, a bus error occurs. See the MPU chapter for more details.
Kojto 90:cb3d968589d8 1011 */
Kojto 90:cb3d968589d8 1012 typedef union _hw_mcm_pid
Kojto 90:cb3d968589d8 1013 {
Kojto 90:cb3d968589d8 1014 uint32_t U;
Kojto 90:cb3d968589d8 1015 struct _hw_mcm_pid_bitfields
Kojto 90:cb3d968589d8 1016 {
Kojto 90:cb3d968589d8 1017 uint32_t PID : 8; /*!< [7:0] M0_PID And M1_PID For MPU */
Kojto 90:cb3d968589d8 1018 uint32_t RESERVED0 : 24; /*!< [31:8] */
Kojto 90:cb3d968589d8 1019 } B;
Kojto 90:cb3d968589d8 1020 } hw_mcm_pid_t;
Kojto 90:cb3d968589d8 1021
Kojto 90:cb3d968589d8 1022 /*!
Kojto 90:cb3d968589d8 1023 * @name Constants and macros for entire MCM_PID register
Kojto 90:cb3d968589d8 1024 */
Kojto 90:cb3d968589d8 1025 /*@{*/
Kojto 90:cb3d968589d8 1026 #define HW_MCM_PID_ADDR(x) ((x) + 0x30U)
Kojto 90:cb3d968589d8 1027
Kojto 90:cb3d968589d8 1028 #define HW_MCM_PID(x) (*(__IO hw_mcm_pid_t *) HW_MCM_PID_ADDR(x))
Kojto 90:cb3d968589d8 1029 #define HW_MCM_PID_RD(x) (HW_MCM_PID(x).U)
Kojto 90:cb3d968589d8 1030 #define HW_MCM_PID_WR(x, v) (HW_MCM_PID(x).U = (v))
Kojto 90:cb3d968589d8 1031 #define HW_MCM_PID_SET(x, v) (HW_MCM_PID_WR(x, HW_MCM_PID_RD(x) | (v)))
Kojto 90:cb3d968589d8 1032 #define HW_MCM_PID_CLR(x, v) (HW_MCM_PID_WR(x, HW_MCM_PID_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 1033 #define HW_MCM_PID_TOG(x, v) (HW_MCM_PID_WR(x, HW_MCM_PID_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 1034 /*@}*/
Kojto 90:cb3d968589d8 1035
Kojto 90:cb3d968589d8 1036 /*
Kojto 90:cb3d968589d8 1037 * Constants & macros for individual MCM_PID bitfields
Kojto 90:cb3d968589d8 1038 */
Kojto 90:cb3d968589d8 1039
Kojto 90:cb3d968589d8 1040 /*!
Kojto 90:cb3d968589d8 1041 * @name Register MCM_PID, field PID[7:0] (RW)
Kojto 90:cb3d968589d8 1042 *
Kojto 90:cb3d968589d8 1043 * Drives the M0_PID and M1_PID values in the MPU.
Kojto 90:cb3d968589d8 1044 */
Kojto 90:cb3d968589d8 1045 /*@{*/
Kojto 90:cb3d968589d8 1046 #define BP_MCM_PID_PID (0U) /*!< Bit position for MCM_PID_PID. */
Kojto 90:cb3d968589d8 1047 #define BM_MCM_PID_PID (0x000000FFU) /*!< Bit mask for MCM_PID_PID. */
Kojto 90:cb3d968589d8 1048 #define BS_MCM_PID_PID (8U) /*!< Bit field size in bits for MCM_PID_PID. */
Kojto 90:cb3d968589d8 1049
Kojto 90:cb3d968589d8 1050 /*! @brief Read current value of the MCM_PID_PID field. */
Kojto 90:cb3d968589d8 1051 #define BR_MCM_PID_PID(x) (HW_MCM_PID(x).B.PID)
Kojto 90:cb3d968589d8 1052
Kojto 90:cb3d968589d8 1053 /*! @brief Format value for bitfield MCM_PID_PID. */
Kojto 90:cb3d968589d8 1054 #define BF_MCM_PID_PID(v) ((uint32_t)((uint32_t)(v) << BP_MCM_PID_PID) & BM_MCM_PID_PID)
Kojto 90:cb3d968589d8 1055
Kojto 90:cb3d968589d8 1056 /*! @brief Set the PID field to a new value. */
Kojto 90:cb3d968589d8 1057 #define BW_MCM_PID_PID(x, v) (HW_MCM_PID_WR(x, (HW_MCM_PID_RD(x) & ~BM_MCM_PID_PID) | BF_MCM_PID_PID(v)))
Kojto 90:cb3d968589d8 1058 /*@}*/
Kojto 90:cb3d968589d8 1059
Kojto 90:cb3d968589d8 1060 /*******************************************************************************
Kojto 90:cb3d968589d8 1061 * hw_mcm_t - module struct
Kojto 90:cb3d968589d8 1062 ******************************************************************************/
Kojto 90:cb3d968589d8 1063 /*!
Kojto 90:cb3d968589d8 1064 * @brief All MCM module registers.
Kojto 90:cb3d968589d8 1065 */
Kojto 90:cb3d968589d8 1066 #pragma pack(1)
Kojto 90:cb3d968589d8 1067 typedef struct _hw_mcm
Kojto 90:cb3d968589d8 1068 {
Kojto 90:cb3d968589d8 1069 uint8_t _reserved0[8];
Kojto 90:cb3d968589d8 1070 __I hw_mcm_plasc_t PLASC; /*!< [0x8] Crossbar Switch (AXBS) Slave Configuration */
Kojto 90:cb3d968589d8 1071 __I hw_mcm_plamc_t PLAMC; /*!< [0xA] Crossbar Switch (AXBS) Master Configuration */
Kojto 90:cb3d968589d8 1072 __IO hw_mcm_cr_t CR; /*!< [0xC] Control Register */
Kojto 90:cb3d968589d8 1073 __IO hw_mcm_iscr_t ISCR; /*!< [0x10] Interrupt Status Register */
Kojto 90:cb3d968589d8 1074 __IO hw_mcm_etbcc_t ETBCC; /*!< [0x14] ETB Counter Control register */
Kojto 90:cb3d968589d8 1075 __IO hw_mcm_etbrl_t ETBRL; /*!< [0x18] ETB Reload register */
Kojto 90:cb3d968589d8 1076 __I hw_mcm_etbcnt_t ETBCNT; /*!< [0x1C] ETB Counter Value register */
Kojto 90:cb3d968589d8 1077 uint8_t _reserved1[16];
Kojto 90:cb3d968589d8 1078 __IO hw_mcm_pid_t PID; /*!< [0x30] Process ID register */
Kojto 90:cb3d968589d8 1079 } hw_mcm_t;
Kojto 90:cb3d968589d8 1080 #pragma pack()
Kojto 90:cb3d968589d8 1081
Kojto 90:cb3d968589d8 1082 /*! @brief Macro to access all MCM registers. */
Kojto 90:cb3d968589d8 1083 /*! @param x MCM module instance base address. */
Kojto 90:cb3d968589d8 1084 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto 90:cb3d968589d8 1085 * use the '&' operator, like <code>&HW_MCM(MCM_BASE)</code>. */
Kojto 90:cb3d968589d8 1086 #define HW_MCM(x) (*(hw_mcm_t *)(x))
Kojto 90:cb3d968589d8 1087
Kojto 90:cb3d968589d8 1088 #endif /* __HW_MCM_REGISTERS_H__ */
Kojto 90:cb3d968589d8 1089 /* EOF */