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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_llwu.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:: Kojto
Date:: Wed Aug 05 13:16:35 2015 +0100
Revision:: 104:b9ad9a133dc7
Parent:: 90:cb3d968589d8

Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	90:cb3d968589d8	1	/*
Kojto	90:cb3d968589d8	2	** ###################################################################
Kojto	90:cb3d968589d8	3	** Compilers: Keil ARM C/C++ Compiler
Kojto	90:cb3d968589d8	4	** Freescale C/C++ for Embedded ARM
Kojto	90:cb3d968589d8	5	** GNU C Compiler
Kojto	90:cb3d968589d8	6	** IAR ANSI C/C++ Compiler for ARM
Kojto	90:cb3d968589d8	7	**
Kojto	90:cb3d968589d8	8	** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto	90:cb3d968589d8	9	** Version: rev. 2.5, 2014-02-10
Kojto	90:cb3d968589d8	10	** Build: b140604
Kojto	90:cb3d968589d8	11	**
Kojto	90:cb3d968589d8	12	** Abstract:
Kojto	90:cb3d968589d8	13	** Extension to the CMSIS register access layer header.
Kojto	90:cb3d968589d8	14	**
Kojto	90:cb3d968589d8	15	** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto	90:cb3d968589d8	16	** All rights reserved.
Kojto	90:cb3d968589d8	17	**
Kojto	90:cb3d968589d8	18	** Redistribution and use in source and binary forms, with or without modification,
Kojto	90:cb3d968589d8	19	** are permitted provided that the following conditions are met:
Kojto	90:cb3d968589d8	20	**
Kojto	90:cb3d968589d8	21	** o Redistributions of source code must retain the above copyright notice, this list
Kojto	90:cb3d968589d8	22	** of conditions and the following disclaimer.
Kojto	90:cb3d968589d8	23	**
Kojto	90:cb3d968589d8	24	** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto	90:cb3d968589d8	25	** list of conditions and the following disclaimer in the documentation and/or
Kojto	90:cb3d968589d8	26	** other materials provided with the distribution.
Kojto	90:cb3d968589d8	27	**
Kojto	90:cb3d968589d8	28	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto	90:cb3d968589d8	29	** contributors may be used to endorse or promote products derived from this
Kojto	90:cb3d968589d8	30	** software without specific prior written permission.
Kojto	90:cb3d968589d8	31	**
Kojto	90:cb3d968589d8	32	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto	90:cb3d968589d8	33	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto	90:cb3d968589d8	34	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	90:cb3d968589d8	35	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto	90:cb3d968589d8	36	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto	90:cb3d968589d8	37	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto	90:cb3d968589d8	38	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto	90:cb3d968589d8	39	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto	90:cb3d968589d8	40	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto	90:cb3d968589d8	41	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	90:cb3d968589d8	42	**
Kojto	90:cb3d968589d8	43	** http: www.freescale.com
Kojto	90:cb3d968589d8	44	** mail: support@freescale.com
Kojto	90:cb3d968589d8	45	**
Kojto	90:cb3d968589d8	46	** Revisions:
Kojto	90:cb3d968589d8	47	** - rev. 1.0 (2013-08-12)
Kojto	90:cb3d968589d8	48	** Initial version.
Kojto	90:cb3d968589d8	49	** - rev. 2.0 (2013-10-29)
Kojto	90:cb3d968589d8	50	** Register accessor macros added to the memory map.
Kojto	90:cb3d968589d8	51	** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto	90:cb3d968589d8	52	** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto	90:cb3d968589d8	53	** System initialization updated.
Kojto	90:cb3d968589d8	54	** MCG - registers updated.
Kojto	90:cb3d968589d8	55	** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto	90:cb3d968589d8	56	** - rev. 2.1 (2013-10-30)
Kojto	90:cb3d968589d8	57	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto	90:cb3d968589d8	58	** - rev. 2.2 (2013-12-09)
Kojto	90:cb3d968589d8	59	** DMA - EARS register removed.
Kojto	90:cb3d968589d8	60	** AIPS0, AIPS1 - MPRA register updated.
Kojto	90:cb3d968589d8	61	** - rev. 2.3 (2014-01-24)
Kojto	90:cb3d968589d8	62	** Update according to reference manual rev. 2
Kojto	90:cb3d968589d8	63	** ENET, MCG, MCM, SIM, USB - registers updated
Kojto	90:cb3d968589d8	64	** - rev. 2.4 (2014-02-10)
Kojto	90:cb3d968589d8	65	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	66	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	67	** - rev. 2.5 (2014-02-10)
Kojto	90:cb3d968589d8	68	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	69	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	70	** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto	90:cb3d968589d8	71	**
Kojto	90:cb3d968589d8	72	** ###################################################################
Kojto	90:cb3d968589d8	73	*/
Kojto	90:cb3d968589d8	74
Kojto	90:cb3d968589d8	75	/*
Kojto	90:cb3d968589d8	76	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto	90:cb3d968589d8	77	*
Kojto	90:cb3d968589d8	78	* This file was generated automatically and any changes may be lost.
Kojto	90:cb3d968589d8	79	*/
Kojto	90:cb3d968589d8	80	#ifndef __HW_LLWU_REGISTERS_H__
Kojto	90:cb3d968589d8	81	#define __HW_LLWU_REGISTERS_H__
Kojto	90:cb3d968589d8	82
Kojto	90:cb3d968589d8	83	#include "MK64F12.h"
Kojto	90:cb3d968589d8	84	#include "fsl_bitaccess.h"
Kojto	90:cb3d968589d8	85
Kojto	90:cb3d968589d8	86	/*
Kojto	90:cb3d968589d8	87	* MK64F12 LLWU
Kojto	90:cb3d968589d8	88	*
Kojto	90:cb3d968589d8	89	* Low leakage wakeup unit
Kojto	90:cb3d968589d8	90	*
Kojto	90:cb3d968589d8	91	* Registers defined in this header file:
Kojto	90:cb3d968589d8	92	* - HW_LLWU_PE1 - LLWU Pin Enable 1 register
Kojto	90:cb3d968589d8	93	* - HW_LLWU_PE2 - LLWU Pin Enable 2 register
Kojto	90:cb3d968589d8	94	* - HW_LLWU_PE3 - LLWU Pin Enable 3 register
Kojto	90:cb3d968589d8	95	* - HW_LLWU_PE4 - LLWU Pin Enable 4 register
Kojto	90:cb3d968589d8	96	* - HW_LLWU_ME - LLWU Module Enable register
Kojto	90:cb3d968589d8	97	* - HW_LLWU_F1 - LLWU Flag 1 register
Kojto	90:cb3d968589d8	98	* - HW_LLWU_F2 - LLWU Flag 2 register
Kojto	90:cb3d968589d8	99	* - HW_LLWU_F3 - LLWU Flag 3 register
Kojto	90:cb3d968589d8	100	* - HW_LLWU_FILT1 - LLWU Pin Filter 1 register
Kojto	90:cb3d968589d8	101	* - HW_LLWU_FILT2 - LLWU Pin Filter 2 register
Kojto	90:cb3d968589d8	102	* - HW_LLWU_RST - LLWU Reset Enable register
Kojto	90:cb3d968589d8	103	*
Kojto	90:cb3d968589d8	104	* - hw_llwu_t - Struct containing all module registers.
Kojto	90:cb3d968589d8	105	*/
Kojto	90:cb3d968589d8	106
Kojto	90:cb3d968589d8	107	#define HW_LLWU_INSTANCE_COUNT (1U) /!< Number of instances of the LLWU module. /
Kojto	90:cb3d968589d8	108
Kojto	90:cb3d968589d8	109	/*******************************************************************************
Kojto	90:cb3d968589d8	110	* HW_LLWU_PE1 - LLWU Pin Enable 1 register
Kojto	90:cb3d968589d8	111	******************************************************************************/
Kojto	90:cb3d968589d8	112
Kojto	90:cb3d968589d8	113	/*!
Kojto	90:cb3d968589d8	114	* @brief HW_LLWU_PE1 - LLWU Pin Enable 1 register (RW)
Kojto	90:cb3d968589d8	115	*
Kojto	90:cb3d968589d8	116	* Reset value: 0x00U
Kojto	90:cb3d968589d8	117	*
Kojto	90:cb3d968589d8	118	* LLWU_PE1 contains the field to enable and select the edge detect type for the
Kojto	90:cb3d968589d8	119	* external wakeup input pins LLWU_P3-LLWU_P0. This register is reset on Chip
Kojto	90:cb3d968589d8	120	* Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
Kojto	90:cb3d968589d8	121	* unaffected by reset types that do not trigger Chip Reset not VLLS. See the
Kojto	90:cb3d968589d8	122	* IntroductionInformation found here describes the registers of the Reset Control Module
Kojto	90:cb3d968589d8	123	* (RCM). The RCM implements many of the reset functions for the chip. See the
Kojto	90:cb3d968589d8	124	* chip's reset chapter for more information. details for more information.
Kojto	90:cb3d968589d8	125	*/
Kojto	90:cb3d968589d8	126	typedef union _hw_llwu_pe1
Kojto	90:cb3d968589d8	127	{
Kojto	90:cb3d968589d8	128	uint8_t U;
Kojto	90:cb3d968589d8	129	struct _hw_llwu_pe1_bitfields
Kojto	90:cb3d968589d8	130	{
Kojto	90:cb3d968589d8	131	uint8_t WUPE0 : 2; /!< [1:0] Wakeup Pin Enable For LLWU_P0 /
Kojto	90:cb3d968589d8	132	uint8_t WUPE1 : 2; /!< [3:2] Wakeup Pin Enable For LLWU_P1 /
Kojto	90:cb3d968589d8	133	uint8_t WUPE2 : 2; /!< [5:4] Wakeup Pin Enable For LLWU_P2 /
Kojto	90:cb3d968589d8	134	uint8_t WUPE3 : 2; /!< [7:6] Wakeup Pin Enable For LLWU_P3 /
Kojto	90:cb3d968589d8	135	} B;
Kojto	90:cb3d968589d8	136	} hw_llwu_pe1_t;
Kojto	90:cb3d968589d8	137
Kojto	90:cb3d968589d8	138	/*!
Kojto	90:cb3d968589d8	139	* @name Constants and macros for entire LLWU_PE1 register
Kojto	90:cb3d968589d8	140	*/
Kojto	90:cb3d968589d8	141	/@{/
Kojto	90:cb3d968589d8	142	#define HW_LLWU_PE1_ADDR(x) ((x) + 0x0U)
Kojto	90:cb3d968589d8	143
Kojto	90:cb3d968589d8	144	#define HW_LLWU_PE1(x) ((__IO hw_llwu_pe1_t ) HW_LLWU_PE1_ADDR(x))
Kojto	90:cb3d968589d8	145	#define HW_LLWU_PE1_RD(x) (HW_LLWU_PE1(x).U)
Kojto	90:cb3d968589d8	146	#define HW_LLWU_PE1_WR(x, v) (HW_LLWU_PE1(x).U = (v))
Kojto	90:cb3d968589d8	147	#define HW_LLWU_PE1_SET(x, v) (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) \| (v)))
Kojto	90:cb3d968589d8	148	#define HW_LLWU_PE1_CLR(x, v) (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	149	#define HW_LLWU_PE1_TOG(x, v) (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	150	/@}/
Kojto	90:cb3d968589d8	151
Kojto	90:cb3d968589d8	152	/*
Kojto	90:cb3d968589d8	153	* Constants & macros for individual LLWU_PE1 bitfields
Kojto	90:cb3d968589d8	154	*/
Kojto	90:cb3d968589d8	155
Kojto	90:cb3d968589d8	156	/*!
Kojto	90:cb3d968589d8	157	* @name Register LLWU_PE1, field WUPE0[1:0] (RW)
Kojto	90:cb3d968589d8	158	*
Kojto	90:cb3d968589d8	159	* Enables and configures the edge detection for the wakeup pin.
Kojto	90:cb3d968589d8	160	*
Kojto	90:cb3d968589d8	161	* Values:
Kojto	90:cb3d968589d8	162	* - 00 - External input pin disabled as wakeup input
Kojto	90:cb3d968589d8	163	* - 01 - External input pin enabled with rising edge detection
Kojto	90:cb3d968589d8	164	* - 10 - External input pin enabled with falling edge detection
Kojto	90:cb3d968589d8	165	* - 11 - External input pin enabled with any change detection
Kojto	90:cb3d968589d8	166	*/
Kojto	90:cb3d968589d8	167	/@{/
Kojto	90:cb3d968589d8	168	#define BP_LLWU_PE1_WUPE0 (0U) /!< Bit position for LLWU_PE1_WUPE0. /
Kojto	90:cb3d968589d8	169	#define BM_LLWU_PE1_WUPE0 (0x03U) /!< Bit mask for LLWU_PE1_WUPE0. /
Kojto	90:cb3d968589d8	170	#define BS_LLWU_PE1_WUPE0 (2U) /!< Bit field size in bits for LLWU_PE1_WUPE0. /
Kojto	90:cb3d968589d8	171
Kojto	90:cb3d968589d8	172	/! @brief Read current value of the LLWU_PE1_WUPE0 field. /
Kojto	90:cb3d968589d8	173	#define BR_LLWU_PE1_WUPE0(x) (HW_LLWU_PE1(x).B.WUPE0)
Kojto	90:cb3d968589d8	174
Kojto	90:cb3d968589d8	175	/! @brief Format value for bitfield LLWU_PE1_WUPE0. /
Kojto	90:cb3d968589d8	176	#define BF_LLWU_PE1_WUPE0(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE0) & BM_LLWU_PE1_WUPE0)
Kojto	90:cb3d968589d8	177
Kojto	90:cb3d968589d8	178	/! @brief Set the WUPE0 field to a new value. /
Kojto	90:cb3d968589d8	179	#define BW_LLWU_PE1_WUPE0(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE0) \| BF_LLWU_PE1_WUPE0(v)))
Kojto	90:cb3d968589d8	180	/@}/
Kojto	90:cb3d968589d8	181
Kojto	90:cb3d968589d8	182	/*!
Kojto	90:cb3d968589d8	183	* @name Register LLWU_PE1, field WUPE1[3:2] (RW)
Kojto	90:cb3d968589d8	184	*
Kojto	90:cb3d968589d8	185	* Enables and configures the edge detection for the wakeup pin.
Kojto	90:cb3d968589d8	186	*
Kojto	90:cb3d968589d8	187	* Values:
Kojto	90:cb3d968589d8	188	* - 00 - External input pin disabled as wakeup input
Kojto	90:cb3d968589d8	189	* - 01 - External input pin enabled with rising edge detection
Kojto	90:cb3d968589d8	190	* - 10 - External input pin enabled with falling edge detection
Kojto	90:cb3d968589d8	191	* - 11 - External input pin enabled with any change detection
Kojto	90:cb3d968589d8	192	*/
Kojto	90:cb3d968589d8	193	/@{/
Kojto	90:cb3d968589d8	194	#define BP_LLWU_PE1_WUPE1 (2U) /!< Bit position for LLWU_PE1_WUPE1. /
Kojto	90:cb3d968589d8	195	#define BM_LLWU_PE1_WUPE1 (0x0CU) /!< Bit mask for LLWU_PE1_WUPE1. /
Kojto	90:cb3d968589d8	196	#define BS_LLWU_PE1_WUPE1 (2U) /!< Bit field size in bits for LLWU_PE1_WUPE1. /
Kojto	90:cb3d968589d8	197
Kojto	90:cb3d968589d8	198	/! @brief Read current value of the LLWU_PE1_WUPE1 field. /
Kojto	90:cb3d968589d8	199	#define BR_LLWU_PE1_WUPE1(x) (HW_LLWU_PE1(x).B.WUPE1)
Kojto	90:cb3d968589d8	200
Kojto	90:cb3d968589d8	201	/! @brief Format value for bitfield LLWU_PE1_WUPE1. /
Kojto	90:cb3d968589d8	202	#define BF_LLWU_PE1_WUPE1(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE1) & BM_LLWU_PE1_WUPE1)
Kojto	90:cb3d968589d8	203
Kojto	90:cb3d968589d8	204	/! @brief Set the WUPE1 field to a new value. /
Kojto	90:cb3d968589d8	205	#define BW_LLWU_PE1_WUPE1(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE1) \| BF_LLWU_PE1_WUPE1(v)))
Kojto	90:cb3d968589d8	206	/@}/
Kojto	90:cb3d968589d8	207
Kojto	90:cb3d968589d8	208	/*!
Kojto	90:cb3d968589d8	209	* @name Register LLWU_PE1, field WUPE2[5:4] (RW)
Kojto	90:cb3d968589d8	210	*
Kojto	90:cb3d968589d8	211	* Enables and configures the edge detection for the wakeup pin.
Kojto	90:cb3d968589d8	212	*
Kojto	90:cb3d968589d8	213	* Values:
Kojto	90:cb3d968589d8	214	* - 00 - External input pin disabled as wakeup input
Kojto	90:cb3d968589d8	215	* - 01 - External input pin enabled with rising edge detection
Kojto	90:cb3d968589d8	216	* - 10 - External input pin enabled with falling edge detection
Kojto	90:cb3d968589d8	217	* - 11 - External input pin enabled with any change detection
Kojto	90:cb3d968589d8	218	*/
Kojto	90:cb3d968589d8	219	/@{/
Kojto	90:cb3d968589d8	220	#define BP_LLWU_PE1_WUPE2 (4U) /!< Bit position for LLWU_PE1_WUPE2. /
Kojto	90:cb3d968589d8	221	#define BM_LLWU_PE1_WUPE2 (0x30U) /!< Bit mask for LLWU_PE1_WUPE2. /
Kojto	90:cb3d968589d8	222	#define BS_LLWU_PE1_WUPE2 (2U) /!< Bit field size in bits for LLWU_PE1_WUPE2. /
Kojto	90:cb3d968589d8	223
Kojto	90:cb3d968589d8	224	/! @brief Read current value of the LLWU_PE1_WUPE2 field. /
Kojto	90:cb3d968589d8	225	#define BR_LLWU_PE1_WUPE2(x) (HW_LLWU_PE1(x).B.WUPE2)
Kojto	90:cb3d968589d8	226
Kojto	90:cb3d968589d8	227	/! @brief Format value for bitfield LLWU_PE1_WUPE2. /
Kojto	90:cb3d968589d8	228	#define BF_LLWU_PE1_WUPE2(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE2) & BM_LLWU_PE1_WUPE2)
Kojto	90:cb3d968589d8	229
Kojto	90:cb3d968589d8	230	/! @brief Set the WUPE2 field to a new value. /
Kojto	90:cb3d968589d8	231	#define BW_LLWU_PE1_WUPE2(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE2) \| BF_LLWU_PE1_WUPE2(v)))
Kojto	90:cb3d968589d8	232	/@}/
Kojto	90:cb3d968589d8	233
Kojto	90:cb3d968589d8	234	/*!
Kojto	90:cb3d968589d8	235	* @name Register LLWU_PE1, field WUPE3[7:6] (RW)
Kojto	90:cb3d968589d8	236	*
Kojto	90:cb3d968589d8	237	* Enables and configures the edge detection for the wakeup pin.
Kojto	90:cb3d968589d8	238	*
Kojto	90:cb3d968589d8	239	* Values:
Kojto	90:cb3d968589d8	240	* - 00 - External input pin disabled as wakeup input
Kojto	90:cb3d968589d8	241	* - 01 - External input pin enabled with rising edge detection
Kojto	90:cb3d968589d8	242	* - 10 - External input pin enabled with falling edge detection
Kojto	90:cb3d968589d8	243	* - 11 - External input pin enabled with any change detection
Kojto	90:cb3d968589d8	244	*/
Kojto	90:cb3d968589d8	245	/@{/
Kojto	90:cb3d968589d8	246	#define BP_LLWU_PE1_WUPE3 (6U) /!< Bit position for LLWU_PE1_WUPE3. /
Kojto	90:cb3d968589d8	247	#define BM_LLWU_PE1_WUPE3 (0xC0U) /!< Bit mask for LLWU_PE1_WUPE3. /
Kojto	90:cb3d968589d8	248	#define BS_LLWU_PE1_WUPE3 (2U) /!< Bit field size in bits for LLWU_PE1_WUPE3. /
Kojto	90:cb3d968589d8	249
Kojto	90:cb3d968589d8	250	/! @brief Read current value of the LLWU_PE1_WUPE3 field. /
Kojto	90:cb3d968589d8	251	#define BR_LLWU_PE1_WUPE3(x) (HW_LLWU_PE1(x).B.WUPE3)
Kojto	90:cb3d968589d8	252
Kojto	90:cb3d968589d8	253	/! @brief Format value for bitfield LLWU_PE1_WUPE3. /
Kojto	90:cb3d968589d8	254	#define BF_LLWU_PE1_WUPE3(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE3) & BM_LLWU_PE1_WUPE3)
Kojto	90:cb3d968589d8	255
Kojto	90:cb3d968589d8	256	/! @brief Set the WUPE3 field to a new value. /
Kojto	90:cb3d968589d8	257	#define BW_LLWU_PE1_WUPE3(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE3) \| BF_LLWU_PE1_WUPE3(v)))
Kojto	90:cb3d968589d8	258	/@}/
Kojto	90:cb3d968589d8	259
Kojto	90:cb3d968589d8	260	/*******************************************************************************
Kojto	90:cb3d968589d8	261	* HW_LLWU_PE2 - LLWU Pin Enable 2 register
Kojto	90:cb3d968589d8	262	******************************************************************************/
Kojto	90:cb3d968589d8	263
Kojto	90:cb3d968589d8	264	/*!
Kojto	90:cb3d968589d8	265	* @brief HW_LLWU_PE2 - LLWU Pin Enable 2 register (RW)
Kojto	90:cb3d968589d8	266	*
Kojto	90:cb3d968589d8	267	* Reset value: 0x00U
Kojto	90:cb3d968589d8	268	*
Kojto	90:cb3d968589d8	269	* LLWU_PE2 contains the field to enable and select the edge detect type for the
Kojto	90:cb3d968589d8	270	* external wakeup input pins LLWU_P7-LLWU_P4. This register is reset on Chip
Kojto	90:cb3d968589d8	271	* Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
Kojto	90:cb3d968589d8	272	* unaffected by reset types that do not trigger Chip Reset not VLLS. See the
Kojto	90:cb3d968589d8	273	* IntroductionInformation found here describes the registers of the Reset Control Module
Kojto	90:cb3d968589d8	274	* (RCM). The RCM implements many of the reset functions for the chip. See the
Kojto	90:cb3d968589d8	275	* chip's reset chapter for more information. details for more information.
Kojto	90:cb3d968589d8	276	*/
Kojto	90:cb3d968589d8	277	typedef union _hw_llwu_pe2
Kojto	90:cb3d968589d8	278	{
Kojto	90:cb3d968589d8	279	uint8_t U;
Kojto	90:cb3d968589d8	280	struct _hw_llwu_pe2_bitfields
Kojto	90:cb3d968589d8	281	{
Kojto	90:cb3d968589d8	282	uint8_t WUPE4 : 2; /!< [1:0] Wakeup Pin Enable For LLWU_P4 /
Kojto	90:cb3d968589d8	283	uint8_t WUPE5 : 2; /!< [3:2] Wakeup Pin Enable For LLWU_P5 /
Kojto	90:cb3d968589d8	284	uint8_t WUPE6 : 2; /!< [5:4] Wakeup Pin Enable For LLWU_P6 /
Kojto	90:cb3d968589d8	285	uint8_t WUPE7 : 2; /!< [7:6] Wakeup Pin Enable For LLWU_P7 /
Kojto	90:cb3d968589d8	286	} B;
Kojto	90:cb3d968589d8	287	} hw_llwu_pe2_t;
Kojto	90:cb3d968589d8	288
Kojto	90:cb3d968589d8	289	/*!
Kojto	90:cb3d968589d8	290	* @name Constants and macros for entire LLWU_PE2 register
Kojto	90:cb3d968589d8	291	*/
Kojto	90:cb3d968589d8	292	/@{/
Kojto	90:cb3d968589d8	293	#define HW_LLWU_PE2_ADDR(x) ((x) + 0x1U)
Kojto	90:cb3d968589d8	294
Kojto	90:cb3d968589d8	295	#define HW_LLWU_PE2(x) ((__IO hw_llwu_pe2_t ) HW_LLWU_PE2_ADDR(x))
Kojto	90:cb3d968589d8	296	#define HW_LLWU_PE2_RD(x) (HW_LLWU_PE2(x).U)
Kojto	90:cb3d968589d8	297	#define HW_LLWU_PE2_WR(x, v) (HW_LLWU_PE2(x).U = (v))
Kojto	90:cb3d968589d8	298	#define HW_LLWU_PE2_SET(x, v) (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) \| (v)))
Kojto	90:cb3d968589d8	299	#define HW_LLWU_PE2_CLR(x, v) (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	300	#define HW_LLWU_PE2_TOG(x, v) (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	301	/@}/
Kojto	90:cb3d968589d8	302
Kojto	90:cb3d968589d8	303	/*
Kojto	90:cb3d968589d8	304	* Constants & macros for individual LLWU_PE2 bitfields
Kojto	90:cb3d968589d8	305	*/
Kojto	90:cb3d968589d8	306
Kojto	90:cb3d968589d8	307	/*!
Kojto	90:cb3d968589d8	308	* @name Register LLWU_PE2, field WUPE4[1:0] (RW)
Kojto	90:cb3d968589d8	309	*
Kojto	90:cb3d968589d8	310	* Enables and configures the edge detection for the wakeup pin.
Kojto	90:cb3d968589d8	311	*
Kojto	90:cb3d968589d8	312	* Values:
Kojto	90:cb3d968589d8	313	* - 00 - External input pin disabled as wakeup input
Kojto	90:cb3d968589d8	314	* - 01 - External input pin enabled with rising edge detection
Kojto	90:cb3d968589d8	315	* - 10 - External input pin enabled with falling edge detection
Kojto	90:cb3d968589d8	316	* - 11 - External input pin enabled with any change detection
Kojto	90:cb3d968589d8	317	*/
Kojto	90:cb3d968589d8	318	/@{/
Kojto	90:cb3d968589d8	319	#define BP_LLWU_PE2_WUPE4 (0U) /!< Bit position for LLWU_PE2_WUPE4. /
Kojto	90:cb3d968589d8	320	#define BM_LLWU_PE2_WUPE4 (0x03U) /!< Bit mask for LLWU_PE2_WUPE4. /
Kojto	90:cb3d968589d8	321	#define BS_LLWU_PE2_WUPE4 (2U) /!< Bit field size in bits for LLWU_PE2_WUPE4. /
Kojto	90:cb3d968589d8	322
Kojto	90:cb3d968589d8	323	/! @brief Read current value of the LLWU_PE2_WUPE4 field. /
Kojto	90:cb3d968589d8	324	#define BR_LLWU_PE2_WUPE4(x) (HW_LLWU_PE2(x).B.WUPE4)
Kojto	90:cb3d968589d8	325
Kojto	90:cb3d968589d8	326	/! @brief Format value for bitfield LLWU_PE2_WUPE4. /
Kojto	90:cb3d968589d8	327	#define BF_LLWU_PE2_WUPE4(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE4) & BM_LLWU_PE2_WUPE4)
Kojto	90:cb3d968589d8	328
Kojto	90:cb3d968589d8	329	/! @brief Set the WUPE4 field to a new value. /
Kojto	90:cb3d968589d8	330	#define BW_LLWU_PE2_WUPE4(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE4) \| BF_LLWU_PE2_WUPE4(v)))
Kojto	90:cb3d968589d8	331	/@}/
Kojto	90:cb3d968589d8	332
Kojto	90:cb3d968589d8	333	/*!
Kojto	90:cb3d968589d8	334	* @name Register LLWU_PE2, field WUPE5[3:2] (RW)
Kojto	90:cb3d968589d8	335	*
Kojto	90:cb3d968589d8	336	* Enables and configures the edge detection for the wakeup pin.
Kojto	90:cb3d968589d8	337	*
Kojto	90:cb3d968589d8	338	* Values:
Kojto	90:cb3d968589d8	339	* - 00 - External input pin disabled as wakeup input
Kojto	90:cb3d968589d8	340	* - 01 - External input pin enabled with rising edge detection
Kojto	90:cb3d968589d8	341	* - 10 - External input pin enabled with falling edge detection
Kojto	90:cb3d968589d8	342	* - 11 - External input pin enabled with any change detection
Kojto	90:cb3d968589d8	343	*/
Kojto	90:cb3d968589d8	344	/@{/
Kojto	90:cb3d968589d8	345	#define BP_LLWU_PE2_WUPE5 (2U) /!< Bit position for LLWU_PE2_WUPE5. /
Kojto	90:cb3d968589d8	346	#define BM_LLWU_PE2_WUPE5 (0x0CU) /!< Bit mask for LLWU_PE2_WUPE5. /
Kojto	90:cb3d968589d8	347	#define BS_LLWU_PE2_WUPE5 (2U) /!< Bit field size in bits for LLWU_PE2_WUPE5. /
Kojto	90:cb3d968589d8	348
Kojto	90:cb3d968589d8	349	/! @brief Read current value of the LLWU_PE2_WUPE5 field. /
Kojto	90:cb3d968589d8	350	#define BR_LLWU_PE2_WUPE5(x) (HW_LLWU_PE2(x).B.WUPE5)
Kojto	90:cb3d968589d8	351
Kojto	90:cb3d968589d8	352	/! @brief Format value for bitfield LLWU_PE2_WUPE5. /
Kojto	90:cb3d968589d8	353	#define BF_LLWU_PE2_WUPE5(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE5) & BM_LLWU_PE2_WUPE5)
Kojto	90:cb3d968589d8	354
Kojto	90:cb3d968589d8	355	/! @brief Set the WUPE5 field to a new value. /
Kojto	90:cb3d968589d8	356	#define BW_LLWU_PE2_WUPE5(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE5) \| BF_LLWU_PE2_WUPE5(v)))
Kojto	90:cb3d968589d8	357	/@}/
Kojto	90:cb3d968589d8	358
Kojto	90:cb3d968589d8	359	/*!
Kojto	90:cb3d968589d8	360	* @name Register LLWU_PE2, field WUPE6[5:4] (RW)
Kojto	90:cb3d968589d8	361	*
Kojto	90:cb3d968589d8	362	* Enables and configures the edge detection for the wakeup pin.
Kojto	90:cb3d968589d8	363	*
Kojto	90:cb3d968589d8	364	* Values:
Kojto	90:cb3d968589d8	365	* - 00 - External input pin disabled as wakeup input
Kojto	90:cb3d968589d8	366	* - 01 - External input pin enabled with rising edge detection
Kojto	90:cb3d968589d8	367	* - 10 - External input pin enabled with falling edge detection
Kojto	90:cb3d968589d8	368	* - 11 - External input pin enabled with any change detection
Kojto	90:cb3d968589d8	369	*/
Kojto	90:cb3d968589d8	370	/@{/
Kojto	90:cb3d968589d8	371	#define BP_LLWU_PE2_WUPE6 (4U) /!< Bit position for LLWU_PE2_WUPE6. /
Kojto	90:cb3d968589d8	372	#define BM_LLWU_PE2_WUPE6 (0x30U) /!< Bit mask for LLWU_PE2_WUPE6. /
Kojto	90:cb3d968589d8	373	#define BS_LLWU_PE2_WUPE6 (2U) /!< Bit field size in bits for LLWU_PE2_WUPE6. /
Kojto	90:cb3d968589d8	374
Kojto	90:cb3d968589d8	375	/! @brief Read current value of the LLWU_PE2_WUPE6 field. /
Kojto	90:cb3d968589d8	376	#define BR_LLWU_PE2_WUPE6(x) (HW_LLWU_PE2(x).B.WUPE6)
Kojto	90:cb3d968589d8	377
Kojto	90:cb3d968589d8	378	/! @brief Format value for bitfield LLWU_PE2_WUPE6. /
Kojto	90:cb3d968589d8	379	#define BF_LLWU_PE2_WUPE6(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE6) & BM_LLWU_PE2_WUPE6)
Kojto	90:cb3d968589d8	380
Kojto	90:cb3d968589d8	381	/! @brief Set the WUPE6 field to a new value. /
Kojto	90:cb3d968589d8	382	#define BW_LLWU_PE2_WUPE6(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE6) \| BF_LLWU_PE2_WUPE6(v)))
Kojto	90:cb3d968589d8	383	/@}/
Kojto	90:cb3d968589d8	384
Kojto	90:cb3d968589d8	385	/*!
Kojto	90:cb3d968589d8	386	* @name Register LLWU_PE2, field WUPE7[7:6] (RW)
Kojto	90:cb3d968589d8	387	*
Kojto	90:cb3d968589d8	388	* Enables and configures the edge detection for the wakeup pin.
Kojto	90:cb3d968589d8	389	*
Kojto	90:cb3d968589d8	390	* Values:
Kojto	90:cb3d968589d8	391	* - 00 - External input pin disabled as wakeup input
Kojto	90:cb3d968589d8	392	* - 01 - External input pin enabled with rising edge detection
Kojto	90:cb3d968589d8	393	* - 10 - External input pin enabled with falling edge detection
Kojto	90:cb3d968589d8	394	* - 11 - External input pin enabled with any change detection
Kojto	90:cb3d968589d8	395	*/
Kojto	90:cb3d968589d8	396	/@{/
Kojto	90:cb3d968589d8	397	#define BP_LLWU_PE2_WUPE7 (6U) /!< Bit position for LLWU_PE2_WUPE7. /
Kojto	90:cb3d968589d8	398	#define BM_LLWU_PE2_WUPE7 (0xC0U) /!< Bit mask for LLWU_PE2_WUPE7. /
Kojto	90:cb3d968589d8	399	#define BS_LLWU_PE2_WUPE7 (2U) /!< Bit field size in bits for LLWU_PE2_WUPE7. /
Kojto	90:cb3d968589d8	400
Kojto	90:cb3d968589d8	401	/! @brief Read current value of the LLWU_PE2_WUPE7 field. /
Kojto	90:cb3d968589d8	402	#define BR_LLWU_PE2_WUPE7(x) (HW_LLWU_PE2(x).B.WUPE7)
Kojto	90:cb3d968589d8	403
Kojto	90:cb3d968589d8	404	/! @brief Format value for bitfield LLWU_PE2_WUPE7. /
Kojto	90:cb3d968589d8	405	#define BF_LLWU_PE2_WUPE7(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE7) & BM_LLWU_PE2_WUPE7)
Kojto	90:cb3d968589d8	406
Kojto	90:cb3d968589d8	407	/! @brief Set the WUPE7 field to a new value. /
Kojto	90:cb3d968589d8	408	#define BW_LLWU_PE2_WUPE7(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE7) \| BF_LLWU_PE2_WUPE7(v)))
Kojto	90:cb3d968589d8	409	/@}/
Kojto	90:cb3d968589d8	410
Kojto	90:cb3d968589d8	411	/*******************************************************************************
Kojto	90:cb3d968589d8	412	* HW_LLWU_PE3 - LLWU Pin Enable 3 register
Kojto	90:cb3d968589d8	413	******************************************************************************/
Kojto	90:cb3d968589d8	414
Kojto	90:cb3d968589d8	415	/*!
Kojto	90:cb3d968589d8	416	* @brief HW_LLWU_PE3 - LLWU Pin Enable 3 register (RW)
Kojto	90:cb3d968589d8	417	*
Kojto	90:cb3d968589d8	418	* Reset value: 0x00U
Kojto	90:cb3d968589d8	419	*
Kojto	90:cb3d968589d8	420	* LLWU_PE3 contains the field to enable and select the edge detect type for the
Kojto	90:cb3d968589d8	421	* external wakeup input pins LLWU_P11-LLWU_P8. This register is reset on Chip
Kojto	90:cb3d968589d8	422	* Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
Kojto	90:cb3d968589d8	423	* unaffected by reset types that do not trigger Chip Reset not VLLS. See the
Kojto	90:cb3d968589d8	424	* IntroductionInformation found here describes the registers of the Reset Control Module
Kojto	90:cb3d968589d8	425	* (RCM). The RCM implements many of the reset functions for the chip. See the
Kojto	90:cb3d968589d8	426	* chip's reset chapter for more information. details for more information.
Kojto	90:cb3d968589d8	427	*/
Kojto	90:cb3d968589d8	428	typedef union _hw_llwu_pe3
Kojto	90:cb3d968589d8	429	{
Kojto	90:cb3d968589d8	430	uint8_t U;
Kojto	90:cb3d968589d8	431	struct _hw_llwu_pe3_bitfields
Kojto	90:cb3d968589d8	432	{
Kojto	90:cb3d968589d8	433	uint8_t WUPE8 : 2; /!< [1:0] Wakeup Pin Enable For LLWU_P8 /
Kojto	90:cb3d968589d8	434	uint8_t WUPE9 : 2; /!< [3:2] Wakeup Pin Enable For LLWU_P9 /
Kojto	90:cb3d968589d8	435	uint8_t WUPE10 : 2; /!< [5:4] Wakeup Pin Enable For LLWU_P10 /
Kojto	90:cb3d968589d8	436	uint8_t WUPE11 : 2; /!< [7:6] Wakeup Pin Enable For LLWU_P11 /
Kojto	90:cb3d968589d8	437	} B;
Kojto	90:cb3d968589d8	438	} hw_llwu_pe3_t;
Kojto	90:cb3d968589d8	439
Kojto	90:cb3d968589d8	440	/*!
Kojto	90:cb3d968589d8	441	* @name Constants and macros for entire LLWU_PE3 register
Kojto	90:cb3d968589d8	442	*/
Kojto	90:cb3d968589d8	443	/@{/
Kojto	90:cb3d968589d8	444	#define HW_LLWU_PE3_ADDR(x) ((x) + 0x2U)
Kojto	90:cb3d968589d8	445
Kojto	90:cb3d968589d8	446	#define HW_LLWU_PE3(x) ((__IO hw_llwu_pe3_t ) HW_LLWU_PE3_ADDR(x))
Kojto	90:cb3d968589d8	447	#define HW_LLWU_PE3_RD(x) (HW_LLWU_PE3(x).U)
Kojto	90:cb3d968589d8	448	#define HW_LLWU_PE3_WR(x, v) (HW_LLWU_PE3(x).U = (v))
Kojto	90:cb3d968589d8	449	#define HW_LLWU_PE3_SET(x, v) (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) \| (v)))
Kojto	90:cb3d968589d8	450	#define HW_LLWU_PE3_CLR(x, v) (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	451	#define HW_LLWU_PE3_TOG(x, v) (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	452	/@}/
Kojto	90:cb3d968589d8	453
Kojto	90:cb3d968589d8	454	/*
Kojto	90:cb3d968589d8	455	* Constants & macros for individual LLWU_PE3 bitfields
Kojto	90:cb3d968589d8	456	*/
Kojto	90:cb3d968589d8	457
Kojto	90:cb3d968589d8	458	/*!
Kojto	90:cb3d968589d8	459	* @name Register LLWU_PE3, field WUPE8[1:0] (RW)
Kojto	90:cb3d968589d8	460	*
Kojto	90:cb3d968589d8	461	* Enables and configures the edge detection for the wakeup pin.
Kojto	90:cb3d968589d8	462	*
Kojto	90:cb3d968589d8	463	* Values:
Kojto	90:cb3d968589d8	464	* - 00 - External input pin disabled as wakeup input
Kojto	90:cb3d968589d8	465	* - 01 - External input pin enabled with rising edge detection
Kojto	90:cb3d968589d8	466	* - 10 - External input pin enabled with falling edge detection
Kojto	90:cb3d968589d8	467	* - 11 - External input pin enabled with any change detection
Kojto	90:cb3d968589d8	468	*/
Kojto	90:cb3d968589d8	469	/@{/
Kojto	90:cb3d968589d8	470	#define BP_LLWU_PE3_WUPE8 (0U) /!< Bit position for LLWU_PE3_WUPE8. /
Kojto	90:cb3d968589d8	471	#define BM_LLWU_PE3_WUPE8 (0x03U) /!< Bit mask for LLWU_PE3_WUPE8. /
Kojto	90:cb3d968589d8	472	#define BS_LLWU_PE3_WUPE8 (2U) /!< Bit field size in bits for LLWU_PE3_WUPE8. /
Kojto	90:cb3d968589d8	473
Kojto	90:cb3d968589d8	474	/! @brief Read current value of the LLWU_PE3_WUPE8 field. /
Kojto	90:cb3d968589d8	475	#define BR_LLWU_PE3_WUPE8(x) (HW_LLWU_PE3(x).B.WUPE8)
Kojto	90:cb3d968589d8	476
Kojto	90:cb3d968589d8	477	/! @brief Format value for bitfield LLWU_PE3_WUPE8. /
Kojto	90:cb3d968589d8	478	#define BF_LLWU_PE3_WUPE8(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE8) & BM_LLWU_PE3_WUPE8)
Kojto	90:cb3d968589d8	479
Kojto	90:cb3d968589d8	480	/! @brief Set the WUPE8 field to a new value. /
Kojto	90:cb3d968589d8	481	#define BW_LLWU_PE3_WUPE8(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE8) \| BF_LLWU_PE3_WUPE8(v)))
Kojto	90:cb3d968589d8	482	/@}/
Kojto	90:cb3d968589d8	483
Kojto	90:cb3d968589d8	484	/*!
Kojto	90:cb3d968589d8	485	* @name Register LLWU_PE3, field WUPE9[3:2] (RW)
Kojto	90:cb3d968589d8	486	*
Kojto	90:cb3d968589d8	487	* Enables and configures the edge detection for the wakeup pin.
Kojto	90:cb3d968589d8	488	*
Kojto	90:cb3d968589d8	489	* Values:
Kojto	90:cb3d968589d8	490	* - 00 - External input pin disabled as wakeup input
Kojto	90:cb3d968589d8	491	* - 01 - External input pin enabled with rising edge detection
Kojto	90:cb3d968589d8	492	* - 10 - External input pin enabled with falling edge detection
Kojto	90:cb3d968589d8	493	* - 11 - External input pin enabled with any change detection
Kojto	90:cb3d968589d8	494	*/
Kojto	90:cb3d968589d8	495	/@{/
Kojto	90:cb3d968589d8	496	#define BP_LLWU_PE3_WUPE9 (2U) /!< Bit position for LLWU_PE3_WUPE9. /
Kojto	90:cb3d968589d8	497	#define BM_LLWU_PE3_WUPE9 (0x0CU) /!< Bit mask for LLWU_PE3_WUPE9. /
Kojto	90:cb3d968589d8	498	#define BS_LLWU_PE3_WUPE9 (2U) /!< Bit field size in bits for LLWU_PE3_WUPE9. /
Kojto	90:cb3d968589d8	499
Kojto	90:cb3d968589d8	500	/! @brief Read current value of the LLWU_PE3_WUPE9 field. /
Kojto	90:cb3d968589d8	501	#define BR_LLWU_PE3_WUPE9(x) (HW_LLWU_PE3(x).B.WUPE9)
Kojto	90:cb3d968589d8	502
Kojto	90:cb3d968589d8	503	/! @brief Format value for bitfield LLWU_PE3_WUPE9. /
Kojto	90:cb3d968589d8	504	#define BF_LLWU_PE3_WUPE9(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE9) & BM_LLWU_PE3_WUPE9)
Kojto	90:cb3d968589d8	505
Kojto	90:cb3d968589d8	506	/! @brief Set the WUPE9 field to a new value. /
Kojto	90:cb3d968589d8	507	#define BW_LLWU_PE3_WUPE9(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE9) \| BF_LLWU_PE3_WUPE9(v)))
Kojto	90:cb3d968589d8	508	/@}/
Kojto	90:cb3d968589d8	509
Kojto	90:cb3d968589d8	510	/*!
Kojto	90:cb3d968589d8	511	* @name Register LLWU_PE3, field WUPE10[5:4] (RW)
Kojto	90:cb3d968589d8	512	*
Kojto	90:cb3d968589d8	513	* Enables and configures the edge detection for the wakeup pin.
Kojto	90:cb3d968589d8	514	*
Kojto	90:cb3d968589d8	515	* Values:
Kojto	90:cb3d968589d8	516	* - 00 - External input pin disabled as wakeup input
Kojto	90:cb3d968589d8	517	* - 01 - External input pin enabled with rising edge detection
Kojto	90:cb3d968589d8	518	* - 10 - External input pin enabled with falling edge detection
Kojto	90:cb3d968589d8	519	* - 11 - External input pin enabled with any change detection
Kojto	90:cb3d968589d8	520	*/
Kojto	90:cb3d968589d8	521	/@{/
Kojto	90:cb3d968589d8	522	#define BP_LLWU_PE3_WUPE10 (4U) /!< Bit position for LLWU_PE3_WUPE10. /
Kojto	90:cb3d968589d8	523	#define BM_LLWU_PE3_WUPE10 (0x30U) /!< Bit mask for LLWU_PE3_WUPE10. /
Kojto	90:cb3d968589d8	524	#define BS_LLWU_PE3_WUPE10 (2U) /!< Bit field size in bits for LLWU_PE3_WUPE10. /
Kojto	90:cb3d968589d8	525
Kojto	90:cb3d968589d8	526	/! @brief Read current value of the LLWU_PE3_WUPE10 field. /
Kojto	90:cb3d968589d8	527	#define BR_LLWU_PE3_WUPE10(x) (HW_LLWU_PE3(x).B.WUPE10)
Kojto	90:cb3d968589d8	528
Kojto	90:cb3d968589d8	529	/! @brief Format value for bitfield LLWU_PE3_WUPE10. /
Kojto	90:cb3d968589d8	530	#define BF_LLWU_PE3_WUPE10(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE10) & BM_LLWU_PE3_WUPE10)
Kojto	90:cb3d968589d8	531
Kojto	90:cb3d968589d8	532	/! @brief Set the WUPE10 field to a new value. /
Kojto	90:cb3d968589d8	533	#define BW_LLWU_PE3_WUPE10(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE10) \| BF_LLWU_PE3_WUPE10(v)))
Kojto	90:cb3d968589d8	534	/@}/
Kojto	90:cb3d968589d8	535
Kojto	90:cb3d968589d8	536	/*!
Kojto	90:cb3d968589d8	537	* @name Register LLWU_PE3, field WUPE11[7:6] (RW)
Kojto	90:cb3d968589d8	538	*
Kojto	90:cb3d968589d8	539	* Enables and configures the edge detection for the wakeup pin.
Kojto	90:cb3d968589d8	540	*
Kojto	90:cb3d968589d8	541	* Values:
Kojto	90:cb3d968589d8	542	* - 00 - External input pin disabled as wakeup input
Kojto	90:cb3d968589d8	543	* - 01 - External input pin enabled with rising edge detection
Kojto	90:cb3d968589d8	544	* - 10 - External input pin enabled with falling edge detection
Kojto	90:cb3d968589d8	545	* - 11 - External input pin enabled with any change detection
Kojto	90:cb3d968589d8	546	*/
Kojto	90:cb3d968589d8	547	/@{/
Kojto	90:cb3d968589d8	548	#define BP_LLWU_PE3_WUPE11 (6U) /!< Bit position for LLWU_PE3_WUPE11. /
Kojto	90:cb3d968589d8	549	#define BM_LLWU_PE3_WUPE11 (0xC0U) /!< Bit mask for LLWU_PE3_WUPE11. /
Kojto	90:cb3d968589d8	550	#define BS_LLWU_PE3_WUPE11 (2U) /!< Bit field size in bits for LLWU_PE3_WUPE11. /
Kojto	90:cb3d968589d8	551
Kojto	90:cb3d968589d8	552	/! @brief Read current value of the LLWU_PE3_WUPE11 field. /
Kojto	90:cb3d968589d8	553	#define BR_LLWU_PE3_WUPE11(x) (HW_LLWU_PE3(x).B.WUPE11)
Kojto	90:cb3d968589d8	554
Kojto	90:cb3d968589d8	555	/! @brief Format value for bitfield LLWU_PE3_WUPE11. /
Kojto	90:cb3d968589d8	556	#define BF_LLWU_PE3_WUPE11(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE11) & BM_LLWU_PE3_WUPE11)
Kojto	90:cb3d968589d8	557
Kojto	90:cb3d968589d8	558	/! @brief Set the WUPE11 field to a new value. /
Kojto	90:cb3d968589d8	559	#define BW_LLWU_PE3_WUPE11(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE11) \| BF_LLWU_PE3_WUPE11(v)))
Kojto	90:cb3d968589d8	560	/@}/
Kojto	90:cb3d968589d8	561
Kojto	90:cb3d968589d8	562	/*******************************************************************************
Kojto	90:cb3d968589d8	563	* HW_LLWU_PE4 - LLWU Pin Enable 4 register
Kojto	90:cb3d968589d8	564	******************************************************************************/
Kojto	90:cb3d968589d8	565
Kojto	90:cb3d968589d8	566	/*!
Kojto	90:cb3d968589d8	567	* @brief HW_LLWU_PE4 - LLWU Pin Enable 4 register (RW)
Kojto	90:cb3d968589d8	568	*
Kojto	90:cb3d968589d8	569	* Reset value: 0x00U
Kojto	90:cb3d968589d8	570	*
Kojto	90:cb3d968589d8	571	* LLWU_PE4 contains the field to enable and select the edge detect type for the
Kojto	90:cb3d968589d8	572	* external wakeup input pins LLWU_P15-LLWU_P12. This register is reset on Chip
Kojto	90:cb3d968589d8	573	* Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
Kojto	90:cb3d968589d8	574	* unaffected by reset types that do not trigger Chip Reset not VLLS. See the
Kojto	90:cb3d968589d8	575	* IntroductionInformation found here describes the registers of the Reset Control
Kojto	90:cb3d968589d8	576	* Module (RCM). The RCM implements many of the reset functions for the chip. See the
Kojto	90:cb3d968589d8	577	* chip's reset chapter for more information. details for more information.
Kojto	90:cb3d968589d8	578	*/
Kojto	90:cb3d968589d8	579	typedef union _hw_llwu_pe4
Kojto	90:cb3d968589d8	580	{
Kojto	90:cb3d968589d8	581	uint8_t U;
Kojto	90:cb3d968589d8	582	struct _hw_llwu_pe4_bitfields
Kojto	90:cb3d968589d8	583	{
Kojto	90:cb3d968589d8	584	uint8_t WUPE12 : 2; /!< [1:0] Wakeup Pin Enable For LLWU_P12 /
Kojto	90:cb3d968589d8	585	uint8_t WUPE13 : 2; /!< [3:2] Wakeup Pin Enable For LLWU_P13 /
Kojto	90:cb3d968589d8	586	uint8_t WUPE14 : 2; /!< [5:4] Wakeup Pin Enable For LLWU_P14 /
Kojto	90:cb3d968589d8	587	uint8_t WUPE15 : 2; /!< [7:6] Wakeup Pin Enable For LLWU_P15 /
Kojto	90:cb3d968589d8	588	} B;
Kojto	90:cb3d968589d8	589	} hw_llwu_pe4_t;
Kojto	90:cb3d968589d8	590
Kojto	90:cb3d968589d8	591	/*!
Kojto	90:cb3d968589d8	592	* @name Constants and macros for entire LLWU_PE4 register
Kojto	90:cb3d968589d8	593	*/
Kojto	90:cb3d968589d8	594	/@{/
Kojto	90:cb3d968589d8	595	#define HW_LLWU_PE4_ADDR(x) ((x) + 0x3U)
Kojto	90:cb3d968589d8	596
Kojto	90:cb3d968589d8	597	#define HW_LLWU_PE4(x) ((__IO hw_llwu_pe4_t ) HW_LLWU_PE4_ADDR(x))
Kojto	90:cb3d968589d8	598	#define HW_LLWU_PE4_RD(x) (HW_LLWU_PE4(x).U)
Kojto	90:cb3d968589d8	599	#define HW_LLWU_PE4_WR(x, v) (HW_LLWU_PE4(x).U = (v))
Kojto	90:cb3d968589d8	600	#define HW_LLWU_PE4_SET(x, v) (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) \| (v)))
Kojto	90:cb3d968589d8	601	#define HW_LLWU_PE4_CLR(x, v) (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	602	#define HW_LLWU_PE4_TOG(x, v) (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	603	/@}/
Kojto	90:cb3d968589d8	604
Kojto	90:cb3d968589d8	605	/*
Kojto	90:cb3d968589d8	606	* Constants & macros for individual LLWU_PE4 bitfields
Kojto	90:cb3d968589d8	607	*/
Kojto	90:cb3d968589d8	608
Kojto	90:cb3d968589d8	609	/*!
Kojto	90:cb3d968589d8	610	* @name Register LLWU_PE4, field WUPE12[1:0] (RW)
Kojto	90:cb3d968589d8	611	*
Kojto	90:cb3d968589d8	612	* Enables and configures the edge detection for the wakeup pin.
Kojto	90:cb3d968589d8	613	*
Kojto	90:cb3d968589d8	614	* Values:
Kojto	90:cb3d968589d8	615	* - 00 - External input pin disabled as wakeup input
Kojto	90:cb3d968589d8	616	* - 01 - External input pin enabled with rising edge detection
Kojto	90:cb3d968589d8	617	* - 10 - External input pin enabled with falling edge detection
Kojto	90:cb3d968589d8	618	* - 11 - External input pin enabled with any change detection
Kojto	90:cb3d968589d8	619	*/
Kojto	90:cb3d968589d8	620	/@{/
Kojto	90:cb3d968589d8	621	#define BP_LLWU_PE4_WUPE12 (0U) /!< Bit position for LLWU_PE4_WUPE12. /
Kojto	90:cb3d968589d8	622	#define BM_LLWU_PE4_WUPE12 (0x03U) /!< Bit mask for LLWU_PE4_WUPE12. /
Kojto	90:cb3d968589d8	623	#define BS_LLWU_PE4_WUPE12 (2U) /!< Bit field size in bits for LLWU_PE4_WUPE12. /
Kojto	90:cb3d968589d8	624
Kojto	90:cb3d968589d8	625	/! @brief Read current value of the LLWU_PE4_WUPE12 field. /
Kojto	90:cb3d968589d8	626	#define BR_LLWU_PE4_WUPE12(x) (HW_LLWU_PE4(x).B.WUPE12)
Kojto	90:cb3d968589d8	627
Kojto	90:cb3d968589d8	628	/! @brief Format value for bitfield LLWU_PE4_WUPE12. /
Kojto	90:cb3d968589d8	629	#define BF_LLWU_PE4_WUPE12(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE12) & BM_LLWU_PE4_WUPE12)
Kojto	90:cb3d968589d8	630
Kojto	90:cb3d968589d8	631	/! @brief Set the WUPE12 field to a new value. /
Kojto	90:cb3d968589d8	632	#define BW_LLWU_PE4_WUPE12(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE12) \| BF_LLWU_PE4_WUPE12(v)))
Kojto	90:cb3d968589d8	633	/@}/
Kojto	90:cb3d968589d8	634
Kojto	90:cb3d968589d8	635	/*!
Kojto	90:cb3d968589d8	636	* @name Register LLWU_PE4, field WUPE13[3:2] (RW)
Kojto	90:cb3d968589d8	637	*
Kojto	90:cb3d968589d8	638	* Enables and configures the edge detection for the wakeup pin.
Kojto	90:cb3d968589d8	639	*
Kojto	90:cb3d968589d8	640	* Values:
Kojto	90:cb3d968589d8	641	* - 00 - External input pin disabled as wakeup input
Kojto	90:cb3d968589d8	642	* - 01 - External input pin enabled with rising edge detection
Kojto	90:cb3d968589d8	643	* - 10 - External input pin enabled with falling edge detection
Kojto	90:cb3d968589d8	644	* - 11 - External input pin enabled with any change detection
Kojto	90:cb3d968589d8	645	*/
Kojto	90:cb3d968589d8	646	/@{/
Kojto	90:cb3d968589d8	647	#define BP_LLWU_PE4_WUPE13 (2U) /!< Bit position for LLWU_PE4_WUPE13. /
Kojto	90:cb3d968589d8	648	#define BM_LLWU_PE4_WUPE13 (0x0CU) /!< Bit mask for LLWU_PE4_WUPE13. /
Kojto	90:cb3d968589d8	649	#define BS_LLWU_PE4_WUPE13 (2U) /!< Bit field size in bits for LLWU_PE4_WUPE13. /
Kojto	90:cb3d968589d8	650
Kojto	90:cb3d968589d8	651	/! @brief Read current value of the LLWU_PE4_WUPE13 field. /
Kojto	90:cb3d968589d8	652	#define BR_LLWU_PE4_WUPE13(x) (HW_LLWU_PE4(x).B.WUPE13)
Kojto	90:cb3d968589d8	653
Kojto	90:cb3d968589d8	654	/! @brief Format value for bitfield LLWU_PE4_WUPE13. /
Kojto	90:cb3d968589d8	655	#define BF_LLWU_PE4_WUPE13(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE13) & BM_LLWU_PE4_WUPE13)
Kojto	90:cb3d968589d8	656
Kojto	90:cb3d968589d8	657	/! @brief Set the WUPE13 field to a new value. /
Kojto	90:cb3d968589d8	658	#define BW_LLWU_PE4_WUPE13(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE13) \| BF_LLWU_PE4_WUPE13(v)))
Kojto	90:cb3d968589d8	659	/@}/
Kojto	90:cb3d968589d8	660
Kojto	90:cb3d968589d8	661	/*!
Kojto	90:cb3d968589d8	662	* @name Register LLWU_PE4, field WUPE14[5:4] (RW)
Kojto	90:cb3d968589d8	663	*
Kojto	90:cb3d968589d8	664	* Enables and configures the edge detection for the wakeup pin.
Kojto	90:cb3d968589d8	665	*
Kojto	90:cb3d968589d8	666	* Values:
Kojto	90:cb3d968589d8	667	* - 00 - External input pin disabled as wakeup input
Kojto	90:cb3d968589d8	668	* - 01 - External input pin enabled with rising edge detection
Kojto	90:cb3d968589d8	669	* - 10 - External input pin enabled with falling edge detection
Kojto	90:cb3d968589d8	670	* - 11 - External input pin enabled with any change detection
Kojto	90:cb3d968589d8	671	*/
Kojto	90:cb3d968589d8	672	/@{/
Kojto	90:cb3d968589d8	673	#define BP_LLWU_PE4_WUPE14 (4U) /!< Bit position for LLWU_PE4_WUPE14. /
Kojto	90:cb3d968589d8	674	#define BM_LLWU_PE4_WUPE14 (0x30U) /!< Bit mask for LLWU_PE4_WUPE14. /
Kojto	90:cb3d968589d8	675	#define BS_LLWU_PE4_WUPE14 (2U) /!< Bit field size in bits for LLWU_PE4_WUPE14. /
Kojto	90:cb3d968589d8	676
Kojto	90:cb3d968589d8	677	/! @brief Read current value of the LLWU_PE4_WUPE14 field. /
Kojto	90:cb3d968589d8	678	#define BR_LLWU_PE4_WUPE14(x) (HW_LLWU_PE4(x).B.WUPE14)
Kojto	90:cb3d968589d8	679
Kojto	90:cb3d968589d8	680	/! @brief Format value for bitfield LLWU_PE4_WUPE14. /
Kojto	90:cb3d968589d8	681	#define BF_LLWU_PE4_WUPE14(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE14) & BM_LLWU_PE4_WUPE14)
Kojto	90:cb3d968589d8	682
Kojto	90:cb3d968589d8	683	/! @brief Set the WUPE14 field to a new value. /
Kojto	90:cb3d968589d8	684	#define BW_LLWU_PE4_WUPE14(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE14) \| BF_LLWU_PE4_WUPE14(v)))
Kojto	90:cb3d968589d8	685	/@}/
Kojto	90:cb3d968589d8	686
Kojto	90:cb3d968589d8	687	/*!
Kojto	90:cb3d968589d8	688	* @name Register LLWU_PE4, field WUPE15[7:6] (RW)
Kojto	90:cb3d968589d8	689	*
Kojto	90:cb3d968589d8	690	* Enables and configures the edge detection for the wakeup pin.
Kojto	90:cb3d968589d8	691	*
Kojto	90:cb3d968589d8	692	* Values:
Kojto	90:cb3d968589d8	693	* - 00 - External input pin disabled as wakeup input
Kojto	90:cb3d968589d8	694	* - 01 - External input pin enabled with rising edge detection
Kojto	90:cb3d968589d8	695	* - 10 - External input pin enabled with falling edge detection
Kojto	90:cb3d968589d8	696	* - 11 - External input pin enabled with any change detection
Kojto	90:cb3d968589d8	697	*/
Kojto	90:cb3d968589d8	698	/@{/
Kojto	90:cb3d968589d8	699	#define BP_LLWU_PE4_WUPE15 (6U) /!< Bit position for LLWU_PE4_WUPE15. /
Kojto	90:cb3d968589d8	700	#define BM_LLWU_PE4_WUPE15 (0xC0U) /!< Bit mask for LLWU_PE4_WUPE15. /
Kojto	90:cb3d968589d8	701	#define BS_LLWU_PE4_WUPE15 (2U) /!< Bit field size in bits for LLWU_PE4_WUPE15. /
Kojto	90:cb3d968589d8	702
Kojto	90:cb3d968589d8	703	/! @brief Read current value of the LLWU_PE4_WUPE15 field. /
Kojto	90:cb3d968589d8	704	#define BR_LLWU_PE4_WUPE15(x) (HW_LLWU_PE4(x).B.WUPE15)
Kojto	90:cb3d968589d8	705
Kojto	90:cb3d968589d8	706	/! @brief Format value for bitfield LLWU_PE4_WUPE15. /
Kojto	90:cb3d968589d8	707	#define BF_LLWU_PE4_WUPE15(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE15) & BM_LLWU_PE4_WUPE15)
Kojto	90:cb3d968589d8	708
Kojto	90:cb3d968589d8	709	/! @brief Set the WUPE15 field to a new value. /
Kojto	90:cb3d968589d8	710	#define BW_LLWU_PE4_WUPE15(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE15) \| BF_LLWU_PE4_WUPE15(v)))
Kojto	90:cb3d968589d8	711	/@}/
Kojto	90:cb3d968589d8	712
Kojto	90:cb3d968589d8	713	/*******************************************************************************
Kojto	90:cb3d968589d8	714	* HW_LLWU_ME - LLWU Module Enable register
Kojto	90:cb3d968589d8	715	******************************************************************************/
Kojto	90:cb3d968589d8	716
Kojto	90:cb3d968589d8	717	/*!
Kojto	90:cb3d968589d8	718	* @brief HW_LLWU_ME - LLWU Module Enable register (RW)
Kojto	90:cb3d968589d8	719	*
Kojto	90:cb3d968589d8	720	* Reset value: 0x00U
Kojto	90:cb3d968589d8	721	*
Kojto	90:cb3d968589d8	722	* LLWU_ME contains the bits to enable the internal module flag as a wakeup
Kojto	90:cb3d968589d8	723	* input source for inputs MWUF7-MWUF0. This register is reset on Chip Reset not VLLS
Kojto	90:cb3d968589d8	724	* and by reset types that trigger Chip Reset not VLLS. It is unaffected by
Kojto	90:cb3d968589d8	725	* reset types that do not trigger Chip Reset not VLLS. See the
Kojto	90:cb3d968589d8	726	* IntroductionInformation found here describes the registers of the Reset Control Module (RCM). The
Kojto	90:cb3d968589d8	727	* RCM implements many of the reset functions for the chip. See the chip's reset
Kojto	90:cb3d968589d8	728	* chapter for more information. details for more information.
Kojto	90:cb3d968589d8	729	*/
Kojto	90:cb3d968589d8	730	typedef union _hw_llwu_me
Kojto	90:cb3d968589d8	731	{
Kojto	90:cb3d968589d8	732	uint8_t U;
Kojto	90:cb3d968589d8	733	struct _hw_llwu_me_bitfields
Kojto	90:cb3d968589d8	734	{
Kojto	90:cb3d968589d8	735	uint8_t WUME0 : 1; /!< [0] Wakeup Module Enable For Module 0 /
Kojto	90:cb3d968589d8	736	uint8_t WUME1 : 1; /!< [1] Wakeup Module Enable for Module 1 /
Kojto	90:cb3d968589d8	737	uint8_t WUME2 : 1; /!< [2] Wakeup Module Enable For Module 2 /
Kojto	90:cb3d968589d8	738	uint8_t WUME3 : 1; /!< [3] Wakeup Module Enable For Module 3 /
Kojto	90:cb3d968589d8	739	uint8_t WUME4 : 1; /!< [4] Wakeup Module Enable For Module 4 /
Kojto	90:cb3d968589d8	740	uint8_t WUME5 : 1; /!< [5] Wakeup Module Enable For Module 5 /
Kojto	90:cb3d968589d8	741	uint8_t WUME6 : 1; /!< [6] Wakeup Module Enable For Module 6 /
Kojto	90:cb3d968589d8	742	uint8_t WUME7 : 1; /!< [7] Wakeup Module Enable For Module 7 /
Kojto	90:cb3d968589d8	743	} B;
Kojto	90:cb3d968589d8	744	} hw_llwu_me_t;
Kojto	90:cb3d968589d8	745
Kojto	90:cb3d968589d8	746	/*!
Kojto	90:cb3d968589d8	747	* @name Constants and macros for entire LLWU_ME register
Kojto	90:cb3d968589d8	748	*/
Kojto	90:cb3d968589d8	749	/@{/
Kojto	90:cb3d968589d8	750	#define HW_LLWU_ME_ADDR(x) ((x) + 0x4U)
Kojto	90:cb3d968589d8	751
Kojto	90:cb3d968589d8	752	#define HW_LLWU_ME(x) ((__IO hw_llwu_me_t ) HW_LLWU_ME_ADDR(x))
Kojto	90:cb3d968589d8	753	#define HW_LLWU_ME_RD(x) (HW_LLWU_ME(x).U)
Kojto	90:cb3d968589d8	754	#define HW_LLWU_ME_WR(x, v) (HW_LLWU_ME(x).U = (v))
Kojto	90:cb3d968589d8	755	#define HW_LLWU_ME_SET(x, v) (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) \| (v)))
Kojto	90:cb3d968589d8	756	#define HW_LLWU_ME_CLR(x, v) (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	757	#define HW_LLWU_ME_TOG(x, v) (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	758	/@}/
Kojto	90:cb3d968589d8	759
Kojto	90:cb3d968589d8	760	/*
Kojto	90:cb3d968589d8	761	* Constants & macros for individual LLWU_ME bitfields
Kojto	90:cb3d968589d8	762	*/
Kojto	90:cb3d968589d8	763
Kojto	90:cb3d968589d8	764	/*!
Kojto	90:cb3d968589d8	765	* @name Register LLWU_ME, field WUME0[0] (RW)
Kojto	90:cb3d968589d8	766	*
Kojto	90:cb3d968589d8	767	* Enables an internal module as a wakeup source input.
Kojto	90:cb3d968589d8	768	*
Kojto	90:cb3d968589d8	769	* Values:
Kojto	90:cb3d968589d8	770	* - 0 - Internal module flag not used as wakeup source
Kojto	90:cb3d968589d8	771	* - 1 - Internal module flag used as wakeup source
Kojto	90:cb3d968589d8	772	*/
Kojto	90:cb3d968589d8	773	/@{/
Kojto	90:cb3d968589d8	774	#define BP_LLWU_ME_WUME0 (0U) /!< Bit position for LLWU_ME_WUME0. /
Kojto	90:cb3d968589d8	775	#define BM_LLWU_ME_WUME0 (0x01U) /!< Bit mask for LLWU_ME_WUME0. /
Kojto	90:cb3d968589d8	776	#define BS_LLWU_ME_WUME0 (1U) /!< Bit field size in bits for LLWU_ME_WUME0. /
Kojto	90:cb3d968589d8	777
Kojto	90:cb3d968589d8	778	/! @brief Read current value of the LLWU_ME_WUME0 field. /
Kojto	90:cb3d968589d8	779	#define BR_LLWU_ME_WUME0(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME0))
Kojto	90:cb3d968589d8	780
Kojto	90:cb3d968589d8	781	/! @brief Format value for bitfield LLWU_ME_WUME0. /
Kojto	90:cb3d968589d8	782	#define BF_LLWU_ME_WUME0(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME0) & BM_LLWU_ME_WUME0)
Kojto	90:cb3d968589d8	783
Kojto	90:cb3d968589d8	784	/! @brief Set the WUME0 field to a new value. /
Kojto	90:cb3d968589d8	785	#define BW_LLWU_ME_WUME0(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME0) = (v))
Kojto	90:cb3d968589d8	786	/@}/
Kojto	90:cb3d968589d8	787
Kojto	90:cb3d968589d8	788	/*!
Kojto	90:cb3d968589d8	789	* @name Register LLWU_ME, field WUME1[1] (RW)
Kojto	90:cb3d968589d8	790	*
Kojto	90:cb3d968589d8	791	* Enables an internal module as a wakeup source input.
Kojto	90:cb3d968589d8	792	*
Kojto	90:cb3d968589d8	793	* Values:
Kojto	90:cb3d968589d8	794	* - 0 - Internal module flag not used as wakeup source
Kojto	90:cb3d968589d8	795	* - 1 - Internal module flag used as wakeup source
Kojto	90:cb3d968589d8	796	*/
Kojto	90:cb3d968589d8	797	/@{/
Kojto	90:cb3d968589d8	798	#define BP_LLWU_ME_WUME1 (1U) /!< Bit position for LLWU_ME_WUME1. /
Kojto	90:cb3d968589d8	799	#define BM_LLWU_ME_WUME1 (0x02U) /!< Bit mask for LLWU_ME_WUME1. /
Kojto	90:cb3d968589d8	800	#define BS_LLWU_ME_WUME1 (1U) /!< Bit field size in bits for LLWU_ME_WUME1. /
Kojto	90:cb3d968589d8	801
Kojto	90:cb3d968589d8	802	/! @brief Read current value of the LLWU_ME_WUME1 field. /
Kojto	90:cb3d968589d8	803	#define BR_LLWU_ME_WUME1(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME1))
Kojto	90:cb3d968589d8	804
Kojto	90:cb3d968589d8	805	/! @brief Format value for bitfield LLWU_ME_WUME1. /
Kojto	90:cb3d968589d8	806	#define BF_LLWU_ME_WUME1(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME1) & BM_LLWU_ME_WUME1)
Kojto	90:cb3d968589d8	807
Kojto	90:cb3d968589d8	808	/! @brief Set the WUME1 field to a new value. /
Kojto	90:cb3d968589d8	809	#define BW_LLWU_ME_WUME1(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME1) = (v))
Kojto	90:cb3d968589d8	810	/@}/
Kojto	90:cb3d968589d8	811
Kojto	90:cb3d968589d8	812	/*!
Kojto	90:cb3d968589d8	813	* @name Register LLWU_ME, field WUME2[2] (RW)
Kojto	90:cb3d968589d8	814	*
Kojto	90:cb3d968589d8	815	* Enables an internal module as a wakeup source input.
Kojto	90:cb3d968589d8	816	*
Kojto	90:cb3d968589d8	817	* Values:
Kojto	90:cb3d968589d8	818	* - 0 - Internal module flag not used as wakeup source
Kojto	90:cb3d968589d8	819	* - 1 - Internal module flag used as wakeup source
Kojto	90:cb3d968589d8	820	*/
Kojto	90:cb3d968589d8	821	/@{/
Kojto	90:cb3d968589d8	822	#define BP_LLWU_ME_WUME2 (2U) /!< Bit position for LLWU_ME_WUME2. /
Kojto	90:cb3d968589d8	823	#define BM_LLWU_ME_WUME2 (0x04U) /!< Bit mask for LLWU_ME_WUME2. /
Kojto	90:cb3d968589d8	824	#define BS_LLWU_ME_WUME2 (1U) /!< Bit field size in bits for LLWU_ME_WUME2. /
Kojto	90:cb3d968589d8	825
Kojto	90:cb3d968589d8	826	/! @brief Read current value of the LLWU_ME_WUME2 field. /
Kojto	90:cb3d968589d8	827	#define BR_LLWU_ME_WUME2(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME2))
Kojto	90:cb3d968589d8	828
Kojto	90:cb3d968589d8	829	/! @brief Format value for bitfield LLWU_ME_WUME2. /
Kojto	90:cb3d968589d8	830	#define BF_LLWU_ME_WUME2(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME2) & BM_LLWU_ME_WUME2)
Kojto	90:cb3d968589d8	831
Kojto	90:cb3d968589d8	832	/! @brief Set the WUME2 field to a new value. /
Kojto	90:cb3d968589d8	833	#define BW_LLWU_ME_WUME2(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME2) = (v))
Kojto	90:cb3d968589d8	834	/@}/
Kojto	90:cb3d968589d8	835
Kojto	90:cb3d968589d8	836	/*!
Kojto	90:cb3d968589d8	837	* @name Register LLWU_ME, field WUME3[3] (RW)
Kojto	90:cb3d968589d8	838	*
Kojto	90:cb3d968589d8	839	* Enables an internal module as a wakeup source input.
Kojto	90:cb3d968589d8	840	*
Kojto	90:cb3d968589d8	841	* Values:
Kojto	90:cb3d968589d8	842	* - 0 - Internal module flag not used as wakeup source
Kojto	90:cb3d968589d8	843	* - 1 - Internal module flag used as wakeup source
Kojto	90:cb3d968589d8	844	*/
Kojto	90:cb3d968589d8	845	/@{/
Kojto	90:cb3d968589d8	846	#define BP_LLWU_ME_WUME3 (3U) /!< Bit position for LLWU_ME_WUME3. /
Kojto	90:cb3d968589d8	847	#define BM_LLWU_ME_WUME3 (0x08U) /!< Bit mask for LLWU_ME_WUME3. /
Kojto	90:cb3d968589d8	848	#define BS_LLWU_ME_WUME3 (1U) /!< Bit field size in bits for LLWU_ME_WUME3. /
Kojto	90:cb3d968589d8	849
Kojto	90:cb3d968589d8	850	/! @brief Read current value of the LLWU_ME_WUME3 field. /
Kojto	90:cb3d968589d8	851	#define BR_LLWU_ME_WUME3(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME3))
Kojto	90:cb3d968589d8	852
Kojto	90:cb3d968589d8	853	/! @brief Format value for bitfield LLWU_ME_WUME3. /
Kojto	90:cb3d968589d8	854	#define BF_LLWU_ME_WUME3(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME3) & BM_LLWU_ME_WUME3)
Kojto	90:cb3d968589d8	855
Kojto	90:cb3d968589d8	856	/! @brief Set the WUME3 field to a new value. /
Kojto	90:cb3d968589d8	857	#define BW_LLWU_ME_WUME3(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME3) = (v))
Kojto	90:cb3d968589d8	858	/@}/
Kojto	90:cb3d968589d8	859
Kojto	90:cb3d968589d8	860	/*!
Kojto	90:cb3d968589d8	861	* @name Register LLWU_ME, field WUME4[4] (RW)
Kojto	90:cb3d968589d8	862	*
Kojto	90:cb3d968589d8	863	* Enables an internal module as a wakeup source input.
Kojto	90:cb3d968589d8	864	*
Kojto	90:cb3d968589d8	865	* Values:
Kojto	90:cb3d968589d8	866	* - 0 - Internal module flag not used as wakeup source
Kojto	90:cb3d968589d8	867	* - 1 - Internal module flag used as wakeup source
Kojto	90:cb3d968589d8	868	*/
Kojto	90:cb3d968589d8	869	/@{/
Kojto	90:cb3d968589d8	870	#define BP_LLWU_ME_WUME4 (4U) /!< Bit position for LLWU_ME_WUME4. /
Kojto	90:cb3d968589d8	871	#define BM_LLWU_ME_WUME4 (0x10U) /!< Bit mask for LLWU_ME_WUME4. /
Kojto	90:cb3d968589d8	872	#define BS_LLWU_ME_WUME4 (1U) /!< Bit field size in bits for LLWU_ME_WUME4. /
Kojto	90:cb3d968589d8	873
Kojto	90:cb3d968589d8	874	/! @brief Read current value of the LLWU_ME_WUME4 field. /
Kojto	90:cb3d968589d8	875	#define BR_LLWU_ME_WUME4(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME4))
Kojto	90:cb3d968589d8	876
Kojto	90:cb3d968589d8	877	/! @brief Format value for bitfield LLWU_ME_WUME4. /
Kojto	90:cb3d968589d8	878	#define BF_LLWU_ME_WUME4(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME4) & BM_LLWU_ME_WUME4)
Kojto	90:cb3d968589d8	879
Kojto	90:cb3d968589d8	880	/! @brief Set the WUME4 field to a new value. /
Kojto	90:cb3d968589d8	881	#define BW_LLWU_ME_WUME4(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME4) = (v))
Kojto	90:cb3d968589d8	882	/@}/
Kojto	90:cb3d968589d8	883
Kojto	90:cb3d968589d8	884	/*!
Kojto	90:cb3d968589d8	885	* @name Register LLWU_ME, field WUME5[5] (RW)
Kojto	90:cb3d968589d8	886	*
Kojto	90:cb3d968589d8	887	* Enables an internal module as a wakeup source input.
Kojto	90:cb3d968589d8	888	*
Kojto	90:cb3d968589d8	889	* Values:
Kojto	90:cb3d968589d8	890	* - 0 - Internal module flag not used as wakeup source
Kojto	90:cb3d968589d8	891	* - 1 - Internal module flag used as wakeup source
Kojto	90:cb3d968589d8	892	*/
Kojto	90:cb3d968589d8	893	/@{/
Kojto	90:cb3d968589d8	894	#define BP_LLWU_ME_WUME5 (5U) /!< Bit position for LLWU_ME_WUME5. /
Kojto	90:cb3d968589d8	895	#define BM_LLWU_ME_WUME5 (0x20U) /!< Bit mask for LLWU_ME_WUME5. /
Kojto	90:cb3d968589d8	896	#define BS_LLWU_ME_WUME5 (1U) /!< Bit field size in bits for LLWU_ME_WUME5. /
Kojto	90:cb3d968589d8	897
Kojto	90:cb3d968589d8	898	/! @brief Read current value of the LLWU_ME_WUME5 field. /
Kojto	90:cb3d968589d8	899	#define BR_LLWU_ME_WUME5(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME5))
Kojto	90:cb3d968589d8	900
Kojto	90:cb3d968589d8	901	/! @brief Format value for bitfield LLWU_ME_WUME5. /
Kojto	90:cb3d968589d8	902	#define BF_LLWU_ME_WUME5(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME5) & BM_LLWU_ME_WUME5)
Kojto	90:cb3d968589d8	903
Kojto	90:cb3d968589d8	904	/! @brief Set the WUME5 field to a new value. /
Kojto	90:cb3d968589d8	905	#define BW_LLWU_ME_WUME5(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME5) = (v))
Kojto	90:cb3d968589d8	906	/@}/
Kojto	90:cb3d968589d8	907
Kojto	90:cb3d968589d8	908	/*!
Kojto	90:cb3d968589d8	909	* @name Register LLWU_ME, field WUME6[6] (RW)
Kojto	90:cb3d968589d8	910	*
Kojto	90:cb3d968589d8	911	* Enables an internal module as a wakeup source input.
Kojto	90:cb3d968589d8	912	*
Kojto	90:cb3d968589d8	913	* Values:
Kojto	90:cb3d968589d8	914	* - 0 - Internal module flag not used as wakeup source
Kojto	90:cb3d968589d8	915	* - 1 - Internal module flag used as wakeup source
Kojto	90:cb3d968589d8	916	*/
Kojto	90:cb3d968589d8	917	/@{/
Kojto	90:cb3d968589d8	918	#define BP_LLWU_ME_WUME6 (6U) /!< Bit position for LLWU_ME_WUME6. /
Kojto	90:cb3d968589d8	919	#define BM_LLWU_ME_WUME6 (0x40U) /!< Bit mask for LLWU_ME_WUME6. /
Kojto	90:cb3d968589d8	920	#define BS_LLWU_ME_WUME6 (1U) /!< Bit field size in bits for LLWU_ME_WUME6. /
Kojto	90:cb3d968589d8	921
Kojto	90:cb3d968589d8	922	/! @brief Read current value of the LLWU_ME_WUME6 field. /
Kojto	90:cb3d968589d8	923	#define BR_LLWU_ME_WUME6(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME6))
Kojto	90:cb3d968589d8	924
Kojto	90:cb3d968589d8	925	/! @brief Format value for bitfield LLWU_ME_WUME6. /
Kojto	90:cb3d968589d8	926	#define BF_LLWU_ME_WUME6(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME6) & BM_LLWU_ME_WUME6)
Kojto	90:cb3d968589d8	927
Kojto	90:cb3d968589d8	928	/! @brief Set the WUME6 field to a new value. /
Kojto	90:cb3d968589d8	929	#define BW_LLWU_ME_WUME6(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME6) = (v))
Kojto	90:cb3d968589d8	930	/@}/
Kojto	90:cb3d968589d8	931
Kojto	90:cb3d968589d8	932	/*!
Kojto	90:cb3d968589d8	933	* @name Register LLWU_ME, field WUME7[7] (RW)
Kojto	90:cb3d968589d8	934	*
Kojto	90:cb3d968589d8	935	* Enables an internal module as a wakeup source input.
Kojto	90:cb3d968589d8	936	*
Kojto	90:cb3d968589d8	937	* Values:
Kojto	90:cb3d968589d8	938	* - 0 - Internal module flag not used as wakeup source
Kojto	90:cb3d968589d8	939	* - 1 - Internal module flag used as wakeup source
Kojto	90:cb3d968589d8	940	*/
Kojto	90:cb3d968589d8	941	/@{/
Kojto	90:cb3d968589d8	942	#define BP_LLWU_ME_WUME7 (7U) /!< Bit position for LLWU_ME_WUME7. /
Kojto	90:cb3d968589d8	943	#define BM_LLWU_ME_WUME7 (0x80U) /!< Bit mask for LLWU_ME_WUME7. /
Kojto	90:cb3d968589d8	944	#define BS_LLWU_ME_WUME7 (1U) /!< Bit field size in bits for LLWU_ME_WUME7. /
Kojto	90:cb3d968589d8	945
Kojto	90:cb3d968589d8	946	/! @brief Read current value of the LLWU_ME_WUME7 field. /
Kojto	90:cb3d968589d8	947	#define BR_LLWU_ME_WUME7(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME7))
Kojto	90:cb3d968589d8	948
Kojto	90:cb3d968589d8	949	/! @brief Format value for bitfield LLWU_ME_WUME7. /
Kojto	90:cb3d968589d8	950	#define BF_LLWU_ME_WUME7(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME7) & BM_LLWU_ME_WUME7)
Kojto	90:cb3d968589d8	951
Kojto	90:cb3d968589d8	952	/! @brief Set the WUME7 field to a new value. /
Kojto	90:cb3d968589d8	953	#define BW_LLWU_ME_WUME7(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME7) = (v))
Kojto	90:cb3d968589d8	954	/@}/
Kojto	90:cb3d968589d8	955
Kojto	90:cb3d968589d8	956	/*******************************************************************************
Kojto	90:cb3d968589d8	957	* HW_LLWU_F1 - LLWU Flag 1 register
Kojto	90:cb3d968589d8	958	******************************************************************************/
Kojto	90:cb3d968589d8	959
Kojto	90:cb3d968589d8	960	/*!
Kojto	90:cb3d968589d8	961	* @brief HW_LLWU_F1 - LLWU Flag 1 register (W1C)
Kojto	90:cb3d968589d8	962	*
Kojto	90:cb3d968589d8	963	* Reset value: 0x00U
Kojto	90:cb3d968589d8	964	*
Kojto	90:cb3d968589d8	965	* LLWU_F1 contains the wakeup flags indicating which wakeup source caused the
Kojto	90:cb3d968589d8	966	* MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
Kojto	90:cb3d968589d8	967	* interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
Kojto	90:cb3d968589d8	968	* external wakeup flags are read-only and clearing a flag is accomplished by a write
Kojto	90:cb3d968589d8	969	* of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
Kojto	90:cb3d968589d8	970	* remain set if the associated WUPEx bit is cleared. This register is reset on Chip
Kojto	90:cb3d968589d8	971	* Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
Kojto	90:cb3d968589d8	972	* unaffected by reset types that do not trigger Chip Reset not VLLS. See the
Kojto	90:cb3d968589d8	973	* IntroductionInformation found here describes the registers of the Reset Control
Kojto	90:cb3d968589d8	974	* Module (RCM). The RCM implements many of the reset functions for the chip. See the
Kojto	90:cb3d968589d8	975	* chip's reset chapter for more information. details for more information.
Kojto	90:cb3d968589d8	976	*/
Kojto	90:cb3d968589d8	977	typedef union _hw_llwu_f1
Kojto	90:cb3d968589d8	978	{
Kojto	90:cb3d968589d8	979	uint8_t U;
Kojto	90:cb3d968589d8	980	struct _hw_llwu_f1_bitfields
Kojto	90:cb3d968589d8	981	{
Kojto	90:cb3d968589d8	982	uint8_t WUF0 : 1; /!< [0] Wakeup Flag For LLWU_P0 /
Kojto	90:cb3d968589d8	983	uint8_t WUF1 : 1; /!< [1] Wakeup Flag For LLWU_P1 /
Kojto	90:cb3d968589d8	984	uint8_t WUF2 : 1; /!< [2] Wakeup Flag For LLWU_P2 /
Kojto	90:cb3d968589d8	985	uint8_t WUF3 : 1; /!< [3] Wakeup Flag For LLWU_P3 /
Kojto	90:cb3d968589d8	986	uint8_t WUF4 : 1; /!< [4] Wakeup Flag For LLWU_P4 /
Kojto	90:cb3d968589d8	987	uint8_t WUF5 : 1; /!< [5] Wakeup Flag For LLWU_P5 /
Kojto	90:cb3d968589d8	988	uint8_t WUF6 : 1; /!< [6] Wakeup Flag For LLWU_P6 /
Kojto	90:cb3d968589d8	989	uint8_t WUF7 : 1; /!< [7] Wakeup Flag For LLWU_P7 /
Kojto	90:cb3d968589d8	990	} B;
Kojto	90:cb3d968589d8	991	} hw_llwu_f1_t;
Kojto	90:cb3d968589d8	992
Kojto	90:cb3d968589d8	993	/*!
Kojto	90:cb3d968589d8	994	* @name Constants and macros for entire LLWU_F1 register
Kojto	90:cb3d968589d8	995	*/
Kojto	90:cb3d968589d8	996	/@{/
Kojto	90:cb3d968589d8	997	#define HW_LLWU_F1_ADDR(x) ((x) + 0x5U)
Kojto	90:cb3d968589d8	998
Kojto	90:cb3d968589d8	999	#define HW_LLWU_F1(x) ((__IO hw_llwu_f1_t ) HW_LLWU_F1_ADDR(x))
Kojto	90:cb3d968589d8	1000	#define HW_LLWU_F1_RD(x) (HW_LLWU_F1(x).U)
Kojto	90:cb3d968589d8	1001	#define HW_LLWU_F1_WR(x, v) (HW_LLWU_F1(x).U = (v))
Kojto	90:cb3d968589d8	1002	#define HW_LLWU_F1_SET(x, v) (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1003	#define HW_LLWU_F1_CLR(x, v) (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1004	#define HW_LLWU_F1_TOG(x, v) (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1005	/@}/
Kojto	90:cb3d968589d8	1006
Kojto	90:cb3d968589d8	1007	/*
Kojto	90:cb3d968589d8	1008	* Constants & macros for individual LLWU_F1 bitfields
Kojto	90:cb3d968589d8	1009	*/
Kojto	90:cb3d968589d8	1010
Kojto	90:cb3d968589d8	1011	/*!
Kojto	90:cb3d968589d8	1012	* @name Register LLWU_F1, field WUF0[0] (W1C)
Kojto	90:cb3d968589d8	1013	*
Kojto	90:cb3d968589d8	1014	* Indicates that an enabled external wake-up pin was a source of exiting a
Kojto	90:cb3d968589d8	1015	* low-leakage power mode. To clear the flag, write a 1 to WUF0.
Kojto	90:cb3d968589d8	1016	*
Kojto	90:cb3d968589d8	1017	* Values:
Kojto	90:cb3d968589d8	1018	* - 0 - LLWU_P0 input was not a wakeup source
Kojto	90:cb3d968589d8	1019	* - 1 - LLWU_P0 input was a wakeup source
Kojto	90:cb3d968589d8	1020	*/
Kojto	90:cb3d968589d8	1021	/@{/
Kojto	90:cb3d968589d8	1022	#define BP_LLWU_F1_WUF0 (0U) /!< Bit position for LLWU_F1_WUF0. /
Kojto	90:cb3d968589d8	1023	#define BM_LLWU_F1_WUF0 (0x01U) /!< Bit mask for LLWU_F1_WUF0. /
Kojto	90:cb3d968589d8	1024	#define BS_LLWU_F1_WUF0 (1U) /!< Bit field size in bits for LLWU_F1_WUF0. /
Kojto	90:cb3d968589d8	1025
Kojto	90:cb3d968589d8	1026	/! @brief Read current value of the LLWU_F1_WUF0 field. /
Kojto	90:cb3d968589d8	1027	#define BR_LLWU_F1_WUF0(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF0))
Kojto	90:cb3d968589d8	1028
Kojto	90:cb3d968589d8	1029	/! @brief Format value for bitfield LLWU_F1_WUF0. /
Kojto	90:cb3d968589d8	1030	#define BF_LLWU_F1_WUF0(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF0) & BM_LLWU_F1_WUF0)
Kojto	90:cb3d968589d8	1031
Kojto	90:cb3d968589d8	1032	/! @brief Set the WUF0 field to a new value. /
Kojto	90:cb3d968589d8	1033	#define BW_LLWU_F1_WUF0(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF0) = (v))
Kojto	90:cb3d968589d8	1034	/@}/
Kojto	90:cb3d968589d8	1035
Kojto	90:cb3d968589d8	1036	/*!
Kojto	90:cb3d968589d8	1037	* @name Register LLWU_F1, field WUF1[1] (W1C)
Kojto	90:cb3d968589d8	1038	*
Kojto	90:cb3d968589d8	1039	* Indicates that an enabled external wakeup pin was a source of exiting a
Kojto	90:cb3d968589d8	1040	* low-leakage power mode. To clear the flag, write a 1 to WUF1.
Kojto	90:cb3d968589d8	1041	*
Kojto	90:cb3d968589d8	1042	* Values:
Kojto	90:cb3d968589d8	1043	* - 0 - LLWU_P1 input was not a wakeup source
Kojto	90:cb3d968589d8	1044	* - 1 - LLWU_P1 input was a wakeup source
Kojto	90:cb3d968589d8	1045	*/
Kojto	90:cb3d968589d8	1046	/@{/
Kojto	90:cb3d968589d8	1047	#define BP_LLWU_F1_WUF1 (1U) /!< Bit position for LLWU_F1_WUF1. /
Kojto	90:cb3d968589d8	1048	#define BM_LLWU_F1_WUF1 (0x02U) /!< Bit mask for LLWU_F1_WUF1. /
Kojto	90:cb3d968589d8	1049	#define BS_LLWU_F1_WUF1 (1U) /!< Bit field size in bits for LLWU_F1_WUF1. /
Kojto	90:cb3d968589d8	1050
Kojto	90:cb3d968589d8	1051	/! @brief Read current value of the LLWU_F1_WUF1 field. /
Kojto	90:cb3d968589d8	1052	#define BR_LLWU_F1_WUF1(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF1))
Kojto	90:cb3d968589d8	1053
Kojto	90:cb3d968589d8	1054	/! @brief Format value for bitfield LLWU_F1_WUF1. /
Kojto	90:cb3d968589d8	1055	#define BF_LLWU_F1_WUF1(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF1) & BM_LLWU_F1_WUF1)
Kojto	90:cb3d968589d8	1056
Kojto	90:cb3d968589d8	1057	/! @brief Set the WUF1 field to a new value. /
Kojto	90:cb3d968589d8	1058	#define BW_LLWU_F1_WUF1(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF1) = (v))
Kojto	90:cb3d968589d8	1059	/@}/
Kojto	90:cb3d968589d8	1060
Kojto	90:cb3d968589d8	1061	/*!
Kojto	90:cb3d968589d8	1062	* @name Register LLWU_F1, field WUF2[2] (W1C)
Kojto	90:cb3d968589d8	1063	*
Kojto	90:cb3d968589d8	1064	* Indicates that an enabled external wakeup pin was a source of exiting a
Kojto	90:cb3d968589d8	1065	* low-leakage power mode. To clear the flag, write a 1 to WUF2.
Kojto	90:cb3d968589d8	1066	*
Kojto	90:cb3d968589d8	1067	* Values:
Kojto	90:cb3d968589d8	1068	* - 0 - LLWU_P2 input was not a wakeup source
Kojto	90:cb3d968589d8	1069	* - 1 - LLWU_P2 input was a wakeup source
Kojto	90:cb3d968589d8	1070	*/
Kojto	90:cb3d968589d8	1071	/@{/
Kojto	90:cb3d968589d8	1072	#define BP_LLWU_F1_WUF2 (2U) /!< Bit position for LLWU_F1_WUF2. /
Kojto	90:cb3d968589d8	1073	#define BM_LLWU_F1_WUF2 (0x04U) /!< Bit mask for LLWU_F1_WUF2. /
Kojto	90:cb3d968589d8	1074	#define BS_LLWU_F1_WUF2 (1U) /!< Bit field size in bits for LLWU_F1_WUF2. /
Kojto	90:cb3d968589d8	1075
Kojto	90:cb3d968589d8	1076	/! @brief Read current value of the LLWU_F1_WUF2 field. /
Kojto	90:cb3d968589d8	1077	#define BR_LLWU_F1_WUF2(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF2))
Kojto	90:cb3d968589d8	1078
Kojto	90:cb3d968589d8	1079	/! @brief Format value for bitfield LLWU_F1_WUF2. /
Kojto	90:cb3d968589d8	1080	#define BF_LLWU_F1_WUF2(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF2) & BM_LLWU_F1_WUF2)
Kojto	90:cb3d968589d8	1081
Kojto	90:cb3d968589d8	1082	/! @brief Set the WUF2 field to a new value. /
Kojto	90:cb3d968589d8	1083	#define BW_LLWU_F1_WUF2(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF2) = (v))
Kojto	90:cb3d968589d8	1084	/@}/
Kojto	90:cb3d968589d8	1085
Kojto	90:cb3d968589d8	1086	/*!
Kojto	90:cb3d968589d8	1087	* @name Register LLWU_F1, field WUF3[3] (W1C)
Kojto	90:cb3d968589d8	1088	*
Kojto	90:cb3d968589d8	1089	* Indicates that an enabled external wakeup pin was a source of exiting a
Kojto	90:cb3d968589d8	1090	* low-leakage power mode. To clear the flag, write a 1 to WUF3.
Kojto	90:cb3d968589d8	1091	*
Kojto	90:cb3d968589d8	1092	* Values:
Kojto	90:cb3d968589d8	1093	* - 0 - LLWU_P3 input was not a wake-up source
Kojto	90:cb3d968589d8	1094	* - 1 - LLWU_P3 input was a wake-up source
Kojto	90:cb3d968589d8	1095	*/
Kojto	90:cb3d968589d8	1096	/@{/
Kojto	90:cb3d968589d8	1097	#define BP_LLWU_F1_WUF3 (3U) /!< Bit position for LLWU_F1_WUF3. /
Kojto	90:cb3d968589d8	1098	#define BM_LLWU_F1_WUF3 (0x08U) /!< Bit mask for LLWU_F1_WUF3. /
Kojto	90:cb3d968589d8	1099	#define BS_LLWU_F1_WUF3 (1U) /!< Bit field size in bits for LLWU_F1_WUF3. /
Kojto	90:cb3d968589d8	1100
Kojto	90:cb3d968589d8	1101	/! @brief Read current value of the LLWU_F1_WUF3 field. /
Kojto	90:cb3d968589d8	1102	#define BR_LLWU_F1_WUF3(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF3))
Kojto	90:cb3d968589d8	1103
Kojto	90:cb3d968589d8	1104	/! @brief Format value for bitfield LLWU_F1_WUF3. /
Kojto	90:cb3d968589d8	1105	#define BF_LLWU_F1_WUF3(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF3) & BM_LLWU_F1_WUF3)
Kojto	90:cb3d968589d8	1106
Kojto	90:cb3d968589d8	1107	/! @brief Set the WUF3 field to a new value. /
Kojto	90:cb3d968589d8	1108	#define BW_LLWU_F1_WUF3(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF3) = (v))
Kojto	90:cb3d968589d8	1109	/@}/
Kojto	90:cb3d968589d8	1110
Kojto	90:cb3d968589d8	1111	/*!
Kojto	90:cb3d968589d8	1112	* @name Register LLWU_F1, field WUF4[4] (W1C)
Kojto	90:cb3d968589d8	1113	*
Kojto	90:cb3d968589d8	1114	* Indicates that an enabled external wake-up pin was a source of exiting a
Kojto	90:cb3d968589d8	1115	* low-leakage power mode. To clear the flag, write a 1 to WUF4.
Kojto	90:cb3d968589d8	1116	*
Kojto	90:cb3d968589d8	1117	* Values:
Kojto	90:cb3d968589d8	1118	* - 0 - LLWU_P4 input was not a wakeup source
Kojto	90:cb3d968589d8	1119	* - 1 - LLWU_P4 input was a wakeup source
Kojto	90:cb3d968589d8	1120	*/
Kojto	90:cb3d968589d8	1121	/@{/
Kojto	90:cb3d968589d8	1122	#define BP_LLWU_F1_WUF4 (4U) /!< Bit position for LLWU_F1_WUF4. /
Kojto	90:cb3d968589d8	1123	#define BM_LLWU_F1_WUF4 (0x10U) /!< Bit mask for LLWU_F1_WUF4. /
Kojto	90:cb3d968589d8	1124	#define BS_LLWU_F1_WUF4 (1U) /!< Bit field size in bits for LLWU_F1_WUF4. /
Kojto	90:cb3d968589d8	1125
Kojto	90:cb3d968589d8	1126	/! @brief Read current value of the LLWU_F1_WUF4 field. /
Kojto	90:cb3d968589d8	1127	#define BR_LLWU_F1_WUF4(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF4))
Kojto	90:cb3d968589d8	1128
Kojto	90:cb3d968589d8	1129	/! @brief Format value for bitfield LLWU_F1_WUF4. /
Kojto	90:cb3d968589d8	1130	#define BF_LLWU_F1_WUF4(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF4) & BM_LLWU_F1_WUF4)
Kojto	90:cb3d968589d8	1131
Kojto	90:cb3d968589d8	1132	/! @brief Set the WUF4 field to a new value. /
Kojto	90:cb3d968589d8	1133	#define BW_LLWU_F1_WUF4(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF4) = (v))
Kojto	90:cb3d968589d8	1134	/@}/
Kojto	90:cb3d968589d8	1135
Kojto	90:cb3d968589d8	1136	/*!
Kojto	90:cb3d968589d8	1137	* @name Register LLWU_F1, field WUF5[5] (W1C)
Kojto	90:cb3d968589d8	1138	*
Kojto	90:cb3d968589d8	1139	* Indicates that an enabled external wakeup pin was a source of exiting a
Kojto	90:cb3d968589d8	1140	* low-leakage power mode. To clear the flag, write a 1 to WUF5.
Kojto	90:cb3d968589d8	1141	*
Kojto	90:cb3d968589d8	1142	* Values:
Kojto	90:cb3d968589d8	1143	* - 0 - LLWU_P5 input was not a wakeup source
Kojto	90:cb3d968589d8	1144	* - 1 - LLWU_P5 input was a wakeup source
Kojto	90:cb3d968589d8	1145	*/
Kojto	90:cb3d968589d8	1146	/@{/
Kojto	90:cb3d968589d8	1147	#define BP_LLWU_F1_WUF5 (5U) /!< Bit position for LLWU_F1_WUF5. /
Kojto	90:cb3d968589d8	1148	#define BM_LLWU_F1_WUF5 (0x20U) /!< Bit mask for LLWU_F1_WUF5. /
Kojto	90:cb3d968589d8	1149	#define BS_LLWU_F1_WUF5 (1U) /!< Bit field size in bits for LLWU_F1_WUF5. /
Kojto	90:cb3d968589d8	1150
Kojto	90:cb3d968589d8	1151	/! @brief Read current value of the LLWU_F1_WUF5 field. /
Kojto	90:cb3d968589d8	1152	#define BR_LLWU_F1_WUF5(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF5))
Kojto	90:cb3d968589d8	1153
Kojto	90:cb3d968589d8	1154	/! @brief Format value for bitfield LLWU_F1_WUF5. /
Kojto	90:cb3d968589d8	1155	#define BF_LLWU_F1_WUF5(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF5) & BM_LLWU_F1_WUF5)
Kojto	90:cb3d968589d8	1156
Kojto	90:cb3d968589d8	1157	/! @brief Set the WUF5 field to a new value. /
Kojto	90:cb3d968589d8	1158	#define BW_LLWU_F1_WUF5(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF5) = (v))
Kojto	90:cb3d968589d8	1159	/@}/
Kojto	90:cb3d968589d8	1160
Kojto	90:cb3d968589d8	1161	/*!
Kojto	90:cb3d968589d8	1162	* @name Register LLWU_F1, field WUF6[6] (W1C)
Kojto	90:cb3d968589d8	1163	*
Kojto	90:cb3d968589d8	1164	* Indicates that an enabled external wakeup pin was a source of exiting a
Kojto	90:cb3d968589d8	1165	* low-leakage power mode. To clear the flag, write a 1 to WUF6.
Kojto	90:cb3d968589d8	1166	*
Kojto	90:cb3d968589d8	1167	* Values:
Kojto	90:cb3d968589d8	1168	* - 0 - LLWU_P6 input was not a wakeup source
Kojto	90:cb3d968589d8	1169	* - 1 - LLWU_P6 input was a wakeup source
Kojto	90:cb3d968589d8	1170	*/
Kojto	90:cb3d968589d8	1171	/@{/
Kojto	90:cb3d968589d8	1172	#define BP_LLWU_F1_WUF6 (6U) /!< Bit position for LLWU_F1_WUF6. /
Kojto	90:cb3d968589d8	1173	#define BM_LLWU_F1_WUF6 (0x40U) /!< Bit mask for LLWU_F1_WUF6. /
Kojto	90:cb3d968589d8	1174	#define BS_LLWU_F1_WUF6 (1U) /!< Bit field size in bits for LLWU_F1_WUF6. /
Kojto	90:cb3d968589d8	1175
Kojto	90:cb3d968589d8	1176	/! @brief Read current value of the LLWU_F1_WUF6 field. /
Kojto	90:cb3d968589d8	1177	#define BR_LLWU_F1_WUF6(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF6))
Kojto	90:cb3d968589d8	1178
Kojto	90:cb3d968589d8	1179	/! @brief Format value for bitfield LLWU_F1_WUF6. /
Kojto	90:cb3d968589d8	1180	#define BF_LLWU_F1_WUF6(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF6) & BM_LLWU_F1_WUF6)
Kojto	90:cb3d968589d8	1181
Kojto	90:cb3d968589d8	1182	/! @brief Set the WUF6 field to a new value. /
Kojto	90:cb3d968589d8	1183	#define BW_LLWU_F1_WUF6(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF6) = (v))
Kojto	90:cb3d968589d8	1184	/@}/
Kojto	90:cb3d968589d8	1185
Kojto	90:cb3d968589d8	1186	/*!
Kojto	90:cb3d968589d8	1187	* @name Register LLWU_F1, field WUF7[7] (W1C)
Kojto	90:cb3d968589d8	1188	*
Kojto	90:cb3d968589d8	1189	* Indicates that an enabled external wakeup pin was a source of exiting a
Kojto	90:cb3d968589d8	1190	* low-leakage power mode. To clear the flag, write a 1 to WUF7.
Kojto	90:cb3d968589d8	1191	*
Kojto	90:cb3d968589d8	1192	* Values:
Kojto	90:cb3d968589d8	1193	* - 0 - LLWU_P7 input was not a wakeup source
Kojto	90:cb3d968589d8	1194	* - 1 - LLWU_P7 input was a wakeup source
Kojto	90:cb3d968589d8	1195	*/
Kojto	90:cb3d968589d8	1196	/@{/
Kojto	90:cb3d968589d8	1197	#define BP_LLWU_F1_WUF7 (7U) /!< Bit position for LLWU_F1_WUF7. /
Kojto	90:cb3d968589d8	1198	#define BM_LLWU_F1_WUF7 (0x80U) /!< Bit mask for LLWU_F1_WUF7. /
Kojto	90:cb3d968589d8	1199	#define BS_LLWU_F1_WUF7 (1U) /!< Bit field size in bits for LLWU_F1_WUF7. /
Kojto	90:cb3d968589d8	1200
Kojto	90:cb3d968589d8	1201	/! @brief Read current value of the LLWU_F1_WUF7 field. /
Kojto	90:cb3d968589d8	1202	#define BR_LLWU_F1_WUF7(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF7))
Kojto	90:cb3d968589d8	1203
Kojto	90:cb3d968589d8	1204	/! @brief Format value for bitfield LLWU_F1_WUF7. /
Kojto	90:cb3d968589d8	1205	#define BF_LLWU_F1_WUF7(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF7) & BM_LLWU_F1_WUF7)
Kojto	90:cb3d968589d8	1206
Kojto	90:cb3d968589d8	1207	/! @brief Set the WUF7 field to a new value. /
Kojto	90:cb3d968589d8	1208	#define BW_LLWU_F1_WUF7(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF7) = (v))
Kojto	90:cb3d968589d8	1209	/@}/
Kojto	90:cb3d968589d8	1210
Kojto	90:cb3d968589d8	1211	/*******************************************************************************
Kojto	90:cb3d968589d8	1212	* HW_LLWU_F2 - LLWU Flag 2 register
Kojto	90:cb3d968589d8	1213	******************************************************************************/
Kojto	90:cb3d968589d8	1214
Kojto	90:cb3d968589d8	1215	/*!
Kojto	90:cb3d968589d8	1216	* @brief HW_LLWU_F2 - LLWU Flag 2 register (W1C)
Kojto	90:cb3d968589d8	1217	*
Kojto	90:cb3d968589d8	1218	* Reset value: 0x00U
Kojto	90:cb3d968589d8	1219	*
Kojto	90:cb3d968589d8	1220	* LLWU_F2 contains the wakeup flags indicating which wakeup source caused the
Kojto	90:cb3d968589d8	1221	* MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
Kojto	90:cb3d968589d8	1222	* interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
Kojto	90:cb3d968589d8	1223	* external wakeup flags are read-only and clearing a flag is accomplished by a write
Kojto	90:cb3d968589d8	1224	* of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
Kojto	90:cb3d968589d8	1225	* remain set if the associated WUPEx bit is cleared. This register is reset on Chip
Kojto	90:cb3d968589d8	1226	* Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
Kojto	90:cb3d968589d8	1227	* unaffected by reset types that do not trigger Chip Reset not VLLS. See the
Kojto	90:cb3d968589d8	1228	* IntroductionInformation found here describes the registers of the Reset Control
Kojto	90:cb3d968589d8	1229	* Module (RCM). The RCM implements many of the reset functions for the chip. See the
Kojto	90:cb3d968589d8	1230	* chip's reset chapter for more information. details for more information.
Kojto	90:cb3d968589d8	1231	*/
Kojto	90:cb3d968589d8	1232	typedef union _hw_llwu_f2
Kojto	90:cb3d968589d8	1233	{
Kojto	90:cb3d968589d8	1234	uint8_t U;
Kojto	90:cb3d968589d8	1235	struct _hw_llwu_f2_bitfields
Kojto	90:cb3d968589d8	1236	{
Kojto	90:cb3d968589d8	1237	uint8_t WUF8 : 1; /!< [0] Wakeup Flag For LLWU_P8 /
Kojto	90:cb3d968589d8	1238	uint8_t WUF9 : 1; /!< [1] Wakeup Flag For LLWU_P9 /
Kojto	90:cb3d968589d8	1239	uint8_t WUF10 : 1; /!< [2] Wakeup Flag For LLWU_P10 /
Kojto	90:cb3d968589d8	1240	uint8_t WUF11 : 1; /!< [3] Wakeup Flag For LLWU_P11 /
Kojto	90:cb3d968589d8	1241	uint8_t WUF12 : 1; /!< [4] Wakeup Flag For LLWU_P12 /
Kojto	90:cb3d968589d8	1242	uint8_t WUF13 : 1; /!< [5] Wakeup Flag For LLWU_P13 /
Kojto	90:cb3d968589d8	1243	uint8_t WUF14 : 1; /!< [6] Wakeup Flag For LLWU_P14 /
Kojto	90:cb3d968589d8	1244	uint8_t WUF15 : 1; /!< [7] Wakeup Flag For LLWU_P15 /
Kojto	90:cb3d968589d8	1245	} B;
Kojto	90:cb3d968589d8	1246	} hw_llwu_f2_t;
Kojto	90:cb3d968589d8	1247
Kojto	90:cb3d968589d8	1248	/*!
Kojto	90:cb3d968589d8	1249	* @name Constants and macros for entire LLWU_F2 register
Kojto	90:cb3d968589d8	1250	*/
Kojto	90:cb3d968589d8	1251	/@{/
Kojto	90:cb3d968589d8	1252	#define HW_LLWU_F2_ADDR(x) ((x) + 0x6U)
Kojto	90:cb3d968589d8	1253
Kojto	90:cb3d968589d8	1254	#define HW_LLWU_F2(x) ((__IO hw_llwu_f2_t ) HW_LLWU_F2_ADDR(x))
Kojto	90:cb3d968589d8	1255	#define HW_LLWU_F2_RD(x) (HW_LLWU_F2(x).U)
Kojto	90:cb3d968589d8	1256	#define HW_LLWU_F2_WR(x, v) (HW_LLWU_F2(x).U = (v))
Kojto	90:cb3d968589d8	1257	#define HW_LLWU_F2_SET(x, v) (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1258	#define HW_LLWU_F2_CLR(x, v) (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1259	#define HW_LLWU_F2_TOG(x, v) (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1260	/@}/
Kojto	90:cb3d968589d8	1261
Kojto	90:cb3d968589d8	1262	/*
Kojto	90:cb3d968589d8	1263	* Constants & macros for individual LLWU_F2 bitfields
Kojto	90:cb3d968589d8	1264	*/
Kojto	90:cb3d968589d8	1265
Kojto	90:cb3d968589d8	1266	/*!
Kojto	90:cb3d968589d8	1267	* @name Register LLWU_F2, field WUF8[0] (W1C)
Kojto	90:cb3d968589d8	1268	*
Kojto	90:cb3d968589d8	1269	* Indicates that an enabled external wakeup pin was a source of exiting a
Kojto	90:cb3d968589d8	1270	* low-leakage power mode. To clear the flag, write a 1 to WUF8.
Kojto	90:cb3d968589d8	1271	*
Kojto	90:cb3d968589d8	1272	* Values:
Kojto	90:cb3d968589d8	1273	* - 0 - LLWU_P8 input was not a wakeup source
Kojto	90:cb3d968589d8	1274	* - 1 - LLWU_P8 input was a wakeup source
Kojto	90:cb3d968589d8	1275	*/
Kojto	90:cb3d968589d8	1276	/@{/
Kojto	90:cb3d968589d8	1277	#define BP_LLWU_F2_WUF8 (0U) /!< Bit position for LLWU_F2_WUF8. /
Kojto	90:cb3d968589d8	1278	#define BM_LLWU_F2_WUF8 (0x01U) /!< Bit mask for LLWU_F2_WUF8. /
Kojto	90:cb3d968589d8	1279	#define BS_LLWU_F2_WUF8 (1U) /!< Bit field size in bits for LLWU_F2_WUF8. /
Kojto	90:cb3d968589d8	1280
Kojto	90:cb3d968589d8	1281	/! @brief Read current value of the LLWU_F2_WUF8 field. /
Kojto	90:cb3d968589d8	1282	#define BR_LLWU_F2_WUF8(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF8))
Kojto	90:cb3d968589d8	1283
Kojto	90:cb3d968589d8	1284	/! @brief Format value for bitfield LLWU_F2_WUF8. /
Kojto	90:cb3d968589d8	1285	#define BF_LLWU_F2_WUF8(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF8) & BM_LLWU_F2_WUF8)
Kojto	90:cb3d968589d8	1286
Kojto	90:cb3d968589d8	1287	/! @brief Set the WUF8 field to a new value. /
Kojto	90:cb3d968589d8	1288	#define BW_LLWU_F2_WUF8(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF8) = (v))
Kojto	90:cb3d968589d8	1289	/@}/
Kojto	90:cb3d968589d8	1290
Kojto	90:cb3d968589d8	1291	/*!
Kojto	90:cb3d968589d8	1292	* @name Register LLWU_F2, field WUF9[1] (W1C)
Kojto	90:cb3d968589d8	1293	*
Kojto	90:cb3d968589d8	1294	* Indicates that an enabled external wakeup pin was a source of exiting a
Kojto	90:cb3d968589d8	1295	* low-leakage power mode. To clear the flag, write a 1 to WUF9.
Kojto	90:cb3d968589d8	1296	*
Kojto	90:cb3d968589d8	1297	* Values:
Kojto	90:cb3d968589d8	1298	* - 0 - LLWU_P9 input was not a wakeup source
Kojto	90:cb3d968589d8	1299	* - 1 - LLWU_P9 input was a wakeup source
Kojto	90:cb3d968589d8	1300	*/
Kojto	90:cb3d968589d8	1301	/@{/
Kojto	90:cb3d968589d8	1302	#define BP_LLWU_F2_WUF9 (1U) /!< Bit position for LLWU_F2_WUF9. /
Kojto	90:cb3d968589d8	1303	#define BM_LLWU_F2_WUF9 (0x02U) /!< Bit mask for LLWU_F2_WUF9. /
Kojto	90:cb3d968589d8	1304	#define BS_LLWU_F2_WUF9 (1U) /!< Bit field size in bits for LLWU_F2_WUF9. /
Kojto	90:cb3d968589d8	1305
Kojto	90:cb3d968589d8	1306	/! @brief Read current value of the LLWU_F2_WUF9 field. /
Kojto	90:cb3d968589d8	1307	#define BR_LLWU_F2_WUF9(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF9))
Kojto	90:cb3d968589d8	1308
Kojto	90:cb3d968589d8	1309	/! @brief Format value for bitfield LLWU_F2_WUF9. /
Kojto	90:cb3d968589d8	1310	#define BF_LLWU_F2_WUF9(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF9) & BM_LLWU_F2_WUF9)
Kojto	90:cb3d968589d8	1311
Kojto	90:cb3d968589d8	1312	/! @brief Set the WUF9 field to a new value. /
Kojto	90:cb3d968589d8	1313	#define BW_LLWU_F2_WUF9(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF9) = (v))
Kojto	90:cb3d968589d8	1314	/@}/
Kojto	90:cb3d968589d8	1315
Kojto	90:cb3d968589d8	1316	/*!
Kojto	90:cb3d968589d8	1317	* @name Register LLWU_F2, field WUF10[2] (W1C)
Kojto	90:cb3d968589d8	1318	*
Kojto	90:cb3d968589d8	1319	* Indicates that an enabled external wakeup pin was a source of exiting a
Kojto	90:cb3d968589d8	1320	* low-leakage power mode. To clear the flag, write a 1 to WUF10.
Kojto	90:cb3d968589d8	1321	*
Kojto	90:cb3d968589d8	1322	* Values:
Kojto	90:cb3d968589d8	1323	* - 0 - LLWU_P10 input was not a wakeup source
Kojto	90:cb3d968589d8	1324	* - 1 - LLWU_P10 input was a wakeup source
Kojto	90:cb3d968589d8	1325	*/
Kojto	90:cb3d968589d8	1326	/@{/
Kojto	90:cb3d968589d8	1327	#define BP_LLWU_F2_WUF10 (2U) /!< Bit position for LLWU_F2_WUF10. /
Kojto	90:cb3d968589d8	1328	#define BM_LLWU_F2_WUF10 (0x04U) /!< Bit mask for LLWU_F2_WUF10. /
Kojto	90:cb3d968589d8	1329	#define BS_LLWU_F2_WUF10 (1U) /!< Bit field size in bits for LLWU_F2_WUF10. /
Kojto	90:cb3d968589d8	1330
Kojto	90:cb3d968589d8	1331	/! @brief Read current value of the LLWU_F2_WUF10 field. /
Kojto	90:cb3d968589d8	1332	#define BR_LLWU_F2_WUF10(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF10))
Kojto	90:cb3d968589d8	1333
Kojto	90:cb3d968589d8	1334	/! @brief Format value for bitfield LLWU_F2_WUF10. /
Kojto	90:cb3d968589d8	1335	#define BF_LLWU_F2_WUF10(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF10) & BM_LLWU_F2_WUF10)
Kojto	90:cb3d968589d8	1336
Kojto	90:cb3d968589d8	1337	/! @brief Set the WUF10 field to a new value. /
Kojto	90:cb3d968589d8	1338	#define BW_LLWU_F2_WUF10(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF10) = (v))
Kojto	90:cb3d968589d8	1339	/@}/
Kojto	90:cb3d968589d8	1340
Kojto	90:cb3d968589d8	1341	/*!
Kojto	90:cb3d968589d8	1342	* @name Register LLWU_F2, field WUF11[3] (W1C)
Kojto	90:cb3d968589d8	1343	*
Kojto	90:cb3d968589d8	1344	* Indicates that an enabled external wakeup pin was a source of exiting a
Kojto	90:cb3d968589d8	1345	* low-leakage power mode. To clear the flag, write a 1 to WUF11.
Kojto	90:cb3d968589d8	1346	*
Kojto	90:cb3d968589d8	1347	* Values:
Kojto	90:cb3d968589d8	1348	* - 0 - LLWU_P11 input was not a wakeup source
Kojto	90:cb3d968589d8	1349	* - 1 - LLWU_P11 input was a wakeup source
Kojto	90:cb3d968589d8	1350	*/
Kojto	90:cb3d968589d8	1351	/@{/
Kojto	90:cb3d968589d8	1352	#define BP_LLWU_F2_WUF11 (3U) /!< Bit position for LLWU_F2_WUF11. /
Kojto	90:cb3d968589d8	1353	#define BM_LLWU_F2_WUF11 (0x08U) /!< Bit mask for LLWU_F2_WUF11. /
Kojto	90:cb3d968589d8	1354	#define BS_LLWU_F2_WUF11 (1U) /!< Bit field size in bits for LLWU_F2_WUF11. /
Kojto	90:cb3d968589d8	1355
Kojto	90:cb3d968589d8	1356	/! @brief Read current value of the LLWU_F2_WUF11 field. /
Kojto	90:cb3d968589d8	1357	#define BR_LLWU_F2_WUF11(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF11))
Kojto	90:cb3d968589d8	1358
Kojto	90:cb3d968589d8	1359	/! @brief Format value for bitfield LLWU_F2_WUF11. /
Kojto	90:cb3d968589d8	1360	#define BF_LLWU_F2_WUF11(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF11) & BM_LLWU_F2_WUF11)
Kojto	90:cb3d968589d8	1361
Kojto	90:cb3d968589d8	1362	/! @brief Set the WUF11 field to a new value. /
Kojto	90:cb3d968589d8	1363	#define BW_LLWU_F2_WUF11(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF11) = (v))
Kojto	90:cb3d968589d8	1364	/@}/
Kojto	90:cb3d968589d8	1365
Kojto	90:cb3d968589d8	1366	/*!
Kojto	90:cb3d968589d8	1367	* @name Register LLWU_F2, field WUF12[4] (W1C)
Kojto	90:cb3d968589d8	1368	*
Kojto	90:cb3d968589d8	1369	* Indicates that an enabled external wakeup pin was a source of exiting a
Kojto	90:cb3d968589d8	1370	* low-leakage power mode. To clear the flag, write a 1 to WUF12.
Kojto	90:cb3d968589d8	1371	*
Kojto	90:cb3d968589d8	1372	* Values:
Kojto	90:cb3d968589d8	1373	* - 0 - LLWU_P12 input was not a wakeup source
Kojto	90:cb3d968589d8	1374	* - 1 - LLWU_P12 input was a wakeup source
Kojto	90:cb3d968589d8	1375	*/
Kojto	90:cb3d968589d8	1376	/@{/
Kojto	90:cb3d968589d8	1377	#define BP_LLWU_F2_WUF12 (4U) /!< Bit position for LLWU_F2_WUF12. /
Kojto	90:cb3d968589d8	1378	#define BM_LLWU_F2_WUF12 (0x10U) /!< Bit mask for LLWU_F2_WUF12. /
Kojto	90:cb3d968589d8	1379	#define BS_LLWU_F2_WUF12 (1U) /!< Bit field size in bits for LLWU_F2_WUF12. /
Kojto	90:cb3d968589d8	1380
Kojto	90:cb3d968589d8	1381	/! @brief Read current value of the LLWU_F2_WUF12 field. /
Kojto	90:cb3d968589d8	1382	#define BR_LLWU_F2_WUF12(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF12))
Kojto	90:cb3d968589d8	1383
Kojto	90:cb3d968589d8	1384	/! @brief Format value for bitfield LLWU_F2_WUF12. /
Kojto	90:cb3d968589d8	1385	#define BF_LLWU_F2_WUF12(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF12) & BM_LLWU_F2_WUF12)
Kojto	90:cb3d968589d8	1386
Kojto	90:cb3d968589d8	1387	/! @brief Set the WUF12 field to a new value. /
Kojto	90:cb3d968589d8	1388	#define BW_LLWU_F2_WUF12(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF12) = (v))
Kojto	90:cb3d968589d8	1389	/@}/
Kojto	90:cb3d968589d8	1390
Kojto	90:cb3d968589d8	1391	/*!
Kojto	90:cb3d968589d8	1392	* @name Register LLWU_F2, field WUF13[5] (W1C)
Kojto	90:cb3d968589d8	1393	*
Kojto	90:cb3d968589d8	1394	* Indicates that an enabled external wakeup pin was a source of exiting a
Kojto	90:cb3d968589d8	1395	* low-leakage power mode. To clear the flag, write a 1 to WUF13.
Kojto	90:cb3d968589d8	1396	*
Kojto	90:cb3d968589d8	1397	* Values:
Kojto	90:cb3d968589d8	1398	* - 0 - LLWU_P13 input was not a wakeup source
Kojto	90:cb3d968589d8	1399	* - 1 - LLWU_P13 input was a wakeup source
Kojto	90:cb3d968589d8	1400	*/
Kojto	90:cb3d968589d8	1401	/@{/
Kojto	90:cb3d968589d8	1402	#define BP_LLWU_F2_WUF13 (5U) /!< Bit position for LLWU_F2_WUF13. /
Kojto	90:cb3d968589d8	1403	#define BM_LLWU_F2_WUF13 (0x20U) /!< Bit mask for LLWU_F2_WUF13. /
Kojto	90:cb3d968589d8	1404	#define BS_LLWU_F2_WUF13 (1U) /!< Bit field size in bits for LLWU_F2_WUF13. /
Kojto	90:cb3d968589d8	1405
Kojto	90:cb3d968589d8	1406	/! @brief Read current value of the LLWU_F2_WUF13 field. /
Kojto	90:cb3d968589d8	1407	#define BR_LLWU_F2_WUF13(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF13))
Kojto	90:cb3d968589d8	1408
Kojto	90:cb3d968589d8	1409	/! @brief Format value for bitfield LLWU_F2_WUF13. /
Kojto	90:cb3d968589d8	1410	#define BF_LLWU_F2_WUF13(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF13) & BM_LLWU_F2_WUF13)
Kojto	90:cb3d968589d8	1411
Kojto	90:cb3d968589d8	1412	/! @brief Set the WUF13 field to a new value. /
Kojto	90:cb3d968589d8	1413	#define BW_LLWU_F2_WUF13(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF13) = (v))
Kojto	90:cb3d968589d8	1414	/@}/
Kojto	90:cb3d968589d8	1415
Kojto	90:cb3d968589d8	1416	/*!
Kojto	90:cb3d968589d8	1417	* @name Register LLWU_F2, field WUF14[6] (W1C)
Kojto	90:cb3d968589d8	1418	*
Kojto	90:cb3d968589d8	1419	* Indicates that an enabled external wakeup pin was a source of exiting a
Kojto	90:cb3d968589d8	1420	* low-leakage power mode. To clear the flag, write a 1 to WUF14.
Kojto	90:cb3d968589d8	1421	*
Kojto	90:cb3d968589d8	1422	* Values:
Kojto	90:cb3d968589d8	1423	* - 0 - LLWU_P14 input was not a wakeup source
Kojto	90:cb3d968589d8	1424	* - 1 - LLWU_P14 input was a wakeup source
Kojto	90:cb3d968589d8	1425	*/
Kojto	90:cb3d968589d8	1426	/@{/
Kojto	90:cb3d968589d8	1427	#define BP_LLWU_F2_WUF14 (6U) /!< Bit position for LLWU_F2_WUF14. /
Kojto	90:cb3d968589d8	1428	#define BM_LLWU_F2_WUF14 (0x40U) /!< Bit mask for LLWU_F2_WUF14. /
Kojto	90:cb3d968589d8	1429	#define BS_LLWU_F2_WUF14 (1U) /!< Bit field size in bits for LLWU_F2_WUF14. /
Kojto	90:cb3d968589d8	1430
Kojto	90:cb3d968589d8	1431	/! @brief Read current value of the LLWU_F2_WUF14 field. /
Kojto	90:cb3d968589d8	1432	#define BR_LLWU_F2_WUF14(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF14))
Kojto	90:cb3d968589d8	1433
Kojto	90:cb3d968589d8	1434	/! @brief Format value for bitfield LLWU_F2_WUF14. /
Kojto	90:cb3d968589d8	1435	#define BF_LLWU_F2_WUF14(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF14) & BM_LLWU_F2_WUF14)
Kojto	90:cb3d968589d8	1436
Kojto	90:cb3d968589d8	1437	/! @brief Set the WUF14 field to a new value. /
Kojto	90:cb3d968589d8	1438	#define BW_LLWU_F2_WUF14(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF14) = (v))
Kojto	90:cb3d968589d8	1439	/@}/
Kojto	90:cb3d968589d8	1440
Kojto	90:cb3d968589d8	1441	/*!
Kojto	90:cb3d968589d8	1442	* @name Register LLWU_F2, field WUF15[7] (W1C)
Kojto	90:cb3d968589d8	1443	*
Kojto	90:cb3d968589d8	1444	* Indicates that an enabled external wakeup pin was a source of exiting a
Kojto	90:cb3d968589d8	1445	* low-leakage power mode. To clear the flag, write a 1 to WUF15.
Kojto	90:cb3d968589d8	1446	*
Kojto	90:cb3d968589d8	1447	* Values:
Kojto	90:cb3d968589d8	1448	* - 0 - LLWU_P15 input was not a wakeup source
Kojto	90:cb3d968589d8	1449	* - 1 - LLWU_P15 input was a wakeup source
Kojto	90:cb3d968589d8	1450	*/
Kojto	90:cb3d968589d8	1451	/@{/
Kojto	90:cb3d968589d8	1452	#define BP_LLWU_F2_WUF15 (7U) /!< Bit position for LLWU_F2_WUF15. /
Kojto	90:cb3d968589d8	1453	#define BM_LLWU_F2_WUF15 (0x80U) /!< Bit mask for LLWU_F2_WUF15. /
Kojto	90:cb3d968589d8	1454	#define BS_LLWU_F2_WUF15 (1U) /!< Bit field size in bits for LLWU_F2_WUF15. /
Kojto	90:cb3d968589d8	1455
Kojto	90:cb3d968589d8	1456	/! @brief Read current value of the LLWU_F2_WUF15 field. /
Kojto	90:cb3d968589d8	1457	#define BR_LLWU_F2_WUF15(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF15))
Kojto	90:cb3d968589d8	1458
Kojto	90:cb3d968589d8	1459	/! @brief Format value for bitfield LLWU_F2_WUF15. /
Kojto	90:cb3d968589d8	1460	#define BF_LLWU_F2_WUF15(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF15) & BM_LLWU_F2_WUF15)
Kojto	90:cb3d968589d8	1461
Kojto	90:cb3d968589d8	1462	/! @brief Set the WUF15 field to a new value. /
Kojto	90:cb3d968589d8	1463	#define BW_LLWU_F2_WUF15(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF15) = (v))
Kojto	90:cb3d968589d8	1464	/@}/
Kojto	90:cb3d968589d8	1465
Kojto	90:cb3d968589d8	1466	/*******************************************************************************
Kojto	90:cb3d968589d8	1467	* HW_LLWU_F3 - LLWU Flag 3 register
Kojto	90:cb3d968589d8	1468	******************************************************************************/
Kojto	90:cb3d968589d8	1469
Kojto	90:cb3d968589d8	1470	/*!
Kojto	90:cb3d968589d8	1471	* @brief HW_LLWU_F3 - LLWU Flag 3 register (RO)
Kojto	90:cb3d968589d8	1472	*
Kojto	90:cb3d968589d8	1473	* Reset value: 0x00U
Kojto	90:cb3d968589d8	1474	*
Kojto	90:cb3d968589d8	1475	* LLWU_F3 contains the wakeup flags indicating which internal wakeup source
Kojto	90:cb3d968589d8	1476	* caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the
Kojto	90:cb3d968589d8	1477	* CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow.
Kojto	90:cb3d968589d8	1478	* For internal peripherals that are capable of running in a low-leakage power
Kojto	90:cb3d968589d8	1479	* mode, such as a real time clock module or CMP module, the flag from the
Kojto	90:cb3d968589d8	1480	* associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared
Kojto	90:cb3d968589d8	1481	* in the peripheral instead of writing a 1 to the MWUFx bit. This register is
Kojto	90:cb3d968589d8	1482	* reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not
Kojto	90:cb3d968589d8	1483	* VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See
Kojto	90:cb3d968589d8	1484	* the IntroductionInformation found here describes the registers of the Reset
Kojto	90:cb3d968589d8	1485	* Control Module (RCM). The RCM implements many of the reset functions for the
Kojto	90:cb3d968589d8	1486	* chip. See the chip's reset chapter for more information. details for more
Kojto	90:cb3d968589d8	1487	* information.
Kojto	90:cb3d968589d8	1488	*/
Kojto	90:cb3d968589d8	1489	typedef union _hw_llwu_f3
Kojto	90:cb3d968589d8	1490	{
Kojto	90:cb3d968589d8	1491	uint8_t U;
Kojto	90:cb3d968589d8	1492	struct _hw_llwu_f3_bitfields
Kojto	90:cb3d968589d8	1493	{
Kojto	90:cb3d968589d8	1494	uint8_t MWUF0 : 1; /!< [0] Wakeup flag For module 0 /
Kojto	90:cb3d968589d8	1495	uint8_t MWUF1 : 1; /!< [1] Wakeup flag For module 1 /
Kojto	90:cb3d968589d8	1496	uint8_t MWUF2 : 1; /!< [2] Wakeup flag For module 2 /
Kojto	90:cb3d968589d8	1497	uint8_t MWUF3 : 1; /!< [3] Wakeup flag For module 3 /
Kojto	90:cb3d968589d8	1498	uint8_t MWUF4 : 1; /!< [4] Wakeup flag For module 4 /
Kojto	90:cb3d968589d8	1499	uint8_t MWUF5 : 1; /!< [5] Wakeup flag For module 5 /
Kojto	90:cb3d968589d8	1500	uint8_t MWUF6 : 1; /!< [6] Wakeup flag For module 6 /
Kojto	90:cb3d968589d8	1501	uint8_t MWUF7 : 1; /!< [7] Wakeup flag For module 7 /
Kojto	90:cb3d968589d8	1502	} B;
Kojto	90:cb3d968589d8	1503	} hw_llwu_f3_t;
Kojto	90:cb3d968589d8	1504
Kojto	90:cb3d968589d8	1505	/*!
Kojto	90:cb3d968589d8	1506	* @name Constants and macros for entire LLWU_F3 register
Kojto	90:cb3d968589d8	1507	*/
Kojto	90:cb3d968589d8	1508	/@{/
Kojto	90:cb3d968589d8	1509	#define HW_LLWU_F3_ADDR(x) ((x) + 0x7U)
Kojto	90:cb3d968589d8	1510
Kojto	90:cb3d968589d8	1511	#define HW_LLWU_F3(x) ((__I hw_llwu_f3_t ) HW_LLWU_F3_ADDR(x))
Kojto	90:cb3d968589d8	1512	#define HW_LLWU_F3_RD(x) (HW_LLWU_F3(x).U)
Kojto	90:cb3d968589d8	1513	/@}/
Kojto	90:cb3d968589d8	1514
Kojto	90:cb3d968589d8	1515	/*
Kojto	90:cb3d968589d8	1516	* Constants & macros for individual LLWU_F3 bitfields
Kojto	90:cb3d968589d8	1517	*/
Kojto	90:cb3d968589d8	1518
Kojto	90:cb3d968589d8	1519	/*!
Kojto	90:cb3d968589d8	1520	* @name Register LLWU_F3, field MWUF0[0] (RO)
Kojto	90:cb3d968589d8	1521	*
Kojto	90:cb3d968589d8	1522	* Indicates that an enabled internal peripheral was a source of exiting a
Kojto	90:cb3d968589d8	1523	* low-leakage power mode. To clear the flag, follow the internal peripheral flag
Kojto	90:cb3d968589d8	1524	* clearing mechanism.
Kojto	90:cb3d968589d8	1525	*
Kojto	90:cb3d968589d8	1526	* Values:
Kojto	90:cb3d968589d8	1527	* - 0 - Module 0 input was not a wakeup source
Kojto	90:cb3d968589d8	1528	* - 1 - Module 0 input was a wakeup source
Kojto	90:cb3d968589d8	1529	*/
Kojto	90:cb3d968589d8	1530	/@{/
Kojto	90:cb3d968589d8	1531	#define BP_LLWU_F3_MWUF0 (0U) /!< Bit position for LLWU_F3_MWUF0. /
Kojto	90:cb3d968589d8	1532	#define BM_LLWU_F3_MWUF0 (0x01U) /!< Bit mask for LLWU_F3_MWUF0. /
Kojto	90:cb3d968589d8	1533	#define BS_LLWU_F3_MWUF0 (1U) /!< Bit field size in bits for LLWU_F3_MWUF0. /
Kojto	90:cb3d968589d8	1534
Kojto	90:cb3d968589d8	1535	/! @brief Read current value of the LLWU_F3_MWUF0 field. /
Kojto	90:cb3d968589d8	1536	#define BR_LLWU_F3_MWUF0(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF0))
Kojto	90:cb3d968589d8	1537	/@}/
Kojto	90:cb3d968589d8	1538
Kojto	90:cb3d968589d8	1539	/*!
Kojto	90:cb3d968589d8	1540	* @name Register LLWU_F3, field MWUF1[1] (RO)
Kojto	90:cb3d968589d8	1541	*
Kojto	90:cb3d968589d8	1542	* Indicates that an enabled internal peripheral was a source of exiting a
Kojto	90:cb3d968589d8	1543	* low-leakage power mode. To clear the flag, follow the internal peripheral flag
Kojto	90:cb3d968589d8	1544	* clearing mechanism.
Kojto	90:cb3d968589d8	1545	*
Kojto	90:cb3d968589d8	1546	* Values:
Kojto	90:cb3d968589d8	1547	* - 0 - Module 1 input was not a wakeup source
Kojto	90:cb3d968589d8	1548	* - 1 - Module 1 input was a wakeup source
Kojto	90:cb3d968589d8	1549	*/
Kojto	90:cb3d968589d8	1550	/@{/
Kojto	90:cb3d968589d8	1551	#define BP_LLWU_F3_MWUF1 (1U) /!< Bit position for LLWU_F3_MWUF1. /
Kojto	90:cb3d968589d8	1552	#define BM_LLWU_F3_MWUF1 (0x02U) /!< Bit mask for LLWU_F3_MWUF1. /
Kojto	90:cb3d968589d8	1553	#define BS_LLWU_F3_MWUF1 (1U) /!< Bit field size in bits for LLWU_F3_MWUF1. /
Kojto	90:cb3d968589d8	1554
Kojto	90:cb3d968589d8	1555	/! @brief Read current value of the LLWU_F3_MWUF1 field. /
Kojto	90:cb3d968589d8	1556	#define BR_LLWU_F3_MWUF1(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF1))
Kojto	90:cb3d968589d8	1557	/@}/
Kojto	90:cb3d968589d8	1558
Kojto	90:cb3d968589d8	1559	/*!
Kojto	90:cb3d968589d8	1560	* @name Register LLWU_F3, field MWUF2[2] (RO)
Kojto	90:cb3d968589d8	1561	*
Kojto	90:cb3d968589d8	1562	* Indicates that an enabled internal peripheral was a source of exiting a
Kojto	90:cb3d968589d8	1563	* low-leakage power mode. To clear the flag, follow the internal peripheral flag
Kojto	90:cb3d968589d8	1564	* clearing mechanism.
Kojto	90:cb3d968589d8	1565	*
Kojto	90:cb3d968589d8	1566	* Values:
Kojto	90:cb3d968589d8	1567	* - 0 - Module 2 input was not a wakeup source
Kojto	90:cb3d968589d8	1568	* - 1 - Module 2 input was a wakeup source
Kojto	90:cb3d968589d8	1569	*/
Kojto	90:cb3d968589d8	1570	/@{/
Kojto	90:cb3d968589d8	1571	#define BP_LLWU_F3_MWUF2 (2U) /!< Bit position for LLWU_F3_MWUF2. /
Kojto	90:cb3d968589d8	1572	#define BM_LLWU_F3_MWUF2 (0x04U) /!< Bit mask for LLWU_F3_MWUF2. /
Kojto	90:cb3d968589d8	1573	#define BS_LLWU_F3_MWUF2 (1U) /!< Bit field size in bits for LLWU_F3_MWUF2. /
Kojto	90:cb3d968589d8	1574
Kojto	90:cb3d968589d8	1575	/! @brief Read current value of the LLWU_F3_MWUF2 field. /
Kojto	90:cb3d968589d8	1576	#define BR_LLWU_F3_MWUF2(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF2))
Kojto	90:cb3d968589d8	1577	/@}/
Kojto	90:cb3d968589d8	1578
Kojto	90:cb3d968589d8	1579	/*!
Kojto	90:cb3d968589d8	1580	* @name Register LLWU_F3, field MWUF3[3] (RO)
Kojto	90:cb3d968589d8	1581	*
Kojto	90:cb3d968589d8	1582	* Indicates that an enabled internal peripheral was a source of exiting a
Kojto	90:cb3d968589d8	1583	* low-leakage power mode. To clear the flag, follow the internal peripheral flag
Kojto	90:cb3d968589d8	1584	* clearing mechanism.
Kojto	90:cb3d968589d8	1585	*
Kojto	90:cb3d968589d8	1586	* Values:
Kojto	90:cb3d968589d8	1587	* - 0 - Module 3 input was not a wakeup source
Kojto	90:cb3d968589d8	1588	* - 1 - Module 3 input was a wakeup source
Kojto	90:cb3d968589d8	1589	*/
Kojto	90:cb3d968589d8	1590	/@{/
Kojto	90:cb3d968589d8	1591	#define BP_LLWU_F3_MWUF3 (3U) /!< Bit position for LLWU_F3_MWUF3. /
Kojto	90:cb3d968589d8	1592	#define BM_LLWU_F3_MWUF3 (0x08U) /!< Bit mask for LLWU_F3_MWUF3. /
Kojto	90:cb3d968589d8	1593	#define BS_LLWU_F3_MWUF3 (1U) /!< Bit field size in bits for LLWU_F3_MWUF3. /
Kojto	90:cb3d968589d8	1594
Kojto	90:cb3d968589d8	1595	/! @brief Read current value of the LLWU_F3_MWUF3 field. /
Kojto	90:cb3d968589d8	1596	#define BR_LLWU_F3_MWUF3(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF3))
Kojto	90:cb3d968589d8	1597	/@}/
Kojto	90:cb3d968589d8	1598
Kojto	90:cb3d968589d8	1599	/*!
Kojto	90:cb3d968589d8	1600	* @name Register LLWU_F3, field MWUF4[4] (RO)
Kojto	90:cb3d968589d8	1601	*
Kojto	90:cb3d968589d8	1602	* Indicates that an enabled internal peripheral was a source of exiting a
Kojto	90:cb3d968589d8	1603	* low-leakage power mode. To clear the flag, follow the internal peripheral flag
Kojto	90:cb3d968589d8	1604	* clearing mechanism.
Kojto	90:cb3d968589d8	1605	*
Kojto	90:cb3d968589d8	1606	* Values:
Kojto	90:cb3d968589d8	1607	* - 0 - Module 4 input was not a wakeup source
Kojto	90:cb3d968589d8	1608	* - 1 - Module 4 input was a wakeup source
Kojto	90:cb3d968589d8	1609	*/
Kojto	90:cb3d968589d8	1610	/@{/
Kojto	90:cb3d968589d8	1611	#define BP_LLWU_F3_MWUF4 (4U) /!< Bit position for LLWU_F3_MWUF4. /
Kojto	90:cb3d968589d8	1612	#define BM_LLWU_F3_MWUF4 (0x10U) /!< Bit mask for LLWU_F3_MWUF4. /
Kojto	90:cb3d968589d8	1613	#define BS_LLWU_F3_MWUF4 (1U) /!< Bit field size in bits for LLWU_F3_MWUF4. /
Kojto	90:cb3d968589d8	1614
Kojto	90:cb3d968589d8	1615	/! @brief Read current value of the LLWU_F3_MWUF4 field. /
Kojto	90:cb3d968589d8	1616	#define BR_LLWU_F3_MWUF4(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF4))
Kojto	90:cb3d968589d8	1617	/@}/
Kojto	90:cb3d968589d8	1618
Kojto	90:cb3d968589d8	1619	/*!
Kojto	90:cb3d968589d8	1620	* @name Register LLWU_F3, field MWUF5[5] (RO)
Kojto	90:cb3d968589d8	1621	*
Kojto	90:cb3d968589d8	1622	* Indicates that an enabled internal peripheral was a source of exiting a
Kojto	90:cb3d968589d8	1623	* low-leakage power mode. To clear the flag, follow the internal peripheral flag
Kojto	90:cb3d968589d8	1624	* clearing mechanism.
Kojto	90:cb3d968589d8	1625	*
Kojto	90:cb3d968589d8	1626	* Values:
Kojto	90:cb3d968589d8	1627	* - 0 - Module 5 input was not a wakeup source
Kojto	90:cb3d968589d8	1628	* - 1 - Module 5 input was a wakeup source
Kojto	90:cb3d968589d8	1629	*/
Kojto	90:cb3d968589d8	1630	/@{/
Kojto	90:cb3d968589d8	1631	#define BP_LLWU_F3_MWUF5 (5U) /!< Bit position for LLWU_F3_MWUF5. /
Kojto	90:cb3d968589d8	1632	#define BM_LLWU_F3_MWUF5 (0x20U) /!< Bit mask for LLWU_F3_MWUF5. /
Kojto	90:cb3d968589d8	1633	#define BS_LLWU_F3_MWUF5 (1U) /!< Bit field size in bits for LLWU_F3_MWUF5. /
Kojto	90:cb3d968589d8	1634
Kojto	90:cb3d968589d8	1635	/! @brief Read current value of the LLWU_F3_MWUF5 field. /
Kojto	90:cb3d968589d8	1636	#define BR_LLWU_F3_MWUF5(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF5))
Kojto	90:cb3d968589d8	1637	/@}/
Kojto	90:cb3d968589d8	1638
Kojto	90:cb3d968589d8	1639	/*!
Kojto	90:cb3d968589d8	1640	* @name Register LLWU_F3, field MWUF6[6] (RO)
Kojto	90:cb3d968589d8	1641	*
Kojto	90:cb3d968589d8	1642	* Indicates that an enabled internal peripheral was a source of exiting a
Kojto	90:cb3d968589d8	1643	* low-leakage power mode. To clear the flag, follow the internal peripheral flag
Kojto	90:cb3d968589d8	1644	* clearing mechanism.
Kojto	90:cb3d968589d8	1645	*
Kojto	90:cb3d968589d8	1646	* Values:
Kojto	90:cb3d968589d8	1647	* - 0 - Module 6 input was not a wakeup source
Kojto	90:cb3d968589d8	1648	* - 1 - Module 6 input was a wakeup source
Kojto	90:cb3d968589d8	1649	*/
Kojto	90:cb3d968589d8	1650	/@{/
Kojto	90:cb3d968589d8	1651	#define BP_LLWU_F3_MWUF6 (6U) /!< Bit position for LLWU_F3_MWUF6. /
Kojto	90:cb3d968589d8	1652	#define BM_LLWU_F3_MWUF6 (0x40U) /!< Bit mask for LLWU_F3_MWUF6. /
Kojto	90:cb3d968589d8	1653	#define BS_LLWU_F3_MWUF6 (1U) /!< Bit field size in bits for LLWU_F3_MWUF6. /
Kojto	90:cb3d968589d8	1654
Kojto	90:cb3d968589d8	1655	/! @brief Read current value of the LLWU_F3_MWUF6 field. /
Kojto	90:cb3d968589d8	1656	#define BR_LLWU_F3_MWUF6(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF6))
Kojto	90:cb3d968589d8	1657	/@}/
Kojto	90:cb3d968589d8	1658
Kojto	90:cb3d968589d8	1659	/*!
Kojto	90:cb3d968589d8	1660	* @name Register LLWU_F3, field MWUF7[7] (RO)
Kojto	90:cb3d968589d8	1661	*
Kojto	90:cb3d968589d8	1662	* Indicates that an enabled internal peripheral was a source of exiting a
Kojto	90:cb3d968589d8	1663	* low-leakage power mode. To clear the flag, follow the internal peripheral flag
Kojto	90:cb3d968589d8	1664	* clearing mechanism.
Kojto	90:cb3d968589d8	1665	*
Kojto	90:cb3d968589d8	1666	* Values:
Kojto	90:cb3d968589d8	1667	* - 0 - Module 7 input was not a wakeup source
Kojto	90:cb3d968589d8	1668	* - 1 - Module 7 input was a wakeup source
Kojto	90:cb3d968589d8	1669	*/
Kojto	90:cb3d968589d8	1670	/@{/
Kojto	90:cb3d968589d8	1671	#define BP_LLWU_F3_MWUF7 (7U) /!< Bit position for LLWU_F3_MWUF7. /
Kojto	90:cb3d968589d8	1672	#define BM_LLWU_F3_MWUF7 (0x80U) /!< Bit mask for LLWU_F3_MWUF7. /
Kojto	90:cb3d968589d8	1673	#define BS_LLWU_F3_MWUF7 (1U) /!< Bit field size in bits for LLWU_F3_MWUF7. /
Kojto	90:cb3d968589d8	1674
Kojto	90:cb3d968589d8	1675	/! @brief Read current value of the LLWU_F3_MWUF7 field. /
Kojto	90:cb3d968589d8	1676	#define BR_LLWU_F3_MWUF7(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF7))
Kojto	90:cb3d968589d8	1677	/@}/
Kojto	90:cb3d968589d8	1678
Kojto	90:cb3d968589d8	1679	/*******************************************************************************
Kojto	90:cb3d968589d8	1680	* HW_LLWU_FILT1 - LLWU Pin Filter 1 register
Kojto	90:cb3d968589d8	1681	******************************************************************************/
Kojto	90:cb3d968589d8	1682
Kojto	90:cb3d968589d8	1683	/*!
Kojto	90:cb3d968589d8	1684	* @brief HW_LLWU_FILT1 - LLWU Pin Filter 1 register (RW)
Kojto	90:cb3d968589d8	1685	*
Kojto	90:cb3d968589d8	1686	* Reset value: 0x00U
Kojto	90:cb3d968589d8	1687	*
Kojto	90:cb3d968589d8	1688	* LLWU_FILT1 is a control and status register that is used to enable/disable
Kojto	90:cb3d968589d8	1689	* the digital filter 1 features for an external pin. This register is reset on
Kojto	90:cb3d968589d8	1690	* Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
Kojto	90:cb3d968589d8	1691	* unaffected by reset types that do not trigger Chip Reset not VLLS. See the
Kojto	90:cb3d968589d8	1692	* IntroductionInformation found here describes the registers of the Reset Control
Kojto	90:cb3d968589d8	1693	* Module (RCM). The RCM implements many of the reset functions for the chip. See
Kojto	90:cb3d968589d8	1694	* the chip's reset chapter for more information. details for more information.
Kojto	90:cb3d968589d8	1695	*/
Kojto	90:cb3d968589d8	1696	typedef union _hw_llwu_filt1
Kojto	90:cb3d968589d8	1697	{
Kojto	90:cb3d968589d8	1698	uint8_t U;
Kojto	90:cb3d968589d8	1699	struct _hw_llwu_filt1_bitfields
Kojto	90:cb3d968589d8	1700	{
Kojto	90:cb3d968589d8	1701	uint8_t FILTSEL : 4; /!< [3:0] Filter Pin Select /
Kojto	90:cb3d968589d8	1702	uint8_t RESERVED0 : 1; /!< [4] /
Kojto	90:cb3d968589d8	1703	uint8_t FILTE : 2; /!< [6:5] Digital Filter On External Pin /
Kojto	90:cb3d968589d8	1704	uint8_t FILTF : 1; /!< [7] Filter Detect Flag /
Kojto	90:cb3d968589d8	1705	} B;
Kojto	90:cb3d968589d8	1706	} hw_llwu_filt1_t;
Kojto	90:cb3d968589d8	1707
Kojto	90:cb3d968589d8	1708	/*!
Kojto	90:cb3d968589d8	1709	* @name Constants and macros for entire LLWU_FILT1 register
Kojto	90:cb3d968589d8	1710	*/
Kojto	90:cb3d968589d8	1711	/@{/
Kojto	90:cb3d968589d8	1712	#define HW_LLWU_FILT1_ADDR(x) ((x) + 0x8U)
Kojto	90:cb3d968589d8	1713
Kojto	90:cb3d968589d8	1714	#define HW_LLWU_FILT1(x) ((__IO hw_llwu_filt1_t ) HW_LLWU_FILT1_ADDR(x))
Kojto	90:cb3d968589d8	1715	#define HW_LLWU_FILT1_RD(x) (HW_LLWU_FILT1(x).U)
Kojto	90:cb3d968589d8	1716	#define HW_LLWU_FILT1_WR(x, v) (HW_LLWU_FILT1(x).U = (v))
Kojto	90:cb3d968589d8	1717	#define HW_LLWU_FILT1_SET(x, v) (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1718	#define HW_LLWU_FILT1_CLR(x, v) (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1719	#define HW_LLWU_FILT1_TOG(x, v) (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1720	/@}/
Kojto	90:cb3d968589d8	1721
Kojto	90:cb3d968589d8	1722	/*
Kojto	90:cb3d968589d8	1723	* Constants & macros for individual LLWU_FILT1 bitfields
Kojto	90:cb3d968589d8	1724	*/
Kojto	90:cb3d968589d8	1725
Kojto	90:cb3d968589d8	1726	/*!
Kojto	90:cb3d968589d8	1727	* @name Register LLWU_FILT1, field FILTSEL[3:0] (RW)
Kojto	90:cb3d968589d8	1728	*
Kojto	90:cb3d968589d8	1729	* Selects 1 out of the 16 wakeup pins to be muxed into the filter.
Kojto	90:cb3d968589d8	1730	*
Kojto	90:cb3d968589d8	1731	* Values:
Kojto	90:cb3d968589d8	1732	* - 0000 - Select LLWU_P0 for filter
Kojto	90:cb3d968589d8	1733	* - 1111 - Select LLWU_P15 for filter
Kojto	90:cb3d968589d8	1734	*/
Kojto	90:cb3d968589d8	1735	/@{/
Kojto	90:cb3d968589d8	1736	#define BP_LLWU_FILT1_FILTSEL (0U) /!< Bit position for LLWU_FILT1_FILTSEL. /
Kojto	90:cb3d968589d8	1737	#define BM_LLWU_FILT1_FILTSEL (0x0FU) /!< Bit mask for LLWU_FILT1_FILTSEL. /
Kojto	90:cb3d968589d8	1738	#define BS_LLWU_FILT1_FILTSEL (4U) /!< Bit field size in bits for LLWU_FILT1_FILTSEL. /
Kojto	90:cb3d968589d8	1739
Kojto	90:cb3d968589d8	1740	/! @brief Read current value of the LLWU_FILT1_FILTSEL field. /
Kojto	90:cb3d968589d8	1741	#define BR_LLWU_FILT1_FILTSEL(x) (HW_LLWU_FILT1(x).B.FILTSEL)
Kojto	90:cb3d968589d8	1742
Kojto	90:cb3d968589d8	1743	/! @brief Format value for bitfield LLWU_FILT1_FILTSEL. /
Kojto	90:cb3d968589d8	1744	#define BF_LLWU_FILT1_FILTSEL(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTSEL) & BM_LLWU_FILT1_FILTSEL)
Kojto	90:cb3d968589d8	1745
Kojto	90:cb3d968589d8	1746	/! @brief Set the FILTSEL field to a new value. /
Kojto	90:cb3d968589d8	1747	#define BW_LLWU_FILT1_FILTSEL(x, v) (HW_LLWU_FILT1_WR(x, (HW_LLWU_FILT1_RD(x) & ~BM_LLWU_FILT1_FILTSEL) \| BF_LLWU_FILT1_FILTSEL(v)))
Kojto	90:cb3d968589d8	1748	/@}/
Kojto	90:cb3d968589d8	1749
Kojto	90:cb3d968589d8	1750	/*!
Kojto	90:cb3d968589d8	1751	* @name Register LLWU_FILT1, field FILTE[6:5] (RW)
Kojto	90:cb3d968589d8	1752	*
Kojto	90:cb3d968589d8	1753	* Controls the digital filter options for the external pin detect.
Kojto	90:cb3d968589d8	1754	*
Kojto	90:cb3d968589d8	1755	* Values:
Kojto	90:cb3d968589d8	1756	* - 00 - Filter disabled
Kojto	90:cb3d968589d8	1757	* - 01 - Filter posedge detect enabled
Kojto	90:cb3d968589d8	1758	* - 10 - Filter negedge detect enabled
Kojto	90:cb3d968589d8	1759	* - 11 - Filter any edge detect enabled
Kojto	90:cb3d968589d8	1760	*/
Kojto	90:cb3d968589d8	1761	/@{/
Kojto	90:cb3d968589d8	1762	#define BP_LLWU_FILT1_FILTE (5U) /!< Bit position for LLWU_FILT1_FILTE. /
Kojto	90:cb3d968589d8	1763	#define BM_LLWU_FILT1_FILTE (0x60U) /!< Bit mask for LLWU_FILT1_FILTE. /
Kojto	90:cb3d968589d8	1764	#define BS_LLWU_FILT1_FILTE (2U) /!< Bit field size in bits for LLWU_FILT1_FILTE. /
Kojto	90:cb3d968589d8	1765
Kojto	90:cb3d968589d8	1766	/! @brief Read current value of the LLWU_FILT1_FILTE field. /
Kojto	90:cb3d968589d8	1767	#define BR_LLWU_FILT1_FILTE(x) (HW_LLWU_FILT1(x).B.FILTE)
Kojto	90:cb3d968589d8	1768
Kojto	90:cb3d968589d8	1769	/! @brief Format value for bitfield LLWU_FILT1_FILTE. /
Kojto	90:cb3d968589d8	1770	#define BF_LLWU_FILT1_FILTE(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTE) & BM_LLWU_FILT1_FILTE)
Kojto	90:cb3d968589d8	1771
Kojto	90:cb3d968589d8	1772	/! @brief Set the FILTE field to a new value. /
Kojto	90:cb3d968589d8	1773	#define BW_LLWU_FILT1_FILTE(x, v) (HW_LLWU_FILT1_WR(x, (HW_LLWU_FILT1_RD(x) & ~BM_LLWU_FILT1_FILTE) \| BF_LLWU_FILT1_FILTE(v)))
Kojto	90:cb3d968589d8	1774	/@}/
Kojto	90:cb3d968589d8	1775
Kojto	90:cb3d968589d8	1776	/*!
Kojto	90:cb3d968589d8	1777	* @name Register LLWU_FILT1, field FILTF[7] (W1C)
Kojto	90:cb3d968589d8	1778	*
Kojto	90:cb3d968589d8	1779	* Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
Kojto	90:cb3d968589d8	1780	* source of exiting a low-leakage power mode. To clear the flag write a one to
Kojto	90:cb3d968589d8	1781	* FILTF.
Kojto	90:cb3d968589d8	1782	*
Kojto	90:cb3d968589d8	1783	* Values:
Kojto	90:cb3d968589d8	1784	* - 0 - Pin Filter 1 was not a wakeup source
Kojto	90:cb3d968589d8	1785	* - 1 - Pin Filter 1 was a wakeup source
Kojto	90:cb3d968589d8	1786	*/
Kojto	90:cb3d968589d8	1787	/@{/
Kojto	90:cb3d968589d8	1788	#define BP_LLWU_FILT1_FILTF (7U) /!< Bit position for LLWU_FILT1_FILTF. /
Kojto	90:cb3d968589d8	1789	#define BM_LLWU_FILT1_FILTF (0x80U) /!< Bit mask for LLWU_FILT1_FILTF. /
Kojto	90:cb3d968589d8	1790	#define BS_LLWU_FILT1_FILTF (1U) /!< Bit field size in bits for LLWU_FILT1_FILTF. /
Kojto	90:cb3d968589d8	1791
Kojto	90:cb3d968589d8	1792	/! @brief Read current value of the LLWU_FILT1_FILTF field. /
Kojto	90:cb3d968589d8	1793	#define BR_LLWU_FILT1_FILTF(x) (BITBAND_ACCESS8(HW_LLWU_FILT1_ADDR(x), BP_LLWU_FILT1_FILTF))
Kojto	90:cb3d968589d8	1794
Kojto	90:cb3d968589d8	1795	/! @brief Format value for bitfield LLWU_FILT1_FILTF. /
Kojto	90:cb3d968589d8	1796	#define BF_LLWU_FILT1_FILTF(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTF) & BM_LLWU_FILT1_FILTF)
Kojto	90:cb3d968589d8	1797
Kojto	90:cb3d968589d8	1798	/! @brief Set the FILTF field to a new value. /
Kojto	90:cb3d968589d8	1799	#define BW_LLWU_FILT1_FILTF(x, v) (BITBAND_ACCESS8(HW_LLWU_FILT1_ADDR(x), BP_LLWU_FILT1_FILTF) = (v))
Kojto	90:cb3d968589d8	1800	/@}/
Kojto	90:cb3d968589d8	1801
Kojto	90:cb3d968589d8	1802	/*******************************************************************************
Kojto	90:cb3d968589d8	1803	* HW_LLWU_FILT2 - LLWU Pin Filter 2 register
Kojto	90:cb3d968589d8	1804	******************************************************************************/
Kojto	90:cb3d968589d8	1805
Kojto	90:cb3d968589d8	1806	/*!
Kojto	90:cb3d968589d8	1807	* @brief HW_LLWU_FILT2 - LLWU Pin Filter 2 register (RW)
Kojto	90:cb3d968589d8	1808	*
Kojto	90:cb3d968589d8	1809	* Reset value: 0x00U
Kojto	90:cb3d968589d8	1810	*
Kojto	90:cb3d968589d8	1811	* LLWU_FILT2 is a control and status register that is used to enable/disable
Kojto	90:cb3d968589d8	1812	* the digital filter 2 features for an external pin. This register is reset on
Kojto	90:cb3d968589d8	1813	* Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
Kojto	90:cb3d968589d8	1814	* unaffected by reset types that do not trigger Chip Reset not VLLS. See the
Kojto	90:cb3d968589d8	1815	* IntroductionInformation found here describes the registers of the Reset Control
Kojto	90:cb3d968589d8	1816	* Module (RCM). The RCM implements many of the reset functions for the chip. See
Kojto	90:cb3d968589d8	1817	* the chip's reset chapter for more information. details for more information.
Kojto	90:cb3d968589d8	1818	*/
Kojto	90:cb3d968589d8	1819	typedef union _hw_llwu_filt2
Kojto	90:cb3d968589d8	1820	{
Kojto	90:cb3d968589d8	1821	uint8_t U;
Kojto	90:cb3d968589d8	1822	struct _hw_llwu_filt2_bitfields
Kojto	90:cb3d968589d8	1823	{
Kojto	90:cb3d968589d8	1824	uint8_t FILTSEL : 4; /!< [3:0] Filter Pin Select /
Kojto	90:cb3d968589d8	1825	uint8_t RESERVED0 : 1; /!< [4] /
Kojto	90:cb3d968589d8	1826	uint8_t FILTE : 2; /!< [6:5] Digital Filter On External Pin /
Kojto	90:cb3d968589d8	1827	uint8_t FILTF : 1; /!< [7] Filter Detect Flag /
Kojto	90:cb3d968589d8	1828	} B;
Kojto	90:cb3d968589d8	1829	} hw_llwu_filt2_t;
Kojto	90:cb3d968589d8	1830
Kojto	90:cb3d968589d8	1831	/*!
Kojto	90:cb3d968589d8	1832	* @name Constants and macros for entire LLWU_FILT2 register
Kojto	90:cb3d968589d8	1833	*/
Kojto	90:cb3d968589d8	1834	/@{/
Kojto	90:cb3d968589d8	1835	#define HW_LLWU_FILT2_ADDR(x) ((x) + 0x9U)
Kojto	90:cb3d968589d8	1836
Kojto	90:cb3d968589d8	1837	#define HW_LLWU_FILT2(x) ((__IO hw_llwu_filt2_t ) HW_LLWU_FILT2_ADDR(x))
Kojto	90:cb3d968589d8	1838	#define HW_LLWU_FILT2_RD(x) (HW_LLWU_FILT2(x).U)
Kojto	90:cb3d968589d8	1839	#define HW_LLWU_FILT2_WR(x, v) (HW_LLWU_FILT2(x).U = (v))
Kojto	90:cb3d968589d8	1840	#define HW_LLWU_FILT2_SET(x, v) (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1841	#define HW_LLWU_FILT2_CLR(x, v) (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1842	#define HW_LLWU_FILT2_TOG(x, v) (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1843	/@}/
Kojto	90:cb3d968589d8	1844
Kojto	90:cb3d968589d8	1845	/*
Kojto	90:cb3d968589d8	1846	* Constants & macros for individual LLWU_FILT2 bitfields
Kojto	90:cb3d968589d8	1847	*/
Kojto	90:cb3d968589d8	1848
Kojto	90:cb3d968589d8	1849	/*!
Kojto	90:cb3d968589d8	1850	* @name Register LLWU_FILT2, field FILTSEL[3:0] (RW)
Kojto	90:cb3d968589d8	1851	*
Kojto	90:cb3d968589d8	1852	* Selects 1 out of the 16 wakeup pins to be muxed into the filter.
Kojto	90:cb3d968589d8	1853	*
Kojto	90:cb3d968589d8	1854	* Values:
Kojto	90:cb3d968589d8	1855	* - 0000 - Select LLWU_P0 for filter
Kojto	90:cb3d968589d8	1856	* - 1111 - Select LLWU_P15 for filter
Kojto	90:cb3d968589d8	1857	*/
Kojto	90:cb3d968589d8	1858	/@{/
Kojto	90:cb3d968589d8	1859	#define BP_LLWU_FILT2_FILTSEL (0U) /!< Bit position for LLWU_FILT2_FILTSEL. /
Kojto	90:cb3d968589d8	1860	#define BM_LLWU_FILT2_FILTSEL (0x0FU) /!< Bit mask for LLWU_FILT2_FILTSEL. /
Kojto	90:cb3d968589d8	1861	#define BS_LLWU_FILT2_FILTSEL (4U) /!< Bit field size in bits for LLWU_FILT2_FILTSEL. /
Kojto	90:cb3d968589d8	1862
Kojto	90:cb3d968589d8	1863	/! @brief Read current value of the LLWU_FILT2_FILTSEL field. /
Kojto	90:cb3d968589d8	1864	#define BR_LLWU_FILT2_FILTSEL(x) (HW_LLWU_FILT2(x).B.FILTSEL)
Kojto	90:cb3d968589d8	1865
Kojto	90:cb3d968589d8	1866	/! @brief Format value for bitfield LLWU_FILT2_FILTSEL. /
Kojto	90:cb3d968589d8	1867	#define BF_LLWU_FILT2_FILTSEL(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTSEL) & BM_LLWU_FILT2_FILTSEL)
Kojto	90:cb3d968589d8	1868
Kojto	90:cb3d968589d8	1869	/! @brief Set the FILTSEL field to a new value. /
Kojto	90:cb3d968589d8	1870	#define BW_LLWU_FILT2_FILTSEL(x, v) (HW_LLWU_FILT2_WR(x, (HW_LLWU_FILT2_RD(x) & ~BM_LLWU_FILT2_FILTSEL) \| BF_LLWU_FILT2_FILTSEL(v)))
Kojto	90:cb3d968589d8	1871	/@}/
Kojto	90:cb3d968589d8	1872
Kojto	90:cb3d968589d8	1873	/*!
Kojto	90:cb3d968589d8	1874	* @name Register LLWU_FILT2, field FILTE[6:5] (RW)
Kojto	90:cb3d968589d8	1875	*
Kojto	90:cb3d968589d8	1876	* Controls the digital filter options for the external pin detect.
Kojto	90:cb3d968589d8	1877	*
Kojto	90:cb3d968589d8	1878	* Values:
Kojto	90:cb3d968589d8	1879	* - 00 - Filter disabled
Kojto	90:cb3d968589d8	1880	* - 01 - Filter posedge detect enabled
Kojto	90:cb3d968589d8	1881	* - 10 - Filter negedge detect enabled
Kojto	90:cb3d968589d8	1882	* - 11 - Filter any edge detect enabled
Kojto	90:cb3d968589d8	1883	*/
Kojto	90:cb3d968589d8	1884	/@{/
Kojto	90:cb3d968589d8	1885	#define BP_LLWU_FILT2_FILTE (5U) /!< Bit position for LLWU_FILT2_FILTE. /
Kojto	90:cb3d968589d8	1886	#define BM_LLWU_FILT2_FILTE (0x60U) /!< Bit mask for LLWU_FILT2_FILTE. /
Kojto	90:cb3d968589d8	1887	#define BS_LLWU_FILT2_FILTE (2U) /!< Bit field size in bits for LLWU_FILT2_FILTE. /
Kojto	90:cb3d968589d8	1888
Kojto	90:cb3d968589d8	1889	/! @brief Read current value of the LLWU_FILT2_FILTE field. /
Kojto	90:cb3d968589d8	1890	#define BR_LLWU_FILT2_FILTE(x) (HW_LLWU_FILT2(x).B.FILTE)
Kojto	90:cb3d968589d8	1891
Kojto	90:cb3d968589d8	1892	/! @brief Format value for bitfield LLWU_FILT2_FILTE. /
Kojto	90:cb3d968589d8	1893	#define BF_LLWU_FILT2_FILTE(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTE) & BM_LLWU_FILT2_FILTE)
Kojto	90:cb3d968589d8	1894
Kojto	90:cb3d968589d8	1895	/! @brief Set the FILTE field to a new value. /
Kojto	90:cb3d968589d8	1896	#define BW_LLWU_FILT2_FILTE(x, v) (HW_LLWU_FILT2_WR(x, (HW_LLWU_FILT2_RD(x) & ~BM_LLWU_FILT2_FILTE) \| BF_LLWU_FILT2_FILTE(v)))
Kojto	90:cb3d968589d8	1897	/@}/
Kojto	90:cb3d968589d8	1898
Kojto	90:cb3d968589d8	1899	/*!
Kojto	90:cb3d968589d8	1900	* @name Register LLWU_FILT2, field FILTF[7] (W1C)
Kojto	90:cb3d968589d8	1901	*
Kojto	90:cb3d968589d8	1902	* Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
Kojto	90:cb3d968589d8	1903	* source of exiting a low-leakage power mode. To clear the flag write a one to
Kojto	90:cb3d968589d8	1904	* FILTF.
Kojto	90:cb3d968589d8	1905	*
Kojto	90:cb3d968589d8	1906	* Values:
Kojto	90:cb3d968589d8	1907	* - 0 - Pin Filter 2 was not a wakeup source
Kojto	90:cb3d968589d8	1908	* - 1 - Pin Filter 2 was a wakeup source
Kojto	90:cb3d968589d8	1909	*/
Kojto	90:cb3d968589d8	1910	/@{/
Kojto	90:cb3d968589d8	1911	#define BP_LLWU_FILT2_FILTF (7U) /!< Bit position for LLWU_FILT2_FILTF. /
Kojto	90:cb3d968589d8	1912	#define BM_LLWU_FILT2_FILTF (0x80U) /!< Bit mask for LLWU_FILT2_FILTF. /
Kojto	90:cb3d968589d8	1913	#define BS_LLWU_FILT2_FILTF (1U) /!< Bit field size in bits for LLWU_FILT2_FILTF. /
Kojto	90:cb3d968589d8	1914
Kojto	90:cb3d968589d8	1915	/! @brief Read current value of the LLWU_FILT2_FILTF field. /
Kojto	90:cb3d968589d8	1916	#define BR_LLWU_FILT2_FILTF(x) (BITBAND_ACCESS8(HW_LLWU_FILT2_ADDR(x), BP_LLWU_FILT2_FILTF))
Kojto	90:cb3d968589d8	1917
Kojto	90:cb3d968589d8	1918	/! @brief Format value for bitfield LLWU_FILT2_FILTF. /
Kojto	90:cb3d968589d8	1919	#define BF_LLWU_FILT2_FILTF(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTF) & BM_LLWU_FILT2_FILTF)
Kojto	90:cb3d968589d8	1920
Kojto	90:cb3d968589d8	1921	/! @brief Set the FILTF field to a new value. /
Kojto	90:cb3d968589d8	1922	#define BW_LLWU_FILT2_FILTF(x, v) (BITBAND_ACCESS8(HW_LLWU_FILT2_ADDR(x), BP_LLWU_FILT2_FILTF) = (v))
Kojto	90:cb3d968589d8	1923	/@}/
Kojto	90:cb3d968589d8	1924
Kojto	90:cb3d968589d8	1925	/*******************************************************************************
Kojto	90:cb3d968589d8	1926	* HW_LLWU_RST - LLWU Reset Enable register
Kojto	90:cb3d968589d8	1927	******************************************************************************/
Kojto	90:cb3d968589d8	1928
Kojto	90:cb3d968589d8	1929	/*!
Kojto	90:cb3d968589d8	1930	* @brief HW_LLWU_RST - LLWU Reset Enable register (RW)
Kojto	90:cb3d968589d8	1931	*
Kojto	90:cb3d968589d8	1932	* Reset value: 0x02U
Kojto	90:cb3d968589d8	1933	*
Kojto	90:cb3d968589d8	1934	* LLWU_RST is a control register that is used to enable/disable the digital
Kojto	90:cb3d968589d8	1935	* filter for the external pin detect and RESET pin. This register is reset on Chip
Kojto	90:cb3d968589d8	1936	* Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
Kojto	90:cb3d968589d8	1937	* unaffected by reset types that do not trigger Chip Reset not VLLS. See the
Kojto	90:cb3d968589d8	1938	* IntroductionInformation found here describes the registers of the Reset Control
Kojto	90:cb3d968589d8	1939	* Module (RCM). The RCM implements many of the reset functions for the chip. See the
Kojto	90:cb3d968589d8	1940	* chip's reset chapter for more information. details for more information.
Kojto	90:cb3d968589d8	1941	*/
Kojto	90:cb3d968589d8	1942	typedef union _hw_llwu_rst
Kojto	90:cb3d968589d8	1943	{
Kojto	90:cb3d968589d8	1944	uint8_t U;
Kojto	90:cb3d968589d8	1945	struct _hw_llwu_rst_bitfields
Kojto	90:cb3d968589d8	1946	{
Kojto	90:cb3d968589d8	1947	uint8_t RSTFILT : 1; /!< [0] Digital Filter On RESET Pin /
Kojto	90:cb3d968589d8	1948	uint8_t LLRSTE : 1; /!< [1] Low-Leakage Mode RESET Enable /
Kojto	90:cb3d968589d8	1949	uint8_t RESERVED0 : 6; /!< [7:2] /
Kojto	90:cb3d968589d8	1950	} B;
Kojto	90:cb3d968589d8	1951	} hw_llwu_rst_t;
Kojto	90:cb3d968589d8	1952
Kojto	90:cb3d968589d8	1953	/*!
Kojto	90:cb3d968589d8	1954	* @name Constants and macros for entire LLWU_RST register
Kojto	90:cb3d968589d8	1955	*/
Kojto	90:cb3d968589d8	1956	/@{/
Kojto	90:cb3d968589d8	1957	#define HW_LLWU_RST_ADDR(x) ((x) + 0xAU)
Kojto	90:cb3d968589d8	1958
Kojto	90:cb3d968589d8	1959	#define HW_LLWU_RST(x) ((__IO hw_llwu_rst_t ) HW_LLWU_RST_ADDR(x))
Kojto	90:cb3d968589d8	1960	#define HW_LLWU_RST_RD(x) (HW_LLWU_RST(x).U)
Kojto	90:cb3d968589d8	1961	#define HW_LLWU_RST_WR(x, v) (HW_LLWU_RST(x).U = (v))
Kojto	90:cb3d968589d8	1962	#define HW_LLWU_RST_SET(x, v) (HW_LLWU_RST_WR(x, HW_LLWU_RST_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1963	#define HW_LLWU_RST_CLR(x, v) (HW_LLWU_RST_WR(x, HW_LLWU_RST_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1964	#define HW_LLWU_RST_TOG(x, v) (HW_LLWU_RST_WR(x, HW_LLWU_RST_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1965	/@}/
Kojto	90:cb3d968589d8	1966
Kojto	90:cb3d968589d8	1967	/*
Kojto	90:cb3d968589d8	1968	* Constants & macros for individual LLWU_RST bitfields
Kojto	90:cb3d968589d8	1969	*/
Kojto	90:cb3d968589d8	1970
Kojto	90:cb3d968589d8	1971	/*!
Kojto	90:cb3d968589d8	1972	* @name Register LLWU_RST, field RSTFILT[0] (RW)
Kojto	90:cb3d968589d8	1973	*
Kojto	90:cb3d968589d8	1974	* Enables the digital filter for the RESET pin during LLS, VLLS3, VLLS2, or
Kojto	90:cb3d968589d8	1975	* VLLS1 modes.
Kojto	90:cb3d968589d8	1976	*
Kojto	90:cb3d968589d8	1977	* Values:
Kojto	90:cb3d968589d8	1978	* - 0 - Filter not enabled
Kojto	90:cb3d968589d8	1979	* - 1 - Filter enabled
Kojto	90:cb3d968589d8	1980	*/
Kojto	90:cb3d968589d8	1981	/@{/
Kojto	90:cb3d968589d8	1982	#define BP_LLWU_RST_RSTFILT (0U) /!< Bit position for LLWU_RST_RSTFILT. /
Kojto	90:cb3d968589d8	1983	#define BM_LLWU_RST_RSTFILT (0x01U) /!< Bit mask for LLWU_RST_RSTFILT. /
Kojto	90:cb3d968589d8	1984	#define BS_LLWU_RST_RSTFILT (1U) /!< Bit field size in bits for LLWU_RST_RSTFILT. /
Kojto	90:cb3d968589d8	1985
Kojto	90:cb3d968589d8	1986	/! @brief Read current value of the LLWU_RST_RSTFILT field. /
Kojto	90:cb3d968589d8	1987	#define BR_LLWU_RST_RSTFILT(x) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR(x), BP_LLWU_RST_RSTFILT))
Kojto	90:cb3d968589d8	1988
Kojto	90:cb3d968589d8	1989	/! @brief Format value for bitfield LLWU_RST_RSTFILT. /
Kojto	90:cb3d968589d8	1990	#define BF_LLWU_RST_RSTFILT(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_RST_RSTFILT) & BM_LLWU_RST_RSTFILT)
Kojto	90:cb3d968589d8	1991
Kojto	90:cb3d968589d8	1992	/! @brief Set the RSTFILT field to a new value. /
Kojto	90:cb3d968589d8	1993	#define BW_LLWU_RST_RSTFILT(x, v) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR(x), BP_LLWU_RST_RSTFILT) = (v))
Kojto	90:cb3d968589d8	1994	/@}/
Kojto	90:cb3d968589d8	1995
Kojto	90:cb3d968589d8	1996	/*!
Kojto	90:cb3d968589d8	1997	* @name Register LLWU_RST, field LLRSTE[1] (RW)
Kojto	90:cb3d968589d8	1998	*
Kojto	90:cb3d968589d8	1999	* This bit must be set to allow the device to be reset while in a low-leakage
Kojto	90:cb3d968589d8	2000	* power mode. On devices where Reset is not a dedicated pin, the RESET pin must
Kojto	90:cb3d968589d8	2001	* also be enabled in the explicit port mux control.
Kojto	90:cb3d968589d8	2002	*
Kojto	90:cb3d968589d8	2003	* Values:
Kojto	90:cb3d968589d8	2004	* - 0 - RESET pin not enabled as a leakage mode exit source
Kojto	90:cb3d968589d8	2005	* - 1 - RESET pin enabled as a low leakage mode exit source
Kojto	90:cb3d968589d8	2006	*/
Kojto	90:cb3d968589d8	2007	/@{/
Kojto	90:cb3d968589d8	2008	#define BP_LLWU_RST_LLRSTE (1U) /!< Bit position for LLWU_RST_LLRSTE. /
Kojto	90:cb3d968589d8	2009	#define BM_LLWU_RST_LLRSTE (0x02U) /!< Bit mask for LLWU_RST_LLRSTE. /
Kojto	90:cb3d968589d8	2010	#define BS_LLWU_RST_LLRSTE (1U) /!< Bit field size in bits for LLWU_RST_LLRSTE. /
Kojto	90:cb3d968589d8	2011
Kojto	90:cb3d968589d8	2012	/! @brief Read current value of the LLWU_RST_LLRSTE field. /
Kojto	90:cb3d968589d8	2013	#define BR_LLWU_RST_LLRSTE(x) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR(x), BP_LLWU_RST_LLRSTE))
Kojto	90:cb3d968589d8	2014
Kojto	90:cb3d968589d8	2015	/! @brief Format value for bitfield LLWU_RST_LLRSTE. /
Kojto	90:cb3d968589d8	2016	#define BF_LLWU_RST_LLRSTE(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_RST_LLRSTE) & BM_LLWU_RST_LLRSTE)
Kojto	90:cb3d968589d8	2017
Kojto	90:cb3d968589d8	2018	/! @brief Set the LLRSTE field to a new value. /
Kojto	90:cb3d968589d8	2019	#define BW_LLWU_RST_LLRSTE(x, v) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR(x), BP_LLWU_RST_LLRSTE) = (v))
Kojto	90:cb3d968589d8	2020	/@}/
Kojto	90:cb3d968589d8	2021
Kojto	90:cb3d968589d8	2022	/*******************************************************************************
Kojto	90:cb3d968589d8	2023	* hw_llwu_t - module struct
Kojto	90:cb3d968589d8	2024	******************************************************************************/
Kojto	90:cb3d968589d8	2025	/*!
Kojto	90:cb3d968589d8	2026	* @brief All LLWU module registers.
Kojto	90:cb3d968589d8	2027	*/
Kojto	90:cb3d968589d8	2028	#pragma pack(1)
Kojto	90:cb3d968589d8	2029	typedef struct _hw_llwu
Kojto	90:cb3d968589d8	2030	{
Kojto	90:cb3d968589d8	2031	__IO hw_llwu_pe1_t PE1; /!< [0x0] LLWU Pin Enable 1 register /
Kojto	90:cb3d968589d8	2032	__IO hw_llwu_pe2_t PE2; /!< [0x1] LLWU Pin Enable 2 register /
Kojto	90:cb3d968589d8	2033	__IO hw_llwu_pe3_t PE3; /!< [0x2] LLWU Pin Enable 3 register /
Kojto	90:cb3d968589d8	2034	__IO hw_llwu_pe4_t PE4; /!< [0x3] LLWU Pin Enable 4 register /
Kojto	90:cb3d968589d8	2035	__IO hw_llwu_me_t ME; /!< [0x4] LLWU Module Enable register /
Kojto	90:cb3d968589d8	2036	__IO hw_llwu_f1_t F1; /!< [0x5] LLWU Flag 1 register /
Kojto	90:cb3d968589d8	2037	__IO hw_llwu_f2_t F2; /!< [0x6] LLWU Flag 2 register /
Kojto	90:cb3d968589d8	2038	__I hw_llwu_f3_t F3; /!< [0x7] LLWU Flag 3 register /
Kojto	90:cb3d968589d8	2039	__IO hw_llwu_filt1_t FILT1; /!< [0x8] LLWU Pin Filter 1 register /
Kojto	90:cb3d968589d8	2040	__IO hw_llwu_filt2_t FILT2; /!< [0x9] LLWU Pin Filter 2 register /
Kojto	90:cb3d968589d8	2041	__IO hw_llwu_rst_t RST; /!< [0xA] LLWU Reset Enable register /
Kojto	90:cb3d968589d8	2042	} hw_llwu_t;
Kojto	90:cb3d968589d8	2043	#pragma pack()
Kojto	90:cb3d968589d8	2044
Kojto	90:cb3d968589d8	2045	/! @brief Macro to access all LLWU registers. /
Kojto	90:cb3d968589d8	2046	/! @param x LLWU module instance base address. /
Kojto	90:cb3d968589d8	2047	/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto	90:cb3d968589d8	2048	* use the '&' operator, like <code>&HW_LLWU(LLWU_BASE)</code>. */
Kojto	90:cb3d968589d8	2049	#define HW_LLWU(x) ((hw_llwu_t )(x))
Kojto	90:cb3d968589d8	2050
Kojto	90:cb3d968589d8	2051	#endif /* __HW_LLWU_REGISTERS_H__ */
Kojto	90:cb3d968589d8	2052	/* EOF */