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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_gpio.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:
Kojto
Date:
Wed Aug 05 13:16:35 2015 +0100
Revision:
104:b9ad9a133dc7
Parent:
90:cb3d968589d8 
Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /*
Kojto 90:cb3d968589d8 2 ** ###################################################################
Kojto 90:cb3d968589d8 3 ** Compilers: Keil ARM C/C++ Compiler
Kojto 90:cb3d968589d8 4 ** Freescale C/C++ for Embedded ARM
Kojto 90:cb3d968589d8 5 ** GNU C Compiler
Kojto 90:cb3d968589d8 6 ** IAR ANSI C/C++ Compiler for ARM
Kojto 90:cb3d968589d8 7 **
Kojto 90:cb3d968589d8 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto 90:cb3d968589d8 9 ** Version: rev. 2.5, 2014-02-10
Kojto 90:cb3d968589d8 10 ** Build: b140604
Kojto 90:cb3d968589d8 11 **
Kojto 90:cb3d968589d8 12 ** Abstract:
Kojto 90:cb3d968589d8 13 ** Extension to the CMSIS register access layer header.
Kojto 90:cb3d968589d8 14 **
Kojto 90:cb3d968589d8 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto 90:cb3d968589d8 16 ** All rights reserved.
Kojto 90:cb3d968589d8 17 **
Kojto 90:cb3d968589d8 18 ** Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 19 ** are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 20 **
Kojto 90:cb3d968589d8 21 ** o Redistributions of source code must retain the above copyright notice, this list
Kojto 90:cb3d968589d8 22 ** of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 23 **
Kojto 90:cb3d968589d8 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto 90:cb3d968589d8 25 ** list of conditions and the following disclaimer in the documentation and/or
Kojto 90:cb3d968589d8 26 ** other materials provided with the distribution.
Kojto 90:cb3d968589d8 27 **
Kojto 90:cb3d968589d8 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto 90:cb3d968589d8 29 ** contributors may be used to endorse or promote products derived from this
Kojto 90:cb3d968589d8 30 ** software without specific prior written permission.
Kojto 90:cb3d968589d8 31 **
Kojto 90:cb3d968589d8 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 90:cb3d968589d8 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 90:cb3d968589d8 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 90:cb3d968589d8 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 90:cb3d968589d8 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 90:cb3d968589d8 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 90:cb3d968589d8 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 90:cb3d968589d8 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 90:cb3d968589d8 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 42 **
Kojto 90:cb3d968589d8 43 ** http: www.freescale.com
Kojto 90:cb3d968589d8 44 ** mail: support@freescale.com
Kojto 90:cb3d968589d8 45 **
Kojto 90:cb3d968589d8 46 ** Revisions:
Kojto 90:cb3d968589d8 47 ** - rev. 1.0 (2013-08-12)
Kojto 90:cb3d968589d8 48 ** Initial version.
Kojto 90:cb3d968589d8 49 ** - rev. 2.0 (2013-10-29)
Kojto 90:cb3d968589d8 50 ** Register accessor macros added to the memory map.
Kojto 90:cb3d968589d8 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto 90:cb3d968589d8 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto 90:cb3d968589d8 53 ** System initialization updated.
Kojto 90:cb3d968589d8 54 ** MCG - registers updated.
Kojto 90:cb3d968589d8 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto 90:cb3d968589d8 56 ** - rev. 2.1 (2013-10-30)
Kojto 90:cb3d968589d8 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto 90:cb3d968589d8 58 ** - rev. 2.2 (2013-12-09)
Kojto 90:cb3d968589d8 59 ** DMA - EARS register removed.
Kojto 90:cb3d968589d8 60 ** AIPS0, AIPS1 - MPRA register updated.
Kojto 90:cb3d968589d8 61 ** - rev. 2.3 (2014-01-24)
Kojto 90:cb3d968589d8 62 ** Update according to reference manual rev. 2
Kojto 90:cb3d968589d8 63 ** ENET, MCG, MCM, SIM, USB - registers updated
Kojto 90:cb3d968589d8 64 ** - rev. 2.4 (2014-02-10)
Kojto 90:cb3d968589d8 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 67 ** - rev. 2.5 (2014-02-10)
Kojto 90:cb3d968589d8 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto 90:cb3d968589d8 71 **
Kojto 90:cb3d968589d8 72 ** ###################################################################
Kojto 90:cb3d968589d8 73 */
Kojto 90:cb3d968589d8 74
Kojto 90:cb3d968589d8 75 /*
Kojto 90:cb3d968589d8 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto 90:cb3d968589d8 77 *
Kojto 90:cb3d968589d8 78 * This file was generated automatically and any changes may be lost.
Kojto 90:cb3d968589d8 79 */
Kojto 90:cb3d968589d8 80 #ifndef __HW_GPIO_REGISTERS_H__
Kojto 90:cb3d968589d8 81 #define __HW_GPIO_REGISTERS_H__
Kojto 90:cb3d968589d8 82
Kojto 90:cb3d968589d8 83 #include "MK64F12.h"
Kojto 90:cb3d968589d8 84 #include "fsl_bitaccess.h"
Kojto 90:cb3d968589d8 85
Kojto 90:cb3d968589d8 86 /*
Kojto 90:cb3d968589d8 87 * MK64F12 GPIO
Kojto 90:cb3d968589d8 88 *
Kojto 90:cb3d968589d8 89 * General Purpose Input/Output
Kojto 90:cb3d968589d8 90 *
Kojto 90:cb3d968589d8 91 * Registers defined in this header file:
Kojto 90:cb3d968589d8 92 * - HW_GPIO_PDOR - Port Data Output Register
Kojto 90:cb3d968589d8 93 * - HW_GPIO_PSOR - Port Set Output Register
Kojto 90:cb3d968589d8 94 * - HW_GPIO_PCOR - Port Clear Output Register
Kojto 90:cb3d968589d8 95 * - HW_GPIO_PTOR - Port Toggle Output Register
Kojto 90:cb3d968589d8 96 * - HW_GPIO_PDIR - Port Data Input Register
Kojto 90:cb3d968589d8 97 * - HW_GPIO_PDDR - Port Data Direction Register
Kojto 90:cb3d968589d8 98 *
Kojto 90:cb3d968589d8 99 * - hw_gpio_t - Struct containing all module registers.
Kojto 90:cb3d968589d8 100 */
Kojto 90:cb3d968589d8 101
Kojto 90:cb3d968589d8 102 #define HW_GPIO_INSTANCE_COUNT (5U) /*!< Number of instances of the GPIO module. */
Kojto 90:cb3d968589d8 103 #define HW_GPIOA (0U) /*!< Instance number for GPIOA. */
Kojto 90:cb3d968589d8 104 #define HW_GPIOB (1U) /*!< Instance number for GPIOB. */
Kojto 90:cb3d968589d8 105 #define HW_GPIOC (2U) /*!< Instance number for GPIOC. */
Kojto 90:cb3d968589d8 106 #define HW_GPIOD (3U) /*!< Instance number for GPIOD. */
Kojto 90:cb3d968589d8 107 #define HW_GPIOE (4U) /*!< Instance number for GPIOE. */
Kojto 90:cb3d968589d8 108
Kojto 90:cb3d968589d8 109 /*******************************************************************************
Kojto 90:cb3d968589d8 110 * HW_GPIO_PDOR - Port Data Output Register
Kojto 90:cb3d968589d8 111 ******************************************************************************/
Kojto 90:cb3d968589d8 112
Kojto 90:cb3d968589d8 113 /*!
Kojto 90:cb3d968589d8 114 * @brief HW_GPIO_PDOR - Port Data Output Register (RW)
Kojto 90:cb3d968589d8 115 *
Kojto 90:cb3d968589d8 116 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 117 *
Kojto 90:cb3d968589d8 118 * This register configures the logic levels that are driven on each
Kojto 90:cb3d968589d8 119 * general-purpose output pins. Do not modify pin configuration registers associated with
Kojto 90:cb3d968589d8 120 * pins not available in your selected package. All unbonded pins not available in
Kojto 90:cb3d968589d8 121 * your package will default to DISABLE state for lowest power consumption.
Kojto 90:cb3d968589d8 122 */
Kojto 90:cb3d968589d8 123 typedef union _hw_gpio_pdor
Kojto 90:cb3d968589d8 124 {
Kojto 90:cb3d968589d8 125 uint32_t U;
Kojto 90:cb3d968589d8 126 struct _hw_gpio_pdor_bitfields
Kojto 90:cb3d968589d8 127 {
Kojto 90:cb3d968589d8 128 uint32_t PDO : 32; /*!< [31:0] Port Data Output */
Kojto 90:cb3d968589d8 129 } B;
Kojto 90:cb3d968589d8 130 } hw_gpio_pdor_t;
Kojto 90:cb3d968589d8 131
Kojto 90:cb3d968589d8 132 /*!
Kojto 90:cb3d968589d8 133 * @name Constants and macros for entire GPIO_PDOR register
Kojto 90:cb3d968589d8 134 */
Kojto 90:cb3d968589d8 135 /*@{*/
Kojto 90:cb3d968589d8 136 #define HW_GPIO_PDOR_ADDR(x) ((x) + 0x0U)
Kojto 90:cb3d968589d8 137
Kojto 90:cb3d968589d8 138 #define HW_GPIO_PDOR(x) (*(__IO hw_gpio_pdor_t *) HW_GPIO_PDOR_ADDR(x))
Kojto 90:cb3d968589d8 139 #define HW_GPIO_PDOR_RD(x) (HW_GPIO_PDOR(x).U)
Kojto 90:cb3d968589d8 140 #define HW_GPIO_PDOR_WR(x, v) (HW_GPIO_PDOR(x).U = (v))
Kojto 90:cb3d968589d8 141 #define HW_GPIO_PDOR_SET(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) | (v)))
Kojto 90:cb3d968589d8 142 #define HW_GPIO_PDOR_CLR(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 143 #define HW_GPIO_PDOR_TOG(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 144 /*@}*/
Kojto 90:cb3d968589d8 145
Kojto 90:cb3d968589d8 146 /*
Kojto 90:cb3d968589d8 147 * Constants & macros for individual GPIO_PDOR bitfields
Kojto 90:cb3d968589d8 148 */
Kojto 90:cb3d968589d8 149
Kojto 90:cb3d968589d8 150 /*!
Kojto 90:cb3d968589d8 151 * @name Register GPIO_PDOR, field PDO[31:0] (RW)
Kojto 90:cb3d968589d8 152 *
Kojto 90:cb3d968589d8 153 * Register bits for unbonded pins return a undefined value when read.
Kojto 90:cb3d968589d8 154 *
Kojto 90:cb3d968589d8 155 * Values:
Kojto 90:cb3d968589d8 156 * - 0 - Logic level 0 is driven on pin, provided pin is configured for
Kojto 90:cb3d968589d8 157 * general-purpose output.
Kojto 90:cb3d968589d8 158 * - 1 - Logic level 1 is driven on pin, provided pin is configured for
Kojto 90:cb3d968589d8 159 * general-purpose output.
Kojto 90:cb3d968589d8 160 */
Kojto 90:cb3d968589d8 161 /*@{*/
Kojto 90:cb3d968589d8 162 #define BP_GPIO_PDOR_PDO (0U) /*!< Bit position for GPIO_PDOR_PDO. */
Kojto 90:cb3d968589d8 163 #define BM_GPIO_PDOR_PDO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDOR_PDO. */
Kojto 90:cb3d968589d8 164 #define BS_GPIO_PDOR_PDO (32U) /*!< Bit field size in bits for GPIO_PDOR_PDO. */
Kojto 90:cb3d968589d8 165
Kojto 90:cb3d968589d8 166 /*! @brief Read current value of the GPIO_PDOR_PDO field. */
Kojto 90:cb3d968589d8 167 #define BR_GPIO_PDOR_PDO(x) (HW_GPIO_PDOR(x).U)
Kojto 90:cb3d968589d8 168
Kojto 90:cb3d968589d8 169 /*! @brief Format value for bitfield GPIO_PDOR_PDO. */
Kojto 90:cb3d968589d8 170 #define BF_GPIO_PDOR_PDO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PDOR_PDO) & BM_GPIO_PDOR_PDO)
Kojto 90:cb3d968589d8 171
Kojto 90:cb3d968589d8 172 /*! @brief Set the PDO field to a new value. */
Kojto 90:cb3d968589d8 173 #define BW_GPIO_PDOR_PDO(x, v) (HW_GPIO_PDOR_WR(x, v))
Kojto 90:cb3d968589d8 174 /*@}*/
Kojto 90:cb3d968589d8 175
Kojto 90:cb3d968589d8 176 /*******************************************************************************
Kojto 90:cb3d968589d8 177 * HW_GPIO_PSOR - Port Set Output Register
Kojto 90:cb3d968589d8 178 ******************************************************************************/
Kojto 90:cb3d968589d8 179
Kojto 90:cb3d968589d8 180 /*!
Kojto 90:cb3d968589d8 181 * @brief HW_GPIO_PSOR - Port Set Output Register (WORZ)
Kojto 90:cb3d968589d8 182 *
Kojto 90:cb3d968589d8 183 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 184 *
Kojto 90:cb3d968589d8 185 * This register configures whether to set the fields of the PDOR.
Kojto 90:cb3d968589d8 186 */
Kojto 90:cb3d968589d8 187 typedef union _hw_gpio_psor
Kojto 90:cb3d968589d8 188 {
Kojto 90:cb3d968589d8 189 uint32_t U;
Kojto 90:cb3d968589d8 190 struct _hw_gpio_psor_bitfields
Kojto 90:cb3d968589d8 191 {
Kojto 90:cb3d968589d8 192 uint32_t PTSO : 32; /*!< [31:0] Port Set Output */
Kojto 90:cb3d968589d8 193 } B;
Kojto 90:cb3d968589d8 194 } hw_gpio_psor_t;
Kojto 90:cb3d968589d8 195
Kojto 90:cb3d968589d8 196 /*!
Kojto 90:cb3d968589d8 197 * @name Constants and macros for entire GPIO_PSOR register
Kojto 90:cb3d968589d8 198 */
Kojto 90:cb3d968589d8 199 /*@{*/
Kojto 90:cb3d968589d8 200 #define HW_GPIO_PSOR_ADDR(x) ((x) + 0x4U)
Kojto 90:cb3d968589d8 201
Kojto 90:cb3d968589d8 202 #define HW_GPIO_PSOR(x) (*(__O hw_gpio_psor_t *) HW_GPIO_PSOR_ADDR(x))
Kojto 90:cb3d968589d8 203 #define HW_GPIO_PSOR_RD(x) (HW_GPIO_PSOR(x).U)
Kojto 90:cb3d968589d8 204 #define HW_GPIO_PSOR_WR(x, v) (HW_GPIO_PSOR(x).U = (v))
Kojto 90:cb3d968589d8 205 /*@}*/
Kojto 90:cb3d968589d8 206
Kojto 90:cb3d968589d8 207 /*
Kojto 90:cb3d968589d8 208 * Constants & macros for individual GPIO_PSOR bitfields
Kojto 90:cb3d968589d8 209 */
Kojto 90:cb3d968589d8 210
Kojto 90:cb3d968589d8 211 /*!
Kojto 90:cb3d968589d8 212 * @name Register GPIO_PSOR, field PTSO[31:0] (WORZ)
Kojto 90:cb3d968589d8 213 *
Kojto 90:cb3d968589d8 214 * Writing to this register will update the contents of the corresponding bit in
Kojto 90:cb3d968589d8 215 * the PDOR as follows:
Kojto 90:cb3d968589d8 216 *
Kojto 90:cb3d968589d8 217 * Values:
Kojto 90:cb3d968589d8 218 * - 0 - Corresponding bit in PDORn does not change.
Kojto 90:cb3d968589d8 219 * - 1 - Corresponding bit in PDORn is set to logic 1.
Kojto 90:cb3d968589d8 220 */
Kojto 90:cb3d968589d8 221 /*@{*/
Kojto 90:cb3d968589d8 222 #define BP_GPIO_PSOR_PTSO (0U) /*!< Bit position for GPIO_PSOR_PTSO. */
Kojto 90:cb3d968589d8 223 #define BM_GPIO_PSOR_PTSO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PSOR_PTSO. */
Kojto 90:cb3d968589d8 224 #define BS_GPIO_PSOR_PTSO (32U) /*!< Bit field size in bits for GPIO_PSOR_PTSO. */
Kojto 90:cb3d968589d8 225
Kojto 90:cb3d968589d8 226 /*! @brief Format value for bitfield GPIO_PSOR_PTSO. */
Kojto 90:cb3d968589d8 227 #define BF_GPIO_PSOR_PTSO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PSOR_PTSO) & BM_GPIO_PSOR_PTSO)
Kojto 90:cb3d968589d8 228
Kojto 90:cb3d968589d8 229 /*! @brief Set the PTSO field to a new value. */
Kojto 90:cb3d968589d8 230 #define BW_GPIO_PSOR_PTSO(x, v) (HW_GPIO_PSOR_WR(x, v))
Kojto 90:cb3d968589d8 231 /*@}*/
Kojto 90:cb3d968589d8 232
Kojto 90:cb3d968589d8 233 /*******************************************************************************
Kojto 90:cb3d968589d8 234 * HW_GPIO_PCOR - Port Clear Output Register
Kojto 90:cb3d968589d8 235 ******************************************************************************/
Kojto 90:cb3d968589d8 236
Kojto 90:cb3d968589d8 237 /*!
Kojto 90:cb3d968589d8 238 * @brief HW_GPIO_PCOR - Port Clear Output Register (WORZ)
Kojto 90:cb3d968589d8 239 *
Kojto 90:cb3d968589d8 240 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 241 *
Kojto 90:cb3d968589d8 242 * This register configures whether to clear the fields of PDOR.
Kojto 90:cb3d968589d8 243 */
Kojto 90:cb3d968589d8 244 typedef union _hw_gpio_pcor
Kojto 90:cb3d968589d8 245 {
Kojto 90:cb3d968589d8 246 uint32_t U;
Kojto 90:cb3d968589d8 247 struct _hw_gpio_pcor_bitfields
Kojto 90:cb3d968589d8 248 {
Kojto 90:cb3d968589d8 249 uint32_t PTCO : 32; /*!< [31:0] Port Clear Output */
Kojto 90:cb3d968589d8 250 } B;
Kojto 90:cb3d968589d8 251 } hw_gpio_pcor_t;
Kojto 90:cb3d968589d8 252
Kojto 90:cb3d968589d8 253 /*!
Kojto 90:cb3d968589d8 254 * @name Constants and macros for entire GPIO_PCOR register
Kojto 90:cb3d968589d8 255 */
Kojto 90:cb3d968589d8 256 /*@{*/
Kojto 90:cb3d968589d8 257 #define HW_GPIO_PCOR_ADDR(x) ((x) + 0x8U)
Kojto 90:cb3d968589d8 258
Kojto 90:cb3d968589d8 259 #define HW_GPIO_PCOR(x) (*(__O hw_gpio_pcor_t *) HW_GPIO_PCOR_ADDR(x))
Kojto 90:cb3d968589d8 260 #define HW_GPIO_PCOR_RD(x) (HW_GPIO_PCOR(x).U)
Kojto 90:cb3d968589d8 261 #define HW_GPIO_PCOR_WR(x, v) (HW_GPIO_PCOR(x).U = (v))
Kojto 90:cb3d968589d8 262 /*@}*/
Kojto 90:cb3d968589d8 263
Kojto 90:cb3d968589d8 264 /*
Kojto 90:cb3d968589d8 265 * Constants & macros for individual GPIO_PCOR bitfields
Kojto 90:cb3d968589d8 266 */
Kojto 90:cb3d968589d8 267
Kojto 90:cb3d968589d8 268 /*!
Kojto 90:cb3d968589d8 269 * @name Register GPIO_PCOR, field PTCO[31:0] (WORZ)
Kojto 90:cb3d968589d8 270 *
Kojto 90:cb3d968589d8 271 * Writing to this register will update the contents of the corresponding bit in
Kojto 90:cb3d968589d8 272 * the Port Data Output Register (PDOR) as follows:
Kojto 90:cb3d968589d8 273 *
Kojto 90:cb3d968589d8 274 * Values:
Kojto 90:cb3d968589d8 275 * - 0 - Corresponding bit in PDORn does not change.
Kojto 90:cb3d968589d8 276 * - 1 - Corresponding bit in PDORn is cleared to logic 0.
Kojto 90:cb3d968589d8 277 */
Kojto 90:cb3d968589d8 278 /*@{*/
Kojto 90:cb3d968589d8 279 #define BP_GPIO_PCOR_PTCO (0U) /*!< Bit position for GPIO_PCOR_PTCO. */
Kojto 90:cb3d968589d8 280 #define BM_GPIO_PCOR_PTCO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PCOR_PTCO. */
Kojto 90:cb3d968589d8 281 #define BS_GPIO_PCOR_PTCO (32U) /*!< Bit field size in bits for GPIO_PCOR_PTCO. */
Kojto 90:cb3d968589d8 282
Kojto 90:cb3d968589d8 283 /*! @brief Format value for bitfield GPIO_PCOR_PTCO. */
Kojto 90:cb3d968589d8 284 #define BF_GPIO_PCOR_PTCO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PCOR_PTCO) & BM_GPIO_PCOR_PTCO)
Kojto 90:cb3d968589d8 285
Kojto 90:cb3d968589d8 286 /*! @brief Set the PTCO field to a new value. */
Kojto 90:cb3d968589d8 287 #define BW_GPIO_PCOR_PTCO(x, v) (HW_GPIO_PCOR_WR(x, v))
Kojto 90:cb3d968589d8 288 /*@}*/
Kojto 90:cb3d968589d8 289
Kojto 90:cb3d968589d8 290 /*******************************************************************************
Kojto 90:cb3d968589d8 291 * HW_GPIO_PTOR - Port Toggle Output Register
Kojto 90:cb3d968589d8 292 ******************************************************************************/
Kojto 90:cb3d968589d8 293
Kojto 90:cb3d968589d8 294 /*!
Kojto 90:cb3d968589d8 295 * @brief HW_GPIO_PTOR - Port Toggle Output Register (WORZ)
Kojto 90:cb3d968589d8 296 *
Kojto 90:cb3d968589d8 297 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 298 */
Kojto 90:cb3d968589d8 299 typedef union _hw_gpio_ptor
Kojto 90:cb3d968589d8 300 {
Kojto 90:cb3d968589d8 301 uint32_t U;
Kojto 90:cb3d968589d8 302 struct _hw_gpio_ptor_bitfields
Kojto 90:cb3d968589d8 303 {
Kojto 90:cb3d968589d8 304 uint32_t PTTO : 32; /*!< [31:0] Port Toggle Output */
Kojto 90:cb3d968589d8 305 } B;
Kojto 90:cb3d968589d8 306 } hw_gpio_ptor_t;
Kojto 90:cb3d968589d8 307
Kojto 90:cb3d968589d8 308 /*!
Kojto 90:cb3d968589d8 309 * @name Constants and macros for entire GPIO_PTOR register
Kojto 90:cb3d968589d8 310 */
Kojto 90:cb3d968589d8 311 /*@{*/
Kojto 90:cb3d968589d8 312 #define HW_GPIO_PTOR_ADDR(x) ((x) + 0xCU)
Kojto 90:cb3d968589d8 313
Kojto 90:cb3d968589d8 314 #define HW_GPIO_PTOR(x) (*(__O hw_gpio_ptor_t *) HW_GPIO_PTOR_ADDR(x))
Kojto 90:cb3d968589d8 315 #define HW_GPIO_PTOR_RD(x) (HW_GPIO_PTOR(x).U)
Kojto 90:cb3d968589d8 316 #define HW_GPIO_PTOR_WR(x, v) (HW_GPIO_PTOR(x).U = (v))
Kojto 90:cb3d968589d8 317 /*@}*/
Kojto 90:cb3d968589d8 318
Kojto 90:cb3d968589d8 319 /*
Kojto 90:cb3d968589d8 320 * Constants & macros for individual GPIO_PTOR bitfields
Kojto 90:cb3d968589d8 321 */
Kojto 90:cb3d968589d8 322
Kojto 90:cb3d968589d8 323 /*!
Kojto 90:cb3d968589d8 324 * @name Register GPIO_PTOR, field PTTO[31:0] (WORZ)
Kojto 90:cb3d968589d8 325 *
Kojto 90:cb3d968589d8 326 * Writing to this register will update the contents of the corresponding bit in
Kojto 90:cb3d968589d8 327 * the PDOR as follows:
Kojto 90:cb3d968589d8 328 *
Kojto 90:cb3d968589d8 329 * Values:
Kojto 90:cb3d968589d8 330 * - 0 - Corresponding bit in PDORn does not change.
Kojto 90:cb3d968589d8 331 * - 1 - Corresponding bit in PDORn is set to the inverse of its existing logic
Kojto 90:cb3d968589d8 332 * state.
Kojto 90:cb3d968589d8 333 */
Kojto 90:cb3d968589d8 334 /*@{*/
Kojto 90:cb3d968589d8 335 #define BP_GPIO_PTOR_PTTO (0U) /*!< Bit position for GPIO_PTOR_PTTO. */
Kojto 90:cb3d968589d8 336 #define BM_GPIO_PTOR_PTTO (0xFFFFFFFFU) /*!< Bit mask for GPIO_PTOR_PTTO. */
Kojto 90:cb3d968589d8 337 #define BS_GPIO_PTOR_PTTO (32U) /*!< Bit field size in bits for GPIO_PTOR_PTTO. */
Kojto 90:cb3d968589d8 338
Kojto 90:cb3d968589d8 339 /*! @brief Format value for bitfield GPIO_PTOR_PTTO. */
Kojto 90:cb3d968589d8 340 #define BF_GPIO_PTOR_PTTO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PTOR_PTTO) & BM_GPIO_PTOR_PTTO)
Kojto 90:cb3d968589d8 341
Kojto 90:cb3d968589d8 342 /*! @brief Set the PTTO field to a new value. */
Kojto 90:cb3d968589d8 343 #define BW_GPIO_PTOR_PTTO(x, v) (HW_GPIO_PTOR_WR(x, v))
Kojto 90:cb3d968589d8 344 /*@}*/
Kojto 90:cb3d968589d8 345
Kojto 90:cb3d968589d8 346 /*******************************************************************************
Kojto 90:cb3d968589d8 347 * HW_GPIO_PDIR - Port Data Input Register
Kojto 90:cb3d968589d8 348 ******************************************************************************/
Kojto 90:cb3d968589d8 349
Kojto 90:cb3d968589d8 350 /*!
Kojto 90:cb3d968589d8 351 * @brief HW_GPIO_PDIR - Port Data Input Register (RO)
Kojto 90:cb3d968589d8 352 *
Kojto 90:cb3d968589d8 353 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 354 *
Kojto 90:cb3d968589d8 355 * Do not modify pin configuration registers associated with pins not available
Kojto 90:cb3d968589d8 356 * in your selected package. All unbonded pins not available in your package will
Kojto 90:cb3d968589d8 357 * default to DISABLE state for lowest power consumption.
Kojto 90:cb3d968589d8 358 */
Kojto 90:cb3d968589d8 359 typedef union _hw_gpio_pdir
Kojto 90:cb3d968589d8 360 {
Kojto 90:cb3d968589d8 361 uint32_t U;
Kojto 90:cb3d968589d8 362 struct _hw_gpio_pdir_bitfields
Kojto 90:cb3d968589d8 363 {
Kojto 90:cb3d968589d8 364 uint32_t PDI : 32; /*!< [31:0] Port Data Input */
Kojto 90:cb3d968589d8 365 } B;
Kojto 90:cb3d968589d8 366 } hw_gpio_pdir_t;
Kojto 90:cb3d968589d8 367
Kojto 90:cb3d968589d8 368 /*!
Kojto 90:cb3d968589d8 369 * @name Constants and macros for entire GPIO_PDIR register
Kojto 90:cb3d968589d8 370 */
Kojto 90:cb3d968589d8 371 /*@{*/
Kojto 90:cb3d968589d8 372 #define HW_GPIO_PDIR_ADDR(x) ((x) + 0x10U)
Kojto 90:cb3d968589d8 373
Kojto 90:cb3d968589d8 374 #define HW_GPIO_PDIR(x) (*(__I hw_gpio_pdir_t *) HW_GPIO_PDIR_ADDR(x))
Kojto 90:cb3d968589d8 375 #define HW_GPIO_PDIR_RD(x) (HW_GPIO_PDIR(x).U)
Kojto 90:cb3d968589d8 376 /*@}*/
Kojto 90:cb3d968589d8 377
Kojto 90:cb3d968589d8 378 /*
Kojto 90:cb3d968589d8 379 * Constants & macros for individual GPIO_PDIR bitfields
Kojto 90:cb3d968589d8 380 */
Kojto 90:cb3d968589d8 381
Kojto 90:cb3d968589d8 382 /*!
Kojto 90:cb3d968589d8 383 * @name Register GPIO_PDIR, field PDI[31:0] (RO)
Kojto 90:cb3d968589d8 384 *
Kojto 90:cb3d968589d8 385 * Reads 0 at the unimplemented pins for a particular device. Pins that are not
Kojto 90:cb3d968589d8 386 * configured for a digital function read 0. If the Port Control and Interrupt
Kojto 90:cb3d968589d8 387 * module is disabled, then the corresponding bit in PDIR does not update.
Kojto 90:cb3d968589d8 388 *
Kojto 90:cb3d968589d8 389 * Values:
Kojto 90:cb3d968589d8 390 * - 0 - Pin logic level is logic 0, or is not configured for use by digital
Kojto 90:cb3d968589d8 391 * function.
Kojto 90:cb3d968589d8 392 * - 1 - Pin logic level is logic 1.
Kojto 90:cb3d968589d8 393 */
Kojto 90:cb3d968589d8 394 /*@{*/
Kojto 90:cb3d968589d8 395 #define BP_GPIO_PDIR_PDI (0U) /*!< Bit position for GPIO_PDIR_PDI. */
Kojto 90:cb3d968589d8 396 #define BM_GPIO_PDIR_PDI (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDIR_PDI. */
Kojto 90:cb3d968589d8 397 #define BS_GPIO_PDIR_PDI (32U) /*!< Bit field size in bits for GPIO_PDIR_PDI. */
Kojto 90:cb3d968589d8 398
Kojto 90:cb3d968589d8 399 /*! @brief Read current value of the GPIO_PDIR_PDI field. */
Kojto 90:cb3d968589d8 400 #define BR_GPIO_PDIR_PDI(x) (HW_GPIO_PDIR(x).U)
Kojto 90:cb3d968589d8 401 /*@}*/
Kojto 90:cb3d968589d8 402
Kojto 90:cb3d968589d8 403 /*******************************************************************************
Kojto 90:cb3d968589d8 404 * HW_GPIO_PDDR - Port Data Direction Register
Kojto 90:cb3d968589d8 405 ******************************************************************************/
Kojto 90:cb3d968589d8 406
Kojto 90:cb3d968589d8 407 /*!
Kojto 90:cb3d968589d8 408 * @brief HW_GPIO_PDDR - Port Data Direction Register (RW)
Kojto 90:cb3d968589d8 409 *
Kojto 90:cb3d968589d8 410 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 411 *
Kojto 90:cb3d968589d8 412 * The PDDR configures the individual port pins for input or output.
Kojto 90:cb3d968589d8 413 */
Kojto 90:cb3d968589d8 414 typedef union _hw_gpio_pddr
Kojto 90:cb3d968589d8 415 {
Kojto 90:cb3d968589d8 416 uint32_t U;
Kojto 90:cb3d968589d8 417 struct _hw_gpio_pddr_bitfields
Kojto 90:cb3d968589d8 418 {
Kojto 90:cb3d968589d8 419 uint32_t PDD : 32; /*!< [31:0] Port Data Direction */
Kojto 90:cb3d968589d8 420 } B;
Kojto 90:cb3d968589d8 421 } hw_gpio_pddr_t;
Kojto 90:cb3d968589d8 422
Kojto 90:cb3d968589d8 423 /*!
Kojto 90:cb3d968589d8 424 * @name Constants and macros for entire GPIO_PDDR register
Kojto 90:cb3d968589d8 425 */
Kojto 90:cb3d968589d8 426 /*@{*/
Kojto 90:cb3d968589d8 427 #define HW_GPIO_PDDR_ADDR(x) ((x) + 0x14U)
Kojto 90:cb3d968589d8 428
Kojto 90:cb3d968589d8 429 #define HW_GPIO_PDDR(x) (*(__IO hw_gpio_pddr_t *) HW_GPIO_PDDR_ADDR(x))
Kojto 90:cb3d968589d8 430 #define HW_GPIO_PDDR_RD(x) (HW_GPIO_PDDR(x).U)
Kojto 90:cb3d968589d8 431 #define HW_GPIO_PDDR_WR(x, v) (HW_GPIO_PDDR(x).U = (v))
Kojto 90:cb3d968589d8 432 #define HW_GPIO_PDDR_SET(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) | (v)))
Kojto 90:cb3d968589d8 433 #define HW_GPIO_PDDR_CLR(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 434 #define HW_GPIO_PDDR_TOG(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 435 /*@}*/
Kojto 90:cb3d968589d8 436
Kojto 90:cb3d968589d8 437 /*
Kojto 90:cb3d968589d8 438 * Constants & macros for individual GPIO_PDDR bitfields
Kojto 90:cb3d968589d8 439 */
Kojto 90:cb3d968589d8 440
Kojto 90:cb3d968589d8 441 /*!
Kojto 90:cb3d968589d8 442 * @name Register GPIO_PDDR, field PDD[31:0] (RW)
Kojto 90:cb3d968589d8 443 *
Kojto 90:cb3d968589d8 444 * Configures individual port pins for input or output.
Kojto 90:cb3d968589d8 445 *
Kojto 90:cb3d968589d8 446 * Values:
Kojto 90:cb3d968589d8 447 * - 0 - Pin is configured as general-purpose input, for the GPIO function.
Kojto 90:cb3d968589d8 448 * - 1 - Pin is configured as general-purpose output, for the GPIO function.
Kojto 90:cb3d968589d8 449 */
Kojto 90:cb3d968589d8 450 /*@{*/
Kojto 90:cb3d968589d8 451 #define BP_GPIO_PDDR_PDD (0U) /*!< Bit position for GPIO_PDDR_PDD. */
Kojto 90:cb3d968589d8 452 #define BM_GPIO_PDDR_PDD (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDDR_PDD. */
Kojto 90:cb3d968589d8 453 #define BS_GPIO_PDDR_PDD (32U) /*!< Bit field size in bits for GPIO_PDDR_PDD. */
Kojto 90:cb3d968589d8 454
Kojto 90:cb3d968589d8 455 /*! @brief Read current value of the GPIO_PDDR_PDD field. */
Kojto 90:cb3d968589d8 456 #define BR_GPIO_PDDR_PDD(x) (HW_GPIO_PDDR(x).U)
Kojto 90:cb3d968589d8 457
Kojto 90:cb3d968589d8 458 /*! @brief Format value for bitfield GPIO_PDDR_PDD. */
Kojto 90:cb3d968589d8 459 #define BF_GPIO_PDDR_PDD(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PDDR_PDD) & BM_GPIO_PDDR_PDD)
Kojto 90:cb3d968589d8 460
Kojto 90:cb3d968589d8 461 /*! @brief Set the PDD field to a new value. */
Kojto 90:cb3d968589d8 462 #define BW_GPIO_PDDR_PDD(x, v) (HW_GPIO_PDDR_WR(x, v))
Kojto 90:cb3d968589d8 463 /*@}*/
Kojto 90:cb3d968589d8 464
Kojto 90:cb3d968589d8 465 /*******************************************************************************
Kojto 90:cb3d968589d8 466 * hw_gpio_t - module struct
Kojto 90:cb3d968589d8 467 ******************************************************************************/
Kojto 90:cb3d968589d8 468 /*!
Kojto 90:cb3d968589d8 469 * @brief All GPIO module registers.
Kojto 90:cb3d968589d8 470 */
Kojto 90:cb3d968589d8 471 #pragma pack(1)
Kojto 90:cb3d968589d8 472 typedef struct _hw_gpio
Kojto 90:cb3d968589d8 473 {
Kojto 90:cb3d968589d8 474 __IO hw_gpio_pdor_t PDOR; /*!< [0x0] Port Data Output Register */
Kojto 90:cb3d968589d8 475 __O hw_gpio_psor_t PSOR; /*!< [0x4] Port Set Output Register */
Kojto 90:cb3d968589d8 476 __O hw_gpio_pcor_t PCOR; /*!< [0x8] Port Clear Output Register */
Kojto 90:cb3d968589d8 477 __O hw_gpio_ptor_t PTOR; /*!< [0xC] Port Toggle Output Register */
Kojto 90:cb3d968589d8 478 __I hw_gpio_pdir_t PDIR; /*!< [0x10] Port Data Input Register */
Kojto 90:cb3d968589d8 479 __IO hw_gpio_pddr_t PDDR; /*!< [0x14] Port Data Direction Register */
Kojto 90:cb3d968589d8 480 } hw_gpio_t;
Kojto 90:cb3d968589d8 481 #pragma pack()
Kojto 90:cb3d968589d8 482
Kojto 90:cb3d968589d8 483 /*! @brief Macro to access all GPIO registers. */
Kojto 90:cb3d968589d8 484 /*! @param x GPIO module instance base address. */
Kojto 90:cb3d968589d8 485 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto 90:cb3d968589d8 486 * use the '&' operator, like <code>&HW_GPIO(GPIOA_BASE)</code>. */
Kojto 90:cb3d968589d8 487 #define HW_GPIO(x) (*(hw_gpio_t *)(x))
Kojto 90:cb3d968589d8 488
Kojto 90:cb3d968589d8 489 #endif /* __HW_GPIO_REGISTERS_H__ */
Kojto 90:cb3d968589d8 490 /* EOF */