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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_fb.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:
Kojto
Date:
Wed Aug 05 13:16:35 2015 +0100
Revision:
104:b9ad9a133dc7
Parent:
90:cb3d968589d8 
Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /*
Kojto 90:cb3d968589d8 2 ** ###################################################################
Kojto 90:cb3d968589d8 3 ** Compilers: Keil ARM C/C++ Compiler
Kojto 90:cb3d968589d8 4 ** Freescale C/C++ for Embedded ARM
Kojto 90:cb3d968589d8 5 ** GNU C Compiler
Kojto 90:cb3d968589d8 6 ** IAR ANSI C/C++ Compiler for ARM
Kojto 90:cb3d968589d8 7 **
Kojto 90:cb3d968589d8 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto 90:cb3d968589d8 9 ** Version: rev. 2.5, 2014-02-10
Kojto 90:cb3d968589d8 10 ** Build: b140604
Kojto 90:cb3d968589d8 11 **
Kojto 90:cb3d968589d8 12 ** Abstract:
Kojto 90:cb3d968589d8 13 ** Extension to the CMSIS register access layer header.
Kojto 90:cb3d968589d8 14 **
Kojto 90:cb3d968589d8 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto 90:cb3d968589d8 16 ** All rights reserved.
Kojto 90:cb3d968589d8 17 **
Kojto 90:cb3d968589d8 18 ** Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 19 ** are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 20 **
Kojto 90:cb3d968589d8 21 ** o Redistributions of source code must retain the above copyright notice, this list
Kojto 90:cb3d968589d8 22 ** of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 23 **
Kojto 90:cb3d968589d8 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto 90:cb3d968589d8 25 ** list of conditions and the following disclaimer in the documentation and/or
Kojto 90:cb3d968589d8 26 ** other materials provided with the distribution.
Kojto 90:cb3d968589d8 27 **
Kojto 90:cb3d968589d8 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto 90:cb3d968589d8 29 ** contributors may be used to endorse or promote products derived from this
Kojto 90:cb3d968589d8 30 ** software without specific prior written permission.
Kojto 90:cb3d968589d8 31 **
Kojto 90:cb3d968589d8 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 90:cb3d968589d8 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 90:cb3d968589d8 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 90:cb3d968589d8 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 90:cb3d968589d8 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 90:cb3d968589d8 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 90:cb3d968589d8 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 90:cb3d968589d8 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 90:cb3d968589d8 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 42 **
Kojto 90:cb3d968589d8 43 ** http: www.freescale.com
Kojto 90:cb3d968589d8 44 ** mail: support@freescale.com
Kojto 90:cb3d968589d8 45 **
Kojto 90:cb3d968589d8 46 ** Revisions:
Kojto 90:cb3d968589d8 47 ** - rev. 1.0 (2013-08-12)
Kojto 90:cb3d968589d8 48 ** Initial version.
Kojto 90:cb3d968589d8 49 ** - rev. 2.0 (2013-10-29)
Kojto 90:cb3d968589d8 50 ** Register accessor macros added to the memory map.
Kojto 90:cb3d968589d8 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto 90:cb3d968589d8 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto 90:cb3d968589d8 53 ** System initialization updated.
Kojto 90:cb3d968589d8 54 ** MCG - registers updated.
Kojto 90:cb3d968589d8 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto 90:cb3d968589d8 56 ** - rev. 2.1 (2013-10-30)
Kojto 90:cb3d968589d8 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto 90:cb3d968589d8 58 ** - rev. 2.2 (2013-12-09)
Kojto 90:cb3d968589d8 59 ** DMA - EARS register removed.
Kojto 90:cb3d968589d8 60 ** AIPS0, AIPS1 - MPRA register updated.
Kojto 90:cb3d968589d8 61 ** - rev. 2.3 (2014-01-24)
Kojto 90:cb3d968589d8 62 ** Update according to reference manual rev. 2
Kojto 90:cb3d968589d8 63 ** ENET, MCG, MCM, SIM, USB - registers updated
Kojto 90:cb3d968589d8 64 ** - rev. 2.4 (2014-02-10)
Kojto 90:cb3d968589d8 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 67 ** - rev. 2.5 (2014-02-10)
Kojto 90:cb3d968589d8 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto 90:cb3d968589d8 71 **
Kojto 90:cb3d968589d8 72 ** ###################################################################
Kojto 90:cb3d968589d8 73 */
Kojto 90:cb3d968589d8 74
Kojto 90:cb3d968589d8 75 /*
Kojto 90:cb3d968589d8 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto 90:cb3d968589d8 77 *
Kojto 90:cb3d968589d8 78 * This file was generated automatically and any changes may be lost.
Kojto 90:cb3d968589d8 79 */
Kojto 90:cb3d968589d8 80 #ifndef __HW_FB_REGISTERS_H__
Kojto 90:cb3d968589d8 81 #define __HW_FB_REGISTERS_H__
Kojto 90:cb3d968589d8 82
Kojto 90:cb3d968589d8 83 #include "MK64F12.h"
Kojto 90:cb3d968589d8 84 #include "fsl_bitaccess.h"
Kojto 90:cb3d968589d8 85
Kojto 90:cb3d968589d8 86 /*
Kojto 90:cb3d968589d8 87 * MK64F12 FB
Kojto 90:cb3d968589d8 88 *
Kojto 90:cb3d968589d8 89 * FlexBus external bus interface
Kojto 90:cb3d968589d8 90 *
Kojto 90:cb3d968589d8 91 * Registers defined in this header file:
Kojto 90:cb3d968589d8 92 * - HW_FB_CSARn - Chip Select Address Register
Kojto 90:cb3d968589d8 93 * - HW_FB_CSMRn - Chip Select Mask Register
Kojto 90:cb3d968589d8 94 * - HW_FB_CSCRn - Chip Select Control Register
Kojto 90:cb3d968589d8 95 * - HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
Kojto 90:cb3d968589d8 96 *
Kojto 90:cb3d968589d8 97 * - hw_fb_t - Struct containing all module registers.
Kojto 90:cb3d968589d8 98 */
Kojto 90:cb3d968589d8 99
Kojto 90:cb3d968589d8 100 #define HW_FB_INSTANCE_COUNT (1U) /*!< Number of instances of the FB module. */
Kojto 90:cb3d968589d8 101
Kojto 90:cb3d968589d8 102 /*******************************************************************************
Kojto 90:cb3d968589d8 103 * HW_FB_CSARn - Chip Select Address Register
Kojto 90:cb3d968589d8 104 ******************************************************************************/
Kojto 90:cb3d968589d8 105
Kojto 90:cb3d968589d8 106 /*!
Kojto 90:cb3d968589d8 107 * @brief HW_FB_CSARn - Chip Select Address Register (RW)
Kojto 90:cb3d968589d8 108 *
Kojto 90:cb3d968589d8 109 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 110 *
Kojto 90:cb3d968589d8 111 * Specifies the associated chip-select's base address.
Kojto 90:cb3d968589d8 112 */
Kojto 90:cb3d968589d8 113 typedef union _hw_fb_csarn
Kojto 90:cb3d968589d8 114 {
Kojto 90:cb3d968589d8 115 uint32_t U;
Kojto 90:cb3d968589d8 116 struct _hw_fb_csarn_bitfields
Kojto 90:cb3d968589d8 117 {
Kojto 90:cb3d968589d8 118 uint32_t RESERVED0 : 16; /*!< [15:0] */
Kojto 90:cb3d968589d8 119 uint32_t BA : 16; /*!< [31:16] Base Address */
Kojto 90:cb3d968589d8 120 } B;
Kojto 90:cb3d968589d8 121 } hw_fb_csarn_t;
Kojto 90:cb3d968589d8 122
Kojto 90:cb3d968589d8 123 /*!
Kojto 90:cb3d968589d8 124 * @name Constants and macros for entire FB_CSARn register
Kojto 90:cb3d968589d8 125 */
Kojto 90:cb3d968589d8 126 /*@{*/
Kojto 90:cb3d968589d8 127 #define HW_FB_CSARn_COUNT (6U)
Kojto 90:cb3d968589d8 128
Kojto 90:cb3d968589d8 129 #define HW_FB_CSARn_ADDR(x, n) ((x) + 0x0U + (0xCU * (n)))
Kojto 90:cb3d968589d8 130
Kojto 90:cb3d968589d8 131 #define HW_FB_CSARn(x, n) (*(__IO hw_fb_csarn_t *) HW_FB_CSARn_ADDR(x, n))
Kojto 90:cb3d968589d8 132 #define HW_FB_CSARn_RD(x, n) (HW_FB_CSARn(x, n).U)
Kojto 90:cb3d968589d8 133 #define HW_FB_CSARn_WR(x, n, v) (HW_FB_CSARn(x, n).U = (v))
Kojto 90:cb3d968589d8 134 #define HW_FB_CSARn_SET(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 135 #define HW_FB_CSARn_CLR(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 136 #define HW_FB_CSARn_TOG(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 137 /*@}*/
Kojto 90:cb3d968589d8 138
Kojto 90:cb3d968589d8 139 /*
Kojto 90:cb3d968589d8 140 * Constants & macros for individual FB_CSARn bitfields
Kojto 90:cb3d968589d8 141 */
Kojto 90:cb3d968589d8 142
Kojto 90:cb3d968589d8 143 /*!
Kojto 90:cb3d968589d8 144 * @name Register FB_CSARn, field BA[31:16] (RW)
Kojto 90:cb3d968589d8 145 *
Kojto 90:cb3d968589d8 146 * Defines the base address for memory dedicated to the associated chip-select.
Kojto 90:cb3d968589d8 147 * BA is compared to bits 31-16 on the internal address bus to determine if the
Kojto 90:cb3d968589d8 148 * associated chip-select's memory is being accessed. Because the FlexBus module
Kojto 90:cb3d968589d8 149 * is one of the slaves connected to the crossbar switch, it is only accessible
Kojto 90:cb3d968589d8 150 * within a certain memory range. See the chip memory map for the applicable
Kojto 90:cb3d968589d8 151 * FlexBus "expansion" address range for which the chip-selects can be active. Set the
Kojto 90:cb3d968589d8 152 * CSARn and CSMRn registers appropriately before accessing this region.
Kojto 90:cb3d968589d8 153 */
Kojto 90:cb3d968589d8 154 /*@{*/
Kojto 90:cb3d968589d8 155 #define BP_FB_CSARn_BA (16U) /*!< Bit position for FB_CSARn_BA. */
Kojto 90:cb3d968589d8 156 #define BM_FB_CSARn_BA (0xFFFF0000U) /*!< Bit mask for FB_CSARn_BA. */
Kojto 90:cb3d968589d8 157 #define BS_FB_CSARn_BA (16U) /*!< Bit field size in bits for FB_CSARn_BA. */
Kojto 90:cb3d968589d8 158
Kojto 90:cb3d968589d8 159 /*! @brief Read current value of the FB_CSARn_BA field. */
Kojto 90:cb3d968589d8 160 #define BR_FB_CSARn_BA(x, n) (HW_FB_CSARn(x, n).B.BA)
Kojto 90:cb3d968589d8 161
Kojto 90:cb3d968589d8 162 /*! @brief Format value for bitfield FB_CSARn_BA. */
Kojto 90:cb3d968589d8 163 #define BF_FB_CSARn_BA(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSARn_BA) & BM_FB_CSARn_BA)
Kojto 90:cb3d968589d8 164
Kojto 90:cb3d968589d8 165 /*! @brief Set the BA field to a new value. */
Kojto 90:cb3d968589d8 166 #define BW_FB_CSARn_BA(x, n, v) (HW_FB_CSARn_WR(x, n, (HW_FB_CSARn_RD(x, n) & ~BM_FB_CSARn_BA) | BF_FB_CSARn_BA(v)))
Kojto 90:cb3d968589d8 167 /*@}*/
Kojto 90:cb3d968589d8 168 /*******************************************************************************
Kojto 90:cb3d968589d8 169 * HW_FB_CSMRn - Chip Select Mask Register
Kojto 90:cb3d968589d8 170 ******************************************************************************/
Kojto 90:cb3d968589d8 171
Kojto 90:cb3d968589d8 172 /*!
Kojto 90:cb3d968589d8 173 * @brief HW_FB_CSMRn - Chip Select Mask Register (RW)
Kojto 90:cb3d968589d8 174 *
Kojto 90:cb3d968589d8 175 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 176 *
Kojto 90:cb3d968589d8 177 * Specifies the address mask and allowable access types for the associated
Kojto 90:cb3d968589d8 178 * chip-select.
Kojto 90:cb3d968589d8 179 */
Kojto 90:cb3d968589d8 180 typedef union _hw_fb_csmrn
Kojto 90:cb3d968589d8 181 {
Kojto 90:cb3d968589d8 182 uint32_t U;
Kojto 90:cb3d968589d8 183 struct _hw_fb_csmrn_bitfields
Kojto 90:cb3d968589d8 184 {
Kojto 90:cb3d968589d8 185 uint32_t V : 1; /*!< [0] Valid */
Kojto 90:cb3d968589d8 186 uint32_t RESERVED0 : 7; /*!< [7:1] */
Kojto 90:cb3d968589d8 187 uint32_t WP : 1; /*!< [8] Write Protect */
Kojto 90:cb3d968589d8 188 uint32_t RESERVED1 : 7; /*!< [15:9] */
Kojto 90:cb3d968589d8 189 uint32_t BAM : 16; /*!< [31:16] Base Address Mask */
Kojto 90:cb3d968589d8 190 } B;
Kojto 90:cb3d968589d8 191 } hw_fb_csmrn_t;
Kojto 90:cb3d968589d8 192
Kojto 90:cb3d968589d8 193 /*!
Kojto 90:cb3d968589d8 194 * @name Constants and macros for entire FB_CSMRn register
Kojto 90:cb3d968589d8 195 */
Kojto 90:cb3d968589d8 196 /*@{*/
Kojto 90:cb3d968589d8 197 #define HW_FB_CSMRn_COUNT (6U)
Kojto 90:cb3d968589d8 198
Kojto 90:cb3d968589d8 199 #define HW_FB_CSMRn_ADDR(x, n) ((x) + 0x4U + (0xCU * (n)))
Kojto 90:cb3d968589d8 200
Kojto 90:cb3d968589d8 201 #define HW_FB_CSMRn(x, n) (*(__IO hw_fb_csmrn_t *) HW_FB_CSMRn_ADDR(x, n))
Kojto 90:cb3d968589d8 202 #define HW_FB_CSMRn_RD(x, n) (HW_FB_CSMRn(x, n).U)
Kojto 90:cb3d968589d8 203 #define HW_FB_CSMRn_WR(x, n, v) (HW_FB_CSMRn(x, n).U = (v))
Kojto 90:cb3d968589d8 204 #define HW_FB_CSMRn_SET(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 205 #define HW_FB_CSMRn_CLR(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 206 #define HW_FB_CSMRn_TOG(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 207 /*@}*/
Kojto 90:cb3d968589d8 208
Kojto 90:cb3d968589d8 209 /*
Kojto 90:cb3d968589d8 210 * Constants & macros for individual FB_CSMRn bitfields
Kojto 90:cb3d968589d8 211 */
Kojto 90:cb3d968589d8 212
Kojto 90:cb3d968589d8 213 /*!
Kojto 90:cb3d968589d8 214 * @name Register FB_CSMRn, field V[0] (RW)
Kojto 90:cb3d968589d8 215 *
Kojto 90:cb3d968589d8 216 * Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid.
Kojto 90:cb3d968589d8 217 * Programmed chip-selects do not assert until the V bit is 1b (except for
Kojto 90:cb3d968589d8 218 * FB_CS0, which acts as the global chip-select). At reset, FB_CS0 will fire for any
Kojto 90:cb3d968589d8 219 * access to the FlexBus memory region. CSMR0[V] must be set as part of the chip
Kojto 90:cb3d968589d8 220 * select initialization sequence to allow other chip selects to function as
Kojto 90:cb3d968589d8 221 * programmed.
Kojto 90:cb3d968589d8 222 *
Kojto 90:cb3d968589d8 223 * Values:
Kojto 90:cb3d968589d8 224 * - 0 - Chip-select is invalid.
Kojto 90:cb3d968589d8 225 * - 1 - Chip-select is valid.
Kojto 90:cb3d968589d8 226 */
Kojto 90:cb3d968589d8 227 /*@{*/
Kojto 90:cb3d968589d8 228 #define BP_FB_CSMRn_V (0U) /*!< Bit position for FB_CSMRn_V. */
Kojto 90:cb3d968589d8 229 #define BM_FB_CSMRn_V (0x00000001U) /*!< Bit mask for FB_CSMRn_V. */
Kojto 90:cb3d968589d8 230 #define BS_FB_CSMRn_V (1U) /*!< Bit field size in bits for FB_CSMRn_V. */
Kojto 90:cb3d968589d8 231
Kojto 90:cb3d968589d8 232 /*! @brief Read current value of the FB_CSMRn_V field. */
Kojto 90:cb3d968589d8 233 #define BR_FB_CSMRn_V(x, n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_V))
Kojto 90:cb3d968589d8 234
Kojto 90:cb3d968589d8 235 /*! @brief Format value for bitfield FB_CSMRn_V. */
Kojto 90:cb3d968589d8 236 #define BF_FB_CSMRn_V(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_V) & BM_FB_CSMRn_V)
Kojto 90:cb3d968589d8 237
Kojto 90:cb3d968589d8 238 /*! @brief Set the V field to a new value. */
Kojto 90:cb3d968589d8 239 #define BW_FB_CSMRn_V(x, n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_V) = (v))
Kojto 90:cb3d968589d8 240 /*@}*/
Kojto 90:cb3d968589d8 241
Kojto 90:cb3d968589d8 242 /*!
Kojto 90:cb3d968589d8 243 * @name Register FB_CSMRn, field WP[8] (RW)
Kojto 90:cb3d968589d8 244 *
Kojto 90:cb3d968589d8 245 * Controls write accesses to the address range in the corresponding CSAR.
Kojto 90:cb3d968589d8 246 *
Kojto 90:cb3d968589d8 247 * Values:
Kojto 90:cb3d968589d8 248 * - 0 - Write accesses are allowed.
Kojto 90:cb3d968589d8 249 * - 1 - Write accesses are not allowed. Attempting to write to the range of
Kojto 90:cb3d968589d8 250 * addresses for which the WP bit is set results in a bus error termination of
Kojto 90:cb3d968589d8 251 * the internal cycle and no external cycle.
Kojto 90:cb3d968589d8 252 */
Kojto 90:cb3d968589d8 253 /*@{*/
Kojto 90:cb3d968589d8 254 #define BP_FB_CSMRn_WP (8U) /*!< Bit position for FB_CSMRn_WP. */
Kojto 90:cb3d968589d8 255 #define BM_FB_CSMRn_WP (0x00000100U) /*!< Bit mask for FB_CSMRn_WP. */
Kojto 90:cb3d968589d8 256 #define BS_FB_CSMRn_WP (1U) /*!< Bit field size in bits for FB_CSMRn_WP. */
Kojto 90:cb3d968589d8 257
Kojto 90:cb3d968589d8 258 /*! @brief Read current value of the FB_CSMRn_WP field. */
Kojto 90:cb3d968589d8 259 #define BR_FB_CSMRn_WP(x, n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_WP))
Kojto 90:cb3d968589d8 260
Kojto 90:cb3d968589d8 261 /*! @brief Format value for bitfield FB_CSMRn_WP. */
Kojto 90:cb3d968589d8 262 #define BF_FB_CSMRn_WP(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_WP) & BM_FB_CSMRn_WP)
Kojto 90:cb3d968589d8 263
Kojto 90:cb3d968589d8 264 /*! @brief Set the WP field to a new value. */
Kojto 90:cb3d968589d8 265 #define BW_FB_CSMRn_WP(x, n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_WP) = (v))
Kojto 90:cb3d968589d8 266 /*@}*/
Kojto 90:cb3d968589d8 267
Kojto 90:cb3d968589d8 268 /*!
Kojto 90:cb3d968589d8 269 * @name Register FB_CSMRn, field BAM[31:16] (RW)
Kojto 90:cb3d968589d8 270 *
Kojto 90:cb3d968589d8 271 * Defines the associated chip-select's block size by masking address bits.
Kojto 90:cb3d968589d8 272 *
Kojto 90:cb3d968589d8 273 * Values:
Kojto 90:cb3d968589d8 274 * - 0 - The corresponding address bit in CSAR is used in the chip-select decode.
Kojto 90:cb3d968589d8 275 * - 1 - The corresponding address bit in CSAR is a don't care in the
Kojto 90:cb3d968589d8 276 * chip-select decode.
Kojto 90:cb3d968589d8 277 */
Kojto 90:cb3d968589d8 278 /*@{*/
Kojto 90:cb3d968589d8 279 #define BP_FB_CSMRn_BAM (16U) /*!< Bit position for FB_CSMRn_BAM. */
Kojto 90:cb3d968589d8 280 #define BM_FB_CSMRn_BAM (0xFFFF0000U) /*!< Bit mask for FB_CSMRn_BAM. */
Kojto 90:cb3d968589d8 281 #define BS_FB_CSMRn_BAM (16U) /*!< Bit field size in bits for FB_CSMRn_BAM. */
Kojto 90:cb3d968589d8 282
Kojto 90:cb3d968589d8 283 /*! @brief Read current value of the FB_CSMRn_BAM field. */
Kojto 90:cb3d968589d8 284 #define BR_FB_CSMRn_BAM(x, n) (HW_FB_CSMRn(x, n).B.BAM)
Kojto 90:cb3d968589d8 285
Kojto 90:cb3d968589d8 286 /*! @brief Format value for bitfield FB_CSMRn_BAM. */
Kojto 90:cb3d968589d8 287 #define BF_FB_CSMRn_BAM(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_BAM) & BM_FB_CSMRn_BAM)
Kojto 90:cb3d968589d8 288
Kojto 90:cb3d968589d8 289 /*! @brief Set the BAM field to a new value. */
Kojto 90:cb3d968589d8 290 #define BW_FB_CSMRn_BAM(x, n, v) (HW_FB_CSMRn_WR(x, n, (HW_FB_CSMRn_RD(x, n) & ~BM_FB_CSMRn_BAM) | BF_FB_CSMRn_BAM(v)))
Kojto 90:cb3d968589d8 291 /*@}*/
Kojto 90:cb3d968589d8 292 /*******************************************************************************
Kojto 90:cb3d968589d8 293 * HW_FB_CSCRn - Chip Select Control Register
Kojto 90:cb3d968589d8 294 ******************************************************************************/
Kojto 90:cb3d968589d8 295
Kojto 90:cb3d968589d8 296 /*!
Kojto 90:cb3d968589d8 297 * @brief HW_FB_CSCRn - Chip Select Control Register (RW)
Kojto 90:cb3d968589d8 298 *
Kojto 90:cb3d968589d8 299 * Reset value: 0x003FFC00U
Kojto 90:cb3d968589d8 300 *
Kojto 90:cb3d968589d8 301 * Controls the auto-acknowledge, address setup and hold times, port size, burst
Kojto 90:cb3d968589d8 302 * capability, and number of wait states for the associated chip select. To
Kojto 90:cb3d968589d8 303 * support the global chip-select (FB_CS0), the CSCR0 reset values differ from the
Kojto 90:cb3d968589d8 304 * other CSCRs. The reset value of CSCR0 is as follows: Bits 31-24 are 0b Bit 23-3
Kojto 90:cb3d968589d8 305 * are chip-dependent Bits 3-0 are 0b See the chip configuration details for your
Kojto 90:cb3d968589d8 306 * particular chip for information on the exact CSCR0 reset value.
Kojto 90:cb3d968589d8 307 */
Kojto 90:cb3d968589d8 308 typedef union _hw_fb_cscrn
Kojto 90:cb3d968589d8 309 {
Kojto 90:cb3d968589d8 310 uint32_t U;
Kojto 90:cb3d968589d8 311 struct _hw_fb_cscrn_bitfields
Kojto 90:cb3d968589d8 312 {
Kojto 90:cb3d968589d8 313 uint32_t RESERVED0 : 3; /*!< [2:0] */
Kojto 90:cb3d968589d8 314 uint32_t BSTW : 1; /*!< [3] Burst-Write Enable */
Kojto 90:cb3d968589d8 315 uint32_t BSTR : 1; /*!< [4] Burst-Read Enable */
Kojto 90:cb3d968589d8 316 uint32_t BEM : 1; /*!< [5] Byte-Enable Mode */
Kojto 90:cb3d968589d8 317 uint32_t PS : 2; /*!< [7:6] Port Size */
Kojto 90:cb3d968589d8 318 uint32_t AA : 1; /*!< [8] Auto-Acknowledge Enable */
Kojto 90:cb3d968589d8 319 uint32_t BLS : 1; /*!< [9] Byte-Lane Shift */
Kojto 90:cb3d968589d8 320 uint32_t WS : 6; /*!< [15:10] Wait States */
Kojto 90:cb3d968589d8 321 uint32_t WRAH : 2; /*!< [17:16] Write Address Hold or Deselect */
Kojto 90:cb3d968589d8 322 uint32_t RDAH : 2; /*!< [19:18] Read Address Hold or Deselect */
Kojto 90:cb3d968589d8 323 uint32_t ASET : 2; /*!< [21:20] Address Setup */
Kojto 90:cb3d968589d8 324 uint32_t EXTS : 1; /*!< [22] */
Kojto 90:cb3d968589d8 325 uint32_t SWSEN : 1; /*!< [23] Secondary Wait State Enable */
Kojto 90:cb3d968589d8 326 uint32_t RESERVED1 : 2; /*!< [25:24] */
Kojto 90:cb3d968589d8 327 uint32_t SWS : 6; /*!< [31:26] Secondary Wait States */
Kojto 90:cb3d968589d8 328 } B;
Kojto 90:cb3d968589d8 329 } hw_fb_cscrn_t;
Kojto 90:cb3d968589d8 330
Kojto 90:cb3d968589d8 331 /*!
Kojto 90:cb3d968589d8 332 * @name Constants and macros for entire FB_CSCRn register
Kojto 90:cb3d968589d8 333 */
Kojto 90:cb3d968589d8 334 /*@{*/
Kojto 90:cb3d968589d8 335 #define HW_FB_CSCRn_COUNT (6U)
Kojto 90:cb3d968589d8 336
Kojto 90:cb3d968589d8 337 #define HW_FB_CSCRn_ADDR(x, n) ((x) + 0x8U + (0xCU * (n)))
Kojto 90:cb3d968589d8 338
Kojto 90:cb3d968589d8 339 #define HW_FB_CSCRn(x, n) (*(__IO hw_fb_cscrn_t *) HW_FB_CSCRn_ADDR(x, n))
Kojto 90:cb3d968589d8 340 #define HW_FB_CSCRn_RD(x, n) (HW_FB_CSCRn(x, n).U)
Kojto 90:cb3d968589d8 341 #define HW_FB_CSCRn_WR(x, n, v) (HW_FB_CSCRn(x, n).U = (v))
Kojto 90:cb3d968589d8 342 #define HW_FB_CSCRn_SET(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 343 #define HW_FB_CSCRn_CLR(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 344 #define HW_FB_CSCRn_TOG(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 345 /*@}*/
Kojto 90:cb3d968589d8 346
Kojto 90:cb3d968589d8 347 /*
Kojto 90:cb3d968589d8 348 * Constants & macros for individual FB_CSCRn bitfields
Kojto 90:cb3d968589d8 349 */
Kojto 90:cb3d968589d8 350
Kojto 90:cb3d968589d8 351 /*!
Kojto 90:cb3d968589d8 352 * @name Register FB_CSCRn, field BSTW[3] (RW)
Kojto 90:cb3d968589d8 353 *
Kojto 90:cb3d968589d8 354 * Specifies whether burst writes are enabled for memory associated with each
Kojto 90:cb3d968589d8 355 * chip select.
Kojto 90:cb3d968589d8 356 *
Kojto 90:cb3d968589d8 357 * Values:
Kojto 90:cb3d968589d8 358 * - 0 - Disabled. Data exceeding the specified port size is broken into
Kojto 90:cb3d968589d8 359 * individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit
Kojto 90:cb3d968589d8 360 * port takes four byte writes.
Kojto 90:cb3d968589d8 361 * - 1 - Enabled. Enables burst write of data larger than the specified port
Kojto 90:cb3d968589d8 362 * size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit
Kojto 90:cb3d968589d8 363 * ports, and line writes to 8-, 16-, and 32-bit ports.
Kojto 90:cb3d968589d8 364 */
Kojto 90:cb3d968589d8 365 /*@{*/
Kojto 90:cb3d968589d8 366 #define BP_FB_CSCRn_BSTW (3U) /*!< Bit position for FB_CSCRn_BSTW. */
Kojto 90:cb3d968589d8 367 #define BM_FB_CSCRn_BSTW (0x00000008U) /*!< Bit mask for FB_CSCRn_BSTW. */
Kojto 90:cb3d968589d8 368 #define BS_FB_CSCRn_BSTW (1U) /*!< Bit field size in bits for FB_CSCRn_BSTW. */
Kojto 90:cb3d968589d8 369
Kojto 90:cb3d968589d8 370 /*! @brief Read current value of the FB_CSCRn_BSTW field. */
Kojto 90:cb3d968589d8 371 #define BR_FB_CSCRn_BSTW(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTW))
Kojto 90:cb3d968589d8 372
Kojto 90:cb3d968589d8 373 /*! @brief Format value for bitfield FB_CSCRn_BSTW. */
Kojto 90:cb3d968589d8 374 #define BF_FB_CSCRn_BSTW(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BSTW) & BM_FB_CSCRn_BSTW)
Kojto 90:cb3d968589d8 375
Kojto 90:cb3d968589d8 376 /*! @brief Set the BSTW field to a new value. */
Kojto 90:cb3d968589d8 377 #define BW_FB_CSCRn_BSTW(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTW) = (v))
Kojto 90:cb3d968589d8 378 /*@}*/
Kojto 90:cb3d968589d8 379
Kojto 90:cb3d968589d8 380 /*!
Kojto 90:cb3d968589d8 381 * @name Register FB_CSCRn, field BSTR[4] (RW)
Kojto 90:cb3d968589d8 382 *
Kojto 90:cb3d968589d8 383 * Specifies whether burst reads are enabled for memory associated with each
Kojto 90:cb3d968589d8 384 * chip select.
Kojto 90:cb3d968589d8 385 *
Kojto 90:cb3d968589d8 386 * Values:
Kojto 90:cb3d968589d8 387 * - 0 - Disabled. Data exceeding the specified port size is broken into
Kojto 90:cb3d968589d8 388 * individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit
Kojto 90:cb3d968589d8 389 * port is broken into four 8-bit reads.
Kojto 90:cb3d968589d8 390 * - 1 - Enabled. Enables data burst reads larger than the specified port size,
Kojto 90:cb3d968589d8 391 * including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit
Kojto 90:cb3d968589d8 392 * ports, and line reads from 8-, 16-, and 32-bit ports.
Kojto 90:cb3d968589d8 393 */
Kojto 90:cb3d968589d8 394 /*@{*/
Kojto 90:cb3d968589d8 395 #define BP_FB_CSCRn_BSTR (4U) /*!< Bit position for FB_CSCRn_BSTR. */
Kojto 90:cb3d968589d8 396 #define BM_FB_CSCRn_BSTR (0x00000010U) /*!< Bit mask for FB_CSCRn_BSTR. */
Kojto 90:cb3d968589d8 397 #define BS_FB_CSCRn_BSTR (1U) /*!< Bit field size in bits for FB_CSCRn_BSTR. */
Kojto 90:cb3d968589d8 398
Kojto 90:cb3d968589d8 399 /*! @brief Read current value of the FB_CSCRn_BSTR field. */
Kojto 90:cb3d968589d8 400 #define BR_FB_CSCRn_BSTR(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTR))
Kojto 90:cb3d968589d8 401
Kojto 90:cb3d968589d8 402 /*! @brief Format value for bitfield FB_CSCRn_BSTR. */
Kojto 90:cb3d968589d8 403 #define BF_FB_CSCRn_BSTR(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BSTR) & BM_FB_CSCRn_BSTR)
Kojto 90:cb3d968589d8 404
Kojto 90:cb3d968589d8 405 /*! @brief Set the BSTR field to a new value. */
Kojto 90:cb3d968589d8 406 #define BW_FB_CSCRn_BSTR(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTR) = (v))
Kojto 90:cb3d968589d8 407 /*@}*/
Kojto 90:cb3d968589d8 408
Kojto 90:cb3d968589d8 409 /*!
Kojto 90:cb3d968589d8 410 * @name Register FB_CSCRn, field BEM[5] (RW)
Kojto 90:cb3d968589d8 411 *
Kojto 90:cb3d968589d8 412 * Specifies whether the corresponding FB_BE is asserted for read accesses.
Kojto 90:cb3d968589d8 413 * Certain memories have byte enables that must be asserted during reads and writes.
Kojto 90:cb3d968589d8 414 * Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode
Kojto 90:cb3d968589d8 415 * of byte enable support for these SRAMs.
Kojto 90:cb3d968589d8 416 *
Kojto 90:cb3d968589d8 417 * Values:
Kojto 90:cb3d968589d8 418 * - 0 - FB_BE is asserted for data write only.
Kojto 90:cb3d968589d8 419 * - 1 - FB_BE is asserted for data read and write accesses.
Kojto 90:cb3d968589d8 420 */
Kojto 90:cb3d968589d8 421 /*@{*/
Kojto 90:cb3d968589d8 422 #define BP_FB_CSCRn_BEM (5U) /*!< Bit position for FB_CSCRn_BEM. */
Kojto 90:cb3d968589d8 423 #define BM_FB_CSCRn_BEM (0x00000020U) /*!< Bit mask for FB_CSCRn_BEM. */
Kojto 90:cb3d968589d8 424 #define BS_FB_CSCRn_BEM (1U) /*!< Bit field size in bits for FB_CSCRn_BEM. */
Kojto 90:cb3d968589d8 425
Kojto 90:cb3d968589d8 426 /*! @brief Read current value of the FB_CSCRn_BEM field. */
Kojto 90:cb3d968589d8 427 #define BR_FB_CSCRn_BEM(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BEM))
Kojto 90:cb3d968589d8 428
Kojto 90:cb3d968589d8 429 /*! @brief Format value for bitfield FB_CSCRn_BEM. */
Kojto 90:cb3d968589d8 430 #define BF_FB_CSCRn_BEM(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BEM) & BM_FB_CSCRn_BEM)
Kojto 90:cb3d968589d8 431
Kojto 90:cb3d968589d8 432 /*! @brief Set the BEM field to a new value. */
Kojto 90:cb3d968589d8 433 #define BW_FB_CSCRn_BEM(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BEM) = (v))
Kojto 90:cb3d968589d8 434 /*@}*/
Kojto 90:cb3d968589d8 435
Kojto 90:cb3d968589d8 436 /*!
Kojto 90:cb3d968589d8 437 * @name Register FB_CSCRn, field PS[7:6] (RW)
Kojto 90:cb3d968589d8 438 *
Kojto 90:cb3d968589d8 439 * Specifies the data port width of the associated chip-select, and determines
Kojto 90:cb3d968589d8 440 * where data is driven during write cycles and where data is sampled during read
Kojto 90:cb3d968589d8 441 * cycles.
Kojto 90:cb3d968589d8 442 *
Kojto 90:cb3d968589d8 443 * Values:
Kojto 90:cb3d968589d8 444 * - 00 - 32-bit port size. Valid data is sampled and driven on FB_D[31:0].
Kojto 90:cb3d968589d8 445 * - 01 - 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when
Kojto 90:cb3d968589d8 446 * BLS is 0b, or FB_D[7:0] when BLS is 1b.
Kojto 90:cb3d968589d8 447 */
Kojto 90:cb3d968589d8 448 /*@{*/
Kojto 90:cb3d968589d8 449 #define BP_FB_CSCRn_PS (6U) /*!< Bit position for FB_CSCRn_PS. */
Kojto 90:cb3d968589d8 450 #define BM_FB_CSCRn_PS (0x000000C0U) /*!< Bit mask for FB_CSCRn_PS. */
Kojto 90:cb3d968589d8 451 #define BS_FB_CSCRn_PS (2U) /*!< Bit field size in bits for FB_CSCRn_PS. */
Kojto 90:cb3d968589d8 452
Kojto 90:cb3d968589d8 453 /*! @brief Read current value of the FB_CSCRn_PS field. */
Kojto 90:cb3d968589d8 454 #define BR_FB_CSCRn_PS(x, n) (HW_FB_CSCRn(x, n).B.PS)
Kojto 90:cb3d968589d8 455
Kojto 90:cb3d968589d8 456 /*! @brief Format value for bitfield FB_CSCRn_PS. */
Kojto 90:cb3d968589d8 457 #define BF_FB_CSCRn_PS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_PS) & BM_FB_CSCRn_PS)
Kojto 90:cb3d968589d8 458
Kojto 90:cb3d968589d8 459 /*! @brief Set the PS field to a new value. */
Kojto 90:cb3d968589d8 460 #define BW_FB_CSCRn_PS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_PS) | BF_FB_CSCRn_PS(v)))
Kojto 90:cb3d968589d8 461 /*@}*/
Kojto 90:cb3d968589d8 462
Kojto 90:cb3d968589d8 463 /*!
Kojto 90:cb3d968589d8 464 * @name Register FB_CSCRn, field AA[8] (RW)
Kojto 90:cb3d968589d8 465 *
Kojto 90:cb3d968589d8 466 * Asserts the internal transfer acknowledge for accesses specified by the
Kojto 90:cb3d968589d8 467 * chip-select address. If AA is 1b for a corresponding FB_CSn and the external system
Kojto 90:cb3d968589d8 468 * asserts an external FB_TA before the wait-state countdown asserts the
Kojto 90:cb3d968589d8 469 * internal FB_TA, the cycle is terminated. Burst cycles increment the address bus
Kojto 90:cb3d968589d8 470 * between each internal termination. This field must be 1b if CSPMCR disables FB_TA.
Kojto 90:cb3d968589d8 471 *
Kojto 90:cb3d968589d8 472 * Values:
Kojto 90:cb3d968589d8 473 * - 0 - Disabled. No internal transfer acknowledge is asserted and the cycle is
Kojto 90:cb3d968589d8 474 * terminated externally.
Kojto 90:cb3d968589d8 475 * - 1 - Enabled. Internal transfer acknowledge is asserted as specified by WS.
Kojto 90:cb3d968589d8 476 */
Kojto 90:cb3d968589d8 477 /*@{*/
Kojto 90:cb3d968589d8 478 #define BP_FB_CSCRn_AA (8U) /*!< Bit position for FB_CSCRn_AA. */
Kojto 90:cb3d968589d8 479 #define BM_FB_CSCRn_AA (0x00000100U) /*!< Bit mask for FB_CSCRn_AA. */
Kojto 90:cb3d968589d8 480 #define BS_FB_CSCRn_AA (1U) /*!< Bit field size in bits for FB_CSCRn_AA. */
Kojto 90:cb3d968589d8 481
Kojto 90:cb3d968589d8 482 /*! @brief Read current value of the FB_CSCRn_AA field. */
Kojto 90:cb3d968589d8 483 #define BR_FB_CSCRn_AA(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_AA))
Kojto 90:cb3d968589d8 484
Kojto 90:cb3d968589d8 485 /*! @brief Format value for bitfield FB_CSCRn_AA. */
Kojto 90:cb3d968589d8 486 #define BF_FB_CSCRn_AA(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_AA) & BM_FB_CSCRn_AA)
Kojto 90:cb3d968589d8 487
Kojto 90:cb3d968589d8 488 /*! @brief Set the AA field to a new value. */
Kojto 90:cb3d968589d8 489 #define BW_FB_CSCRn_AA(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_AA) = (v))
Kojto 90:cb3d968589d8 490 /*@}*/
Kojto 90:cb3d968589d8 491
Kojto 90:cb3d968589d8 492 /*!
Kojto 90:cb3d968589d8 493 * @name Register FB_CSCRn, field BLS[9] (RW)
Kojto 90:cb3d968589d8 494 *
Kojto 90:cb3d968589d8 495 * Specifies if data on FB_AD appears left-aligned or right-aligned during the
Kojto 90:cb3d968589d8 496 * data phase of a FlexBus access.
Kojto 90:cb3d968589d8 497 *
Kojto 90:cb3d968589d8 498 * Values:
Kojto 90:cb3d968589d8 499 * - 0 - Not shifted. Data is left-aligned on FB_AD.
Kojto 90:cb3d968589d8 500 * - 1 - Shifted. Data is right-aligned on FB_AD.
Kojto 90:cb3d968589d8 501 */
Kojto 90:cb3d968589d8 502 /*@{*/
Kojto 90:cb3d968589d8 503 #define BP_FB_CSCRn_BLS (9U) /*!< Bit position for FB_CSCRn_BLS. */
Kojto 90:cb3d968589d8 504 #define BM_FB_CSCRn_BLS (0x00000200U) /*!< Bit mask for FB_CSCRn_BLS. */
Kojto 90:cb3d968589d8 505 #define BS_FB_CSCRn_BLS (1U) /*!< Bit field size in bits for FB_CSCRn_BLS. */
Kojto 90:cb3d968589d8 506
Kojto 90:cb3d968589d8 507 /*! @brief Read current value of the FB_CSCRn_BLS field. */
Kojto 90:cb3d968589d8 508 #define BR_FB_CSCRn_BLS(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BLS))
Kojto 90:cb3d968589d8 509
Kojto 90:cb3d968589d8 510 /*! @brief Format value for bitfield FB_CSCRn_BLS. */
Kojto 90:cb3d968589d8 511 #define BF_FB_CSCRn_BLS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BLS) & BM_FB_CSCRn_BLS)
Kojto 90:cb3d968589d8 512
Kojto 90:cb3d968589d8 513 /*! @brief Set the BLS field to a new value. */
Kojto 90:cb3d968589d8 514 #define BW_FB_CSCRn_BLS(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BLS) = (v))
Kojto 90:cb3d968589d8 515 /*@}*/
Kojto 90:cb3d968589d8 516
Kojto 90:cb3d968589d8 517 /*!
Kojto 90:cb3d968589d8 518 * @name Register FB_CSCRn, field WS[15:10] (RW)
Kojto 90:cb3d968589d8 519 *
Kojto 90:cb3d968589d8 520 * Specifies the number of wait states inserted after FlexBus asserts the
Kojto 90:cb3d968589d8 521 * associated chip-select and before an internal transfer acknowledge is generated (WS
Kojto 90:cb3d968589d8 522 * = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states).
Kojto 90:cb3d968589d8 523 */
Kojto 90:cb3d968589d8 524 /*@{*/
Kojto 90:cb3d968589d8 525 #define BP_FB_CSCRn_WS (10U) /*!< Bit position for FB_CSCRn_WS. */
Kojto 90:cb3d968589d8 526 #define BM_FB_CSCRn_WS (0x0000FC00U) /*!< Bit mask for FB_CSCRn_WS. */
Kojto 90:cb3d968589d8 527 #define BS_FB_CSCRn_WS (6U) /*!< Bit field size in bits for FB_CSCRn_WS. */
Kojto 90:cb3d968589d8 528
Kojto 90:cb3d968589d8 529 /*! @brief Read current value of the FB_CSCRn_WS field. */
Kojto 90:cb3d968589d8 530 #define BR_FB_CSCRn_WS(x, n) (HW_FB_CSCRn(x, n).B.WS)
Kojto 90:cb3d968589d8 531
Kojto 90:cb3d968589d8 532 /*! @brief Format value for bitfield FB_CSCRn_WS. */
Kojto 90:cb3d968589d8 533 #define BF_FB_CSCRn_WS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_WS) & BM_FB_CSCRn_WS)
Kojto 90:cb3d968589d8 534
Kojto 90:cb3d968589d8 535 /*! @brief Set the WS field to a new value. */
Kojto 90:cb3d968589d8 536 #define BW_FB_CSCRn_WS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_WS) | BF_FB_CSCRn_WS(v)))
Kojto 90:cb3d968589d8 537 /*@}*/
Kojto 90:cb3d968589d8 538
Kojto 90:cb3d968589d8 539 /*!
Kojto 90:cb3d968589d8 540 * @name Register FB_CSCRn, field WRAH[17:16] (RW)
Kojto 90:cb3d968589d8 541 *
Kojto 90:cb3d968589d8 542 * Controls the address, data, and attribute hold time after the termination of
Kojto 90:cb3d968589d8 543 * a write cycle that hits in the associated chip-select's address space. The
Kojto 90:cb3d968589d8 544 * hold time applies only at the end of a transfer. Therefore, during a burst
Kojto 90:cb3d968589d8 545 * transfer or a transfer to a port size smaller than the transfer size, the hold time
Kojto 90:cb3d968589d8 546 * is only added after the last bus cycle.
Kojto 90:cb3d968589d8 547 *
Kojto 90:cb3d968589d8 548 * Values:
Kojto 90:cb3d968589d8 549 * - 00 - 1 cycle (default for all but FB_CS0 )
Kojto 90:cb3d968589d8 550 * - 01 - 2 cycles
Kojto 90:cb3d968589d8 551 * - 10 - 3 cycles
Kojto 90:cb3d968589d8 552 * - 11 - 4 cycles (default for FB_CS0 )
Kojto 90:cb3d968589d8 553 */
Kojto 90:cb3d968589d8 554 /*@{*/
Kojto 90:cb3d968589d8 555 #define BP_FB_CSCRn_WRAH (16U) /*!< Bit position for FB_CSCRn_WRAH. */
Kojto 90:cb3d968589d8 556 #define BM_FB_CSCRn_WRAH (0x00030000U) /*!< Bit mask for FB_CSCRn_WRAH. */
Kojto 90:cb3d968589d8 557 #define BS_FB_CSCRn_WRAH (2U) /*!< Bit field size in bits for FB_CSCRn_WRAH. */
Kojto 90:cb3d968589d8 558
Kojto 90:cb3d968589d8 559 /*! @brief Read current value of the FB_CSCRn_WRAH field. */
Kojto 90:cb3d968589d8 560 #define BR_FB_CSCRn_WRAH(x, n) (HW_FB_CSCRn(x, n).B.WRAH)
Kojto 90:cb3d968589d8 561
Kojto 90:cb3d968589d8 562 /*! @brief Format value for bitfield FB_CSCRn_WRAH. */
Kojto 90:cb3d968589d8 563 #define BF_FB_CSCRn_WRAH(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_WRAH) & BM_FB_CSCRn_WRAH)
Kojto 90:cb3d968589d8 564
Kojto 90:cb3d968589d8 565 /*! @brief Set the WRAH field to a new value. */
Kojto 90:cb3d968589d8 566 #define BW_FB_CSCRn_WRAH(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_WRAH) | BF_FB_CSCRn_WRAH(v)))
Kojto 90:cb3d968589d8 567 /*@}*/
Kojto 90:cb3d968589d8 568
Kojto 90:cb3d968589d8 569 /*!
Kojto 90:cb3d968589d8 570 * @name Register FB_CSCRn, field RDAH[19:18] (RW)
Kojto 90:cb3d968589d8 571 *
Kojto 90:cb3d968589d8 572 * Controls the address and attribute hold time after the termination during a
Kojto 90:cb3d968589d8 573 * read cycle that hits in the associated chip-select's address space. The hold
Kojto 90:cb3d968589d8 574 * time applies only at the end of a transfer. Therefore, during a burst transfer
Kojto 90:cb3d968589d8 575 * or a transfer to a port size smaller than the transfer size, the hold time is
Kojto 90:cb3d968589d8 576 * only added after the last bus cycle. The number of cycles the address and
Kojto 90:cb3d968589d8 577 * attributes are held after FB_CSn deassertion depends on the value of the AA bit.
Kojto 90:cb3d968589d8 578 *
Kojto 90:cb3d968589d8 579 * Values:
Kojto 90:cb3d968589d8 580 * - 00 - When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
Kojto 90:cb3d968589d8 581 * - 01 - When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
Kojto 90:cb3d968589d8 582 * - 10 - When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
Kojto 90:cb3d968589d8 583 * - 11 - When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
Kojto 90:cb3d968589d8 584 */
Kojto 90:cb3d968589d8 585 /*@{*/
Kojto 90:cb3d968589d8 586 #define BP_FB_CSCRn_RDAH (18U) /*!< Bit position for FB_CSCRn_RDAH. */
Kojto 90:cb3d968589d8 587 #define BM_FB_CSCRn_RDAH (0x000C0000U) /*!< Bit mask for FB_CSCRn_RDAH. */
Kojto 90:cb3d968589d8 588 #define BS_FB_CSCRn_RDAH (2U) /*!< Bit field size in bits for FB_CSCRn_RDAH. */
Kojto 90:cb3d968589d8 589
Kojto 90:cb3d968589d8 590 /*! @brief Read current value of the FB_CSCRn_RDAH field. */
Kojto 90:cb3d968589d8 591 #define BR_FB_CSCRn_RDAH(x, n) (HW_FB_CSCRn(x, n).B.RDAH)
Kojto 90:cb3d968589d8 592
Kojto 90:cb3d968589d8 593 /*! @brief Format value for bitfield FB_CSCRn_RDAH. */
Kojto 90:cb3d968589d8 594 #define BF_FB_CSCRn_RDAH(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_RDAH) & BM_FB_CSCRn_RDAH)
Kojto 90:cb3d968589d8 595
Kojto 90:cb3d968589d8 596 /*! @brief Set the RDAH field to a new value. */
Kojto 90:cb3d968589d8 597 #define BW_FB_CSCRn_RDAH(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_RDAH) | BF_FB_CSCRn_RDAH(v)))
Kojto 90:cb3d968589d8 598 /*@}*/
Kojto 90:cb3d968589d8 599
Kojto 90:cb3d968589d8 600 /*!
Kojto 90:cb3d968589d8 601 * @name Register FB_CSCRn, field ASET[21:20] (RW)
Kojto 90:cb3d968589d8 602 *
Kojto 90:cb3d968589d8 603 * Controls when the chip-select is asserted with respect to assertion of a
Kojto 90:cb3d968589d8 604 * valid address and attributes.
Kojto 90:cb3d968589d8 605 *
Kojto 90:cb3d968589d8 606 * Values:
Kojto 90:cb3d968589d8 607 * - 00 - Assert FB_CSn on the first rising clock edge after the address is
Kojto 90:cb3d968589d8 608 * asserted (default for all but FB_CS0 ).
Kojto 90:cb3d968589d8 609 * - 01 - Assert FB_CSn on the second rising clock edge after the address is
Kojto 90:cb3d968589d8 610 * asserted.
Kojto 90:cb3d968589d8 611 * - 10 - Assert FB_CSn on the third rising clock edge after the address is
Kojto 90:cb3d968589d8 612 * asserted.
Kojto 90:cb3d968589d8 613 * - 11 - Assert FB_CSn on the fourth rising clock edge after the address is
Kojto 90:cb3d968589d8 614 * asserted (default for FB_CS0 ).
Kojto 90:cb3d968589d8 615 */
Kojto 90:cb3d968589d8 616 /*@{*/
Kojto 90:cb3d968589d8 617 #define BP_FB_CSCRn_ASET (20U) /*!< Bit position for FB_CSCRn_ASET. */
Kojto 90:cb3d968589d8 618 #define BM_FB_CSCRn_ASET (0x00300000U) /*!< Bit mask for FB_CSCRn_ASET. */
Kojto 90:cb3d968589d8 619 #define BS_FB_CSCRn_ASET (2U) /*!< Bit field size in bits for FB_CSCRn_ASET. */
Kojto 90:cb3d968589d8 620
Kojto 90:cb3d968589d8 621 /*! @brief Read current value of the FB_CSCRn_ASET field. */
Kojto 90:cb3d968589d8 622 #define BR_FB_CSCRn_ASET(x, n) (HW_FB_CSCRn(x, n).B.ASET)
Kojto 90:cb3d968589d8 623
Kojto 90:cb3d968589d8 624 /*! @brief Format value for bitfield FB_CSCRn_ASET. */
Kojto 90:cb3d968589d8 625 #define BF_FB_CSCRn_ASET(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_ASET) & BM_FB_CSCRn_ASET)
Kojto 90:cb3d968589d8 626
Kojto 90:cb3d968589d8 627 /*! @brief Set the ASET field to a new value. */
Kojto 90:cb3d968589d8 628 #define BW_FB_CSCRn_ASET(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_ASET) | BF_FB_CSCRn_ASET(v)))
Kojto 90:cb3d968589d8 629 /*@}*/
Kojto 90:cb3d968589d8 630
Kojto 90:cb3d968589d8 631 /*!
Kojto 90:cb3d968589d8 632 * @name Register FB_CSCRn, field EXTS[22] (RW)
Kojto 90:cb3d968589d8 633 *
Kojto 90:cb3d968589d8 634 * Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS
Kojto 90:cb3d968589d8 635 * /FB_ALE is asserted.
Kojto 90:cb3d968589d8 636 *
Kojto 90:cb3d968589d8 637 * Values:
Kojto 90:cb3d968589d8 638 * - 0 - Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
Kojto 90:cb3d968589d8 639 * - 1 - Enabled. FB_TS /FB_ALE remains asserted until the first positive clock
Kojto 90:cb3d968589d8 640 * edge after FB_CSn asserts.
Kojto 90:cb3d968589d8 641 */
Kojto 90:cb3d968589d8 642 /*@{*/
Kojto 90:cb3d968589d8 643 #define BP_FB_CSCRn_EXTS (22U) /*!< Bit position for FB_CSCRn_EXTS. */
Kojto 90:cb3d968589d8 644 #define BM_FB_CSCRn_EXTS (0x00400000U) /*!< Bit mask for FB_CSCRn_EXTS. */
Kojto 90:cb3d968589d8 645 #define BS_FB_CSCRn_EXTS (1U) /*!< Bit field size in bits for FB_CSCRn_EXTS. */
Kojto 90:cb3d968589d8 646
Kojto 90:cb3d968589d8 647 /*! @brief Read current value of the FB_CSCRn_EXTS field. */
Kojto 90:cb3d968589d8 648 #define BR_FB_CSCRn_EXTS(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_EXTS))
Kojto 90:cb3d968589d8 649
Kojto 90:cb3d968589d8 650 /*! @brief Format value for bitfield FB_CSCRn_EXTS. */
Kojto 90:cb3d968589d8 651 #define BF_FB_CSCRn_EXTS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_EXTS) & BM_FB_CSCRn_EXTS)
Kojto 90:cb3d968589d8 652
Kojto 90:cb3d968589d8 653 /*! @brief Set the EXTS field to a new value. */
Kojto 90:cb3d968589d8 654 #define BW_FB_CSCRn_EXTS(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_EXTS) = (v))
Kojto 90:cb3d968589d8 655 /*@}*/
Kojto 90:cb3d968589d8 656
Kojto 90:cb3d968589d8 657 /*!
Kojto 90:cb3d968589d8 658 * @name Register FB_CSCRn, field SWSEN[23] (RW)
Kojto 90:cb3d968589d8 659 *
Kojto 90:cb3d968589d8 660 * Values:
Kojto 90:cb3d968589d8 661 * - 0 - Disabled. A number of wait states (specified by WS) are inserted before
Kojto 90:cb3d968589d8 662 * an internal transfer acknowledge is generated for all transfers.
Kojto 90:cb3d968589d8 663 * - 1 - Enabled. A number of wait states (specified by SWS) are inserted before
Kojto 90:cb3d968589d8 664 * an internal transfer acknowledge is generated for burst transfer
Kojto 90:cb3d968589d8 665 * secondary terminations.
Kojto 90:cb3d968589d8 666 */
Kojto 90:cb3d968589d8 667 /*@{*/
Kojto 90:cb3d968589d8 668 #define BP_FB_CSCRn_SWSEN (23U) /*!< Bit position for FB_CSCRn_SWSEN. */
Kojto 90:cb3d968589d8 669 #define BM_FB_CSCRn_SWSEN (0x00800000U) /*!< Bit mask for FB_CSCRn_SWSEN. */
Kojto 90:cb3d968589d8 670 #define BS_FB_CSCRn_SWSEN (1U) /*!< Bit field size in bits for FB_CSCRn_SWSEN. */
Kojto 90:cb3d968589d8 671
Kojto 90:cb3d968589d8 672 /*! @brief Read current value of the FB_CSCRn_SWSEN field. */
Kojto 90:cb3d968589d8 673 #define BR_FB_CSCRn_SWSEN(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_SWSEN))
Kojto 90:cb3d968589d8 674
Kojto 90:cb3d968589d8 675 /*! @brief Format value for bitfield FB_CSCRn_SWSEN. */
Kojto 90:cb3d968589d8 676 #define BF_FB_CSCRn_SWSEN(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_SWSEN) & BM_FB_CSCRn_SWSEN)
Kojto 90:cb3d968589d8 677
Kojto 90:cb3d968589d8 678 /*! @brief Set the SWSEN field to a new value. */
Kojto 90:cb3d968589d8 679 #define BW_FB_CSCRn_SWSEN(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_SWSEN) = (v))
Kojto 90:cb3d968589d8 680 /*@}*/
Kojto 90:cb3d968589d8 681
Kojto 90:cb3d968589d8 682 /*!
Kojto 90:cb3d968589d8 683 * @name Register FB_CSCRn, field SWS[31:26] (RW)
Kojto 90:cb3d968589d8 684 *
Kojto 90:cb3d968589d8 685 * Used only when the SWSEN bit is 1b. Specifies the number of wait states
Kojto 90:cb3d968589d8 686 * inserted before an internal transfer acknowledge is generated for a burst transfer
Kojto 90:cb3d968589d8 687 * (except for the first termination, which is controlled by WS).
Kojto 90:cb3d968589d8 688 */
Kojto 90:cb3d968589d8 689 /*@{*/
Kojto 90:cb3d968589d8 690 #define BP_FB_CSCRn_SWS (26U) /*!< Bit position for FB_CSCRn_SWS. */
Kojto 90:cb3d968589d8 691 #define BM_FB_CSCRn_SWS (0xFC000000U) /*!< Bit mask for FB_CSCRn_SWS. */
Kojto 90:cb3d968589d8 692 #define BS_FB_CSCRn_SWS (6U) /*!< Bit field size in bits for FB_CSCRn_SWS. */
Kojto 90:cb3d968589d8 693
Kojto 90:cb3d968589d8 694 /*! @brief Read current value of the FB_CSCRn_SWS field. */
Kojto 90:cb3d968589d8 695 #define BR_FB_CSCRn_SWS(x, n) (HW_FB_CSCRn(x, n).B.SWS)
Kojto 90:cb3d968589d8 696
Kojto 90:cb3d968589d8 697 /*! @brief Format value for bitfield FB_CSCRn_SWS. */
Kojto 90:cb3d968589d8 698 #define BF_FB_CSCRn_SWS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_SWS) & BM_FB_CSCRn_SWS)
Kojto 90:cb3d968589d8 699
Kojto 90:cb3d968589d8 700 /*! @brief Set the SWS field to a new value. */
Kojto 90:cb3d968589d8 701 #define BW_FB_CSCRn_SWS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_SWS) | BF_FB_CSCRn_SWS(v)))
Kojto 90:cb3d968589d8 702 /*@}*/
Kojto 90:cb3d968589d8 703
Kojto 90:cb3d968589d8 704 /*******************************************************************************
Kojto 90:cb3d968589d8 705 * HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
Kojto 90:cb3d968589d8 706 ******************************************************************************/
Kojto 90:cb3d968589d8 707
Kojto 90:cb3d968589d8 708 /*!
Kojto 90:cb3d968589d8 709 * @brief HW_FB_CSPMCR - Chip Select port Multiplexing Control Register (RW)
Kojto 90:cb3d968589d8 710 *
Kojto 90:cb3d968589d8 711 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 712 *
Kojto 90:cb3d968589d8 713 * Controls the multiplexing of the FlexBus signals. A bus error occurs when you
Kojto 90:cb3d968589d8 714 * do any of the following: Write to a reserved address Write to a reserved
Kojto 90:cb3d968589d8 715 * field in this register, or Access this register using a size other than 32 bits.
Kojto 90:cb3d968589d8 716 */
Kojto 90:cb3d968589d8 717 typedef union _hw_fb_cspmcr
Kojto 90:cb3d968589d8 718 {
Kojto 90:cb3d968589d8 719 uint32_t U;
Kojto 90:cb3d968589d8 720 struct _hw_fb_cspmcr_bitfields
Kojto 90:cb3d968589d8 721 {
Kojto 90:cb3d968589d8 722 uint32_t RESERVED0 : 12; /*!< [11:0] */
Kojto 90:cb3d968589d8 723 uint32_t GROUP5 : 4; /*!< [15:12] FlexBus Signal Group 5 Multiplex
Kojto 90:cb3d968589d8 724 * control */
Kojto 90:cb3d968589d8 725 uint32_t GROUP4 : 4; /*!< [19:16] FlexBus Signal Group 4 Multiplex
Kojto 90:cb3d968589d8 726 * control */
Kojto 90:cb3d968589d8 727 uint32_t GROUP3 : 4; /*!< [23:20] FlexBus Signal Group 3 Multiplex
Kojto 90:cb3d968589d8 728 * control */
Kojto 90:cb3d968589d8 729 uint32_t GROUP2 : 4; /*!< [27:24] FlexBus Signal Group 2 Multiplex
Kojto 90:cb3d968589d8 730 * control */
Kojto 90:cb3d968589d8 731 uint32_t GROUP1 : 4; /*!< [31:28] FlexBus Signal Group 1 Multiplex
Kojto 90:cb3d968589d8 732 * control */
Kojto 90:cb3d968589d8 733 } B;
Kojto 90:cb3d968589d8 734 } hw_fb_cspmcr_t;
Kojto 90:cb3d968589d8 735
Kojto 90:cb3d968589d8 736 /*!
Kojto 90:cb3d968589d8 737 * @name Constants and macros for entire FB_CSPMCR register
Kojto 90:cb3d968589d8 738 */
Kojto 90:cb3d968589d8 739 /*@{*/
Kojto 90:cb3d968589d8 740 #define HW_FB_CSPMCR_ADDR(x) ((x) + 0x60U)
Kojto 90:cb3d968589d8 741
Kojto 90:cb3d968589d8 742 #define HW_FB_CSPMCR(x) (*(__IO hw_fb_cspmcr_t *) HW_FB_CSPMCR_ADDR(x))
Kojto 90:cb3d968589d8 743 #define HW_FB_CSPMCR_RD(x) (HW_FB_CSPMCR(x).U)
Kojto 90:cb3d968589d8 744 #define HW_FB_CSPMCR_WR(x, v) (HW_FB_CSPMCR(x).U = (v))
Kojto 90:cb3d968589d8 745 #define HW_FB_CSPMCR_SET(x, v) (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) | (v)))
Kojto 90:cb3d968589d8 746 #define HW_FB_CSPMCR_CLR(x, v) (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 747 #define HW_FB_CSPMCR_TOG(x, v) (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 748 /*@}*/
Kojto 90:cb3d968589d8 749
Kojto 90:cb3d968589d8 750 /*
Kojto 90:cb3d968589d8 751 * Constants & macros for individual FB_CSPMCR bitfields
Kojto 90:cb3d968589d8 752 */
Kojto 90:cb3d968589d8 753
Kojto 90:cb3d968589d8 754 /*!
Kojto 90:cb3d968589d8 755 * @name Register FB_CSPMCR, field GROUP5[15:12] (RW)
Kojto 90:cb3d968589d8 756 *
Kojto 90:cb3d968589d8 757 * Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When
Kojto 90:cb3d968589d8 758 * GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the
Kojto 90:cb3d968589d8 759 * bus hangs during a transfer.
Kojto 90:cb3d968589d8 760 *
Kojto 90:cb3d968589d8 761 * Values:
Kojto 90:cb3d968589d8 762 * - 0000 - FB_TA
Kojto 90:cb3d968589d8 763 * - 0001 - FB_CS3 . You must also write 1b to CSCR[AA].
Kojto 90:cb3d968589d8 764 * - 0010 - FB_BE_7_0 . You must also write 1b to CSCR[AA].
Kojto 90:cb3d968589d8 765 */
Kojto 90:cb3d968589d8 766 /*@{*/
Kojto 90:cb3d968589d8 767 #define BP_FB_CSPMCR_GROUP5 (12U) /*!< Bit position for FB_CSPMCR_GROUP5. */
Kojto 90:cb3d968589d8 768 #define BM_FB_CSPMCR_GROUP5 (0x0000F000U) /*!< Bit mask for FB_CSPMCR_GROUP5. */
Kojto 90:cb3d968589d8 769 #define BS_FB_CSPMCR_GROUP5 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP5. */
Kojto 90:cb3d968589d8 770
Kojto 90:cb3d968589d8 771 /*! @brief Read current value of the FB_CSPMCR_GROUP5 field. */
Kojto 90:cb3d968589d8 772 #define BR_FB_CSPMCR_GROUP5(x) (HW_FB_CSPMCR(x).B.GROUP5)
Kojto 90:cb3d968589d8 773
Kojto 90:cb3d968589d8 774 /*! @brief Format value for bitfield FB_CSPMCR_GROUP5. */
Kojto 90:cb3d968589d8 775 #define BF_FB_CSPMCR_GROUP5(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP5) & BM_FB_CSPMCR_GROUP5)
Kojto 90:cb3d968589d8 776
Kojto 90:cb3d968589d8 777 /*! @brief Set the GROUP5 field to a new value. */
Kojto 90:cb3d968589d8 778 #define BW_FB_CSPMCR_GROUP5(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP5) | BF_FB_CSPMCR_GROUP5(v)))
Kojto 90:cb3d968589d8 779 /*@}*/
Kojto 90:cb3d968589d8 780
Kojto 90:cb3d968589d8 781 /*!
Kojto 90:cb3d968589d8 782 * @name Register FB_CSPMCR, field GROUP4[19:16] (RW)
Kojto 90:cb3d968589d8 783 *
Kojto 90:cb3d968589d8 784 * Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals.
Kojto 90:cb3d968589d8 785 *
Kojto 90:cb3d968589d8 786 * Values:
Kojto 90:cb3d968589d8 787 * - 0000 - FB_TBST
Kojto 90:cb3d968589d8 788 * - 0001 - FB_CS2
Kojto 90:cb3d968589d8 789 * - 0010 - FB_BE_15_8
Kojto 90:cb3d968589d8 790 */
Kojto 90:cb3d968589d8 791 /*@{*/
Kojto 90:cb3d968589d8 792 #define BP_FB_CSPMCR_GROUP4 (16U) /*!< Bit position for FB_CSPMCR_GROUP4. */
Kojto 90:cb3d968589d8 793 #define BM_FB_CSPMCR_GROUP4 (0x000F0000U) /*!< Bit mask for FB_CSPMCR_GROUP4. */
Kojto 90:cb3d968589d8 794 #define BS_FB_CSPMCR_GROUP4 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP4. */
Kojto 90:cb3d968589d8 795
Kojto 90:cb3d968589d8 796 /*! @brief Read current value of the FB_CSPMCR_GROUP4 field. */
Kojto 90:cb3d968589d8 797 #define BR_FB_CSPMCR_GROUP4(x) (HW_FB_CSPMCR(x).B.GROUP4)
Kojto 90:cb3d968589d8 798
Kojto 90:cb3d968589d8 799 /*! @brief Format value for bitfield FB_CSPMCR_GROUP4. */
Kojto 90:cb3d968589d8 800 #define BF_FB_CSPMCR_GROUP4(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP4) & BM_FB_CSPMCR_GROUP4)
Kojto 90:cb3d968589d8 801
Kojto 90:cb3d968589d8 802 /*! @brief Set the GROUP4 field to a new value. */
Kojto 90:cb3d968589d8 803 #define BW_FB_CSPMCR_GROUP4(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP4) | BF_FB_CSPMCR_GROUP4(v)))
Kojto 90:cb3d968589d8 804 /*@}*/
Kojto 90:cb3d968589d8 805
Kojto 90:cb3d968589d8 806 /*!
Kojto 90:cb3d968589d8 807 * @name Register FB_CSPMCR, field GROUP3[23:20] (RW)
Kojto 90:cb3d968589d8 808 *
Kojto 90:cb3d968589d8 809 * Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals.
Kojto 90:cb3d968589d8 810 *
Kojto 90:cb3d968589d8 811 * Values:
Kojto 90:cb3d968589d8 812 * - 0000 - FB_CS5
Kojto 90:cb3d968589d8 813 * - 0001 - FB_TSIZ1
Kojto 90:cb3d968589d8 814 * - 0010 - FB_BE_23_16
Kojto 90:cb3d968589d8 815 */
Kojto 90:cb3d968589d8 816 /*@{*/
Kojto 90:cb3d968589d8 817 #define BP_FB_CSPMCR_GROUP3 (20U) /*!< Bit position for FB_CSPMCR_GROUP3. */
Kojto 90:cb3d968589d8 818 #define BM_FB_CSPMCR_GROUP3 (0x00F00000U) /*!< Bit mask for FB_CSPMCR_GROUP3. */
Kojto 90:cb3d968589d8 819 #define BS_FB_CSPMCR_GROUP3 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP3. */
Kojto 90:cb3d968589d8 820
Kojto 90:cb3d968589d8 821 /*! @brief Read current value of the FB_CSPMCR_GROUP3 field. */
Kojto 90:cb3d968589d8 822 #define BR_FB_CSPMCR_GROUP3(x) (HW_FB_CSPMCR(x).B.GROUP3)
Kojto 90:cb3d968589d8 823
Kojto 90:cb3d968589d8 824 /*! @brief Format value for bitfield FB_CSPMCR_GROUP3. */
Kojto 90:cb3d968589d8 825 #define BF_FB_CSPMCR_GROUP3(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP3) & BM_FB_CSPMCR_GROUP3)
Kojto 90:cb3d968589d8 826
Kojto 90:cb3d968589d8 827 /*! @brief Set the GROUP3 field to a new value. */
Kojto 90:cb3d968589d8 828 #define BW_FB_CSPMCR_GROUP3(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP3) | BF_FB_CSPMCR_GROUP3(v)))
Kojto 90:cb3d968589d8 829 /*@}*/
Kojto 90:cb3d968589d8 830
Kojto 90:cb3d968589d8 831 /*!
Kojto 90:cb3d968589d8 832 * @name Register FB_CSPMCR, field GROUP2[27:24] (RW)
Kojto 90:cb3d968589d8 833 *
Kojto 90:cb3d968589d8 834 * Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals.
Kojto 90:cb3d968589d8 835 *
Kojto 90:cb3d968589d8 836 * Values:
Kojto 90:cb3d968589d8 837 * - 0000 - FB_CS4
Kojto 90:cb3d968589d8 838 * - 0001 - FB_TSIZ0
Kojto 90:cb3d968589d8 839 * - 0010 - FB_BE_31_24
Kojto 90:cb3d968589d8 840 */
Kojto 90:cb3d968589d8 841 /*@{*/
Kojto 90:cb3d968589d8 842 #define BP_FB_CSPMCR_GROUP2 (24U) /*!< Bit position for FB_CSPMCR_GROUP2. */
Kojto 90:cb3d968589d8 843 #define BM_FB_CSPMCR_GROUP2 (0x0F000000U) /*!< Bit mask for FB_CSPMCR_GROUP2. */
Kojto 90:cb3d968589d8 844 #define BS_FB_CSPMCR_GROUP2 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP2. */
Kojto 90:cb3d968589d8 845
Kojto 90:cb3d968589d8 846 /*! @brief Read current value of the FB_CSPMCR_GROUP2 field. */
Kojto 90:cb3d968589d8 847 #define BR_FB_CSPMCR_GROUP2(x) (HW_FB_CSPMCR(x).B.GROUP2)
Kojto 90:cb3d968589d8 848
Kojto 90:cb3d968589d8 849 /*! @brief Format value for bitfield FB_CSPMCR_GROUP2. */
Kojto 90:cb3d968589d8 850 #define BF_FB_CSPMCR_GROUP2(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP2) & BM_FB_CSPMCR_GROUP2)
Kojto 90:cb3d968589d8 851
Kojto 90:cb3d968589d8 852 /*! @brief Set the GROUP2 field to a new value. */
Kojto 90:cb3d968589d8 853 #define BW_FB_CSPMCR_GROUP2(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP2) | BF_FB_CSPMCR_GROUP2(v)))
Kojto 90:cb3d968589d8 854 /*@}*/
Kojto 90:cb3d968589d8 855
Kojto 90:cb3d968589d8 856 /*!
Kojto 90:cb3d968589d8 857 * @name Register FB_CSPMCR, field GROUP1[31:28] (RW)
Kojto 90:cb3d968589d8 858 *
Kojto 90:cb3d968589d8 859 * Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals.
Kojto 90:cb3d968589d8 860 *
Kojto 90:cb3d968589d8 861 * Values:
Kojto 90:cb3d968589d8 862 * - 0000 - FB_ALE
Kojto 90:cb3d968589d8 863 * - 0001 - FB_CS1
Kojto 90:cb3d968589d8 864 * - 0010 - FB_TS
Kojto 90:cb3d968589d8 865 */
Kojto 90:cb3d968589d8 866 /*@{*/
Kojto 90:cb3d968589d8 867 #define BP_FB_CSPMCR_GROUP1 (28U) /*!< Bit position for FB_CSPMCR_GROUP1. */
Kojto 90:cb3d968589d8 868 #define BM_FB_CSPMCR_GROUP1 (0xF0000000U) /*!< Bit mask for FB_CSPMCR_GROUP1. */
Kojto 90:cb3d968589d8 869 #define BS_FB_CSPMCR_GROUP1 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP1. */
Kojto 90:cb3d968589d8 870
Kojto 90:cb3d968589d8 871 /*! @brief Read current value of the FB_CSPMCR_GROUP1 field. */
Kojto 90:cb3d968589d8 872 #define BR_FB_CSPMCR_GROUP1(x) (HW_FB_CSPMCR(x).B.GROUP1)
Kojto 90:cb3d968589d8 873
Kojto 90:cb3d968589d8 874 /*! @brief Format value for bitfield FB_CSPMCR_GROUP1. */
Kojto 90:cb3d968589d8 875 #define BF_FB_CSPMCR_GROUP1(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP1) & BM_FB_CSPMCR_GROUP1)
Kojto 90:cb3d968589d8 876
Kojto 90:cb3d968589d8 877 /*! @brief Set the GROUP1 field to a new value. */
Kojto 90:cb3d968589d8 878 #define BW_FB_CSPMCR_GROUP1(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP1) | BF_FB_CSPMCR_GROUP1(v)))
Kojto 90:cb3d968589d8 879 /*@}*/
Kojto 90:cb3d968589d8 880
Kojto 90:cb3d968589d8 881 /*******************************************************************************
Kojto 90:cb3d968589d8 882 * hw_fb_t - module struct
Kojto 90:cb3d968589d8 883 ******************************************************************************/
Kojto 90:cb3d968589d8 884 /*!
Kojto 90:cb3d968589d8 885 * @brief All FB module registers.
Kojto 90:cb3d968589d8 886 */
Kojto 90:cb3d968589d8 887 #pragma pack(1)
Kojto 90:cb3d968589d8 888 typedef struct _hw_fb
Kojto 90:cb3d968589d8 889 {
Kojto 90:cb3d968589d8 890 struct {
Kojto 90:cb3d968589d8 891 __IO hw_fb_csarn_t CSARn; /*!< [0x0] Chip Select Address Register */
Kojto 90:cb3d968589d8 892 __IO hw_fb_csmrn_t CSMRn; /*!< [0x4] Chip Select Mask Register */
Kojto 90:cb3d968589d8 893 __IO hw_fb_cscrn_t CSCRn; /*!< [0x8] Chip Select Control Register */
Kojto 90:cb3d968589d8 894 } CS[6];
Kojto 90:cb3d968589d8 895 uint8_t _reserved0[24];
Kojto 90:cb3d968589d8 896 __IO hw_fb_cspmcr_t CSPMCR; /*!< [0x60] Chip Select port Multiplexing Control Register */
Kojto 90:cb3d968589d8 897 } hw_fb_t;
Kojto 90:cb3d968589d8 898 #pragma pack()
Kojto 90:cb3d968589d8 899
Kojto 90:cb3d968589d8 900 /*! @brief Macro to access all FB registers. */
Kojto 90:cb3d968589d8 901 /*! @param x FB module instance base address. */
Kojto 90:cb3d968589d8 902 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto 90:cb3d968589d8 903 * use the '&' operator, like <code>&HW_FB(FB_BASE)</code>. */
Kojto 90:cb3d968589d8 904 #define HW_FB(x) (*(hw_fb_t *)(x))
Kojto 90:cb3d968589d8 905
Kojto 90:cb3d968589d8 906 #endif /* __HW_FB_REGISTERS_H__ */
Kojto 90:cb3d968589d8 907 /* EOF */