The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
mbed 2
This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.
TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_ewm.h@104:b9ad9a133dc7, 2015-08-05 (annotated)
- Committer:
- Kojto
- Date:
- Wed Aug 05 13:16:35 2015 +0100
- Revision:
- 104:b9ad9a133dc7
- Parent:
- 90:cb3d968589d8
Release 104 of the mbed library:
Changes:
- new platforms: nrf51 microbit
- MAXxxx - fix pwm array search
- LPC8xx - usart enable fix
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Kojto | 90:cb3d968589d8 | 1 | /* |
Kojto | 90:cb3d968589d8 | 2 | ** ################################################################### |
Kojto | 90:cb3d968589d8 | 3 | ** Compilers: Keil ARM C/C++ Compiler |
Kojto | 90:cb3d968589d8 | 4 | ** Freescale C/C++ for Embedded ARM |
Kojto | 90:cb3d968589d8 | 5 | ** GNU C Compiler |
Kojto | 90:cb3d968589d8 | 6 | ** IAR ANSI C/C++ Compiler for ARM |
Kojto | 90:cb3d968589d8 | 7 | ** |
Kojto | 90:cb3d968589d8 | 8 | ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 |
Kojto | 90:cb3d968589d8 | 9 | ** Version: rev. 2.5, 2014-02-10 |
Kojto | 90:cb3d968589d8 | 10 | ** Build: b140604 |
Kojto | 90:cb3d968589d8 | 11 | ** |
Kojto | 90:cb3d968589d8 | 12 | ** Abstract: |
Kojto | 90:cb3d968589d8 | 13 | ** Extension to the CMSIS register access layer header. |
Kojto | 90:cb3d968589d8 | 14 | ** |
Kojto | 90:cb3d968589d8 | 15 | ** Copyright (c) 2014 Freescale Semiconductor, Inc. |
Kojto | 90:cb3d968589d8 | 16 | ** All rights reserved. |
Kojto | 90:cb3d968589d8 | 17 | ** |
Kojto | 90:cb3d968589d8 | 18 | ** Redistribution and use in source and binary forms, with or without modification, |
Kojto | 90:cb3d968589d8 | 19 | ** are permitted provided that the following conditions are met: |
Kojto | 90:cb3d968589d8 | 20 | ** |
Kojto | 90:cb3d968589d8 | 21 | ** o Redistributions of source code must retain the above copyright notice, this list |
Kojto | 90:cb3d968589d8 | 22 | ** of conditions and the following disclaimer. |
Kojto | 90:cb3d968589d8 | 23 | ** |
Kojto | 90:cb3d968589d8 | 24 | ** o Redistributions in binary form must reproduce the above copyright notice, this |
Kojto | 90:cb3d968589d8 | 25 | ** list of conditions and the following disclaimer in the documentation and/or |
Kojto | 90:cb3d968589d8 | 26 | ** other materials provided with the distribution. |
Kojto | 90:cb3d968589d8 | 27 | ** |
Kojto | 90:cb3d968589d8 | 28 | ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
Kojto | 90:cb3d968589d8 | 29 | ** contributors may be used to endorse or promote products derived from this |
Kojto | 90:cb3d968589d8 | 30 | ** software without specific prior written permission. |
Kojto | 90:cb3d968589d8 | 31 | ** |
Kojto | 90:cb3d968589d8 | 32 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
Kojto | 90:cb3d968589d8 | 33 | ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
Kojto | 90:cb3d968589d8 | 34 | ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
Kojto | 90:cb3d968589d8 | 35 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
Kojto | 90:cb3d968589d8 | 36 | ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
Kojto | 90:cb3d968589d8 | 37 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
Kojto | 90:cb3d968589d8 | 38 | ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
Kojto | 90:cb3d968589d8 | 39 | ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
Kojto | 90:cb3d968589d8 | 40 | ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
Kojto | 90:cb3d968589d8 | 41 | ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Kojto | 90:cb3d968589d8 | 42 | ** |
Kojto | 90:cb3d968589d8 | 43 | ** http: www.freescale.com |
Kojto | 90:cb3d968589d8 | 44 | ** mail: support@freescale.com |
Kojto | 90:cb3d968589d8 | 45 | ** |
Kojto | 90:cb3d968589d8 | 46 | ** Revisions: |
Kojto | 90:cb3d968589d8 | 47 | ** - rev. 1.0 (2013-08-12) |
Kojto | 90:cb3d968589d8 | 48 | ** Initial version. |
Kojto | 90:cb3d968589d8 | 49 | ** - rev. 2.0 (2013-10-29) |
Kojto | 90:cb3d968589d8 | 50 | ** Register accessor macros added to the memory map. |
Kojto | 90:cb3d968589d8 | 51 | ** Symbols for Processor Expert memory map compatibility added to the memory map. |
Kojto | 90:cb3d968589d8 | 52 | ** Startup file for gcc has been updated according to CMSIS 3.2. |
Kojto | 90:cb3d968589d8 | 53 | ** System initialization updated. |
Kojto | 90:cb3d968589d8 | 54 | ** MCG - registers updated. |
Kojto | 90:cb3d968589d8 | 55 | ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. |
Kojto | 90:cb3d968589d8 | 56 | ** - rev. 2.1 (2013-10-30) |
Kojto | 90:cb3d968589d8 | 57 | ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. |
Kojto | 90:cb3d968589d8 | 58 | ** - rev. 2.2 (2013-12-09) |
Kojto | 90:cb3d968589d8 | 59 | ** DMA - EARS register removed. |
Kojto | 90:cb3d968589d8 | 60 | ** AIPS0, AIPS1 - MPRA register updated. |
Kojto | 90:cb3d968589d8 | 61 | ** - rev. 2.3 (2014-01-24) |
Kojto | 90:cb3d968589d8 | 62 | ** Update according to reference manual rev. 2 |
Kojto | 90:cb3d968589d8 | 63 | ** ENET, MCG, MCM, SIM, USB - registers updated |
Kojto | 90:cb3d968589d8 | 64 | ** - rev. 2.4 (2014-02-10) |
Kojto | 90:cb3d968589d8 | 65 | ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h |
Kojto | 90:cb3d968589d8 | 66 | ** Update of SystemInit() and SystemCoreClockUpdate() functions. |
Kojto | 90:cb3d968589d8 | 67 | ** - rev. 2.5 (2014-02-10) |
Kojto | 90:cb3d968589d8 | 68 | ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h |
Kojto | 90:cb3d968589d8 | 69 | ** Update of SystemInit() and SystemCoreClockUpdate() functions. |
Kojto | 90:cb3d968589d8 | 70 | ** Module access macro module_BASES replaced by module_BASE_PTRS. |
Kojto | 90:cb3d968589d8 | 71 | ** |
Kojto | 90:cb3d968589d8 | 72 | ** ################################################################### |
Kojto | 90:cb3d968589d8 | 73 | */ |
Kojto | 90:cb3d968589d8 | 74 | |
Kojto | 90:cb3d968589d8 | 75 | /* |
Kojto | 90:cb3d968589d8 | 76 | * WARNING! DO NOT EDIT THIS FILE DIRECTLY! |
Kojto | 90:cb3d968589d8 | 77 | * |
Kojto | 90:cb3d968589d8 | 78 | * This file was generated automatically and any changes may be lost. |
Kojto | 90:cb3d968589d8 | 79 | */ |
Kojto | 90:cb3d968589d8 | 80 | #ifndef __HW_EWM_REGISTERS_H__ |
Kojto | 90:cb3d968589d8 | 81 | #define __HW_EWM_REGISTERS_H__ |
Kojto | 90:cb3d968589d8 | 82 | |
Kojto | 90:cb3d968589d8 | 83 | #include "MK64F12.h" |
Kojto | 90:cb3d968589d8 | 84 | #include "fsl_bitaccess.h" |
Kojto | 90:cb3d968589d8 | 85 | |
Kojto | 90:cb3d968589d8 | 86 | /* |
Kojto | 90:cb3d968589d8 | 87 | * MK64F12 EWM |
Kojto | 90:cb3d968589d8 | 88 | * |
Kojto | 90:cb3d968589d8 | 89 | * External Watchdog Monitor |
Kojto | 90:cb3d968589d8 | 90 | * |
Kojto | 90:cb3d968589d8 | 91 | * Registers defined in this header file: |
Kojto | 90:cb3d968589d8 | 92 | * - HW_EWM_CTRL - Control Register |
Kojto | 90:cb3d968589d8 | 93 | * - HW_EWM_SERV - Service Register |
Kojto | 90:cb3d968589d8 | 94 | * - HW_EWM_CMPL - Compare Low Register |
Kojto | 90:cb3d968589d8 | 95 | * - HW_EWM_CMPH - Compare High Register |
Kojto | 90:cb3d968589d8 | 96 | * |
Kojto | 90:cb3d968589d8 | 97 | * - hw_ewm_t - Struct containing all module registers. |
Kojto | 90:cb3d968589d8 | 98 | */ |
Kojto | 90:cb3d968589d8 | 99 | |
Kojto | 90:cb3d968589d8 | 100 | #define HW_EWM_INSTANCE_COUNT (1U) /*!< Number of instances of the EWM module. */ |
Kojto | 90:cb3d968589d8 | 101 | |
Kojto | 90:cb3d968589d8 | 102 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 103 | * HW_EWM_CTRL - Control Register |
Kojto | 90:cb3d968589d8 | 104 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 105 | |
Kojto | 90:cb3d968589d8 | 106 | /*! |
Kojto | 90:cb3d968589d8 | 107 | * @brief HW_EWM_CTRL - Control Register (RW) |
Kojto | 90:cb3d968589d8 | 108 | * |
Kojto | 90:cb3d968589d8 | 109 | * Reset value: 0x00U |
Kojto | 90:cb3d968589d8 | 110 | * |
Kojto | 90:cb3d968589d8 | 111 | * The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be |
Kojto | 90:cb3d968589d8 | 112 | * written once after a CPU reset. Modifying these bits more than once, generates |
Kojto | 90:cb3d968589d8 | 113 | * a bus transfer error. |
Kojto | 90:cb3d968589d8 | 114 | */ |
Kojto | 90:cb3d968589d8 | 115 | typedef union _hw_ewm_ctrl |
Kojto | 90:cb3d968589d8 | 116 | { |
Kojto | 90:cb3d968589d8 | 117 | uint8_t U; |
Kojto | 90:cb3d968589d8 | 118 | struct _hw_ewm_ctrl_bitfields |
Kojto | 90:cb3d968589d8 | 119 | { |
Kojto | 90:cb3d968589d8 | 120 | uint8_t EWMEN : 1; /*!< [0] EWM enable. */ |
Kojto | 90:cb3d968589d8 | 121 | uint8_t ASSIN : 1; /*!< [1] EWM_in's Assertion State Select. */ |
Kojto | 90:cb3d968589d8 | 122 | uint8_t INEN : 1; /*!< [2] Input Enable. */ |
Kojto | 90:cb3d968589d8 | 123 | uint8_t INTEN : 1; /*!< [3] Interrupt Enable. */ |
Kojto | 90:cb3d968589d8 | 124 | uint8_t RESERVED0 : 4; /*!< [7:4] */ |
Kojto | 90:cb3d968589d8 | 125 | } B; |
Kojto | 90:cb3d968589d8 | 126 | } hw_ewm_ctrl_t; |
Kojto | 90:cb3d968589d8 | 127 | |
Kojto | 90:cb3d968589d8 | 128 | /*! |
Kojto | 90:cb3d968589d8 | 129 | * @name Constants and macros for entire EWM_CTRL register |
Kojto | 90:cb3d968589d8 | 130 | */ |
Kojto | 90:cb3d968589d8 | 131 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 132 | #define HW_EWM_CTRL_ADDR(x) ((x) + 0x0U) |
Kojto | 90:cb3d968589d8 | 133 | |
Kojto | 90:cb3d968589d8 | 134 | #define HW_EWM_CTRL(x) (*(__IO hw_ewm_ctrl_t *) HW_EWM_CTRL_ADDR(x)) |
Kojto | 90:cb3d968589d8 | 135 | #define HW_EWM_CTRL_RD(x) (HW_EWM_CTRL(x).U) |
Kojto | 90:cb3d968589d8 | 136 | #define HW_EWM_CTRL_WR(x, v) (HW_EWM_CTRL(x).U = (v)) |
Kojto | 90:cb3d968589d8 | 137 | #define HW_EWM_CTRL_SET(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) | (v))) |
Kojto | 90:cb3d968589d8 | 138 | #define HW_EWM_CTRL_CLR(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) & ~(v))) |
Kojto | 90:cb3d968589d8 | 139 | #define HW_EWM_CTRL_TOG(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) ^ (v))) |
Kojto | 90:cb3d968589d8 | 140 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 141 | |
Kojto | 90:cb3d968589d8 | 142 | /* |
Kojto | 90:cb3d968589d8 | 143 | * Constants & macros for individual EWM_CTRL bitfields |
Kojto | 90:cb3d968589d8 | 144 | */ |
Kojto | 90:cb3d968589d8 | 145 | |
Kojto | 90:cb3d968589d8 | 146 | /*! |
Kojto | 90:cb3d968589d8 | 147 | * @name Register EWM_CTRL, field EWMEN[0] (RW) |
Kojto | 90:cb3d968589d8 | 148 | * |
Kojto | 90:cb3d968589d8 | 149 | * This bit when set, enables the EWM module. This resets the EWM counter to |
Kojto | 90:cb3d968589d8 | 150 | * zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and |
Kojto | 90:cb3d968589d8 | 151 | * therefore it cannot be enabled until a reset occurs, due to the write-once |
Kojto | 90:cb3d968589d8 | 152 | * nature of this bit. |
Kojto | 90:cb3d968589d8 | 153 | */ |
Kojto | 90:cb3d968589d8 | 154 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 155 | #define BP_EWM_CTRL_EWMEN (0U) /*!< Bit position for EWM_CTRL_EWMEN. */ |
Kojto | 90:cb3d968589d8 | 156 | #define BM_EWM_CTRL_EWMEN (0x01U) /*!< Bit mask for EWM_CTRL_EWMEN. */ |
Kojto | 90:cb3d968589d8 | 157 | #define BS_EWM_CTRL_EWMEN (1U) /*!< Bit field size in bits for EWM_CTRL_EWMEN. */ |
Kojto | 90:cb3d968589d8 | 158 | |
Kojto | 90:cb3d968589d8 | 159 | /*! @brief Read current value of the EWM_CTRL_EWMEN field. */ |
Kojto | 90:cb3d968589d8 | 160 | #define BR_EWM_CTRL_EWMEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_EWMEN)) |
Kojto | 90:cb3d968589d8 | 161 | |
Kojto | 90:cb3d968589d8 | 162 | /*! @brief Format value for bitfield EWM_CTRL_EWMEN. */ |
Kojto | 90:cb3d968589d8 | 163 | #define BF_EWM_CTRL_EWMEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_EWMEN) & BM_EWM_CTRL_EWMEN) |
Kojto | 90:cb3d968589d8 | 164 | |
Kojto | 90:cb3d968589d8 | 165 | /*! @brief Set the EWMEN field to a new value. */ |
Kojto | 90:cb3d968589d8 | 166 | #define BW_EWM_CTRL_EWMEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_EWMEN) = (v)) |
Kojto | 90:cb3d968589d8 | 167 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 168 | |
Kojto | 90:cb3d968589d8 | 169 | /*! |
Kojto | 90:cb3d968589d8 | 170 | * @name Register EWM_CTRL, field ASSIN[1] (RW) |
Kojto | 90:cb3d968589d8 | 171 | * |
Kojto | 90:cb3d968589d8 | 172 | * Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit |
Kojto | 90:cb3d968589d8 | 173 | * inverts the assert state to a logic one. |
Kojto | 90:cb3d968589d8 | 174 | */ |
Kojto | 90:cb3d968589d8 | 175 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 176 | #define BP_EWM_CTRL_ASSIN (1U) /*!< Bit position for EWM_CTRL_ASSIN. */ |
Kojto | 90:cb3d968589d8 | 177 | #define BM_EWM_CTRL_ASSIN (0x02U) /*!< Bit mask for EWM_CTRL_ASSIN. */ |
Kojto | 90:cb3d968589d8 | 178 | #define BS_EWM_CTRL_ASSIN (1U) /*!< Bit field size in bits for EWM_CTRL_ASSIN. */ |
Kojto | 90:cb3d968589d8 | 179 | |
Kojto | 90:cb3d968589d8 | 180 | /*! @brief Read current value of the EWM_CTRL_ASSIN field. */ |
Kojto | 90:cb3d968589d8 | 181 | #define BR_EWM_CTRL_ASSIN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_ASSIN)) |
Kojto | 90:cb3d968589d8 | 182 | |
Kojto | 90:cb3d968589d8 | 183 | /*! @brief Format value for bitfield EWM_CTRL_ASSIN. */ |
Kojto | 90:cb3d968589d8 | 184 | #define BF_EWM_CTRL_ASSIN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_ASSIN) & BM_EWM_CTRL_ASSIN) |
Kojto | 90:cb3d968589d8 | 185 | |
Kojto | 90:cb3d968589d8 | 186 | /*! @brief Set the ASSIN field to a new value. */ |
Kojto | 90:cb3d968589d8 | 187 | #define BW_EWM_CTRL_ASSIN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_ASSIN) = (v)) |
Kojto | 90:cb3d968589d8 | 188 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 189 | |
Kojto | 90:cb3d968589d8 | 190 | /*! |
Kojto | 90:cb3d968589d8 | 191 | * @name Register EWM_CTRL, field INEN[2] (RW) |
Kojto | 90:cb3d968589d8 | 192 | * |
Kojto | 90:cb3d968589d8 | 193 | * This bit when set, enables the EWM_in port. |
Kojto | 90:cb3d968589d8 | 194 | */ |
Kojto | 90:cb3d968589d8 | 195 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 196 | #define BP_EWM_CTRL_INEN (2U) /*!< Bit position for EWM_CTRL_INEN. */ |
Kojto | 90:cb3d968589d8 | 197 | #define BM_EWM_CTRL_INEN (0x04U) /*!< Bit mask for EWM_CTRL_INEN. */ |
Kojto | 90:cb3d968589d8 | 198 | #define BS_EWM_CTRL_INEN (1U) /*!< Bit field size in bits for EWM_CTRL_INEN. */ |
Kojto | 90:cb3d968589d8 | 199 | |
Kojto | 90:cb3d968589d8 | 200 | /*! @brief Read current value of the EWM_CTRL_INEN field. */ |
Kojto | 90:cb3d968589d8 | 201 | #define BR_EWM_CTRL_INEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INEN)) |
Kojto | 90:cb3d968589d8 | 202 | |
Kojto | 90:cb3d968589d8 | 203 | /*! @brief Format value for bitfield EWM_CTRL_INEN. */ |
Kojto | 90:cb3d968589d8 | 204 | #define BF_EWM_CTRL_INEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_INEN) & BM_EWM_CTRL_INEN) |
Kojto | 90:cb3d968589d8 | 205 | |
Kojto | 90:cb3d968589d8 | 206 | /*! @brief Set the INEN field to a new value. */ |
Kojto | 90:cb3d968589d8 | 207 | #define BW_EWM_CTRL_INEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INEN) = (v)) |
Kojto | 90:cb3d968589d8 | 208 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 209 | |
Kojto | 90:cb3d968589d8 | 210 | /*! |
Kojto | 90:cb3d968589d8 | 211 | * @name Register EWM_CTRL, field INTEN[3] (RW) |
Kojto | 90:cb3d968589d8 | 212 | * |
Kojto | 90:cb3d968589d8 | 213 | * This bit when set and EWM_out is asserted, an interrupt request is generated. |
Kojto | 90:cb3d968589d8 | 214 | * To de-assert interrupt request, user should clear this bit by writing 0. |
Kojto | 90:cb3d968589d8 | 215 | */ |
Kojto | 90:cb3d968589d8 | 216 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 217 | #define BP_EWM_CTRL_INTEN (3U) /*!< Bit position for EWM_CTRL_INTEN. */ |
Kojto | 90:cb3d968589d8 | 218 | #define BM_EWM_CTRL_INTEN (0x08U) /*!< Bit mask for EWM_CTRL_INTEN. */ |
Kojto | 90:cb3d968589d8 | 219 | #define BS_EWM_CTRL_INTEN (1U) /*!< Bit field size in bits for EWM_CTRL_INTEN. */ |
Kojto | 90:cb3d968589d8 | 220 | |
Kojto | 90:cb3d968589d8 | 221 | /*! @brief Read current value of the EWM_CTRL_INTEN field. */ |
Kojto | 90:cb3d968589d8 | 222 | #define BR_EWM_CTRL_INTEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INTEN)) |
Kojto | 90:cb3d968589d8 | 223 | |
Kojto | 90:cb3d968589d8 | 224 | /*! @brief Format value for bitfield EWM_CTRL_INTEN. */ |
Kojto | 90:cb3d968589d8 | 225 | #define BF_EWM_CTRL_INTEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_INTEN) & BM_EWM_CTRL_INTEN) |
Kojto | 90:cb3d968589d8 | 226 | |
Kojto | 90:cb3d968589d8 | 227 | /*! @brief Set the INTEN field to a new value. */ |
Kojto | 90:cb3d968589d8 | 228 | #define BW_EWM_CTRL_INTEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INTEN) = (v)) |
Kojto | 90:cb3d968589d8 | 229 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 230 | |
Kojto | 90:cb3d968589d8 | 231 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 232 | * HW_EWM_SERV - Service Register |
Kojto | 90:cb3d968589d8 | 233 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 234 | |
Kojto | 90:cb3d968589d8 | 235 | /*! |
Kojto | 90:cb3d968589d8 | 236 | * @brief HW_EWM_SERV - Service Register (WORZ) |
Kojto | 90:cb3d968589d8 | 237 | * |
Kojto | 90:cb3d968589d8 | 238 | * Reset value: 0x00U |
Kojto | 90:cb3d968589d8 | 239 | * |
Kojto | 90:cb3d968589d8 | 240 | * The SERV register provides the interface from the CPU to the EWM module. It |
Kojto | 90:cb3d968589d8 | 241 | * is write-only and reads of this register return zero. |
Kojto | 90:cb3d968589d8 | 242 | */ |
Kojto | 90:cb3d968589d8 | 243 | typedef union _hw_ewm_serv |
Kojto | 90:cb3d968589d8 | 244 | { |
Kojto | 90:cb3d968589d8 | 245 | uint8_t U; |
Kojto | 90:cb3d968589d8 | 246 | struct _hw_ewm_serv_bitfields |
Kojto | 90:cb3d968589d8 | 247 | { |
Kojto | 90:cb3d968589d8 | 248 | uint8_t SERVICE : 8; /*!< [7:0] */ |
Kojto | 90:cb3d968589d8 | 249 | } B; |
Kojto | 90:cb3d968589d8 | 250 | } hw_ewm_serv_t; |
Kojto | 90:cb3d968589d8 | 251 | |
Kojto | 90:cb3d968589d8 | 252 | /*! |
Kojto | 90:cb3d968589d8 | 253 | * @name Constants and macros for entire EWM_SERV register |
Kojto | 90:cb3d968589d8 | 254 | */ |
Kojto | 90:cb3d968589d8 | 255 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 256 | #define HW_EWM_SERV_ADDR(x) ((x) + 0x1U) |
Kojto | 90:cb3d968589d8 | 257 | |
Kojto | 90:cb3d968589d8 | 258 | #define HW_EWM_SERV(x) (*(__O hw_ewm_serv_t *) HW_EWM_SERV_ADDR(x)) |
Kojto | 90:cb3d968589d8 | 259 | #define HW_EWM_SERV_RD(x) (HW_EWM_SERV(x).U) |
Kojto | 90:cb3d968589d8 | 260 | #define HW_EWM_SERV_WR(x, v) (HW_EWM_SERV(x).U = (v)) |
Kojto | 90:cb3d968589d8 | 261 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 262 | |
Kojto | 90:cb3d968589d8 | 263 | /* |
Kojto | 90:cb3d968589d8 | 264 | * Constants & macros for individual EWM_SERV bitfields |
Kojto | 90:cb3d968589d8 | 265 | */ |
Kojto | 90:cb3d968589d8 | 266 | |
Kojto | 90:cb3d968589d8 | 267 | /*! |
Kojto | 90:cb3d968589d8 | 268 | * @name Register EWM_SERV, field SERVICE[7:0] (WORZ) |
Kojto | 90:cb3d968589d8 | 269 | * |
Kojto | 90:cb3d968589d8 | 270 | * The EWM service mechanism requires the CPU to write two values to the SERV |
Kojto | 90:cb3d968589d8 | 271 | * register: a first data byte of 0xB4, followed by a second data byte of 0x2C. The |
Kojto | 90:cb3d968589d8 | 272 | * EWM service is illegal if either of the following conditions is true. The |
Kojto | 90:cb3d968589d8 | 273 | * first or second data byte is not written correctly. The second data byte is not |
Kojto | 90:cb3d968589d8 | 274 | * written within a fixed number of peripheral bus cycles of the first data byte. |
Kojto | 90:cb3d968589d8 | 275 | * This fixed number of cycles is called EWM_service_time. |
Kojto | 90:cb3d968589d8 | 276 | */ |
Kojto | 90:cb3d968589d8 | 277 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 278 | #define BP_EWM_SERV_SERVICE (0U) /*!< Bit position for EWM_SERV_SERVICE. */ |
Kojto | 90:cb3d968589d8 | 279 | #define BM_EWM_SERV_SERVICE (0xFFU) /*!< Bit mask for EWM_SERV_SERVICE. */ |
Kojto | 90:cb3d968589d8 | 280 | #define BS_EWM_SERV_SERVICE (8U) /*!< Bit field size in bits for EWM_SERV_SERVICE. */ |
Kojto | 90:cb3d968589d8 | 281 | |
Kojto | 90:cb3d968589d8 | 282 | /*! @brief Format value for bitfield EWM_SERV_SERVICE. */ |
Kojto | 90:cb3d968589d8 | 283 | #define BF_EWM_SERV_SERVICE(v) ((uint8_t)((uint8_t)(v) << BP_EWM_SERV_SERVICE) & BM_EWM_SERV_SERVICE) |
Kojto | 90:cb3d968589d8 | 284 | |
Kojto | 90:cb3d968589d8 | 285 | /*! @brief Set the SERVICE field to a new value. */ |
Kojto | 90:cb3d968589d8 | 286 | #define BW_EWM_SERV_SERVICE(x, v) (HW_EWM_SERV_WR(x, v)) |
Kojto | 90:cb3d968589d8 | 287 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 288 | |
Kojto | 90:cb3d968589d8 | 289 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 290 | * HW_EWM_CMPL - Compare Low Register |
Kojto | 90:cb3d968589d8 | 291 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 292 | |
Kojto | 90:cb3d968589d8 | 293 | /*! |
Kojto | 90:cb3d968589d8 | 294 | * @brief HW_EWM_CMPL - Compare Low Register (RW) |
Kojto | 90:cb3d968589d8 | 295 | * |
Kojto | 90:cb3d968589d8 | 296 | * Reset value: 0x00U |
Kojto | 90:cb3d968589d8 | 297 | * |
Kojto | 90:cb3d968589d8 | 298 | * The CMPL register is reset to zero after a CPU reset. This provides no |
Kojto | 90:cb3d968589d8 | 299 | * minimum time for the CPU to service the EWM counter. This register can be written |
Kojto | 90:cb3d968589d8 | 300 | * only once after a CPU reset. Writing this register more than once generates a |
Kojto | 90:cb3d968589d8 | 301 | * bus transfer error. |
Kojto | 90:cb3d968589d8 | 302 | */ |
Kojto | 90:cb3d968589d8 | 303 | typedef union _hw_ewm_cmpl |
Kojto | 90:cb3d968589d8 | 304 | { |
Kojto | 90:cb3d968589d8 | 305 | uint8_t U; |
Kojto | 90:cb3d968589d8 | 306 | struct _hw_ewm_cmpl_bitfields |
Kojto | 90:cb3d968589d8 | 307 | { |
Kojto | 90:cb3d968589d8 | 308 | uint8_t COMPAREL : 8; /*!< [7:0] */ |
Kojto | 90:cb3d968589d8 | 309 | } B; |
Kojto | 90:cb3d968589d8 | 310 | } hw_ewm_cmpl_t; |
Kojto | 90:cb3d968589d8 | 311 | |
Kojto | 90:cb3d968589d8 | 312 | /*! |
Kojto | 90:cb3d968589d8 | 313 | * @name Constants and macros for entire EWM_CMPL register |
Kojto | 90:cb3d968589d8 | 314 | */ |
Kojto | 90:cb3d968589d8 | 315 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 316 | #define HW_EWM_CMPL_ADDR(x) ((x) + 0x2U) |
Kojto | 90:cb3d968589d8 | 317 | |
Kojto | 90:cb3d968589d8 | 318 | #define HW_EWM_CMPL(x) (*(__IO hw_ewm_cmpl_t *) HW_EWM_CMPL_ADDR(x)) |
Kojto | 90:cb3d968589d8 | 319 | #define HW_EWM_CMPL_RD(x) (HW_EWM_CMPL(x).U) |
Kojto | 90:cb3d968589d8 | 320 | #define HW_EWM_CMPL_WR(x, v) (HW_EWM_CMPL(x).U = (v)) |
Kojto | 90:cb3d968589d8 | 321 | #define HW_EWM_CMPL_SET(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) | (v))) |
Kojto | 90:cb3d968589d8 | 322 | #define HW_EWM_CMPL_CLR(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) & ~(v))) |
Kojto | 90:cb3d968589d8 | 323 | #define HW_EWM_CMPL_TOG(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) ^ (v))) |
Kojto | 90:cb3d968589d8 | 324 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 325 | |
Kojto | 90:cb3d968589d8 | 326 | /* |
Kojto | 90:cb3d968589d8 | 327 | * Constants & macros for individual EWM_CMPL bitfields |
Kojto | 90:cb3d968589d8 | 328 | */ |
Kojto | 90:cb3d968589d8 | 329 | |
Kojto | 90:cb3d968589d8 | 330 | /*! |
Kojto | 90:cb3d968589d8 | 331 | * @name Register EWM_CMPL, field COMPAREL[7:0] (RW) |
Kojto | 90:cb3d968589d8 | 332 | * |
Kojto | 90:cb3d968589d8 | 333 | * To prevent runaway code from changing this field, software should write to |
Kojto | 90:cb3d968589d8 | 334 | * this field after a CPU reset even if the (default) minimum service time is |
Kojto | 90:cb3d968589d8 | 335 | * required. |
Kojto | 90:cb3d968589d8 | 336 | */ |
Kojto | 90:cb3d968589d8 | 337 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 338 | #define BP_EWM_CMPL_COMPAREL (0U) /*!< Bit position for EWM_CMPL_COMPAREL. */ |
Kojto | 90:cb3d968589d8 | 339 | #define BM_EWM_CMPL_COMPAREL (0xFFU) /*!< Bit mask for EWM_CMPL_COMPAREL. */ |
Kojto | 90:cb3d968589d8 | 340 | #define BS_EWM_CMPL_COMPAREL (8U) /*!< Bit field size in bits for EWM_CMPL_COMPAREL. */ |
Kojto | 90:cb3d968589d8 | 341 | |
Kojto | 90:cb3d968589d8 | 342 | /*! @brief Read current value of the EWM_CMPL_COMPAREL field. */ |
Kojto | 90:cb3d968589d8 | 343 | #define BR_EWM_CMPL_COMPAREL(x) (HW_EWM_CMPL(x).U) |
Kojto | 90:cb3d968589d8 | 344 | |
Kojto | 90:cb3d968589d8 | 345 | /*! @brief Format value for bitfield EWM_CMPL_COMPAREL. */ |
Kojto | 90:cb3d968589d8 | 346 | #define BF_EWM_CMPL_COMPAREL(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CMPL_COMPAREL) & BM_EWM_CMPL_COMPAREL) |
Kojto | 90:cb3d968589d8 | 347 | |
Kojto | 90:cb3d968589d8 | 348 | /*! @brief Set the COMPAREL field to a new value. */ |
Kojto | 90:cb3d968589d8 | 349 | #define BW_EWM_CMPL_COMPAREL(x, v) (HW_EWM_CMPL_WR(x, v)) |
Kojto | 90:cb3d968589d8 | 350 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 351 | |
Kojto | 90:cb3d968589d8 | 352 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 353 | * HW_EWM_CMPH - Compare High Register |
Kojto | 90:cb3d968589d8 | 354 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 355 | |
Kojto | 90:cb3d968589d8 | 356 | /*! |
Kojto | 90:cb3d968589d8 | 357 | * @brief HW_EWM_CMPH - Compare High Register (RW) |
Kojto | 90:cb3d968589d8 | 358 | * |
Kojto | 90:cb3d968589d8 | 359 | * Reset value: 0xFFU |
Kojto | 90:cb3d968589d8 | 360 | * |
Kojto | 90:cb3d968589d8 | 361 | * The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum |
Kojto | 90:cb3d968589d8 | 362 | * of 256 clocks time, for the CPU to service the EWM counter. This register can |
Kojto | 90:cb3d968589d8 | 363 | * be written only once after a CPU reset. Writing this register more than once |
Kojto | 90:cb3d968589d8 | 364 | * generates a bus transfer error. The valid values for CMPH are up to 0xFE |
Kojto | 90:cb3d968589d8 | 365 | * because the EWM counter never expires when CMPH = 0xFF. The expiration happens only |
Kojto | 90:cb3d968589d8 | 366 | * if EWM counter is greater than CMPH. |
Kojto | 90:cb3d968589d8 | 367 | */ |
Kojto | 90:cb3d968589d8 | 368 | typedef union _hw_ewm_cmph |
Kojto | 90:cb3d968589d8 | 369 | { |
Kojto | 90:cb3d968589d8 | 370 | uint8_t U; |
Kojto | 90:cb3d968589d8 | 371 | struct _hw_ewm_cmph_bitfields |
Kojto | 90:cb3d968589d8 | 372 | { |
Kojto | 90:cb3d968589d8 | 373 | uint8_t COMPAREH : 8; /*!< [7:0] */ |
Kojto | 90:cb3d968589d8 | 374 | } B; |
Kojto | 90:cb3d968589d8 | 375 | } hw_ewm_cmph_t; |
Kojto | 90:cb3d968589d8 | 376 | |
Kojto | 90:cb3d968589d8 | 377 | /*! |
Kojto | 90:cb3d968589d8 | 378 | * @name Constants and macros for entire EWM_CMPH register |
Kojto | 90:cb3d968589d8 | 379 | */ |
Kojto | 90:cb3d968589d8 | 380 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 381 | #define HW_EWM_CMPH_ADDR(x) ((x) + 0x3U) |
Kojto | 90:cb3d968589d8 | 382 | |
Kojto | 90:cb3d968589d8 | 383 | #define HW_EWM_CMPH(x) (*(__IO hw_ewm_cmph_t *) HW_EWM_CMPH_ADDR(x)) |
Kojto | 90:cb3d968589d8 | 384 | #define HW_EWM_CMPH_RD(x) (HW_EWM_CMPH(x).U) |
Kojto | 90:cb3d968589d8 | 385 | #define HW_EWM_CMPH_WR(x, v) (HW_EWM_CMPH(x).U = (v)) |
Kojto | 90:cb3d968589d8 | 386 | #define HW_EWM_CMPH_SET(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) | (v))) |
Kojto | 90:cb3d968589d8 | 387 | #define HW_EWM_CMPH_CLR(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) & ~(v))) |
Kojto | 90:cb3d968589d8 | 388 | #define HW_EWM_CMPH_TOG(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) ^ (v))) |
Kojto | 90:cb3d968589d8 | 389 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 390 | |
Kojto | 90:cb3d968589d8 | 391 | /* |
Kojto | 90:cb3d968589d8 | 392 | * Constants & macros for individual EWM_CMPH bitfields |
Kojto | 90:cb3d968589d8 | 393 | */ |
Kojto | 90:cb3d968589d8 | 394 | |
Kojto | 90:cb3d968589d8 | 395 | /*! |
Kojto | 90:cb3d968589d8 | 396 | * @name Register EWM_CMPH, field COMPAREH[7:0] (RW) |
Kojto | 90:cb3d968589d8 | 397 | * |
Kojto | 90:cb3d968589d8 | 398 | * To prevent runaway code from changing this field, software should write to |
Kojto | 90:cb3d968589d8 | 399 | * this field after a CPU reset even if the (default) maximum service time is |
Kojto | 90:cb3d968589d8 | 400 | * required. |
Kojto | 90:cb3d968589d8 | 401 | */ |
Kojto | 90:cb3d968589d8 | 402 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 403 | #define BP_EWM_CMPH_COMPAREH (0U) /*!< Bit position for EWM_CMPH_COMPAREH. */ |
Kojto | 90:cb3d968589d8 | 404 | #define BM_EWM_CMPH_COMPAREH (0xFFU) /*!< Bit mask for EWM_CMPH_COMPAREH. */ |
Kojto | 90:cb3d968589d8 | 405 | #define BS_EWM_CMPH_COMPAREH (8U) /*!< Bit field size in bits for EWM_CMPH_COMPAREH. */ |
Kojto | 90:cb3d968589d8 | 406 | |
Kojto | 90:cb3d968589d8 | 407 | /*! @brief Read current value of the EWM_CMPH_COMPAREH field. */ |
Kojto | 90:cb3d968589d8 | 408 | #define BR_EWM_CMPH_COMPAREH(x) (HW_EWM_CMPH(x).U) |
Kojto | 90:cb3d968589d8 | 409 | |
Kojto | 90:cb3d968589d8 | 410 | /*! @brief Format value for bitfield EWM_CMPH_COMPAREH. */ |
Kojto | 90:cb3d968589d8 | 411 | #define BF_EWM_CMPH_COMPAREH(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CMPH_COMPAREH) & BM_EWM_CMPH_COMPAREH) |
Kojto | 90:cb3d968589d8 | 412 | |
Kojto | 90:cb3d968589d8 | 413 | /*! @brief Set the COMPAREH field to a new value. */ |
Kojto | 90:cb3d968589d8 | 414 | #define BW_EWM_CMPH_COMPAREH(x, v) (HW_EWM_CMPH_WR(x, v)) |
Kojto | 90:cb3d968589d8 | 415 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 416 | |
Kojto | 90:cb3d968589d8 | 417 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 418 | * hw_ewm_t - module struct |
Kojto | 90:cb3d968589d8 | 419 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 420 | /*! |
Kojto | 90:cb3d968589d8 | 421 | * @brief All EWM module registers. |
Kojto | 90:cb3d968589d8 | 422 | */ |
Kojto | 90:cb3d968589d8 | 423 | #pragma pack(1) |
Kojto | 90:cb3d968589d8 | 424 | typedef struct _hw_ewm |
Kojto | 90:cb3d968589d8 | 425 | { |
Kojto | 90:cb3d968589d8 | 426 | __IO hw_ewm_ctrl_t CTRL; /*!< [0x0] Control Register */ |
Kojto | 90:cb3d968589d8 | 427 | __O hw_ewm_serv_t SERV; /*!< [0x1] Service Register */ |
Kojto | 90:cb3d968589d8 | 428 | __IO hw_ewm_cmpl_t CMPL; /*!< [0x2] Compare Low Register */ |
Kojto | 90:cb3d968589d8 | 429 | __IO hw_ewm_cmph_t CMPH; /*!< [0x3] Compare High Register */ |
Kojto | 90:cb3d968589d8 | 430 | } hw_ewm_t; |
Kojto | 90:cb3d968589d8 | 431 | #pragma pack() |
Kojto | 90:cb3d968589d8 | 432 | |
Kojto | 90:cb3d968589d8 | 433 | /*! @brief Macro to access all EWM registers. */ |
Kojto | 90:cb3d968589d8 | 434 | /*! @param x EWM module instance base address. */ |
Kojto | 90:cb3d968589d8 | 435 | /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, |
Kojto | 90:cb3d968589d8 | 436 | * use the '&' operator, like <code>&HW_EWM(EWM_BASE)</code>. */ |
Kojto | 90:cb3d968589d8 | 437 | #define HW_EWM(x) (*(hw_ewm_t *)(x)) |
Kojto | 90:cb3d968589d8 | 438 | |
Kojto | 90:cb3d968589d8 | 439 | #endif /* __HW_EWM_REGISTERS_H__ */ |
Kojto | 90:cb3d968589d8 | 440 | /* EOF */ |