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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_cmp.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:
Kojto
Date:
Wed Aug 05 13:16:35 2015 +0100
Revision:
104:b9ad9a133dc7
Parent:
90:cb3d968589d8 
Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /*
Kojto 90:cb3d968589d8 2 ** ###################################################################
Kojto 90:cb3d968589d8 3 ** Compilers: Keil ARM C/C++ Compiler
Kojto 90:cb3d968589d8 4 ** Freescale C/C++ for Embedded ARM
Kojto 90:cb3d968589d8 5 ** GNU C Compiler
Kojto 90:cb3d968589d8 6 ** IAR ANSI C/C++ Compiler for ARM
Kojto 90:cb3d968589d8 7 **
Kojto 90:cb3d968589d8 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto 90:cb3d968589d8 9 ** Version: rev. 2.5, 2014-02-10
Kojto 90:cb3d968589d8 10 ** Build: b140604
Kojto 90:cb3d968589d8 11 **
Kojto 90:cb3d968589d8 12 ** Abstract:
Kojto 90:cb3d968589d8 13 ** Extension to the CMSIS register access layer header.
Kojto 90:cb3d968589d8 14 **
Kojto 90:cb3d968589d8 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto 90:cb3d968589d8 16 ** All rights reserved.
Kojto 90:cb3d968589d8 17 **
Kojto 90:cb3d968589d8 18 ** Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 19 ** are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 20 **
Kojto 90:cb3d968589d8 21 ** o Redistributions of source code must retain the above copyright notice, this list
Kojto 90:cb3d968589d8 22 ** of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 23 **
Kojto 90:cb3d968589d8 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto 90:cb3d968589d8 25 ** list of conditions and the following disclaimer in the documentation and/or
Kojto 90:cb3d968589d8 26 ** other materials provided with the distribution.
Kojto 90:cb3d968589d8 27 **
Kojto 90:cb3d968589d8 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto 90:cb3d968589d8 29 ** contributors may be used to endorse or promote products derived from this
Kojto 90:cb3d968589d8 30 ** software without specific prior written permission.
Kojto 90:cb3d968589d8 31 **
Kojto 90:cb3d968589d8 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 90:cb3d968589d8 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 90:cb3d968589d8 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 90:cb3d968589d8 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 90:cb3d968589d8 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 90:cb3d968589d8 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 90:cb3d968589d8 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 90:cb3d968589d8 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 90:cb3d968589d8 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 42 **
Kojto 90:cb3d968589d8 43 ** http: www.freescale.com
Kojto 90:cb3d968589d8 44 ** mail: support@freescale.com
Kojto 90:cb3d968589d8 45 **
Kojto 90:cb3d968589d8 46 ** Revisions:
Kojto 90:cb3d968589d8 47 ** - rev. 1.0 (2013-08-12)
Kojto 90:cb3d968589d8 48 ** Initial version.
Kojto 90:cb3d968589d8 49 ** - rev. 2.0 (2013-10-29)
Kojto 90:cb3d968589d8 50 ** Register accessor macros added to the memory map.
Kojto 90:cb3d968589d8 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto 90:cb3d968589d8 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto 90:cb3d968589d8 53 ** System initialization updated.
Kojto 90:cb3d968589d8 54 ** MCG - registers updated.
Kojto 90:cb3d968589d8 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto 90:cb3d968589d8 56 ** - rev. 2.1 (2013-10-30)
Kojto 90:cb3d968589d8 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto 90:cb3d968589d8 58 ** - rev. 2.2 (2013-12-09)
Kojto 90:cb3d968589d8 59 ** DMA - EARS register removed.
Kojto 90:cb3d968589d8 60 ** AIPS0, AIPS1 - MPRA register updated.
Kojto 90:cb3d968589d8 61 ** - rev. 2.3 (2014-01-24)
Kojto 90:cb3d968589d8 62 ** Update according to reference manual rev. 2
Kojto 90:cb3d968589d8 63 ** ENET, MCG, MCM, SIM, USB - registers updated
Kojto 90:cb3d968589d8 64 ** - rev. 2.4 (2014-02-10)
Kojto 90:cb3d968589d8 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 67 ** - rev. 2.5 (2014-02-10)
Kojto 90:cb3d968589d8 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto 90:cb3d968589d8 71 **
Kojto 90:cb3d968589d8 72 ** ###################################################################
Kojto 90:cb3d968589d8 73 */
Kojto 90:cb3d968589d8 74
Kojto 90:cb3d968589d8 75 /*
Kojto 90:cb3d968589d8 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto 90:cb3d968589d8 77 *
Kojto 90:cb3d968589d8 78 * This file was generated automatically and any changes may be lost.
Kojto 90:cb3d968589d8 79 */
Kojto 90:cb3d968589d8 80 #ifndef __HW_CMP_REGISTERS_H__
Kojto 90:cb3d968589d8 81 #define __HW_CMP_REGISTERS_H__
Kojto 90:cb3d968589d8 82
Kojto 90:cb3d968589d8 83 #include "MK64F12.h"
Kojto 90:cb3d968589d8 84 #include "fsl_bitaccess.h"
Kojto 90:cb3d968589d8 85
Kojto 90:cb3d968589d8 86 /*
Kojto 90:cb3d968589d8 87 * MK64F12 CMP
Kojto 90:cb3d968589d8 88 *
Kojto 90:cb3d968589d8 89 * High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
Kojto 90:cb3d968589d8 90 *
Kojto 90:cb3d968589d8 91 * Registers defined in this header file:
Kojto 90:cb3d968589d8 92 * - HW_CMP_CR0 - CMP Control Register 0
Kojto 90:cb3d968589d8 93 * - HW_CMP_CR1 - CMP Control Register 1
Kojto 90:cb3d968589d8 94 * - HW_CMP_FPR - CMP Filter Period Register
Kojto 90:cb3d968589d8 95 * - HW_CMP_SCR - CMP Status and Control Register
Kojto 90:cb3d968589d8 96 * - HW_CMP_DACCR - DAC Control Register
Kojto 90:cb3d968589d8 97 * - HW_CMP_MUXCR - MUX Control Register
Kojto 90:cb3d968589d8 98 *
Kojto 90:cb3d968589d8 99 * - hw_cmp_t - Struct containing all module registers.
Kojto 90:cb3d968589d8 100 */
Kojto 90:cb3d968589d8 101
Kojto 90:cb3d968589d8 102 #define HW_CMP_INSTANCE_COUNT (3U) /*!< Number of instances of the CMP module. */
Kojto 90:cb3d968589d8 103 #define HW_CMP0 (0U) /*!< Instance number for CMP0. */
Kojto 90:cb3d968589d8 104 #define HW_CMP1 (1U) /*!< Instance number for CMP1. */
Kojto 90:cb3d968589d8 105 #define HW_CMP2 (2U) /*!< Instance number for CMP2. */
Kojto 90:cb3d968589d8 106
Kojto 90:cb3d968589d8 107 /*******************************************************************************
Kojto 90:cb3d968589d8 108 * HW_CMP_CR0 - CMP Control Register 0
Kojto 90:cb3d968589d8 109 ******************************************************************************/
Kojto 90:cb3d968589d8 110
Kojto 90:cb3d968589d8 111 /*!
Kojto 90:cb3d968589d8 112 * @brief HW_CMP_CR0 - CMP Control Register 0 (RW)
Kojto 90:cb3d968589d8 113 *
Kojto 90:cb3d968589d8 114 * Reset value: 0x00U
Kojto 90:cb3d968589d8 115 */
Kojto 90:cb3d968589d8 116 typedef union _hw_cmp_cr0
Kojto 90:cb3d968589d8 117 {
Kojto 90:cb3d968589d8 118 uint8_t U;
Kojto 90:cb3d968589d8 119 struct _hw_cmp_cr0_bitfields
Kojto 90:cb3d968589d8 120 {
Kojto 90:cb3d968589d8 121 uint8_t HYSTCTR : 2; /*!< [1:0] Comparator hard block hysteresis
Kojto 90:cb3d968589d8 122 * control */
Kojto 90:cb3d968589d8 123 uint8_t RESERVED0 : 2; /*!< [3:2] */
Kojto 90:cb3d968589d8 124 uint8_t FILTER_CNT : 3; /*!< [6:4] Filter Sample Count */
Kojto 90:cb3d968589d8 125 uint8_t RESERVED1 : 1; /*!< [7] */
Kojto 90:cb3d968589d8 126 } B;
Kojto 90:cb3d968589d8 127 } hw_cmp_cr0_t;
Kojto 90:cb3d968589d8 128
Kojto 90:cb3d968589d8 129 /*!
Kojto 90:cb3d968589d8 130 * @name Constants and macros for entire CMP_CR0 register
Kojto 90:cb3d968589d8 131 */
Kojto 90:cb3d968589d8 132 /*@{*/
Kojto 90:cb3d968589d8 133 #define HW_CMP_CR0_ADDR(x) ((x) + 0x0U)
Kojto 90:cb3d968589d8 134
Kojto 90:cb3d968589d8 135 #define HW_CMP_CR0(x) (*(__IO hw_cmp_cr0_t *) HW_CMP_CR0_ADDR(x))
Kojto 90:cb3d968589d8 136 #define HW_CMP_CR0_RD(x) (HW_CMP_CR0(x).U)
Kojto 90:cb3d968589d8 137 #define HW_CMP_CR0_WR(x, v) (HW_CMP_CR0(x).U = (v))
Kojto 90:cb3d968589d8 138 #define HW_CMP_CR0_SET(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) | (v)))
Kojto 90:cb3d968589d8 139 #define HW_CMP_CR0_CLR(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 140 #define HW_CMP_CR0_TOG(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 141 /*@}*/
Kojto 90:cb3d968589d8 142
Kojto 90:cb3d968589d8 143 /*
Kojto 90:cb3d968589d8 144 * Constants & macros for individual CMP_CR0 bitfields
Kojto 90:cb3d968589d8 145 */
Kojto 90:cb3d968589d8 146
Kojto 90:cb3d968589d8 147 /*!
Kojto 90:cb3d968589d8 148 * @name Register CMP_CR0, field HYSTCTR[1:0] (RW)
Kojto 90:cb3d968589d8 149 *
Kojto 90:cb3d968589d8 150 * Defines the programmable hysteresis level. The hysteresis values associated
Kojto 90:cb3d968589d8 151 * with each level are device-specific. See the Data Sheet of the device for the
Kojto 90:cb3d968589d8 152 * exact values.
Kojto 90:cb3d968589d8 153 *
Kojto 90:cb3d968589d8 154 * Values:
Kojto 90:cb3d968589d8 155 * - 00 - Level 0
Kojto 90:cb3d968589d8 156 * - 01 - Level 1
Kojto 90:cb3d968589d8 157 * - 10 - Level 2
Kojto 90:cb3d968589d8 158 * - 11 - Level 3
Kojto 90:cb3d968589d8 159 */
Kojto 90:cb3d968589d8 160 /*@{*/
Kojto 90:cb3d968589d8 161 #define BP_CMP_CR0_HYSTCTR (0U) /*!< Bit position for CMP_CR0_HYSTCTR. */
Kojto 90:cb3d968589d8 162 #define BM_CMP_CR0_HYSTCTR (0x03U) /*!< Bit mask for CMP_CR0_HYSTCTR. */
Kojto 90:cb3d968589d8 163 #define BS_CMP_CR0_HYSTCTR (2U) /*!< Bit field size in bits for CMP_CR0_HYSTCTR. */
Kojto 90:cb3d968589d8 164
Kojto 90:cb3d968589d8 165 /*! @brief Read current value of the CMP_CR0_HYSTCTR field. */
Kojto 90:cb3d968589d8 166 #define BR_CMP_CR0_HYSTCTR(x) (HW_CMP_CR0(x).B.HYSTCTR)
Kojto 90:cb3d968589d8 167
Kojto 90:cb3d968589d8 168 /*! @brief Format value for bitfield CMP_CR0_HYSTCTR. */
Kojto 90:cb3d968589d8 169 #define BF_CMP_CR0_HYSTCTR(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR0_HYSTCTR) & BM_CMP_CR0_HYSTCTR)
Kojto 90:cb3d968589d8 170
Kojto 90:cb3d968589d8 171 /*! @brief Set the HYSTCTR field to a new value. */
Kojto 90:cb3d968589d8 172 #define BW_CMP_CR0_HYSTCTR(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_HYSTCTR) | BF_CMP_CR0_HYSTCTR(v)))
Kojto 90:cb3d968589d8 173 /*@}*/
Kojto 90:cb3d968589d8 174
Kojto 90:cb3d968589d8 175 /*!
Kojto 90:cb3d968589d8 176 * @name Register CMP_CR0, field FILTER_CNT[6:4] (RW)
Kojto 90:cb3d968589d8 177 *
Kojto 90:cb3d968589d8 178 * Represents the number of consecutive samples that must agree prior to the
Kojto 90:cb3d968589d8 179 * comparator ouput filter accepting a new output state. For information regarding
Kojto 90:cb3d968589d8 180 * filter programming and latency, see the Functional descriptionThe CMP module
Kojto 90:cb3d968589d8 181 * can be used to compare two analog input voltages applied to INP and INM. .
Kojto 90:cb3d968589d8 182 *
Kojto 90:cb3d968589d8 183 * Values:
Kojto 90:cb3d968589d8 184 * - 000 - Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a
Kojto 90:cb3d968589d8 185 * legal state, and is not recommended. If SE = 0, COUT = COUTA.
Kojto 90:cb3d968589d8 186 * - 001 - One sample must agree. The comparator output is simply sampled.
Kojto 90:cb3d968589d8 187 * - 010 - 2 consecutive samples must agree.
Kojto 90:cb3d968589d8 188 * - 011 - 3 consecutive samples must agree.
Kojto 90:cb3d968589d8 189 * - 100 - 4 consecutive samples must agree.
Kojto 90:cb3d968589d8 190 * - 101 - 5 consecutive samples must agree.
Kojto 90:cb3d968589d8 191 * - 110 - 6 consecutive samples must agree.
Kojto 90:cb3d968589d8 192 * - 111 - 7 consecutive samples must agree.
Kojto 90:cb3d968589d8 193 */
Kojto 90:cb3d968589d8 194 /*@{*/
Kojto 90:cb3d968589d8 195 #define BP_CMP_CR0_FILTER_CNT (4U) /*!< Bit position for CMP_CR0_FILTER_CNT. */
Kojto 90:cb3d968589d8 196 #define BM_CMP_CR0_FILTER_CNT (0x70U) /*!< Bit mask for CMP_CR0_FILTER_CNT. */
Kojto 90:cb3d968589d8 197 #define BS_CMP_CR0_FILTER_CNT (3U) /*!< Bit field size in bits for CMP_CR0_FILTER_CNT. */
Kojto 90:cb3d968589d8 198
Kojto 90:cb3d968589d8 199 /*! @brief Read current value of the CMP_CR0_FILTER_CNT field. */
Kojto 90:cb3d968589d8 200 #define BR_CMP_CR0_FILTER_CNT(x) (HW_CMP_CR0(x).B.FILTER_CNT)
Kojto 90:cb3d968589d8 201
Kojto 90:cb3d968589d8 202 /*! @brief Format value for bitfield CMP_CR0_FILTER_CNT. */
Kojto 90:cb3d968589d8 203 #define BF_CMP_CR0_FILTER_CNT(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR0_FILTER_CNT) & BM_CMP_CR0_FILTER_CNT)
Kojto 90:cb3d968589d8 204
Kojto 90:cb3d968589d8 205 /*! @brief Set the FILTER_CNT field to a new value. */
Kojto 90:cb3d968589d8 206 #define BW_CMP_CR0_FILTER_CNT(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_FILTER_CNT) | BF_CMP_CR0_FILTER_CNT(v)))
Kojto 90:cb3d968589d8 207 /*@}*/
Kojto 90:cb3d968589d8 208
Kojto 90:cb3d968589d8 209 /*******************************************************************************
Kojto 90:cb3d968589d8 210 * HW_CMP_CR1 - CMP Control Register 1
Kojto 90:cb3d968589d8 211 ******************************************************************************/
Kojto 90:cb3d968589d8 212
Kojto 90:cb3d968589d8 213 /*!
Kojto 90:cb3d968589d8 214 * @brief HW_CMP_CR1 - CMP Control Register 1 (RW)
Kojto 90:cb3d968589d8 215 *
Kojto 90:cb3d968589d8 216 * Reset value: 0x00U
Kojto 90:cb3d968589d8 217 */
Kojto 90:cb3d968589d8 218 typedef union _hw_cmp_cr1
Kojto 90:cb3d968589d8 219 {
Kojto 90:cb3d968589d8 220 uint8_t U;
Kojto 90:cb3d968589d8 221 struct _hw_cmp_cr1_bitfields
Kojto 90:cb3d968589d8 222 {
Kojto 90:cb3d968589d8 223 uint8_t EN : 1; /*!< [0] Comparator Module Enable */
Kojto 90:cb3d968589d8 224 uint8_t OPE : 1; /*!< [1] Comparator Output Pin Enable */
Kojto 90:cb3d968589d8 225 uint8_t COS : 1; /*!< [2] Comparator Output Select */
Kojto 90:cb3d968589d8 226 uint8_t INV : 1; /*!< [3] Comparator INVERT */
Kojto 90:cb3d968589d8 227 uint8_t PMODE : 1; /*!< [4] Power Mode Select */
Kojto 90:cb3d968589d8 228 uint8_t RESERVED0 : 1; /*!< [5] */
Kojto 90:cb3d968589d8 229 uint8_t WE : 1; /*!< [6] Windowing Enable */
Kojto 90:cb3d968589d8 230 uint8_t SE : 1; /*!< [7] Sample Enable */
Kojto 90:cb3d968589d8 231 } B;
Kojto 90:cb3d968589d8 232 } hw_cmp_cr1_t;
Kojto 90:cb3d968589d8 233
Kojto 90:cb3d968589d8 234 /*!
Kojto 90:cb3d968589d8 235 * @name Constants and macros for entire CMP_CR1 register
Kojto 90:cb3d968589d8 236 */
Kojto 90:cb3d968589d8 237 /*@{*/
Kojto 90:cb3d968589d8 238 #define HW_CMP_CR1_ADDR(x) ((x) + 0x1U)
Kojto 90:cb3d968589d8 239
Kojto 90:cb3d968589d8 240 #define HW_CMP_CR1(x) (*(__IO hw_cmp_cr1_t *) HW_CMP_CR1_ADDR(x))
Kojto 90:cb3d968589d8 241 #define HW_CMP_CR1_RD(x) (HW_CMP_CR1(x).U)
Kojto 90:cb3d968589d8 242 #define HW_CMP_CR1_WR(x, v) (HW_CMP_CR1(x).U = (v))
Kojto 90:cb3d968589d8 243 #define HW_CMP_CR1_SET(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) | (v)))
Kojto 90:cb3d968589d8 244 #define HW_CMP_CR1_CLR(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 245 #define HW_CMP_CR1_TOG(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 246 /*@}*/
Kojto 90:cb3d968589d8 247
Kojto 90:cb3d968589d8 248 /*
Kojto 90:cb3d968589d8 249 * Constants & macros for individual CMP_CR1 bitfields
Kojto 90:cb3d968589d8 250 */
Kojto 90:cb3d968589d8 251
Kojto 90:cb3d968589d8 252 /*!
Kojto 90:cb3d968589d8 253 * @name Register CMP_CR1, field EN[0] (RW)
Kojto 90:cb3d968589d8 254 *
Kojto 90:cb3d968589d8 255 * Enables the Analog Comparator module. When the module is not enabled, it
Kojto 90:cb3d968589d8 256 * remains in the off state, and consumes no power. When the user selects the same
Kojto 90:cb3d968589d8 257 * input from analog mux to the positive and negative port, the comparator is
Kojto 90:cb3d968589d8 258 * disabled automatically.
Kojto 90:cb3d968589d8 259 *
Kojto 90:cb3d968589d8 260 * Values:
Kojto 90:cb3d968589d8 261 * - 0 - Analog Comparator is disabled.
Kojto 90:cb3d968589d8 262 * - 1 - Analog Comparator is enabled.
Kojto 90:cb3d968589d8 263 */
Kojto 90:cb3d968589d8 264 /*@{*/
Kojto 90:cb3d968589d8 265 #define BP_CMP_CR1_EN (0U) /*!< Bit position for CMP_CR1_EN. */
Kojto 90:cb3d968589d8 266 #define BM_CMP_CR1_EN (0x01U) /*!< Bit mask for CMP_CR1_EN. */
Kojto 90:cb3d968589d8 267 #define BS_CMP_CR1_EN (1U) /*!< Bit field size in bits for CMP_CR1_EN. */
Kojto 90:cb3d968589d8 268
Kojto 90:cb3d968589d8 269 /*! @brief Read current value of the CMP_CR1_EN field. */
Kojto 90:cb3d968589d8 270 #define BR_CMP_CR1_EN(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN))
Kojto 90:cb3d968589d8 271
Kojto 90:cb3d968589d8 272 /*! @brief Format value for bitfield CMP_CR1_EN. */
Kojto 90:cb3d968589d8 273 #define BF_CMP_CR1_EN(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_EN) & BM_CMP_CR1_EN)
Kojto 90:cb3d968589d8 274
Kojto 90:cb3d968589d8 275 /*! @brief Set the EN field to a new value. */
Kojto 90:cb3d968589d8 276 #define BW_CMP_CR1_EN(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN) = (v))
Kojto 90:cb3d968589d8 277 /*@}*/
Kojto 90:cb3d968589d8 278
Kojto 90:cb3d968589d8 279 /*!
Kojto 90:cb3d968589d8 280 * @name Register CMP_CR1, field OPE[1] (RW)
Kojto 90:cb3d968589d8 281 *
Kojto 90:cb3d968589d8 282 * Values:
Kojto 90:cb3d968589d8 283 * - 0 - CMPO is not available on the associated CMPO output pin. If the
Kojto 90:cb3d968589d8 284 * comparator does not own the pin, this field has no effect.
Kojto 90:cb3d968589d8 285 * - 1 - CMPO is available on the associated CMPO output pin. The comparator
Kojto 90:cb3d968589d8 286 * output (CMPO) is driven out on the associated CMPO output pin if the
Kojto 90:cb3d968589d8 287 * comparator owns the pin. If the comparator does not own the field, this bit has no
Kojto 90:cb3d968589d8 288 * effect.
Kojto 90:cb3d968589d8 289 */
Kojto 90:cb3d968589d8 290 /*@{*/
Kojto 90:cb3d968589d8 291 #define BP_CMP_CR1_OPE (1U) /*!< Bit position for CMP_CR1_OPE. */
Kojto 90:cb3d968589d8 292 #define BM_CMP_CR1_OPE (0x02U) /*!< Bit mask for CMP_CR1_OPE. */
Kojto 90:cb3d968589d8 293 #define BS_CMP_CR1_OPE (1U) /*!< Bit field size in bits for CMP_CR1_OPE. */
Kojto 90:cb3d968589d8 294
Kojto 90:cb3d968589d8 295 /*! @brief Read current value of the CMP_CR1_OPE field. */
Kojto 90:cb3d968589d8 296 #define BR_CMP_CR1_OPE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE))
Kojto 90:cb3d968589d8 297
Kojto 90:cb3d968589d8 298 /*! @brief Format value for bitfield CMP_CR1_OPE. */
Kojto 90:cb3d968589d8 299 #define BF_CMP_CR1_OPE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_OPE) & BM_CMP_CR1_OPE)
Kojto 90:cb3d968589d8 300
Kojto 90:cb3d968589d8 301 /*! @brief Set the OPE field to a new value. */
Kojto 90:cb3d968589d8 302 #define BW_CMP_CR1_OPE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE) = (v))
Kojto 90:cb3d968589d8 303 /*@}*/
Kojto 90:cb3d968589d8 304
Kojto 90:cb3d968589d8 305 /*!
Kojto 90:cb3d968589d8 306 * @name Register CMP_CR1, field COS[2] (RW)
Kojto 90:cb3d968589d8 307 *
Kojto 90:cb3d968589d8 308 * Values:
Kojto 90:cb3d968589d8 309 * - 0 - Set the filtered comparator output (CMPO) to equal COUT.
Kojto 90:cb3d968589d8 310 * - 1 - Set the unfiltered comparator output (CMPO) to equal COUTA.
Kojto 90:cb3d968589d8 311 */
Kojto 90:cb3d968589d8 312 /*@{*/
Kojto 90:cb3d968589d8 313 #define BP_CMP_CR1_COS (2U) /*!< Bit position for CMP_CR1_COS. */
Kojto 90:cb3d968589d8 314 #define BM_CMP_CR1_COS (0x04U) /*!< Bit mask for CMP_CR1_COS. */
Kojto 90:cb3d968589d8 315 #define BS_CMP_CR1_COS (1U) /*!< Bit field size in bits for CMP_CR1_COS. */
Kojto 90:cb3d968589d8 316
Kojto 90:cb3d968589d8 317 /*! @brief Read current value of the CMP_CR1_COS field. */
Kojto 90:cb3d968589d8 318 #define BR_CMP_CR1_COS(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS))
Kojto 90:cb3d968589d8 319
Kojto 90:cb3d968589d8 320 /*! @brief Format value for bitfield CMP_CR1_COS. */
Kojto 90:cb3d968589d8 321 #define BF_CMP_CR1_COS(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_COS) & BM_CMP_CR1_COS)
Kojto 90:cb3d968589d8 322
Kojto 90:cb3d968589d8 323 /*! @brief Set the COS field to a new value. */
Kojto 90:cb3d968589d8 324 #define BW_CMP_CR1_COS(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS) = (v))
Kojto 90:cb3d968589d8 325 /*@}*/
Kojto 90:cb3d968589d8 326
Kojto 90:cb3d968589d8 327 /*!
Kojto 90:cb3d968589d8 328 * @name Register CMP_CR1, field INV[3] (RW)
Kojto 90:cb3d968589d8 329 *
Kojto 90:cb3d968589d8 330 * Allows selection of the polarity of the analog comparator function. It is
Kojto 90:cb3d968589d8 331 * also driven to the COUT output, on both the device pin and as SCR[COUT], when
Kojto 90:cb3d968589d8 332 * OPE=0.
Kojto 90:cb3d968589d8 333 *
Kojto 90:cb3d968589d8 334 * Values:
Kojto 90:cb3d968589d8 335 * - 0 - Does not invert the comparator output.
Kojto 90:cb3d968589d8 336 * - 1 - Inverts the comparator output.
Kojto 90:cb3d968589d8 337 */
Kojto 90:cb3d968589d8 338 /*@{*/
Kojto 90:cb3d968589d8 339 #define BP_CMP_CR1_INV (3U) /*!< Bit position for CMP_CR1_INV. */
Kojto 90:cb3d968589d8 340 #define BM_CMP_CR1_INV (0x08U) /*!< Bit mask for CMP_CR1_INV. */
Kojto 90:cb3d968589d8 341 #define BS_CMP_CR1_INV (1U) /*!< Bit field size in bits for CMP_CR1_INV. */
Kojto 90:cb3d968589d8 342
Kojto 90:cb3d968589d8 343 /*! @brief Read current value of the CMP_CR1_INV field. */
Kojto 90:cb3d968589d8 344 #define BR_CMP_CR1_INV(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV))
Kojto 90:cb3d968589d8 345
Kojto 90:cb3d968589d8 346 /*! @brief Format value for bitfield CMP_CR1_INV. */
Kojto 90:cb3d968589d8 347 #define BF_CMP_CR1_INV(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_INV) & BM_CMP_CR1_INV)
Kojto 90:cb3d968589d8 348
Kojto 90:cb3d968589d8 349 /*! @brief Set the INV field to a new value. */
Kojto 90:cb3d968589d8 350 #define BW_CMP_CR1_INV(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV) = (v))
Kojto 90:cb3d968589d8 351 /*@}*/
Kojto 90:cb3d968589d8 352
Kojto 90:cb3d968589d8 353 /*!
Kojto 90:cb3d968589d8 354 * @name Register CMP_CR1, field PMODE[4] (RW)
Kojto 90:cb3d968589d8 355 *
Kojto 90:cb3d968589d8 356 * See the electrical specifications table in the device Data Sheet for details.
Kojto 90:cb3d968589d8 357 *
Kojto 90:cb3d968589d8 358 * Values:
Kojto 90:cb3d968589d8 359 * - 0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower
Kojto 90:cb3d968589d8 360 * output propagation delay and lower current consumption.
Kojto 90:cb3d968589d8 361 * - 1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has faster
Kojto 90:cb3d968589d8 362 * output propagation delay and higher current consumption.
Kojto 90:cb3d968589d8 363 */
Kojto 90:cb3d968589d8 364 /*@{*/
Kojto 90:cb3d968589d8 365 #define BP_CMP_CR1_PMODE (4U) /*!< Bit position for CMP_CR1_PMODE. */
Kojto 90:cb3d968589d8 366 #define BM_CMP_CR1_PMODE (0x10U) /*!< Bit mask for CMP_CR1_PMODE. */
Kojto 90:cb3d968589d8 367 #define BS_CMP_CR1_PMODE (1U) /*!< Bit field size in bits for CMP_CR1_PMODE. */
Kojto 90:cb3d968589d8 368
Kojto 90:cb3d968589d8 369 /*! @brief Read current value of the CMP_CR1_PMODE field. */
Kojto 90:cb3d968589d8 370 #define BR_CMP_CR1_PMODE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE))
Kojto 90:cb3d968589d8 371
Kojto 90:cb3d968589d8 372 /*! @brief Format value for bitfield CMP_CR1_PMODE. */
Kojto 90:cb3d968589d8 373 #define BF_CMP_CR1_PMODE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_PMODE) & BM_CMP_CR1_PMODE)
Kojto 90:cb3d968589d8 374
Kojto 90:cb3d968589d8 375 /*! @brief Set the PMODE field to a new value. */
Kojto 90:cb3d968589d8 376 #define BW_CMP_CR1_PMODE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE) = (v))
Kojto 90:cb3d968589d8 377 /*@}*/
Kojto 90:cb3d968589d8 378
Kojto 90:cb3d968589d8 379 /*!
Kojto 90:cb3d968589d8 380 * @name Register CMP_CR1, field WE[6] (RW)
Kojto 90:cb3d968589d8 381 *
Kojto 90:cb3d968589d8 382 * At any given time, either SE or WE can be set. If a write to this register
Kojto 90:cb3d968589d8 383 * attempts to set both, then SE is set and WE is cleared. However, avoid writing
Kojto 90:cb3d968589d8 384 * 1s to both field locations because this "11" case is reserved and may change in
Kojto 90:cb3d968589d8 385 * future implementations.
Kojto 90:cb3d968589d8 386 *
Kojto 90:cb3d968589d8 387 * Values:
Kojto 90:cb3d968589d8 388 * - 0 - Windowing mode is not selected.
Kojto 90:cb3d968589d8 389 * - 1 - Windowing mode is selected.
Kojto 90:cb3d968589d8 390 */
Kojto 90:cb3d968589d8 391 /*@{*/
Kojto 90:cb3d968589d8 392 #define BP_CMP_CR1_WE (6U) /*!< Bit position for CMP_CR1_WE. */
Kojto 90:cb3d968589d8 393 #define BM_CMP_CR1_WE (0x40U) /*!< Bit mask for CMP_CR1_WE. */
Kojto 90:cb3d968589d8 394 #define BS_CMP_CR1_WE (1U) /*!< Bit field size in bits for CMP_CR1_WE. */
Kojto 90:cb3d968589d8 395
Kojto 90:cb3d968589d8 396 /*! @brief Read current value of the CMP_CR1_WE field. */
Kojto 90:cb3d968589d8 397 #define BR_CMP_CR1_WE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE))
Kojto 90:cb3d968589d8 398
Kojto 90:cb3d968589d8 399 /*! @brief Format value for bitfield CMP_CR1_WE. */
Kojto 90:cb3d968589d8 400 #define BF_CMP_CR1_WE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_WE) & BM_CMP_CR1_WE)
Kojto 90:cb3d968589d8 401
Kojto 90:cb3d968589d8 402 /*! @brief Set the WE field to a new value. */
Kojto 90:cb3d968589d8 403 #define BW_CMP_CR1_WE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE) = (v))
Kojto 90:cb3d968589d8 404 /*@}*/
Kojto 90:cb3d968589d8 405
Kojto 90:cb3d968589d8 406 /*!
Kojto 90:cb3d968589d8 407 * @name Register CMP_CR1, field SE[7] (RW)
Kojto 90:cb3d968589d8 408 *
Kojto 90:cb3d968589d8 409 * At any given time, either SE or WE can be set. If a write to this register
Kojto 90:cb3d968589d8 410 * attempts to set both, then SE is set and WE is cleared. However, avoid writing
Kojto 90:cb3d968589d8 411 * 1s to both field locations because this "11" case is reserved and may change in
Kojto 90:cb3d968589d8 412 * future implementations.
Kojto 90:cb3d968589d8 413 *
Kojto 90:cb3d968589d8 414 * Values:
Kojto 90:cb3d968589d8 415 * - 0 - Sampling mode is not selected.
Kojto 90:cb3d968589d8 416 * - 1 - Sampling mode is selected.
Kojto 90:cb3d968589d8 417 */
Kojto 90:cb3d968589d8 418 /*@{*/
Kojto 90:cb3d968589d8 419 #define BP_CMP_CR1_SE (7U) /*!< Bit position for CMP_CR1_SE. */
Kojto 90:cb3d968589d8 420 #define BM_CMP_CR1_SE (0x80U) /*!< Bit mask for CMP_CR1_SE. */
Kojto 90:cb3d968589d8 421 #define BS_CMP_CR1_SE (1U) /*!< Bit field size in bits for CMP_CR1_SE. */
Kojto 90:cb3d968589d8 422
Kojto 90:cb3d968589d8 423 /*! @brief Read current value of the CMP_CR1_SE field. */
Kojto 90:cb3d968589d8 424 #define BR_CMP_CR1_SE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE))
Kojto 90:cb3d968589d8 425
Kojto 90:cb3d968589d8 426 /*! @brief Format value for bitfield CMP_CR1_SE. */
Kojto 90:cb3d968589d8 427 #define BF_CMP_CR1_SE(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_SE) & BM_CMP_CR1_SE)
Kojto 90:cb3d968589d8 428
Kojto 90:cb3d968589d8 429 /*! @brief Set the SE field to a new value. */
Kojto 90:cb3d968589d8 430 #define BW_CMP_CR1_SE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE) = (v))
Kojto 90:cb3d968589d8 431 /*@}*/
Kojto 90:cb3d968589d8 432
Kojto 90:cb3d968589d8 433 /*******************************************************************************
Kojto 90:cb3d968589d8 434 * HW_CMP_FPR - CMP Filter Period Register
Kojto 90:cb3d968589d8 435 ******************************************************************************/
Kojto 90:cb3d968589d8 436
Kojto 90:cb3d968589d8 437 /*!
Kojto 90:cb3d968589d8 438 * @brief HW_CMP_FPR - CMP Filter Period Register (RW)
Kojto 90:cb3d968589d8 439 *
Kojto 90:cb3d968589d8 440 * Reset value: 0x00U
Kojto 90:cb3d968589d8 441 */
Kojto 90:cb3d968589d8 442 typedef union _hw_cmp_fpr
Kojto 90:cb3d968589d8 443 {
Kojto 90:cb3d968589d8 444 uint8_t U;
Kojto 90:cb3d968589d8 445 struct _hw_cmp_fpr_bitfields
Kojto 90:cb3d968589d8 446 {
Kojto 90:cb3d968589d8 447 uint8_t FILT_PER : 8; /*!< [7:0] Filter Sample Period */
Kojto 90:cb3d968589d8 448 } B;
Kojto 90:cb3d968589d8 449 } hw_cmp_fpr_t;
Kojto 90:cb3d968589d8 450
Kojto 90:cb3d968589d8 451 /*!
Kojto 90:cb3d968589d8 452 * @name Constants and macros for entire CMP_FPR register
Kojto 90:cb3d968589d8 453 */
Kojto 90:cb3d968589d8 454 /*@{*/
Kojto 90:cb3d968589d8 455 #define HW_CMP_FPR_ADDR(x) ((x) + 0x2U)
Kojto 90:cb3d968589d8 456
Kojto 90:cb3d968589d8 457 #define HW_CMP_FPR(x) (*(__IO hw_cmp_fpr_t *) HW_CMP_FPR_ADDR(x))
Kojto 90:cb3d968589d8 458 #define HW_CMP_FPR_RD(x) (HW_CMP_FPR(x).U)
Kojto 90:cb3d968589d8 459 #define HW_CMP_FPR_WR(x, v) (HW_CMP_FPR(x).U = (v))
Kojto 90:cb3d968589d8 460 #define HW_CMP_FPR_SET(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) | (v)))
Kojto 90:cb3d968589d8 461 #define HW_CMP_FPR_CLR(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 462 #define HW_CMP_FPR_TOG(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 463 /*@}*/
Kojto 90:cb3d968589d8 464
Kojto 90:cb3d968589d8 465 /*
Kojto 90:cb3d968589d8 466 * Constants & macros for individual CMP_FPR bitfields
Kojto 90:cb3d968589d8 467 */
Kojto 90:cb3d968589d8 468
Kojto 90:cb3d968589d8 469 /*!
Kojto 90:cb3d968589d8 470 * @name Register CMP_FPR, field FILT_PER[7:0] (RW)
Kojto 90:cb3d968589d8 471 *
Kojto 90:cb3d968589d8 472 * Specifies the sampling period, in bus clock cycles, of the comparator output
Kojto 90:cb3d968589d8 473 * filter, when CR1[SE]=0. Setting FILT_PER to 0x0 disables the filter. Filter
Kojto 90:cb3d968589d8 474 * programming and latency details appear in the Functional descriptionThe CMP
Kojto 90:cb3d968589d8 475 * module can be used to compare two analog input voltages applied to INP and INM. .
Kojto 90:cb3d968589d8 476 * This field has no effect when CR1[SE]=1. In that case, the external SAMPLE
Kojto 90:cb3d968589d8 477 * signal is used to determine the sampling period.
Kojto 90:cb3d968589d8 478 */
Kojto 90:cb3d968589d8 479 /*@{*/
Kojto 90:cb3d968589d8 480 #define BP_CMP_FPR_FILT_PER (0U) /*!< Bit position for CMP_FPR_FILT_PER. */
Kojto 90:cb3d968589d8 481 #define BM_CMP_FPR_FILT_PER (0xFFU) /*!< Bit mask for CMP_FPR_FILT_PER. */
Kojto 90:cb3d968589d8 482 #define BS_CMP_FPR_FILT_PER (8U) /*!< Bit field size in bits for CMP_FPR_FILT_PER. */
Kojto 90:cb3d968589d8 483
Kojto 90:cb3d968589d8 484 /*! @brief Read current value of the CMP_FPR_FILT_PER field. */
Kojto 90:cb3d968589d8 485 #define BR_CMP_FPR_FILT_PER(x) (HW_CMP_FPR(x).U)
Kojto 90:cb3d968589d8 486
Kojto 90:cb3d968589d8 487 /*! @brief Format value for bitfield CMP_FPR_FILT_PER. */
Kojto 90:cb3d968589d8 488 #define BF_CMP_FPR_FILT_PER(v) ((uint8_t)((uint8_t)(v) << BP_CMP_FPR_FILT_PER) & BM_CMP_FPR_FILT_PER)
Kojto 90:cb3d968589d8 489
Kojto 90:cb3d968589d8 490 /*! @brief Set the FILT_PER field to a new value. */
Kojto 90:cb3d968589d8 491 #define BW_CMP_FPR_FILT_PER(x, v) (HW_CMP_FPR_WR(x, v))
Kojto 90:cb3d968589d8 492 /*@}*/
Kojto 90:cb3d968589d8 493
Kojto 90:cb3d968589d8 494 /*******************************************************************************
Kojto 90:cb3d968589d8 495 * HW_CMP_SCR - CMP Status and Control Register
Kojto 90:cb3d968589d8 496 ******************************************************************************/
Kojto 90:cb3d968589d8 497
Kojto 90:cb3d968589d8 498 /*!
Kojto 90:cb3d968589d8 499 * @brief HW_CMP_SCR - CMP Status and Control Register (RW)
Kojto 90:cb3d968589d8 500 *
Kojto 90:cb3d968589d8 501 * Reset value: 0x00U
Kojto 90:cb3d968589d8 502 */
Kojto 90:cb3d968589d8 503 typedef union _hw_cmp_scr
Kojto 90:cb3d968589d8 504 {
Kojto 90:cb3d968589d8 505 uint8_t U;
Kojto 90:cb3d968589d8 506 struct _hw_cmp_scr_bitfields
Kojto 90:cb3d968589d8 507 {
Kojto 90:cb3d968589d8 508 uint8_t COUT : 1; /*!< [0] Analog Comparator Output */
Kojto 90:cb3d968589d8 509 uint8_t CFF : 1; /*!< [1] Analog Comparator Flag Falling */
Kojto 90:cb3d968589d8 510 uint8_t CFR : 1; /*!< [2] Analog Comparator Flag Rising */
Kojto 90:cb3d968589d8 511 uint8_t IEF : 1; /*!< [3] Comparator Interrupt Enable Falling */
Kojto 90:cb3d968589d8 512 uint8_t IER : 1; /*!< [4] Comparator Interrupt Enable Rising */
Kojto 90:cb3d968589d8 513 uint8_t RESERVED0 : 1; /*!< [5] */
Kojto 90:cb3d968589d8 514 uint8_t DMAEN : 1; /*!< [6] DMA Enable Control */
Kojto 90:cb3d968589d8 515 uint8_t RESERVED1 : 1; /*!< [7] */
Kojto 90:cb3d968589d8 516 } B;
Kojto 90:cb3d968589d8 517 } hw_cmp_scr_t;
Kojto 90:cb3d968589d8 518
Kojto 90:cb3d968589d8 519 /*!
Kojto 90:cb3d968589d8 520 * @name Constants and macros for entire CMP_SCR register
Kojto 90:cb3d968589d8 521 */
Kojto 90:cb3d968589d8 522 /*@{*/
Kojto 90:cb3d968589d8 523 #define HW_CMP_SCR_ADDR(x) ((x) + 0x3U)
Kojto 90:cb3d968589d8 524
Kojto 90:cb3d968589d8 525 #define HW_CMP_SCR(x) (*(__IO hw_cmp_scr_t *) HW_CMP_SCR_ADDR(x))
Kojto 90:cb3d968589d8 526 #define HW_CMP_SCR_RD(x) (HW_CMP_SCR(x).U)
Kojto 90:cb3d968589d8 527 #define HW_CMP_SCR_WR(x, v) (HW_CMP_SCR(x).U = (v))
Kojto 90:cb3d968589d8 528 #define HW_CMP_SCR_SET(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) | (v)))
Kojto 90:cb3d968589d8 529 #define HW_CMP_SCR_CLR(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 530 #define HW_CMP_SCR_TOG(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 531 /*@}*/
Kojto 90:cb3d968589d8 532
Kojto 90:cb3d968589d8 533 /*
Kojto 90:cb3d968589d8 534 * Constants & macros for individual CMP_SCR bitfields
Kojto 90:cb3d968589d8 535 */
Kojto 90:cb3d968589d8 536
Kojto 90:cb3d968589d8 537 /*!
Kojto 90:cb3d968589d8 538 * @name Register CMP_SCR, field COUT[0] (RO)
Kojto 90:cb3d968589d8 539 *
Kojto 90:cb3d968589d8 540 * Returns the current value of the Analog Comparator output, when read. The
Kojto 90:cb3d968589d8 541 * field is reset to 0 and will read as CR1[INV] when the Analog Comparator module
Kojto 90:cb3d968589d8 542 * is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored.
Kojto 90:cb3d968589d8 543 */
Kojto 90:cb3d968589d8 544 /*@{*/
Kojto 90:cb3d968589d8 545 #define BP_CMP_SCR_COUT (0U) /*!< Bit position for CMP_SCR_COUT. */
Kojto 90:cb3d968589d8 546 #define BM_CMP_SCR_COUT (0x01U) /*!< Bit mask for CMP_SCR_COUT. */
Kojto 90:cb3d968589d8 547 #define BS_CMP_SCR_COUT (1U) /*!< Bit field size in bits for CMP_SCR_COUT. */
Kojto 90:cb3d968589d8 548
Kojto 90:cb3d968589d8 549 /*! @brief Read current value of the CMP_SCR_COUT field. */
Kojto 90:cb3d968589d8 550 #define BR_CMP_SCR_COUT(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_COUT))
Kojto 90:cb3d968589d8 551 /*@}*/
Kojto 90:cb3d968589d8 552
Kojto 90:cb3d968589d8 553 /*!
Kojto 90:cb3d968589d8 554 * @name Register CMP_SCR, field CFF[1] (W1C)
Kojto 90:cb3d968589d8 555 *
Kojto 90:cb3d968589d8 556 * Detects a falling-edge on COUT, when set, during normal operation. CFF is
Kojto 90:cb3d968589d8 557 * cleared by writing 1 to it. During Stop modes, CFF is level sensitive is edge
Kojto 90:cb3d968589d8 558 * sensitive .
Kojto 90:cb3d968589d8 559 *
Kojto 90:cb3d968589d8 560 * Values:
Kojto 90:cb3d968589d8 561 * - 0 - Falling-edge on COUT has not been detected.
Kojto 90:cb3d968589d8 562 * - 1 - Falling-edge on COUT has occurred.
Kojto 90:cb3d968589d8 563 */
Kojto 90:cb3d968589d8 564 /*@{*/
Kojto 90:cb3d968589d8 565 #define BP_CMP_SCR_CFF (1U) /*!< Bit position for CMP_SCR_CFF. */
Kojto 90:cb3d968589d8 566 #define BM_CMP_SCR_CFF (0x02U) /*!< Bit mask for CMP_SCR_CFF. */
Kojto 90:cb3d968589d8 567 #define BS_CMP_SCR_CFF (1U) /*!< Bit field size in bits for CMP_SCR_CFF. */
Kojto 90:cb3d968589d8 568
Kojto 90:cb3d968589d8 569 /*! @brief Read current value of the CMP_SCR_CFF field. */
Kojto 90:cb3d968589d8 570 #define BR_CMP_SCR_CFF(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF))
Kojto 90:cb3d968589d8 571
Kojto 90:cb3d968589d8 572 /*! @brief Format value for bitfield CMP_SCR_CFF. */
Kojto 90:cb3d968589d8 573 #define BF_CMP_SCR_CFF(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_CFF) & BM_CMP_SCR_CFF)
Kojto 90:cb3d968589d8 574
Kojto 90:cb3d968589d8 575 /*! @brief Set the CFF field to a new value. */
Kojto 90:cb3d968589d8 576 #define BW_CMP_SCR_CFF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF) = (v))
Kojto 90:cb3d968589d8 577 /*@}*/
Kojto 90:cb3d968589d8 578
Kojto 90:cb3d968589d8 579 /*!
Kojto 90:cb3d968589d8 580 * @name Register CMP_SCR, field CFR[2] (W1C)
Kojto 90:cb3d968589d8 581 *
Kojto 90:cb3d968589d8 582 * Detects a rising-edge on COUT, when set, during normal operation. CFR is
Kojto 90:cb3d968589d8 583 * cleared by writing 1 to it. During Stop modes, CFR is level sensitive is edge
Kojto 90:cb3d968589d8 584 * sensitive .
Kojto 90:cb3d968589d8 585 *
Kojto 90:cb3d968589d8 586 * Values:
Kojto 90:cb3d968589d8 587 * - 0 - Rising-edge on COUT has not been detected.
Kojto 90:cb3d968589d8 588 * - 1 - Rising-edge on COUT has occurred.
Kojto 90:cb3d968589d8 589 */
Kojto 90:cb3d968589d8 590 /*@{*/
Kojto 90:cb3d968589d8 591 #define BP_CMP_SCR_CFR (2U) /*!< Bit position for CMP_SCR_CFR. */
Kojto 90:cb3d968589d8 592 #define BM_CMP_SCR_CFR (0x04U) /*!< Bit mask for CMP_SCR_CFR. */
Kojto 90:cb3d968589d8 593 #define BS_CMP_SCR_CFR (1U) /*!< Bit field size in bits for CMP_SCR_CFR. */
Kojto 90:cb3d968589d8 594
Kojto 90:cb3d968589d8 595 /*! @brief Read current value of the CMP_SCR_CFR field. */
Kojto 90:cb3d968589d8 596 #define BR_CMP_SCR_CFR(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR))
Kojto 90:cb3d968589d8 597
Kojto 90:cb3d968589d8 598 /*! @brief Format value for bitfield CMP_SCR_CFR. */
Kojto 90:cb3d968589d8 599 #define BF_CMP_SCR_CFR(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_CFR) & BM_CMP_SCR_CFR)
Kojto 90:cb3d968589d8 600
Kojto 90:cb3d968589d8 601 /*! @brief Set the CFR field to a new value. */
Kojto 90:cb3d968589d8 602 #define BW_CMP_SCR_CFR(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR) = (v))
Kojto 90:cb3d968589d8 603 /*@}*/
Kojto 90:cb3d968589d8 604
Kojto 90:cb3d968589d8 605 /*!
Kojto 90:cb3d968589d8 606 * @name Register CMP_SCR, field IEF[3] (RW)
Kojto 90:cb3d968589d8 607 *
Kojto 90:cb3d968589d8 608 * Enables the CFF interrupt from the CMP. When this field is set, an interrupt
Kojto 90:cb3d968589d8 609 * will be asserted when CFF is set.
Kojto 90:cb3d968589d8 610 *
Kojto 90:cb3d968589d8 611 * Values:
Kojto 90:cb3d968589d8 612 * - 0 - Interrupt is disabled.
Kojto 90:cb3d968589d8 613 * - 1 - Interrupt is enabled.
Kojto 90:cb3d968589d8 614 */
Kojto 90:cb3d968589d8 615 /*@{*/
Kojto 90:cb3d968589d8 616 #define BP_CMP_SCR_IEF (3U) /*!< Bit position for CMP_SCR_IEF. */
Kojto 90:cb3d968589d8 617 #define BM_CMP_SCR_IEF (0x08U) /*!< Bit mask for CMP_SCR_IEF. */
Kojto 90:cb3d968589d8 618 #define BS_CMP_SCR_IEF (1U) /*!< Bit field size in bits for CMP_SCR_IEF. */
Kojto 90:cb3d968589d8 619
Kojto 90:cb3d968589d8 620 /*! @brief Read current value of the CMP_SCR_IEF field. */
Kojto 90:cb3d968589d8 621 #define BR_CMP_SCR_IEF(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF))
Kojto 90:cb3d968589d8 622
Kojto 90:cb3d968589d8 623 /*! @brief Format value for bitfield CMP_SCR_IEF. */
Kojto 90:cb3d968589d8 624 #define BF_CMP_SCR_IEF(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_IEF) & BM_CMP_SCR_IEF)
Kojto 90:cb3d968589d8 625
Kojto 90:cb3d968589d8 626 /*! @brief Set the IEF field to a new value. */
Kojto 90:cb3d968589d8 627 #define BW_CMP_SCR_IEF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF) = (v))
Kojto 90:cb3d968589d8 628 /*@}*/
Kojto 90:cb3d968589d8 629
Kojto 90:cb3d968589d8 630 /*!
Kojto 90:cb3d968589d8 631 * @name Register CMP_SCR, field IER[4] (RW)
Kojto 90:cb3d968589d8 632 *
Kojto 90:cb3d968589d8 633 * Enables the CFR interrupt from the CMP. When this field is set, an interrupt
Kojto 90:cb3d968589d8 634 * will be asserted when CFR is set.
Kojto 90:cb3d968589d8 635 *
Kojto 90:cb3d968589d8 636 * Values:
Kojto 90:cb3d968589d8 637 * - 0 - Interrupt is disabled.
Kojto 90:cb3d968589d8 638 * - 1 - Interrupt is enabled.
Kojto 90:cb3d968589d8 639 */
Kojto 90:cb3d968589d8 640 /*@{*/
Kojto 90:cb3d968589d8 641 #define BP_CMP_SCR_IER (4U) /*!< Bit position for CMP_SCR_IER. */
Kojto 90:cb3d968589d8 642 #define BM_CMP_SCR_IER (0x10U) /*!< Bit mask for CMP_SCR_IER. */
Kojto 90:cb3d968589d8 643 #define BS_CMP_SCR_IER (1U) /*!< Bit field size in bits for CMP_SCR_IER. */
Kojto 90:cb3d968589d8 644
Kojto 90:cb3d968589d8 645 /*! @brief Read current value of the CMP_SCR_IER field. */
Kojto 90:cb3d968589d8 646 #define BR_CMP_SCR_IER(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER))
Kojto 90:cb3d968589d8 647
Kojto 90:cb3d968589d8 648 /*! @brief Format value for bitfield CMP_SCR_IER. */
Kojto 90:cb3d968589d8 649 #define BF_CMP_SCR_IER(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_IER) & BM_CMP_SCR_IER)
Kojto 90:cb3d968589d8 650
Kojto 90:cb3d968589d8 651 /*! @brief Set the IER field to a new value. */
Kojto 90:cb3d968589d8 652 #define BW_CMP_SCR_IER(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER) = (v))
Kojto 90:cb3d968589d8 653 /*@}*/
Kojto 90:cb3d968589d8 654
Kojto 90:cb3d968589d8 655 /*!
Kojto 90:cb3d968589d8 656 * @name Register CMP_SCR, field DMAEN[6] (RW)
Kojto 90:cb3d968589d8 657 *
Kojto 90:cb3d968589d8 658 * Enables the DMA transfer triggered from the CMP module. When this field is
Kojto 90:cb3d968589d8 659 * set, a DMA request is asserted when CFR or CFF is set.
Kojto 90:cb3d968589d8 660 *
Kojto 90:cb3d968589d8 661 * Values:
Kojto 90:cb3d968589d8 662 * - 0 - DMA is disabled.
Kojto 90:cb3d968589d8 663 * - 1 - DMA is enabled.
Kojto 90:cb3d968589d8 664 */
Kojto 90:cb3d968589d8 665 /*@{*/
Kojto 90:cb3d968589d8 666 #define BP_CMP_SCR_DMAEN (6U) /*!< Bit position for CMP_SCR_DMAEN. */
Kojto 90:cb3d968589d8 667 #define BM_CMP_SCR_DMAEN (0x40U) /*!< Bit mask for CMP_SCR_DMAEN. */
Kojto 90:cb3d968589d8 668 #define BS_CMP_SCR_DMAEN (1U) /*!< Bit field size in bits for CMP_SCR_DMAEN. */
Kojto 90:cb3d968589d8 669
Kojto 90:cb3d968589d8 670 /*! @brief Read current value of the CMP_SCR_DMAEN field. */
Kojto 90:cb3d968589d8 671 #define BR_CMP_SCR_DMAEN(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN))
Kojto 90:cb3d968589d8 672
Kojto 90:cb3d968589d8 673 /*! @brief Format value for bitfield CMP_SCR_DMAEN. */
Kojto 90:cb3d968589d8 674 #define BF_CMP_SCR_DMAEN(v) ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_DMAEN) & BM_CMP_SCR_DMAEN)
Kojto 90:cb3d968589d8 675
Kojto 90:cb3d968589d8 676 /*! @brief Set the DMAEN field to a new value. */
Kojto 90:cb3d968589d8 677 #define BW_CMP_SCR_DMAEN(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN) = (v))
Kojto 90:cb3d968589d8 678 /*@}*/
Kojto 90:cb3d968589d8 679
Kojto 90:cb3d968589d8 680 /*******************************************************************************
Kojto 90:cb3d968589d8 681 * HW_CMP_DACCR - DAC Control Register
Kojto 90:cb3d968589d8 682 ******************************************************************************/
Kojto 90:cb3d968589d8 683
Kojto 90:cb3d968589d8 684 /*!
Kojto 90:cb3d968589d8 685 * @brief HW_CMP_DACCR - DAC Control Register (RW)
Kojto 90:cb3d968589d8 686 *
Kojto 90:cb3d968589d8 687 * Reset value: 0x00U
Kojto 90:cb3d968589d8 688 */
Kojto 90:cb3d968589d8 689 typedef union _hw_cmp_daccr
Kojto 90:cb3d968589d8 690 {
Kojto 90:cb3d968589d8 691 uint8_t U;
Kojto 90:cb3d968589d8 692 struct _hw_cmp_daccr_bitfields
Kojto 90:cb3d968589d8 693 {
Kojto 90:cb3d968589d8 694 uint8_t VOSEL : 6; /*!< [5:0] DAC Output Voltage Select */
Kojto 90:cb3d968589d8 695 uint8_t VRSEL : 1; /*!< [6] Supply Voltage Reference Source Select */
Kojto 90:cb3d968589d8 696 uint8_t DACEN : 1; /*!< [7] DAC Enable */
Kojto 90:cb3d968589d8 697 } B;
Kojto 90:cb3d968589d8 698 } hw_cmp_daccr_t;
Kojto 90:cb3d968589d8 699
Kojto 90:cb3d968589d8 700 /*!
Kojto 90:cb3d968589d8 701 * @name Constants and macros for entire CMP_DACCR register
Kojto 90:cb3d968589d8 702 */
Kojto 90:cb3d968589d8 703 /*@{*/
Kojto 90:cb3d968589d8 704 #define HW_CMP_DACCR_ADDR(x) ((x) + 0x4U)
Kojto 90:cb3d968589d8 705
Kojto 90:cb3d968589d8 706 #define HW_CMP_DACCR(x) (*(__IO hw_cmp_daccr_t *) HW_CMP_DACCR_ADDR(x))
Kojto 90:cb3d968589d8 707 #define HW_CMP_DACCR_RD(x) (HW_CMP_DACCR(x).U)
Kojto 90:cb3d968589d8 708 #define HW_CMP_DACCR_WR(x, v) (HW_CMP_DACCR(x).U = (v))
Kojto 90:cb3d968589d8 709 #define HW_CMP_DACCR_SET(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) | (v)))
Kojto 90:cb3d968589d8 710 #define HW_CMP_DACCR_CLR(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 711 #define HW_CMP_DACCR_TOG(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 712 /*@}*/
Kojto 90:cb3d968589d8 713
Kojto 90:cb3d968589d8 714 /*
Kojto 90:cb3d968589d8 715 * Constants & macros for individual CMP_DACCR bitfields
Kojto 90:cb3d968589d8 716 */
Kojto 90:cb3d968589d8 717
Kojto 90:cb3d968589d8 718 /*!
Kojto 90:cb3d968589d8 719 * @name Register CMP_DACCR, field VOSEL[5:0] (RW)
Kojto 90:cb3d968589d8 720 *
Kojto 90:cb3d968589d8 721 * Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) *
Kojto 90:cb3d968589d8 722 * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in .
Kojto 90:cb3d968589d8 723 */
Kojto 90:cb3d968589d8 724 /*@{*/
Kojto 90:cb3d968589d8 725 #define BP_CMP_DACCR_VOSEL (0U) /*!< Bit position for CMP_DACCR_VOSEL. */
Kojto 90:cb3d968589d8 726 #define BM_CMP_DACCR_VOSEL (0x3FU) /*!< Bit mask for CMP_DACCR_VOSEL. */
Kojto 90:cb3d968589d8 727 #define BS_CMP_DACCR_VOSEL (6U) /*!< Bit field size in bits for CMP_DACCR_VOSEL. */
Kojto 90:cb3d968589d8 728
Kojto 90:cb3d968589d8 729 /*! @brief Read current value of the CMP_DACCR_VOSEL field. */
Kojto 90:cb3d968589d8 730 #define BR_CMP_DACCR_VOSEL(x) (HW_CMP_DACCR(x).B.VOSEL)
Kojto 90:cb3d968589d8 731
Kojto 90:cb3d968589d8 732 /*! @brief Format value for bitfield CMP_DACCR_VOSEL. */
Kojto 90:cb3d968589d8 733 #define BF_CMP_DACCR_VOSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_VOSEL) & BM_CMP_DACCR_VOSEL)
Kojto 90:cb3d968589d8 734
Kojto 90:cb3d968589d8 735 /*! @brief Set the VOSEL field to a new value. */
Kojto 90:cb3d968589d8 736 #define BW_CMP_DACCR_VOSEL(x, v) (HW_CMP_DACCR_WR(x, (HW_CMP_DACCR_RD(x) & ~BM_CMP_DACCR_VOSEL) | BF_CMP_DACCR_VOSEL(v)))
Kojto 90:cb3d968589d8 737 /*@}*/
Kojto 90:cb3d968589d8 738
Kojto 90:cb3d968589d8 739 /*!
Kojto 90:cb3d968589d8 740 * @name Register CMP_DACCR, field VRSEL[6] (RW)
Kojto 90:cb3d968589d8 741 *
Kojto 90:cb3d968589d8 742 * Values:
Kojto 90:cb3d968589d8 743 * - 0 - V is selected as resistor ladder network supply reference V. in1 in
Kojto 90:cb3d968589d8 744 * - 1 - V is selected as resistor ladder network supply reference V. in2 in
Kojto 90:cb3d968589d8 745 */
Kojto 90:cb3d968589d8 746 /*@{*/
Kojto 90:cb3d968589d8 747 #define BP_CMP_DACCR_VRSEL (6U) /*!< Bit position for CMP_DACCR_VRSEL. */
Kojto 90:cb3d968589d8 748 #define BM_CMP_DACCR_VRSEL (0x40U) /*!< Bit mask for CMP_DACCR_VRSEL. */
Kojto 90:cb3d968589d8 749 #define BS_CMP_DACCR_VRSEL (1U) /*!< Bit field size in bits for CMP_DACCR_VRSEL. */
Kojto 90:cb3d968589d8 750
Kojto 90:cb3d968589d8 751 /*! @brief Read current value of the CMP_DACCR_VRSEL field. */
Kojto 90:cb3d968589d8 752 #define BR_CMP_DACCR_VRSEL(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL))
Kojto 90:cb3d968589d8 753
Kojto 90:cb3d968589d8 754 /*! @brief Format value for bitfield CMP_DACCR_VRSEL. */
Kojto 90:cb3d968589d8 755 #define BF_CMP_DACCR_VRSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_VRSEL) & BM_CMP_DACCR_VRSEL)
Kojto 90:cb3d968589d8 756
Kojto 90:cb3d968589d8 757 /*! @brief Set the VRSEL field to a new value. */
Kojto 90:cb3d968589d8 758 #define BW_CMP_DACCR_VRSEL(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL) = (v))
Kojto 90:cb3d968589d8 759 /*@}*/
Kojto 90:cb3d968589d8 760
Kojto 90:cb3d968589d8 761 /*!
Kojto 90:cb3d968589d8 762 * @name Register CMP_DACCR, field DACEN[7] (RW)
Kojto 90:cb3d968589d8 763 *
Kojto 90:cb3d968589d8 764 * Enables the DAC. When the DAC is disabled, it is powered down to conserve
Kojto 90:cb3d968589d8 765 * power.
Kojto 90:cb3d968589d8 766 *
Kojto 90:cb3d968589d8 767 * Values:
Kojto 90:cb3d968589d8 768 * - 0 - DAC is disabled.
Kojto 90:cb3d968589d8 769 * - 1 - DAC is enabled.
Kojto 90:cb3d968589d8 770 */
Kojto 90:cb3d968589d8 771 /*@{*/
Kojto 90:cb3d968589d8 772 #define BP_CMP_DACCR_DACEN (7U) /*!< Bit position for CMP_DACCR_DACEN. */
Kojto 90:cb3d968589d8 773 #define BM_CMP_DACCR_DACEN (0x80U) /*!< Bit mask for CMP_DACCR_DACEN. */
Kojto 90:cb3d968589d8 774 #define BS_CMP_DACCR_DACEN (1U) /*!< Bit field size in bits for CMP_DACCR_DACEN. */
Kojto 90:cb3d968589d8 775
Kojto 90:cb3d968589d8 776 /*! @brief Read current value of the CMP_DACCR_DACEN field. */
Kojto 90:cb3d968589d8 777 #define BR_CMP_DACCR_DACEN(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN))
Kojto 90:cb3d968589d8 778
Kojto 90:cb3d968589d8 779 /*! @brief Format value for bitfield CMP_DACCR_DACEN. */
Kojto 90:cb3d968589d8 780 #define BF_CMP_DACCR_DACEN(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_DACEN) & BM_CMP_DACCR_DACEN)
Kojto 90:cb3d968589d8 781
Kojto 90:cb3d968589d8 782 /*! @brief Set the DACEN field to a new value. */
Kojto 90:cb3d968589d8 783 #define BW_CMP_DACCR_DACEN(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN) = (v))
Kojto 90:cb3d968589d8 784 /*@}*/
Kojto 90:cb3d968589d8 785
Kojto 90:cb3d968589d8 786 /*******************************************************************************
Kojto 90:cb3d968589d8 787 * HW_CMP_MUXCR - MUX Control Register
Kojto 90:cb3d968589d8 788 ******************************************************************************/
Kojto 90:cb3d968589d8 789
Kojto 90:cb3d968589d8 790 /*!
Kojto 90:cb3d968589d8 791 * @brief HW_CMP_MUXCR - MUX Control Register (RW)
Kojto 90:cb3d968589d8 792 *
Kojto 90:cb3d968589d8 793 * Reset value: 0x00U
Kojto 90:cb3d968589d8 794 */
Kojto 90:cb3d968589d8 795 typedef union _hw_cmp_muxcr
Kojto 90:cb3d968589d8 796 {
Kojto 90:cb3d968589d8 797 uint8_t U;
Kojto 90:cb3d968589d8 798 struct _hw_cmp_muxcr_bitfields
Kojto 90:cb3d968589d8 799 {
Kojto 90:cb3d968589d8 800 uint8_t MSEL : 3; /*!< [2:0] Minus Input Mux Control */
Kojto 90:cb3d968589d8 801 uint8_t PSEL : 3; /*!< [5:3] Plus Input Mux Control */
Kojto 90:cb3d968589d8 802 uint8_t RESERVED0 : 1; /*!< [6] */
Kojto 90:cb3d968589d8 803 uint8_t PSTM : 1; /*!< [7] Pass Through Mode Enable */
Kojto 90:cb3d968589d8 804 } B;
Kojto 90:cb3d968589d8 805 } hw_cmp_muxcr_t;
Kojto 90:cb3d968589d8 806
Kojto 90:cb3d968589d8 807 /*!
Kojto 90:cb3d968589d8 808 * @name Constants and macros for entire CMP_MUXCR register
Kojto 90:cb3d968589d8 809 */
Kojto 90:cb3d968589d8 810 /*@{*/
Kojto 90:cb3d968589d8 811 #define HW_CMP_MUXCR_ADDR(x) ((x) + 0x5U)
Kojto 90:cb3d968589d8 812
Kojto 90:cb3d968589d8 813 #define HW_CMP_MUXCR(x) (*(__IO hw_cmp_muxcr_t *) HW_CMP_MUXCR_ADDR(x))
Kojto 90:cb3d968589d8 814 #define HW_CMP_MUXCR_RD(x) (HW_CMP_MUXCR(x).U)
Kojto 90:cb3d968589d8 815 #define HW_CMP_MUXCR_WR(x, v) (HW_CMP_MUXCR(x).U = (v))
Kojto 90:cb3d968589d8 816 #define HW_CMP_MUXCR_SET(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) | (v)))
Kojto 90:cb3d968589d8 817 #define HW_CMP_MUXCR_CLR(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 818 #define HW_CMP_MUXCR_TOG(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 819 /*@}*/
Kojto 90:cb3d968589d8 820
Kojto 90:cb3d968589d8 821 /*
Kojto 90:cb3d968589d8 822 * Constants & macros for individual CMP_MUXCR bitfields
Kojto 90:cb3d968589d8 823 */
Kojto 90:cb3d968589d8 824
Kojto 90:cb3d968589d8 825 /*!
Kojto 90:cb3d968589d8 826 * @name Register CMP_MUXCR, field MSEL[2:0] (RW)
Kojto 90:cb3d968589d8 827 *
Kojto 90:cb3d968589d8 828 * Determines which input is selected for the minus input of the comparator. For
Kojto 90:cb3d968589d8 829 * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
Kojto 90:cb3d968589d8 830 * operation selects the same input for both muxes, the comparator automatically
Kojto 90:cb3d968589d8 831 * shuts down to prevent itself from becoming a noise generator.
Kojto 90:cb3d968589d8 832 *
Kojto 90:cb3d968589d8 833 * Values:
Kojto 90:cb3d968589d8 834 * - 000 - IN0
Kojto 90:cb3d968589d8 835 * - 001 - IN1
Kojto 90:cb3d968589d8 836 * - 010 - IN2
Kojto 90:cb3d968589d8 837 * - 011 - IN3
Kojto 90:cb3d968589d8 838 * - 100 - IN4
Kojto 90:cb3d968589d8 839 * - 101 - IN5
Kojto 90:cb3d968589d8 840 * - 110 - IN6
Kojto 90:cb3d968589d8 841 * - 111 - IN7
Kojto 90:cb3d968589d8 842 */
Kojto 90:cb3d968589d8 843 /*@{*/
Kojto 90:cb3d968589d8 844 #define BP_CMP_MUXCR_MSEL (0U) /*!< Bit position for CMP_MUXCR_MSEL. */
Kojto 90:cb3d968589d8 845 #define BM_CMP_MUXCR_MSEL (0x07U) /*!< Bit mask for CMP_MUXCR_MSEL. */
Kojto 90:cb3d968589d8 846 #define BS_CMP_MUXCR_MSEL (3U) /*!< Bit field size in bits for CMP_MUXCR_MSEL. */
Kojto 90:cb3d968589d8 847
Kojto 90:cb3d968589d8 848 /*! @brief Read current value of the CMP_MUXCR_MSEL field. */
Kojto 90:cb3d968589d8 849 #define BR_CMP_MUXCR_MSEL(x) (HW_CMP_MUXCR(x).B.MSEL)
Kojto 90:cb3d968589d8 850
Kojto 90:cb3d968589d8 851 /*! @brief Format value for bitfield CMP_MUXCR_MSEL. */
Kojto 90:cb3d968589d8 852 #define BF_CMP_MUXCR_MSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_MSEL) & BM_CMP_MUXCR_MSEL)
Kojto 90:cb3d968589d8 853
Kojto 90:cb3d968589d8 854 /*! @brief Set the MSEL field to a new value. */
Kojto 90:cb3d968589d8 855 #define BW_CMP_MUXCR_MSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_MSEL) | BF_CMP_MUXCR_MSEL(v)))
Kojto 90:cb3d968589d8 856 /*@}*/
Kojto 90:cb3d968589d8 857
Kojto 90:cb3d968589d8 858 /*!
Kojto 90:cb3d968589d8 859 * @name Register CMP_MUXCR, field PSEL[5:3] (RW)
Kojto 90:cb3d968589d8 860 *
Kojto 90:cb3d968589d8 861 * Determines which input is selected for the plus input of the comparator. For
Kojto 90:cb3d968589d8 862 * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
Kojto 90:cb3d968589d8 863 * operation selects the same input for both muxes, the comparator automatically
Kojto 90:cb3d968589d8 864 * shuts down to prevent itself from becoming a noise generator.
Kojto 90:cb3d968589d8 865 *
Kojto 90:cb3d968589d8 866 * Values:
Kojto 90:cb3d968589d8 867 * - 000 - IN0
Kojto 90:cb3d968589d8 868 * - 001 - IN1
Kojto 90:cb3d968589d8 869 * - 010 - IN2
Kojto 90:cb3d968589d8 870 * - 011 - IN3
Kojto 90:cb3d968589d8 871 * - 100 - IN4
Kojto 90:cb3d968589d8 872 * - 101 - IN5
Kojto 90:cb3d968589d8 873 * - 110 - IN6
Kojto 90:cb3d968589d8 874 * - 111 - IN7
Kojto 90:cb3d968589d8 875 */
Kojto 90:cb3d968589d8 876 /*@{*/
Kojto 90:cb3d968589d8 877 #define BP_CMP_MUXCR_PSEL (3U) /*!< Bit position for CMP_MUXCR_PSEL. */
Kojto 90:cb3d968589d8 878 #define BM_CMP_MUXCR_PSEL (0x38U) /*!< Bit mask for CMP_MUXCR_PSEL. */
Kojto 90:cb3d968589d8 879 #define BS_CMP_MUXCR_PSEL (3U) /*!< Bit field size in bits for CMP_MUXCR_PSEL. */
Kojto 90:cb3d968589d8 880
Kojto 90:cb3d968589d8 881 /*! @brief Read current value of the CMP_MUXCR_PSEL field. */
Kojto 90:cb3d968589d8 882 #define BR_CMP_MUXCR_PSEL(x) (HW_CMP_MUXCR(x).B.PSEL)
Kojto 90:cb3d968589d8 883
Kojto 90:cb3d968589d8 884 /*! @brief Format value for bitfield CMP_MUXCR_PSEL. */
Kojto 90:cb3d968589d8 885 #define BF_CMP_MUXCR_PSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_PSEL) & BM_CMP_MUXCR_PSEL)
Kojto 90:cb3d968589d8 886
Kojto 90:cb3d968589d8 887 /*! @brief Set the PSEL field to a new value. */
Kojto 90:cb3d968589d8 888 #define BW_CMP_MUXCR_PSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_PSEL) | BF_CMP_MUXCR_PSEL(v)))
Kojto 90:cb3d968589d8 889 /*@}*/
Kojto 90:cb3d968589d8 890
Kojto 90:cb3d968589d8 891 /*!
Kojto 90:cb3d968589d8 892 * @name Register CMP_MUXCR, field PSTM[7] (RW)
Kojto 90:cb3d968589d8 893 *
Kojto 90:cb3d968589d8 894 * This bit is used to enable to MUX pass through mode. Pass through mode is
Kojto 90:cb3d968589d8 895 * always available but for some devices this feature must be always disabled due to
Kojto 90:cb3d968589d8 896 * the lack of package pins.
Kojto 90:cb3d968589d8 897 *
Kojto 90:cb3d968589d8 898 * Values:
Kojto 90:cb3d968589d8 899 * - 0 - Pass Through Mode is disabled.
Kojto 90:cb3d968589d8 900 * - 1 - Pass Through Mode is enabled.
Kojto 90:cb3d968589d8 901 */
Kojto 90:cb3d968589d8 902 /*@{*/
Kojto 90:cb3d968589d8 903 #define BP_CMP_MUXCR_PSTM (7U) /*!< Bit position for CMP_MUXCR_PSTM. */
Kojto 90:cb3d968589d8 904 #define BM_CMP_MUXCR_PSTM (0x80U) /*!< Bit mask for CMP_MUXCR_PSTM. */
Kojto 90:cb3d968589d8 905 #define BS_CMP_MUXCR_PSTM (1U) /*!< Bit field size in bits for CMP_MUXCR_PSTM. */
Kojto 90:cb3d968589d8 906
Kojto 90:cb3d968589d8 907 /*! @brief Read current value of the CMP_MUXCR_PSTM field. */
Kojto 90:cb3d968589d8 908 #define BR_CMP_MUXCR_PSTM(x) (BITBAND_ACCESS8(HW_CMP_MUXCR_ADDR(x), BP_CMP_MUXCR_PSTM))
Kojto 90:cb3d968589d8 909
Kojto 90:cb3d968589d8 910 /*! @brief Format value for bitfield CMP_MUXCR_PSTM. */
Kojto 90:cb3d968589d8 911 #define BF_CMP_MUXCR_PSTM(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_PSTM) & BM_CMP_MUXCR_PSTM)
Kojto 90:cb3d968589d8 912
Kojto 90:cb3d968589d8 913 /*! @brief Set the PSTM field to a new value. */
Kojto 90:cb3d968589d8 914 #define BW_CMP_MUXCR_PSTM(x, v) (BITBAND_ACCESS8(HW_CMP_MUXCR_ADDR(x), BP_CMP_MUXCR_PSTM) = (v))
Kojto 90:cb3d968589d8 915 /*@}*/
Kojto 90:cb3d968589d8 916
Kojto 90:cb3d968589d8 917 /*******************************************************************************
Kojto 90:cb3d968589d8 918 * hw_cmp_t - module struct
Kojto 90:cb3d968589d8 919 ******************************************************************************/
Kojto 90:cb3d968589d8 920 /*!
Kojto 90:cb3d968589d8 921 * @brief All CMP module registers.
Kojto 90:cb3d968589d8 922 */
Kojto 90:cb3d968589d8 923 #pragma pack(1)
Kojto 90:cb3d968589d8 924 typedef struct _hw_cmp
Kojto 90:cb3d968589d8 925 {
Kojto 90:cb3d968589d8 926 __IO hw_cmp_cr0_t CR0; /*!< [0x0] CMP Control Register 0 */
Kojto 90:cb3d968589d8 927 __IO hw_cmp_cr1_t CR1; /*!< [0x1] CMP Control Register 1 */
Kojto 90:cb3d968589d8 928 __IO hw_cmp_fpr_t FPR; /*!< [0x2] CMP Filter Period Register */
Kojto 90:cb3d968589d8 929 __IO hw_cmp_scr_t SCR; /*!< [0x3] CMP Status and Control Register */
Kojto 90:cb3d968589d8 930 __IO hw_cmp_daccr_t DACCR; /*!< [0x4] DAC Control Register */
Kojto 90:cb3d968589d8 931 __IO hw_cmp_muxcr_t MUXCR; /*!< [0x5] MUX Control Register */
Kojto 90:cb3d968589d8 932 } hw_cmp_t;
Kojto 90:cb3d968589d8 933 #pragma pack()
Kojto 90:cb3d968589d8 934
Kojto 90:cb3d968589d8 935 /*! @brief Macro to access all CMP registers. */
Kojto 90:cb3d968589d8 936 /*! @param x CMP module instance base address. */
Kojto 90:cb3d968589d8 937 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto 90:cb3d968589d8 938 * use the '&' operator, like <code>&HW_CMP(CMP0_BASE)</code>. */
Kojto 90:cb3d968589d8 939 #define HW_CMP(x) (*(hw_cmp_t *)(x))
Kojto 90:cb3d968589d8 940
Kojto 90:cb3d968589d8 941 #endif /* __HW_CMP_REGISTERS_H__ */
Kojto 90:cb3d968589d8 942 /* EOF */