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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_can.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:: Kojto
Date:: Wed Aug 05 13:16:35 2015 +0100
Revision:: 104:b9ad9a133dc7
Parent:: 90:cb3d968589d8

Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	90:cb3d968589d8	1	/*
Kojto	90:cb3d968589d8	2	** ###################################################################
Kojto	90:cb3d968589d8	3	** Compilers: Keil ARM C/C++ Compiler
Kojto	90:cb3d968589d8	4	** Freescale C/C++ for Embedded ARM
Kojto	90:cb3d968589d8	5	** GNU C Compiler
Kojto	90:cb3d968589d8	6	** IAR ANSI C/C++ Compiler for ARM
Kojto	90:cb3d968589d8	7	**
Kojto	90:cb3d968589d8	8	** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto	90:cb3d968589d8	9	** Version: rev. 2.5, 2014-02-10
Kojto	90:cb3d968589d8	10	** Build: b140604
Kojto	90:cb3d968589d8	11	**
Kojto	90:cb3d968589d8	12	** Abstract:
Kojto	90:cb3d968589d8	13	** Extension to the CMSIS register access layer header.
Kojto	90:cb3d968589d8	14	**
Kojto	90:cb3d968589d8	15	** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto	90:cb3d968589d8	16	** All rights reserved.
Kojto	90:cb3d968589d8	17	**
Kojto	90:cb3d968589d8	18	** Redistribution and use in source and binary forms, with or without modification,
Kojto	90:cb3d968589d8	19	** are permitted provided that the following conditions are met:
Kojto	90:cb3d968589d8	20	**
Kojto	90:cb3d968589d8	21	** o Redistributions of source code must retain the above copyright notice, this list
Kojto	90:cb3d968589d8	22	** of conditions and the following disclaimer.
Kojto	90:cb3d968589d8	23	**
Kojto	90:cb3d968589d8	24	** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto	90:cb3d968589d8	25	** list of conditions and the following disclaimer in the documentation and/or
Kojto	90:cb3d968589d8	26	** other materials provided with the distribution.
Kojto	90:cb3d968589d8	27	**
Kojto	90:cb3d968589d8	28	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto	90:cb3d968589d8	29	** contributors may be used to endorse or promote products derived from this
Kojto	90:cb3d968589d8	30	** software without specific prior written permission.
Kojto	90:cb3d968589d8	31	**
Kojto	90:cb3d968589d8	32	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto	90:cb3d968589d8	33	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto	90:cb3d968589d8	34	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	90:cb3d968589d8	35	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto	90:cb3d968589d8	36	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto	90:cb3d968589d8	37	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto	90:cb3d968589d8	38	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto	90:cb3d968589d8	39	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto	90:cb3d968589d8	40	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto	90:cb3d968589d8	41	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	90:cb3d968589d8	42	**
Kojto	90:cb3d968589d8	43	** http: www.freescale.com
Kojto	90:cb3d968589d8	44	** mail: support@freescale.com
Kojto	90:cb3d968589d8	45	**
Kojto	90:cb3d968589d8	46	** Revisions:
Kojto	90:cb3d968589d8	47	** - rev. 1.0 (2013-08-12)
Kojto	90:cb3d968589d8	48	** Initial version.
Kojto	90:cb3d968589d8	49	** - rev. 2.0 (2013-10-29)
Kojto	90:cb3d968589d8	50	** Register accessor macros added to the memory map.
Kojto	90:cb3d968589d8	51	** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto	90:cb3d968589d8	52	** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto	90:cb3d968589d8	53	** System initialization updated.
Kojto	90:cb3d968589d8	54	** MCG - registers updated.
Kojto	90:cb3d968589d8	55	** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto	90:cb3d968589d8	56	** - rev. 2.1 (2013-10-30)
Kojto	90:cb3d968589d8	57	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto	90:cb3d968589d8	58	** - rev. 2.2 (2013-12-09)
Kojto	90:cb3d968589d8	59	** DMA - EARS register removed.
Kojto	90:cb3d968589d8	60	** AIPS0, AIPS1 - MPRA register updated.
Kojto	90:cb3d968589d8	61	** - rev. 2.3 (2014-01-24)
Kojto	90:cb3d968589d8	62	** Update according to reference manual rev. 2
Kojto	90:cb3d968589d8	63	** ENET, MCG, MCM, SIM, USB - registers updated
Kojto	90:cb3d968589d8	64	** - rev. 2.4 (2014-02-10)
Kojto	90:cb3d968589d8	65	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	66	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	67	** - rev. 2.5 (2014-02-10)
Kojto	90:cb3d968589d8	68	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	69	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	70	** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto	90:cb3d968589d8	71	**
Kojto	90:cb3d968589d8	72	** ###################################################################
Kojto	90:cb3d968589d8	73	*/
Kojto	90:cb3d968589d8	74
Kojto	90:cb3d968589d8	75	/*
Kojto	90:cb3d968589d8	76	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto	90:cb3d968589d8	77	*
Kojto	90:cb3d968589d8	78	* This file was generated automatically and any changes may be lost.
Kojto	90:cb3d968589d8	79	*/
Kojto	90:cb3d968589d8	80	#ifndef __HW_CAN_REGISTERS_H__
Kojto	90:cb3d968589d8	81	#define __HW_CAN_REGISTERS_H__
Kojto	90:cb3d968589d8	82
Kojto	90:cb3d968589d8	83	#include "MK64F12.h"
Kojto	90:cb3d968589d8	84	#include "fsl_bitaccess.h"
Kojto	90:cb3d968589d8	85
Kojto	90:cb3d968589d8	86	/*
Kojto	90:cb3d968589d8	87	* MK64F12 CAN
Kojto	90:cb3d968589d8	88	*
Kojto	90:cb3d968589d8	89	* Flex Controller Area Network module
Kojto	90:cb3d968589d8	90	*
Kojto	90:cb3d968589d8	91	* Registers defined in this header file:
Kojto	90:cb3d968589d8	92	* - HW_CAN_MCR - Module Configuration Register
Kojto	90:cb3d968589d8	93	* - HW_CAN_CTRL1 - Control 1 register
Kojto	90:cb3d968589d8	94	* - HW_CAN_TIMER - Free Running Timer
Kojto	90:cb3d968589d8	95	* - HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register
Kojto	90:cb3d968589d8	96	* - HW_CAN_RX14MASK - Rx 14 Mask register
Kojto	90:cb3d968589d8	97	* - HW_CAN_RX15MASK - Rx 15 Mask register
Kojto	90:cb3d968589d8	98	* - HW_CAN_ECR - Error Counter
Kojto	90:cb3d968589d8	99	* - HW_CAN_ESR1 - Error and Status 1 register
Kojto	90:cb3d968589d8	100	* - HW_CAN_IMASK1 - Interrupt Masks 1 register
Kojto	90:cb3d968589d8	101	* - HW_CAN_IFLAG1 - Interrupt Flags 1 register
Kojto	90:cb3d968589d8	102	* - HW_CAN_CTRL2 - Control 2 register
Kojto	90:cb3d968589d8	103	* - HW_CAN_ESR2 - Error and Status 2 register
Kojto	90:cb3d968589d8	104	* - HW_CAN_CRCR - CRC Register
Kojto	90:cb3d968589d8	105	* - HW_CAN_RXFGMASK - Rx FIFO Global Mask register
Kojto	90:cb3d968589d8	106	* - HW_CAN_RXFIR - Rx FIFO Information Register
Kojto	90:cb3d968589d8	107	* - HW_CAN_CSn - Message Buffer 0 CS Register
Kojto	90:cb3d968589d8	108	* - HW_CAN_IDn - Message Buffer 0 ID Register
Kojto	90:cb3d968589d8	109	* - HW_CAN_WORD0n - Message Buffer 0 WORD0 Register
Kojto	90:cb3d968589d8	110	* - HW_CAN_WORD1n - Message Buffer 0 WORD1 Register
Kojto	90:cb3d968589d8	111	* - HW_CAN_RXIMRn - Rx Individual Mask Registers
Kojto	90:cb3d968589d8	112	*
Kojto	90:cb3d968589d8	113	* - hw_can_t - Struct containing all module registers.
Kojto	90:cb3d968589d8	114	*/
Kojto	90:cb3d968589d8	115
Kojto	90:cb3d968589d8	116	#define HW_CAN_INSTANCE_COUNT (1U) /!< Number of instances of the CAN module. /
Kojto	90:cb3d968589d8	117
Kojto	90:cb3d968589d8	118	/*******************************************************************************
Kojto	90:cb3d968589d8	119	* HW_CAN_MCR - Module Configuration Register
Kojto	90:cb3d968589d8	120	******************************************************************************/
Kojto	90:cb3d968589d8	121
Kojto	90:cb3d968589d8	122	/*!
Kojto	90:cb3d968589d8	123	* @brief HW_CAN_MCR - Module Configuration Register (RW)
Kojto	90:cb3d968589d8	124	*
Kojto	90:cb3d968589d8	125	* Reset value: 0xD890000FU
Kojto	90:cb3d968589d8	126	*
Kojto	90:cb3d968589d8	127	* This register defines global system configurations, such as the module
Kojto	90:cb3d968589d8	128	* operation modes and the maximum message buffer configuration.
Kojto	90:cb3d968589d8	129	*/
Kojto	90:cb3d968589d8	130	typedef union _hw_can_mcr
Kojto	90:cb3d968589d8	131	{
Kojto	90:cb3d968589d8	132	uint32_t U;
Kojto	90:cb3d968589d8	133	struct _hw_can_mcr_bitfields
Kojto	90:cb3d968589d8	134	{
Kojto	90:cb3d968589d8	135	uint32_t MAXMB : 7; /!< [6:0] Number Of The Last Message Buffer /
Kojto	90:cb3d968589d8	136	uint32_t RESERVED0 : 1; /!< [7] /
Kojto	90:cb3d968589d8	137	uint32_t IDAM : 2; /!< [9:8] ID Acceptance Mode /
Kojto	90:cb3d968589d8	138	uint32_t RESERVED1 : 2; /!< [11:10] /
Kojto	90:cb3d968589d8	139	uint32_t AEN : 1; /!< [12] Abort Enable /
Kojto	90:cb3d968589d8	140	uint32_t LPRIOEN : 1; /!< [13] Local Priority Enable /
Kojto	90:cb3d968589d8	141	uint32_t RESERVED2 : 2; /!< [15:14] /
Kojto	90:cb3d968589d8	142	uint32_t IRMQ : 1; /!< [16] Individual Rx Masking And Queue Enable /
Kojto	90:cb3d968589d8	143	uint32_t SRXDIS : 1; /!< [17] Self Reception Disable /
Kojto	90:cb3d968589d8	144	uint32_t RESERVED3 : 1; /!< [18] /
Kojto	90:cb3d968589d8	145	uint32_t WAKSRC : 1; /!< [19] Wake Up Source /
Kojto	90:cb3d968589d8	146	uint32_t LPMACK : 1; /!< [20] Low-Power Mode Acknowledge /
Kojto	90:cb3d968589d8	147	uint32_t WRNEN : 1; /!< [21] Warning Interrupt Enable /
Kojto	90:cb3d968589d8	148	uint32_t SLFWAK : 1; /!< [22] Self Wake Up /
Kojto	90:cb3d968589d8	149	uint32_t SUPV : 1; /!< [23] Supervisor Mode /
Kojto	90:cb3d968589d8	150	uint32_t FRZACK : 1; /!< [24] Freeze Mode Acknowledge /
Kojto	90:cb3d968589d8	151	uint32_t SOFTRST : 1; /!< [25] Soft Reset /
Kojto	90:cb3d968589d8	152	uint32_t WAKMSK : 1; /!< [26] Wake Up Interrupt Mask /
Kojto	90:cb3d968589d8	153	uint32_t NOTRDY : 1; /!< [27] FlexCAN Not Ready /
Kojto	90:cb3d968589d8	154	uint32_t HALT : 1; /!< [28] Halt FlexCAN /
Kojto	90:cb3d968589d8	155	uint32_t RFEN : 1; /!< [29] Rx FIFO Enable /
Kojto	90:cb3d968589d8	156	uint32_t FRZ : 1; /!< [30] Freeze Enable /
Kojto	90:cb3d968589d8	157	uint32_t MDIS : 1; /!< [31] Module Disable /
Kojto	90:cb3d968589d8	158	} B;
Kojto	90:cb3d968589d8	159	} hw_can_mcr_t;
Kojto	90:cb3d968589d8	160
Kojto	90:cb3d968589d8	161	/*!
Kojto	90:cb3d968589d8	162	* @name Constants and macros for entire CAN_MCR register
Kojto	90:cb3d968589d8	163	*/
Kojto	90:cb3d968589d8	164	/@{/
Kojto	90:cb3d968589d8	165	#define HW_CAN_MCR_ADDR(x) ((x) + 0x0U)
Kojto	90:cb3d968589d8	166
Kojto	90:cb3d968589d8	167	#define HW_CAN_MCR(x) ((__IO hw_can_mcr_t ) HW_CAN_MCR_ADDR(x))
Kojto	90:cb3d968589d8	168	#define HW_CAN_MCR_RD(x) (HW_CAN_MCR(x).U)
Kojto	90:cb3d968589d8	169	#define HW_CAN_MCR_WR(x, v) (HW_CAN_MCR(x).U = (v))
Kojto	90:cb3d968589d8	170	#define HW_CAN_MCR_SET(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	171	#define HW_CAN_MCR_CLR(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	172	#define HW_CAN_MCR_TOG(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	173	/@}/
Kojto	90:cb3d968589d8	174
Kojto	90:cb3d968589d8	175	/*
Kojto	90:cb3d968589d8	176	* Constants & macros for individual CAN_MCR bitfields
Kojto	90:cb3d968589d8	177	*/
Kojto	90:cb3d968589d8	178
Kojto	90:cb3d968589d8	179	/*!
Kojto	90:cb3d968589d8	180	* @name Register CAN_MCR, field MAXMB[6:0] (RW)
Kojto	90:cb3d968589d8	181	*
Kojto	90:cb3d968589d8	182	* This 7-bit field defines the number of the last Message Buffers that will
Kojto	90:cb3d968589d8	183	* take part in the matching and arbitration processes. The reset value (0x0F) is
Kojto	90:cb3d968589d8	184	* equivalent to a 16 MB configuration. This field can be written only in Freeze
Kojto	90:cb3d968589d8	185	* mode because it is blocked by hardware in other modes. Number of the last MB =
Kojto	90:cb3d968589d8	186	* MAXMB MAXMB must be programmed with a value smaller than the parameter
Kojto	90:cb3d968589d8	187	* NUMBER_OF_MB, otherwise the number of the last effective Message Buffer will be:
Kojto	90:cb3d968589d8	188	* (NUMBER_OF_MB - 1) Additionally, the value of MAXMB must encompass the FIFO size
Kojto	90:cb3d968589d8	189	* defined by CTRL2[RFFN]. MAXMB also impacts the definition of the minimum number
Kojto	90:cb3d968589d8	190	* of peripheral clocks per CAN bit as described in Table "Minimum Ratio Between
Kojto	90:cb3d968589d8	191	* Peripheral Clock Frequency and CAN Bit Rate" (in Section "Arbitration and
Kojto	90:cb3d968589d8	192	* Matching Timing").
Kojto	90:cb3d968589d8	193	*/
Kojto	90:cb3d968589d8	194	/@{/
Kojto	90:cb3d968589d8	195	#define BP_CAN_MCR_MAXMB (0U) /!< Bit position for CAN_MCR_MAXMB. /
Kojto	90:cb3d968589d8	196	#define BM_CAN_MCR_MAXMB (0x0000007FU) /!< Bit mask for CAN_MCR_MAXMB. /
Kojto	90:cb3d968589d8	197	#define BS_CAN_MCR_MAXMB (7U) /!< Bit field size in bits for CAN_MCR_MAXMB. /
Kojto	90:cb3d968589d8	198
Kojto	90:cb3d968589d8	199	/! @brief Read current value of the CAN_MCR_MAXMB field. /
Kojto	90:cb3d968589d8	200	#define BR_CAN_MCR_MAXMB(x) (HW_CAN_MCR(x).B.MAXMB)
Kojto	90:cb3d968589d8	201
Kojto	90:cb3d968589d8	202	/! @brief Format value for bitfield CAN_MCR_MAXMB. /
Kojto	90:cb3d968589d8	203	#define BF_CAN_MCR_MAXMB(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_MAXMB) & BM_CAN_MCR_MAXMB)
Kojto	90:cb3d968589d8	204
Kojto	90:cb3d968589d8	205	/! @brief Set the MAXMB field to a new value. /
Kojto	90:cb3d968589d8	206	#define BW_CAN_MCR_MAXMB(x, v) (HW_CAN_MCR_WR(x, (HW_CAN_MCR_RD(x) & ~BM_CAN_MCR_MAXMB) \| BF_CAN_MCR_MAXMB(v)))
Kojto	90:cb3d968589d8	207	/@}/
Kojto	90:cb3d968589d8	208
Kojto	90:cb3d968589d8	209	/*!
Kojto	90:cb3d968589d8	210	* @name Register CAN_MCR, field IDAM[9:8] (RW)
Kojto	90:cb3d968589d8	211	*
Kojto	90:cb3d968589d8	212	* This 2-bit field identifies the format of the Rx FIFO ID Filter Table
Kojto	90:cb3d968589d8	213	* elements. Note that all elements of the table are configured at the same time by this
Kojto	90:cb3d968589d8	214	* field (they are all the same format). See Section "Rx FIFO Structure". This
Kojto	90:cb3d968589d8	215	* field can be written only in Freeze mode because it is blocked by hardware in
Kojto	90:cb3d968589d8	216	* other modes.
Kojto	90:cb3d968589d8	217	*
Kojto	90:cb3d968589d8	218	* Values:
Kojto	90:cb3d968589d8	219	* - 00 - Format A: One full ID (standard and extended) per ID Filter Table
Kojto	90:cb3d968589d8	220	* element.
Kojto	90:cb3d968589d8	221	* - 01 - Format B: Two full standard IDs or two partial 14-bit (standard and
Kojto	90:cb3d968589d8	222	* extended) IDs per ID Filter Table element.
Kojto	90:cb3d968589d8	223	* - 10 - Format C: Four partial 8-bit Standard IDs per ID Filter Table element.
Kojto	90:cb3d968589d8	224	* - 11 - Format D: All frames rejected.
Kojto	90:cb3d968589d8	225	*/
Kojto	90:cb3d968589d8	226	/@{/
Kojto	90:cb3d968589d8	227	#define BP_CAN_MCR_IDAM (8U) /!< Bit position for CAN_MCR_IDAM. /
Kojto	90:cb3d968589d8	228	#define BM_CAN_MCR_IDAM (0x00000300U) /!< Bit mask for CAN_MCR_IDAM. /
Kojto	90:cb3d968589d8	229	#define BS_CAN_MCR_IDAM (2U) /!< Bit field size in bits for CAN_MCR_IDAM. /
Kojto	90:cb3d968589d8	230
Kojto	90:cb3d968589d8	231	/! @brief Read current value of the CAN_MCR_IDAM field. /
Kojto	90:cb3d968589d8	232	#define BR_CAN_MCR_IDAM(x) (HW_CAN_MCR(x).B.IDAM)
Kojto	90:cb3d968589d8	233
Kojto	90:cb3d968589d8	234	/! @brief Format value for bitfield CAN_MCR_IDAM. /
Kojto	90:cb3d968589d8	235	#define BF_CAN_MCR_IDAM(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_IDAM) & BM_CAN_MCR_IDAM)
Kojto	90:cb3d968589d8	236
Kojto	90:cb3d968589d8	237	/! @brief Set the IDAM field to a new value. /
Kojto	90:cb3d968589d8	238	#define BW_CAN_MCR_IDAM(x, v) (HW_CAN_MCR_WR(x, (HW_CAN_MCR_RD(x) & ~BM_CAN_MCR_IDAM) \| BF_CAN_MCR_IDAM(v)))
Kojto	90:cb3d968589d8	239	/@}/
Kojto	90:cb3d968589d8	240
Kojto	90:cb3d968589d8	241	/*!
Kojto	90:cb3d968589d8	242	* @name Register CAN_MCR, field AEN[12] (RW)
Kojto	90:cb3d968589d8	243	*
Kojto	90:cb3d968589d8	244	* This bit is supplied for backwards compatibility with legacy applications.
Kojto	90:cb3d968589d8	245	* When asserted, it enables the Tx abort mechanism. This mechanism guarantees a
Kojto	90:cb3d968589d8	246	* safe procedure for aborting a pending transmission, so that no frame is sent in
Kojto	90:cb3d968589d8	247	* the CAN bus without notification. This bit can be written only in Freeze mode
Kojto	90:cb3d968589d8	248	* because it is blocked by hardware in other modes. When MCR[AEN] is asserted,
Kojto	90:cb3d968589d8	249	* only the abort mechanism (see Section "Transmission Abort Mechanism") must be
Kojto	90:cb3d968589d8	250	* used for updating Mailboxes configured for transmission. Writing the Abort code
Kojto	90:cb3d968589d8	251	* into Rx Mailboxes can cause unpredictable results when the MCR[AEN] is
Kojto	90:cb3d968589d8	252	* asserted.
Kojto	90:cb3d968589d8	253	*
Kojto	90:cb3d968589d8	254	* Values:
Kojto	90:cb3d968589d8	255	* - 0 - Abort disabled.
Kojto	90:cb3d968589d8	256	* - 1 - Abort enabled.
Kojto	90:cb3d968589d8	257	*/
Kojto	90:cb3d968589d8	258	/@{/
Kojto	90:cb3d968589d8	259	#define BP_CAN_MCR_AEN (12U) /!< Bit position for CAN_MCR_AEN. /
Kojto	90:cb3d968589d8	260	#define BM_CAN_MCR_AEN (0x00001000U) /!< Bit mask for CAN_MCR_AEN. /
Kojto	90:cb3d968589d8	261	#define BS_CAN_MCR_AEN (1U) /!< Bit field size in bits for CAN_MCR_AEN. /
Kojto	90:cb3d968589d8	262
Kojto	90:cb3d968589d8	263	/! @brief Read current value of the CAN_MCR_AEN field. /
Kojto	90:cb3d968589d8	264	#define BR_CAN_MCR_AEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_AEN))
Kojto	90:cb3d968589d8	265
Kojto	90:cb3d968589d8	266	/! @brief Format value for bitfield CAN_MCR_AEN. /
Kojto	90:cb3d968589d8	267	#define BF_CAN_MCR_AEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_AEN) & BM_CAN_MCR_AEN)
Kojto	90:cb3d968589d8	268
Kojto	90:cb3d968589d8	269	/! @brief Set the AEN field to a new value. /
Kojto	90:cb3d968589d8	270	#define BW_CAN_MCR_AEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_AEN) = (v))
Kojto	90:cb3d968589d8	271	/@}/
Kojto	90:cb3d968589d8	272
Kojto	90:cb3d968589d8	273	/*!
Kojto	90:cb3d968589d8	274	* @name Register CAN_MCR, field LPRIOEN[13] (RW)
Kojto	90:cb3d968589d8	275	*
Kojto	90:cb3d968589d8	276	* This bit is provided for backwards compatibility with legacy applications. It
Kojto	90:cb3d968589d8	277	* controls whether the local priority feature is enabled or not. It is used to
Kojto	90:cb3d968589d8	278	* expand the ID used during the arbitration process. With this expanded ID
Kojto	90:cb3d968589d8	279	* concept, the arbitration process is done based on the full 32-bit word, but the
Kojto	90:cb3d968589d8	280	* actual transmitted ID still has 11-bit for standard frames and 29-bit for
Kojto	90:cb3d968589d8	281	* extended frames. This bit can be written only in Freeze mode because it is blocked by
Kojto	90:cb3d968589d8	282	* hardware in other modes.
Kojto	90:cb3d968589d8	283	*
Kojto	90:cb3d968589d8	284	* Values:
Kojto	90:cb3d968589d8	285	* - 0 - Local Priority disabled.
Kojto	90:cb3d968589d8	286	* - 1 - Local Priority enabled.
Kojto	90:cb3d968589d8	287	*/
Kojto	90:cb3d968589d8	288	/@{/
Kojto	90:cb3d968589d8	289	#define BP_CAN_MCR_LPRIOEN (13U) /!< Bit position for CAN_MCR_LPRIOEN. /
Kojto	90:cb3d968589d8	290	#define BM_CAN_MCR_LPRIOEN (0x00002000U) /!< Bit mask for CAN_MCR_LPRIOEN. /
Kojto	90:cb3d968589d8	291	#define BS_CAN_MCR_LPRIOEN (1U) /!< Bit field size in bits for CAN_MCR_LPRIOEN. /
Kojto	90:cb3d968589d8	292
Kojto	90:cb3d968589d8	293	/! @brief Read current value of the CAN_MCR_LPRIOEN field. /
Kojto	90:cb3d968589d8	294	#define BR_CAN_MCR_LPRIOEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPRIOEN))
Kojto	90:cb3d968589d8	295
Kojto	90:cb3d968589d8	296	/! @brief Format value for bitfield CAN_MCR_LPRIOEN. /
Kojto	90:cb3d968589d8	297	#define BF_CAN_MCR_LPRIOEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_LPRIOEN) & BM_CAN_MCR_LPRIOEN)
Kojto	90:cb3d968589d8	298
Kojto	90:cb3d968589d8	299	/! @brief Set the LPRIOEN field to a new value. /
Kojto	90:cb3d968589d8	300	#define BW_CAN_MCR_LPRIOEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPRIOEN) = (v))
Kojto	90:cb3d968589d8	301	/@}/
Kojto	90:cb3d968589d8	302
Kojto	90:cb3d968589d8	303	/*!
Kojto	90:cb3d968589d8	304	* @name Register CAN_MCR, field IRMQ[16] (RW)
Kojto	90:cb3d968589d8	305	*
Kojto	90:cb3d968589d8	306	* This bit indicates whether Rx matching process will be based either on
Kojto	90:cb3d968589d8	307	* individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and
Kojto	90:cb3d968589d8	308	* RX15MASK, RXFGMASK. This bit can be written only in Freeze mode because it is
Kojto	90:cb3d968589d8	309	* blocked by hardware in other modes.
Kojto	90:cb3d968589d8	310	*
Kojto	90:cb3d968589d8	311	* Values:
Kojto	90:cb3d968589d8	312	* - 0 - Individual Rx masking and queue feature are disabled. For backward
Kojto	90:cb3d968589d8	313	* compatibility with legacy applications, the reading of C/S word locks the MB
Kojto	90:cb3d968589d8	314	* even if it is EMPTY.
Kojto	90:cb3d968589d8	315	* - 1 - Individual Rx masking and queue feature are enabled.
Kojto	90:cb3d968589d8	316	*/
Kojto	90:cb3d968589d8	317	/@{/
Kojto	90:cb3d968589d8	318	#define BP_CAN_MCR_IRMQ (16U) /!< Bit position for CAN_MCR_IRMQ. /
Kojto	90:cb3d968589d8	319	#define BM_CAN_MCR_IRMQ (0x00010000U) /!< Bit mask for CAN_MCR_IRMQ. /
Kojto	90:cb3d968589d8	320	#define BS_CAN_MCR_IRMQ (1U) /!< Bit field size in bits for CAN_MCR_IRMQ. /
Kojto	90:cb3d968589d8	321
Kojto	90:cb3d968589d8	322	/! @brief Read current value of the CAN_MCR_IRMQ field. /
Kojto	90:cb3d968589d8	323	#define BR_CAN_MCR_IRMQ(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_IRMQ))
Kojto	90:cb3d968589d8	324
Kojto	90:cb3d968589d8	325	/! @brief Format value for bitfield CAN_MCR_IRMQ. /
Kojto	90:cb3d968589d8	326	#define BF_CAN_MCR_IRMQ(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_IRMQ) & BM_CAN_MCR_IRMQ)
Kojto	90:cb3d968589d8	327
Kojto	90:cb3d968589d8	328	/! @brief Set the IRMQ field to a new value. /
Kojto	90:cb3d968589d8	329	#define BW_CAN_MCR_IRMQ(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_IRMQ) = (v))
Kojto	90:cb3d968589d8	330	/@}/
Kojto	90:cb3d968589d8	331
Kojto	90:cb3d968589d8	332	/*!
Kojto	90:cb3d968589d8	333	* @name Register CAN_MCR, field SRXDIS[17] (RW)
Kojto	90:cb3d968589d8	334	*
Kojto	90:cb3d968589d8	335	* This bit defines whether FlexCAN is allowed to receive frames transmitted by
Kojto	90:cb3d968589d8	336	* itself. If this bit is asserted, frames transmitted by the module will not be
Kojto	90:cb3d968589d8	337	* stored in any MB, regardless if the MB is programmed with an ID that matches
Kojto	90:cb3d968589d8	338	* the transmitted frame, and no interrupt flag or interrupt signal will be
Kojto	90:cb3d968589d8	339	* generated due to the frame reception. This bit can be written only in Freeze mode
Kojto	90:cb3d968589d8	340	* because it is blocked by hardware in other modes.
Kojto	90:cb3d968589d8	341	*
Kojto	90:cb3d968589d8	342	* Values:
Kojto	90:cb3d968589d8	343	* - 0 - Self reception enabled.
Kojto	90:cb3d968589d8	344	* - 1 - Self reception disabled.
Kojto	90:cb3d968589d8	345	*/
Kojto	90:cb3d968589d8	346	/@{/
Kojto	90:cb3d968589d8	347	#define BP_CAN_MCR_SRXDIS (17U) /!< Bit position for CAN_MCR_SRXDIS. /
Kojto	90:cb3d968589d8	348	#define BM_CAN_MCR_SRXDIS (0x00020000U) /!< Bit mask for CAN_MCR_SRXDIS. /
Kojto	90:cb3d968589d8	349	#define BS_CAN_MCR_SRXDIS (1U) /!< Bit field size in bits for CAN_MCR_SRXDIS. /
Kojto	90:cb3d968589d8	350
Kojto	90:cb3d968589d8	351	/! @brief Read current value of the CAN_MCR_SRXDIS field. /
Kojto	90:cb3d968589d8	352	#define BR_CAN_MCR_SRXDIS(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SRXDIS))
Kojto	90:cb3d968589d8	353
Kojto	90:cb3d968589d8	354	/! @brief Format value for bitfield CAN_MCR_SRXDIS. /
Kojto	90:cb3d968589d8	355	#define BF_CAN_MCR_SRXDIS(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SRXDIS) & BM_CAN_MCR_SRXDIS)
Kojto	90:cb3d968589d8	356
Kojto	90:cb3d968589d8	357	/! @brief Set the SRXDIS field to a new value. /
Kojto	90:cb3d968589d8	358	#define BW_CAN_MCR_SRXDIS(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SRXDIS) = (v))
Kojto	90:cb3d968589d8	359	/@}/
Kojto	90:cb3d968589d8	360
Kojto	90:cb3d968589d8	361	/*!
Kojto	90:cb3d968589d8	362	* @name Register CAN_MCR, field WAKSRC[19] (RW)
Kojto	90:cb3d968589d8	363	*
Kojto	90:cb3d968589d8	364	* This bit defines whether the integrated low-pass filter is applied to protect
Kojto	90:cb3d968589d8	365	* the Rx CAN input from spurious wake up. This bit can be written only in
Kojto	90:cb3d968589d8	366	* Freeze mode because it is blocked by hardware in other modes.
Kojto	90:cb3d968589d8	367	*
Kojto	90:cb3d968589d8	368	* Values:
Kojto	90:cb3d968589d8	369	* - 0 - FlexCAN uses the unfiltered Rx input to detect recessive to dominant
Kojto	90:cb3d968589d8	370	* edges on the CAN bus.
Kojto	90:cb3d968589d8	371	* - 1 - FlexCAN uses the filtered Rx input to detect recessive to dominant
Kojto	90:cb3d968589d8	372	* edges on the CAN bus.
Kojto	90:cb3d968589d8	373	*/
Kojto	90:cb3d968589d8	374	/@{/
Kojto	90:cb3d968589d8	375	#define BP_CAN_MCR_WAKSRC (19U) /!< Bit position for CAN_MCR_WAKSRC. /
Kojto	90:cb3d968589d8	376	#define BM_CAN_MCR_WAKSRC (0x00080000U) /!< Bit mask for CAN_MCR_WAKSRC. /
Kojto	90:cb3d968589d8	377	#define BS_CAN_MCR_WAKSRC (1U) /!< Bit field size in bits for CAN_MCR_WAKSRC. /
Kojto	90:cb3d968589d8	378
Kojto	90:cb3d968589d8	379	/! @brief Read current value of the CAN_MCR_WAKSRC field. /
Kojto	90:cb3d968589d8	380	#define BR_CAN_MCR_WAKSRC(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKSRC))
Kojto	90:cb3d968589d8	381
Kojto	90:cb3d968589d8	382	/! @brief Format value for bitfield CAN_MCR_WAKSRC. /
Kojto	90:cb3d968589d8	383	#define BF_CAN_MCR_WAKSRC(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_WAKSRC) & BM_CAN_MCR_WAKSRC)
Kojto	90:cb3d968589d8	384
Kojto	90:cb3d968589d8	385	/! @brief Set the WAKSRC field to a new value. /
Kojto	90:cb3d968589d8	386	#define BW_CAN_MCR_WAKSRC(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKSRC) = (v))
Kojto	90:cb3d968589d8	387	/@}/
Kojto	90:cb3d968589d8	388
Kojto	90:cb3d968589d8	389	/*!
Kojto	90:cb3d968589d8	390	* @name Register CAN_MCR, field LPMACK[20] (RO)
Kojto	90:cb3d968589d8	391	*
Kojto	90:cb3d968589d8	392	* This read-only bit indicates that FlexCAN is in a low-power mode (Disable
Kojto	90:cb3d968589d8	393	* mode , Stop mode ). A low-power mode cannot be entered until all current
Kojto	90:cb3d968589d8	394	* transmission or reception processes have finished, so the CPU can poll the LPMACK bit
Kojto	90:cb3d968589d8	395	* to know when FlexCAN has actually entered low power mode. LPMACK will be
Kojto	90:cb3d968589d8	396	* asserted within 180 CAN bits from the low-power mode request by the CPU, and
Kojto	90:cb3d968589d8	397	* negated within 2 CAN bits after the low-power mode request removal (see Section
Kojto	90:cb3d968589d8	398	* "Protocol Timing").
Kojto	90:cb3d968589d8	399	*
Kojto	90:cb3d968589d8	400	* Values:
Kojto	90:cb3d968589d8	401	* - 0 - FlexCAN is not in a low-power mode.
Kojto	90:cb3d968589d8	402	* - 1 - FlexCAN is in a low-power mode.
Kojto	90:cb3d968589d8	403	*/
Kojto	90:cb3d968589d8	404	/@{/
Kojto	90:cb3d968589d8	405	#define BP_CAN_MCR_LPMACK (20U) /!< Bit position for CAN_MCR_LPMACK. /
Kojto	90:cb3d968589d8	406	#define BM_CAN_MCR_LPMACK (0x00100000U) /!< Bit mask for CAN_MCR_LPMACK. /
Kojto	90:cb3d968589d8	407	#define BS_CAN_MCR_LPMACK (1U) /!< Bit field size in bits for CAN_MCR_LPMACK. /
Kojto	90:cb3d968589d8	408
Kojto	90:cb3d968589d8	409	/! @brief Read current value of the CAN_MCR_LPMACK field. /
Kojto	90:cb3d968589d8	410	#define BR_CAN_MCR_LPMACK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPMACK))
Kojto	90:cb3d968589d8	411	/@}/
Kojto	90:cb3d968589d8	412
Kojto	90:cb3d968589d8	413	/*!
Kojto	90:cb3d968589d8	414	* @name Register CAN_MCR, field WRNEN[21] (RW)
Kojto	90:cb3d968589d8	415	*
Kojto	90:cb3d968589d8	416	* When asserted, this bit enables the generation of the TWRNINT and RWRNINT
Kojto	90:cb3d968589d8	417	* flags in the Error and Status Register. If WRNEN is negated, the TWRNINT and
Kojto	90:cb3d968589d8	418	* RWRNINT flags will always be zero, independent of the values of the error
Kojto	90:cb3d968589d8	419	* counters, and no warning interrupt will ever be generated. This bit can be written
Kojto	90:cb3d968589d8	420	* only in Freeze mode because it is blocked by hardware in other modes.
Kojto	90:cb3d968589d8	421	*
Kojto	90:cb3d968589d8	422	* Values:
Kojto	90:cb3d968589d8	423	* - 0 - TWRNINT and RWRNINT bits are zero, independent of the values in the
Kojto	90:cb3d968589d8	424	* error counters.
Kojto	90:cb3d968589d8	425	* - 1 - TWRNINT and RWRNINT bits are set when the respective error counter
Kojto	90:cb3d968589d8	426	* transitions from less than 96 to greater than or equal to 96.
Kojto	90:cb3d968589d8	427	*/
Kojto	90:cb3d968589d8	428	/@{/
Kojto	90:cb3d968589d8	429	#define BP_CAN_MCR_WRNEN (21U) /!< Bit position for CAN_MCR_WRNEN. /
Kojto	90:cb3d968589d8	430	#define BM_CAN_MCR_WRNEN (0x00200000U) /!< Bit mask for CAN_MCR_WRNEN. /
Kojto	90:cb3d968589d8	431	#define BS_CAN_MCR_WRNEN (1U) /!< Bit field size in bits for CAN_MCR_WRNEN. /
Kojto	90:cb3d968589d8	432
Kojto	90:cb3d968589d8	433	/! @brief Read current value of the CAN_MCR_WRNEN field. /
Kojto	90:cb3d968589d8	434	#define BR_CAN_MCR_WRNEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WRNEN))
Kojto	90:cb3d968589d8	435
Kojto	90:cb3d968589d8	436	/! @brief Format value for bitfield CAN_MCR_WRNEN. /
Kojto	90:cb3d968589d8	437	#define BF_CAN_MCR_WRNEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_WRNEN) & BM_CAN_MCR_WRNEN)
Kojto	90:cb3d968589d8	438
Kojto	90:cb3d968589d8	439	/! @brief Set the WRNEN field to a new value. /
Kojto	90:cb3d968589d8	440	#define BW_CAN_MCR_WRNEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WRNEN) = (v))
Kojto	90:cb3d968589d8	441	/@}/
Kojto	90:cb3d968589d8	442
Kojto	90:cb3d968589d8	443	/*!
Kojto	90:cb3d968589d8	444	* @name Register CAN_MCR, field SLFWAK[22] (RW)
Kojto	90:cb3d968589d8	445	*
Kojto	90:cb3d968589d8	446	* This bit enables the Self Wake Up feature when FlexCAN is in a low-power mode
Kojto	90:cb3d968589d8	447	* other than Disable mode. When this feature is enabled, the FlexCAN module
Kojto	90:cb3d968589d8	448	* monitors the bus for wake up event, that is, a recessive-to-dominant transition.
Kojto	90:cb3d968589d8	449	* If a wake up event is detected during Stop mode, then FlexCAN generates, if
Kojto	90:cb3d968589d8	450	* enabled to do so, a Wake Up interrupt to the CPU so that it can exit Stop mode
Kojto	90:cb3d968589d8	451	* globally and FlexCAN can request to resume the clocks. When FlexCAN is in a
Kojto	90:cb3d968589d8	452	* low-power mode other than Disable mode, this bit cannot be written as it is
Kojto	90:cb3d968589d8	453	* blocked by hardware.
Kojto	90:cb3d968589d8	454	*
Kojto	90:cb3d968589d8	455	* Values:
Kojto	90:cb3d968589d8	456	* - 0 - FlexCAN Self Wake Up feature is disabled.
Kojto	90:cb3d968589d8	457	* - 1 - FlexCAN Self Wake Up feature is enabled.
Kojto	90:cb3d968589d8	458	*/
Kojto	90:cb3d968589d8	459	/@{/
Kojto	90:cb3d968589d8	460	#define BP_CAN_MCR_SLFWAK (22U) /!< Bit position for CAN_MCR_SLFWAK. /
Kojto	90:cb3d968589d8	461	#define BM_CAN_MCR_SLFWAK (0x00400000U) /!< Bit mask for CAN_MCR_SLFWAK. /
Kojto	90:cb3d968589d8	462	#define BS_CAN_MCR_SLFWAK (1U) /!< Bit field size in bits for CAN_MCR_SLFWAK. /
Kojto	90:cb3d968589d8	463
Kojto	90:cb3d968589d8	464	/! @brief Read current value of the CAN_MCR_SLFWAK field. /
Kojto	90:cb3d968589d8	465	#define BR_CAN_MCR_SLFWAK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SLFWAK))
Kojto	90:cb3d968589d8	466
Kojto	90:cb3d968589d8	467	/! @brief Format value for bitfield CAN_MCR_SLFWAK. /
Kojto	90:cb3d968589d8	468	#define BF_CAN_MCR_SLFWAK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SLFWAK) & BM_CAN_MCR_SLFWAK)
Kojto	90:cb3d968589d8	469
Kojto	90:cb3d968589d8	470	/! @brief Set the SLFWAK field to a new value. /
Kojto	90:cb3d968589d8	471	#define BW_CAN_MCR_SLFWAK(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SLFWAK) = (v))
Kojto	90:cb3d968589d8	472	/@}/
Kojto	90:cb3d968589d8	473
Kojto	90:cb3d968589d8	474	/*!
Kojto	90:cb3d968589d8	475	* @name Register CAN_MCR, field SUPV[23] (RW)
Kojto	90:cb3d968589d8	476	*
Kojto	90:cb3d968589d8	477	* This bit configures the FlexCAN to be either in Supervisor or User mode. The
Kojto	90:cb3d968589d8	478	* registers affected by this bit are marked as S/U in the Access Type column of
Kojto	90:cb3d968589d8	479	* the module memory map. Reset value of this bit is 1, so the affected registers
Kojto	90:cb3d968589d8	480	* start with Supervisor access allowance only . This bit can be written only in
Kojto	90:cb3d968589d8	481	* Freeze mode because it is blocked by hardware in other modes.
Kojto	90:cb3d968589d8	482	*
Kojto	90:cb3d968589d8	483	* Values:
Kojto	90:cb3d968589d8	484	* - 0 - FlexCAN is in User mode. Affected registers allow both Supervisor and
Kojto	90:cb3d968589d8	485	* Unrestricted accesses .
Kojto	90:cb3d968589d8	486	* - 1 - FlexCAN is in Supervisor mode. Affected registers allow only Supervisor
Kojto	90:cb3d968589d8	487	* access. Unrestricted access behaves as though the access was done to an
Kojto	90:cb3d968589d8	488	* unimplemented register location .
Kojto	90:cb3d968589d8	489	*/
Kojto	90:cb3d968589d8	490	/@{/
Kojto	90:cb3d968589d8	491	#define BP_CAN_MCR_SUPV (23U) /!< Bit position for CAN_MCR_SUPV. /
Kojto	90:cb3d968589d8	492	#define BM_CAN_MCR_SUPV (0x00800000U) /!< Bit mask for CAN_MCR_SUPV. /
Kojto	90:cb3d968589d8	493	#define BS_CAN_MCR_SUPV (1U) /!< Bit field size in bits for CAN_MCR_SUPV. /
Kojto	90:cb3d968589d8	494
Kojto	90:cb3d968589d8	495	/! @brief Read current value of the CAN_MCR_SUPV field. /
Kojto	90:cb3d968589d8	496	#define BR_CAN_MCR_SUPV(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SUPV))
Kojto	90:cb3d968589d8	497
Kojto	90:cb3d968589d8	498	/! @brief Format value for bitfield CAN_MCR_SUPV. /
Kojto	90:cb3d968589d8	499	#define BF_CAN_MCR_SUPV(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SUPV) & BM_CAN_MCR_SUPV)
Kojto	90:cb3d968589d8	500
Kojto	90:cb3d968589d8	501	/! @brief Set the SUPV field to a new value. /
Kojto	90:cb3d968589d8	502	#define BW_CAN_MCR_SUPV(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SUPV) = (v))
Kojto	90:cb3d968589d8	503	/@}/
Kojto	90:cb3d968589d8	504
Kojto	90:cb3d968589d8	505	/*!
Kojto	90:cb3d968589d8	506	* @name Register CAN_MCR, field FRZACK[24] (RO)
Kojto	90:cb3d968589d8	507	*
Kojto	90:cb3d968589d8	508	* This read-only bit indicates that FlexCAN is in Freeze mode and its prescaler
Kojto	90:cb3d968589d8	509	* is stopped. The Freeze mode request cannot be granted until current
Kojto	90:cb3d968589d8	510	* transmission or reception processes have finished. Therefore the software can poll the
Kojto	90:cb3d968589d8	511	* FRZACK bit to know when FlexCAN has actually entered Freeze mode. If Freeze
Kojto	90:cb3d968589d8	512	* Mode request is negated, then this bit is negated after the FlexCAN prescaler is
Kojto	90:cb3d968589d8	513	* running again. If Freeze mode is requested while FlexCAN is in a low power
Kojto	90:cb3d968589d8	514	* mode, then the FRZACK bit will be set only when the low-power mode is exited.
Kojto	90:cb3d968589d8	515	* See Section "Freeze Mode". FRZACK will be asserted within 178 CAN bits from the
Kojto	90:cb3d968589d8	516	* freeze mode request by the CPU, and negated within 2 CAN bits after the freeze
Kojto	90:cb3d968589d8	517	* mode request removal (see Section "Protocol Timing").
Kojto	90:cb3d968589d8	518	*
Kojto	90:cb3d968589d8	519	* Values:
Kojto	90:cb3d968589d8	520	* - 0 - FlexCAN not in Freeze mode, prescaler running.
Kojto	90:cb3d968589d8	521	* - 1 - FlexCAN in Freeze mode, prescaler stopped.
Kojto	90:cb3d968589d8	522	*/
Kojto	90:cb3d968589d8	523	/@{/
Kojto	90:cb3d968589d8	524	#define BP_CAN_MCR_FRZACK (24U) /!< Bit position for CAN_MCR_FRZACK. /
Kojto	90:cb3d968589d8	525	#define BM_CAN_MCR_FRZACK (0x01000000U) /!< Bit mask for CAN_MCR_FRZACK. /
Kojto	90:cb3d968589d8	526	#define BS_CAN_MCR_FRZACK (1U) /!< Bit field size in bits for CAN_MCR_FRZACK. /
Kojto	90:cb3d968589d8	527
Kojto	90:cb3d968589d8	528	/! @brief Read current value of the CAN_MCR_FRZACK field. /
Kojto	90:cb3d968589d8	529	#define BR_CAN_MCR_FRZACK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZACK))
Kojto	90:cb3d968589d8	530	/@}/
Kojto	90:cb3d968589d8	531
Kojto	90:cb3d968589d8	532	/*!
Kojto	90:cb3d968589d8	533	* @name Register CAN_MCR, field SOFTRST[25] (RW)
Kojto	90:cb3d968589d8	534	*
Kojto	90:cb3d968589d8	535	* When this bit is asserted, FlexCAN resets its internal state machines and
Kojto	90:cb3d968589d8	536	* some of the memory mapped registers. The following registers are reset: MCR
Kojto	90:cb3d968589d8	537	* (except the MDIS bit), TIMER , ECR, ESR1, ESR2, IMASK1, IMASK2, IFLAG1, IFLAG2 and
Kojto	90:cb3d968589d8	538	* CRCR. Configuration registers that control the interface to the CAN bus are
Kojto	90:cb3d968589d8	539	* not affected by soft reset. The following registers are unaffected: CTRL1,
Kojto	90:cb3d968589d8	540	* CTRL2, all RXIMR registers, RXMGMASK, RX14MASK, RX15MASK, RXFGMASK, RXFIR, all
Kojto	90:cb3d968589d8	541	* Message Buffers . The SOFTRST bit can be asserted directly by the CPU when it
Kojto	90:cb3d968589d8	542	* writes to the MCR Register, but it is also asserted when global soft reset is
Kojto	90:cb3d968589d8	543	* requested at MCU level . Because soft reset is synchronous and has to follow a
Kojto	90:cb3d968589d8	544	* request/acknowledge procedure across clock domains, it may take some time to
Kojto	90:cb3d968589d8	545	* fully propagate its effect. The SOFTRST bit remains asserted while reset is
Kojto	90:cb3d968589d8	546	* pending, and is automatically negated when reset completes. Therefore, software can
Kojto	90:cb3d968589d8	547	* poll this bit to know when the soft reset has completed. Soft reset cannot be
Kojto	90:cb3d968589d8	548	* applied while clocks are shut down in a low power mode. The module should be
Kojto	90:cb3d968589d8	549	* first removed from low power mode, and then soft reset can be applied.
Kojto	90:cb3d968589d8	550	*
Kojto	90:cb3d968589d8	551	* Values:
Kojto	90:cb3d968589d8	552	* - 0 - No reset request.
Kojto	90:cb3d968589d8	553	* - 1 - Resets the registers affected by soft reset.
Kojto	90:cb3d968589d8	554	*/
Kojto	90:cb3d968589d8	555	/@{/
Kojto	90:cb3d968589d8	556	#define BP_CAN_MCR_SOFTRST (25U) /!< Bit position for CAN_MCR_SOFTRST. /
Kojto	90:cb3d968589d8	557	#define BM_CAN_MCR_SOFTRST (0x02000000U) /!< Bit mask for CAN_MCR_SOFTRST. /
Kojto	90:cb3d968589d8	558	#define BS_CAN_MCR_SOFTRST (1U) /!< Bit field size in bits for CAN_MCR_SOFTRST. /
Kojto	90:cb3d968589d8	559
Kojto	90:cb3d968589d8	560	/! @brief Read current value of the CAN_MCR_SOFTRST field. /
Kojto	90:cb3d968589d8	561	#define BR_CAN_MCR_SOFTRST(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SOFTRST))
Kojto	90:cb3d968589d8	562
Kojto	90:cb3d968589d8	563	/! @brief Format value for bitfield CAN_MCR_SOFTRST. /
Kojto	90:cb3d968589d8	564	#define BF_CAN_MCR_SOFTRST(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SOFTRST) & BM_CAN_MCR_SOFTRST)
Kojto	90:cb3d968589d8	565
Kojto	90:cb3d968589d8	566	/! @brief Set the SOFTRST field to a new value. /
Kojto	90:cb3d968589d8	567	#define BW_CAN_MCR_SOFTRST(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SOFTRST) = (v))
Kojto	90:cb3d968589d8	568	/@}/
Kojto	90:cb3d968589d8	569
Kojto	90:cb3d968589d8	570	/*!
Kojto	90:cb3d968589d8	571	* @name Register CAN_MCR, field WAKMSK[26] (RW)
Kojto	90:cb3d968589d8	572	*
Kojto	90:cb3d968589d8	573	* This bit enables the Wake Up Interrupt generation under Self Wake Up
Kojto	90:cb3d968589d8	574	* mechanism.
Kojto	90:cb3d968589d8	575	*
Kojto	90:cb3d968589d8	576	* Values:
Kojto	90:cb3d968589d8	577	* - 0 - Wake Up Interrupt is disabled.
Kojto	90:cb3d968589d8	578	* - 1 - Wake Up Interrupt is enabled.
Kojto	90:cb3d968589d8	579	*/
Kojto	90:cb3d968589d8	580	/@{/
Kojto	90:cb3d968589d8	581	#define BP_CAN_MCR_WAKMSK (26U) /!< Bit position for CAN_MCR_WAKMSK. /
Kojto	90:cb3d968589d8	582	#define BM_CAN_MCR_WAKMSK (0x04000000U) /!< Bit mask for CAN_MCR_WAKMSK. /
Kojto	90:cb3d968589d8	583	#define BS_CAN_MCR_WAKMSK (1U) /!< Bit field size in bits for CAN_MCR_WAKMSK. /
Kojto	90:cb3d968589d8	584
Kojto	90:cb3d968589d8	585	/! @brief Read current value of the CAN_MCR_WAKMSK field. /
Kojto	90:cb3d968589d8	586	#define BR_CAN_MCR_WAKMSK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKMSK))
Kojto	90:cb3d968589d8	587
Kojto	90:cb3d968589d8	588	/! @brief Format value for bitfield CAN_MCR_WAKMSK. /
Kojto	90:cb3d968589d8	589	#define BF_CAN_MCR_WAKMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_WAKMSK) & BM_CAN_MCR_WAKMSK)
Kojto	90:cb3d968589d8	590
Kojto	90:cb3d968589d8	591	/! @brief Set the WAKMSK field to a new value. /
Kojto	90:cb3d968589d8	592	#define BW_CAN_MCR_WAKMSK(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKMSK) = (v))
Kojto	90:cb3d968589d8	593	/@}/
Kojto	90:cb3d968589d8	594
Kojto	90:cb3d968589d8	595	/*!
Kojto	90:cb3d968589d8	596	* @name Register CAN_MCR, field NOTRDY[27] (RO)
Kojto	90:cb3d968589d8	597	*
Kojto	90:cb3d968589d8	598	* This read-only bit indicates that FlexCAN is either in Disable mode , Stop
Kojto	90:cb3d968589d8	599	* mode or Freeze mode. It is negated once FlexCAN has exited these modes.
Kojto	90:cb3d968589d8	600	*
Kojto	90:cb3d968589d8	601	* Values:
Kojto	90:cb3d968589d8	602	* - 0 - FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back
Kojto	90:cb3d968589d8	603	* mode.
Kojto	90:cb3d968589d8	604	* - 1 - FlexCAN module is either in Disable mode , Stop mode or Freeze mode.
Kojto	90:cb3d968589d8	605	*/
Kojto	90:cb3d968589d8	606	/@{/
Kojto	90:cb3d968589d8	607	#define BP_CAN_MCR_NOTRDY (27U) /!< Bit position for CAN_MCR_NOTRDY. /
Kojto	90:cb3d968589d8	608	#define BM_CAN_MCR_NOTRDY (0x08000000U) /!< Bit mask for CAN_MCR_NOTRDY. /
Kojto	90:cb3d968589d8	609	#define BS_CAN_MCR_NOTRDY (1U) /!< Bit field size in bits for CAN_MCR_NOTRDY. /
Kojto	90:cb3d968589d8	610
Kojto	90:cb3d968589d8	611	/! @brief Read current value of the CAN_MCR_NOTRDY field. /
Kojto	90:cb3d968589d8	612	#define BR_CAN_MCR_NOTRDY(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_NOTRDY))
Kojto	90:cb3d968589d8	613	/@}/
Kojto	90:cb3d968589d8	614
Kojto	90:cb3d968589d8	615	/*!
Kojto	90:cb3d968589d8	616	* @name Register CAN_MCR, field HALT[28] (RW)
Kojto	90:cb3d968589d8	617	*
Kojto	90:cb3d968589d8	618	* Assertion of this bit puts the FlexCAN module into Freeze mode. The CPU
Kojto	90:cb3d968589d8	619	* should clear it after initializing the Message Buffers and Control Register. No
Kojto	90:cb3d968589d8	620	* reception or transmission is performed by FlexCAN before this bit is cleared.
Kojto	90:cb3d968589d8	621	* Freeze mode cannot be entered while FlexCAN is in a low power mode.
Kojto	90:cb3d968589d8	622	*
Kojto	90:cb3d968589d8	623	* Values:
Kojto	90:cb3d968589d8	624	* - 0 - No Freeze mode request.
Kojto	90:cb3d968589d8	625	* - 1 - Enters Freeze mode if the FRZ bit is asserted.
Kojto	90:cb3d968589d8	626	*/
Kojto	90:cb3d968589d8	627	/@{/
Kojto	90:cb3d968589d8	628	#define BP_CAN_MCR_HALT (28U) /!< Bit position for CAN_MCR_HALT. /
Kojto	90:cb3d968589d8	629	#define BM_CAN_MCR_HALT (0x10000000U) /!< Bit mask for CAN_MCR_HALT. /
Kojto	90:cb3d968589d8	630	#define BS_CAN_MCR_HALT (1U) /!< Bit field size in bits for CAN_MCR_HALT. /
Kojto	90:cb3d968589d8	631
Kojto	90:cb3d968589d8	632	/! @brief Read current value of the CAN_MCR_HALT field. /
Kojto	90:cb3d968589d8	633	#define BR_CAN_MCR_HALT(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_HALT))
Kojto	90:cb3d968589d8	634
Kojto	90:cb3d968589d8	635	/! @brief Format value for bitfield CAN_MCR_HALT. /
Kojto	90:cb3d968589d8	636	#define BF_CAN_MCR_HALT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_HALT) & BM_CAN_MCR_HALT)
Kojto	90:cb3d968589d8	637
Kojto	90:cb3d968589d8	638	/! @brief Set the HALT field to a new value. /
Kojto	90:cb3d968589d8	639	#define BW_CAN_MCR_HALT(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_HALT) = (v))
Kojto	90:cb3d968589d8	640	/@}/
Kojto	90:cb3d968589d8	641
Kojto	90:cb3d968589d8	642	/*!
Kojto	90:cb3d968589d8	643	* @name Register CAN_MCR, field RFEN[29] (RW)
Kojto	90:cb3d968589d8	644	*
Kojto	90:cb3d968589d8	645	* This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is
Kojto	90:cb3d968589d8	646	* set, MBs 0 to 5 cannot be used for normal reception and transmission because
Kojto	90:cb3d968589d8	647	* the corresponding memory region (0x80-0xDC) is used by the FIFO engine as well
Kojto	90:cb3d968589d8	648	* as additional MBs (up to 32, depending on CTRL2[RFFN] setting) which are used
Kojto	90:cb3d968589d8	649	* as Rx FIFO ID Filter Table elements. RFEN also impacts the definition of the
Kojto	90:cb3d968589d8	650	* minimum number of peripheral clocks per CAN bit as described in the table
Kojto	90:cb3d968589d8	651	* "Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate" (in section
Kojto	90:cb3d968589d8	652	* "Arbitration and Matching Timing"). This bit can be written only in Freeze mode
Kojto	90:cb3d968589d8	653	* because it is blocked by hardware in other modes.
Kojto	90:cb3d968589d8	654	*
Kojto	90:cb3d968589d8	655	* Values:
Kojto	90:cb3d968589d8	656	* - 0 - Rx FIFO not enabled.
Kojto	90:cb3d968589d8	657	* - 1 - Rx FIFO enabled.
Kojto	90:cb3d968589d8	658	*/
Kojto	90:cb3d968589d8	659	/@{/
Kojto	90:cb3d968589d8	660	#define BP_CAN_MCR_RFEN (29U) /!< Bit position for CAN_MCR_RFEN. /
Kojto	90:cb3d968589d8	661	#define BM_CAN_MCR_RFEN (0x20000000U) /!< Bit mask for CAN_MCR_RFEN. /
Kojto	90:cb3d968589d8	662	#define BS_CAN_MCR_RFEN (1U) /!< Bit field size in bits for CAN_MCR_RFEN. /
Kojto	90:cb3d968589d8	663
Kojto	90:cb3d968589d8	664	/! @brief Read current value of the CAN_MCR_RFEN field. /
Kojto	90:cb3d968589d8	665	#define BR_CAN_MCR_RFEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_RFEN))
Kojto	90:cb3d968589d8	666
Kojto	90:cb3d968589d8	667	/! @brief Format value for bitfield CAN_MCR_RFEN. /
Kojto	90:cb3d968589d8	668	#define BF_CAN_MCR_RFEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_RFEN) & BM_CAN_MCR_RFEN)
Kojto	90:cb3d968589d8	669
Kojto	90:cb3d968589d8	670	/! @brief Set the RFEN field to a new value. /
Kojto	90:cb3d968589d8	671	#define BW_CAN_MCR_RFEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_RFEN) = (v))
Kojto	90:cb3d968589d8	672	/@}/
Kojto	90:cb3d968589d8	673
Kojto	90:cb3d968589d8	674	/*!
Kojto	90:cb3d968589d8	675	* @name Register CAN_MCR, field FRZ[30] (RW)
Kojto	90:cb3d968589d8	676	*
Kojto	90:cb3d968589d8	677	* The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR
Kojto	90:cb3d968589d8	678	* Register is set or when Debug mode is requested at MCU level . When FRZ is
Kojto	90:cb3d968589d8	679	* asserted, FlexCAN is enabled to enter Freeze mode. Negation of this bit field causes
Kojto	90:cb3d968589d8	680	* FlexCAN to exit from Freeze mode.
Kojto	90:cb3d968589d8	681	*
Kojto	90:cb3d968589d8	682	* Values:
Kojto	90:cb3d968589d8	683	* - 0 - Not enabled to enter Freeze mode.
Kojto	90:cb3d968589d8	684	* - 1 - Enabled to enter Freeze mode.
Kojto	90:cb3d968589d8	685	*/
Kojto	90:cb3d968589d8	686	/@{/
Kojto	90:cb3d968589d8	687	#define BP_CAN_MCR_FRZ (30U) /!< Bit position for CAN_MCR_FRZ. /
Kojto	90:cb3d968589d8	688	#define BM_CAN_MCR_FRZ (0x40000000U) /!< Bit mask for CAN_MCR_FRZ. /
Kojto	90:cb3d968589d8	689	#define BS_CAN_MCR_FRZ (1U) /!< Bit field size in bits for CAN_MCR_FRZ. /
Kojto	90:cb3d968589d8	690
Kojto	90:cb3d968589d8	691	/! @brief Read current value of the CAN_MCR_FRZ field. /
Kojto	90:cb3d968589d8	692	#define BR_CAN_MCR_FRZ(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZ))
Kojto	90:cb3d968589d8	693
Kojto	90:cb3d968589d8	694	/! @brief Format value for bitfield CAN_MCR_FRZ. /
Kojto	90:cb3d968589d8	695	#define BF_CAN_MCR_FRZ(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_FRZ) & BM_CAN_MCR_FRZ)
Kojto	90:cb3d968589d8	696
Kojto	90:cb3d968589d8	697	/! @brief Set the FRZ field to a new value. /
Kojto	90:cb3d968589d8	698	#define BW_CAN_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZ) = (v))
Kojto	90:cb3d968589d8	699	/@}/
Kojto	90:cb3d968589d8	700
Kojto	90:cb3d968589d8	701	/*!
Kojto	90:cb3d968589d8	702	* @name Register CAN_MCR, field MDIS[31] (RW)
Kojto	90:cb3d968589d8	703	*
Kojto	90:cb3d968589d8	704	* This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN
Kojto	90:cb3d968589d8	705	* disables the clocks to the CAN Protocol Engine and Controller Host Interface
Kojto	90:cb3d968589d8	706	* sub-modules. This is the only bit within this register not affected by soft
Kojto	90:cb3d968589d8	707	* reset.
Kojto	90:cb3d968589d8	708	*
Kojto	90:cb3d968589d8	709	* Values:
Kojto	90:cb3d968589d8	710	* - 0 - Enable the FlexCAN module.
Kojto	90:cb3d968589d8	711	* - 1 - Disable the FlexCAN module.
Kojto	90:cb3d968589d8	712	*/
Kojto	90:cb3d968589d8	713	/@{/
Kojto	90:cb3d968589d8	714	#define BP_CAN_MCR_MDIS (31U) /!< Bit position for CAN_MCR_MDIS. /
Kojto	90:cb3d968589d8	715	#define BM_CAN_MCR_MDIS (0x80000000U) /!< Bit mask for CAN_MCR_MDIS. /
Kojto	90:cb3d968589d8	716	#define BS_CAN_MCR_MDIS (1U) /!< Bit field size in bits for CAN_MCR_MDIS. /
Kojto	90:cb3d968589d8	717
Kojto	90:cb3d968589d8	718	/! @brief Read current value of the CAN_MCR_MDIS field. /
Kojto	90:cb3d968589d8	719	#define BR_CAN_MCR_MDIS(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_MDIS))
Kojto	90:cb3d968589d8	720
Kojto	90:cb3d968589d8	721	/! @brief Format value for bitfield CAN_MCR_MDIS. /
Kojto	90:cb3d968589d8	722	#define BF_CAN_MCR_MDIS(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_MDIS) & BM_CAN_MCR_MDIS)
Kojto	90:cb3d968589d8	723
Kojto	90:cb3d968589d8	724	/! @brief Set the MDIS field to a new value. /
Kojto	90:cb3d968589d8	725	#define BW_CAN_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_MDIS) = (v))
Kojto	90:cb3d968589d8	726	/@}/
Kojto	90:cb3d968589d8	727
Kojto	90:cb3d968589d8	728	/*******************************************************************************
Kojto	90:cb3d968589d8	729	* HW_CAN_CTRL1 - Control 1 register
Kojto	90:cb3d968589d8	730	******************************************************************************/
Kojto	90:cb3d968589d8	731
Kojto	90:cb3d968589d8	732	/*!
Kojto	90:cb3d968589d8	733	* @brief HW_CAN_CTRL1 - Control 1 register (RW)
Kojto	90:cb3d968589d8	734	*
Kojto	90:cb3d968589d8	735	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	736	*
Kojto	90:cb3d968589d8	737	* This register is defined for specific FlexCAN control features related to the
Kojto	90:cb3d968589d8	738	* CAN bus, such as bit-rate, programmable sampling point within an Rx bit, Loop
Kojto	90:cb3d968589d8	739	* Back mode, Listen-Only mode, Bus Off recovery behavior and interrupt enabling
Kojto	90:cb3d968589d8	740	* (Bus-Off, Error, Warning). It also determines the Division Factor for the
Kojto	90:cb3d968589d8	741	* clock prescaler.
Kojto	90:cb3d968589d8	742	*/
Kojto	90:cb3d968589d8	743	typedef union _hw_can_ctrl1
Kojto	90:cb3d968589d8	744	{
Kojto	90:cb3d968589d8	745	uint32_t U;
Kojto	90:cb3d968589d8	746	struct _hw_can_ctrl1_bitfields
Kojto	90:cb3d968589d8	747	{
Kojto	90:cb3d968589d8	748	uint32_t PROPSEG : 3; /!< [2:0] Propagation Segment /
Kojto	90:cb3d968589d8	749	uint32_t LOM : 1; /!< [3] Listen-Only Mode /
Kojto	90:cb3d968589d8	750	uint32_t LBUF : 1; /!< [4] Lowest Buffer Transmitted First /
Kojto	90:cb3d968589d8	751	uint32_t TSYN : 1; /!< [5] Timer Sync /
Kojto	90:cb3d968589d8	752	uint32_t BOFFREC : 1; /!< [6] Bus Off Recovery /
Kojto	90:cb3d968589d8	753	uint32_t SMP : 1; /!< [7] CAN Bit Sampling /
Kojto	90:cb3d968589d8	754	uint32_t RESERVED0 : 2; /!< [9:8] /
Kojto	90:cb3d968589d8	755	uint32_t RWRNMSK : 1; /!< [10] Rx Warning Interrupt Mask /
Kojto	90:cb3d968589d8	756	uint32_t TWRNMSK : 1; /!< [11] Tx Warning Interrupt Mask /
Kojto	90:cb3d968589d8	757	uint32_t LPB : 1; /!< [12] Loop Back Mode /
Kojto	90:cb3d968589d8	758	uint32_t CLKSRC : 1; /!< [13] CAN Engine Clock Source /
Kojto	90:cb3d968589d8	759	uint32_t ERRMSK : 1; /!< [14] Error Mask /
Kojto	90:cb3d968589d8	760	uint32_t BOFFMSK : 1; /!< [15] Bus Off Mask /
Kojto	90:cb3d968589d8	761	uint32_t PSEG2 : 3; /!< [18:16] Phase Segment 2 /
Kojto	90:cb3d968589d8	762	uint32_t PSEG1 : 3; /!< [21:19] Phase Segment 1 /
Kojto	90:cb3d968589d8	763	uint32_t RJW : 2; /!< [23:22] Resync Jump Width /
Kojto	90:cb3d968589d8	764	uint32_t PRESDIV : 8; /!< [31:24] Prescaler Division Factor /
Kojto	90:cb3d968589d8	765	} B;
Kojto	90:cb3d968589d8	766	} hw_can_ctrl1_t;
Kojto	90:cb3d968589d8	767
Kojto	90:cb3d968589d8	768	/*!
Kojto	90:cb3d968589d8	769	* @name Constants and macros for entire CAN_CTRL1 register
Kojto	90:cb3d968589d8	770	*/
Kojto	90:cb3d968589d8	771	/@{/
Kojto	90:cb3d968589d8	772	#define HW_CAN_CTRL1_ADDR(x) ((x) + 0x4U)
Kojto	90:cb3d968589d8	773
Kojto	90:cb3d968589d8	774	#define HW_CAN_CTRL1(x) ((__IO hw_can_ctrl1_t ) HW_CAN_CTRL1_ADDR(x))
Kojto	90:cb3d968589d8	775	#define HW_CAN_CTRL1_RD(x) (HW_CAN_CTRL1(x).U)
Kojto	90:cb3d968589d8	776	#define HW_CAN_CTRL1_WR(x, v) (HW_CAN_CTRL1(x).U = (v))
Kojto	90:cb3d968589d8	777	#define HW_CAN_CTRL1_SET(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) \| (v)))
Kojto	90:cb3d968589d8	778	#define HW_CAN_CTRL1_CLR(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	779	#define HW_CAN_CTRL1_TOG(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	780	/@}/
Kojto	90:cb3d968589d8	781
Kojto	90:cb3d968589d8	782	/*
Kojto	90:cb3d968589d8	783	* Constants & macros for individual CAN_CTRL1 bitfields
Kojto	90:cb3d968589d8	784	*/
Kojto	90:cb3d968589d8	785
Kojto	90:cb3d968589d8	786	/*!
Kojto	90:cb3d968589d8	787	* @name Register CAN_CTRL1, field PROPSEG[2:0] (RW)
Kojto	90:cb3d968589d8	788	*
Kojto	90:cb3d968589d8	789	* This 3-bit field defines the length of the Propagation Segment in the bit
Kojto	90:cb3d968589d8	790	* time. The valid programmable values are 0-7. This field can be written only in
Kojto	90:cb3d968589d8	791	* Freeze mode because it is blocked by hardware in other modes. Propagation
Kojto	90:cb3d968589d8	792	* Segment Time = (PROPSEG + 1) * Time-Quanta. Time-Quantum = one Sclock period.
Kojto	90:cb3d968589d8	793	*/
Kojto	90:cb3d968589d8	794	/@{/
Kojto	90:cb3d968589d8	795	#define BP_CAN_CTRL1_PROPSEG (0U) /!< Bit position for CAN_CTRL1_PROPSEG. /
Kojto	90:cb3d968589d8	796	#define BM_CAN_CTRL1_PROPSEG (0x00000007U) /!< Bit mask for CAN_CTRL1_PROPSEG. /
Kojto	90:cb3d968589d8	797	#define BS_CAN_CTRL1_PROPSEG (3U) /!< Bit field size in bits for CAN_CTRL1_PROPSEG. /
Kojto	90:cb3d968589d8	798
Kojto	90:cb3d968589d8	799	/! @brief Read current value of the CAN_CTRL1_PROPSEG field. /
Kojto	90:cb3d968589d8	800	#define BR_CAN_CTRL1_PROPSEG(x) (HW_CAN_CTRL1(x).B.PROPSEG)
Kojto	90:cb3d968589d8	801
Kojto	90:cb3d968589d8	802	/! @brief Format value for bitfield CAN_CTRL1_PROPSEG. /
Kojto	90:cb3d968589d8	803	#define BF_CAN_CTRL1_PROPSEG(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PROPSEG) & BM_CAN_CTRL1_PROPSEG)
Kojto	90:cb3d968589d8	804
Kojto	90:cb3d968589d8	805	/! @brief Set the PROPSEG field to a new value. /
Kojto	90:cb3d968589d8	806	#define BW_CAN_CTRL1_PROPSEG(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PROPSEG) \| BF_CAN_CTRL1_PROPSEG(v)))
Kojto	90:cb3d968589d8	807	/@}/
Kojto	90:cb3d968589d8	808
Kojto	90:cb3d968589d8	809	/*!
Kojto	90:cb3d968589d8	810	* @name Register CAN_CTRL1, field LOM[3] (RW)
Kojto	90:cb3d968589d8	811	*
Kojto	90:cb3d968589d8	812	* This bit configures FlexCAN to operate in Listen-Only mode. In this mode,
Kojto	90:cb3d968589d8	813	* transmission is disabled, all error counters are frozen and the module operates
Kojto	90:cb3d968589d8	814	* in a CAN Error Passive mode. Only messages acknowledged by another CAN station
Kojto	90:cb3d968589d8	815	* will be received. If FlexCAN detects a message that has not been acknowledged,
Kojto	90:cb3d968589d8	816	* it will flag a BIT0 error without changing the REC, as if it was trying to
Kojto	90:cb3d968589d8	817	* acknowledge the message. Listen-Only mode acknowledgement can be obtained by the
Kojto	90:cb3d968589d8	818	* state of ESR1[FLTCONF] field which is Passive Error when Listen-Only mode is
Kojto	90:cb3d968589d8	819	* entered. There can be some delay between the Listen-Only mode request and
Kojto	90:cb3d968589d8	820	* acknowledge. This bit can be written only in Freeze mode because it is blocked by
Kojto	90:cb3d968589d8	821	* hardware in other modes.
Kojto	90:cb3d968589d8	822	*
Kojto	90:cb3d968589d8	823	* Values:
Kojto	90:cb3d968589d8	824	* - 0 - Listen-Only mode is deactivated.
Kojto	90:cb3d968589d8	825	* - 1 - FlexCAN module operates in Listen-Only mode.
Kojto	90:cb3d968589d8	826	*/
Kojto	90:cb3d968589d8	827	/@{/
Kojto	90:cb3d968589d8	828	#define BP_CAN_CTRL1_LOM (3U) /!< Bit position for CAN_CTRL1_LOM. /
Kojto	90:cb3d968589d8	829	#define BM_CAN_CTRL1_LOM (0x00000008U) /!< Bit mask for CAN_CTRL1_LOM. /
Kojto	90:cb3d968589d8	830	#define BS_CAN_CTRL1_LOM (1U) /!< Bit field size in bits for CAN_CTRL1_LOM. /
Kojto	90:cb3d968589d8	831
Kojto	90:cb3d968589d8	832	/! @brief Read current value of the CAN_CTRL1_LOM field. /
Kojto	90:cb3d968589d8	833	#define BR_CAN_CTRL1_LOM(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LOM))
Kojto	90:cb3d968589d8	834
Kojto	90:cb3d968589d8	835	/! @brief Format value for bitfield CAN_CTRL1_LOM. /
Kojto	90:cb3d968589d8	836	#define BF_CAN_CTRL1_LOM(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_LOM) & BM_CAN_CTRL1_LOM)
Kojto	90:cb3d968589d8	837
Kojto	90:cb3d968589d8	838	/! @brief Set the LOM field to a new value. /
Kojto	90:cb3d968589d8	839	#define BW_CAN_CTRL1_LOM(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LOM) = (v))
Kojto	90:cb3d968589d8	840	/@}/
Kojto	90:cb3d968589d8	841
Kojto	90:cb3d968589d8	842	/*!
Kojto	90:cb3d968589d8	843	* @name Register CAN_CTRL1, field LBUF[4] (RW)
Kojto	90:cb3d968589d8	844	*
Kojto	90:cb3d968589d8	845	* This bit defines the ordering mechanism for Message Buffer transmission. When
Kojto	90:cb3d968589d8	846	* asserted, the LPRIOEN bit does not affect the priority arbitration. This bit
Kojto	90:cb3d968589d8	847	* can be written only in Freeze mode because it is blocked by hardware in other
Kojto	90:cb3d968589d8	848	* modes.
Kojto	90:cb3d968589d8	849	*
Kojto	90:cb3d968589d8	850	* Values:
Kojto	90:cb3d968589d8	851	* - 0 - Buffer with highest priority is transmitted first.
Kojto	90:cb3d968589d8	852	* - 1 - Lowest number buffer is transmitted first.
Kojto	90:cb3d968589d8	853	*/
Kojto	90:cb3d968589d8	854	/@{/
Kojto	90:cb3d968589d8	855	#define BP_CAN_CTRL1_LBUF (4U) /!< Bit position for CAN_CTRL1_LBUF. /
Kojto	90:cb3d968589d8	856	#define BM_CAN_CTRL1_LBUF (0x00000010U) /!< Bit mask for CAN_CTRL1_LBUF. /
Kojto	90:cb3d968589d8	857	#define BS_CAN_CTRL1_LBUF (1U) /!< Bit field size in bits for CAN_CTRL1_LBUF. /
Kojto	90:cb3d968589d8	858
Kojto	90:cb3d968589d8	859	/! @brief Read current value of the CAN_CTRL1_LBUF field. /
Kojto	90:cb3d968589d8	860	#define BR_CAN_CTRL1_LBUF(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LBUF))
Kojto	90:cb3d968589d8	861
Kojto	90:cb3d968589d8	862	/! @brief Format value for bitfield CAN_CTRL1_LBUF. /
Kojto	90:cb3d968589d8	863	#define BF_CAN_CTRL1_LBUF(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_LBUF) & BM_CAN_CTRL1_LBUF)
Kojto	90:cb3d968589d8	864
Kojto	90:cb3d968589d8	865	/! @brief Set the LBUF field to a new value. /
Kojto	90:cb3d968589d8	866	#define BW_CAN_CTRL1_LBUF(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LBUF) = (v))
Kojto	90:cb3d968589d8	867	/@}/
Kojto	90:cb3d968589d8	868
Kojto	90:cb3d968589d8	869	/*!
Kojto	90:cb3d968589d8	870	* @name Register CAN_CTRL1, field TSYN[5] (RW)
Kojto	90:cb3d968589d8	871	*
Kojto	90:cb3d968589d8	872	* This bit enables a mechanism that resets the free-running timer each time a
Kojto	90:cb3d968589d8	873	* message is received in Message Buffer 0. This feature provides means to
Kojto	90:cb3d968589d8	874	* synchronize multiple FlexCAN stations with a special "SYNC" message, that is, global
Kojto	90:cb3d968589d8	875	* network time. If the RFEN bit in MCR is set (Rx FIFO enabled), the first
Kojto	90:cb3d968589d8	876	* available Mailbox, according to CTRL2[RFFN] setting, is used for timer
Kojto	90:cb3d968589d8	877	* synchronization instead of MB0. This bit can be written only in Freeze mode because it is
Kojto	90:cb3d968589d8	878	* blocked by hardware in other modes.
Kojto	90:cb3d968589d8	879	*
Kojto	90:cb3d968589d8	880	* Values:
Kojto	90:cb3d968589d8	881	* - 0 - Timer Sync feature disabled
Kojto	90:cb3d968589d8	882	* - 1 - Timer Sync feature enabled
Kojto	90:cb3d968589d8	883	*/
Kojto	90:cb3d968589d8	884	/@{/
Kojto	90:cb3d968589d8	885	#define BP_CAN_CTRL1_TSYN (5U) /!< Bit position for CAN_CTRL1_TSYN. /
Kojto	90:cb3d968589d8	886	#define BM_CAN_CTRL1_TSYN (0x00000020U) /!< Bit mask for CAN_CTRL1_TSYN. /
Kojto	90:cb3d968589d8	887	#define BS_CAN_CTRL1_TSYN (1U) /!< Bit field size in bits for CAN_CTRL1_TSYN. /
Kojto	90:cb3d968589d8	888
Kojto	90:cb3d968589d8	889	/! @brief Read current value of the CAN_CTRL1_TSYN field. /
Kojto	90:cb3d968589d8	890	#define BR_CAN_CTRL1_TSYN(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TSYN))
Kojto	90:cb3d968589d8	891
Kojto	90:cb3d968589d8	892	/! @brief Format value for bitfield CAN_CTRL1_TSYN. /
Kojto	90:cb3d968589d8	893	#define BF_CAN_CTRL1_TSYN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_TSYN) & BM_CAN_CTRL1_TSYN)
Kojto	90:cb3d968589d8	894
Kojto	90:cb3d968589d8	895	/! @brief Set the TSYN field to a new value. /
Kojto	90:cb3d968589d8	896	#define BW_CAN_CTRL1_TSYN(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TSYN) = (v))
Kojto	90:cb3d968589d8	897	/@}/
Kojto	90:cb3d968589d8	898
Kojto	90:cb3d968589d8	899	/*!
Kojto	90:cb3d968589d8	900	* @name Register CAN_CTRL1, field BOFFREC[6] (RW)
Kojto	90:cb3d968589d8	901	*
Kojto	90:cb3d968589d8	902	* This bit defines how FlexCAN recovers from Bus Off state. If this bit is
Kojto	90:cb3d968589d8	903	* negated, automatic recovering from Bus Off state occurs according to the CAN
Kojto	90:cb3d968589d8	904	* Specification 2.0B. If the bit is asserted, automatic recovering from Bus Off is
Kojto	90:cb3d968589d8	905	* disabled and the module remains in Bus Off state until the bit is negated by the
Kojto	90:cb3d968589d8	906	* user. If the negation occurs before 128 sequences of 11 recessive bits are
Kojto	90:cb3d968589d8	907	* detected on the CAN bus, then Bus Off recovery happens as if the BOFFREC bit had
Kojto	90:cb3d968589d8	908	* never been asserted. If the negation occurs after 128 sequences of 11
Kojto	90:cb3d968589d8	909	* recessive bits occurred, then FlexCAN will re-synchronize to the bus by waiting for
Kojto	90:cb3d968589d8	910	* 11 recessive bits before joining the bus. After negation, the BOFFREC bit can
Kojto	90:cb3d968589d8	911	* be re-asserted again during Bus Off, but it will be effective only the next
Kojto	90:cb3d968589d8	912	* time the module enters Bus Off. If BOFFREC was negated when the module entered
Kojto	90:cb3d968589d8	913	* Bus Off, asserting it during Bus Off will not be effective for the current Bus
Kojto	90:cb3d968589d8	914	* Off recovery.
Kojto	90:cb3d968589d8	915	*
Kojto	90:cb3d968589d8	916	* Values:
Kojto	90:cb3d968589d8	917	* - 0 - Automatic recovering from Bus Off state enabled, according to CAN Spec
Kojto	90:cb3d968589d8	918	* 2.0 part B.
Kojto	90:cb3d968589d8	919	* - 1 - Automatic recovering from Bus Off state disabled.
Kojto	90:cb3d968589d8	920	*/
Kojto	90:cb3d968589d8	921	/@{/
Kojto	90:cb3d968589d8	922	#define BP_CAN_CTRL1_BOFFREC (6U) /!< Bit position for CAN_CTRL1_BOFFREC. /
Kojto	90:cb3d968589d8	923	#define BM_CAN_CTRL1_BOFFREC (0x00000040U) /!< Bit mask for CAN_CTRL1_BOFFREC. /
Kojto	90:cb3d968589d8	924	#define BS_CAN_CTRL1_BOFFREC (1U) /!< Bit field size in bits for CAN_CTRL1_BOFFREC. /
Kojto	90:cb3d968589d8	925
Kojto	90:cb3d968589d8	926	/! @brief Read current value of the CAN_CTRL1_BOFFREC field. /
Kojto	90:cb3d968589d8	927	#define BR_CAN_CTRL1_BOFFREC(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFREC))
Kojto	90:cb3d968589d8	928
Kojto	90:cb3d968589d8	929	/! @brief Format value for bitfield CAN_CTRL1_BOFFREC. /
Kojto	90:cb3d968589d8	930	#define BF_CAN_CTRL1_BOFFREC(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_BOFFREC) & BM_CAN_CTRL1_BOFFREC)
Kojto	90:cb3d968589d8	931
Kojto	90:cb3d968589d8	932	/! @brief Set the BOFFREC field to a new value. /
Kojto	90:cb3d968589d8	933	#define BW_CAN_CTRL1_BOFFREC(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFREC) = (v))
Kojto	90:cb3d968589d8	934	/@}/
Kojto	90:cb3d968589d8	935
Kojto	90:cb3d968589d8	936	/*!
Kojto	90:cb3d968589d8	937	* @name Register CAN_CTRL1, field SMP[7] (RW)
Kojto	90:cb3d968589d8	938	*
Kojto	90:cb3d968589d8	939	* This bit defines the sampling mode of CAN bits at the Rx input. This bit can
Kojto	90:cb3d968589d8	940	* be written only in Freeze mode because it is blocked by hardware in other
Kojto	90:cb3d968589d8	941	* modes.
Kojto	90:cb3d968589d8	942	*
Kojto	90:cb3d968589d8	943	* Values:
Kojto	90:cb3d968589d8	944	* - 0 - Just one sample is used to determine the bit value.
Kojto	90:cb3d968589d8	945	* - 1 - Three samples are used to determine the value of the received bit: the
Kojto	90:cb3d968589d8	946	* regular one (sample point) and 2 preceding samples; a majority rule is
Kojto	90:cb3d968589d8	947	* used.
Kojto	90:cb3d968589d8	948	*/
Kojto	90:cb3d968589d8	949	/@{/
Kojto	90:cb3d968589d8	950	#define BP_CAN_CTRL1_SMP (7U) /!< Bit position for CAN_CTRL1_SMP. /
Kojto	90:cb3d968589d8	951	#define BM_CAN_CTRL1_SMP (0x00000080U) /!< Bit mask for CAN_CTRL1_SMP. /
Kojto	90:cb3d968589d8	952	#define BS_CAN_CTRL1_SMP (1U) /!< Bit field size in bits for CAN_CTRL1_SMP. /
Kojto	90:cb3d968589d8	953
Kojto	90:cb3d968589d8	954	/! @brief Read current value of the CAN_CTRL1_SMP field. /
Kojto	90:cb3d968589d8	955	#define BR_CAN_CTRL1_SMP(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_SMP))
Kojto	90:cb3d968589d8	956
Kojto	90:cb3d968589d8	957	/! @brief Format value for bitfield CAN_CTRL1_SMP. /
Kojto	90:cb3d968589d8	958	#define BF_CAN_CTRL1_SMP(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_SMP) & BM_CAN_CTRL1_SMP)
Kojto	90:cb3d968589d8	959
Kojto	90:cb3d968589d8	960	/! @brief Set the SMP field to a new value. /
Kojto	90:cb3d968589d8	961	#define BW_CAN_CTRL1_SMP(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_SMP) = (v))
Kojto	90:cb3d968589d8	962	/@}/
Kojto	90:cb3d968589d8	963
Kojto	90:cb3d968589d8	964	/*!
Kojto	90:cb3d968589d8	965	* @name Register CAN_CTRL1, field RWRNMSK[10] (RW)
Kojto	90:cb3d968589d8	966	*
Kojto	90:cb3d968589d8	967	* This bit provides a mask for the Rx Warning Interrupt associated with the
Kojto	90:cb3d968589d8	968	* RWRNINT flag in the Error and Status Register. This bit is read as zero when
Kojto	90:cb3d968589d8	969	* MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
Kojto	90:cb3d968589d8	970	* asserted.
Kojto	90:cb3d968589d8	971	*
Kojto	90:cb3d968589d8	972	* Values:
Kojto	90:cb3d968589d8	973	* - 0 - Rx Warning Interrupt disabled.
Kojto	90:cb3d968589d8	974	* - 1 - Rx Warning Interrupt enabled.
Kojto	90:cb3d968589d8	975	*/
Kojto	90:cb3d968589d8	976	/@{/
Kojto	90:cb3d968589d8	977	#define BP_CAN_CTRL1_RWRNMSK (10U) /!< Bit position for CAN_CTRL1_RWRNMSK. /
Kojto	90:cb3d968589d8	978	#define BM_CAN_CTRL1_RWRNMSK (0x00000400U) /!< Bit mask for CAN_CTRL1_RWRNMSK. /
Kojto	90:cb3d968589d8	979	#define BS_CAN_CTRL1_RWRNMSK (1U) /!< Bit field size in bits for CAN_CTRL1_RWRNMSK. /
Kojto	90:cb3d968589d8	980
Kojto	90:cb3d968589d8	981	/! @brief Read current value of the CAN_CTRL1_RWRNMSK field. /
Kojto	90:cb3d968589d8	982	#define BR_CAN_CTRL1_RWRNMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_RWRNMSK))
Kojto	90:cb3d968589d8	983
Kojto	90:cb3d968589d8	984	/! @brief Format value for bitfield CAN_CTRL1_RWRNMSK. /
Kojto	90:cb3d968589d8	985	#define BF_CAN_CTRL1_RWRNMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_RWRNMSK) & BM_CAN_CTRL1_RWRNMSK)
Kojto	90:cb3d968589d8	986
Kojto	90:cb3d968589d8	987	/! @brief Set the RWRNMSK field to a new value. /
Kojto	90:cb3d968589d8	988	#define BW_CAN_CTRL1_RWRNMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_RWRNMSK) = (v))
Kojto	90:cb3d968589d8	989	/@}/
Kojto	90:cb3d968589d8	990
Kojto	90:cb3d968589d8	991	/*!
Kojto	90:cb3d968589d8	992	* @name Register CAN_CTRL1, field TWRNMSK[11] (RW)
Kojto	90:cb3d968589d8	993	*
Kojto	90:cb3d968589d8	994	* This bit provides a mask for the Tx Warning Interrupt associated with the
Kojto	90:cb3d968589d8	995	* TWRNINT flag in the Error and Status Register. This bit is read as zero when
Kojto	90:cb3d968589d8	996	* MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
Kojto	90:cb3d968589d8	997	* asserted.
Kojto	90:cb3d968589d8	998	*
Kojto	90:cb3d968589d8	999	* Values:
Kojto	90:cb3d968589d8	1000	* - 0 - Tx Warning Interrupt disabled.
Kojto	90:cb3d968589d8	1001	* - 1 - Tx Warning Interrupt enabled.
Kojto	90:cb3d968589d8	1002	*/
Kojto	90:cb3d968589d8	1003	/@{/
Kojto	90:cb3d968589d8	1004	#define BP_CAN_CTRL1_TWRNMSK (11U) /!< Bit position for CAN_CTRL1_TWRNMSK. /
Kojto	90:cb3d968589d8	1005	#define BM_CAN_CTRL1_TWRNMSK (0x00000800U) /!< Bit mask for CAN_CTRL1_TWRNMSK. /
Kojto	90:cb3d968589d8	1006	#define BS_CAN_CTRL1_TWRNMSK (1U) /!< Bit field size in bits for CAN_CTRL1_TWRNMSK. /
Kojto	90:cb3d968589d8	1007
Kojto	90:cb3d968589d8	1008	/! @brief Read current value of the CAN_CTRL1_TWRNMSK field. /
Kojto	90:cb3d968589d8	1009	#define BR_CAN_CTRL1_TWRNMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TWRNMSK))
Kojto	90:cb3d968589d8	1010
Kojto	90:cb3d968589d8	1011	/! @brief Format value for bitfield CAN_CTRL1_TWRNMSK. /
Kojto	90:cb3d968589d8	1012	#define BF_CAN_CTRL1_TWRNMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_TWRNMSK) & BM_CAN_CTRL1_TWRNMSK)
Kojto	90:cb3d968589d8	1013
Kojto	90:cb3d968589d8	1014	/! @brief Set the TWRNMSK field to a new value. /
Kojto	90:cb3d968589d8	1015	#define BW_CAN_CTRL1_TWRNMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TWRNMSK) = (v))
Kojto	90:cb3d968589d8	1016	/@}/
Kojto	90:cb3d968589d8	1017
Kojto	90:cb3d968589d8	1018	/*!
Kojto	90:cb3d968589d8	1019	* @name Register CAN_CTRL1, field LPB[12] (RW)
Kojto	90:cb3d968589d8	1020	*
Kojto	90:cb3d968589d8	1021	* This bit configures FlexCAN to operate in Loop-Back mode. In this mode,
Kojto	90:cb3d968589d8	1022	* FlexCAN performs an internal loop back that can be used for self test operation.
Kojto	90:cb3d968589d8	1023	* The bit stream output of the transmitter is fed back internally to the receiver
Kojto	90:cb3d968589d8	1024	* input. The Rx CAN input pin is ignored and the Tx CAN output goes to the
Kojto	90:cb3d968589d8	1025	* recessive state (logic 1). FlexCAN behaves as it normally does when transmitting,
Kojto	90:cb3d968589d8	1026	* and treats its own transmitted message as a message received from a remote
Kojto	90:cb3d968589d8	1027	* node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN
Kojto	90:cb3d968589d8	1028	* frame acknowledge field, generating an internal acknowledge bit to ensure proper
Kojto	90:cb3d968589d8	1029	* reception of its own message. Both transmit and receive interrupts are
Kojto	90:cb3d968589d8	1030	* generated. This bit can be written only in Freeze mode because it is blocked by
Kojto	90:cb3d968589d8	1031	* hardware in other modes. In this mode, the MCR[SRXDIS] cannot be asserted because
Kojto	90:cb3d968589d8	1032	* this will impede the self reception of a transmitted message.
Kojto	90:cb3d968589d8	1033	*
Kojto	90:cb3d968589d8	1034	* Values:
Kojto	90:cb3d968589d8	1035	* - 0 - Loop Back disabled.
Kojto	90:cb3d968589d8	1036	* - 1 - Loop Back enabled.
Kojto	90:cb3d968589d8	1037	*/
Kojto	90:cb3d968589d8	1038	/@{/
Kojto	90:cb3d968589d8	1039	#define BP_CAN_CTRL1_LPB (12U) /!< Bit position for CAN_CTRL1_LPB. /
Kojto	90:cb3d968589d8	1040	#define BM_CAN_CTRL1_LPB (0x00001000U) /!< Bit mask for CAN_CTRL1_LPB. /
Kojto	90:cb3d968589d8	1041	#define BS_CAN_CTRL1_LPB (1U) /!< Bit field size in bits for CAN_CTRL1_LPB. /
Kojto	90:cb3d968589d8	1042
Kojto	90:cb3d968589d8	1043	/! @brief Read current value of the CAN_CTRL1_LPB field. /
Kojto	90:cb3d968589d8	1044	#define BR_CAN_CTRL1_LPB(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LPB))
Kojto	90:cb3d968589d8	1045
Kojto	90:cb3d968589d8	1046	/! @brief Format value for bitfield CAN_CTRL1_LPB. /
Kojto	90:cb3d968589d8	1047	#define BF_CAN_CTRL1_LPB(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_LPB) & BM_CAN_CTRL1_LPB)
Kojto	90:cb3d968589d8	1048
Kojto	90:cb3d968589d8	1049	/! @brief Set the LPB field to a new value. /
Kojto	90:cb3d968589d8	1050	#define BW_CAN_CTRL1_LPB(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LPB) = (v))
Kojto	90:cb3d968589d8	1051	/@}/
Kojto	90:cb3d968589d8	1052
Kojto	90:cb3d968589d8	1053	/*!
Kojto	90:cb3d968589d8	1054	* @name Register CAN_CTRL1, field CLKSRC[13] (RW)
Kojto	90:cb3d968589d8	1055	*
Kojto	90:cb3d968589d8	1056	* This bit selects the clock source to the CAN Protocol Engine (PE) to be
Kojto	90:cb3d968589d8	1057	* either the peripheral clock (driven by the PLL) or the crystal oscillator clock.
Kojto	90:cb3d968589d8	1058	* The selected clock is the one fed to the prescaler to generate the Serial Clock
Kojto	90:cb3d968589d8	1059	* (Sclock). In order to guarantee reliable operation, this bit can be written
Kojto	90:cb3d968589d8	1060	* only in Disable mode because it is blocked by hardware in other modes. See
Kojto	90:cb3d968589d8	1061	* Section "Protocol Timing".
Kojto	90:cb3d968589d8	1062	*
Kojto	90:cb3d968589d8	1063	* Values:
Kojto	90:cb3d968589d8	1064	* - 0 - The CAN engine clock source is the oscillator clock. Under this
Kojto	90:cb3d968589d8	1065	* condition, the oscillator clock frequency must be lower than the bus clock.
Kojto	90:cb3d968589d8	1066	* - 1 - The CAN engine clock source is the peripheral clock.
Kojto	90:cb3d968589d8	1067	*/
Kojto	90:cb3d968589d8	1068	/@{/
Kojto	90:cb3d968589d8	1069	#define BP_CAN_CTRL1_CLKSRC (13U) /!< Bit position for CAN_CTRL1_CLKSRC. /
Kojto	90:cb3d968589d8	1070	#define BM_CAN_CTRL1_CLKSRC (0x00002000U) /!< Bit mask for CAN_CTRL1_CLKSRC. /
Kojto	90:cb3d968589d8	1071	#define BS_CAN_CTRL1_CLKSRC (1U) /!< Bit field size in bits for CAN_CTRL1_CLKSRC. /
Kojto	90:cb3d968589d8	1072
Kojto	90:cb3d968589d8	1073	/! @brief Read current value of the CAN_CTRL1_CLKSRC field. /
Kojto	90:cb3d968589d8	1074	#define BR_CAN_CTRL1_CLKSRC(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_CLKSRC))
Kojto	90:cb3d968589d8	1075
Kojto	90:cb3d968589d8	1076	/! @brief Format value for bitfield CAN_CTRL1_CLKSRC. /
Kojto	90:cb3d968589d8	1077	#define BF_CAN_CTRL1_CLKSRC(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_CLKSRC) & BM_CAN_CTRL1_CLKSRC)
Kojto	90:cb3d968589d8	1078
Kojto	90:cb3d968589d8	1079	/! @brief Set the CLKSRC field to a new value. /
Kojto	90:cb3d968589d8	1080	#define BW_CAN_CTRL1_CLKSRC(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_CLKSRC) = (v))
Kojto	90:cb3d968589d8	1081	/@}/
Kojto	90:cb3d968589d8	1082
Kojto	90:cb3d968589d8	1083	/*!
Kojto	90:cb3d968589d8	1084	* @name Register CAN_CTRL1, field ERRMSK[14] (RW)
Kojto	90:cb3d968589d8	1085	*
Kojto	90:cb3d968589d8	1086	* This bit provides a mask for the Error Interrupt.
Kojto	90:cb3d968589d8	1087	*
Kojto	90:cb3d968589d8	1088	* Values:
Kojto	90:cb3d968589d8	1089	* - 0 - Error interrupt disabled.
Kojto	90:cb3d968589d8	1090	* - 1 - Error interrupt enabled.
Kojto	90:cb3d968589d8	1091	*/
Kojto	90:cb3d968589d8	1092	/@{/
Kojto	90:cb3d968589d8	1093	#define BP_CAN_CTRL1_ERRMSK (14U) /!< Bit position for CAN_CTRL1_ERRMSK. /
Kojto	90:cb3d968589d8	1094	#define BM_CAN_CTRL1_ERRMSK (0x00004000U) /!< Bit mask for CAN_CTRL1_ERRMSK. /
Kojto	90:cb3d968589d8	1095	#define BS_CAN_CTRL1_ERRMSK (1U) /!< Bit field size in bits for CAN_CTRL1_ERRMSK. /
Kojto	90:cb3d968589d8	1096
Kojto	90:cb3d968589d8	1097	/! @brief Read current value of the CAN_CTRL1_ERRMSK field. /
Kojto	90:cb3d968589d8	1098	#define BR_CAN_CTRL1_ERRMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_ERRMSK))
Kojto	90:cb3d968589d8	1099
Kojto	90:cb3d968589d8	1100	/! @brief Format value for bitfield CAN_CTRL1_ERRMSK. /
Kojto	90:cb3d968589d8	1101	#define BF_CAN_CTRL1_ERRMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_ERRMSK) & BM_CAN_CTRL1_ERRMSK)
Kojto	90:cb3d968589d8	1102
Kojto	90:cb3d968589d8	1103	/! @brief Set the ERRMSK field to a new value. /
Kojto	90:cb3d968589d8	1104	#define BW_CAN_CTRL1_ERRMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_ERRMSK) = (v))
Kojto	90:cb3d968589d8	1105	/@}/
Kojto	90:cb3d968589d8	1106
Kojto	90:cb3d968589d8	1107	/*!
Kojto	90:cb3d968589d8	1108	* @name Register CAN_CTRL1, field BOFFMSK[15] (RW)
Kojto	90:cb3d968589d8	1109	*
Kojto	90:cb3d968589d8	1110	* This bit provides a mask for the Bus Off Interrupt.
Kojto	90:cb3d968589d8	1111	*
Kojto	90:cb3d968589d8	1112	* Values:
Kojto	90:cb3d968589d8	1113	* - 0 - Bus Off interrupt disabled.
Kojto	90:cb3d968589d8	1114	* - 1 - Bus Off interrupt enabled.
Kojto	90:cb3d968589d8	1115	*/
Kojto	90:cb3d968589d8	1116	/@{/
Kojto	90:cb3d968589d8	1117	#define BP_CAN_CTRL1_BOFFMSK (15U) /!< Bit position for CAN_CTRL1_BOFFMSK. /
Kojto	90:cb3d968589d8	1118	#define BM_CAN_CTRL1_BOFFMSK (0x00008000U) /!< Bit mask for CAN_CTRL1_BOFFMSK. /
Kojto	90:cb3d968589d8	1119	#define BS_CAN_CTRL1_BOFFMSK (1U) /!< Bit field size in bits for CAN_CTRL1_BOFFMSK. /
Kojto	90:cb3d968589d8	1120
Kojto	90:cb3d968589d8	1121	/! @brief Read current value of the CAN_CTRL1_BOFFMSK field. /
Kojto	90:cb3d968589d8	1122	#define BR_CAN_CTRL1_BOFFMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFMSK))
Kojto	90:cb3d968589d8	1123
Kojto	90:cb3d968589d8	1124	/! @brief Format value for bitfield CAN_CTRL1_BOFFMSK. /
Kojto	90:cb3d968589d8	1125	#define BF_CAN_CTRL1_BOFFMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_BOFFMSK) & BM_CAN_CTRL1_BOFFMSK)
Kojto	90:cb3d968589d8	1126
Kojto	90:cb3d968589d8	1127	/! @brief Set the BOFFMSK field to a new value. /
Kojto	90:cb3d968589d8	1128	#define BW_CAN_CTRL1_BOFFMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFMSK) = (v))
Kojto	90:cb3d968589d8	1129	/@}/
Kojto	90:cb3d968589d8	1130
Kojto	90:cb3d968589d8	1131	/*!
Kojto	90:cb3d968589d8	1132	* @name Register CAN_CTRL1, field PSEG2[18:16] (RW)
Kojto	90:cb3d968589d8	1133	*
Kojto	90:cb3d968589d8	1134	* This 3-bit field defines the length of Phase Buffer Segment 2 in the bit
Kojto	90:cb3d968589d8	1135	* time. The valid programmable values are 1-7. This field can be written only in
Kojto	90:cb3d968589d8	1136	* Freeze mode because it is blocked by hardware in other modes. Phase Buffer
Kojto	90:cb3d968589d8	1137	* Segment 2 = (PSEG2 + 1) * Time-Quanta.
Kojto	90:cb3d968589d8	1138	*/
Kojto	90:cb3d968589d8	1139	/@{/
Kojto	90:cb3d968589d8	1140	#define BP_CAN_CTRL1_PSEG2 (16U) /!< Bit position for CAN_CTRL1_PSEG2. /
Kojto	90:cb3d968589d8	1141	#define BM_CAN_CTRL1_PSEG2 (0x00070000U) /!< Bit mask for CAN_CTRL1_PSEG2. /
Kojto	90:cb3d968589d8	1142	#define BS_CAN_CTRL1_PSEG2 (3U) /!< Bit field size in bits for CAN_CTRL1_PSEG2. /
Kojto	90:cb3d968589d8	1143
Kojto	90:cb3d968589d8	1144	/! @brief Read current value of the CAN_CTRL1_PSEG2 field. /
Kojto	90:cb3d968589d8	1145	#define BR_CAN_CTRL1_PSEG2(x) (HW_CAN_CTRL1(x).B.PSEG2)
Kojto	90:cb3d968589d8	1146
Kojto	90:cb3d968589d8	1147	/! @brief Format value for bitfield CAN_CTRL1_PSEG2. /
Kojto	90:cb3d968589d8	1148	#define BF_CAN_CTRL1_PSEG2(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PSEG2) & BM_CAN_CTRL1_PSEG2)
Kojto	90:cb3d968589d8	1149
Kojto	90:cb3d968589d8	1150	/! @brief Set the PSEG2 field to a new value. /
Kojto	90:cb3d968589d8	1151	#define BW_CAN_CTRL1_PSEG2(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PSEG2) \| BF_CAN_CTRL1_PSEG2(v)))
Kojto	90:cb3d968589d8	1152	/@}/
Kojto	90:cb3d968589d8	1153
Kojto	90:cb3d968589d8	1154	/*!
Kojto	90:cb3d968589d8	1155	* @name Register CAN_CTRL1, field PSEG1[21:19] (RW)
Kojto	90:cb3d968589d8	1156	*
Kojto	90:cb3d968589d8	1157	* This 3-bit field defines the length of Phase Buffer Segment 1 in the bit
Kojto	90:cb3d968589d8	1158	* time. The valid programmable values are 0-7. This field can be written only in
Kojto	90:cb3d968589d8	1159	* Freeze mode because it is blocked by hardware in other modes. Phase Buffer
Kojto	90:cb3d968589d8	1160	* Segment 1 = (PSEG1 + 1) * Time-Quanta.
Kojto	90:cb3d968589d8	1161	*/
Kojto	90:cb3d968589d8	1162	/@{/
Kojto	90:cb3d968589d8	1163	#define BP_CAN_CTRL1_PSEG1 (19U) /!< Bit position for CAN_CTRL1_PSEG1. /
Kojto	90:cb3d968589d8	1164	#define BM_CAN_CTRL1_PSEG1 (0x00380000U) /!< Bit mask for CAN_CTRL1_PSEG1. /
Kojto	90:cb3d968589d8	1165	#define BS_CAN_CTRL1_PSEG1 (3U) /!< Bit field size in bits for CAN_CTRL1_PSEG1. /
Kojto	90:cb3d968589d8	1166
Kojto	90:cb3d968589d8	1167	/! @brief Read current value of the CAN_CTRL1_PSEG1 field. /
Kojto	90:cb3d968589d8	1168	#define BR_CAN_CTRL1_PSEG1(x) (HW_CAN_CTRL1(x).B.PSEG1)
Kojto	90:cb3d968589d8	1169
Kojto	90:cb3d968589d8	1170	/! @brief Format value for bitfield CAN_CTRL1_PSEG1. /
Kojto	90:cb3d968589d8	1171	#define BF_CAN_CTRL1_PSEG1(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PSEG1) & BM_CAN_CTRL1_PSEG1)
Kojto	90:cb3d968589d8	1172
Kojto	90:cb3d968589d8	1173	/! @brief Set the PSEG1 field to a new value. /
Kojto	90:cb3d968589d8	1174	#define BW_CAN_CTRL1_PSEG1(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PSEG1) \| BF_CAN_CTRL1_PSEG1(v)))
Kojto	90:cb3d968589d8	1175	/@}/
Kojto	90:cb3d968589d8	1176
Kojto	90:cb3d968589d8	1177	/*!
Kojto	90:cb3d968589d8	1178	* @name Register CAN_CTRL1, field RJW[23:22] (RW)
Kojto	90:cb3d968589d8	1179	*
Kojto	90:cb3d968589d8	1180	* This 2-bit field defines the maximum number of time quanta that a bit time
Kojto	90:cb3d968589d8	1181	* can be changed by one re-synchronization. One time quantum is equal to the
Kojto	90:cb3d968589d8	1182	* Sclock period. The valid programmable values are 0-3. This field can be written
Kojto	90:cb3d968589d8	1183	* only in Freeze mode because it is blocked by hardware in other modes. Resync Jump
Kojto	90:cb3d968589d8	1184	* Width = RJW + 1.
Kojto	90:cb3d968589d8	1185	*/
Kojto	90:cb3d968589d8	1186	/@{/
Kojto	90:cb3d968589d8	1187	#define BP_CAN_CTRL1_RJW (22U) /!< Bit position for CAN_CTRL1_RJW. /
Kojto	90:cb3d968589d8	1188	#define BM_CAN_CTRL1_RJW (0x00C00000U) /!< Bit mask for CAN_CTRL1_RJW. /
Kojto	90:cb3d968589d8	1189	#define BS_CAN_CTRL1_RJW (2U) /!< Bit field size in bits for CAN_CTRL1_RJW. /
Kojto	90:cb3d968589d8	1190
Kojto	90:cb3d968589d8	1191	/! @brief Read current value of the CAN_CTRL1_RJW field. /
Kojto	90:cb3d968589d8	1192	#define BR_CAN_CTRL1_RJW(x) (HW_CAN_CTRL1(x).B.RJW)
Kojto	90:cb3d968589d8	1193
Kojto	90:cb3d968589d8	1194	/! @brief Format value for bitfield CAN_CTRL1_RJW. /
Kojto	90:cb3d968589d8	1195	#define BF_CAN_CTRL1_RJW(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_RJW) & BM_CAN_CTRL1_RJW)
Kojto	90:cb3d968589d8	1196
Kojto	90:cb3d968589d8	1197	/! @brief Set the RJW field to a new value. /
Kojto	90:cb3d968589d8	1198	#define BW_CAN_CTRL1_RJW(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_RJW) \| BF_CAN_CTRL1_RJW(v)))
Kojto	90:cb3d968589d8	1199	/@}/
Kojto	90:cb3d968589d8	1200
Kojto	90:cb3d968589d8	1201	/*!
Kojto	90:cb3d968589d8	1202	* @name Register CAN_CTRL1, field PRESDIV[31:24] (RW)
Kojto	90:cb3d968589d8	1203	*
Kojto	90:cb3d968589d8	1204	* This 8-bit field defines the ratio between the PE clock frequency and the
Kojto	90:cb3d968589d8	1205	* Serial Clock (Sclock) frequency. The Sclock period defines the time quantum of
Kojto	90:cb3d968589d8	1206	* the CAN protocol. For the reset value, the Sclock frequency is equal to the PE
Kojto	90:cb3d968589d8	1207	* clock frequency. The Maximum value of this field is 0xFF, that gives a minimum
Kojto	90:cb3d968589d8	1208	* Sclock frequency equal to the PE clock frequency divided by 256. See Section
Kojto	90:cb3d968589d8	1209	* "Protocol Timing". This field can be written only in Freeze mode because it is
Kojto	90:cb3d968589d8	1210	* blocked by hardware in other modes. Sclock frequency = PE clock frequency /
Kojto	90:cb3d968589d8	1211	* (PRESDIV + 1)
Kojto	90:cb3d968589d8	1212	*/
Kojto	90:cb3d968589d8	1213	/@{/
Kojto	90:cb3d968589d8	1214	#define BP_CAN_CTRL1_PRESDIV (24U) /!< Bit position for CAN_CTRL1_PRESDIV. /
Kojto	90:cb3d968589d8	1215	#define BM_CAN_CTRL1_PRESDIV (0xFF000000U) /!< Bit mask for CAN_CTRL1_PRESDIV. /
Kojto	90:cb3d968589d8	1216	#define BS_CAN_CTRL1_PRESDIV (8U) /!< Bit field size in bits for CAN_CTRL1_PRESDIV. /
Kojto	90:cb3d968589d8	1217
Kojto	90:cb3d968589d8	1218	/! @brief Read current value of the CAN_CTRL1_PRESDIV field. /
Kojto	90:cb3d968589d8	1219	#define BR_CAN_CTRL1_PRESDIV(x) (HW_CAN_CTRL1(x).B.PRESDIV)
Kojto	90:cb3d968589d8	1220
Kojto	90:cb3d968589d8	1221	/! @brief Format value for bitfield CAN_CTRL1_PRESDIV. /
Kojto	90:cb3d968589d8	1222	#define BF_CAN_CTRL1_PRESDIV(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PRESDIV) & BM_CAN_CTRL1_PRESDIV)
Kojto	90:cb3d968589d8	1223
Kojto	90:cb3d968589d8	1224	/! @brief Set the PRESDIV field to a new value. /
Kojto	90:cb3d968589d8	1225	#define BW_CAN_CTRL1_PRESDIV(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PRESDIV) \| BF_CAN_CTRL1_PRESDIV(v)))
Kojto	90:cb3d968589d8	1226	/@}/
Kojto	90:cb3d968589d8	1227
Kojto	90:cb3d968589d8	1228	/*******************************************************************************
Kojto	90:cb3d968589d8	1229	* HW_CAN_TIMER - Free Running Timer
Kojto	90:cb3d968589d8	1230	******************************************************************************/
Kojto	90:cb3d968589d8	1231
Kojto	90:cb3d968589d8	1232	/*!
Kojto	90:cb3d968589d8	1233	* @brief HW_CAN_TIMER - Free Running Timer (RW)
Kojto	90:cb3d968589d8	1234	*
Kojto	90:cb3d968589d8	1235	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1236	*
Kojto	90:cb3d968589d8	1237	* This register represents a 16-bit free running counter that can be read and
Kojto	90:cb3d968589d8	1238	* written by the CPU. The timer starts from 0x0 after Reset, counts linearly to
Kojto	90:cb3d968589d8	1239	* 0xFFFF, and wraps around. The timer is clocked by the FlexCAN bit-clock, which
Kojto	90:cb3d968589d8	1240	* defines the baud rate on the CAN bus. During a message transmission/reception,
Kojto	90:cb3d968589d8	1241	* it increments by one for each bit that is received or transmitted. When there
Kojto	90:cb3d968589d8	1242	* is no message on the bus, it counts using the previously programmed baud
Kojto	90:cb3d968589d8	1243	* rate. The timer is not incremented during Disable , Stop, and Freeze modes. The
Kojto	90:cb3d968589d8	1244	* timer value is captured when the second bit of the identifier field of any frame
Kojto	90:cb3d968589d8	1245	* is on the CAN bus. This captured value is written into the Time Stamp entry
Kojto	90:cb3d968589d8	1246	* in a message buffer after a successful reception or transmission of a message.
Kojto	90:cb3d968589d8	1247	* If bit CTRL1[TSYN] is asserted, the Timer is reset whenever a message is
Kojto	90:cb3d968589d8	1248	* received in the first available Mailbox, according to CTRL2[RFFN] setting. The CPU
Kojto	90:cb3d968589d8	1249	* can write to this register anytime. However, if the write occurs at the same
Kojto	90:cb3d968589d8	1250	* time that the Timer is being reset by a reception in the first Mailbox, then
Kojto	90:cb3d968589d8	1251	* the write value is discarded. Reading this register affects the Mailbox
Kojto	90:cb3d968589d8	1252	* Unlocking procedure; see Section "Mailbox Lock Mechanism".
Kojto	90:cb3d968589d8	1253	*/
Kojto	90:cb3d968589d8	1254	typedef union _hw_can_timer
Kojto	90:cb3d968589d8	1255	{
Kojto	90:cb3d968589d8	1256	uint32_t U;
Kojto	90:cb3d968589d8	1257	struct _hw_can_timer_bitfields
Kojto	90:cb3d968589d8	1258	{
Kojto	90:cb3d968589d8	1259	uint32_t TIMER : 16; /!< [15:0] Timer Value /
Kojto	90:cb3d968589d8	1260	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	1261	} B;
Kojto	90:cb3d968589d8	1262	} hw_can_timer_t;
Kojto	90:cb3d968589d8	1263
Kojto	90:cb3d968589d8	1264	/*!
Kojto	90:cb3d968589d8	1265	* @name Constants and macros for entire CAN_TIMER register
Kojto	90:cb3d968589d8	1266	*/
Kojto	90:cb3d968589d8	1267	/@{/
Kojto	90:cb3d968589d8	1268	#define HW_CAN_TIMER_ADDR(x) ((x) + 0x8U)
Kojto	90:cb3d968589d8	1269
Kojto	90:cb3d968589d8	1270	#define HW_CAN_TIMER(x) ((__IO hw_can_timer_t ) HW_CAN_TIMER_ADDR(x))
Kojto	90:cb3d968589d8	1271	#define HW_CAN_TIMER_RD(x) (HW_CAN_TIMER(x).U)
Kojto	90:cb3d968589d8	1272	#define HW_CAN_TIMER_WR(x, v) (HW_CAN_TIMER(x).U = (v))
Kojto	90:cb3d968589d8	1273	#define HW_CAN_TIMER_SET(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1274	#define HW_CAN_TIMER_CLR(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1275	#define HW_CAN_TIMER_TOG(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1276	/@}/
Kojto	90:cb3d968589d8	1277
Kojto	90:cb3d968589d8	1278	/*
Kojto	90:cb3d968589d8	1279	* Constants & macros for individual CAN_TIMER bitfields
Kojto	90:cb3d968589d8	1280	*/
Kojto	90:cb3d968589d8	1281
Kojto	90:cb3d968589d8	1282	/*!
Kojto	90:cb3d968589d8	1283	* @name Register CAN_TIMER, field TIMER[15:0] (RW)
Kojto	90:cb3d968589d8	1284	*
Kojto	90:cb3d968589d8	1285	* Contains the free-running counter value.
Kojto	90:cb3d968589d8	1286	*/
Kojto	90:cb3d968589d8	1287	/@{/
Kojto	90:cb3d968589d8	1288	#define BP_CAN_TIMER_TIMER (0U) /!< Bit position for CAN_TIMER_TIMER. /
Kojto	90:cb3d968589d8	1289	#define BM_CAN_TIMER_TIMER (0x0000FFFFU) /!< Bit mask for CAN_TIMER_TIMER. /
Kojto	90:cb3d968589d8	1290	#define BS_CAN_TIMER_TIMER (16U) /!< Bit field size in bits for CAN_TIMER_TIMER. /
Kojto	90:cb3d968589d8	1291
Kojto	90:cb3d968589d8	1292	/! @brief Read current value of the CAN_TIMER_TIMER field. /
Kojto	90:cb3d968589d8	1293	#define BR_CAN_TIMER_TIMER(x) (HW_CAN_TIMER(x).B.TIMER)
Kojto	90:cb3d968589d8	1294
Kojto	90:cb3d968589d8	1295	/! @brief Format value for bitfield CAN_TIMER_TIMER. /
Kojto	90:cb3d968589d8	1296	#define BF_CAN_TIMER_TIMER(v) ((uint32_t)((uint32_t)(v) << BP_CAN_TIMER_TIMER) & BM_CAN_TIMER_TIMER)
Kojto	90:cb3d968589d8	1297
Kojto	90:cb3d968589d8	1298	/! @brief Set the TIMER field to a new value. /
Kojto	90:cb3d968589d8	1299	#define BW_CAN_TIMER_TIMER(x, v) (HW_CAN_TIMER_WR(x, (HW_CAN_TIMER_RD(x) & ~BM_CAN_TIMER_TIMER) \| BF_CAN_TIMER_TIMER(v)))
Kojto	90:cb3d968589d8	1300	/@}/
Kojto	90:cb3d968589d8	1301
Kojto	90:cb3d968589d8	1302	/*******************************************************************************
Kojto	90:cb3d968589d8	1303	* HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register
Kojto	90:cb3d968589d8	1304	******************************************************************************/
Kojto	90:cb3d968589d8	1305
Kojto	90:cb3d968589d8	1306	/*!
Kojto	90:cb3d968589d8	1307	* @brief HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register (RW)
Kojto	90:cb3d968589d8	1308	*
Kojto	90:cb3d968589d8	1309	* Reset value: 0xFFFFFFFFU
Kojto	90:cb3d968589d8	1310	*
Kojto	90:cb3d968589d8	1311	* This register is located in RAM. RXMGMASK is provided for legacy application
Kojto	90:cb3d968589d8	1312	* support. When the MCR[IRMQ] bit is negated, RXMGMASK is always in effect. When
Kojto	90:cb3d968589d8	1313	* the MCR[IRMQ] bit is asserted, RXMGMASK has no effect. RXMGMASK is used to
Kojto	90:cb3d968589d8	1314	* mask the filter fields of all Rx MBs, excluding MBs 14-15, which have individual
Kojto	90:cb3d968589d8	1315	* mask registers. This register can only be written in Freeze mode as it is
Kojto	90:cb3d968589d8	1316	* blocked by hardware in other modes.
Kojto	90:cb3d968589d8	1317	*/
Kojto	90:cb3d968589d8	1318	typedef union _hw_can_rxmgmask
Kojto	90:cb3d968589d8	1319	{
Kojto	90:cb3d968589d8	1320	uint32_t U;
Kojto	90:cb3d968589d8	1321	struct _hw_can_rxmgmask_bitfields
Kojto	90:cb3d968589d8	1322	{
Kojto	90:cb3d968589d8	1323	uint32_t MG : 32; /!< [31:0] Rx Mailboxes Global Mask Bits /
Kojto	90:cb3d968589d8	1324	} B;
Kojto	90:cb3d968589d8	1325	} hw_can_rxmgmask_t;
Kojto	90:cb3d968589d8	1326
Kojto	90:cb3d968589d8	1327	/*!
Kojto	90:cb3d968589d8	1328	* @name Constants and macros for entire CAN_RXMGMASK register
Kojto	90:cb3d968589d8	1329	*/
Kojto	90:cb3d968589d8	1330	/@{/
Kojto	90:cb3d968589d8	1331	#define HW_CAN_RXMGMASK_ADDR(x) ((x) + 0x10U)
Kojto	90:cb3d968589d8	1332
Kojto	90:cb3d968589d8	1333	#define HW_CAN_RXMGMASK(x) ((__IO hw_can_rxmgmask_t ) HW_CAN_RXMGMASK_ADDR(x))
Kojto	90:cb3d968589d8	1334	#define HW_CAN_RXMGMASK_RD(x) (HW_CAN_RXMGMASK(x).U)
Kojto	90:cb3d968589d8	1335	#define HW_CAN_RXMGMASK_WR(x, v) (HW_CAN_RXMGMASK(x).U = (v))
Kojto	90:cb3d968589d8	1336	#define HW_CAN_RXMGMASK_SET(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1337	#define HW_CAN_RXMGMASK_CLR(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1338	#define HW_CAN_RXMGMASK_TOG(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1339	/@}/
Kojto	90:cb3d968589d8	1340
Kojto	90:cb3d968589d8	1341	/*
Kojto	90:cb3d968589d8	1342	* Constants & macros for individual CAN_RXMGMASK bitfields
Kojto	90:cb3d968589d8	1343	*/
Kojto	90:cb3d968589d8	1344
Kojto	90:cb3d968589d8	1345	/*!
Kojto	90:cb3d968589d8	1346	* @name Register CAN_RXMGMASK, field MG[31:0] (RW)
Kojto	90:cb3d968589d8	1347	*
Kojto	90:cb3d968589d8	1348	* These bits mask the Mailbox filter bits. Note that the alignment with the ID
Kojto	90:cb3d968589d8	1349	* word of the Mailbox is not perfect as the two most significant MG bits affect
Kojto	90:cb3d968589d8	1350	* the fields RTR and IDE, which are located in the Control and Status word of
Kojto	90:cb3d968589d8	1351	* the Mailbox. The following table shows in detail which MG bits mask each Mailbox
Kojto	90:cb3d968589d8	1352	* filter field. SMB[RTR] RTR bit of the Incoming Frame. It is saved into an
Kojto	90:cb3d968589d8	1353	* auxiliary MB called Rx Serial Message Buffer (Rx SMB). CTRL2[RRS] CTRL2[EACEN]
Kojto	90:cb3d968589d8	1354	* Mailbox filter fields MB[RTR] MB[IDE] MB[ID] Reserved 0 - 0 note If the
Kojto	90:cb3d968589d8	1355	* CTRL2[EACEN] bit is negated, the RTR bit of Mailbox is never compared with the RTR bit
Kojto	90:cb3d968589d8	1356	* of the incoming frame. note If the CTRL2[EACEN] bit is negated, the IDE bit
Kojto	90:cb3d968589d8	1357	* of Mailbox is always compared with the IDE bit of the incoming frame. MG[28:0]
Kojto	90:cb3d968589d8	1358	* MG[31:29] 0 - 1 MG[31] MG[30] MG[28:0] MG[29] 1 0 - - - - MG[31:0] 1 1 0 - -
Kojto	90:cb3d968589d8	1359	* MG[28:0] MG[31:29] 1 1 1 MG[31] MG[30] MG[28:0] MG[29]
Kojto	90:cb3d968589d8	1360	*
Kojto	90:cb3d968589d8	1361	* Values:
Kojto	90:cb3d968589d8	1362	* - 0 - The corresponding bit in the filter is "don't care."
Kojto	90:cb3d968589d8	1363	* - 1 - The corresponding bit in the filter is checked.
Kojto	90:cb3d968589d8	1364	*/
Kojto	90:cb3d968589d8	1365	/@{/
Kojto	90:cb3d968589d8	1366	#define BP_CAN_RXMGMASK_MG (0U) /!< Bit position for CAN_RXMGMASK_MG. /
Kojto	90:cb3d968589d8	1367	#define BM_CAN_RXMGMASK_MG (0xFFFFFFFFU) /!< Bit mask for CAN_RXMGMASK_MG. /
Kojto	90:cb3d968589d8	1368	#define BS_CAN_RXMGMASK_MG (32U) /!< Bit field size in bits for CAN_RXMGMASK_MG. /
Kojto	90:cb3d968589d8	1369
Kojto	90:cb3d968589d8	1370	/! @brief Read current value of the CAN_RXMGMASK_MG field. /
Kojto	90:cb3d968589d8	1371	#define BR_CAN_RXMGMASK_MG(x) (HW_CAN_RXMGMASK(x).U)
Kojto	90:cb3d968589d8	1372
Kojto	90:cb3d968589d8	1373	/! @brief Format value for bitfield CAN_RXMGMASK_MG. /
Kojto	90:cb3d968589d8	1374	#define BF_CAN_RXMGMASK_MG(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RXMGMASK_MG) & BM_CAN_RXMGMASK_MG)
Kojto	90:cb3d968589d8	1375
Kojto	90:cb3d968589d8	1376	/! @brief Set the MG field to a new value. /
Kojto	90:cb3d968589d8	1377	#define BW_CAN_RXMGMASK_MG(x, v) (HW_CAN_RXMGMASK_WR(x, v))
Kojto	90:cb3d968589d8	1378	/@}/
Kojto	90:cb3d968589d8	1379
Kojto	90:cb3d968589d8	1380	/*******************************************************************************
Kojto	90:cb3d968589d8	1381	* HW_CAN_RX14MASK - Rx 14 Mask register
Kojto	90:cb3d968589d8	1382	******************************************************************************/
Kojto	90:cb3d968589d8	1383
Kojto	90:cb3d968589d8	1384	/*!
Kojto	90:cb3d968589d8	1385	* @brief HW_CAN_RX14MASK - Rx 14 Mask register (RW)
Kojto	90:cb3d968589d8	1386	*
Kojto	90:cb3d968589d8	1387	* Reset value: 0xFFFFFFFFU
Kojto	90:cb3d968589d8	1388	*
Kojto	90:cb3d968589d8	1389	* This register is located in RAM. RX14MASK is provided for legacy application
Kojto	90:cb3d968589d8	1390	* support. When the MCR[IRMQ] bit is asserted, RX14MASK has no effect. RX14MASK
Kojto	90:cb3d968589d8	1391	* is used to mask the filter fields of Message Buffer 14. This register can only
Kojto	90:cb3d968589d8	1392	* be programmed while the module is in Freeze mode as it is blocked by hardware
Kojto	90:cb3d968589d8	1393	* in other modes.
Kojto	90:cb3d968589d8	1394	*/
Kojto	90:cb3d968589d8	1395	typedef union _hw_can_rx14mask
Kojto	90:cb3d968589d8	1396	{
Kojto	90:cb3d968589d8	1397	uint32_t U;
Kojto	90:cb3d968589d8	1398	struct _hw_can_rx14mask_bitfields
Kojto	90:cb3d968589d8	1399	{
Kojto	90:cb3d968589d8	1400	uint32_t RX14M : 32; /!< [31:0] Rx Buffer 14 Mask Bits /
Kojto	90:cb3d968589d8	1401	} B;
Kojto	90:cb3d968589d8	1402	} hw_can_rx14mask_t;
Kojto	90:cb3d968589d8	1403
Kojto	90:cb3d968589d8	1404	/*!
Kojto	90:cb3d968589d8	1405	* @name Constants and macros for entire CAN_RX14MASK register
Kojto	90:cb3d968589d8	1406	*/
Kojto	90:cb3d968589d8	1407	/@{/
Kojto	90:cb3d968589d8	1408	#define HW_CAN_RX14MASK_ADDR(x) ((x) + 0x14U)
Kojto	90:cb3d968589d8	1409
Kojto	90:cb3d968589d8	1410	#define HW_CAN_RX14MASK(x) ((__IO hw_can_rx14mask_t ) HW_CAN_RX14MASK_ADDR(x))
Kojto	90:cb3d968589d8	1411	#define HW_CAN_RX14MASK_RD(x) (HW_CAN_RX14MASK(x).U)
Kojto	90:cb3d968589d8	1412	#define HW_CAN_RX14MASK_WR(x, v) (HW_CAN_RX14MASK(x).U = (v))
Kojto	90:cb3d968589d8	1413	#define HW_CAN_RX14MASK_SET(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1414	#define HW_CAN_RX14MASK_CLR(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1415	#define HW_CAN_RX14MASK_TOG(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1416	/@}/
Kojto	90:cb3d968589d8	1417
Kojto	90:cb3d968589d8	1418	/*
Kojto	90:cb3d968589d8	1419	* Constants & macros for individual CAN_RX14MASK bitfields
Kojto	90:cb3d968589d8	1420	*/
Kojto	90:cb3d968589d8	1421
Kojto	90:cb3d968589d8	1422	/*!
Kojto	90:cb3d968589d8	1423	* @name Register CAN_RX14MASK, field RX14M[31:0] (RW)
Kojto	90:cb3d968589d8	1424	*
Kojto	90:cb3d968589d8	1425	* Each mask bit masks the corresponding Mailbox 14 filter field in the same way
Kojto	90:cb3d968589d8	1426	* that RXMGMASK masks other Mailboxes' filters. See the description of the
Kojto	90:cb3d968589d8	1427	* CAN_RXMGMASK register.
Kojto	90:cb3d968589d8	1428	*
Kojto	90:cb3d968589d8	1429	* Values:
Kojto	90:cb3d968589d8	1430	* - 0 - The corresponding bit in the filter is "don't care."
Kojto	90:cb3d968589d8	1431	* - 1 - The corresponding bit in the filter is checked.
Kojto	90:cb3d968589d8	1432	*/
Kojto	90:cb3d968589d8	1433	/@{/
Kojto	90:cb3d968589d8	1434	#define BP_CAN_RX14MASK_RX14M (0U) /!< Bit position for CAN_RX14MASK_RX14M. /
Kojto	90:cb3d968589d8	1435	#define BM_CAN_RX14MASK_RX14M (0xFFFFFFFFU) /!< Bit mask for CAN_RX14MASK_RX14M. /
Kojto	90:cb3d968589d8	1436	#define BS_CAN_RX14MASK_RX14M (32U) /!< Bit field size in bits for CAN_RX14MASK_RX14M. /
Kojto	90:cb3d968589d8	1437
Kojto	90:cb3d968589d8	1438	/! @brief Read current value of the CAN_RX14MASK_RX14M field. /
Kojto	90:cb3d968589d8	1439	#define BR_CAN_RX14MASK_RX14M(x) (HW_CAN_RX14MASK(x).U)
Kojto	90:cb3d968589d8	1440
Kojto	90:cb3d968589d8	1441	/! @brief Format value for bitfield CAN_RX14MASK_RX14M. /
Kojto	90:cb3d968589d8	1442	#define BF_CAN_RX14MASK_RX14M(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RX14MASK_RX14M) & BM_CAN_RX14MASK_RX14M)
Kojto	90:cb3d968589d8	1443
Kojto	90:cb3d968589d8	1444	/! @brief Set the RX14M field to a new value. /
Kojto	90:cb3d968589d8	1445	#define BW_CAN_RX14MASK_RX14M(x, v) (HW_CAN_RX14MASK_WR(x, v))
Kojto	90:cb3d968589d8	1446	/@}/
Kojto	90:cb3d968589d8	1447
Kojto	90:cb3d968589d8	1448	/*******************************************************************************
Kojto	90:cb3d968589d8	1449	* HW_CAN_RX15MASK - Rx 15 Mask register
Kojto	90:cb3d968589d8	1450	******************************************************************************/
Kojto	90:cb3d968589d8	1451
Kojto	90:cb3d968589d8	1452	/*!
Kojto	90:cb3d968589d8	1453	* @brief HW_CAN_RX15MASK - Rx 15 Mask register (RW)
Kojto	90:cb3d968589d8	1454	*
Kojto	90:cb3d968589d8	1455	* Reset value: 0xFFFFFFFFU
Kojto	90:cb3d968589d8	1456	*
Kojto	90:cb3d968589d8	1457	* This register is located in RAM. RX15MASK is provided for legacy application
Kojto	90:cb3d968589d8	1458	* support. When the MCR[IRMQ] bit is asserted, RX15MASK has no effect. RX15MASK
Kojto	90:cb3d968589d8	1459	* is used to mask the filter fields of Message Buffer 15. This register can be
Kojto	90:cb3d968589d8	1460	* programmed only while the module is in Freeze mode because it is blocked by
Kojto	90:cb3d968589d8	1461	* hardware in other modes.
Kojto	90:cb3d968589d8	1462	*/
Kojto	90:cb3d968589d8	1463	typedef union _hw_can_rx15mask
Kojto	90:cb3d968589d8	1464	{
Kojto	90:cb3d968589d8	1465	uint32_t U;
Kojto	90:cb3d968589d8	1466	struct _hw_can_rx15mask_bitfields
Kojto	90:cb3d968589d8	1467	{
Kojto	90:cb3d968589d8	1468	uint32_t RX15M : 32; /!< [31:0] Rx Buffer 15 Mask Bits /
Kojto	90:cb3d968589d8	1469	} B;
Kojto	90:cb3d968589d8	1470	} hw_can_rx15mask_t;
Kojto	90:cb3d968589d8	1471
Kojto	90:cb3d968589d8	1472	/*!
Kojto	90:cb3d968589d8	1473	* @name Constants and macros for entire CAN_RX15MASK register
Kojto	90:cb3d968589d8	1474	*/
Kojto	90:cb3d968589d8	1475	/@{/
Kojto	90:cb3d968589d8	1476	#define HW_CAN_RX15MASK_ADDR(x) ((x) + 0x18U)
Kojto	90:cb3d968589d8	1477
Kojto	90:cb3d968589d8	1478	#define HW_CAN_RX15MASK(x) ((__IO hw_can_rx15mask_t ) HW_CAN_RX15MASK_ADDR(x))
Kojto	90:cb3d968589d8	1479	#define HW_CAN_RX15MASK_RD(x) (HW_CAN_RX15MASK(x).U)
Kojto	90:cb3d968589d8	1480	#define HW_CAN_RX15MASK_WR(x, v) (HW_CAN_RX15MASK(x).U = (v))
Kojto	90:cb3d968589d8	1481	#define HW_CAN_RX15MASK_SET(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1482	#define HW_CAN_RX15MASK_CLR(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1483	#define HW_CAN_RX15MASK_TOG(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1484	/@}/
Kojto	90:cb3d968589d8	1485
Kojto	90:cb3d968589d8	1486	/*
Kojto	90:cb3d968589d8	1487	* Constants & macros for individual CAN_RX15MASK bitfields
Kojto	90:cb3d968589d8	1488	*/
Kojto	90:cb3d968589d8	1489
Kojto	90:cb3d968589d8	1490	/*!
Kojto	90:cb3d968589d8	1491	* @name Register CAN_RX15MASK, field RX15M[31:0] (RW)
Kojto	90:cb3d968589d8	1492	*
Kojto	90:cb3d968589d8	1493	* Each mask bit masks the corresponding Mailbox 15 filter field in the same way
Kojto	90:cb3d968589d8	1494	* that RXMGMASK masks other Mailboxes' filters. See the description of the
Kojto	90:cb3d968589d8	1495	* CAN_RXMGMASK register.
Kojto	90:cb3d968589d8	1496	*
Kojto	90:cb3d968589d8	1497	* Values:
Kojto	90:cb3d968589d8	1498	* - 0 - The corresponding bit in the filter is "don't care."
Kojto	90:cb3d968589d8	1499	* - 1 - The corresponding bit in the filter is checked.
Kojto	90:cb3d968589d8	1500	*/
Kojto	90:cb3d968589d8	1501	/@{/
Kojto	90:cb3d968589d8	1502	#define BP_CAN_RX15MASK_RX15M (0U) /!< Bit position for CAN_RX15MASK_RX15M. /
Kojto	90:cb3d968589d8	1503	#define BM_CAN_RX15MASK_RX15M (0xFFFFFFFFU) /!< Bit mask for CAN_RX15MASK_RX15M. /
Kojto	90:cb3d968589d8	1504	#define BS_CAN_RX15MASK_RX15M (32U) /!< Bit field size in bits for CAN_RX15MASK_RX15M. /
Kojto	90:cb3d968589d8	1505
Kojto	90:cb3d968589d8	1506	/! @brief Read current value of the CAN_RX15MASK_RX15M field. /
Kojto	90:cb3d968589d8	1507	#define BR_CAN_RX15MASK_RX15M(x) (HW_CAN_RX15MASK(x).U)
Kojto	90:cb3d968589d8	1508
Kojto	90:cb3d968589d8	1509	/! @brief Format value for bitfield CAN_RX15MASK_RX15M. /
Kojto	90:cb3d968589d8	1510	#define BF_CAN_RX15MASK_RX15M(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RX15MASK_RX15M) & BM_CAN_RX15MASK_RX15M)
Kojto	90:cb3d968589d8	1511
Kojto	90:cb3d968589d8	1512	/! @brief Set the RX15M field to a new value. /
Kojto	90:cb3d968589d8	1513	#define BW_CAN_RX15MASK_RX15M(x, v) (HW_CAN_RX15MASK_WR(x, v))
Kojto	90:cb3d968589d8	1514	/@}/
Kojto	90:cb3d968589d8	1515
Kojto	90:cb3d968589d8	1516	/*******************************************************************************
Kojto	90:cb3d968589d8	1517	* HW_CAN_ECR - Error Counter
Kojto	90:cb3d968589d8	1518	******************************************************************************/
Kojto	90:cb3d968589d8	1519
Kojto	90:cb3d968589d8	1520	/*!
Kojto	90:cb3d968589d8	1521	* @brief HW_CAN_ECR - Error Counter (RW)
Kojto	90:cb3d968589d8	1522	*
Kojto	90:cb3d968589d8	1523	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1524	*
Kojto	90:cb3d968589d8	1525	* This register has two 8-bit fields reflecting the value of two FlexCAN error
Kojto	90:cb3d968589d8	1526	* counters: Transmit Error Counter (TXERRCNT field) and Receive Error Counter
Kojto	90:cb3d968589d8	1527	* (RXERRCNT field). The rules for increasing and decreasing these counters are
Kojto	90:cb3d968589d8	1528	* described in the CAN protocol and are completely implemented in the FlexCAN
Kojto	90:cb3d968589d8	1529	* module. Both counters are read-only except in Freeze mode, where they can be
Kojto	90:cb3d968589d8	1530	* written by the CPU. FlexCAN responds to any bus state as described in the protocol,
Kojto	90:cb3d968589d8	1531	* for example, transmit Error Active or Error Passive flag, delay its
Kojto	90:cb3d968589d8	1532	* transmission start time (Error Passive) and avoid any influence on the bus when in Bus
Kojto	90:cb3d968589d8	1533	* Off state. The following are the basic rules for FlexCAN bus state transitions:
Kojto	90:cb3d968589d8	1534	* If the value of TXERRCNT or RXERRCNT increases to be greater than or equal to
Kojto	90:cb3d968589d8	1535	* 128, the FLTCONF field in the Error and Status Register is updated to reflect
Kojto	90:cb3d968589d8	1536	* 'Error Passive' state. If the FlexCAN state is 'Error Passive', and either
Kojto	90:cb3d968589d8	1537	* TXERRCNT or RXERRCNT decrements to a value less than or equal to 127 while the
Kojto	90:cb3d968589d8	1538	* other already satisfies this condition, the FLTCONF field in the Error and
Kojto	90:cb3d968589d8	1539	* Status Register is updated to reflect 'Error Active' state. If the value of
Kojto	90:cb3d968589d8	1540	* TXERRCNT increases to be greater than 255, the FLTCONF field in the Error and Status
Kojto	90:cb3d968589d8	1541	* Register is updated to reflect 'Bus Off' state, and an interrupt may be
Kojto	90:cb3d968589d8	1542	* issued. The value of TXERRCNT is then reset to zero. If FlexCAN is in 'Bus Off'
Kojto	90:cb3d968589d8	1543	* state, then TXERRCNT is cascaded together with another internal counter to count
Kojto	90:cb3d968589d8	1544	* the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
Kojto	90:cb3d968589d8	1545	* TXERRCNT is reset to zero and counts in a manner where the internal counter counts
Kojto	90:cb3d968589d8	1546	* 11 such bits and then wraps around while incrementing the TXERRCNT. When
Kojto	90:cb3d968589d8	1547	* TXERRCNT reaches the value of 128, the FLTCONF field in the Error and Status
Kojto	90:cb3d968589d8	1548	* Register is updated to be 'Error Active' and both error counters are reset to zero.
Kojto	90:cb3d968589d8	1549	* At any instance of dominant bit following a stream of less than 11
Kojto	90:cb3d968589d8	1550	* consecutive recessive bits, the internal counter resets itself to zero without affecting
Kojto	90:cb3d968589d8	1551	* the TXERRCNT value. If during system start-up, only one node is operating,
Kojto	90:cb3d968589d8	1552	* then its TXERRCNT increases in each message it is trying to transmit, as a
Kojto	90:cb3d968589d8	1553	* result of acknowledge errors (indicated by the ACKERR bit in the Error and Status
Kojto	90:cb3d968589d8	1554	* Register). After the transition to 'Error Passive' state, the TXERRCNT does not
Kojto	90:cb3d968589d8	1555	* increment anymore by acknowledge errors. Therefore the device never goes to
Kojto	90:cb3d968589d8	1556	* the 'Bus Off' state. If the RXERRCNT increases to a value greater than 127, it
Kojto	90:cb3d968589d8	1557	* is not incremented further, even if more errors are detected while being a
Kojto	90:cb3d968589d8	1558	* receiver. At the next successful message reception, the counter is set to a value
Kojto	90:cb3d968589d8	1559	* between 119 and 127 to resume to 'Error Active' state.
Kojto	90:cb3d968589d8	1560	*/
Kojto	90:cb3d968589d8	1561	typedef union _hw_can_ecr
Kojto	90:cb3d968589d8	1562	{
Kojto	90:cb3d968589d8	1563	uint32_t U;
Kojto	90:cb3d968589d8	1564	struct _hw_can_ecr_bitfields
Kojto	90:cb3d968589d8	1565	{
Kojto	90:cb3d968589d8	1566	uint32_t TXERRCNT : 8; /!< [7:0] Transmit Error Counter /
Kojto	90:cb3d968589d8	1567	uint32_t RXERRCNT : 8; /!< [15:8] Receive Error Counter /
Kojto	90:cb3d968589d8	1568	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	1569	} B;
Kojto	90:cb3d968589d8	1570	} hw_can_ecr_t;
Kojto	90:cb3d968589d8	1571
Kojto	90:cb3d968589d8	1572	/*!
Kojto	90:cb3d968589d8	1573	* @name Constants and macros for entire CAN_ECR register
Kojto	90:cb3d968589d8	1574	*/
Kojto	90:cb3d968589d8	1575	/@{/
Kojto	90:cb3d968589d8	1576	#define HW_CAN_ECR_ADDR(x) ((x) + 0x1CU)
Kojto	90:cb3d968589d8	1577
Kojto	90:cb3d968589d8	1578	#define HW_CAN_ECR(x) ((__IO hw_can_ecr_t ) HW_CAN_ECR_ADDR(x))
Kojto	90:cb3d968589d8	1579	#define HW_CAN_ECR_RD(x) (HW_CAN_ECR(x).U)
Kojto	90:cb3d968589d8	1580	#define HW_CAN_ECR_WR(x, v) (HW_CAN_ECR(x).U = (v))
Kojto	90:cb3d968589d8	1581	#define HW_CAN_ECR_SET(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1582	#define HW_CAN_ECR_CLR(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1583	#define HW_CAN_ECR_TOG(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1584	/@}/
Kojto	90:cb3d968589d8	1585
Kojto	90:cb3d968589d8	1586	/*
Kojto	90:cb3d968589d8	1587	* Constants & macros for individual CAN_ECR bitfields
Kojto	90:cb3d968589d8	1588	*/
Kojto	90:cb3d968589d8	1589
Kojto	90:cb3d968589d8	1590	/*!
Kojto	90:cb3d968589d8	1591	* @name Register CAN_ECR, field TXERRCNT[7:0] (RW)
Kojto	90:cb3d968589d8	1592	*/
Kojto	90:cb3d968589d8	1593	/@{/
Kojto	90:cb3d968589d8	1594	#define BP_CAN_ECR_TXERRCNT (0U) /!< Bit position for CAN_ECR_TXERRCNT. /
Kojto	90:cb3d968589d8	1595	#define BM_CAN_ECR_TXERRCNT (0x000000FFU) /!< Bit mask for CAN_ECR_TXERRCNT. /
Kojto	90:cb3d968589d8	1596	#define BS_CAN_ECR_TXERRCNT (8U) /!< Bit field size in bits for CAN_ECR_TXERRCNT. /
Kojto	90:cb3d968589d8	1597
Kojto	90:cb3d968589d8	1598	/! @brief Read current value of the CAN_ECR_TXERRCNT field. /
Kojto	90:cb3d968589d8	1599	#define BR_CAN_ECR_TXERRCNT(x) (HW_CAN_ECR(x).B.TXERRCNT)
Kojto	90:cb3d968589d8	1600
Kojto	90:cb3d968589d8	1601	/! @brief Format value for bitfield CAN_ECR_TXERRCNT. /
Kojto	90:cb3d968589d8	1602	#define BF_CAN_ECR_TXERRCNT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ECR_TXERRCNT) & BM_CAN_ECR_TXERRCNT)
Kojto	90:cb3d968589d8	1603
Kojto	90:cb3d968589d8	1604	/! @brief Set the TXERRCNT field to a new value. /
Kojto	90:cb3d968589d8	1605	#define BW_CAN_ECR_TXERRCNT(x, v) (HW_CAN_ECR_WR(x, (HW_CAN_ECR_RD(x) & ~BM_CAN_ECR_TXERRCNT) \| BF_CAN_ECR_TXERRCNT(v)))
Kojto	90:cb3d968589d8	1606	/@}/
Kojto	90:cb3d968589d8	1607
Kojto	90:cb3d968589d8	1608	/*!
Kojto	90:cb3d968589d8	1609	* @name Register CAN_ECR, field RXERRCNT[15:8] (RW)
Kojto	90:cb3d968589d8	1610	*/
Kojto	90:cb3d968589d8	1611	/@{/
Kojto	90:cb3d968589d8	1612	#define BP_CAN_ECR_RXERRCNT (8U) /!< Bit position for CAN_ECR_RXERRCNT. /
Kojto	90:cb3d968589d8	1613	#define BM_CAN_ECR_RXERRCNT (0x0000FF00U) /!< Bit mask for CAN_ECR_RXERRCNT. /
Kojto	90:cb3d968589d8	1614	#define BS_CAN_ECR_RXERRCNT (8U) /!< Bit field size in bits for CAN_ECR_RXERRCNT. /
Kojto	90:cb3d968589d8	1615
Kojto	90:cb3d968589d8	1616	/! @brief Read current value of the CAN_ECR_RXERRCNT field. /
Kojto	90:cb3d968589d8	1617	#define BR_CAN_ECR_RXERRCNT(x) (HW_CAN_ECR(x).B.RXERRCNT)
Kojto	90:cb3d968589d8	1618
Kojto	90:cb3d968589d8	1619	/! @brief Format value for bitfield CAN_ECR_RXERRCNT. /
Kojto	90:cb3d968589d8	1620	#define BF_CAN_ECR_RXERRCNT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ECR_RXERRCNT) & BM_CAN_ECR_RXERRCNT)
Kojto	90:cb3d968589d8	1621
Kojto	90:cb3d968589d8	1622	/! @brief Set the RXERRCNT field to a new value. /
Kojto	90:cb3d968589d8	1623	#define BW_CAN_ECR_RXERRCNT(x, v) (HW_CAN_ECR_WR(x, (HW_CAN_ECR_RD(x) & ~BM_CAN_ECR_RXERRCNT) \| BF_CAN_ECR_RXERRCNT(v)))
Kojto	90:cb3d968589d8	1624	/@}/
Kojto	90:cb3d968589d8	1625
Kojto	90:cb3d968589d8	1626	/*******************************************************************************
Kojto	90:cb3d968589d8	1627	* HW_CAN_ESR1 - Error and Status 1 register
Kojto	90:cb3d968589d8	1628	******************************************************************************/
Kojto	90:cb3d968589d8	1629
Kojto	90:cb3d968589d8	1630	/*!
Kojto	90:cb3d968589d8	1631	* @brief HW_CAN_ESR1 - Error and Status 1 register (RW)
Kojto	90:cb3d968589d8	1632	*
Kojto	90:cb3d968589d8	1633	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1634	*
Kojto	90:cb3d968589d8	1635	* This register reflects various error conditions, some general status of the
Kojto	90:cb3d968589d8	1636	* device and it is the source of interrupts to the CPU. The CPU read action
Kojto	90:cb3d968589d8	1637	* clears bits 15-10. Therefore the reported error conditions (bits 15-10) are those
Kojto	90:cb3d968589d8	1638	* that occurred since the last time the CPU read this register. Bits 9-3 are
Kojto	90:cb3d968589d8	1639	* status bits. The following table shows the FlexCAN state variables and their
Kojto	90:cb3d968589d8	1640	* meanings. Other combinations not shown in the table are reserved. SYNCH IDLE TX RX
Kojto	90:cb3d968589d8	1641	* FlexCAN State 0 0 0 0 Not synchronized to CAN bus 1 1 x x Idle 1 0 1 0
Kojto	90:cb3d968589d8	1642	* Transmitting 1 0 0 1 Receiving
Kojto	90:cb3d968589d8	1643	*/
Kojto	90:cb3d968589d8	1644	typedef union _hw_can_esr1
Kojto	90:cb3d968589d8	1645	{
Kojto	90:cb3d968589d8	1646	uint32_t U;
Kojto	90:cb3d968589d8	1647	struct _hw_can_esr1_bitfields
Kojto	90:cb3d968589d8	1648	{
Kojto	90:cb3d968589d8	1649	uint32_t WAKINT : 1; /!< [0] Wake-Up Interrupt /
Kojto	90:cb3d968589d8	1650	uint32_t ERRINT : 1; /!< [1] Error Interrupt /
Kojto	90:cb3d968589d8	1651	uint32_t BOFFINT : 1; /!< [2] Bus Off Interrupt /
Kojto	90:cb3d968589d8	1652	uint32_t RX : 1; /!< [3] FlexCAN In Reception /
Kojto	90:cb3d968589d8	1653	uint32_t FLTCONF : 2; /!< [5:4] Fault Confinement State /
Kojto	90:cb3d968589d8	1654	uint32_t TX : 1; /!< [6] FlexCAN In Transmission /
Kojto	90:cb3d968589d8	1655	uint32_t IDLE : 1; /!< [7] /
Kojto	90:cb3d968589d8	1656	uint32_t RXWRN : 1; /!< [8] Rx Error Warning /
Kojto	90:cb3d968589d8	1657	uint32_t TXWRN : 1; /!< [9] TX Error Warning /
Kojto	90:cb3d968589d8	1658	uint32_t STFERR : 1; /!< [10] Stuffing Error /
Kojto	90:cb3d968589d8	1659	uint32_t FRMERR : 1; /!< [11] Form Error /
Kojto	90:cb3d968589d8	1660	uint32_t CRCERR : 1; /!< [12] Cyclic Redundancy Check Error /
Kojto	90:cb3d968589d8	1661	uint32_t ACKERR : 1; /!< [13] Acknowledge Error /
Kojto	90:cb3d968589d8	1662	uint32_t BIT0ERR : 1; /!< [14] Bit0 Error /
Kojto	90:cb3d968589d8	1663	uint32_t BIT1ERR : 1; /!< [15] Bit1 Error /
Kojto	90:cb3d968589d8	1664	uint32_t RWRNINT : 1; /!< [16] Rx Warning Interrupt Flag /
Kojto	90:cb3d968589d8	1665	uint32_t TWRNINT : 1; /!< [17] Tx Warning Interrupt Flag /
Kojto	90:cb3d968589d8	1666	uint32_t SYNCH : 1; /!< [18] CAN Synchronization Status /
Kojto	90:cb3d968589d8	1667	uint32_t RESERVED0 : 13; /!< [31:19] /
Kojto	90:cb3d968589d8	1668	} B;
Kojto	90:cb3d968589d8	1669	} hw_can_esr1_t;
Kojto	90:cb3d968589d8	1670
Kojto	90:cb3d968589d8	1671	/*!
Kojto	90:cb3d968589d8	1672	* @name Constants and macros for entire CAN_ESR1 register
Kojto	90:cb3d968589d8	1673	*/
Kojto	90:cb3d968589d8	1674	/@{/
Kojto	90:cb3d968589d8	1675	#define HW_CAN_ESR1_ADDR(x) ((x) + 0x20U)
Kojto	90:cb3d968589d8	1676
Kojto	90:cb3d968589d8	1677	#define HW_CAN_ESR1(x) ((__IO hw_can_esr1_t ) HW_CAN_ESR1_ADDR(x))
Kojto	90:cb3d968589d8	1678	#define HW_CAN_ESR1_RD(x) (HW_CAN_ESR1(x).U)
Kojto	90:cb3d968589d8	1679	#define HW_CAN_ESR1_WR(x, v) (HW_CAN_ESR1(x).U = (v))
Kojto	90:cb3d968589d8	1680	#define HW_CAN_ESR1_SET(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1681	#define HW_CAN_ESR1_CLR(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1682	#define HW_CAN_ESR1_TOG(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1683	/@}/
Kojto	90:cb3d968589d8	1684
Kojto	90:cb3d968589d8	1685	/*
Kojto	90:cb3d968589d8	1686	* Constants & macros for individual CAN_ESR1 bitfields
Kojto	90:cb3d968589d8	1687	*/
Kojto	90:cb3d968589d8	1688
Kojto	90:cb3d968589d8	1689	/*!
Kojto	90:cb3d968589d8	1690	* @name Register CAN_ESR1, field WAKINT[0] (W1C)
Kojto	90:cb3d968589d8	1691	*
Kojto	90:cb3d968589d8	1692	* This field applies when FlexCAN is in low-power mode under Self Wake Up
Kojto	90:cb3d968589d8	1693	* mechanism: Stop mode When a recessive-to-dominant transition is detected on the CAN
Kojto	90:cb3d968589d8	1694	* bus and if the MCR[WAKMSK] bit is set, an interrupt is generated to the CPU.
Kojto	90:cb3d968589d8	1695	* This bit is cleared by writing it to 1. When MCR[SLFWAK] is negated, this flag
Kojto	90:cb3d968589d8	1696	* is masked. The CPU must clear this flag before disabling the bit. Otherwise
Kojto	90:cb3d968589d8	1697	* it will be set when the SLFWAK is set again. Writing 0 has no effect.
Kojto	90:cb3d968589d8	1698	*
Kojto	90:cb3d968589d8	1699	* Values:
Kojto	90:cb3d968589d8	1700	* - 0 - No such occurrence.
Kojto	90:cb3d968589d8	1701	* - 1 - Indicates a recessive to dominant transition was received on the CAN
Kojto	90:cb3d968589d8	1702	* bus.
Kojto	90:cb3d968589d8	1703	*/
Kojto	90:cb3d968589d8	1704	/@{/
Kojto	90:cb3d968589d8	1705	#define BP_CAN_ESR1_WAKINT (0U) /!< Bit position for CAN_ESR1_WAKINT. /
Kojto	90:cb3d968589d8	1706	#define BM_CAN_ESR1_WAKINT (0x00000001U) /!< Bit mask for CAN_ESR1_WAKINT. /
Kojto	90:cb3d968589d8	1707	#define BS_CAN_ESR1_WAKINT (1U) /!< Bit field size in bits for CAN_ESR1_WAKINT. /
Kojto	90:cb3d968589d8	1708
Kojto	90:cb3d968589d8	1709	/! @brief Read current value of the CAN_ESR1_WAKINT field. /
Kojto	90:cb3d968589d8	1710	#define BR_CAN_ESR1_WAKINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_WAKINT))
Kojto	90:cb3d968589d8	1711
Kojto	90:cb3d968589d8	1712	/! @brief Format value for bitfield CAN_ESR1_WAKINT. /
Kojto	90:cb3d968589d8	1713	#define BF_CAN_ESR1_WAKINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_WAKINT) & BM_CAN_ESR1_WAKINT)
Kojto	90:cb3d968589d8	1714
Kojto	90:cb3d968589d8	1715	/! @brief Set the WAKINT field to a new value. /
Kojto	90:cb3d968589d8	1716	#define BW_CAN_ESR1_WAKINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_WAKINT) = (v))
Kojto	90:cb3d968589d8	1717	/@}/
Kojto	90:cb3d968589d8	1718
Kojto	90:cb3d968589d8	1719	/*!
Kojto	90:cb3d968589d8	1720	* @name Register CAN_ESR1, field ERRINT[1] (W1C)
Kojto	90:cb3d968589d8	1721	*
Kojto	90:cb3d968589d8	1722	* This bit indicates that at least one of the Error Bits (bits 15-10) is set.
Kojto	90:cb3d968589d8	1723	* If the corresponding mask bit CTRL1[ERRMSK] is set, an interrupt is generated
Kojto	90:cb3d968589d8	1724	* to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
Kojto	90:cb3d968589d8	1725	*
Kojto	90:cb3d968589d8	1726	* Values:
Kojto	90:cb3d968589d8	1727	* - 0 - No such occurrence.
Kojto	90:cb3d968589d8	1728	* - 1 - Indicates setting of any Error Bit in the Error and Status Register.
Kojto	90:cb3d968589d8	1729	*/
Kojto	90:cb3d968589d8	1730	/@{/
Kojto	90:cb3d968589d8	1731	#define BP_CAN_ESR1_ERRINT (1U) /!< Bit position for CAN_ESR1_ERRINT. /
Kojto	90:cb3d968589d8	1732	#define BM_CAN_ESR1_ERRINT (0x00000002U) /!< Bit mask for CAN_ESR1_ERRINT. /
Kojto	90:cb3d968589d8	1733	#define BS_CAN_ESR1_ERRINT (1U) /!< Bit field size in bits for CAN_ESR1_ERRINT. /
Kojto	90:cb3d968589d8	1734
Kojto	90:cb3d968589d8	1735	/! @brief Read current value of the CAN_ESR1_ERRINT field. /
Kojto	90:cb3d968589d8	1736	#define BR_CAN_ESR1_ERRINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ERRINT))
Kojto	90:cb3d968589d8	1737
Kojto	90:cb3d968589d8	1738	/! @brief Format value for bitfield CAN_ESR1_ERRINT. /
Kojto	90:cb3d968589d8	1739	#define BF_CAN_ESR1_ERRINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_ERRINT) & BM_CAN_ESR1_ERRINT)
Kojto	90:cb3d968589d8	1740
Kojto	90:cb3d968589d8	1741	/! @brief Set the ERRINT field to a new value. /
Kojto	90:cb3d968589d8	1742	#define BW_CAN_ESR1_ERRINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ERRINT) = (v))
Kojto	90:cb3d968589d8	1743	/@}/
Kojto	90:cb3d968589d8	1744
Kojto	90:cb3d968589d8	1745	/*!
Kojto	90:cb3d968589d8	1746	* @name Register CAN_ESR1, field BOFFINT[2] (W1C)
Kojto	90:cb3d968589d8	1747	*
Kojto	90:cb3d968589d8	1748	* This bit is set when FlexCAN enters 'Bus Off' state. If the corresponding
Kojto	90:cb3d968589d8	1749	* mask bit in the Control Register (BOFFMSK) is set, an interrupt is generated to
Kojto	90:cb3d968589d8	1750	* the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
Kojto	90:cb3d968589d8	1751	*
Kojto	90:cb3d968589d8	1752	* Values:
Kojto	90:cb3d968589d8	1753	* - 0 - No such occurrence.
Kojto	90:cb3d968589d8	1754	* - 1 - FlexCAN module entered Bus Off state.
Kojto	90:cb3d968589d8	1755	*/
Kojto	90:cb3d968589d8	1756	/@{/
Kojto	90:cb3d968589d8	1757	#define BP_CAN_ESR1_BOFFINT (2U) /!< Bit position for CAN_ESR1_BOFFINT. /
Kojto	90:cb3d968589d8	1758	#define BM_CAN_ESR1_BOFFINT (0x00000004U) /!< Bit mask for CAN_ESR1_BOFFINT. /
Kojto	90:cb3d968589d8	1759	#define BS_CAN_ESR1_BOFFINT (1U) /!< Bit field size in bits for CAN_ESR1_BOFFINT. /
Kojto	90:cb3d968589d8	1760
Kojto	90:cb3d968589d8	1761	/! @brief Read current value of the CAN_ESR1_BOFFINT field. /
Kojto	90:cb3d968589d8	1762	#define BR_CAN_ESR1_BOFFINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BOFFINT))
Kojto	90:cb3d968589d8	1763
Kojto	90:cb3d968589d8	1764	/! @brief Format value for bitfield CAN_ESR1_BOFFINT. /
Kojto	90:cb3d968589d8	1765	#define BF_CAN_ESR1_BOFFINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_BOFFINT) & BM_CAN_ESR1_BOFFINT)
Kojto	90:cb3d968589d8	1766
Kojto	90:cb3d968589d8	1767	/! @brief Set the BOFFINT field to a new value. /
Kojto	90:cb3d968589d8	1768	#define BW_CAN_ESR1_BOFFINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BOFFINT) = (v))
Kojto	90:cb3d968589d8	1769	/@}/
Kojto	90:cb3d968589d8	1770
Kojto	90:cb3d968589d8	1771	/*!
Kojto	90:cb3d968589d8	1772	* @name Register CAN_ESR1, field RX[3] (RO)
Kojto	90:cb3d968589d8	1773	*
Kojto	90:cb3d968589d8	1774	* This bit indicates if FlexCAN is receiving a message. See the table in the
Kojto	90:cb3d968589d8	1775	* overall CAN_ESR1 register description.
Kojto	90:cb3d968589d8	1776	*
Kojto	90:cb3d968589d8	1777	* Values:
Kojto	90:cb3d968589d8	1778	* - 0 - FlexCAN is not receiving a message.
Kojto	90:cb3d968589d8	1779	* - 1 - FlexCAN is receiving a message.
Kojto	90:cb3d968589d8	1780	*/
Kojto	90:cb3d968589d8	1781	/@{/
Kojto	90:cb3d968589d8	1782	#define BP_CAN_ESR1_RX (3U) /!< Bit position for CAN_ESR1_RX. /
Kojto	90:cb3d968589d8	1783	#define BM_CAN_ESR1_RX (0x00000008U) /!< Bit mask for CAN_ESR1_RX. /
Kojto	90:cb3d968589d8	1784	#define BS_CAN_ESR1_RX (1U) /!< Bit field size in bits for CAN_ESR1_RX. /
Kojto	90:cb3d968589d8	1785
Kojto	90:cb3d968589d8	1786	/! @brief Read current value of the CAN_ESR1_RX field. /
Kojto	90:cb3d968589d8	1787	#define BR_CAN_ESR1_RX(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RX))
Kojto	90:cb3d968589d8	1788	/@}/
Kojto	90:cb3d968589d8	1789
Kojto	90:cb3d968589d8	1790	/*!
Kojto	90:cb3d968589d8	1791	* @name Register CAN_ESR1, field FLTCONF[5:4] (RO)
Kojto	90:cb3d968589d8	1792	*
Kojto	90:cb3d968589d8	1793	* This 2-bit field indicates the Confinement State of the FlexCAN module. If
Kojto	90:cb3d968589d8	1794	* the LOM bit in the Control Register is asserted, after some delay that depends
Kojto	90:cb3d968589d8	1795	* on the CAN bit timing the FLTCONF field will indicate "Error Passive". The very
Kojto	90:cb3d968589d8	1796	* same delay affects the way how FLTCONF reflects an update to ECR register by
Kojto	90:cb3d968589d8	1797	* the CPU. It may be necessary up to one CAN bit time to get them coherent
Kojto	90:cb3d968589d8	1798	* again. Because the Control Register is not affected by soft reset, the FLTCONF
Kojto	90:cb3d968589d8	1799	* field will not be affected by soft reset if the LOM bit is asserted.
Kojto	90:cb3d968589d8	1800	*
Kojto	90:cb3d968589d8	1801	* Values:
Kojto	90:cb3d968589d8	1802	* - 00 - Error Active
Kojto	90:cb3d968589d8	1803	* - 01 - Error Passive
Kojto	90:cb3d968589d8	1804	* - 1x - Bus Off
Kojto	90:cb3d968589d8	1805	*/
Kojto	90:cb3d968589d8	1806	/@{/
Kojto	90:cb3d968589d8	1807	#define BP_CAN_ESR1_FLTCONF (4U) /!< Bit position for CAN_ESR1_FLTCONF. /
Kojto	90:cb3d968589d8	1808	#define BM_CAN_ESR1_FLTCONF (0x00000030U) /!< Bit mask for CAN_ESR1_FLTCONF. /
Kojto	90:cb3d968589d8	1809	#define BS_CAN_ESR1_FLTCONF (2U) /!< Bit field size in bits for CAN_ESR1_FLTCONF. /
Kojto	90:cb3d968589d8	1810
Kojto	90:cb3d968589d8	1811	/! @brief Read current value of the CAN_ESR1_FLTCONF field. /
Kojto	90:cb3d968589d8	1812	#define BR_CAN_ESR1_FLTCONF(x) (HW_CAN_ESR1(x).B.FLTCONF)
Kojto	90:cb3d968589d8	1813	/@}/
Kojto	90:cb3d968589d8	1814
Kojto	90:cb3d968589d8	1815	/*!
Kojto	90:cb3d968589d8	1816	* @name Register CAN_ESR1, field TX[6] (RO)
Kojto	90:cb3d968589d8	1817	*
Kojto	90:cb3d968589d8	1818	* This bit indicates if FlexCAN is transmitting a message. See the table in the
Kojto	90:cb3d968589d8	1819	* overall CAN_ESR1 register description.
Kojto	90:cb3d968589d8	1820	*
Kojto	90:cb3d968589d8	1821	* Values:
Kojto	90:cb3d968589d8	1822	* - 0 - FlexCAN is not transmitting a message.
Kojto	90:cb3d968589d8	1823	* - 1 - FlexCAN is transmitting a message.
Kojto	90:cb3d968589d8	1824	*/
Kojto	90:cb3d968589d8	1825	/@{/
Kojto	90:cb3d968589d8	1826	#define BP_CAN_ESR1_TX (6U) /!< Bit position for CAN_ESR1_TX. /
Kojto	90:cb3d968589d8	1827	#define BM_CAN_ESR1_TX (0x00000040U) /!< Bit mask for CAN_ESR1_TX. /
Kojto	90:cb3d968589d8	1828	#define BS_CAN_ESR1_TX (1U) /!< Bit field size in bits for CAN_ESR1_TX. /
Kojto	90:cb3d968589d8	1829
Kojto	90:cb3d968589d8	1830	/! @brief Read current value of the CAN_ESR1_TX field. /
Kojto	90:cb3d968589d8	1831	#define BR_CAN_ESR1_TX(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TX))
Kojto	90:cb3d968589d8	1832	/@}/
Kojto	90:cb3d968589d8	1833
Kojto	90:cb3d968589d8	1834	/*!
Kojto	90:cb3d968589d8	1835	* @name Register CAN_ESR1, field IDLE[7] (RO)
Kojto	90:cb3d968589d8	1836	*
Kojto	90:cb3d968589d8	1837	* This bit indicates when CAN bus is in IDLE state. See the table in the
Kojto	90:cb3d968589d8	1838	* overall CAN_ESR1 register description.
Kojto	90:cb3d968589d8	1839	*
Kojto	90:cb3d968589d8	1840	* Values:
Kojto	90:cb3d968589d8	1841	* - 0 - No such occurrence.
Kojto	90:cb3d968589d8	1842	* - 1 - CAN bus is now IDLE.
Kojto	90:cb3d968589d8	1843	*/
Kojto	90:cb3d968589d8	1844	/@{/
Kojto	90:cb3d968589d8	1845	#define BP_CAN_ESR1_IDLE (7U) /!< Bit position for CAN_ESR1_IDLE. /
Kojto	90:cb3d968589d8	1846	#define BM_CAN_ESR1_IDLE (0x00000080U) /!< Bit mask for CAN_ESR1_IDLE. /
Kojto	90:cb3d968589d8	1847	#define BS_CAN_ESR1_IDLE (1U) /!< Bit field size in bits for CAN_ESR1_IDLE. /
Kojto	90:cb3d968589d8	1848
Kojto	90:cb3d968589d8	1849	/! @brief Read current value of the CAN_ESR1_IDLE field. /
Kojto	90:cb3d968589d8	1850	#define BR_CAN_ESR1_IDLE(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_IDLE))
Kojto	90:cb3d968589d8	1851	/@}/
Kojto	90:cb3d968589d8	1852
Kojto	90:cb3d968589d8	1853	/*!
Kojto	90:cb3d968589d8	1854	* @name Register CAN_ESR1, field RXWRN[8] (RO)
Kojto	90:cb3d968589d8	1855	*
Kojto	90:cb3d968589d8	1856	* This bit indicates when repetitive errors are occurring during message
Kojto	90:cb3d968589d8	1857	* reception. This bit is not updated during Freeze mode.
Kojto	90:cb3d968589d8	1858	*
Kojto	90:cb3d968589d8	1859	* Values:
Kojto	90:cb3d968589d8	1860	* - 0 - No such occurrence.
Kojto	90:cb3d968589d8	1861	* - 1 - RXERRCNT is greater than or equal to 96.
Kojto	90:cb3d968589d8	1862	*/
Kojto	90:cb3d968589d8	1863	/@{/
Kojto	90:cb3d968589d8	1864	#define BP_CAN_ESR1_RXWRN (8U) /!< Bit position for CAN_ESR1_RXWRN. /
Kojto	90:cb3d968589d8	1865	#define BM_CAN_ESR1_RXWRN (0x00000100U) /!< Bit mask for CAN_ESR1_RXWRN. /
Kojto	90:cb3d968589d8	1866	#define BS_CAN_ESR1_RXWRN (1U) /!< Bit field size in bits for CAN_ESR1_RXWRN. /
Kojto	90:cb3d968589d8	1867
Kojto	90:cb3d968589d8	1868	/! @brief Read current value of the CAN_ESR1_RXWRN field. /
Kojto	90:cb3d968589d8	1869	#define BR_CAN_ESR1_RXWRN(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RXWRN))
Kojto	90:cb3d968589d8	1870	/@}/
Kojto	90:cb3d968589d8	1871
Kojto	90:cb3d968589d8	1872	/*!
Kojto	90:cb3d968589d8	1873	* @name Register CAN_ESR1, field TXWRN[9] (RO)
Kojto	90:cb3d968589d8	1874	*
Kojto	90:cb3d968589d8	1875	* This bit indicates when repetitive errors are occurring during message
Kojto	90:cb3d968589d8	1876	* transmission. This bit is not updated during Freeze mode.
Kojto	90:cb3d968589d8	1877	*
Kojto	90:cb3d968589d8	1878	* Values:
Kojto	90:cb3d968589d8	1879	* - 0 - No such occurrence.
Kojto	90:cb3d968589d8	1880	* - 1 - TXERRCNT is greater than or equal to 96.
Kojto	90:cb3d968589d8	1881	*/
Kojto	90:cb3d968589d8	1882	/@{/
Kojto	90:cb3d968589d8	1883	#define BP_CAN_ESR1_TXWRN (9U) /!< Bit position for CAN_ESR1_TXWRN. /
Kojto	90:cb3d968589d8	1884	#define BM_CAN_ESR1_TXWRN (0x00000200U) /!< Bit mask for CAN_ESR1_TXWRN. /
Kojto	90:cb3d968589d8	1885	#define BS_CAN_ESR1_TXWRN (1U) /!< Bit field size in bits for CAN_ESR1_TXWRN. /
Kojto	90:cb3d968589d8	1886
Kojto	90:cb3d968589d8	1887	/! @brief Read current value of the CAN_ESR1_TXWRN field. /
Kojto	90:cb3d968589d8	1888	#define BR_CAN_ESR1_TXWRN(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TXWRN))
Kojto	90:cb3d968589d8	1889	/@}/
Kojto	90:cb3d968589d8	1890
Kojto	90:cb3d968589d8	1891	/*!
Kojto	90:cb3d968589d8	1892	* @name Register CAN_ESR1, field STFERR[10] (RO)
Kojto	90:cb3d968589d8	1893	*
Kojto	90:cb3d968589d8	1894	* This bit indicates that a Stuffing Error has been etected.
Kojto	90:cb3d968589d8	1895	*
Kojto	90:cb3d968589d8	1896	* Values:
Kojto	90:cb3d968589d8	1897	* - 0 - No such occurrence.
Kojto	90:cb3d968589d8	1898	* - 1 - A Stuffing Error occurred since last read of this register.
Kojto	90:cb3d968589d8	1899	*/
Kojto	90:cb3d968589d8	1900	/@{/
Kojto	90:cb3d968589d8	1901	#define BP_CAN_ESR1_STFERR (10U) /!< Bit position for CAN_ESR1_STFERR. /
Kojto	90:cb3d968589d8	1902	#define BM_CAN_ESR1_STFERR (0x00000400U) /!< Bit mask for CAN_ESR1_STFERR. /
Kojto	90:cb3d968589d8	1903	#define BS_CAN_ESR1_STFERR (1U) /!< Bit field size in bits for CAN_ESR1_STFERR. /
Kojto	90:cb3d968589d8	1904
Kojto	90:cb3d968589d8	1905	/! @brief Read current value of the CAN_ESR1_STFERR field. /
Kojto	90:cb3d968589d8	1906	#define BR_CAN_ESR1_STFERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_STFERR))
Kojto	90:cb3d968589d8	1907	/@}/
Kojto	90:cb3d968589d8	1908
Kojto	90:cb3d968589d8	1909	/*!
Kojto	90:cb3d968589d8	1910	* @name Register CAN_ESR1, field FRMERR[11] (RO)
Kojto	90:cb3d968589d8	1911	*
Kojto	90:cb3d968589d8	1912	* This bit indicates that a Form Error has been detected by the receiver node,
Kojto	90:cb3d968589d8	1913	* that is, a fixed-form bit field contains at least one illegal bit.
Kojto	90:cb3d968589d8	1914	*
Kojto	90:cb3d968589d8	1915	* Values:
Kojto	90:cb3d968589d8	1916	* - 0 - No such occurrence.
Kojto	90:cb3d968589d8	1917	* - 1 - A Form Error occurred since last read of this register.
Kojto	90:cb3d968589d8	1918	*/
Kojto	90:cb3d968589d8	1919	/@{/
Kojto	90:cb3d968589d8	1920	#define BP_CAN_ESR1_FRMERR (11U) /!< Bit position for CAN_ESR1_FRMERR. /
Kojto	90:cb3d968589d8	1921	#define BM_CAN_ESR1_FRMERR (0x00000800U) /!< Bit mask for CAN_ESR1_FRMERR. /
Kojto	90:cb3d968589d8	1922	#define BS_CAN_ESR1_FRMERR (1U) /!< Bit field size in bits for CAN_ESR1_FRMERR. /
Kojto	90:cb3d968589d8	1923
Kojto	90:cb3d968589d8	1924	/! @brief Read current value of the CAN_ESR1_FRMERR field. /
Kojto	90:cb3d968589d8	1925	#define BR_CAN_ESR1_FRMERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_FRMERR))
Kojto	90:cb3d968589d8	1926	/@}/
Kojto	90:cb3d968589d8	1927
Kojto	90:cb3d968589d8	1928	/*!
Kojto	90:cb3d968589d8	1929	* @name Register CAN_ESR1, field CRCERR[12] (RO)
Kojto	90:cb3d968589d8	1930	*
Kojto	90:cb3d968589d8	1931	* This bit indicates that a CRC Error has been detected by the receiver node,
Kojto	90:cb3d968589d8	1932	* that is, the calculated CRC is different from the received.
Kojto	90:cb3d968589d8	1933	*
Kojto	90:cb3d968589d8	1934	* Values:
Kojto	90:cb3d968589d8	1935	* - 0 - No such occurrence.
Kojto	90:cb3d968589d8	1936	* - 1 - A CRC error occurred since last read of this register.
Kojto	90:cb3d968589d8	1937	*/
Kojto	90:cb3d968589d8	1938	/@{/
Kojto	90:cb3d968589d8	1939	#define BP_CAN_ESR1_CRCERR (12U) /!< Bit position for CAN_ESR1_CRCERR. /
Kojto	90:cb3d968589d8	1940	#define BM_CAN_ESR1_CRCERR (0x00001000U) /!< Bit mask for CAN_ESR1_CRCERR. /
Kojto	90:cb3d968589d8	1941	#define BS_CAN_ESR1_CRCERR (1U) /!< Bit field size in bits for CAN_ESR1_CRCERR. /
Kojto	90:cb3d968589d8	1942
Kojto	90:cb3d968589d8	1943	/! @brief Read current value of the CAN_ESR1_CRCERR field. /
Kojto	90:cb3d968589d8	1944	#define BR_CAN_ESR1_CRCERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_CRCERR))
Kojto	90:cb3d968589d8	1945	/@}/
Kojto	90:cb3d968589d8	1946
Kojto	90:cb3d968589d8	1947	/*!
Kojto	90:cb3d968589d8	1948	* @name Register CAN_ESR1, field ACKERR[13] (RO)
Kojto	90:cb3d968589d8	1949	*
Kojto	90:cb3d968589d8	1950	* This bit indicates that an Acknowledge Error has been detected by the
Kojto	90:cb3d968589d8	1951	* transmitter node, that is, a dominant bit has not been detected during the ACK SLOT.
Kojto	90:cb3d968589d8	1952	*
Kojto	90:cb3d968589d8	1953	* Values:
Kojto	90:cb3d968589d8	1954	* - 0 - No such occurrence.
Kojto	90:cb3d968589d8	1955	* - 1 - An ACK error occurred since last read of this register.
Kojto	90:cb3d968589d8	1956	*/
Kojto	90:cb3d968589d8	1957	/@{/
Kojto	90:cb3d968589d8	1958	#define BP_CAN_ESR1_ACKERR (13U) /!< Bit position for CAN_ESR1_ACKERR. /
Kojto	90:cb3d968589d8	1959	#define BM_CAN_ESR1_ACKERR (0x00002000U) /!< Bit mask for CAN_ESR1_ACKERR. /
Kojto	90:cb3d968589d8	1960	#define BS_CAN_ESR1_ACKERR (1U) /!< Bit field size in bits for CAN_ESR1_ACKERR. /
Kojto	90:cb3d968589d8	1961
Kojto	90:cb3d968589d8	1962	/! @brief Read current value of the CAN_ESR1_ACKERR field. /
Kojto	90:cb3d968589d8	1963	#define BR_CAN_ESR1_ACKERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ACKERR))
Kojto	90:cb3d968589d8	1964	/@}/
Kojto	90:cb3d968589d8	1965
Kojto	90:cb3d968589d8	1966	/*!
Kojto	90:cb3d968589d8	1967	* @name Register CAN_ESR1, field BIT0ERR[14] (RO)
Kojto	90:cb3d968589d8	1968	*
Kojto	90:cb3d968589d8	1969	* This bit indicates when an inconsistency occurs between the transmitted and
Kojto	90:cb3d968589d8	1970	* the received bit in a message.
Kojto	90:cb3d968589d8	1971	*
Kojto	90:cb3d968589d8	1972	* Values:
Kojto	90:cb3d968589d8	1973	* - 0 - No such occurrence.
Kojto	90:cb3d968589d8	1974	* - 1 - At least one bit sent as dominant is received as recessive.
Kojto	90:cb3d968589d8	1975	*/
Kojto	90:cb3d968589d8	1976	/@{/
Kojto	90:cb3d968589d8	1977	#define BP_CAN_ESR1_BIT0ERR (14U) /!< Bit position for CAN_ESR1_BIT0ERR. /
Kojto	90:cb3d968589d8	1978	#define BM_CAN_ESR1_BIT0ERR (0x00004000U) /!< Bit mask for CAN_ESR1_BIT0ERR. /
Kojto	90:cb3d968589d8	1979	#define BS_CAN_ESR1_BIT0ERR (1U) /!< Bit field size in bits for CAN_ESR1_BIT0ERR. /
Kojto	90:cb3d968589d8	1980
Kojto	90:cb3d968589d8	1981	/! @brief Read current value of the CAN_ESR1_BIT0ERR field. /
Kojto	90:cb3d968589d8	1982	#define BR_CAN_ESR1_BIT0ERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BIT0ERR))
Kojto	90:cb3d968589d8	1983	/@}/
Kojto	90:cb3d968589d8	1984
Kojto	90:cb3d968589d8	1985	/*!
Kojto	90:cb3d968589d8	1986	* @name Register CAN_ESR1, field BIT1ERR[15] (RO)
Kojto	90:cb3d968589d8	1987	*
Kojto	90:cb3d968589d8	1988	* This bit indicates when an inconsistency occurs between the transmitted and
Kojto	90:cb3d968589d8	1989	* the received bit in a message. This bit is not set by a transmitter in case of
Kojto	90:cb3d968589d8	1990	* arbitration field or ACK slot, or in case of a node sending a passive error
Kojto	90:cb3d968589d8	1991	* flag that detects dominant bits.
Kojto	90:cb3d968589d8	1992	*
Kojto	90:cb3d968589d8	1993	* Values:
Kojto	90:cb3d968589d8	1994	* - 0 - No such occurrence.
Kojto	90:cb3d968589d8	1995	* - 1 - At least one bit sent as recessive is received as dominant.
Kojto	90:cb3d968589d8	1996	*/
Kojto	90:cb3d968589d8	1997	/@{/
Kojto	90:cb3d968589d8	1998	#define BP_CAN_ESR1_BIT1ERR (15U) /!< Bit position for CAN_ESR1_BIT1ERR. /
Kojto	90:cb3d968589d8	1999	#define BM_CAN_ESR1_BIT1ERR (0x00008000U) /!< Bit mask for CAN_ESR1_BIT1ERR. /
Kojto	90:cb3d968589d8	2000	#define BS_CAN_ESR1_BIT1ERR (1U) /!< Bit field size in bits for CAN_ESR1_BIT1ERR. /
Kojto	90:cb3d968589d8	2001
Kojto	90:cb3d968589d8	2002	/! @brief Read current value of the CAN_ESR1_BIT1ERR field. /
Kojto	90:cb3d968589d8	2003	#define BR_CAN_ESR1_BIT1ERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BIT1ERR))
Kojto	90:cb3d968589d8	2004	/@}/
Kojto	90:cb3d968589d8	2005
Kojto	90:cb3d968589d8	2006	/*!
Kojto	90:cb3d968589d8	2007	* @name Register CAN_ESR1, field RWRNINT[16] (W1C)
Kojto	90:cb3d968589d8	2008	*
Kojto	90:cb3d968589d8	2009	* If the WRNEN bit in MCR is asserted, the RWRNINT bit is set when the RXWRN
Kojto	90:cb3d968589d8	2010	* flag transitions from 0 to 1, meaning that the Rx error counters reached 96. If
Kojto	90:cb3d968589d8	2011	* the corresponding mask bit in the Control Register (RWRNMSK) is set, an
Kojto	90:cb3d968589d8	2012	* interrupt is generated to the CPU. This bit is cleared by writing it to 1. When
Kojto	90:cb3d968589d8	2013	* WRNEN is negated, this flag is masked. CPU must clear this flag before disabling
Kojto	90:cb3d968589d8	2014	* the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
Kojto	90:cb3d968589d8	2015	* effect. This bit is not updated during Freeze mode.
Kojto	90:cb3d968589d8	2016	*
Kojto	90:cb3d968589d8	2017	* Values:
Kojto	90:cb3d968589d8	2018	* - 0 - No such occurrence.
Kojto	90:cb3d968589d8	2019	* - 1 - The Rx error counter transitioned from less than 96 to greater than or
Kojto	90:cb3d968589d8	2020	* equal to 96.
Kojto	90:cb3d968589d8	2021	*/
Kojto	90:cb3d968589d8	2022	/@{/
Kojto	90:cb3d968589d8	2023	#define BP_CAN_ESR1_RWRNINT (16U) /!< Bit position for CAN_ESR1_RWRNINT. /
Kojto	90:cb3d968589d8	2024	#define BM_CAN_ESR1_RWRNINT (0x00010000U) /!< Bit mask for CAN_ESR1_RWRNINT. /
Kojto	90:cb3d968589d8	2025	#define BS_CAN_ESR1_RWRNINT (1U) /!< Bit field size in bits for CAN_ESR1_RWRNINT. /
Kojto	90:cb3d968589d8	2026
Kojto	90:cb3d968589d8	2027	/! @brief Read current value of the CAN_ESR1_RWRNINT field. /
Kojto	90:cb3d968589d8	2028	#define BR_CAN_ESR1_RWRNINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RWRNINT))
Kojto	90:cb3d968589d8	2029
Kojto	90:cb3d968589d8	2030	/! @brief Format value for bitfield CAN_ESR1_RWRNINT. /
Kojto	90:cb3d968589d8	2031	#define BF_CAN_ESR1_RWRNINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_RWRNINT) & BM_CAN_ESR1_RWRNINT)
Kojto	90:cb3d968589d8	2032
Kojto	90:cb3d968589d8	2033	/! @brief Set the RWRNINT field to a new value. /
Kojto	90:cb3d968589d8	2034	#define BW_CAN_ESR1_RWRNINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RWRNINT) = (v))
Kojto	90:cb3d968589d8	2035	/@}/
Kojto	90:cb3d968589d8	2036
Kojto	90:cb3d968589d8	2037	/*!
Kojto	90:cb3d968589d8	2038	* @name Register CAN_ESR1, field TWRNINT[17] (W1C)
Kojto	90:cb3d968589d8	2039	*
Kojto	90:cb3d968589d8	2040	* If the WRNEN bit in MCR is asserted, the TWRNINT bit is set when the TXWRN
Kojto	90:cb3d968589d8	2041	* flag transitions from 0 to 1, meaning that the Tx error counter reached 96. If
Kojto	90:cb3d968589d8	2042	* the corresponding mask bit in the Control Register (TWRNMSK) is set, an
Kojto	90:cb3d968589d8	2043	* interrupt is generated to the CPU. This bit is cleared by writing it to 1. When WRNEN
Kojto	90:cb3d968589d8	2044	* is negated, this flag is masked. CPU must clear this flag before disabling
Kojto	90:cb3d968589d8	2045	* the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
Kojto	90:cb3d968589d8	2046	* effect. This flag is not generated during Bus Off state. This bit is not
Kojto	90:cb3d968589d8	2047	* updated during Freeze mode.
Kojto	90:cb3d968589d8	2048	*
Kojto	90:cb3d968589d8	2049	* Values:
Kojto	90:cb3d968589d8	2050	* - 0 - No such occurrence.
Kojto	90:cb3d968589d8	2051	* - 1 - The Tx error counter transitioned from less than 96 to greater than or
Kojto	90:cb3d968589d8	2052	* equal to 96.
Kojto	90:cb3d968589d8	2053	*/
Kojto	90:cb3d968589d8	2054	/@{/
Kojto	90:cb3d968589d8	2055	#define BP_CAN_ESR1_TWRNINT (17U) /!< Bit position for CAN_ESR1_TWRNINT. /
Kojto	90:cb3d968589d8	2056	#define BM_CAN_ESR1_TWRNINT (0x00020000U) /!< Bit mask for CAN_ESR1_TWRNINT. /
Kojto	90:cb3d968589d8	2057	#define BS_CAN_ESR1_TWRNINT (1U) /!< Bit field size in bits for CAN_ESR1_TWRNINT. /
Kojto	90:cb3d968589d8	2058
Kojto	90:cb3d968589d8	2059	/! @brief Read current value of the CAN_ESR1_TWRNINT field. /
Kojto	90:cb3d968589d8	2060	#define BR_CAN_ESR1_TWRNINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TWRNINT))
Kojto	90:cb3d968589d8	2061
Kojto	90:cb3d968589d8	2062	/! @brief Format value for bitfield CAN_ESR1_TWRNINT. /
Kojto	90:cb3d968589d8	2063	#define BF_CAN_ESR1_TWRNINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_TWRNINT) & BM_CAN_ESR1_TWRNINT)
Kojto	90:cb3d968589d8	2064
Kojto	90:cb3d968589d8	2065	/! @brief Set the TWRNINT field to a new value. /
Kojto	90:cb3d968589d8	2066	#define BW_CAN_ESR1_TWRNINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TWRNINT) = (v))
Kojto	90:cb3d968589d8	2067	/@}/
Kojto	90:cb3d968589d8	2068
Kojto	90:cb3d968589d8	2069	/*!
Kojto	90:cb3d968589d8	2070	* @name Register CAN_ESR1, field SYNCH[18] (RO)
Kojto	90:cb3d968589d8	2071	*
Kojto	90:cb3d968589d8	2072	* This read-only flag indicates whether the FlexCAN is synchronized to the CAN
Kojto	90:cb3d968589d8	2073	* bus and able to participate in the communication process. It is set and
Kojto	90:cb3d968589d8	2074	* cleared by the FlexCAN. See the table in the overall CAN_ESR1 register description.
Kojto	90:cb3d968589d8	2075	*
Kojto	90:cb3d968589d8	2076	* Values:
Kojto	90:cb3d968589d8	2077	* - 0 - FlexCAN is not synchronized to the CAN bus.
Kojto	90:cb3d968589d8	2078	* - 1 - FlexCAN is synchronized to the CAN bus.
Kojto	90:cb3d968589d8	2079	*/
Kojto	90:cb3d968589d8	2080	/@{/
Kojto	90:cb3d968589d8	2081	#define BP_CAN_ESR1_SYNCH (18U) /!< Bit position for CAN_ESR1_SYNCH. /
Kojto	90:cb3d968589d8	2082	#define BM_CAN_ESR1_SYNCH (0x00040000U) /!< Bit mask for CAN_ESR1_SYNCH. /
Kojto	90:cb3d968589d8	2083	#define BS_CAN_ESR1_SYNCH (1U) /!< Bit field size in bits for CAN_ESR1_SYNCH. /
Kojto	90:cb3d968589d8	2084
Kojto	90:cb3d968589d8	2085	/! @brief Read current value of the CAN_ESR1_SYNCH field. /
Kojto	90:cb3d968589d8	2086	#define BR_CAN_ESR1_SYNCH(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_SYNCH))
Kojto	90:cb3d968589d8	2087	/@}/
Kojto	90:cb3d968589d8	2088
Kojto	90:cb3d968589d8	2089	/*******************************************************************************
Kojto	90:cb3d968589d8	2090	* HW_CAN_IMASK1 - Interrupt Masks 1 register
Kojto	90:cb3d968589d8	2091	******************************************************************************/
Kojto	90:cb3d968589d8	2092
Kojto	90:cb3d968589d8	2093	/*!
Kojto	90:cb3d968589d8	2094	* @brief HW_CAN_IMASK1 - Interrupt Masks 1 register (RW)
Kojto	90:cb3d968589d8	2095	*
Kojto	90:cb3d968589d8	2096	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2097	*
Kojto	90:cb3d968589d8	2098	* This register allows any number of a range of the 32 Message Buffer
Kojto	90:cb3d968589d8	2099	* Interrupts to be enabled or disabled for MB31 to MB0. It contains one interrupt mask
Kojto	90:cb3d968589d8	2100	* bit per buffer, enabling the CPU to determine which buffer generates an
Kojto	90:cb3d968589d8	2101	* interrupt after a successful transmission or reception, that is, when the
Kojto	90:cb3d968589d8	2102	* corresponding IFLAG1 bit is set.
Kojto	90:cb3d968589d8	2103	*/
Kojto	90:cb3d968589d8	2104	typedef union _hw_can_imask1
Kojto	90:cb3d968589d8	2105	{
Kojto	90:cb3d968589d8	2106	uint32_t U;
Kojto	90:cb3d968589d8	2107	struct _hw_can_imask1_bitfields
Kojto	90:cb3d968589d8	2108	{
Kojto	90:cb3d968589d8	2109	uint32_t BUFLM : 32; /!< [31:0] Buffer MB i Mask /
Kojto	90:cb3d968589d8	2110	} B;
Kojto	90:cb3d968589d8	2111	} hw_can_imask1_t;
Kojto	90:cb3d968589d8	2112
Kojto	90:cb3d968589d8	2113	/*!
Kojto	90:cb3d968589d8	2114	* @name Constants and macros for entire CAN_IMASK1 register
Kojto	90:cb3d968589d8	2115	*/
Kojto	90:cb3d968589d8	2116	/@{/
Kojto	90:cb3d968589d8	2117	#define HW_CAN_IMASK1_ADDR(x) ((x) + 0x28U)
Kojto	90:cb3d968589d8	2118
Kojto	90:cb3d968589d8	2119	#define HW_CAN_IMASK1(x) ((__IO hw_can_imask1_t ) HW_CAN_IMASK1_ADDR(x))
Kojto	90:cb3d968589d8	2120	#define HW_CAN_IMASK1_RD(x) (HW_CAN_IMASK1(x).U)
Kojto	90:cb3d968589d8	2121	#define HW_CAN_IMASK1_WR(x, v) (HW_CAN_IMASK1(x).U = (v))
Kojto	90:cb3d968589d8	2122	#define HW_CAN_IMASK1_SET(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2123	#define HW_CAN_IMASK1_CLR(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2124	#define HW_CAN_IMASK1_TOG(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2125	/@}/
Kojto	90:cb3d968589d8	2126
Kojto	90:cb3d968589d8	2127	/*
Kojto	90:cb3d968589d8	2128	* Constants & macros for individual CAN_IMASK1 bitfields
Kojto	90:cb3d968589d8	2129	*/
Kojto	90:cb3d968589d8	2130
Kojto	90:cb3d968589d8	2131	/*!
Kojto	90:cb3d968589d8	2132	* @name Register CAN_IMASK1, field BUFLM[31:0] (RW)
Kojto	90:cb3d968589d8	2133	*
Kojto	90:cb3d968589d8	2134	* Each bit enables or disables the corresponding FlexCAN Message Buffer
Kojto	90:cb3d968589d8	2135	* Interrupt for MB31 to MB0. Setting or clearing a bit in the IMASK1 Register can
Kojto	90:cb3d968589d8	2136	* assert or negate an interrupt request, if the corresponding IFLAG1 bit is set.
Kojto	90:cb3d968589d8	2137	*
Kojto	90:cb3d968589d8	2138	* Values:
Kojto	90:cb3d968589d8	2139	* - 0 - The corresponding buffer Interrupt is disabled.
Kojto	90:cb3d968589d8	2140	* - 1 - The corresponding buffer Interrupt is enabled.
Kojto	90:cb3d968589d8	2141	*/
Kojto	90:cb3d968589d8	2142	/@{/
Kojto	90:cb3d968589d8	2143	#define BP_CAN_IMASK1_BUFLM (0U) /!< Bit position for CAN_IMASK1_BUFLM. /
Kojto	90:cb3d968589d8	2144	#define BM_CAN_IMASK1_BUFLM (0xFFFFFFFFU) /!< Bit mask for CAN_IMASK1_BUFLM. /
Kojto	90:cb3d968589d8	2145	#define BS_CAN_IMASK1_BUFLM (32U) /!< Bit field size in bits for CAN_IMASK1_BUFLM. /
Kojto	90:cb3d968589d8	2146
Kojto	90:cb3d968589d8	2147	/! @brief Read current value of the CAN_IMASK1_BUFLM field. /
Kojto	90:cb3d968589d8	2148	#define BR_CAN_IMASK1_BUFLM(x) (HW_CAN_IMASK1(x).U)
Kojto	90:cb3d968589d8	2149
Kojto	90:cb3d968589d8	2150	/! @brief Format value for bitfield CAN_IMASK1_BUFLM. /
Kojto	90:cb3d968589d8	2151	#define BF_CAN_IMASK1_BUFLM(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IMASK1_BUFLM) & BM_CAN_IMASK1_BUFLM)
Kojto	90:cb3d968589d8	2152
Kojto	90:cb3d968589d8	2153	/! @brief Set the BUFLM field to a new value. /
Kojto	90:cb3d968589d8	2154	#define BW_CAN_IMASK1_BUFLM(x, v) (HW_CAN_IMASK1_WR(x, v))
Kojto	90:cb3d968589d8	2155	/@}/
Kojto	90:cb3d968589d8	2156
Kojto	90:cb3d968589d8	2157	/*******************************************************************************
Kojto	90:cb3d968589d8	2158	* HW_CAN_IFLAG1 - Interrupt Flags 1 register
Kojto	90:cb3d968589d8	2159	******************************************************************************/
Kojto	90:cb3d968589d8	2160
Kojto	90:cb3d968589d8	2161	/*!
Kojto	90:cb3d968589d8	2162	* @brief HW_CAN_IFLAG1 - Interrupt Flags 1 register (W1C)
Kojto	90:cb3d968589d8	2163	*
Kojto	90:cb3d968589d8	2164	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2165	*
Kojto	90:cb3d968589d8	2166	* This register defines the flags for the 32 Message Buffer interrupts for MB31
Kojto	90:cb3d968589d8	2167	* to MB0. It contains one interrupt flag bit per buffer. Each successful
Kojto	90:cb3d968589d8	2168	* transmission or reception sets the corresponding IFLAG1 bit. If the corresponding
Kojto	90:cb3d968589d8	2169	* IMASK1 bit is set, an interrupt will be generated. The interrupt flag must be
Kojto	90:cb3d968589d8	2170	* cleared by writing 1 to it. Writing 0 has no effect. The BUF7I to BUF5I flags
Kojto	90:cb3d968589d8	2171	* are also used to represent FIFO interrupts when the Rx FIFO is enabled. When the
Kojto	90:cb3d968589d8	2172	* bit MCR[RFEN] is set, the function of the 8 least significant interrupt flags
Kojto	90:cb3d968589d8	2173	* BUF[7:0]I changes: BUF7I, BUF6I and BUF5I indicate operating conditions of
Kojto	90:cb3d968589d8	2174	* the FIFO, and the BUF4TO0I field is reserved. Before enabling the RFEN, the CPU
Kojto	90:cb3d968589d8	2175	* must service the IFLAG bits asserted in the Rx FIFO region; see Section "Rx
Kojto	90:cb3d968589d8	2176	* FIFO". Otherwise, these IFLAG bits will mistakenly show the related MBs now
Kojto	90:cb3d968589d8	2177	* belonging to FIFO as having contents to be serviced. When the RFEN bit is negated,
Kojto	90:cb3d968589d8	2178	* the FIFO flags must be cleared. The same care must be taken when an RFFN
Kojto	90:cb3d968589d8	2179	* value is selected extending Rx FIFO filters beyond MB7. For example, when RFFN is
Kojto	90:cb3d968589d8	2180	* 0x8, the MB0-23 range is occupied by Rx FIFO filters and related IFLAG bits
Kojto	90:cb3d968589d8	2181	* must be cleared. Before updating MCR[MAXMB] field, CPU must service the IFLAG1
Kojto	90:cb3d968589d8	2182	* bits whose MB value is greater than the MCR[MAXMB] to be updated; otherwise,
Kojto	90:cb3d968589d8	2183	* they will remain set and be inconsistent with the number of MBs available.
Kojto	90:cb3d968589d8	2184	*/
Kojto	90:cb3d968589d8	2185	typedef union _hw_can_iflag1
Kojto	90:cb3d968589d8	2186	{
Kojto	90:cb3d968589d8	2187	uint32_t U;
Kojto	90:cb3d968589d8	2188	struct _hw_can_iflag1_bitfields
Kojto	90:cb3d968589d8	2189	{
Kojto	90:cb3d968589d8	2190	uint32_t BUF0I : 1; /!< [0] Buffer MB0 Interrupt Or "reserved" /
Kojto	90:cb3d968589d8	2191	uint32_t BUF4TO1I : 4; /*!< [4:1] Buffer MB i Interrupt Or "reserved"
Kojto	90:cb3d968589d8	2192	* */
Kojto	90:cb3d968589d8	2193	uint32_t BUF5I : 1; /*!< [5] Buffer MB5 Interrupt Or "Frames
Kojto	90:cb3d968589d8	2194	* available in Rx FIFO" */
Kojto	90:cb3d968589d8	2195	uint32_t BUF6I : 1; /*!< [6] Buffer MB6 Interrupt Or "Rx FIFO
Kojto	90:cb3d968589d8	2196	* Warning" */
Kojto	90:cb3d968589d8	2197	uint32_t BUF7I : 1; /*!< [7] Buffer MB7 Interrupt Or "Rx FIFO
Kojto	90:cb3d968589d8	2198	* Overflow" */
Kojto	90:cb3d968589d8	2199	uint32_t BUF31TO8I : 24; /!< [31:8] Buffer MBi Interrupt /
Kojto	90:cb3d968589d8	2200	} B;
Kojto	90:cb3d968589d8	2201	} hw_can_iflag1_t;
Kojto	90:cb3d968589d8	2202
Kojto	90:cb3d968589d8	2203	/*!
Kojto	90:cb3d968589d8	2204	* @name Constants and macros for entire CAN_IFLAG1 register
Kojto	90:cb3d968589d8	2205	*/
Kojto	90:cb3d968589d8	2206	/@{/
Kojto	90:cb3d968589d8	2207	#define HW_CAN_IFLAG1_ADDR(x) ((x) + 0x30U)
Kojto	90:cb3d968589d8	2208
Kojto	90:cb3d968589d8	2209	#define HW_CAN_IFLAG1(x) ((__IO hw_can_iflag1_t ) HW_CAN_IFLAG1_ADDR(x))
Kojto	90:cb3d968589d8	2210	#define HW_CAN_IFLAG1_RD(x) (HW_CAN_IFLAG1(x).U)
Kojto	90:cb3d968589d8	2211	#define HW_CAN_IFLAG1_WR(x, v) (HW_CAN_IFLAG1(x).U = (v))
Kojto	90:cb3d968589d8	2212	#define HW_CAN_IFLAG1_SET(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2213	#define HW_CAN_IFLAG1_CLR(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2214	#define HW_CAN_IFLAG1_TOG(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2215	/@}/
Kojto	90:cb3d968589d8	2216
Kojto	90:cb3d968589d8	2217	/*
Kojto	90:cb3d968589d8	2218	* Constants & macros for individual CAN_IFLAG1 bitfields
Kojto	90:cb3d968589d8	2219	*/
Kojto	90:cb3d968589d8	2220
Kojto	90:cb3d968589d8	2221	/*!
Kojto	90:cb3d968589d8	2222	* @name Register CAN_IFLAG1, field BUF0I[0] (W1C)
Kojto	90:cb3d968589d8	2223	*
Kojto	90:cb3d968589d8	2224	* When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
Kojto	90:cb3d968589d8	2225	* the interrupt for MB0. This flag is cleared by the FlexCAN whenever the bit
Kojto	90:cb3d968589d8	2226	* MCR[RFEN] is changed by CPU writes. The BUF0I flag is reserved when MCR[RFEN] is
Kojto	90:cb3d968589d8	2227	* set.
Kojto	90:cb3d968589d8	2228	*
Kojto	90:cb3d968589d8	2229	* Values:
Kojto	90:cb3d968589d8	2230	* - 0 - The corresponding buffer has no occurrence of successfully completed
Kojto	90:cb3d968589d8	2231	* transmission or reception when MCR[RFEN]=0.
Kojto	90:cb3d968589d8	2232	* - 1 - The corresponding buffer has successfully completed transmission or
Kojto	90:cb3d968589d8	2233	* reception when MCR[RFEN]=0.
Kojto	90:cb3d968589d8	2234	*/
Kojto	90:cb3d968589d8	2235	/@{/
Kojto	90:cb3d968589d8	2236	#define BP_CAN_IFLAG1_BUF0I (0U) /!< Bit position for CAN_IFLAG1_BUF0I. /
Kojto	90:cb3d968589d8	2237	#define BM_CAN_IFLAG1_BUF0I (0x00000001U) /!< Bit mask for CAN_IFLAG1_BUF0I. /
Kojto	90:cb3d968589d8	2238	#define BS_CAN_IFLAG1_BUF0I (1U) /!< Bit field size in bits for CAN_IFLAG1_BUF0I. /
Kojto	90:cb3d968589d8	2239
Kojto	90:cb3d968589d8	2240	/! @brief Read current value of the CAN_IFLAG1_BUF0I field. /
Kojto	90:cb3d968589d8	2241	#define BR_CAN_IFLAG1_BUF0I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF0I))
Kojto	90:cb3d968589d8	2242
Kojto	90:cb3d968589d8	2243	/! @brief Format value for bitfield CAN_IFLAG1_BUF0I. /
Kojto	90:cb3d968589d8	2244	#define BF_CAN_IFLAG1_BUF0I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF0I) & BM_CAN_IFLAG1_BUF0I)
Kojto	90:cb3d968589d8	2245
Kojto	90:cb3d968589d8	2246	/! @brief Set the BUF0I field to a new value. /
Kojto	90:cb3d968589d8	2247	#define BW_CAN_IFLAG1_BUF0I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF0I) = (v))
Kojto	90:cb3d968589d8	2248	/@}/
Kojto	90:cb3d968589d8	2249
Kojto	90:cb3d968589d8	2250	/*!
Kojto	90:cb3d968589d8	2251	* @name Register CAN_IFLAG1, field BUF4TO1I[4:1] (W1C)
Kojto	90:cb3d968589d8	2252	*
Kojto	90:cb3d968589d8	2253	* When the RFEN bit in the MCR is cleared (Rx FIFO disabled), these bits flag
Kojto	90:cb3d968589d8	2254	* the interrupts for MB4 to MB1. These flags are cleared by the FlexCAN whenever
Kojto	90:cb3d968589d8	2255	* the bit MCR[RFEN] is changed by CPU writes. The BUF4TO1I flags are reserved
Kojto	90:cb3d968589d8	2256	* when MCR[RFEN] is set.
Kojto	90:cb3d968589d8	2257	*
Kojto	90:cb3d968589d8	2258	* Values:
Kojto	90:cb3d968589d8	2259	* - 0 - The corresponding buffer has no occurrence of successfully completed
Kojto	90:cb3d968589d8	2260	* transmission or reception when MCR[RFEN]=0.
Kojto	90:cb3d968589d8	2261	* - 1 - The corresponding buffer has successfully completed transmission or
Kojto	90:cb3d968589d8	2262	* reception when MCR[RFEN]=0.
Kojto	90:cb3d968589d8	2263	*/
Kojto	90:cb3d968589d8	2264	/@{/
Kojto	90:cb3d968589d8	2265	#define BP_CAN_IFLAG1_BUF4TO1I (1U) /!< Bit position for CAN_IFLAG1_BUF4TO1I. /
Kojto	90:cb3d968589d8	2266	#define BM_CAN_IFLAG1_BUF4TO1I (0x0000001EU) /!< Bit mask for CAN_IFLAG1_BUF4TO1I. /
Kojto	90:cb3d968589d8	2267	#define BS_CAN_IFLAG1_BUF4TO1I (4U) /!< Bit field size in bits for CAN_IFLAG1_BUF4TO1I. /
Kojto	90:cb3d968589d8	2268
Kojto	90:cb3d968589d8	2269	/! @brief Read current value of the CAN_IFLAG1_BUF4TO1I field. /
Kojto	90:cb3d968589d8	2270	#define BR_CAN_IFLAG1_BUF4TO1I(x) (HW_CAN_IFLAG1(x).B.BUF4TO1I)
Kojto	90:cb3d968589d8	2271
Kojto	90:cb3d968589d8	2272	/! @brief Format value for bitfield CAN_IFLAG1_BUF4TO1I. /
Kojto	90:cb3d968589d8	2273	#define BF_CAN_IFLAG1_BUF4TO1I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF4TO1I) & BM_CAN_IFLAG1_BUF4TO1I)
Kojto	90:cb3d968589d8	2274
Kojto	90:cb3d968589d8	2275	/! @brief Set the BUF4TO1I field to a new value. /
Kojto	90:cb3d968589d8	2276	#define BW_CAN_IFLAG1_BUF4TO1I(x, v) (HW_CAN_IFLAG1_WR(x, (HW_CAN_IFLAG1_RD(x) & ~BM_CAN_IFLAG1_BUF4TO1I) \| BF_CAN_IFLAG1_BUF4TO1I(v)))
Kojto	90:cb3d968589d8	2277	/@}/
Kojto	90:cb3d968589d8	2278
Kojto	90:cb3d968589d8	2279	/*!
Kojto	90:cb3d968589d8	2280	* @name Register CAN_IFLAG1, field BUF5I[5] (W1C)
Kojto	90:cb3d968589d8	2281	*
Kojto	90:cb3d968589d8	2282	* When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
Kojto	90:cb3d968589d8	2283	* the interrupt for MB5. This flag is cleared by the FlexCAN whenever the bit
Kojto	90:cb3d968589d8	2284	* MCR[RFEN] is changed by CPU writes. The BUF5I flag represents "Frames available in
Kojto	90:cb3d968589d8	2285	* Rx FIFO" when MCR[RFEN] is set. In this case, the flag indicates that at
Kojto	90:cb3d968589d8	2286	* least one frame is available to be read from the Rx FIFO.
Kojto	90:cb3d968589d8	2287	*
Kojto	90:cb3d968589d8	2288	* Values:
Kojto	90:cb3d968589d8	2289	* - 0 - No occurrence of MB5 completing transmission/reception when
Kojto	90:cb3d968589d8	2290	* MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
Kojto	90:cb3d968589d8	2291	* - 1 - MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s)
Kojto	90:cb3d968589d8	2292	* available in the Rx FIFO when MCR[RFEN]=1
Kojto	90:cb3d968589d8	2293	*/
Kojto	90:cb3d968589d8	2294	/@{/
Kojto	90:cb3d968589d8	2295	#define BP_CAN_IFLAG1_BUF5I (5U) /!< Bit position for CAN_IFLAG1_BUF5I. /
Kojto	90:cb3d968589d8	2296	#define BM_CAN_IFLAG1_BUF5I (0x00000020U) /!< Bit mask for CAN_IFLAG1_BUF5I. /
Kojto	90:cb3d968589d8	2297	#define BS_CAN_IFLAG1_BUF5I (1U) /!< Bit field size in bits for CAN_IFLAG1_BUF5I. /
Kojto	90:cb3d968589d8	2298
Kojto	90:cb3d968589d8	2299	/! @brief Read current value of the CAN_IFLAG1_BUF5I field. /
Kojto	90:cb3d968589d8	2300	#define BR_CAN_IFLAG1_BUF5I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF5I))
Kojto	90:cb3d968589d8	2301
Kojto	90:cb3d968589d8	2302	/! @brief Format value for bitfield CAN_IFLAG1_BUF5I. /
Kojto	90:cb3d968589d8	2303	#define BF_CAN_IFLAG1_BUF5I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF5I) & BM_CAN_IFLAG1_BUF5I)
Kojto	90:cb3d968589d8	2304
Kojto	90:cb3d968589d8	2305	/! @brief Set the BUF5I field to a new value. /
Kojto	90:cb3d968589d8	2306	#define BW_CAN_IFLAG1_BUF5I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF5I) = (v))
Kojto	90:cb3d968589d8	2307	/@}/
Kojto	90:cb3d968589d8	2308
Kojto	90:cb3d968589d8	2309	/*!
Kojto	90:cb3d968589d8	2310	* @name Register CAN_IFLAG1, field BUF6I[6] (W1C)
Kojto	90:cb3d968589d8	2311	*
Kojto	90:cb3d968589d8	2312	* When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
Kojto	90:cb3d968589d8	2313	* the interrupt for MB6. This flag is cleared by the FlexCAN whenever the bit
Kojto	90:cb3d968589d8	2314	* MCR[RFEN] is changed by CPU writes. The BUF6I flag represents "Rx FIFO Warning"
Kojto	90:cb3d968589d8	2315	* when MCR[RFEN] is set. In this case, the flag indicates when the number of
Kojto	90:cb3d968589d8	2316	* unread messages within the Rx FIFO is increased to 5 from 4 due to the reception of
Kojto	90:cb3d968589d8	2317	* a new one, meaning that the Rx FIFO is almost full. Note that if the flag is
Kojto	90:cb3d968589d8	2318	* cleared while the number of unread messages is greater than 4, it does not
Kojto	90:cb3d968589d8	2319	* assert again until the number of unread messages within the Rx FIFO is decreased
Kojto	90:cb3d968589d8	2320	* to be equal to or less than 4.
Kojto	90:cb3d968589d8	2321	*
Kojto	90:cb3d968589d8	2322	* Values:
Kojto	90:cb3d968589d8	2323	* - 0 - No occurrence of MB6 completing transmission/reception when
Kojto	90:cb3d968589d8	2324	* MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
Kojto	90:cb3d968589d8	2325	* - 1 - MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
Kojto	90:cb3d968589d8	2326	* almost full when MCR[RFEN]=1
Kojto	90:cb3d968589d8	2327	*/
Kojto	90:cb3d968589d8	2328	/@{/
Kojto	90:cb3d968589d8	2329	#define BP_CAN_IFLAG1_BUF6I (6U) /!< Bit position for CAN_IFLAG1_BUF6I. /
Kojto	90:cb3d968589d8	2330	#define BM_CAN_IFLAG1_BUF6I (0x00000040U) /!< Bit mask for CAN_IFLAG1_BUF6I. /
Kojto	90:cb3d968589d8	2331	#define BS_CAN_IFLAG1_BUF6I (1U) /!< Bit field size in bits for CAN_IFLAG1_BUF6I. /
Kojto	90:cb3d968589d8	2332
Kojto	90:cb3d968589d8	2333	/! @brief Read current value of the CAN_IFLAG1_BUF6I field. /
Kojto	90:cb3d968589d8	2334	#define BR_CAN_IFLAG1_BUF6I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF6I))
Kojto	90:cb3d968589d8	2335
Kojto	90:cb3d968589d8	2336	/! @brief Format value for bitfield CAN_IFLAG1_BUF6I. /
Kojto	90:cb3d968589d8	2337	#define BF_CAN_IFLAG1_BUF6I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF6I) & BM_CAN_IFLAG1_BUF6I)
Kojto	90:cb3d968589d8	2338
Kojto	90:cb3d968589d8	2339	/! @brief Set the BUF6I field to a new value. /
Kojto	90:cb3d968589d8	2340	#define BW_CAN_IFLAG1_BUF6I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF6I) = (v))
Kojto	90:cb3d968589d8	2341	/@}/
Kojto	90:cb3d968589d8	2342
Kojto	90:cb3d968589d8	2343	/*!
Kojto	90:cb3d968589d8	2344	* @name Register CAN_IFLAG1, field BUF7I[7] (W1C)
Kojto	90:cb3d968589d8	2345	*
Kojto	90:cb3d968589d8	2346	* When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
Kojto	90:cb3d968589d8	2347	* the interrupt for MB7. This flag is cleared by the FlexCAN whenever the bit
Kojto	90:cb3d968589d8	2348	* MCR[RFEN] is changed by CPU writes. The BUF7I flag represents "Rx FIFO Overflow"
Kojto	90:cb3d968589d8	2349	* when MCR[RFEN] is set. In this case, the flag indicates that a message was lost
Kojto	90:cb3d968589d8	2350	* because the Rx FIFO is full. Note that the flag will not be asserted when the
Kojto	90:cb3d968589d8	2351	* Rx FIFO is full and the message was captured by a Mailbox.
Kojto	90:cb3d968589d8	2352	*
Kojto	90:cb3d968589d8	2353	* Values:
Kojto	90:cb3d968589d8	2354	* - 0 - No occurrence of MB7 completing transmission/reception when
Kojto	90:cb3d968589d8	2355	* MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
Kojto	90:cb3d968589d8	2356	* - 1 - MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
Kojto	90:cb3d968589d8	2357	* overflow when MCR[RFEN]=1
Kojto	90:cb3d968589d8	2358	*/
Kojto	90:cb3d968589d8	2359	/@{/
Kojto	90:cb3d968589d8	2360	#define BP_CAN_IFLAG1_BUF7I (7U) /!< Bit position for CAN_IFLAG1_BUF7I. /
Kojto	90:cb3d968589d8	2361	#define BM_CAN_IFLAG1_BUF7I (0x00000080U) /!< Bit mask for CAN_IFLAG1_BUF7I. /
Kojto	90:cb3d968589d8	2362	#define BS_CAN_IFLAG1_BUF7I (1U) /!< Bit field size in bits for CAN_IFLAG1_BUF7I. /
Kojto	90:cb3d968589d8	2363
Kojto	90:cb3d968589d8	2364	/! @brief Read current value of the CAN_IFLAG1_BUF7I field. /
Kojto	90:cb3d968589d8	2365	#define BR_CAN_IFLAG1_BUF7I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF7I))
Kojto	90:cb3d968589d8	2366
Kojto	90:cb3d968589d8	2367	/! @brief Format value for bitfield CAN_IFLAG1_BUF7I. /
Kojto	90:cb3d968589d8	2368	#define BF_CAN_IFLAG1_BUF7I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF7I) & BM_CAN_IFLAG1_BUF7I)
Kojto	90:cb3d968589d8	2369
Kojto	90:cb3d968589d8	2370	/! @brief Set the BUF7I field to a new value. /
Kojto	90:cb3d968589d8	2371	#define BW_CAN_IFLAG1_BUF7I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF7I) = (v))
Kojto	90:cb3d968589d8	2372	/@}/
Kojto	90:cb3d968589d8	2373
Kojto	90:cb3d968589d8	2374	/*!
Kojto	90:cb3d968589d8	2375	* @name Register CAN_IFLAG1, field BUF31TO8I[31:8] (W1C)
Kojto	90:cb3d968589d8	2376	*
Kojto	90:cb3d968589d8	2377	* Each bit flags the corresponding FlexCAN Message Buffer interrupt for MB31 to
Kojto	90:cb3d968589d8	2378	* MB8.
Kojto	90:cb3d968589d8	2379	*
Kojto	90:cb3d968589d8	2380	* Values:
Kojto	90:cb3d968589d8	2381	* - 0 - The corresponding buffer has no occurrence of successfully completed
Kojto	90:cb3d968589d8	2382	* transmission or reception.
Kojto	90:cb3d968589d8	2383	* - 1 - The corresponding buffer has successfully completed transmission or
Kojto	90:cb3d968589d8	2384	* reception.
Kojto	90:cb3d968589d8	2385	*/
Kojto	90:cb3d968589d8	2386	/@{/
Kojto	90:cb3d968589d8	2387	#define BP_CAN_IFLAG1_BUF31TO8I (8U) /!< Bit position for CAN_IFLAG1_BUF31TO8I. /
Kojto	90:cb3d968589d8	2388	#define BM_CAN_IFLAG1_BUF31TO8I (0xFFFFFF00U) /!< Bit mask for CAN_IFLAG1_BUF31TO8I. /
Kojto	90:cb3d968589d8	2389	#define BS_CAN_IFLAG1_BUF31TO8I (24U) /!< Bit field size in bits for CAN_IFLAG1_BUF31TO8I. /
Kojto	90:cb3d968589d8	2390
Kojto	90:cb3d968589d8	2391	/! @brief Read current value of the CAN_IFLAG1_BUF31TO8I field. /
Kojto	90:cb3d968589d8	2392	#define BR_CAN_IFLAG1_BUF31TO8I(x) (HW_CAN_IFLAG1(x).B.BUF31TO8I)
Kojto	90:cb3d968589d8	2393
Kojto	90:cb3d968589d8	2394	/! @brief Format value for bitfield CAN_IFLAG1_BUF31TO8I. /
Kojto	90:cb3d968589d8	2395	#define BF_CAN_IFLAG1_BUF31TO8I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF31TO8I) & BM_CAN_IFLAG1_BUF31TO8I)
Kojto	90:cb3d968589d8	2396
Kojto	90:cb3d968589d8	2397	/! @brief Set the BUF31TO8I field to a new value. /
Kojto	90:cb3d968589d8	2398	#define BW_CAN_IFLAG1_BUF31TO8I(x, v) (HW_CAN_IFLAG1_WR(x, (HW_CAN_IFLAG1_RD(x) & ~BM_CAN_IFLAG1_BUF31TO8I) \| BF_CAN_IFLAG1_BUF31TO8I(v)))
Kojto	90:cb3d968589d8	2399	/@}/
Kojto	90:cb3d968589d8	2400
Kojto	90:cb3d968589d8	2401	/*******************************************************************************
Kojto	90:cb3d968589d8	2402	* HW_CAN_CTRL2 - Control 2 register
Kojto	90:cb3d968589d8	2403	******************************************************************************/
Kojto	90:cb3d968589d8	2404
Kojto	90:cb3d968589d8	2405	/*!
Kojto	90:cb3d968589d8	2406	* @brief HW_CAN_CTRL2 - Control 2 register (RW)
Kojto	90:cb3d968589d8	2407	*
Kojto	90:cb3d968589d8	2408	* Reset value: 0x00B00000U
Kojto	90:cb3d968589d8	2409	*
Kojto	90:cb3d968589d8	2410	* This register contains control bits for CAN errors, FIFO features, and mode
Kojto	90:cb3d968589d8	2411	* selection.
Kojto	90:cb3d968589d8	2412	*/
Kojto	90:cb3d968589d8	2413	typedef union _hw_can_ctrl2
Kojto	90:cb3d968589d8	2414	{
Kojto	90:cb3d968589d8	2415	uint32_t U;
Kojto	90:cb3d968589d8	2416	struct _hw_can_ctrl2_bitfields
Kojto	90:cb3d968589d8	2417	{
Kojto	90:cb3d968589d8	2418	uint32_t RESERVED0 : 16; /!< [15:0] /
Kojto	90:cb3d968589d8	2419	uint32_t EACEN : 1; /*!< [16] Entire Frame Arbitration Field
Kojto	90:cb3d968589d8	2420	* Comparison Enable For Rx Mailboxes */
Kojto	90:cb3d968589d8	2421	uint32_t RRS : 1; /!< [17] Remote Request Storing /
Kojto	90:cb3d968589d8	2422	uint32_t MRP : 1; /!< [18] Mailboxes Reception Priority /
Kojto	90:cb3d968589d8	2423	uint32_t TASD : 5; /!< [23:19] Tx Arbitration Start Delay /
Kojto	90:cb3d968589d8	2424	uint32_t RFFN : 4; /!< [27:24] Number Of Rx FIFO Filters /
Kojto	90:cb3d968589d8	2425	uint32_t WRMFRZ : 1; /*!< [28] Write-Access To Memory In Freeze Mode
Kojto	90:cb3d968589d8	2426	* */
Kojto	90:cb3d968589d8	2427	uint32_t RESERVED1 : 3; /!< [31:29] /
Kojto	90:cb3d968589d8	2428	} B;
Kojto	90:cb3d968589d8	2429	} hw_can_ctrl2_t;
Kojto	90:cb3d968589d8	2430
Kojto	90:cb3d968589d8	2431	/*!
Kojto	90:cb3d968589d8	2432	* @name Constants and macros for entire CAN_CTRL2 register
Kojto	90:cb3d968589d8	2433	*/
Kojto	90:cb3d968589d8	2434	/@{/
Kojto	90:cb3d968589d8	2435	#define HW_CAN_CTRL2_ADDR(x) ((x) + 0x34U)
Kojto	90:cb3d968589d8	2436
Kojto	90:cb3d968589d8	2437	#define HW_CAN_CTRL2(x) ((__IO hw_can_ctrl2_t ) HW_CAN_CTRL2_ADDR(x))
Kojto	90:cb3d968589d8	2438	#define HW_CAN_CTRL2_RD(x) (HW_CAN_CTRL2(x).U)
Kojto	90:cb3d968589d8	2439	#define HW_CAN_CTRL2_WR(x, v) (HW_CAN_CTRL2(x).U = (v))
Kojto	90:cb3d968589d8	2440	#define HW_CAN_CTRL2_SET(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2441	#define HW_CAN_CTRL2_CLR(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2442	#define HW_CAN_CTRL2_TOG(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2443	/@}/
Kojto	90:cb3d968589d8	2444
Kojto	90:cb3d968589d8	2445	/*
Kojto	90:cb3d968589d8	2446	* Constants & macros for individual CAN_CTRL2 bitfields
Kojto	90:cb3d968589d8	2447	*/
Kojto	90:cb3d968589d8	2448
Kojto	90:cb3d968589d8	2449	/*!
Kojto	90:cb3d968589d8	2450	* @name Register CAN_CTRL2, field EACEN[16] (RW)
Kojto	90:cb3d968589d8	2451	*
Kojto	90:cb3d968589d8	2452	* This bit controls the comparison of IDE and RTR bits whithin Rx Mailboxes
Kojto	90:cb3d968589d8	2453	* filters with their corresponding bits in the incoming frame by the matching
Kojto	90:cb3d968589d8	2454	* process. This bit does not affect matching for Rx FIFO. This bit can be written
Kojto	90:cb3d968589d8	2455	* only in Freeze mode because it is blocked by hardware in other modes.
Kojto	90:cb3d968589d8	2456	*
Kojto	90:cb3d968589d8	2457	* Values:
Kojto	90:cb3d968589d8	2458	* - 0 - Rx Mailbox filter's IDE bit is always compared and RTR is never
Kojto	90:cb3d968589d8	2459	* compared despite mask bits.
Kojto	90:cb3d968589d8	2460	* - 1 - Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with
Kojto	90:cb3d968589d8	2461	* their corresponding bits within the incoming frame. Mask bits do apply.
Kojto	90:cb3d968589d8	2462	*/
Kojto	90:cb3d968589d8	2463	/@{/
Kojto	90:cb3d968589d8	2464	#define BP_CAN_CTRL2_EACEN (16U) /!< Bit position for CAN_CTRL2_EACEN. /
Kojto	90:cb3d968589d8	2465	#define BM_CAN_CTRL2_EACEN (0x00010000U) /!< Bit mask for CAN_CTRL2_EACEN. /
Kojto	90:cb3d968589d8	2466	#define BS_CAN_CTRL2_EACEN (1U) /!< Bit field size in bits for CAN_CTRL2_EACEN. /
Kojto	90:cb3d968589d8	2467
Kojto	90:cb3d968589d8	2468	/! @brief Read current value of the CAN_CTRL2_EACEN field. /
Kojto	90:cb3d968589d8	2469	#define BR_CAN_CTRL2_EACEN(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_EACEN))
Kojto	90:cb3d968589d8	2470
Kojto	90:cb3d968589d8	2471	/! @brief Format value for bitfield CAN_CTRL2_EACEN. /
Kojto	90:cb3d968589d8	2472	#define BF_CAN_CTRL2_EACEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_EACEN) & BM_CAN_CTRL2_EACEN)
Kojto	90:cb3d968589d8	2473
Kojto	90:cb3d968589d8	2474	/! @brief Set the EACEN field to a new value. /
Kojto	90:cb3d968589d8	2475	#define BW_CAN_CTRL2_EACEN(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_EACEN) = (v))
Kojto	90:cb3d968589d8	2476	/@}/
Kojto	90:cb3d968589d8	2477
Kojto	90:cb3d968589d8	2478	/*!
Kojto	90:cb3d968589d8	2479	* @name Register CAN_CTRL2, field RRS[17] (RW)
Kojto	90:cb3d968589d8	2480	*
Kojto	90:cb3d968589d8	2481	* If this bit is asserted Remote Request Frame is submitted to a matching
Kojto	90:cb3d968589d8	2482	* process and stored in the corresponding Message Buffer in the same fashion of a
Kojto	90:cb3d968589d8	2483	* Data Frame. No automatic Remote Response Frame will be generated. If this bit is
Kojto	90:cb3d968589d8	2484	* negated the Remote Request Frame is submitted to a matching process and an
Kojto	90:cb3d968589d8	2485	* automatic Remote Response Frame is generated if a Message Buffer with CODE=0b1010
Kojto	90:cb3d968589d8	2486	* is found with the same ID. This bit can be written only in Freeze mode
Kojto	90:cb3d968589d8	2487	* because it is blocked by hardware in other modes.
Kojto	90:cb3d968589d8	2488	*
Kojto	90:cb3d968589d8	2489	* Values:
Kojto	90:cb3d968589d8	2490	* - 0 - Remote Response Frame is generated.
Kojto	90:cb3d968589d8	2491	* - 1 - Remote Request Frame is stored.
Kojto	90:cb3d968589d8	2492	*/
Kojto	90:cb3d968589d8	2493	/@{/
Kojto	90:cb3d968589d8	2494	#define BP_CAN_CTRL2_RRS (17U) /!< Bit position for CAN_CTRL2_RRS. /
Kojto	90:cb3d968589d8	2495	#define BM_CAN_CTRL2_RRS (0x00020000U) /!< Bit mask for CAN_CTRL2_RRS. /
Kojto	90:cb3d968589d8	2496	#define BS_CAN_CTRL2_RRS (1U) /!< Bit field size in bits for CAN_CTRL2_RRS. /
Kojto	90:cb3d968589d8	2497
Kojto	90:cb3d968589d8	2498	/! @brief Read current value of the CAN_CTRL2_RRS field. /
Kojto	90:cb3d968589d8	2499	#define BR_CAN_CTRL2_RRS(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_RRS))
Kojto	90:cb3d968589d8	2500
Kojto	90:cb3d968589d8	2501	/! @brief Format value for bitfield CAN_CTRL2_RRS. /
Kojto	90:cb3d968589d8	2502	#define BF_CAN_CTRL2_RRS(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_RRS) & BM_CAN_CTRL2_RRS)
Kojto	90:cb3d968589d8	2503
Kojto	90:cb3d968589d8	2504	/! @brief Set the RRS field to a new value. /
Kojto	90:cb3d968589d8	2505	#define BW_CAN_CTRL2_RRS(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_RRS) = (v))
Kojto	90:cb3d968589d8	2506	/@}/
Kojto	90:cb3d968589d8	2507
Kojto	90:cb3d968589d8	2508	/*!
Kojto	90:cb3d968589d8	2509	* @name Register CAN_CTRL2, field MRP[18] (RW)
Kojto	90:cb3d968589d8	2510	*
Kojto	90:cb3d968589d8	2511	* If this bit is set the matching process starts from the Mailboxes and if no
Kojto	90:cb3d968589d8	2512	* match occurs the matching continues on the Rx FIFO. This bit can be written
Kojto	90:cb3d968589d8	2513	* only in Freeze mode because it is blocked by hardware in other modes.
Kojto	90:cb3d968589d8	2514	*
Kojto	90:cb3d968589d8	2515	* Values:
Kojto	90:cb3d968589d8	2516	* - 0 - Matching starts from Rx FIFO and continues on Mailboxes.
Kojto	90:cb3d968589d8	2517	* - 1 - Matching starts from Mailboxes and continues on Rx FIFO.
Kojto	90:cb3d968589d8	2518	*/
Kojto	90:cb3d968589d8	2519	/@{/
Kojto	90:cb3d968589d8	2520	#define BP_CAN_CTRL2_MRP (18U) /!< Bit position for CAN_CTRL2_MRP. /
Kojto	90:cb3d968589d8	2521	#define BM_CAN_CTRL2_MRP (0x00040000U) /!< Bit mask for CAN_CTRL2_MRP. /
Kojto	90:cb3d968589d8	2522	#define BS_CAN_CTRL2_MRP (1U) /!< Bit field size in bits for CAN_CTRL2_MRP. /
Kojto	90:cb3d968589d8	2523
Kojto	90:cb3d968589d8	2524	/! @brief Read current value of the CAN_CTRL2_MRP field. /
Kojto	90:cb3d968589d8	2525	#define BR_CAN_CTRL2_MRP(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_MRP))
Kojto	90:cb3d968589d8	2526
Kojto	90:cb3d968589d8	2527	/! @brief Format value for bitfield CAN_CTRL2_MRP. /
Kojto	90:cb3d968589d8	2528	#define BF_CAN_CTRL2_MRP(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_MRP) & BM_CAN_CTRL2_MRP)
Kojto	90:cb3d968589d8	2529
Kojto	90:cb3d968589d8	2530	/! @brief Set the MRP field to a new value. /
Kojto	90:cb3d968589d8	2531	#define BW_CAN_CTRL2_MRP(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_MRP) = (v))
Kojto	90:cb3d968589d8	2532	/@}/
Kojto	90:cb3d968589d8	2533
Kojto	90:cb3d968589d8	2534	/*!
Kojto	90:cb3d968589d8	2535	* @name Register CAN_CTRL2, field TASD[23:19] (RW)
Kojto	90:cb3d968589d8	2536	*
Kojto	90:cb3d968589d8	2537	* This 5-bit field indicates how many CAN bits the Tx arbitration process start
Kojto	90:cb3d968589d8	2538	* point can be delayed from the first bit of CRC field on CAN bus. This field
Kojto	90:cb3d968589d8	2539	* can be written only in Freeze mode because it is blocked by hardware in other
Kojto	90:cb3d968589d8	2540	* modes. This field is useful to optimize the transmit performance based on
Kojto	90:cb3d968589d8	2541	* factors such as: peripheral/serial clock ratio, CAN bit timing and number of MBs.
Kojto	90:cb3d968589d8	2542	* The duration of an arbitration process, in terms of CAN bits, is directly
Kojto	90:cb3d968589d8	2543	* proportional to the number of available MBs and CAN baud rate and inversely
Kojto	90:cb3d968589d8	2544	* proportional to the peripheral clock frequency. The optimal arbitration timing is
Kojto	90:cb3d968589d8	2545	* that in which the last MB is scanned right before the first bit of the
Kojto	90:cb3d968589d8	2546	* Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial
Kojto	90:cb3d968589d8	2547	* clock ratio is high and the CAN baud rate is low then the arbitration can be
Kojto	90:cb3d968589d8	2548	* delayed and vice-versa. If TASD is 0 then the arbitration start is not
Kojto	90:cb3d968589d8	2549	* delayed, thus the CPU has less time to configure a Tx MB for the next arbitration,
Kojto	90:cb3d968589d8	2550	* but more time is reserved for arbitration. On the other hand, if TASD is 24 then
Kojto	90:cb3d968589d8	2551	* the CPU can configure a Tx MB later and less time is reserved for
Kojto	90:cb3d968589d8	2552	* arbitration. If too little time is reserved for arbitration the FlexCAN may be not able
Kojto	90:cb3d968589d8	2553	* to find winner MBs in time to compete with other nodes for the CAN bus. If the
Kojto	90:cb3d968589d8	2554	* arbitration ends too much time before the first bit of Intermission field then
Kojto	90:cb3d968589d8	2555	* there is a chance that the CPU reconfigures some Tx MBs and the winner MB is
Kojto	90:cb3d968589d8	2556	* not the best to be transmitted. The optimal configuration for TASD can be
Kojto	90:cb3d968589d8	2557	* calculated as: TASD = 25 - {f CANCLK * [MAXMB + 3 - (RFEN * 8) - (RFEN * RFFN *
Kojto	90:cb3d968589d8	2558	* 2)] * 2} / {f SYS * [1+(PSEG1+1)+(PSEG2+1)+(PROPSEG+1)] * (PRESDIV+1)} where: f
Kojto	90:cb3d968589d8	2559	* CANCLK is the Protocol Engine (PE) Clock (see section "Protocol Timing"), in
Kojto	90:cb3d968589d8	2560	* Hz f SYS is the peripheral clock, in Hz MAXMB is the value in CTRL1[MAXMB]
Kojto	90:cb3d968589d8	2561	* field RFEN is the value in CTRL1[RFEN] bit RFFN is the value in CTRL2[RFFN] field
Kojto	90:cb3d968589d8	2562	* PSEG1 is the value in CTRL1[PSEG1] field PSEG2 is the value in CTRL1[PSEG2]
Kojto	90:cb3d968589d8	2563	* field PROPSEG is the value in CTRL1[PROPSEG] field PRESDIV is the value in
Kojto	90:cb3d968589d8	2564	* CTRL1[PRESDIV] field See Section "Arbitration process" and Section "Protocol
Kojto	90:cb3d968589d8	2565	* Timing" for more details.
Kojto	90:cb3d968589d8	2566	*/
Kojto	90:cb3d968589d8	2567	/@{/
Kojto	90:cb3d968589d8	2568	#define BP_CAN_CTRL2_TASD (19U) /!< Bit position for CAN_CTRL2_TASD. /
Kojto	90:cb3d968589d8	2569	#define BM_CAN_CTRL2_TASD (0x00F80000U) /!< Bit mask for CAN_CTRL2_TASD. /
Kojto	90:cb3d968589d8	2570	#define BS_CAN_CTRL2_TASD (5U) /!< Bit field size in bits for CAN_CTRL2_TASD. /
Kojto	90:cb3d968589d8	2571
Kojto	90:cb3d968589d8	2572	/! @brief Read current value of the CAN_CTRL2_TASD field. /
Kojto	90:cb3d968589d8	2573	#define BR_CAN_CTRL2_TASD(x) (HW_CAN_CTRL2(x).B.TASD)
Kojto	90:cb3d968589d8	2574
Kojto	90:cb3d968589d8	2575	/! @brief Format value for bitfield CAN_CTRL2_TASD. /
Kojto	90:cb3d968589d8	2576	#define BF_CAN_CTRL2_TASD(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_TASD) & BM_CAN_CTRL2_TASD)
Kojto	90:cb3d968589d8	2577
Kojto	90:cb3d968589d8	2578	/! @brief Set the TASD field to a new value. /
Kojto	90:cb3d968589d8	2579	#define BW_CAN_CTRL2_TASD(x, v) (HW_CAN_CTRL2_WR(x, (HW_CAN_CTRL2_RD(x) & ~BM_CAN_CTRL2_TASD) \| BF_CAN_CTRL2_TASD(v)))
Kojto	90:cb3d968589d8	2580	/@}/
Kojto	90:cb3d968589d8	2581
Kojto	90:cb3d968589d8	2582	/*!
Kojto	90:cb3d968589d8	2583	* @name Register CAN_CTRL2, field RFFN[27:24] (RW)
Kojto	90:cb3d968589d8	2584	*
Kojto	90:cb3d968589d8	2585	* This 4-bit field defines the number of Rx FIFO filters, as shown in the
Kojto	90:cb3d968589d8	2586	* following table. The maximum selectable number of filters is determined by the MCU.
Kojto	90:cb3d968589d8	2587	* This field can only be written in Freeze mode as it is blocked by hardware in
Kojto	90:cb3d968589d8	2588	* other modes. This field must not be programmed with values that make the
Kojto	90:cb3d968589d8	2589	* number of Message Buffers occupied by Rx FIFO and ID Filter exceed the number of
Kojto	90:cb3d968589d8	2590	* Mailboxes present, defined by MCR[MAXMB]. Each group of eight filters occupies
Kojto	90:cb3d968589d8	2591	* a memory space equivalent to two Message Buffers which means that the more
Kojto	90:cb3d968589d8	2592	* filters are implemented the less Mailboxes will be available. Considering that
Kojto	90:cb3d968589d8	2593	* the Rx FIFO occupies the memory space originally reserved for MB0-5, RFFN should
Kojto	90:cb3d968589d8	2594	* be programmed with a value correponding to a number of filters not greater
Kojto	90:cb3d968589d8	2595	* than the number of available memory words which can be calculated as follows:
Kojto	90:cb3d968589d8	2596	* (SETUP_MB - 6) * 4 where SETUP_MB is the least between NUMBER_OF_MB and MAXMB.
Kojto	90:cb3d968589d8	2597	* The number of remaining Mailboxes available will be: (SETUP_MB - 8) - (RFFN *
Kojto	90:cb3d968589d8	2598	* 2) If the Number of Rx FIFO Filters programmed through RFFN exceeds the
Kojto	90:cb3d968589d8	2599	* SETUP_MB value (memory space available) the exceeding ones will not be functional.
Kojto	90:cb3d968589d8	2600	* RFFN[3:0] Number of Rx FIFO filters Message Buffers occupied by Rx FIFO and ID
Kojto	90:cb3d968589d8	2601	* Filter Table Remaining Available MailboxesThe number of the last remaining
Kojto	90:cb3d968589d8	2602	* available mailboxes is defined by the least value between the parameter
Kojto	90:cb3d968589d8	2603	* NUMBER_OF_MB minus 1 and the MCR[MAXMB] field. Rx FIFO ID Filter Table Elements Affected
Kojto	90:cb3d968589d8	2604	* by Rx Individual MasksIf Rx Individual Mask Registers are not enabled then
Kojto	90:cb3d968589d8	2605	* all Rx FIFO filters are affected by the Rx FIFO Global Mask. Rx FIFO ID Filter
Kojto	90:cb3d968589d8	2606	* Table Elements Affected by Rx FIFO Global Mask #rxfgmask-note 0x0 8 MB 0-7 MB
Kojto	90:cb3d968589d8	2607	* 8-63 Elements 0-7 none 0x1 16 MB 0-9 MB 10-63 Elements 0-9 Elements 10-15 0x2
Kojto	90:cb3d968589d8	2608	* 24 MB 0-11 MB 12-63 Elements 0-11 Elements 12-23 0x3 32 MB 0-13 MB 14-63
Kojto	90:cb3d968589d8	2609	* Elements 0-13 Elements 14-31 0x4 40 MB 0-15 MB 16-63 Elements 0-15 Elements 16-39
Kojto	90:cb3d968589d8	2610	* 0x5 48 MB 0-17 MB 18-63 Elements 0-17 Elements 18-47 0x6 56 MB 0-19 MB 20-63
Kojto	90:cb3d968589d8	2611	* Elements 0-19 Elements 20-55 0x7 64 MB 0-21 MB 22-63 Elements 0-21 Elements 22-63
Kojto	90:cb3d968589d8	2612	* 0x8 72 MB 0-23 MB 24-63 Elements 0-23 Elements 24-71 0x9 80 MB 0-25 MB 26-63
Kojto	90:cb3d968589d8	2613	* Elements 0-25 Elements 26-79 0xA 88 MB 0-27 MB 28-63 Elements 0-27 Elements
Kojto	90:cb3d968589d8	2614	* 28-87 0xB 96 MB 0-29 MB 30-63 Elements 0-29 Elements 30-95 0xC 104 MB 0-31 MB
Kojto	90:cb3d968589d8	2615	* 32-63 Elements 0-31 Elements 32-103 0xD 112 MB 0-33 MB 34-63 Elements 0-31
Kojto	90:cb3d968589d8	2616	* Elements 32-111 0xE 120 MB 0-35 MB 36-63 Elements 0-31 Elements 32-119 0xF 128 MB
Kojto	90:cb3d968589d8	2617	* 0-37 MB 38-63 Elements 0-31 Elements 32-127
Kojto	90:cb3d968589d8	2618	*/
Kojto	90:cb3d968589d8	2619	/@{/
Kojto	90:cb3d968589d8	2620	#define BP_CAN_CTRL2_RFFN (24U) /!< Bit position for CAN_CTRL2_RFFN. /
Kojto	90:cb3d968589d8	2621	#define BM_CAN_CTRL2_RFFN (0x0F000000U) /!< Bit mask for CAN_CTRL2_RFFN. /
Kojto	90:cb3d968589d8	2622	#define BS_CAN_CTRL2_RFFN (4U) /!< Bit field size in bits for CAN_CTRL2_RFFN. /
Kojto	90:cb3d968589d8	2623
Kojto	90:cb3d968589d8	2624	/! @brief Read current value of the CAN_CTRL2_RFFN field. /
Kojto	90:cb3d968589d8	2625	#define BR_CAN_CTRL2_RFFN(x) (HW_CAN_CTRL2(x).B.RFFN)
Kojto	90:cb3d968589d8	2626
Kojto	90:cb3d968589d8	2627	/! @brief Format value for bitfield CAN_CTRL2_RFFN. /
Kojto	90:cb3d968589d8	2628	#define BF_CAN_CTRL2_RFFN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_RFFN) & BM_CAN_CTRL2_RFFN)
Kojto	90:cb3d968589d8	2629
Kojto	90:cb3d968589d8	2630	/! @brief Set the RFFN field to a new value. /
Kojto	90:cb3d968589d8	2631	#define BW_CAN_CTRL2_RFFN(x, v) (HW_CAN_CTRL2_WR(x, (HW_CAN_CTRL2_RD(x) & ~BM_CAN_CTRL2_RFFN) \| BF_CAN_CTRL2_RFFN(v)))
Kojto	90:cb3d968589d8	2632	/@}/
Kojto	90:cb3d968589d8	2633
Kojto	90:cb3d968589d8	2634	/*!
Kojto	90:cb3d968589d8	2635	* @name Register CAN_CTRL2, field WRMFRZ[28] (RW)
Kojto	90:cb3d968589d8	2636	*
Kojto	90:cb3d968589d8	2637	* Enable unrestricted write access to FlexCAN memory in Freeze mode. This bit
Kojto	90:cb3d968589d8	2638	* can only be written in Freeze mode and has no effect out of Freeze mode.
Kojto	90:cb3d968589d8	2639	*
Kojto	90:cb3d968589d8	2640	* Values:
Kojto	90:cb3d968589d8	2641	* - 0 - Maintain the write access restrictions.
Kojto	90:cb3d968589d8	2642	* - 1 - Enable unrestricted write access to FlexCAN memory.
Kojto	90:cb3d968589d8	2643	*/
Kojto	90:cb3d968589d8	2644	/@{/
Kojto	90:cb3d968589d8	2645	#define BP_CAN_CTRL2_WRMFRZ (28U) /!< Bit position for CAN_CTRL2_WRMFRZ. /
Kojto	90:cb3d968589d8	2646	#define BM_CAN_CTRL2_WRMFRZ (0x10000000U) /!< Bit mask for CAN_CTRL2_WRMFRZ. /
Kojto	90:cb3d968589d8	2647	#define BS_CAN_CTRL2_WRMFRZ (1U) /!< Bit field size in bits for CAN_CTRL2_WRMFRZ. /
Kojto	90:cb3d968589d8	2648
Kojto	90:cb3d968589d8	2649	/! @brief Read current value of the CAN_CTRL2_WRMFRZ field. /
Kojto	90:cb3d968589d8	2650	#define BR_CAN_CTRL2_WRMFRZ(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_WRMFRZ))
Kojto	90:cb3d968589d8	2651
Kojto	90:cb3d968589d8	2652	/! @brief Format value for bitfield CAN_CTRL2_WRMFRZ. /
Kojto	90:cb3d968589d8	2653	#define BF_CAN_CTRL2_WRMFRZ(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_WRMFRZ) & BM_CAN_CTRL2_WRMFRZ)
Kojto	90:cb3d968589d8	2654
Kojto	90:cb3d968589d8	2655	/! @brief Set the WRMFRZ field to a new value. /
Kojto	90:cb3d968589d8	2656	#define BW_CAN_CTRL2_WRMFRZ(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_WRMFRZ) = (v))
Kojto	90:cb3d968589d8	2657	/@}/
Kojto	90:cb3d968589d8	2658
Kojto	90:cb3d968589d8	2659	/*******************************************************************************
Kojto	90:cb3d968589d8	2660	* HW_CAN_ESR2 - Error and Status 2 register
Kojto	90:cb3d968589d8	2661	******************************************************************************/
Kojto	90:cb3d968589d8	2662
Kojto	90:cb3d968589d8	2663	/*!
Kojto	90:cb3d968589d8	2664	* @brief HW_CAN_ESR2 - Error and Status 2 register (RO)
Kojto	90:cb3d968589d8	2665	*
Kojto	90:cb3d968589d8	2666	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2667	*
Kojto	90:cb3d968589d8	2668	* This register reflects various interrupt flags and some general status.
Kojto	90:cb3d968589d8	2669	*/
Kojto	90:cb3d968589d8	2670	typedef union _hw_can_esr2
Kojto	90:cb3d968589d8	2671	{
Kojto	90:cb3d968589d8	2672	uint32_t U;
Kojto	90:cb3d968589d8	2673	struct _hw_can_esr2_bitfields
Kojto	90:cb3d968589d8	2674	{
Kojto	90:cb3d968589d8	2675	uint32_t RESERVED0 : 13; /!< [12:0] /
Kojto	90:cb3d968589d8	2676	uint32_t IMB : 1; /!< [13] Inactive Mailbox /
Kojto	90:cb3d968589d8	2677	uint32_t VPS : 1; /!< [14] Valid Priority Status /
Kojto	90:cb3d968589d8	2678	uint32_t RESERVED1 : 1; /!< [15] /
Kojto	90:cb3d968589d8	2679	uint32_t LPTM : 7; /!< [22:16] Lowest Priority Tx Mailbox /
Kojto	90:cb3d968589d8	2680	uint32_t RESERVED2 : 9; /!< [31:23] /
Kojto	90:cb3d968589d8	2681	} B;
Kojto	90:cb3d968589d8	2682	} hw_can_esr2_t;
Kojto	90:cb3d968589d8	2683
Kojto	90:cb3d968589d8	2684	/*!
Kojto	90:cb3d968589d8	2685	* @name Constants and macros for entire CAN_ESR2 register
Kojto	90:cb3d968589d8	2686	*/
Kojto	90:cb3d968589d8	2687	/@{/
Kojto	90:cb3d968589d8	2688	#define HW_CAN_ESR2_ADDR(x) ((x) + 0x38U)
Kojto	90:cb3d968589d8	2689
Kojto	90:cb3d968589d8	2690	#define HW_CAN_ESR2(x) ((__I hw_can_esr2_t ) HW_CAN_ESR2_ADDR(x))
Kojto	90:cb3d968589d8	2691	#define HW_CAN_ESR2_RD(x) (HW_CAN_ESR2(x).U)
Kojto	90:cb3d968589d8	2692	/@}/
Kojto	90:cb3d968589d8	2693
Kojto	90:cb3d968589d8	2694	/*
Kojto	90:cb3d968589d8	2695	* Constants & macros for individual CAN_ESR2 bitfields
Kojto	90:cb3d968589d8	2696	*/
Kojto	90:cb3d968589d8	2697
Kojto	90:cb3d968589d8	2698	/*!
Kojto	90:cb3d968589d8	2699	* @name Register CAN_ESR2, field IMB[13] (RO)
Kojto	90:cb3d968589d8	2700	*
Kojto	90:cb3d968589d8	2701	* If ESR2[VPS] is asserted, this bit indicates whether there is any inactive
Kojto	90:cb3d968589d8	2702	* Mailbox (CODE field is either 0b1000 or 0b0000). This bit is asserted in the
Kojto	90:cb3d968589d8	2703	* following cases: During arbitration, if an LPTM is found and it is inactive. If
Kojto	90:cb3d968589d8	2704	* IMB is not asserted and a frame is transmitted successfully. This bit is
Kojto	90:cb3d968589d8	2705	* cleared in all start of arbitration (see Section "Arbitration process"). LPTM
Kojto	90:cb3d968589d8	2706	* mechanism have the following behavior: if an MB is successfully transmitted and
Kojto	90:cb3d968589d8	2707	* ESR2[IMB]=0 (no inactive Mailbox), then ESR2[VPS] and ESR2[IMB] are asserted and
Kojto	90:cb3d968589d8	2708	* the index related to the MB just transmitted is loaded into ESR2[LPTM].
Kojto	90:cb3d968589d8	2709	*
Kojto	90:cb3d968589d8	2710	* Values:
Kojto	90:cb3d968589d8	2711	* - 0 - If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
Kojto	90:cb3d968589d8	2712	* - 1 - If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM
Kojto	90:cb3d968589d8	2713	* content is the number of the first one.
Kojto	90:cb3d968589d8	2714	*/
Kojto	90:cb3d968589d8	2715	/@{/
Kojto	90:cb3d968589d8	2716	#define BP_CAN_ESR2_IMB (13U) /!< Bit position for CAN_ESR2_IMB. /
Kojto	90:cb3d968589d8	2717	#define BM_CAN_ESR2_IMB (0x00002000U) /!< Bit mask for CAN_ESR2_IMB. /
Kojto	90:cb3d968589d8	2718	#define BS_CAN_ESR2_IMB (1U) /!< Bit field size in bits for CAN_ESR2_IMB. /
Kojto	90:cb3d968589d8	2719
Kojto	90:cb3d968589d8	2720	/! @brief Read current value of the CAN_ESR2_IMB field. /
Kojto	90:cb3d968589d8	2721	#define BR_CAN_ESR2_IMB(x) (BITBAND_ACCESS32(HW_CAN_ESR2_ADDR(x), BP_CAN_ESR2_IMB))
Kojto	90:cb3d968589d8	2722	/@}/
Kojto	90:cb3d968589d8	2723
Kojto	90:cb3d968589d8	2724	/*!
Kojto	90:cb3d968589d8	2725	* @name Register CAN_ESR2, field VPS[14] (RO)
Kojto	90:cb3d968589d8	2726	*
Kojto	90:cb3d968589d8	2727	* This bit indicates whether IMB and LPTM contents are currently valid or not.
Kojto	90:cb3d968589d8	2728	* VPS is asserted upon every complete Tx arbitration process unless the CPU
Kojto	90:cb3d968589d8	2729	* writes to Control and Status word of a Mailbox that has already been scanned, that
Kojto	90:cb3d968589d8	2730	* is, it is behind Tx Arbitration Pointer, during the Tx arbitration process.
Kojto	90:cb3d968589d8	2731	* If there is no inactive Mailbox and only one Tx Mailbox that is being
Kojto	90:cb3d968589d8	2732	* transmitted then VPS is not asserted. VPS is negated upon the start of every Tx
Kojto	90:cb3d968589d8	2733	* arbitration process or upon a write to Control and Status word of any Mailbox.
Kojto	90:cb3d968589d8	2734	* ESR2[VPS] is not affected by any CPU write into Control Status (C/S) of a MB that is
Kojto	90:cb3d968589d8	2735	* blocked by abort mechanism. When MCR[AEN] is asserted, the abort code write
Kojto	90:cb3d968589d8	2736	* in C/S of a MB that is being transmitted (pending abort), or any write attempt
Kojto	90:cb3d968589d8	2737	* into a Tx MB with IFLAG set is blocked.
Kojto	90:cb3d968589d8	2738	*
Kojto	90:cb3d968589d8	2739	* Values:
Kojto	90:cb3d968589d8	2740	* - 0 - Contents of IMB and LPTM are invalid.
Kojto	90:cb3d968589d8	2741	* - 1 - Contents of IMB and LPTM are valid.
Kojto	90:cb3d968589d8	2742	*/
Kojto	90:cb3d968589d8	2743	/@{/
Kojto	90:cb3d968589d8	2744	#define BP_CAN_ESR2_VPS (14U) /!< Bit position for CAN_ESR2_VPS. /
Kojto	90:cb3d968589d8	2745	#define BM_CAN_ESR2_VPS (0x00004000U) /!< Bit mask for CAN_ESR2_VPS. /
Kojto	90:cb3d968589d8	2746	#define BS_CAN_ESR2_VPS (1U) /!< Bit field size in bits for CAN_ESR2_VPS. /
Kojto	90:cb3d968589d8	2747
Kojto	90:cb3d968589d8	2748	/! @brief Read current value of the CAN_ESR2_VPS field. /
Kojto	90:cb3d968589d8	2749	#define BR_CAN_ESR2_VPS(x) (BITBAND_ACCESS32(HW_CAN_ESR2_ADDR(x), BP_CAN_ESR2_VPS))
Kojto	90:cb3d968589d8	2750	/@}/
Kojto	90:cb3d968589d8	2751
Kojto	90:cb3d968589d8	2752	/*!
Kojto	90:cb3d968589d8	2753	* @name Register CAN_ESR2, field LPTM[22:16] (RO)
Kojto	90:cb3d968589d8	2754	*
Kojto	90:cb3d968589d8	2755	* If ESR2[VPS] is asserted, this field indicates the lowest number inactive
Kojto	90:cb3d968589d8	2756	* Mailbox (see the IMB bit description). If there is no inactive Mailbox then the
Kojto	90:cb3d968589d8	2757	* Mailbox indicated depends on CTRL1[LBUF] bit value. If CTRL1[LBUF] bit is
Kojto	90:cb3d968589d8	2758	* negated then the Mailbox indicated is the one that has the greatest arbitration
Kojto	90:cb3d968589d8	2759	* value (see the "Highest priority Mailbox first" section). If CTRL1[LBUF] bit is
Kojto	90:cb3d968589d8	2760	* asserted then the Mailbox indicated is the highest number active Tx Mailbox. If
Kojto	90:cb3d968589d8	2761	* a Tx Mailbox is being transmitted it is not considered in LPTM calculation.
Kojto	90:cb3d968589d8	2762	* If ESR2[IMB] is not asserted and a frame is transmitted successfully, LPTM is
Kojto	90:cb3d968589d8	2763	* updated with its Mailbox number.
Kojto	90:cb3d968589d8	2764	*/
Kojto	90:cb3d968589d8	2765	/@{/
Kojto	90:cb3d968589d8	2766	#define BP_CAN_ESR2_LPTM (16U) /!< Bit position for CAN_ESR2_LPTM. /
Kojto	90:cb3d968589d8	2767	#define BM_CAN_ESR2_LPTM (0x007F0000U) /!< Bit mask for CAN_ESR2_LPTM. /
Kojto	90:cb3d968589d8	2768	#define BS_CAN_ESR2_LPTM (7U) /!< Bit field size in bits for CAN_ESR2_LPTM. /
Kojto	90:cb3d968589d8	2769
Kojto	90:cb3d968589d8	2770	/! @brief Read current value of the CAN_ESR2_LPTM field. /
Kojto	90:cb3d968589d8	2771	#define BR_CAN_ESR2_LPTM(x) (HW_CAN_ESR2(x).B.LPTM)
Kojto	90:cb3d968589d8	2772	/@}/
Kojto	90:cb3d968589d8	2773
Kojto	90:cb3d968589d8	2774	/*******************************************************************************
Kojto	90:cb3d968589d8	2775	* HW_CAN_CRCR - CRC Register
Kojto	90:cb3d968589d8	2776	******************************************************************************/
Kojto	90:cb3d968589d8	2777
Kojto	90:cb3d968589d8	2778	/*!
Kojto	90:cb3d968589d8	2779	* @brief HW_CAN_CRCR - CRC Register (RO)
Kojto	90:cb3d968589d8	2780	*
Kojto	90:cb3d968589d8	2781	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2782	*
Kojto	90:cb3d968589d8	2783	* This register provides information about the CRC of transmitted messages.
Kojto	90:cb3d968589d8	2784	*/
Kojto	90:cb3d968589d8	2785	typedef union _hw_can_crcr
Kojto	90:cb3d968589d8	2786	{
Kojto	90:cb3d968589d8	2787	uint32_t U;
Kojto	90:cb3d968589d8	2788	struct _hw_can_crcr_bitfields
Kojto	90:cb3d968589d8	2789	{
Kojto	90:cb3d968589d8	2790	uint32_t TXCRC : 15; /!< [14:0] CRC Transmitted /
Kojto	90:cb3d968589d8	2791	uint32_t RESERVED0 : 1; /!< [15] /
Kojto	90:cb3d968589d8	2792	uint32_t MBCRC : 7; /!< [22:16] CRC Mailbox /
Kojto	90:cb3d968589d8	2793	uint32_t RESERVED1 : 9; /!< [31:23] /
Kojto	90:cb3d968589d8	2794	} B;
Kojto	90:cb3d968589d8	2795	} hw_can_crcr_t;
Kojto	90:cb3d968589d8	2796
Kojto	90:cb3d968589d8	2797	/*!
Kojto	90:cb3d968589d8	2798	* @name Constants and macros for entire CAN_CRCR register
Kojto	90:cb3d968589d8	2799	*/
Kojto	90:cb3d968589d8	2800	/@{/
Kojto	90:cb3d968589d8	2801	#define HW_CAN_CRCR_ADDR(x) ((x) + 0x44U)
Kojto	90:cb3d968589d8	2802
Kojto	90:cb3d968589d8	2803	#define HW_CAN_CRCR(x) ((__I hw_can_crcr_t ) HW_CAN_CRCR_ADDR(x))
Kojto	90:cb3d968589d8	2804	#define HW_CAN_CRCR_RD(x) (HW_CAN_CRCR(x).U)
Kojto	90:cb3d968589d8	2805	/@}/
Kojto	90:cb3d968589d8	2806
Kojto	90:cb3d968589d8	2807	/*
Kojto	90:cb3d968589d8	2808	* Constants & macros for individual CAN_CRCR bitfields
Kojto	90:cb3d968589d8	2809	*/
Kojto	90:cb3d968589d8	2810
Kojto	90:cb3d968589d8	2811	/*!
Kojto	90:cb3d968589d8	2812	* @name Register CAN_CRCR, field TXCRC[14:0] (RO)
Kojto	90:cb3d968589d8	2813	*
Kojto	90:cb3d968589d8	2814	* This field indicates the CRC value of the last message transmitted. This
Kojto	90:cb3d968589d8	2815	* field is updated at the same time the Tx Interrupt Flag is asserted.
Kojto	90:cb3d968589d8	2816	*/
Kojto	90:cb3d968589d8	2817	/@{/
Kojto	90:cb3d968589d8	2818	#define BP_CAN_CRCR_TXCRC (0U) /!< Bit position for CAN_CRCR_TXCRC. /
Kojto	90:cb3d968589d8	2819	#define BM_CAN_CRCR_TXCRC (0x00007FFFU) /!< Bit mask for CAN_CRCR_TXCRC. /
Kojto	90:cb3d968589d8	2820	#define BS_CAN_CRCR_TXCRC (15U) /!< Bit field size in bits for CAN_CRCR_TXCRC. /
Kojto	90:cb3d968589d8	2821
Kojto	90:cb3d968589d8	2822	/! @brief Read current value of the CAN_CRCR_TXCRC field. /
Kojto	90:cb3d968589d8	2823	#define BR_CAN_CRCR_TXCRC(x) (HW_CAN_CRCR(x).B.TXCRC)
Kojto	90:cb3d968589d8	2824	/@}/
Kojto	90:cb3d968589d8	2825
Kojto	90:cb3d968589d8	2826	/*!
Kojto	90:cb3d968589d8	2827	* @name Register CAN_CRCR, field MBCRC[22:16] (RO)
Kojto	90:cb3d968589d8	2828	*
Kojto	90:cb3d968589d8	2829	* This field indicates the number of the Mailbox corresponding to the value in
Kojto	90:cb3d968589d8	2830	* TXCRC field.
Kojto	90:cb3d968589d8	2831	*/
Kojto	90:cb3d968589d8	2832	/@{/
Kojto	90:cb3d968589d8	2833	#define BP_CAN_CRCR_MBCRC (16U) /!< Bit position for CAN_CRCR_MBCRC. /
Kojto	90:cb3d968589d8	2834	#define BM_CAN_CRCR_MBCRC (0x007F0000U) /!< Bit mask for CAN_CRCR_MBCRC. /
Kojto	90:cb3d968589d8	2835	#define BS_CAN_CRCR_MBCRC (7U) /!< Bit field size in bits for CAN_CRCR_MBCRC. /
Kojto	90:cb3d968589d8	2836
Kojto	90:cb3d968589d8	2837	/! @brief Read current value of the CAN_CRCR_MBCRC field. /
Kojto	90:cb3d968589d8	2838	#define BR_CAN_CRCR_MBCRC(x) (HW_CAN_CRCR(x).B.MBCRC)
Kojto	90:cb3d968589d8	2839	/@}/
Kojto	90:cb3d968589d8	2840
Kojto	90:cb3d968589d8	2841	/*******************************************************************************
Kojto	90:cb3d968589d8	2842	* HW_CAN_RXFGMASK - Rx FIFO Global Mask register
Kojto	90:cb3d968589d8	2843	******************************************************************************/
Kojto	90:cb3d968589d8	2844
Kojto	90:cb3d968589d8	2845	/*!
Kojto	90:cb3d968589d8	2846	* @brief HW_CAN_RXFGMASK - Rx FIFO Global Mask register (RW)
Kojto	90:cb3d968589d8	2847	*
Kojto	90:cb3d968589d8	2848	* Reset value: 0xFFFFFFFFU
Kojto	90:cb3d968589d8	2849	*
Kojto	90:cb3d968589d8	2850	* This register is located in RAM. If Rx FIFO is enabled RXFGMASK is used to
Kojto	90:cb3d968589d8	2851	* mask the Rx FIFO ID Filter Table elements that do not have a corresponding RXIMR
Kojto	90:cb3d968589d8	2852	* according to CTRL2[RFFN] field setting. This register can only be written in
Kojto	90:cb3d968589d8	2853	* Freeze mode as it is blocked by hardware in other modes.
Kojto	90:cb3d968589d8	2854	*/
Kojto	90:cb3d968589d8	2855	typedef union _hw_can_rxfgmask
Kojto	90:cb3d968589d8	2856	{
Kojto	90:cb3d968589d8	2857	uint32_t U;
Kojto	90:cb3d968589d8	2858	struct _hw_can_rxfgmask_bitfields
Kojto	90:cb3d968589d8	2859	{
Kojto	90:cb3d968589d8	2860	uint32_t FGM : 32; /!< [31:0] Rx FIFO Global Mask Bits /
Kojto	90:cb3d968589d8	2861	} B;
Kojto	90:cb3d968589d8	2862	} hw_can_rxfgmask_t;
Kojto	90:cb3d968589d8	2863
Kojto	90:cb3d968589d8	2864	/*!
Kojto	90:cb3d968589d8	2865	* @name Constants and macros for entire CAN_RXFGMASK register
Kojto	90:cb3d968589d8	2866	*/
Kojto	90:cb3d968589d8	2867	/@{/
Kojto	90:cb3d968589d8	2868	#define HW_CAN_RXFGMASK_ADDR(x) ((x) + 0x48U)
Kojto	90:cb3d968589d8	2869
Kojto	90:cb3d968589d8	2870	#define HW_CAN_RXFGMASK(x) ((__IO hw_can_rxfgmask_t ) HW_CAN_RXFGMASK_ADDR(x))
Kojto	90:cb3d968589d8	2871	#define HW_CAN_RXFGMASK_RD(x) (HW_CAN_RXFGMASK(x).U)
Kojto	90:cb3d968589d8	2872	#define HW_CAN_RXFGMASK_WR(x, v) (HW_CAN_RXFGMASK(x).U = (v))
Kojto	90:cb3d968589d8	2873	#define HW_CAN_RXFGMASK_SET(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2874	#define HW_CAN_RXFGMASK_CLR(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2875	#define HW_CAN_RXFGMASK_TOG(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2876	/@}/
Kojto	90:cb3d968589d8	2877
Kojto	90:cb3d968589d8	2878	/*
Kojto	90:cb3d968589d8	2879	* Constants & macros for individual CAN_RXFGMASK bitfields
Kojto	90:cb3d968589d8	2880	*/
Kojto	90:cb3d968589d8	2881
Kojto	90:cb3d968589d8	2882	/*!
Kojto	90:cb3d968589d8	2883	* @name Register CAN_RXFGMASK, field FGM[31:0] (RW)
Kojto	90:cb3d968589d8	2884	*
Kojto	90:cb3d968589d8	2885	* These bits mask the ID Filter Table elements bits in a perfect alignment. The
Kojto	90:cb3d968589d8	2886	* following table shows how the FGM bits correspond to each IDAF field. Rx FIFO
Kojto	90:cb3d968589d8	2887	* ID Filter Table Elements Format (MCR[IDAM]) Identifier Acceptance Filter
Kojto	90:cb3d968589d8	2888	* Fields RTR IDE RXIDA RXIDB If MCR[IDAM] field is equivalent to the format B only
Kojto	90:cb3d968589d8	2889	* the fourteen most significant bits of the Identifier of the incoming frame are
Kojto	90:cb3d968589d8	2890	* compared with the Rx FIFO filter. RXIDC If MCR[IDAM] field is equivalent to
Kojto	90:cb3d968589d8	2891	* the format C only the eight most significant bits of the Identifier of the
Kojto	90:cb3d968589d8	2892	* incoming frame are compared with the Rx FIFO filter. Reserved A FGM[31] FGM[30]
Kojto	90:cb3d968589d8	2893	* FGM[29:1] - - FGM[0] B FGM[31], FGM[15] FGM[30], FGM[14] - FGM[29:16], FGM[13:0]
Kojto	90:cb3d968589d8	2894	* - C - - - FGM[31:24], FGM[23:16], FGM[15:8], FGM[7:0]
Kojto	90:cb3d968589d8	2895	*
Kojto	90:cb3d968589d8	2896	* Values:
Kojto	90:cb3d968589d8	2897	* - 0 - The corresponding bit in the filter is "don't care."
Kojto	90:cb3d968589d8	2898	* - 1 - The corresponding bit in the filter is checked.
Kojto	90:cb3d968589d8	2899	*/
Kojto	90:cb3d968589d8	2900	/@{/
Kojto	90:cb3d968589d8	2901	#define BP_CAN_RXFGMASK_FGM (0U) /!< Bit position for CAN_RXFGMASK_FGM. /
Kojto	90:cb3d968589d8	2902	#define BM_CAN_RXFGMASK_FGM (0xFFFFFFFFU) /!< Bit mask for CAN_RXFGMASK_FGM. /
Kojto	90:cb3d968589d8	2903	#define BS_CAN_RXFGMASK_FGM (32U) /!< Bit field size in bits for CAN_RXFGMASK_FGM. /
Kojto	90:cb3d968589d8	2904
Kojto	90:cb3d968589d8	2905	/! @brief Read current value of the CAN_RXFGMASK_FGM field. /
Kojto	90:cb3d968589d8	2906	#define BR_CAN_RXFGMASK_FGM(x) (HW_CAN_RXFGMASK(x).U)
Kojto	90:cb3d968589d8	2907
Kojto	90:cb3d968589d8	2908	/! @brief Format value for bitfield CAN_RXFGMASK_FGM. /
Kojto	90:cb3d968589d8	2909	#define BF_CAN_RXFGMASK_FGM(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RXFGMASK_FGM) & BM_CAN_RXFGMASK_FGM)
Kojto	90:cb3d968589d8	2910
Kojto	90:cb3d968589d8	2911	/! @brief Set the FGM field to a new value. /
Kojto	90:cb3d968589d8	2912	#define BW_CAN_RXFGMASK_FGM(x, v) (HW_CAN_RXFGMASK_WR(x, v))
Kojto	90:cb3d968589d8	2913	/@}/
Kojto	90:cb3d968589d8	2914
Kojto	90:cb3d968589d8	2915	/*******************************************************************************
Kojto	90:cb3d968589d8	2916	* HW_CAN_RXFIR - Rx FIFO Information Register
Kojto	90:cb3d968589d8	2917	******************************************************************************/
Kojto	90:cb3d968589d8	2918
Kojto	90:cb3d968589d8	2919	/*!
Kojto	90:cb3d968589d8	2920	* @brief HW_CAN_RXFIR - Rx FIFO Information Register (RO)
Kojto	90:cb3d968589d8	2921	*
Kojto	90:cb3d968589d8	2922	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2923	*
Kojto	90:cb3d968589d8	2924	* RXFIR provides information on Rx FIFO. This register is the port through
Kojto	90:cb3d968589d8	2925	* which the CPU accesses the output of the RXFIR FIFO located in RAM. The RXFIR FIFO
Kojto	90:cb3d968589d8	2926	* is written by the FlexCAN whenever a new message is moved into the Rx FIFO as
Kojto	90:cb3d968589d8	2927	* well as its output is updated whenever the output of the Rx FIFO is updated
Kojto	90:cb3d968589d8	2928	* with the next message. See Section "Rx FIFO" for instructions on reading this
Kojto	90:cb3d968589d8	2929	* register.
Kojto	90:cb3d968589d8	2930	*/
Kojto	90:cb3d968589d8	2931	typedef union _hw_can_rxfir
Kojto	90:cb3d968589d8	2932	{
Kojto	90:cb3d968589d8	2933	uint32_t U;
Kojto	90:cb3d968589d8	2934	struct _hw_can_rxfir_bitfields
Kojto	90:cb3d968589d8	2935	{
Kojto	90:cb3d968589d8	2936	uint32_t IDHIT : 9; /*!< [8:0] Identifier Acceptance Filter Hit
Kojto	90:cb3d968589d8	2937	* Indicator */
Kojto	90:cb3d968589d8	2938	uint32_t RESERVED0 : 23; /!< [31:9] /
Kojto	90:cb3d968589d8	2939	} B;
Kojto	90:cb3d968589d8	2940	} hw_can_rxfir_t;
Kojto	90:cb3d968589d8	2941
Kojto	90:cb3d968589d8	2942	/*!
Kojto	90:cb3d968589d8	2943	* @name Constants and macros for entire CAN_RXFIR register
Kojto	90:cb3d968589d8	2944	*/
Kojto	90:cb3d968589d8	2945	/@{/
Kojto	90:cb3d968589d8	2946	#define HW_CAN_RXFIR_ADDR(x) ((x) + 0x4CU)
Kojto	90:cb3d968589d8	2947
Kojto	90:cb3d968589d8	2948	#define HW_CAN_RXFIR(x) ((__I hw_can_rxfir_t ) HW_CAN_RXFIR_ADDR(x))
Kojto	90:cb3d968589d8	2949	#define HW_CAN_RXFIR_RD(x) (HW_CAN_RXFIR(x).U)
Kojto	90:cb3d968589d8	2950	/@}/
Kojto	90:cb3d968589d8	2951
Kojto	90:cb3d968589d8	2952	/*
Kojto	90:cb3d968589d8	2953	* Constants & macros for individual CAN_RXFIR bitfields
Kojto	90:cb3d968589d8	2954	*/
Kojto	90:cb3d968589d8	2955
Kojto	90:cb3d968589d8	2956	/*!
Kojto	90:cb3d968589d8	2957	* @name Register CAN_RXFIR, field IDHIT[8:0] (RO)
Kojto	90:cb3d968589d8	2958	*
Kojto	90:cb3d968589d8	2959	* This field indicates which Identifier Acceptance Filter was hit by the
Kojto	90:cb3d968589d8	2960	* received message that is in the output of the Rx FIFO. If multiple filters match the
Kojto	90:cb3d968589d8	2961	* incoming message ID then the first matching IDAF found (lowest number) by the
Kojto	90:cb3d968589d8	2962	* matching process is indicated. This field is valid only while the
Kojto	90:cb3d968589d8	2963	* IFLAG[BUF5I] is asserted.
Kojto	90:cb3d968589d8	2964	*/
Kojto	90:cb3d968589d8	2965	/@{/
Kojto	90:cb3d968589d8	2966	#define BP_CAN_RXFIR_IDHIT (0U) /!< Bit position for CAN_RXFIR_IDHIT. /
Kojto	90:cb3d968589d8	2967	#define BM_CAN_RXFIR_IDHIT (0x000001FFU) /!< Bit mask for CAN_RXFIR_IDHIT. /
Kojto	90:cb3d968589d8	2968	#define BS_CAN_RXFIR_IDHIT (9U) /!< Bit field size in bits for CAN_RXFIR_IDHIT. /
Kojto	90:cb3d968589d8	2969
Kojto	90:cb3d968589d8	2970	/! @brief Read current value of the CAN_RXFIR_IDHIT field. /
Kojto	90:cb3d968589d8	2971	#define BR_CAN_RXFIR_IDHIT(x) (HW_CAN_RXFIR(x).B.IDHIT)
Kojto	90:cb3d968589d8	2972	/@}/
Kojto	90:cb3d968589d8	2973
Kojto	90:cb3d968589d8	2974	/*******************************************************************************
Kojto	90:cb3d968589d8	2975	* HW_CAN_CSn - Message Buffer 0 CS Register
Kojto	90:cb3d968589d8	2976	******************************************************************************/
Kojto	90:cb3d968589d8	2977
Kojto	90:cb3d968589d8	2978	/*!
Kojto	90:cb3d968589d8	2979	* @brief HW_CAN_CSn - Message Buffer 0 CS Register (RW)
Kojto	90:cb3d968589d8	2980	*
Kojto	90:cb3d968589d8	2981	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2982	*/
Kojto	90:cb3d968589d8	2983	typedef union _hw_can_csn
Kojto	90:cb3d968589d8	2984	{
Kojto	90:cb3d968589d8	2985	uint32_t U;
Kojto	90:cb3d968589d8	2986	struct _hw_can_csn_bitfields
Kojto	90:cb3d968589d8	2987	{
Kojto	90:cb3d968589d8	2988	uint32_t TIME_STAMP : 16; /*!< [15:0] Free-Running Counter Time
Kojto	90:cb3d968589d8	2989	* stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx
Kojto	90:cb3d968589d8	2990	* and Rx frames at the time when the beginning of the Identifier field
Kojto	90:cb3d968589d8	2991	* appears on the CAN bus. */
Kojto	90:cb3d968589d8	2992	uint32_t DLC : 4; /*!< [19:16] Length of the data to be
Kojto	90:cb3d968589d8	2993	* stored/transmitted. */
Kojto	90:cb3d968589d8	2994	uint32_t RTR : 1; /*!< [20] Remote Transmission Request. One/zero for
Kojto	90:cb3d968589d8	2995	* remote/data frame. */
Kojto	90:cb3d968589d8	2996	uint32_t IDE : 1; /*!< [21] ID Extended. One/zero for
Kojto	90:cb3d968589d8	2997	* extended/standard format frame. */
Kojto	90:cb3d968589d8	2998	uint32_t SRR : 1; /*!< [22] Substitute Remote Request. Contains a
Kojto	90:cb3d968589d8	2999	* fixed recessive bit. */
Kojto	90:cb3d968589d8	3000	uint32_t RESERVED0 : 1; /!< [23] Reserved /
Kojto	90:cb3d968589d8	3001	uint32_t CODE : 4; /!< [27:24] Reserved /
Kojto	90:cb3d968589d8	3002	uint32_t RESERVED1 : 4; /!< [31:28] Reserved /
Kojto	90:cb3d968589d8	3003	} B;
Kojto	90:cb3d968589d8	3004	} hw_can_csn_t;
Kojto	90:cb3d968589d8	3005
Kojto	90:cb3d968589d8	3006	/*!
Kojto	90:cb3d968589d8	3007	* @name Constants and macros for entire CAN_CSn register
Kojto	90:cb3d968589d8	3008	*/
Kojto	90:cb3d968589d8	3009	/@{/
Kojto	90:cb3d968589d8	3010	#define HW_CAN_CSn_COUNT (16U)
Kojto	90:cb3d968589d8	3011
Kojto	90:cb3d968589d8	3012	#define HW_CAN_CSn_ADDR(x, n) ((x) + 0x80U + (0x10U * (n)))
Kojto	90:cb3d968589d8	3013
Kojto	90:cb3d968589d8	3014	#define HW_CAN_CSn(x, n) ((__IO hw_can_csn_t ) HW_CAN_CSn_ADDR(x, n))
Kojto	90:cb3d968589d8	3015	#define HW_CAN_CSn_RD(x, n) (HW_CAN_CSn(x, n).U)
Kojto	90:cb3d968589d8	3016	#define HW_CAN_CSn_WR(x, n, v) (HW_CAN_CSn(x, n).U = (v))
Kojto	90:cb3d968589d8	3017	#define HW_CAN_CSn_SET(x, n, v) (HW_CAN_CSn_WR(x, n, HW_CAN_CSn_RD(x, n) \| (v)))
Kojto	90:cb3d968589d8	3018	#define HW_CAN_CSn_CLR(x, n, v) (HW_CAN_CSn_WR(x, n, HW_CAN_CSn_RD(x, n) & ~(v)))
Kojto	90:cb3d968589d8	3019	#define HW_CAN_CSn_TOG(x, n, v) (HW_CAN_CSn_WR(x, n, HW_CAN_CSn_RD(x, n) ^ (v)))
Kojto	90:cb3d968589d8	3020	/@}/
Kojto	90:cb3d968589d8	3021
Kojto	90:cb3d968589d8	3022	/*
Kojto	90:cb3d968589d8	3023	* Constants & macros for individual CAN_CSn bitfields
Kojto	90:cb3d968589d8	3024	*/
Kojto	90:cb3d968589d8	3025
Kojto	90:cb3d968589d8	3026	/*!
Kojto	90:cb3d968589d8	3027	* @name Register CAN_CSn, field TIME_STAMP[15:0] (RW)
Kojto	90:cb3d968589d8	3028	*/
Kojto	90:cb3d968589d8	3029	/@{/
Kojto	90:cb3d968589d8	3030	#define BP_CAN_CSn_TIME_STAMP (0U) /!< Bit position for CAN_CSn_TIME_STAMP. /
Kojto	90:cb3d968589d8	3031	#define BM_CAN_CSn_TIME_STAMP (0x0000FFFFU) /!< Bit mask for CAN_CSn_TIME_STAMP. /
Kojto	90:cb3d968589d8	3032	#define BS_CAN_CSn_TIME_STAMP (16U) /!< Bit field size in bits for CAN_CSn_TIME_STAMP. /
Kojto	90:cb3d968589d8	3033
Kojto	90:cb3d968589d8	3034	/! @brief Read current value of the CAN_CSn_TIME_STAMP field. /
Kojto	90:cb3d968589d8	3035	#define BR_CAN_CSn_TIME_STAMP(x, n) (HW_CAN_CSn(x, n).B.TIME_STAMP)
Kojto	90:cb3d968589d8	3036
Kojto	90:cb3d968589d8	3037	/! @brief Format value for bitfield CAN_CSn_TIME_STAMP. /
Kojto	90:cb3d968589d8	3038	#define BF_CAN_CSn_TIME_STAMP(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_TIME_STAMP) & BM_CAN_CSn_TIME_STAMP)
Kojto	90:cb3d968589d8	3039
Kojto	90:cb3d968589d8	3040	/! @brief Set the TIME_STAMP field to a new value. /
Kojto	90:cb3d968589d8	3041	#define BW_CAN_CSn_TIME_STAMP(x, n, v) (HW_CAN_CSn_WR(x, n, (HW_CAN_CSn_RD(x, n) & ~BM_CAN_CSn_TIME_STAMP) \| BF_CAN_CSn_TIME_STAMP(v)))
Kojto	90:cb3d968589d8	3042	/@}/
Kojto	90:cb3d968589d8	3043
Kojto	90:cb3d968589d8	3044	/*!
Kojto	90:cb3d968589d8	3045	* @name Register CAN_CSn, field DLC[19:16] (RW)
Kojto	90:cb3d968589d8	3046	*/
Kojto	90:cb3d968589d8	3047	/@{/
Kojto	90:cb3d968589d8	3048	#define BP_CAN_CSn_DLC (16U) /!< Bit position for CAN_CSn_DLC. /
Kojto	90:cb3d968589d8	3049	#define BM_CAN_CSn_DLC (0x000F0000U) /!< Bit mask for CAN_CSn_DLC. /
Kojto	90:cb3d968589d8	3050	#define BS_CAN_CSn_DLC (4U) /!< Bit field size in bits for CAN_CSn_DLC. /
Kojto	90:cb3d968589d8	3051
Kojto	90:cb3d968589d8	3052	/! @brief Read current value of the CAN_CSn_DLC field. /
Kojto	90:cb3d968589d8	3053	#define BR_CAN_CSn_DLC(x, n) (HW_CAN_CSn(x, n).B.DLC)
Kojto	90:cb3d968589d8	3054
Kojto	90:cb3d968589d8	3055	/! @brief Format value for bitfield CAN_CSn_DLC. /
Kojto	90:cb3d968589d8	3056	#define BF_CAN_CSn_DLC(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_DLC) & BM_CAN_CSn_DLC)
Kojto	90:cb3d968589d8	3057
Kojto	90:cb3d968589d8	3058	/! @brief Set the DLC field to a new value. /
Kojto	90:cb3d968589d8	3059	#define BW_CAN_CSn_DLC(x, n, v) (HW_CAN_CSn_WR(x, n, (HW_CAN_CSn_RD(x, n) & ~BM_CAN_CSn_DLC) \| BF_CAN_CSn_DLC(v)))
Kojto	90:cb3d968589d8	3060	/@}/
Kojto	90:cb3d968589d8	3061
Kojto	90:cb3d968589d8	3062	/*!
Kojto	90:cb3d968589d8	3063	* @name Register CAN_CSn, field RTR[20] (RW)
Kojto	90:cb3d968589d8	3064	*/
Kojto	90:cb3d968589d8	3065	/@{/
Kojto	90:cb3d968589d8	3066	#define BP_CAN_CSn_RTR (20U) /!< Bit position for CAN_CSn_RTR. /
Kojto	90:cb3d968589d8	3067	#define BM_CAN_CSn_RTR (0x00100000U) /!< Bit mask for CAN_CSn_RTR. /
Kojto	90:cb3d968589d8	3068	#define BS_CAN_CSn_RTR (1U) /!< Bit field size in bits for CAN_CSn_RTR. /
Kojto	90:cb3d968589d8	3069
Kojto	90:cb3d968589d8	3070	/! @brief Read current value of the CAN_CSn_RTR field. /
Kojto	90:cb3d968589d8	3071	#define BR_CAN_CSn_RTR(x, n) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_RTR))
Kojto	90:cb3d968589d8	3072
Kojto	90:cb3d968589d8	3073	/! @brief Format value for bitfield CAN_CSn_RTR. /
Kojto	90:cb3d968589d8	3074	#define BF_CAN_CSn_RTR(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_RTR) & BM_CAN_CSn_RTR)
Kojto	90:cb3d968589d8	3075
Kojto	90:cb3d968589d8	3076	/! @brief Set the RTR field to a new value. /
Kojto	90:cb3d968589d8	3077	#define BW_CAN_CSn_RTR(x, n, v) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_RTR) = (v))
Kojto	90:cb3d968589d8	3078	/@}/
Kojto	90:cb3d968589d8	3079
Kojto	90:cb3d968589d8	3080	/*!
Kojto	90:cb3d968589d8	3081	* @name Register CAN_CSn, field IDE[21] (RW)
Kojto	90:cb3d968589d8	3082	*/
Kojto	90:cb3d968589d8	3083	/@{/
Kojto	90:cb3d968589d8	3084	#define BP_CAN_CSn_IDE (21U) /!< Bit position for CAN_CSn_IDE. /
Kojto	90:cb3d968589d8	3085	#define BM_CAN_CSn_IDE (0x00200000U) /!< Bit mask for CAN_CSn_IDE. /
Kojto	90:cb3d968589d8	3086	#define BS_CAN_CSn_IDE (1U) /!< Bit field size in bits for CAN_CSn_IDE. /
Kojto	90:cb3d968589d8	3087
Kojto	90:cb3d968589d8	3088	/! @brief Read current value of the CAN_CSn_IDE field. /
Kojto	90:cb3d968589d8	3089	#define BR_CAN_CSn_IDE(x, n) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_IDE))
Kojto	90:cb3d968589d8	3090
Kojto	90:cb3d968589d8	3091	/! @brief Format value for bitfield CAN_CSn_IDE. /
Kojto	90:cb3d968589d8	3092	#define BF_CAN_CSn_IDE(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_IDE) & BM_CAN_CSn_IDE)
Kojto	90:cb3d968589d8	3093
Kojto	90:cb3d968589d8	3094	/! @brief Set the IDE field to a new value. /
Kojto	90:cb3d968589d8	3095	#define BW_CAN_CSn_IDE(x, n, v) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_IDE) = (v))
Kojto	90:cb3d968589d8	3096	/@}/
Kojto	90:cb3d968589d8	3097
Kojto	90:cb3d968589d8	3098	/*!
Kojto	90:cb3d968589d8	3099	* @name Register CAN_CSn, field SRR[22] (RW)
Kojto	90:cb3d968589d8	3100	*/
Kojto	90:cb3d968589d8	3101	/@{/
Kojto	90:cb3d968589d8	3102	#define BP_CAN_CSn_SRR (22U) /!< Bit position for CAN_CSn_SRR. /
Kojto	90:cb3d968589d8	3103	#define BM_CAN_CSn_SRR (0x00400000U) /!< Bit mask for CAN_CSn_SRR. /
Kojto	90:cb3d968589d8	3104	#define BS_CAN_CSn_SRR (1U) /!< Bit field size in bits for CAN_CSn_SRR. /
Kojto	90:cb3d968589d8	3105
Kojto	90:cb3d968589d8	3106	/! @brief Read current value of the CAN_CSn_SRR field. /
Kojto	90:cb3d968589d8	3107	#define BR_CAN_CSn_SRR(x, n) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_SRR))
Kojto	90:cb3d968589d8	3108
Kojto	90:cb3d968589d8	3109	/! @brief Format value for bitfield CAN_CSn_SRR. /
Kojto	90:cb3d968589d8	3110	#define BF_CAN_CSn_SRR(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_SRR) & BM_CAN_CSn_SRR)
Kojto	90:cb3d968589d8	3111
Kojto	90:cb3d968589d8	3112	/! @brief Set the SRR field to a new value. /
Kojto	90:cb3d968589d8	3113	#define BW_CAN_CSn_SRR(x, n, v) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_SRR) = (v))
Kojto	90:cb3d968589d8	3114	/@}/
Kojto	90:cb3d968589d8	3115
Kojto	90:cb3d968589d8	3116	/*!
Kojto	90:cb3d968589d8	3117	* @name Register CAN_CSn, field CODE[27:24] (RW)
Kojto	90:cb3d968589d8	3118	*/
Kojto	90:cb3d968589d8	3119	/@{/
Kojto	90:cb3d968589d8	3120	#define BP_CAN_CSn_CODE (24U) /!< Bit position for CAN_CSn_CODE. /
Kojto	90:cb3d968589d8	3121	#define BM_CAN_CSn_CODE (0x0F000000U) /!< Bit mask for CAN_CSn_CODE. /
Kojto	90:cb3d968589d8	3122	#define BS_CAN_CSn_CODE (4U) /!< Bit field size in bits for CAN_CSn_CODE. /
Kojto	90:cb3d968589d8	3123
Kojto	90:cb3d968589d8	3124	/! @brief Read current value of the CAN_CSn_CODE field. /
Kojto	90:cb3d968589d8	3125	#define BR_CAN_CSn_CODE(x, n) (HW_CAN_CSn(x, n).B.CODE)
Kojto	90:cb3d968589d8	3126
Kojto	90:cb3d968589d8	3127	/! @brief Format value for bitfield CAN_CSn_CODE. /
Kojto	90:cb3d968589d8	3128	#define BF_CAN_CSn_CODE(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_CODE) & BM_CAN_CSn_CODE)
Kojto	90:cb3d968589d8	3129
Kojto	90:cb3d968589d8	3130	/! @brief Set the CODE field to a new value. /
Kojto	90:cb3d968589d8	3131	#define BW_CAN_CSn_CODE(x, n, v) (HW_CAN_CSn_WR(x, n, (HW_CAN_CSn_RD(x, n) & ~BM_CAN_CSn_CODE) \| BF_CAN_CSn_CODE(v)))
Kojto	90:cb3d968589d8	3132	/@}/
Kojto	90:cb3d968589d8	3133	/*******************************************************************************
Kojto	90:cb3d968589d8	3134	* HW_CAN_IDn - Message Buffer 0 ID Register
Kojto	90:cb3d968589d8	3135	******************************************************************************/
Kojto	90:cb3d968589d8	3136
Kojto	90:cb3d968589d8	3137	/*!
Kojto	90:cb3d968589d8	3138	* @brief HW_CAN_IDn - Message Buffer 0 ID Register (RW)
Kojto	90:cb3d968589d8	3139	*
Kojto	90:cb3d968589d8	3140	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	3141	*/
Kojto	90:cb3d968589d8	3142	typedef union _hw_can_idn
Kojto	90:cb3d968589d8	3143	{
Kojto	90:cb3d968589d8	3144	uint32_t U;
Kojto	90:cb3d968589d8	3145	struct _hw_can_idn_bitfields
Kojto	90:cb3d968589d8	3146	{
Kojto	90:cb3d968589d8	3147	uint32_t EXT : 18; /*!< [17:0] Contains extended (LOW word)
Kojto	90:cb3d968589d8	3148	* identifier of message buffer. */
Kojto	90:cb3d968589d8	3149	uint32_t STD : 11; /*!< [28:18] Contains standard/extended (HIGH
Kojto	90:cb3d968589d8	3150	* word) identifier of message buffer. */
Kojto	90:cb3d968589d8	3151	uint32_t PRIO : 3; /*!< [31:29] Local priority. This 3-bit fieldis
Kojto	90:cb3d968589d8	3152	* only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx
Kojto	90:cb3d968589d8	3153	* buffers. These bits are not transmitted. They are appended to the regular
Kojto	90:cb3d968589d8	3154	* ID to define the transmission priority. */
Kojto	90:cb3d968589d8	3155	} B;
Kojto	90:cb3d968589d8	3156	} hw_can_idn_t;
Kojto	90:cb3d968589d8	3157
Kojto	90:cb3d968589d8	3158	/*!
Kojto	90:cb3d968589d8	3159	* @name Constants and macros for entire CAN_IDn register
Kojto	90:cb3d968589d8	3160	*/
Kojto	90:cb3d968589d8	3161	/@{/
Kojto	90:cb3d968589d8	3162	#define HW_CAN_IDn_COUNT (16U)
Kojto	90:cb3d968589d8	3163
Kojto	90:cb3d968589d8	3164	#define HW_CAN_IDn_ADDR(x, n) ((x) + 0x84U + (0x10U * (n)))
Kojto	90:cb3d968589d8	3165
Kojto	90:cb3d968589d8	3166	#define HW_CAN_IDn(x, n) ((__IO hw_can_idn_t ) HW_CAN_IDn_ADDR(x, n))
Kojto	90:cb3d968589d8	3167	#define HW_CAN_IDn_RD(x, n) (HW_CAN_IDn(x, n).U)
Kojto	90:cb3d968589d8	3168	#define HW_CAN_IDn_WR(x, n, v) (HW_CAN_IDn(x, n).U = (v))
Kojto	90:cb3d968589d8	3169	#define HW_CAN_IDn_SET(x, n, v) (HW_CAN_IDn_WR(x, n, HW_CAN_IDn_RD(x, n) \| (v)))
Kojto	90:cb3d968589d8	3170	#define HW_CAN_IDn_CLR(x, n, v) (HW_CAN_IDn_WR(x, n, HW_CAN_IDn_RD(x, n) & ~(v)))
Kojto	90:cb3d968589d8	3171	#define HW_CAN_IDn_TOG(x, n, v) (HW_CAN_IDn_WR(x, n, HW_CAN_IDn_RD(x, n) ^ (v)))
Kojto	90:cb3d968589d8	3172	/@}/
Kojto	90:cb3d968589d8	3173
Kojto	90:cb3d968589d8	3174	/*
Kojto	90:cb3d968589d8	3175	* Constants & macros for individual CAN_IDn bitfields
Kojto	90:cb3d968589d8	3176	*/
Kojto	90:cb3d968589d8	3177
Kojto	90:cb3d968589d8	3178	/*!
Kojto	90:cb3d968589d8	3179	* @name Register CAN_IDn, field EXT[17:0] (RW)
Kojto	90:cb3d968589d8	3180	*/
Kojto	90:cb3d968589d8	3181	/@{/
Kojto	90:cb3d968589d8	3182	#define BP_CAN_IDn_EXT (0U) /!< Bit position for CAN_IDn_EXT. /
Kojto	90:cb3d968589d8	3183	#define BM_CAN_IDn_EXT (0x0003FFFFU) /!< Bit mask for CAN_IDn_EXT. /
Kojto	90:cb3d968589d8	3184	#define BS_CAN_IDn_EXT (18U) /!< Bit field size in bits for CAN_IDn_EXT. /
Kojto	90:cb3d968589d8	3185
Kojto	90:cb3d968589d8	3186	/! @brief Read current value of the CAN_IDn_EXT field. /
Kojto	90:cb3d968589d8	3187	#define BR_CAN_IDn_EXT(x, n) (HW_CAN_IDn(x, n).B.EXT)
Kojto	90:cb3d968589d8	3188
Kojto	90:cb3d968589d8	3189	/! @brief Format value for bitfield CAN_IDn_EXT. /
Kojto	90:cb3d968589d8	3190	#define BF_CAN_IDn_EXT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IDn_EXT) & BM_CAN_IDn_EXT)
Kojto	90:cb3d968589d8	3191
Kojto	90:cb3d968589d8	3192	/! @brief Set the EXT field to a new value. /
Kojto	90:cb3d968589d8	3193	#define BW_CAN_IDn_EXT(x, n, v) (HW_CAN_IDn_WR(x, n, (HW_CAN_IDn_RD(x, n) & ~BM_CAN_IDn_EXT) \| BF_CAN_IDn_EXT(v)))
Kojto	90:cb3d968589d8	3194	/@}/
Kojto	90:cb3d968589d8	3195
Kojto	90:cb3d968589d8	3196	/*!
Kojto	90:cb3d968589d8	3197	* @name Register CAN_IDn, field STD[28:18] (RW)
Kojto	90:cb3d968589d8	3198	*/
Kojto	90:cb3d968589d8	3199	/@{/
Kojto	90:cb3d968589d8	3200	#define BP_CAN_IDn_STD (18U) /!< Bit position for CAN_IDn_STD. /
Kojto	90:cb3d968589d8	3201	#define BM_CAN_IDn_STD (0x1FFC0000U) /!< Bit mask for CAN_IDn_STD. /
Kojto	90:cb3d968589d8	3202	#define BS_CAN_IDn_STD (11U) /!< Bit field size in bits for CAN_IDn_STD. /
Kojto	90:cb3d968589d8	3203
Kojto	90:cb3d968589d8	3204	/! @brief Read current value of the CAN_IDn_STD field. /
Kojto	90:cb3d968589d8	3205	#define BR_CAN_IDn_STD(x, n) (HW_CAN_IDn(x, n).B.STD)
Kojto	90:cb3d968589d8	3206
Kojto	90:cb3d968589d8	3207	/! @brief Format value for bitfield CAN_IDn_STD. /
Kojto	90:cb3d968589d8	3208	#define BF_CAN_IDn_STD(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IDn_STD) & BM_CAN_IDn_STD)
Kojto	90:cb3d968589d8	3209
Kojto	90:cb3d968589d8	3210	/! @brief Set the STD field to a new value. /
Kojto	90:cb3d968589d8	3211	#define BW_CAN_IDn_STD(x, n, v) (HW_CAN_IDn_WR(x, n, (HW_CAN_IDn_RD(x, n) & ~BM_CAN_IDn_STD) \| BF_CAN_IDn_STD(v)))
Kojto	90:cb3d968589d8	3212	/@}/
Kojto	90:cb3d968589d8	3213
Kojto	90:cb3d968589d8	3214	/*!
Kojto	90:cb3d968589d8	3215	* @name Register CAN_IDn, field PRIO[31:29] (RW)
Kojto	90:cb3d968589d8	3216	*/
Kojto	90:cb3d968589d8	3217	/@{/
Kojto	90:cb3d968589d8	3218	#define BP_CAN_IDn_PRIO (29U) /!< Bit position for CAN_IDn_PRIO. /
Kojto	90:cb3d968589d8	3219	#define BM_CAN_IDn_PRIO (0xE0000000U) /!< Bit mask for CAN_IDn_PRIO. /
Kojto	90:cb3d968589d8	3220	#define BS_CAN_IDn_PRIO (3U) /!< Bit field size in bits for CAN_IDn_PRIO. /
Kojto	90:cb3d968589d8	3221
Kojto	90:cb3d968589d8	3222	/! @brief Read current value of the CAN_IDn_PRIO field. /
Kojto	90:cb3d968589d8	3223	#define BR_CAN_IDn_PRIO(x, n) (HW_CAN_IDn(x, n).B.PRIO)
Kojto	90:cb3d968589d8	3224
Kojto	90:cb3d968589d8	3225	/! @brief Format value for bitfield CAN_IDn_PRIO. /
Kojto	90:cb3d968589d8	3226	#define BF_CAN_IDn_PRIO(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IDn_PRIO) & BM_CAN_IDn_PRIO)
Kojto	90:cb3d968589d8	3227
Kojto	90:cb3d968589d8	3228	/! @brief Set the PRIO field to a new value. /
Kojto	90:cb3d968589d8	3229	#define BW_CAN_IDn_PRIO(x, n, v) (HW_CAN_IDn_WR(x, n, (HW_CAN_IDn_RD(x, n) & ~BM_CAN_IDn_PRIO) \| BF_CAN_IDn_PRIO(v)))
Kojto	90:cb3d968589d8	3230	/@}/
Kojto	90:cb3d968589d8	3231	/*******************************************************************************
Kojto	90:cb3d968589d8	3232	* HW_CAN_WORD0n - Message Buffer 0 WORD0 Register
Kojto	90:cb3d968589d8	3233	******************************************************************************/
Kojto	90:cb3d968589d8	3234
Kojto	90:cb3d968589d8	3235	/*!
Kojto	90:cb3d968589d8	3236	* @brief HW_CAN_WORD0n - Message Buffer 0 WORD0 Register (RW)
Kojto	90:cb3d968589d8	3237	*
Kojto	90:cb3d968589d8	3238	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	3239	*/
Kojto	90:cb3d968589d8	3240	typedef union _hw_can_word0n
Kojto	90:cb3d968589d8	3241	{
Kojto	90:cb3d968589d8	3242	uint32_t U;
Kojto	90:cb3d968589d8	3243	struct _hw_can_word0n_bitfields
Kojto	90:cb3d968589d8	3244	{
Kojto	90:cb3d968589d8	3245	uint32_t DATA_BYTE_3 : 8; /!< [7:0] Data byte 3 of Rx/Tx frame. /
Kojto	90:cb3d968589d8	3246	uint32_t DATA_BYTE_2 : 8; /!< [15:8] Data byte 2 of Rx/Tx frame. /
Kojto	90:cb3d968589d8	3247	uint32_t DATA_BYTE_1 : 8; /!< [23:16] Data byte 1 of Rx/Tx frame. /
Kojto	90:cb3d968589d8	3248	uint32_t DATA_BYTE_0 : 8; /!< [31:24] Data byte 0 of Rx/Tx frame. /
Kojto	90:cb3d968589d8	3249	} B;
Kojto	90:cb3d968589d8	3250	} hw_can_word0n_t;
Kojto	90:cb3d968589d8	3251
Kojto	90:cb3d968589d8	3252	/*!
Kojto	90:cb3d968589d8	3253	* @name Constants and macros for entire CAN_WORD0n register
Kojto	90:cb3d968589d8	3254	*/
Kojto	90:cb3d968589d8	3255	/@{/
Kojto	90:cb3d968589d8	3256	#define HW_CAN_WORD0n_COUNT (16U)
Kojto	90:cb3d968589d8	3257
Kojto	90:cb3d968589d8	3258	#define HW_CAN_WORD0n_ADDR(x, n) ((x) + 0x88U + (0x10U * (n)))
Kojto	90:cb3d968589d8	3259
Kojto	90:cb3d968589d8	3260	#define HW_CAN_WORD0n(x, n) ((__IO hw_can_word0n_t ) HW_CAN_WORD0n_ADDR(x, n))
Kojto	90:cb3d968589d8	3261	#define HW_CAN_WORD0n_RD(x, n) (HW_CAN_WORD0n(x, n).U)
Kojto	90:cb3d968589d8	3262	#define HW_CAN_WORD0n_WR(x, n, v) (HW_CAN_WORD0n(x, n).U = (v))
Kojto	90:cb3d968589d8	3263	#define HW_CAN_WORD0n_SET(x, n, v) (HW_CAN_WORD0n_WR(x, n, HW_CAN_WORD0n_RD(x, n) \| (v)))
Kojto	90:cb3d968589d8	3264	#define HW_CAN_WORD0n_CLR(x, n, v) (HW_CAN_WORD0n_WR(x, n, HW_CAN_WORD0n_RD(x, n) & ~(v)))
Kojto	90:cb3d968589d8	3265	#define HW_CAN_WORD0n_TOG(x, n, v) (HW_CAN_WORD0n_WR(x, n, HW_CAN_WORD0n_RD(x, n) ^ (v)))
Kojto	90:cb3d968589d8	3266	/@}/
Kojto	90:cb3d968589d8	3267
Kojto	90:cb3d968589d8	3268	/*
Kojto	90:cb3d968589d8	3269	* Constants & macros for individual CAN_WORD0n bitfields
Kojto	90:cb3d968589d8	3270	*/
Kojto	90:cb3d968589d8	3271
Kojto	90:cb3d968589d8	3272	/*!
Kojto	90:cb3d968589d8	3273	* @name Register CAN_WORD0n, field DATA_BYTE_3[7:0] (RW)
Kojto	90:cb3d968589d8	3274	*/
Kojto	90:cb3d968589d8	3275	/@{/
Kojto	90:cb3d968589d8	3276	#define BP_CAN_WORD0n_DATA_BYTE_3 (0U) /!< Bit position for CAN_WORD0n_DATA_BYTE_3. /
Kojto	90:cb3d968589d8	3277	#define BM_CAN_WORD0n_DATA_BYTE_3 (0x000000FFU) /!< Bit mask for CAN_WORD0n_DATA_BYTE_3. /
Kojto	90:cb3d968589d8	3278	#define BS_CAN_WORD0n_DATA_BYTE_3 (8U) /!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_3. /
Kojto	90:cb3d968589d8	3279
Kojto	90:cb3d968589d8	3280	/! @brief Read current value of the CAN_WORD0n_DATA_BYTE_3 field. /
Kojto	90:cb3d968589d8	3281	#define BR_CAN_WORD0n_DATA_BYTE_3(x, n) (HW_CAN_WORD0n(x, n).B.DATA_BYTE_3)
Kojto	90:cb3d968589d8	3282
Kojto	90:cb3d968589d8	3283	/! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_3. /
Kojto	90:cb3d968589d8	3284	#define BF_CAN_WORD0n_DATA_BYTE_3(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_3) & BM_CAN_WORD0n_DATA_BYTE_3)
Kojto	90:cb3d968589d8	3285
Kojto	90:cb3d968589d8	3286	/! @brief Set the DATA_BYTE_3 field to a new value. /
Kojto	90:cb3d968589d8	3287	#define BW_CAN_WORD0n_DATA_BYTE_3(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_3) \| BF_CAN_WORD0n_DATA_BYTE_3(v)))
Kojto	90:cb3d968589d8	3288	/@}/
Kojto	90:cb3d968589d8	3289
Kojto	90:cb3d968589d8	3290	/*!
Kojto	90:cb3d968589d8	3291	* @name Register CAN_WORD0n, field DATA_BYTE_2[15:8] (RW)
Kojto	90:cb3d968589d8	3292	*/
Kojto	90:cb3d968589d8	3293	/@{/
Kojto	90:cb3d968589d8	3294	#define BP_CAN_WORD0n_DATA_BYTE_2 (8U) /!< Bit position for CAN_WORD0n_DATA_BYTE_2. /
Kojto	90:cb3d968589d8	3295	#define BM_CAN_WORD0n_DATA_BYTE_2 (0x0000FF00U) /!< Bit mask for CAN_WORD0n_DATA_BYTE_2. /
Kojto	90:cb3d968589d8	3296	#define BS_CAN_WORD0n_DATA_BYTE_2 (8U) /!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_2. /
Kojto	90:cb3d968589d8	3297
Kojto	90:cb3d968589d8	3298	/! @brief Read current value of the CAN_WORD0n_DATA_BYTE_2 field. /
Kojto	90:cb3d968589d8	3299	#define BR_CAN_WORD0n_DATA_BYTE_2(x, n) (HW_CAN_WORD0n(x, n).B.DATA_BYTE_2)
Kojto	90:cb3d968589d8	3300
Kojto	90:cb3d968589d8	3301	/! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_2. /
Kojto	90:cb3d968589d8	3302	#define BF_CAN_WORD0n_DATA_BYTE_2(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_2) & BM_CAN_WORD0n_DATA_BYTE_2)
Kojto	90:cb3d968589d8	3303
Kojto	90:cb3d968589d8	3304	/! @brief Set the DATA_BYTE_2 field to a new value. /
Kojto	90:cb3d968589d8	3305	#define BW_CAN_WORD0n_DATA_BYTE_2(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_2) \| BF_CAN_WORD0n_DATA_BYTE_2(v)))
Kojto	90:cb3d968589d8	3306	/@}/
Kojto	90:cb3d968589d8	3307
Kojto	90:cb3d968589d8	3308	/*!
Kojto	90:cb3d968589d8	3309	* @name Register CAN_WORD0n, field DATA_BYTE_1[23:16] (RW)
Kojto	90:cb3d968589d8	3310	*/
Kojto	90:cb3d968589d8	3311	/@{/
Kojto	90:cb3d968589d8	3312	#define BP_CAN_WORD0n_DATA_BYTE_1 (16U) /!< Bit position for CAN_WORD0n_DATA_BYTE_1. /
Kojto	90:cb3d968589d8	3313	#define BM_CAN_WORD0n_DATA_BYTE_1 (0x00FF0000U) /!< Bit mask for CAN_WORD0n_DATA_BYTE_1. /
Kojto	90:cb3d968589d8	3314	#define BS_CAN_WORD0n_DATA_BYTE_1 (8U) /!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_1. /
Kojto	90:cb3d968589d8	3315
Kojto	90:cb3d968589d8	3316	/! @brief Read current value of the CAN_WORD0n_DATA_BYTE_1 field. /
Kojto	90:cb3d968589d8	3317	#define BR_CAN_WORD0n_DATA_BYTE_1(x, n) (HW_CAN_WORD0n(x, n).B.DATA_BYTE_1)
Kojto	90:cb3d968589d8	3318
Kojto	90:cb3d968589d8	3319	/! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_1. /
Kojto	90:cb3d968589d8	3320	#define BF_CAN_WORD0n_DATA_BYTE_1(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_1) & BM_CAN_WORD0n_DATA_BYTE_1)
Kojto	90:cb3d968589d8	3321
Kojto	90:cb3d968589d8	3322	/! @brief Set the DATA_BYTE_1 field to a new value. /
Kojto	90:cb3d968589d8	3323	#define BW_CAN_WORD0n_DATA_BYTE_1(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_1) \| BF_CAN_WORD0n_DATA_BYTE_1(v)))
Kojto	90:cb3d968589d8	3324	/@}/
Kojto	90:cb3d968589d8	3325
Kojto	90:cb3d968589d8	3326	/*!
Kojto	90:cb3d968589d8	3327	* @name Register CAN_WORD0n, field DATA_BYTE_0[31:24] (RW)
Kojto	90:cb3d968589d8	3328	*/
Kojto	90:cb3d968589d8	3329	/@{/
Kojto	90:cb3d968589d8	3330	#define BP_CAN_WORD0n_DATA_BYTE_0 (24U) /!< Bit position for CAN_WORD0n_DATA_BYTE_0. /
Kojto	90:cb3d968589d8	3331	#define BM_CAN_WORD0n_DATA_BYTE_0 (0xFF000000U) /!< Bit mask for CAN_WORD0n_DATA_BYTE_0. /
Kojto	90:cb3d968589d8	3332	#define BS_CAN_WORD0n_DATA_BYTE_0 (8U) /!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_0. /
Kojto	90:cb3d968589d8	3333
Kojto	90:cb3d968589d8	3334	/! @brief Read current value of the CAN_WORD0n_DATA_BYTE_0 field. /
Kojto	90:cb3d968589d8	3335	#define BR_CAN_WORD0n_DATA_BYTE_0(x, n) (HW_CAN_WORD0n(x, n).B.DATA_BYTE_0)
Kojto	90:cb3d968589d8	3336
Kojto	90:cb3d968589d8	3337	/! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_0. /
Kojto	90:cb3d968589d8	3338	#define BF_CAN_WORD0n_DATA_BYTE_0(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_0) & BM_CAN_WORD0n_DATA_BYTE_0)
Kojto	90:cb3d968589d8	3339
Kojto	90:cb3d968589d8	3340	/! @brief Set the DATA_BYTE_0 field to a new value. /
Kojto	90:cb3d968589d8	3341	#define BW_CAN_WORD0n_DATA_BYTE_0(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_0) \| BF_CAN_WORD0n_DATA_BYTE_0(v)))
Kojto	90:cb3d968589d8	3342	/@}/
Kojto	90:cb3d968589d8	3343	/*******************************************************************************
Kojto	90:cb3d968589d8	3344	* HW_CAN_WORD1n - Message Buffer 0 WORD1 Register
Kojto	90:cb3d968589d8	3345	******************************************************************************/
Kojto	90:cb3d968589d8	3346
Kojto	90:cb3d968589d8	3347	/*!
Kojto	90:cb3d968589d8	3348	* @brief HW_CAN_WORD1n - Message Buffer 0 WORD1 Register (RW)
Kojto	90:cb3d968589d8	3349	*
Kojto	90:cb3d968589d8	3350	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	3351	*/
Kojto	90:cb3d968589d8	3352	typedef union _hw_can_word1n
Kojto	90:cb3d968589d8	3353	{
Kojto	90:cb3d968589d8	3354	uint32_t U;
Kojto	90:cb3d968589d8	3355	struct _hw_can_word1n_bitfields
Kojto	90:cb3d968589d8	3356	{
Kojto	90:cb3d968589d8	3357	uint32_t DATA_BYTE_7 : 8; /!< [7:0] Data byte 7 of Rx/Tx frame. /
Kojto	90:cb3d968589d8	3358	uint32_t DATA_BYTE_6 : 8; /!< [15:8] Data byte 6 of Rx/Tx frame. /
Kojto	90:cb3d968589d8	3359	uint32_t DATA_BYTE_5 : 8; /!< [23:16] Data byte 5 of Rx/Tx frame. /
Kojto	90:cb3d968589d8	3360	uint32_t DATA_BYTE_4 : 8; /!< [31:24] Data byte 4 of Rx/Tx frame. /
Kojto	90:cb3d968589d8	3361	} B;
Kojto	90:cb3d968589d8	3362	} hw_can_word1n_t;
Kojto	90:cb3d968589d8	3363
Kojto	90:cb3d968589d8	3364	/*!
Kojto	90:cb3d968589d8	3365	* @name Constants and macros for entire CAN_WORD1n register
Kojto	90:cb3d968589d8	3366	*/
Kojto	90:cb3d968589d8	3367	/@{/
Kojto	90:cb3d968589d8	3368	#define HW_CAN_WORD1n_COUNT (16U)
Kojto	90:cb3d968589d8	3369
Kojto	90:cb3d968589d8	3370	#define HW_CAN_WORD1n_ADDR(x, n) ((x) + 0x8CU + (0x10U * (n)))
Kojto	90:cb3d968589d8	3371
Kojto	90:cb3d968589d8	3372	#define HW_CAN_WORD1n(x, n) ((__IO hw_can_word1n_t ) HW_CAN_WORD1n_ADDR(x, n))
Kojto	90:cb3d968589d8	3373	#define HW_CAN_WORD1n_RD(x, n) (HW_CAN_WORD1n(x, n).U)
Kojto	90:cb3d968589d8	3374	#define HW_CAN_WORD1n_WR(x, n, v) (HW_CAN_WORD1n(x, n).U = (v))
Kojto	90:cb3d968589d8	3375	#define HW_CAN_WORD1n_SET(x, n, v) (HW_CAN_WORD1n_WR(x, n, HW_CAN_WORD1n_RD(x, n) \| (v)))
Kojto	90:cb3d968589d8	3376	#define HW_CAN_WORD1n_CLR(x, n, v) (HW_CAN_WORD1n_WR(x, n, HW_CAN_WORD1n_RD(x, n) & ~(v)))
Kojto	90:cb3d968589d8	3377	#define HW_CAN_WORD1n_TOG(x, n, v) (HW_CAN_WORD1n_WR(x, n, HW_CAN_WORD1n_RD(x, n) ^ (v)))
Kojto	90:cb3d968589d8	3378	/@}/
Kojto	90:cb3d968589d8	3379
Kojto	90:cb3d968589d8	3380	/*
Kojto	90:cb3d968589d8	3381	* Constants & macros for individual CAN_WORD1n bitfields
Kojto	90:cb3d968589d8	3382	*/
Kojto	90:cb3d968589d8	3383
Kojto	90:cb3d968589d8	3384	/*!
Kojto	90:cb3d968589d8	3385	* @name Register CAN_WORD1n, field DATA_BYTE_7[7:0] (RW)
Kojto	90:cb3d968589d8	3386	*/
Kojto	90:cb3d968589d8	3387	/@{/
Kojto	90:cb3d968589d8	3388	#define BP_CAN_WORD1n_DATA_BYTE_7 (0U) /!< Bit position for CAN_WORD1n_DATA_BYTE_7. /
Kojto	90:cb3d968589d8	3389	#define BM_CAN_WORD1n_DATA_BYTE_7 (0x000000FFU) /!< Bit mask for CAN_WORD1n_DATA_BYTE_7. /
Kojto	90:cb3d968589d8	3390	#define BS_CAN_WORD1n_DATA_BYTE_7 (8U) /!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_7. /
Kojto	90:cb3d968589d8	3391
Kojto	90:cb3d968589d8	3392	/! @brief Read current value of the CAN_WORD1n_DATA_BYTE_7 field. /
Kojto	90:cb3d968589d8	3393	#define BR_CAN_WORD1n_DATA_BYTE_7(x, n) (HW_CAN_WORD1n(x, n).B.DATA_BYTE_7)
Kojto	90:cb3d968589d8	3394
Kojto	90:cb3d968589d8	3395	/! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_7. /
Kojto	90:cb3d968589d8	3396	#define BF_CAN_WORD1n_DATA_BYTE_7(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_7) & BM_CAN_WORD1n_DATA_BYTE_7)
Kojto	90:cb3d968589d8	3397
Kojto	90:cb3d968589d8	3398	/! @brief Set the DATA_BYTE_7 field to a new value. /
Kojto	90:cb3d968589d8	3399	#define BW_CAN_WORD1n_DATA_BYTE_7(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_7) \| BF_CAN_WORD1n_DATA_BYTE_7(v)))
Kojto	90:cb3d968589d8	3400	/@}/
Kojto	90:cb3d968589d8	3401
Kojto	90:cb3d968589d8	3402	/*!
Kojto	90:cb3d968589d8	3403	* @name Register CAN_WORD1n, field DATA_BYTE_6[15:8] (RW)
Kojto	90:cb3d968589d8	3404	*/
Kojto	90:cb3d968589d8	3405	/@{/
Kojto	90:cb3d968589d8	3406	#define BP_CAN_WORD1n_DATA_BYTE_6 (8U) /!< Bit position for CAN_WORD1n_DATA_BYTE_6. /
Kojto	90:cb3d968589d8	3407	#define BM_CAN_WORD1n_DATA_BYTE_6 (0x0000FF00U) /!< Bit mask for CAN_WORD1n_DATA_BYTE_6. /
Kojto	90:cb3d968589d8	3408	#define BS_CAN_WORD1n_DATA_BYTE_6 (8U) /!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_6. /
Kojto	90:cb3d968589d8	3409
Kojto	90:cb3d968589d8	3410	/! @brief Read current value of the CAN_WORD1n_DATA_BYTE_6 field. /
Kojto	90:cb3d968589d8	3411	#define BR_CAN_WORD1n_DATA_BYTE_6(x, n) (HW_CAN_WORD1n(x, n).B.DATA_BYTE_6)
Kojto	90:cb3d968589d8	3412
Kojto	90:cb3d968589d8	3413	/! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_6. /
Kojto	90:cb3d968589d8	3414	#define BF_CAN_WORD1n_DATA_BYTE_6(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_6) & BM_CAN_WORD1n_DATA_BYTE_6)
Kojto	90:cb3d968589d8	3415
Kojto	90:cb3d968589d8	3416	/! @brief Set the DATA_BYTE_6 field to a new value. /
Kojto	90:cb3d968589d8	3417	#define BW_CAN_WORD1n_DATA_BYTE_6(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_6) \| BF_CAN_WORD1n_DATA_BYTE_6(v)))
Kojto	90:cb3d968589d8	3418	/@}/
Kojto	90:cb3d968589d8	3419
Kojto	90:cb3d968589d8	3420	/*!
Kojto	90:cb3d968589d8	3421	* @name Register CAN_WORD1n, field DATA_BYTE_5[23:16] (RW)
Kojto	90:cb3d968589d8	3422	*/
Kojto	90:cb3d968589d8	3423	/@{/
Kojto	90:cb3d968589d8	3424	#define BP_CAN_WORD1n_DATA_BYTE_5 (16U) /!< Bit position for CAN_WORD1n_DATA_BYTE_5. /
Kojto	90:cb3d968589d8	3425	#define BM_CAN_WORD1n_DATA_BYTE_5 (0x00FF0000U) /!< Bit mask for CAN_WORD1n_DATA_BYTE_5. /
Kojto	90:cb3d968589d8	3426	#define BS_CAN_WORD1n_DATA_BYTE_5 (8U) /!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_5. /
Kojto	90:cb3d968589d8	3427
Kojto	90:cb3d968589d8	3428	/! @brief Read current value of the CAN_WORD1n_DATA_BYTE_5 field. /
Kojto	90:cb3d968589d8	3429	#define BR_CAN_WORD1n_DATA_BYTE_5(x, n) (HW_CAN_WORD1n(x, n).B.DATA_BYTE_5)
Kojto	90:cb3d968589d8	3430
Kojto	90:cb3d968589d8	3431	/! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_5. /
Kojto	90:cb3d968589d8	3432	#define BF_CAN_WORD1n_DATA_BYTE_5(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_5) & BM_CAN_WORD1n_DATA_BYTE_5)
Kojto	90:cb3d968589d8	3433
Kojto	90:cb3d968589d8	3434	/! @brief Set the DATA_BYTE_5 field to a new value. /
Kojto	90:cb3d968589d8	3435	#define BW_CAN_WORD1n_DATA_BYTE_5(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_5) \| BF_CAN_WORD1n_DATA_BYTE_5(v)))
Kojto	90:cb3d968589d8	3436	/@}/
Kojto	90:cb3d968589d8	3437
Kojto	90:cb3d968589d8	3438	/*!
Kojto	90:cb3d968589d8	3439	* @name Register CAN_WORD1n, field DATA_BYTE_4[31:24] (RW)
Kojto	90:cb3d968589d8	3440	*/
Kojto	90:cb3d968589d8	3441	/@{/
Kojto	90:cb3d968589d8	3442	#define BP_CAN_WORD1n_DATA_BYTE_4 (24U) /!< Bit position for CAN_WORD1n_DATA_BYTE_4. /
Kojto	90:cb3d968589d8	3443	#define BM_CAN_WORD1n_DATA_BYTE_4 (0xFF000000U) /!< Bit mask for CAN_WORD1n_DATA_BYTE_4. /
Kojto	90:cb3d968589d8	3444	#define BS_CAN_WORD1n_DATA_BYTE_4 (8U) /!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_4. /
Kojto	90:cb3d968589d8	3445
Kojto	90:cb3d968589d8	3446	/! @brief Read current value of the CAN_WORD1n_DATA_BYTE_4 field. /
Kojto	90:cb3d968589d8	3447	#define BR_CAN_WORD1n_DATA_BYTE_4(x, n) (HW_CAN_WORD1n(x, n).B.DATA_BYTE_4)
Kojto	90:cb3d968589d8	3448
Kojto	90:cb3d968589d8	3449	/! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_4. /
Kojto	90:cb3d968589d8	3450	#define BF_CAN_WORD1n_DATA_BYTE_4(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_4) & BM_CAN_WORD1n_DATA_BYTE_4)
Kojto	90:cb3d968589d8	3451
Kojto	90:cb3d968589d8	3452	/! @brief Set the DATA_BYTE_4 field to a new value. /
Kojto	90:cb3d968589d8	3453	#define BW_CAN_WORD1n_DATA_BYTE_4(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_4) \| BF_CAN_WORD1n_DATA_BYTE_4(v)))
Kojto	90:cb3d968589d8	3454	/@}/
Kojto	90:cb3d968589d8	3455
Kojto	90:cb3d968589d8	3456	/*******************************************************************************
Kojto	90:cb3d968589d8	3457	* HW_CAN_RXIMRn - Rx Individual Mask Registers
Kojto	90:cb3d968589d8	3458	******************************************************************************/
Kojto	90:cb3d968589d8	3459
Kojto	90:cb3d968589d8	3460	/*!
Kojto	90:cb3d968589d8	3461	* @brief HW_CAN_RXIMRn - Rx Individual Mask Registers (RW)
Kojto	90:cb3d968589d8	3462	*
Kojto	90:cb3d968589d8	3463	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	3464	*
Kojto	90:cb3d968589d8	3465	* These registers are located in RAM. RXIMR are used as acceptance masks for ID
Kojto	90:cb3d968589d8	3466	* filtering in Rx MBs and the Rx FIFO. If the Rx FIFO is not enabled, one mask
Kojto	90:cb3d968589d8	3467	* register is provided for each available Mailbox, providing ID masking
Kojto	90:cb3d968589d8	3468	* capability on a per Mailbox basis. When the Rx FIFO is enabled (MCR[RFEN] bit is
Kojto	90:cb3d968589d8	3469	* asserted), up to 32 Rx Individual Mask Registers can apply to the Rx FIFO ID Filter
Kojto	90:cb3d968589d8	3470	* Table elements on a one-to-one correspondence depending on the setting of
Kojto	90:cb3d968589d8	3471	* CTRL2[RFFN]. RXIMR can only be written by the CPU while the module is in Freeze
Kojto	90:cb3d968589d8	3472	* mode; otherwise, they are blocked by hardware. The Individual Rx Mask Registers
Kojto	90:cb3d968589d8	3473	* are not affected by reset and must be explicitly initialized prior to any
Kojto	90:cb3d968589d8	3474	* reception.
Kojto	90:cb3d968589d8	3475	*/
Kojto	90:cb3d968589d8	3476	typedef union _hw_can_rximrn
Kojto	90:cb3d968589d8	3477	{
Kojto	90:cb3d968589d8	3478	uint32_t U;
Kojto	90:cb3d968589d8	3479	struct _hw_can_rximrn_bitfields
Kojto	90:cb3d968589d8	3480	{
Kojto	90:cb3d968589d8	3481	uint32_t MI : 32; /!< [31:0] Individual Mask Bits /
Kojto	90:cb3d968589d8	3482	} B;
Kojto	90:cb3d968589d8	3483	} hw_can_rximrn_t;
Kojto	90:cb3d968589d8	3484
Kojto	90:cb3d968589d8	3485	/*!
Kojto	90:cb3d968589d8	3486	* @name Constants and macros for entire CAN_RXIMRn register
Kojto	90:cb3d968589d8	3487	*/
Kojto	90:cb3d968589d8	3488	/@{/
Kojto	90:cb3d968589d8	3489	#define HW_CAN_RXIMRn_COUNT (16U)
Kojto	90:cb3d968589d8	3490
Kojto	90:cb3d968589d8	3491	#define HW_CAN_RXIMRn_ADDR(x, n) ((x) + 0x880U + (0x4U * (n)))
Kojto	90:cb3d968589d8	3492
Kojto	90:cb3d968589d8	3493	#define HW_CAN_RXIMRn(x, n) ((__IO hw_can_rximrn_t ) HW_CAN_RXIMRn_ADDR(x, n))
Kojto	90:cb3d968589d8	3494	#define HW_CAN_RXIMRn_RD(x, n) (HW_CAN_RXIMRn(x, n).U)
Kojto	90:cb3d968589d8	3495	#define HW_CAN_RXIMRn_WR(x, n, v) (HW_CAN_RXIMRn(x, n).U = (v))
Kojto	90:cb3d968589d8	3496	#define HW_CAN_RXIMRn_SET(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) \| (v)))
Kojto	90:cb3d968589d8	3497	#define HW_CAN_RXIMRn_CLR(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) & ~(v)))
Kojto	90:cb3d968589d8	3498	#define HW_CAN_RXIMRn_TOG(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) ^ (v)))
Kojto	90:cb3d968589d8	3499	/@}/
Kojto	90:cb3d968589d8	3500
Kojto	90:cb3d968589d8	3501	/*
Kojto	90:cb3d968589d8	3502	* Constants & macros for individual CAN_RXIMRn bitfields
Kojto	90:cb3d968589d8	3503	*/
Kojto	90:cb3d968589d8	3504
Kojto	90:cb3d968589d8	3505	/*!
Kojto	90:cb3d968589d8	3506	* @name Register CAN_RXIMRn, field MI[31:0] (RW)
Kojto	90:cb3d968589d8	3507	*
Kojto	90:cb3d968589d8	3508	* Each Individual Mask Bit masks the corresponding bit in both the Mailbox
Kojto	90:cb3d968589d8	3509	* filter and Rx FIFO ID Filter Table element in distinct ways. For Mailbox filters,
Kojto	90:cb3d968589d8	3510	* see the RXMGMASK register description. For Rx FIFO ID Filter Table elements,
Kojto	90:cb3d968589d8	3511	* see the RXFGMASK register description.
Kojto	90:cb3d968589d8	3512	*
Kojto	90:cb3d968589d8	3513	* Values:
Kojto	90:cb3d968589d8	3514	* - 0 - The corresponding bit in the filter is "don't care."
Kojto	90:cb3d968589d8	3515	* - 1 - The corresponding bit in the filter is checked.
Kojto	90:cb3d968589d8	3516	*/
Kojto	90:cb3d968589d8	3517	/@{/
Kojto	90:cb3d968589d8	3518	#define BP_CAN_RXIMRn_MI (0U) /!< Bit position for CAN_RXIMRn_MI. /
Kojto	90:cb3d968589d8	3519	#define BM_CAN_RXIMRn_MI (0xFFFFFFFFU) /!< Bit mask for CAN_RXIMRn_MI. /
Kojto	90:cb3d968589d8	3520	#define BS_CAN_RXIMRn_MI (32U) /!< Bit field size in bits for CAN_RXIMRn_MI. /
Kojto	90:cb3d968589d8	3521
Kojto	90:cb3d968589d8	3522	/! @brief Read current value of the CAN_RXIMRn_MI field. /
Kojto	90:cb3d968589d8	3523	#define BR_CAN_RXIMRn_MI(x, n) (HW_CAN_RXIMRn(x, n).U)
Kojto	90:cb3d968589d8	3524
Kojto	90:cb3d968589d8	3525	/! @brief Format value for bitfield CAN_RXIMRn_MI. /
Kojto	90:cb3d968589d8	3526	#define BF_CAN_RXIMRn_MI(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RXIMRn_MI) & BM_CAN_RXIMRn_MI)
Kojto	90:cb3d968589d8	3527
Kojto	90:cb3d968589d8	3528	/! @brief Set the MI field to a new value. /
Kojto	90:cb3d968589d8	3529	#define BW_CAN_RXIMRn_MI(x, n, v) (HW_CAN_RXIMRn_WR(x, n, v))
Kojto	90:cb3d968589d8	3530	/@}/
Kojto	90:cb3d968589d8	3531
Kojto	90:cb3d968589d8	3532	/*******************************************************************************
Kojto	90:cb3d968589d8	3533	* hw_can_t - module struct
Kojto	90:cb3d968589d8	3534	******************************************************************************/
Kojto	90:cb3d968589d8	3535	/*!
Kojto	90:cb3d968589d8	3536	* @brief All CAN module registers.
Kojto	90:cb3d968589d8	3537	*/
Kojto	90:cb3d968589d8	3538	#pragma pack(1)
Kojto	90:cb3d968589d8	3539	typedef struct _hw_can
Kojto	90:cb3d968589d8	3540	{
Kojto	90:cb3d968589d8	3541	__IO hw_can_mcr_t MCR; /!< [0x0] Module Configuration Register /
Kojto	90:cb3d968589d8	3542	__IO hw_can_ctrl1_t CTRL1; /!< [0x4] Control 1 register /
Kojto	90:cb3d968589d8	3543	__IO hw_can_timer_t TIMER; /!< [0x8] Free Running Timer /
Kojto	90:cb3d968589d8	3544	uint8_t _reserved0[4];
Kojto	90:cb3d968589d8	3545	__IO hw_can_rxmgmask_t RXMGMASK; /!< [0x10] Rx Mailboxes Global Mask Register /
Kojto	90:cb3d968589d8	3546	__IO hw_can_rx14mask_t RX14MASK; /!< [0x14] Rx 14 Mask register /
Kojto	90:cb3d968589d8	3547	__IO hw_can_rx15mask_t RX15MASK; /!< [0x18] Rx 15 Mask register /
Kojto	90:cb3d968589d8	3548	__IO hw_can_ecr_t ECR; /!< [0x1C] Error Counter /
Kojto	90:cb3d968589d8	3549	__IO hw_can_esr1_t ESR1; /!< [0x20] Error and Status 1 register /
Kojto	90:cb3d968589d8	3550	uint8_t _reserved1[4];
Kojto	90:cb3d968589d8	3551	__IO hw_can_imask1_t IMASK1; /!< [0x28] Interrupt Masks 1 register /
Kojto	90:cb3d968589d8	3552	uint8_t _reserved2[4];
Kojto	90:cb3d968589d8	3553	__IO hw_can_iflag1_t IFLAG1; /!< [0x30] Interrupt Flags 1 register /
Kojto	90:cb3d968589d8	3554	__IO hw_can_ctrl2_t CTRL2; /!< [0x34] Control 2 register /
Kojto	90:cb3d968589d8	3555	__I hw_can_esr2_t ESR2; /!< [0x38] Error and Status 2 register /
Kojto	90:cb3d968589d8	3556	uint8_t _reserved3[8];
Kojto	90:cb3d968589d8	3557	__I hw_can_crcr_t CRCR; /!< [0x44] CRC Register /
Kojto	90:cb3d968589d8	3558	__IO hw_can_rxfgmask_t RXFGMASK; /!< [0x48] Rx FIFO Global Mask register /
Kojto	90:cb3d968589d8	3559	__I hw_can_rxfir_t RXFIR; /!< [0x4C] Rx FIFO Information Register /
Kojto	90:cb3d968589d8	3560	uint8_t _reserved4[48];
Kojto	90:cb3d968589d8	3561	struct {
Kojto	90:cb3d968589d8	3562	__IO hw_can_csn_t CSn; /!< [0x80] Message Buffer 0 CS Register /
Kojto	90:cb3d968589d8	3563	__IO hw_can_idn_t IDn; /!< [0x84] Message Buffer 0 ID Register /
Kojto	90:cb3d968589d8	3564	__IO hw_can_word0n_t WORD0n; /!< [0x88] Message Buffer 0 WORD0 Register /
Kojto	90:cb3d968589d8	3565	__IO hw_can_word1n_t WORD1n; /!< [0x8C] Message Buffer 0 WORD1 Register /
Kojto	90:cb3d968589d8	3566	} MB[16];
Kojto	90:cb3d968589d8	3567	uint8_t _reserved5[1792];
Kojto	90:cb3d968589d8	3568	__IO hw_can_rximrn_t RXIMRn[16]; /!< [0x880] Rx Individual Mask Registers /
Kojto	90:cb3d968589d8	3569	} hw_can_t;
Kojto	90:cb3d968589d8	3570	#pragma pack()
Kojto	90:cb3d968589d8	3571
Kojto	90:cb3d968589d8	3572	/! @brief Macro to access all CAN registers. /
Kojto	90:cb3d968589d8	3573	/! @param x CAN module instance base address. /
Kojto	90:cb3d968589d8	3574	/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto	90:cb3d968589d8	3575	* use the '&' operator, like <code>&HW_CAN(CAN0_BASE)</code>. */
Kojto	90:cb3d968589d8	3576	#define HW_CAN(x) ((hw_can_t )(x))
Kojto	90:cb3d968589d8	3577
Kojto	90:cb3d968589d8	3578	#endif /* __HW_CAN_REGISTERS_H__ */
Kojto	90:cb3d968589d8	3579	/* EOF */