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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_adc.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:: Kojto
Date:: Wed Aug 05 13:16:35 2015 +0100
Revision:: 104:b9ad9a133dc7
Parent:: 90:cb3d968589d8

Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	90:cb3d968589d8	1	/*
Kojto	90:cb3d968589d8	2	** ###################################################################
Kojto	90:cb3d968589d8	3	** Compilers: Keil ARM C/C++ Compiler
Kojto	90:cb3d968589d8	4	** Freescale C/C++ for Embedded ARM
Kojto	90:cb3d968589d8	5	** GNU C Compiler
Kojto	90:cb3d968589d8	6	** IAR ANSI C/C++ Compiler for ARM
Kojto	90:cb3d968589d8	7	**
Kojto	90:cb3d968589d8	8	** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto	90:cb3d968589d8	9	** Version: rev. 2.5, 2014-02-10
Kojto	90:cb3d968589d8	10	** Build: b140604
Kojto	90:cb3d968589d8	11	**
Kojto	90:cb3d968589d8	12	** Abstract:
Kojto	90:cb3d968589d8	13	** Extension to the CMSIS register access layer header.
Kojto	90:cb3d968589d8	14	**
Kojto	90:cb3d968589d8	15	** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto	90:cb3d968589d8	16	** All rights reserved.
Kojto	90:cb3d968589d8	17	**
Kojto	90:cb3d968589d8	18	** Redistribution and use in source and binary forms, with or without modification,
Kojto	90:cb3d968589d8	19	** are permitted provided that the following conditions are met:
Kojto	90:cb3d968589d8	20	**
Kojto	90:cb3d968589d8	21	** o Redistributions of source code must retain the above copyright notice, this list
Kojto	90:cb3d968589d8	22	** of conditions and the following disclaimer.
Kojto	90:cb3d968589d8	23	**
Kojto	90:cb3d968589d8	24	** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto	90:cb3d968589d8	25	** list of conditions and the following disclaimer in the documentation and/or
Kojto	90:cb3d968589d8	26	** other materials provided with the distribution.
Kojto	90:cb3d968589d8	27	**
Kojto	90:cb3d968589d8	28	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto	90:cb3d968589d8	29	** contributors may be used to endorse or promote products derived from this
Kojto	90:cb3d968589d8	30	** software without specific prior written permission.
Kojto	90:cb3d968589d8	31	**
Kojto	90:cb3d968589d8	32	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto	90:cb3d968589d8	33	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto	90:cb3d968589d8	34	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	90:cb3d968589d8	35	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto	90:cb3d968589d8	36	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto	90:cb3d968589d8	37	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto	90:cb3d968589d8	38	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto	90:cb3d968589d8	39	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto	90:cb3d968589d8	40	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto	90:cb3d968589d8	41	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	90:cb3d968589d8	42	**
Kojto	90:cb3d968589d8	43	** http: www.freescale.com
Kojto	90:cb3d968589d8	44	** mail: support@freescale.com
Kojto	90:cb3d968589d8	45	**
Kojto	90:cb3d968589d8	46	** Revisions:
Kojto	90:cb3d968589d8	47	** - rev. 1.0 (2013-08-12)
Kojto	90:cb3d968589d8	48	** Initial version.
Kojto	90:cb3d968589d8	49	** - rev. 2.0 (2013-10-29)
Kojto	90:cb3d968589d8	50	** Register accessor macros added to the memory map.
Kojto	90:cb3d968589d8	51	** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto	90:cb3d968589d8	52	** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto	90:cb3d968589d8	53	** System initialization updated.
Kojto	90:cb3d968589d8	54	** MCG - registers updated.
Kojto	90:cb3d968589d8	55	** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto	90:cb3d968589d8	56	** - rev. 2.1 (2013-10-30)
Kojto	90:cb3d968589d8	57	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto	90:cb3d968589d8	58	** - rev. 2.2 (2013-12-09)
Kojto	90:cb3d968589d8	59	** DMA - EARS register removed.
Kojto	90:cb3d968589d8	60	** AIPS0, AIPS1 - MPRA register updated.
Kojto	90:cb3d968589d8	61	** - rev. 2.3 (2014-01-24)
Kojto	90:cb3d968589d8	62	** Update according to reference manual rev. 2
Kojto	90:cb3d968589d8	63	** ENET, MCG, MCM, SIM, USB - registers updated
Kojto	90:cb3d968589d8	64	** - rev. 2.4 (2014-02-10)
Kojto	90:cb3d968589d8	65	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	66	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	67	** - rev. 2.5 (2014-02-10)
Kojto	90:cb3d968589d8	68	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	69	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	70	** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto	90:cb3d968589d8	71	**
Kojto	90:cb3d968589d8	72	** ###################################################################
Kojto	90:cb3d968589d8	73	*/
Kojto	90:cb3d968589d8	74
Kojto	90:cb3d968589d8	75	/*
Kojto	90:cb3d968589d8	76	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto	90:cb3d968589d8	77	*
Kojto	90:cb3d968589d8	78	* This file was generated automatically and any changes may be lost.
Kojto	90:cb3d968589d8	79	*/
Kojto	90:cb3d968589d8	80	#ifndef __HW_ADC_REGISTERS_H__
Kojto	90:cb3d968589d8	81	#define __HW_ADC_REGISTERS_H__
Kojto	90:cb3d968589d8	82
Kojto	90:cb3d968589d8	83	#include "MK64F12.h"
Kojto	90:cb3d968589d8	84	#include "fsl_bitaccess.h"
Kojto	90:cb3d968589d8	85
Kojto	90:cb3d968589d8	86	/*
Kojto	90:cb3d968589d8	87	* MK64F12 ADC
Kojto	90:cb3d968589d8	88	*
Kojto	90:cb3d968589d8	89	* Analog-to-Digital Converter
Kojto	90:cb3d968589d8	90	*
Kojto	90:cb3d968589d8	91	* Registers defined in this header file:
Kojto	90:cb3d968589d8	92	* - HW_ADC_SC1n - ADC Status and Control Registers 1
Kojto	90:cb3d968589d8	93	* - HW_ADC_CFG1 - ADC Configuration Register 1
Kojto	90:cb3d968589d8	94	* - HW_ADC_CFG2 - ADC Configuration Register 2
Kojto	90:cb3d968589d8	95	* - HW_ADC_Rn - ADC Data Result Register
Kojto	90:cb3d968589d8	96	* - HW_ADC_CV1 - Compare Value Registers
Kojto	90:cb3d968589d8	97	* - HW_ADC_CV2 - Compare Value Registers
Kojto	90:cb3d968589d8	98	* - HW_ADC_SC2 - Status and Control Register 2
Kojto	90:cb3d968589d8	99	* - HW_ADC_SC3 - Status and Control Register 3
Kojto	90:cb3d968589d8	100	* - HW_ADC_OFS - ADC Offset Correction Register
Kojto	90:cb3d968589d8	101	* - HW_ADC_PG - ADC Plus-Side Gain Register
Kojto	90:cb3d968589d8	102	* - HW_ADC_MG - ADC Minus-Side Gain Register
Kojto	90:cb3d968589d8	103	* - HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	104	* - HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	105	* - HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	106	* - HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	107	* - HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	108	* - HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	109	* - HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	110	* - HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	111	* - HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	112	* - HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	113	* - HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	114	* - HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	115	* - HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	116	* - HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	117	*
Kojto	90:cb3d968589d8	118	* - hw_adc_t - Struct containing all module registers.
Kojto	90:cb3d968589d8	119	*/
Kojto	90:cb3d968589d8	120
Kojto	90:cb3d968589d8	121	#define HW_ADC_INSTANCE_COUNT (2U) /!< Number of instances of the ADC module. /
Kojto	90:cb3d968589d8	122	#define HW_ADC0 (0U) /!< Instance number for ADC0. /
Kojto	90:cb3d968589d8	123	#define HW_ADC1 (1U) /!< Instance number for ADC1. /
Kojto	90:cb3d968589d8	124
Kojto	90:cb3d968589d8	125	/*******************************************************************************
Kojto	90:cb3d968589d8	126	* HW_ADC_SC1n - ADC Status and Control Registers 1
Kojto	90:cb3d968589d8	127	******************************************************************************/
Kojto	90:cb3d968589d8	128
Kojto	90:cb3d968589d8	129	/*!
Kojto	90:cb3d968589d8	130	* @brief HW_ADC_SC1n - ADC Status and Control Registers 1 (RW)
Kojto	90:cb3d968589d8	131	*
Kojto	90:cb3d968589d8	132	* Reset value: 0x0000001FU
Kojto	90:cb3d968589d8	133	*
Kojto	90:cb3d968589d8	134	* SC1A is used for both software and hardware trigger modes of operation. To
Kojto	90:cb3d968589d8	135	* allow sequential conversions of the ADC to be triggered by internal peripherals,
Kojto	90:cb3d968589d8	136	* the ADC can have more than one status and control register: one for each
Kojto	90:cb3d968589d8	137	* conversion. The SC1B-SC1n registers indicate potentially multiple SC1 registers
Kojto	90:cb3d968589d8	138	* for use only in hardware trigger mode. See the chip configuration information
Kojto	90:cb3d968589d8	139	* about the number of SC1n registers specific to this device. The SC1n registers
Kojto	90:cb3d968589d8	140	* have identical fields, and are used in a "ping-pong" approach to control ADC
Kojto	90:cb3d968589d8	141	* operation. At any one point in time, only one of the SC1n registers is actively
Kojto	90:cb3d968589d8	142	* controlling ADC conversions. Updating SC1A while SC1n is actively controlling
Kojto	90:cb3d968589d8	143	* a conversion is allowed, and vice-versa for any of the SC1n registers specific
Kojto	90:cb3d968589d8	144	* to this MCU. Writing SC1A while SC1A is actively controlling a conversion
Kojto	90:cb3d968589d8	145	* aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0,
Kojto	90:cb3d968589d8	146	* writes to SC1A subsequently initiate a new conversion, if SC1[ADCH] contains a
Kojto	90:cb3d968589d8	147	* value other than all 1s. Writing any of the SC1n registers while that specific
Kojto	90:cb3d968589d8	148	* SC1n register is actively controlling a conversion aborts the current conversion.
Kojto	90:cb3d968589d8	149	* None of the SC1B-SC1n registers are used for software trigger operation and
Kojto	90:cb3d968589d8	150	* therefore writes to the SC1B-SC1n registers do not initiate a new conversion.
Kojto	90:cb3d968589d8	151	*/
Kojto	90:cb3d968589d8	152	typedef union _hw_adc_sc1n
Kojto	90:cb3d968589d8	153	{
Kojto	90:cb3d968589d8	154	uint32_t U;
Kojto	90:cb3d968589d8	155	struct _hw_adc_sc1n_bitfields
Kojto	90:cb3d968589d8	156	{
Kojto	90:cb3d968589d8	157	uint32_t ADCH : 5; /!< [4:0] Input channel select /
Kojto	90:cb3d968589d8	158	uint32_t DIFF : 1; /!< [5] Differential Mode Enable /
Kojto	90:cb3d968589d8	159	uint32_t AIEN : 1; /!< [6] Interrupt Enable /
Kojto	90:cb3d968589d8	160	uint32_t COCO : 1; /!< [7] Conversion Complete Flag /
Kojto	90:cb3d968589d8	161	uint32_t RESERVED0 : 24; /!< [31:8] /
Kojto	90:cb3d968589d8	162	} B;
Kojto	90:cb3d968589d8	163	} hw_adc_sc1n_t;
Kojto	90:cb3d968589d8	164
Kojto	90:cb3d968589d8	165	/*!
Kojto	90:cb3d968589d8	166	* @name Constants and macros for entire ADC_SC1n register
Kojto	90:cb3d968589d8	167	*/
Kojto	90:cb3d968589d8	168	/@{/
Kojto	90:cb3d968589d8	169	#define HW_ADC_SC1n_COUNT (2U)
Kojto	90:cb3d968589d8	170
Kojto	90:cb3d968589d8	171	#define HW_ADC_SC1n_ADDR(x, n) ((x) + 0x0U + (0x4U * (n)))
Kojto	90:cb3d968589d8	172
Kojto	90:cb3d968589d8	173	#define HW_ADC_SC1n(x, n) ((__IO hw_adc_sc1n_t ) HW_ADC_SC1n_ADDR(x, n))
Kojto	90:cb3d968589d8	174	#define HW_ADC_SC1n_RD(x, n) (HW_ADC_SC1n(x, n).U)
Kojto	90:cb3d968589d8	175	#define HW_ADC_SC1n_WR(x, n, v) (HW_ADC_SC1n(x, n).U = (v))
Kojto	90:cb3d968589d8	176	#define HW_ADC_SC1n_SET(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) \| (v)))
Kojto	90:cb3d968589d8	177	#define HW_ADC_SC1n_CLR(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) & ~(v)))
Kojto	90:cb3d968589d8	178	#define HW_ADC_SC1n_TOG(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) ^ (v)))
Kojto	90:cb3d968589d8	179	/@}/
Kojto	90:cb3d968589d8	180
Kojto	90:cb3d968589d8	181	/*
Kojto	90:cb3d968589d8	182	* Constants & macros for individual ADC_SC1n bitfields
Kojto	90:cb3d968589d8	183	*/
Kojto	90:cb3d968589d8	184
Kojto	90:cb3d968589d8	185	/*!
Kojto	90:cb3d968589d8	186	* @name Register ADC_SC1n, field ADCH[4:0] (RW)
Kojto	90:cb3d968589d8	187	*
Kojto	90:cb3d968589d8	188	* Selects one of the input channels. The input channel decode depends on the
Kojto	90:cb3d968589d8	189	* value of DIFF. DAD0-DAD3 are associated with the input pin pairs DADPx and
Kojto	90:cb3d968589d8	190	* DADMx. Some of the input channel options in the bitfield-setting descriptions might
Kojto	90:cb3d968589d8	191	* not be available for your device. For the actual ADC channel assignments for
Kojto	90:cb3d968589d8	192	* your device, see the Chip Configuration details. The successive approximation
Kojto	90:cb3d968589d8	193	* converter subsystem is turned off when the channel select bits are all set,
Kojto	90:cb3d968589d8	194	* that is, ADCH = 11111. This feature allows explicit disabling of the ADC and
Kojto	90:cb3d968589d8	195	* isolation of the input channel from all sources. Terminating continuous
Kojto	90:cb3d968589d8	196	* conversions this way prevents an additional single conversion from being performed. It
Kojto	90:cb3d968589d8	197	* is not necessary to set ADCH to all 1s to place the ADC in a low-power state
Kojto	90:cb3d968589d8	198	* when continuous conversions are not enabled because the module automatically
Kojto	90:cb3d968589d8	199	* enters a low-power state when a conversion completes.
Kojto	90:cb3d968589d8	200	*
Kojto	90:cb3d968589d8	201	* Values:
Kojto	90:cb3d968589d8	202	* - 00000 - When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is
Kojto	90:cb3d968589d8	203	* selected as input.
Kojto	90:cb3d968589d8	204	* - 00001 - When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is
Kojto	90:cb3d968589d8	205	* selected as input.
Kojto	90:cb3d968589d8	206	* - 00010 - When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is
Kojto	90:cb3d968589d8	207	* selected as input.
Kojto	90:cb3d968589d8	208	* - 00011 - When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is
Kojto	90:cb3d968589d8	209	* selected as input.
Kojto	90:cb3d968589d8	210	* - 00100 - When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
Kojto	90:cb3d968589d8	211	* - 00101 - When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
Kojto	90:cb3d968589d8	212	* - 00110 - When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
Kojto	90:cb3d968589d8	213	* - 00111 - When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
Kojto	90:cb3d968589d8	214	* - 01000 - When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
Kojto	90:cb3d968589d8	215	* - 01001 - When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
Kojto	90:cb3d968589d8	216	* - 01010 - When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
Kojto	90:cb3d968589d8	217	* - 01011 - When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
Kojto	90:cb3d968589d8	218	* - 01100 - When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
Kojto	90:cb3d968589d8	219	* - 01101 - When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
Kojto	90:cb3d968589d8	220	* - 01110 - When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
Kojto	90:cb3d968589d8	221	* - 01111 - When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
Kojto	90:cb3d968589d8	222	* - 10000 - When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
Kojto	90:cb3d968589d8	223	* - 10001 - When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
Kojto	90:cb3d968589d8	224	* - 10010 - When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
Kojto	90:cb3d968589d8	225	* - 10011 - When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
Kojto	90:cb3d968589d8	226	* - 10100 - When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
Kojto	90:cb3d968589d8	227	* - 10101 - When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
Kojto	90:cb3d968589d8	228	* - 10110 - When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
Kojto	90:cb3d968589d8	229	* - 10111 - When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
Kojto	90:cb3d968589d8	230	* - 11000 - Reserved.
Kojto	90:cb3d968589d8	231	* - 11001 - Reserved.
Kojto	90:cb3d968589d8	232	* - 11010 - When DIFF=0, Temp Sensor (single-ended) is selected as input; when
Kojto	90:cb3d968589d8	233	* DIFF=1, Temp Sensor (differential) is selected as input.
Kojto	90:cb3d968589d8	234	* - 11011 - When DIFF=0, Bandgap (single-ended) is selected as input; when
Kojto	90:cb3d968589d8	235	* DIFF=1, Bandgap (differential) is selected as input.
Kojto	90:cb3d968589d8	236	* - 11100 - Reserved.
Kojto	90:cb3d968589d8	237	* - 11101 - When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH
Kojto	90:cb3d968589d8	238	* (differential) is selected as input. Voltage reference selected is determined
Kojto	90:cb3d968589d8	239	* by SC2[REFSEL].
Kojto	90:cb3d968589d8	240	* - 11110 - When DIFF=0,VREFSL is selected as input; when DIFF=1, it is
Kojto	90:cb3d968589d8	241	* reserved. Voltage reference selected is determined by SC2[REFSEL].
Kojto	90:cb3d968589d8	242	* - 11111 - Module is disabled.
Kojto	90:cb3d968589d8	243	*/
Kojto	90:cb3d968589d8	244	/@{/
Kojto	90:cb3d968589d8	245	#define BP_ADC_SC1n_ADCH (0U) /!< Bit position for ADC_SC1n_ADCH. /
Kojto	90:cb3d968589d8	246	#define BM_ADC_SC1n_ADCH (0x0000001FU) /!< Bit mask for ADC_SC1n_ADCH. /
Kojto	90:cb3d968589d8	247	#define BS_ADC_SC1n_ADCH (5U) /!< Bit field size in bits for ADC_SC1n_ADCH. /
Kojto	90:cb3d968589d8	248
Kojto	90:cb3d968589d8	249	/! @brief Read current value of the ADC_SC1n_ADCH field. /
Kojto	90:cb3d968589d8	250	#define BR_ADC_SC1n_ADCH(x, n) (HW_ADC_SC1n(x, n).B.ADCH)
Kojto	90:cb3d968589d8	251
Kojto	90:cb3d968589d8	252	/! @brief Format value for bitfield ADC_SC1n_ADCH. /
Kojto	90:cb3d968589d8	253	#define BF_ADC_SC1n_ADCH(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC1n_ADCH) & BM_ADC_SC1n_ADCH)
Kojto	90:cb3d968589d8	254
Kojto	90:cb3d968589d8	255	/! @brief Set the ADCH field to a new value. /
Kojto	90:cb3d968589d8	256	#define BW_ADC_SC1n_ADCH(x, n, v) (HW_ADC_SC1n_WR(x, n, (HW_ADC_SC1n_RD(x, n) & ~BM_ADC_SC1n_ADCH) \| BF_ADC_SC1n_ADCH(v)))
Kojto	90:cb3d968589d8	257	/@}/
Kojto	90:cb3d968589d8	258
Kojto	90:cb3d968589d8	259	/*!
Kojto	90:cb3d968589d8	260	* @name Register ADC_SC1n, field DIFF[5] (RW)
Kojto	90:cb3d968589d8	261	*
Kojto	90:cb3d968589d8	262	* Configures the ADC to operate in differential mode. When enabled, this mode
Kojto	90:cb3d968589d8	263	* automatically selects from the differential channels, and changes the
Kojto	90:cb3d968589d8	264	* conversion algorithm and the number of cycles to complete a conversion.
Kojto	90:cb3d968589d8	265	*
Kojto	90:cb3d968589d8	266	* Values:
Kojto	90:cb3d968589d8	267	* - 0 - Single-ended conversions and input channels are selected.
Kojto	90:cb3d968589d8	268	* - 1 - Differential conversions and input channels are selected.
Kojto	90:cb3d968589d8	269	*/
Kojto	90:cb3d968589d8	270	/@{/
Kojto	90:cb3d968589d8	271	#define BP_ADC_SC1n_DIFF (5U) /!< Bit position for ADC_SC1n_DIFF. /
Kojto	90:cb3d968589d8	272	#define BM_ADC_SC1n_DIFF (0x00000020U) /!< Bit mask for ADC_SC1n_DIFF. /
Kojto	90:cb3d968589d8	273	#define BS_ADC_SC1n_DIFF (1U) /!< Bit field size in bits for ADC_SC1n_DIFF. /
Kojto	90:cb3d968589d8	274
Kojto	90:cb3d968589d8	275	/! @brief Read current value of the ADC_SC1n_DIFF field. /
Kojto	90:cb3d968589d8	276	#define BR_ADC_SC1n_DIFF(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_DIFF))
Kojto	90:cb3d968589d8	277
Kojto	90:cb3d968589d8	278	/! @brief Format value for bitfield ADC_SC1n_DIFF. /
Kojto	90:cb3d968589d8	279	#define BF_ADC_SC1n_DIFF(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC1n_DIFF) & BM_ADC_SC1n_DIFF)
Kojto	90:cb3d968589d8	280
Kojto	90:cb3d968589d8	281	/! @brief Set the DIFF field to a new value. /
Kojto	90:cb3d968589d8	282	#define BW_ADC_SC1n_DIFF(x, n, v) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_DIFF) = (v))
Kojto	90:cb3d968589d8	283	/@}/
Kojto	90:cb3d968589d8	284
Kojto	90:cb3d968589d8	285	/*!
Kojto	90:cb3d968589d8	286	* @name Register ADC_SC1n, field AIEN[6] (RW)
Kojto	90:cb3d968589d8	287	*
Kojto	90:cb3d968589d8	288	* Enables conversion complete interrupts. When COCO becomes set while the
Kojto	90:cb3d968589d8	289	* respective AIEN is high, an interrupt is asserted.
Kojto	90:cb3d968589d8	290	*
Kojto	90:cb3d968589d8	291	* Values:
Kojto	90:cb3d968589d8	292	* - 0 - Conversion complete interrupt is disabled.
Kojto	90:cb3d968589d8	293	* - 1 - Conversion complete interrupt is enabled.
Kojto	90:cb3d968589d8	294	*/
Kojto	90:cb3d968589d8	295	/@{/
Kojto	90:cb3d968589d8	296	#define BP_ADC_SC1n_AIEN (6U) /!< Bit position for ADC_SC1n_AIEN. /
Kojto	90:cb3d968589d8	297	#define BM_ADC_SC1n_AIEN (0x00000040U) /!< Bit mask for ADC_SC1n_AIEN. /
Kojto	90:cb3d968589d8	298	#define BS_ADC_SC1n_AIEN (1U) /!< Bit field size in bits for ADC_SC1n_AIEN. /
Kojto	90:cb3d968589d8	299
Kojto	90:cb3d968589d8	300	/! @brief Read current value of the ADC_SC1n_AIEN field. /
Kojto	90:cb3d968589d8	301	#define BR_ADC_SC1n_AIEN(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_AIEN))
Kojto	90:cb3d968589d8	302
Kojto	90:cb3d968589d8	303	/! @brief Format value for bitfield ADC_SC1n_AIEN. /
Kojto	90:cb3d968589d8	304	#define BF_ADC_SC1n_AIEN(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC1n_AIEN) & BM_ADC_SC1n_AIEN)
Kojto	90:cb3d968589d8	305
Kojto	90:cb3d968589d8	306	/! @brief Set the AIEN field to a new value. /
Kojto	90:cb3d968589d8	307	#define BW_ADC_SC1n_AIEN(x, n, v) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_AIEN) = (v))
Kojto	90:cb3d968589d8	308	/@}/
Kojto	90:cb3d968589d8	309
Kojto	90:cb3d968589d8	310	/*!
Kojto	90:cb3d968589d8	311	* @name Register ADC_SC1n, field COCO[7] (RO)
Kojto	90:cb3d968589d8	312	*
Kojto	90:cb3d968589d8	313	* This is a read-only field that is set each time a conversion is completed
Kojto	90:cb3d968589d8	314	* when the compare function is disabled, or SC2[ACFE]=0 and the hardware average
Kojto	90:cb3d968589d8	315	* function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or
Kojto	90:cb3d968589d8	316	* SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare
Kojto	90:cb3d968589d8	317	* result is true. When the hardware average function is enabled, or SC3[AVGE]=1,
Kojto	90:cb3d968589d8	318	* COCO is set upon completion of the selected number of conversions (determined
Kojto	90:cb3d968589d8	319	* by AVGS). COCO in SC1A is also set at the completion of a calibration sequence.
Kojto	90:cb3d968589d8	320	* COCO is cleared when the respective SC1n register is written or when the
Kojto	90:cb3d968589d8	321	* respective Rn register is read.
Kojto	90:cb3d968589d8	322	*
Kojto	90:cb3d968589d8	323	* Values:
Kojto	90:cb3d968589d8	324	* - 0 - Conversion is not completed.
Kojto	90:cb3d968589d8	325	* - 1 - Conversion is completed.
Kojto	90:cb3d968589d8	326	*/
Kojto	90:cb3d968589d8	327	/@{/
Kojto	90:cb3d968589d8	328	#define BP_ADC_SC1n_COCO (7U) /!< Bit position for ADC_SC1n_COCO. /
Kojto	90:cb3d968589d8	329	#define BM_ADC_SC1n_COCO (0x00000080U) /!< Bit mask for ADC_SC1n_COCO. /
Kojto	90:cb3d968589d8	330	#define BS_ADC_SC1n_COCO (1U) /!< Bit field size in bits for ADC_SC1n_COCO. /
Kojto	90:cb3d968589d8	331
Kojto	90:cb3d968589d8	332	/! @brief Read current value of the ADC_SC1n_COCO field. /
Kojto	90:cb3d968589d8	333	#define BR_ADC_SC1n_COCO(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_COCO))
Kojto	90:cb3d968589d8	334	/@}/
Kojto	90:cb3d968589d8	335
Kojto	90:cb3d968589d8	336	/*******************************************************************************
Kojto	90:cb3d968589d8	337	* HW_ADC_CFG1 - ADC Configuration Register 1
Kojto	90:cb3d968589d8	338	******************************************************************************/
Kojto	90:cb3d968589d8	339
Kojto	90:cb3d968589d8	340	/*!
Kojto	90:cb3d968589d8	341	* @brief HW_ADC_CFG1 - ADC Configuration Register 1 (RW)
Kojto	90:cb3d968589d8	342	*
Kojto	90:cb3d968589d8	343	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	344	*
Kojto	90:cb3d968589d8	345	* The configuration Register 1 (CFG1) selects the mode of operation, clock
Kojto	90:cb3d968589d8	346	* source, clock divide, and configuration for low power or long sample time.
Kojto	90:cb3d968589d8	347	*/
Kojto	90:cb3d968589d8	348	typedef union _hw_adc_cfg1
Kojto	90:cb3d968589d8	349	{
Kojto	90:cb3d968589d8	350	uint32_t U;
Kojto	90:cb3d968589d8	351	struct _hw_adc_cfg1_bitfields
Kojto	90:cb3d968589d8	352	{
Kojto	90:cb3d968589d8	353	uint32_t ADICLK : 2; /!< [1:0] Input Clock Select /
Kojto	90:cb3d968589d8	354	uint32_t MODE : 2; /!< [3:2] Conversion mode selection /
Kojto	90:cb3d968589d8	355	uint32_t ADLSMP : 1; /!< [4] Sample Time Configuration /
Kojto	90:cb3d968589d8	356	uint32_t ADIV : 2; /!< [6:5] Clock Divide Select /
Kojto	90:cb3d968589d8	357	uint32_t ADLPC : 1; /!< [7] Low-Power Configuration /
Kojto	90:cb3d968589d8	358	uint32_t RESERVED0 : 24; /!< [31:8] /
Kojto	90:cb3d968589d8	359	} B;
Kojto	90:cb3d968589d8	360	} hw_adc_cfg1_t;
Kojto	90:cb3d968589d8	361
Kojto	90:cb3d968589d8	362	/*!
Kojto	90:cb3d968589d8	363	* @name Constants and macros for entire ADC_CFG1 register
Kojto	90:cb3d968589d8	364	*/
Kojto	90:cb3d968589d8	365	/@{/
Kojto	90:cb3d968589d8	366	#define HW_ADC_CFG1_ADDR(x) ((x) + 0x8U)
Kojto	90:cb3d968589d8	367
Kojto	90:cb3d968589d8	368	#define HW_ADC_CFG1(x) ((__IO hw_adc_cfg1_t ) HW_ADC_CFG1_ADDR(x))
Kojto	90:cb3d968589d8	369	#define HW_ADC_CFG1_RD(x) (HW_ADC_CFG1(x).U)
Kojto	90:cb3d968589d8	370	#define HW_ADC_CFG1_WR(x, v) (HW_ADC_CFG1(x).U = (v))
Kojto	90:cb3d968589d8	371	#define HW_ADC_CFG1_SET(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) \| (v)))
Kojto	90:cb3d968589d8	372	#define HW_ADC_CFG1_CLR(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	373	#define HW_ADC_CFG1_TOG(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	374	/@}/
Kojto	90:cb3d968589d8	375
Kojto	90:cb3d968589d8	376	/*
Kojto	90:cb3d968589d8	377	* Constants & macros for individual ADC_CFG1 bitfields
Kojto	90:cb3d968589d8	378	*/
Kojto	90:cb3d968589d8	379
Kojto	90:cb3d968589d8	380	/*!
Kojto	90:cb3d968589d8	381	* @name Register ADC_CFG1, field ADICLK[1:0] (RW)
Kojto	90:cb3d968589d8	382	*
Kojto	90:cb3d968589d8	383	* Selects the input clock source to generate the internal clock, ADCK. Note
Kojto	90:cb3d968589d8	384	* that when the ADACK clock source is selected, it is not required to be active
Kojto	90:cb3d968589d8	385	* prior to conversion start. When it is selected and it is not active prior to a
Kojto	90:cb3d968589d8	386	* conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at
Kojto	90:cb3d968589d8	387	* the start of a conversion and deactivated when conversions are terminated. In
Kojto	90:cb3d968589d8	388	* this case, there is an associated clock startup delay each time the clock
Kojto	90:cb3d968589d8	389	* source is re-activated.
Kojto	90:cb3d968589d8	390	*
Kojto	90:cb3d968589d8	391	* Values:
Kojto	90:cb3d968589d8	392	* - 00 - Bus clock
Kojto	90:cb3d968589d8	393	* - 01 - Alternate clock 2 (ALTCLK2)
Kojto	90:cb3d968589d8	394	* - 10 - Alternate clock (ALTCLK)
Kojto	90:cb3d968589d8	395	* - 11 - Asynchronous clock (ADACK)
Kojto	90:cb3d968589d8	396	*/
Kojto	90:cb3d968589d8	397	/@{/
Kojto	90:cb3d968589d8	398	#define BP_ADC_CFG1_ADICLK (0U) /!< Bit position for ADC_CFG1_ADICLK. /
Kojto	90:cb3d968589d8	399	#define BM_ADC_CFG1_ADICLK (0x00000003U) /!< Bit mask for ADC_CFG1_ADICLK. /
Kojto	90:cb3d968589d8	400	#define BS_ADC_CFG1_ADICLK (2U) /!< Bit field size in bits for ADC_CFG1_ADICLK. /
Kojto	90:cb3d968589d8	401
Kojto	90:cb3d968589d8	402	/! @brief Read current value of the ADC_CFG1_ADICLK field. /
Kojto	90:cb3d968589d8	403	#define BR_ADC_CFG1_ADICLK(x) (HW_ADC_CFG1(x).B.ADICLK)
Kojto	90:cb3d968589d8	404
Kojto	90:cb3d968589d8	405	/! @brief Format value for bitfield ADC_CFG1_ADICLK. /
Kojto	90:cb3d968589d8	406	#define BF_ADC_CFG1_ADICLK(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADICLK) & BM_ADC_CFG1_ADICLK)
Kojto	90:cb3d968589d8	407
Kojto	90:cb3d968589d8	408	/! @brief Set the ADICLK field to a new value. /
Kojto	90:cb3d968589d8	409	#define BW_ADC_CFG1_ADICLK(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_ADICLK) \| BF_ADC_CFG1_ADICLK(v)))
Kojto	90:cb3d968589d8	410	/@}/
Kojto	90:cb3d968589d8	411
Kojto	90:cb3d968589d8	412	/*!
Kojto	90:cb3d968589d8	413	* @name Register ADC_CFG1, field MODE[3:2] (RW)
Kojto	90:cb3d968589d8	414	*
Kojto	90:cb3d968589d8	415	* Selects the ADC resolution mode.
Kojto	90:cb3d968589d8	416	*
Kojto	90:cb3d968589d8	417	* Values:
Kojto	90:cb3d968589d8	418	* - 00 - When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is
Kojto	90:cb3d968589d8	419	* differential 9-bit conversion with 2's complement output.
Kojto	90:cb3d968589d8	420	* - 01 - When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is
Kojto	90:cb3d968589d8	421	* differential 13-bit conversion with 2's complement output.
Kojto	90:cb3d968589d8	422	* - 10 - When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is
Kojto	90:cb3d968589d8	423	* differential 11-bit conversion with 2's complement output
Kojto	90:cb3d968589d8	424	* - 11 - When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is
Kojto	90:cb3d968589d8	425	* differential 16-bit conversion with 2's complement output
Kojto	90:cb3d968589d8	426	*/
Kojto	90:cb3d968589d8	427	/@{/
Kojto	90:cb3d968589d8	428	#define BP_ADC_CFG1_MODE (2U) /!< Bit position for ADC_CFG1_MODE. /
Kojto	90:cb3d968589d8	429	#define BM_ADC_CFG1_MODE (0x0000000CU) /!< Bit mask for ADC_CFG1_MODE. /
Kojto	90:cb3d968589d8	430	#define BS_ADC_CFG1_MODE (2U) /!< Bit field size in bits for ADC_CFG1_MODE. /
Kojto	90:cb3d968589d8	431
Kojto	90:cb3d968589d8	432	/! @brief Read current value of the ADC_CFG1_MODE field. /
Kojto	90:cb3d968589d8	433	#define BR_ADC_CFG1_MODE(x) (HW_ADC_CFG1(x).B.MODE)
Kojto	90:cb3d968589d8	434
Kojto	90:cb3d968589d8	435	/! @brief Format value for bitfield ADC_CFG1_MODE. /
Kojto	90:cb3d968589d8	436	#define BF_ADC_CFG1_MODE(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_MODE) & BM_ADC_CFG1_MODE)
Kojto	90:cb3d968589d8	437
Kojto	90:cb3d968589d8	438	/! @brief Set the MODE field to a new value. /
Kojto	90:cb3d968589d8	439	#define BW_ADC_CFG1_MODE(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_MODE) \| BF_ADC_CFG1_MODE(v)))
Kojto	90:cb3d968589d8	440	/@}/
Kojto	90:cb3d968589d8	441
Kojto	90:cb3d968589d8	442	/*!
Kojto	90:cb3d968589d8	443	* @name Register ADC_CFG1, field ADLSMP[4] (RW)
Kojto	90:cb3d968589d8	444	*
Kojto	90:cb3d968589d8	445	* Selects between different sample times based on the conversion mode selected.
Kojto	90:cb3d968589d8	446	* This field adjusts the sample period to allow higher impedance inputs to be
Kojto	90:cb3d968589d8	447	* accurately sampled or to maximize conversion speed for lower impedance inputs.
Kojto	90:cb3d968589d8	448	* Longer sample times can also be used to lower overall power consumption if
Kojto	90:cb3d968589d8	449	* continuous conversions are enabled and high conversion rates are not required.
Kojto	90:cb3d968589d8	450	* When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the
Kojto	90:cb3d968589d8	451	* extent of the long sample time.
Kojto	90:cb3d968589d8	452	*
Kojto	90:cb3d968589d8	453	* Values:
Kojto	90:cb3d968589d8	454	* - 0 - Short sample time.
Kojto	90:cb3d968589d8	455	* - 1 - Long sample time.
Kojto	90:cb3d968589d8	456	*/
Kojto	90:cb3d968589d8	457	/@{/
Kojto	90:cb3d968589d8	458	#define BP_ADC_CFG1_ADLSMP (4U) /!< Bit position for ADC_CFG1_ADLSMP. /
Kojto	90:cb3d968589d8	459	#define BM_ADC_CFG1_ADLSMP (0x00000010U) /!< Bit mask for ADC_CFG1_ADLSMP. /
Kojto	90:cb3d968589d8	460	#define BS_ADC_CFG1_ADLSMP (1U) /!< Bit field size in bits for ADC_CFG1_ADLSMP. /
Kojto	90:cb3d968589d8	461
Kojto	90:cb3d968589d8	462	/! @brief Read current value of the ADC_CFG1_ADLSMP field. /
Kojto	90:cb3d968589d8	463	#define BR_ADC_CFG1_ADLSMP(x) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLSMP))
Kojto	90:cb3d968589d8	464
Kojto	90:cb3d968589d8	465	/! @brief Format value for bitfield ADC_CFG1_ADLSMP. /
Kojto	90:cb3d968589d8	466	#define BF_ADC_CFG1_ADLSMP(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADLSMP) & BM_ADC_CFG1_ADLSMP)
Kojto	90:cb3d968589d8	467
Kojto	90:cb3d968589d8	468	/! @brief Set the ADLSMP field to a new value. /
Kojto	90:cb3d968589d8	469	#define BW_ADC_CFG1_ADLSMP(x, v) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLSMP) = (v))
Kojto	90:cb3d968589d8	470	/@}/
Kojto	90:cb3d968589d8	471
Kojto	90:cb3d968589d8	472	/*!
Kojto	90:cb3d968589d8	473	* @name Register ADC_CFG1, field ADIV[6:5] (RW)
Kojto	90:cb3d968589d8	474	*
Kojto	90:cb3d968589d8	475	* Selects the divide ratio used by the ADC to generate the internal clock ADCK.
Kojto	90:cb3d968589d8	476	*
Kojto	90:cb3d968589d8	477	* Values:
Kojto	90:cb3d968589d8	478	* - 00 - The divide ratio is 1 and the clock rate is input clock.
Kojto	90:cb3d968589d8	479	* - 01 - The divide ratio is 2 and the clock rate is (input clock)/2.
Kojto	90:cb3d968589d8	480	* - 10 - The divide ratio is 4 and the clock rate is (input clock)/4.
Kojto	90:cb3d968589d8	481	* - 11 - The divide ratio is 8 and the clock rate is (input clock)/8.
Kojto	90:cb3d968589d8	482	*/
Kojto	90:cb3d968589d8	483	/@{/
Kojto	90:cb3d968589d8	484	#define BP_ADC_CFG1_ADIV (5U) /!< Bit position for ADC_CFG1_ADIV. /
Kojto	90:cb3d968589d8	485	#define BM_ADC_CFG1_ADIV (0x00000060U) /!< Bit mask for ADC_CFG1_ADIV. /
Kojto	90:cb3d968589d8	486	#define BS_ADC_CFG1_ADIV (2U) /!< Bit field size in bits for ADC_CFG1_ADIV. /
Kojto	90:cb3d968589d8	487
Kojto	90:cb3d968589d8	488	/! @brief Read current value of the ADC_CFG1_ADIV field. /
Kojto	90:cb3d968589d8	489	#define BR_ADC_CFG1_ADIV(x) (HW_ADC_CFG1(x).B.ADIV)
Kojto	90:cb3d968589d8	490
Kojto	90:cb3d968589d8	491	/! @brief Format value for bitfield ADC_CFG1_ADIV. /
Kojto	90:cb3d968589d8	492	#define BF_ADC_CFG1_ADIV(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADIV) & BM_ADC_CFG1_ADIV)
Kojto	90:cb3d968589d8	493
Kojto	90:cb3d968589d8	494	/! @brief Set the ADIV field to a new value. /
Kojto	90:cb3d968589d8	495	#define BW_ADC_CFG1_ADIV(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_ADIV) \| BF_ADC_CFG1_ADIV(v)))
Kojto	90:cb3d968589d8	496	/@}/
Kojto	90:cb3d968589d8	497
Kojto	90:cb3d968589d8	498	/*!
Kojto	90:cb3d968589d8	499	* @name Register ADC_CFG1, field ADLPC[7] (RW)
Kojto	90:cb3d968589d8	500	*
Kojto	90:cb3d968589d8	501	* Controls the power configuration of the successive approximation converter.
Kojto	90:cb3d968589d8	502	* This optimizes power consumption when higher sample rates are not required.
Kojto	90:cb3d968589d8	503	*
Kojto	90:cb3d968589d8	504	* Values:
Kojto	90:cb3d968589d8	505	* - 0 - Normal power configuration.
Kojto	90:cb3d968589d8	506	* - 1 - Low-power configuration. The power is reduced at the expense of maximum
Kojto	90:cb3d968589d8	507	* clock speed.
Kojto	90:cb3d968589d8	508	*/
Kojto	90:cb3d968589d8	509	/@{/
Kojto	90:cb3d968589d8	510	#define BP_ADC_CFG1_ADLPC (7U) /!< Bit position for ADC_CFG1_ADLPC. /
Kojto	90:cb3d968589d8	511	#define BM_ADC_CFG1_ADLPC (0x00000080U) /!< Bit mask for ADC_CFG1_ADLPC. /
Kojto	90:cb3d968589d8	512	#define BS_ADC_CFG1_ADLPC (1U) /!< Bit field size in bits for ADC_CFG1_ADLPC. /
Kojto	90:cb3d968589d8	513
Kojto	90:cb3d968589d8	514	/! @brief Read current value of the ADC_CFG1_ADLPC field. /
Kojto	90:cb3d968589d8	515	#define BR_ADC_CFG1_ADLPC(x) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLPC))
Kojto	90:cb3d968589d8	516
Kojto	90:cb3d968589d8	517	/! @brief Format value for bitfield ADC_CFG1_ADLPC. /
Kojto	90:cb3d968589d8	518	#define BF_ADC_CFG1_ADLPC(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADLPC) & BM_ADC_CFG1_ADLPC)
Kojto	90:cb3d968589d8	519
Kojto	90:cb3d968589d8	520	/! @brief Set the ADLPC field to a new value. /
Kojto	90:cb3d968589d8	521	#define BW_ADC_CFG1_ADLPC(x, v) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLPC) = (v))
Kojto	90:cb3d968589d8	522	/@}/
Kojto	90:cb3d968589d8	523
Kojto	90:cb3d968589d8	524	/*******************************************************************************
Kojto	90:cb3d968589d8	525	* HW_ADC_CFG2 - ADC Configuration Register 2
Kojto	90:cb3d968589d8	526	******************************************************************************/
Kojto	90:cb3d968589d8	527
Kojto	90:cb3d968589d8	528	/*!
Kojto	90:cb3d968589d8	529	* @brief HW_ADC_CFG2 - ADC Configuration Register 2 (RW)
Kojto	90:cb3d968589d8	530	*
Kojto	90:cb3d968589d8	531	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	532	*
Kojto	90:cb3d968589d8	533	* Configuration Register 2 (CFG2) selects the special high-speed configuration
Kojto	90:cb3d968589d8	534	* for very high speed conversions and selects the long sample time duration
Kojto	90:cb3d968589d8	535	* during long sample mode.
Kojto	90:cb3d968589d8	536	*/
Kojto	90:cb3d968589d8	537	typedef union _hw_adc_cfg2
Kojto	90:cb3d968589d8	538	{
Kojto	90:cb3d968589d8	539	uint32_t U;
Kojto	90:cb3d968589d8	540	struct _hw_adc_cfg2_bitfields
Kojto	90:cb3d968589d8	541	{
Kojto	90:cb3d968589d8	542	uint32_t ADLSTS : 2; /!< [1:0] Long Sample Time Select /
Kojto	90:cb3d968589d8	543	uint32_t ADHSC : 1; /!< [2] High-Speed Configuration /
Kojto	90:cb3d968589d8	544	uint32_t ADACKEN : 1; /!< [3] Asynchronous Clock Output Enable /
Kojto	90:cb3d968589d8	545	uint32_t MUXSEL : 1; /!< [4] ADC Mux Select /
Kojto	90:cb3d968589d8	546	uint32_t RESERVED0 : 27; /!< [31:5] /
Kojto	90:cb3d968589d8	547	} B;
Kojto	90:cb3d968589d8	548	} hw_adc_cfg2_t;
Kojto	90:cb3d968589d8	549
Kojto	90:cb3d968589d8	550	/*!
Kojto	90:cb3d968589d8	551	* @name Constants and macros for entire ADC_CFG2 register
Kojto	90:cb3d968589d8	552	*/
Kojto	90:cb3d968589d8	553	/@{/
Kojto	90:cb3d968589d8	554	#define HW_ADC_CFG2_ADDR(x) ((x) + 0xCU)
Kojto	90:cb3d968589d8	555
Kojto	90:cb3d968589d8	556	#define HW_ADC_CFG2(x) ((__IO hw_adc_cfg2_t ) HW_ADC_CFG2_ADDR(x))
Kojto	90:cb3d968589d8	557	#define HW_ADC_CFG2_RD(x) (HW_ADC_CFG2(x).U)
Kojto	90:cb3d968589d8	558	#define HW_ADC_CFG2_WR(x, v) (HW_ADC_CFG2(x).U = (v))
Kojto	90:cb3d968589d8	559	#define HW_ADC_CFG2_SET(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) \| (v)))
Kojto	90:cb3d968589d8	560	#define HW_ADC_CFG2_CLR(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	561	#define HW_ADC_CFG2_TOG(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	562	/@}/
Kojto	90:cb3d968589d8	563
Kojto	90:cb3d968589d8	564	/*
Kojto	90:cb3d968589d8	565	* Constants & macros for individual ADC_CFG2 bitfields
Kojto	90:cb3d968589d8	566	*/
Kojto	90:cb3d968589d8	567
Kojto	90:cb3d968589d8	568	/*!
Kojto	90:cb3d968589d8	569	* @name Register ADC_CFG2, field ADLSTS[1:0] (RW)
Kojto	90:cb3d968589d8	570	*
Kojto	90:cb3d968589d8	571	* Selects between the extended sample times when long sample time is selected,
Kojto	90:cb3d968589d8	572	* that is, when CFG1[ADLSMP]=1. This allows higher impedance inputs to be
Kojto	90:cb3d968589d8	573	* accurately sampled or to maximize conversion speed for lower impedance inputs.
Kojto	90:cb3d968589d8	574	* Longer sample times can also be used to lower overall power consumption when
Kojto	90:cb3d968589d8	575	* continuous conversions are enabled if high conversion rates are not required.
Kojto	90:cb3d968589d8	576	*
Kojto	90:cb3d968589d8	577	* Values:
Kojto	90:cb3d968589d8	578	* - 00 - Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles
Kojto	90:cb3d968589d8	579	* total.
Kojto	90:cb3d968589d8	580	* - 01 - 12 extra ADCK cycles; 16 ADCK cycles total sample time.
Kojto	90:cb3d968589d8	581	* - 10 - 6 extra ADCK cycles; 10 ADCK cycles total sample time.
Kojto	90:cb3d968589d8	582	* - 11 - 2 extra ADCK cycles; 6 ADCK cycles total sample time.
Kojto	90:cb3d968589d8	583	*/
Kojto	90:cb3d968589d8	584	/@{/
Kojto	90:cb3d968589d8	585	#define BP_ADC_CFG2_ADLSTS (0U) /!< Bit position for ADC_CFG2_ADLSTS. /
Kojto	90:cb3d968589d8	586	#define BM_ADC_CFG2_ADLSTS (0x00000003U) /!< Bit mask for ADC_CFG2_ADLSTS. /
Kojto	90:cb3d968589d8	587	#define BS_ADC_CFG2_ADLSTS (2U) /!< Bit field size in bits for ADC_CFG2_ADLSTS. /
Kojto	90:cb3d968589d8	588
Kojto	90:cb3d968589d8	589	/! @brief Read current value of the ADC_CFG2_ADLSTS field. /
Kojto	90:cb3d968589d8	590	#define BR_ADC_CFG2_ADLSTS(x) (HW_ADC_CFG2(x).B.ADLSTS)
Kojto	90:cb3d968589d8	591
Kojto	90:cb3d968589d8	592	/! @brief Format value for bitfield ADC_CFG2_ADLSTS. /
Kojto	90:cb3d968589d8	593	#define BF_ADC_CFG2_ADLSTS(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_ADLSTS) & BM_ADC_CFG2_ADLSTS)
Kojto	90:cb3d968589d8	594
Kojto	90:cb3d968589d8	595	/! @brief Set the ADLSTS field to a new value. /
Kojto	90:cb3d968589d8	596	#define BW_ADC_CFG2_ADLSTS(x, v) (HW_ADC_CFG2_WR(x, (HW_ADC_CFG2_RD(x) & ~BM_ADC_CFG2_ADLSTS) \| BF_ADC_CFG2_ADLSTS(v)))
Kojto	90:cb3d968589d8	597	/@}/
Kojto	90:cb3d968589d8	598
Kojto	90:cb3d968589d8	599	/*!
Kojto	90:cb3d968589d8	600	* @name Register ADC_CFG2, field ADHSC[2] (RW)
Kojto	90:cb3d968589d8	601	*
Kojto	90:cb3d968589d8	602	* Configures the ADC for very high-speed operation. The conversion sequence is
Kojto	90:cb3d968589d8	603	* altered with 2 ADCK cycles added to the conversion time to allow higher speed
Kojto	90:cb3d968589d8	604	* conversion clocks.
Kojto	90:cb3d968589d8	605	*
Kojto	90:cb3d968589d8	606	* Values:
Kojto	90:cb3d968589d8	607	* - 0 - Normal conversion sequence selected.
Kojto	90:cb3d968589d8	608	* - 1 - High-speed conversion sequence selected with 2 additional ADCK cycles
Kojto	90:cb3d968589d8	609	* to total conversion time.
Kojto	90:cb3d968589d8	610	*/
Kojto	90:cb3d968589d8	611	/@{/
Kojto	90:cb3d968589d8	612	#define BP_ADC_CFG2_ADHSC (2U) /!< Bit position for ADC_CFG2_ADHSC. /
Kojto	90:cb3d968589d8	613	#define BM_ADC_CFG2_ADHSC (0x00000004U) /!< Bit mask for ADC_CFG2_ADHSC. /
Kojto	90:cb3d968589d8	614	#define BS_ADC_CFG2_ADHSC (1U) /!< Bit field size in bits for ADC_CFG2_ADHSC. /
Kojto	90:cb3d968589d8	615
Kojto	90:cb3d968589d8	616	/! @brief Read current value of the ADC_CFG2_ADHSC field. /
Kojto	90:cb3d968589d8	617	#define BR_ADC_CFG2_ADHSC(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADHSC))
Kojto	90:cb3d968589d8	618
Kojto	90:cb3d968589d8	619	/! @brief Format value for bitfield ADC_CFG2_ADHSC. /
Kojto	90:cb3d968589d8	620	#define BF_ADC_CFG2_ADHSC(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_ADHSC) & BM_ADC_CFG2_ADHSC)
Kojto	90:cb3d968589d8	621
Kojto	90:cb3d968589d8	622	/! @brief Set the ADHSC field to a new value. /
Kojto	90:cb3d968589d8	623	#define BW_ADC_CFG2_ADHSC(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADHSC) = (v))
Kojto	90:cb3d968589d8	624	/@}/
Kojto	90:cb3d968589d8	625
Kojto	90:cb3d968589d8	626	/*!
Kojto	90:cb3d968589d8	627	* @name Register ADC_CFG2, field ADACKEN[3] (RW)
Kojto	90:cb3d968589d8	628	*
Kojto	90:cb3d968589d8	629	* Enables the asynchronous clock source and the clock source output regardless
Kojto	90:cb3d968589d8	630	* of the conversion and status of CFG1[ADICLK]. Based on MCU configuration, the
Kojto	90:cb3d968589d8	631	* asynchronous clock may be used by other modules. See chip configuration
Kojto	90:cb3d968589d8	632	* information. Setting this field allows the clock to be used even while the ADC is
Kojto	90:cb3d968589d8	633	* idle or operating from a different clock source. Also, latency of initiating a
Kojto	90:cb3d968589d8	634	* single or first-continuous conversion with the asynchronous clock selected is
Kojto	90:cb3d968589d8	635	* reduced because the ADACK clock is already operational.
Kojto	90:cb3d968589d8	636	*
Kojto	90:cb3d968589d8	637	* Values:
Kojto	90:cb3d968589d8	638	* - 0 - Asynchronous clock output disabled; Asynchronous clock is enabled only
Kojto	90:cb3d968589d8	639	* if selected by ADICLK and a conversion is active.
Kojto	90:cb3d968589d8	640	* - 1 - Asynchronous clock and clock output is enabled regardless of the state
Kojto	90:cb3d968589d8	641	* of the ADC.
Kojto	90:cb3d968589d8	642	*/
Kojto	90:cb3d968589d8	643	/@{/
Kojto	90:cb3d968589d8	644	#define BP_ADC_CFG2_ADACKEN (3U) /!< Bit position for ADC_CFG2_ADACKEN. /
Kojto	90:cb3d968589d8	645	#define BM_ADC_CFG2_ADACKEN (0x00000008U) /!< Bit mask for ADC_CFG2_ADACKEN. /
Kojto	90:cb3d968589d8	646	#define BS_ADC_CFG2_ADACKEN (1U) /!< Bit field size in bits for ADC_CFG2_ADACKEN. /
Kojto	90:cb3d968589d8	647
Kojto	90:cb3d968589d8	648	/! @brief Read current value of the ADC_CFG2_ADACKEN field. /
Kojto	90:cb3d968589d8	649	#define BR_ADC_CFG2_ADACKEN(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADACKEN))
Kojto	90:cb3d968589d8	650
Kojto	90:cb3d968589d8	651	/! @brief Format value for bitfield ADC_CFG2_ADACKEN. /
Kojto	90:cb3d968589d8	652	#define BF_ADC_CFG2_ADACKEN(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_ADACKEN) & BM_ADC_CFG2_ADACKEN)
Kojto	90:cb3d968589d8	653
Kojto	90:cb3d968589d8	654	/! @brief Set the ADACKEN field to a new value. /
Kojto	90:cb3d968589d8	655	#define BW_ADC_CFG2_ADACKEN(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADACKEN) = (v))
Kojto	90:cb3d968589d8	656	/@}/
Kojto	90:cb3d968589d8	657
Kojto	90:cb3d968589d8	658	/*!
Kojto	90:cb3d968589d8	659	* @name Register ADC_CFG2, field MUXSEL[4] (RW)
Kojto	90:cb3d968589d8	660	*
Kojto	90:cb3d968589d8	661	* Changes the ADC mux setting to select between alternate sets of ADC channels.
Kojto	90:cb3d968589d8	662	*
Kojto	90:cb3d968589d8	663	* Values:
Kojto	90:cb3d968589d8	664	* - 0 - ADxxa channels are selected.
Kojto	90:cb3d968589d8	665	* - 1 - ADxxb channels are selected.
Kojto	90:cb3d968589d8	666	*/
Kojto	90:cb3d968589d8	667	/@{/
Kojto	90:cb3d968589d8	668	#define BP_ADC_CFG2_MUXSEL (4U) /!< Bit position for ADC_CFG2_MUXSEL. /
Kojto	90:cb3d968589d8	669	#define BM_ADC_CFG2_MUXSEL (0x00000010U) /!< Bit mask for ADC_CFG2_MUXSEL. /
Kojto	90:cb3d968589d8	670	#define BS_ADC_CFG2_MUXSEL (1U) /!< Bit field size in bits for ADC_CFG2_MUXSEL. /
Kojto	90:cb3d968589d8	671
Kojto	90:cb3d968589d8	672	/! @brief Read current value of the ADC_CFG2_MUXSEL field. /
Kojto	90:cb3d968589d8	673	#define BR_ADC_CFG2_MUXSEL(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_MUXSEL))
Kojto	90:cb3d968589d8	674
Kojto	90:cb3d968589d8	675	/! @brief Format value for bitfield ADC_CFG2_MUXSEL. /
Kojto	90:cb3d968589d8	676	#define BF_ADC_CFG2_MUXSEL(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_MUXSEL) & BM_ADC_CFG2_MUXSEL)
Kojto	90:cb3d968589d8	677
Kojto	90:cb3d968589d8	678	/! @brief Set the MUXSEL field to a new value. /
Kojto	90:cb3d968589d8	679	#define BW_ADC_CFG2_MUXSEL(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_MUXSEL) = (v))
Kojto	90:cb3d968589d8	680	/@}/
Kojto	90:cb3d968589d8	681
Kojto	90:cb3d968589d8	682	/*******************************************************************************
Kojto	90:cb3d968589d8	683	* HW_ADC_Rn - ADC Data Result Register
Kojto	90:cb3d968589d8	684	******************************************************************************/
Kojto	90:cb3d968589d8	685
Kojto	90:cb3d968589d8	686	/*!
Kojto	90:cb3d968589d8	687	* @brief HW_ADC_Rn - ADC Data Result Register (RO)
Kojto	90:cb3d968589d8	688	*
Kojto	90:cb3d968589d8	689	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	690	*
Kojto	90:cb3d968589d8	691	* The data result registers (Rn) contain the result of an ADC conversion of the
Kojto	90:cb3d968589d8	692	* channel selected by the corresponding status and channel control register
Kojto	90:cb3d968589d8	693	* (SC1A:SC1n). For every status and channel control register, there is a
Kojto	90:cb3d968589d8	694	* corresponding data result register. Unused bits in R n are cleared in unsigned
Kojto	90:cb3d968589d8	695	* right-aligned modes and carry the sign bit (MSB) in sign-extended 2's complement modes.
Kojto	90:cb3d968589d8	696	* For example, when configured for 10-bit single-ended mode, D[15:10] are
Kojto	90:cb3d968589d8	697	* cleared. When configured for 11-bit differential mode, D[15:10] carry the sign bit,
Kojto	90:cb3d968589d8	698	* that is, bit 10 extended through bit 15. The following table describes the
Kojto	90:cb3d968589d8	699	* behavior of the data result registers in the different modes of operation. Data
Kojto	90:cb3d968589d8	700	* result register description Conversion mode D15 D14 D13 D12 D11 D10 D9 D8 D7
Kojto	90:cb3d968589d8	701	* D6 D5 D4 D3 D2 D1 D0 Format 16-bit differential S D D D D D D D D D D D D D D D
Kojto	90:cb3d968589d8	702	* Signed 2's complement 16-bit single-ended D D D D D D D D D D D D D D D D
Kojto	90:cb3d968589d8	703	* Unsigned right justified 13-bit differential S S S S D D D D D D D D D D D D
Kojto	90:cb3d968589d8	704	* Sign-extended 2's complement 12-bit single-ended 0 0 0 0 D D D D D D D D D D D D
Kojto	90:cb3d968589d8	705	* Unsigned right-justified 11-bit differential S S S S S S D D D D D D D D D D
Kojto	90:cb3d968589d8	706	* Sign-extended 2's complement 10-bit single-ended 0 0 0 0 0 0 D D D D D D D D D D
Kojto	90:cb3d968589d8	707	* Unsigned right-justified 9-bit differential S S S S S S S S D D D D D D D D
Kojto	90:cb3d968589d8	708	* Sign-extended 2's complement 8-bit single-ended 0 0 0 0 0 0 0 0 D D D D D D D D
Kojto	90:cb3d968589d8	709	* Unsigned right-justified S: Sign bit or sign bit extension; D: Data, which is
Kojto	90:cb3d968589d8	710	* 2's complement data if indicated
Kojto	90:cb3d968589d8	711	*/
Kojto	90:cb3d968589d8	712	typedef union _hw_adc_rn
Kojto	90:cb3d968589d8	713	{
Kojto	90:cb3d968589d8	714	uint32_t U;
Kojto	90:cb3d968589d8	715	struct _hw_adc_rn_bitfields
Kojto	90:cb3d968589d8	716	{
Kojto	90:cb3d968589d8	717	uint32_t D : 16; /!< [15:0] Data result /
Kojto	90:cb3d968589d8	718	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	719	} B;
Kojto	90:cb3d968589d8	720	} hw_adc_rn_t;
Kojto	90:cb3d968589d8	721
Kojto	90:cb3d968589d8	722	/*!
Kojto	90:cb3d968589d8	723	* @name Constants and macros for entire ADC_Rn register
Kojto	90:cb3d968589d8	724	*/
Kojto	90:cb3d968589d8	725	/@{/
Kojto	90:cb3d968589d8	726	#define HW_ADC_Rn_COUNT (2U)
Kojto	90:cb3d968589d8	727
Kojto	90:cb3d968589d8	728	#define HW_ADC_Rn_ADDR(x, n) ((x) + 0x10U + (0x4U * (n)))
Kojto	90:cb3d968589d8	729
Kojto	90:cb3d968589d8	730	#define HW_ADC_Rn(x, n) ((__I hw_adc_rn_t ) HW_ADC_Rn_ADDR(x, n))
Kojto	90:cb3d968589d8	731	#define HW_ADC_Rn_RD(x, n) (HW_ADC_Rn(x, n).U)
Kojto	90:cb3d968589d8	732	/@}/
Kojto	90:cb3d968589d8	733
Kojto	90:cb3d968589d8	734	/*
Kojto	90:cb3d968589d8	735	* Constants & macros for individual ADC_Rn bitfields
Kojto	90:cb3d968589d8	736	*/
Kojto	90:cb3d968589d8	737
Kojto	90:cb3d968589d8	738	/*!
Kojto	90:cb3d968589d8	739	* @name Register ADC_Rn, field D[15:0] (RO)
Kojto	90:cb3d968589d8	740	*/
Kojto	90:cb3d968589d8	741	/@{/
Kojto	90:cb3d968589d8	742	#define BP_ADC_Rn_D (0U) /!< Bit position for ADC_Rn_D. /
Kojto	90:cb3d968589d8	743	#define BM_ADC_Rn_D (0x0000FFFFU) /!< Bit mask for ADC_Rn_D. /
Kojto	90:cb3d968589d8	744	#define BS_ADC_Rn_D (16U) /!< Bit field size in bits for ADC_Rn_D. /
Kojto	90:cb3d968589d8	745
Kojto	90:cb3d968589d8	746	/! @brief Read current value of the ADC_Rn_D field. /
Kojto	90:cb3d968589d8	747	#define BR_ADC_Rn_D(x, n) (HW_ADC_Rn(x, n).B.D)
Kojto	90:cb3d968589d8	748	/@}/
Kojto	90:cb3d968589d8	749
Kojto	90:cb3d968589d8	750	/*******************************************************************************
Kojto	90:cb3d968589d8	751	* HW_ADC_CV1 - Compare Value Registers
Kojto	90:cb3d968589d8	752	******************************************************************************/
Kojto	90:cb3d968589d8	753
Kojto	90:cb3d968589d8	754	/*!
Kojto	90:cb3d968589d8	755	* @brief HW_ADC_CV1 - Compare Value Registers (RW)
Kojto	90:cb3d968589d8	756	*
Kojto	90:cb3d968589d8	757	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	758	*
Kojto	90:cb3d968589d8	759	* The Compare Value Registers (CV1 and CV2) contain a compare value used to
Kojto	90:cb3d968589d8	760	* compare the conversion result when the compare function is enabled, that is,
Kojto	90:cb3d968589d8	761	* SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
Kojto	90:cb3d968589d8	762	* different modes of operation for both bit position definition and value format
Kojto	90:cb3d968589d8	763	* using unsigned or sign-extended 2's complement. Therefore, the compare function
Kojto	90:cb3d968589d8	764	* uses only the CVn fields that are related to the ADC mode of operation. The
Kojto	90:cb3d968589d8	765	* compare value 2 register (CV2) is used only when the compare range function is
Kojto	90:cb3d968589d8	766	* enabled, that is, SC2[ACREN]=1.
Kojto	90:cb3d968589d8	767	*/
Kojto	90:cb3d968589d8	768	typedef union _hw_adc_cv1
Kojto	90:cb3d968589d8	769	{
Kojto	90:cb3d968589d8	770	uint32_t U;
Kojto	90:cb3d968589d8	771	struct _hw_adc_cv1_bitfields
Kojto	90:cb3d968589d8	772	{
Kojto	90:cb3d968589d8	773	uint32_t CV : 16; /!< [15:0] Compare Value. /
Kojto	90:cb3d968589d8	774	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	775	} B;
Kojto	90:cb3d968589d8	776	} hw_adc_cv1_t;
Kojto	90:cb3d968589d8	777
Kojto	90:cb3d968589d8	778	/*!
Kojto	90:cb3d968589d8	779	* @name Constants and macros for entire ADC_CV1 register
Kojto	90:cb3d968589d8	780	*/
Kojto	90:cb3d968589d8	781	/@{/
Kojto	90:cb3d968589d8	782	#define HW_ADC_CV1_ADDR(x) ((x) + 0x18U)
Kojto	90:cb3d968589d8	783
Kojto	90:cb3d968589d8	784	#define HW_ADC_CV1(x) ((__IO hw_adc_cv1_t ) HW_ADC_CV1_ADDR(x))
Kojto	90:cb3d968589d8	785	#define HW_ADC_CV1_RD(x) (HW_ADC_CV1(x).U)
Kojto	90:cb3d968589d8	786	#define HW_ADC_CV1_WR(x, v) (HW_ADC_CV1(x).U = (v))
Kojto	90:cb3d968589d8	787	#define HW_ADC_CV1_SET(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) \| (v)))
Kojto	90:cb3d968589d8	788	#define HW_ADC_CV1_CLR(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	789	#define HW_ADC_CV1_TOG(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	790	/@}/
Kojto	90:cb3d968589d8	791
Kojto	90:cb3d968589d8	792	/*
Kojto	90:cb3d968589d8	793	* Constants & macros for individual ADC_CV1 bitfields
Kojto	90:cb3d968589d8	794	*/
Kojto	90:cb3d968589d8	795
Kojto	90:cb3d968589d8	796	/*!
Kojto	90:cb3d968589d8	797	* @name Register ADC_CV1, field CV[15:0] (RW)
Kojto	90:cb3d968589d8	798	*/
Kojto	90:cb3d968589d8	799	/@{/
Kojto	90:cb3d968589d8	800	#define BP_ADC_CV1_CV (0U) /!< Bit position for ADC_CV1_CV. /
Kojto	90:cb3d968589d8	801	#define BM_ADC_CV1_CV (0x0000FFFFU) /!< Bit mask for ADC_CV1_CV. /
Kojto	90:cb3d968589d8	802	#define BS_ADC_CV1_CV (16U) /!< Bit field size in bits for ADC_CV1_CV. /
Kojto	90:cb3d968589d8	803
Kojto	90:cb3d968589d8	804	/! @brief Read current value of the ADC_CV1_CV field. /
Kojto	90:cb3d968589d8	805	#define BR_ADC_CV1_CV(x) (HW_ADC_CV1(x).B.CV)
Kojto	90:cb3d968589d8	806
Kojto	90:cb3d968589d8	807	/! @brief Format value for bitfield ADC_CV1_CV. /
Kojto	90:cb3d968589d8	808	#define BF_ADC_CV1_CV(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CV1_CV) & BM_ADC_CV1_CV)
Kojto	90:cb3d968589d8	809
Kojto	90:cb3d968589d8	810	/! @brief Set the CV field to a new value. /
Kojto	90:cb3d968589d8	811	#define BW_ADC_CV1_CV(x, v) (HW_ADC_CV1_WR(x, (HW_ADC_CV1_RD(x) & ~BM_ADC_CV1_CV) \| BF_ADC_CV1_CV(v)))
Kojto	90:cb3d968589d8	812	/@}/
Kojto	90:cb3d968589d8	813
Kojto	90:cb3d968589d8	814	/*******************************************************************************
Kojto	90:cb3d968589d8	815	* HW_ADC_CV2 - Compare Value Registers
Kojto	90:cb3d968589d8	816	******************************************************************************/
Kojto	90:cb3d968589d8	817
Kojto	90:cb3d968589d8	818	/*!
Kojto	90:cb3d968589d8	819	* @brief HW_ADC_CV2 - Compare Value Registers (RW)
Kojto	90:cb3d968589d8	820	*
Kojto	90:cb3d968589d8	821	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	822	*
Kojto	90:cb3d968589d8	823	* The Compare Value Registers (CV1 and CV2) contain a compare value used to
Kojto	90:cb3d968589d8	824	* compare the conversion result when the compare function is enabled, that is,
Kojto	90:cb3d968589d8	825	* SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
Kojto	90:cb3d968589d8	826	* different modes of operation for both bit position definition and value format
Kojto	90:cb3d968589d8	827	* using unsigned or sign-extended 2's complement. Therefore, the compare function
Kojto	90:cb3d968589d8	828	* uses only the CVn fields that are related to the ADC mode of operation. The
Kojto	90:cb3d968589d8	829	* compare value 2 register (CV2) is used only when the compare range function is
Kojto	90:cb3d968589d8	830	* enabled, that is, SC2[ACREN]=1.
Kojto	90:cb3d968589d8	831	*/
Kojto	90:cb3d968589d8	832	typedef union _hw_adc_cv2
Kojto	90:cb3d968589d8	833	{
Kojto	90:cb3d968589d8	834	uint32_t U;
Kojto	90:cb3d968589d8	835	struct _hw_adc_cv2_bitfields
Kojto	90:cb3d968589d8	836	{
Kojto	90:cb3d968589d8	837	uint32_t CV : 16; /!< [15:0] Compare Value. /
Kojto	90:cb3d968589d8	838	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	839	} B;
Kojto	90:cb3d968589d8	840	} hw_adc_cv2_t;
Kojto	90:cb3d968589d8	841
Kojto	90:cb3d968589d8	842	/*!
Kojto	90:cb3d968589d8	843	* @name Constants and macros for entire ADC_CV2 register
Kojto	90:cb3d968589d8	844	*/
Kojto	90:cb3d968589d8	845	/@{/
Kojto	90:cb3d968589d8	846	#define HW_ADC_CV2_ADDR(x) ((x) + 0x1CU)
Kojto	90:cb3d968589d8	847
Kojto	90:cb3d968589d8	848	#define HW_ADC_CV2(x) ((__IO hw_adc_cv2_t ) HW_ADC_CV2_ADDR(x))
Kojto	90:cb3d968589d8	849	#define HW_ADC_CV2_RD(x) (HW_ADC_CV2(x).U)
Kojto	90:cb3d968589d8	850	#define HW_ADC_CV2_WR(x, v) (HW_ADC_CV2(x).U = (v))
Kojto	90:cb3d968589d8	851	#define HW_ADC_CV2_SET(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) \| (v)))
Kojto	90:cb3d968589d8	852	#define HW_ADC_CV2_CLR(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	853	#define HW_ADC_CV2_TOG(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	854	/@}/
Kojto	90:cb3d968589d8	855
Kojto	90:cb3d968589d8	856	/*
Kojto	90:cb3d968589d8	857	* Constants & macros for individual ADC_CV2 bitfields
Kojto	90:cb3d968589d8	858	*/
Kojto	90:cb3d968589d8	859
Kojto	90:cb3d968589d8	860	/*!
Kojto	90:cb3d968589d8	861	* @name Register ADC_CV2, field CV[15:0] (RW)
Kojto	90:cb3d968589d8	862	*/
Kojto	90:cb3d968589d8	863	/@{/
Kojto	90:cb3d968589d8	864	#define BP_ADC_CV2_CV (0U) /!< Bit position for ADC_CV2_CV. /
Kojto	90:cb3d968589d8	865	#define BM_ADC_CV2_CV (0x0000FFFFU) /!< Bit mask for ADC_CV2_CV. /
Kojto	90:cb3d968589d8	866	#define BS_ADC_CV2_CV (16U) /!< Bit field size in bits for ADC_CV2_CV. /
Kojto	90:cb3d968589d8	867
Kojto	90:cb3d968589d8	868	/! @brief Read current value of the ADC_CV2_CV field. /
Kojto	90:cb3d968589d8	869	#define BR_ADC_CV2_CV(x) (HW_ADC_CV2(x).B.CV)
Kojto	90:cb3d968589d8	870
Kojto	90:cb3d968589d8	871	/! @brief Format value for bitfield ADC_CV2_CV. /
Kojto	90:cb3d968589d8	872	#define BF_ADC_CV2_CV(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CV2_CV) & BM_ADC_CV2_CV)
Kojto	90:cb3d968589d8	873
Kojto	90:cb3d968589d8	874	/! @brief Set the CV field to a new value. /
Kojto	90:cb3d968589d8	875	#define BW_ADC_CV2_CV(x, v) (HW_ADC_CV2_WR(x, (HW_ADC_CV2_RD(x) & ~BM_ADC_CV2_CV) \| BF_ADC_CV2_CV(v)))
Kojto	90:cb3d968589d8	876	/@}/
Kojto	90:cb3d968589d8	877
Kojto	90:cb3d968589d8	878	/*******************************************************************************
Kojto	90:cb3d968589d8	879	* HW_ADC_SC2 - Status and Control Register 2
Kojto	90:cb3d968589d8	880	******************************************************************************/
Kojto	90:cb3d968589d8	881
Kojto	90:cb3d968589d8	882	/*!
Kojto	90:cb3d968589d8	883	* @brief HW_ADC_SC2 - Status and Control Register 2 (RW)
Kojto	90:cb3d968589d8	884	*
Kojto	90:cb3d968589d8	885	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	886	*
Kojto	90:cb3d968589d8	887	* The status and control register 2 (SC2) contains the conversion active,
Kojto	90:cb3d968589d8	888	* hardware/software trigger select, compare function, and voltage reference select of
Kojto	90:cb3d968589d8	889	* the ADC module.
Kojto	90:cb3d968589d8	890	*/
Kojto	90:cb3d968589d8	891	typedef union _hw_adc_sc2
Kojto	90:cb3d968589d8	892	{
Kojto	90:cb3d968589d8	893	uint32_t U;
Kojto	90:cb3d968589d8	894	struct _hw_adc_sc2_bitfields
Kojto	90:cb3d968589d8	895	{
Kojto	90:cb3d968589d8	896	uint32_t REFSEL : 2; /!< [1:0] Voltage Reference Selection /
Kojto	90:cb3d968589d8	897	uint32_t DMAEN : 1; /!< [2] DMA Enable /
Kojto	90:cb3d968589d8	898	uint32_t ACREN : 1; /!< [3] Compare Function Range Enable /
Kojto	90:cb3d968589d8	899	uint32_t ACFGT : 1; /!< [4] Compare Function Greater Than Enable /
Kojto	90:cb3d968589d8	900	uint32_t ACFE : 1; /!< [5] Compare Function Enable /
Kojto	90:cb3d968589d8	901	uint32_t ADTRG : 1; /!< [6] Conversion Trigger Select /
Kojto	90:cb3d968589d8	902	uint32_t ADACT : 1; /!< [7] Conversion Active /
Kojto	90:cb3d968589d8	903	uint32_t RESERVED0 : 24; /!< [31:8] /
Kojto	90:cb3d968589d8	904	} B;
Kojto	90:cb3d968589d8	905	} hw_adc_sc2_t;
Kojto	90:cb3d968589d8	906
Kojto	90:cb3d968589d8	907	/*!
Kojto	90:cb3d968589d8	908	* @name Constants and macros for entire ADC_SC2 register
Kojto	90:cb3d968589d8	909	*/
Kojto	90:cb3d968589d8	910	/@{/
Kojto	90:cb3d968589d8	911	#define HW_ADC_SC2_ADDR(x) ((x) + 0x20U)
Kojto	90:cb3d968589d8	912
Kojto	90:cb3d968589d8	913	#define HW_ADC_SC2(x) ((__IO hw_adc_sc2_t ) HW_ADC_SC2_ADDR(x))
Kojto	90:cb3d968589d8	914	#define HW_ADC_SC2_RD(x) (HW_ADC_SC2(x).U)
Kojto	90:cb3d968589d8	915	#define HW_ADC_SC2_WR(x, v) (HW_ADC_SC2(x).U = (v))
Kojto	90:cb3d968589d8	916	#define HW_ADC_SC2_SET(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) \| (v)))
Kojto	90:cb3d968589d8	917	#define HW_ADC_SC2_CLR(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	918	#define HW_ADC_SC2_TOG(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	919	/@}/
Kojto	90:cb3d968589d8	920
Kojto	90:cb3d968589d8	921	/*
Kojto	90:cb3d968589d8	922	* Constants & macros for individual ADC_SC2 bitfields
Kojto	90:cb3d968589d8	923	*/
Kojto	90:cb3d968589d8	924
Kojto	90:cb3d968589d8	925	/*!
Kojto	90:cb3d968589d8	926	* @name Register ADC_SC2, field REFSEL[1:0] (RW)
Kojto	90:cb3d968589d8	927	*
Kojto	90:cb3d968589d8	928	* Selects the voltage reference source used for conversions.
Kojto	90:cb3d968589d8	929	*
Kojto	90:cb3d968589d8	930	* Values:
Kojto	90:cb3d968589d8	931	* - 00 - Default voltage reference pin pair, that is, external pins VREFH and
Kojto	90:cb3d968589d8	932	* VREFL
Kojto	90:cb3d968589d8	933	* - 01 - Alternate reference pair, that is, VALTH and VALTL . This pair may be
Kojto	90:cb3d968589d8	934	* additional external pins or internal sources depending on the MCU
Kojto	90:cb3d968589d8	935	* configuration. See the chip configuration information for details specific to this
Kojto	90:cb3d968589d8	936	* MCU
Kojto	90:cb3d968589d8	937	* - 10 - Reserved
Kojto	90:cb3d968589d8	938	* - 11 - Reserved
Kojto	90:cb3d968589d8	939	*/
Kojto	90:cb3d968589d8	940	/@{/
Kojto	90:cb3d968589d8	941	#define BP_ADC_SC2_REFSEL (0U) /!< Bit position for ADC_SC2_REFSEL. /
Kojto	90:cb3d968589d8	942	#define BM_ADC_SC2_REFSEL (0x00000003U) /!< Bit mask for ADC_SC2_REFSEL. /
Kojto	90:cb3d968589d8	943	#define BS_ADC_SC2_REFSEL (2U) /!< Bit field size in bits for ADC_SC2_REFSEL. /
Kojto	90:cb3d968589d8	944
Kojto	90:cb3d968589d8	945	/! @brief Read current value of the ADC_SC2_REFSEL field. /
Kojto	90:cb3d968589d8	946	#define BR_ADC_SC2_REFSEL(x) (HW_ADC_SC2(x).B.REFSEL)
Kojto	90:cb3d968589d8	947
Kojto	90:cb3d968589d8	948	/! @brief Format value for bitfield ADC_SC2_REFSEL. /
Kojto	90:cb3d968589d8	949	#define BF_ADC_SC2_REFSEL(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_REFSEL) & BM_ADC_SC2_REFSEL)
Kojto	90:cb3d968589d8	950
Kojto	90:cb3d968589d8	951	/! @brief Set the REFSEL field to a new value. /
Kojto	90:cb3d968589d8	952	#define BW_ADC_SC2_REFSEL(x, v) (HW_ADC_SC2_WR(x, (HW_ADC_SC2_RD(x) & ~BM_ADC_SC2_REFSEL) \| BF_ADC_SC2_REFSEL(v)))
Kojto	90:cb3d968589d8	953	/@}/
Kojto	90:cb3d968589d8	954
Kojto	90:cb3d968589d8	955	/*!
Kojto	90:cb3d968589d8	956	* @name Register ADC_SC2, field DMAEN[2] (RW)
Kojto	90:cb3d968589d8	957	*
Kojto	90:cb3d968589d8	958	* Values:
Kojto	90:cb3d968589d8	959	* - 0 - DMA is disabled.
Kojto	90:cb3d968589d8	960	* - 1 - DMA is enabled and will assert the ADC DMA request during an ADC
Kojto	90:cb3d968589d8	961	* conversion complete event noted when any of the SC1n[COCO] flags is asserted.
Kojto	90:cb3d968589d8	962	*/
Kojto	90:cb3d968589d8	963	/@{/
Kojto	90:cb3d968589d8	964	#define BP_ADC_SC2_DMAEN (2U) /!< Bit position for ADC_SC2_DMAEN. /
Kojto	90:cb3d968589d8	965	#define BM_ADC_SC2_DMAEN (0x00000004U) /!< Bit mask for ADC_SC2_DMAEN. /
Kojto	90:cb3d968589d8	966	#define BS_ADC_SC2_DMAEN (1U) /!< Bit field size in bits for ADC_SC2_DMAEN. /
Kojto	90:cb3d968589d8	967
Kojto	90:cb3d968589d8	968	/! @brief Read current value of the ADC_SC2_DMAEN field. /
Kojto	90:cb3d968589d8	969	#define BR_ADC_SC2_DMAEN(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_DMAEN))
Kojto	90:cb3d968589d8	970
Kojto	90:cb3d968589d8	971	/! @brief Format value for bitfield ADC_SC2_DMAEN. /
Kojto	90:cb3d968589d8	972	#define BF_ADC_SC2_DMAEN(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_DMAEN) & BM_ADC_SC2_DMAEN)
Kojto	90:cb3d968589d8	973
Kojto	90:cb3d968589d8	974	/! @brief Set the DMAEN field to a new value. /
Kojto	90:cb3d968589d8	975	#define BW_ADC_SC2_DMAEN(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_DMAEN) = (v))
Kojto	90:cb3d968589d8	976	/@}/
Kojto	90:cb3d968589d8	977
Kojto	90:cb3d968589d8	978	/*!
Kojto	90:cb3d968589d8	979	* @name Register ADC_SC2, field ACREN[3] (RW)
Kojto	90:cb3d968589d8	980	*
Kojto	90:cb3d968589d8	981	* Configures the compare function to check if the conversion result of the
Kojto	90:cb3d968589d8	982	* input being monitored is either between or outside the range formed by CV1 and CV2
Kojto	90:cb3d968589d8	983	* determined by the value of ACFGT. ACFE must be set for ACFGT to have any
Kojto	90:cb3d968589d8	984	* effect.
Kojto	90:cb3d968589d8	985	*
Kojto	90:cb3d968589d8	986	* Values:
Kojto	90:cb3d968589d8	987	* - 0 - Range function disabled. Only CV1 is compared.
Kojto	90:cb3d968589d8	988	* - 1 - Range function enabled. Both CV1 and CV2 are compared.
Kojto	90:cb3d968589d8	989	*/
Kojto	90:cb3d968589d8	990	/@{/
Kojto	90:cb3d968589d8	991	#define BP_ADC_SC2_ACREN (3U) /!< Bit position for ADC_SC2_ACREN. /
Kojto	90:cb3d968589d8	992	#define BM_ADC_SC2_ACREN (0x00000008U) /!< Bit mask for ADC_SC2_ACREN. /
Kojto	90:cb3d968589d8	993	#define BS_ADC_SC2_ACREN (1U) /!< Bit field size in bits for ADC_SC2_ACREN. /
Kojto	90:cb3d968589d8	994
Kojto	90:cb3d968589d8	995	/! @brief Read current value of the ADC_SC2_ACREN field. /
Kojto	90:cb3d968589d8	996	#define BR_ADC_SC2_ACREN(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACREN))
Kojto	90:cb3d968589d8	997
Kojto	90:cb3d968589d8	998	/! @brief Format value for bitfield ADC_SC2_ACREN. /
Kojto	90:cb3d968589d8	999	#define BF_ADC_SC2_ACREN(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ACREN) & BM_ADC_SC2_ACREN)
Kojto	90:cb3d968589d8	1000
Kojto	90:cb3d968589d8	1001	/! @brief Set the ACREN field to a new value. /
Kojto	90:cb3d968589d8	1002	#define BW_ADC_SC2_ACREN(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACREN) = (v))
Kojto	90:cb3d968589d8	1003	/@}/
Kojto	90:cb3d968589d8	1004
Kojto	90:cb3d968589d8	1005	/*!
Kojto	90:cb3d968589d8	1006	* @name Register ADC_SC2, field ACFGT[4] (RW)
Kojto	90:cb3d968589d8	1007	*
Kojto	90:cb3d968589d8	1008	* Configures the compare function to check the conversion result relative to
Kojto	90:cb3d968589d8	1009	* the CV1 and CV2 based upon the value of ACREN. ACFE must be set for ACFGT to
Kojto	90:cb3d968589d8	1010	* have any effect.
Kojto	90:cb3d968589d8	1011	*
Kojto	90:cb3d968589d8	1012	* Values:
Kojto	90:cb3d968589d8	1013	* - 0 - Configures less than threshold, outside range not inclusive and inside
Kojto	90:cb3d968589d8	1014	* range not inclusive; functionality based on the values placed in CV1 and
Kojto	90:cb3d968589d8	1015	* CV2.
Kojto	90:cb3d968589d8	1016	* - 1 - Configures greater than or equal to threshold, outside and inside
Kojto	90:cb3d968589d8	1017	* ranges inclusive; functionality based on the values placed in CV1 and CV2.
Kojto	90:cb3d968589d8	1018	*/
Kojto	90:cb3d968589d8	1019	/@{/
Kojto	90:cb3d968589d8	1020	#define BP_ADC_SC2_ACFGT (4U) /!< Bit position for ADC_SC2_ACFGT. /
Kojto	90:cb3d968589d8	1021	#define BM_ADC_SC2_ACFGT (0x00000010U) /!< Bit mask for ADC_SC2_ACFGT. /
Kojto	90:cb3d968589d8	1022	#define BS_ADC_SC2_ACFGT (1U) /!< Bit field size in bits for ADC_SC2_ACFGT. /
Kojto	90:cb3d968589d8	1023
Kojto	90:cb3d968589d8	1024	/! @brief Read current value of the ADC_SC2_ACFGT field. /
Kojto	90:cb3d968589d8	1025	#define BR_ADC_SC2_ACFGT(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFGT))
Kojto	90:cb3d968589d8	1026
Kojto	90:cb3d968589d8	1027	/! @brief Format value for bitfield ADC_SC2_ACFGT. /
Kojto	90:cb3d968589d8	1028	#define BF_ADC_SC2_ACFGT(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ACFGT) & BM_ADC_SC2_ACFGT)
Kojto	90:cb3d968589d8	1029
Kojto	90:cb3d968589d8	1030	/! @brief Set the ACFGT field to a new value. /
Kojto	90:cb3d968589d8	1031	#define BW_ADC_SC2_ACFGT(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFGT) = (v))
Kojto	90:cb3d968589d8	1032	/@}/
Kojto	90:cb3d968589d8	1033
Kojto	90:cb3d968589d8	1034	/*!
Kojto	90:cb3d968589d8	1035	* @name Register ADC_SC2, field ACFE[5] (RW)
Kojto	90:cb3d968589d8	1036	*
Kojto	90:cb3d968589d8	1037	* Enables the compare function.
Kojto	90:cb3d968589d8	1038	*
Kojto	90:cb3d968589d8	1039	* Values:
Kojto	90:cb3d968589d8	1040	* - 0 - Compare function disabled.
Kojto	90:cb3d968589d8	1041	* - 1 - Compare function enabled.
Kojto	90:cb3d968589d8	1042	*/
Kojto	90:cb3d968589d8	1043	/@{/
Kojto	90:cb3d968589d8	1044	#define BP_ADC_SC2_ACFE (5U) /!< Bit position for ADC_SC2_ACFE. /
Kojto	90:cb3d968589d8	1045	#define BM_ADC_SC2_ACFE (0x00000020U) /!< Bit mask for ADC_SC2_ACFE. /
Kojto	90:cb3d968589d8	1046	#define BS_ADC_SC2_ACFE (1U) /!< Bit field size in bits for ADC_SC2_ACFE. /
Kojto	90:cb3d968589d8	1047
Kojto	90:cb3d968589d8	1048	/! @brief Read current value of the ADC_SC2_ACFE field. /
Kojto	90:cb3d968589d8	1049	#define BR_ADC_SC2_ACFE(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFE))
Kojto	90:cb3d968589d8	1050
Kojto	90:cb3d968589d8	1051	/! @brief Format value for bitfield ADC_SC2_ACFE. /
Kojto	90:cb3d968589d8	1052	#define BF_ADC_SC2_ACFE(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ACFE) & BM_ADC_SC2_ACFE)
Kojto	90:cb3d968589d8	1053
Kojto	90:cb3d968589d8	1054	/! @brief Set the ACFE field to a new value. /
Kojto	90:cb3d968589d8	1055	#define BW_ADC_SC2_ACFE(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFE) = (v))
Kojto	90:cb3d968589d8	1056	/@}/
Kojto	90:cb3d968589d8	1057
Kojto	90:cb3d968589d8	1058	/*!
Kojto	90:cb3d968589d8	1059	* @name Register ADC_SC2, field ADTRG[6] (RW)
Kojto	90:cb3d968589d8	1060	*
Kojto	90:cb3d968589d8	1061	* Selects the type of trigger used for initiating a conversion. Two types of
Kojto	90:cb3d968589d8	1062	* trigger are selectable: Software trigger: When software trigger is selected, a
Kojto	90:cb3d968589d8	1063	* conversion is initiated following a write to SC1A. Hardware trigger: When
Kojto	90:cb3d968589d8	1064	* hardware trigger is selected, a conversion is initiated following the assertion of
Kojto	90:cb3d968589d8	1065	* the ADHWT input after a pulse of the ADHWTSn input.
Kojto	90:cb3d968589d8	1066	*
Kojto	90:cb3d968589d8	1067	* Values:
Kojto	90:cb3d968589d8	1068	* - 0 - Software trigger selected.
Kojto	90:cb3d968589d8	1069	* - 1 - Hardware trigger selected.
Kojto	90:cb3d968589d8	1070	*/
Kojto	90:cb3d968589d8	1071	/@{/
Kojto	90:cb3d968589d8	1072	#define BP_ADC_SC2_ADTRG (6U) /!< Bit position for ADC_SC2_ADTRG. /
Kojto	90:cb3d968589d8	1073	#define BM_ADC_SC2_ADTRG (0x00000040U) /!< Bit mask for ADC_SC2_ADTRG. /
Kojto	90:cb3d968589d8	1074	#define BS_ADC_SC2_ADTRG (1U) /!< Bit field size in bits for ADC_SC2_ADTRG. /
Kojto	90:cb3d968589d8	1075
Kojto	90:cb3d968589d8	1076	/! @brief Read current value of the ADC_SC2_ADTRG field. /
Kojto	90:cb3d968589d8	1077	#define BR_ADC_SC2_ADTRG(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADTRG))
Kojto	90:cb3d968589d8	1078
Kojto	90:cb3d968589d8	1079	/! @brief Format value for bitfield ADC_SC2_ADTRG. /
Kojto	90:cb3d968589d8	1080	#define BF_ADC_SC2_ADTRG(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ADTRG) & BM_ADC_SC2_ADTRG)
Kojto	90:cb3d968589d8	1081
Kojto	90:cb3d968589d8	1082	/! @brief Set the ADTRG field to a new value. /
Kojto	90:cb3d968589d8	1083	#define BW_ADC_SC2_ADTRG(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADTRG) = (v))
Kojto	90:cb3d968589d8	1084	/@}/
Kojto	90:cb3d968589d8	1085
Kojto	90:cb3d968589d8	1086	/*!
Kojto	90:cb3d968589d8	1087	* @name Register ADC_SC2, field ADACT[7] (RO)
Kojto	90:cb3d968589d8	1088	*
Kojto	90:cb3d968589d8	1089	* Indicates that a conversion or hardware averaging is in progress. ADACT is
Kojto	90:cb3d968589d8	1090	* set when a conversion is initiated and cleared when a conversion is completed or
Kojto	90:cb3d968589d8	1091	* aborted.
Kojto	90:cb3d968589d8	1092	*
Kojto	90:cb3d968589d8	1093	* Values:
Kojto	90:cb3d968589d8	1094	* - 0 - Conversion not in progress.
Kojto	90:cb3d968589d8	1095	* - 1 - Conversion in progress.
Kojto	90:cb3d968589d8	1096	*/
Kojto	90:cb3d968589d8	1097	/@{/
Kojto	90:cb3d968589d8	1098	#define BP_ADC_SC2_ADACT (7U) /!< Bit position for ADC_SC2_ADACT. /
Kojto	90:cb3d968589d8	1099	#define BM_ADC_SC2_ADACT (0x00000080U) /!< Bit mask for ADC_SC2_ADACT. /
Kojto	90:cb3d968589d8	1100	#define BS_ADC_SC2_ADACT (1U) /!< Bit field size in bits for ADC_SC2_ADACT. /
Kojto	90:cb3d968589d8	1101
Kojto	90:cb3d968589d8	1102	/! @brief Read current value of the ADC_SC2_ADACT field. /
Kojto	90:cb3d968589d8	1103	#define BR_ADC_SC2_ADACT(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADACT))
Kojto	90:cb3d968589d8	1104	/@}/
Kojto	90:cb3d968589d8	1105
Kojto	90:cb3d968589d8	1106	/*******************************************************************************
Kojto	90:cb3d968589d8	1107	* HW_ADC_SC3 - Status and Control Register 3
Kojto	90:cb3d968589d8	1108	******************************************************************************/
Kojto	90:cb3d968589d8	1109
Kojto	90:cb3d968589d8	1110	/*!
Kojto	90:cb3d968589d8	1111	* @brief HW_ADC_SC3 - Status and Control Register 3 (RW)
Kojto	90:cb3d968589d8	1112	*
Kojto	90:cb3d968589d8	1113	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1114	*
Kojto	90:cb3d968589d8	1115	* The Status and Control Register 3 (SC3) controls the calibration, continuous
Kojto	90:cb3d968589d8	1116	* convert, and hardware averaging functions of the ADC module.
Kojto	90:cb3d968589d8	1117	*/
Kojto	90:cb3d968589d8	1118	typedef union _hw_adc_sc3
Kojto	90:cb3d968589d8	1119	{
Kojto	90:cb3d968589d8	1120	uint32_t U;
Kojto	90:cb3d968589d8	1121	struct _hw_adc_sc3_bitfields
Kojto	90:cb3d968589d8	1122	{
Kojto	90:cb3d968589d8	1123	uint32_t AVGS : 2; /!< [1:0] Hardware Average Select /
Kojto	90:cb3d968589d8	1124	uint32_t AVGE : 1; /!< [2] Hardware Average Enable /
Kojto	90:cb3d968589d8	1125	uint32_t ADCO : 1; /!< [3] Continuous Conversion Enable /
Kojto	90:cb3d968589d8	1126	uint32_t RESERVED0 : 2; /!< [5:4] /
Kojto	90:cb3d968589d8	1127	uint32_t CALF : 1; /!< [6] Calibration Failed Flag /
Kojto	90:cb3d968589d8	1128	uint32_t CAL : 1; /!< [7] Calibration /
Kojto	90:cb3d968589d8	1129	uint32_t RESERVED1 : 24; /!< [31:8] /
Kojto	90:cb3d968589d8	1130	} B;
Kojto	90:cb3d968589d8	1131	} hw_adc_sc3_t;
Kojto	90:cb3d968589d8	1132
Kojto	90:cb3d968589d8	1133	/*!
Kojto	90:cb3d968589d8	1134	* @name Constants and macros for entire ADC_SC3 register
Kojto	90:cb3d968589d8	1135	*/
Kojto	90:cb3d968589d8	1136	/@{/
Kojto	90:cb3d968589d8	1137	#define HW_ADC_SC3_ADDR(x) ((x) + 0x24U)
Kojto	90:cb3d968589d8	1138
Kojto	90:cb3d968589d8	1139	#define HW_ADC_SC3(x) ((__IO hw_adc_sc3_t ) HW_ADC_SC3_ADDR(x))
Kojto	90:cb3d968589d8	1140	#define HW_ADC_SC3_RD(x) (HW_ADC_SC3(x).U)
Kojto	90:cb3d968589d8	1141	#define HW_ADC_SC3_WR(x, v) (HW_ADC_SC3(x).U = (v))
Kojto	90:cb3d968589d8	1142	#define HW_ADC_SC3_SET(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1143	#define HW_ADC_SC3_CLR(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1144	#define HW_ADC_SC3_TOG(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1145	/@}/
Kojto	90:cb3d968589d8	1146
Kojto	90:cb3d968589d8	1147	/*
Kojto	90:cb3d968589d8	1148	* Constants & macros for individual ADC_SC3 bitfields
Kojto	90:cb3d968589d8	1149	*/
Kojto	90:cb3d968589d8	1150
Kojto	90:cb3d968589d8	1151	/*!
Kojto	90:cb3d968589d8	1152	* @name Register ADC_SC3, field AVGS[1:0] (RW)
Kojto	90:cb3d968589d8	1153	*
Kojto	90:cb3d968589d8	1154	* Determines how many ADC conversions will be averaged to create the ADC
Kojto	90:cb3d968589d8	1155	* average result.
Kojto	90:cb3d968589d8	1156	*
Kojto	90:cb3d968589d8	1157	* Values:
Kojto	90:cb3d968589d8	1158	* - 00 - 4 samples averaged.
Kojto	90:cb3d968589d8	1159	* - 01 - 8 samples averaged.
Kojto	90:cb3d968589d8	1160	* - 10 - 16 samples averaged.
Kojto	90:cb3d968589d8	1161	* - 11 - 32 samples averaged.
Kojto	90:cb3d968589d8	1162	*/
Kojto	90:cb3d968589d8	1163	/@{/
Kojto	90:cb3d968589d8	1164	#define BP_ADC_SC3_AVGS (0U) /!< Bit position for ADC_SC3_AVGS. /
Kojto	90:cb3d968589d8	1165	#define BM_ADC_SC3_AVGS (0x00000003U) /!< Bit mask for ADC_SC3_AVGS. /
Kojto	90:cb3d968589d8	1166	#define BS_ADC_SC3_AVGS (2U) /!< Bit field size in bits for ADC_SC3_AVGS. /
Kojto	90:cb3d968589d8	1167
Kojto	90:cb3d968589d8	1168	/! @brief Read current value of the ADC_SC3_AVGS field. /
Kojto	90:cb3d968589d8	1169	#define BR_ADC_SC3_AVGS(x) (HW_ADC_SC3(x).B.AVGS)
Kojto	90:cb3d968589d8	1170
Kojto	90:cb3d968589d8	1171	/! @brief Format value for bitfield ADC_SC3_AVGS. /
Kojto	90:cb3d968589d8	1172	#define BF_ADC_SC3_AVGS(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_AVGS) & BM_ADC_SC3_AVGS)
Kojto	90:cb3d968589d8	1173
Kojto	90:cb3d968589d8	1174	/! @brief Set the AVGS field to a new value. /
Kojto	90:cb3d968589d8	1175	#define BW_ADC_SC3_AVGS(x, v) (HW_ADC_SC3_WR(x, (HW_ADC_SC3_RD(x) & ~BM_ADC_SC3_AVGS) \| BF_ADC_SC3_AVGS(v)))
Kojto	90:cb3d968589d8	1176	/@}/
Kojto	90:cb3d968589d8	1177
Kojto	90:cb3d968589d8	1178	/*!
Kojto	90:cb3d968589d8	1179	* @name Register ADC_SC3, field AVGE[2] (RW)
Kojto	90:cb3d968589d8	1180	*
Kojto	90:cb3d968589d8	1181	* Enables the hardware average function of the ADC.
Kojto	90:cb3d968589d8	1182	*
Kojto	90:cb3d968589d8	1183	* Values:
Kojto	90:cb3d968589d8	1184	* - 0 - Hardware average function disabled.
Kojto	90:cb3d968589d8	1185	* - 1 - Hardware average function enabled.
Kojto	90:cb3d968589d8	1186	*/
Kojto	90:cb3d968589d8	1187	/@{/
Kojto	90:cb3d968589d8	1188	#define BP_ADC_SC3_AVGE (2U) /!< Bit position for ADC_SC3_AVGE. /
Kojto	90:cb3d968589d8	1189	#define BM_ADC_SC3_AVGE (0x00000004U) /!< Bit mask for ADC_SC3_AVGE. /
Kojto	90:cb3d968589d8	1190	#define BS_ADC_SC3_AVGE (1U) /!< Bit field size in bits for ADC_SC3_AVGE. /
Kojto	90:cb3d968589d8	1191
Kojto	90:cb3d968589d8	1192	/! @brief Read current value of the ADC_SC3_AVGE field. /
Kojto	90:cb3d968589d8	1193	#define BR_ADC_SC3_AVGE(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_AVGE))
Kojto	90:cb3d968589d8	1194
Kojto	90:cb3d968589d8	1195	/! @brief Format value for bitfield ADC_SC3_AVGE. /
Kojto	90:cb3d968589d8	1196	#define BF_ADC_SC3_AVGE(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_AVGE) & BM_ADC_SC3_AVGE)
Kojto	90:cb3d968589d8	1197
Kojto	90:cb3d968589d8	1198	/! @brief Set the AVGE field to a new value. /
Kojto	90:cb3d968589d8	1199	#define BW_ADC_SC3_AVGE(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_AVGE) = (v))
Kojto	90:cb3d968589d8	1200	/@}/
Kojto	90:cb3d968589d8	1201
Kojto	90:cb3d968589d8	1202	/*!
Kojto	90:cb3d968589d8	1203	* @name Register ADC_SC3, field ADCO[3] (RW)
Kojto	90:cb3d968589d8	1204	*
Kojto	90:cb3d968589d8	1205	* Enables continuous conversions.
Kojto	90:cb3d968589d8	1206	*
Kojto	90:cb3d968589d8	1207	* Values:
Kojto	90:cb3d968589d8	1208	* - 0 - One conversion or one set of conversions if the hardware average
Kojto	90:cb3d968589d8	1209	* function is enabled, that is, AVGE=1, after initiating a conversion.
Kojto	90:cb3d968589d8	1210	* - 1 - Continuous conversions or sets of conversions if the hardware average
Kojto	90:cb3d968589d8	1211	* function is enabled, that is, AVGE=1, after initiating a conversion.
Kojto	90:cb3d968589d8	1212	*/
Kojto	90:cb3d968589d8	1213	/@{/
Kojto	90:cb3d968589d8	1214	#define BP_ADC_SC3_ADCO (3U) /!< Bit position for ADC_SC3_ADCO. /
Kojto	90:cb3d968589d8	1215	#define BM_ADC_SC3_ADCO (0x00000008U) /!< Bit mask for ADC_SC3_ADCO. /
Kojto	90:cb3d968589d8	1216	#define BS_ADC_SC3_ADCO (1U) /!< Bit field size in bits for ADC_SC3_ADCO. /
Kojto	90:cb3d968589d8	1217
Kojto	90:cb3d968589d8	1218	/! @brief Read current value of the ADC_SC3_ADCO field. /
Kojto	90:cb3d968589d8	1219	#define BR_ADC_SC3_ADCO(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_ADCO))
Kojto	90:cb3d968589d8	1220
Kojto	90:cb3d968589d8	1221	/! @brief Format value for bitfield ADC_SC3_ADCO. /
Kojto	90:cb3d968589d8	1222	#define BF_ADC_SC3_ADCO(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_ADCO) & BM_ADC_SC3_ADCO)
Kojto	90:cb3d968589d8	1223
Kojto	90:cb3d968589d8	1224	/! @brief Set the ADCO field to a new value. /
Kojto	90:cb3d968589d8	1225	#define BW_ADC_SC3_ADCO(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_ADCO) = (v))
Kojto	90:cb3d968589d8	1226	/@}/
Kojto	90:cb3d968589d8	1227
Kojto	90:cb3d968589d8	1228	/*!
Kojto	90:cb3d968589d8	1229	* @name Register ADC_SC3, field CALF[6] (RO)
Kojto	90:cb3d968589d8	1230	*
Kojto	90:cb3d968589d8	1231	* Displays the result of the calibration sequence. The calibration sequence
Kojto	90:cb3d968589d8	1232	* will fail if SC2[ADTRG] = 1, any ADC register is written, or any stop mode is
Kojto	90:cb3d968589d8	1233	* entered before the calibration sequence completes. Writing 1 to CALF clears it.
Kojto	90:cb3d968589d8	1234	*
Kojto	90:cb3d968589d8	1235	* Values:
Kojto	90:cb3d968589d8	1236	* - 0 - Calibration completed normally.
Kojto	90:cb3d968589d8	1237	* - 1 - Calibration failed. ADC accuracy specifications are not guaranteed.
Kojto	90:cb3d968589d8	1238	*/
Kojto	90:cb3d968589d8	1239	/@{/
Kojto	90:cb3d968589d8	1240	#define BP_ADC_SC3_CALF (6U) /!< Bit position for ADC_SC3_CALF. /
Kojto	90:cb3d968589d8	1241	#define BM_ADC_SC3_CALF (0x00000040U) /!< Bit mask for ADC_SC3_CALF. /
Kojto	90:cb3d968589d8	1242	#define BS_ADC_SC3_CALF (1U) /!< Bit field size in bits for ADC_SC3_CALF. /
Kojto	90:cb3d968589d8	1243
Kojto	90:cb3d968589d8	1244	/! @brief Read current value of the ADC_SC3_CALF field. /
Kojto	90:cb3d968589d8	1245	#define BR_ADC_SC3_CALF(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CALF))
Kojto	90:cb3d968589d8	1246	/@}/
Kojto	90:cb3d968589d8	1247
Kojto	90:cb3d968589d8	1248	/*!
Kojto	90:cb3d968589d8	1249	* @name Register ADC_SC3, field CAL[7] (RW)
Kojto	90:cb3d968589d8	1250	*
Kojto	90:cb3d968589d8	1251	* Begins the calibration sequence when set. This field stays set while the
Kojto	90:cb3d968589d8	1252	* calibration is in progress and is cleared when the calibration sequence is
Kojto	90:cb3d968589d8	1253	* completed. CALF must be checked to determine the result of the calibration sequence.
Kojto	90:cb3d968589d8	1254	* Once started, the calibration routine cannot be interrupted by writes to the
Kojto	90:cb3d968589d8	1255	* ADC registers or the results will be invalid and CALF will set. Setting CAL
Kojto	90:cb3d968589d8	1256	* will abort any current conversion.
Kojto	90:cb3d968589d8	1257	*/
Kojto	90:cb3d968589d8	1258	/@{/
Kojto	90:cb3d968589d8	1259	#define BP_ADC_SC3_CAL (7U) /!< Bit position for ADC_SC3_CAL. /
Kojto	90:cb3d968589d8	1260	#define BM_ADC_SC3_CAL (0x00000080U) /!< Bit mask for ADC_SC3_CAL. /
Kojto	90:cb3d968589d8	1261	#define BS_ADC_SC3_CAL (1U) /!< Bit field size in bits for ADC_SC3_CAL. /
Kojto	90:cb3d968589d8	1262
Kojto	90:cb3d968589d8	1263	/! @brief Read current value of the ADC_SC3_CAL field. /
Kojto	90:cb3d968589d8	1264	#define BR_ADC_SC3_CAL(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CAL))
Kojto	90:cb3d968589d8	1265
Kojto	90:cb3d968589d8	1266	/! @brief Format value for bitfield ADC_SC3_CAL. /
Kojto	90:cb3d968589d8	1267	#define BF_ADC_SC3_CAL(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_CAL) & BM_ADC_SC3_CAL)
Kojto	90:cb3d968589d8	1268
Kojto	90:cb3d968589d8	1269	/! @brief Set the CAL field to a new value. /
Kojto	90:cb3d968589d8	1270	#define BW_ADC_SC3_CAL(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CAL) = (v))
Kojto	90:cb3d968589d8	1271	/@}/
Kojto	90:cb3d968589d8	1272
Kojto	90:cb3d968589d8	1273	/*******************************************************************************
Kojto	90:cb3d968589d8	1274	* HW_ADC_OFS - ADC Offset Correction Register
Kojto	90:cb3d968589d8	1275	******************************************************************************/
Kojto	90:cb3d968589d8	1276
Kojto	90:cb3d968589d8	1277	/*!
Kojto	90:cb3d968589d8	1278	* @brief HW_ADC_OFS - ADC Offset Correction Register (RW)
Kojto	90:cb3d968589d8	1279	*
Kojto	90:cb3d968589d8	1280	* Reset value: 0x00000004U
Kojto	90:cb3d968589d8	1281	*
Kojto	90:cb3d968589d8	1282	* The ADC Offset Correction Register (OFS) contains the user-selected or
Kojto	90:cb3d968589d8	1283	* calibration-generated offset error correction value. This register is a 2's
Kojto	90:cb3d968589d8	1284	* complement, left-justified, 16-bit value . The value in OFS is subtracted from the
Kojto	90:cb3d968589d8	1285	* conversion and the result is transferred into the result registers, Rn. If the
Kojto	90:cb3d968589d8	1286	* result is greater than the maximum or less than the minimum result value, it is
Kojto	90:cb3d968589d8	1287	* forced to the appropriate limit for the current mode of operation.
Kojto	90:cb3d968589d8	1288	*/
Kojto	90:cb3d968589d8	1289	typedef union _hw_adc_ofs
Kojto	90:cb3d968589d8	1290	{
Kojto	90:cb3d968589d8	1291	uint32_t U;
Kojto	90:cb3d968589d8	1292	struct _hw_adc_ofs_bitfields
Kojto	90:cb3d968589d8	1293	{
Kojto	90:cb3d968589d8	1294	uint32_t OFS : 16; /!< [15:0] Offset Error Correction Value /
Kojto	90:cb3d968589d8	1295	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	1296	} B;
Kojto	90:cb3d968589d8	1297	} hw_adc_ofs_t;
Kojto	90:cb3d968589d8	1298
Kojto	90:cb3d968589d8	1299	/*!
Kojto	90:cb3d968589d8	1300	* @name Constants and macros for entire ADC_OFS register
Kojto	90:cb3d968589d8	1301	*/
Kojto	90:cb3d968589d8	1302	/@{/
Kojto	90:cb3d968589d8	1303	#define HW_ADC_OFS_ADDR(x) ((x) + 0x28U)
Kojto	90:cb3d968589d8	1304
Kojto	90:cb3d968589d8	1305	#define HW_ADC_OFS(x) ((__IO hw_adc_ofs_t ) HW_ADC_OFS_ADDR(x))
Kojto	90:cb3d968589d8	1306	#define HW_ADC_OFS_RD(x) (HW_ADC_OFS(x).U)
Kojto	90:cb3d968589d8	1307	#define HW_ADC_OFS_WR(x, v) (HW_ADC_OFS(x).U = (v))
Kojto	90:cb3d968589d8	1308	#define HW_ADC_OFS_SET(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1309	#define HW_ADC_OFS_CLR(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1310	#define HW_ADC_OFS_TOG(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1311	/@}/
Kojto	90:cb3d968589d8	1312
Kojto	90:cb3d968589d8	1313	/*
Kojto	90:cb3d968589d8	1314	* Constants & macros for individual ADC_OFS bitfields
Kojto	90:cb3d968589d8	1315	*/
Kojto	90:cb3d968589d8	1316
Kojto	90:cb3d968589d8	1317	/*!
Kojto	90:cb3d968589d8	1318	* @name Register ADC_OFS, field OFS[15:0] (RW)
Kojto	90:cb3d968589d8	1319	*/
Kojto	90:cb3d968589d8	1320	/@{/
Kojto	90:cb3d968589d8	1321	#define BP_ADC_OFS_OFS (0U) /!< Bit position for ADC_OFS_OFS. /
Kojto	90:cb3d968589d8	1322	#define BM_ADC_OFS_OFS (0x0000FFFFU) /!< Bit mask for ADC_OFS_OFS. /
Kojto	90:cb3d968589d8	1323	#define BS_ADC_OFS_OFS (16U) /!< Bit field size in bits for ADC_OFS_OFS. /
Kojto	90:cb3d968589d8	1324
Kojto	90:cb3d968589d8	1325	/! @brief Read current value of the ADC_OFS_OFS field. /
Kojto	90:cb3d968589d8	1326	#define BR_ADC_OFS_OFS(x) (HW_ADC_OFS(x).B.OFS)
Kojto	90:cb3d968589d8	1327
Kojto	90:cb3d968589d8	1328	/! @brief Format value for bitfield ADC_OFS_OFS. /
Kojto	90:cb3d968589d8	1329	#define BF_ADC_OFS_OFS(v) ((uint32_t)((uint32_t)(v) << BP_ADC_OFS_OFS) & BM_ADC_OFS_OFS)
Kojto	90:cb3d968589d8	1330
Kojto	90:cb3d968589d8	1331	/! @brief Set the OFS field to a new value. /
Kojto	90:cb3d968589d8	1332	#define BW_ADC_OFS_OFS(x, v) (HW_ADC_OFS_WR(x, (HW_ADC_OFS_RD(x) & ~BM_ADC_OFS_OFS) \| BF_ADC_OFS_OFS(v)))
Kojto	90:cb3d968589d8	1333	/@}/
Kojto	90:cb3d968589d8	1334
Kojto	90:cb3d968589d8	1335	/*******************************************************************************
Kojto	90:cb3d968589d8	1336	* HW_ADC_PG - ADC Plus-Side Gain Register
Kojto	90:cb3d968589d8	1337	******************************************************************************/
Kojto	90:cb3d968589d8	1338
Kojto	90:cb3d968589d8	1339	/*!
Kojto	90:cb3d968589d8	1340	* @brief HW_ADC_PG - ADC Plus-Side Gain Register (RW)
Kojto	90:cb3d968589d8	1341	*
Kojto	90:cb3d968589d8	1342	* Reset value: 0x00008200U
Kojto	90:cb3d968589d8	1343	*
Kojto	90:cb3d968589d8	1344	* The Plus-Side Gain Register (PG) contains the gain error correction for the
Kojto	90:cb3d968589d8	1345	* plus-side input in differential mode or the overall conversion in single-ended
Kojto	90:cb3d968589d8	1346	* mode. PG, a 16-bit real number in binary format, is the gain adjustment
Kojto	90:cb3d968589d8	1347	* factor, with the radix point fixed between ADPG15 and ADPG14. This register must be
Kojto	90:cb3d968589d8	1348	* written by the user with the value described in the calibration procedure.
Kojto	90:cb3d968589d8	1349	* Otherwise, the gain error specifications may not be met.
Kojto	90:cb3d968589d8	1350	*/
Kojto	90:cb3d968589d8	1351	typedef union _hw_adc_pg
Kojto	90:cb3d968589d8	1352	{
Kojto	90:cb3d968589d8	1353	uint32_t U;
Kojto	90:cb3d968589d8	1354	struct _hw_adc_pg_bitfields
Kojto	90:cb3d968589d8	1355	{
Kojto	90:cb3d968589d8	1356	uint32_t PG : 16; /!< [15:0] Plus-Side Gain /
Kojto	90:cb3d968589d8	1357	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	1358	} B;
Kojto	90:cb3d968589d8	1359	} hw_adc_pg_t;
Kojto	90:cb3d968589d8	1360
Kojto	90:cb3d968589d8	1361	/*!
Kojto	90:cb3d968589d8	1362	* @name Constants and macros for entire ADC_PG register
Kojto	90:cb3d968589d8	1363	*/
Kojto	90:cb3d968589d8	1364	/@{/
Kojto	90:cb3d968589d8	1365	#define HW_ADC_PG_ADDR(x) ((x) + 0x2CU)
Kojto	90:cb3d968589d8	1366
Kojto	90:cb3d968589d8	1367	#define HW_ADC_PG(x) ((__IO hw_adc_pg_t ) HW_ADC_PG_ADDR(x))
Kojto	90:cb3d968589d8	1368	#define HW_ADC_PG_RD(x) (HW_ADC_PG(x).U)
Kojto	90:cb3d968589d8	1369	#define HW_ADC_PG_WR(x, v) (HW_ADC_PG(x).U = (v))
Kojto	90:cb3d968589d8	1370	#define HW_ADC_PG_SET(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1371	#define HW_ADC_PG_CLR(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1372	#define HW_ADC_PG_TOG(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1373	/@}/
Kojto	90:cb3d968589d8	1374
Kojto	90:cb3d968589d8	1375	/*
Kojto	90:cb3d968589d8	1376	* Constants & macros for individual ADC_PG bitfields
Kojto	90:cb3d968589d8	1377	*/
Kojto	90:cb3d968589d8	1378
Kojto	90:cb3d968589d8	1379	/*!
Kojto	90:cb3d968589d8	1380	* @name Register ADC_PG, field PG[15:0] (RW)
Kojto	90:cb3d968589d8	1381	*/
Kojto	90:cb3d968589d8	1382	/@{/
Kojto	90:cb3d968589d8	1383	#define BP_ADC_PG_PG (0U) /!< Bit position for ADC_PG_PG. /
Kojto	90:cb3d968589d8	1384	#define BM_ADC_PG_PG (0x0000FFFFU) /!< Bit mask for ADC_PG_PG. /
Kojto	90:cb3d968589d8	1385	#define BS_ADC_PG_PG (16U) /!< Bit field size in bits for ADC_PG_PG. /
Kojto	90:cb3d968589d8	1386
Kojto	90:cb3d968589d8	1387	/! @brief Read current value of the ADC_PG_PG field. /
Kojto	90:cb3d968589d8	1388	#define BR_ADC_PG_PG(x) (HW_ADC_PG(x).B.PG)
Kojto	90:cb3d968589d8	1389
Kojto	90:cb3d968589d8	1390	/! @brief Format value for bitfield ADC_PG_PG. /
Kojto	90:cb3d968589d8	1391	#define BF_ADC_PG_PG(v) ((uint32_t)((uint32_t)(v) << BP_ADC_PG_PG) & BM_ADC_PG_PG)
Kojto	90:cb3d968589d8	1392
Kojto	90:cb3d968589d8	1393	/! @brief Set the PG field to a new value. /
Kojto	90:cb3d968589d8	1394	#define BW_ADC_PG_PG(x, v) (HW_ADC_PG_WR(x, (HW_ADC_PG_RD(x) & ~BM_ADC_PG_PG) \| BF_ADC_PG_PG(v)))
Kojto	90:cb3d968589d8	1395	/@}/
Kojto	90:cb3d968589d8	1396
Kojto	90:cb3d968589d8	1397	/*******************************************************************************
Kojto	90:cb3d968589d8	1398	* HW_ADC_MG - ADC Minus-Side Gain Register
Kojto	90:cb3d968589d8	1399	******************************************************************************/
Kojto	90:cb3d968589d8	1400
Kojto	90:cb3d968589d8	1401	/*!
Kojto	90:cb3d968589d8	1402	* @brief HW_ADC_MG - ADC Minus-Side Gain Register (RW)
Kojto	90:cb3d968589d8	1403	*
Kojto	90:cb3d968589d8	1404	* Reset value: 0x00008200U
Kojto	90:cb3d968589d8	1405	*
Kojto	90:cb3d968589d8	1406	* The Minus-Side Gain Register (MG) contains the gain error correction for the
Kojto	90:cb3d968589d8	1407	* minus-side input in differential mode. This register is ignored in
Kojto	90:cb3d968589d8	1408	* single-ended mode. MG, a 16-bit real number in binary format, is the gain adjustment
Kojto	90:cb3d968589d8	1409	* factor, with the radix point fixed between ADMG15 and ADMG14. This register must
Kojto	90:cb3d968589d8	1410	* be written by the user with the value described in the calibration procedure.
Kojto	90:cb3d968589d8	1411	* Otherwise, the gain error specifications may not be met.
Kojto	90:cb3d968589d8	1412	*/
Kojto	90:cb3d968589d8	1413	typedef union _hw_adc_mg
Kojto	90:cb3d968589d8	1414	{
Kojto	90:cb3d968589d8	1415	uint32_t U;
Kojto	90:cb3d968589d8	1416	struct _hw_adc_mg_bitfields
Kojto	90:cb3d968589d8	1417	{
Kojto	90:cb3d968589d8	1418	uint32_t MG : 16; /!< [15:0] Minus-Side Gain /
Kojto	90:cb3d968589d8	1419	uint32_t RESERVED0 : 16; /!< [31:16] /
Kojto	90:cb3d968589d8	1420	} B;
Kojto	90:cb3d968589d8	1421	} hw_adc_mg_t;
Kojto	90:cb3d968589d8	1422
Kojto	90:cb3d968589d8	1423	/*!
Kojto	90:cb3d968589d8	1424	* @name Constants and macros for entire ADC_MG register
Kojto	90:cb3d968589d8	1425	*/
Kojto	90:cb3d968589d8	1426	/@{/
Kojto	90:cb3d968589d8	1427	#define HW_ADC_MG_ADDR(x) ((x) + 0x30U)
Kojto	90:cb3d968589d8	1428
Kojto	90:cb3d968589d8	1429	#define HW_ADC_MG(x) ((__IO hw_adc_mg_t ) HW_ADC_MG_ADDR(x))
Kojto	90:cb3d968589d8	1430	#define HW_ADC_MG_RD(x) (HW_ADC_MG(x).U)
Kojto	90:cb3d968589d8	1431	#define HW_ADC_MG_WR(x, v) (HW_ADC_MG(x).U = (v))
Kojto	90:cb3d968589d8	1432	#define HW_ADC_MG_SET(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1433	#define HW_ADC_MG_CLR(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1434	#define HW_ADC_MG_TOG(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1435	/@}/
Kojto	90:cb3d968589d8	1436
Kojto	90:cb3d968589d8	1437	/*
Kojto	90:cb3d968589d8	1438	* Constants & macros for individual ADC_MG bitfields
Kojto	90:cb3d968589d8	1439	*/
Kojto	90:cb3d968589d8	1440
Kojto	90:cb3d968589d8	1441	/*!
Kojto	90:cb3d968589d8	1442	* @name Register ADC_MG, field MG[15:0] (RW)
Kojto	90:cb3d968589d8	1443	*/
Kojto	90:cb3d968589d8	1444	/@{/
Kojto	90:cb3d968589d8	1445	#define BP_ADC_MG_MG (0U) /!< Bit position for ADC_MG_MG. /
Kojto	90:cb3d968589d8	1446	#define BM_ADC_MG_MG (0x0000FFFFU) /!< Bit mask for ADC_MG_MG. /
Kojto	90:cb3d968589d8	1447	#define BS_ADC_MG_MG (16U) /!< Bit field size in bits for ADC_MG_MG. /
Kojto	90:cb3d968589d8	1448
Kojto	90:cb3d968589d8	1449	/! @brief Read current value of the ADC_MG_MG field. /
Kojto	90:cb3d968589d8	1450	#define BR_ADC_MG_MG(x) (HW_ADC_MG(x).B.MG)
Kojto	90:cb3d968589d8	1451
Kojto	90:cb3d968589d8	1452	/! @brief Format value for bitfield ADC_MG_MG. /
Kojto	90:cb3d968589d8	1453	#define BF_ADC_MG_MG(v) ((uint32_t)((uint32_t)(v) << BP_ADC_MG_MG) & BM_ADC_MG_MG)
Kojto	90:cb3d968589d8	1454
Kojto	90:cb3d968589d8	1455	/! @brief Set the MG field to a new value. /
Kojto	90:cb3d968589d8	1456	#define BW_ADC_MG_MG(x, v) (HW_ADC_MG_WR(x, (HW_ADC_MG_RD(x) & ~BM_ADC_MG_MG) \| BF_ADC_MG_MG(v)))
Kojto	90:cb3d968589d8	1457	/@}/
Kojto	90:cb3d968589d8	1458
Kojto	90:cb3d968589d8	1459	/*******************************************************************************
Kojto	90:cb3d968589d8	1460	* HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	1461	******************************************************************************/
Kojto	90:cb3d968589d8	1462
Kojto	90:cb3d968589d8	1463	/*!
Kojto	90:cb3d968589d8	1464	* @brief HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register (RW)
Kojto	90:cb3d968589d8	1465	*
Kojto	90:cb3d968589d8	1466	* Reset value: 0x0000000AU
Kojto	90:cb3d968589d8	1467	*
Kojto	90:cb3d968589d8	1468	* The Plus-Side General Calibration Value Registers (CLPx) contain calibration
Kojto	90:cb3d968589d8	1469	* information that is generated by the calibration function. These registers
Kojto	90:cb3d968589d8	1470	* contain seven calibration values of varying widths: CLP0[5:0], CLP1[6:0],
Kojto	90:cb3d968589d8	1471	* CLP2[7:0], CLP3[8:0], CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set
Kojto	90:cb3d968589d8	1472	* when the self-calibration sequence is done, that is, CAL is cleared. If these
Kojto	90:cb3d968589d8	1473	* registers are written by the user after calibration, the linearity error
Kojto	90:cb3d968589d8	1474	* specifications may not be met.
Kojto	90:cb3d968589d8	1475	*/
Kojto	90:cb3d968589d8	1476	typedef union _hw_adc_clpd
Kojto	90:cb3d968589d8	1477	{
Kojto	90:cb3d968589d8	1478	uint32_t U;
Kojto	90:cb3d968589d8	1479	struct _hw_adc_clpd_bitfields
Kojto	90:cb3d968589d8	1480	{
Kojto	90:cb3d968589d8	1481	uint32_t CLPD : 6; /!< [5:0] /
Kojto	90:cb3d968589d8	1482	uint32_t RESERVED0 : 26; /!< [31:6] /
Kojto	90:cb3d968589d8	1483	} B;
Kojto	90:cb3d968589d8	1484	} hw_adc_clpd_t;
Kojto	90:cb3d968589d8	1485
Kojto	90:cb3d968589d8	1486	/*!
Kojto	90:cb3d968589d8	1487	* @name Constants and macros for entire ADC_CLPD register
Kojto	90:cb3d968589d8	1488	*/
Kojto	90:cb3d968589d8	1489	/@{/
Kojto	90:cb3d968589d8	1490	#define HW_ADC_CLPD_ADDR(x) ((x) + 0x34U)
Kojto	90:cb3d968589d8	1491
Kojto	90:cb3d968589d8	1492	#define HW_ADC_CLPD(x) ((__IO hw_adc_clpd_t ) HW_ADC_CLPD_ADDR(x))
Kojto	90:cb3d968589d8	1493	#define HW_ADC_CLPD_RD(x) (HW_ADC_CLPD(x).U)
Kojto	90:cb3d968589d8	1494	#define HW_ADC_CLPD_WR(x, v) (HW_ADC_CLPD(x).U = (v))
Kojto	90:cb3d968589d8	1495	#define HW_ADC_CLPD_SET(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1496	#define HW_ADC_CLPD_CLR(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1497	#define HW_ADC_CLPD_TOG(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1498	/@}/
Kojto	90:cb3d968589d8	1499
Kojto	90:cb3d968589d8	1500	/*
Kojto	90:cb3d968589d8	1501	* Constants & macros for individual ADC_CLPD bitfields
Kojto	90:cb3d968589d8	1502	*/
Kojto	90:cb3d968589d8	1503
Kojto	90:cb3d968589d8	1504	/*!
Kojto	90:cb3d968589d8	1505	* @name Register ADC_CLPD, field CLPD[5:0] (RW)
Kojto	90:cb3d968589d8	1506	*
Kojto	90:cb3d968589d8	1507	* Calibration Value
Kojto	90:cb3d968589d8	1508	*/
Kojto	90:cb3d968589d8	1509	/@{/
Kojto	90:cb3d968589d8	1510	#define BP_ADC_CLPD_CLPD (0U) /!< Bit position for ADC_CLPD_CLPD. /
Kojto	90:cb3d968589d8	1511	#define BM_ADC_CLPD_CLPD (0x0000003FU) /!< Bit mask for ADC_CLPD_CLPD. /
Kojto	90:cb3d968589d8	1512	#define BS_ADC_CLPD_CLPD (6U) /!< Bit field size in bits for ADC_CLPD_CLPD. /
Kojto	90:cb3d968589d8	1513
Kojto	90:cb3d968589d8	1514	/! @brief Read current value of the ADC_CLPD_CLPD field. /
Kojto	90:cb3d968589d8	1515	#define BR_ADC_CLPD_CLPD(x) (HW_ADC_CLPD(x).B.CLPD)
Kojto	90:cb3d968589d8	1516
Kojto	90:cb3d968589d8	1517	/! @brief Format value for bitfield ADC_CLPD_CLPD. /
Kojto	90:cb3d968589d8	1518	#define BF_ADC_CLPD_CLPD(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLPD_CLPD) & BM_ADC_CLPD_CLPD)
Kojto	90:cb3d968589d8	1519
Kojto	90:cb3d968589d8	1520	/! @brief Set the CLPD field to a new value. /
Kojto	90:cb3d968589d8	1521	#define BW_ADC_CLPD_CLPD(x, v) (HW_ADC_CLPD_WR(x, (HW_ADC_CLPD_RD(x) & ~BM_ADC_CLPD_CLPD) \| BF_ADC_CLPD_CLPD(v)))
Kojto	90:cb3d968589d8	1522	/@}/
Kojto	90:cb3d968589d8	1523
Kojto	90:cb3d968589d8	1524	/*******************************************************************************
Kojto	90:cb3d968589d8	1525	* HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	1526	******************************************************************************/
Kojto	90:cb3d968589d8	1527
Kojto	90:cb3d968589d8	1528	/*!
Kojto	90:cb3d968589d8	1529	* @brief HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register (RW)
Kojto	90:cb3d968589d8	1530	*
Kojto	90:cb3d968589d8	1531	* Reset value: 0x00000020U
Kojto	90:cb3d968589d8	1532	*
Kojto	90:cb3d968589d8	1533	* For more information, see CLPD register description.
Kojto	90:cb3d968589d8	1534	*/
Kojto	90:cb3d968589d8	1535	typedef union _hw_adc_clps
Kojto	90:cb3d968589d8	1536	{
Kojto	90:cb3d968589d8	1537	uint32_t U;
Kojto	90:cb3d968589d8	1538	struct _hw_adc_clps_bitfields
Kojto	90:cb3d968589d8	1539	{
Kojto	90:cb3d968589d8	1540	uint32_t CLPS : 6; /!< [5:0] /
Kojto	90:cb3d968589d8	1541	uint32_t RESERVED0 : 26; /!< [31:6] /
Kojto	90:cb3d968589d8	1542	} B;
Kojto	90:cb3d968589d8	1543	} hw_adc_clps_t;
Kojto	90:cb3d968589d8	1544
Kojto	90:cb3d968589d8	1545	/*!
Kojto	90:cb3d968589d8	1546	* @name Constants and macros for entire ADC_CLPS register
Kojto	90:cb3d968589d8	1547	*/
Kojto	90:cb3d968589d8	1548	/@{/
Kojto	90:cb3d968589d8	1549	#define HW_ADC_CLPS_ADDR(x) ((x) + 0x38U)
Kojto	90:cb3d968589d8	1550
Kojto	90:cb3d968589d8	1551	#define HW_ADC_CLPS(x) ((__IO hw_adc_clps_t ) HW_ADC_CLPS_ADDR(x))
Kojto	90:cb3d968589d8	1552	#define HW_ADC_CLPS_RD(x) (HW_ADC_CLPS(x).U)
Kojto	90:cb3d968589d8	1553	#define HW_ADC_CLPS_WR(x, v) (HW_ADC_CLPS(x).U = (v))
Kojto	90:cb3d968589d8	1554	#define HW_ADC_CLPS_SET(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1555	#define HW_ADC_CLPS_CLR(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1556	#define HW_ADC_CLPS_TOG(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1557	/@}/
Kojto	90:cb3d968589d8	1558
Kojto	90:cb3d968589d8	1559	/*
Kojto	90:cb3d968589d8	1560	* Constants & macros for individual ADC_CLPS bitfields
Kojto	90:cb3d968589d8	1561	*/
Kojto	90:cb3d968589d8	1562
Kojto	90:cb3d968589d8	1563	/*!
Kojto	90:cb3d968589d8	1564	* @name Register ADC_CLPS, field CLPS[5:0] (RW)
Kojto	90:cb3d968589d8	1565	*
Kojto	90:cb3d968589d8	1566	* Calibration Value
Kojto	90:cb3d968589d8	1567	*/
Kojto	90:cb3d968589d8	1568	/@{/
Kojto	90:cb3d968589d8	1569	#define BP_ADC_CLPS_CLPS (0U) /!< Bit position for ADC_CLPS_CLPS. /
Kojto	90:cb3d968589d8	1570	#define BM_ADC_CLPS_CLPS (0x0000003FU) /!< Bit mask for ADC_CLPS_CLPS. /
Kojto	90:cb3d968589d8	1571	#define BS_ADC_CLPS_CLPS (6U) /!< Bit field size in bits for ADC_CLPS_CLPS. /
Kojto	90:cb3d968589d8	1572
Kojto	90:cb3d968589d8	1573	/! @brief Read current value of the ADC_CLPS_CLPS field. /
Kojto	90:cb3d968589d8	1574	#define BR_ADC_CLPS_CLPS(x) (HW_ADC_CLPS(x).B.CLPS)
Kojto	90:cb3d968589d8	1575
Kojto	90:cb3d968589d8	1576	/! @brief Format value for bitfield ADC_CLPS_CLPS. /
Kojto	90:cb3d968589d8	1577	#define BF_ADC_CLPS_CLPS(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLPS_CLPS) & BM_ADC_CLPS_CLPS)
Kojto	90:cb3d968589d8	1578
Kojto	90:cb3d968589d8	1579	/! @brief Set the CLPS field to a new value. /
Kojto	90:cb3d968589d8	1580	#define BW_ADC_CLPS_CLPS(x, v) (HW_ADC_CLPS_WR(x, (HW_ADC_CLPS_RD(x) & ~BM_ADC_CLPS_CLPS) \| BF_ADC_CLPS_CLPS(v)))
Kojto	90:cb3d968589d8	1581	/@}/
Kojto	90:cb3d968589d8	1582
Kojto	90:cb3d968589d8	1583	/*******************************************************************************
Kojto	90:cb3d968589d8	1584	* HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	1585	******************************************************************************/
Kojto	90:cb3d968589d8	1586
Kojto	90:cb3d968589d8	1587	/*!
Kojto	90:cb3d968589d8	1588	* @brief HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register (RW)
Kojto	90:cb3d968589d8	1589	*
Kojto	90:cb3d968589d8	1590	* Reset value: 0x00000200U
Kojto	90:cb3d968589d8	1591	*
Kojto	90:cb3d968589d8	1592	* For more information, see CLPD register description.
Kojto	90:cb3d968589d8	1593	*/
Kojto	90:cb3d968589d8	1594	typedef union _hw_adc_clp4
Kojto	90:cb3d968589d8	1595	{
Kojto	90:cb3d968589d8	1596	uint32_t U;
Kojto	90:cb3d968589d8	1597	struct _hw_adc_clp4_bitfields
Kojto	90:cb3d968589d8	1598	{
Kojto	90:cb3d968589d8	1599	uint32_t CLP4 : 10; /!< [9:0] /
Kojto	90:cb3d968589d8	1600	uint32_t RESERVED0 : 22; /!< [31:10] /
Kojto	90:cb3d968589d8	1601	} B;
Kojto	90:cb3d968589d8	1602	} hw_adc_clp4_t;
Kojto	90:cb3d968589d8	1603
Kojto	90:cb3d968589d8	1604	/*!
Kojto	90:cb3d968589d8	1605	* @name Constants and macros for entire ADC_CLP4 register
Kojto	90:cb3d968589d8	1606	*/
Kojto	90:cb3d968589d8	1607	/@{/
Kojto	90:cb3d968589d8	1608	#define HW_ADC_CLP4_ADDR(x) ((x) + 0x3CU)
Kojto	90:cb3d968589d8	1609
Kojto	90:cb3d968589d8	1610	#define HW_ADC_CLP4(x) ((__IO hw_adc_clp4_t ) HW_ADC_CLP4_ADDR(x))
Kojto	90:cb3d968589d8	1611	#define HW_ADC_CLP4_RD(x) (HW_ADC_CLP4(x).U)
Kojto	90:cb3d968589d8	1612	#define HW_ADC_CLP4_WR(x, v) (HW_ADC_CLP4(x).U = (v))
Kojto	90:cb3d968589d8	1613	#define HW_ADC_CLP4_SET(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1614	#define HW_ADC_CLP4_CLR(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1615	#define HW_ADC_CLP4_TOG(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1616	/@}/
Kojto	90:cb3d968589d8	1617
Kojto	90:cb3d968589d8	1618	/*
Kojto	90:cb3d968589d8	1619	* Constants & macros for individual ADC_CLP4 bitfields
Kojto	90:cb3d968589d8	1620	*/
Kojto	90:cb3d968589d8	1621
Kojto	90:cb3d968589d8	1622	/*!
Kojto	90:cb3d968589d8	1623	* @name Register ADC_CLP4, field CLP4[9:0] (RW)
Kojto	90:cb3d968589d8	1624	*
Kojto	90:cb3d968589d8	1625	* Calibration Value
Kojto	90:cb3d968589d8	1626	*/
Kojto	90:cb3d968589d8	1627	/@{/
Kojto	90:cb3d968589d8	1628	#define BP_ADC_CLP4_CLP4 (0U) /!< Bit position for ADC_CLP4_CLP4. /
Kojto	90:cb3d968589d8	1629	#define BM_ADC_CLP4_CLP4 (0x000003FFU) /!< Bit mask for ADC_CLP4_CLP4. /
Kojto	90:cb3d968589d8	1630	#define BS_ADC_CLP4_CLP4 (10U) /!< Bit field size in bits for ADC_CLP4_CLP4. /
Kojto	90:cb3d968589d8	1631
Kojto	90:cb3d968589d8	1632	/! @brief Read current value of the ADC_CLP4_CLP4 field. /
Kojto	90:cb3d968589d8	1633	#define BR_ADC_CLP4_CLP4(x) (HW_ADC_CLP4(x).B.CLP4)
Kojto	90:cb3d968589d8	1634
Kojto	90:cb3d968589d8	1635	/! @brief Format value for bitfield ADC_CLP4_CLP4. /
Kojto	90:cb3d968589d8	1636	#define BF_ADC_CLP4_CLP4(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLP4_CLP4) & BM_ADC_CLP4_CLP4)
Kojto	90:cb3d968589d8	1637
Kojto	90:cb3d968589d8	1638	/! @brief Set the CLP4 field to a new value. /
Kojto	90:cb3d968589d8	1639	#define BW_ADC_CLP4_CLP4(x, v) (HW_ADC_CLP4_WR(x, (HW_ADC_CLP4_RD(x) & ~BM_ADC_CLP4_CLP4) \| BF_ADC_CLP4_CLP4(v)))
Kojto	90:cb3d968589d8	1640	/@}/
Kojto	90:cb3d968589d8	1641
Kojto	90:cb3d968589d8	1642	/*******************************************************************************
Kojto	90:cb3d968589d8	1643	* HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	1644	******************************************************************************/
Kojto	90:cb3d968589d8	1645
Kojto	90:cb3d968589d8	1646	/*!
Kojto	90:cb3d968589d8	1647	* @brief HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register (RW)
Kojto	90:cb3d968589d8	1648	*
Kojto	90:cb3d968589d8	1649	* Reset value: 0x00000100U
Kojto	90:cb3d968589d8	1650	*
Kojto	90:cb3d968589d8	1651	* For more information, see CLPD register description.
Kojto	90:cb3d968589d8	1652	*/
Kojto	90:cb3d968589d8	1653	typedef union _hw_adc_clp3
Kojto	90:cb3d968589d8	1654	{
Kojto	90:cb3d968589d8	1655	uint32_t U;
Kojto	90:cb3d968589d8	1656	struct _hw_adc_clp3_bitfields
Kojto	90:cb3d968589d8	1657	{
Kojto	90:cb3d968589d8	1658	uint32_t CLP3 : 9; /!< [8:0] /
Kojto	90:cb3d968589d8	1659	uint32_t RESERVED0 : 23; /!< [31:9] /
Kojto	90:cb3d968589d8	1660	} B;
Kojto	90:cb3d968589d8	1661	} hw_adc_clp3_t;
Kojto	90:cb3d968589d8	1662
Kojto	90:cb3d968589d8	1663	/*!
Kojto	90:cb3d968589d8	1664	* @name Constants and macros for entire ADC_CLP3 register
Kojto	90:cb3d968589d8	1665	*/
Kojto	90:cb3d968589d8	1666	/@{/
Kojto	90:cb3d968589d8	1667	#define HW_ADC_CLP3_ADDR(x) ((x) + 0x40U)
Kojto	90:cb3d968589d8	1668
Kojto	90:cb3d968589d8	1669	#define HW_ADC_CLP3(x) ((__IO hw_adc_clp3_t ) HW_ADC_CLP3_ADDR(x))
Kojto	90:cb3d968589d8	1670	#define HW_ADC_CLP3_RD(x) (HW_ADC_CLP3(x).U)
Kojto	90:cb3d968589d8	1671	#define HW_ADC_CLP3_WR(x, v) (HW_ADC_CLP3(x).U = (v))
Kojto	90:cb3d968589d8	1672	#define HW_ADC_CLP3_SET(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1673	#define HW_ADC_CLP3_CLR(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1674	#define HW_ADC_CLP3_TOG(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1675	/@}/
Kojto	90:cb3d968589d8	1676
Kojto	90:cb3d968589d8	1677	/*
Kojto	90:cb3d968589d8	1678	* Constants & macros for individual ADC_CLP3 bitfields
Kojto	90:cb3d968589d8	1679	*/
Kojto	90:cb3d968589d8	1680
Kojto	90:cb3d968589d8	1681	/*!
Kojto	90:cb3d968589d8	1682	* @name Register ADC_CLP3, field CLP3[8:0] (RW)
Kojto	90:cb3d968589d8	1683	*
Kojto	90:cb3d968589d8	1684	* Calibration Value
Kojto	90:cb3d968589d8	1685	*/
Kojto	90:cb3d968589d8	1686	/@{/
Kojto	90:cb3d968589d8	1687	#define BP_ADC_CLP3_CLP3 (0U) /!< Bit position for ADC_CLP3_CLP3. /
Kojto	90:cb3d968589d8	1688	#define BM_ADC_CLP3_CLP3 (0x000001FFU) /!< Bit mask for ADC_CLP3_CLP3. /
Kojto	90:cb3d968589d8	1689	#define BS_ADC_CLP3_CLP3 (9U) /!< Bit field size in bits for ADC_CLP3_CLP3. /
Kojto	90:cb3d968589d8	1690
Kojto	90:cb3d968589d8	1691	/! @brief Read current value of the ADC_CLP3_CLP3 field. /
Kojto	90:cb3d968589d8	1692	#define BR_ADC_CLP3_CLP3(x) (HW_ADC_CLP3(x).B.CLP3)
Kojto	90:cb3d968589d8	1693
Kojto	90:cb3d968589d8	1694	/! @brief Format value for bitfield ADC_CLP3_CLP3. /
Kojto	90:cb3d968589d8	1695	#define BF_ADC_CLP3_CLP3(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLP3_CLP3) & BM_ADC_CLP3_CLP3)
Kojto	90:cb3d968589d8	1696
Kojto	90:cb3d968589d8	1697	/! @brief Set the CLP3 field to a new value. /
Kojto	90:cb3d968589d8	1698	#define BW_ADC_CLP3_CLP3(x, v) (HW_ADC_CLP3_WR(x, (HW_ADC_CLP3_RD(x) & ~BM_ADC_CLP3_CLP3) \| BF_ADC_CLP3_CLP3(v)))
Kojto	90:cb3d968589d8	1699	/@}/
Kojto	90:cb3d968589d8	1700
Kojto	90:cb3d968589d8	1701	/*******************************************************************************
Kojto	90:cb3d968589d8	1702	* HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	1703	******************************************************************************/
Kojto	90:cb3d968589d8	1704
Kojto	90:cb3d968589d8	1705	/*!
Kojto	90:cb3d968589d8	1706	* @brief HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register (RW)
Kojto	90:cb3d968589d8	1707	*
Kojto	90:cb3d968589d8	1708	* Reset value: 0x00000080U
Kojto	90:cb3d968589d8	1709	*
Kojto	90:cb3d968589d8	1710	* For more information, see CLPD register description.
Kojto	90:cb3d968589d8	1711	*/
Kojto	90:cb3d968589d8	1712	typedef union _hw_adc_clp2
Kojto	90:cb3d968589d8	1713	{
Kojto	90:cb3d968589d8	1714	uint32_t U;
Kojto	90:cb3d968589d8	1715	struct _hw_adc_clp2_bitfields
Kojto	90:cb3d968589d8	1716	{
Kojto	90:cb3d968589d8	1717	uint32_t CLP2 : 8; /!< [7:0] /
Kojto	90:cb3d968589d8	1718	uint32_t RESERVED0 : 24; /!< [31:8] /
Kojto	90:cb3d968589d8	1719	} B;
Kojto	90:cb3d968589d8	1720	} hw_adc_clp2_t;
Kojto	90:cb3d968589d8	1721
Kojto	90:cb3d968589d8	1722	/*!
Kojto	90:cb3d968589d8	1723	* @name Constants and macros for entire ADC_CLP2 register
Kojto	90:cb3d968589d8	1724	*/
Kojto	90:cb3d968589d8	1725	/@{/
Kojto	90:cb3d968589d8	1726	#define HW_ADC_CLP2_ADDR(x) ((x) + 0x44U)
Kojto	90:cb3d968589d8	1727
Kojto	90:cb3d968589d8	1728	#define HW_ADC_CLP2(x) ((__IO hw_adc_clp2_t ) HW_ADC_CLP2_ADDR(x))
Kojto	90:cb3d968589d8	1729	#define HW_ADC_CLP2_RD(x) (HW_ADC_CLP2(x).U)
Kojto	90:cb3d968589d8	1730	#define HW_ADC_CLP2_WR(x, v) (HW_ADC_CLP2(x).U = (v))
Kojto	90:cb3d968589d8	1731	#define HW_ADC_CLP2_SET(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1732	#define HW_ADC_CLP2_CLR(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1733	#define HW_ADC_CLP2_TOG(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1734	/@}/
Kojto	90:cb3d968589d8	1735
Kojto	90:cb3d968589d8	1736	/*
Kojto	90:cb3d968589d8	1737	* Constants & macros for individual ADC_CLP2 bitfields
Kojto	90:cb3d968589d8	1738	*/
Kojto	90:cb3d968589d8	1739
Kojto	90:cb3d968589d8	1740	/*!
Kojto	90:cb3d968589d8	1741	* @name Register ADC_CLP2, field CLP2[7:0] (RW)
Kojto	90:cb3d968589d8	1742	*
Kojto	90:cb3d968589d8	1743	* Calibration Value
Kojto	90:cb3d968589d8	1744	*/
Kojto	90:cb3d968589d8	1745	/@{/
Kojto	90:cb3d968589d8	1746	#define BP_ADC_CLP2_CLP2 (0U) /!< Bit position for ADC_CLP2_CLP2. /
Kojto	90:cb3d968589d8	1747	#define BM_ADC_CLP2_CLP2 (0x000000FFU) /!< Bit mask for ADC_CLP2_CLP2. /
Kojto	90:cb3d968589d8	1748	#define BS_ADC_CLP2_CLP2 (8U) /!< Bit field size in bits for ADC_CLP2_CLP2. /
Kojto	90:cb3d968589d8	1749
Kojto	90:cb3d968589d8	1750	/! @brief Read current value of the ADC_CLP2_CLP2 field. /
Kojto	90:cb3d968589d8	1751	#define BR_ADC_CLP2_CLP2(x) (HW_ADC_CLP2(x).B.CLP2)
Kojto	90:cb3d968589d8	1752
Kojto	90:cb3d968589d8	1753	/! @brief Format value for bitfield ADC_CLP2_CLP2. /
Kojto	90:cb3d968589d8	1754	#define BF_ADC_CLP2_CLP2(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLP2_CLP2) & BM_ADC_CLP2_CLP2)
Kojto	90:cb3d968589d8	1755
Kojto	90:cb3d968589d8	1756	/! @brief Set the CLP2 field to a new value. /
Kojto	90:cb3d968589d8	1757	#define BW_ADC_CLP2_CLP2(x, v) (HW_ADC_CLP2_WR(x, (HW_ADC_CLP2_RD(x) & ~BM_ADC_CLP2_CLP2) \| BF_ADC_CLP2_CLP2(v)))
Kojto	90:cb3d968589d8	1758	/@}/
Kojto	90:cb3d968589d8	1759
Kojto	90:cb3d968589d8	1760	/*******************************************************************************
Kojto	90:cb3d968589d8	1761	* HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	1762	******************************************************************************/
Kojto	90:cb3d968589d8	1763
Kojto	90:cb3d968589d8	1764	/*!
Kojto	90:cb3d968589d8	1765	* @brief HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register (RW)
Kojto	90:cb3d968589d8	1766	*
Kojto	90:cb3d968589d8	1767	* Reset value: 0x00000040U
Kojto	90:cb3d968589d8	1768	*
Kojto	90:cb3d968589d8	1769	* For more information, see CLPD register description.
Kojto	90:cb3d968589d8	1770	*/
Kojto	90:cb3d968589d8	1771	typedef union _hw_adc_clp1
Kojto	90:cb3d968589d8	1772	{
Kojto	90:cb3d968589d8	1773	uint32_t U;
Kojto	90:cb3d968589d8	1774	struct _hw_adc_clp1_bitfields
Kojto	90:cb3d968589d8	1775	{
Kojto	90:cb3d968589d8	1776	uint32_t CLP1 : 7; /!< [6:0] /
Kojto	90:cb3d968589d8	1777	uint32_t RESERVED0 : 25; /!< [31:7] /
Kojto	90:cb3d968589d8	1778	} B;
Kojto	90:cb3d968589d8	1779	} hw_adc_clp1_t;
Kojto	90:cb3d968589d8	1780
Kojto	90:cb3d968589d8	1781	/*!
Kojto	90:cb3d968589d8	1782	* @name Constants and macros for entire ADC_CLP1 register
Kojto	90:cb3d968589d8	1783	*/
Kojto	90:cb3d968589d8	1784	/@{/
Kojto	90:cb3d968589d8	1785	#define HW_ADC_CLP1_ADDR(x) ((x) + 0x48U)
Kojto	90:cb3d968589d8	1786
Kojto	90:cb3d968589d8	1787	#define HW_ADC_CLP1(x) ((__IO hw_adc_clp1_t ) HW_ADC_CLP1_ADDR(x))
Kojto	90:cb3d968589d8	1788	#define HW_ADC_CLP1_RD(x) (HW_ADC_CLP1(x).U)
Kojto	90:cb3d968589d8	1789	#define HW_ADC_CLP1_WR(x, v) (HW_ADC_CLP1(x).U = (v))
Kojto	90:cb3d968589d8	1790	#define HW_ADC_CLP1_SET(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1791	#define HW_ADC_CLP1_CLR(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1792	#define HW_ADC_CLP1_TOG(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1793	/@}/
Kojto	90:cb3d968589d8	1794
Kojto	90:cb3d968589d8	1795	/*
Kojto	90:cb3d968589d8	1796	* Constants & macros for individual ADC_CLP1 bitfields
Kojto	90:cb3d968589d8	1797	*/
Kojto	90:cb3d968589d8	1798
Kojto	90:cb3d968589d8	1799	/*!
Kojto	90:cb3d968589d8	1800	* @name Register ADC_CLP1, field CLP1[6:0] (RW)
Kojto	90:cb3d968589d8	1801	*
Kojto	90:cb3d968589d8	1802	* Calibration Value
Kojto	90:cb3d968589d8	1803	*/
Kojto	90:cb3d968589d8	1804	/@{/
Kojto	90:cb3d968589d8	1805	#define BP_ADC_CLP1_CLP1 (0U) /!< Bit position for ADC_CLP1_CLP1. /
Kojto	90:cb3d968589d8	1806	#define BM_ADC_CLP1_CLP1 (0x0000007FU) /!< Bit mask for ADC_CLP1_CLP1. /
Kojto	90:cb3d968589d8	1807	#define BS_ADC_CLP1_CLP1 (7U) /!< Bit field size in bits for ADC_CLP1_CLP1. /
Kojto	90:cb3d968589d8	1808
Kojto	90:cb3d968589d8	1809	/! @brief Read current value of the ADC_CLP1_CLP1 field. /
Kojto	90:cb3d968589d8	1810	#define BR_ADC_CLP1_CLP1(x) (HW_ADC_CLP1(x).B.CLP1)
Kojto	90:cb3d968589d8	1811
Kojto	90:cb3d968589d8	1812	/! @brief Format value for bitfield ADC_CLP1_CLP1. /
Kojto	90:cb3d968589d8	1813	#define BF_ADC_CLP1_CLP1(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLP1_CLP1) & BM_ADC_CLP1_CLP1)
Kojto	90:cb3d968589d8	1814
Kojto	90:cb3d968589d8	1815	/! @brief Set the CLP1 field to a new value. /
Kojto	90:cb3d968589d8	1816	#define BW_ADC_CLP1_CLP1(x, v) (HW_ADC_CLP1_WR(x, (HW_ADC_CLP1_RD(x) & ~BM_ADC_CLP1_CLP1) \| BF_ADC_CLP1_CLP1(v)))
Kojto	90:cb3d968589d8	1817	/@}/
Kojto	90:cb3d968589d8	1818
Kojto	90:cb3d968589d8	1819	/*******************************************************************************
Kojto	90:cb3d968589d8	1820	* HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	1821	******************************************************************************/
Kojto	90:cb3d968589d8	1822
Kojto	90:cb3d968589d8	1823	/*!
Kojto	90:cb3d968589d8	1824	* @brief HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register (RW)
Kojto	90:cb3d968589d8	1825	*
Kojto	90:cb3d968589d8	1826	* Reset value: 0x00000020U
Kojto	90:cb3d968589d8	1827	*
Kojto	90:cb3d968589d8	1828	* For more information, see CLPD register description.
Kojto	90:cb3d968589d8	1829	*/
Kojto	90:cb3d968589d8	1830	typedef union _hw_adc_clp0
Kojto	90:cb3d968589d8	1831	{
Kojto	90:cb3d968589d8	1832	uint32_t U;
Kojto	90:cb3d968589d8	1833	struct _hw_adc_clp0_bitfields
Kojto	90:cb3d968589d8	1834	{
Kojto	90:cb3d968589d8	1835	uint32_t CLP0 : 6; /!< [5:0] /
Kojto	90:cb3d968589d8	1836	uint32_t RESERVED0 : 26; /!< [31:6] /
Kojto	90:cb3d968589d8	1837	} B;
Kojto	90:cb3d968589d8	1838	} hw_adc_clp0_t;
Kojto	90:cb3d968589d8	1839
Kojto	90:cb3d968589d8	1840	/*!
Kojto	90:cb3d968589d8	1841	* @name Constants and macros for entire ADC_CLP0 register
Kojto	90:cb3d968589d8	1842	*/
Kojto	90:cb3d968589d8	1843	/@{/
Kojto	90:cb3d968589d8	1844	#define HW_ADC_CLP0_ADDR(x) ((x) + 0x4CU)
Kojto	90:cb3d968589d8	1845
Kojto	90:cb3d968589d8	1846	#define HW_ADC_CLP0(x) ((__IO hw_adc_clp0_t ) HW_ADC_CLP0_ADDR(x))
Kojto	90:cb3d968589d8	1847	#define HW_ADC_CLP0_RD(x) (HW_ADC_CLP0(x).U)
Kojto	90:cb3d968589d8	1848	#define HW_ADC_CLP0_WR(x, v) (HW_ADC_CLP0(x).U = (v))
Kojto	90:cb3d968589d8	1849	#define HW_ADC_CLP0_SET(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1850	#define HW_ADC_CLP0_CLR(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1851	#define HW_ADC_CLP0_TOG(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1852	/@}/
Kojto	90:cb3d968589d8	1853
Kojto	90:cb3d968589d8	1854	/*
Kojto	90:cb3d968589d8	1855	* Constants & macros for individual ADC_CLP0 bitfields
Kojto	90:cb3d968589d8	1856	*/
Kojto	90:cb3d968589d8	1857
Kojto	90:cb3d968589d8	1858	/*!
Kojto	90:cb3d968589d8	1859	* @name Register ADC_CLP0, field CLP0[5:0] (RW)
Kojto	90:cb3d968589d8	1860	*
Kojto	90:cb3d968589d8	1861	* Calibration Value
Kojto	90:cb3d968589d8	1862	*/
Kojto	90:cb3d968589d8	1863	/@{/
Kojto	90:cb3d968589d8	1864	#define BP_ADC_CLP0_CLP0 (0U) /!< Bit position for ADC_CLP0_CLP0. /
Kojto	90:cb3d968589d8	1865	#define BM_ADC_CLP0_CLP0 (0x0000003FU) /!< Bit mask for ADC_CLP0_CLP0. /
Kojto	90:cb3d968589d8	1866	#define BS_ADC_CLP0_CLP0 (6U) /!< Bit field size in bits for ADC_CLP0_CLP0. /
Kojto	90:cb3d968589d8	1867
Kojto	90:cb3d968589d8	1868	/! @brief Read current value of the ADC_CLP0_CLP0 field. /
Kojto	90:cb3d968589d8	1869	#define BR_ADC_CLP0_CLP0(x) (HW_ADC_CLP0(x).B.CLP0)
Kojto	90:cb3d968589d8	1870
Kojto	90:cb3d968589d8	1871	/! @brief Format value for bitfield ADC_CLP0_CLP0. /
Kojto	90:cb3d968589d8	1872	#define BF_ADC_CLP0_CLP0(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLP0_CLP0) & BM_ADC_CLP0_CLP0)
Kojto	90:cb3d968589d8	1873
Kojto	90:cb3d968589d8	1874	/! @brief Set the CLP0 field to a new value. /
Kojto	90:cb3d968589d8	1875	#define BW_ADC_CLP0_CLP0(x, v) (HW_ADC_CLP0_WR(x, (HW_ADC_CLP0_RD(x) & ~BM_ADC_CLP0_CLP0) \| BF_ADC_CLP0_CLP0(v)))
Kojto	90:cb3d968589d8	1876	/@}/
Kojto	90:cb3d968589d8	1877
Kojto	90:cb3d968589d8	1878	/*******************************************************************************
Kojto	90:cb3d968589d8	1879	* HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	1880	******************************************************************************/
Kojto	90:cb3d968589d8	1881
Kojto	90:cb3d968589d8	1882	/*!
Kojto	90:cb3d968589d8	1883	* @brief HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register (RW)
Kojto	90:cb3d968589d8	1884	*
Kojto	90:cb3d968589d8	1885	* Reset value: 0x0000000AU
Kojto	90:cb3d968589d8	1886	*
Kojto	90:cb3d968589d8	1887	* The Minus-Side General Calibration Value (CLMx) registers contain calibration
Kojto	90:cb3d968589d8	1888	* information that is generated by the calibration function. These registers
Kojto	90:cb3d968589d8	1889	* contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0],
Kojto	90:cb3d968589d8	1890	* CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically
Kojto	90:cb3d968589d8	1891	* set when the self-calibration sequence is done, that is, CAL is cleared. If
Kojto	90:cb3d968589d8	1892	* these registers are written by the user after calibration, the linearity error
Kojto	90:cb3d968589d8	1893	* specifications may not be met.
Kojto	90:cb3d968589d8	1894	*/
Kojto	90:cb3d968589d8	1895	typedef union _hw_adc_clmd
Kojto	90:cb3d968589d8	1896	{
Kojto	90:cb3d968589d8	1897	uint32_t U;
Kojto	90:cb3d968589d8	1898	struct _hw_adc_clmd_bitfields
Kojto	90:cb3d968589d8	1899	{
Kojto	90:cb3d968589d8	1900	uint32_t CLMD : 6; /!< [5:0] /
Kojto	90:cb3d968589d8	1901	uint32_t RESERVED0 : 26; /!< [31:6] /
Kojto	90:cb3d968589d8	1902	} B;
Kojto	90:cb3d968589d8	1903	} hw_adc_clmd_t;
Kojto	90:cb3d968589d8	1904
Kojto	90:cb3d968589d8	1905	/*!
Kojto	90:cb3d968589d8	1906	* @name Constants and macros for entire ADC_CLMD register
Kojto	90:cb3d968589d8	1907	*/
Kojto	90:cb3d968589d8	1908	/@{/
Kojto	90:cb3d968589d8	1909	#define HW_ADC_CLMD_ADDR(x) ((x) + 0x54U)
Kojto	90:cb3d968589d8	1910
Kojto	90:cb3d968589d8	1911	#define HW_ADC_CLMD(x) ((__IO hw_adc_clmd_t ) HW_ADC_CLMD_ADDR(x))
Kojto	90:cb3d968589d8	1912	#define HW_ADC_CLMD_RD(x) (HW_ADC_CLMD(x).U)
Kojto	90:cb3d968589d8	1913	#define HW_ADC_CLMD_WR(x, v) (HW_ADC_CLMD(x).U = (v))
Kojto	90:cb3d968589d8	1914	#define HW_ADC_CLMD_SET(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1915	#define HW_ADC_CLMD_CLR(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1916	#define HW_ADC_CLMD_TOG(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1917	/@}/
Kojto	90:cb3d968589d8	1918
Kojto	90:cb3d968589d8	1919	/*
Kojto	90:cb3d968589d8	1920	* Constants & macros for individual ADC_CLMD bitfields
Kojto	90:cb3d968589d8	1921	*/
Kojto	90:cb3d968589d8	1922
Kojto	90:cb3d968589d8	1923	/*!
Kojto	90:cb3d968589d8	1924	* @name Register ADC_CLMD, field CLMD[5:0] (RW)
Kojto	90:cb3d968589d8	1925	*
Kojto	90:cb3d968589d8	1926	* Calibration Value
Kojto	90:cb3d968589d8	1927	*/
Kojto	90:cb3d968589d8	1928	/@{/
Kojto	90:cb3d968589d8	1929	#define BP_ADC_CLMD_CLMD (0U) /!< Bit position for ADC_CLMD_CLMD. /
Kojto	90:cb3d968589d8	1930	#define BM_ADC_CLMD_CLMD (0x0000003FU) /!< Bit mask for ADC_CLMD_CLMD. /
Kojto	90:cb3d968589d8	1931	#define BS_ADC_CLMD_CLMD (6U) /!< Bit field size in bits for ADC_CLMD_CLMD. /
Kojto	90:cb3d968589d8	1932
Kojto	90:cb3d968589d8	1933	/! @brief Read current value of the ADC_CLMD_CLMD field. /
Kojto	90:cb3d968589d8	1934	#define BR_ADC_CLMD_CLMD(x) (HW_ADC_CLMD(x).B.CLMD)
Kojto	90:cb3d968589d8	1935
Kojto	90:cb3d968589d8	1936	/! @brief Format value for bitfield ADC_CLMD_CLMD. /
Kojto	90:cb3d968589d8	1937	#define BF_ADC_CLMD_CLMD(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLMD_CLMD) & BM_ADC_CLMD_CLMD)
Kojto	90:cb3d968589d8	1938
Kojto	90:cb3d968589d8	1939	/! @brief Set the CLMD field to a new value. /
Kojto	90:cb3d968589d8	1940	#define BW_ADC_CLMD_CLMD(x, v) (HW_ADC_CLMD_WR(x, (HW_ADC_CLMD_RD(x) & ~BM_ADC_CLMD_CLMD) \| BF_ADC_CLMD_CLMD(v)))
Kojto	90:cb3d968589d8	1941	/@}/
Kojto	90:cb3d968589d8	1942
Kojto	90:cb3d968589d8	1943	/*******************************************************************************
Kojto	90:cb3d968589d8	1944	* HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	1945	******************************************************************************/
Kojto	90:cb3d968589d8	1946
Kojto	90:cb3d968589d8	1947	/*!
Kojto	90:cb3d968589d8	1948	* @brief HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register (RW)
Kojto	90:cb3d968589d8	1949	*
Kojto	90:cb3d968589d8	1950	* Reset value: 0x00000020U
Kojto	90:cb3d968589d8	1951	*
Kojto	90:cb3d968589d8	1952	* For more information, see CLMD register description.
Kojto	90:cb3d968589d8	1953	*/
Kojto	90:cb3d968589d8	1954	typedef union _hw_adc_clms
Kojto	90:cb3d968589d8	1955	{
Kojto	90:cb3d968589d8	1956	uint32_t U;
Kojto	90:cb3d968589d8	1957	struct _hw_adc_clms_bitfields
Kojto	90:cb3d968589d8	1958	{
Kojto	90:cb3d968589d8	1959	uint32_t CLMS : 6; /!< [5:0] /
Kojto	90:cb3d968589d8	1960	uint32_t RESERVED0 : 26; /!< [31:6] /
Kojto	90:cb3d968589d8	1961	} B;
Kojto	90:cb3d968589d8	1962	} hw_adc_clms_t;
Kojto	90:cb3d968589d8	1963
Kojto	90:cb3d968589d8	1964	/*!
Kojto	90:cb3d968589d8	1965	* @name Constants and macros for entire ADC_CLMS register
Kojto	90:cb3d968589d8	1966	*/
Kojto	90:cb3d968589d8	1967	/@{/
Kojto	90:cb3d968589d8	1968	#define HW_ADC_CLMS_ADDR(x) ((x) + 0x58U)
Kojto	90:cb3d968589d8	1969
Kojto	90:cb3d968589d8	1970	#define HW_ADC_CLMS(x) ((__IO hw_adc_clms_t ) HW_ADC_CLMS_ADDR(x))
Kojto	90:cb3d968589d8	1971	#define HW_ADC_CLMS_RD(x) (HW_ADC_CLMS(x).U)
Kojto	90:cb3d968589d8	1972	#define HW_ADC_CLMS_WR(x, v) (HW_ADC_CLMS(x).U = (v))
Kojto	90:cb3d968589d8	1973	#define HW_ADC_CLMS_SET(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1974	#define HW_ADC_CLMS_CLR(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1975	#define HW_ADC_CLMS_TOG(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1976	/@}/
Kojto	90:cb3d968589d8	1977
Kojto	90:cb3d968589d8	1978	/*
Kojto	90:cb3d968589d8	1979	* Constants & macros for individual ADC_CLMS bitfields
Kojto	90:cb3d968589d8	1980	*/
Kojto	90:cb3d968589d8	1981
Kojto	90:cb3d968589d8	1982	/*!
Kojto	90:cb3d968589d8	1983	* @name Register ADC_CLMS, field CLMS[5:0] (RW)
Kojto	90:cb3d968589d8	1984	*
Kojto	90:cb3d968589d8	1985	* Calibration Value
Kojto	90:cb3d968589d8	1986	*/
Kojto	90:cb3d968589d8	1987	/@{/
Kojto	90:cb3d968589d8	1988	#define BP_ADC_CLMS_CLMS (0U) /!< Bit position for ADC_CLMS_CLMS. /
Kojto	90:cb3d968589d8	1989	#define BM_ADC_CLMS_CLMS (0x0000003FU) /!< Bit mask for ADC_CLMS_CLMS. /
Kojto	90:cb3d968589d8	1990	#define BS_ADC_CLMS_CLMS (6U) /!< Bit field size in bits for ADC_CLMS_CLMS. /
Kojto	90:cb3d968589d8	1991
Kojto	90:cb3d968589d8	1992	/! @brief Read current value of the ADC_CLMS_CLMS field. /
Kojto	90:cb3d968589d8	1993	#define BR_ADC_CLMS_CLMS(x) (HW_ADC_CLMS(x).B.CLMS)
Kojto	90:cb3d968589d8	1994
Kojto	90:cb3d968589d8	1995	/! @brief Format value for bitfield ADC_CLMS_CLMS. /
Kojto	90:cb3d968589d8	1996	#define BF_ADC_CLMS_CLMS(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLMS_CLMS) & BM_ADC_CLMS_CLMS)
Kojto	90:cb3d968589d8	1997
Kojto	90:cb3d968589d8	1998	/! @brief Set the CLMS field to a new value. /
Kojto	90:cb3d968589d8	1999	#define BW_ADC_CLMS_CLMS(x, v) (HW_ADC_CLMS_WR(x, (HW_ADC_CLMS_RD(x) & ~BM_ADC_CLMS_CLMS) \| BF_ADC_CLMS_CLMS(v)))
Kojto	90:cb3d968589d8	2000	/@}/
Kojto	90:cb3d968589d8	2001
Kojto	90:cb3d968589d8	2002	/*******************************************************************************
Kojto	90:cb3d968589d8	2003	* HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	2004	******************************************************************************/
Kojto	90:cb3d968589d8	2005
Kojto	90:cb3d968589d8	2006	/*!
Kojto	90:cb3d968589d8	2007	* @brief HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register (RW)
Kojto	90:cb3d968589d8	2008	*
Kojto	90:cb3d968589d8	2009	* Reset value: 0x00000200U
Kojto	90:cb3d968589d8	2010	*
Kojto	90:cb3d968589d8	2011	* For more information, see CLMD register description.
Kojto	90:cb3d968589d8	2012	*/
Kojto	90:cb3d968589d8	2013	typedef union _hw_adc_clm4
Kojto	90:cb3d968589d8	2014	{
Kojto	90:cb3d968589d8	2015	uint32_t U;
Kojto	90:cb3d968589d8	2016	struct _hw_adc_clm4_bitfields
Kojto	90:cb3d968589d8	2017	{
Kojto	90:cb3d968589d8	2018	uint32_t CLM4 : 10; /!< [9:0] /
Kojto	90:cb3d968589d8	2019	uint32_t RESERVED0 : 22; /!< [31:10] /
Kojto	90:cb3d968589d8	2020	} B;
Kojto	90:cb3d968589d8	2021	} hw_adc_clm4_t;
Kojto	90:cb3d968589d8	2022
Kojto	90:cb3d968589d8	2023	/*!
Kojto	90:cb3d968589d8	2024	* @name Constants and macros for entire ADC_CLM4 register
Kojto	90:cb3d968589d8	2025	*/
Kojto	90:cb3d968589d8	2026	/@{/
Kojto	90:cb3d968589d8	2027	#define HW_ADC_CLM4_ADDR(x) ((x) + 0x5CU)
Kojto	90:cb3d968589d8	2028
Kojto	90:cb3d968589d8	2029	#define HW_ADC_CLM4(x) ((__IO hw_adc_clm4_t ) HW_ADC_CLM4_ADDR(x))
Kojto	90:cb3d968589d8	2030	#define HW_ADC_CLM4_RD(x) (HW_ADC_CLM4(x).U)
Kojto	90:cb3d968589d8	2031	#define HW_ADC_CLM4_WR(x, v) (HW_ADC_CLM4(x).U = (v))
Kojto	90:cb3d968589d8	2032	#define HW_ADC_CLM4_SET(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2033	#define HW_ADC_CLM4_CLR(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2034	#define HW_ADC_CLM4_TOG(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2035	/@}/
Kojto	90:cb3d968589d8	2036
Kojto	90:cb3d968589d8	2037	/*
Kojto	90:cb3d968589d8	2038	* Constants & macros for individual ADC_CLM4 bitfields
Kojto	90:cb3d968589d8	2039	*/
Kojto	90:cb3d968589d8	2040
Kojto	90:cb3d968589d8	2041	/*!
Kojto	90:cb3d968589d8	2042	* @name Register ADC_CLM4, field CLM4[9:0] (RW)
Kojto	90:cb3d968589d8	2043	*
Kojto	90:cb3d968589d8	2044	* Calibration Value
Kojto	90:cb3d968589d8	2045	*/
Kojto	90:cb3d968589d8	2046	/@{/
Kojto	90:cb3d968589d8	2047	#define BP_ADC_CLM4_CLM4 (0U) /!< Bit position for ADC_CLM4_CLM4. /
Kojto	90:cb3d968589d8	2048	#define BM_ADC_CLM4_CLM4 (0x000003FFU) /!< Bit mask for ADC_CLM4_CLM4. /
Kojto	90:cb3d968589d8	2049	#define BS_ADC_CLM4_CLM4 (10U) /!< Bit field size in bits for ADC_CLM4_CLM4. /
Kojto	90:cb3d968589d8	2050
Kojto	90:cb3d968589d8	2051	/! @brief Read current value of the ADC_CLM4_CLM4 field. /
Kojto	90:cb3d968589d8	2052	#define BR_ADC_CLM4_CLM4(x) (HW_ADC_CLM4(x).B.CLM4)
Kojto	90:cb3d968589d8	2053
Kojto	90:cb3d968589d8	2054	/! @brief Format value for bitfield ADC_CLM4_CLM4. /
Kojto	90:cb3d968589d8	2055	#define BF_ADC_CLM4_CLM4(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLM4_CLM4) & BM_ADC_CLM4_CLM4)
Kojto	90:cb3d968589d8	2056
Kojto	90:cb3d968589d8	2057	/! @brief Set the CLM4 field to a new value. /
Kojto	90:cb3d968589d8	2058	#define BW_ADC_CLM4_CLM4(x, v) (HW_ADC_CLM4_WR(x, (HW_ADC_CLM4_RD(x) & ~BM_ADC_CLM4_CLM4) \| BF_ADC_CLM4_CLM4(v)))
Kojto	90:cb3d968589d8	2059	/@}/
Kojto	90:cb3d968589d8	2060
Kojto	90:cb3d968589d8	2061	/*******************************************************************************
Kojto	90:cb3d968589d8	2062	* HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	2063	******************************************************************************/
Kojto	90:cb3d968589d8	2064
Kojto	90:cb3d968589d8	2065	/*!
Kojto	90:cb3d968589d8	2066	* @brief HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register (RW)
Kojto	90:cb3d968589d8	2067	*
Kojto	90:cb3d968589d8	2068	* Reset value: 0x00000100U
Kojto	90:cb3d968589d8	2069	*
Kojto	90:cb3d968589d8	2070	* For more information, see CLMD register description.
Kojto	90:cb3d968589d8	2071	*/
Kojto	90:cb3d968589d8	2072	typedef union _hw_adc_clm3
Kojto	90:cb3d968589d8	2073	{
Kojto	90:cb3d968589d8	2074	uint32_t U;
Kojto	90:cb3d968589d8	2075	struct _hw_adc_clm3_bitfields
Kojto	90:cb3d968589d8	2076	{
Kojto	90:cb3d968589d8	2077	uint32_t CLM3 : 9; /!< [8:0] /
Kojto	90:cb3d968589d8	2078	uint32_t RESERVED0 : 23; /!< [31:9] /
Kojto	90:cb3d968589d8	2079	} B;
Kojto	90:cb3d968589d8	2080	} hw_adc_clm3_t;
Kojto	90:cb3d968589d8	2081
Kojto	90:cb3d968589d8	2082	/*!
Kojto	90:cb3d968589d8	2083	* @name Constants and macros for entire ADC_CLM3 register
Kojto	90:cb3d968589d8	2084	*/
Kojto	90:cb3d968589d8	2085	/@{/
Kojto	90:cb3d968589d8	2086	#define HW_ADC_CLM3_ADDR(x) ((x) + 0x60U)
Kojto	90:cb3d968589d8	2087
Kojto	90:cb3d968589d8	2088	#define HW_ADC_CLM3(x) ((__IO hw_adc_clm3_t ) HW_ADC_CLM3_ADDR(x))
Kojto	90:cb3d968589d8	2089	#define HW_ADC_CLM3_RD(x) (HW_ADC_CLM3(x).U)
Kojto	90:cb3d968589d8	2090	#define HW_ADC_CLM3_WR(x, v) (HW_ADC_CLM3(x).U = (v))
Kojto	90:cb3d968589d8	2091	#define HW_ADC_CLM3_SET(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2092	#define HW_ADC_CLM3_CLR(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2093	#define HW_ADC_CLM3_TOG(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2094	/@}/
Kojto	90:cb3d968589d8	2095
Kojto	90:cb3d968589d8	2096	/*
Kojto	90:cb3d968589d8	2097	* Constants & macros for individual ADC_CLM3 bitfields
Kojto	90:cb3d968589d8	2098	*/
Kojto	90:cb3d968589d8	2099
Kojto	90:cb3d968589d8	2100	/*!
Kojto	90:cb3d968589d8	2101	* @name Register ADC_CLM3, field CLM3[8:0] (RW)
Kojto	90:cb3d968589d8	2102	*
Kojto	90:cb3d968589d8	2103	* Calibration Value
Kojto	90:cb3d968589d8	2104	*/
Kojto	90:cb3d968589d8	2105	/@{/
Kojto	90:cb3d968589d8	2106	#define BP_ADC_CLM3_CLM3 (0U) /!< Bit position for ADC_CLM3_CLM3. /
Kojto	90:cb3d968589d8	2107	#define BM_ADC_CLM3_CLM3 (0x000001FFU) /!< Bit mask for ADC_CLM3_CLM3. /
Kojto	90:cb3d968589d8	2108	#define BS_ADC_CLM3_CLM3 (9U) /!< Bit field size in bits for ADC_CLM3_CLM3. /
Kojto	90:cb3d968589d8	2109
Kojto	90:cb3d968589d8	2110	/! @brief Read current value of the ADC_CLM3_CLM3 field. /
Kojto	90:cb3d968589d8	2111	#define BR_ADC_CLM3_CLM3(x) (HW_ADC_CLM3(x).B.CLM3)
Kojto	90:cb3d968589d8	2112
Kojto	90:cb3d968589d8	2113	/! @brief Format value for bitfield ADC_CLM3_CLM3. /
Kojto	90:cb3d968589d8	2114	#define BF_ADC_CLM3_CLM3(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLM3_CLM3) & BM_ADC_CLM3_CLM3)
Kojto	90:cb3d968589d8	2115
Kojto	90:cb3d968589d8	2116	/! @brief Set the CLM3 field to a new value. /
Kojto	90:cb3d968589d8	2117	#define BW_ADC_CLM3_CLM3(x, v) (HW_ADC_CLM3_WR(x, (HW_ADC_CLM3_RD(x) & ~BM_ADC_CLM3_CLM3) \| BF_ADC_CLM3_CLM3(v)))
Kojto	90:cb3d968589d8	2118	/@}/
Kojto	90:cb3d968589d8	2119
Kojto	90:cb3d968589d8	2120	/*******************************************************************************
Kojto	90:cb3d968589d8	2121	* HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	2122	******************************************************************************/
Kojto	90:cb3d968589d8	2123
Kojto	90:cb3d968589d8	2124	/*!
Kojto	90:cb3d968589d8	2125	* @brief HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register (RW)
Kojto	90:cb3d968589d8	2126	*
Kojto	90:cb3d968589d8	2127	* Reset value: 0x00000080U
Kojto	90:cb3d968589d8	2128	*
Kojto	90:cb3d968589d8	2129	* For more information, see CLMD register description.
Kojto	90:cb3d968589d8	2130	*/
Kojto	90:cb3d968589d8	2131	typedef union _hw_adc_clm2
Kojto	90:cb3d968589d8	2132	{
Kojto	90:cb3d968589d8	2133	uint32_t U;
Kojto	90:cb3d968589d8	2134	struct _hw_adc_clm2_bitfields
Kojto	90:cb3d968589d8	2135	{
Kojto	90:cb3d968589d8	2136	uint32_t CLM2 : 8; /!< [7:0] /
Kojto	90:cb3d968589d8	2137	uint32_t RESERVED0 : 24; /!< [31:8] /
Kojto	90:cb3d968589d8	2138	} B;
Kojto	90:cb3d968589d8	2139	} hw_adc_clm2_t;
Kojto	90:cb3d968589d8	2140
Kojto	90:cb3d968589d8	2141	/*!
Kojto	90:cb3d968589d8	2142	* @name Constants and macros for entire ADC_CLM2 register
Kojto	90:cb3d968589d8	2143	*/
Kojto	90:cb3d968589d8	2144	/@{/
Kojto	90:cb3d968589d8	2145	#define HW_ADC_CLM2_ADDR(x) ((x) + 0x64U)
Kojto	90:cb3d968589d8	2146
Kojto	90:cb3d968589d8	2147	#define HW_ADC_CLM2(x) ((__IO hw_adc_clm2_t ) HW_ADC_CLM2_ADDR(x))
Kojto	90:cb3d968589d8	2148	#define HW_ADC_CLM2_RD(x) (HW_ADC_CLM2(x).U)
Kojto	90:cb3d968589d8	2149	#define HW_ADC_CLM2_WR(x, v) (HW_ADC_CLM2(x).U = (v))
Kojto	90:cb3d968589d8	2150	#define HW_ADC_CLM2_SET(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2151	#define HW_ADC_CLM2_CLR(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2152	#define HW_ADC_CLM2_TOG(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2153	/@}/
Kojto	90:cb3d968589d8	2154
Kojto	90:cb3d968589d8	2155	/*
Kojto	90:cb3d968589d8	2156	* Constants & macros for individual ADC_CLM2 bitfields
Kojto	90:cb3d968589d8	2157	*/
Kojto	90:cb3d968589d8	2158
Kojto	90:cb3d968589d8	2159	/*!
Kojto	90:cb3d968589d8	2160	* @name Register ADC_CLM2, field CLM2[7:0] (RW)
Kojto	90:cb3d968589d8	2161	*
Kojto	90:cb3d968589d8	2162	* Calibration Value
Kojto	90:cb3d968589d8	2163	*/
Kojto	90:cb3d968589d8	2164	/@{/
Kojto	90:cb3d968589d8	2165	#define BP_ADC_CLM2_CLM2 (0U) /!< Bit position for ADC_CLM2_CLM2. /
Kojto	90:cb3d968589d8	2166	#define BM_ADC_CLM2_CLM2 (0x000000FFU) /!< Bit mask for ADC_CLM2_CLM2. /
Kojto	90:cb3d968589d8	2167	#define BS_ADC_CLM2_CLM2 (8U) /!< Bit field size in bits for ADC_CLM2_CLM2. /
Kojto	90:cb3d968589d8	2168
Kojto	90:cb3d968589d8	2169	/! @brief Read current value of the ADC_CLM2_CLM2 field. /
Kojto	90:cb3d968589d8	2170	#define BR_ADC_CLM2_CLM2(x) (HW_ADC_CLM2(x).B.CLM2)
Kojto	90:cb3d968589d8	2171
Kojto	90:cb3d968589d8	2172	/! @brief Format value for bitfield ADC_CLM2_CLM2. /
Kojto	90:cb3d968589d8	2173	#define BF_ADC_CLM2_CLM2(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLM2_CLM2) & BM_ADC_CLM2_CLM2)
Kojto	90:cb3d968589d8	2174
Kojto	90:cb3d968589d8	2175	/! @brief Set the CLM2 field to a new value. /
Kojto	90:cb3d968589d8	2176	#define BW_ADC_CLM2_CLM2(x, v) (HW_ADC_CLM2_WR(x, (HW_ADC_CLM2_RD(x) & ~BM_ADC_CLM2_CLM2) \| BF_ADC_CLM2_CLM2(v)))
Kojto	90:cb3d968589d8	2177	/@}/
Kojto	90:cb3d968589d8	2178
Kojto	90:cb3d968589d8	2179	/*******************************************************************************
Kojto	90:cb3d968589d8	2180	* HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	2181	******************************************************************************/
Kojto	90:cb3d968589d8	2182
Kojto	90:cb3d968589d8	2183	/*!
Kojto	90:cb3d968589d8	2184	* @brief HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register (RW)
Kojto	90:cb3d968589d8	2185	*
Kojto	90:cb3d968589d8	2186	* Reset value: 0x00000040U
Kojto	90:cb3d968589d8	2187	*
Kojto	90:cb3d968589d8	2188	* For more information, see CLMD register description.
Kojto	90:cb3d968589d8	2189	*/
Kojto	90:cb3d968589d8	2190	typedef union _hw_adc_clm1
Kojto	90:cb3d968589d8	2191	{
Kojto	90:cb3d968589d8	2192	uint32_t U;
Kojto	90:cb3d968589d8	2193	struct _hw_adc_clm1_bitfields
Kojto	90:cb3d968589d8	2194	{
Kojto	90:cb3d968589d8	2195	uint32_t CLM1 : 7; /!< [6:0] /
Kojto	90:cb3d968589d8	2196	uint32_t RESERVED0 : 25; /!< [31:7] /
Kojto	90:cb3d968589d8	2197	} B;
Kojto	90:cb3d968589d8	2198	} hw_adc_clm1_t;
Kojto	90:cb3d968589d8	2199
Kojto	90:cb3d968589d8	2200	/*!
Kojto	90:cb3d968589d8	2201	* @name Constants and macros for entire ADC_CLM1 register
Kojto	90:cb3d968589d8	2202	*/
Kojto	90:cb3d968589d8	2203	/@{/
Kojto	90:cb3d968589d8	2204	#define HW_ADC_CLM1_ADDR(x) ((x) + 0x68U)
Kojto	90:cb3d968589d8	2205
Kojto	90:cb3d968589d8	2206	#define HW_ADC_CLM1(x) ((__IO hw_adc_clm1_t ) HW_ADC_CLM1_ADDR(x))
Kojto	90:cb3d968589d8	2207	#define HW_ADC_CLM1_RD(x) (HW_ADC_CLM1(x).U)
Kojto	90:cb3d968589d8	2208	#define HW_ADC_CLM1_WR(x, v) (HW_ADC_CLM1(x).U = (v))
Kojto	90:cb3d968589d8	2209	#define HW_ADC_CLM1_SET(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2210	#define HW_ADC_CLM1_CLR(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2211	#define HW_ADC_CLM1_TOG(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2212	/@}/
Kojto	90:cb3d968589d8	2213
Kojto	90:cb3d968589d8	2214	/*
Kojto	90:cb3d968589d8	2215	* Constants & macros for individual ADC_CLM1 bitfields
Kojto	90:cb3d968589d8	2216	*/
Kojto	90:cb3d968589d8	2217
Kojto	90:cb3d968589d8	2218	/*!
Kojto	90:cb3d968589d8	2219	* @name Register ADC_CLM1, field CLM1[6:0] (RW)
Kojto	90:cb3d968589d8	2220	*
Kojto	90:cb3d968589d8	2221	* Calibration Value
Kojto	90:cb3d968589d8	2222	*/
Kojto	90:cb3d968589d8	2223	/@{/
Kojto	90:cb3d968589d8	2224	#define BP_ADC_CLM1_CLM1 (0U) /!< Bit position for ADC_CLM1_CLM1. /
Kojto	90:cb3d968589d8	2225	#define BM_ADC_CLM1_CLM1 (0x0000007FU) /!< Bit mask for ADC_CLM1_CLM1. /
Kojto	90:cb3d968589d8	2226	#define BS_ADC_CLM1_CLM1 (7U) /!< Bit field size in bits for ADC_CLM1_CLM1. /
Kojto	90:cb3d968589d8	2227
Kojto	90:cb3d968589d8	2228	/! @brief Read current value of the ADC_CLM1_CLM1 field. /
Kojto	90:cb3d968589d8	2229	#define BR_ADC_CLM1_CLM1(x) (HW_ADC_CLM1(x).B.CLM1)
Kojto	90:cb3d968589d8	2230
Kojto	90:cb3d968589d8	2231	/! @brief Format value for bitfield ADC_CLM1_CLM1. /
Kojto	90:cb3d968589d8	2232	#define BF_ADC_CLM1_CLM1(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLM1_CLM1) & BM_ADC_CLM1_CLM1)
Kojto	90:cb3d968589d8	2233
Kojto	90:cb3d968589d8	2234	/! @brief Set the CLM1 field to a new value. /
Kojto	90:cb3d968589d8	2235	#define BW_ADC_CLM1_CLM1(x, v) (HW_ADC_CLM1_WR(x, (HW_ADC_CLM1_RD(x) & ~BM_ADC_CLM1_CLM1) \| BF_ADC_CLM1_CLM1(v)))
Kojto	90:cb3d968589d8	2236	/@}/
Kojto	90:cb3d968589d8	2237
Kojto	90:cb3d968589d8	2238	/*******************************************************************************
Kojto	90:cb3d968589d8	2239	* HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register
Kojto	90:cb3d968589d8	2240	******************************************************************************/
Kojto	90:cb3d968589d8	2241
Kojto	90:cb3d968589d8	2242	/*!
Kojto	90:cb3d968589d8	2243	* @brief HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register (RW)
Kojto	90:cb3d968589d8	2244	*
Kojto	90:cb3d968589d8	2245	* Reset value: 0x00000020U
Kojto	90:cb3d968589d8	2246	*
Kojto	90:cb3d968589d8	2247	* For more information, see CLMD register description.
Kojto	90:cb3d968589d8	2248	*/
Kojto	90:cb3d968589d8	2249	typedef union _hw_adc_clm0
Kojto	90:cb3d968589d8	2250	{
Kojto	90:cb3d968589d8	2251	uint32_t U;
Kojto	90:cb3d968589d8	2252	struct _hw_adc_clm0_bitfields
Kojto	90:cb3d968589d8	2253	{
Kojto	90:cb3d968589d8	2254	uint32_t CLM0 : 6; /!< [5:0] /
Kojto	90:cb3d968589d8	2255	uint32_t RESERVED0 : 26; /!< [31:6] /
Kojto	90:cb3d968589d8	2256	} B;
Kojto	90:cb3d968589d8	2257	} hw_adc_clm0_t;
Kojto	90:cb3d968589d8	2258
Kojto	90:cb3d968589d8	2259	/*!
Kojto	90:cb3d968589d8	2260	* @name Constants and macros for entire ADC_CLM0 register
Kojto	90:cb3d968589d8	2261	*/
Kojto	90:cb3d968589d8	2262	/@{/
Kojto	90:cb3d968589d8	2263	#define HW_ADC_CLM0_ADDR(x) ((x) + 0x6CU)
Kojto	90:cb3d968589d8	2264
Kojto	90:cb3d968589d8	2265	#define HW_ADC_CLM0(x) ((__IO hw_adc_clm0_t ) HW_ADC_CLM0_ADDR(x))
Kojto	90:cb3d968589d8	2266	#define HW_ADC_CLM0_RD(x) (HW_ADC_CLM0(x).U)
Kojto	90:cb3d968589d8	2267	#define HW_ADC_CLM0_WR(x, v) (HW_ADC_CLM0(x).U = (v))
Kojto	90:cb3d968589d8	2268	#define HW_ADC_CLM0_SET(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2269	#define HW_ADC_CLM0_CLR(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2270	#define HW_ADC_CLM0_TOG(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2271	/@}/
Kojto	90:cb3d968589d8	2272
Kojto	90:cb3d968589d8	2273	/*
Kojto	90:cb3d968589d8	2274	* Constants & macros for individual ADC_CLM0 bitfields
Kojto	90:cb3d968589d8	2275	*/
Kojto	90:cb3d968589d8	2276
Kojto	90:cb3d968589d8	2277	/*!
Kojto	90:cb3d968589d8	2278	* @name Register ADC_CLM0, field CLM0[5:0] (RW)
Kojto	90:cb3d968589d8	2279	*
Kojto	90:cb3d968589d8	2280	* Calibration Value
Kojto	90:cb3d968589d8	2281	*/
Kojto	90:cb3d968589d8	2282	/@{/
Kojto	90:cb3d968589d8	2283	#define BP_ADC_CLM0_CLM0 (0U) /!< Bit position for ADC_CLM0_CLM0. /
Kojto	90:cb3d968589d8	2284	#define BM_ADC_CLM0_CLM0 (0x0000003FU) /!< Bit mask for ADC_CLM0_CLM0. /
Kojto	90:cb3d968589d8	2285	#define BS_ADC_CLM0_CLM0 (6U) /!< Bit field size in bits for ADC_CLM0_CLM0. /
Kojto	90:cb3d968589d8	2286
Kojto	90:cb3d968589d8	2287	/! @brief Read current value of the ADC_CLM0_CLM0 field. /
Kojto	90:cb3d968589d8	2288	#define BR_ADC_CLM0_CLM0(x) (HW_ADC_CLM0(x).B.CLM0)
Kojto	90:cb3d968589d8	2289
Kojto	90:cb3d968589d8	2290	/! @brief Format value for bitfield ADC_CLM0_CLM0. /
Kojto	90:cb3d968589d8	2291	#define BF_ADC_CLM0_CLM0(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLM0_CLM0) & BM_ADC_CLM0_CLM0)
Kojto	90:cb3d968589d8	2292
Kojto	90:cb3d968589d8	2293	/! @brief Set the CLM0 field to a new value. /
Kojto	90:cb3d968589d8	2294	#define BW_ADC_CLM0_CLM0(x, v) (HW_ADC_CLM0_WR(x, (HW_ADC_CLM0_RD(x) & ~BM_ADC_CLM0_CLM0) \| BF_ADC_CLM0_CLM0(v)))
Kojto	90:cb3d968589d8	2295	/@}/
Kojto	90:cb3d968589d8	2296
Kojto	90:cb3d968589d8	2297	/*******************************************************************************
Kojto	90:cb3d968589d8	2298	* hw_adc_t - module struct
Kojto	90:cb3d968589d8	2299	******************************************************************************/
Kojto	90:cb3d968589d8	2300	/*!
Kojto	90:cb3d968589d8	2301	* @brief All ADC module registers.
Kojto	90:cb3d968589d8	2302	*/
Kojto	90:cb3d968589d8	2303	#pragma pack(1)
Kojto	90:cb3d968589d8	2304	typedef struct _hw_adc
Kojto	90:cb3d968589d8	2305	{
Kojto	90:cb3d968589d8	2306	__IO hw_adc_sc1n_t SC1n[2]; /!< [0x0] ADC Status and Control Registers 1 /
Kojto	90:cb3d968589d8	2307	__IO hw_adc_cfg1_t CFG1; /!< [0x8] ADC Configuration Register 1 /
Kojto	90:cb3d968589d8	2308	__IO hw_adc_cfg2_t CFG2; /!< [0xC] ADC Configuration Register 2 /
Kojto	90:cb3d968589d8	2309	__I hw_adc_rn_t Rn[2]; /!< [0x10] ADC Data Result Register /
Kojto	90:cb3d968589d8	2310	__IO hw_adc_cv1_t CV1; /!< [0x18] Compare Value Registers /
Kojto	90:cb3d968589d8	2311	__IO hw_adc_cv2_t CV2; /!< [0x1C] Compare Value Registers /
Kojto	90:cb3d968589d8	2312	__IO hw_adc_sc2_t SC2; /!< [0x20] Status and Control Register 2 /
Kojto	90:cb3d968589d8	2313	__IO hw_adc_sc3_t SC3; /!< [0x24] Status and Control Register 3 /
Kojto	90:cb3d968589d8	2314	__IO hw_adc_ofs_t OFS; /!< [0x28] ADC Offset Correction Register /
Kojto	90:cb3d968589d8	2315	__IO hw_adc_pg_t PG; /!< [0x2C] ADC Plus-Side Gain Register /
Kojto	90:cb3d968589d8	2316	__IO hw_adc_mg_t MG; /!< [0x30] ADC Minus-Side Gain Register /
Kojto	90:cb3d968589d8	2317	__IO hw_adc_clpd_t CLPD; /!< [0x34] ADC Plus-Side General Calibration Value Register /
Kojto	90:cb3d968589d8	2318	__IO hw_adc_clps_t CLPS; /!< [0x38] ADC Plus-Side General Calibration Value Register /
Kojto	90:cb3d968589d8	2319	__IO hw_adc_clp4_t CLP4; /!< [0x3C] ADC Plus-Side General Calibration Value Register /
Kojto	90:cb3d968589d8	2320	__IO hw_adc_clp3_t CLP3; /!< [0x40] ADC Plus-Side General Calibration Value Register /
Kojto	90:cb3d968589d8	2321	__IO hw_adc_clp2_t CLP2; /!< [0x44] ADC Plus-Side General Calibration Value Register /
Kojto	90:cb3d968589d8	2322	__IO hw_adc_clp1_t CLP1; /!< [0x48] ADC Plus-Side General Calibration Value Register /
Kojto	90:cb3d968589d8	2323	__IO hw_adc_clp0_t CLP0; /!< [0x4C] ADC Plus-Side General Calibration Value Register /
Kojto	90:cb3d968589d8	2324	uint8_t _reserved0[4];
Kojto	90:cb3d968589d8	2325	__IO hw_adc_clmd_t CLMD; /!< [0x54] ADC Minus-Side General Calibration Value Register /
Kojto	90:cb3d968589d8	2326	__IO hw_adc_clms_t CLMS; /!< [0x58] ADC Minus-Side General Calibration Value Register /
Kojto	90:cb3d968589d8	2327	__IO hw_adc_clm4_t CLM4; /!< [0x5C] ADC Minus-Side General Calibration Value Register /
Kojto	90:cb3d968589d8	2328	__IO hw_adc_clm3_t CLM3; /!< [0x60] ADC Minus-Side General Calibration Value Register /
Kojto	90:cb3d968589d8	2329	__IO hw_adc_clm2_t CLM2; /!< [0x64] ADC Minus-Side General Calibration Value Register /
Kojto	90:cb3d968589d8	2330	__IO hw_adc_clm1_t CLM1; /!< [0x68] ADC Minus-Side General Calibration Value Register /
Kojto	90:cb3d968589d8	2331	__IO hw_adc_clm0_t CLM0; /!< [0x6C] ADC Minus-Side General Calibration Value Register /
Kojto	90:cb3d968589d8	2332	} hw_adc_t;
Kojto	90:cb3d968589d8	2333	#pragma pack()
Kojto	90:cb3d968589d8	2334
Kojto	90:cb3d968589d8	2335	/! @brief Macro to access all ADC registers. /
Kojto	90:cb3d968589d8	2336	/! @param x ADC module instance base address. /
Kojto	90:cb3d968589d8	2337	/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto	90:cb3d968589d8	2338	* use the '&' operator, like <code>&HW_ADC(ADC0_BASE)</code>. */
Kojto	90:cb3d968589d8	2339	#define HW_ADC(x) ((hw_adc_t )(x))
Kojto	90:cb3d968589d8	2340
Kojto	90:cb3d968589d8	2341	#endif /* __HW_ADC_REGISTERS_H__ */
Kojto	90:cb3d968589d8	2342	/* EOF */