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TARGET_K66F/core_cm4.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:: Anna Bridge
Date:: Fri Jun 22 15:38:59 2018 +0100
Revision:: 169:a7c7b631e539
Parent:: 160:5571c4ff569f

mbed library. Release version 162

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	156:ff21514d8981	1	/************************************************************************//
AnnaBridge	156:ff21514d8981	2	* @file core_cm4.h
AnnaBridge	156:ff21514d8981	3	* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
Anna Bridge	169:a7c7b631e539	4	* @version V5.0.5
Anna Bridge	169:a7c7b631e539	5	* @date 08. January 2018
AnnaBridge	156:ff21514d8981	6	******************************************************************************/
AnnaBridge	156:ff21514d8981	7	/*
AnnaBridge	156:ff21514d8981	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge	156:ff21514d8981	9	*
AnnaBridge	156:ff21514d8981	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	156:ff21514d8981	11	*
AnnaBridge	156:ff21514d8981	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	156:ff21514d8981	13	* not use this file except in compliance with the License.
AnnaBridge	156:ff21514d8981	14	* You may obtain a copy of the License at
AnnaBridge	156:ff21514d8981	15	*
AnnaBridge	156:ff21514d8981	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	156:ff21514d8981	17	*
AnnaBridge	156:ff21514d8981	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	156:ff21514d8981	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	156:ff21514d8981	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	156:ff21514d8981	21	* See the License for the specific language governing permissions and
AnnaBridge	156:ff21514d8981	22	* limitations under the License.
AnnaBridge	156:ff21514d8981	23	*/
AnnaBridge	156:ff21514d8981	24
AnnaBridge	156:ff21514d8981	25	#if defined ( __ICCARM__ )
Anna Bridge	169:a7c7b631e539	26	#pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge	169:a7c7b631e539	27	#elif defined (__clang__)
AnnaBridge	156:ff21514d8981	28	#pragma clang system_header /* treat file as system include file */
AnnaBridge	156:ff21514d8981	29	#endif
AnnaBridge	156:ff21514d8981	30
AnnaBridge	156:ff21514d8981	31	#ifndef __CORE_CM4_H_GENERIC
AnnaBridge	156:ff21514d8981	32	#define __CORE_CM4_H_GENERIC
AnnaBridge	156:ff21514d8981	33
AnnaBridge	156:ff21514d8981	34	#include <stdint.h>
AnnaBridge	156:ff21514d8981	35
AnnaBridge	156:ff21514d8981	36	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	37	extern "C" {
AnnaBridge	156:ff21514d8981	38	#endif
AnnaBridge	156:ff21514d8981	39
AnnaBridge	156:ff21514d8981	40	/**
AnnaBridge	156:ff21514d8981	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge	156:ff21514d8981	42	CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge	156:ff21514d8981	43
AnnaBridge	156:ff21514d8981	44	\li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge	156:ff21514d8981	45	Function definitions in header files are used to allow 'inlining'.
AnnaBridge	156:ff21514d8981	46
AnnaBridge	156:ff21514d8981	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge	156:ff21514d8981	48	Unions are used for effective representation of core registers.
AnnaBridge	156:ff21514d8981	49
AnnaBridge	156:ff21514d8981	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge	156:ff21514d8981	51	Function-like macros are used to allow more efficient code.
AnnaBridge	156:ff21514d8981	52	*/
AnnaBridge	156:ff21514d8981	53
AnnaBridge	156:ff21514d8981	54
AnnaBridge	156:ff21514d8981	55	/*******************************************************************************
AnnaBridge	156:ff21514d8981	56	* CMSIS definitions
AnnaBridge	156:ff21514d8981	57	******************************************************************************/
AnnaBridge	156:ff21514d8981	58	/**
AnnaBridge	156:ff21514d8981	59	\ingroup Cortex_M4
AnnaBridge	156:ff21514d8981	60	@{
AnnaBridge	156:ff21514d8981	61	*/
AnnaBridge	156:ff21514d8981	62
Anna Bridge	160:5571c4ff569f	63	#include "cmsis_version.h"
Anna Bridge	160:5571c4ff569f	64
Anna Bridge	160:5571c4ff569f	65	/* CMSIS CM4 definitions */
Anna Bridge	160:5571c4ff569f	66	#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
Anna Bridge	160:5571c4ff569f	67	#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
AnnaBridge	156:ff21514d8981	68	#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) \| \
Anna Bridge	160:5571c4ff569f	69	__CM4_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
AnnaBridge	156:ff21514d8981	70
AnnaBridge	156:ff21514d8981	71	#define __CORTEX_M (4U) /!< Cortex-M Core /
AnnaBridge	156:ff21514d8981	72
AnnaBridge	156:ff21514d8981	73	/** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge	156:ff21514d8981	74	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
AnnaBridge	156:ff21514d8981	75	*/
AnnaBridge	156:ff21514d8981	76	#if defined ( __CC_ARM )
AnnaBridge	156:ff21514d8981	77	#if defined __TARGET_FPU_VFP
AnnaBridge	156:ff21514d8981	78	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	79	#define __FPU_USED 1U
AnnaBridge	156:ff21514d8981	80	#else
AnnaBridge	156:ff21514d8981	81	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	156:ff21514d8981	82	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	83	#endif
AnnaBridge	156:ff21514d8981	84	#else
AnnaBridge	156:ff21514d8981	85	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	86	#endif
AnnaBridge	156:ff21514d8981	87
AnnaBridge	156:ff21514d8981	88	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	156:ff21514d8981	89	#if defined __ARM_PCS_VFP
AnnaBridge	156:ff21514d8981	90	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	91	#define __FPU_USED 1U
AnnaBridge	156:ff21514d8981	92	#else
AnnaBridge	156:ff21514d8981	93	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	156:ff21514d8981	94	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	95	#endif
AnnaBridge	156:ff21514d8981	96	#else
AnnaBridge	156:ff21514d8981	97	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	98	#endif
AnnaBridge	156:ff21514d8981	99
AnnaBridge	156:ff21514d8981	100	#elif defined ( __GNUC__ )
AnnaBridge	156:ff21514d8981	101	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge	156:ff21514d8981	102	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	103	#define __FPU_USED 1U
AnnaBridge	156:ff21514d8981	104	#else
AnnaBridge	156:ff21514d8981	105	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	156:ff21514d8981	106	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	107	#endif
AnnaBridge	156:ff21514d8981	108	#else
AnnaBridge	156:ff21514d8981	109	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	110	#endif
AnnaBridge	156:ff21514d8981	111
AnnaBridge	156:ff21514d8981	112	#elif defined ( __ICCARM__ )
AnnaBridge	156:ff21514d8981	113	#if defined __ARMVFP__
AnnaBridge	156:ff21514d8981	114	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	115	#define __FPU_USED 1U
AnnaBridge	156:ff21514d8981	116	#else
AnnaBridge	156:ff21514d8981	117	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	156:ff21514d8981	118	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	119	#endif
AnnaBridge	156:ff21514d8981	120	#else
AnnaBridge	156:ff21514d8981	121	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	122	#endif
AnnaBridge	156:ff21514d8981	123
AnnaBridge	156:ff21514d8981	124	#elif defined ( __TI_ARM__ )
AnnaBridge	156:ff21514d8981	125	#if defined __TI_VFP_SUPPORT__
AnnaBridge	156:ff21514d8981	126	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	127	#define __FPU_USED 1U
AnnaBridge	156:ff21514d8981	128	#else
AnnaBridge	156:ff21514d8981	129	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	156:ff21514d8981	130	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	131	#endif
AnnaBridge	156:ff21514d8981	132	#else
AnnaBridge	156:ff21514d8981	133	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	134	#endif
AnnaBridge	156:ff21514d8981	135
AnnaBridge	156:ff21514d8981	136	#elif defined ( __TASKING__ )
AnnaBridge	156:ff21514d8981	137	#if defined __FPU_VFP__
AnnaBridge	156:ff21514d8981	138	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	139	#define __FPU_USED 1U
AnnaBridge	156:ff21514d8981	140	#else
AnnaBridge	156:ff21514d8981	141	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	156:ff21514d8981	142	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	143	#endif
AnnaBridge	156:ff21514d8981	144	#else
AnnaBridge	156:ff21514d8981	145	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	146	#endif
AnnaBridge	156:ff21514d8981	147
AnnaBridge	156:ff21514d8981	148	#elif defined ( __CSMC__ )
AnnaBridge	156:ff21514d8981	149	#if ( __CSMC__ & 0x400U)
AnnaBridge	156:ff21514d8981	150	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	151	#define __FPU_USED 1U
AnnaBridge	156:ff21514d8981	152	#else
AnnaBridge	156:ff21514d8981	153	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	156:ff21514d8981	154	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	155	#endif
AnnaBridge	156:ff21514d8981	156	#else
AnnaBridge	156:ff21514d8981	157	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	158	#endif
AnnaBridge	156:ff21514d8981	159
AnnaBridge	156:ff21514d8981	160	#endif
AnnaBridge	156:ff21514d8981	161
AnnaBridge	156:ff21514d8981	162	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge	156:ff21514d8981	163
AnnaBridge	156:ff21514d8981	164
AnnaBridge	156:ff21514d8981	165	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	166	}
AnnaBridge	156:ff21514d8981	167	#endif
AnnaBridge	156:ff21514d8981	168
AnnaBridge	156:ff21514d8981	169	#endif /* __CORE_CM4_H_GENERIC */
AnnaBridge	156:ff21514d8981	170
AnnaBridge	156:ff21514d8981	171	#ifndef __CMSIS_GENERIC
AnnaBridge	156:ff21514d8981	172
AnnaBridge	156:ff21514d8981	173	#ifndef __CORE_CM4_H_DEPENDANT
AnnaBridge	156:ff21514d8981	174	#define __CORE_CM4_H_DEPENDANT
AnnaBridge	156:ff21514d8981	175
AnnaBridge	156:ff21514d8981	176	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	177	extern "C" {
AnnaBridge	156:ff21514d8981	178	#endif
AnnaBridge	156:ff21514d8981	179
AnnaBridge	156:ff21514d8981	180	/* check device defines and use defaults */
AnnaBridge	156:ff21514d8981	181	#if defined __CHECK_DEVICE_DEFINES
AnnaBridge	156:ff21514d8981	182	#ifndef __CM4_REV
AnnaBridge	156:ff21514d8981	183	#define __CM4_REV 0x0000U
AnnaBridge	156:ff21514d8981	184	#warning "__CM4_REV not defined in device header file; using default!"
AnnaBridge	156:ff21514d8981	185	#endif
AnnaBridge	156:ff21514d8981	186
AnnaBridge	156:ff21514d8981	187	#ifndef __FPU_PRESENT
AnnaBridge	156:ff21514d8981	188	#define __FPU_PRESENT 0U
AnnaBridge	156:ff21514d8981	189	#warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge	156:ff21514d8981	190	#endif
AnnaBridge	156:ff21514d8981	191
AnnaBridge	156:ff21514d8981	192	#ifndef __MPU_PRESENT
AnnaBridge	156:ff21514d8981	193	#define __MPU_PRESENT 0U
AnnaBridge	156:ff21514d8981	194	#warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge	156:ff21514d8981	195	#endif
AnnaBridge	156:ff21514d8981	196
AnnaBridge	156:ff21514d8981	197	#ifndef __NVIC_PRIO_BITS
AnnaBridge	156:ff21514d8981	198	#define __NVIC_PRIO_BITS 3U
AnnaBridge	156:ff21514d8981	199	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge	156:ff21514d8981	200	#endif
AnnaBridge	156:ff21514d8981	201
AnnaBridge	156:ff21514d8981	202	#ifndef __Vendor_SysTickConfig
AnnaBridge	156:ff21514d8981	203	#define __Vendor_SysTickConfig 0U
AnnaBridge	156:ff21514d8981	204	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge	156:ff21514d8981	205	#endif
AnnaBridge	156:ff21514d8981	206	#endif
AnnaBridge	156:ff21514d8981	207
AnnaBridge	156:ff21514d8981	208	/* IO definitions (access restrictions to peripheral registers) */
AnnaBridge	156:ff21514d8981	209	/**
AnnaBridge	156:ff21514d8981	210	\defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge	156:ff21514d8981	211
AnnaBridge	156:ff21514d8981	212	<strong>IO Type Qualifiers</strong> are used
AnnaBridge	156:ff21514d8981	213	\li to specify the access to peripheral variables.
AnnaBridge	156:ff21514d8981	214	\li for automatic generation of peripheral register debug information.
AnnaBridge	156:ff21514d8981	215	*/
AnnaBridge	156:ff21514d8981	216	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	217	#define __I volatile /!< Defines 'read only' permissions /
AnnaBridge	156:ff21514d8981	218	#else
AnnaBridge	156:ff21514d8981	219	#define __I volatile const /!< Defines 'read only' permissions /
AnnaBridge	156:ff21514d8981	220	#endif
AnnaBridge	156:ff21514d8981	221	#define __O volatile /!< Defines 'write only' permissions /
AnnaBridge	156:ff21514d8981	222	#define __IO volatile /!< Defines 'read / write' permissions /
AnnaBridge	156:ff21514d8981	223
AnnaBridge	156:ff21514d8981	224	/* following defines should be used for structure members */
AnnaBridge	156:ff21514d8981	225	#define __IM volatile const /! Defines 'read only' structure member permissions /
AnnaBridge	156:ff21514d8981	226	#define __OM volatile /! Defines 'write only' structure member permissions /
AnnaBridge	156:ff21514d8981	227	#define __IOM volatile /! Defines 'read / write' structure member permissions /
AnnaBridge	156:ff21514d8981	228
AnnaBridge	156:ff21514d8981	229	/@} end of group Cortex_M4 /
AnnaBridge	156:ff21514d8981	230
AnnaBridge	156:ff21514d8981	231
AnnaBridge	156:ff21514d8981	232
AnnaBridge	156:ff21514d8981	233	/*******************************************************************************
AnnaBridge	156:ff21514d8981	234	* Register Abstraction
AnnaBridge	156:ff21514d8981	235	Core Register contain:
AnnaBridge	156:ff21514d8981	236	- Core Register
AnnaBridge	156:ff21514d8981	237	- Core NVIC Register
AnnaBridge	156:ff21514d8981	238	- Core SCB Register
AnnaBridge	156:ff21514d8981	239	- Core SysTick Register
AnnaBridge	156:ff21514d8981	240	- Core Debug Register
AnnaBridge	156:ff21514d8981	241	- Core MPU Register
AnnaBridge	156:ff21514d8981	242	- Core FPU Register
AnnaBridge	156:ff21514d8981	243	******************************************************************************/
AnnaBridge	156:ff21514d8981	244	/**
AnnaBridge	156:ff21514d8981	245	\defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge	156:ff21514d8981	246	\brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge	156:ff21514d8981	247	*/
AnnaBridge	156:ff21514d8981	248
AnnaBridge	156:ff21514d8981	249	/**
AnnaBridge	156:ff21514d8981	250	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	251	\defgroup CMSIS_CORE Status and Control Registers
AnnaBridge	156:ff21514d8981	252	\brief Core Register type definitions.
AnnaBridge	156:ff21514d8981	253	@{
AnnaBridge	156:ff21514d8981	254	*/
AnnaBridge	156:ff21514d8981	255
AnnaBridge	156:ff21514d8981	256	/**
AnnaBridge	156:ff21514d8981	257	\brief Union type to access the Application Program Status Register (APSR).
AnnaBridge	156:ff21514d8981	258	*/
AnnaBridge	156:ff21514d8981	259	typedef union
AnnaBridge	156:ff21514d8981	260	{
AnnaBridge	156:ff21514d8981	261	struct
AnnaBridge	156:ff21514d8981	262	{
AnnaBridge	156:ff21514d8981	263	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
AnnaBridge	156:ff21514d8981	264	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
AnnaBridge	156:ff21514d8981	265	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
AnnaBridge	156:ff21514d8981	266	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	156:ff21514d8981	267	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	156:ff21514d8981	268	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	156:ff21514d8981	269	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	156:ff21514d8981	270	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	156:ff21514d8981	271	} b; /!< Structure used for bit access /
AnnaBridge	156:ff21514d8981	272	uint32_t w; /!< Type used for word access /
AnnaBridge	156:ff21514d8981	273	} APSR_Type;
AnnaBridge	156:ff21514d8981	274
AnnaBridge	156:ff21514d8981	275	/* APSR Register Definitions */
AnnaBridge	156:ff21514d8981	276	#define APSR_N_Pos 31U /!< APSR: N Position /
AnnaBridge	156:ff21514d8981	277	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
AnnaBridge	156:ff21514d8981	278
AnnaBridge	156:ff21514d8981	279	#define APSR_Z_Pos 30U /!< APSR: Z Position /
AnnaBridge	156:ff21514d8981	280	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
AnnaBridge	156:ff21514d8981	281
AnnaBridge	156:ff21514d8981	282	#define APSR_C_Pos 29U /!< APSR: C Position /
AnnaBridge	156:ff21514d8981	283	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
AnnaBridge	156:ff21514d8981	284
AnnaBridge	156:ff21514d8981	285	#define APSR_V_Pos 28U /!< APSR: V Position /
AnnaBridge	156:ff21514d8981	286	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
AnnaBridge	156:ff21514d8981	287
AnnaBridge	156:ff21514d8981	288	#define APSR_Q_Pos 27U /!< APSR: Q Position /
AnnaBridge	156:ff21514d8981	289	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
AnnaBridge	156:ff21514d8981	290
AnnaBridge	156:ff21514d8981	291	#define APSR_GE_Pos 16U /!< APSR: GE Position /
AnnaBridge	156:ff21514d8981	292	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
AnnaBridge	156:ff21514d8981	293
AnnaBridge	156:ff21514d8981	294
AnnaBridge	156:ff21514d8981	295	/**
AnnaBridge	156:ff21514d8981	296	\brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge	156:ff21514d8981	297	*/
AnnaBridge	156:ff21514d8981	298	typedef union
AnnaBridge	156:ff21514d8981	299	{
AnnaBridge	156:ff21514d8981	300	struct
AnnaBridge	156:ff21514d8981	301	{
AnnaBridge	156:ff21514d8981	302	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	156:ff21514d8981	303	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
AnnaBridge	156:ff21514d8981	304	} b; /!< Structure used for bit access /
AnnaBridge	156:ff21514d8981	305	uint32_t w; /!< Type used for word access /
AnnaBridge	156:ff21514d8981	306	} IPSR_Type;
AnnaBridge	156:ff21514d8981	307
AnnaBridge	156:ff21514d8981	308	/* IPSR Register Definitions */
AnnaBridge	156:ff21514d8981	309	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
AnnaBridge	156:ff21514d8981	310	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
AnnaBridge	156:ff21514d8981	311
AnnaBridge	156:ff21514d8981	312
AnnaBridge	156:ff21514d8981	313	/**
AnnaBridge	156:ff21514d8981	314	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge	156:ff21514d8981	315	*/
AnnaBridge	156:ff21514d8981	316	typedef union
AnnaBridge	156:ff21514d8981	317	{
AnnaBridge	156:ff21514d8981	318	struct
AnnaBridge	156:ff21514d8981	319	{
AnnaBridge	156:ff21514d8981	320	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	156:ff21514d8981	321	uint32_t _reserved0:1; /!< bit: 9 Reserved /
AnnaBridge	156:ff21514d8981	322	uint32_t ICI_IT_1:6; /!< bit: 10..15 ICI/IT part 1 /
AnnaBridge	156:ff21514d8981	323	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
AnnaBridge	156:ff21514d8981	324	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
AnnaBridge	156:ff21514d8981	325	uint32_t T:1; /!< bit: 24 Thumb bit /
AnnaBridge	156:ff21514d8981	326	uint32_t ICI_IT_2:2; /!< bit: 25..26 ICI/IT part 2 /
AnnaBridge	156:ff21514d8981	327	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	156:ff21514d8981	328	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	156:ff21514d8981	329	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	156:ff21514d8981	330	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	156:ff21514d8981	331	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	156:ff21514d8981	332	} b; /!< Structure used for bit access /
AnnaBridge	156:ff21514d8981	333	uint32_t w; /!< Type used for word access /
AnnaBridge	156:ff21514d8981	334	} xPSR_Type;
AnnaBridge	156:ff21514d8981	335
AnnaBridge	156:ff21514d8981	336	/* xPSR Register Definitions */
AnnaBridge	156:ff21514d8981	337	#define xPSR_N_Pos 31U /!< xPSR: N Position /
AnnaBridge	156:ff21514d8981	338	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
AnnaBridge	156:ff21514d8981	339
AnnaBridge	156:ff21514d8981	340	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
AnnaBridge	156:ff21514d8981	341	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
AnnaBridge	156:ff21514d8981	342
AnnaBridge	156:ff21514d8981	343	#define xPSR_C_Pos 29U /!< xPSR: C Position /
AnnaBridge	156:ff21514d8981	344	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
AnnaBridge	156:ff21514d8981	345
AnnaBridge	156:ff21514d8981	346	#define xPSR_V_Pos 28U /!< xPSR: V Position /
AnnaBridge	156:ff21514d8981	347	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
AnnaBridge	156:ff21514d8981	348
AnnaBridge	156:ff21514d8981	349	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
AnnaBridge	156:ff21514d8981	350	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
AnnaBridge	156:ff21514d8981	351
AnnaBridge	156:ff21514d8981	352	#define xPSR_ICI_IT_2_Pos 25U /!< xPSR: ICI/IT part 2 Position /
AnnaBridge	156:ff21514d8981	353	#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /!< xPSR: ICI/IT part 2 Mask /
AnnaBridge	156:ff21514d8981	354
AnnaBridge	156:ff21514d8981	355	#define xPSR_T_Pos 24U /!< xPSR: T Position /
AnnaBridge	156:ff21514d8981	356	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
AnnaBridge	156:ff21514d8981	357
AnnaBridge	156:ff21514d8981	358	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
AnnaBridge	156:ff21514d8981	359	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
AnnaBridge	156:ff21514d8981	360
AnnaBridge	156:ff21514d8981	361	#define xPSR_ICI_IT_1_Pos 10U /!< xPSR: ICI/IT part 1 Position /
AnnaBridge	156:ff21514d8981	362	#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /!< xPSR: ICI/IT part 1 Mask /
AnnaBridge	156:ff21514d8981	363
AnnaBridge	156:ff21514d8981	364	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
AnnaBridge	156:ff21514d8981	365	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
AnnaBridge	156:ff21514d8981	366
AnnaBridge	156:ff21514d8981	367
AnnaBridge	156:ff21514d8981	368	/**
AnnaBridge	156:ff21514d8981	369	\brief Union type to access the Control Registers (CONTROL).
AnnaBridge	156:ff21514d8981	370	*/
AnnaBridge	156:ff21514d8981	371	typedef union
AnnaBridge	156:ff21514d8981	372	{
AnnaBridge	156:ff21514d8981	373	struct
AnnaBridge	156:ff21514d8981	374	{
AnnaBridge	156:ff21514d8981	375	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
AnnaBridge	156:ff21514d8981	376	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
AnnaBridge	156:ff21514d8981	377	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
AnnaBridge	156:ff21514d8981	378	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
AnnaBridge	156:ff21514d8981	379	} b; /!< Structure used for bit access /
AnnaBridge	156:ff21514d8981	380	uint32_t w; /!< Type used for word access /
AnnaBridge	156:ff21514d8981	381	} CONTROL_Type;
AnnaBridge	156:ff21514d8981	382
AnnaBridge	156:ff21514d8981	383	/* CONTROL Register Definitions */
AnnaBridge	156:ff21514d8981	384	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
AnnaBridge	156:ff21514d8981	385	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
AnnaBridge	156:ff21514d8981	386
AnnaBridge	156:ff21514d8981	387	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
AnnaBridge	156:ff21514d8981	388	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
AnnaBridge	156:ff21514d8981	389
AnnaBridge	156:ff21514d8981	390	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
AnnaBridge	156:ff21514d8981	391	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
AnnaBridge	156:ff21514d8981	392
AnnaBridge	156:ff21514d8981	393	/@} end of group CMSIS_CORE /
AnnaBridge	156:ff21514d8981	394
AnnaBridge	156:ff21514d8981	395
AnnaBridge	156:ff21514d8981	396	/**
AnnaBridge	156:ff21514d8981	397	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	398	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge	156:ff21514d8981	399	\brief Type definitions for the NVIC Registers
AnnaBridge	156:ff21514d8981	400	@{
AnnaBridge	156:ff21514d8981	401	*/
AnnaBridge	156:ff21514d8981	402
AnnaBridge	156:ff21514d8981	403	/**
AnnaBridge	156:ff21514d8981	404	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge	156:ff21514d8981	405	*/
AnnaBridge	156:ff21514d8981	406	typedef struct
AnnaBridge	156:ff21514d8981	407	{
AnnaBridge	156:ff21514d8981	408	__IOM uint32_t ISER[8U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
AnnaBridge	156:ff21514d8981	409	uint32_t RESERVED0[24U];
AnnaBridge	156:ff21514d8981	410	__IOM uint32_t ICER[8U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
AnnaBridge	156:ff21514d8981	411	uint32_t RSERVED1[24U];
AnnaBridge	156:ff21514d8981	412	__IOM uint32_t ISPR[8U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
AnnaBridge	156:ff21514d8981	413	uint32_t RESERVED2[24U];
AnnaBridge	156:ff21514d8981	414	__IOM uint32_t ICPR[8U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
AnnaBridge	156:ff21514d8981	415	uint32_t RESERVED3[24U];
AnnaBridge	156:ff21514d8981	416	__IOM uint32_t IABR[8U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
AnnaBridge	156:ff21514d8981	417	uint32_t RESERVED4[56U];
AnnaBridge	156:ff21514d8981	418	__IOM uint8_t IP[240U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
AnnaBridge	156:ff21514d8981	419	uint32_t RESERVED5[644U];
AnnaBridge	156:ff21514d8981	420	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
AnnaBridge	156:ff21514d8981	421	} NVIC_Type;
AnnaBridge	156:ff21514d8981	422
AnnaBridge	156:ff21514d8981	423	/* Software Triggered Interrupt Register Definitions */
AnnaBridge	156:ff21514d8981	424	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
AnnaBridge	156:ff21514d8981	425	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
AnnaBridge	156:ff21514d8981	426
AnnaBridge	156:ff21514d8981	427	/@} end of group CMSIS_NVIC /
AnnaBridge	156:ff21514d8981	428
AnnaBridge	156:ff21514d8981	429
AnnaBridge	156:ff21514d8981	430	/**
AnnaBridge	156:ff21514d8981	431	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	432	\defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge	156:ff21514d8981	433	\brief Type definitions for the System Control Block Registers
AnnaBridge	156:ff21514d8981	434	@{
AnnaBridge	156:ff21514d8981	435	*/
AnnaBridge	156:ff21514d8981	436
AnnaBridge	156:ff21514d8981	437	/**
AnnaBridge	156:ff21514d8981	438	\brief Structure type to access the System Control Block (SCB).
AnnaBridge	156:ff21514d8981	439	*/
AnnaBridge	156:ff21514d8981	440	typedef struct
AnnaBridge	156:ff21514d8981	441	{
AnnaBridge	156:ff21514d8981	442	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
AnnaBridge	156:ff21514d8981	443	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
AnnaBridge	156:ff21514d8981	444	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
AnnaBridge	156:ff21514d8981	445	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
AnnaBridge	156:ff21514d8981	446	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
AnnaBridge	156:ff21514d8981	447	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
AnnaBridge	156:ff21514d8981	448	__IOM uint8_t SHP[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
AnnaBridge	156:ff21514d8981	449	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
AnnaBridge	156:ff21514d8981	450	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
AnnaBridge	156:ff21514d8981	451	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
AnnaBridge	156:ff21514d8981	452	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
AnnaBridge	156:ff21514d8981	453	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
AnnaBridge	156:ff21514d8981	454	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
AnnaBridge	156:ff21514d8981	455	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
AnnaBridge	156:ff21514d8981	456	__IM uint32_t PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
AnnaBridge	156:ff21514d8981	457	__IM uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
AnnaBridge	156:ff21514d8981	458	__IM uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
AnnaBridge	156:ff21514d8981	459	__IM uint32_t MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
AnnaBridge	156:ff21514d8981	460	__IM uint32_t ISAR[5U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
AnnaBridge	156:ff21514d8981	461	uint32_t RESERVED0[5U];
AnnaBridge	156:ff21514d8981	462	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
AnnaBridge	156:ff21514d8981	463	} SCB_Type;
AnnaBridge	156:ff21514d8981	464
AnnaBridge	156:ff21514d8981	465	/* SCB CPUID Register Definitions */
AnnaBridge	156:ff21514d8981	466	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
AnnaBridge	156:ff21514d8981	467	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
AnnaBridge	156:ff21514d8981	468
AnnaBridge	156:ff21514d8981	469	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
AnnaBridge	156:ff21514d8981	470	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
AnnaBridge	156:ff21514d8981	471
AnnaBridge	156:ff21514d8981	472	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
AnnaBridge	156:ff21514d8981	473	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
AnnaBridge	156:ff21514d8981	474
AnnaBridge	156:ff21514d8981	475	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
AnnaBridge	156:ff21514d8981	476	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
AnnaBridge	156:ff21514d8981	477
AnnaBridge	156:ff21514d8981	478	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
AnnaBridge	156:ff21514d8981	479	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
AnnaBridge	156:ff21514d8981	480
AnnaBridge	156:ff21514d8981	481	/* SCB Interrupt Control State Register Definitions */
AnnaBridge	156:ff21514d8981	482	#define SCB_ICSR_NMIPENDSET_Pos 31U /!< SCB ICSR: NMIPENDSET Position /
AnnaBridge	156:ff21514d8981	483	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
AnnaBridge	156:ff21514d8981	484
AnnaBridge	156:ff21514d8981	485	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
AnnaBridge	156:ff21514d8981	486	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
AnnaBridge	156:ff21514d8981	487
AnnaBridge	156:ff21514d8981	488	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
AnnaBridge	156:ff21514d8981	489	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
AnnaBridge	156:ff21514d8981	490
AnnaBridge	156:ff21514d8981	491	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
AnnaBridge	156:ff21514d8981	492	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
AnnaBridge	156:ff21514d8981	493
AnnaBridge	156:ff21514d8981	494	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
AnnaBridge	156:ff21514d8981	495	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
AnnaBridge	156:ff21514d8981	496
AnnaBridge	156:ff21514d8981	497	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
AnnaBridge	156:ff21514d8981	498	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
AnnaBridge	156:ff21514d8981	499
AnnaBridge	156:ff21514d8981	500	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
AnnaBridge	156:ff21514d8981	501	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
AnnaBridge	156:ff21514d8981	502
AnnaBridge	156:ff21514d8981	503	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
AnnaBridge	156:ff21514d8981	504	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
AnnaBridge	156:ff21514d8981	505
AnnaBridge	156:ff21514d8981	506	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
AnnaBridge	156:ff21514d8981	507	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
AnnaBridge	156:ff21514d8981	508
AnnaBridge	156:ff21514d8981	509	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
AnnaBridge	156:ff21514d8981	510	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
AnnaBridge	156:ff21514d8981	511
AnnaBridge	156:ff21514d8981	512	/* SCB Vector Table Offset Register Definitions */
AnnaBridge	156:ff21514d8981	513	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
AnnaBridge	156:ff21514d8981	514	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
AnnaBridge	156:ff21514d8981	515
AnnaBridge	156:ff21514d8981	516	/* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge	156:ff21514d8981	517	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
AnnaBridge	156:ff21514d8981	518	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
AnnaBridge	156:ff21514d8981	519
AnnaBridge	156:ff21514d8981	520	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
AnnaBridge	156:ff21514d8981	521	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
AnnaBridge	156:ff21514d8981	522
AnnaBridge	156:ff21514d8981	523	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
AnnaBridge	156:ff21514d8981	524	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
AnnaBridge	156:ff21514d8981	525
AnnaBridge	156:ff21514d8981	526	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
AnnaBridge	156:ff21514d8981	527	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
AnnaBridge	156:ff21514d8981	528
AnnaBridge	156:ff21514d8981	529	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
AnnaBridge	156:ff21514d8981	530	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
AnnaBridge	156:ff21514d8981	531
AnnaBridge	156:ff21514d8981	532	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
AnnaBridge	156:ff21514d8981	533	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
AnnaBridge	156:ff21514d8981	534
AnnaBridge	156:ff21514d8981	535	#define SCB_AIRCR_VECTRESET_Pos 0U /!< SCB AIRCR: VECTRESET Position /
AnnaBridge	156:ff21514d8981	536	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
AnnaBridge	156:ff21514d8981	537
AnnaBridge	156:ff21514d8981	538	/* SCB System Control Register Definitions */
AnnaBridge	156:ff21514d8981	539	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
AnnaBridge	156:ff21514d8981	540	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
AnnaBridge	156:ff21514d8981	541
AnnaBridge	156:ff21514d8981	542	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
AnnaBridge	156:ff21514d8981	543	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
AnnaBridge	156:ff21514d8981	544
AnnaBridge	156:ff21514d8981	545	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
AnnaBridge	156:ff21514d8981	546	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
AnnaBridge	156:ff21514d8981	547
AnnaBridge	156:ff21514d8981	548	/* SCB Configuration Control Register Definitions */
AnnaBridge	156:ff21514d8981	549	#define SCB_CCR_STKALIGN_Pos 9U /!< SCB CCR: STKALIGN Position /
AnnaBridge	156:ff21514d8981	550	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
AnnaBridge	156:ff21514d8981	551
AnnaBridge	156:ff21514d8981	552	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
AnnaBridge	156:ff21514d8981	553	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
AnnaBridge	156:ff21514d8981	554
AnnaBridge	156:ff21514d8981	555	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
AnnaBridge	156:ff21514d8981	556	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
AnnaBridge	156:ff21514d8981	557
AnnaBridge	156:ff21514d8981	558	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
AnnaBridge	156:ff21514d8981	559	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
AnnaBridge	156:ff21514d8981	560
AnnaBridge	156:ff21514d8981	561	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
AnnaBridge	156:ff21514d8981	562	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
AnnaBridge	156:ff21514d8981	563
AnnaBridge	156:ff21514d8981	564	#define SCB_CCR_NONBASETHRDENA_Pos 0U /!< SCB CCR: NONBASETHRDENA Position /
AnnaBridge	156:ff21514d8981	565	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
AnnaBridge	156:ff21514d8981	566
AnnaBridge	156:ff21514d8981	567	/* SCB System Handler Control and State Register Definitions */
AnnaBridge	156:ff21514d8981	568	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
AnnaBridge	156:ff21514d8981	569	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
AnnaBridge	156:ff21514d8981	570
AnnaBridge	156:ff21514d8981	571	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
AnnaBridge	156:ff21514d8981	572	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
AnnaBridge	156:ff21514d8981	573
AnnaBridge	156:ff21514d8981	574	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
AnnaBridge	156:ff21514d8981	575	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
AnnaBridge	156:ff21514d8981	576
AnnaBridge	156:ff21514d8981	577	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
AnnaBridge	156:ff21514d8981	578	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
AnnaBridge	156:ff21514d8981	579
AnnaBridge	156:ff21514d8981	580	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
AnnaBridge	156:ff21514d8981	581	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
AnnaBridge	156:ff21514d8981	582
AnnaBridge	156:ff21514d8981	583	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
AnnaBridge	156:ff21514d8981	584	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
AnnaBridge	156:ff21514d8981	585
AnnaBridge	156:ff21514d8981	586	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
AnnaBridge	156:ff21514d8981	587	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
AnnaBridge	156:ff21514d8981	588
AnnaBridge	156:ff21514d8981	589	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
AnnaBridge	156:ff21514d8981	590	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
AnnaBridge	156:ff21514d8981	591
AnnaBridge	156:ff21514d8981	592	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
AnnaBridge	156:ff21514d8981	593	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
AnnaBridge	156:ff21514d8981	594
AnnaBridge	156:ff21514d8981	595	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
AnnaBridge	156:ff21514d8981	596	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
AnnaBridge	156:ff21514d8981	597
AnnaBridge	156:ff21514d8981	598	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
AnnaBridge	156:ff21514d8981	599	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
AnnaBridge	156:ff21514d8981	600
AnnaBridge	156:ff21514d8981	601	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
AnnaBridge	156:ff21514d8981	602	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
AnnaBridge	156:ff21514d8981	603
AnnaBridge	156:ff21514d8981	604	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
AnnaBridge	156:ff21514d8981	605	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
AnnaBridge	156:ff21514d8981	606
AnnaBridge	156:ff21514d8981	607	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
AnnaBridge	156:ff21514d8981	608	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
AnnaBridge	156:ff21514d8981	609
AnnaBridge	156:ff21514d8981	610	/* SCB Configurable Fault Status Register Definitions */
AnnaBridge	156:ff21514d8981	611	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
AnnaBridge	156:ff21514d8981	612	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
AnnaBridge	156:ff21514d8981	613
AnnaBridge	156:ff21514d8981	614	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
AnnaBridge	156:ff21514d8981	615	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
AnnaBridge	156:ff21514d8981	616
AnnaBridge	156:ff21514d8981	617	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
AnnaBridge	156:ff21514d8981	618	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
AnnaBridge	156:ff21514d8981	619
AnnaBridge	156:ff21514d8981	620	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	156:ff21514d8981	621	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
AnnaBridge	156:ff21514d8981	622	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
AnnaBridge	156:ff21514d8981	623
AnnaBridge	156:ff21514d8981	624	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
AnnaBridge	156:ff21514d8981	625	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
AnnaBridge	156:ff21514d8981	626
AnnaBridge	156:ff21514d8981	627	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
AnnaBridge	156:ff21514d8981	628	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
AnnaBridge	156:ff21514d8981	629
AnnaBridge	156:ff21514d8981	630	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
AnnaBridge	156:ff21514d8981	631	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
AnnaBridge	156:ff21514d8981	632
AnnaBridge	156:ff21514d8981	633	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
AnnaBridge	156:ff21514d8981	634	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
AnnaBridge	156:ff21514d8981	635
AnnaBridge	156:ff21514d8981	636	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
AnnaBridge	156:ff21514d8981	637	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
AnnaBridge	156:ff21514d8981	638
AnnaBridge	156:ff21514d8981	639	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	156:ff21514d8981	640	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
AnnaBridge	156:ff21514d8981	641	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
AnnaBridge	156:ff21514d8981	642
AnnaBridge	156:ff21514d8981	643	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
AnnaBridge	156:ff21514d8981	644	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
AnnaBridge	156:ff21514d8981	645
AnnaBridge	156:ff21514d8981	646	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
AnnaBridge	156:ff21514d8981	647	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
AnnaBridge	156:ff21514d8981	648
AnnaBridge	156:ff21514d8981	649	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
AnnaBridge	156:ff21514d8981	650	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
AnnaBridge	156:ff21514d8981	651
AnnaBridge	156:ff21514d8981	652	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
AnnaBridge	156:ff21514d8981	653	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
AnnaBridge	156:ff21514d8981	654
AnnaBridge	156:ff21514d8981	655	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
AnnaBridge	156:ff21514d8981	656	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
AnnaBridge	156:ff21514d8981	657
AnnaBridge	156:ff21514d8981	658	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
AnnaBridge	156:ff21514d8981	659	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
AnnaBridge	156:ff21514d8981	660
AnnaBridge	156:ff21514d8981	661	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	156:ff21514d8981	662	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
AnnaBridge	156:ff21514d8981	663	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
AnnaBridge	156:ff21514d8981	664
AnnaBridge	156:ff21514d8981	665	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
AnnaBridge	156:ff21514d8981	666	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
AnnaBridge	156:ff21514d8981	667
AnnaBridge	156:ff21514d8981	668	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
AnnaBridge	156:ff21514d8981	669	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
AnnaBridge	156:ff21514d8981	670
AnnaBridge	156:ff21514d8981	671	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
AnnaBridge	156:ff21514d8981	672	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
AnnaBridge	156:ff21514d8981	673
AnnaBridge	156:ff21514d8981	674	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
AnnaBridge	156:ff21514d8981	675	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
AnnaBridge	156:ff21514d8981	676
AnnaBridge	156:ff21514d8981	677	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
AnnaBridge	156:ff21514d8981	678	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
AnnaBridge	156:ff21514d8981	679
AnnaBridge	156:ff21514d8981	680	/* SCB Hard Fault Status Register Definitions */
AnnaBridge	156:ff21514d8981	681	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
AnnaBridge	156:ff21514d8981	682	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
AnnaBridge	156:ff21514d8981	683
AnnaBridge	156:ff21514d8981	684	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
AnnaBridge	156:ff21514d8981	685	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
AnnaBridge	156:ff21514d8981	686
AnnaBridge	156:ff21514d8981	687	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
AnnaBridge	156:ff21514d8981	688	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
AnnaBridge	156:ff21514d8981	689
AnnaBridge	156:ff21514d8981	690	/* SCB Debug Fault Status Register Definitions */
AnnaBridge	156:ff21514d8981	691	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
AnnaBridge	156:ff21514d8981	692	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
AnnaBridge	156:ff21514d8981	693
AnnaBridge	156:ff21514d8981	694	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
AnnaBridge	156:ff21514d8981	695	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
AnnaBridge	156:ff21514d8981	696
AnnaBridge	156:ff21514d8981	697	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
AnnaBridge	156:ff21514d8981	698	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
AnnaBridge	156:ff21514d8981	699
AnnaBridge	156:ff21514d8981	700	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
AnnaBridge	156:ff21514d8981	701	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
AnnaBridge	156:ff21514d8981	702
AnnaBridge	156:ff21514d8981	703	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
AnnaBridge	156:ff21514d8981	704	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
AnnaBridge	156:ff21514d8981	705
AnnaBridge	156:ff21514d8981	706	/@} end of group CMSIS_SCB /
AnnaBridge	156:ff21514d8981	707
AnnaBridge	156:ff21514d8981	708
AnnaBridge	156:ff21514d8981	709	/**
AnnaBridge	156:ff21514d8981	710	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	711	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge	156:ff21514d8981	712	\brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge	156:ff21514d8981	713	@{
AnnaBridge	156:ff21514d8981	714	*/
AnnaBridge	156:ff21514d8981	715
AnnaBridge	156:ff21514d8981	716	/**
AnnaBridge	156:ff21514d8981	717	\brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge	156:ff21514d8981	718	*/
AnnaBridge	156:ff21514d8981	719	typedef struct
AnnaBridge	156:ff21514d8981	720	{
AnnaBridge	156:ff21514d8981	721	uint32_t RESERVED0[1U];
AnnaBridge	156:ff21514d8981	722	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
AnnaBridge	156:ff21514d8981	723	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
AnnaBridge	156:ff21514d8981	724	} SCnSCB_Type;
AnnaBridge	156:ff21514d8981	725
AnnaBridge	156:ff21514d8981	726	/* Interrupt Controller Type Register Definitions */
AnnaBridge	156:ff21514d8981	727	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
AnnaBridge	156:ff21514d8981	728	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
AnnaBridge	156:ff21514d8981	729
AnnaBridge	156:ff21514d8981	730	/* Auxiliary Control Register Definitions */
AnnaBridge	156:ff21514d8981	731	#define SCnSCB_ACTLR_DISOOFP_Pos 9U /!< ACTLR: DISOOFP Position /
AnnaBridge	156:ff21514d8981	732	#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /!< ACTLR: DISOOFP Mask /
AnnaBridge	156:ff21514d8981	733
AnnaBridge	156:ff21514d8981	734	#define SCnSCB_ACTLR_DISFPCA_Pos 8U /!< ACTLR: DISFPCA Position /
AnnaBridge	156:ff21514d8981	735	#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /!< ACTLR: DISFPCA Mask /
AnnaBridge	156:ff21514d8981	736
AnnaBridge	156:ff21514d8981	737	#define SCnSCB_ACTLR_DISFOLD_Pos 2U /!< ACTLR: DISFOLD Position /
AnnaBridge	156:ff21514d8981	738	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
AnnaBridge	156:ff21514d8981	739
AnnaBridge	156:ff21514d8981	740	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /!< ACTLR: DISDEFWBUF Position /
AnnaBridge	156:ff21514d8981	741	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
AnnaBridge	156:ff21514d8981	742
AnnaBridge	156:ff21514d8981	743	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /!< ACTLR: DISMCYCINT Position /
AnnaBridge	156:ff21514d8981	744	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
AnnaBridge	156:ff21514d8981	745
AnnaBridge	156:ff21514d8981	746	/@} end of group CMSIS_SCnotSCB /
AnnaBridge	156:ff21514d8981	747
AnnaBridge	156:ff21514d8981	748
AnnaBridge	156:ff21514d8981	749	/**
AnnaBridge	156:ff21514d8981	750	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	751	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge	156:ff21514d8981	752	\brief Type definitions for the System Timer Registers.
AnnaBridge	156:ff21514d8981	753	@{
AnnaBridge	156:ff21514d8981	754	*/
AnnaBridge	156:ff21514d8981	755
AnnaBridge	156:ff21514d8981	756	/**
AnnaBridge	156:ff21514d8981	757	\brief Structure type to access the System Timer (SysTick).
AnnaBridge	156:ff21514d8981	758	*/
AnnaBridge	156:ff21514d8981	759	typedef struct
AnnaBridge	156:ff21514d8981	760	{
AnnaBridge	156:ff21514d8981	761	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
AnnaBridge	156:ff21514d8981	762	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
AnnaBridge	156:ff21514d8981	763	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
AnnaBridge	156:ff21514d8981	764	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
AnnaBridge	156:ff21514d8981	765	} SysTick_Type;
AnnaBridge	156:ff21514d8981	766
AnnaBridge	156:ff21514d8981	767	/* SysTick Control / Status Register Definitions */
AnnaBridge	156:ff21514d8981	768	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
AnnaBridge	156:ff21514d8981	769	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
AnnaBridge	156:ff21514d8981	770
AnnaBridge	156:ff21514d8981	771	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
AnnaBridge	156:ff21514d8981	772	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
AnnaBridge	156:ff21514d8981	773
AnnaBridge	156:ff21514d8981	774	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
AnnaBridge	156:ff21514d8981	775	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
AnnaBridge	156:ff21514d8981	776
AnnaBridge	156:ff21514d8981	777	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
AnnaBridge	156:ff21514d8981	778	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
AnnaBridge	156:ff21514d8981	779
AnnaBridge	156:ff21514d8981	780	/* SysTick Reload Register Definitions */
AnnaBridge	156:ff21514d8981	781	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
AnnaBridge	156:ff21514d8981	782	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
AnnaBridge	156:ff21514d8981	783
AnnaBridge	156:ff21514d8981	784	/* SysTick Current Register Definitions */
AnnaBridge	156:ff21514d8981	785	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
AnnaBridge	156:ff21514d8981	786	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
AnnaBridge	156:ff21514d8981	787
AnnaBridge	156:ff21514d8981	788	/* SysTick Calibration Register Definitions */
AnnaBridge	156:ff21514d8981	789	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
AnnaBridge	156:ff21514d8981	790	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
AnnaBridge	156:ff21514d8981	791
AnnaBridge	156:ff21514d8981	792	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
AnnaBridge	156:ff21514d8981	793	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
AnnaBridge	156:ff21514d8981	794
AnnaBridge	156:ff21514d8981	795	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
AnnaBridge	156:ff21514d8981	796	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
AnnaBridge	156:ff21514d8981	797
AnnaBridge	156:ff21514d8981	798	/@} end of group CMSIS_SysTick /
AnnaBridge	156:ff21514d8981	799
AnnaBridge	156:ff21514d8981	800
AnnaBridge	156:ff21514d8981	801	/**
AnnaBridge	156:ff21514d8981	802	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	803	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge	156:ff21514d8981	804	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
AnnaBridge	156:ff21514d8981	805	@{
AnnaBridge	156:ff21514d8981	806	*/
AnnaBridge	156:ff21514d8981	807
AnnaBridge	156:ff21514d8981	808	/**
AnnaBridge	156:ff21514d8981	809	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
AnnaBridge	156:ff21514d8981	810	*/
AnnaBridge	156:ff21514d8981	811	typedef struct
AnnaBridge	156:ff21514d8981	812	{
AnnaBridge	156:ff21514d8981	813	__OM union
AnnaBridge	156:ff21514d8981	814	{
AnnaBridge	156:ff21514d8981	815	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
AnnaBridge	156:ff21514d8981	816	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
AnnaBridge	156:ff21514d8981	817	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
AnnaBridge	156:ff21514d8981	818	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
AnnaBridge	156:ff21514d8981	819	uint32_t RESERVED0[864U];
AnnaBridge	156:ff21514d8981	820	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
AnnaBridge	156:ff21514d8981	821	uint32_t RESERVED1[15U];
AnnaBridge	156:ff21514d8981	822	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
AnnaBridge	156:ff21514d8981	823	uint32_t RESERVED2[15U];
AnnaBridge	156:ff21514d8981	824	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
AnnaBridge	156:ff21514d8981	825	uint32_t RESERVED3[29U];
AnnaBridge	156:ff21514d8981	826	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
AnnaBridge	156:ff21514d8981	827	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
AnnaBridge	156:ff21514d8981	828	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
AnnaBridge	156:ff21514d8981	829	uint32_t RESERVED4[43U];
AnnaBridge	156:ff21514d8981	830	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
AnnaBridge	156:ff21514d8981	831	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
AnnaBridge	156:ff21514d8981	832	uint32_t RESERVED5[6U];
AnnaBridge	156:ff21514d8981	833	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
AnnaBridge	156:ff21514d8981	834	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
AnnaBridge	156:ff21514d8981	835	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
AnnaBridge	156:ff21514d8981	836	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
AnnaBridge	156:ff21514d8981	837	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
AnnaBridge	156:ff21514d8981	838	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
AnnaBridge	156:ff21514d8981	839	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
AnnaBridge	156:ff21514d8981	840	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
AnnaBridge	156:ff21514d8981	841	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
AnnaBridge	156:ff21514d8981	842	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
AnnaBridge	156:ff21514d8981	843	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
AnnaBridge	156:ff21514d8981	844	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
AnnaBridge	156:ff21514d8981	845	} ITM_Type;
AnnaBridge	156:ff21514d8981	846
AnnaBridge	156:ff21514d8981	847	/* ITM Trace Privilege Register Definitions */
AnnaBridge	156:ff21514d8981	848	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
Anna Bridge	169:a7c7b631e539	849	#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
AnnaBridge	156:ff21514d8981	850
AnnaBridge	156:ff21514d8981	851	/* ITM Trace Control Register Definitions */
AnnaBridge	156:ff21514d8981	852	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
AnnaBridge	156:ff21514d8981	853	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
AnnaBridge	156:ff21514d8981	854
AnnaBridge	156:ff21514d8981	855	#define ITM_TCR_TraceBusID_Pos 16U /!< ITM TCR: ATBID Position /
AnnaBridge	156:ff21514d8981	856	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
AnnaBridge	156:ff21514d8981	857
AnnaBridge	156:ff21514d8981	858	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
AnnaBridge	156:ff21514d8981	859	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
AnnaBridge	156:ff21514d8981	860
AnnaBridge	156:ff21514d8981	861	#define ITM_TCR_TSPrescale_Pos 8U /!< ITM TCR: TSPrescale Position /
AnnaBridge	156:ff21514d8981	862	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
AnnaBridge	156:ff21514d8981	863
AnnaBridge	156:ff21514d8981	864	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
AnnaBridge	156:ff21514d8981	865	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
AnnaBridge	156:ff21514d8981	866
AnnaBridge	156:ff21514d8981	867	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
AnnaBridge	156:ff21514d8981	868	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
AnnaBridge	156:ff21514d8981	869
AnnaBridge	156:ff21514d8981	870	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
AnnaBridge	156:ff21514d8981	871	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
AnnaBridge	156:ff21514d8981	872
AnnaBridge	156:ff21514d8981	873	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
AnnaBridge	156:ff21514d8981	874	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
AnnaBridge	156:ff21514d8981	875
AnnaBridge	156:ff21514d8981	876	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
AnnaBridge	156:ff21514d8981	877	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
AnnaBridge	156:ff21514d8981	878
AnnaBridge	156:ff21514d8981	879	/* ITM Integration Write Register Definitions */
AnnaBridge	156:ff21514d8981	880	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
AnnaBridge	156:ff21514d8981	881	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
AnnaBridge	156:ff21514d8981	882
AnnaBridge	156:ff21514d8981	883	/* ITM Integration Read Register Definitions */
AnnaBridge	156:ff21514d8981	884	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
AnnaBridge	156:ff21514d8981	885	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
AnnaBridge	156:ff21514d8981	886
AnnaBridge	156:ff21514d8981	887	/* ITM Integration Mode Control Register Definitions */
AnnaBridge	156:ff21514d8981	888	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
AnnaBridge	156:ff21514d8981	889	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
AnnaBridge	156:ff21514d8981	890
AnnaBridge	156:ff21514d8981	891	/* ITM Lock Status Register Definitions */
AnnaBridge	156:ff21514d8981	892	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
AnnaBridge	156:ff21514d8981	893	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
AnnaBridge	156:ff21514d8981	894
AnnaBridge	156:ff21514d8981	895	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
AnnaBridge	156:ff21514d8981	896	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
AnnaBridge	156:ff21514d8981	897
AnnaBridge	156:ff21514d8981	898	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
AnnaBridge	156:ff21514d8981	899	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
AnnaBridge	156:ff21514d8981	900
AnnaBridge	156:ff21514d8981	901	/@}/ /* end of group CMSIS_ITM */
AnnaBridge	156:ff21514d8981	902
AnnaBridge	156:ff21514d8981	903
AnnaBridge	156:ff21514d8981	904	/**
AnnaBridge	156:ff21514d8981	905	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	906	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge	156:ff21514d8981	907	\brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge	156:ff21514d8981	908	@{
AnnaBridge	156:ff21514d8981	909	*/
AnnaBridge	156:ff21514d8981	910
AnnaBridge	156:ff21514d8981	911	/**
AnnaBridge	156:ff21514d8981	912	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge	156:ff21514d8981	913	*/
AnnaBridge	156:ff21514d8981	914	typedef struct
AnnaBridge	156:ff21514d8981	915	{
AnnaBridge	156:ff21514d8981	916	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
AnnaBridge	156:ff21514d8981	917	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
AnnaBridge	156:ff21514d8981	918	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
AnnaBridge	156:ff21514d8981	919	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
AnnaBridge	156:ff21514d8981	920	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
AnnaBridge	156:ff21514d8981	921	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
AnnaBridge	156:ff21514d8981	922	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
AnnaBridge	156:ff21514d8981	923	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
AnnaBridge	156:ff21514d8981	924	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
AnnaBridge	156:ff21514d8981	925	__IOM uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
AnnaBridge	156:ff21514d8981	926	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
AnnaBridge	156:ff21514d8981	927	uint32_t RESERVED0[1U];
AnnaBridge	156:ff21514d8981	928	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
AnnaBridge	156:ff21514d8981	929	__IOM uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
AnnaBridge	156:ff21514d8981	930	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
AnnaBridge	156:ff21514d8981	931	uint32_t RESERVED1[1U];
AnnaBridge	156:ff21514d8981	932	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
AnnaBridge	156:ff21514d8981	933	__IOM uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
AnnaBridge	156:ff21514d8981	934	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
AnnaBridge	156:ff21514d8981	935	uint32_t RESERVED2[1U];
AnnaBridge	156:ff21514d8981	936	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
AnnaBridge	156:ff21514d8981	937	__IOM uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
AnnaBridge	156:ff21514d8981	938	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
AnnaBridge	156:ff21514d8981	939	} DWT_Type;
AnnaBridge	156:ff21514d8981	940
AnnaBridge	156:ff21514d8981	941	/* DWT Control Register Definitions */
AnnaBridge	156:ff21514d8981	942	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
AnnaBridge	156:ff21514d8981	943	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
AnnaBridge	156:ff21514d8981	944
AnnaBridge	156:ff21514d8981	945	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
AnnaBridge	156:ff21514d8981	946	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
AnnaBridge	156:ff21514d8981	947
AnnaBridge	156:ff21514d8981	948	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
AnnaBridge	156:ff21514d8981	949	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
AnnaBridge	156:ff21514d8981	950
AnnaBridge	156:ff21514d8981	951	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
AnnaBridge	156:ff21514d8981	952	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
AnnaBridge	156:ff21514d8981	953
AnnaBridge	156:ff21514d8981	954	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
AnnaBridge	156:ff21514d8981	955	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
AnnaBridge	156:ff21514d8981	956
AnnaBridge	156:ff21514d8981	957	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
AnnaBridge	156:ff21514d8981	958	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
AnnaBridge	156:ff21514d8981	959
AnnaBridge	156:ff21514d8981	960	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
AnnaBridge	156:ff21514d8981	961	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
AnnaBridge	156:ff21514d8981	962
AnnaBridge	156:ff21514d8981	963	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
AnnaBridge	156:ff21514d8981	964	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
AnnaBridge	156:ff21514d8981	965
AnnaBridge	156:ff21514d8981	966	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
AnnaBridge	156:ff21514d8981	967	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
AnnaBridge	156:ff21514d8981	968
AnnaBridge	156:ff21514d8981	969	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
AnnaBridge	156:ff21514d8981	970	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
AnnaBridge	156:ff21514d8981	971
AnnaBridge	156:ff21514d8981	972	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
AnnaBridge	156:ff21514d8981	973	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
AnnaBridge	156:ff21514d8981	974
AnnaBridge	156:ff21514d8981	975	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
AnnaBridge	156:ff21514d8981	976	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
AnnaBridge	156:ff21514d8981	977
AnnaBridge	156:ff21514d8981	978	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
AnnaBridge	156:ff21514d8981	979	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
AnnaBridge	156:ff21514d8981	980
AnnaBridge	156:ff21514d8981	981	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
AnnaBridge	156:ff21514d8981	982	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
AnnaBridge	156:ff21514d8981	983
AnnaBridge	156:ff21514d8981	984	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
AnnaBridge	156:ff21514d8981	985	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
AnnaBridge	156:ff21514d8981	986
AnnaBridge	156:ff21514d8981	987	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
AnnaBridge	156:ff21514d8981	988	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
AnnaBridge	156:ff21514d8981	989
AnnaBridge	156:ff21514d8981	990	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
AnnaBridge	156:ff21514d8981	991	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
AnnaBridge	156:ff21514d8981	992
AnnaBridge	156:ff21514d8981	993	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
AnnaBridge	156:ff21514d8981	994	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
AnnaBridge	156:ff21514d8981	995
AnnaBridge	156:ff21514d8981	996	/* DWT CPI Count Register Definitions */
AnnaBridge	156:ff21514d8981	997	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
AnnaBridge	156:ff21514d8981	998	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
AnnaBridge	156:ff21514d8981	999
AnnaBridge	156:ff21514d8981	1000	/* DWT Exception Overhead Count Register Definitions */
AnnaBridge	156:ff21514d8981	1001	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
AnnaBridge	156:ff21514d8981	1002	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
AnnaBridge	156:ff21514d8981	1003
AnnaBridge	156:ff21514d8981	1004	/* DWT Sleep Count Register Definitions */
AnnaBridge	156:ff21514d8981	1005	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
AnnaBridge	156:ff21514d8981	1006	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
AnnaBridge	156:ff21514d8981	1007
AnnaBridge	156:ff21514d8981	1008	/* DWT LSU Count Register Definitions */
AnnaBridge	156:ff21514d8981	1009	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
AnnaBridge	156:ff21514d8981	1010	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
AnnaBridge	156:ff21514d8981	1011
AnnaBridge	156:ff21514d8981	1012	/* DWT Folded-instruction Count Register Definitions */
AnnaBridge	156:ff21514d8981	1013	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
AnnaBridge	156:ff21514d8981	1014	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
AnnaBridge	156:ff21514d8981	1015
AnnaBridge	156:ff21514d8981	1016	/* DWT Comparator Mask Register Definitions */
AnnaBridge	156:ff21514d8981	1017	#define DWT_MASK_MASK_Pos 0U /!< DWT MASK: MASK Position /
AnnaBridge	156:ff21514d8981	1018	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
AnnaBridge	156:ff21514d8981	1019
AnnaBridge	156:ff21514d8981	1020	/* DWT Comparator Function Register Definitions */
AnnaBridge	156:ff21514d8981	1021	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
AnnaBridge	156:ff21514d8981	1022	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
AnnaBridge	156:ff21514d8981	1023
AnnaBridge	156:ff21514d8981	1024	#define DWT_FUNCTION_DATAVADDR1_Pos 16U /!< DWT FUNCTION: DATAVADDR1 Position /
AnnaBridge	156:ff21514d8981	1025	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
AnnaBridge	156:ff21514d8981	1026
AnnaBridge	156:ff21514d8981	1027	#define DWT_FUNCTION_DATAVADDR0_Pos 12U /!< DWT FUNCTION: DATAVADDR0 Position /
AnnaBridge	156:ff21514d8981	1028	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
AnnaBridge	156:ff21514d8981	1029
AnnaBridge	156:ff21514d8981	1030	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
AnnaBridge	156:ff21514d8981	1031	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
AnnaBridge	156:ff21514d8981	1032
AnnaBridge	156:ff21514d8981	1033	#define DWT_FUNCTION_LNK1ENA_Pos 9U /!< DWT FUNCTION: LNK1ENA Position /
AnnaBridge	156:ff21514d8981	1034	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
AnnaBridge	156:ff21514d8981	1035
AnnaBridge	156:ff21514d8981	1036	#define DWT_FUNCTION_DATAVMATCH_Pos 8U /!< DWT FUNCTION: DATAVMATCH Position /
AnnaBridge	156:ff21514d8981	1037	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
AnnaBridge	156:ff21514d8981	1038
AnnaBridge	156:ff21514d8981	1039	#define DWT_FUNCTION_CYCMATCH_Pos 7U /!< DWT FUNCTION: CYCMATCH Position /
AnnaBridge	156:ff21514d8981	1040	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
AnnaBridge	156:ff21514d8981	1041
AnnaBridge	156:ff21514d8981	1042	#define DWT_FUNCTION_EMITRANGE_Pos 5U /!< DWT FUNCTION: EMITRANGE Position /
AnnaBridge	156:ff21514d8981	1043	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
AnnaBridge	156:ff21514d8981	1044
AnnaBridge	156:ff21514d8981	1045	#define DWT_FUNCTION_FUNCTION_Pos 0U /!< DWT FUNCTION: FUNCTION Position /
AnnaBridge	156:ff21514d8981	1046	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
AnnaBridge	156:ff21514d8981	1047
AnnaBridge	156:ff21514d8981	1048	/@}/ /* end of group CMSIS_DWT */
AnnaBridge	156:ff21514d8981	1049
AnnaBridge	156:ff21514d8981	1050
AnnaBridge	156:ff21514d8981	1051	/**
AnnaBridge	156:ff21514d8981	1052	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	1053	\defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge	156:ff21514d8981	1054	\brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge	156:ff21514d8981	1055	@{
AnnaBridge	156:ff21514d8981	1056	*/
AnnaBridge	156:ff21514d8981	1057
AnnaBridge	156:ff21514d8981	1058	/**
AnnaBridge	156:ff21514d8981	1059	\brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge	156:ff21514d8981	1060	*/
AnnaBridge	156:ff21514d8981	1061	typedef struct
AnnaBridge	156:ff21514d8981	1062	{
AnnaBridge	156:ff21514d8981	1063	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
AnnaBridge	156:ff21514d8981	1064	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
AnnaBridge	156:ff21514d8981	1065	uint32_t RESERVED0[2U];
AnnaBridge	156:ff21514d8981	1066	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
AnnaBridge	156:ff21514d8981	1067	uint32_t RESERVED1[55U];
AnnaBridge	156:ff21514d8981	1068	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
AnnaBridge	156:ff21514d8981	1069	uint32_t RESERVED2[131U];
AnnaBridge	156:ff21514d8981	1070	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
AnnaBridge	156:ff21514d8981	1071	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
AnnaBridge	156:ff21514d8981	1072	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
AnnaBridge	156:ff21514d8981	1073	uint32_t RESERVED3[759U];
AnnaBridge	156:ff21514d8981	1074	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
AnnaBridge	156:ff21514d8981	1075	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
AnnaBridge	156:ff21514d8981	1076	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
AnnaBridge	156:ff21514d8981	1077	uint32_t RESERVED4[1U];
AnnaBridge	156:ff21514d8981	1078	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
AnnaBridge	156:ff21514d8981	1079	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
AnnaBridge	156:ff21514d8981	1080	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
AnnaBridge	156:ff21514d8981	1081	uint32_t RESERVED5[39U];
AnnaBridge	156:ff21514d8981	1082	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
AnnaBridge	156:ff21514d8981	1083	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
AnnaBridge	156:ff21514d8981	1084	uint32_t RESERVED7[8U];
AnnaBridge	156:ff21514d8981	1085	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
AnnaBridge	156:ff21514d8981	1086	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
AnnaBridge	156:ff21514d8981	1087	} TPI_Type;
AnnaBridge	156:ff21514d8981	1088
AnnaBridge	156:ff21514d8981	1089	/* TPI Asynchronous Clock Prescaler Register Definitions */
Anna Bridge	169:a7c7b631e539	1090	#define TPI_ACPR_PRESCALER_Pos 0U /!< @Deprecated TPI ACPR: PRESCALER Position /
Anna Bridge	169:a7c7b631e539	1091	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< @Deprecated TPI ACPR: PRESCALER Mask /
Anna Bridge	169:a7c7b631e539	1092
Anna Bridge	169:a7c7b631e539	1093	#define TPI_ACPR_SWOSCALER_Pos 0U /!< TPI ACPR: SWOSCALER Position /
Anna Bridge	169:a7c7b631e539	1094	#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/) /!< TPI ACPR: SWOSCALER Mask /
AnnaBridge	156:ff21514d8981	1095
AnnaBridge	156:ff21514d8981	1096	/* TPI Selected Pin Protocol Register Definitions */
AnnaBridge	156:ff21514d8981	1097	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
AnnaBridge	156:ff21514d8981	1098	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
AnnaBridge	156:ff21514d8981	1099
AnnaBridge	156:ff21514d8981	1100	/* TPI Formatter and Flush Status Register Definitions */
AnnaBridge	156:ff21514d8981	1101	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
AnnaBridge	156:ff21514d8981	1102	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
AnnaBridge	156:ff21514d8981	1103
AnnaBridge	156:ff21514d8981	1104	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
AnnaBridge	156:ff21514d8981	1105	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
AnnaBridge	156:ff21514d8981	1106
AnnaBridge	156:ff21514d8981	1107	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
AnnaBridge	156:ff21514d8981	1108	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
AnnaBridge	156:ff21514d8981	1109
AnnaBridge	156:ff21514d8981	1110	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
AnnaBridge	156:ff21514d8981	1111	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
AnnaBridge	156:ff21514d8981	1112
AnnaBridge	156:ff21514d8981	1113	/* TPI Formatter and Flush Control Register Definitions */
AnnaBridge	156:ff21514d8981	1114	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
AnnaBridge	156:ff21514d8981	1115	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
AnnaBridge	156:ff21514d8981	1116
AnnaBridge	156:ff21514d8981	1117	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
AnnaBridge	156:ff21514d8981	1118	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
AnnaBridge	156:ff21514d8981	1119
AnnaBridge	156:ff21514d8981	1120	/* TPI TRIGGER Register Definitions */
AnnaBridge	156:ff21514d8981	1121	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
AnnaBridge	156:ff21514d8981	1122	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
AnnaBridge	156:ff21514d8981	1123
AnnaBridge	156:ff21514d8981	1124	/* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge	156:ff21514d8981	1125	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
AnnaBridge	156:ff21514d8981	1126	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
AnnaBridge	156:ff21514d8981	1127
AnnaBridge	156:ff21514d8981	1128	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
AnnaBridge	156:ff21514d8981	1129	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
AnnaBridge	156:ff21514d8981	1130
AnnaBridge	156:ff21514d8981	1131	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
AnnaBridge	156:ff21514d8981	1132	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
AnnaBridge	156:ff21514d8981	1133
AnnaBridge	156:ff21514d8981	1134	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
AnnaBridge	156:ff21514d8981	1135	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
AnnaBridge	156:ff21514d8981	1136
AnnaBridge	156:ff21514d8981	1137	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
AnnaBridge	156:ff21514d8981	1138	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
AnnaBridge	156:ff21514d8981	1139
AnnaBridge	156:ff21514d8981	1140	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
AnnaBridge	156:ff21514d8981	1141	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
AnnaBridge	156:ff21514d8981	1142
AnnaBridge	156:ff21514d8981	1143	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
AnnaBridge	156:ff21514d8981	1144	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
AnnaBridge	156:ff21514d8981	1145
AnnaBridge	156:ff21514d8981	1146	/* TPI ITATBCTR2 Register Definitions */
AnnaBridge	156:ff21514d8981	1147	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
AnnaBridge	156:ff21514d8981	1148	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
AnnaBridge	156:ff21514d8981	1149
AnnaBridge	156:ff21514d8981	1150	/* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge	156:ff21514d8981	1151	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
AnnaBridge	156:ff21514d8981	1152	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
AnnaBridge	156:ff21514d8981	1153
AnnaBridge	156:ff21514d8981	1154	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
AnnaBridge	156:ff21514d8981	1155	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
AnnaBridge	156:ff21514d8981	1156
AnnaBridge	156:ff21514d8981	1157	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
AnnaBridge	156:ff21514d8981	1158	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
AnnaBridge	156:ff21514d8981	1159
AnnaBridge	156:ff21514d8981	1160	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
AnnaBridge	156:ff21514d8981	1161	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
AnnaBridge	156:ff21514d8981	1162
AnnaBridge	156:ff21514d8981	1163	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
AnnaBridge	156:ff21514d8981	1164	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
AnnaBridge	156:ff21514d8981	1165
AnnaBridge	156:ff21514d8981	1166	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
AnnaBridge	156:ff21514d8981	1167	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
AnnaBridge	156:ff21514d8981	1168
AnnaBridge	156:ff21514d8981	1169	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
AnnaBridge	156:ff21514d8981	1170	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
AnnaBridge	156:ff21514d8981	1171
AnnaBridge	156:ff21514d8981	1172	/* TPI ITATBCTR0 Register Definitions */
AnnaBridge	156:ff21514d8981	1173	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
AnnaBridge	156:ff21514d8981	1174	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
AnnaBridge	156:ff21514d8981	1175
AnnaBridge	156:ff21514d8981	1176	/* TPI Integration Mode Control Register Definitions */
AnnaBridge	156:ff21514d8981	1177	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
AnnaBridge	156:ff21514d8981	1178	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
AnnaBridge	156:ff21514d8981	1179
AnnaBridge	156:ff21514d8981	1180	/* TPI DEVID Register Definitions */
AnnaBridge	156:ff21514d8981	1181	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
AnnaBridge	156:ff21514d8981	1182	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
AnnaBridge	156:ff21514d8981	1183
AnnaBridge	156:ff21514d8981	1184	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
AnnaBridge	156:ff21514d8981	1185	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
AnnaBridge	156:ff21514d8981	1186
AnnaBridge	156:ff21514d8981	1187	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
AnnaBridge	156:ff21514d8981	1188	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
AnnaBridge	156:ff21514d8981	1189
AnnaBridge	156:ff21514d8981	1190	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
AnnaBridge	156:ff21514d8981	1191	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
AnnaBridge	156:ff21514d8981	1192
AnnaBridge	156:ff21514d8981	1193	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
AnnaBridge	156:ff21514d8981	1194	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
AnnaBridge	156:ff21514d8981	1195
AnnaBridge	156:ff21514d8981	1196	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
AnnaBridge	156:ff21514d8981	1197	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
AnnaBridge	156:ff21514d8981	1198
AnnaBridge	156:ff21514d8981	1199	/* TPI DEVTYPE Register Definitions */
AnnaBridge	156:ff21514d8981	1200	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
AnnaBridge	156:ff21514d8981	1201	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
AnnaBridge	156:ff21514d8981	1202
AnnaBridge	156:ff21514d8981	1203	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
AnnaBridge	156:ff21514d8981	1204	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
AnnaBridge	156:ff21514d8981	1205
AnnaBridge	156:ff21514d8981	1206	/@}/ /* end of group CMSIS_TPI */
AnnaBridge	156:ff21514d8981	1207
AnnaBridge	156:ff21514d8981	1208
AnnaBridge	156:ff21514d8981	1209	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	1210	/**
AnnaBridge	156:ff21514d8981	1211	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	1212	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge	156:ff21514d8981	1213	\brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge	156:ff21514d8981	1214	@{
AnnaBridge	156:ff21514d8981	1215	*/
AnnaBridge	156:ff21514d8981	1216
AnnaBridge	156:ff21514d8981	1217	/**
AnnaBridge	156:ff21514d8981	1218	\brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge	156:ff21514d8981	1219	*/
AnnaBridge	156:ff21514d8981	1220	typedef struct
AnnaBridge	156:ff21514d8981	1221	{
AnnaBridge	156:ff21514d8981	1222	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
AnnaBridge	156:ff21514d8981	1223	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
AnnaBridge	156:ff21514d8981	1224	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
AnnaBridge	156:ff21514d8981	1225	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
AnnaBridge	156:ff21514d8981	1226	__IOM uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
AnnaBridge	156:ff21514d8981	1227	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
AnnaBridge	156:ff21514d8981	1228	__IOM uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
AnnaBridge	156:ff21514d8981	1229	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
AnnaBridge	156:ff21514d8981	1230	__IOM uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
AnnaBridge	156:ff21514d8981	1231	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
AnnaBridge	156:ff21514d8981	1232	__IOM uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
AnnaBridge	156:ff21514d8981	1233	} MPU_Type;
AnnaBridge	156:ff21514d8981	1234
Anna Bridge	160:5571c4ff569f	1235	#define MPU_TYPE_RALIASES 4U
Anna Bridge	160:5571c4ff569f	1236
AnnaBridge	156:ff21514d8981	1237	/* MPU Type Register Definitions */
AnnaBridge	156:ff21514d8981	1238	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
AnnaBridge	156:ff21514d8981	1239	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
AnnaBridge	156:ff21514d8981	1240
AnnaBridge	156:ff21514d8981	1241	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
AnnaBridge	156:ff21514d8981	1242	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
AnnaBridge	156:ff21514d8981	1243
AnnaBridge	156:ff21514d8981	1244	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
AnnaBridge	156:ff21514d8981	1245	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
AnnaBridge	156:ff21514d8981	1246
AnnaBridge	156:ff21514d8981	1247	/* MPU Control Register Definitions */
AnnaBridge	156:ff21514d8981	1248	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
AnnaBridge	156:ff21514d8981	1249	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
AnnaBridge	156:ff21514d8981	1250
AnnaBridge	156:ff21514d8981	1251	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
AnnaBridge	156:ff21514d8981	1252	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
AnnaBridge	156:ff21514d8981	1253
AnnaBridge	156:ff21514d8981	1254	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
AnnaBridge	156:ff21514d8981	1255	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
AnnaBridge	156:ff21514d8981	1256
AnnaBridge	156:ff21514d8981	1257	/* MPU Region Number Register Definitions */
AnnaBridge	156:ff21514d8981	1258	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
AnnaBridge	156:ff21514d8981	1259	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
AnnaBridge	156:ff21514d8981	1260
AnnaBridge	156:ff21514d8981	1261	/* MPU Region Base Address Register Definitions */
AnnaBridge	156:ff21514d8981	1262	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
AnnaBridge	156:ff21514d8981	1263	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
AnnaBridge	156:ff21514d8981	1264
AnnaBridge	156:ff21514d8981	1265	#define MPU_RBAR_VALID_Pos 4U /!< MPU RBAR: VALID Position /
AnnaBridge	156:ff21514d8981	1266	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
AnnaBridge	156:ff21514d8981	1267
AnnaBridge	156:ff21514d8981	1268	#define MPU_RBAR_REGION_Pos 0U /!< MPU RBAR: REGION Position /
AnnaBridge	156:ff21514d8981	1269	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
AnnaBridge	156:ff21514d8981	1270
AnnaBridge	156:ff21514d8981	1271	/* MPU Region Attribute and Size Register Definitions */
AnnaBridge	156:ff21514d8981	1272	#define MPU_RASR_ATTRS_Pos 16U /!< MPU RASR: MPU Region Attribute field Position /
AnnaBridge	156:ff21514d8981	1273	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
AnnaBridge	156:ff21514d8981	1274
AnnaBridge	156:ff21514d8981	1275	#define MPU_RASR_XN_Pos 28U /!< MPU RASR: ATTRS.XN Position /
AnnaBridge	156:ff21514d8981	1276	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
AnnaBridge	156:ff21514d8981	1277
AnnaBridge	156:ff21514d8981	1278	#define MPU_RASR_AP_Pos 24U /!< MPU RASR: ATTRS.AP Position /
AnnaBridge	156:ff21514d8981	1279	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
AnnaBridge	156:ff21514d8981	1280
AnnaBridge	156:ff21514d8981	1281	#define MPU_RASR_TEX_Pos 19U /!< MPU RASR: ATTRS.TEX Position /
AnnaBridge	156:ff21514d8981	1282	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
AnnaBridge	156:ff21514d8981	1283
AnnaBridge	156:ff21514d8981	1284	#define MPU_RASR_S_Pos 18U /!< MPU RASR: ATTRS.S Position /
AnnaBridge	156:ff21514d8981	1285	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
AnnaBridge	156:ff21514d8981	1286
AnnaBridge	156:ff21514d8981	1287	#define MPU_RASR_C_Pos 17U /!< MPU RASR: ATTRS.C Position /
AnnaBridge	156:ff21514d8981	1288	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
AnnaBridge	156:ff21514d8981	1289
AnnaBridge	156:ff21514d8981	1290	#define MPU_RASR_B_Pos 16U /!< MPU RASR: ATTRS.B Position /
AnnaBridge	156:ff21514d8981	1291	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
AnnaBridge	156:ff21514d8981	1292
AnnaBridge	156:ff21514d8981	1293	#define MPU_RASR_SRD_Pos 8U /!< MPU RASR: Sub-Region Disable Position /
AnnaBridge	156:ff21514d8981	1294	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
AnnaBridge	156:ff21514d8981	1295
AnnaBridge	156:ff21514d8981	1296	#define MPU_RASR_SIZE_Pos 1U /!< MPU RASR: Region Size Field Position /
AnnaBridge	156:ff21514d8981	1297	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
AnnaBridge	156:ff21514d8981	1298
AnnaBridge	156:ff21514d8981	1299	#define MPU_RASR_ENABLE_Pos 0U /!< MPU RASR: Region enable bit Position /
AnnaBridge	156:ff21514d8981	1300	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
AnnaBridge	156:ff21514d8981	1301
AnnaBridge	156:ff21514d8981	1302	/@} end of group CMSIS_MPU /
AnnaBridge	156:ff21514d8981	1303	#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
AnnaBridge	156:ff21514d8981	1304
AnnaBridge	156:ff21514d8981	1305
AnnaBridge	156:ff21514d8981	1306	/**
AnnaBridge	156:ff21514d8981	1307	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	1308	\defgroup CMSIS_FPU Floating Point Unit (FPU)
AnnaBridge	156:ff21514d8981	1309	\brief Type definitions for the Floating Point Unit (FPU)
AnnaBridge	156:ff21514d8981	1310	@{
AnnaBridge	156:ff21514d8981	1311	*/
AnnaBridge	156:ff21514d8981	1312
AnnaBridge	156:ff21514d8981	1313	/**
AnnaBridge	156:ff21514d8981	1314	\brief Structure type to access the Floating Point Unit (FPU).
AnnaBridge	156:ff21514d8981	1315	*/
AnnaBridge	156:ff21514d8981	1316	typedef struct
AnnaBridge	156:ff21514d8981	1317	{
AnnaBridge	156:ff21514d8981	1318	uint32_t RESERVED0[1U];
AnnaBridge	156:ff21514d8981	1319	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
AnnaBridge	156:ff21514d8981	1320	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
AnnaBridge	156:ff21514d8981	1321	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
AnnaBridge	156:ff21514d8981	1322	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
AnnaBridge	156:ff21514d8981	1323	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
AnnaBridge	156:ff21514d8981	1324	} FPU_Type;
AnnaBridge	156:ff21514d8981	1325
AnnaBridge	156:ff21514d8981	1326	/* Floating-Point Context Control Register Definitions */
AnnaBridge	156:ff21514d8981	1327	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
AnnaBridge	156:ff21514d8981	1328	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
AnnaBridge	156:ff21514d8981	1329
AnnaBridge	156:ff21514d8981	1330	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
AnnaBridge	156:ff21514d8981	1331	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
AnnaBridge	156:ff21514d8981	1332
AnnaBridge	156:ff21514d8981	1333	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
AnnaBridge	156:ff21514d8981	1334	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
AnnaBridge	156:ff21514d8981	1335
AnnaBridge	156:ff21514d8981	1336	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
AnnaBridge	156:ff21514d8981	1337	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
AnnaBridge	156:ff21514d8981	1338
AnnaBridge	156:ff21514d8981	1339	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
AnnaBridge	156:ff21514d8981	1340	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
AnnaBridge	156:ff21514d8981	1341
AnnaBridge	156:ff21514d8981	1342	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
AnnaBridge	156:ff21514d8981	1343	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
AnnaBridge	156:ff21514d8981	1344
AnnaBridge	156:ff21514d8981	1345	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
AnnaBridge	156:ff21514d8981	1346	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
AnnaBridge	156:ff21514d8981	1347
AnnaBridge	156:ff21514d8981	1348	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
AnnaBridge	156:ff21514d8981	1349	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
AnnaBridge	156:ff21514d8981	1350
AnnaBridge	156:ff21514d8981	1351	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
AnnaBridge	156:ff21514d8981	1352	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
AnnaBridge	156:ff21514d8981	1353
AnnaBridge	156:ff21514d8981	1354	/* Floating-Point Context Address Register Definitions */
AnnaBridge	156:ff21514d8981	1355	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
AnnaBridge	156:ff21514d8981	1356	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
AnnaBridge	156:ff21514d8981	1357
AnnaBridge	156:ff21514d8981	1358	/* Floating-Point Default Status Control Register Definitions */
AnnaBridge	156:ff21514d8981	1359	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
AnnaBridge	156:ff21514d8981	1360	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
AnnaBridge	156:ff21514d8981	1361
AnnaBridge	156:ff21514d8981	1362	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
AnnaBridge	156:ff21514d8981	1363	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
AnnaBridge	156:ff21514d8981	1364
AnnaBridge	156:ff21514d8981	1365	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
AnnaBridge	156:ff21514d8981	1366	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
AnnaBridge	156:ff21514d8981	1367
AnnaBridge	156:ff21514d8981	1368	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
AnnaBridge	156:ff21514d8981	1369	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
AnnaBridge	156:ff21514d8981	1370
AnnaBridge	156:ff21514d8981	1371	/* Media and FP Feature Register 0 Definitions */
AnnaBridge	156:ff21514d8981	1372	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
AnnaBridge	156:ff21514d8981	1373	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
AnnaBridge	156:ff21514d8981	1374
AnnaBridge	156:ff21514d8981	1375	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
AnnaBridge	156:ff21514d8981	1376	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
AnnaBridge	156:ff21514d8981	1377
AnnaBridge	156:ff21514d8981	1378	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
AnnaBridge	156:ff21514d8981	1379	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
AnnaBridge	156:ff21514d8981	1380
AnnaBridge	156:ff21514d8981	1381	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
AnnaBridge	156:ff21514d8981	1382	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
AnnaBridge	156:ff21514d8981	1383
AnnaBridge	156:ff21514d8981	1384	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
AnnaBridge	156:ff21514d8981	1385	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
AnnaBridge	156:ff21514d8981	1386
AnnaBridge	156:ff21514d8981	1387	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
AnnaBridge	156:ff21514d8981	1388	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
AnnaBridge	156:ff21514d8981	1389
AnnaBridge	156:ff21514d8981	1390	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
AnnaBridge	156:ff21514d8981	1391	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
AnnaBridge	156:ff21514d8981	1392
AnnaBridge	156:ff21514d8981	1393	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
AnnaBridge	156:ff21514d8981	1394	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
AnnaBridge	156:ff21514d8981	1395
AnnaBridge	156:ff21514d8981	1396	/* Media and FP Feature Register 1 Definitions */
AnnaBridge	156:ff21514d8981	1397	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
AnnaBridge	156:ff21514d8981	1398	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
AnnaBridge	156:ff21514d8981	1399
AnnaBridge	156:ff21514d8981	1400	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
AnnaBridge	156:ff21514d8981	1401	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
AnnaBridge	156:ff21514d8981	1402
AnnaBridge	156:ff21514d8981	1403	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
AnnaBridge	156:ff21514d8981	1404	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
AnnaBridge	156:ff21514d8981	1405
AnnaBridge	156:ff21514d8981	1406	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
AnnaBridge	156:ff21514d8981	1407	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
AnnaBridge	156:ff21514d8981	1408
AnnaBridge	156:ff21514d8981	1409	/@} end of group CMSIS_FPU /
AnnaBridge	156:ff21514d8981	1410
AnnaBridge	156:ff21514d8981	1411
AnnaBridge	156:ff21514d8981	1412	/**
AnnaBridge	156:ff21514d8981	1413	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	1414	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge	156:ff21514d8981	1415	\brief Type definitions for the Core Debug Registers
AnnaBridge	156:ff21514d8981	1416	@{
AnnaBridge	156:ff21514d8981	1417	*/
AnnaBridge	156:ff21514d8981	1418
AnnaBridge	156:ff21514d8981	1419	/**
AnnaBridge	156:ff21514d8981	1420	\brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge	156:ff21514d8981	1421	*/
AnnaBridge	156:ff21514d8981	1422	typedef struct
AnnaBridge	156:ff21514d8981	1423	{
AnnaBridge	156:ff21514d8981	1424	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
AnnaBridge	156:ff21514d8981	1425	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
AnnaBridge	156:ff21514d8981	1426	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
AnnaBridge	156:ff21514d8981	1427	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
AnnaBridge	156:ff21514d8981	1428	} CoreDebug_Type;
AnnaBridge	156:ff21514d8981	1429
AnnaBridge	156:ff21514d8981	1430	/* Debug Halting Control and Status Register Definitions */
AnnaBridge	156:ff21514d8981	1431	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
AnnaBridge	156:ff21514d8981	1432	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
AnnaBridge	156:ff21514d8981	1433
AnnaBridge	156:ff21514d8981	1434	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
AnnaBridge	156:ff21514d8981	1435	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
AnnaBridge	156:ff21514d8981	1436
AnnaBridge	156:ff21514d8981	1437	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
AnnaBridge	156:ff21514d8981	1438	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
AnnaBridge	156:ff21514d8981	1439
AnnaBridge	156:ff21514d8981	1440	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
AnnaBridge	156:ff21514d8981	1441	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
AnnaBridge	156:ff21514d8981	1442
AnnaBridge	156:ff21514d8981	1443	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
AnnaBridge	156:ff21514d8981	1444	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
AnnaBridge	156:ff21514d8981	1445
AnnaBridge	156:ff21514d8981	1446	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
AnnaBridge	156:ff21514d8981	1447	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
AnnaBridge	156:ff21514d8981	1448
AnnaBridge	156:ff21514d8981	1449	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
AnnaBridge	156:ff21514d8981	1450	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
AnnaBridge	156:ff21514d8981	1451
AnnaBridge	156:ff21514d8981	1452	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
AnnaBridge	156:ff21514d8981	1453	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
AnnaBridge	156:ff21514d8981	1454
AnnaBridge	156:ff21514d8981	1455	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
AnnaBridge	156:ff21514d8981	1456	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
AnnaBridge	156:ff21514d8981	1457
AnnaBridge	156:ff21514d8981	1458	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
AnnaBridge	156:ff21514d8981	1459	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
AnnaBridge	156:ff21514d8981	1460
AnnaBridge	156:ff21514d8981	1461	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
AnnaBridge	156:ff21514d8981	1462	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
AnnaBridge	156:ff21514d8981	1463
AnnaBridge	156:ff21514d8981	1464	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
AnnaBridge	156:ff21514d8981	1465	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
AnnaBridge	156:ff21514d8981	1466
AnnaBridge	156:ff21514d8981	1467	/* Debug Core Register Selector Register Definitions */
AnnaBridge	156:ff21514d8981	1468	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
AnnaBridge	156:ff21514d8981	1469	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
AnnaBridge	156:ff21514d8981	1470
AnnaBridge	156:ff21514d8981	1471	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
AnnaBridge	156:ff21514d8981	1472	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
AnnaBridge	156:ff21514d8981	1473
AnnaBridge	156:ff21514d8981	1474	/* Debug Exception and Monitor Control Register Definitions */
AnnaBridge	156:ff21514d8981	1475	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
AnnaBridge	156:ff21514d8981	1476	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
AnnaBridge	156:ff21514d8981	1477
AnnaBridge	156:ff21514d8981	1478	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
AnnaBridge	156:ff21514d8981	1479	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
AnnaBridge	156:ff21514d8981	1480
AnnaBridge	156:ff21514d8981	1481	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
AnnaBridge	156:ff21514d8981	1482	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
AnnaBridge	156:ff21514d8981	1483
AnnaBridge	156:ff21514d8981	1484	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
AnnaBridge	156:ff21514d8981	1485	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
AnnaBridge	156:ff21514d8981	1486
AnnaBridge	156:ff21514d8981	1487	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
AnnaBridge	156:ff21514d8981	1488	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
AnnaBridge	156:ff21514d8981	1489
AnnaBridge	156:ff21514d8981	1490	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
AnnaBridge	156:ff21514d8981	1491	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
AnnaBridge	156:ff21514d8981	1492
AnnaBridge	156:ff21514d8981	1493	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
AnnaBridge	156:ff21514d8981	1494	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
AnnaBridge	156:ff21514d8981	1495
AnnaBridge	156:ff21514d8981	1496	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
AnnaBridge	156:ff21514d8981	1497	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
AnnaBridge	156:ff21514d8981	1498
AnnaBridge	156:ff21514d8981	1499	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
AnnaBridge	156:ff21514d8981	1500	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
AnnaBridge	156:ff21514d8981	1501
AnnaBridge	156:ff21514d8981	1502	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
AnnaBridge	156:ff21514d8981	1503	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
AnnaBridge	156:ff21514d8981	1504
AnnaBridge	156:ff21514d8981	1505	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
AnnaBridge	156:ff21514d8981	1506	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
AnnaBridge	156:ff21514d8981	1507
AnnaBridge	156:ff21514d8981	1508	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
AnnaBridge	156:ff21514d8981	1509	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
AnnaBridge	156:ff21514d8981	1510
AnnaBridge	156:ff21514d8981	1511	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
AnnaBridge	156:ff21514d8981	1512	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
AnnaBridge	156:ff21514d8981	1513
AnnaBridge	156:ff21514d8981	1514	/@} end of group CMSIS_CoreDebug /
AnnaBridge	156:ff21514d8981	1515
AnnaBridge	156:ff21514d8981	1516
AnnaBridge	156:ff21514d8981	1517	/**
AnnaBridge	156:ff21514d8981	1518	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	1519	\defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge	156:ff21514d8981	1520	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge	156:ff21514d8981	1521	@{
AnnaBridge	156:ff21514d8981	1522	*/
AnnaBridge	156:ff21514d8981	1523
AnnaBridge	156:ff21514d8981	1524	/**
AnnaBridge	156:ff21514d8981	1525	\brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge	156:ff21514d8981	1526	\param[in] field Name of the register bit field.
AnnaBridge	156:ff21514d8981	1527	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge	156:ff21514d8981	1528	\return Masked and shifted value.
AnnaBridge	156:ff21514d8981	1529	*/
AnnaBridge	156:ff21514d8981	1530	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge	156:ff21514d8981	1531
AnnaBridge	156:ff21514d8981	1532	/**
AnnaBridge	156:ff21514d8981	1533	\brief Mask and shift a register value to extract a bit filed value.
AnnaBridge	156:ff21514d8981	1534	\param[in] field Name of the register bit field.
AnnaBridge	156:ff21514d8981	1535	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge	156:ff21514d8981	1536	\return Masked and shifted bit field value.
AnnaBridge	156:ff21514d8981	1537	*/
AnnaBridge	156:ff21514d8981	1538	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge	156:ff21514d8981	1539
AnnaBridge	156:ff21514d8981	1540	/@} end of group CMSIS_core_bitfield /
AnnaBridge	156:ff21514d8981	1541
AnnaBridge	156:ff21514d8981	1542
AnnaBridge	156:ff21514d8981	1543	/**
AnnaBridge	156:ff21514d8981	1544	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	1545	\defgroup CMSIS_core_base Core Definitions
AnnaBridge	156:ff21514d8981	1546	\brief Definitions for base addresses, unions, and structures.
AnnaBridge	156:ff21514d8981	1547	@{
AnnaBridge	156:ff21514d8981	1548	*/
AnnaBridge	156:ff21514d8981	1549
AnnaBridge	156:ff21514d8981	1550	/* Memory mapping of Core Hardware */
AnnaBridge	156:ff21514d8981	1551	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
AnnaBridge	156:ff21514d8981	1552	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
AnnaBridge	156:ff21514d8981	1553	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
AnnaBridge	156:ff21514d8981	1554	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
AnnaBridge	156:ff21514d8981	1555	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
AnnaBridge	156:ff21514d8981	1556	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
AnnaBridge	156:ff21514d8981	1557	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
AnnaBridge	156:ff21514d8981	1558	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
AnnaBridge	156:ff21514d8981	1559
AnnaBridge	156:ff21514d8981	1560	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
AnnaBridge	156:ff21514d8981	1561	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
AnnaBridge	156:ff21514d8981	1562	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
AnnaBridge	156:ff21514d8981	1563	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
AnnaBridge	156:ff21514d8981	1564	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
AnnaBridge	156:ff21514d8981	1565	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
AnnaBridge	156:ff21514d8981	1566	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
AnnaBridge	156:ff21514d8981	1567	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
AnnaBridge	156:ff21514d8981	1568
AnnaBridge	156:ff21514d8981	1569	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	1570	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
AnnaBridge	156:ff21514d8981	1571	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
AnnaBridge	156:ff21514d8981	1572	#endif
AnnaBridge	156:ff21514d8981	1573
AnnaBridge	156:ff21514d8981	1574	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
AnnaBridge	156:ff21514d8981	1575	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
AnnaBridge	156:ff21514d8981	1576
AnnaBridge	156:ff21514d8981	1577	/@} /
AnnaBridge	156:ff21514d8981	1578
AnnaBridge	156:ff21514d8981	1579
AnnaBridge	156:ff21514d8981	1580
AnnaBridge	156:ff21514d8981	1581	/*******************************************************************************
AnnaBridge	156:ff21514d8981	1582	* Hardware Abstraction Layer
AnnaBridge	156:ff21514d8981	1583	Core Function Interface contains:
AnnaBridge	156:ff21514d8981	1584	- Core NVIC Functions
AnnaBridge	156:ff21514d8981	1585	- Core SysTick Functions
AnnaBridge	156:ff21514d8981	1586	- Core Debug Functions
AnnaBridge	156:ff21514d8981	1587	- Core Register Access Functions
AnnaBridge	156:ff21514d8981	1588	******************************************************************************/
AnnaBridge	156:ff21514d8981	1589	/**
AnnaBridge	156:ff21514d8981	1590	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge	156:ff21514d8981	1591	*/
AnnaBridge	156:ff21514d8981	1592
AnnaBridge	156:ff21514d8981	1593
AnnaBridge	156:ff21514d8981	1594
AnnaBridge	156:ff21514d8981	1595	/* ########################## NVIC functions #################################### */
AnnaBridge	156:ff21514d8981	1596	/**
AnnaBridge	156:ff21514d8981	1597	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	156:ff21514d8981	1598	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge	156:ff21514d8981	1599	\brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge	156:ff21514d8981	1600	@{
AnnaBridge	156:ff21514d8981	1601	*/
AnnaBridge	156:ff21514d8981	1602
AnnaBridge	156:ff21514d8981	1603	#ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge	156:ff21514d8981	1604	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	156:ff21514d8981	1605	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge	156:ff21514d8981	1606	#endif
AnnaBridge	156:ff21514d8981	1607	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	156:ff21514d8981	1608	#else
AnnaBridge	156:ff21514d8981	1609	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
AnnaBridge	156:ff21514d8981	1610	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
AnnaBridge	156:ff21514d8981	1611	#define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge	156:ff21514d8981	1612	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge	156:ff21514d8981	1613	#define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge	156:ff21514d8981	1614	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge	156:ff21514d8981	1615	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge	156:ff21514d8981	1616	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge	156:ff21514d8981	1617	#define NVIC_GetActive __NVIC_GetActive
AnnaBridge	156:ff21514d8981	1618	#define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge	156:ff21514d8981	1619	#define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge	156:ff21514d8981	1620	#define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge	156:ff21514d8981	1621	#endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge	156:ff21514d8981	1622
AnnaBridge	156:ff21514d8981	1623	#ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge	156:ff21514d8981	1624	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	156:ff21514d8981	1625	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge	156:ff21514d8981	1626	#endif
AnnaBridge	156:ff21514d8981	1627	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	156:ff21514d8981	1628	#else
AnnaBridge	156:ff21514d8981	1629	#define NVIC_SetVector __NVIC_SetVector
AnnaBridge	156:ff21514d8981	1630	#define NVIC_GetVector __NVIC_GetVector
AnnaBridge	156:ff21514d8981	1631	#endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge	156:ff21514d8981	1632
AnnaBridge	156:ff21514d8981	1633	#define NVIC_USER_IRQ_OFFSET 16
AnnaBridge	156:ff21514d8981	1634
AnnaBridge	156:ff21514d8981	1635
AnnaBridge	156:ff21514d8981	1636
AnnaBridge	156:ff21514d8981	1637	/**
AnnaBridge	156:ff21514d8981	1638	\brief Set Priority Grouping
AnnaBridge	156:ff21514d8981	1639	\details Sets the priority grouping field using the required unlock sequence.
AnnaBridge	156:ff21514d8981	1640	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge	156:ff21514d8981	1641	Only values from 0..7 are used.
AnnaBridge	156:ff21514d8981	1642	In case of a conflict between priority grouping and available
AnnaBridge	156:ff21514d8981	1643	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	156:ff21514d8981	1644	\param [in] PriorityGroup Priority grouping field.
AnnaBridge	156:ff21514d8981	1645	*/
AnnaBridge	156:ff21514d8981	1646	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
AnnaBridge	156:ff21514d8981	1647	{
AnnaBridge	156:ff21514d8981	1648	uint32_t reg_value;
AnnaBridge	156:ff21514d8981	1649	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	156:ff21514d8981	1650
AnnaBridge	156:ff21514d8981	1651	reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge	156:ff21514d8981	1652	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge	156:ff21514d8981	1653	reg_value = (reg_value \|
AnnaBridge	156:ff21514d8981	1654	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Anna Bridge	169:a7c7b631e539	1655	(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
AnnaBridge	156:ff21514d8981	1656	SCB->AIRCR = reg_value;
AnnaBridge	156:ff21514d8981	1657	}
AnnaBridge	156:ff21514d8981	1658
AnnaBridge	156:ff21514d8981	1659
AnnaBridge	156:ff21514d8981	1660	/**
AnnaBridge	156:ff21514d8981	1661	\brief Get Priority Grouping
AnnaBridge	156:ff21514d8981	1662	\details Reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge	156:ff21514d8981	1663	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge	156:ff21514d8981	1664	*/
AnnaBridge	156:ff21514d8981	1665	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
AnnaBridge	156:ff21514d8981	1666	{
AnnaBridge	156:ff21514d8981	1667	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge	156:ff21514d8981	1668	}
AnnaBridge	156:ff21514d8981	1669
AnnaBridge	156:ff21514d8981	1670
AnnaBridge	156:ff21514d8981	1671	/**
AnnaBridge	156:ff21514d8981	1672	\brief Enable Interrupt
AnnaBridge	156:ff21514d8981	1673	\details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	156:ff21514d8981	1674	\param [in] IRQn Device specific interrupt number.
AnnaBridge	156:ff21514d8981	1675	\note IRQn must not be negative.
AnnaBridge	156:ff21514d8981	1676	*/
AnnaBridge	156:ff21514d8981	1677	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge	156:ff21514d8981	1678	{
AnnaBridge	156:ff21514d8981	1679	if ((int32_t)(IRQn) >= 0)
AnnaBridge	156:ff21514d8981	1680	{
Anna Bridge	169:a7c7b631e539	1681	NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	156:ff21514d8981	1682	}
AnnaBridge	156:ff21514d8981	1683	}
AnnaBridge	156:ff21514d8981	1684
AnnaBridge	156:ff21514d8981	1685
AnnaBridge	156:ff21514d8981	1686	/**
AnnaBridge	156:ff21514d8981	1687	\brief Get Interrupt Enable status
AnnaBridge	156:ff21514d8981	1688	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge	156:ff21514d8981	1689	\param [in] IRQn Device specific interrupt number.
AnnaBridge	156:ff21514d8981	1690	\return 0 Interrupt is not enabled.
AnnaBridge	156:ff21514d8981	1691	\return 1 Interrupt is enabled.
AnnaBridge	156:ff21514d8981	1692	\note IRQn must not be negative.
AnnaBridge	156:ff21514d8981	1693	*/
AnnaBridge	156:ff21514d8981	1694	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge	156:ff21514d8981	1695	{
AnnaBridge	156:ff21514d8981	1696	if ((int32_t)(IRQn) >= 0)
AnnaBridge	156:ff21514d8981	1697	{
Anna Bridge	169:a7c7b631e539	1698	return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	156:ff21514d8981	1699	}
AnnaBridge	156:ff21514d8981	1700	else
AnnaBridge	156:ff21514d8981	1701	{
AnnaBridge	156:ff21514d8981	1702	return(0U);
AnnaBridge	156:ff21514d8981	1703	}
AnnaBridge	156:ff21514d8981	1704	}
AnnaBridge	156:ff21514d8981	1705
AnnaBridge	156:ff21514d8981	1706
AnnaBridge	156:ff21514d8981	1707	/**
AnnaBridge	156:ff21514d8981	1708	\brief Disable Interrupt
AnnaBridge	156:ff21514d8981	1709	\details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	156:ff21514d8981	1710	\param [in] IRQn Device specific interrupt number.
AnnaBridge	156:ff21514d8981	1711	\note IRQn must not be negative.
AnnaBridge	156:ff21514d8981	1712	*/
AnnaBridge	156:ff21514d8981	1713	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge	156:ff21514d8981	1714	{
AnnaBridge	156:ff21514d8981	1715	if ((int32_t)(IRQn) >= 0)
AnnaBridge	156:ff21514d8981	1716	{
Anna Bridge	169:a7c7b631e539	1717	NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	156:ff21514d8981	1718	__DSB();
AnnaBridge	156:ff21514d8981	1719	__ISB();
AnnaBridge	156:ff21514d8981	1720	}
AnnaBridge	156:ff21514d8981	1721	}
AnnaBridge	156:ff21514d8981	1722
AnnaBridge	156:ff21514d8981	1723
AnnaBridge	156:ff21514d8981	1724	/**
AnnaBridge	156:ff21514d8981	1725	\brief Get Pending Interrupt
AnnaBridge	156:ff21514d8981	1726	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge	156:ff21514d8981	1727	\param [in] IRQn Device specific interrupt number.
AnnaBridge	156:ff21514d8981	1728	\return 0 Interrupt status is not pending.
AnnaBridge	156:ff21514d8981	1729	\return 1 Interrupt status is pending.
AnnaBridge	156:ff21514d8981	1730	\note IRQn must not be negative.
AnnaBridge	156:ff21514d8981	1731	*/
AnnaBridge	156:ff21514d8981	1732	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	156:ff21514d8981	1733	{
AnnaBridge	156:ff21514d8981	1734	if ((int32_t)(IRQn) >= 0)
AnnaBridge	156:ff21514d8981	1735	{
Anna Bridge	169:a7c7b631e539	1736	return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	156:ff21514d8981	1737	}
AnnaBridge	156:ff21514d8981	1738	else
AnnaBridge	156:ff21514d8981	1739	{
AnnaBridge	156:ff21514d8981	1740	return(0U);
AnnaBridge	156:ff21514d8981	1741	}
AnnaBridge	156:ff21514d8981	1742	}
AnnaBridge	156:ff21514d8981	1743
AnnaBridge	156:ff21514d8981	1744
AnnaBridge	156:ff21514d8981	1745	/**
AnnaBridge	156:ff21514d8981	1746	\brief Set Pending Interrupt
AnnaBridge	156:ff21514d8981	1747	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	156:ff21514d8981	1748	\param [in] IRQn Device specific interrupt number.
AnnaBridge	156:ff21514d8981	1749	\note IRQn must not be negative.
AnnaBridge	156:ff21514d8981	1750	*/
AnnaBridge	156:ff21514d8981	1751	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	156:ff21514d8981	1752	{
AnnaBridge	156:ff21514d8981	1753	if ((int32_t)(IRQn) >= 0)
AnnaBridge	156:ff21514d8981	1754	{
Anna Bridge	169:a7c7b631e539	1755	NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	156:ff21514d8981	1756	}
AnnaBridge	156:ff21514d8981	1757	}
AnnaBridge	156:ff21514d8981	1758
AnnaBridge	156:ff21514d8981	1759
AnnaBridge	156:ff21514d8981	1760	/**
AnnaBridge	156:ff21514d8981	1761	\brief Clear Pending Interrupt
AnnaBridge	156:ff21514d8981	1762	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	156:ff21514d8981	1763	\param [in] IRQn Device specific interrupt number.
AnnaBridge	156:ff21514d8981	1764	\note IRQn must not be negative.
AnnaBridge	156:ff21514d8981	1765	*/
AnnaBridge	156:ff21514d8981	1766	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge	156:ff21514d8981	1767	{
AnnaBridge	156:ff21514d8981	1768	if ((int32_t)(IRQn) >= 0)
AnnaBridge	156:ff21514d8981	1769	{
Anna Bridge	169:a7c7b631e539	1770	NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	156:ff21514d8981	1771	}
AnnaBridge	156:ff21514d8981	1772	}
AnnaBridge	156:ff21514d8981	1773
AnnaBridge	156:ff21514d8981	1774
AnnaBridge	156:ff21514d8981	1775	/**
AnnaBridge	156:ff21514d8981	1776	\brief Get Active Interrupt
AnnaBridge	156:ff21514d8981	1777	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge	156:ff21514d8981	1778	\param [in] IRQn Device specific interrupt number.
AnnaBridge	156:ff21514d8981	1779	\return 0 Interrupt status is not active.
AnnaBridge	156:ff21514d8981	1780	\return 1 Interrupt status is active.
AnnaBridge	156:ff21514d8981	1781	\note IRQn must not be negative.
AnnaBridge	156:ff21514d8981	1782	*/
AnnaBridge	156:ff21514d8981	1783	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge	156:ff21514d8981	1784	{
AnnaBridge	156:ff21514d8981	1785	if ((int32_t)(IRQn) >= 0)
AnnaBridge	156:ff21514d8981	1786	{
Anna Bridge	169:a7c7b631e539	1787	return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	156:ff21514d8981	1788	}
AnnaBridge	156:ff21514d8981	1789	else
AnnaBridge	156:ff21514d8981	1790	{
AnnaBridge	156:ff21514d8981	1791	return(0U);
AnnaBridge	156:ff21514d8981	1792	}
AnnaBridge	156:ff21514d8981	1793	}
AnnaBridge	156:ff21514d8981	1794
AnnaBridge	156:ff21514d8981	1795
AnnaBridge	156:ff21514d8981	1796	/**
AnnaBridge	156:ff21514d8981	1797	\brief Set Interrupt Priority
AnnaBridge	156:ff21514d8981	1798	\details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge	156:ff21514d8981	1799	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	156:ff21514d8981	1800	or negative to specify a processor exception.
AnnaBridge	156:ff21514d8981	1801	\param [in] IRQn Interrupt number.
AnnaBridge	156:ff21514d8981	1802	\param [in] priority Priority to set.
AnnaBridge	156:ff21514d8981	1803	\note The priority cannot be set for every processor exception.
AnnaBridge	156:ff21514d8981	1804	*/
AnnaBridge	156:ff21514d8981	1805	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	156:ff21514d8981	1806	{
AnnaBridge	156:ff21514d8981	1807	if ((int32_t)(IRQn) >= 0)
AnnaBridge	156:ff21514d8981	1808	{
Anna Bridge	169:a7c7b631e539	1809	NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	156:ff21514d8981	1810	}
AnnaBridge	156:ff21514d8981	1811	else
AnnaBridge	156:ff21514d8981	1812	{
Anna Bridge	169:a7c7b631e539	1813	SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	156:ff21514d8981	1814	}
AnnaBridge	156:ff21514d8981	1815	}
AnnaBridge	156:ff21514d8981	1816
AnnaBridge	156:ff21514d8981	1817
AnnaBridge	156:ff21514d8981	1818	/**
AnnaBridge	156:ff21514d8981	1819	\brief Get Interrupt Priority
AnnaBridge	156:ff21514d8981	1820	\details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge	156:ff21514d8981	1821	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	156:ff21514d8981	1822	or negative to specify a processor exception.
AnnaBridge	156:ff21514d8981	1823	\param [in] IRQn Interrupt number.
AnnaBridge	156:ff21514d8981	1824	\return Interrupt Priority.
AnnaBridge	156:ff21514d8981	1825	Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	156:ff21514d8981	1826	*/
AnnaBridge	156:ff21514d8981	1827	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge	156:ff21514d8981	1828	{
AnnaBridge	156:ff21514d8981	1829
AnnaBridge	156:ff21514d8981	1830	if ((int32_t)(IRQn) >= 0)
AnnaBridge	156:ff21514d8981	1831	{
Anna Bridge	169:a7c7b631e539	1832	return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	156:ff21514d8981	1833	}
AnnaBridge	156:ff21514d8981	1834	else
AnnaBridge	156:ff21514d8981	1835	{
Anna Bridge	169:a7c7b631e539	1836	return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	156:ff21514d8981	1837	}
AnnaBridge	156:ff21514d8981	1838	}
AnnaBridge	156:ff21514d8981	1839
AnnaBridge	156:ff21514d8981	1840
AnnaBridge	156:ff21514d8981	1841	/**
AnnaBridge	156:ff21514d8981	1842	\brief Encode Priority
AnnaBridge	156:ff21514d8981	1843	\details Encodes the priority for an interrupt with the given priority group,
AnnaBridge	156:ff21514d8981	1844	preemptive priority value, and subpriority value.
AnnaBridge	156:ff21514d8981	1845	In case of a conflict between priority grouping and available
AnnaBridge	156:ff21514d8981	1846	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	156:ff21514d8981	1847	\param [in] PriorityGroup Used priority group.
AnnaBridge	156:ff21514d8981	1848	\param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	156:ff21514d8981	1849	\param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge	156:ff21514d8981	1850	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge	156:ff21514d8981	1851	*/
AnnaBridge	156:ff21514d8981	1852	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge	156:ff21514d8981	1853	{
AnnaBridge	156:ff21514d8981	1854	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	156:ff21514d8981	1855	uint32_t PreemptPriorityBits;
AnnaBridge	156:ff21514d8981	1856	uint32_t SubPriorityBits;
AnnaBridge	156:ff21514d8981	1857
AnnaBridge	156:ff21514d8981	1858	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	156:ff21514d8981	1859	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	156:ff21514d8981	1860
AnnaBridge	156:ff21514d8981	1861	return (
AnnaBridge	156:ff21514d8981	1862	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
AnnaBridge	156:ff21514d8981	1863	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge	156:ff21514d8981	1864	);
AnnaBridge	156:ff21514d8981	1865	}
AnnaBridge	156:ff21514d8981	1866
AnnaBridge	156:ff21514d8981	1867
AnnaBridge	156:ff21514d8981	1868	/**
AnnaBridge	156:ff21514d8981	1869	\brief Decode Priority
AnnaBridge	156:ff21514d8981	1870	\details Decodes an interrupt priority value with a given priority group to
AnnaBridge	156:ff21514d8981	1871	preemptive priority value and subpriority value.
AnnaBridge	156:ff21514d8981	1872	In case of a conflict between priority grouping and available
AnnaBridge	156:ff21514d8981	1873	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge	156:ff21514d8981	1874	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge	156:ff21514d8981	1875	\param [in] PriorityGroup Used priority group.
AnnaBridge	156:ff21514d8981	1876	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	156:ff21514d8981	1877	\param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge	156:ff21514d8981	1878	*/
AnnaBridge	156:ff21514d8981	1879	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
AnnaBridge	156:ff21514d8981	1880	{
AnnaBridge	156:ff21514d8981	1881	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	156:ff21514d8981	1882	uint32_t PreemptPriorityBits;
AnnaBridge	156:ff21514d8981	1883	uint32_t SubPriorityBits;
AnnaBridge	156:ff21514d8981	1884
AnnaBridge	156:ff21514d8981	1885	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	156:ff21514d8981	1886	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	156:ff21514d8981	1887
AnnaBridge	156:ff21514d8981	1888	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge	156:ff21514d8981	1889	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge	156:ff21514d8981	1890	}
AnnaBridge	156:ff21514d8981	1891
AnnaBridge	156:ff21514d8981	1892
AnnaBridge	156:ff21514d8981	1893	/**
AnnaBridge	156:ff21514d8981	1894	\brief Set Interrupt Vector
AnnaBridge	156:ff21514d8981	1895	\details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge	156:ff21514d8981	1896	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	156:ff21514d8981	1897	or negative to specify a processor exception.
AnnaBridge	156:ff21514d8981	1898	VTOR must been relocated to SRAM before.
AnnaBridge	156:ff21514d8981	1899	\param [in] IRQn Interrupt number
AnnaBridge	156:ff21514d8981	1900	\param [in] vector Address of interrupt handler function
AnnaBridge	156:ff21514d8981	1901	*/
AnnaBridge	156:ff21514d8981	1902	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge	156:ff21514d8981	1903	{
AnnaBridge	156:ff21514d8981	1904	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	156:ff21514d8981	1905	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge	156:ff21514d8981	1906	}
AnnaBridge	156:ff21514d8981	1907
AnnaBridge	156:ff21514d8981	1908
AnnaBridge	156:ff21514d8981	1909	/**
AnnaBridge	156:ff21514d8981	1910	\brief Get Interrupt Vector
AnnaBridge	156:ff21514d8981	1911	\details Reads an interrupt vector from interrupt vector table.
AnnaBridge	156:ff21514d8981	1912	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	156:ff21514d8981	1913	or negative to specify a processor exception.
AnnaBridge	156:ff21514d8981	1914	\param [in] IRQn Interrupt number.
AnnaBridge	156:ff21514d8981	1915	\return Address of interrupt handler function
AnnaBridge	156:ff21514d8981	1916	*/
AnnaBridge	156:ff21514d8981	1917	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge	156:ff21514d8981	1918	{
AnnaBridge	156:ff21514d8981	1919	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	156:ff21514d8981	1920	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge	156:ff21514d8981	1921	}
AnnaBridge	156:ff21514d8981	1922
AnnaBridge	156:ff21514d8981	1923
AnnaBridge	156:ff21514d8981	1924	/**
AnnaBridge	156:ff21514d8981	1925	\brief System Reset
AnnaBridge	156:ff21514d8981	1926	\details Initiates a system reset request to reset the MCU.
AnnaBridge	156:ff21514d8981	1927	*/
AnnaBridge	156:ff21514d8981	1928	__STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge	156:ff21514d8981	1929	{
AnnaBridge	156:ff21514d8981	1930	__DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge	156:ff21514d8981	1931	buffered write are completed before reset */
AnnaBridge	156:ff21514d8981	1932	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	156:ff21514d8981	1933	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
AnnaBridge	156:ff21514d8981	1934	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
AnnaBridge	156:ff21514d8981	1935	__DSB(); /* Ensure completion of memory access */
AnnaBridge	156:ff21514d8981	1936
AnnaBridge	156:ff21514d8981	1937	for(;;) /* wait until reset */
AnnaBridge	156:ff21514d8981	1938	{
AnnaBridge	156:ff21514d8981	1939	__NOP();
AnnaBridge	156:ff21514d8981	1940	}
AnnaBridge	156:ff21514d8981	1941	}
AnnaBridge	156:ff21514d8981	1942
AnnaBridge	156:ff21514d8981	1943	/@} end of CMSIS_Core_NVICFunctions /
AnnaBridge	156:ff21514d8981	1944
Anna Bridge	160:5571c4ff569f	1945	/* ########################## MPU functions #################################### */
Anna Bridge	160:5571c4ff569f	1946
Anna Bridge	160:5571c4ff569f	1947	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	1948
Anna Bridge	160:5571c4ff569f	1949	#include "mpu_armv7.h"
Anna Bridge	160:5571c4ff569f	1950
Anna Bridge	160:5571c4ff569f	1951	#endif
Anna Bridge	160:5571c4ff569f	1952
AnnaBridge	156:ff21514d8981	1953
AnnaBridge	156:ff21514d8981	1954	/* ########################## FPU functions #################################### */
AnnaBridge	156:ff21514d8981	1955	/**
AnnaBridge	156:ff21514d8981	1956	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	156:ff21514d8981	1957	\defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge	156:ff21514d8981	1958	\brief Function that provides FPU type.
AnnaBridge	156:ff21514d8981	1959	@{
AnnaBridge	156:ff21514d8981	1960	*/
AnnaBridge	156:ff21514d8981	1961
AnnaBridge	156:ff21514d8981	1962	/**
AnnaBridge	156:ff21514d8981	1963	\brief get FPU type
AnnaBridge	156:ff21514d8981	1964	\details returns the FPU type
AnnaBridge	156:ff21514d8981	1965	\returns
AnnaBridge	156:ff21514d8981	1966	- \b 0: No FPU
AnnaBridge	156:ff21514d8981	1967	- \b 1: Single precision FPU
AnnaBridge	156:ff21514d8981	1968	- \b 2: Double + Single precision FPU
AnnaBridge	156:ff21514d8981	1969	*/
AnnaBridge	156:ff21514d8981	1970	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge	156:ff21514d8981	1971	{
AnnaBridge	156:ff21514d8981	1972	uint32_t mvfr0;
AnnaBridge	156:ff21514d8981	1973
AnnaBridge	156:ff21514d8981	1974	mvfr0 = FPU->MVFR0;
AnnaBridge	156:ff21514d8981	1975	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
AnnaBridge	156:ff21514d8981	1976	{
AnnaBridge	156:ff21514d8981	1977	return 1U; /* Single precision FPU */
AnnaBridge	156:ff21514d8981	1978	}
AnnaBridge	156:ff21514d8981	1979	else
AnnaBridge	156:ff21514d8981	1980	{
AnnaBridge	156:ff21514d8981	1981	return 0U; /* No FPU */
AnnaBridge	156:ff21514d8981	1982	}
AnnaBridge	156:ff21514d8981	1983	}
AnnaBridge	156:ff21514d8981	1984
AnnaBridge	156:ff21514d8981	1985
AnnaBridge	156:ff21514d8981	1986	/@} end of CMSIS_Core_FpuFunctions /
AnnaBridge	156:ff21514d8981	1987
AnnaBridge	156:ff21514d8981	1988
AnnaBridge	156:ff21514d8981	1989
AnnaBridge	156:ff21514d8981	1990	/* ################################## SysTick function ############################################ */
AnnaBridge	156:ff21514d8981	1991	/**
AnnaBridge	156:ff21514d8981	1992	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	156:ff21514d8981	1993	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge	156:ff21514d8981	1994	\brief Functions that configure the System.
AnnaBridge	156:ff21514d8981	1995	@{
AnnaBridge	156:ff21514d8981	1996	*/
AnnaBridge	156:ff21514d8981	1997
AnnaBridge	156:ff21514d8981	1998	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge	156:ff21514d8981	1999
AnnaBridge	156:ff21514d8981	2000	/**
AnnaBridge	156:ff21514d8981	2001	\brief System Tick Configuration
AnnaBridge	156:ff21514d8981	2002	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge	156:ff21514d8981	2003	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	156:ff21514d8981	2004	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	156:ff21514d8981	2005	\return 0 Function succeeded.
AnnaBridge	156:ff21514d8981	2006	\return 1 Function failed.
AnnaBridge	156:ff21514d8981	2007	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	156:ff21514d8981	2008	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	156:ff21514d8981	2009	must contain a vendor-specific implementation of this function.
AnnaBridge	156:ff21514d8981	2010	*/
AnnaBridge	156:ff21514d8981	2011	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge	156:ff21514d8981	2012	{
AnnaBridge	156:ff21514d8981	2013	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	156:ff21514d8981	2014	{
AnnaBridge	156:ff21514d8981	2015	return (1UL); /* Reload value impossible */
AnnaBridge	156:ff21514d8981	2016	}
AnnaBridge	156:ff21514d8981	2017
AnnaBridge	156:ff21514d8981	2018	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge	156:ff21514d8981	2019	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge	156:ff21514d8981	2020	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge	156:ff21514d8981	2021	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
AnnaBridge	156:ff21514d8981	2022	SysTick_CTRL_TICKINT_Msk \|
AnnaBridge	156:ff21514d8981	2023	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge	156:ff21514d8981	2024	return (0UL); /* Function successful */
AnnaBridge	156:ff21514d8981	2025	}
AnnaBridge	156:ff21514d8981	2026
AnnaBridge	156:ff21514d8981	2027	#endif
AnnaBridge	156:ff21514d8981	2028
AnnaBridge	156:ff21514d8981	2029	/@} end of CMSIS_Core_SysTickFunctions /
AnnaBridge	156:ff21514d8981	2030
AnnaBridge	156:ff21514d8981	2031
AnnaBridge	156:ff21514d8981	2032
AnnaBridge	156:ff21514d8981	2033	/* ##################################### Debug In/Output function ########################################### */
AnnaBridge	156:ff21514d8981	2034	/**
AnnaBridge	156:ff21514d8981	2035	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	156:ff21514d8981	2036	\defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge	156:ff21514d8981	2037	\brief Functions that access the ITM debug interface.
AnnaBridge	156:ff21514d8981	2038	@{
AnnaBridge	156:ff21514d8981	2039	*/
AnnaBridge	156:ff21514d8981	2040
AnnaBridge	156:ff21514d8981	2041	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
AnnaBridge	156:ff21514d8981	2042	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
AnnaBridge	156:ff21514d8981	2043
AnnaBridge	156:ff21514d8981	2044
AnnaBridge	156:ff21514d8981	2045	/**
AnnaBridge	156:ff21514d8981	2046	\brief ITM Send Character
AnnaBridge	156:ff21514d8981	2047	\details Transmits a character via the ITM channel 0, and
AnnaBridge	156:ff21514d8981	2048	\li Just returns when no debugger is connected that has booked the output.
AnnaBridge	156:ff21514d8981	2049	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge	156:ff21514d8981	2050	\param [in] ch Character to transmit.
AnnaBridge	156:ff21514d8981	2051	\returns Character to transmit.
AnnaBridge	156:ff21514d8981	2052	*/
AnnaBridge	156:ff21514d8981	2053	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
AnnaBridge	156:ff21514d8981	2054	{
AnnaBridge	156:ff21514d8981	2055	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
AnnaBridge	156:ff21514d8981	2056	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
AnnaBridge	156:ff21514d8981	2057	{
AnnaBridge	156:ff21514d8981	2058	while (ITM->PORT[0U].u32 == 0UL)
AnnaBridge	156:ff21514d8981	2059	{
AnnaBridge	156:ff21514d8981	2060	__NOP();
AnnaBridge	156:ff21514d8981	2061	}
AnnaBridge	156:ff21514d8981	2062	ITM->PORT[0U].u8 = (uint8_t)ch;
AnnaBridge	156:ff21514d8981	2063	}
AnnaBridge	156:ff21514d8981	2064	return (ch);
AnnaBridge	156:ff21514d8981	2065	}
AnnaBridge	156:ff21514d8981	2066
AnnaBridge	156:ff21514d8981	2067
AnnaBridge	156:ff21514d8981	2068	/**
AnnaBridge	156:ff21514d8981	2069	\brief ITM Receive Character
AnnaBridge	156:ff21514d8981	2070	\details Inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge	156:ff21514d8981	2071	\return Received character.
AnnaBridge	156:ff21514d8981	2072	\return -1 No character pending.
AnnaBridge	156:ff21514d8981	2073	*/
AnnaBridge	156:ff21514d8981	2074	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
AnnaBridge	156:ff21514d8981	2075	{
AnnaBridge	156:ff21514d8981	2076	int32_t ch = -1; /* no character available */
AnnaBridge	156:ff21514d8981	2077
AnnaBridge	156:ff21514d8981	2078	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
AnnaBridge	156:ff21514d8981	2079	{
AnnaBridge	156:ff21514d8981	2080	ch = ITM_RxBuffer;
AnnaBridge	156:ff21514d8981	2081	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
AnnaBridge	156:ff21514d8981	2082	}
AnnaBridge	156:ff21514d8981	2083
AnnaBridge	156:ff21514d8981	2084	return (ch);
AnnaBridge	156:ff21514d8981	2085	}
AnnaBridge	156:ff21514d8981	2086
AnnaBridge	156:ff21514d8981	2087
AnnaBridge	156:ff21514d8981	2088	/**
AnnaBridge	156:ff21514d8981	2089	\brief ITM Check Character
AnnaBridge	156:ff21514d8981	2090	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge	156:ff21514d8981	2091	\return 0 No character available.
AnnaBridge	156:ff21514d8981	2092	\return 1 Character available.
AnnaBridge	156:ff21514d8981	2093	*/
AnnaBridge	156:ff21514d8981	2094	__STATIC_INLINE int32_t ITM_CheckChar (void)
AnnaBridge	156:ff21514d8981	2095	{
AnnaBridge	156:ff21514d8981	2096
AnnaBridge	156:ff21514d8981	2097	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
AnnaBridge	156:ff21514d8981	2098	{
AnnaBridge	156:ff21514d8981	2099	return (0); /* no character available */
AnnaBridge	156:ff21514d8981	2100	}
AnnaBridge	156:ff21514d8981	2101	else
AnnaBridge	156:ff21514d8981	2102	{
AnnaBridge	156:ff21514d8981	2103	return (1); /* character available */
AnnaBridge	156:ff21514d8981	2104	}
AnnaBridge	156:ff21514d8981	2105	}
AnnaBridge	156:ff21514d8981	2106
AnnaBridge	156:ff21514d8981	2107	/@} end of CMSIS_core_DebugFunctions /
AnnaBridge	156:ff21514d8981	2108
AnnaBridge	156:ff21514d8981	2109
AnnaBridge	156:ff21514d8981	2110
AnnaBridge	156:ff21514d8981	2111
AnnaBridge	156:ff21514d8981	2112	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	2113	}
AnnaBridge	156:ff21514d8981	2114	#endif
AnnaBridge	156:ff21514d8981	2115
AnnaBridge	156:ff21514d8981	2116	#endif /* __CORE_CM4_H_DEPENDANT */
AnnaBridge	156:ff21514d8981	2117
AnnaBridge	156:ff21514d8981	2118	#endif /* __CMSIS_GENERIC */