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TARGET_WIO_BG96/TOOLCHAIN_IAR/stm32f4xx_ll_dma.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- TARGET_ELMO_F411RE/TOOLCHAIN_ARM_STD/stm32f4xx_ll_dma.h@171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
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AnnaBridge | 145:64910690c574 | 1 | /** |
AnnaBridge | 145:64910690c574 | 2 | ****************************************************************************** |
AnnaBridge | 145:64910690c574 | 3 | * @file stm32f4xx_ll_dma.h |
AnnaBridge | 145:64910690c574 | 4 | * @author MCD Application Team |
AnnaBridge | 145:64910690c574 | 5 | * @brief Header file of DMA LL module. |
AnnaBridge | 145:64910690c574 | 6 | ****************************************************************************** |
AnnaBridge | 145:64910690c574 | 7 | * @attention |
AnnaBridge | 145:64910690c574 | 8 | * |
AnnaBridge | 145:64910690c574 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
AnnaBridge | 145:64910690c574 | 10 | * |
AnnaBridge | 145:64910690c574 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 145:64910690c574 | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 145:64910690c574 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 145:64910690c574 | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 145:64910690c574 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 145:64910690c574 | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 145:64910690c574 | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 145:64910690c574 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 145:64910690c574 | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 145:64910690c574 | 20 | * without specific prior written permission. |
AnnaBridge | 145:64910690c574 | 21 | * |
AnnaBridge | 145:64910690c574 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 145:64910690c574 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 145:64910690c574 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 145:64910690c574 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 145:64910690c574 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 145:64910690c574 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 145:64910690c574 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 145:64910690c574 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 145:64910690c574 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 145:64910690c574 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 145:64910690c574 | 32 | * |
AnnaBridge | 145:64910690c574 | 33 | ****************************************************************************** |
AnnaBridge | 145:64910690c574 | 34 | */ |
AnnaBridge | 145:64910690c574 | 35 | |
AnnaBridge | 145:64910690c574 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 37 | #ifndef __STM32F4xx_LL_DMA_H |
AnnaBridge | 145:64910690c574 | 38 | #define __STM32F4xx_LL_DMA_H |
AnnaBridge | 145:64910690c574 | 39 | |
AnnaBridge | 145:64910690c574 | 40 | #ifdef __cplusplus |
AnnaBridge | 145:64910690c574 | 41 | extern "C" { |
AnnaBridge | 145:64910690c574 | 42 | #endif |
AnnaBridge | 145:64910690c574 | 43 | |
AnnaBridge | 145:64910690c574 | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 45 | #include "stm32f4xx.h" |
AnnaBridge | 145:64910690c574 | 46 | |
AnnaBridge | 145:64910690c574 | 47 | /** @addtogroup STM32F4xx_LL_Driver |
AnnaBridge | 145:64910690c574 | 48 | * @{ |
AnnaBridge | 145:64910690c574 | 49 | */ |
AnnaBridge | 145:64910690c574 | 50 | |
AnnaBridge | 145:64910690c574 | 51 | #if defined (DMA1) || defined (DMA2) |
AnnaBridge | 145:64910690c574 | 52 | |
AnnaBridge | 145:64910690c574 | 53 | /** @defgroup DMA_LL DMA |
AnnaBridge | 145:64910690c574 | 54 | * @{ |
AnnaBridge | 145:64910690c574 | 55 | */ |
AnnaBridge | 145:64910690c574 | 56 | |
AnnaBridge | 145:64910690c574 | 57 | /* Private types -------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 58 | /* Private variables ---------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 59 | /** @defgroup DMA_LL_Private_Variables DMA Private Variables |
AnnaBridge | 145:64910690c574 | 60 | * @{ |
AnnaBridge | 145:64910690c574 | 61 | */ |
AnnaBridge | 145:64910690c574 | 62 | /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ |
AnnaBridge | 145:64910690c574 | 63 | static const uint8_t STREAM_OFFSET_TAB[] = |
AnnaBridge | 145:64910690c574 | 64 | { |
AnnaBridge | 145:64910690c574 | 65 | (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), |
AnnaBridge | 145:64910690c574 | 66 | (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), |
AnnaBridge | 145:64910690c574 | 67 | (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), |
AnnaBridge | 145:64910690c574 | 68 | (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), |
AnnaBridge | 145:64910690c574 | 69 | (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), |
AnnaBridge | 145:64910690c574 | 70 | (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), |
AnnaBridge | 145:64910690c574 | 71 | (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), |
AnnaBridge | 145:64910690c574 | 72 | (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) |
AnnaBridge | 145:64910690c574 | 73 | }; |
AnnaBridge | 145:64910690c574 | 74 | |
AnnaBridge | 145:64910690c574 | 75 | /** |
AnnaBridge | 145:64910690c574 | 76 | * @} |
AnnaBridge | 145:64910690c574 | 77 | */ |
AnnaBridge | 145:64910690c574 | 78 | |
AnnaBridge | 145:64910690c574 | 79 | /* Private constants ---------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 80 | /** @defgroup DMA_LL_Private_Constants DMA Private Constants |
AnnaBridge | 145:64910690c574 | 81 | * @{ |
AnnaBridge | 145:64910690c574 | 82 | */ |
AnnaBridge | 145:64910690c574 | 83 | /** |
AnnaBridge | 145:64910690c574 | 84 | * @} |
AnnaBridge | 145:64910690c574 | 85 | */ |
AnnaBridge | 145:64910690c574 | 86 | |
AnnaBridge | 145:64910690c574 | 87 | |
AnnaBridge | 145:64910690c574 | 88 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 89 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 90 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 145:64910690c574 | 91 | /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure |
AnnaBridge | 145:64910690c574 | 92 | * @{ |
AnnaBridge | 145:64910690c574 | 93 | */ |
AnnaBridge | 145:64910690c574 | 94 | typedef struct |
AnnaBridge | 145:64910690c574 | 95 | { |
AnnaBridge | 145:64910690c574 | 96 | uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer |
AnnaBridge | 145:64910690c574 | 97 | or as Source base address in case of memory to memory transfer direction. |
AnnaBridge | 145:64910690c574 | 98 | |
AnnaBridge | 145:64910690c574 | 99 | This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ |
AnnaBridge | 145:64910690c574 | 100 | |
AnnaBridge | 145:64910690c574 | 101 | uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer |
AnnaBridge | 145:64910690c574 | 102 | or as Destination base address in case of memory to memory transfer direction. |
AnnaBridge | 145:64910690c574 | 103 | |
AnnaBridge | 145:64910690c574 | 104 | This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ |
AnnaBridge | 145:64910690c574 | 105 | |
AnnaBridge | 145:64910690c574 | 106 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
AnnaBridge | 145:64910690c574 | 107 | from memory to memory or from peripheral to memory. |
AnnaBridge | 145:64910690c574 | 108 | This parameter can be a value of @ref DMA_LL_EC_DIRECTION |
AnnaBridge | 145:64910690c574 | 109 | |
AnnaBridge | 145:64910690c574 | 110 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ |
AnnaBridge | 145:64910690c574 | 111 | |
AnnaBridge | 145:64910690c574 | 112 | uint32_t Mode; /*!< Specifies the normal or circular operation mode. |
AnnaBridge | 145:64910690c574 | 113 | This parameter can be a value of @ref DMA_LL_EC_MODE |
AnnaBridge | 145:64910690c574 | 114 | @note The circular buffer mode cannot be used if the memory to memory |
AnnaBridge | 145:64910690c574 | 115 | data transfer direction is configured on the selected Stream |
AnnaBridge | 145:64910690c574 | 116 | |
AnnaBridge | 145:64910690c574 | 117 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ |
AnnaBridge | 145:64910690c574 | 118 | |
AnnaBridge | 145:64910690c574 | 119 | uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction |
AnnaBridge | 145:64910690c574 | 120 | is incremented or not. |
AnnaBridge | 145:64910690c574 | 121 | This parameter can be a value of @ref DMA_LL_EC_PERIPH |
AnnaBridge | 145:64910690c574 | 122 | |
AnnaBridge | 145:64910690c574 | 123 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ |
AnnaBridge | 145:64910690c574 | 124 | |
AnnaBridge | 145:64910690c574 | 125 | uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction |
AnnaBridge | 145:64910690c574 | 126 | is incremented or not. |
AnnaBridge | 145:64910690c574 | 127 | This parameter can be a value of @ref DMA_LL_EC_MEMORY |
AnnaBridge | 145:64910690c574 | 128 | |
AnnaBridge | 145:64910690c574 | 129 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ |
AnnaBridge | 145:64910690c574 | 130 | |
AnnaBridge | 145:64910690c574 | 131 | uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) |
AnnaBridge | 145:64910690c574 | 132 | in case of memory to memory transfer direction. |
AnnaBridge | 145:64910690c574 | 133 | This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN |
AnnaBridge | 145:64910690c574 | 134 | |
AnnaBridge | 145:64910690c574 | 135 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ |
AnnaBridge | 145:64910690c574 | 136 | |
AnnaBridge | 145:64910690c574 | 137 | uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) |
AnnaBridge | 145:64910690c574 | 138 | in case of memory to memory transfer direction. |
AnnaBridge | 145:64910690c574 | 139 | This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN |
AnnaBridge | 145:64910690c574 | 140 | |
AnnaBridge | 145:64910690c574 | 141 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ |
AnnaBridge | 145:64910690c574 | 142 | |
AnnaBridge | 145:64910690c574 | 143 | uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. |
AnnaBridge | 145:64910690c574 | 144 | The data unit is equal to the source buffer configuration set in PeripheralSize |
AnnaBridge | 145:64910690c574 | 145 | or MemorySize parameters depending in the transfer direction. |
AnnaBridge | 145:64910690c574 | 146 | This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF |
AnnaBridge | 145:64910690c574 | 147 | |
AnnaBridge | 145:64910690c574 | 148 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ |
AnnaBridge | 145:64910690c574 | 149 | |
AnnaBridge | 145:64910690c574 | 150 | uint32_t Channel; /*!< Specifies the peripheral channel. |
AnnaBridge | 145:64910690c574 | 151 | This parameter can be a value of @ref DMA_LL_EC_CHANNEL |
AnnaBridge | 145:64910690c574 | 152 | |
AnnaBridge | 145:64910690c574 | 153 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */ |
AnnaBridge | 145:64910690c574 | 154 | |
AnnaBridge | 145:64910690c574 | 155 | uint32_t Priority; /*!< Specifies the channel priority level. |
AnnaBridge | 145:64910690c574 | 156 | This parameter can be a value of @ref DMA_LL_EC_PRIORITY |
AnnaBridge | 145:64910690c574 | 157 | |
AnnaBridge | 145:64910690c574 | 158 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */ |
AnnaBridge | 145:64910690c574 | 159 | |
AnnaBridge | 145:64910690c574 | 160 | uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. |
AnnaBridge | 145:64910690c574 | 161 | This parameter can be a value of @ref DMA_LL_FIFOMODE |
AnnaBridge | 145:64910690c574 | 162 | @note The Direct mode (FIFO mode disabled) cannot be used if the |
AnnaBridge | 145:64910690c574 | 163 | memory-to-memory data transfer is configured on the selected stream |
AnnaBridge | 145:64910690c574 | 164 | |
AnnaBridge | 145:64910690c574 | 165 | This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */ |
AnnaBridge | 145:64910690c574 | 166 | |
AnnaBridge | 145:64910690c574 | 167 | uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. |
AnnaBridge | 145:64910690c574 | 168 | This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD |
AnnaBridge | 145:64910690c574 | 169 | |
AnnaBridge | 145:64910690c574 | 170 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */ |
AnnaBridge | 145:64910690c574 | 171 | |
AnnaBridge | 145:64910690c574 | 172 | uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. |
AnnaBridge | 145:64910690c574 | 173 | It specifies the amount of data to be transferred in a single non interruptible |
AnnaBridge | 145:64910690c574 | 174 | transaction. |
AnnaBridge | 145:64910690c574 | 175 | This parameter can be a value of @ref DMA_LL_EC_MBURST |
AnnaBridge | 145:64910690c574 | 176 | @note The burst mode is possible only if the address Increment mode is enabled. |
AnnaBridge | 145:64910690c574 | 177 | |
AnnaBridge | 145:64910690c574 | 178 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */ |
AnnaBridge | 145:64910690c574 | 179 | |
AnnaBridge | 145:64910690c574 | 180 | uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. |
AnnaBridge | 145:64910690c574 | 181 | It specifies the amount of data to be transferred in a single non interruptible |
AnnaBridge | 145:64910690c574 | 182 | transaction. |
AnnaBridge | 145:64910690c574 | 183 | This parameter can be a value of @ref DMA_LL_EC_PBURST |
AnnaBridge | 145:64910690c574 | 184 | @note The burst mode is possible only if the address Increment mode is enabled. |
AnnaBridge | 145:64910690c574 | 185 | |
AnnaBridge | 145:64910690c574 | 186 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */ |
AnnaBridge | 145:64910690c574 | 187 | |
AnnaBridge | 145:64910690c574 | 188 | } LL_DMA_InitTypeDef; |
AnnaBridge | 145:64910690c574 | 189 | /** |
AnnaBridge | 145:64910690c574 | 190 | * @} |
AnnaBridge | 145:64910690c574 | 191 | */ |
AnnaBridge | 145:64910690c574 | 192 | #endif /*USE_FULL_LL_DRIVER*/ |
AnnaBridge | 145:64910690c574 | 193 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 194 | /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants |
AnnaBridge | 145:64910690c574 | 195 | * @{ |
AnnaBridge | 145:64910690c574 | 196 | */ |
AnnaBridge | 145:64910690c574 | 197 | |
AnnaBridge | 145:64910690c574 | 198 | /** @defgroup DMA_LL_EC_STREAM STREAM |
AnnaBridge | 145:64910690c574 | 199 | * @{ |
AnnaBridge | 145:64910690c574 | 200 | */ |
AnnaBridge | 145:64910690c574 | 201 | #define LL_DMA_STREAM_0 0x00000000U |
AnnaBridge | 145:64910690c574 | 202 | #define LL_DMA_STREAM_1 0x00000001U |
AnnaBridge | 145:64910690c574 | 203 | #define LL_DMA_STREAM_2 0x00000002U |
AnnaBridge | 145:64910690c574 | 204 | #define LL_DMA_STREAM_3 0x00000003U |
AnnaBridge | 145:64910690c574 | 205 | #define LL_DMA_STREAM_4 0x00000004U |
AnnaBridge | 145:64910690c574 | 206 | #define LL_DMA_STREAM_5 0x00000005U |
AnnaBridge | 145:64910690c574 | 207 | #define LL_DMA_STREAM_6 0x00000006U |
AnnaBridge | 145:64910690c574 | 208 | #define LL_DMA_STREAM_7 0x00000007U |
AnnaBridge | 145:64910690c574 | 209 | #define LL_DMA_STREAM_ALL 0xFFFF0000U |
AnnaBridge | 145:64910690c574 | 210 | /** |
AnnaBridge | 145:64910690c574 | 211 | * @} |
AnnaBridge | 145:64910690c574 | 212 | */ |
AnnaBridge | 145:64910690c574 | 213 | |
AnnaBridge | 145:64910690c574 | 214 | /** @defgroup DMA_LL_EC_DIRECTION DIRECTION |
AnnaBridge | 145:64910690c574 | 215 | * @{ |
AnnaBridge | 145:64910690c574 | 216 | */ |
AnnaBridge | 145:64910690c574 | 217 | #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ |
AnnaBridge | 145:64910690c574 | 218 | #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */ |
AnnaBridge | 145:64910690c574 | 219 | #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */ |
AnnaBridge | 145:64910690c574 | 220 | /** |
AnnaBridge | 145:64910690c574 | 221 | * @} |
AnnaBridge | 145:64910690c574 | 222 | */ |
AnnaBridge | 145:64910690c574 | 223 | |
AnnaBridge | 145:64910690c574 | 224 | /** @defgroup DMA_LL_EC_MODE MODE |
AnnaBridge | 145:64910690c574 | 225 | * @{ |
AnnaBridge | 145:64910690c574 | 226 | */ |
AnnaBridge | 145:64910690c574 | 227 | #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ |
AnnaBridge | 145:64910690c574 | 228 | #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */ |
AnnaBridge | 145:64910690c574 | 229 | #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */ |
AnnaBridge | 145:64910690c574 | 230 | /** |
AnnaBridge | 145:64910690c574 | 231 | * @} |
AnnaBridge | 145:64910690c574 | 232 | */ |
AnnaBridge | 145:64910690c574 | 233 | |
AnnaBridge | 145:64910690c574 | 234 | /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLEBUFFER MODE |
AnnaBridge | 145:64910690c574 | 235 | * @{ |
AnnaBridge | 145:64910690c574 | 236 | */ |
AnnaBridge | 145:64910690c574 | 237 | #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */ |
AnnaBridge | 145:64910690c574 | 238 | #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */ |
AnnaBridge | 145:64910690c574 | 239 | /** |
AnnaBridge | 145:64910690c574 | 240 | * @} |
AnnaBridge | 145:64910690c574 | 241 | */ |
AnnaBridge | 145:64910690c574 | 242 | |
AnnaBridge | 145:64910690c574 | 243 | /** @defgroup DMA_LL_EC_PERIPH PERIPH |
AnnaBridge | 145:64910690c574 | 244 | * @{ |
AnnaBridge | 145:64910690c574 | 245 | */ |
AnnaBridge | 145:64910690c574 | 246 | #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ |
AnnaBridge | 145:64910690c574 | 247 | #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */ |
AnnaBridge | 145:64910690c574 | 248 | /** |
AnnaBridge | 145:64910690c574 | 249 | * @} |
AnnaBridge | 145:64910690c574 | 250 | */ |
AnnaBridge | 145:64910690c574 | 251 | |
AnnaBridge | 145:64910690c574 | 252 | /** @defgroup DMA_LL_EC_MEMORY MEMORY |
AnnaBridge | 145:64910690c574 | 253 | * @{ |
AnnaBridge | 145:64910690c574 | 254 | */ |
AnnaBridge | 145:64910690c574 | 255 | #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ |
AnnaBridge | 145:64910690c574 | 256 | #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */ |
AnnaBridge | 145:64910690c574 | 257 | /** |
AnnaBridge | 145:64910690c574 | 258 | * @} |
AnnaBridge | 145:64910690c574 | 259 | */ |
AnnaBridge | 145:64910690c574 | 260 | |
AnnaBridge | 145:64910690c574 | 261 | /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN |
AnnaBridge | 145:64910690c574 | 262 | * @{ |
AnnaBridge | 145:64910690c574 | 263 | */ |
AnnaBridge | 145:64910690c574 | 264 | #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ |
AnnaBridge | 145:64910690c574 | 265 | #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ |
AnnaBridge | 145:64910690c574 | 266 | #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */ |
AnnaBridge | 145:64910690c574 | 267 | /** |
AnnaBridge | 145:64910690c574 | 268 | * @} |
AnnaBridge | 145:64910690c574 | 269 | */ |
AnnaBridge | 145:64910690c574 | 270 | |
AnnaBridge | 145:64910690c574 | 271 | /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN |
AnnaBridge | 145:64910690c574 | 272 | * @{ |
AnnaBridge | 145:64910690c574 | 273 | */ |
AnnaBridge | 145:64910690c574 | 274 | #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ |
AnnaBridge | 145:64910690c574 | 275 | #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ |
AnnaBridge | 145:64910690c574 | 276 | #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */ |
AnnaBridge | 145:64910690c574 | 277 | /** |
AnnaBridge | 145:64910690c574 | 278 | * @} |
AnnaBridge | 145:64910690c574 | 279 | */ |
AnnaBridge | 145:64910690c574 | 280 | |
AnnaBridge | 145:64910690c574 | 281 | /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE |
AnnaBridge | 145:64910690c574 | 282 | * @{ |
AnnaBridge | 145:64910690c574 | 283 | */ |
AnnaBridge | 145:64910690c574 | 284 | #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */ |
AnnaBridge | 145:64910690c574 | 285 | #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */ |
AnnaBridge | 145:64910690c574 | 286 | /** |
AnnaBridge | 145:64910690c574 | 287 | * @} |
AnnaBridge | 145:64910690c574 | 288 | */ |
AnnaBridge | 145:64910690c574 | 289 | |
AnnaBridge | 145:64910690c574 | 290 | /** @defgroup DMA_LL_EC_PRIORITY PRIORITY |
AnnaBridge | 145:64910690c574 | 291 | * @{ |
AnnaBridge | 145:64910690c574 | 292 | */ |
AnnaBridge | 145:64910690c574 | 293 | #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ |
AnnaBridge | 145:64910690c574 | 294 | #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */ |
AnnaBridge | 145:64910690c574 | 295 | #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */ |
AnnaBridge | 145:64910690c574 | 296 | #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */ |
AnnaBridge | 145:64910690c574 | 297 | /** |
AnnaBridge | 145:64910690c574 | 298 | * @} |
AnnaBridge | 145:64910690c574 | 299 | */ |
AnnaBridge | 145:64910690c574 | 300 | |
AnnaBridge | 145:64910690c574 | 301 | /** @defgroup DMA_LL_EC_CHANNEL CHANNEL |
AnnaBridge | 145:64910690c574 | 302 | * @{ |
AnnaBridge | 145:64910690c574 | 303 | */ |
AnnaBridge | 145:64910690c574 | 304 | #define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */ |
AnnaBridge | 145:64910690c574 | 305 | #define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */ |
AnnaBridge | 145:64910690c574 | 306 | #define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */ |
AnnaBridge | 145:64910690c574 | 307 | #define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */ |
AnnaBridge | 145:64910690c574 | 308 | #define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */ |
AnnaBridge | 145:64910690c574 | 309 | #define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */ |
AnnaBridge | 145:64910690c574 | 310 | #define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */ |
AnnaBridge | 145:64910690c574 | 311 | #define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */ |
AnnaBridge | 145:64910690c574 | 312 | /** |
AnnaBridge | 145:64910690c574 | 313 | * @} |
AnnaBridge | 145:64910690c574 | 314 | */ |
AnnaBridge | 145:64910690c574 | 315 | |
AnnaBridge | 145:64910690c574 | 316 | /** @defgroup DMA_LL_EC_MBURST MBURST |
AnnaBridge | 145:64910690c574 | 317 | * @{ |
AnnaBridge | 145:64910690c574 | 318 | */ |
AnnaBridge | 145:64910690c574 | 319 | #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */ |
AnnaBridge | 145:64910690c574 | 320 | #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */ |
AnnaBridge | 145:64910690c574 | 321 | #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */ |
AnnaBridge | 145:64910690c574 | 322 | #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */ |
AnnaBridge | 145:64910690c574 | 323 | /** |
AnnaBridge | 145:64910690c574 | 324 | * @} |
AnnaBridge | 145:64910690c574 | 325 | */ |
AnnaBridge | 145:64910690c574 | 326 | |
AnnaBridge | 145:64910690c574 | 327 | /** @defgroup DMA_LL_EC_PBURST PBURST |
AnnaBridge | 145:64910690c574 | 328 | * @{ |
AnnaBridge | 145:64910690c574 | 329 | */ |
AnnaBridge | 145:64910690c574 | 330 | #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */ |
AnnaBridge | 145:64910690c574 | 331 | #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */ |
AnnaBridge | 145:64910690c574 | 332 | #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */ |
AnnaBridge | 145:64910690c574 | 333 | #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */ |
AnnaBridge | 145:64910690c574 | 334 | /** |
AnnaBridge | 145:64910690c574 | 335 | * @} |
AnnaBridge | 145:64910690c574 | 336 | */ |
AnnaBridge | 145:64910690c574 | 337 | |
AnnaBridge | 145:64910690c574 | 338 | /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE |
AnnaBridge | 145:64910690c574 | 339 | * @{ |
AnnaBridge | 145:64910690c574 | 340 | */ |
AnnaBridge | 145:64910690c574 | 341 | #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */ |
AnnaBridge | 145:64910690c574 | 342 | #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ |
AnnaBridge | 145:64910690c574 | 343 | /** |
AnnaBridge | 145:64910690c574 | 344 | * @} |
AnnaBridge | 145:64910690c574 | 345 | */ |
AnnaBridge | 145:64910690c574 | 346 | |
AnnaBridge | 145:64910690c574 | 347 | /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 |
AnnaBridge | 145:64910690c574 | 348 | * @{ |
AnnaBridge | 145:64910690c574 | 349 | */ |
AnnaBridge | 145:64910690c574 | 350 | #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */ |
AnnaBridge | 145:64910690c574 | 351 | #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */ |
AnnaBridge | 145:64910690c574 | 352 | #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */ |
AnnaBridge | 145:64910690c574 | 353 | #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */ |
AnnaBridge | 145:64910690c574 | 354 | #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */ |
AnnaBridge | 145:64910690c574 | 355 | #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */ |
AnnaBridge | 145:64910690c574 | 356 | /** |
AnnaBridge | 145:64910690c574 | 357 | * @} |
AnnaBridge | 145:64910690c574 | 358 | */ |
AnnaBridge | 145:64910690c574 | 359 | |
AnnaBridge | 145:64910690c574 | 360 | /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD |
AnnaBridge | 145:64910690c574 | 361 | * @{ |
AnnaBridge | 145:64910690c574 | 362 | */ |
AnnaBridge | 145:64910690c574 | 363 | #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */ |
AnnaBridge | 145:64910690c574 | 364 | #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */ |
AnnaBridge | 145:64910690c574 | 365 | #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */ |
AnnaBridge | 145:64910690c574 | 366 | #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */ |
AnnaBridge | 145:64910690c574 | 367 | /** |
AnnaBridge | 145:64910690c574 | 368 | * @} |
AnnaBridge | 145:64910690c574 | 369 | */ |
AnnaBridge | 145:64910690c574 | 370 | |
AnnaBridge | 145:64910690c574 | 371 | /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM |
AnnaBridge | 145:64910690c574 | 372 | * @{ |
AnnaBridge | 145:64910690c574 | 373 | */ |
AnnaBridge | 145:64910690c574 | 374 | #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */ |
AnnaBridge | 145:64910690c574 | 375 | #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */ |
AnnaBridge | 145:64910690c574 | 376 | /** |
AnnaBridge | 145:64910690c574 | 377 | * @} |
AnnaBridge | 145:64910690c574 | 378 | */ |
AnnaBridge | 145:64910690c574 | 379 | |
AnnaBridge | 145:64910690c574 | 380 | /** |
AnnaBridge | 145:64910690c574 | 381 | * @} |
AnnaBridge | 145:64910690c574 | 382 | */ |
AnnaBridge | 145:64910690c574 | 383 | |
AnnaBridge | 145:64910690c574 | 384 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 385 | /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros |
AnnaBridge | 145:64910690c574 | 386 | * @{ |
AnnaBridge | 145:64910690c574 | 387 | */ |
AnnaBridge | 145:64910690c574 | 388 | |
AnnaBridge | 145:64910690c574 | 389 | /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros |
AnnaBridge | 145:64910690c574 | 390 | * @{ |
AnnaBridge | 145:64910690c574 | 391 | */ |
AnnaBridge | 145:64910690c574 | 392 | /** |
AnnaBridge | 145:64910690c574 | 393 | * @brief Write a value in DMA register |
AnnaBridge | 145:64910690c574 | 394 | * @param __INSTANCE__ DMA Instance |
AnnaBridge | 145:64910690c574 | 395 | * @param __REG__ Register to be written |
AnnaBridge | 145:64910690c574 | 396 | * @param __VALUE__ Value to be written in the register |
AnnaBridge | 145:64910690c574 | 397 | * @retval None |
AnnaBridge | 145:64910690c574 | 398 | */ |
AnnaBridge | 145:64910690c574 | 399 | #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
AnnaBridge | 145:64910690c574 | 400 | |
AnnaBridge | 145:64910690c574 | 401 | /** |
AnnaBridge | 145:64910690c574 | 402 | * @brief Read a value in DMA register |
AnnaBridge | 145:64910690c574 | 403 | * @param __INSTANCE__ DMA Instance |
AnnaBridge | 145:64910690c574 | 404 | * @param __REG__ Register to be read |
AnnaBridge | 145:64910690c574 | 405 | * @retval Register value |
AnnaBridge | 145:64910690c574 | 406 | */ |
AnnaBridge | 145:64910690c574 | 407 | #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
AnnaBridge | 145:64910690c574 | 408 | /** |
AnnaBridge | 145:64910690c574 | 409 | * @} |
AnnaBridge | 145:64910690c574 | 410 | */ |
AnnaBridge | 145:64910690c574 | 411 | |
AnnaBridge | 145:64910690c574 | 412 | /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy |
AnnaBridge | 145:64910690c574 | 413 | * @{ |
AnnaBridge | 145:64910690c574 | 414 | */ |
AnnaBridge | 145:64910690c574 | 415 | /** |
AnnaBridge | 145:64910690c574 | 416 | * @brief Convert DMAx_Streamy into DMAx |
AnnaBridge | 145:64910690c574 | 417 | * @param __STREAM_INSTANCE__ DMAx_Streamy |
AnnaBridge | 145:64910690c574 | 418 | * @retval DMAx |
AnnaBridge | 145:64910690c574 | 419 | */ |
AnnaBridge | 145:64910690c574 | 420 | #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ |
AnnaBridge | 145:64910690c574 | 421 | (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) |
AnnaBridge | 145:64910690c574 | 422 | |
AnnaBridge | 145:64910690c574 | 423 | /** |
AnnaBridge | 145:64910690c574 | 424 | * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y |
AnnaBridge | 145:64910690c574 | 425 | * @param __STREAM_INSTANCE__ DMAx_Streamy |
AnnaBridge | 145:64910690c574 | 426 | * @retval LL_DMA_CHANNEL_y |
AnnaBridge | 145:64910690c574 | 427 | */ |
AnnaBridge | 145:64910690c574 | 428 | #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ |
AnnaBridge | 145:64910690c574 | 429 | (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ |
AnnaBridge | 145:64910690c574 | 430 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ |
AnnaBridge | 145:64910690c574 | 431 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ |
AnnaBridge | 145:64910690c574 | 432 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ |
AnnaBridge | 145:64910690c574 | 433 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ |
AnnaBridge | 145:64910690c574 | 434 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ |
AnnaBridge | 145:64910690c574 | 435 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ |
AnnaBridge | 145:64910690c574 | 436 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ |
AnnaBridge | 145:64910690c574 | 437 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ |
AnnaBridge | 145:64910690c574 | 438 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ |
AnnaBridge | 145:64910690c574 | 439 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ |
AnnaBridge | 145:64910690c574 | 440 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ |
AnnaBridge | 145:64910690c574 | 441 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ |
AnnaBridge | 145:64910690c574 | 442 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ |
AnnaBridge | 145:64910690c574 | 443 | LL_DMA_STREAM_7) |
AnnaBridge | 145:64910690c574 | 444 | |
AnnaBridge | 145:64910690c574 | 445 | /** |
AnnaBridge | 145:64910690c574 | 446 | * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy |
AnnaBridge | 145:64910690c574 | 447 | * @param __DMA_INSTANCE__ DMAx |
AnnaBridge | 145:64910690c574 | 448 | * @param __STREAM__ LL_DMA_STREAM_y |
AnnaBridge | 145:64910690c574 | 449 | * @retval DMAx_Streamy |
AnnaBridge | 145:64910690c574 | 450 | */ |
AnnaBridge | 145:64910690c574 | 451 | #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ |
AnnaBridge | 145:64910690c574 | 452 | ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \ |
AnnaBridge | 145:64910690c574 | 453 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \ |
AnnaBridge | 145:64910690c574 | 454 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \ |
AnnaBridge | 145:64910690c574 | 455 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \ |
AnnaBridge | 145:64910690c574 | 456 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \ |
AnnaBridge | 145:64910690c574 | 457 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \ |
AnnaBridge | 145:64910690c574 | 458 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \ |
AnnaBridge | 145:64910690c574 | 459 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \ |
AnnaBridge | 145:64910690c574 | 460 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \ |
AnnaBridge | 145:64910690c574 | 461 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \ |
AnnaBridge | 145:64910690c574 | 462 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \ |
AnnaBridge | 145:64910690c574 | 463 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \ |
AnnaBridge | 145:64910690c574 | 464 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \ |
AnnaBridge | 145:64910690c574 | 465 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \ |
AnnaBridge | 145:64910690c574 | 466 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \ |
AnnaBridge | 145:64910690c574 | 467 | DMA2_Stream7) |
AnnaBridge | 145:64910690c574 | 468 | |
AnnaBridge | 145:64910690c574 | 469 | /** |
AnnaBridge | 145:64910690c574 | 470 | * @} |
AnnaBridge | 145:64910690c574 | 471 | */ |
AnnaBridge | 145:64910690c574 | 472 | |
AnnaBridge | 145:64910690c574 | 473 | /** |
AnnaBridge | 145:64910690c574 | 474 | * @} |
AnnaBridge | 145:64910690c574 | 475 | */ |
AnnaBridge | 145:64910690c574 | 476 | |
AnnaBridge | 145:64910690c574 | 477 | |
AnnaBridge | 145:64910690c574 | 478 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 479 | /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions |
AnnaBridge | 145:64910690c574 | 480 | * @{ |
AnnaBridge | 145:64910690c574 | 481 | */ |
AnnaBridge | 145:64910690c574 | 482 | |
AnnaBridge | 145:64910690c574 | 483 | /** @defgroup DMA_LL_EF_Configuration Configuration |
AnnaBridge | 145:64910690c574 | 484 | * @{ |
AnnaBridge | 145:64910690c574 | 485 | */ |
AnnaBridge | 145:64910690c574 | 486 | /** |
AnnaBridge | 145:64910690c574 | 487 | * @brief Enable DMA stream. |
AnnaBridge | 145:64910690c574 | 488 | * @rmtoll CR EN LL_DMA_EnableStream |
AnnaBridge | 145:64910690c574 | 489 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 490 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 491 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 492 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 493 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 494 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 495 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 496 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 497 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 498 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 499 | * @retval None |
AnnaBridge | 145:64910690c574 | 500 | */ |
AnnaBridge | 145:64910690c574 | 501 | __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 502 | { |
AnnaBridge | 145:64910690c574 | 503 | SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); |
AnnaBridge | 145:64910690c574 | 504 | } |
AnnaBridge | 145:64910690c574 | 505 | |
AnnaBridge | 145:64910690c574 | 506 | /** |
AnnaBridge | 145:64910690c574 | 507 | * @brief Disable DMA stream. |
AnnaBridge | 145:64910690c574 | 508 | * @rmtoll CR EN LL_DMA_DisableStream |
AnnaBridge | 145:64910690c574 | 509 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 510 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 511 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 512 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 513 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 514 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 515 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 516 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 517 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 518 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 519 | * @retval None |
AnnaBridge | 145:64910690c574 | 520 | */ |
AnnaBridge | 145:64910690c574 | 521 | __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 522 | { |
AnnaBridge | 145:64910690c574 | 523 | CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); |
AnnaBridge | 145:64910690c574 | 524 | } |
AnnaBridge | 145:64910690c574 | 525 | |
AnnaBridge | 145:64910690c574 | 526 | /** |
AnnaBridge | 145:64910690c574 | 527 | * @brief Check if DMA stream is enabled or disabled. |
AnnaBridge | 145:64910690c574 | 528 | * @rmtoll CR EN LL_DMA_IsEnabledStream |
AnnaBridge | 145:64910690c574 | 529 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 530 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 531 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 532 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 533 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 534 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 535 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 536 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 537 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 538 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 539 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 540 | */ |
AnnaBridge | 145:64910690c574 | 541 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 542 | { |
AnnaBridge | 145:64910690c574 | 543 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)); |
AnnaBridge | 145:64910690c574 | 544 | } |
AnnaBridge | 145:64910690c574 | 545 | |
AnnaBridge | 145:64910690c574 | 546 | /** |
AnnaBridge | 145:64910690c574 | 547 | * @brief Configure all parameters linked to DMA transfer. |
AnnaBridge | 145:64910690c574 | 548 | * @rmtoll CR DIR LL_DMA_ConfigTransfer\n |
AnnaBridge | 145:64910690c574 | 549 | * CR CIRC LL_DMA_ConfigTransfer\n |
AnnaBridge | 145:64910690c574 | 550 | * CR PINC LL_DMA_ConfigTransfer\n |
AnnaBridge | 145:64910690c574 | 551 | * CR MINC LL_DMA_ConfigTransfer\n |
AnnaBridge | 145:64910690c574 | 552 | * CR PSIZE LL_DMA_ConfigTransfer\n |
AnnaBridge | 145:64910690c574 | 553 | * CR MSIZE LL_DMA_ConfigTransfer\n |
AnnaBridge | 145:64910690c574 | 554 | * CR PL LL_DMA_ConfigTransfer\n |
AnnaBridge | 145:64910690c574 | 555 | * CR PFCTRL LL_DMA_ConfigTransfer |
AnnaBridge | 145:64910690c574 | 556 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 557 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 558 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 559 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 560 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 561 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 562 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 563 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 564 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 565 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 566 | * @param Configuration This parameter must be a combination of all the following values: |
AnnaBridge | 145:64910690c574 | 567 | * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY |
AnnaBridge | 145:64910690c574 | 568 | * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL |
AnnaBridge | 145:64910690c574 | 569 | * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT |
AnnaBridge | 145:64910690c574 | 570 | * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT |
AnnaBridge | 145:64910690c574 | 571 | * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD |
AnnaBridge | 145:64910690c574 | 572 | * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD |
AnnaBridge | 145:64910690c574 | 573 | * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH |
AnnaBridge | 145:64910690c574 | 574 | *@retval None |
AnnaBridge | 145:64910690c574 | 575 | */ |
AnnaBridge | 145:64910690c574 | 576 | __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) |
AnnaBridge | 145:64910690c574 | 577 | { |
AnnaBridge | 145:64910690c574 | 578 | MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, |
AnnaBridge | 145:64910690c574 | 579 | DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL, |
AnnaBridge | 145:64910690c574 | 580 | Configuration); |
AnnaBridge | 145:64910690c574 | 581 | } |
AnnaBridge | 145:64910690c574 | 582 | |
AnnaBridge | 145:64910690c574 | 583 | /** |
AnnaBridge | 145:64910690c574 | 584 | * @brief Set Data transfer direction (read from peripheral or from memory). |
AnnaBridge | 145:64910690c574 | 585 | * @rmtoll CR DIR LL_DMA_SetDataTransferDirection |
AnnaBridge | 145:64910690c574 | 586 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 587 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 588 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 589 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 590 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 591 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 592 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 593 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 594 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 595 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 596 | * @param Direction This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 597 | * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY |
AnnaBridge | 145:64910690c574 | 598 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH |
AnnaBridge | 145:64910690c574 | 599 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY |
AnnaBridge | 145:64910690c574 | 600 | * @retval None |
AnnaBridge | 145:64910690c574 | 601 | */ |
AnnaBridge | 145:64910690c574 | 602 | __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) |
AnnaBridge | 145:64910690c574 | 603 | { |
AnnaBridge | 145:64910690c574 | 604 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction); |
AnnaBridge | 145:64910690c574 | 605 | } |
AnnaBridge | 145:64910690c574 | 606 | |
AnnaBridge | 145:64910690c574 | 607 | /** |
AnnaBridge | 145:64910690c574 | 608 | * @brief Get Data transfer direction (read from peripheral or from memory). |
AnnaBridge | 145:64910690c574 | 609 | * @rmtoll CR DIR LL_DMA_GetDataTransferDirection |
AnnaBridge | 145:64910690c574 | 610 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 611 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 612 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 613 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 614 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 615 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 616 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 617 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 618 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 619 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 620 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 621 | * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY |
AnnaBridge | 145:64910690c574 | 622 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH |
AnnaBridge | 145:64910690c574 | 623 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY |
AnnaBridge | 145:64910690c574 | 624 | */ |
AnnaBridge | 145:64910690c574 | 625 | __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 626 | { |
AnnaBridge | 145:64910690c574 | 627 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR)); |
AnnaBridge | 145:64910690c574 | 628 | } |
AnnaBridge | 145:64910690c574 | 629 | |
AnnaBridge | 145:64910690c574 | 630 | /** |
AnnaBridge | 145:64910690c574 | 631 | * @brief Set DMA mode normal, circular or peripheral flow control. |
AnnaBridge | 145:64910690c574 | 632 | * @rmtoll CR CIRC LL_DMA_SetMode\n |
AnnaBridge | 145:64910690c574 | 633 | * CR PFCTRL LL_DMA_SetMode |
AnnaBridge | 145:64910690c574 | 634 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 635 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 636 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 637 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 638 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 639 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 640 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 641 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 642 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 643 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 644 | * @param Mode This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 645 | * @arg @ref LL_DMA_MODE_NORMAL |
AnnaBridge | 145:64910690c574 | 646 | * @arg @ref LL_DMA_MODE_CIRCULAR |
AnnaBridge | 145:64910690c574 | 647 | * @arg @ref LL_DMA_MODE_PFCTRL |
AnnaBridge | 145:64910690c574 | 648 | * @retval None |
AnnaBridge | 145:64910690c574 | 649 | */ |
AnnaBridge | 145:64910690c574 | 650 | __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) |
AnnaBridge | 145:64910690c574 | 651 | { |
AnnaBridge | 145:64910690c574 | 652 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode); |
AnnaBridge | 145:64910690c574 | 653 | } |
AnnaBridge | 145:64910690c574 | 654 | |
AnnaBridge | 145:64910690c574 | 655 | /** |
AnnaBridge | 145:64910690c574 | 656 | * @brief Get DMA mode normal, circular or peripheral flow control. |
AnnaBridge | 145:64910690c574 | 657 | * @rmtoll CR CIRC LL_DMA_GetMode\n |
AnnaBridge | 145:64910690c574 | 658 | * CR PFCTRL LL_DMA_GetMode |
AnnaBridge | 145:64910690c574 | 659 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 660 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 661 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 662 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 663 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 664 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 665 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 666 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 667 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 668 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 669 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 670 | * @arg @ref LL_DMA_MODE_NORMAL |
AnnaBridge | 145:64910690c574 | 671 | * @arg @ref LL_DMA_MODE_CIRCULAR |
AnnaBridge | 145:64910690c574 | 672 | * @arg @ref LL_DMA_MODE_PFCTRL |
AnnaBridge | 145:64910690c574 | 673 | */ |
AnnaBridge | 145:64910690c574 | 674 | __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 675 | { |
AnnaBridge | 145:64910690c574 | 676 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL)); |
AnnaBridge | 145:64910690c574 | 677 | } |
AnnaBridge | 145:64910690c574 | 678 | |
AnnaBridge | 145:64910690c574 | 679 | /** |
AnnaBridge | 145:64910690c574 | 680 | * @brief Set Peripheral increment mode. |
AnnaBridge | 145:64910690c574 | 681 | * @rmtoll CR PINC LL_DMA_SetPeriphIncMode |
AnnaBridge | 145:64910690c574 | 682 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 683 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 684 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 685 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 686 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 687 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 688 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 689 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 690 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 691 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 692 | * @param IncrementMode This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 693 | * @arg @ref LL_DMA_PERIPH_NOINCREMENT |
AnnaBridge | 145:64910690c574 | 694 | * @arg @ref LL_DMA_PERIPH_INCREMENT |
AnnaBridge | 145:64910690c574 | 695 | * @retval None |
AnnaBridge | 145:64910690c574 | 696 | */ |
AnnaBridge | 145:64910690c574 | 697 | __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) |
AnnaBridge | 145:64910690c574 | 698 | { |
AnnaBridge | 145:64910690c574 | 699 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode); |
AnnaBridge | 145:64910690c574 | 700 | } |
AnnaBridge | 145:64910690c574 | 701 | |
AnnaBridge | 145:64910690c574 | 702 | /** |
AnnaBridge | 145:64910690c574 | 703 | * @brief Get Peripheral increment mode. |
AnnaBridge | 145:64910690c574 | 704 | * @rmtoll CR PINC LL_DMA_GetPeriphIncMode |
AnnaBridge | 145:64910690c574 | 705 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 706 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 707 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 708 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 709 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 710 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 711 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 712 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 713 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 714 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 715 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 716 | * @arg @ref LL_DMA_PERIPH_NOINCREMENT |
AnnaBridge | 145:64910690c574 | 717 | * @arg @ref LL_DMA_PERIPH_INCREMENT |
AnnaBridge | 145:64910690c574 | 718 | */ |
AnnaBridge | 145:64910690c574 | 719 | __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 720 | { |
AnnaBridge | 145:64910690c574 | 721 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC)); |
AnnaBridge | 145:64910690c574 | 722 | } |
AnnaBridge | 145:64910690c574 | 723 | |
AnnaBridge | 145:64910690c574 | 724 | /** |
AnnaBridge | 145:64910690c574 | 725 | * @brief Set Memory increment mode. |
AnnaBridge | 145:64910690c574 | 726 | * @rmtoll CR MINC LL_DMA_SetMemoryIncMode |
AnnaBridge | 145:64910690c574 | 727 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 728 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 729 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 730 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 731 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 732 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 733 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 734 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 735 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 736 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 737 | * @param IncrementMode This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 738 | * @arg @ref LL_DMA_MEMORY_NOINCREMENT |
AnnaBridge | 145:64910690c574 | 739 | * @arg @ref LL_DMA_MEMORY_INCREMENT |
AnnaBridge | 145:64910690c574 | 740 | * @retval None |
AnnaBridge | 145:64910690c574 | 741 | */ |
AnnaBridge | 145:64910690c574 | 742 | __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) |
AnnaBridge | 145:64910690c574 | 743 | { |
AnnaBridge | 145:64910690c574 | 744 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode); |
AnnaBridge | 145:64910690c574 | 745 | } |
AnnaBridge | 145:64910690c574 | 746 | |
AnnaBridge | 145:64910690c574 | 747 | /** |
AnnaBridge | 145:64910690c574 | 748 | * @brief Get Memory increment mode. |
AnnaBridge | 145:64910690c574 | 749 | * @rmtoll CR MINC LL_DMA_GetMemoryIncMode |
AnnaBridge | 145:64910690c574 | 750 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 751 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 752 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 753 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 754 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 755 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 756 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 757 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 758 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 759 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 760 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 761 | * @arg @ref LL_DMA_MEMORY_NOINCREMENT |
AnnaBridge | 145:64910690c574 | 762 | * @arg @ref LL_DMA_MEMORY_INCREMENT |
AnnaBridge | 145:64910690c574 | 763 | */ |
AnnaBridge | 145:64910690c574 | 764 | __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 765 | { |
AnnaBridge | 145:64910690c574 | 766 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC)); |
AnnaBridge | 145:64910690c574 | 767 | } |
AnnaBridge | 145:64910690c574 | 768 | |
AnnaBridge | 145:64910690c574 | 769 | /** |
AnnaBridge | 145:64910690c574 | 770 | * @brief Set Peripheral size. |
AnnaBridge | 145:64910690c574 | 771 | * @rmtoll CR PSIZE LL_DMA_SetPeriphSize |
AnnaBridge | 145:64910690c574 | 772 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 773 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 774 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 775 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 776 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 777 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 778 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 779 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 780 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 781 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 782 | * @param Size This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 783 | * @arg @ref LL_DMA_PDATAALIGN_BYTE |
AnnaBridge | 145:64910690c574 | 784 | * @arg @ref LL_DMA_PDATAALIGN_HALFWORD |
AnnaBridge | 145:64910690c574 | 785 | * @arg @ref LL_DMA_PDATAALIGN_WORD |
AnnaBridge | 145:64910690c574 | 786 | * @retval None |
AnnaBridge | 145:64910690c574 | 787 | */ |
AnnaBridge | 145:64910690c574 | 788 | __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) |
AnnaBridge | 145:64910690c574 | 789 | { |
AnnaBridge | 145:64910690c574 | 790 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size); |
AnnaBridge | 145:64910690c574 | 791 | } |
AnnaBridge | 145:64910690c574 | 792 | |
AnnaBridge | 145:64910690c574 | 793 | /** |
AnnaBridge | 145:64910690c574 | 794 | * @brief Get Peripheral size. |
AnnaBridge | 145:64910690c574 | 795 | * @rmtoll CR PSIZE LL_DMA_GetPeriphSize |
AnnaBridge | 145:64910690c574 | 796 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 797 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 798 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 799 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 800 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 801 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 802 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 803 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 804 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 805 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 806 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 807 | * @arg @ref LL_DMA_PDATAALIGN_BYTE |
AnnaBridge | 145:64910690c574 | 808 | * @arg @ref LL_DMA_PDATAALIGN_HALFWORD |
AnnaBridge | 145:64910690c574 | 809 | * @arg @ref LL_DMA_PDATAALIGN_WORD |
AnnaBridge | 145:64910690c574 | 810 | */ |
AnnaBridge | 145:64910690c574 | 811 | __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 812 | { |
AnnaBridge | 145:64910690c574 | 813 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE)); |
AnnaBridge | 145:64910690c574 | 814 | } |
AnnaBridge | 145:64910690c574 | 815 | |
AnnaBridge | 145:64910690c574 | 816 | /** |
AnnaBridge | 145:64910690c574 | 817 | * @brief Set Memory size. |
AnnaBridge | 145:64910690c574 | 818 | * @rmtoll CR MSIZE LL_DMA_SetMemorySize |
AnnaBridge | 145:64910690c574 | 819 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 820 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 821 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 822 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 823 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 824 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 825 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 826 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 827 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 828 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 829 | * @param Size This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 830 | * @arg @ref LL_DMA_MDATAALIGN_BYTE |
AnnaBridge | 145:64910690c574 | 831 | * @arg @ref LL_DMA_MDATAALIGN_HALFWORD |
AnnaBridge | 145:64910690c574 | 832 | * @arg @ref LL_DMA_MDATAALIGN_WORD |
AnnaBridge | 145:64910690c574 | 833 | * @retval None |
AnnaBridge | 145:64910690c574 | 834 | */ |
AnnaBridge | 145:64910690c574 | 835 | __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) |
AnnaBridge | 145:64910690c574 | 836 | { |
AnnaBridge | 145:64910690c574 | 837 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size); |
AnnaBridge | 145:64910690c574 | 838 | } |
AnnaBridge | 145:64910690c574 | 839 | |
AnnaBridge | 145:64910690c574 | 840 | /** |
AnnaBridge | 145:64910690c574 | 841 | * @brief Get Memory size. |
AnnaBridge | 145:64910690c574 | 842 | * @rmtoll CR MSIZE LL_DMA_GetMemorySize |
AnnaBridge | 145:64910690c574 | 843 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 844 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 845 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 846 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 847 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 848 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 849 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 850 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 851 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 852 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 853 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 854 | * @arg @ref LL_DMA_MDATAALIGN_BYTE |
AnnaBridge | 145:64910690c574 | 855 | * @arg @ref LL_DMA_MDATAALIGN_HALFWORD |
AnnaBridge | 145:64910690c574 | 856 | * @arg @ref LL_DMA_MDATAALIGN_WORD |
AnnaBridge | 145:64910690c574 | 857 | */ |
AnnaBridge | 145:64910690c574 | 858 | __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 859 | { |
AnnaBridge | 145:64910690c574 | 860 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE)); |
AnnaBridge | 145:64910690c574 | 861 | } |
AnnaBridge | 145:64910690c574 | 862 | |
AnnaBridge | 145:64910690c574 | 863 | /** |
AnnaBridge | 145:64910690c574 | 864 | * @brief Set Peripheral increment offset size. |
AnnaBridge | 145:64910690c574 | 865 | * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize |
AnnaBridge | 145:64910690c574 | 866 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 867 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 868 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 869 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 870 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 871 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 872 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 873 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 874 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 875 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 876 | * @param OffsetSize This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 877 | * @arg @ref LL_DMA_OFFSETSIZE_PSIZE |
AnnaBridge | 145:64910690c574 | 878 | * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 |
AnnaBridge | 145:64910690c574 | 879 | * @retval None |
AnnaBridge | 145:64910690c574 | 880 | */ |
AnnaBridge | 145:64910690c574 | 881 | __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) |
AnnaBridge | 145:64910690c574 | 882 | { |
AnnaBridge | 145:64910690c574 | 883 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize); |
AnnaBridge | 145:64910690c574 | 884 | } |
AnnaBridge | 145:64910690c574 | 885 | |
AnnaBridge | 145:64910690c574 | 886 | /** |
AnnaBridge | 145:64910690c574 | 887 | * @brief Get Peripheral increment offset size. |
AnnaBridge | 145:64910690c574 | 888 | * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize |
AnnaBridge | 145:64910690c574 | 889 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 890 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 891 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 892 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 893 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 894 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 895 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 896 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 897 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 898 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 899 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 900 | * @arg @ref LL_DMA_OFFSETSIZE_PSIZE |
AnnaBridge | 145:64910690c574 | 901 | * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 |
AnnaBridge | 145:64910690c574 | 902 | */ |
AnnaBridge | 145:64910690c574 | 903 | __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 904 | { |
AnnaBridge | 145:64910690c574 | 905 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS)); |
AnnaBridge | 145:64910690c574 | 906 | } |
AnnaBridge | 145:64910690c574 | 907 | |
AnnaBridge | 145:64910690c574 | 908 | /** |
AnnaBridge | 145:64910690c574 | 909 | * @brief Set Stream priority level. |
AnnaBridge | 145:64910690c574 | 910 | * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel |
AnnaBridge | 145:64910690c574 | 911 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 912 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 913 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 914 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 915 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 916 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 917 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 918 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 919 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 920 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 921 | * @param Priority This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 922 | * @arg @ref LL_DMA_PRIORITY_LOW |
AnnaBridge | 145:64910690c574 | 923 | * @arg @ref LL_DMA_PRIORITY_MEDIUM |
AnnaBridge | 145:64910690c574 | 924 | * @arg @ref LL_DMA_PRIORITY_HIGH |
AnnaBridge | 145:64910690c574 | 925 | * @arg @ref LL_DMA_PRIORITY_VERYHIGH |
AnnaBridge | 145:64910690c574 | 926 | * @retval None |
AnnaBridge | 145:64910690c574 | 927 | */ |
AnnaBridge | 145:64910690c574 | 928 | __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) |
AnnaBridge | 145:64910690c574 | 929 | { |
AnnaBridge | 145:64910690c574 | 930 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority); |
AnnaBridge | 145:64910690c574 | 931 | } |
AnnaBridge | 145:64910690c574 | 932 | |
AnnaBridge | 145:64910690c574 | 933 | /** |
AnnaBridge | 145:64910690c574 | 934 | * @brief Get Stream priority level. |
AnnaBridge | 145:64910690c574 | 935 | * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel |
AnnaBridge | 145:64910690c574 | 936 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 937 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 938 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 939 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 940 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 941 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 942 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 943 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 944 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 945 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 946 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 947 | * @arg @ref LL_DMA_PRIORITY_LOW |
AnnaBridge | 145:64910690c574 | 948 | * @arg @ref LL_DMA_PRIORITY_MEDIUM |
AnnaBridge | 145:64910690c574 | 949 | * @arg @ref LL_DMA_PRIORITY_HIGH |
AnnaBridge | 145:64910690c574 | 950 | * @arg @ref LL_DMA_PRIORITY_VERYHIGH |
AnnaBridge | 145:64910690c574 | 951 | */ |
AnnaBridge | 145:64910690c574 | 952 | __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 953 | { |
AnnaBridge | 145:64910690c574 | 954 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL)); |
AnnaBridge | 145:64910690c574 | 955 | } |
AnnaBridge | 145:64910690c574 | 956 | |
AnnaBridge | 145:64910690c574 | 957 | /** |
AnnaBridge | 145:64910690c574 | 958 | * @brief Set Number of data to transfer. |
AnnaBridge | 145:64910690c574 | 959 | * @rmtoll NDTR NDT LL_DMA_SetDataLength |
AnnaBridge | 145:64910690c574 | 960 | * @note This action has no effect if |
AnnaBridge | 145:64910690c574 | 961 | * stream is enabled. |
AnnaBridge | 145:64910690c574 | 962 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 963 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 964 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 965 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 966 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 967 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 968 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 969 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 970 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 971 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 972 | * @param NbData Between 0 to 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 973 | * @retval None |
AnnaBridge | 145:64910690c574 | 974 | */ |
AnnaBridge | 145:64910690c574 | 975 | __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData) |
AnnaBridge | 145:64910690c574 | 976 | { |
AnnaBridge | 145:64910690c574 | 977 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData); |
AnnaBridge | 145:64910690c574 | 978 | } |
AnnaBridge | 145:64910690c574 | 979 | |
AnnaBridge | 145:64910690c574 | 980 | /** |
AnnaBridge | 145:64910690c574 | 981 | * @brief Get Number of data to transfer. |
AnnaBridge | 145:64910690c574 | 982 | * @rmtoll NDTR NDT LL_DMA_GetDataLength |
AnnaBridge | 145:64910690c574 | 983 | * @note Once the stream is enabled, the return value indicate the |
AnnaBridge | 145:64910690c574 | 984 | * remaining bytes to be transmitted. |
AnnaBridge | 145:64910690c574 | 985 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 986 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 987 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 988 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 989 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 990 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 991 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 992 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 993 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 994 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 995 | * @retval Between 0 to 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 996 | */ |
AnnaBridge | 145:64910690c574 | 997 | __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 998 | { |
AnnaBridge | 145:64910690c574 | 999 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT)); |
AnnaBridge | 145:64910690c574 | 1000 | } |
AnnaBridge | 145:64910690c574 | 1001 | |
AnnaBridge | 145:64910690c574 | 1002 | /** |
AnnaBridge | 145:64910690c574 | 1003 | * @brief Select Channel number associated to the Stream. |
AnnaBridge | 145:64910690c574 | 1004 | * @rmtoll CR CHSEL LL_DMA_SetChannelSelection |
AnnaBridge | 145:64910690c574 | 1005 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1006 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1007 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1008 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1009 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1010 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1011 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1012 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1013 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1014 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1015 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1016 | * @arg @ref LL_DMA_CHANNEL_0 |
AnnaBridge | 145:64910690c574 | 1017 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 1018 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 1019 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 1020 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 1021 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 1022 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 1023 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 1024 | * @retval None |
AnnaBridge | 145:64910690c574 | 1025 | */ |
AnnaBridge | 145:64910690c574 | 1026 | __STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 1027 | { |
AnnaBridge | 145:64910690c574 | 1028 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel); |
AnnaBridge | 145:64910690c574 | 1029 | } |
AnnaBridge | 145:64910690c574 | 1030 | |
AnnaBridge | 145:64910690c574 | 1031 | /** |
AnnaBridge | 145:64910690c574 | 1032 | * @brief Get the Channel number associated to the Stream. |
AnnaBridge | 145:64910690c574 | 1033 | * @rmtoll CR CHSEL LL_DMA_GetChannelSelection |
AnnaBridge | 145:64910690c574 | 1034 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1035 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1036 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1037 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1038 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1039 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1040 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1041 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1042 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1043 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1044 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1045 | * @arg @ref LL_DMA_CHANNEL_0 |
AnnaBridge | 145:64910690c574 | 1046 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 1047 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 1048 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 1049 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 1050 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 1051 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 1052 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 1053 | */ |
AnnaBridge | 145:64910690c574 | 1054 | __STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 1055 | { |
AnnaBridge | 145:64910690c574 | 1056 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL)); |
AnnaBridge | 145:64910690c574 | 1057 | } |
AnnaBridge | 145:64910690c574 | 1058 | |
AnnaBridge | 145:64910690c574 | 1059 | /** |
AnnaBridge | 145:64910690c574 | 1060 | * @brief Set Memory burst transfer configuration. |
AnnaBridge | 145:64910690c574 | 1061 | * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer |
AnnaBridge | 145:64910690c574 | 1062 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1063 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1064 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1065 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1066 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1067 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1068 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1069 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1070 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1071 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1072 | * @param Mburst This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1073 | * @arg @ref LL_DMA_MBURST_SINGLE |
AnnaBridge | 145:64910690c574 | 1074 | * @arg @ref LL_DMA_MBURST_INC4 |
AnnaBridge | 145:64910690c574 | 1075 | * @arg @ref LL_DMA_MBURST_INC8 |
AnnaBridge | 145:64910690c574 | 1076 | * @arg @ref LL_DMA_MBURST_INC16 |
AnnaBridge | 145:64910690c574 | 1077 | * @retval None |
AnnaBridge | 145:64910690c574 | 1078 | */ |
AnnaBridge | 145:64910690c574 | 1079 | __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) |
AnnaBridge | 145:64910690c574 | 1080 | { |
AnnaBridge | 145:64910690c574 | 1081 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst); |
AnnaBridge | 145:64910690c574 | 1082 | } |
AnnaBridge | 145:64910690c574 | 1083 | |
AnnaBridge | 145:64910690c574 | 1084 | /** |
AnnaBridge | 145:64910690c574 | 1085 | * @brief Get Memory burst transfer configuration. |
AnnaBridge | 145:64910690c574 | 1086 | * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer |
AnnaBridge | 145:64910690c574 | 1087 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1088 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1089 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1090 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1091 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1092 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1093 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1094 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1095 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1096 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1097 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1098 | * @arg @ref LL_DMA_MBURST_SINGLE |
AnnaBridge | 145:64910690c574 | 1099 | * @arg @ref LL_DMA_MBURST_INC4 |
AnnaBridge | 145:64910690c574 | 1100 | * @arg @ref LL_DMA_MBURST_INC8 |
AnnaBridge | 145:64910690c574 | 1101 | * @arg @ref LL_DMA_MBURST_INC16 |
AnnaBridge | 145:64910690c574 | 1102 | */ |
AnnaBridge | 145:64910690c574 | 1103 | __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 1104 | { |
AnnaBridge | 145:64910690c574 | 1105 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST)); |
AnnaBridge | 145:64910690c574 | 1106 | } |
AnnaBridge | 145:64910690c574 | 1107 | |
AnnaBridge | 145:64910690c574 | 1108 | /** |
AnnaBridge | 145:64910690c574 | 1109 | * @brief Set Peripheral burst transfer configuration. |
AnnaBridge | 145:64910690c574 | 1110 | * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer |
AnnaBridge | 145:64910690c574 | 1111 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1112 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1113 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1114 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1115 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1116 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1117 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1118 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1119 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1120 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1121 | * @param Pburst This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1122 | * @arg @ref LL_DMA_PBURST_SINGLE |
AnnaBridge | 145:64910690c574 | 1123 | * @arg @ref LL_DMA_PBURST_INC4 |
AnnaBridge | 145:64910690c574 | 1124 | * @arg @ref LL_DMA_PBURST_INC8 |
AnnaBridge | 145:64910690c574 | 1125 | * @arg @ref LL_DMA_PBURST_INC16 |
AnnaBridge | 145:64910690c574 | 1126 | * @retval None |
AnnaBridge | 145:64910690c574 | 1127 | */ |
AnnaBridge | 145:64910690c574 | 1128 | __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) |
AnnaBridge | 145:64910690c574 | 1129 | { |
AnnaBridge | 145:64910690c574 | 1130 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst); |
AnnaBridge | 145:64910690c574 | 1131 | } |
AnnaBridge | 145:64910690c574 | 1132 | |
AnnaBridge | 145:64910690c574 | 1133 | /** |
AnnaBridge | 145:64910690c574 | 1134 | * @brief Get Peripheral burst transfer configuration. |
AnnaBridge | 145:64910690c574 | 1135 | * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer |
AnnaBridge | 145:64910690c574 | 1136 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1137 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1138 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1139 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1140 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1141 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1142 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1143 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1144 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1145 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1146 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1147 | * @arg @ref LL_DMA_PBURST_SINGLE |
AnnaBridge | 145:64910690c574 | 1148 | * @arg @ref LL_DMA_PBURST_INC4 |
AnnaBridge | 145:64910690c574 | 1149 | * @arg @ref LL_DMA_PBURST_INC8 |
AnnaBridge | 145:64910690c574 | 1150 | * @arg @ref LL_DMA_PBURST_INC16 |
AnnaBridge | 145:64910690c574 | 1151 | */ |
AnnaBridge | 145:64910690c574 | 1152 | __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 1153 | { |
AnnaBridge | 145:64910690c574 | 1154 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST)); |
AnnaBridge | 145:64910690c574 | 1155 | } |
AnnaBridge | 145:64910690c574 | 1156 | |
AnnaBridge | 145:64910690c574 | 1157 | /** |
AnnaBridge | 145:64910690c574 | 1158 | * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. |
AnnaBridge | 145:64910690c574 | 1159 | * @rmtoll CR CT LL_DMA_SetCurrentTargetMem |
AnnaBridge | 145:64910690c574 | 1160 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1161 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1162 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1163 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1164 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1165 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1166 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1167 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1168 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1169 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1170 | * @param CurrentMemory This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1171 | * @arg @ref LL_DMA_CURRENTTARGETMEM0 |
AnnaBridge | 145:64910690c574 | 1172 | * @arg @ref LL_DMA_CURRENTTARGETMEM1 |
AnnaBridge | 145:64910690c574 | 1173 | * @retval None |
AnnaBridge | 145:64910690c574 | 1174 | */ |
AnnaBridge | 145:64910690c574 | 1175 | __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) |
AnnaBridge | 145:64910690c574 | 1176 | { |
AnnaBridge | 145:64910690c574 | 1177 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory); |
AnnaBridge | 145:64910690c574 | 1178 | } |
AnnaBridge | 145:64910690c574 | 1179 | |
AnnaBridge | 145:64910690c574 | 1180 | /** |
AnnaBridge | 145:64910690c574 | 1181 | * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. |
AnnaBridge | 145:64910690c574 | 1182 | * @rmtoll CR CT LL_DMA_GetCurrentTargetMem |
AnnaBridge | 145:64910690c574 | 1183 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1184 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1185 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1186 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1187 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1188 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1189 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1190 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1191 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1192 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1193 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1194 | * @arg @ref LL_DMA_CURRENTTARGETMEM0 |
AnnaBridge | 145:64910690c574 | 1195 | * @arg @ref LL_DMA_CURRENTTARGETMEM1 |
AnnaBridge | 145:64910690c574 | 1196 | */ |
AnnaBridge | 145:64910690c574 | 1197 | __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 1198 | { |
AnnaBridge | 145:64910690c574 | 1199 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT)); |
AnnaBridge | 145:64910690c574 | 1200 | } |
AnnaBridge | 145:64910690c574 | 1201 | |
AnnaBridge | 145:64910690c574 | 1202 | /** |
AnnaBridge | 145:64910690c574 | 1203 | * @brief Enable the double buffer mode. |
AnnaBridge | 145:64910690c574 | 1204 | * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode |
AnnaBridge | 145:64910690c574 | 1205 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1206 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1207 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1208 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1209 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1210 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1211 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1212 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1213 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1214 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1215 | * @retval None |
AnnaBridge | 145:64910690c574 | 1216 | */ |
AnnaBridge | 145:64910690c574 | 1217 | __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 1218 | { |
AnnaBridge | 145:64910690c574 | 1219 | SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM); |
AnnaBridge | 145:64910690c574 | 1220 | } |
AnnaBridge | 145:64910690c574 | 1221 | |
AnnaBridge | 145:64910690c574 | 1222 | /** |
AnnaBridge | 145:64910690c574 | 1223 | * @brief Disable the double buffer mode. |
AnnaBridge | 145:64910690c574 | 1224 | * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode |
AnnaBridge | 145:64910690c574 | 1225 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1226 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1227 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1228 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1229 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1230 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1231 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1232 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1233 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1234 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1235 | * @retval None |
AnnaBridge | 145:64910690c574 | 1236 | */ |
AnnaBridge | 145:64910690c574 | 1237 | __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 1238 | { |
AnnaBridge | 145:64910690c574 | 1239 | CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM); |
AnnaBridge | 145:64910690c574 | 1240 | } |
AnnaBridge | 145:64910690c574 | 1241 | |
AnnaBridge | 145:64910690c574 | 1242 | /** |
AnnaBridge | 145:64910690c574 | 1243 | * @brief Get FIFO status. |
AnnaBridge | 145:64910690c574 | 1244 | * @rmtoll FCR FS LL_DMA_GetFIFOStatus |
AnnaBridge | 145:64910690c574 | 1245 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1246 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1247 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1248 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1249 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1250 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1251 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1252 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1253 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1254 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1255 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1256 | * @arg @ref LL_DMA_FIFOSTATUS_0_25 |
AnnaBridge | 145:64910690c574 | 1257 | * @arg @ref LL_DMA_FIFOSTATUS_25_50 |
AnnaBridge | 145:64910690c574 | 1258 | * @arg @ref LL_DMA_FIFOSTATUS_50_75 |
AnnaBridge | 145:64910690c574 | 1259 | * @arg @ref LL_DMA_FIFOSTATUS_75_100 |
AnnaBridge | 145:64910690c574 | 1260 | * @arg @ref LL_DMA_FIFOSTATUS_EMPTY |
AnnaBridge | 145:64910690c574 | 1261 | * @arg @ref LL_DMA_FIFOSTATUS_FULL |
AnnaBridge | 145:64910690c574 | 1262 | */ |
AnnaBridge | 145:64910690c574 | 1263 | __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 1264 | { |
AnnaBridge | 145:64910690c574 | 1265 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS)); |
AnnaBridge | 145:64910690c574 | 1266 | } |
AnnaBridge | 145:64910690c574 | 1267 | |
AnnaBridge | 145:64910690c574 | 1268 | /** |
AnnaBridge | 145:64910690c574 | 1269 | * @brief Disable Fifo mode. |
AnnaBridge | 145:64910690c574 | 1270 | * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode |
AnnaBridge | 145:64910690c574 | 1271 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1272 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1273 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1274 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1275 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1276 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1277 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1278 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1279 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1280 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1281 | * @retval None |
AnnaBridge | 145:64910690c574 | 1282 | */ |
AnnaBridge | 145:64910690c574 | 1283 | __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 1284 | { |
AnnaBridge | 145:64910690c574 | 1285 | CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS); |
AnnaBridge | 145:64910690c574 | 1286 | } |
AnnaBridge | 145:64910690c574 | 1287 | |
AnnaBridge | 145:64910690c574 | 1288 | /** |
AnnaBridge | 145:64910690c574 | 1289 | * @brief Enable Fifo mode. |
AnnaBridge | 145:64910690c574 | 1290 | * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode |
AnnaBridge | 145:64910690c574 | 1291 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1292 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1293 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1294 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1295 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1296 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1297 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1298 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1299 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1300 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1301 | * @retval None |
AnnaBridge | 145:64910690c574 | 1302 | */ |
AnnaBridge | 145:64910690c574 | 1303 | __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 1304 | { |
AnnaBridge | 145:64910690c574 | 1305 | SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS); |
AnnaBridge | 145:64910690c574 | 1306 | } |
AnnaBridge | 145:64910690c574 | 1307 | |
AnnaBridge | 145:64910690c574 | 1308 | /** |
AnnaBridge | 145:64910690c574 | 1309 | * @brief Select FIFO threshold. |
AnnaBridge | 145:64910690c574 | 1310 | * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold |
AnnaBridge | 145:64910690c574 | 1311 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1312 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1313 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1314 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1315 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1316 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1317 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1318 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1319 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1320 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1321 | * @param Threshold This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1322 | * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 |
AnnaBridge | 145:64910690c574 | 1323 | * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 |
AnnaBridge | 145:64910690c574 | 1324 | * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 |
AnnaBridge | 145:64910690c574 | 1325 | * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL |
AnnaBridge | 145:64910690c574 | 1326 | * @retval None |
AnnaBridge | 145:64910690c574 | 1327 | */ |
AnnaBridge | 145:64910690c574 | 1328 | __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) |
AnnaBridge | 145:64910690c574 | 1329 | { |
AnnaBridge | 145:64910690c574 | 1330 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold); |
AnnaBridge | 145:64910690c574 | 1331 | } |
AnnaBridge | 145:64910690c574 | 1332 | |
AnnaBridge | 145:64910690c574 | 1333 | /** |
AnnaBridge | 145:64910690c574 | 1334 | * @brief Get FIFO threshold. |
AnnaBridge | 145:64910690c574 | 1335 | * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold |
AnnaBridge | 145:64910690c574 | 1336 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1337 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1338 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1339 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1340 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1341 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1342 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1343 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1344 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1345 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1346 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1347 | * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 |
AnnaBridge | 145:64910690c574 | 1348 | * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 |
AnnaBridge | 145:64910690c574 | 1349 | * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 |
AnnaBridge | 145:64910690c574 | 1350 | * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL |
AnnaBridge | 145:64910690c574 | 1351 | */ |
AnnaBridge | 145:64910690c574 | 1352 | __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 1353 | { |
AnnaBridge | 145:64910690c574 | 1354 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH)); |
AnnaBridge | 145:64910690c574 | 1355 | } |
AnnaBridge | 145:64910690c574 | 1356 | |
AnnaBridge | 145:64910690c574 | 1357 | /** |
AnnaBridge | 145:64910690c574 | 1358 | * @brief Configure the FIFO . |
AnnaBridge | 145:64910690c574 | 1359 | * @rmtoll FCR FTH LL_DMA_ConfigFifo\n |
AnnaBridge | 145:64910690c574 | 1360 | * FCR DMDIS LL_DMA_ConfigFifo |
AnnaBridge | 145:64910690c574 | 1361 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1362 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1363 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1364 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1365 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1366 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1367 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1368 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1369 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1370 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1371 | * @param FifoMode This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1372 | * @arg @ref LL_DMA_FIFOMODE_ENABLE |
AnnaBridge | 145:64910690c574 | 1373 | * @arg @ref LL_DMA_FIFOMODE_DISABLE |
AnnaBridge | 145:64910690c574 | 1374 | * @param FifoThreshold This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1375 | * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 |
AnnaBridge | 145:64910690c574 | 1376 | * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 |
AnnaBridge | 145:64910690c574 | 1377 | * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 |
AnnaBridge | 145:64910690c574 | 1378 | * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL |
AnnaBridge | 145:64910690c574 | 1379 | * @retval None |
AnnaBridge | 145:64910690c574 | 1380 | */ |
AnnaBridge | 145:64910690c574 | 1381 | __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) |
AnnaBridge | 145:64910690c574 | 1382 | { |
AnnaBridge | 145:64910690c574 | 1383 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold); |
AnnaBridge | 145:64910690c574 | 1384 | } |
AnnaBridge | 145:64910690c574 | 1385 | |
AnnaBridge | 145:64910690c574 | 1386 | /** |
AnnaBridge | 145:64910690c574 | 1387 | * @brief Configure the Source and Destination addresses. |
AnnaBridge | 145:64910690c574 | 1388 | * @note This API must not be called when the DMA stream is enabled. |
AnnaBridge | 145:64910690c574 | 1389 | * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n |
AnnaBridge | 145:64910690c574 | 1390 | * PAR PA LL_DMA_ConfigAddresses |
AnnaBridge | 145:64910690c574 | 1391 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1392 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1393 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1394 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1395 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1396 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1397 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1398 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1399 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1400 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1401 | * @param SrcAddress Between 0 to 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1402 | * @param DstAddress Between 0 to 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1403 | * @param Direction This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1404 | * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY |
AnnaBridge | 145:64910690c574 | 1405 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH |
AnnaBridge | 145:64910690c574 | 1406 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY |
AnnaBridge | 145:64910690c574 | 1407 | * @retval None |
AnnaBridge | 145:64910690c574 | 1408 | */ |
AnnaBridge | 145:64910690c574 | 1409 | __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) |
AnnaBridge | 145:64910690c574 | 1410 | { |
AnnaBridge | 145:64910690c574 | 1411 | /* Direction Memory to Periph */ |
AnnaBridge | 145:64910690c574 | 1412 | if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) |
AnnaBridge | 145:64910690c574 | 1413 | { |
AnnaBridge | 145:64910690c574 | 1414 | WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress); |
AnnaBridge | 145:64910690c574 | 1415 | WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress); |
AnnaBridge | 145:64910690c574 | 1416 | } |
AnnaBridge | 145:64910690c574 | 1417 | /* Direction Periph to Memory and Memory to Memory */ |
AnnaBridge | 145:64910690c574 | 1418 | else |
AnnaBridge | 145:64910690c574 | 1419 | { |
AnnaBridge | 145:64910690c574 | 1420 | WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress); |
AnnaBridge | 145:64910690c574 | 1421 | WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress); |
AnnaBridge | 145:64910690c574 | 1422 | } |
AnnaBridge | 145:64910690c574 | 1423 | } |
AnnaBridge | 145:64910690c574 | 1424 | |
AnnaBridge | 145:64910690c574 | 1425 | /** |
AnnaBridge | 145:64910690c574 | 1426 | * @brief Set the Memory address. |
AnnaBridge | 145:64910690c574 | 1427 | * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress |
AnnaBridge | 145:64910690c574 | 1428 | * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. |
AnnaBridge | 145:64910690c574 | 1429 | * @note This API must not be called when the DMA channel is enabled. |
AnnaBridge | 145:64910690c574 | 1430 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1431 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1432 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1433 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1434 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1435 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1436 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1437 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1438 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1439 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1440 | * @param MemoryAddress Between 0 to 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1441 | * @retval None |
AnnaBridge | 145:64910690c574 | 1442 | */ |
AnnaBridge | 145:64910690c574 | 1443 | __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) |
AnnaBridge | 145:64910690c574 | 1444 | { |
AnnaBridge | 145:64910690c574 | 1445 | WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress); |
AnnaBridge | 145:64910690c574 | 1446 | } |
AnnaBridge | 145:64910690c574 | 1447 | |
AnnaBridge | 145:64910690c574 | 1448 | /** |
AnnaBridge | 145:64910690c574 | 1449 | * @brief Set the Peripheral address. |
AnnaBridge | 145:64910690c574 | 1450 | * @rmtoll PAR PA LL_DMA_SetPeriphAddress |
AnnaBridge | 145:64910690c574 | 1451 | * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. |
AnnaBridge | 145:64910690c574 | 1452 | * @note This API must not be called when the DMA channel is enabled. |
AnnaBridge | 145:64910690c574 | 1453 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1454 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1455 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1456 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1457 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1458 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1459 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1460 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1461 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1462 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1463 | * @param PeriphAddress Between 0 to 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1464 | * @retval None |
AnnaBridge | 145:64910690c574 | 1465 | */ |
AnnaBridge | 145:64910690c574 | 1466 | __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress) |
AnnaBridge | 145:64910690c574 | 1467 | { |
AnnaBridge | 145:64910690c574 | 1468 | WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress); |
AnnaBridge | 145:64910690c574 | 1469 | } |
AnnaBridge | 145:64910690c574 | 1470 | |
AnnaBridge | 145:64910690c574 | 1471 | /** |
AnnaBridge | 145:64910690c574 | 1472 | * @brief Get the Memory address. |
AnnaBridge | 145:64910690c574 | 1473 | * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress |
AnnaBridge | 145:64910690c574 | 1474 | * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. |
AnnaBridge | 145:64910690c574 | 1475 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1476 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1477 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1478 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1479 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1480 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1481 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1482 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1483 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1484 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1485 | * @retval Between 0 to 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1486 | */ |
AnnaBridge | 145:64910690c574 | 1487 | __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 1488 | { |
AnnaBridge | 145:64910690c574 | 1489 | return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR)); |
AnnaBridge | 145:64910690c574 | 1490 | } |
AnnaBridge | 145:64910690c574 | 1491 | |
AnnaBridge | 145:64910690c574 | 1492 | /** |
AnnaBridge | 145:64910690c574 | 1493 | * @brief Get the Peripheral address. |
AnnaBridge | 145:64910690c574 | 1494 | * @rmtoll PAR PA LL_DMA_GetPeriphAddress |
AnnaBridge | 145:64910690c574 | 1495 | * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. |
AnnaBridge | 145:64910690c574 | 1496 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1497 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1498 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1499 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1500 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1501 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1502 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1503 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1504 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1505 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1506 | * @retval Between 0 to 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1507 | */ |
AnnaBridge | 145:64910690c574 | 1508 | __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 1509 | { |
AnnaBridge | 145:64910690c574 | 1510 | return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR)); |
AnnaBridge | 145:64910690c574 | 1511 | } |
AnnaBridge | 145:64910690c574 | 1512 | |
AnnaBridge | 145:64910690c574 | 1513 | /** |
AnnaBridge | 145:64910690c574 | 1514 | * @brief Set the Memory to Memory Source address. |
AnnaBridge | 145:64910690c574 | 1515 | * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress |
AnnaBridge | 145:64910690c574 | 1516 | * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. |
AnnaBridge | 145:64910690c574 | 1517 | * @note This API must not be called when the DMA channel is enabled. |
AnnaBridge | 145:64910690c574 | 1518 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1519 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1520 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1521 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1522 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1523 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1524 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1525 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1526 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1527 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1528 | * @param MemoryAddress Between 0 to 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1529 | * @retval None |
AnnaBridge | 145:64910690c574 | 1530 | */ |
AnnaBridge | 145:64910690c574 | 1531 | __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) |
AnnaBridge | 145:64910690c574 | 1532 | { |
AnnaBridge | 145:64910690c574 | 1533 | WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress); |
AnnaBridge | 145:64910690c574 | 1534 | } |
AnnaBridge | 145:64910690c574 | 1535 | |
AnnaBridge | 145:64910690c574 | 1536 | /** |
AnnaBridge | 145:64910690c574 | 1537 | * @brief Set the Memory to Memory Destination address. |
AnnaBridge | 145:64910690c574 | 1538 | * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress |
AnnaBridge | 145:64910690c574 | 1539 | * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. |
AnnaBridge | 145:64910690c574 | 1540 | * @note This API must not be called when the DMA channel is enabled. |
AnnaBridge | 145:64910690c574 | 1541 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1542 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1543 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1544 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1545 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1546 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1547 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1548 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1549 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1550 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1551 | * @param MemoryAddress Between 0 to 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1552 | * @retval None |
AnnaBridge | 145:64910690c574 | 1553 | */ |
AnnaBridge | 145:64910690c574 | 1554 | __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) |
AnnaBridge | 145:64910690c574 | 1555 | { |
AnnaBridge | 145:64910690c574 | 1556 | WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress); |
AnnaBridge | 145:64910690c574 | 1557 | } |
AnnaBridge | 145:64910690c574 | 1558 | |
AnnaBridge | 145:64910690c574 | 1559 | /** |
AnnaBridge | 145:64910690c574 | 1560 | * @brief Get the Memory to Memory Source address. |
AnnaBridge | 145:64910690c574 | 1561 | * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress |
AnnaBridge | 145:64910690c574 | 1562 | * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. |
AnnaBridge | 145:64910690c574 | 1563 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1564 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1565 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1566 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1567 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1568 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1569 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1570 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1571 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1572 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1573 | * @retval Between 0 to 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1574 | */ |
AnnaBridge | 145:64910690c574 | 1575 | __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 1576 | { |
AnnaBridge | 145:64910690c574 | 1577 | return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR)); |
AnnaBridge | 145:64910690c574 | 1578 | } |
AnnaBridge | 145:64910690c574 | 1579 | |
AnnaBridge | 145:64910690c574 | 1580 | /** |
AnnaBridge | 145:64910690c574 | 1581 | * @brief Get the Memory to Memory Destination address. |
AnnaBridge | 145:64910690c574 | 1582 | * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress |
AnnaBridge | 145:64910690c574 | 1583 | * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. |
AnnaBridge | 145:64910690c574 | 1584 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1585 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1586 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1587 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1588 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1589 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1590 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1591 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1592 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1593 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1594 | * @retval Between 0 to 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1595 | */ |
AnnaBridge | 145:64910690c574 | 1596 | __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 1597 | { |
AnnaBridge | 145:64910690c574 | 1598 | return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR)); |
AnnaBridge | 145:64910690c574 | 1599 | } |
AnnaBridge | 145:64910690c574 | 1600 | |
AnnaBridge | 145:64910690c574 | 1601 | /** |
AnnaBridge | 145:64910690c574 | 1602 | * @brief Set Memory 1 address (used in case of Double buffer mode). |
AnnaBridge | 145:64910690c574 | 1603 | * @rmtoll M1AR M1A LL_DMA_SetMemory1Address |
AnnaBridge | 145:64910690c574 | 1604 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1605 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1606 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1607 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1608 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1609 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1610 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1611 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1612 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1613 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1614 | * @param Address Between 0 to 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1615 | * @retval None |
AnnaBridge | 145:64910690c574 | 1616 | */ |
AnnaBridge | 145:64910690c574 | 1617 | __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) |
AnnaBridge | 145:64910690c574 | 1618 | { |
AnnaBridge | 145:64910690c574 | 1619 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address); |
AnnaBridge | 145:64910690c574 | 1620 | } |
AnnaBridge | 145:64910690c574 | 1621 | |
AnnaBridge | 145:64910690c574 | 1622 | /** |
AnnaBridge | 145:64910690c574 | 1623 | * @brief Get Memory 1 address (used in case of Double buffer mode). |
AnnaBridge | 145:64910690c574 | 1624 | * @rmtoll M1AR M1A LL_DMA_GetMemory1Address |
AnnaBridge | 145:64910690c574 | 1625 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1626 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1627 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 1628 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 1629 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 1630 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 1631 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 1632 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 1633 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 1634 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 1635 | * @retval Between 0 to 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1636 | */ |
AnnaBridge | 145:64910690c574 | 1637 | __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 1638 | { |
AnnaBridge | 145:64910690c574 | 1639 | return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR); |
AnnaBridge | 145:64910690c574 | 1640 | } |
AnnaBridge | 145:64910690c574 | 1641 | |
AnnaBridge | 145:64910690c574 | 1642 | /** |
AnnaBridge | 145:64910690c574 | 1643 | * @} |
AnnaBridge | 145:64910690c574 | 1644 | */ |
AnnaBridge | 145:64910690c574 | 1645 | |
AnnaBridge | 145:64910690c574 | 1646 | /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management |
AnnaBridge | 145:64910690c574 | 1647 | * @{ |
AnnaBridge | 145:64910690c574 | 1648 | */ |
AnnaBridge | 145:64910690c574 | 1649 | |
AnnaBridge | 145:64910690c574 | 1650 | /** |
AnnaBridge | 145:64910690c574 | 1651 | * @brief Get Stream 0 half transfer flag. |
AnnaBridge | 145:64910690c574 | 1652 | * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0 |
AnnaBridge | 145:64910690c574 | 1653 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1654 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1655 | */ |
AnnaBridge | 145:64910690c574 | 1656 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1657 | { |
AnnaBridge | 145:64910690c574 | 1658 | return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0)); |
AnnaBridge | 145:64910690c574 | 1659 | } |
AnnaBridge | 145:64910690c574 | 1660 | |
AnnaBridge | 145:64910690c574 | 1661 | /** |
AnnaBridge | 145:64910690c574 | 1662 | * @brief Get Stream 1 half transfer flag. |
AnnaBridge | 145:64910690c574 | 1663 | * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1 |
AnnaBridge | 145:64910690c574 | 1664 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1665 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1666 | */ |
AnnaBridge | 145:64910690c574 | 1667 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1668 | { |
AnnaBridge | 145:64910690c574 | 1669 | return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1)); |
AnnaBridge | 145:64910690c574 | 1670 | } |
AnnaBridge | 145:64910690c574 | 1671 | |
AnnaBridge | 145:64910690c574 | 1672 | /** |
AnnaBridge | 145:64910690c574 | 1673 | * @brief Get Stream 2 half transfer flag. |
AnnaBridge | 145:64910690c574 | 1674 | * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2 |
AnnaBridge | 145:64910690c574 | 1675 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1676 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1677 | */ |
AnnaBridge | 145:64910690c574 | 1678 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1679 | { |
AnnaBridge | 145:64910690c574 | 1680 | return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2)); |
AnnaBridge | 145:64910690c574 | 1681 | } |
AnnaBridge | 145:64910690c574 | 1682 | |
AnnaBridge | 145:64910690c574 | 1683 | /** |
AnnaBridge | 145:64910690c574 | 1684 | * @brief Get Stream 3 half transfer flag. |
AnnaBridge | 145:64910690c574 | 1685 | * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3 |
AnnaBridge | 145:64910690c574 | 1686 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1687 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1688 | */ |
AnnaBridge | 145:64910690c574 | 1689 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1690 | { |
AnnaBridge | 145:64910690c574 | 1691 | return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3)); |
AnnaBridge | 145:64910690c574 | 1692 | } |
AnnaBridge | 145:64910690c574 | 1693 | |
AnnaBridge | 145:64910690c574 | 1694 | /** |
AnnaBridge | 145:64910690c574 | 1695 | * @brief Get Stream 4 half transfer flag. |
AnnaBridge | 145:64910690c574 | 1696 | * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4 |
AnnaBridge | 145:64910690c574 | 1697 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1698 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1699 | */ |
AnnaBridge | 145:64910690c574 | 1700 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1701 | { |
AnnaBridge | 145:64910690c574 | 1702 | return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4)); |
AnnaBridge | 145:64910690c574 | 1703 | } |
AnnaBridge | 145:64910690c574 | 1704 | |
AnnaBridge | 145:64910690c574 | 1705 | /** |
AnnaBridge | 145:64910690c574 | 1706 | * @brief Get Stream 5 half transfer flag. |
AnnaBridge | 145:64910690c574 | 1707 | * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5 |
AnnaBridge | 145:64910690c574 | 1708 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1709 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1710 | */ |
AnnaBridge | 145:64910690c574 | 1711 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1712 | { |
AnnaBridge | 145:64910690c574 | 1713 | return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5)); |
AnnaBridge | 145:64910690c574 | 1714 | } |
AnnaBridge | 145:64910690c574 | 1715 | |
AnnaBridge | 145:64910690c574 | 1716 | /** |
AnnaBridge | 145:64910690c574 | 1717 | * @brief Get Stream 6 half transfer flag. |
AnnaBridge | 145:64910690c574 | 1718 | * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6 |
AnnaBridge | 145:64910690c574 | 1719 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1720 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1721 | */ |
AnnaBridge | 145:64910690c574 | 1722 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1723 | { |
AnnaBridge | 145:64910690c574 | 1724 | return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6)); |
AnnaBridge | 145:64910690c574 | 1725 | } |
AnnaBridge | 145:64910690c574 | 1726 | |
AnnaBridge | 145:64910690c574 | 1727 | /** |
AnnaBridge | 145:64910690c574 | 1728 | * @brief Get Stream 7 half transfer flag. |
AnnaBridge | 145:64910690c574 | 1729 | * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7 |
AnnaBridge | 145:64910690c574 | 1730 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1731 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1732 | */ |
AnnaBridge | 145:64910690c574 | 1733 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1734 | { |
AnnaBridge | 145:64910690c574 | 1735 | return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7)); |
AnnaBridge | 145:64910690c574 | 1736 | } |
AnnaBridge | 145:64910690c574 | 1737 | |
AnnaBridge | 145:64910690c574 | 1738 | /** |
AnnaBridge | 145:64910690c574 | 1739 | * @brief Get Stream 0 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 1740 | * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0 |
AnnaBridge | 145:64910690c574 | 1741 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1742 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1743 | */ |
AnnaBridge | 145:64910690c574 | 1744 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1745 | { |
AnnaBridge | 145:64910690c574 | 1746 | return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0)); |
AnnaBridge | 145:64910690c574 | 1747 | } |
AnnaBridge | 145:64910690c574 | 1748 | |
AnnaBridge | 145:64910690c574 | 1749 | /** |
AnnaBridge | 145:64910690c574 | 1750 | * @brief Get Stream 1 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 1751 | * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1 |
AnnaBridge | 145:64910690c574 | 1752 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1753 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1754 | */ |
AnnaBridge | 145:64910690c574 | 1755 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1756 | { |
AnnaBridge | 145:64910690c574 | 1757 | return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1)); |
AnnaBridge | 145:64910690c574 | 1758 | } |
AnnaBridge | 145:64910690c574 | 1759 | |
AnnaBridge | 145:64910690c574 | 1760 | /** |
AnnaBridge | 145:64910690c574 | 1761 | * @brief Get Stream 2 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 1762 | * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2 |
AnnaBridge | 145:64910690c574 | 1763 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1764 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1765 | */ |
AnnaBridge | 145:64910690c574 | 1766 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1767 | { |
AnnaBridge | 145:64910690c574 | 1768 | return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2)); |
AnnaBridge | 145:64910690c574 | 1769 | } |
AnnaBridge | 145:64910690c574 | 1770 | |
AnnaBridge | 145:64910690c574 | 1771 | /** |
AnnaBridge | 145:64910690c574 | 1772 | * @brief Get Stream 3 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 1773 | * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3 |
AnnaBridge | 145:64910690c574 | 1774 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1775 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1776 | */ |
AnnaBridge | 145:64910690c574 | 1777 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1778 | { |
AnnaBridge | 145:64910690c574 | 1779 | return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3)); |
AnnaBridge | 145:64910690c574 | 1780 | } |
AnnaBridge | 145:64910690c574 | 1781 | |
AnnaBridge | 145:64910690c574 | 1782 | /** |
AnnaBridge | 145:64910690c574 | 1783 | * @brief Get Stream 4 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 1784 | * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4 |
AnnaBridge | 145:64910690c574 | 1785 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1786 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1787 | */ |
AnnaBridge | 145:64910690c574 | 1788 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1789 | { |
AnnaBridge | 145:64910690c574 | 1790 | return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4)); |
AnnaBridge | 145:64910690c574 | 1791 | } |
AnnaBridge | 145:64910690c574 | 1792 | |
AnnaBridge | 145:64910690c574 | 1793 | /** |
AnnaBridge | 145:64910690c574 | 1794 | * @brief Get Stream 5 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 1795 | * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5 |
AnnaBridge | 145:64910690c574 | 1796 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1797 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1798 | */ |
AnnaBridge | 145:64910690c574 | 1799 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1800 | { |
AnnaBridge | 145:64910690c574 | 1801 | return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5)); |
AnnaBridge | 145:64910690c574 | 1802 | } |
AnnaBridge | 145:64910690c574 | 1803 | |
AnnaBridge | 145:64910690c574 | 1804 | /** |
AnnaBridge | 145:64910690c574 | 1805 | * @brief Get Stream 6 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 1806 | * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6 |
AnnaBridge | 145:64910690c574 | 1807 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1808 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1809 | */ |
AnnaBridge | 145:64910690c574 | 1810 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1811 | { |
AnnaBridge | 145:64910690c574 | 1812 | return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6)); |
AnnaBridge | 145:64910690c574 | 1813 | } |
AnnaBridge | 145:64910690c574 | 1814 | |
AnnaBridge | 145:64910690c574 | 1815 | /** |
AnnaBridge | 145:64910690c574 | 1816 | * @brief Get Stream 7 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 1817 | * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7 |
AnnaBridge | 145:64910690c574 | 1818 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1819 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1820 | */ |
AnnaBridge | 145:64910690c574 | 1821 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1822 | { |
AnnaBridge | 145:64910690c574 | 1823 | return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7)); |
AnnaBridge | 145:64910690c574 | 1824 | } |
AnnaBridge | 145:64910690c574 | 1825 | |
AnnaBridge | 145:64910690c574 | 1826 | /** |
AnnaBridge | 145:64910690c574 | 1827 | * @brief Get Stream 0 transfer error flag. |
AnnaBridge | 145:64910690c574 | 1828 | * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0 |
AnnaBridge | 145:64910690c574 | 1829 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1830 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1831 | */ |
AnnaBridge | 145:64910690c574 | 1832 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1833 | { |
AnnaBridge | 145:64910690c574 | 1834 | return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0)); |
AnnaBridge | 145:64910690c574 | 1835 | } |
AnnaBridge | 145:64910690c574 | 1836 | |
AnnaBridge | 145:64910690c574 | 1837 | /** |
AnnaBridge | 145:64910690c574 | 1838 | * @brief Get Stream 1 transfer error flag. |
AnnaBridge | 145:64910690c574 | 1839 | * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1 |
AnnaBridge | 145:64910690c574 | 1840 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1841 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1842 | */ |
AnnaBridge | 145:64910690c574 | 1843 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1844 | { |
AnnaBridge | 145:64910690c574 | 1845 | return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1)); |
AnnaBridge | 145:64910690c574 | 1846 | } |
AnnaBridge | 145:64910690c574 | 1847 | |
AnnaBridge | 145:64910690c574 | 1848 | /** |
AnnaBridge | 145:64910690c574 | 1849 | * @brief Get Stream 2 transfer error flag. |
AnnaBridge | 145:64910690c574 | 1850 | * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2 |
AnnaBridge | 145:64910690c574 | 1851 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1852 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1853 | */ |
AnnaBridge | 145:64910690c574 | 1854 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1855 | { |
AnnaBridge | 145:64910690c574 | 1856 | return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2)); |
AnnaBridge | 145:64910690c574 | 1857 | } |
AnnaBridge | 145:64910690c574 | 1858 | |
AnnaBridge | 145:64910690c574 | 1859 | /** |
AnnaBridge | 145:64910690c574 | 1860 | * @brief Get Stream 3 transfer error flag. |
AnnaBridge | 145:64910690c574 | 1861 | * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3 |
AnnaBridge | 145:64910690c574 | 1862 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1863 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1864 | */ |
AnnaBridge | 145:64910690c574 | 1865 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1866 | { |
AnnaBridge | 145:64910690c574 | 1867 | return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3)); |
AnnaBridge | 145:64910690c574 | 1868 | } |
AnnaBridge | 145:64910690c574 | 1869 | |
AnnaBridge | 145:64910690c574 | 1870 | /** |
AnnaBridge | 145:64910690c574 | 1871 | * @brief Get Stream 4 transfer error flag. |
AnnaBridge | 145:64910690c574 | 1872 | * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4 |
AnnaBridge | 145:64910690c574 | 1873 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1874 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1875 | */ |
AnnaBridge | 145:64910690c574 | 1876 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1877 | { |
AnnaBridge | 145:64910690c574 | 1878 | return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4)); |
AnnaBridge | 145:64910690c574 | 1879 | } |
AnnaBridge | 145:64910690c574 | 1880 | |
AnnaBridge | 145:64910690c574 | 1881 | /** |
AnnaBridge | 145:64910690c574 | 1882 | * @brief Get Stream 5 transfer error flag. |
AnnaBridge | 145:64910690c574 | 1883 | * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5 |
AnnaBridge | 145:64910690c574 | 1884 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1885 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1886 | */ |
AnnaBridge | 145:64910690c574 | 1887 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1888 | { |
AnnaBridge | 145:64910690c574 | 1889 | return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5)); |
AnnaBridge | 145:64910690c574 | 1890 | } |
AnnaBridge | 145:64910690c574 | 1891 | |
AnnaBridge | 145:64910690c574 | 1892 | /** |
AnnaBridge | 145:64910690c574 | 1893 | * @brief Get Stream 6 transfer error flag. |
AnnaBridge | 145:64910690c574 | 1894 | * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6 |
AnnaBridge | 145:64910690c574 | 1895 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1896 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1897 | */ |
AnnaBridge | 145:64910690c574 | 1898 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1899 | { |
AnnaBridge | 145:64910690c574 | 1900 | return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6)); |
AnnaBridge | 145:64910690c574 | 1901 | } |
AnnaBridge | 145:64910690c574 | 1902 | |
AnnaBridge | 145:64910690c574 | 1903 | /** |
AnnaBridge | 145:64910690c574 | 1904 | * @brief Get Stream 7 transfer error flag. |
AnnaBridge | 145:64910690c574 | 1905 | * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7 |
AnnaBridge | 145:64910690c574 | 1906 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1907 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1908 | */ |
AnnaBridge | 145:64910690c574 | 1909 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1910 | { |
AnnaBridge | 145:64910690c574 | 1911 | return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7)); |
AnnaBridge | 145:64910690c574 | 1912 | } |
AnnaBridge | 145:64910690c574 | 1913 | |
AnnaBridge | 145:64910690c574 | 1914 | /** |
AnnaBridge | 145:64910690c574 | 1915 | * @brief Get Stream 0 direct mode error flag. |
AnnaBridge | 145:64910690c574 | 1916 | * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0 |
AnnaBridge | 145:64910690c574 | 1917 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1918 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1919 | */ |
AnnaBridge | 145:64910690c574 | 1920 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1921 | { |
AnnaBridge | 145:64910690c574 | 1922 | return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0)); |
AnnaBridge | 145:64910690c574 | 1923 | } |
AnnaBridge | 145:64910690c574 | 1924 | |
AnnaBridge | 145:64910690c574 | 1925 | /** |
AnnaBridge | 145:64910690c574 | 1926 | * @brief Get Stream 1 direct mode error flag. |
AnnaBridge | 145:64910690c574 | 1927 | * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1 |
AnnaBridge | 145:64910690c574 | 1928 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1929 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1930 | */ |
AnnaBridge | 145:64910690c574 | 1931 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1932 | { |
AnnaBridge | 145:64910690c574 | 1933 | return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1)); |
AnnaBridge | 145:64910690c574 | 1934 | } |
AnnaBridge | 145:64910690c574 | 1935 | |
AnnaBridge | 145:64910690c574 | 1936 | /** |
AnnaBridge | 145:64910690c574 | 1937 | * @brief Get Stream 2 direct mode error flag. |
AnnaBridge | 145:64910690c574 | 1938 | * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2 |
AnnaBridge | 145:64910690c574 | 1939 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1940 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1941 | */ |
AnnaBridge | 145:64910690c574 | 1942 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1943 | { |
AnnaBridge | 145:64910690c574 | 1944 | return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2)); |
AnnaBridge | 145:64910690c574 | 1945 | } |
AnnaBridge | 145:64910690c574 | 1946 | |
AnnaBridge | 145:64910690c574 | 1947 | /** |
AnnaBridge | 145:64910690c574 | 1948 | * @brief Get Stream 3 direct mode error flag. |
AnnaBridge | 145:64910690c574 | 1949 | * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3 |
AnnaBridge | 145:64910690c574 | 1950 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1951 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1952 | */ |
AnnaBridge | 145:64910690c574 | 1953 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1954 | { |
AnnaBridge | 145:64910690c574 | 1955 | return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3)); |
AnnaBridge | 145:64910690c574 | 1956 | } |
AnnaBridge | 145:64910690c574 | 1957 | |
AnnaBridge | 145:64910690c574 | 1958 | /** |
AnnaBridge | 145:64910690c574 | 1959 | * @brief Get Stream 4 direct mode error flag. |
AnnaBridge | 145:64910690c574 | 1960 | * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4 |
AnnaBridge | 145:64910690c574 | 1961 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1962 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1963 | */ |
AnnaBridge | 145:64910690c574 | 1964 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1965 | { |
AnnaBridge | 145:64910690c574 | 1966 | return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4)); |
AnnaBridge | 145:64910690c574 | 1967 | } |
AnnaBridge | 145:64910690c574 | 1968 | |
AnnaBridge | 145:64910690c574 | 1969 | /** |
AnnaBridge | 145:64910690c574 | 1970 | * @brief Get Stream 5 direct mode error flag. |
AnnaBridge | 145:64910690c574 | 1971 | * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5 |
AnnaBridge | 145:64910690c574 | 1972 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1973 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1974 | */ |
AnnaBridge | 145:64910690c574 | 1975 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1976 | { |
AnnaBridge | 145:64910690c574 | 1977 | return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5)); |
AnnaBridge | 145:64910690c574 | 1978 | } |
AnnaBridge | 145:64910690c574 | 1979 | |
AnnaBridge | 145:64910690c574 | 1980 | /** |
AnnaBridge | 145:64910690c574 | 1981 | * @brief Get Stream 6 direct mode error flag. |
AnnaBridge | 145:64910690c574 | 1982 | * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6 |
AnnaBridge | 145:64910690c574 | 1983 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1984 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1985 | */ |
AnnaBridge | 145:64910690c574 | 1986 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1987 | { |
AnnaBridge | 145:64910690c574 | 1988 | return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6)); |
AnnaBridge | 145:64910690c574 | 1989 | } |
AnnaBridge | 145:64910690c574 | 1990 | |
AnnaBridge | 145:64910690c574 | 1991 | /** |
AnnaBridge | 145:64910690c574 | 1992 | * @brief Get Stream 7 direct mode error flag. |
AnnaBridge | 145:64910690c574 | 1993 | * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7 |
AnnaBridge | 145:64910690c574 | 1994 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1995 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1996 | */ |
AnnaBridge | 145:64910690c574 | 1997 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1998 | { |
AnnaBridge | 145:64910690c574 | 1999 | return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7)); |
AnnaBridge | 145:64910690c574 | 2000 | } |
AnnaBridge | 145:64910690c574 | 2001 | |
AnnaBridge | 145:64910690c574 | 2002 | /** |
AnnaBridge | 145:64910690c574 | 2003 | * @brief Get Stream 0 FIFO error flag. |
AnnaBridge | 145:64910690c574 | 2004 | * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0 |
AnnaBridge | 145:64910690c574 | 2005 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2006 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 2007 | */ |
AnnaBridge | 145:64910690c574 | 2008 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2009 | { |
AnnaBridge | 145:64910690c574 | 2010 | return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0)); |
AnnaBridge | 145:64910690c574 | 2011 | } |
AnnaBridge | 145:64910690c574 | 2012 | |
AnnaBridge | 145:64910690c574 | 2013 | /** |
AnnaBridge | 145:64910690c574 | 2014 | * @brief Get Stream 1 FIFO error flag. |
AnnaBridge | 145:64910690c574 | 2015 | * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1 |
AnnaBridge | 145:64910690c574 | 2016 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2017 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 2018 | */ |
AnnaBridge | 145:64910690c574 | 2019 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2020 | { |
AnnaBridge | 145:64910690c574 | 2021 | return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1)); |
AnnaBridge | 145:64910690c574 | 2022 | } |
AnnaBridge | 145:64910690c574 | 2023 | |
AnnaBridge | 145:64910690c574 | 2024 | /** |
AnnaBridge | 145:64910690c574 | 2025 | * @brief Get Stream 2 FIFO error flag. |
AnnaBridge | 145:64910690c574 | 2026 | * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2 |
AnnaBridge | 145:64910690c574 | 2027 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2028 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 2029 | */ |
AnnaBridge | 145:64910690c574 | 2030 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2031 | { |
AnnaBridge | 145:64910690c574 | 2032 | return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2)); |
AnnaBridge | 145:64910690c574 | 2033 | } |
AnnaBridge | 145:64910690c574 | 2034 | |
AnnaBridge | 145:64910690c574 | 2035 | /** |
AnnaBridge | 145:64910690c574 | 2036 | * @brief Get Stream 3 FIFO error flag. |
AnnaBridge | 145:64910690c574 | 2037 | * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3 |
AnnaBridge | 145:64910690c574 | 2038 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2039 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 2040 | */ |
AnnaBridge | 145:64910690c574 | 2041 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2042 | { |
AnnaBridge | 145:64910690c574 | 2043 | return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3)); |
AnnaBridge | 145:64910690c574 | 2044 | } |
AnnaBridge | 145:64910690c574 | 2045 | |
AnnaBridge | 145:64910690c574 | 2046 | /** |
AnnaBridge | 145:64910690c574 | 2047 | * @brief Get Stream 4 FIFO error flag. |
AnnaBridge | 145:64910690c574 | 2048 | * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4 |
AnnaBridge | 145:64910690c574 | 2049 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2050 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 2051 | */ |
AnnaBridge | 145:64910690c574 | 2052 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2053 | { |
AnnaBridge | 145:64910690c574 | 2054 | return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4)); |
AnnaBridge | 145:64910690c574 | 2055 | } |
AnnaBridge | 145:64910690c574 | 2056 | |
AnnaBridge | 145:64910690c574 | 2057 | /** |
AnnaBridge | 145:64910690c574 | 2058 | * @brief Get Stream 5 FIFO error flag. |
AnnaBridge | 145:64910690c574 | 2059 | * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5 |
AnnaBridge | 145:64910690c574 | 2060 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2061 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 2062 | */ |
AnnaBridge | 145:64910690c574 | 2063 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2064 | { |
AnnaBridge | 145:64910690c574 | 2065 | return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5)); |
AnnaBridge | 145:64910690c574 | 2066 | } |
AnnaBridge | 145:64910690c574 | 2067 | |
AnnaBridge | 145:64910690c574 | 2068 | /** |
AnnaBridge | 145:64910690c574 | 2069 | * @brief Get Stream 6 FIFO error flag. |
AnnaBridge | 145:64910690c574 | 2070 | * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6 |
AnnaBridge | 145:64910690c574 | 2071 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2072 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 2073 | */ |
AnnaBridge | 145:64910690c574 | 2074 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2075 | { |
AnnaBridge | 145:64910690c574 | 2076 | return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6)); |
AnnaBridge | 145:64910690c574 | 2077 | } |
AnnaBridge | 145:64910690c574 | 2078 | |
AnnaBridge | 145:64910690c574 | 2079 | /** |
AnnaBridge | 145:64910690c574 | 2080 | * @brief Get Stream 7 FIFO error flag. |
AnnaBridge | 145:64910690c574 | 2081 | * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7 |
AnnaBridge | 145:64910690c574 | 2082 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2083 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 2084 | */ |
AnnaBridge | 145:64910690c574 | 2085 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2086 | { |
AnnaBridge | 145:64910690c574 | 2087 | return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7)); |
AnnaBridge | 145:64910690c574 | 2088 | } |
AnnaBridge | 145:64910690c574 | 2089 | |
AnnaBridge | 145:64910690c574 | 2090 | /** |
AnnaBridge | 145:64910690c574 | 2091 | * @brief Clear Stream 0 half transfer flag. |
AnnaBridge | 145:64910690c574 | 2092 | * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0 |
AnnaBridge | 145:64910690c574 | 2093 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2094 | * @retval None |
AnnaBridge | 145:64910690c574 | 2095 | */ |
AnnaBridge | 145:64910690c574 | 2096 | __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2097 | { |
AnnaBridge | 163:e59c8e839560 | 2098 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0); |
AnnaBridge | 145:64910690c574 | 2099 | } |
AnnaBridge | 145:64910690c574 | 2100 | |
AnnaBridge | 145:64910690c574 | 2101 | /** |
AnnaBridge | 145:64910690c574 | 2102 | * @brief Clear Stream 1 half transfer flag. |
AnnaBridge | 145:64910690c574 | 2103 | * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1 |
AnnaBridge | 145:64910690c574 | 2104 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2105 | * @retval None |
AnnaBridge | 145:64910690c574 | 2106 | */ |
AnnaBridge | 145:64910690c574 | 2107 | __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2108 | { |
AnnaBridge | 163:e59c8e839560 | 2109 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1); |
AnnaBridge | 145:64910690c574 | 2110 | } |
AnnaBridge | 145:64910690c574 | 2111 | |
AnnaBridge | 145:64910690c574 | 2112 | /** |
AnnaBridge | 145:64910690c574 | 2113 | * @brief Clear Stream 2 half transfer flag. |
AnnaBridge | 145:64910690c574 | 2114 | * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2 |
AnnaBridge | 145:64910690c574 | 2115 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2116 | * @retval None |
AnnaBridge | 145:64910690c574 | 2117 | */ |
AnnaBridge | 145:64910690c574 | 2118 | __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2119 | { |
AnnaBridge | 163:e59c8e839560 | 2120 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2); |
AnnaBridge | 145:64910690c574 | 2121 | } |
AnnaBridge | 145:64910690c574 | 2122 | |
AnnaBridge | 145:64910690c574 | 2123 | /** |
AnnaBridge | 145:64910690c574 | 2124 | * @brief Clear Stream 3 half transfer flag. |
AnnaBridge | 145:64910690c574 | 2125 | * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3 |
AnnaBridge | 145:64910690c574 | 2126 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2127 | * @retval None |
AnnaBridge | 145:64910690c574 | 2128 | */ |
AnnaBridge | 145:64910690c574 | 2129 | __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2130 | { |
AnnaBridge | 163:e59c8e839560 | 2131 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3); |
AnnaBridge | 145:64910690c574 | 2132 | } |
AnnaBridge | 145:64910690c574 | 2133 | |
AnnaBridge | 145:64910690c574 | 2134 | /** |
AnnaBridge | 145:64910690c574 | 2135 | * @brief Clear Stream 4 half transfer flag. |
AnnaBridge | 145:64910690c574 | 2136 | * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4 |
AnnaBridge | 145:64910690c574 | 2137 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2138 | * @retval None |
AnnaBridge | 145:64910690c574 | 2139 | */ |
AnnaBridge | 145:64910690c574 | 2140 | __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2141 | { |
AnnaBridge | 163:e59c8e839560 | 2142 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4); |
AnnaBridge | 145:64910690c574 | 2143 | } |
AnnaBridge | 145:64910690c574 | 2144 | |
AnnaBridge | 145:64910690c574 | 2145 | /** |
AnnaBridge | 145:64910690c574 | 2146 | * @brief Clear Stream 5 half transfer flag. |
AnnaBridge | 145:64910690c574 | 2147 | * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5 |
AnnaBridge | 145:64910690c574 | 2148 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2149 | * @retval None |
AnnaBridge | 145:64910690c574 | 2150 | */ |
AnnaBridge | 145:64910690c574 | 2151 | __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2152 | { |
AnnaBridge | 163:e59c8e839560 | 2153 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5); |
AnnaBridge | 145:64910690c574 | 2154 | } |
AnnaBridge | 145:64910690c574 | 2155 | |
AnnaBridge | 145:64910690c574 | 2156 | /** |
AnnaBridge | 145:64910690c574 | 2157 | * @brief Clear Stream 6 half transfer flag. |
AnnaBridge | 145:64910690c574 | 2158 | * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6 |
AnnaBridge | 145:64910690c574 | 2159 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2160 | * @retval None |
AnnaBridge | 145:64910690c574 | 2161 | */ |
AnnaBridge | 145:64910690c574 | 2162 | __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2163 | { |
AnnaBridge | 163:e59c8e839560 | 2164 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6); |
AnnaBridge | 145:64910690c574 | 2165 | } |
AnnaBridge | 145:64910690c574 | 2166 | |
AnnaBridge | 145:64910690c574 | 2167 | /** |
AnnaBridge | 145:64910690c574 | 2168 | * @brief Clear Stream 7 half transfer flag. |
AnnaBridge | 145:64910690c574 | 2169 | * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7 |
AnnaBridge | 145:64910690c574 | 2170 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2171 | * @retval None |
AnnaBridge | 145:64910690c574 | 2172 | */ |
AnnaBridge | 145:64910690c574 | 2173 | __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2174 | { |
AnnaBridge | 163:e59c8e839560 | 2175 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7); |
AnnaBridge | 145:64910690c574 | 2176 | } |
AnnaBridge | 145:64910690c574 | 2177 | |
AnnaBridge | 145:64910690c574 | 2178 | /** |
AnnaBridge | 145:64910690c574 | 2179 | * @brief Clear Stream 0 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 2180 | * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0 |
AnnaBridge | 145:64910690c574 | 2181 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2182 | * @retval None |
AnnaBridge | 145:64910690c574 | 2183 | */ |
AnnaBridge | 145:64910690c574 | 2184 | __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2185 | { |
AnnaBridge | 163:e59c8e839560 | 2186 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0); |
AnnaBridge | 145:64910690c574 | 2187 | } |
AnnaBridge | 145:64910690c574 | 2188 | |
AnnaBridge | 145:64910690c574 | 2189 | /** |
AnnaBridge | 145:64910690c574 | 2190 | * @brief Clear Stream 1 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 2191 | * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1 |
AnnaBridge | 145:64910690c574 | 2192 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2193 | * @retval None |
AnnaBridge | 145:64910690c574 | 2194 | */ |
AnnaBridge | 145:64910690c574 | 2195 | __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2196 | { |
AnnaBridge | 163:e59c8e839560 | 2197 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1); |
AnnaBridge | 145:64910690c574 | 2198 | } |
AnnaBridge | 145:64910690c574 | 2199 | |
AnnaBridge | 145:64910690c574 | 2200 | /** |
AnnaBridge | 145:64910690c574 | 2201 | * @brief Clear Stream 2 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 2202 | * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2 |
AnnaBridge | 145:64910690c574 | 2203 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2204 | * @retval None |
AnnaBridge | 145:64910690c574 | 2205 | */ |
AnnaBridge | 145:64910690c574 | 2206 | __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2207 | { |
AnnaBridge | 163:e59c8e839560 | 2208 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2); |
AnnaBridge | 145:64910690c574 | 2209 | } |
AnnaBridge | 145:64910690c574 | 2210 | |
AnnaBridge | 145:64910690c574 | 2211 | /** |
AnnaBridge | 145:64910690c574 | 2212 | * @brief Clear Stream 3 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 2213 | * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3 |
AnnaBridge | 145:64910690c574 | 2214 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2215 | * @retval None |
AnnaBridge | 145:64910690c574 | 2216 | */ |
AnnaBridge | 145:64910690c574 | 2217 | __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2218 | { |
AnnaBridge | 163:e59c8e839560 | 2219 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3); |
AnnaBridge | 145:64910690c574 | 2220 | } |
AnnaBridge | 145:64910690c574 | 2221 | |
AnnaBridge | 145:64910690c574 | 2222 | /** |
AnnaBridge | 145:64910690c574 | 2223 | * @brief Clear Stream 4 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 2224 | * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4 |
AnnaBridge | 145:64910690c574 | 2225 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2226 | * @retval None |
AnnaBridge | 145:64910690c574 | 2227 | */ |
AnnaBridge | 145:64910690c574 | 2228 | __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2229 | { |
AnnaBridge | 163:e59c8e839560 | 2230 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4); |
AnnaBridge | 145:64910690c574 | 2231 | } |
AnnaBridge | 145:64910690c574 | 2232 | |
AnnaBridge | 145:64910690c574 | 2233 | /** |
AnnaBridge | 145:64910690c574 | 2234 | * @brief Clear Stream 5 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 2235 | * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5 |
AnnaBridge | 145:64910690c574 | 2236 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2237 | * @retval None |
AnnaBridge | 145:64910690c574 | 2238 | */ |
AnnaBridge | 145:64910690c574 | 2239 | __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2240 | { |
AnnaBridge | 163:e59c8e839560 | 2241 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5); |
AnnaBridge | 145:64910690c574 | 2242 | } |
AnnaBridge | 145:64910690c574 | 2243 | |
AnnaBridge | 145:64910690c574 | 2244 | /** |
AnnaBridge | 145:64910690c574 | 2245 | * @brief Clear Stream 6 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 2246 | * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6 |
AnnaBridge | 145:64910690c574 | 2247 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2248 | * @retval None |
AnnaBridge | 145:64910690c574 | 2249 | */ |
AnnaBridge | 145:64910690c574 | 2250 | __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2251 | { |
AnnaBridge | 163:e59c8e839560 | 2252 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6); |
AnnaBridge | 145:64910690c574 | 2253 | } |
AnnaBridge | 145:64910690c574 | 2254 | |
AnnaBridge | 145:64910690c574 | 2255 | /** |
AnnaBridge | 145:64910690c574 | 2256 | * @brief Clear Stream 7 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 2257 | * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7 |
AnnaBridge | 145:64910690c574 | 2258 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2259 | * @retval None |
AnnaBridge | 145:64910690c574 | 2260 | */ |
AnnaBridge | 145:64910690c574 | 2261 | __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2262 | { |
AnnaBridge | 163:e59c8e839560 | 2263 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7); |
AnnaBridge | 145:64910690c574 | 2264 | } |
AnnaBridge | 145:64910690c574 | 2265 | |
AnnaBridge | 145:64910690c574 | 2266 | /** |
AnnaBridge | 145:64910690c574 | 2267 | * @brief Clear Stream 0 transfer error flag. |
AnnaBridge | 145:64910690c574 | 2268 | * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0 |
AnnaBridge | 145:64910690c574 | 2269 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2270 | * @retval None |
AnnaBridge | 145:64910690c574 | 2271 | */ |
AnnaBridge | 145:64910690c574 | 2272 | __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2273 | { |
AnnaBridge | 163:e59c8e839560 | 2274 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0); |
AnnaBridge | 145:64910690c574 | 2275 | } |
AnnaBridge | 145:64910690c574 | 2276 | |
AnnaBridge | 145:64910690c574 | 2277 | /** |
AnnaBridge | 145:64910690c574 | 2278 | * @brief Clear Stream 1 transfer error flag. |
AnnaBridge | 145:64910690c574 | 2279 | * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1 |
AnnaBridge | 145:64910690c574 | 2280 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2281 | * @retval None |
AnnaBridge | 145:64910690c574 | 2282 | */ |
AnnaBridge | 145:64910690c574 | 2283 | __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2284 | { |
AnnaBridge | 163:e59c8e839560 | 2285 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1); |
AnnaBridge | 145:64910690c574 | 2286 | } |
AnnaBridge | 145:64910690c574 | 2287 | |
AnnaBridge | 145:64910690c574 | 2288 | /** |
AnnaBridge | 145:64910690c574 | 2289 | * @brief Clear Stream 2 transfer error flag. |
AnnaBridge | 145:64910690c574 | 2290 | * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2 |
AnnaBridge | 145:64910690c574 | 2291 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2292 | * @retval None |
AnnaBridge | 145:64910690c574 | 2293 | */ |
AnnaBridge | 145:64910690c574 | 2294 | __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2295 | { |
AnnaBridge | 163:e59c8e839560 | 2296 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2); |
AnnaBridge | 145:64910690c574 | 2297 | } |
AnnaBridge | 145:64910690c574 | 2298 | |
AnnaBridge | 145:64910690c574 | 2299 | /** |
AnnaBridge | 145:64910690c574 | 2300 | * @brief Clear Stream 3 transfer error flag. |
AnnaBridge | 145:64910690c574 | 2301 | * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3 |
AnnaBridge | 145:64910690c574 | 2302 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2303 | * @retval None |
AnnaBridge | 145:64910690c574 | 2304 | */ |
AnnaBridge | 145:64910690c574 | 2305 | __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2306 | { |
AnnaBridge | 163:e59c8e839560 | 2307 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3); |
AnnaBridge | 145:64910690c574 | 2308 | } |
AnnaBridge | 145:64910690c574 | 2309 | |
AnnaBridge | 145:64910690c574 | 2310 | /** |
AnnaBridge | 145:64910690c574 | 2311 | * @brief Clear Stream 4 transfer error flag. |
AnnaBridge | 145:64910690c574 | 2312 | * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4 |
AnnaBridge | 145:64910690c574 | 2313 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2314 | * @retval None |
AnnaBridge | 145:64910690c574 | 2315 | */ |
AnnaBridge | 145:64910690c574 | 2316 | __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2317 | { |
AnnaBridge | 163:e59c8e839560 | 2318 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4); |
AnnaBridge | 145:64910690c574 | 2319 | } |
AnnaBridge | 145:64910690c574 | 2320 | |
AnnaBridge | 145:64910690c574 | 2321 | /** |
AnnaBridge | 145:64910690c574 | 2322 | * @brief Clear Stream 5 transfer error flag. |
AnnaBridge | 145:64910690c574 | 2323 | * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5 |
AnnaBridge | 145:64910690c574 | 2324 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2325 | * @retval None |
AnnaBridge | 145:64910690c574 | 2326 | */ |
AnnaBridge | 145:64910690c574 | 2327 | __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2328 | { |
AnnaBridge | 163:e59c8e839560 | 2329 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5); |
AnnaBridge | 145:64910690c574 | 2330 | } |
AnnaBridge | 145:64910690c574 | 2331 | |
AnnaBridge | 145:64910690c574 | 2332 | /** |
AnnaBridge | 145:64910690c574 | 2333 | * @brief Clear Stream 6 transfer error flag. |
AnnaBridge | 145:64910690c574 | 2334 | * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6 |
AnnaBridge | 145:64910690c574 | 2335 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2336 | * @retval None |
AnnaBridge | 145:64910690c574 | 2337 | */ |
AnnaBridge | 145:64910690c574 | 2338 | __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2339 | { |
AnnaBridge | 163:e59c8e839560 | 2340 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6); |
AnnaBridge | 145:64910690c574 | 2341 | } |
AnnaBridge | 145:64910690c574 | 2342 | |
AnnaBridge | 145:64910690c574 | 2343 | /** |
AnnaBridge | 145:64910690c574 | 2344 | * @brief Clear Stream 7 transfer error flag. |
AnnaBridge | 145:64910690c574 | 2345 | * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7 |
AnnaBridge | 145:64910690c574 | 2346 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2347 | * @retval None |
AnnaBridge | 145:64910690c574 | 2348 | */ |
AnnaBridge | 145:64910690c574 | 2349 | __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2350 | { |
AnnaBridge | 163:e59c8e839560 | 2351 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7); |
AnnaBridge | 145:64910690c574 | 2352 | } |
AnnaBridge | 145:64910690c574 | 2353 | |
AnnaBridge | 145:64910690c574 | 2354 | /** |
AnnaBridge | 145:64910690c574 | 2355 | * @brief Clear Stream 0 direct mode error flag. |
AnnaBridge | 145:64910690c574 | 2356 | * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0 |
AnnaBridge | 145:64910690c574 | 2357 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2358 | * @retval None |
AnnaBridge | 145:64910690c574 | 2359 | */ |
AnnaBridge | 145:64910690c574 | 2360 | __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2361 | { |
AnnaBridge | 163:e59c8e839560 | 2362 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0); |
AnnaBridge | 145:64910690c574 | 2363 | } |
AnnaBridge | 145:64910690c574 | 2364 | |
AnnaBridge | 145:64910690c574 | 2365 | /** |
AnnaBridge | 145:64910690c574 | 2366 | * @brief Clear Stream 1 direct mode error flag. |
AnnaBridge | 145:64910690c574 | 2367 | * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1 |
AnnaBridge | 145:64910690c574 | 2368 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2369 | * @retval None |
AnnaBridge | 145:64910690c574 | 2370 | */ |
AnnaBridge | 145:64910690c574 | 2371 | __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2372 | { |
AnnaBridge | 163:e59c8e839560 | 2373 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1); |
AnnaBridge | 145:64910690c574 | 2374 | } |
AnnaBridge | 145:64910690c574 | 2375 | |
AnnaBridge | 145:64910690c574 | 2376 | /** |
AnnaBridge | 145:64910690c574 | 2377 | * @brief Clear Stream 2 direct mode error flag. |
AnnaBridge | 145:64910690c574 | 2378 | * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2 |
AnnaBridge | 145:64910690c574 | 2379 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2380 | * @retval None |
AnnaBridge | 145:64910690c574 | 2381 | */ |
AnnaBridge | 145:64910690c574 | 2382 | __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2383 | { |
AnnaBridge | 163:e59c8e839560 | 2384 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2); |
AnnaBridge | 145:64910690c574 | 2385 | } |
AnnaBridge | 145:64910690c574 | 2386 | |
AnnaBridge | 145:64910690c574 | 2387 | /** |
AnnaBridge | 145:64910690c574 | 2388 | * @brief Clear Stream 3 direct mode error flag. |
AnnaBridge | 145:64910690c574 | 2389 | * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3 |
AnnaBridge | 145:64910690c574 | 2390 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2391 | * @retval None |
AnnaBridge | 145:64910690c574 | 2392 | */ |
AnnaBridge | 145:64910690c574 | 2393 | __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2394 | { |
AnnaBridge | 163:e59c8e839560 | 2395 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3); |
AnnaBridge | 145:64910690c574 | 2396 | } |
AnnaBridge | 145:64910690c574 | 2397 | |
AnnaBridge | 145:64910690c574 | 2398 | /** |
AnnaBridge | 145:64910690c574 | 2399 | * @brief Clear Stream 4 direct mode error flag. |
AnnaBridge | 145:64910690c574 | 2400 | * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4 |
AnnaBridge | 145:64910690c574 | 2401 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2402 | * @retval None |
AnnaBridge | 145:64910690c574 | 2403 | */ |
AnnaBridge | 145:64910690c574 | 2404 | __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2405 | { |
AnnaBridge | 163:e59c8e839560 | 2406 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4); |
AnnaBridge | 145:64910690c574 | 2407 | } |
AnnaBridge | 145:64910690c574 | 2408 | |
AnnaBridge | 145:64910690c574 | 2409 | /** |
AnnaBridge | 145:64910690c574 | 2410 | * @brief Clear Stream 5 direct mode error flag. |
AnnaBridge | 145:64910690c574 | 2411 | * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5 |
AnnaBridge | 145:64910690c574 | 2412 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2413 | * @retval None |
AnnaBridge | 145:64910690c574 | 2414 | */ |
AnnaBridge | 145:64910690c574 | 2415 | __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2416 | { |
AnnaBridge | 163:e59c8e839560 | 2417 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5); |
AnnaBridge | 145:64910690c574 | 2418 | } |
AnnaBridge | 145:64910690c574 | 2419 | |
AnnaBridge | 145:64910690c574 | 2420 | /** |
AnnaBridge | 145:64910690c574 | 2421 | * @brief Clear Stream 6 direct mode error flag. |
AnnaBridge | 145:64910690c574 | 2422 | * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6 |
AnnaBridge | 145:64910690c574 | 2423 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2424 | * @retval None |
AnnaBridge | 145:64910690c574 | 2425 | */ |
AnnaBridge | 145:64910690c574 | 2426 | __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2427 | { |
AnnaBridge | 163:e59c8e839560 | 2428 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6); |
AnnaBridge | 145:64910690c574 | 2429 | } |
AnnaBridge | 145:64910690c574 | 2430 | |
AnnaBridge | 145:64910690c574 | 2431 | /** |
AnnaBridge | 145:64910690c574 | 2432 | * @brief Clear Stream 7 direct mode error flag. |
AnnaBridge | 145:64910690c574 | 2433 | * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7 |
AnnaBridge | 145:64910690c574 | 2434 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2435 | * @retval None |
AnnaBridge | 145:64910690c574 | 2436 | */ |
AnnaBridge | 145:64910690c574 | 2437 | __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2438 | { |
AnnaBridge | 163:e59c8e839560 | 2439 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7); |
AnnaBridge | 145:64910690c574 | 2440 | } |
AnnaBridge | 145:64910690c574 | 2441 | |
AnnaBridge | 145:64910690c574 | 2442 | /** |
AnnaBridge | 145:64910690c574 | 2443 | * @brief Clear Stream 0 FIFO error flag. |
AnnaBridge | 145:64910690c574 | 2444 | * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0 |
AnnaBridge | 145:64910690c574 | 2445 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2446 | * @retval None |
AnnaBridge | 145:64910690c574 | 2447 | */ |
AnnaBridge | 145:64910690c574 | 2448 | __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2449 | { |
AnnaBridge | 163:e59c8e839560 | 2450 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0); |
AnnaBridge | 145:64910690c574 | 2451 | } |
AnnaBridge | 145:64910690c574 | 2452 | |
AnnaBridge | 145:64910690c574 | 2453 | /** |
AnnaBridge | 145:64910690c574 | 2454 | * @brief Clear Stream 1 FIFO error flag. |
AnnaBridge | 145:64910690c574 | 2455 | * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1 |
AnnaBridge | 145:64910690c574 | 2456 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2457 | * @retval None |
AnnaBridge | 145:64910690c574 | 2458 | */ |
AnnaBridge | 145:64910690c574 | 2459 | __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2460 | { |
AnnaBridge | 163:e59c8e839560 | 2461 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1); |
AnnaBridge | 145:64910690c574 | 2462 | } |
AnnaBridge | 145:64910690c574 | 2463 | |
AnnaBridge | 145:64910690c574 | 2464 | /** |
AnnaBridge | 145:64910690c574 | 2465 | * @brief Clear Stream 2 FIFO error flag. |
AnnaBridge | 145:64910690c574 | 2466 | * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2 |
AnnaBridge | 145:64910690c574 | 2467 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2468 | * @retval None |
AnnaBridge | 145:64910690c574 | 2469 | */ |
AnnaBridge | 145:64910690c574 | 2470 | __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2471 | { |
AnnaBridge | 163:e59c8e839560 | 2472 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2); |
AnnaBridge | 145:64910690c574 | 2473 | } |
AnnaBridge | 145:64910690c574 | 2474 | |
AnnaBridge | 145:64910690c574 | 2475 | /** |
AnnaBridge | 145:64910690c574 | 2476 | * @brief Clear Stream 3 FIFO error flag. |
AnnaBridge | 145:64910690c574 | 2477 | * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3 |
AnnaBridge | 145:64910690c574 | 2478 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2479 | * @retval None |
AnnaBridge | 145:64910690c574 | 2480 | */ |
AnnaBridge | 145:64910690c574 | 2481 | __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2482 | { |
AnnaBridge | 163:e59c8e839560 | 2483 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3); |
AnnaBridge | 145:64910690c574 | 2484 | } |
AnnaBridge | 145:64910690c574 | 2485 | |
AnnaBridge | 145:64910690c574 | 2486 | /** |
AnnaBridge | 145:64910690c574 | 2487 | * @brief Clear Stream 4 FIFO error flag. |
AnnaBridge | 145:64910690c574 | 2488 | * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4 |
AnnaBridge | 145:64910690c574 | 2489 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2490 | * @retval None |
AnnaBridge | 145:64910690c574 | 2491 | */ |
AnnaBridge | 145:64910690c574 | 2492 | __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2493 | { |
AnnaBridge | 163:e59c8e839560 | 2494 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4); |
AnnaBridge | 145:64910690c574 | 2495 | } |
AnnaBridge | 145:64910690c574 | 2496 | |
AnnaBridge | 145:64910690c574 | 2497 | /** |
AnnaBridge | 145:64910690c574 | 2498 | * @brief Clear Stream 5 FIFO error flag. |
AnnaBridge | 145:64910690c574 | 2499 | * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5 |
AnnaBridge | 145:64910690c574 | 2500 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2501 | * @retval None |
AnnaBridge | 145:64910690c574 | 2502 | */ |
AnnaBridge | 145:64910690c574 | 2503 | __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2504 | { |
AnnaBridge | 163:e59c8e839560 | 2505 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5); |
AnnaBridge | 145:64910690c574 | 2506 | } |
AnnaBridge | 145:64910690c574 | 2507 | |
AnnaBridge | 145:64910690c574 | 2508 | /** |
AnnaBridge | 145:64910690c574 | 2509 | * @brief Clear Stream 6 FIFO error flag. |
AnnaBridge | 145:64910690c574 | 2510 | * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6 |
AnnaBridge | 145:64910690c574 | 2511 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2512 | * @retval None |
AnnaBridge | 145:64910690c574 | 2513 | */ |
AnnaBridge | 145:64910690c574 | 2514 | __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2515 | { |
AnnaBridge | 163:e59c8e839560 | 2516 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6); |
AnnaBridge | 145:64910690c574 | 2517 | } |
AnnaBridge | 145:64910690c574 | 2518 | |
AnnaBridge | 145:64910690c574 | 2519 | /** |
AnnaBridge | 145:64910690c574 | 2520 | * @brief Clear Stream 7 FIFO error flag. |
AnnaBridge | 145:64910690c574 | 2521 | * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7 |
AnnaBridge | 145:64910690c574 | 2522 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2523 | * @retval None |
AnnaBridge | 145:64910690c574 | 2524 | */ |
AnnaBridge | 145:64910690c574 | 2525 | __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2526 | { |
AnnaBridge | 163:e59c8e839560 | 2527 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7); |
AnnaBridge | 145:64910690c574 | 2528 | } |
AnnaBridge | 145:64910690c574 | 2529 | |
AnnaBridge | 145:64910690c574 | 2530 | /** |
AnnaBridge | 145:64910690c574 | 2531 | * @} |
AnnaBridge | 145:64910690c574 | 2532 | */ |
AnnaBridge | 145:64910690c574 | 2533 | |
AnnaBridge | 145:64910690c574 | 2534 | /** @defgroup DMA_LL_EF_IT_Management IT_Management |
AnnaBridge | 145:64910690c574 | 2535 | * @{ |
AnnaBridge | 145:64910690c574 | 2536 | */ |
AnnaBridge | 145:64910690c574 | 2537 | |
AnnaBridge | 145:64910690c574 | 2538 | /** |
AnnaBridge | 145:64910690c574 | 2539 | * @brief Enable Half transfer interrupt. |
AnnaBridge | 145:64910690c574 | 2540 | * @rmtoll CR HTIE LL_DMA_EnableIT_HT |
AnnaBridge | 145:64910690c574 | 2541 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2542 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2543 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 2544 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 2545 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 2546 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 2547 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 2548 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 2549 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 2550 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 2551 | * @retval None |
AnnaBridge | 145:64910690c574 | 2552 | */ |
AnnaBridge | 145:64910690c574 | 2553 | __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 2554 | { |
AnnaBridge | 145:64910690c574 | 2555 | SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); |
AnnaBridge | 145:64910690c574 | 2556 | } |
AnnaBridge | 145:64910690c574 | 2557 | |
AnnaBridge | 145:64910690c574 | 2558 | /** |
AnnaBridge | 145:64910690c574 | 2559 | * @brief Enable Transfer error interrupt. |
AnnaBridge | 145:64910690c574 | 2560 | * @rmtoll CR TEIE LL_DMA_EnableIT_TE |
AnnaBridge | 145:64910690c574 | 2561 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2562 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2563 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 2564 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 2565 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 2566 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 2567 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 2568 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 2569 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 2570 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 2571 | * @retval None |
AnnaBridge | 145:64910690c574 | 2572 | */ |
AnnaBridge | 145:64910690c574 | 2573 | __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 2574 | { |
AnnaBridge | 145:64910690c574 | 2575 | SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE); |
AnnaBridge | 145:64910690c574 | 2576 | } |
AnnaBridge | 145:64910690c574 | 2577 | |
AnnaBridge | 145:64910690c574 | 2578 | /** |
AnnaBridge | 145:64910690c574 | 2579 | * @brief Enable Transfer complete interrupt. |
AnnaBridge | 145:64910690c574 | 2580 | * @rmtoll CR TCIE LL_DMA_EnableIT_TC |
AnnaBridge | 145:64910690c574 | 2581 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2582 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2583 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 2584 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 2585 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 2586 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 2587 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 2588 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 2589 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 2590 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 2591 | * @retval None |
AnnaBridge | 145:64910690c574 | 2592 | */ |
AnnaBridge | 145:64910690c574 | 2593 | __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 2594 | { |
AnnaBridge | 145:64910690c574 | 2595 | SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); |
AnnaBridge | 145:64910690c574 | 2596 | } |
AnnaBridge | 145:64910690c574 | 2597 | |
AnnaBridge | 145:64910690c574 | 2598 | /** |
AnnaBridge | 145:64910690c574 | 2599 | * @brief Enable Direct mode error interrupt. |
AnnaBridge | 145:64910690c574 | 2600 | * @rmtoll CR DMEIE LL_DMA_EnableIT_DME |
AnnaBridge | 145:64910690c574 | 2601 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2602 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2603 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 2604 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 2605 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 2606 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 2607 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 2608 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 2609 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 2610 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 2611 | * @retval None |
AnnaBridge | 145:64910690c574 | 2612 | */ |
AnnaBridge | 145:64910690c574 | 2613 | __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 2614 | { |
AnnaBridge | 145:64910690c574 | 2615 | SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE); |
AnnaBridge | 145:64910690c574 | 2616 | } |
AnnaBridge | 145:64910690c574 | 2617 | |
AnnaBridge | 145:64910690c574 | 2618 | /** |
AnnaBridge | 145:64910690c574 | 2619 | * @brief Enable FIFO error interrupt. |
AnnaBridge | 145:64910690c574 | 2620 | * @rmtoll FCR FEIE LL_DMA_EnableIT_FE |
AnnaBridge | 145:64910690c574 | 2621 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2622 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2623 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 2624 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 2625 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 2626 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 2627 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 2628 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 2629 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 2630 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 2631 | * @retval None |
AnnaBridge | 145:64910690c574 | 2632 | */ |
AnnaBridge | 145:64910690c574 | 2633 | __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 2634 | { |
AnnaBridge | 145:64910690c574 | 2635 | SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE); |
AnnaBridge | 145:64910690c574 | 2636 | } |
AnnaBridge | 145:64910690c574 | 2637 | |
AnnaBridge | 145:64910690c574 | 2638 | /** |
AnnaBridge | 145:64910690c574 | 2639 | * @brief Disable Half transfer interrupt. |
AnnaBridge | 145:64910690c574 | 2640 | * @rmtoll CR HTIE LL_DMA_DisableIT_HT |
AnnaBridge | 145:64910690c574 | 2641 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2642 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2643 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 2644 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 2645 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 2646 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 2647 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 2648 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 2649 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 2650 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 2651 | * @retval None |
AnnaBridge | 145:64910690c574 | 2652 | */ |
AnnaBridge | 145:64910690c574 | 2653 | __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 2654 | { |
AnnaBridge | 145:64910690c574 | 2655 | CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); |
AnnaBridge | 145:64910690c574 | 2656 | } |
AnnaBridge | 145:64910690c574 | 2657 | |
AnnaBridge | 145:64910690c574 | 2658 | /** |
AnnaBridge | 145:64910690c574 | 2659 | * @brief Disable Transfer error interrupt. |
AnnaBridge | 145:64910690c574 | 2660 | * @rmtoll CR TEIE LL_DMA_DisableIT_TE |
AnnaBridge | 145:64910690c574 | 2661 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2662 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2663 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 2664 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 2665 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 2666 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 2667 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 2668 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 2669 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 2670 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 2671 | * @retval None |
AnnaBridge | 145:64910690c574 | 2672 | */ |
AnnaBridge | 145:64910690c574 | 2673 | __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 2674 | { |
AnnaBridge | 145:64910690c574 | 2675 | CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE); |
AnnaBridge | 145:64910690c574 | 2676 | } |
AnnaBridge | 145:64910690c574 | 2677 | |
AnnaBridge | 145:64910690c574 | 2678 | /** |
AnnaBridge | 145:64910690c574 | 2679 | * @brief Disable Transfer complete interrupt. |
AnnaBridge | 145:64910690c574 | 2680 | * @rmtoll CR TCIE LL_DMA_DisableIT_TC |
AnnaBridge | 145:64910690c574 | 2681 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2682 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2683 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 2684 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 2685 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 2686 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 2687 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 2688 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 2689 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 2690 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 2691 | * @retval None |
AnnaBridge | 145:64910690c574 | 2692 | */ |
AnnaBridge | 145:64910690c574 | 2693 | __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 2694 | { |
AnnaBridge | 145:64910690c574 | 2695 | CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); |
AnnaBridge | 145:64910690c574 | 2696 | } |
AnnaBridge | 145:64910690c574 | 2697 | |
AnnaBridge | 145:64910690c574 | 2698 | /** |
AnnaBridge | 145:64910690c574 | 2699 | * @brief Disable Direct mode error interrupt. |
AnnaBridge | 145:64910690c574 | 2700 | * @rmtoll CR DMEIE LL_DMA_DisableIT_DME |
AnnaBridge | 145:64910690c574 | 2701 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2702 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2703 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 2704 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 2705 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 2706 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 2707 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 2708 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 2709 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 2710 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 2711 | * @retval None |
AnnaBridge | 145:64910690c574 | 2712 | */ |
AnnaBridge | 145:64910690c574 | 2713 | __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 2714 | { |
AnnaBridge | 145:64910690c574 | 2715 | CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE); |
AnnaBridge | 145:64910690c574 | 2716 | } |
AnnaBridge | 145:64910690c574 | 2717 | |
AnnaBridge | 145:64910690c574 | 2718 | /** |
AnnaBridge | 145:64910690c574 | 2719 | * @brief Disable FIFO error interrupt. |
AnnaBridge | 145:64910690c574 | 2720 | * @rmtoll FCR FEIE LL_DMA_DisableIT_FE |
AnnaBridge | 145:64910690c574 | 2721 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2722 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2723 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 2724 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 2725 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 2726 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 2727 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 2728 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 2729 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 2730 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 2731 | * @retval None |
AnnaBridge | 145:64910690c574 | 2732 | */ |
AnnaBridge | 145:64910690c574 | 2733 | __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 2734 | { |
AnnaBridge | 145:64910690c574 | 2735 | CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE); |
AnnaBridge | 145:64910690c574 | 2736 | } |
AnnaBridge | 145:64910690c574 | 2737 | |
AnnaBridge | 145:64910690c574 | 2738 | /** |
AnnaBridge | 145:64910690c574 | 2739 | * @brief Check if Half transfer interrup is enabled. |
AnnaBridge | 145:64910690c574 | 2740 | * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT |
AnnaBridge | 145:64910690c574 | 2741 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2742 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2743 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 2744 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 2745 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 2746 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 2747 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 2748 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 2749 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 2750 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 2751 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 2752 | */ |
AnnaBridge | 145:64910690c574 | 2753 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 2754 | { |
AnnaBridge | 145:64910690c574 | 2755 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE); |
AnnaBridge | 145:64910690c574 | 2756 | } |
AnnaBridge | 145:64910690c574 | 2757 | |
AnnaBridge | 145:64910690c574 | 2758 | /** |
AnnaBridge | 145:64910690c574 | 2759 | * @brief Check if Transfer error nterrup is enabled. |
AnnaBridge | 145:64910690c574 | 2760 | * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE |
AnnaBridge | 145:64910690c574 | 2761 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2762 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2763 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 2764 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 2765 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 2766 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 2767 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 2768 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 2769 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 2770 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 2771 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 2772 | */ |
AnnaBridge | 145:64910690c574 | 2773 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 2774 | { |
AnnaBridge | 145:64910690c574 | 2775 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE); |
AnnaBridge | 145:64910690c574 | 2776 | } |
AnnaBridge | 145:64910690c574 | 2777 | |
AnnaBridge | 145:64910690c574 | 2778 | /** |
AnnaBridge | 145:64910690c574 | 2779 | * @brief Check if Transfer complete interrup is enabled. |
AnnaBridge | 145:64910690c574 | 2780 | * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC |
AnnaBridge | 145:64910690c574 | 2781 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2782 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2783 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 2784 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 2785 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 2786 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 2787 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 2788 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 2789 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 2790 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 2791 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 2792 | */ |
AnnaBridge | 145:64910690c574 | 2793 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 2794 | { |
AnnaBridge | 145:64910690c574 | 2795 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE); |
AnnaBridge | 145:64910690c574 | 2796 | } |
AnnaBridge | 145:64910690c574 | 2797 | |
AnnaBridge | 145:64910690c574 | 2798 | /** |
AnnaBridge | 145:64910690c574 | 2799 | * @brief Check if Direct mode error interrupt is enabled. |
AnnaBridge | 145:64910690c574 | 2800 | * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME |
AnnaBridge | 145:64910690c574 | 2801 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2802 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2803 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 2804 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 2805 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 2806 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 2807 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 2808 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 2809 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 2810 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 2811 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 2812 | */ |
AnnaBridge | 145:64910690c574 | 2813 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 2814 | { |
AnnaBridge | 145:64910690c574 | 2815 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE); |
AnnaBridge | 145:64910690c574 | 2816 | } |
AnnaBridge | 145:64910690c574 | 2817 | |
AnnaBridge | 145:64910690c574 | 2818 | /** |
AnnaBridge | 145:64910690c574 | 2819 | * @brief Check if FIFO error interrup is enabled. |
AnnaBridge | 145:64910690c574 | 2820 | * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE |
AnnaBridge | 145:64910690c574 | 2821 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2822 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2823 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 145:64910690c574 | 2824 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 145:64910690c574 | 2825 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 145:64910690c574 | 2826 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 145:64910690c574 | 2827 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 145:64910690c574 | 2828 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 145:64910690c574 | 2829 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 145:64910690c574 | 2830 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 145:64910690c574 | 2831 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 2832 | */ |
AnnaBridge | 145:64910690c574 | 2833 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 145:64910690c574 | 2834 | { |
AnnaBridge | 145:64910690c574 | 2835 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE); |
AnnaBridge | 145:64910690c574 | 2836 | } |
AnnaBridge | 145:64910690c574 | 2837 | |
AnnaBridge | 145:64910690c574 | 2838 | /** |
AnnaBridge | 145:64910690c574 | 2839 | * @} |
AnnaBridge | 145:64910690c574 | 2840 | */ |
AnnaBridge | 145:64910690c574 | 2841 | |
AnnaBridge | 145:64910690c574 | 2842 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 145:64910690c574 | 2843 | /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions |
AnnaBridge | 145:64910690c574 | 2844 | * @{ |
AnnaBridge | 145:64910690c574 | 2845 | */ |
AnnaBridge | 145:64910690c574 | 2846 | |
AnnaBridge | 145:64910690c574 | 2847 | uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct); |
AnnaBridge | 145:64910690c574 | 2848 | uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream); |
AnnaBridge | 145:64910690c574 | 2849 | void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); |
AnnaBridge | 145:64910690c574 | 2850 | |
AnnaBridge | 145:64910690c574 | 2851 | /** |
AnnaBridge | 145:64910690c574 | 2852 | * @} |
AnnaBridge | 145:64910690c574 | 2853 | */ |
AnnaBridge | 145:64910690c574 | 2854 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 145:64910690c574 | 2855 | |
AnnaBridge | 145:64910690c574 | 2856 | /** |
AnnaBridge | 145:64910690c574 | 2857 | * @} |
AnnaBridge | 145:64910690c574 | 2858 | */ |
AnnaBridge | 145:64910690c574 | 2859 | |
AnnaBridge | 145:64910690c574 | 2860 | /** |
AnnaBridge | 145:64910690c574 | 2861 | * @} |
AnnaBridge | 145:64910690c574 | 2862 | */ |
AnnaBridge | 145:64910690c574 | 2863 | |
AnnaBridge | 145:64910690c574 | 2864 | #endif /* DMA1 || DMA2 */ |
AnnaBridge | 145:64910690c574 | 2865 | |
AnnaBridge | 145:64910690c574 | 2866 | /** |
AnnaBridge | 145:64910690c574 | 2867 | * @} |
AnnaBridge | 145:64910690c574 | 2868 | */ |
AnnaBridge | 145:64910690c574 | 2869 | |
AnnaBridge | 145:64910690c574 | 2870 | #ifdef __cplusplus |
AnnaBridge | 145:64910690c574 | 2871 | } |
AnnaBridge | 145:64910690c574 | 2872 | #endif |
AnnaBridge | 145:64910690c574 | 2873 | |
AnnaBridge | 145:64910690c574 | 2874 | #endif /* __STM32F4xx_LL_DMA_H */ |
AnnaBridge | 145:64910690c574 | 2875 | |
AnnaBridge | 145:64910690c574 | 2876 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |