The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
mbed 2
This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.
TARGET_VK_RZ_A1H/TOOLCHAIN_IAR/vdc5_iodefine.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 161:aa5281ff4a02 | 1 | /******************************************************************************* |
AnnaBridge | 161:aa5281ff4a02 | 2 | * DISCLAIMER |
AnnaBridge | 161:aa5281ff4a02 | 3 | * This software is supplied by Renesas Electronics Corporation and is only |
AnnaBridge | 161:aa5281ff4a02 | 4 | * intended for use with Renesas products. No other uses are authorized. This |
AnnaBridge | 161:aa5281ff4a02 | 5 | * software is owned by Renesas Electronics Corporation and is protected under |
AnnaBridge | 161:aa5281ff4a02 | 6 | * all applicable laws, including copyright laws. |
AnnaBridge | 161:aa5281ff4a02 | 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING |
AnnaBridge | 161:aa5281ff4a02 | 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT |
AnnaBridge | 161:aa5281ff4a02 | 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE |
AnnaBridge | 161:aa5281ff4a02 | 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. |
AnnaBridge | 161:aa5281ff4a02 | 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS |
AnnaBridge | 161:aa5281ff4a02 | 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE |
AnnaBridge | 161:aa5281ff4a02 | 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR |
AnnaBridge | 161:aa5281ff4a02 | 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE |
AnnaBridge | 161:aa5281ff4a02 | 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
AnnaBridge | 161:aa5281ff4a02 | 16 | * Renesas reserves the right, without notice, to make changes to this software |
AnnaBridge | 161:aa5281ff4a02 | 17 | * and to discontinue the availability of this software. By using this software, |
AnnaBridge | 161:aa5281ff4a02 | 18 | * you agree to the additional terms and conditions found by accessing the |
AnnaBridge | 161:aa5281ff4a02 | 19 | * following link: |
AnnaBridge | 161:aa5281ff4a02 | 20 | * http://www.renesas.com/disclaimer* |
AnnaBridge | 161:aa5281ff4a02 | 21 | * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. |
AnnaBridge | 161:aa5281ff4a02 | 22 | *******************************************************************************/ |
AnnaBridge | 161:aa5281ff4a02 | 23 | /******************************************************************************* |
AnnaBridge | 161:aa5281ff4a02 | 24 | * File Name : vdc5_iodefine.h |
AnnaBridge | 161:aa5281ff4a02 | 25 | * $Rev: $ |
AnnaBridge | 161:aa5281ff4a02 | 26 | * $Date:: $ |
AnnaBridge | 161:aa5281ff4a02 | 27 | * Description : Definition of I/O Register for RZ/A1H,M (V2.00h) |
AnnaBridge | 161:aa5281ff4a02 | 28 | ******************************************************************************/ |
AnnaBridge | 161:aa5281ff4a02 | 29 | #ifndef VDC5_IODEFINE_H |
AnnaBridge | 161:aa5281ff4a02 | 30 | #define VDC5_IODEFINE_H |
AnnaBridge | 161:aa5281ff4a02 | 31 | /* ->QAC 0639 : Over 127 members (C90) */ |
AnnaBridge | 161:aa5281ff4a02 | 32 | /* ->QAC 0857 : Over 1024 #define (C90) */ |
AnnaBridge | 161:aa5281ff4a02 | 33 | /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ |
AnnaBridge | 161:aa5281ff4a02 | 34 | /* ->SEC M1.10.1 : Not magic number */ |
AnnaBridge | 161:aa5281ff4a02 | 35 | |
AnnaBridge | 161:aa5281ff4a02 | 36 | #define VDC50 (*(struct st_vdc5 *)0xFCFF7400uL) /* VDC50 */ |
AnnaBridge | 161:aa5281ff4a02 | 37 | #define VDC51 (*(struct st_vdc5 *)0xFCFF9400uL) /* VDC51 */ |
AnnaBridge | 161:aa5281ff4a02 | 38 | |
AnnaBridge | 161:aa5281ff4a02 | 39 | |
AnnaBridge | 161:aa5281ff4a02 | 40 | /* Start of channel array defines of VDC5 */ |
AnnaBridge | 161:aa5281ff4a02 | 41 | |
AnnaBridge | 161:aa5281ff4a02 | 42 | /* Channel array defines of VDC5 */ |
AnnaBridge | 161:aa5281ff4a02 | 43 | /*(Sample) value = VDC5[ channel ]->INP_UPDATE; */ |
AnnaBridge | 161:aa5281ff4a02 | 44 | #define VDC5_COUNT (2) |
AnnaBridge | 161:aa5281ff4a02 | 45 | #define VDC5_ADDRESS_LIST \ |
AnnaBridge | 161:aa5281ff4a02 | 46 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
AnnaBridge | 161:aa5281ff4a02 | 47 | &VDC50, &VDC51 \ |
AnnaBridge | 161:aa5281ff4a02 | 48 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
AnnaBridge | 161:aa5281ff4a02 | 49 | |
AnnaBridge | 161:aa5281ff4a02 | 50 | |
AnnaBridge | 161:aa5281ff4a02 | 51 | |
AnnaBridge | 161:aa5281ff4a02 | 52 | /* Channel array defines of VDC50_FROM_GR2_AB7_ARRAY */ |
AnnaBridge | 161:aa5281ff4a02 | 53 | /*(Sample) value = VDC50_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ |
AnnaBridge | 161:aa5281ff4a02 | 54 | #define VDC50_FROM_GR2_AB7_ARRAY_COUNT (2) |
AnnaBridge | 161:aa5281ff4a02 | 55 | #define VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \ |
AnnaBridge | 161:aa5281ff4a02 | 56 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
AnnaBridge | 161:aa5281ff4a02 | 57 | { \ |
AnnaBridge | 161:aa5281ff4a02 | 58 | &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \ |
AnnaBridge | 161:aa5281ff4a02 | 59 | &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \ |
AnnaBridge | 161:aa5281ff4a02 | 60 | } \ |
AnnaBridge | 161:aa5281ff4a02 | 61 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
AnnaBridge | 161:aa5281ff4a02 | 62 | #define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */ |
AnnaBridge | 161:aa5281ff4a02 | 63 | #define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */ |
AnnaBridge | 161:aa5281ff4a02 | 64 | #define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */ |
AnnaBridge | 161:aa5281ff4a02 | 65 | #define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */ |
AnnaBridge | 161:aa5281ff4a02 | 66 | |
AnnaBridge | 161:aa5281ff4a02 | 67 | |
AnnaBridge | 161:aa5281ff4a02 | 68 | |
AnnaBridge | 161:aa5281ff4a02 | 69 | |
AnnaBridge | 161:aa5281ff4a02 | 70 | /* Channel array defines of VDC50_FROM_GR2_UPDATE_ARRAY */ |
AnnaBridge | 161:aa5281ff4a02 | 71 | /*(Sample) value = VDC50_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ |
AnnaBridge | 161:aa5281ff4a02 | 72 | #define VDC50_FROM_GR2_UPDATE_ARRAY_COUNT (2) |
AnnaBridge | 161:aa5281ff4a02 | 73 | #define VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \ |
AnnaBridge | 161:aa5281ff4a02 | 74 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
AnnaBridge | 161:aa5281ff4a02 | 75 | { \ |
AnnaBridge | 161:aa5281ff4a02 | 76 | &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \ |
AnnaBridge | 161:aa5281ff4a02 | 77 | &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \ |
AnnaBridge | 161:aa5281ff4a02 | 78 | } \ |
AnnaBridge | 161:aa5281ff4a02 | 79 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
AnnaBridge | 161:aa5281ff4a02 | 80 | #define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 81 | #define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 82 | #define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 83 | #define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 84 | |
AnnaBridge | 161:aa5281ff4a02 | 85 | |
AnnaBridge | 161:aa5281ff4a02 | 86 | |
AnnaBridge | 161:aa5281ff4a02 | 87 | |
AnnaBridge | 161:aa5281ff4a02 | 88 | /* Channel array defines of VDC50_FROM_SC0_SCL1_PBUF0_ARRAY */ |
AnnaBridge | 161:aa5281ff4a02 | 89 | /*(Sample) value = VDC50_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */ |
AnnaBridge | 161:aa5281ff4a02 | 90 | #define VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT (2) |
AnnaBridge | 161:aa5281ff4a02 | 91 | #define VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \ |
AnnaBridge | 161:aa5281ff4a02 | 92 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
AnnaBridge | 161:aa5281ff4a02 | 93 | { \ |
AnnaBridge | 161:aa5281ff4a02 | 94 | &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \ |
AnnaBridge | 161:aa5281ff4a02 | 95 | &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \ |
AnnaBridge | 161:aa5281ff4a02 | 96 | } \ |
AnnaBridge | 161:aa5281ff4a02 | 97 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
AnnaBridge | 161:aa5281ff4a02 | 98 | #define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */ |
AnnaBridge | 161:aa5281ff4a02 | 99 | #define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */ |
AnnaBridge | 161:aa5281ff4a02 | 100 | #define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */ |
AnnaBridge | 161:aa5281ff4a02 | 101 | #define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */ |
AnnaBridge | 161:aa5281ff4a02 | 102 | |
AnnaBridge | 161:aa5281ff4a02 | 103 | |
AnnaBridge | 161:aa5281ff4a02 | 104 | |
AnnaBridge | 161:aa5281ff4a02 | 105 | |
AnnaBridge | 161:aa5281ff4a02 | 106 | /* Channel array defines of VDC50_FROM_SC0_SCL0_UPDATE_ARRAY */ |
AnnaBridge | 161:aa5281ff4a02 | 107 | /*(Sample) value = VDC50_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */ |
AnnaBridge | 161:aa5281ff4a02 | 108 | #define VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT (2) |
AnnaBridge | 161:aa5281ff4a02 | 109 | #define VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \ |
AnnaBridge | 161:aa5281ff4a02 | 110 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
AnnaBridge | 161:aa5281ff4a02 | 111 | { \ |
AnnaBridge | 161:aa5281ff4a02 | 112 | &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \ |
AnnaBridge | 161:aa5281ff4a02 | 113 | &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \ |
AnnaBridge | 161:aa5281ff4a02 | 114 | } \ |
AnnaBridge | 161:aa5281ff4a02 | 115 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
AnnaBridge | 161:aa5281ff4a02 | 116 | #define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 117 | #define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 118 | #define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 119 | #define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 120 | |
AnnaBridge | 161:aa5281ff4a02 | 121 | |
AnnaBridge | 161:aa5281ff4a02 | 122 | |
AnnaBridge | 161:aa5281ff4a02 | 123 | |
AnnaBridge | 161:aa5281ff4a02 | 124 | /* Channel array defines of VDC50_FROM_ADJ0_UPDATE_ARRAY */ |
AnnaBridge | 161:aa5281ff4a02 | 125 | /*(Sample) value = VDC50_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */ |
AnnaBridge | 161:aa5281ff4a02 | 126 | #define VDC50_FROM_ADJ0_UPDATE_ARRAY_COUNT (2) |
AnnaBridge | 161:aa5281ff4a02 | 127 | #define VDC50_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \ |
AnnaBridge | 161:aa5281ff4a02 | 128 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
AnnaBridge | 161:aa5281ff4a02 | 129 | { \ |
AnnaBridge | 161:aa5281ff4a02 | 130 | &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \ |
AnnaBridge | 161:aa5281ff4a02 | 131 | &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \ |
AnnaBridge | 161:aa5281ff4a02 | 132 | } \ |
AnnaBridge | 161:aa5281ff4a02 | 133 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
AnnaBridge | 161:aa5281ff4a02 | 134 | #define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 135 | #define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 136 | #define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 137 | #define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 138 | |
AnnaBridge | 161:aa5281ff4a02 | 139 | |
AnnaBridge | 161:aa5281ff4a02 | 140 | |
AnnaBridge | 161:aa5281ff4a02 | 141 | |
AnnaBridge | 161:aa5281ff4a02 | 142 | /* Channel array defines of VDC50_FROM_GR0_AB7_ARRAY */ |
AnnaBridge | 161:aa5281ff4a02 | 143 | /*(Sample) value = VDC50_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ |
AnnaBridge | 161:aa5281ff4a02 | 144 | #define VDC50_FROM_GR0_AB7_ARRAY_COUNT (2) |
AnnaBridge | 161:aa5281ff4a02 | 145 | #define VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \ |
AnnaBridge | 161:aa5281ff4a02 | 146 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
AnnaBridge | 161:aa5281ff4a02 | 147 | { \ |
AnnaBridge | 161:aa5281ff4a02 | 148 | &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \ |
AnnaBridge | 161:aa5281ff4a02 | 149 | &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \ |
AnnaBridge | 161:aa5281ff4a02 | 150 | } \ |
AnnaBridge | 161:aa5281ff4a02 | 151 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
AnnaBridge | 161:aa5281ff4a02 | 152 | #define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */ |
AnnaBridge | 161:aa5281ff4a02 | 153 | #define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */ |
AnnaBridge | 161:aa5281ff4a02 | 154 | #define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */ |
AnnaBridge | 161:aa5281ff4a02 | 155 | #define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */ |
AnnaBridge | 161:aa5281ff4a02 | 156 | |
AnnaBridge | 161:aa5281ff4a02 | 157 | |
AnnaBridge | 161:aa5281ff4a02 | 158 | |
AnnaBridge | 161:aa5281ff4a02 | 159 | |
AnnaBridge | 161:aa5281ff4a02 | 160 | /* Channel array defines of VDC50_FROM_GR0_UPDATE_ARRAY */ |
AnnaBridge | 161:aa5281ff4a02 | 161 | /*(Sample) value = VDC50_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ |
AnnaBridge | 161:aa5281ff4a02 | 162 | #define VDC50_FROM_GR0_UPDATE_ARRAY_COUNT (2) |
AnnaBridge | 161:aa5281ff4a02 | 163 | #define VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \ |
AnnaBridge | 161:aa5281ff4a02 | 164 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
AnnaBridge | 161:aa5281ff4a02 | 165 | { \ |
AnnaBridge | 161:aa5281ff4a02 | 166 | &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \ |
AnnaBridge | 161:aa5281ff4a02 | 167 | &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \ |
AnnaBridge | 161:aa5281ff4a02 | 168 | } \ |
AnnaBridge | 161:aa5281ff4a02 | 169 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
AnnaBridge | 161:aa5281ff4a02 | 170 | #define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 171 | #define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 172 | #define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 173 | #define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 174 | |
AnnaBridge | 161:aa5281ff4a02 | 175 | |
AnnaBridge | 161:aa5281ff4a02 | 176 | /* End of channel array defines of VDC5 */ |
AnnaBridge | 161:aa5281ff4a02 | 177 | |
AnnaBridge | 161:aa5281ff4a02 | 178 | |
AnnaBridge | 161:aa5281ff4a02 | 179 | #define VDC50INP_UPDATE (VDC50.INP_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 180 | #define VDC50INP_SEL_CNT (VDC50.INP_SEL_CNT) |
AnnaBridge | 161:aa5281ff4a02 | 181 | #define VDC50INP_EXT_SYNC_CNT (VDC50.INP_EXT_SYNC_CNT) |
AnnaBridge | 161:aa5281ff4a02 | 182 | #define VDC50INP_VSYNC_PH_ADJ (VDC50.INP_VSYNC_PH_ADJ) |
AnnaBridge | 161:aa5281ff4a02 | 183 | #define VDC50INP_DLY_ADJ (VDC50.INP_DLY_ADJ) |
AnnaBridge | 161:aa5281ff4a02 | 184 | #define VDC50IMGCNT_UPDATE (VDC50.IMGCNT_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 185 | #define VDC50IMGCNT_NR_CNT0 (VDC50.IMGCNT_NR_CNT0) |
AnnaBridge | 161:aa5281ff4a02 | 186 | #define VDC50IMGCNT_NR_CNT1 (VDC50.IMGCNT_NR_CNT1) |
AnnaBridge | 161:aa5281ff4a02 | 187 | #define VDC50IMGCNT_MTX_MODE (VDC50.IMGCNT_MTX_MODE) |
AnnaBridge | 161:aa5281ff4a02 | 188 | #define VDC50IMGCNT_MTX_YG_ADJ0 (VDC50.IMGCNT_MTX_YG_ADJ0) |
AnnaBridge | 161:aa5281ff4a02 | 189 | #define VDC50IMGCNT_MTX_YG_ADJ1 (VDC50.IMGCNT_MTX_YG_ADJ1) |
AnnaBridge | 161:aa5281ff4a02 | 190 | #define VDC50IMGCNT_MTX_CBB_ADJ0 (VDC50.IMGCNT_MTX_CBB_ADJ0) |
AnnaBridge | 161:aa5281ff4a02 | 191 | #define VDC50IMGCNT_MTX_CBB_ADJ1 (VDC50.IMGCNT_MTX_CBB_ADJ1) |
AnnaBridge | 161:aa5281ff4a02 | 192 | #define VDC50IMGCNT_MTX_CRR_ADJ0 (VDC50.IMGCNT_MTX_CRR_ADJ0) |
AnnaBridge | 161:aa5281ff4a02 | 193 | #define VDC50IMGCNT_MTX_CRR_ADJ1 (VDC50.IMGCNT_MTX_CRR_ADJ1) |
AnnaBridge | 161:aa5281ff4a02 | 194 | #define VDC50IMGCNT_DRC_REG (VDC50.IMGCNT_DRC_REG) |
AnnaBridge | 161:aa5281ff4a02 | 195 | #define VDC50SC0_SCL0_UPDATE (VDC50.SC0_SCL0_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 196 | #define VDC50SC0_SCL0_FRC1 (VDC50.SC0_SCL0_FRC1) |
AnnaBridge | 161:aa5281ff4a02 | 197 | #define VDC50SC0_SCL0_FRC2 (VDC50.SC0_SCL0_FRC2) |
AnnaBridge | 161:aa5281ff4a02 | 198 | #define VDC50SC0_SCL0_FRC3 (VDC50.SC0_SCL0_FRC3) |
AnnaBridge | 161:aa5281ff4a02 | 199 | #define VDC50SC0_SCL0_FRC4 (VDC50.SC0_SCL0_FRC4) |
AnnaBridge | 161:aa5281ff4a02 | 200 | #define VDC50SC0_SCL0_FRC5 (VDC50.SC0_SCL0_FRC5) |
AnnaBridge | 161:aa5281ff4a02 | 201 | #define VDC50SC0_SCL0_FRC6 (VDC50.SC0_SCL0_FRC6) |
AnnaBridge | 161:aa5281ff4a02 | 202 | #define VDC50SC0_SCL0_FRC7 (VDC50.SC0_SCL0_FRC7) |
AnnaBridge | 161:aa5281ff4a02 | 203 | #define VDC50SC0_SCL0_FRC9 (VDC50.SC0_SCL0_FRC9) |
AnnaBridge | 161:aa5281ff4a02 | 204 | #define VDC50SC0_SCL0_MON0 (VDC50.SC0_SCL0_MON0) |
AnnaBridge | 161:aa5281ff4a02 | 205 | #define VDC50SC0_SCL0_INT (VDC50.SC0_SCL0_INT) |
AnnaBridge | 161:aa5281ff4a02 | 206 | #define VDC50SC0_SCL0_DS1 (VDC50.SC0_SCL0_DS1) |
AnnaBridge | 161:aa5281ff4a02 | 207 | #define VDC50SC0_SCL0_DS2 (VDC50.SC0_SCL0_DS2) |
AnnaBridge | 161:aa5281ff4a02 | 208 | #define VDC50SC0_SCL0_DS3 (VDC50.SC0_SCL0_DS3) |
AnnaBridge | 161:aa5281ff4a02 | 209 | #define VDC50SC0_SCL0_DS4 (VDC50.SC0_SCL0_DS4) |
AnnaBridge | 161:aa5281ff4a02 | 210 | #define VDC50SC0_SCL0_DS5 (VDC50.SC0_SCL0_DS5) |
AnnaBridge | 161:aa5281ff4a02 | 211 | #define VDC50SC0_SCL0_DS6 (VDC50.SC0_SCL0_DS6) |
AnnaBridge | 161:aa5281ff4a02 | 212 | #define VDC50SC0_SCL0_DS7 (VDC50.SC0_SCL0_DS7) |
AnnaBridge | 161:aa5281ff4a02 | 213 | #define VDC50SC0_SCL0_US1 (VDC50.SC0_SCL0_US1) |
AnnaBridge | 161:aa5281ff4a02 | 214 | #define VDC50SC0_SCL0_US2 (VDC50.SC0_SCL0_US2) |
AnnaBridge | 161:aa5281ff4a02 | 215 | #define VDC50SC0_SCL0_US3 (VDC50.SC0_SCL0_US3) |
AnnaBridge | 161:aa5281ff4a02 | 216 | #define VDC50SC0_SCL0_US4 (VDC50.SC0_SCL0_US4) |
AnnaBridge | 161:aa5281ff4a02 | 217 | #define VDC50SC0_SCL0_US5 (VDC50.SC0_SCL0_US5) |
AnnaBridge | 161:aa5281ff4a02 | 218 | #define VDC50SC0_SCL0_US6 (VDC50.SC0_SCL0_US6) |
AnnaBridge | 161:aa5281ff4a02 | 219 | #define VDC50SC0_SCL0_US7 (VDC50.SC0_SCL0_US7) |
AnnaBridge | 161:aa5281ff4a02 | 220 | #define VDC50SC0_SCL0_US8 (VDC50.SC0_SCL0_US8) |
AnnaBridge | 161:aa5281ff4a02 | 221 | #define VDC50SC0_SCL0_OVR1 (VDC50.SC0_SCL0_OVR1) |
AnnaBridge | 161:aa5281ff4a02 | 222 | #define VDC50SC0_SCL1_UPDATE (VDC50.SC0_SCL1_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 223 | #define VDC50SC0_SCL1_WR1 (VDC50.SC0_SCL1_WR1) |
AnnaBridge | 161:aa5281ff4a02 | 224 | #define VDC50SC0_SCL1_WR2 (VDC50.SC0_SCL1_WR2) |
AnnaBridge | 161:aa5281ff4a02 | 225 | #define VDC50SC0_SCL1_WR3 (VDC50.SC0_SCL1_WR3) |
AnnaBridge | 161:aa5281ff4a02 | 226 | #define VDC50SC0_SCL1_WR4 (VDC50.SC0_SCL1_WR4) |
AnnaBridge | 161:aa5281ff4a02 | 227 | #define VDC50SC0_SCL1_WR5 (VDC50.SC0_SCL1_WR5) |
AnnaBridge | 161:aa5281ff4a02 | 228 | #define VDC50SC0_SCL1_WR6 (VDC50.SC0_SCL1_WR6) |
AnnaBridge | 161:aa5281ff4a02 | 229 | #define VDC50SC0_SCL1_WR7 (VDC50.SC0_SCL1_WR7) |
AnnaBridge | 161:aa5281ff4a02 | 230 | #define VDC50SC0_SCL1_WR8 (VDC50.SC0_SCL1_WR8) |
AnnaBridge | 161:aa5281ff4a02 | 231 | #define VDC50SC0_SCL1_WR9 (VDC50.SC0_SCL1_WR9) |
AnnaBridge | 161:aa5281ff4a02 | 232 | #define VDC50SC0_SCL1_WR10 (VDC50.SC0_SCL1_WR10) |
AnnaBridge | 161:aa5281ff4a02 | 233 | #define VDC50SC0_SCL1_WR11 (VDC50.SC0_SCL1_WR11) |
AnnaBridge | 161:aa5281ff4a02 | 234 | #define VDC50SC0_SCL1_MON1 (VDC50.SC0_SCL1_MON1) |
AnnaBridge | 161:aa5281ff4a02 | 235 | #define VDC50SC0_SCL1_PBUF0 (VDC50.SC0_SCL1_PBUF0) |
AnnaBridge | 161:aa5281ff4a02 | 236 | #define VDC50SC0_SCL1_PBUF1 (VDC50.SC0_SCL1_PBUF1) |
AnnaBridge | 161:aa5281ff4a02 | 237 | #define VDC50SC0_SCL1_PBUF2 (VDC50.SC0_SCL1_PBUF2) |
AnnaBridge | 161:aa5281ff4a02 | 238 | #define VDC50SC0_SCL1_PBUF3 (VDC50.SC0_SCL1_PBUF3) |
AnnaBridge | 161:aa5281ff4a02 | 239 | #define VDC50SC0_SCL1_PBUF_FLD (VDC50.SC0_SCL1_PBUF_FLD) |
AnnaBridge | 161:aa5281ff4a02 | 240 | #define VDC50SC0_SCL1_PBUF_CNT (VDC50.SC0_SCL1_PBUF_CNT) |
AnnaBridge | 161:aa5281ff4a02 | 241 | #define VDC50GR0_UPDATE (VDC50.GR0_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 242 | #define VDC50GR0_FLM_RD (VDC50.GR0_FLM_RD) |
AnnaBridge | 161:aa5281ff4a02 | 243 | #define VDC50GR0_FLM1 (VDC50.GR0_FLM1) |
AnnaBridge | 161:aa5281ff4a02 | 244 | #define VDC50GR0_FLM2 (VDC50.GR0_FLM2) |
AnnaBridge | 161:aa5281ff4a02 | 245 | #define VDC50GR0_FLM3 (VDC50.GR0_FLM3) |
AnnaBridge | 161:aa5281ff4a02 | 246 | #define VDC50GR0_FLM4 (VDC50.GR0_FLM4) |
AnnaBridge | 161:aa5281ff4a02 | 247 | #define VDC50GR0_FLM5 (VDC50.GR0_FLM5) |
AnnaBridge | 161:aa5281ff4a02 | 248 | #define VDC50GR0_FLM6 (VDC50.GR0_FLM6) |
AnnaBridge | 161:aa5281ff4a02 | 249 | #define VDC50GR0_AB1 (VDC50.GR0_AB1) |
AnnaBridge | 161:aa5281ff4a02 | 250 | #define VDC50GR0_AB2 (VDC50.GR0_AB2) |
AnnaBridge | 161:aa5281ff4a02 | 251 | #define VDC50GR0_AB3 (VDC50.GR0_AB3) |
AnnaBridge | 161:aa5281ff4a02 | 252 | #define VDC50GR0_AB7 (VDC50.GR0_AB7) |
AnnaBridge | 161:aa5281ff4a02 | 253 | #define VDC50GR0_AB8 (VDC50.GR0_AB8) |
AnnaBridge | 161:aa5281ff4a02 | 254 | #define VDC50GR0_AB9 (VDC50.GR0_AB9) |
AnnaBridge | 161:aa5281ff4a02 | 255 | #define VDC50GR0_AB10 (VDC50.GR0_AB10) |
AnnaBridge | 161:aa5281ff4a02 | 256 | #define VDC50GR0_AB11 (VDC50.GR0_AB11) |
AnnaBridge | 161:aa5281ff4a02 | 257 | #define VDC50GR0_BASE (VDC50.GR0_BASE) |
AnnaBridge | 161:aa5281ff4a02 | 258 | #define VDC50GR0_CLUT (VDC50.GR0_CLUT) |
AnnaBridge | 161:aa5281ff4a02 | 259 | #define VDC50ADJ0_UPDATE (VDC50.ADJ0_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 260 | #define VDC50ADJ0_BKSTR_SET (VDC50.ADJ0_BKSTR_SET) |
AnnaBridge | 161:aa5281ff4a02 | 261 | #define VDC50ADJ0_ENH_TIM1 (VDC50.ADJ0_ENH_TIM1) |
AnnaBridge | 161:aa5281ff4a02 | 262 | #define VDC50ADJ0_ENH_TIM2 (VDC50.ADJ0_ENH_TIM2) |
AnnaBridge | 161:aa5281ff4a02 | 263 | #define VDC50ADJ0_ENH_TIM3 (VDC50.ADJ0_ENH_TIM3) |
AnnaBridge | 161:aa5281ff4a02 | 264 | #define VDC50ADJ0_ENH_SHP1 (VDC50.ADJ0_ENH_SHP1) |
AnnaBridge | 161:aa5281ff4a02 | 265 | #define VDC50ADJ0_ENH_SHP2 (VDC50.ADJ0_ENH_SHP2) |
AnnaBridge | 161:aa5281ff4a02 | 266 | #define VDC50ADJ0_ENH_SHP3 (VDC50.ADJ0_ENH_SHP3) |
AnnaBridge | 161:aa5281ff4a02 | 267 | #define VDC50ADJ0_ENH_SHP4 (VDC50.ADJ0_ENH_SHP4) |
AnnaBridge | 161:aa5281ff4a02 | 268 | #define VDC50ADJ0_ENH_SHP5 (VDC50.ADJ0_ENH_SHP5) |
AnnaBridge | 161:aa5281ff4a02 | 269 | #define VDC50ADJ0_ENH_SHP6 (VDC50.ADJ0_ENH_SHP6) |
AnnaBridge | 161:aa5281ff4a02 | 270 | #define VDC50ADJ0_ENH_LTI1 (VDC50.ADJ0_ENH_LTI1) |
AnnaBridge | 161:aa5281ff4a02 | 271 | #define VDC50ADJ0_ENH_LTI2 (VDC50.ADJ0_ENH_LTI2) |
AnnaBridge | 161:aa5281ff4a02 | 272 | #define VDC50ADJ0_MTX_MODE (VDC50.ADJ0_MTX_MODE) |
AnnaBridge | 161:aa5281ff4a02 | 273 | #define VDC50ADJ0_MTX_YG_ADJ0 (VDC50.ADJ0_MTX_YG_ADJ0) |
AnnaBridge | 161:aa5281ff4a02 | 274 | #define VDC50ADJ0_MTX_YG_ADJ1 (VDC50.ADJ0_MTX_YG_ADJ1) |
AnnaBridge | 161:aa5281ff4a02 | 275 | #define VDC50ADJ0_MTX_CBB_ADJ0 (VDC50.ADJ0_MTX_CBB_ADJ0) |
AnnaBridge | 161:aa5281ff4a02 | 276 | #define VDC50ADJ0_MTX_CBB_ADJ1 (VDC50.ADJ0_MTX_CBB_ADJ1) |
AnnaBridge | 161:aa5281ff4a02 | 277 | #define VDC50ADJ0_MTX_CRR_ADJ0 (VDC50.ADJ0_MTX_CRR_ADJ0) |
AnnaBridge | 161:aa5281ff4a02 | 278 | #define VDC50ADJ0_MTX_CRR_ADJ1 (VDC50.ADJ0_MTX_CRR_ADJ1) |
AnnaBridge | 161:aa5281ff4a02 | 279 | #define VDC50GR2_UPDATE (VDC50.GR2_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 280 | #define VDC50GR2_FLM_RD (VDC50.GR2_FLM_RD) |
AnnaBridge | 161:aa5281ff4a02 | 281 | #define VDC50GR2_FLM1 (VDC50.GR2_FLM1) |
AnnaBridge | 161:aa5281ff4a02 | 282 | #define VDC50GR2_FLM2 (VDC50.GR2_FLM2) |
AnnaBridge | 161:aa5281ff4a02 | 283 | #define VDC50GR2_FLM3 (VDC50.GR2_FLM3) |
AnnaBridge | 161:aa5281ff4a02 | 284 | #define VDC50GR2_FLM4 (VDC50.GR2_FLM4) |
AnnaBridge | 161:aa5281ff4a02 | 285 | #define VDC50GR2_FLM5 (VDC50.GR2_FLM5) |
AnnaBridge | 161:aa5281ff4a02 | 286 | #define VDC50GR2_FLM6 (VDC50.GR2_FLM6) |
AnnaBridge | 161:aa5281ff4a02 | 287 | #define VDC50GR2_AB1 (VDC50.GR2_AB1) |
AnnaBridge | 161:aa5281ff4a02 | 288 | #define VDC50GR2_AB2 (VDC50.GR2_AB2) |
AnnaBridge | 161:aa5281ff4a02 | 289 | #define VDC50GR2_AB3 (VDC50.GR2_AB3) |
AnnaBridge | 161:aa5281ff4a02 | 290 | #define VDC50GR2_AB4 (VDC50.GR2_AB4) |
AnnaBridge | 161:aa5281ff4a02 | 291 | #define VDC50GR2_AB5 (VDC50.GR2_AB5) |
AnnaBridge | 161:aa5281ff4a02 | 292 | #define VDC50GR2_AB6 (VDC50.GR2_AB6) |
AnnaBridge | 161:aa5281ff4a02 | 293 | #define VDC50GR2_AB7 (VDC50.GR2_AB7) |
AnnaBridge | 161:aa5281ff4a02 | 294 | #define VDC50GR2_AB8 (VDC50.GR2_AB8) |
AnnaBridge | 161:aa5281ff4a02 | 295 | #define VDC50GR2_AB9 (VDC50.GR2_AB9) |
AnnaBridge | 161:aa5281ff4a02 | 296 | #define VDC50GR2_AB10 (VDC50.GR2_AB10) |
AnnaBridge | 161:aa5281ff4a02 | 297 | #define VDC50GR2_AB11 (VDC50.GR2_AB11) |
AnnaBridge | 161:aa5281ff4a02 | 298 | #define VDC50GR2_BASE (VDC50.GR2_BASE) |
AnnaBridge | 161:aa5281ff4a02 | 299 | #define VDC50GR2_CLUT (VDC50.GR2_CLUT) |
AnnaBridge | 161:aa5281ff4a02 | 300 | #define VDC50GR2_MON (VDC50.GR2_MON) |
AnnaBridge | 161:aa5281ff4a02 | 301 | #define VDC50GR3_UPDATE (VDC50.GR3_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 302 | #define VDC50GR3_FLM_RD (VDC50.GR3_FLM_RD) |
AnnaBridge | 161:aa5281ff4a02 | 303 | #define VDC50GR3_FLM1 (VDC50.GR3_FLM1) |
AnnaBridge | 161:aa5281ff4a02 | 304 | #define VDC50GR3_FLM2 (VDC50.GR3_FLM2) |
AnnaBridge | 161:aa5281ff4a02 | 305 | #define VDC50GR3_FLM3 (VDC50.GR3_FLM3) |
AnnaBridge | 161:aa5281ff4a02 | 306 | #define VDC50GR3_FLM4 (VDC50.GR3_FLM4) |
AnnaBridge | 161:aa5281ff4a02 | 307 | #define VDC50GR3_FLM5 (VDC50.GR3_FLM5) |
AnnaBridge | 161:aa5281ff4a02 | 308 | #define VDC50GR3_FLM6 (VDC50.GR3_FLM6) |
AnnaBridge | 161:aa5281ff4a02 | 309 | #define VDC50GR3_AB1 (VDC50.GR3_AB1) |
AnnaBridge | 161:aa5281ff4a02 | 310 | #define VDC50GR3_AB2 (VDC50.GR3_AB2) |
AnnaBridge | 161:aa5281ff4a02 | 311 | #define VDC50GR3_AB3 (VDC50.GR3_AB3) |
AnnaBridge | 161:aa5281ff4a02 | 312 | #define VDC50GR3_AB4 (VDC50.GR3_AB4) |
AnnaBridge | 161:aa5281ff4a02 | 313 | #define VDC50GR3_AB5 (VDC50.GR3_AB5) |
AnnaBridge | 161:aa5281ff4a02 | 314 | #define VDC50GR3_AB6 (VDC50.GR3_AB6) |
AnnaBridge | 161:aa5281ff4a02 | 315 | #define VDC50GR3_AB7 (VDC50.GR3_AB7) |
AnnaBridge | 161:aa5281ff4a02 | 316 | #define VDC50GR3_AB8 (VDC50.GR3_AB8) |
AnnaBridge | 161:aa5281ff4a02 | 317 | #define VDC50GR3_AB9 (VDC50.GR3_AB9) |
AnnaBridge | 161:aa5281ff4a02 | 318 | #define VDC50GR3_AB10 (VDC50.GR3_AB10) |
AnnaBridge | 161:aa5281ff4a02 | 319 | #define VDC50GR3_AB11 (VDC50.GR3_AB11) |
AnnaBridge | 161:aa5281ff4a02 | 320 | #define VDC50GR3_BASE (VDC50.GR3_BASE) |
AnnaBridge | 161:aa5281ff4a02 | 321 | #define VDC50GR3_CLUT_INT (VDC50.GR3_CLUT_INT) |
AnnaBridge | 161:aa5281ff4a02 | 322 | #define VDC50GR3_MON (VDC50.GR3_MON) |
AnnaBridge | 161:aa5281ff4a02 | 323 | #define VDC50GAM_G_UPDATE (VDC50.GAM_G_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 324 | #define VDC50GAM_SW (VDC50.GAM_SW) |
AnnaBridge | 161:aa5281ff4a02 | 325 | #define VDC50GAM_G_LUT1 (VDC50.GAM_G_LUT1) |
AnnaBridge | 161:aa5281ff4a02 | 326 | #define VDC50GAM_G_LUT2 (VDC50.GAM_G_LUT2) |
AnnaBridge | 161:aa5281ff4a02 | 327 | #define VDC50GAM_G_LUT3 (VDC50.GAM_G_LUT3) |
AnnaBridge | 161:aa5281ff4a02 | 328 | #define VDC50GAM_G_LUT4 (VDC50.GAM_G_LUT4) |
AnnaBridge | 161:aa5281ff4a02 | 329 | #define VDC50GAM_G_LUT5 (VDC50.GAM_G_LUT5) |
AnnaBridge | 161:aa5281ff4a02 | 330 | #define VDC50GAM_G_LUT6 (VDC50.GAM_G_LUT6) |
AnnaBridge | 161:aa5281ff4a02 | 331 | #define VDC50GAM_G_LUT7 (VDC50.GAM_G_LUT7) |
AnnaBridge | 161:aa5281ff4a02 | 332 | #define VDC50GAM_G_LUT8 (VDC50.GAM_G_LUT8) |
AnnaBridge | 161:aa5281ff4a02 | 333 | #define VDC50GAM_G_LUT9 (VDC50.GAM_G_LUT9) |
AnnaBridge | 161:aa5281ff4a02 | 334 | #define VDC50GAM_G_LUT10 (VDC50.GAM_G_LUT10) |
AnnaBridge | 161:aa5281ff4a02 | 335 | #define VDC50GAM_G_LUT11 (VDC50.GAM_G_LUT11) |
AnnaBridge | 161:aa5281ff4a02 | 336 | #define VDC50GAM_G_LUT12 (VDC50.GAM_G_LUT12) |
AnnaBridge | 161:aa5281ff4a02 | 337 | #define VDC50GAM_G_LUT13 (VDC50.GAM_G_LUT13) |
AnnaBridge | 161:aa5281ff4a02 | 338 | #define VDC50GAM_G_LUT14 (VDC50.GAM_G_LUT14) |
AnnaBridge | 161:aa5281ff4a02 | 339 | #define VDC50GAM_G_LUT15 (VDC50.GAM_G_LUT15) |
AnnaBridge | 161:aa5281ff4a02 | 340 | #define VDC50GAM_G_LUT16 (VDC50.GAM_G_LUT16) |
AnnaBridge | 161:aa5281ff4a02 | 341 | #define VDC50GAM_G_AREA1 (VDC50.GAM_G_AREA1) |
AnnaBridge | 161:aa5281ff4a02 | 342 | #define VDC50GAM_G_AREA2 (VDC50.GAM_G_AREA2) |
AnnaBridge | 161:aa5281ff4a02 | 343 | #define VDC50GAM_G_AREA3 (VDC50.GAM_G_AREA3) |
AnnaBridge | 161:aa5281ff4a02 | 344 | #define VDC50GAM_G_AREA4 (VDC50.GAM_G_AREA4) |
AnnaBridge | 161:aa5281ff4a02 | 345 | #define VDC50GAM_G_AREA5 (VDC50.GAM_G_AREA5) |
AnnaBridge | 161:aa5281ff4a02 | 346 | #define VDC50GAM_G_AREA6 (VDC50.GAM_G_AREA6) |
AnnaBridge | 161:aa5281ff4a02 | 347 | #define VDC50GAM_G_AREA7 (VDC50.GAM_G_AREA7) |
AnnaBridge | 161:aa5281ff4a02 | 348 | #define VDC50GAM_G_AREA8 (VDC50.GAM_G_AREA8) |
AnnaBridge | 161:aa5281ff4a02 | 349 | #define VDC50GAM_B_UPDATE (VDC50.GAM_B_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 350 | #define VDC50GAM_B_LUT1 (VDC50.GAM_B_LUT1) |
AnnaBridge | 161:aa5281ff4a02 | 351 | #define VDC50GAM_B_LUT2 (VDC50.GAM_B_LUT2) |
AnnaBridge | 161:aa5281ff4a02 | 352 | #define VDC50GAM_B_LUT3 (VDC50.GAM_B_LUT3) |
AnnaBridge | 161:aa5281ff4a02 | 353 | #define VDC50GAM_B_LUT4 (VDC50.GAM_B_LUT4) |
AnnaBridge | 161:aa5281ff4a02 | 354 | #define VDC50GAM_B_LUT5 (VDC50.GAM_B_LUT5) |
AnnaBridge | 161:aa5281ff4a02 | 355 | #define VDC50GAM_B_LUT6 (VDC50.GAM_B_LUT6) |
AnnaBridge | 161:aa5281ff4a02 | 356 | #define VDC50GAM_B_LUT7 (VDC50.GAM_B_LUT7) |
AnnaBridge | 161:aa5281ff4a02 | 357 | #define VDC50GAM_B_LUT8 (VDC50.GAM_B_LUT8) |
AnnaBridge | 161:aa5281ff4a02 | 358 | #define VDC50GAM_B_LUT9 (VDC50.GAM_B_LUT9) |
AnnaBridge | 161:aa5281ff4a02 | 359 | #define VDC50GAM_B_LUT10 (VDC50.GAM_B_LUT10) |
AnnaBridge | 161:aa5281ff4a02 | 360 | #define VDC50GAM_B_LUT11 (VDC50.GAM_B_LUT11) |
AnnaBridge | 161:aa5281ff4a02 | 361 | #define VDC50GAM_B_LUT12 (VDC50.GAM_B_LUT12) |
AnnaBridge | 161:aa5281ff4a02 | 362 | #define VDC50GAM_B_LUT13 (VDC50.GAM_B_LUT13) |
AnnaBridge | 161:aa5281ff4a02 | 363 | #define VDC50GAM_B_LUT14 (VDC50.GAM_B_LUT14) |
AnnaBridge | 161:aa5281ff4a02 | 364 | #define VDC50GAM_B_LUT15 (VDC50.GAM_B_LUT15) |
AnnaBridge | 161:aa5281ff4a02 | 365 | #define VDC50GAM_B_LUT16 (VDC50.GAM_B_LUT16) |
AnnaBridge | 161:aa5281ff4a02 | 366 | #define VDC50GAM_B_AREA1 (VDC50.GAM_B_AREA1) |
AnnaBridge | 161:aa5281ff4a02 | 367 | #define VDC50GAM_B_AREA2 (VDC50.GAM_B_AREA2) |
AnnaBridge | 161:aa5281ff4a02 | 368 | #define VDC50GAM_B_AREA3 (VDC50.GAM_B_AREA3) |
AnnaBridge | 161:aa5281ff4a02 | 369 | #define VDC50GAM_B_AREA4 (VDC50.GAM_B_AREA4) |
AnnaBridge | 161:aa5281ff4a02 | 370 | #define VDC50GAM_B_AREA5 (VDC50.GAM_B_AREA5) |
AnnaBridge | 161:aa5281ff4a02 | 371 | #define VDC50GAM_B_AREA6 (VDC50.GAM_B_AREA6) |
AnnaBridge | 161:aa5281ff4a02 | 372 | #define VDC50GAM_B_AREA7 (VDC50.GAM_B_AREA7) |
AnnaBridge | 161:aa5281ff4a02 | 373 | #define VDC50GAM_B_AREA8 (VDC50.GAM_B_AREA8) |
AnnaBridge | 161:aa5281ff4a02 | 374 | #define VDC50GAM_R_UPDATE (VDC50.GAM_R_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 375 | #define VDC50GAM_R_LUT1 (VDC50.GAM_R_LUT1) |
AnnaBridge | 161:aa5281ff4a02 | 376 | #define VDC50GAM_R_LUT2 (VDC50.GAM_R_LUT2) |
AnnaBridge | 161:aa5281ff4a02 | 377 | #define VDC50GAM_R_LUT3 (VDC50.GAM_R_LUT3) |
AnnaBridge | 161:aa5281ff4a02 | 378 | #define VDC50GAM_R_LUT4 (VDC50.GAM_R_LUT4) |
AnnaBridge | 161:aa5281ff4a02 | 379 | #define VDC50GAM_R_LUT5 (VDC50.GAM_R_LUT5) |
AnnaBridge | 161:aa5281ff4a02 | 380 | #define VDC50GAM_R_LUT6 (VDC50.GAM_R_LUT6) |
AnnaBridge | 161:aa5281ff4a02 | 381 | #define VDC50GAM_R_LUT7 (VDC50.GAM_R_LUT7) |
AnnaBridge | 161:aa5281ff4a02 | 382 | #define VDC50GAM_R_LUT8 (VDC50.GAM_R_LUT8) |
AnnaBridge | 161:aa5281ff4a02 | 383 | #define VDC50GAM_R_LUT9 (VDC50.GAM_R_LUT9) |
AnnaBridge | 161:aa5281ff4a02 | 384 | #define VDC50GAM_R_LUT10 (VDC50.GAM_R_LUT10) |
AnnaBridge | 161:aa5281ff4a02 | 385 | #define VDC50GAM_R_LUT11 (VDC50.GAM_R_LUT11) |
AnnaBridge | 161:aa5281ff4a02 | 386 | #define VDC50GAM_R_LUT12 (VDC50.GAM_R_LUT12) |
AnnaBridge | 161:aa5281ff4a02 | 387 | #define VDC50GAM_R_LUT13 (VDC50.GAM_R_LUT13) |
AnnaBridge | 161:aa5281ff4a02 | 388 | #define VDC50GAM_R_LUT14 (VDC50.GAM_R_LUT14) |
AnnaBridge | 161:aa5281ff4a02 | 389 | #define VDC50GAM_R_LUT15 (VDC50.GAM_R_LUT15) |
AnnaBridge | 161:aa5281ff4a02 | 390 | #define VDC50GAM_R_LUT16 (VDC50.GAM_R_LUT16) |
AnnaBridge | 161:aa5281ff4a02 | 391 | #define VDC50GAM_R_AREA1 (VDC50.GAM_R_AREA1) |
AnnaBridge | 161:aa5281ff4a02 | 392 | #define VDC50GAM_R_AREA2 (VDC50.GAM_R_AREA2) |
AnnaBridge | 161:aa5281ff4a02 | 393 | #define VDC50GAM_R_AREA3 (VDC50.GAM_R_AREA3) |
AnnaBridge | 161:aa5281ff4a02 | 394 | #define VDC50GAM_R_AREA4 (VDC50.GAM_R_AREA4) |
AnnaBridge | 161:aa5281ff4a02 | 395 | #define VDC50GAM_R_AREA5 (VDC50.GAM_R_AREA5) |
AnnaBridge | 161:aa5281ff4a02 | 396 | #define VDC50GAM_R_AREA6 (VDC50.GAM_R_AREA6) |
AnnaBridge | 161:aa5281ff4a02 | 397 | #define VDC50GAM_R_AREA7 (VDC50.GAM_R_AREA7) |
AnnaBridge | 161:aa5281ff4a02 | 398 | #define VDC50GAM_R_AREA8 (VDC50.GAM_R_AREA8) |
AnnaBridge | 161:aa5281ff4a02 | 399 | #define VDC50TCON_UPDATE (VDC50.TCON_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 400 | #define VDC50TCON_TIM (VDC50.TCON_TIM) |
AnnaBridge | 161:aa5281ff4a02 | 401 | #define VDC50TCON_TIM_STVA1 (VDC50.TCON_TIM_STVA1) |
AnnaBridge | 161:aa5281ff4a02 | 402 | #define VDC50TCON_TIM_STVA2 (VDC50.TCON_TIM_STVA2) |
AnnaBridge | 161:aa5281ff4a02 | 403 | #define VDC50TCON_TIM_STVB1 (VDC50.TCON_TIM_STVB1) |
AnnaBridge | 161:aa5281ff4a02 | 404 | #define VDC50TCON_TIM_STVB2 (VDC50.TCON_TIM_STVB2) |
AnnaBridge | 161:aa5281ff4a02 | 405 | #define VDC50TCON_TIM_STH1 (VDC50.TCON_TIM_STH1) |
AnnaBridge | 161:aa5281ff4a02 | 406 | #define VDC50TCON_TIM_STH2 (VDC50.TCON_TIM_STH2) |
AnnaBridge | 161:aa5281ff4a02 | 407 | #define VDC50TCON_TIM_STB1 (VDC50.TCON_TIM_STB1) |
AnnaBridge | 161:aa5281ff4a02 | 408 | #define VDC50TCON_TIM_STB2 (VDC50.TCON_TIM_STB2) |
AnnaBridge | 161:aa5281ff4a02 | 409 | #define VDC50TCON_TIM_CPV1 (VDC50.TCON_TIM_CPV1) |
AnnaBridge | 161:aa5281ff4a02 | 410 | #define VDC50TCON_TIM_CPV2 (VDC50.TCON_TIM_CPV2) |
AnnaBridge | 161:aa5281ff4a02 | 411 | #define VDC50TCON_TIM_POLA1 (VDC50.TCON_TIM_POLA1) |
AnnaBridge | 161:aa5281ff4a02 | 412 | #define VDC50TCON_TIM_POLA2 (VDC50.TCON_TIM_POLA2) |
AnnaBridge | 161:aa5281ff4a02 | 413 | #define VDC50TCON_TIM_POLB1 (VDC50.TCON_TIM_POLB1) |
AnnaBridge | 161:aa5281ff4a02 | 414 | #define VDC50TCON_TIM_POLB2 (VDC50.TCON_TIM_POLB2) |
AnnaBridge | 161:aa5281ff4a02 | 415 | #define VDC50TCON_TIM_DE (VDC50.TCON_TIM_DE) |
AnnaBridge | 161:aa5281ff4a02 | 416 | #define VDC50OUT_UPDATE (VDC50.OUT_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 417 | #define VDC50OUT_SET (VDC50.OUT_SET) |
AnnaBridge | 161:aa5281ff4a02 | 418 | #define VDC50OUT_BRIGHT1 (VDC50.OUT_BRIGHT1) |
AnnaBridge | 161:aa5281ff4a02 | 419 | #define VDC50OUT_BRIGHT2 (VDC50.OUT_BRIGHT2) |
AnnaBridge | 161:aa5281ff4a02 | 420 | #define VDC50OUT_CONTRAST (VDC50.OUT_CONTRAST) |
AnnaBridge | 161:aa5281ff4a02 | 421 | #define VDC50OUT_PDTHA (VDC50.OUT_PDTHA) |
AnnaBridge | 161:aa5281ff4a02 | 422 | #define VDC50OUT_CLK_PHASE (VDC50.OUT_CLK_PHASE) |
AnnaBridge | 161:aa5281ff4a02 | 423 | #define VDC50SYSCNT_INT1 (VDC50.SYSCNT_INT1) |
AnnaBridge | 161:aa5281ff4a02 | 424 | #define VDC50SYSCNT_INT2 (VDC50.SYSCNT_INT2) |
AnnaBridge | 161:aa5281ff4a02 | 425 | #define VDC50SYSCNT_INT3 (VDC50.SYSCNT_INT3) |
AnnaBridge | 161:aa5281ff4a02 | 426 | #define VDC50SYSCNT_INT4 (VDC50.SYSCNT_INT4) |
AnnaBridge | 161:aa5281ff4a02 | 427 | #define VDC50SYSCNT_INT5 (VDC50.SYSCNT_INT5) |
AnnaBridge | 161:aa5281ff4a02 | 428 | #define VDC50SYSCNT_INT6 (VDC50.SYSCNT_INT6) |
AnnaBridge | 161:aa5281ff4a02 | 429 | #define VDC50SYSCNT_PANEL_CLK (VDC50.SYSCNT_PANEL_CLK) |
AnnaBridge | 161:aa5281ff4a02 | 430 | #define VDC50SYSCNT_CLUT (VDC50.SYSCNT_CLUT) |
AnnaBridge | 161:aa5281ff4a02 | 431 | #define VDC50SC1_SCL0_UPDATE (VDC50.SC1_SCL0_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 432 | #define VDC50SC1_SCL0_FRC1 (VDC50.SC1_SCL0_FRC1) |
AnnaBridge | 161:aa5281ff4a02 | 433 | #define VDC50SC1_SCL0_FRC2 (VDC50.SC1_SCL0_FRC2) |
AnnaBridge | 161:aa5281ff4a02 | 434 | #define VDC50SC1_SCL0_FRC3 (VDC50.SC1_SCL0_FRC3) |
AnnaBridge | 161:aa5281ff4a02 | 435 | #define VDC50SC1_SCL0_FRC4 (VDC50.SC1_SCL0_FRC4) |
AnnaBridge | 161:aa5281ff4a02 | 436 | #define VDC50SC1_SCL0_FRC5 (VDC50.SC1_SCL0_FRC5) |
AnnaBridge | 161:aa5281ff4a02 | 437 | #define VDC50SC1_SCL0_FRC6 (VDC50.SC1_SCL0_FRC6) |
AnnaBridge | 161:aa5281ff4a02 | 438 | #define VDC50SC1_SCL0_FRC7 (VDC50.SC1_SCL0_FRC7) |
AnnaBridge | 161:aa5281ff4a02 | 439 | #define VDC50SC1_SCL0_FRC9 (VDC50.SC1_SCL0_FRC9) |
AnnaBridge | 161:aa5281ff4a02 | 440 | #define VDC50SC1_SCL0_MON0 (VDC50.SC1_SCL0_MON0) |
AnnaBridge | 161:aa5281ff4a02 | 441 | #define VDC50SC1_SCL0_INT (VDC50.SC1_SCL0_INT) |
AnnaBridge | 161:aa5281ff4a02 | 442 | #define VDC50SC1_SCL0_DS1 (VDC50.SC1_SCL0_DS1) |
AnnaBridge | 161:aa5281ff4a02 | 443 | #define VDC50SC1_SCL0_DS2 (VDC50.SC1_SCL0_DS2) |
AnnaBridge | 161:aa5281ff4a02 | 444 | #define VDC50SC1_SCL0_DS3 (VDC50.SC1_SCL0_DS3) |
AnnaBridge | 161:aa5281ff4a02 | 445 | #define VDC50SC1_SCL0_DS4 (VDC50.SC1_SCL0_DS4) |
AnnaBridge | 161:aa5281ff4a02 | 446 | #define VDC50SC1_SCL0_DS5 (VDC50.SC1_SCL0_DS5) |
AnnaBridge | 161:aa5281ff4a02 | 447 | #define VDC50SC1_SCL0_DS6 (VDC50.SC1_SCL0_DS6) |
AnnaBridge | 161:aa5281ff4a02 | 448 | #define VDC50SC1_SCL0_DS7 (VDC50.SC1_SCL0_DS7) |
AnnaBridge | 161:aa5281ff4a02 | 449 | #define VDC50SC1_SCL0_US1 (VDC50.SC1_SCL0_US1) |
AnnaBridge | 161:aa5281ff4a02 | 450 | #define VDC50SC1_SCL0_US2 (VDC50.SC1_SCL0_US2) |
AnnaBridge | 161:aa5281ff4a02 | 451 | #define VDC50SC1_SCL0_US3 (VDC50.SC1_SCL0_US3) |
AnnaBridge | 161:aa5281ff4a02 | 452 | #define VDC50SC1_SCL0_US4 (VDC50.SC1_SCL0_US4) |
AnnaBridge | 161:aa5281ff4a02 | 453 | #define VDC50SC1_SCL0_US5 (VDC50.SC1_SCL0_US5) |
AnnaBridge | 161:aa5281ff4a02 | 454 | #define VDC50SC1_SCL0_US6 (VDC50.SC1_SCL0_US6) |
AnnaBridge | 161:aa5281ff4a02 | 455 | #define VDC50SC1_SCL0_US7 (VDC50.SC1_SCL0_US7) |
AnnaBridge | 161:aa5281ff4a02 | 456 | #define VDC50SC1_SCL0_US8 (VDC50.SC1_SCL0_US8) |
AnnaBridge | 161:aa5281ff4a02 | 457 | #define VDC50SC1_SCL0_OVR1 (VDC50.SC1_SCL0_OVR1) |
AnnaBridge | 161:aa5281ff4a02 | 458 | #define VDC50SC1_SCL1_UPDATE (VDC50.SC1_SCL1_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 459 | #define VDC50SC1_SCL1_WR1 (VDC50.SC1_SCL1_WR1) |
AnnaBridge | 161:aa5281ff4a02 | 460 | #define VDC50SC1_SCL1_WR2 (VDC50.SC1_SCL1_WR2) |
AnnaBridge | 161:aa5281ff4a02 | 461 | #define VDC50SC1_SCL1_WR3 (VDC50.SC1_SCL1_WR3) |
AnnaBridge | 161:aa5281ff4a02 | 462 | #define VDC50SC1_SCL1_WR4 (VDC50.SC1_SCL1_WR4) |
AnnaBridge | 161:aa5281ff4a02 | 463 | #define VDC50SC1_SCL1_WR5 (VDC50.SC1_SCL1_WR5) |
AnnaBridge | 161:aa5281ff4a02 | 464 | #define VDC50SC1_SCL1_WR6 (VDC50.SC1_SCL1_WR6) |
AnnaBridge | 161:aa5281ff4a02 | 465 | #define VDC50SC1_SCL1_WR7 (VDC50.SC1_SCL1_WR7) |
AnnaBridge | 161:aa5281ff4a02 | 466 | #define VDC50SC1_SCL1_WR8 (VDC50.SC1_SCL1_WR8) |
AnnaBridge | 161:aa5281ff4a02 | 467 | #define VDC50SC1_SCL1_WR9 (VDC50.SC1_SCL1_WR9) |
AnnaBridge | 161:aa5281ff4a02 | 468 | #define VDC50SC1_SCL1_WR10 (VDC50.SC1_SCL1_WR10) |
AnnaBridge | 161:aa5281ff4a02 | 469 | #define VDC50SC1_SCL1_WR11 (VDC50.SC1_SCL1_WR11) |
AnnaBridge | 161:aa5281ff4a02 | 470 | #define VDC50SC1_SCL1_MON1 (VDC50.SC1_SCL1_MON1) |
AnnaBridge | 161:aa5281ff4a02 | 471 | #define VDC50SC1_SCL1_PBUF0 (VDC50.SC1_SCL1_PBUF0) |
AnnaBridge | 161:aa5281ff4a02 | 472 | #define VDC50SC1_SCL1_PBUF1 (VDC50.SC1_SCL1_PBUF1) |
AnnaBridge | 161:aa5281ff4a02 | 473 | #define VDC50SC1_SCL1_PBUF2 (VDC50.SC1_SCL1_PBUF2) |
AnnaBridge | 161:aa5281ff4a02 | 474 | #define VDC50SC1_SCL1_PBUF3 (VDC50.SC1_SCL1_PBUF3) |
AnnaBridge | 161:aa5281ff4a02 | 475 | #define VDC50SC1_SCL1_PBUF_FLD (VDC50.SC1_SCL1_PBUF_FLD) |
AnnaBridge | 161:aa5281ff4a02 | 476 | #define VDC50SC1_SCL1_PBUF_CNT (VDC50.SC1_SCL1_PBUF_CNT) |
AnnaBridge | 161:aa5281ff4a02 | 477 | #define VDC50GR1_UPDATE (VDC50.GR1_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 478 | #define VDC50GR1_FLM_RD (VDC50.GR1_FLM_RD) |
AnnaBridge | 161:aa5281ff4a02 | 479 | #define VDC50GR1_FLM1 (VDC50.GR1_FLM1) |
AnnaBridge | 161:aa5281ff4a02 | 480 | #define VDC50GR1_FLM2 (VDC50.GR1_FLM2) |
AnnaBridge | 161:aa5281ff4a02 | 481 | #define VDC50GR1_FLM3 (VDC50.GR1_FLM3) |
AnnaBridge | 161:aa5281ff4a02 | 482 | #define VDC50GR1_FLM4 (VDC50.GR1_FLM4) |
AnnaBridge | 161:aa5281ff4a02 | 483 | #define VDC50GR1_FLM5 (VDC50.GR1_FLM5) |
AnnaBridge | 161:aa5281ff4a02 | 484 | #define VDC50GR1_FLM6 (VDC50.GR1_FLM6) |
AnnaBridge | 161:aa5281ff4a02 | 485 | #define VDC50GR1_AB1 (VDC50.GR1_AB1) |
AnnaBridge | 161:aa5281ff4a02 | 486 | #define VDC50GR1_AB2 (VDC50.GR1_AB2) |
AnnaBridge | 161:aa5281ff4a02 | 487 | #define VDC50GR1_AB3 (VDC50.GR1_AB3) |
AnnaBridge | 161:aa5281ff4a02 | 488 | #define VDC50GR1_AB4 (VDC50.GR1_AB4) |
AnnaBridge | 161:aa5281ff4a02 | 489 | #define VDC50GR1_AB5 (VDC50.GR1_AB5) |
AnnaBridge | 161:aa5281ff4a02 | 490 | #define VDC50GR1_AB6 (VDC50.GR1_AB6) |
AnnaBridge | 161:aa5281ff4a02 | 491 | #define VDC50GR1_AB7 (VDC50.GR1_AB7) |
AnnaBridge | 161:aa5281ff4a02 | 492 | #define VDC50GR1_AB8 (VDC50.GR1_AB8) |
AnnaBridge | 161:aa5281ff4a02 | 493 | #define VDC50GR1_AB9 (VDC50.GR1_AB9) |
AnnaBridge | 161:aa5281ff4a02 | 494 | #define VDC50GR1_AB10 (VDC50.GR1_AB10) |
AnnaBridge | 161:aa5281ff4a02 | 495 | #define VDC50GR1_AB11 (VDC50.GR1_AB11) |
AnnaBridge | 161:aa5281ff4a02 | 496 | #define VDC50GR1_BASE (VDC50.GR1_BASE) |
AnnaBridge | 161:aa5281ff4a02 | 497 | #define VDC50GR1_CLUT (VDC50.GR1_CLUT) |
AnnaBridge | 161:aa5281ff4a02 | 498 | #define VDC50GR1_MON (VDC50.GR1_MON) |
AnnaBridge | 161:aa5281ff4a02 | 499 | #define VDC50ADJ1_UPDATE (VDC50.ADJ1_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 500 | #define VDC50ADJ1_BKSTR_SET (VDC50.ADJ1_BKSTR_SET) |
AnnaBridge | 161:aa5281ff4a02 | 501 | #define VDC50ADJ1_ENH_TIM1 (VDC50.ADJ1_ENH_TIM1) |
AnnaBridge | 161:aa5281ff4a02 | 502 | #define VDC50ADJ1_ENH_TIM2 (VDC50.ADJ1_ENH_TIM2) |
AnnaBridge | 161:aa5281ff4a02 | 503 | #define VDC50ADJ1_ENH_TIM3 (VDC50.ADJ1_ENH_TIM3) |
AnnaBridge | 161:aa5281ff4a02 | 504 | #define VDC50ADJ1_ENH_SHP1 (VDC50.ADJ1_ENH_SHP1) |
AnnaBridge | 161:aa5281ff4a02 | 505 | #define VDC50ADJ1_ENH_SHP2 (VDC50.ADJ1_ENH_SHP2) |
AnnaBridge | 161:aa5281ff4a02 | 506 | #define VDC50ADJ1_ENH_SHP3 (VDC50.ADJ1_ENH_SHP3) |
AnnaBridge | 161:aa5281ff4a02 | 507 | #define VDC50ADJ1_ENH_SHP4 (VDC50.ADJ1_ENH_SHP4) |
AnnaBridge | 161:aa5281ff4a02 | 508 | #define VDC50ADJ1_ENH_SHP5 (VDC50.ADJ1_ENH_SHP5) |
AnnaBridge | 161:aa5281ff4a02 | 509 | #define VDC50ADJ1_ENH_SHP6 (VDC50.ADJ1_ENH_SHP6) |
AnnaBridge | 161:aa5281ff4a02 | 510 | #define VDC50ADJ1_ENH_LTI1 (VDC50.ADJ1_ENH_LTI1) |
AnnaBridge | 161:aa5281ff4a02 | 511 | #define VDC50ADJ1_ENH_LTI2 (VDC50.ADJ1_ENH_LTI2) |
AnnaBridge | 161:aa5281ff4a02 | 512 | #define VDC50ADJ1_MTX_MODE (VDC50.ADJ1_MTX_MODE) |
AnnaBridge | 161:aa5281ff4a02 | 513 | #define VDC50ADJ1_MTX_YG_ADJ0 (VDC50.ADJ1_MTX_YG_ADJ0) |
AnnaBridge | 161:aa5281ff4a02 | 514 | #define VDC50ADJ1_MTX_YG_ADJ1 (VDC50.ADJ1_MTX_YG_ADJ1) |
AnnaBridge | 161:aa5281ff4a02 | 515 | #define VDC50ADJ1_MTX_CBB_ADJ0 (VDC50.ADJ1_MTX_CBB_ADJ0) |
AnnaBridge | 161:aa5281ff4a02 | 516 | #define VDC50ADJ1_MTX_CBB_ADJ1 (VDC50.ADJ1_MTX_CBB_ADJ1) |
AnnaBridge | 161:aa5281ff4a02 | 517 | #define VDC50ADJ1_MTX_CRR_ADJ0 (VDC50.ADJ1_MTX_CRR_ADJ0) |
AnnaBridge | 161:aa5281ff4a02 | 518 | #define VDC50ADJ1_MTX_CRR_ADJ1 (VDC50.ADJ1_MTX_CRR_ADJ1) |
AnnaBridge | 161:aa5281ff4a02 | 519 | #define VDC50GR_VIN_UPDATE (VDC50.GR_VIN_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 520 | #define VDC50GR_VIN_AB1 (VDC50.GR_VIN_AB1) |
AnnaBridge | 161:aa5281ff4a02 | 521 | #define VDC50GR_VIN_AB2 (VDC50.GR_VIN_AB2) |
AnnaBridge | 161:aa5281ff4a02 | 522 | #define VDC50GR_VIN_AB3 (VDC50.GR_VIN_AB3) |
AnnaBridge | 161:aa5281ff4a02 | 523 | #define VDC50GR_VIN_AB4 (VDC50.GR_VIN_AB4) |
AnnaBridge | 161:aa5281ff4a02 | 524 | #define VDC50GR_VIN_AB5 (VDC50.GR_VIN_AB5) |
AnnaBridge | 161:aa5281ff4a02 | 525 | #define VDC50GR_VIN_AB6 (VDC50.GR_VIN_AB6) |
AnnaBridge | 161:aa5281ff4a02 | 526 | #define VDC50GR_VIN_AB7 (VDC50.GR_VIN_AB7) |
AnnaBridge | 161:aa5281ff4a02 | 527 | #define VDC50GR_VIN_BASE (VDC50.GR_VIN_BASE) |
AnnaBridge | 161:aa5281ff4a02 | 528 | #define VDC50GR_VIN_MON (VDC50.GR_VIN_MON) |
AnnaBridge | 161:aa5281ff4a02 | 529 | #define VDC50OIR_SCL0_UPDATE (VDC50.OIR_SCL0_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 530 | #define VDC50OIR_SCL0_FRC1 (VDC50.OIR_SCL0_FRC1) |
AnnaBridge | 161:aa5281ff4a02 | 531 | #define VDC50OIR_SCL0_FRC2 (VDC50.OIR_SCL0_FRC2) |
AnnaBridge | 161:aa5281ff4a02 | 532 | #define VDC50OIR_SCL0_FRC3 (VDC50.OIR_SCL0_FRC3) |
AnnaBridge | 161:aa5281ff4a02 | 533 | #define VDC50OIR_SCL0_FRC4 (VDC50.OIR_SCL0_FRC4) |
AnnaBridge | 161:aa5281ff4a02 | 534 | #define VDC50OIR_SCL0_FRC5 (VDC50.OIR_SCL0_FRC5) |
AnnaBridge | 161:aa5281ff4a02 | 535 | #define VDC50OIR_SCL0_FRC6 (VDC50.OIR_SCL0_FRC6) |
AnnaBridge | 161:aa5281ff4a02 | 536 | #define VDC50OIR_SCL0_FRC7 (VDC50.OIR_SCL0_FRC7) |
AnnaBridge | 161:aa5281ff4a02 | 537 | #define VDC50OIR_SCL0_DS1 (VDC50.OIR_SCL0_DS1) |
AnnaBridge | 161:aa5281ff4a02 | 538 | #define VDC50OIR_SCL0_DS2 (VDC50.OIR_SCL0_DS2) |
AnnaBridge | 161:aa5281ff4a02 | 539 | #define VDC50OIR_SCL0_DS3 (VDC50.OIR_SCL0_DS3) |
AnnaBridge | 161:aa5281ff4a02 | 540 | #define VDC50OIR_SCL0_DS7 (VDC50.OIR_SCL0_DS7) |
AnnaBridge | 161:aa5281ff4a02 | 541 | #define VDC50OIR_SCL0_US1 (VDC50.OIR_SCL0_US1) |
AnnaBridge | 161:aa5281ff4a02 | 542 | #define VDC50OIR_SCL0_US2 (VDC50.OIR_SCL0_US2) |
AnnaBridge | 161:aa5281ff4a02 | 543 | #define VDC50OIR_SCL0_US3 (VDC50.OIR_SCL0_US3) |
AnnaBridge | 161:aa5281ff4a02 | 544 | #define VDC50OIR_SCL0_US8 (VDC50.OIR_SCL0_US8) |
AnnaBridge | 161:aa5281ff4a02 | 545 | #define VDC50OIR_SCL0_OVR1 (VDC50.OIR_SCL0_OVR1) |
AnnaBridge | 161:aa5281ff4a02 | 546 | #define VDC50OIR_SCL1_UPDATE (VDC50.OIR_SCL1_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 547 | #define VDC50OIR_SCL1_WR1 (VDC50.OIR_SCL1_WR1) |
AnnaBridge | 161:aa5281ff4a02 | 548 | #define VDC50OIR_SCL1_WR2 (VDC50.OIR_SCL1_WR2) |
AnnaBridge | 161:aa5281ff4a02 | 549 | #define VDC50OIR_SCL1_WR3 (VDC50.OIR_SCL1_WR3) |
AnnaBridge | 161:aa5281ff4a02 | 550 | #define VDC50OIR_SCL1_WR4 (VDC50.OIR_SCL1_WR4) |
AnnaBridge | 161:aa5281ff4a02 | 551 | #define VDC50OIR_SCL1_WR5 (VDC50.OIR_SCL1_WR5) |
AnnaBridge | 161:aa5281ff4a02 | 552 | #define VDC50OIR_SCL1_WR6 (VDC50.OIR_SCL1_WR6) |
AnnaBridge | 161:aa5281ff4a02 | 553 | #define VDC50OIR_SCL1_WR7 (VDC50.OIR_SCL1_WR7) |
AnnaBridge | 161:aa5281ff4a02 | 554 | #define VDC50GR_OIR_UPDATE (VDC50.GR_OIR_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 555 | #define VDC50GR_OIR_FLM_RD (VDC50.GR_OIR_FLM_RD) |
AnnaBridge | 161:aa5281ff4a02 | 556 | #define VDC50GR_OIR_FLM1 (VDC50.GR_OIR_FLM1) |
AnnaBridge | 161:aa5281ff4a02 | 557 | #define VDC50GR_OIR_FLM2 (VDC50.GR_OIR_FLM2) |
AnnaBridge | 161:aa5281ff4a02 | 558 | #define VDC50GR_OIR_FLM3 (VDC50.GR_OIR_FLM3) |
AnnaBridge | 161:aa5281ff4a02 | 559 | #define VDC50GR_OIR_FLM4 (VDC50.GR_OIR_FLM4) |
AnnaBridge | 161:aa5281ff4a02 | 560 | #define VDC50GR_OIR_FLM5 (VDC50.GR_OIR_FLM5) |
AnnaBridge | 161:aa5281ff4a02 | 561 | #define VDC50GR_OIR_FLM6 (VDC50.GR_OIR_FLM6) |
AnnaBridge | 161:aa5281ff4a02 | 562 | #define VDC50GR_OIR_AB1 (VDC50.GR_OIR_AB1) |
AnnaBridge | 161:aa5281ff4a02 | 563 | #define VDC50GR_OIR_AB2 (VDC50.GR_OIR_AB2) |
AnnaBridge | 161:aa5281ff4a02 | 564 | #define VDC50GR_OIR_AB3 (VDC50.GR_OIR_AB3) |
AnnaBridge | 161:aa5281ff4a02 | 565 | #define VDC50GR_OIR_AB7 (VDC50.GR_OIR_AB7) |
AnnaBridge | 161:aa5281ff4a02 | 566 | #define VDC50GR_OIR_AB8 (VDC50.GR_OIR_AB8) |
AnnaBridge | 161:aa5281ff4a02 | 567 | #define VDC50GR_OIR_AB9 (VDC50.GR_OIR_AB9) |
AnnaBridge | 161:aa5281ff4a02 | 568 | #define VDC50GR_OIR_AB10 (VDC50.GR_OIR_AB10) |
AnnaBridge | 161:aa5281ff4a02 | 569 | #define VDC50GR_OIR_AB11 (VDC50.GR_OIR_AB11) |
AnnaBridge | 161:aa5281ff4a02 | 570 | #define VDC50GR_OIR_BASE (VDC50.GR_OIR_BASE) |
AnnaBridge | 161:aa5281ff4a02 | 571 | #define VDC50GR_OIR_CLUT (VDC50.GR_OIR_CLUT) |
AnnaBridge | 161:aa5281ff4a02 | 572 | #define VDC50GR_OIR_MON (VDC50.GR_OIR_MON) |
AnnaBridge | 161:aa5281ff4a02 | 573 | #define VDC51INP_UPDATE (VDC51.INP_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 574 | #define VDC51INP_SEL_CNT (VDC51.INP_SEL_CNT) |
AnnaBridge | 161:aa5281ff4a02 | 575 | #define VDC51INP_EXT_SYNC_CNT (VDC51.INP_EXT_SYNC_CNT) |
AnnaBridge | 161:aa5281ff4a02 | 576 | #define VDC51INP_VSYNC_PH_ADJ (VDC51.INP_VSYNC_PH_ADJ) |
AnnaBridge | 161:aa5281ff4a02 | 577 | #define VDC51INP_DLY_ADJ (VDC51.INP_DLY_ADJ) |
AnnaBridge | 161:aa5281ff4a02 | 578 | #define VDC51IMGCNT_UPDATE (VDC51.IMGCNT_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 579 | #define VDC51IMGCNT_NR_CNT0 (VDC51.IMGCNT_NR_CNT0) |
AnnaBridge | 161:aa5281ff4a02 | 580 | #define VDC51IMGCNT_NR_CNT1 (VDC51.IMGCNT_NR_CNT1) |
AnnaBridge | 161:aa5281ff4a02 | 581 | #define VDC51IMGCNT_MTX_MODE (VDC51.IMGCNT_MTX_MODE) |
AnnaBridge | 161:aa5281ff4a02 | 582 | #define VDC51IMGCNT_MTX_YG_ADJ0 (VDC51.IMGCNT_MTX_YG_ADJ0) |
AnnaBridge | 161:aa5281ff4a02 | 583 | #define VDC51IMGCNT_MTX_YG_ADJ1 (VDC51.IMGCNT_MTX_YG_ADJ1) |
AnnaBridge | 161:aa5281ff4a02 | 584 | #define VDC51IMGCNT_MTX_CBB_ADJ0 (VDC51.IMGCNT_MTX_CBB_ADJ0) |
AnnaBridge | 161:aa5281ff4a02 | 585 | #define VDC51IMGCNT_MTX_CBB_ADJ1 (VDC51.IMGCNT_MTX_CBB_ADJ1) |
AnnaBridge | 161:aa5281ff4a02 | 586 | #define VDC51IMGCNT_MTX_CRR_ADJ0 (VDC51.IMGCNT_MTX_CRR_ADJ0) |
AnnaBridge | 161:aa5281ff4a02 | 587 | #define VDC51IMGCNT_MTX_CRR_ADJ1 (VDC51.IMGCNT_MTX_CRR_ADJ1) |
AnnaBridge | 161:aa5281ff4a02 | 588 | #define VDC51IMGCNT_DRC_REG (VDC51.IMGCNT_DRC_REG) |
AnnaBridge | 161:aa5281ff4a02 | 589 | #define VDC51SC0_SCL0_UPDATE (VDC51.SC0_SCL0_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 590 | #define VDC51SC0_SCL0_FRC1 (VDC51.SC0_SCL0_FRC1) |
AnnaBridge | 161:aa5281ff4a02 | 591 | #define VDC51SC0_SCL0_FRC2 (VDC51.SC0_SCL0_FRC2) |
AnnaBridge | 161:aa5281ff4a02 | 592 | #define VDC51SC0_SCL0_FRC3 (VDC51.SC0_SCL0_FRC3) |
AnnaBridge | 161:aa5281ff4a02 | 593 | #define VDC51SC0_SCL0_FRC4 (VDC51.SC0_SCL0_FRC4) |
AnnaBridge | 161:aa5281ff4a02 | 594 | #define VDC51SC0_SCL0_FRC5 (VDC51.SC0_SCL0_FRC5) |
AnnaBridge | 161:aa5281ff4a02 | 595 | #define VDC51SC0_SCL0_FRC6 (VDC51.SC0_SCL0_FRC6) |
AnnaBridge | 161:aa5281ff4a02 | 596 | #define VDC51SC0_SCL0_FRC7 (VDC51.SC0_SCL0_FRC7) |
AnnaBridge | 161:aa5281ff4a02 | 597 | #define VDC51SC0_SCL0_FRC9 (VDC51.SC0_SCL0_FRC9) |
AnnaBridge | 161:aa5281ff4a02 | 598 | #define VDC51SC0_SCL0_MON0 (VDC51.SC0_SCL0_MON0) |
AnnaBridge | 161:aa5281ff4a02 | 599 | #define VDC51SC0_SCL0_INT (VDC51.SC0_SCL0_INT) |
AnnaBridge | 161:aa5281ff4a02 | 600 | #define VDC51SC0_SCL0_DS1 (VDC51.SC0_SCL0_DS1) |
AnnaBridge | 161:aa5281ff4a02 | 601 | #define VDC51SC0_SCL0_DS2 (VDC51.SC0_SCL0_DS2) |
AnnaBridge | 161:aa5281ff4a02 | 602 | #define VDC51SC0_SCL0_DS3 (VDC51.SC0_SCL0_DS3) |
AnnaBridge | 161:aa5281ff4a02 | 603 | #define VDC51SC0_SCL0_DS4 (VDC51.SC0_SCL0_DS4) |
AnnaBridge | 161:aa5281ff4a02 | 604 | #define VDC51SC0_SCL0_DS5 (VDC51.SC0_SCL0_DS5) |
AnnaBridge | 161:aa5281ff4a02 | 605 | #define VDC51SC0_SCL0_DS6 (VDC51.SC0_SCL0_DS6) |
AnnaBridge | 161:aa5281ff4a02 | 606 | #define VDC51SC0_SCL0_DS7 (VDC51.SC0_SCL0_DS7) |
AnnaBridge | 161:aa5281ff4a02 | 607 | #define VDC51SC0_SCL0_US1 (VDC51.SC0_SCL0_US1) |
AnnaBridge | 161:aa5281ff4a02 | 608 | #define VDC51SC0_SCL0_US2 (VDC51.SC0_SCL0_US2) |
AnnaBridge | 161:aa5281ff4a02 | 609 | #define VDC51SC0_SCL0_US3 (VDC51.SC0_SCL0_US3) |
AnnaBridge | 161:aa5281ff4a02 | 610 | #define VDC51SC0_SCL0_US4 (VDC51.SC0_SCL0_US4) |
AnnaBridge | 161:aa5281ff4a02 | 611 | #define VDC51SC0_SCL0_US5 (VDC51.SC0_SCL0_US5) |
AnnaBridge | 161:aa5281ff4a02 | 612 | #define VDC51SC0_SCL0_US6 (VDC51.SC0_SCL0_US6) |
AnnaBridge | 161:aa5281ff4a02 | 613 | #define VDC51SC0_SCL0_US7 (VDC51.SC0_SCL0_US7) |
AnnaBridge | 161:aa5281ff4a02 | 614 | #define VDC51SC0_SCL0_US8 (VDC51.SC0_SCL0_US8) |
AnnaBridge | 161:aa5281ff4a02 | 615 | #define VDC51SC0_SCL0_OVR1 (VDC51.SC0_SCL0_OVR1) |
AnnaBridge | 161:aa5281ff4a02 | 616 | #define VDC51SC0_SCL1_UPDATE (VDC51.SC0_SCL1_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 617 | #define VDC51SC0_SCL1_WR1 (VDC51.SC0_SCL1_WR1) |
AnnaBridge | 161:aa5281ff4a02 | 618 | #define VDC51SC0_SCL1_WR2 (VDC51.SC0_SCL1_WR2) |
AnnaBridge | 161:aa5281ff4a02 | 619 | #define VDC51SC0_SCL1_WR3 (VDC51.SC0_SCL1_WR3) |
AnnaBridge | 161:aa5281ff4a02 | 620 | #define VDC51SC0_SCL1_WR4 (VDC51.SC0_SCL1_WR4) |
AnnaBridge | 161:aa5281ff4a02 | 621 | #define VDC51SC0_SCL1_WR5 (VDC51.SC0_SCL1_WR5) |
AnnaBridge | 161:aa5281ff4a02 | 622 | #define VDC51SC0_SCL1_WR6 (VDC51.SC0_SCL1_WR6) |
AnnaBridge | 161:aa5281ff4a02 | 623 | #define VDC51SC0_SCL1_WR7 (VDC51.SC0_SCL1_WR7) |
AnnaBridge | 161:aa5281ff4a02 | 624 | #define VDC51SC0_SCL1_WR8 (VDC51.SC0_SCL1_WR8) |
AnnaBridge | 161:aa5281ff4a02 | 625 | #define VDC51SC0_SCL1_WR9 (VDC51.SC0_SCL1_WR9) |
AnnaBridge | 161:aa5281ff4a02 | 626 | #define VDC51SC0_SCL1_WR10 (VDC51.SC0_SCL1_WR10) |
AnnaBridge | 161:aa5281ff4a02 | 627 | #define VDC51SC0_SCL1_WR11 (VDC51.SC0_SCL1_WR11) |
AnnaBridge | 161:aa5281ff4a02 | 628 | #define VDC51SC0_SCL1_MON1 (VDC51.SC0_SCL1_MON1) |
AnnaBridge | 161:aa5281ff4a02 | 629 | #define VDC51SC0_SCL1_PBUF0 (VDC51.SC0_SCL1_PBUF0) |
AnnaBridge | 161:aa5281ff4a02 | 630 | #define VDC51SC0_SCL1_PBUF1 (VDC51.SC0_SCL1_PBUF1) |
AnnaBridge | 161:aa5281ff4a02 | 631 | #define VDC51SC0_SCL1_PBUF2 (VDC51.SC0_SCL1_PBUF2) |
AnnaBridge | 161:aa5281ff4a02 | 632 | #define VDC51SC0_SCL1_PBUF3 (VDC51.SC0_SCL1_PBUF3) |
AnnaBridge | 161:aa5281ff4a02 | 633 | #define VDC51SC0_SCL1_PBUF_FLD (VDC51.SC0_SCL1_PBUF_FLD) |
AnnaBridge | 161:aa5281ff4a02 | 634 | #define VDC51SC0_SCL1_PBUF_CNT (VDC51.SC0_SCL1_PBUF_CNT) |
AnnaBridge | 161:aa5281ff4a02 | 635 | #define VDC51GR0_UPDATE (VDC51.GR0_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 636 | #define VDC51GR0_FLM_RD (VDC51.GR0_FLM_RD) |
AnnaBridge | 161:aa5281ff4a02 | 637 | #define VDC51GR0_FLM1 (VDC51.GR0_FLM1) |
AnnaBridge | 161:aa5281ff4a02 | 638 | #define VDC51GR0_FLM2 (VDC51.GR0_FLM2) |
AnnaBridge | 161:aa5281ff4a02 | 639 | #define VDC51GR0_FLM3 (VDC51.GR0_FLM3) |
AnnaBridge | 161:aa5281ff4a02 | 640 | #define VDC51GR0_FLM4 (VDC51.GR0_FLM4) |
AnnaBridge | 161:aa5281ff4a02 | 641 | #define VDC51GR0_FLM5 (VDC51.GR0_FLM5) |
AnnaBridge | 161:aa5281ff4a02 | 642 | #define VDC51GR0_FLM6 (VDC51.GR0_FLM6) |
AnnaBridge | 161:aa5281ff4a02 | 643 | #define VDC51GR0_AB1 (VDC51.GR0_AB1) |
AnnaBridge | 161:aa5281ff4a02 | 644 | #define VDC51GR0_AB2 (VDC51.GR0_AB2) |
AnnaBridge | 161:aa5281ff4a02 | 645 | #define VDC51GR0_AB3 (VDC51.GR0_AB3) |
AnnaBridge | 161:aa5281ff4a02 | 646 | #define VDC51GR0_AB7 (VDC51.GR0_AB7) |
AnnaBridge | 161:aa5281ff4a02 | 647 | #define VDC51GR0_AB8 (VDC51.GR0_AB8) |
AnnaBridge | 161:aa5281ff4a02 | 648 | #define VDC51GR0_AB9 (VDC51.GR0_AB9) |
AnnaBridge | 161:aa5281ff4a02 | 649 | #define VDC51GR0_AB10 (VDC51.GR0_AB10) |
AnnaBridge | 161:aa5281ff4a02 | 650 | #define VDC51GR0_AB11 (VDC51.GR0_AB11) |
AnnaBridge | 161:aa5281ff4a02 | 651 | #define VDC51GR0_BASE (VDC51.GR0_BASE) |
AnnaBridge | 161:aa5281ff4a02 | 652 | #define VDC51GR0_CLUT (VDC51.GR0_CLUT) |
AnnaBridge | 161:aa5281ff4a02 | 653 | #define VDC51ADJ0_UPDATE (VDC51.ADJ0_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 654 | #define VDC51ADJ0_BKSTR_SET (VDC51.ADJ0_BKSTR_SET) |
AnnaBridge | 161:aa5281ff4a02 | 655 | #define VDC51ADJ0_ENH_TIM1 (VDC51.ADJ0_ENH_TIM1) |
AnnaBridge | 161:aa5281ff4a02 | 656 | #define VDC51ADJ0_ENH_TIM2 (VDC51.ADJ0_ENH_TIM2) |
AnnaBridge | 161:aa5281ff4a02 | 657 | #define VDC51ADJ0_ENH_TIM3 (VDC51.ADJ0_ENH_TIM3) |
AnnaBridge | 161:aa5281ff4a02 | 658 | #define VDC51ADJ0_ENH_SHP1 (VDC51.ADJ0_ENH_SHP1) |
AnnaBridge | 161:aa5281ff4a02 | 659 | #define VDC51ADJ0_ENH_SHP2 (VDC51.ADJ0_ENH_SHP2) |
AnnaBridge | 161:aa5281ff4a02 | 660 | #define VDC51ADJ0_ENH_SHP3 (VDC51.ADJ0_ENH_SHP3) |
AnnaBridge | 161:aa5281ff4a02 | 661 | #define VDC51ADJ0_ENH_SHP4 (VDC51.ADJ0_ENH_SHP4) |
AnnaBridge | 161:aa5281ff4a02 | 662 | #define VDC51ADJ0_ENH_SHP5 (VDC51.ADJ0_ENH_SHP5) |
AnnaBridge | 161:aa5281ff4a02 | 663 | #define VDC51ADJ0_ENH_SHP6 (VDC51.ADJ0_ENH_SHP6) |
AnnaBridge | 161:aa5281ff4a02 | 664 | #define VDC51ADJ0_ENH_LTI1 (VDC51.ADJ0_ENH_LTI1) |
AnnaBridge | 161:aa5281ff4a02 | 665 | #define VDC51ADJ0_ENH_LTI2 (VDC51.ADJ0_ENH_LTI2) |
AnnaBridge | 161:aa5281ff4a02 | 666 | #define VDC51ADJ0_MTX_MODE (VDC51.ADJ0_MTX_MODE) |
AnnaBridge | 161:aa5281ff4a02 | 667 | #define VDC51ADJ0_MTX_YG_ADJ0 (VDC51.ADJ0_MTX_YG_ADJ0) |
AnnaBridge | 161:aa5281ff4a02 | 668 | #define VDC51ADJ0_MTX_YG_ADJ1 (VDC51.ADJ0_MTX_YG_ADJ1) |
AnnaBridge | 161:aa5281ff4a02 | 669 | #define VDC51ADJ0_MTX_CBB_ADJ0 (VDC51.ADJ0_MTX_CBB_ADJ0) |
AnnaBridge | 161:aa5281ff4a02 | 670 | #define VDC51ADJ0_MTX_CBB_ADJ1 (VDC51.ADJ0_MTX_CBB_ADJ1) |
AnnaBridge | 161:aa5281ff4a02 | 671 | #define VDC51ADJ0_MTX_CRR_ADJ0 (VDC51.ADJ0_MTX_CRR_ADJ0) |
AnnaBridge | 161:aa5281ff4a02 | 672 | #define VDC51ADJ0_MTX_CRR_ADJ1 (VDC51.ADJ0_MTX_CRR_ADJ1) |
AnnaBridge | 161:aa5281ff4a02 | 673 | #define VDC51GR2_UPDATE (VDC51.GR2_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 674 | #define VDC51GR2_FLM_RD (VDC51.GR2_FLM_RD) |
AnnaBridge | 161:aa5281ff4a02 | 675 | #define VDC51GR2_FLM1 (VDC51.GR2_FLM1) |
AnnaBridge | 161:aa5281ff4a02 | 676 | #define VDC51GR2_FLM2 (VDC51.GR2_FLM2) |
AnnaBridge | 161:aa5281ff4a02 | 677 | #define VDC51GR2_FLM3 (VDC51.GR2_FLM3) |
AnnaBridge | 161:aa5281ff4a02 | 678 | #define VDC51GR2_FLM4 (VDC51.GR2_FLM4) |
AnnaBridge | 161:aa5281ff4a02 | 679 | #define VDC51GR2_FLM5 (VDC51.GR2_FLM5) |
AnnaBridge | 161:aa5281ff4a02 | 680 | #define VDC51GR2_FLM6 (VDC51.GR2_FLM6) |
AnnaBridge | 161:aa5281ff4a02 | 681 | #define VDC51GR2_AB1 (VDC51.GR2_AB1) |
AnnaBridge | 161:aa5281ff4a02 | 682 | #define VDC51GR2_AB2 (VDC51.GR2_AB2) |
AnnaBridge | 161:aa5281ff4a02 | 683 | #define VDC51GR2_AB3 (VDC51.GR2_AB3) |
AnnaBridge | 161:aa5281ff4a02 | 684 | #define VDC51GR2_AB4 (VDC51.GR2_AB4) |
AnnaBridge | 161:aa5281ff4a02 | 685 | #define VDC51GR2_AB5 (VDC51.GR2_AB5) |
AnnaBridge | 161:aa5281ff4a02 | 686 | #define VDC51GR2_AB6 (VDC51.GR2_AB6) |
AnnaBridge | 161:aa5281ff4a02 | 687 | #define VDC51GR2_AB7 (VDC51.GR2_AB7) |
AnnaBridge | 161:aa5281ff4a02 | 688 | #define VDC51GR2_AB8 (VDC51.GR2_AB8) |
AnnaBridge | 161:aa5281ff4a02 | 689 | #define VDC51GR2_AB9 (VDC51.GR2_AB9) |
AnnaBridge | 161:aa5281ff4a02 | 690 | #define VDC51GR2_AB10 (VDC51.GR2_AB10) |
AnnaBridge | 161:aa5281ff4a02 | 691 | #define VDC51GR2_AB11 (VDC51.GR2_AB11) |
AnnaBridge | 161:aa5281ff4a02 | 692 | #define VDC51GR2_BASE (VDC51.GR2_BASE) |
AnnaBridge | 161:aa5281ff4a02 | 693 | #define VDC51GR2_CLUT (VDC51.GR2_CLUT) |
AnnaBridge | 161:aa5281ff4a02 | 694 | #define VDC51GR2_MON (VDC51.GR2_MON) |
AnnaBridge | 161:aa5281ff4a02 | 695 | #define VDC51GR3_UPDATE (VDC51.GR3_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 696 | #define VDC51GR3_FLM_RD (VDC51.GR3_FLM_RD) |
AnnaBridge | 161:aa5281ff4a02 | 697 | #define VDC51GR3_FLM1 (VDC51.GR3_FLM1) |
AnnaBridge | 161:aa5281ff4a02 | 698 | #define VDC51GR3_FLM2 (VDC51.GR3_FLM2) |
AnnaBridge | 161:aa5281ff4a02 | 699 | #define VDC51GR3_FLM3 (VDC51.GR3_FLM3) |
AnnaBridge | 161:aa5281ff4a02 | 700 | #define VDC51GR3_FLM4 (VDC51.GR3_FLM4) |
AnnaBridge | 161:aa5281ff4a02 | 701 | #define VDC51GR3_FLM5 (VDC51.GR3_FLM5) |
AnnaBridge | 161:aa5281ff4a02 | 702 | #define VDC51GR3_FLM6 (VDC51.GR3_FLM6) |
AnnaBridge | 161:aa5281ff4a02 | 703 | #define VDC51GR3_AB1 (VDC51.GR3_AB1) |
AnnaBridge | 161:aa5281ff4a02 | 704 | #define VDC51GR3_AB2 (VDC51.GR3_AB2) |
AnnaBridge | 161:aa5281ff4a02 | 705 | #define VDC51GR3_AB3 (VDC51.GR3_AB3) |
AnnaBridge | 161:aa5281ff4a02 | 706 | #define VDC51GR3_AB4 (VDC51.GR3_AB4) |
AnnaBridge | 161:aa5281ff4a02 | 707 | #define VDC51GR3_AB5 (VDC51.GR3_AB5) |
AnnaBridge | 161:aa5281ff4a02 | 708 | #define VDC51GR3_AB6 (VDC51.GR3_AB6) |
AnnaBridge | 161:aa5281ff4a02 | 709 | #define VDC51GR3_AB7 (VDC51.GR3_AB7) |
AnnaBridge | 161:aa5281ff4a02 | 710 | #define VDC51GR3_AB8 (VDC51.GR3_AB8) |
AnnaBridge | 161:aa5281ff4a02 | 711 | #define VDC51GR3_AB9 (VDC51.GR3_AB9) |
AnnaBridge | 161:aa5281ff4a02 | 712 | #define VDC51GR3_AB10 (VDC51.GR3_AB10) |
AnnaBridge | 161:aa5281ff4a02 | 713 | #define VDC51GR3_AB11 (VDC51.GR3_AB11) |
AnnaBridge | 161:aa5281ff4a02 | 714 | #define VDC51GR3_BASE (VDC51.GR3_BASE) |
AnnaBridge | 161:aa5281ff4a02 | 715 | #define VDC51GR3_CLUT_INT (VDC51.GR3_CLUT_INT) |
AnnaBridge | 161:aa5281ff4a02 | 716 | #define VDC51GR3_MON (VDC51.GR3_MON) |
AnnaBridge | 161:aa5281ff4a02 | 717 | #define VDC51GAM_G_UPDATE (VDC51.GAM_G_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 718 | #define VDC51GAM_SW (VDC51.GAM_SW) |
AnnaBridge | 161:aa5281ff4a02 | 719 | #define VDC51GAM_G_LUT1 (VDC51.GAM_G_LUT1) |
AnnaBridge | 161:aa5281ff4a02 | 720 | #define VDC51GAM_G_LUT2 (VDC51.GAM_G_LUT2) |
AnnaBridge | 161:aa5281ff4a02 | 721 | #define VDC51GAM_G_LUT3 (VDC51.GAM_G_LUT3) |
AnnaBridge | 161:aa5281ff4a02 | 722 | #define VDC51GAM_G_LUT4 (VDC51.GAM_G_LUT4) |
AnnaBridge | 161:aa5281ff4a02 | 723 | #define VDC51GAM_G_LUT5 (VDC51.GAM_G_LUT5) |
AnnaBridge | 161:aa5281ff4a02 | 724 | #define VDC51GAM_G_LUT6 (VDC51.GAM_G_LUT6) |
AnnaBridge | 161:aa5281ff4a02 | 725 | #define VDC51GAM_G_LUT7 (VDC51.GAM_G_LUT7) |
AnnaBridge | 161:aa5281ff4a02 | 726 | #define VDC51GAM_G_LUT8 (VDC51.GAM_G_LUT8) |
AnnaBridge | 161:aa5281ff4a02 | 727 | #define VDC51GAM_G_LUT9 (VDC51.GAM_G_LUT9) |
AnnaBridge | 161:aa5281ff4a02 | 728 | #define VDC51GAM_G_LUT10 (VDC51.GAM_G_LUT10) |
AnnaBridge | 161:aa5281ff4a02 | 729 | #define VDC51GAM_G_LUT11 (VDC51.GAM_G_LUT11) |
AnnaBridge | 161:aa5281ff4a02 | 730 | #define VDC51GAM_G_LUT12 (VDC51.GAM_G_LUT12) |
AnnaBridge | 161:aa5281ff4a02 | 731 | #define VDC51GAM_G_LUT13 (VDC51.GAM_G_LUT13) |
AnnaBridge | 161:aa5281ff4a02 | 732 | #define VDC51GAM_G_LUT14 (VDC51.GAM_G_LUT14) |
AnnaBridge | 161:aa5281ff4a02 | 733 | #define VDC51GAM_G_LUT15 (VDC51.GAM_G_LUT15) |
AnnaBridge | 161:aa5281ff4a02 | 734 | #define VDC51GAM_G_LUT16 (VDC51.GAM_G_LUT16) |
AnnaBridge | 161:aa5281ff4a02 | 735 | #define VDC51GAM_G_AREA1 (VDC51.GAM_G_AREA1) |
AnnaBridge | 161:aa5281ff4a02 | 736 | #define VDC51GAM_G_AREA2 (VDC51.GAM_G_AREA2) |
AnnaBridge | 161:aa5281ff4a02 | 737 | #define VDC51GAM_G_AREA3 (VDC51.GAM_G_AREA3) |
AnnaBridge | 161:aa5281ff4a02 | 738 | #define VDC51GAM_G_AREA4 (VDC51.GAM_G_AREA4) |
AnnaBridge | 161:aa5281ff4a02 | 739 | #define VDC51GAM_G_AREA5 (VDC51.GAM_G_AREA5) |
AnnaBridge | 161:aa5281ff4a02 | 740 | #define VDC51GAM_G_AREA6 (VDC51.GAM_G_AREA6) |
AnnaBridge | 161:aa5281ff4a02 | 741 | #define VDC51GAM_G_AREA7 (VDC51.GAM_G_AREA7) |
AnnaBridge | 161:aa5281ff4a02 | 742 | #define VDC51GAM_G_AREA8 (VDC51.GAM_G_AREA8) |
AnnaBridge | 161:aa5281ff4a02 | 743 | #define VDC51GAM_B_UPDATE (VDC51.GAM_B_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 744 | #define VDC51GAM_B_LUT1 (VDC51.GAM_B_LUT1) |
AnnaBridge | 161:aa5281ff4a02 | 745 | #define VDC51GAM_B_LUT2 (VDC51.GAM_B_LUT2) |
AnnaBridge | 161:aa5281ff4a02 | 746 | #define VDC51GAM_B_LUT3 (VDC51.GAM_B_LUT3) |
AnnaBridge | 161:aa5281ff4a02 | 747 | #define VDC51GAM_B_LUT4 (VDC51.GAM_B_LUT4) |
AnnaBridge | 161:aa5281ff4a02 | 748 | #define VDC51GAM_B_LUT5 (VDC51.GAM_B_LUT5) |
AnnaBridge | 161:aa5281ff4a02 | 749 | #define VDC51GAM_B_LUT6 (VDC51.GAM_B_LUT6) |
AnnaBridge | 161:aa5281ff4a02 | 750 | #define VDC51GAM_B_LUT7 (VDC51.GAM_B_LUT7) |
AnnaBridge | 161:aa5281ff4a02 | 751 | #define VDC51GAM_B_LUT8 (VDC51.GAM_B_LUT8) |
AnnaBridge | 161:aa5281ff4a02 | 752 | #define VDC51GAM_B_LUT9 (VDC51.GAM_B_LUT9) |
AnnaBridge | 161:aa5281ff4a02 | 753 | #define VDC51GAM_B_LUT10 (VDC51.GAM_B_LUT10) |
AnnaBridge | 161:aa5281ff4a02 | 754 | #define VDC51GAM_B_LUT11 (VDC51.GAM_B_LUT11) |
AnnaBridge | 161:aa5281ff4a02 | 755 | #define VDC51GAM_B_LUT12 (VDC51.GAM_B_LUT12) |
AnnaBridge | 161:aa5281ff4a02 | 756 | #define VDC51GAM_B_LUT13 (VDC51.GAM_B_LUT13) |
AnnaBridge | 161:aa5281ff4a02 | 757 | #define VDC51GAM_B_LUT14 (VDC51.GAM_B_LUT14) |
AnnaBridge | 161:aa5281ff4a02 | 758 | #define VDC51GAM_B_LUT15 (VDC51.GAM_B_LUT15) |
AnnaBridge | 161:aa5281ff4a02 | 759 | #define VDC51GAM_B_LUT16 (VDC51.GAM_B_LUT16) |
AnnaBridge | 161:aa5281ff4a02 | 760 | #define VDC51GAM_B_AREA1 (VDC51.GAM_B_AREA1) |
AnnaBridge | 161:aa5281ff4a02 | 761 | #define VDC51GAM_B_AREA2 (VDC51.GAM_B_AREA2) |
AnnaBridge | 161:aa5281ff4a02 | 762 | #define VDC51GAM_B_AREA3 (VDC51.GAM_B_AREA3) |
AnnaBridge | 161:aa5281ff4a02 | 763 | #define VDC51GAM_B_AREA4 (VDC51.GAM_B_AREA4) |
AnnaBridge | 161:aa5281ff4a02 | 764 | #define VDC51GAM_B_AREA5 (VDC51.GAM_B_AREA5) |
AnnaBridge | 161:aa5281ff4a02 | 765 | #define VDC51GAM_B_AREA6 (VDC51.GAM_B_AREA6) |
AnnaBridge | 161:aa5281ff4a02 | 766 | #define VDC51GAM_B_AREA7 (VDC51.GAM_B_AREA7) |
AnnaBridge | 161:aa5281ff4a02 | 767 | #define VDC51GAM_B_AREA8 (VDC51.GAM_B_AREA8) |
AnnaBridge | 161:aa5281ff4a02 | 768 | #define VDC51GAM_R_UPDATE (VDC51.GAM_R_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 769 | #define VDC51GAM_R_LUT1 (VDC51.GAM_R_LUT1) |
AnnaBridge | 161:aa5281ff4a02 | 770 | #define VDC51GAM_R_LUT2 (VDC51.GAM_R_LUT2) |
AnnaBridge | 161:aa5281ff4a02 | 771 | #define VDC51GAM_R_LUT3 (VDC51.GAM_R_LUT3) |
AnnaBridge | 161:aa5281ff4a02 | 772 | #define VDC51GAM_R_LUT4 (VDC51.GAM_R_LUT4) |
AnnaBridge | 161:aa5281ff4a02 | 773 | #define VDC51GAM_R_LUT5 (VDC51.GAM_R_LUT5) |
AnnaBridge | 161:aa5281ff4a02 | 774 | #define VDC51GAM_R_LUT6 (VDC51.GAM_R_LUT6) |
AnnaBridge | 161:aa5281ff4a02 | 775 | #define VDC51GAM_R_LUT7 (VDC51.GAM_R_LUT7) |
AnnaBridge | 161:aa5281ff4a02 | 776 | #define VDC51GAM_R_LUT8 (VDC51.GAM_R_LUT8) |
AnnaBridge | 161:aa5281ff4a02 | 777 | #define VDC51GAM_R_LUT9 (VDC51.GAM_R_LUT9) |
AnnaBridge | 161:aa5281ff4a02 | 778 | #define VDC51GAM_R_LUT10 (VDC51.GAM_R_LUT10) |
AnnaBridge | 161:aa5281ff4a02 | 779 | #define VDC51GAM_R_LUT11 (VDC51.GAM_R_LUT11) |
AnnaBridge | 161:aa5281ff4a02 | 780 | #define VDC51GAM_R_LUT12 (VDC51.GAM_R_LUT12) |
AnnaBridge | 161:aa5281ff4a02 | 781 | #define VDC51GAM_R_LUT13 (VDC51.GAM_R_LUT13) |
AnnaBridge | 161:aa5281ff4a02 | 782 | #define VDC51GAM_R_LUT14 (VDC51.GAM_R_LUT14) |
AnnaBridge | 161:aa5281ff4a02 | 783 | #define VDC51GAM_R_LUT15 (VDC51.GAM_R_LUT15) |
AnnaBridge | 161:aa5281ff4a02 | 784 | #define VDC51GAM_R_LUT16 (VDC51.GAM_R_LUT16) |
AnnaBridge | 161:aa5281ff4a02 | 785 | #define VDC51GAM_R_AREA1 (VDC51.GAM_R_AREA1) |
AnnaBridge | 161:aa5281ff4a02 | 786 | #define VDC51GAM_R_AREA2 (VDC51.GAM_R_AREA2) |
AnnaBridge | 161:aa5281ff4a02 | 787 | #define VDC51GAM_R_AREA3 (VDC51.GAM_R_AREA3) |
AnnaBridge | 161:aa5281ff4a02 | 788 | #define VDC51GAM_R_AREA4 (VDC51.GAM_R_AREA4) |
AnnaBridge | 161:aa5281ff4a02 | 789 | #define VDC51GAM_R_AREA5 (VDC51.GAM_R_AREA5) |
AnnaBridge | 161:aa5281ff4a02 | 790 | #define VDC51GAM_R_AREA6 (VDC51.GAM_R_AREA6) |
AnnaBridge | 161:aa5281ff4a02 | 791 | #define VDC51GAM_R_AREA7 (VDC51.GAM_R_AREA7) |
AnnaBridge | 161:aa5281ff4a02 | 792 | #define VDC51GAM_R_AREA8 (VDC51.GAM_R_AREA8) |
AnnaBridge | 161:aa5281ff4a02 | 793 | #define VDC51TCON_UPDATE (VDC51.TCON_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 794 | #define VDC51TCON_TIM (VDC51.TCON_TIM) |
AnnaBridge | 161:aa5281ff4a02 | 795 | #define VDC51TCON_TIM_STVA1 (VDC51.TCON_TIM_STVA1) |
AnnaBridge | 161:aa5281ff4a02 | 796 | #define VDC51TCON_TIM_STVA2 (VDC51.TCON_TIM_STVA2) |
AnnaBridge | 161:aa5281ff4a02 | 797 | #define VDC51TCON_TIM_STVB1 (VDC51.TCON_TIM_STVB1) |
AnnaBridge | 161:aa5281ff4a02 | 798 | #define VDC51TCON_TIM_STVB2 (VDC51.TCON_TIM_STVB2) |
AnnaBridge | 161:aa5281ff4a02 | 799 | #define VDC51TCON_TIM_STH1 (VDC51.TCON_TIM_STH1) |
AnnaBridge | 161:aa5281ff4a02 | 800 | #define VDC51TCON_TIM_STH2 (VDC51.TCON_TIM_STH2) |
AnnaBridge | 161:aa5281ff4a02 | 801 | #define VDC51TCON_TIM_STB1 (VDC51.TCON_TIM_STB1) |
AnnaBridge | 161:aa5281ff4a02 | 802 | #define VDC51TCON_TIM_STB2 (VDC51.TCON_TIM_STB2) |
AnnaBridge | 161:aa5281ff4a02 | 803 | #define VDC51TCON_TIM_CPV1 (VDC51.TCON_TIM_CPV1) |
AnnaBridge | 161:aa5281ff4a02 | 804 | #define VDC51TCON_TIM_CPV2 (VDC51.TCON_TIM_CPV2) |
AnnaBridge | 161:aa5281ff4a02 | 805 | #define VDC51TCON_TIM_POLA1 (VDC51.TCON_TIM_POLA1) |
AnnaBridge | 161:aa5281ff4a02 | 806 | #define VDC51TCON_TIM_POLA2 (VDC51.TCON_TIM_POLA2) |
AnnaBridge | 161:aa5281ff4a02 | 807 | #define VDC51TCON_TIM_POLB1 (VDC51.TCON_TIM_POLB1) |
AnnaBridge | 161:aa5281ff4a02 | 808 | #define VDC51TCON_TIM_POLB2 (VDC51.TCON_TIM_POLB2) |
AnnaBridge | 161:aa5281ff4a02 | 809 | #define VDC51TCON_TIM_DE (VDC51.TCON_TIM_DE) |
AnnaBridge | 161:aa5281ff4a02 | 810 | #define VDC51OUT_UPDATE (VDC51.OUT_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 811 | #define VDC51OUT_SET (VDC51.OUT_SET) |
AnnaBridge | 161:aa5281ff4a02 | 812 | #define VDC51OUT_BRIGHT1 (VDC51.OUT_BRIGHT1) |
AnnaBridge | 161:aa5281ff4a02 | 813 | #define VDC51OUT_BRIGHT2 (VDC51.OUT_BRIGHT2) |
AnnaBridge | 161:aa5281ff4a02 | 814 | #define VDC51OUT_CONTRAST (VDC51.OUT_CONTRAST) |
AnnaBridge | 161:aa5281ff4a02 | 815 | #define VDC51OUT_PDTHA (VDC51.OUT_PDTHA) |
AnnaBridge | 161:aa5281ff4a02 | 816 | #define VDC51OUT_CLK_PHASE (VDC51.OUT_CLK_PHASE) |
AnnaBridge | 161:aa5281ff4a02 | 817 | #define VDC51SYSCNT_INT1 (VDC51.SYSCNT_INT1) |
AnnaBridge | 161:aa5281ff4a02 | 818 | #define VDC51SYSCNT_INT2 (VDC51.SYSCNT_INT2) |
AnnaBridge | 161:aa5281ff4a02 | 819 | #define VDC51SYSCNT_INT3 (VDC51.SYSCNT_INT3) |
AnnaBridge | 161:aa5281ff4a02 | 820 | #define VDC51SYSCNT_INT4 (VDC51.SYSCNT_INT4) |
AnnaBridge | 161:aa5281ff4a02 | 821 | #define VDC51SYSCNT_INT5 (VDC51.SYSCNT_INT5) |
AnnaBridge | 161:aa5281ff4a02 | 822 | #define VDC51SYSCNT_INT6 (VDC51.SYSCNT_INT6) |
AnnaBridge | 161:aa5281ff4a02 | 823 | #define VDC51SYSCNT_PANEL_CLK (VDC51.SYSCNT_PANEL_CLK) |
AnnaBridge | 161:aa5281ff4a02 | 824 | #define VDC51SYSCNT_CLUT (VDC51.SYSCNT_CLUT) |
AnnaBridge | 161:aa5281ff4a02 | 825 | #define VDC51SC1_SCL0_UPDATE (VDC51.SC1_SCL0_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 826 | #define VDC51SC1_SCL0_FRC1 (VDC51.SC1_SCL0_FRC1) |
AnnaBridge | 161:aa5281ff4a02 | 827 | #define VDC51SC1_SCL0_FRC2 (VDC51.SC1_SCL0_FRC2) |
AnnaBridge | 161:aa5281ff4a02 | 828 | #define VDC51SC1_SCL0_FRC3 (VDC51.SC1_SCL0_FRC3) |
AnnaBridge | 161:aa5281ff4a02 | 829 | #define VDC51SC1_SCL0_FRC4 (VDC51.SC1_SCL0_FRC4) |
AnnaBridge | 161:aa5281ff4a02 | 830 | #define VDC51SC1_SCL0_FRC5 (VDC51.SC1_SCL0_FRC5) |
AnnaBridge | 161:aa5281ff4a02 | 831 | #define VDC51SC1_SCL0_FRC6 (VDC51.SC1_SCL0_FRC6) |
AnnaBridge | 161:aa5281ff4a02 | 832 | #define VDC51SC1_SCL0_FRC7 (VDC51.SC1_SCL0_FRC7) |
AnnaBridge | 161:aa5281ff4a02 | 833 | #define VDC51SC1_SCL0_FRC9 (VDC51.SC1_SCL0_FRC9) |
AnnaBridge | 161:aa5281ff4a02 | 834 | #define VDC51SC1_SCL0_MON0 (VDC51.SC1_SCL0_MON0) |
AnnaBridge | 161:aa5281ff4a02 | 835 | #define VDC51SC1_SCL0_INT (VDC51.SC1_SCL0_INT) |
AnnaBridge | 161:aa5281ff4a02 | 836 | #define VDC51SC1_SCL0_DS1 (VDC51.SC1_SCL0_DS1) |
AnnaBridge | 161:aa5281ff4a02 | 837 | #define VDC51SC1_SCL0_DS2 (VDC51.SC1_SCL0_DS2) |
AnnaBridge | 161:aa5281ff4a02 | 838 | #define VDC51SC1_SCL0_DS3 (VDC51.SC1_SCL0_DS3) |
AnnaBridge | 161:aa5281ff4a02 | 839 | #define VDC51SC1_SCL0_DS4 (VDC51.SC1_SCL0_DS4) |
AnnaBridge | 161:aa5281ff4a02 | 840 | #define VDC51SC1_SCL0_DS5 (VDC51.SC1_SCL0_DS5) |
AnnaBridge | 161:aa5281ff4a02 | 841 | #define VDC51SC1_SCL0_DS6 (VDC51.SC1_SCL0_DS6) |
AnnaBridge | 161:aa5281ff4a02 | 842 | #define VDC51SC1_SCL0_DS7 (VDC51.SC1_SCL0_DS7) |
AnnaBridge | 161:aa5281ff4a02 | 843 | #define VDC51SC1_SCL0_US1 (VDC51.SC1_SCL0_US1) |
AnnaBridge | 161:aa5281ff4a02 | 844 | #define VDC51SC1_SCL0_US2 (VDC51.SC1_SCL0_US2) |
AnnaBridge | 161:aa5281ff4a02 | 845 | #define VDC51SC1_SCL0_US3 (VDC51.SC1_SCL0_US3) |
AnnaBridge | 161:aa5281ff4a02 | 846 | #define VDC51SC1_SCL0_US4 (VDC51.SC1_SCL0_US4) |
AnnaBridge | 161:aa5281ff4a02 | 847 | #define VDC51SC1_SCL0_US5 (VDC51.SC1_SCL0_US5) |
AnnaBridge | 161:aa5281ff4a02 | 848 | #define VDC51SC1_SCL0_US6 (VDC51.SC1_SCL0_US6) |
AnnaBridge | 161:aa5281ff4a02 | 849 | #define VDC51SC1_SCL0_US7 (VDC51.SC1_SCL0_US7) |
AnnaBridge | 161:aa5281ff4a02 | 850 | #define VDC51SC1_SCL0_US8 (VDC51.SC1_SCL0_US8) |
AnnaBridge | 161:aa5281ff4a02 | 851 | #define VDC51SC1_SCL0_OVR1 (VDC51.SC1_SCL0_OVR1) |
AnnaBridge | 161:aa5281ff4a02 | 852 | #define VDC51SC1_SCL1_UPDATE (VDC51.SC1_SCL1_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 853 | #define VDC51SC1_SCL1_WR1 (VDC51.SC1_SCL1_WR1) |
AnnaBridge | 161:aa5281ff4a02 | 854 | #define VDC51SC1_SCL1_WR2 (VDC51.SC1_SCL1_WR2) |
AnnaBridge | 161:aa5281ff4a02 | 855 | #define VDC51SC1_SCL1_WR3 (VDC51.SC1_SCL1_WR3) |
AnnaBridge | 161:aa5281ff4a02 | 856 | #define VDC51SC1_SCL1_WR4 (VDC51.SC1_SCL1_WR4) |
AnnaBridge | 161:aa5281ff4a02 | 857 | #define VDC51SC1_SCL1_WR5 (VDC51.SC1_SCL1_WR5) |
AnnaBridge | 161:aa5281ff4a02 | 858 | #define VDC51SC1_SCL1_WR6 (VDC51.SC1_SCL1_WR6) |
AnnaBridge | 161:aa5281ff4a02 | 859 | #define VDC51SC1_SCL1_WR7 (VDC51.SC1_SCL1_WR7) |
AnnaBridge | 161:aa5281ff4a02 | 860 | #define VDC51SC1_SCL1_WR8 (VDC51.SC1_SCL1_WR8) |
AnnaBridge | 161:aa5281ff4a02 | 861 | #define VDC51SC1_SCL1_WR9 (VDC51.SC1_SCL1_WR9) |
AnnaBridge | 161:aa5281ff4a02 | 862 | #define VDC51SC1_SCL1_WR10 (VDC51.SC1_SCL1_WR10) |
AnnaBridge | 161:aa5281ff4a02 | 863 | #define VDC51SC1_SCL1_WR11 (VDC51.SC1_SCL1_WR11) |
AnnaBridge | 161:aa5281ff4a02 | 864 | #define VDC51SC1_SCL1_MON1 (VDC51.SC1_SCL1_MON1) |
AnnaBridge | 161:aa5281ff4a02 | 865 | #define VDC51SC1_SCL1_PBUF0 (VDC51.SC1_SCL1_PBUF0) |
AnnaBridge | 161:aa5281ff4a02 | 866 | #define VDC51SC1_SCL1_PBUF1 (VDC51.SC1_SCL1_PBUF1) |
AnnaBridge | 161:aa5281ff4a02 | 867 | #define VDC51SC1_SCL1_PBUF2 (VDC51.SC1_SCL1_PBUF2) |
AnnaBridge | 161:aa5281ff4a02 | 868 | #define VDC51SC1_SCL1_PBUF3 (VDC51.SC1_SCL1_PBUF3) |
AnnaBridge | 161:aa5281ff4a02 | 869 | #define VDC51SC1_SCL1_PBUF_FLD (VDC51.SC1_SCL1_PBUF_FLD) |
AnnaBridge | 161:aa5281ff4a02 | 870 | #define VDC51SC1_SCL1_PBUF_CNT (VDC51.SC1_SCL1_PBUF_CNT) |
AnnaBridge | 161:aa5281ff4a02 | 871 | #define VDC51GR1_UPDATE (VDC51.GR1_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 872 | #define VDC51GR1_FLM_RD (VDC51.GR1_FLM_RD) |
AnnaBridge | 161:aa5281ff4a02 | 873 | #define VDC51GR1_FLM1 (VDC51.GR1_FLM1) |
AnnaBridge | 161:aa5281ff4a02 | 874 | #define VDC51GR1_FLM2 (VDC51.GR1_FLM2) |
AnnaBridge | 161:aa5281ff4a02 | 875 | #define VDC51GR1_FLM3 (VDC51.GR1_FLM3) |
AnnaBridge | 161:aa5281ff4a02 | 876 | #define VDC51GR1_FLM4 (VDC51.GR1_FLM4) |
AnnaBridge | 161:aa5281ff4a02 | 877 | #define VDC51GR1_FLM5 (VDC51.GR1_FLM5) |
AnnaBridge | 161:aa5281ff4a02 | 878 | #define VDC51GR1_FLM6 (VDC51.GR1_FLM6) |
AnnaBridge | 161:aa5281ff4a02 | 879 | #define VDC51GR1_AB1 (VDC51.GR1_AB1) |
AnnaBridge | 161:aa5281ff4a02 | 880 | #define VDC51GR1_AB2 (VDC51.GR1_AB2) |
AnnaBridge | 161:aa5281ff4a02 | 881 | #define VDC51GR1_AB3 (VDC51.GR1_AB3) |
AnnaBridge | 161:aa5281ff4a02 | 882 | #define VDC51GR1_AB4 (VDC51.GR1_AB4) |
AnnaBridge | 161:aa5281ff4a02 | 883 | #define VDC51GR1_AB5 (VDC51.GR1_AB5) |
AnnaBridge | 161:aa5281ff4a02 | 884 | #define VDC51GR1_AB6 (VDC51.GR1_AB6) |
AnnaBridge | 161:aa5281ff4a02 | 885 | #define VDC51GR1_AB7 (VDC51.GR1_AB7) |
AnnaBridge | 161:aa5281ff4a02 | 886 | #define VDC51GR1_AB8 (VDC51.GR1_AB8) |
AnnaBridge | 161:aa5281ff4a02 | 887 | #define VDC51GR1_AB9 (VDC51.GR1_AB9) |
AnnaBridge | 161:aa5281ff4a02 | 888 | #define VDC51GR1_AB10 (VDC51.GR1_AB10) |
AnnaBridge | 161:aa5281ff4a02 | 889 | #define VDC51GR1_AB11 (VDC51.GR1_AB11) |
AnnaBridge | 161:aa5281ff4a02 | 890 | #define VDC51GR1_BASE (VDC51.GR1_BASE) |
AnnaBridge | 161:aa5281ff4a02 | 891 | #define VDC51GR1_CLUT (VDC51.GR1_CLUT) |
AnnaBridge | 161:aa5281ff4a02 | 892 | #define VDC51GR1_MON (VDC51.GR1_MON) |
AnnaBridge | 161:aa5281ff4a02 | 893 | #define VDC51ADJ1_UPDATE (VDC51.ADJ1_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 894 | #define VDC51ADJ1_BKSTR_SET (VDC51.ADJ1_BKSTR_SET) |
AnnaBridge | 161:aa5281ff4a02 | 895 | #define VDC51ADJ1_ENH_TIM1 (VDC51.ADJ1_ENH_TIM1) |
AnnaBridge | 161:aa5281ff4a02 | 896 | #define VDC51ADJ1_ENH_TIM2 (VDC51.ADJ1_ENH_TIM2) |
AnnaBridge | 161:aa5281ff4a02 | 897 | #define VDC51ADJ1_ENH_TIM3 (VDC51.ADJ1_ENH_TIM3) |
AnnaBridge | 161:aa5281ff4a02 | 898 | #define VDC51ADJ1_ENH_SHP1 (VDC51.ADJ1_ENH_SHP1) |
AnnaBridge | 161:aa5281ff4a02 | 899 | #define VDC51ADJ1_ENH_SHP2 (VDC51.ADJ1_ENH_SHP2) |
AnnaBridge | 161:aa5281ff4a02 | 900 | #define VDC51ADJ1_ENH_SHP3 (VDC51.ADJ1_ENH_SHP3) |
AnnaBridge | 161:aa5281ff4a02 | 901 | #define VDC51ADJ1_ENH_SHP4 (VDC51.ADJ1_ENH_SHP4) |
AnnaBridge | 161:aa5281ff4a02 | 902 | #define VDC51ADJ1_ENH_SHP5 (VDC51.ADJ1_ENH_SHP5) |
AnnaBridge | 161:aa5281ff4a02 | 903 | #define VDC51ADJ1_ENH_SHP6 (VDC51.ADJ1_ENH_SHP6) |
AnnaBridge | 161:aa5281ff4a02 | 904 | #define VDC51ADJ1_ENH_LTI1 (VDC51.ADJ1_ENH_LTI1) |
AnnaBridge | 161:aa5281ff4a02 | 905 | #define VDC51ADJ1_ENH_LTI2 (VDC51.ADJ1_ENH_LTI2) |
AnnaBridge | 161:aa5281ff4a02 | 906 | #define VDC51ADJ1_MTX_MODE (VDC51.ADJ1_MTX_MODE) |
AnnaBridge | 161:aa5281ff4a02 | 907 | #define VDC51ADJ1_MTX_YG_ADJ0 (VDC51.ADJ1_MTX_YG_ADJ0) |
AnnaBridge | 161:aa5281ff4a02 | 908 | #define VDC51ADJ1_MTX_YG_ADJ1 (VDC51.ADJ1_MTX_YG_ADJ1) |
AnnaBridge | 161:aa5281ff4a02 | 909 | #define VDC51ADJ1_MTX_CBB_ADJ0 (VDC51.ADJ1_MTX_CBB_ADJ0) |
AnnaBridge | 161:aa5281ff4a02 | 910 | #define VDC51ADJ1_MTX_CBB_ADJ1 (VDC51.ADJ1_MTX_CBB_ADJ1) |
AnnaBridge | 161:aa5281ff4a02 | 911 | #define VDC51ADJ1_MTX_CRR_ADJ0 (VDC51.ADJ1_MTX_CRR_ADJ0) |
AnnaBridge | 161:aa5281ff4a02 | 912 | #define VDC51ADJ1_MTX_CRR_ADJ1 (VDC51.ADJ1_MTX_CRR_ADJ1) |
AnnaBridge | 161:aa5281ff4a02 | 913 | #define VDC51GR_VIN_UPDATE (VDC51.GR_VIN_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 914 | #define VDC51GR_VIN_AB1 (VDC51.GR_VIN_AB1) |
AnnaBridge | 161:aa5281ff4a02 | 915 | #define VDC51GR_VIN_AB2 (VDC51.GR_VIN_AB2) |
AnnaBridge | 161:aa5281ff4a02 | 916 | #define VDC51GR_VIN_AB3 (VDC51.GR_VIN_AB3) |
AnnaBridge | 161:aa5281ff4a02 | 917 | #define VDC51GR_VIN_AB4 (VDC51.GR_VIN_AB4) |
AnnaBridge | 161:aa5281ff4a02 | 918 | #define VDC51GR_VIN_AB5 (VDC51.GR_VIN_AB5) |
AnnaBridge | 161:aa5281ff4a02 | 919 | #define VDC51GR_VIN_AB6 (VDC51.GR_VIN_AB6) |
AnnaBridge | 161:aa5281ff4a02 | 920 | #define VDC51GR_VIN_AB7 (VDC51.GR_VIN_AB7) |
AnnaBridge | 161:aa5281ff4a02 | 921 | #define VDC51GR_VIN_BASE (VDC51.GR_VIN_BASE) |
AnnaBridge | 161:aa5281ff4a02 | 922 | #define VDC51GR_VIN_MON (VDC51.GR_VIN_MON) |
AnnaBridge | 161:aa5281ff4a02 | 923 | #define VDC51OIR_SCL0_UPDATE (VDC51.OIR_SCL0_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 924 | #define VDC51OIR_SCL0_FRC1 (VDC51.OIR_SCL0_FRC1) |
AnnaBridge | 161:aa5281ff4a02 | 925 | #define VDC51OIR_SCL0_FRC2 (VDC51.OIR_SCL0_FRC2) |
AnnaBridge | 161:aa5281ff4a02 | 926 | #define VDC51OIR_SCL0_FRC3 (VDC51.OIR_SCL0_FRC3) |
AnnaBridge | 161:aa5281ff4a02 | 927 | #define VDC51OIR_SCL0_FRC4 (VDC51.OIR_SCL0_FRC4) |
AnnaBridge | 161:aa5281ff4a02 | 928 | #define VDC51OIR_SCL0_FRC5 (VDC51.OIR_SCL0_FRC5) |
AnnaBridge | 161:aa5281ff4a02 | 929 | #define VDC51OIR_SCL0_FRC6 (VDC51.OIR_SCL0_FRC6) |
AnnaBridge | 161:aa5281ff4a02 | 930 | #define VDC51OIR_SCL0_FRC7 (VDC51.OIR_SCL0_FRC7) |
AnnaBridge | 161:aa5281ff4a02 | 931 | #define VDC51OIR_SCL0_DS1 (VDC51.OIR_SCL0_DS1) |
AnnaBridge | 161:aa5281ff4a02 | 932 | #define VDC51OIR_SCL0_DS2 (VDC51.OIR_SCL0_DS2) |
AnnaBridge | 161:aa5281ff4a02 | 933 | #define VDC51OIR_SCL0_DS3 (VDC51.OIR_SCL0_DS3) |
AnnaBridge | 161:aa5281ff4a02 | 934 | #define VDC51OIR_SCL0_DS7 (VDC51.OIR_SCL0_DS7) |
AnnaBridge | 161:aa5281ff4a02 | 935 | #define VDC51OIR_SCL0_US1 (VDC51.OIR_SCL0_US1) |
AnnaBridge | 161:aa5281ff4a02 | 936 | #define VDC51OIR_SCL0_US2 (VDC51.OIR_SCL0_US2) |
AnnaBridge | 161:aa5281ff4a02 | 937 | #define VDC51OIR_SCL0_US3 (VDC51.OIR_SCL0_US3) |
AnnaBridge | 161:aa5281ff4a02 | 938 | #define VDC51OIR_SCL0_US8 (VDC51.OIR_SCL0_US8) |
AnnaBridge | 161:aa5281ff4a02 | 939 | #define VDC51OIR_SCL0_OVR1 (VDC51.OIR_SCL0_OVR1) |
AnnaBridge | 161:aa5281ff4a02 | 940 | #define VDC51OIR_SCL1_UPDATE (VDC51.OIR_SCL1_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 941 | #define VDC51OIR_SCL1_WR1 (VDC51.OIR_SCL1_WR1) |
AnnaBridge | 161:aa5281ff4a02 | 942 | #define VDC51OIR_SCL1_WR2 (VDC51.OIR_SCL1_WR2) |
AnnaBridge | 161:aa5281ff4a02 | 943 | #define VDC51OIR_SCL1_WR3 (VDC51.OIR_SCL1_WR3) |
AnnaBridge | 161:aa5281ff4a02 | 944 | #define VDC51OIR_SCL1_WR4 (VDC51.OIR_SCL1_WR4) |
AnnaBridge | 161:aa5281ff4a02 | 945 | #define VDC51OIR_SCL1_WR5 (VDC51.OIR_SCL1_WR5) |
AnnaBridge | 161:aa5281ff4a02 | 946 | #define VDC51OIR_SCL1_WR6 (VDC51.OIR_SCL1_WR6) |
AnnaBridge | 161:aa5281ff4a02 | 947 | #define VDC51OIR_SCL1_WR7 (VDC51.OIR_SCL1_WR7) |
AnnaBridge | 161:aa5281ff4a02 | 948 | #define VDC51GR_OIR_UPDATE (VDC51.GR_OIR_UPDATE) |
AnnaBridge | 161:aa5281ff4a02 | 949 | #define VDC51GR_OIR_FLM_RD (VDC51.GR_OIR_FLM_RD) |
AnnaBridge | 161:aa5281ff4a02 | 950 | #define VDC51GR_OIR_FLM1 (VDC51.GR_OIR_FLM1) |
AnnaBridge | 161:aa5281ff4a02 | 951 | #define VDC51GR_OIR_FLM2 (VDC51.GR_OIR_FLM2) |
AnnaBridge | 161:aa5281ff4a02 | 952 | #define VDC51GR_OIR_FLM3 (VDC51.GR_OIR_FLM3) |
AnnaBridge | 161:aa5281ff4a02 | 953 | #define VDC51GR_OIR_FLM4 (VDC51.GR_OIR_FLM4) |
AnnaBridge | 161:aa5281ff4a02 | 954 | #define VDC51GR_OIR_FLM5 (VDC51.GR_OIR_FLM5) |
AnnaBridge | 161:aa5281ff4a02 | 955 | #define VDC51GR_OIR_FLM6 (VDC51.GR_OIR_FLM6) |
AnnaBridge | 161:aa5281ff4a02 | 956 | #define VDC51GR_OIR_AB1 (VDC51.GR_OIR_AB1) |
AnnaBridge | 161:aa5281ff4a02 | 957 | #define VDC51GR_OIR_AB2 (VDC51.GR_OIR_AB2) |
AnnaBridge | 161:aa5281ff4a02 | 958 | #define VDC51GR_OIR_AB3 (VDC51.GR_OIR_AB3) |
AnnaBridge | 161:aa5281ff4a02 | 959 | #define VDC51GR_OIR_AB7 (VDC51.GR_OIR_AB7) |
AnnaBridge | 161:aa5281ff4a02 | 960 | #define VDC51GR_OIR_AB8 (VDC51.GR_OIR_AB8) |
AnnaBridge | 161:aa5281ff4a02 | 961 | #define VDC51GR_OIR_AB9 (VDC51.GR_OIR_AB9) |
AnnaBridge | 161:aa5281ff4a02 | 962 | #define VDC51GR_OIR_AB10 (VDC51.GR_OIR_AB10) |
AnnaBridge | 161:aa5281ff4a02 | 963 | #define VDC51GR_OIR_AB11 (VDC51.GR_OIR_AB11) |
AnnaBridge | 161:aa5281ff4a02 | 964 | #define VDC51GR_OIR_BASE (VDC51.GR_OIR_BASE) |
AnnaBridge | 161:aa5281ff4a02 | 965 | #define VDC51GR_OIR_CLUT (VDC51.GR_OIR_CLUT) |
AnnaBridge | 161:aa5281ff4a02 | 966 | #define VDC51GR_OIR_MON (VDC51.GR_OIR_MON) |
AnnaBridge | 161:aa5281ff4a02 | 967 | |
AnnaBridge | 161:aa5281ff4a02 | 968 | #define VDC5_IMGCNT_NR_CNT0_COUNT (2) |
AnnaBridge | 161:aa5281ff4a02 | 969 | #define VDC5_SC0_SCL0_FRC1_COUNT (7) |
AnnaBridge | 161:aa5281ff4a02 | 970 | #define VDC5_SC0_SCL0_DS1_COUNT (7) |
AnnaBridge | 161:aa5281ff4a02 | 971 | #define VDC5_SC0_SCL0_US1_COUNT (8) |
AnnaBridge | 161:aa5281ff4a02 | 972 | #define VDC5_SC0_SCL1_WR1_COUNT (4) |
AnnaBridge | 161:aa5281ff4a02 | 973 | #define VDC5_SC0_SCL1_PBUF0_COUNT (4) |
AnnaBridge | 161:aa5281ff4a02 | 974 | #define VDC5_GR0_FLM1_COUNT (6) |
AnnaBridge | 161:aa5281ff4a02 | 975 | #define VDC5_GR0_AB1_COUNT (3) |
AnnaBridge | 161:aa5281ff4a02 | 976 | #define VDC5_ADJ0_ENH_TIM1_COUNT (3) |
AnnaBridge | 161:aa5281ff4a02 | 977 | #define VDC5_ADJ0_ENH_SHP1_COUNT (6) |
AnnaBridge | 161:aa5281ff4a02 | 978 | #define VDC5_ADJ0_ENH_LTI1_COUNT (2) |
AnnaBridge | 161:aa5281ff4a02 | 979 | #define VDC5_GR2_FLM1_COUNT (6) |
AnnaBridge | 161:aa5281ff4a02 | 980 | #define VDC5_GR2_AB1_COUNT (3) |
AnnaBridge | 161:aa5281ff4a02 | 981 | #define VDC5_GR3_FLM1_COUNT (6) |
AnnaBridge | 161:aa5281ff4a02 | 982 | #define VDC5_GR3_AB1_COUNT (3) |
AnnaBridge | 161:aa5281ff4a02 | 983 | #define VDC5_GAM_G_LUT1_COUNT (16) |
AnnaBridge | 161:aa5281ff4a02 | 984 | #define VDC5_GAM_G_AREA1_COUNT (8) |
AnnaBridge | 161:aa5281ff4a02 | 985 | #define VDC5_GAM_B_LUT1_COUNT (16) |
AnnaBridge | 161:aa5281ff4a02 | 986 | #define VDC5_GAM_B_AREA1_COUNT (8) |
AnnaBridge | 161:aa5281ff4a02 | 987 | #define VDC5_GAM_R_LUT1_COUNT (16) |
AnnaBridge | 161:aa5281ff4a02 | 988 | #define VDC5_GAM_R_AREA1_COUNT (8) |
AnnaBridge | 161:aa5281ff4a02 | 989 | #define VDC5_TCON_TIM_STVA1_COUNT (2) |
AnnaBridge | 161:aa5281ff4a02 | 990 | #define VDC5_TCON_TIM_STVB1_COUNT (2) |
AnnaBridge | 161:aa5281ff4a02 | 991 | #define VDC5_TCON_TIM_STH1_COUNT (2) |
AnnaBridge | 161:aa5281ff4a02 | 992 | #define VDC5_TCON_TIM_STB1_COUNT (2) |
AnnaBridge | 161:aa5281ff4a02 | 993 | #define VDC5_TCON_TIM_CPV1_COUNT (2) |
AnnaBridge | 161:aa5281ff4a02 | 994 | #define VDC5_TCON_TIM_POLA1_COUNT (2) |
AnnaBridge | 161:aa5281ff4a02 | 995 | #define VDC5_TCON_TIM_POLB1_COUNT (2) |
AnnaBridge | 161:aa5281ff4a02 | 996 | #define VDC5_OUT_BRIGHT1_COUNT (2) |
AnnaBridge | 161:aa5281ff4a02 | 997 | #define VDC5_SYSCNT_INT1_COUNT (6) |
AnnaBridge | 161:aa5281ff4a02 | 998 | #define VDC5_SC1_SCL0_FRC1_COUNT (7) |
AnnaBridge | 161:aa5281ff4a02 | 999 | #define VDC5_SC1_SC1_SCL0_DS1_COUNT (7) |
AnnaBridge | 161:aa5281ff4a02 | 1000 | #define VDC5_SC1_SC1_SCL0_US1_COUNT (8) |
AnnaBridge | 161:aa5281ff4a02 | 1001 | #define VDC5_SC1_SCL1_WR1_COUNT (4) |
AnnaBridge | 161:aa5281ff4a02 | 1002 | #define VDC5_SC1_SCL1_PBUF0_COUNT (4) |
AnnaBridge | 161:aa5281ff4a02 | 1003 | #define VDC5_GR1_FLM1_COUNT (6) |
AnnaBridge | 161:aa5281ff4a02 | 1004 | #define VDC5_GR1_AB1_COUNT (3) |
AnnaBridge | 161:aa5281ff4a02 | 1005 | #define VDC5_ADJ1_ENH_TIM1_COUNT (3) |
AnnaBridge | 161:aa5281ff4a02 | 1006 | #define VDC5_ADJ1_ENH_SHP1_COUNT (6) |
AnnaBridge | 161:aa5281ff4a02 | 1007 | #define VDC5_ADJ1_ENH_LTI1_COUNT (2) |
AnnaBridge | 161:aa5281ff4a02 | 1008 | #define VDC5_GR_VIN_AB1_COUNT (7) |
AnnaBridge | 161:aa5281ff4a02 | 1009 | #define VDC5_OIR_SCL0_FRC1_COUNT (7) |
AnnaBridge | 161:aa5281ff4a02 | 1010 | #define VDC5_OIR_SCL0_DS1_COUNT (3) |
AnnaBridge | 161:aa5281ff4a02 | 1011 | #define VDC5_OIR_SCL1_WR1_COUNT (4) |
AnnaBridge | 161:aa5281ff4a02 | 1012 | #define VDC5_GR_OIR_FLM1_COUNT (6) |
AnnaBridge | 161:aa5281ff4a02 | 1013 | #define VDC5_GR_OIR_AB1_COUNT (3) |
AnnaBridge | 161:aa5281ff4a02 | 1014 | |
AnnaBridge | 161:aa5281ff4a02 | 1015 | |
AnnaBridge | 161:aa5281ff4a02 | 1016 | typedef struct st_vdc5 |
AnnaBridge | 161:aa5281ff4a02 | 1017 | { |
AnnaBridge | 161:aa5281ff4a02 | 1018 | /* VDC5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1019 | volatile uint32_t INP_UPDATE; /* INP_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1020 | volatile uint32_t INP_SEL_CNT; /* INP_SEL_CNT */ |
AnnaBridge | 161:aa5281ff4a02 | 1021 | volatile uint32_t INP_EXT_SYNC_CNT; /* INP_EXT_SYNC_CNT */ |
AnnaBridge | 161:aa5281ff4a02 | 1022 | volatile uint32_t INP_VSYNC_PH_ADJ; /* INP_VSYNC_PH_ADJ */ |
AnnaBridge | 161:aa5281ff4a02 | 1023 | volatile uint32_t INP_DLY_ADJ; /* INP_DLY_ADJ */ |
AnnaBridge | 161:aa5281ff4a02 | 1024 | volatile uint8_t dummy1[108]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1025 | volatile uint32_t IMGCNT_UPDATE; /* IMGCNT_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1026 | |
AnnaBridge | 161:aa5281ff4a02 | 1027 | /* #define VDC5_IMGCNT_NR_CNT0_COUNT (2) */ |
AnnaBridge | 161:aa5281ff4a02 | 1028 | volatile uint32_t IMGCNT_NR_CNT0; /* IMGCNT_NR_CNT0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1029 | volatile uint32_t IMGCNT_NR_CNT1; /* IMGCNT_NR_CNT1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1030 | volatile uint8_t dummy2[20]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1031 | volatile uint32_t IMGCNT_MTX_MODE; /* IMGCNT_MTX_MODE */ |
AnnaBridge | 161:aa5281ff4a02 | 1032 | volatile uint32_t IMGCNT_MTX_YG_ADJ0; /* IMGCNT_MTX_YG_ADJ0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1033 | volatile uint32_t IMGCNT_MTX_YG_ADJ1; /* IMGCNT_MTX_YG_ADJ1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1034 | volatile uint32_t IMGCNT_MTX_CBB_ADJ0; /* IMGCNT_MTX_CBB_ADJ0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1035 | volatile uint32_t IMGCNT_MTX_CBB_ADJ1; /* IMGCNT_MTX_CBB_ADJ1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1036 | volatile uint32_t IMGCNT_MTX_CRR_ADJ0; /* IMGCNT_MTX_CRR_ADJ0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1037 | volatile uint32_t IMGCNT_MTX_CRR_ADJ1; /* IMGCNT_MTX_CRR_ADJ1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1038 | volatile uint8_t dummy3[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1039 | volatile uint32_t IMGCNT_DRC_REG; /* IMGCNT_DRC_REG */ |
AnnaBridge | 161:aa5281ff4a02 | 1040 | volatile uint8_t dummy4[60]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1041 | |
AnnaBridge | 161:aa5281ff4a02 | 1042 | /* start of struct st_vdc5_from_sc0_scl0_update */ |
AnnaBridge | 161:aa5281ff4a02 | 1043 | volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1044 | |
AnnaBridge | 161:aa5281ff4a02 | 1045 | /* #define VDC5_SC0_SCL0_FRC1_COUNT (7) */ |
AnnaBridge | 161:aa5281ff4a02 | 1046 | volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1047 | volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1048 | volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1049 | volatile uint32_t SC0_SCL0_FRC4; /* SC0_SCL0_FRC4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1050 | volatile uint32_t SC0_SCL0_FRC5; /* SC0_SCL0_FRC5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1051 | volatile uint32_t SC0_SCL0_FRC6; /* SC0_SCL0_FRC6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1052 | volatile uint32_t SC0_SCL0_FRC7; /* SC0_SCL0_FRC7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1053 | volatile uint8_t dummy5[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1054 | volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */ |
AnnaBridge | 161:aa5281ff4a02 | 1055 | volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1056 | volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */ |
AnnaBridge | 161:aa5281ff4a02 | 1057 | |
AnnaBridge | 161:aa5281ff4a02 | 1058 | /* #define VDC5_SC0_SCL0_DS1_COUNT (7) */ |
AnnaBridge | 161:aa5281ff4a02 | 1059 | volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1060 | volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1061 | volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1062 | volatile uint32_t SC0_SCL0_DS4; /* SC0_SCL0_DS4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1063 | volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1064 | volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1065 | volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1066 | |
AnnaBridge | 161:aa5281ff4a02 | 1067 | /* #define VDC5_SC0_SCL0_US1_COUNT (8) */ |
AnnaBridge | 161:aa5281ff4a02 | 1068 | volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1069 | volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1070 | volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1071 | volatile uint32_t SC0_SCL0_US4; /* SC0_SCL0_US4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1072 | volatile uint32_t SC0_SCL0_US5; /* SC0_SCL0_US5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1073 | volatile uint32_t SC0_SCL0_US6; /* SC0_SCL0_US6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1074 | volatile uint32_t SC0_SCL0_US7; /* SC0_SCL0_US7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1075 | volatile uint32_t SC0_SCL0_US8; /* SC0_SCL0_US8 */ |
AnnaBridge | 161:aa5281ff4a02 | 1076 | volatile uint8_t dummy6[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1077 | volatile uint32_t SC0_SCL0_OVR1; /* SC0_SCL0_OVR1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1078 | volatile uint8_t dummy7[16]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1079 | volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1080 | volatile uint8_t dummy8[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1081 | |
AnnaBridge | 161:aa5281ff4a02 | 1082 | /* #define VDC5_SC0_SCL1_WR1_COUNT (4) */ |
AnnaBridge | 161:aa5281ff4a02 | 1083 | volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1084 | volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1085 | volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1086 | volatile uint32_t SC0_SCL1_WR4; /* SC0_SCL1_WR4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1087 | volatile uint8_t dummy9[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1088 | volatile uint32_t SC0_SCL1_WR5; /* SC0_SCL1_WR5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1089 | volatile uint32_t SC0_SCL1_WR6; /* SC0_SCL1_WR6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1090 | volatile uint32_t SC0_SCL1_WR7; /* SC0_SCL1_WR7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1091 | volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */ |
AnnaBridge | 161:aa5281ff4a02 | 1092 | volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */ |
AnnaBridge | 161:aa5281ff4a02 | 1093 | volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */ |
AnnaBridge | 161:aa5281ff4a02 | 1094 | |
AnnaBridge | 161:aa5281ff4a02 | 1095 | /* end of struct st_vdc5_from_sc0_scl0_update */ |
AnnaBridge | 161:aa5281ff4a02 | 1096 | volatile uint32_t SC0_SCL1_WR11; /* SC0_SCL1_WR11 */ |
AnnaBridge | 161:aa5281ff4a02 | 1097 | volatile uint32_t SC0_SCL1_MON1; /* SC0_SCL1_MON1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1098 | |
AnnaBridge | 161:aa5281ff4a02 | 1099 | /* start of struct st_vdc5_from_sc0_scl1_pbuf0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1100 | |
AnnaBridge | 161:aa5281ff4a02 | 1101 | /* #define VDC5_SC0_SCL1_PBUF0_COUNT (4) */ |
AnnaBridge | 161:aa5281ff4a02 | 1102 | volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1103 | volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1104 | volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1105 | volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1106 | volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */ |
AnnaBridge | 161:aa5281ff4a02 | 1107 | volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */ |
AnnaBridge | 161:aa5281ff4a02 | 1108 | |
AnnaBridge | 161:aa5281ff4a02 | 1109 | /* end of struct st_vdc5_from_sc0_scl1_pbuf0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1110 | volatile uint8_t dummy10[44]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1111 | |
AnnaBridge | 161:aa5281ff4a02 | 1112 | /* start of struct st_vdc5_from_gr0_update */ |
AnnaBridge | 161:aa5281ff4a02 | 1113 | volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1114 | volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */ |
AnnaBridge | 161:aa5281ff4a02 | 1115 | |
AnnaBridge | 161:aa5281ff4a02 | 1116 | /* #define VDC5_GR0_FLM1_COUNT (6) */ |
AnnaBridge | 161:aa5281ff4a02 | 1117 | volatile uint32_t GR0_FLM1; /* GR0_FLM1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1118 | volatile uint32_t GR0_FLM2; /* GR0_FLM2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1119 | volatile uint32_t GR0_FLM3; /* GR0_FLM3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1120 | volatile uint32_t GR0_FLM4; /* GR0_FLM4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1121 | volatile uint32_t GR0_FLM5; /* GR0_FLM5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1122 | volatile uint32_t GR0_FLM6; /* GR0_FLM6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1123 | |
AnnaBridge | 161:aa5281ff4a02 | 1124 | /* #define VDC5_GR0_AB1_COUNT (3) */ |
AnnaBridge | 161:aa5281ff4a02 | 1125 | volatile uint32_t GR0_AB1; /* GR0_AB1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1126 | volatile uint32_t GR0_AB2; /* GR0_AB2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1127 | volatile uint32_t GR0_AB3; /* GR0_AB3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1128 | |
AnnaBridge | 161:aa5281ff4a02 | 1129 | /* end of struct st_vdc5_from_gr0_update */ |
AnnaBridge | 161:aa5281ff4a02 | 1130 | volatile uint8_t dummy11[12]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1131 | |
AnnaBridge | 161:aa5281ff4a02 | 1132 | /* start of struct st_vdc5_from_gr0_ab7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1133 | volatile uint32_t GR0_AB7; /* GR0_AB7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1134 | volatile uint32_t GR0_AB8; /* GR0_AB8 */ |
AnnaBridge | 161:aa5281ff4a02 | 1135 | volatile uint32_t GR0_AB9; /* GR0_AB9 */ |
AnnaBridge | 161:aa5281ff4a02 | 1136 | volatile uint32_t GR0_AB10; /* GR0_AB10 */ |
AnnaBridge | 161:aa5281ff4a02 | 1137 | volatile uint32_t GR0_AB11; /* GR0_AB11 */ |
AnnaBridge | 161:aa5281ff4a02 | 1138 | volatile uint32_t GR0_BASE; /* GR0_BASE */ |
AnnaBridge | 161:aa5281ff4a02 | 1139 | |
AnnaBridge | 161:aa5281ff4a02 | 1140 | /* end of struct st_vdc5_from_gr0_ab7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1141 | volatile uint32_t GR0_CLUT; /* GR0_CLUT */ |
AnnaBridge | 161:aa5281ff4a02 | 1142 | volatile uint8_t dummy12[44]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1143 | |
AnnaBridge | 161:aa5281ff4a02 | 1144 | /* start of struct st_vdc5_from_adj0_update */ |
AnnaBridge | 161:aa5281ff4a02 | 1145 | volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1146 | volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */ |
AnnaBridge | 161:aa5281ff4a02 | 1147 | |
AnnaBridge | 161:aa5281ff4a02 | 1148 | /* #define VDC5_ADJ0_ENH_TIM1_COUNT (3) */ |
AnnaBridge | 161:aa5281ff4a02 | 1149 | volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1150 | volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1151 | volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1152 | |
AnnaBridge | 161:aa5281ff4a02 | 1153 | /* #define VDC5_ADJ0_ENH_SHP1_COUNT (6) */ |
AnnaBridge | 161:aa5281ff4a02 | 1154 | volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1155 | volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1156 | volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1157 | volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1158 | volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1159 | volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1160 | |
AnnaBridge | 161:aa5281ff4a02 | 1161 | /* #define VDC5_ADJ0_ENH_LTI1_COUNT (2) */ |
AnnaBridge | 161:aa5281ff4a02 | 1162 | volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1163 | volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1164 | volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */ |
AnnaBridge | 161:aa5281ff4a02 | 1165 | volatile uint32_t ADJ0_MTX_YG_ADJ0; /* ADJ0_MTX_YG_ADJ0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1166 | volatile uint32_t ADJ0_MTX_YG_ADJ1; /* ADJ0_MTX_YG_ADJ1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1167 | volatile uint32_t ADJ0_MTX_CBB_ADJ0; /* ADJ0_MTX_CBB_ADJ0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1168 | volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1169 | volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1170 | volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1171 | |
AnnaBridge | 161:aa5281ff4a02 | 1172 | /* end of struct st_vdc5_from_adj0_update */ |
AnnaBridge | 161:aa5281ff4a02 | 1173 | volatile uint8_t dummy13[48]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1174 | |
AnnaBridge | 161:aa5281ff4a02 | 1175 | /* start of struct st_vdc5_from_gr0_update */ |
AnnaBridge | 161:aa5281ff4a02 | 1176 | volatile uint32_t GR2_UPDATE; /* GR2_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1177 | volatile uint32_t GR2_FLM_RD; /* GR2_FLM_RD */ |
AnnaBridge | 161:aa5281ff4a02 | 1178 | |
AnnaBridge | 161:aa5281ff4a02 | 1179 | /* #define VDC5_GR2_FLM1_COUNT (6) */ |
AnnaBridge | 161:aa5281ff4a02 | 1180 | volatile uint32_t GR2_FLM1; /* GR2_FLM1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1181 | volatile uint32_t GR2_FLM2; /* GR2_FLM2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1182 | volatile uint32_t GR2_FLM3; /* GR2_FLM3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1183 | volatile uint32_t GR2_FLM4; /* GR2_FLM4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1184 | volatile uint32_t GR2_FLM5; /* GR2_FLM5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1185 | volatile uint32_t GR2_FLM6; /* GR2_FLM6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1186 | |
AnnaBridge | 161:aa5281ff4a02 | 1187 | /* #define VDC5_GR2_AB1_COUNT (3) */ |
AnnaBridge | 161:aa5281ff4a02 | 1188 | volatile uint32_t GR2_AB1; /* GR2_AB1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1189 | volatile uint32_t GR2_AB2; /* GR2_AB2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1190 | volatile uint32_t GR2_AB3; /* GR2_AB3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1191 | |
AnnaBridge | 161:aa5281ff4a02 | 1192 | /* end of struct st_vdc5_from_gr0_update */ |
AnnaBridge | 161:aa5281ff4a02 | 1193 | volatile uint32_t GR2_AB4; /* GR2_AB4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1194 | volatile uint32_t GR2_AB5; /* GR2_AB5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1195 | volatile uint32_t GR2_AB6; /* GR2_AB6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1196 | |
AnnaBridge | 161:aa5281ff4a02 | 1197 | /* start of struct st_vdc5_from_gr0_ab7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1198 | volatile uint32_t GR2_AB7; /* GR2_AB7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1199 | volatile uint32_t GR2_AB8; /* GR2_AB8 */ |
AnnaBridge | 161:aa5281ff4a02 | 1200 | volatile uint32_t GR2_AB9; /* GR2_AB9 */ |
AnnaBridge | 161:aa5281ff4a02 | 1201 | volatile uint32_t GR2_AB10; /* GR2_AB10 */ |
AnnaBridge | 161:aa5281ff4a02 | 1202 | volatile uint32_t GR2_AB11; /* GR2_AB11 */ |
AnnaBridge | 161:aa5281ff4a02 | 1203 | volatile uint32_t GR2_BASE; /* GR2_BASE */ |
AnnaBridge | 161:aa5281ff4a02 | 1204 | |
AnnaBridge | 161:aa5281ff4a02 | 1205 | /* end of struct st_vdc5_from_gr0_ab7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1206 | volatile uint32_t GR2_CLUT; /* GR2_CLUT */ |
AnnaBridge | 161:aa5281ff4a02 | 1207 | volatile uint32_t GR2_MON; /* GR2_MON */ |
AnnaBridge | 161:aa5281ff4a02 | 1208 | volatile uint8_t dummy14[40]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1209 | |
AnnaBridge | 161:aa5281ff4a02 | 1210 | /* start of struct st_vdc5_from_gr0_update */ |
AnnaBridge | 161:aa5281ff4a02 | 1211 | volatile uint32_t GR3_UPDATE; /* GR3_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1212 | volatile uint32_t GR3_FLM_RD; /* GR3_FLM_RD */ |
AnnaBridge | 161:aa5281ff4a02 | 1213 | |
AnnaBridge | 161:aa5281ff4a02 | 1214 | /* #define VDC5_GR3_FLM1_COUNT (6) */ |
AnnaBridge | 161:aa5281ff4a02 | 1215 | volatile uint32_t GR3_FLM1; /* GR3_FLM1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1216 | volatile uint32_t GR3_FLM2; /* GR3_FLM2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1217 | volatile uint32_t GR3_FLM3; /* GR3_FLM3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1218 | volatile uint32_t GR3_FLM4; /* GR3_FLM4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1219 | volatile uint32_t GR3_FLM5; /* GR3_FLM5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1220 | volatile uint32_t GR3_FLM6; /* GR3_FLM6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1221 | |
AnnaBridge | 161:aa5281ff4a02 | 1222 | /* #define VDC5_GR3_AB1_COUNT (3) */ |
AnnaBridge | 161:aa5281ff4a02 | 1223 | volatile uint32_t GR3_AB1; /* GR3_AB1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1224 | volatile uint32_t GR3_AB2; /* GR3_AB2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1225 | volatile uint32_t GR3_AB3; /* GR3_AB3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1226 | |
AnnaBridge | 161:aa5281ff4a02 | 1227 | /* end of struct st_vdc5_from_gr0_update */ |
AnnaBridge | 161:aa5281ff4a02 | 1228 | volatile uint32_t GR3_AB4; /* GR3_AB4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1229 | volatile uint32_t GR3_AB5; /* GR3_AB5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1230 | volatile uint32_t GR3_AB6; /* GR3_AB6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1231 | |
AnnaBridge | 161:aa5281ff4a02 | 1232 | /* start of struct st_vdc5_from_gr0_ab7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1233 | volatile uint32_t GR3_AB7; /* GR3_AB7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1234 | volatile uint32_t GR3_AB8; /* GR3_AB8 */ |
AnnaBridge | 161:aa5281ff4a02 | 1235 | volatile uint32_t GR3_AB9; /* GR3_AB9 */ |
AnnaBridge | 161:aa5281ff4a02 | 1236 | volatile uint32_t GR3_AB10; /* GR3_AB10 */ |
AnnaBridge | 161:aa5281ff4a02 | 1237 | volatile uint32_t GR3_AB11; /* GR3_AB11 */ |
AnnaBridge | 161:aa5281ff4a02 | 1238 | volatile uint32_t GR3_BASE; /* GR3_BASE */ |
AnnaBridge | 161:aa5281ff4a02 | 1239 | |
AnnaBridge | 161:aa5281ff4a02 | 1240 | /* end of struct st_vdc5_from_gr0_ab7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1241 | volatile uint32_t GR3_CLUT_INT; /* GR3_CLUT_INT */ |
AnnaBridge | 161:aa5281ff4a02 | 1242 | volatile uint32_t GR3_MON; /* GR3_MON */ |
AnnaBridge | 161:aa5281ff4a02 | 1243 | volatile uint8_t dummy15[40]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1244 | volatile uint32_t GAM_G_UPDATE; /* GAM_G_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1245 | volatile uint32_t GAM_SW; /* GAM_SW */ |
AnnaBridge | 161:aa5281ff4a02 | 1246 | |
AnnaBridge | 161:aa5281ff4a02 | 1247 | /* #define VDC5_GAM_G_LUT1_COUNT (16) */ |
AnnaBridge | 161:aa5281ff4a02 | 1248 | volatile uint32_t GAM_G_LUT1; /* GAM_G_LUT1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1249 | volatile uint32_t GAM_G_LUT2; /* GAM_G_LUT2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1250 | volatile uint32_t GAM_G_LUT3; /* GAM_G_LUT3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1251 | volatile uint32_t GAM_G_LUT4; /* GAM_G_LUT4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1252 | volatile uint32_t GAM_G_LUT5; /* GAM_G_LUT5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1253 | volatile uint32_t GAM_G_LUT6; /* GAM_G_LUT6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1254 | volatile uint32_t GAM_G_LUT7; /* GAM_G_LUT7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1255 | volatile uint32_t GAM_G_LUT8; /* GAM_G_LUT8 */ |
AnnaBridge | 161:aa5281ff4a02 | 1256 | volatile uint32_t GAM_G_LUT9; /* GAM_G_LUT9 */ |
AnnaBridge | 161:aa5281ff4a02 | 1257 | volatile uint32_t GAM_G_LUT10; /* GAM_G_LUT10 */ |
AnnaBridge | 161:aa5281ff4a02 | 1258 | volatile uint32_t GAM_G_LUT11; /* GAM_G_LUT11 */ |
AnnaBridge | 161:aa5281ff4a02 | 1259 | volatile uint32_t GAM_G_LUT12; /* GAM_G_LUT12 */ |
AnnaBridge | 161:aa5281ff4a02 | 1260 | volatile uint32_t GAM_G_LUT13; /* GAM_G_LUT13 */ |
AnnaBridge | 161:aa5281ff4a02 | 1261 | volatile uint32_t GAM_G_LUT14; /* GAM_G_LUT14 */ |
AnnaBridge | 161:aa5281ff4a02 | 1262 | volatile uint32_t GAM_G_LUT15; /* GAM_G_LUT15 */ |
AnnaBridge | 161:aa5281ff4a02 | 1263 | volatile uint32_t GAM_G_LUT16; /* GAM_G_LUT16 */ |
AnnaBridge | 161:aa5281ff4a02 | 1264 | |
AnnaBridge | 161:aa5281ff4a02 | 1265 | /* #define VDC5_GAM_G_AREA1_COUNT (8) */ |
AnnaBridge | 161:aa5281ff4a02 | 1266 | volatile uint32_t GAM_G_AREA1; /* GAM_G_AREA1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1267 | volatile uint32_t GAM_G_AREA2; /* GAM_G_AREA2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1268 | volatile uint32_t GAM_G_AREA3; /* GAM_G_AREA3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1269 | volatile uint32_t GAM_G_AREA4; /* GAM_G_AREA4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1270 | volatile uint32_t GAM_G_AREA5; /* GAM_G_AREA5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1271 | volatile uint32_t GAM_G_AREA6; /* GAM_G_AREA6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1272 | volatile uint32_t GAM_G_AREA7; /* GAM_G_AREA7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1273 | volatile uint32_t GAM_G_AREA8; /* GAM_G_AREA8 */ |
AnnaBridge | 161:aa5281ff4a02 | 1274 | volatile uint8_t dummy16[24]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1275 | volatile uint32_t GAM_B_UPDATE; /* GAM_B_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1276 | volatile uint8_t dummy17[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1277 | |
AnnaBridge | 161:aa5281ff4a02 | 1278 | /* #define VDC5_GAM_B_LUT1_COUNT (16) */ |
AnnaBridge | 161:aa5281ff4a02 | 1279 | volatile uint32_t GAM_B_LUT1; /* GAM_B_LUT1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1280 | volatile uint32_t GAM_B_LUT2; /* GAM_B_LUT2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1281 | volatile uint32_t GAM_B_LUT3; /* GAM_B_LUT3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1282 | volatile uint32_t GAM_B_LUT4; /* GAM_B_LUT4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1283 | volatile uint32_t GAM_B_LUT5; /* GAM_B_LUT5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1284 | volatile uint32_t GAM_B_LUT6; /* GAM_B_LUT6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1285 | volatile uint32_t GAM_B_LUT7; /* GAM_B_LUT7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1286 | volatile uint32_t GAM_B_LUT8; /* GAM_B_LUT8 */ |
AnnaBridge | 161:aa5281ff4a02 | 1287 | volatile uint32_t GAM_B_LUT9; /* GAM_B_LUT9 */ |
AnnaBridge | 161:aa5281ff4a02 | 1288 | volatile uint32_t GAM_B_LUT10; /* GAM_B_LUT10 */ |
AnnaBridge | 161:aa5281ff4a02 | 1289 | volatile uint32_t GAM_B_LUT11; /* GAM_B_LUT11 */ |
AnnaBridge | 161:aa5281ff4a02 | 1290 | volatile uint32_t GAM_B_LUT12; /* GAM_B_LUT12 */ |
AnnaBridge | 161:aa5281ff4a02 | 1291 | volatile uint32_t GAM_B_LUT13; /* GAM_B_LUT13 */ |
AnnaBridge | 161:aa5281ff4a02 | 1292 | volatile uint32_t GAM_B_LUT14; /* GAM_B_LUT14 */ |
AnnaBridge | 161:aa5281ff4a02 | 1293 | volatile uint32_t GAM_B_LUT15; /* GAM_B_LUT15 */ |
AnnaBridge | 161:aa5281ff4a02 | 1294 | volatile uint32_t GAM_B_LUT16; /* GAM_B_LUT16 */ |
AnnaBridge | 161:aa5281ff4a02 | 1295 | |
AnnaBridge | 161:aa5281ff4a02 | 1296 | /* #define VDC5_GAM_B_AREA1_COUNT (8) */ |
AnnaBridge | 161:aa5281ff4a02 | 1297 | volatile uint32_t GAM_B_AREA1; /* GAM_B_AREA1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1298 | volatile uint32_t GAM_B_AREA2; /* GAM_B_AREA2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1299 | volatile uint32_t GAM_B_AREA3; /* GAM_B_AREA3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1300 | volatile uint32_t GAM_B_AREA4; /* GAM_B_AREA4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1301 | volatile uint32_t GAM_B_AREA5; /* GAM_B_AREA5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1302 | volatile uint32_t GAM_B_AREA6; /* GAM_B_AREA6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1303 | volatile uint32_t GAM_B_AREA7; /* GAM_B_AREA7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1304 | volatile uint32_t GAM_B_AREA8; /* GAM_B_AREA8 */ |
AnnaBridge | 161:aa5281ff4a02 | 1305 | volatile uint8_t dummy18[24]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1306 | volatile uint32_t GAM_R_UPDATE; /* GAM_R_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1307 | volatile uint8_t dummy19[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1308 | |
AnnaBridge | 161:aa5281ff4a02 | 1309 | /* #define VDC5_GAM_R_LUT1_COUNT (16) */ |
AnnaBridge | 161:aa5281ff4a02 | 1310 | volatile uint32_t GAM_R_LUT1; /* GAM_R_LUT1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1311 | volatile uint32_t GAM_R_LUT2; /* GAM_R_LUT2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1312 | volatile uint32_t GAM_R_LUT3; /* GAM_R_LUT3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1313 | volatile uint32_t GAM_R_LUT4; /* GAM_R_LUT4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1314 | volatile uint32_t GAM_R_LUT5; /* GAM_R_LUT5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1315 | volatile uint32_t GAM_R_LUT6; /* GAM_R_LUT6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1316 | volatile uint32_t GAM_R_LUT7; /* GAM_R_LUT7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1317 | volatile uint32_t GAM_R_LUT8; /* GAM_R_LUT8 */ |
AnnaBridge | 161:aa5281ff4a02 | 1318 | volatile uint32_t GAM_R_LUT9; /* GAM_R_LUT9 */ |
AnnaBridge | 161:aa5281ff4a02 | 1319 | volatile uint32_t GAM_R_LUT10; /* GAM_R_LUT10 */ |
AnnaBridge | 161:aa5281ff4a02 | 1320 | volatile uint32_t GAM_R_LUT11; /* GAM_R_LUT11 */ |
AnnaBridge | 161:aa5281ff4a02 | 1321 | volatile uint32_t GAM_R_LUT12; /* GAM_R_LUT12 */ |
AnnaBridge | 161:aa5281ff4a02 | 1322 | volatile uint32_t GAM_R_LUT13; /* GAM_R_LUT13 */ |
AnnaBridge | 161:aa5281ff4a02 | 1323 | volatile uint32_t GAM_R_LUT14; /* GAM_R_LUT14 */ |
AnnaBridge | 161:aa5281ff4a02 | 1324 | volatile uint32_t GAM_R_LUT15; /* GAM_R_LUT15 */ |
AnnaBridge | 161:aa5281ff4a02 | 1325 | volatile uint32_t GAM_R_LUT16; /* GAM_R_LUT16 */ |
AnnaBridge | 161:aa5281ff4a02 | 1326 | |
AnnaBridge | 161:aa5281ff4a02 | 1327 | /* #define VDC5_GAM_R_AREA1_COUNT (8) */ |
AnnaBridge | 161:aa5281ff4a02 | 1328 | volatile uint32_t GAM_R_AREA1; /* GAM_R_AREA1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1329 | volatile uint32_t GAM_R_AREA2; /* GAM_R_AREA2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1330 | volatile uint32_t GAM_R_AREA3; /* GAM_R_AREA3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1331 | volatile uint32_t GAM_R_AREA4; /* GAM_R_AREA4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1332 | volatile uint32_t GAM_R_AREA5; /* GAM_R_AREA5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1333 | volatile uint32_t GAM_R_AREA6; /* GAM_R_AREA6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1334 | volatile uint32_t GAM_R_AREA7; /* GAM_R_AREA7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1335 | volatile uint32_t GAM_R_AREA8; /* GAM_R_AREA8 */ |
AnnaBridge | 161:aa5281ff4a02 | 1336 | volatile uint8_t dummy20[24]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1337 | volatile uint32_t TCON_UPDATE; /* TCON_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1338 | volatile uint32_t TCON_TIM; /* TCON_TIM */ |
AnnaBridge | 161:aa5281ff4a02 | 1339 | |
AnnaBridge | 161:aa5281ff4a02 | 1340 | /* #define VDC5_TCON_TIM_STVA1_COUNT (2) */ |
AnnaBridge | 161:aa5281ff4a02 | 1341 | volatile uint32_t TCON_TIM_STVA1; /* TCON_TIM_STVA1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1342 | volatile uint32_t TCON_TIM_STVA2; /* TCON_TIM_STVA2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1343 | |
AnnaBridge | 161:aa5281ff4a02 | 1344 | /* #define VDC5_TCON_TIM_STVB1_COUNT (2) */ |
AnnaBridge | 161:aa5281ff4a02 | 1345 | volatile uint32_t TCON_TIM_STVB1; /* TCON_TIM_STVB1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1346 | volatile uint32_t TCON_TIM_STVB2; /* TCON_TIM_STVB2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1347 | |
AnnaBridge | 161:aa5281ff4a02 | 1348 | /* #define VDC5_TCON_TIM_STH1_COUNT (2) */ |
AnnaBridge | 161:aa5281ff4a02 | 1349 | volatile uint32_t TCON_TIM_STH1; /* TCON_TIM_STH1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1350 | volatile uint32_t TCON_TIM_STH2; /* TCON_TIM_STH2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1351 | |
AnnaBridge | 161:aa5281ff4a02 | 1352 | /* #define VDC5_TCON_TIM_STB1_COUNT (2) */ |
AnnaBridge | 161:aa5281ff4a02 | 1353 | volatile uint32_t TCON_TIM_STB1; /* TCON_TIM_STB1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1354 | volatile uint32_t TCON_TIM_STB2; /* TCON_TIM_STB2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1355 | |
AnnaBridge | 161:aa5281ff4a02 | 1356 | /* #define VDC5_TCON_TIM_CPV1_COUNT (2) */ |
AnnaBridge | 161:aa5281ff4a02 | 1357 | volatile uint32_t TCON_TIM_CPV1; /* TCON_TIM_CPV1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1358 | volatile uint32_t TCON_TIM_CPV2; /* TCON_TIM_CPV2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1359 | |
AnnaBridge | 161:aa5281ff4a02 | 1360 | /* #define VDC5_TCON_TIM_POLA1_COUNT (2) */ |
AnnaBridge | 161:aa5281ff4a02 | 1361 | volatile uint32_t TCON_TIM_POLA1; /* TCON_TIM_POLA1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1362 | volatile uint32_t TCON_TIM_POLA2; /* TCON_TIM_POLA2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1363 | |
AnnaBridge | 161:aa5281ff4a02 | 1364 | /* #define VDC5_TCON_TIM_POLB1_COUNT (2) */ |
AnnaBridge | 161:aa5281ff4a02 | 1365 | volatile uint32_t TCON_TIM_POLB1; /* TCON_TIM_POLB1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1366 | volatile uint32_t TCON_TIM_POLB2; /* TCON_TIM_POLB2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1367 | volatile uint32_t TCON_TIM_DE; /* TCON_TIM_DE */ |
AnnaBridge | 161:aa5281ff4a02 | 1368 | volatile uint8_t dummy21[60]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1369 | volatile uint32_t OUT_UPDATE; /* OUT_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1370 | volatile uint32_t OUT_SET; /* OUT_SET */ |
AnnaBridge | 161:aa5281ff4a02 | 1371 | |
AnnaBridge | 161:aa5281ff4a02 | 1372 | /* #define VDC5_OUT_BRIGHT1_COUNT (2) */ |
AnnaBridge | 161:aa5281ff4a02 | 1373 | volatile uint32_t OUT_BRIGHT1; /* OUT_BRIGHT1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1374 | volatile uint32_t OUT_BRIGHT2; /* OUT_BRIGHT2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1375 | volatile uint32_t OUT_CONTRAST; /* OUT_CONTRAST */ |
AnnaBridge | 161:aa5281ff4a02 | 1376 | volatile uint32_t OUT_PDTHA; /* OUT_PDTHA */ |
AnnaBridge | 161:aa5281ff4a02 | 1377 | volatile uint8_t dummy22[12]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1378 | volatile uint32_t OUT_CLK_PHASE; /* OUT_CLK_PHASE */ |
AnnaBridge | 161:aa5281ff4a02 | 1379 | volatile uint8_t dummy23[88]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1380 | |
AnnaBridge | 161:aa5281ff4a02 | 1381 | /* #define VDC5_SYSCNT_INT1_COUNT (6) */ |
AnnaBridge | 161:aa5281ff4a02 | 1382 | volatile uint32_t SYSCNT_INT1; /* SYSCNT_INT1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1383 | volatile uint32_t SYSCNT_INT2; /* SYSCNT_INT2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1384 | volatile uint32_t SYSCNT_INT3; /* SYSCNT_INT3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1385 | volatile uint32_t SYSCNT_INT4; /* SYSCNT_INT4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1386 | volatile uint32_t SYSCNT_INT5; /* SYSCNT_INT5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1387 | volatile uint32_t SYSCNT_INT6; /* SYSCNT_INT6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1388 | volatile uint16_t SYSCNT_PANEL_CLK; /* SYSCNT_PANEL_CLK */ |
AnnaBridge | 161:aa5281ff4a02 | 1389 | volatile uint16_t SYSCNT_CLUT; /* SYSCNT_CLUT */ |
AnnaBridge | 161:aa5281ff4a02 | 1390 | volatile uint8_t dummy24[356]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1391 | |
AnnaBridge | 161:aa5281ff4a02 | 1392 | /* start of struct st_vdc5_from_sc0_scl0_update */ |
AnnaBridge | 161:aa5281ff4a02 | 1393 | volatile uint32_t SC1_SCL0_UPDATE; /* SC1_SCL0_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1394 | |
AnnaBridge | 161:aa5281ff4a02 | 1395 | /* #define VDC5_SC1_SCL0_FRC1_COUNT (7) */ |
AnnaBridge | 161:aa5281ff4a02 | 1396 | volatile uint32_t SC1_SCL0_FRC1; /* SC1_SCL0_FRC1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1397 | volatile uint32_t SC1_SCL0_FRC2; /* SC1_SCL0_FRC2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1398 | volatile uint32_t SC1_SCL0_FRC3; /* SC1_SCL0_FRC3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1399 | volatile uint32_t SC1_SCL0_FRC4; /* SC1_SCL0_FRC4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1400 | volatile uint32_t SC1_SCL0_FRC5; /* SC1_SCL0_FRC5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1401 | volatile uint32_t SC1_SCL0_FRC6; /* SC1_SCL0_FRC6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1402 | volatile uint32_t SC1_SCL0_FRC7; /* SC1_SCL0_FRC7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1403 | volatile uint8_t dummy25[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1404 | volatile uint32_t SC1_SCL0_FRC9; /* SC1_SCL0_FRC9 */ |
AnnaBridge | 161:aa5281ff4a02 | 1405 | volatile uint16_t SC1_SCL0_MON0; /* SC1_SCL0_MON0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1406 | volatile uint16_t SC1_SCL0_INT; /* SC1_SCL0_INT */ |
AnnaBridge | 161:aa5281ff4a02 | 1407 | |
AnnaBridge | 161:aa5281ff4a02 | 1408 | /* #define VDC5_SC1_SC1_SCL0_DS1_COUNT (7) */ |
AnnaBridge | 161:aa5281ff4a02 | 1409 | volatile uint32_t SC1_SCL0_DS1; /* SC1_SCL0_DS1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1410 | volatile uint32_t SC1_SCL0_DS2; /* SC1_SCL0_DS2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1411 | volatile uint32_t SC1_SCL0_DS3; /* SC1_SCL0_DS3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1412 | volatile uint32_t SC1_SCL0_DS4; /* SC1_SCL0_DS4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1413 | volatile uint32_t SC1_SCL0_DS5; /* SC1_SCL0_DS5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1414 | volatile uint32_t SC1_SCL0_DS6; /* SC1_SCL0_DS6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1415 | volatile uint32_t SC1_SCL0_DS7; /* SC1_SCL0_DS7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1416 | |
AnnaBridge | 161:aa5281ff4a02 | 1417 | /* #define VDC5_SC1_SC1_SCL0_US1_COUNT (8) */ |
AnnaBridge | 161:aa5281ff4a02 | 1418 | volatile uint32_t SC1_SCL0_US1; /* SC1_SCL0_US1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1419 | volatile uint32_t SC1_SCL0_US2; /* SC1_SCL0_US2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1420 | volatile uint32_t SC1_SCL0_US3; /* SC1_SCL0_US3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1421 | volatile uint32_t SC1_SCL0_US4; /* SC1_SCL0_US4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1422 | volatile uint32_t SC1_SCL0_US5; /* SC1_SCL0_US5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1423 | volatile uint32_t SC1_SCL0_US6; /* SC1_SCL0_US6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1424 | volatile uint32_t SC1_SCL0_US7; /* SC1_SCL0_US7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1425 | volatile uint32_t SC1_SCL0_US8; /* SC1_SCL0_US8 */ |
AnnaBridge | 161:aa5281ff4a02 | 1426 | volatile uint8_t dummy26[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1427 | volatile uint32_t SC1_SCL0_OVR1; /* SC1_SCL0_OVR1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1428 | volatile uint8_t dummy27[16]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1429 | volatile uint32_t SC1_SCL1_UPDATE; /* SC1_SCL1_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1430 | volatile uint8_t dummy28[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1431 | |
AnnaBridge | 161:aa5281ff4a02 | 1432 | /* #define VDC5_SC1_SCL1_WR1_COUNT (4) */ |
AnnaBridge | 161:aa5281ff4a02 | 1433 | volatile uint32_t SC1_SCL1_WR1; /* SC1_SCL1_WR1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1434 | volatile uint32_t SC1_SCL1_WR2; /* SC1_SCL1_WR2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1435 | volatile uint32_t SC1_SCL1_WR3; /* SC1_SCL1_WR3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1436 | volatile uint32_t SC1_SCL1_WR4; /* SC1_SCL1_WR4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1437 | volatile uint8_t dummy29[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1438 | volatile uint32_t SC1_SCL1_WR5; /* SC1_SCL1_WR5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1439 | volatile uint32_t SC1_SCL1_WR6; /* SC1_SCL1_WR6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1440 | volatile uint32_t SC1_SCL1_WR7; /* SC1_SCL1_WR7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1441 | volatile uint32_t SC1_SCL1_WR8; /* SC1_SCL1_WR8 */ |
AnnaBridge | 161:aa5281ff4a02 | 1442 | volatile uint32_t SC1_SCL1_WR9; /* SC1_SCL1_WR9 */ |
AnnaBridge | 161:aa5281ff4a02 | 1443 | volatile uint32_t SC1_SCL1_WR10; /* SC1_SCL1_WR10 */ |
AnnaBridge | 161:aa5281ff4a02 | 1444 | |
AnnaBridge | 161:aa5281ff4a02 | 1445 | /* end of struct st_vdc5_from_sc0_scl0_update */ |
AnnaBridge | 161:aa5281ff4a02 | 1446 | volatile uint32_t SC1_SCL1_WR11; /* SC1_SCL1_WR11 */ |
AnnaBridge | 161:aa5281ff4a02 | 1447 | volatile uint32_t SC1_SCL1_MON1; /* SC1_SCL1_MON1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1448 | |
AnnaBridge | 161:aa5281ff4a02 | 1449 | /* start of struct st_vdc5_from_sc0_scl1_pbuf0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1450 | |
AnnaBridge | 161:aa5281ff4a02 | 1451 | /* #define VDC5_SC1_SCL1_PBUF0_COUNT (4) */ |
AnnaBridge | 161:aa5281ff4a02 | 1452 | volatile uint32_t SC1_SCL1_PBUF0; /* SC1_SCL1_PBUF0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1453 | volatile uint32_t SC1_SCL1_PBUF1; /* SC1_SCL1_PBUF1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1454 | volatile uint32_t SC1_SCL1_PBUF2; /* SC1_SCL1_PBUF2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1455 | volatile uint32_t SC1_SCL1_PBUF3; /* SC1_SCL1_PBUF3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1456 | volatile uint32_t SC1_SCL1_PBUF_FLD; /* SC1_SCL1_PBUF_FLD */ |
AnnaBridge | 161:aa5281ff4a02 | 1457 | volatile uint32_t SC1_SCL1_PBUF_CNT; /* SC1_SCL1_PBUF_CNT */ |
AnnaBridge | 161:aa5281ff4a02 | 1458 | |
AnnaBridge | 161:aa5281ff4a02 | 1459 | /* end of struct st_vdc5_from_sc0_scl1_pbuf0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1460 | volatile uint8_t dummy30[44]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1461 | |
AnnaBridge | 161:aa5281ff4a02 | 1462 | /* start of struct st_vdc5_from_gr0_update */ |
AnnaBridge | 161:aa5281ff4a02 | 1463 | volatile uint32_t GR1_UPDATE; /* GR1_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1464 | volatile uint32_t GR1_FLM_RD; /* GR1_FLM_RD */ |
AnnaBridge | 161:aa5281ff4a02 | 1465 | |
AnnaBridge | 161:aa5281ff4a02 | 1466 | /* #define VDC5_GR1_FLM1_COUNT (6) */ |
AnnaBridge | 161:aa5281ff4a02 | 1467 | volatile uint32_t GR1_FLM1; /* GR1_FLM1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1468 | volatile uint32_t GR1_FLM2; /* GR1_FLM2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1469 | volatile uint32_t GR1_FLM3; /* GR1_FLM3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1470 | volatile uint32_t GR1_FLM4; /* GR1_FLM4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1471 | volatile uint32_t GR1_FLM5; /* GR1_FLM5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1472 | volatile uint32_t GR1_FLM6; /* GR1_FLM6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1473 | |
AnnaBridge | 161:aa5281ff4a02 | 1474 | /* #define VDC5_GR1_AB1_COUNT (3) */ |
AnnaBridge | 161:aa5281ff4a02 | 1475 | volatile uint32_t GR1_AB1; /* GR1_AB1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1476 | volatile uint32_t GR1_AB2; /* GR1_AB2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1477 | volatile uint32_t GR1_AB3; /* GR1_AB3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1478 | |
AnnaBridge | 161:aa5281ff4a02 | 1479 | /* end of struct st_vdc5_from_gr0_update */ |
AnnaBridge | 161:aa5281ff4a02 | 1480 | volatile uint32_t GR1_AB4; /* GR1_AB4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1481 | volatile uint32_t GR1_AB5; /* GR1_AB5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1482 | volatile uint32_t GR1_AB6; /* GR1_AB6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1483 | |
AnnaBridge | 161:aa5281ff4a02 | 1484 | /* start of struct st_vdc5_from_gr0_ab7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1485 | volatile uint32_t GR1_AB7; /* GR1_AB7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1486 | volatile uint32_t GR1_AB8; /* GR1_AB8 */ |
AnnaBridge | 161:aa5281ff4a02 | 1487 | volatile uint32_t GR1_AB9; /* GR1_AB9 */ |
AnnaBridge | 161:aa5281ff4a02 | 1488 | volatile uint32_t GR1_AB10; /* GR1_AB10 */ |
AnnaBridge | 161:aa5281ff4a02 | 1489 | volatile uint32_t GR1_AB11; /* GR1_AB11 */ |
AnnaBridge | 161:aa5281ff4a02 | 1490 | volatile uint32_t GR1_BASE; /* GR1_BASE */ |
AnnaBridge | 161:aa5281ff4a02 | 1491 | |
AnnaBridge | 161:aa5281ff4a02 | 1492 | /* end of struct st_vdc5_from_gr0_ab7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1493 | volatile uint32_t GR1_CLUT; /* GR1_CLUT */ |
AnnaBridge | 161:aa5281ff4a02 | 1494 | volatile uint32_t GR1_MON; /* GR1_MON */ |
AnnaBridge | 161:aa5281ff4a02 | 1495 | volatile uint8_t dummy31[40]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1496 | |
AnnaBridge | 161:aa5281ff4a02 | 1497 | /* start of struct st_vdc5_from_adj0_update */ |
AnnaBridge | 161:aa5281ff4a02 | 1498 | volatile uint32_t ADJ1_UPDATE; /* ADJ1_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1499 | volatile uint32_t ADJ1_BKSTR_SET; /* ADJ1_BKSTR_SET */ |
AnnaBridge | 161:aa5281ff4a02 | 1500 | |
AnnaBridge | 161:aa5281ff4a02 | 1501 | /* #define VDC5_ADJ1_ENH_TIM1_COUNT (3) */ |
AnnaBridge | 161:aa5281ff4a02 | 1502 | volatile uint32_t ADJ1_ENH_TIM1; /* ADJ1_ENH_TIM1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1503 | volatile uint32_t ADJ1_ENH_TIM2; /* ADJ1_ENH_TIM2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1504 | volatile uint32_t ADJ1_ENH_TIM3; /* ADJ1_ENH_TIM3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1505 | |
AnnaBridge | 161:aa5281ff4a02 | 1506 | /* #define VDC5_ADJ1_ENH_SHP1_COUNT (6) */ |
AnnaBridge | 161:aa5281ff4a02 | 1507 | volatile uint32_t ADJ1_ENH_SHP1; /* ADJ1_ENH_SHP1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1508 | volatile uint32_t ADJ1_ENH_SHP2; /* ADJ1_ENH_SHP2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1509 | volatile uint32_t ADJ1_ENH_SHP3; /* ADJ1_ENH_SHP3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1510 | volatile uint32_t ADJ1_ENH_SHP4; /* ADJ1_ENH_SHP4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1511 | volatile uint32_t ADJ1_ENH_SHP5; /* ADJ1_ENH_SHP5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1512 | volatile uint32_t ADJ1_ENH_SHP6; /* ADJ1_ENH_SHP6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1513 | |
AnnaBridge | 161:aa5281ff4a02 | 1514 | /* #define VDC5_ADJ1_ENH_LTI1_COUNT (2) */ |
AnnaBridge | 161:aa5281ff4a02 | 1515 | volatile uint32_t ADJ1_ENH_LTI1; /* ADJ1_ENH_LTI1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1516 | volatile uint32_t ADJ1_ENH_LTI2; /* ADJ1_ENH_LTI2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1517 | volatile uint32_t ADJ1_MTX_MODE; /* ADJ1_MTX_MODE */ |
AnnaBridge | 161:aa5281ff4a02 | 1518 | volatile uint32_t ADJ1_MTX_YG_ADJ0; /* ADJ1_MTX_YG_ADJ0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1519 | volatile uint32_t ADJ1_MTX_YG_ADJ1; /* ADJ1_MTX_YG_ADJ1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1520 | volatile uint32_t ADJ1_MTX_CBB_ADJ0; /* ADJ1_MTX_CBB_ADJ0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1521 | volatile uint32_t ADJ1_MTX_CBB_ADJ1; /* ADJ1_MTX_CBB_ADJ1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1522 | volatile uint32_t ADJ1_MTX_CRR_ADJ0; /* ADJ1_MTX_CRR_ADJ0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1523 | volatile uint32_t ADJ1_MTX_CRR_ADJ1; /* ADJ1_MTX_CRR_ADJ1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1524 | |
AnnaBridge | 161:aa5281ff4a02 | 1525 | /* end of struct st_vdc5_from_adj0_update */ |
AnnaBridge | 161:aa5281ff4a02 | 1526 | volatile uint8_t dummy32[48]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1527 | volatile uint32_t GR_VIN_UPDATE; /* GR_VIN_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1528 | volatile uint8_t dummy33[28]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1529 | |
AnnaBridge | 161:aa5281ff4a02 | 1530 | /* #define VDC5_GR_VIN_AB1_COUNT (7) */ |
AnnaBridge | 161:aa5281ff4a02 | 1531 | volatile uint32_t GR_VIN_AB1; /* GR_VIN_AB1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1532 | volatile uint32_t GR_VIN_AB2; /* GR_VIN_AB2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1533 | volatile uint32_t GR_VIN_AB3; /* GR_VIN_AB3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1534 | volatile uint32_t GR_VIN_AB4; /* GR_VIN_AB4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1535 | volatile uint32_t GR_VIN_AB5; /* GR_VIN_AB5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1536 | volatile uint32_t GR_VIN_AB6; /* GR_VIN_AB6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1537 | volatile uint32_t GR_VIN_AB7; /* GR_VIN_AB7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1538 | volatile uint8_t dummy34[16]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1539 | volatile uint32_t GR_VIN_BASE; /* GR_VIN_BASE */ |
AnnaBridge | 161:aa5281ff4a02 | 1540 | volatile uint8_t dummy35[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1541 | volatile uint32_t GR_VIN_MON; /* GR_VIN_MON */ |
AnnaBridge | 161:aa5281ff4a02 | 1542 | volatile uint8_t dummy36[40]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1543 | volatile uint32_t OIR_SCL0_UPDATE; /* OIR_SCL0_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1544 | |
AnnaBridge | 161:aa5281ff4a02 | 1545 | /* #define VDC5_OIR_SCL0_FRC1_COUNT (7) */ |
AnnaBridge | 161:aa5281ff4a02 | 1546 | volatile uint32_t OIR_SCL0_FRC1; /* OIR_SCL0_FRC1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1547 | volatile uint32_t OIR_SCL0_FRC2; /* OIR_SCL0_FRC2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1548 | volatile uint32_t OIR_SCL0_FRC3; /* OIR_SCL0_FRC3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1549 | volatile uint32_t OIR_SCL0_FRC4; /* OIR_SCL0_FRC4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1550 | volatile uint32_t OIR_SCL0_FRC5; /* OIR_SCL0_FRC5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1551 | volatile uint32_t OIR_SCL0_FRC6; /* OIR_SCL0_FRC6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1552 | volatile uint32_t OIR_SCL0_FRC7; /* OIR_SCL0_FRC7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1553 | volatile uint8_t dummy37[12]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1554 | |
AnnaBridge | 161:aa5281ff4a02 | 1555 | /* #define VDC5_OIR_SCL0_DS1_COUNT (3) */ |
AnnaBridge | 161:aa5281ff4a02 | 1556 | volatile uint32_t OIR_SCL0_DS1; /* OIR_SCL0_DS1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1557 | volatile uint32_t OIR_SCL0_DS2; /* OIR_SCL0_DS2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1558 | volatile uint32_t OIR_SCL0_DS3; /* OIR_SCL0_DS3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1559 | volatile uint8_t dummy38[12]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1560 | volatile uint32_t OIR_SCL0_DS7; /* OIR_SCL0_DS7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1561 | volatile uint32_t OIR_SCL0_US1; /* OIR_SCL0_US1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1562 | volatile uint32_t OIR_SCL0_US2; /* OIR_SCL0_US2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1563 | volatile uint32_t OIR_SCL0_US3; /* OIR_SCL0_US3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1564 | volatile uint8_t dummy39[16]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1565 | volatile uint32_t OIR_SCL0_US8; /* OIR_SCL0_US8 */ |
AnnaBridge | 161:aa5281ff4a02 | 1566 | volatile uint8_t dummy40[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1567 | volatile uint32_t OIR_SCL0_OVR1; /* OIR_SCL0_OVR1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1568 | volatile uint8_t dummy41[16]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1569 | volatile uint32_t OIR_SCL1_UPDATE; /* OIR_SCL1_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1570 | volatile uint8_t dummy42[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1571 | |
AnnaBridge | 161:aa5281ff4a02 | 1572 | /* #define VDC5_OIR_SCL1_WR1_COUNT (4) */ |
AnnaBridge | 161:aa5281ff4a02 | 1573 | volatile uint32_t OIR_SCL1_WR1; /* OIR_SCL1_WR1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1574 | volatile uint32_t OIR_SCL1_WR2; /* OIR_SCL1_WR2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1575 | volatile uint32_t OIR_SCL1_WR3; /* OIR_SCL1_WR3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1576 | volatile uint32_t OIR_SCL1_WR4; /* OIR_SCL1_WR4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1577 | volatile uint8_t dummy43[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1578 | volatile uint32_t OIR_SCL1_WR5; /* OIR_SCL1_WR5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1579 | volatile uint32_t OIR_SCL1_WR6; /* OIR_SCL1_WR6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1580 | volatile uint32_t OIR_SCL1_WR7; /* OIR_SCL1_WR7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1581 | volatile uint8_t dummy44[88]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1582 | volatile uint32_t GR_OIR_UPDATE; /* GR_OIR_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1583 | volatile uint32_t GR_OIR_FLM_RD; /* GR_OIR_FLM_RD */ |
AnnaBridge | 161:aa5281ff4a02 | 1584 | |
AnnaBridge | 161:aa5281ff4a02 | 1585 | /* #define VDC5_GR_OIR_FLM1_COUNT (6) */ |
AnnaBridge | 161:aa5281ff4a02 | 1586 | volatile uint32_t GR_OIR_FLM1; /* GR_OIR_FLM1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1587 | volatile uint32_t GR_OIR_FLM2; /* GR_OIR_FLM2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1588 | volatile uint32_t GR_OIR_FLM3; /* GR_OIR_FLM3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1589 | volatile uint32_t GR_OIR_FLM4; /* GR_OIR_FLM4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1590 | volatile uint32_t GR_OIR_FLM5; /* GR_OIR_FLM5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1591 | volatile uint32_t GR_OIR_FLM6; /* GR_OIR_FLM6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1592 | |
AnnaBridge | 161:aa5281ff4a02 | 1593 | /* #define VDC5_GR_OIR_AB1_COUNT (3) */ |
AnnaBridge | 161:aa5281ff4a02 | 1594 | volatile uint32_t GR_OIR_AB1; /* GR_OIR_AB1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1595 | volatile uint32_t GR_OIR_AB2; /* GR_OIR_AB2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1596 | volatile uint32_t GR_OIR_AB3; /* GR_OIR_AB3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1597 | volatile uint8_t dummy45[12]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1598 | volatile uint32_t GR_OIR_AB7; /* GR_OIR_AB7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1599 | volatile uint32_t GR_OIR_AB8; /* GR_OIR_AB8 */ |
AnnaBridge | 161:aa5281ff4a02 | 1600 | volatile uint32_t GR_OIR_AB9; /* GR_OIR_AB9 */ |
AnnaBridge | 161:aa5281ff4a02 | 1601 | volatile uint32_t GR_OIR_AB10; /* GR_OIR_AB10 */ |
AnnaBridge | 161:aa5281ff4a02 | 1602 | volatile uint32_t GR_OIR_AB11; /* GR_OIR_AB11 */ |
AnnaBridge | 161:aa5281ff4a02 | 1603 | volatile uint32_t GR_OIR_BASE; /* GR_OIR_BASE */ |
AnnaBridge | 161:aa5281ff4a02 | 1604 | volatile uint32_t GR_OIR_CLUT; /* GR_OIR_CLUT */ |
AnnaBridge | 161:aa5281ff4a02 | 1605 | volatile uint32_t GR_OIR_MON; /* GR_OIR_MON */ |
AnnaBridge | 161:aa5281ff4a02 | 1606 | } r_io_vdc5_t; |
AnnaBridge | 161:aa5281ff4a02 | 1607 | |
AnnaBridge | 161:aa5281ff4a02 | 1608 | |
AnnaBridge | 161:aa5281ff4a02 | 1609 | typedef struct st_vdc5_from_gr0_update |
AnnaBridge | 161:aa5281ff4a02 | 1610 | { |
AnnaBridge | 161:aa5281ff4a02 | 1611 | |
AnnaBridge | 161:aa5281ff4a02 | 1612 | volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1613 | volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */ |
AnnaBridge | 161:aa5281ff4a02 | 1614 | volatile uint32_t GR0_FLM1; /* GR0_FLM1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1615 | volatile uint32_t GR0_FLM2; /* GR0_FLM2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1616 | volatile uint32_t GR0_FLM3; /* GR0_FLM3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1617 | volatile uint32_t GR0_FLM4; /* GR0_FLM4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1618 | volatile uint32_t GR0_FLM5; /* GR0_FLM5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1619 | volatile uint32_t GR0_FLM6; /* GR0_FLM6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1620 | volatile uint32_t GR0_AB1; /* GR0_AB1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1621 | volatile uint32_t GR0_AB2; /* GR0_AB2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1622 | volatile uint32_t GR0_AB3; /* GR0_AB3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1623 | } r_io_vdc5_from_gr0_update_t; |
AnnaBridge | 161:aa5281ff4a02 | 1624 | |
AnnaBridge | 161:aa5281ff4a02 | 1625 | |
AnnaBridge | 161:aa5281ff4a02 | 1626 | typedef struct st_vdc5_from_gr0_ab7 |
AnnaBridge | 161:aa5281ff4a02 | 1627 | { |
AnnaBridge | 161:aa5281ff4a02 | 1628 | |
AnnaBridge | 161:aa5281ff4a02 | 1629 | volatile uint32_t GR0_AB7; /* GR0_AB7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1630 | volatile uint32_t GR0_AB8; /* GR0_AB8 */ |
AnnaBridge | 161:aa5281ff4a02 | 1631 | volatile uint32_t GR0_AB9; /* GR0_AB9 */ |
AnnaBridge | 161:aa5281ff4a02 | 1632 | volatile uint32_t GR0_AB10; /* GR0_AB10 */ |
AnnaBridge | 161:aa5281ff4a02 | 1633 | volatile uint32_t GR0_AB11; /* GR0_AB11 */ |
AnnaBridge | 161:aa5281ff4a02 | 1634 | volatile uint32_t GR0_BASE; /* GR0_BASE */ |
AnnaBridge | 161:aa5281ff4a02 | 1635 | } r_io_vdc5_from_gr0_ab7_t; |
AnnaBridge | 161:aa5281ff4a02 | 1636 | |
AnnaBridge | 161:aa5281ff4a02 | 1637 | |
AnnaBridge | 161:aa5281ff4a02 | 1638 | typedef struct st_vdc5_from_adj0_update |
AnnaBridge | 161:aa5281ff4a02 | 1639 | { |
AnnaBridge | 161:aa5281ff4a02 | 1640 | |
AnnaBridge | 161:aa5281ff4a02 | 1641 | volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1642 | volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */ |
AnnaBridge | 161:aa5281ff4a02 | 1643 | volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1644 | volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1645 | volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1646 | volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1647 | volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1648 | volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1649 | volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1650 | volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1651 | volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1652 | volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1653 | volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1654 | volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */ |
AnnaBridge | 161:aa5281ff4a02 | 1655 | volatile uint32_t ADJ0_MTX_YG_ADJ0; /* ADJ0_MTX_YG_ADJ0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1656 | volatile uint32_t ADJ0_MTX_YG_ADJ1; /* ADJ0_MTX_YG_ADJ1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1657 | volatile uint32_t ADJ0_MTX_CBB_ADJ0; /* ADJ0_MTX_CBB_ADJ0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1658 | volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1659 | volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1660 | volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1661 | } r_io_vdc5_from_adj0_update_t; |
AnnaBridge | 161:aa5281ff4a02 | 1662 | |
AnnaBridge | 161:aa5281ff4a02 | 1663 | |
AnnaBridge | 161:aa5281ff4a02 | 1664 | typedef struct st_vdc5_from_sc0_scl0_update |
AnnaBridge | 161:aa5281ff4a02 | 1665 | { |
AnnaBridge | 161:aa5281ff4a02 | 1666 | |
AnnaBridge | 161:aa5281ff4a02 | 1667 | volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1668 | volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1669 | volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1670 | volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1671 | volatile uint32_t SC0_SCL0_FRC4; /* SC0_SCL0_FRC4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1672 | volatile uint32_t SC0_SCL0_FRC5; /* SC0_SCL0_FRC5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1673 | volatile uint32_t SC0_SCL0_FRC6; /* SC0_SCL0_FRC6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1674 | volatile uint32_t SC0_SCL0_FRC7; /* SC0_SCL0_FRC7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1675 | volatile uint8_t dummy5[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1676 | volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */ |
AnnaBridge | 161:aa5281ff4a02 | 1677 | volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1678 | volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */ |
AnnaBridge | 161:aa5281ff4a02 | 1679 | volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1680 | volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1681 | volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1682 | volatile uint32_t SC0_SCL0_DS4; /* SC0_SCL0_DS4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1683 | volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1684 | volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1685 | volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1686 | volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1687 | volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1688 | volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1689 | volatile uint32_t SC0_SCL0_US4; /* SC0_SCL0_US4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1690 | volatile uint32_t SC0_SCL0_US5; /* SC0_SCL0_US5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1691 | volatile uint32_t SC0_SCL0_US6; /* SC0_SCL0_US6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1692 | volatile uint32_t SC0_SCL0_US7; /* SC0_SCL0_US7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1693 | volatile uint32_t SC0_SCL0_US8; /* SC0_SCL0_US8 */ |
AnnaBridge | 161:aa5281ff4a02 | 1694 | volatile uint8_t dummy6[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1695 | volatile uint32_t SC0_SCL0_OVR1; /* SC0_SCL0_OVR1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1696 | volatile uint8_t dummy7[16]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1697 | volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */ |
AnnaBridge | 161:aa5281ff4a02 | 1698 | volatile uint8_t dummy8[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1699 | volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1700 | volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1701 | volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1702 | volatile uint32_t SC0_SCL1_WR4; /* SC0_SCL1_WR4 */ |
AnnaBridge | 161:aa5281ff4a02 | 1703 | volatile uint8_t dummy9[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 1704 | volatile uint32_t SC0_SCL1_WR5; /* SC0_SCL1_WR5 */ |
AnnaBridge | 161:aa5281ff4a02 | 1705 | volatile uint32_t SC0_SCL1_WR6; /* SC0_SCL1_WR6 */ |
AnnaBridge | 161:aa5281ff4a02 | 1706 | volatile uint32_t SC0_SCL1_WR7; /* SC0_SCL1_WR7 */ |
AnnaBridge | 161:aa5281ff4a02 | 1707 | volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */ |
AnnaBridge | 161:aa5281ff4a02 | 1708 | volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */ |
AnnaBridge | 161:aa5281ff4a02 | 1709 | volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */ |
AnnaBridge | 161:aa5281ff4a02 | 1710 | } r_io_vdc5_from_sc0_scl0_updat_t /* Short of r_io_vdc5_from_sc0_scl0_update_t */; |
AnnaBridge | 161:aa5281ff4a02 | 1711 | |
AnnaBridge | 161:aa5281ff4a02 | 1712 | |
AnnaBridge | 161:aa5281ff4a02 | 1713 | typedef struct st_vdc5_from_sc0_scl1_pbuf0 |
AnnaBridge | 161:aa5281ff4a02 | 1714 | { |
AnnaBridge | 161:aa5281ff4a02 | 1715 | |
AnnaBridge | 161:aa5281ff4a02 | 1716 | volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */ |
AnnaBridge | 161:aa5281ff4a02 | 1717 | volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1718 | volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1719 | volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */ |
AnnaBridge | 161:aa5281ff4a02 | 1720 | volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */ |
AnnaBridge | 161:aa5281ff4a02 | 1721 | volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */ |
AnnaBridge | 161:aa5281ff4a02 | 1722 | } r_io_vdc5_from_sc0_scl1_pbuf0_t; |
AnnaBridge | 161:aa5281ff4a02 | 1723 | |
AnnaBridge | 161:aa5281ff4a02 | 1724 | |
AnnaBridge | 161:aa5281ff4a02 | 1725 | /* Channel array defines of VDC5 (2)*/ |
AnnaBridge | 161:aa5281ff4a02 | 1726 | #ifdef DECLARE_VDC5_CHANNELS |
AnnaBridge | 161:aa5281ff4a02 | 1727 | volatile struct st_vdc5* VDC5[ VDC5_COUNT ] = |
AnnaBridge | 161:aa5281ff4a02 | 1728 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1729 | VDC5_ADDRESS_LIST; |
AnnaBridge | 161:aa5281ff4a02 | 1730 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1731 | #endif /* DECLARE_VDC5_CHANNELS */ |
AnnaBridge | 161:aa5281ff4a02 | 1732 | |
AnnaBridge | 161:aa5281ff4a02 | 1733 | #ifdef DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS |
AnnaBridge | 161:aa5281ff4a02 | 1734 | volatile struct st_vdc5_from_gr0_ab7* VDC50_FROM_GR2_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_AB7_ARRAY_COUNT ] = |
AnnaBridge | 161:aa5281ff4a02 | 1735 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1736 | VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST; |
AnnaBridge | 161:aa5281ff4a02 | 1737 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1738 | #endif /* DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS */ |
AnnaBridge | 161:aa5281ff4a02 | 1739 | |
AnnaBridge | 161:aa5281ff4a02 | 1740 | #ifdef DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS |
AnnaBridge | 161:aa5281ff4a02 | 1741 | volatile struct st_vdc5_from_gr0_update* VDC50_FROM_GR2_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_UPDATE_ARRAY_COUNT ] = |
AnnaBridge | 161:aa5281ff4a02 | 1742 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1743 | VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST; |
AnnaBridge | 161:aa5281ff4a02 | 1744 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1745 | #endif /* DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS */ |
AnnaBridge | 161:aa5281ff4a02 | 1746 | |
AnnaBridge | 161:aa5281ff4a02 | 1747 | #ifdef DECLARE_VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_CHANNELS |
AnnaBridge | 161:aa5281ff4a02 | 1748 | volatile struct st_vdc5_from_sc0_scl1_pbuf0* VDC50_FROM_SC0_SCL1_PBUF0_ARRAY[ VDC5_COUNT ][ VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT ] = |
AnnaBridge | 161:aa5281ff4a02 | 1749 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1750 | VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST; |
AnnaBridge | 161:aa5281ff4a02 | 1751 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1752 | #endif /* DECLARE_VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_CHANNELS */ |
AnnaBridge | 161:aa5281ff4a02 | 1753 | |
AnnaBridge | 161:aa5281ff4a02 | 1754 | #ifdef DECLARE_VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_CHANNELS |
AnnaBridge | 161:aa5281ff4a02 | 1755 | volatile struct st_vdc5_from_sc0_scl0_update* VDC50_FROM_SC0_SCL0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT ] = |
AnnaBridge | 161:aa5281ff4a02 | 1756 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1757 | VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST; |
AnnaBridge | 161:aa5281ff4a02 | 1758 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1759 | #endif /* DECLARE_VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_CHANNELS */ |
AnnaBridge | 161:aa5281ff4a02 | 1760 | |
AnnaBridge | 161:aa5281ff4a02 | 1761 | #ifdef DECLARE_VDC50_FROM_ADJ0_UPDATE_ARRAY_CHANNELS |
AnnaBridge | 161:aa5281ff4a02 | 1762 | volatile struct st_vdc5_from_adj0_update* VDC50_FROM_ADJ0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_ADJ0_UPDATE_ARRAY_COUNT ] = |
AnnaBridge | 161:aa5281ff4a02 | 1763 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1764 | VDC50_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST; |
AnnaBridge | 161:aa5281ff4a02 | 1765 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1766 | #endif /* DECLARE_VDC50_FROM_ADJ0_UPDATE_ARRAY_CHANNELS */ |
AnnaBridge | 161:aa5281ff4a02 | 1767 | |
AnnaBridge | 161:aa5281ff4a02 | 1768 | #ifdef DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS |
AnnaBridge | 161:aa5281ff4a02 | 1769 | volatile struct st_vdc5_from_gr0_ab7* VDC50_FROM_GR0_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_AB7_ARRAY_COUNT ] = |
AnnaBridge | 161:aa5281ff4a02 | 1770 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1771 | VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST; |
AnnaBridge | 161:aa5281ff4a02 | 1772 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1773 | #endif /* DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS */ |
AnnaBridge | 161:aa5281ff4a02 | 1774 | |
AnnaBridge | 161:aa5281ff4a02 | 1775 | #ifdef DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS |
AnnaBridge | 161:aa5281ff4a02 | 1776 | volatile struct st_vdc5_from_gr0_update* VDC50_FROM_GR0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_UPDATE_ARRAY_COUNT ] = |
AnnaBridge | 161:aa5281ff4a02 | 1777 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1778 | VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST; |
AnnaBridge | 161:aa5281ff4a02 | 1779 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1780 | #endif /* DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS */ |
AnnaBridge | 161:aa5281ff4a02 | 1781 | /* End of channel array defines of VDC5 (2)*/ |
AnnaBridge | 161:aa5281ff4a02 | 1782 | |
AnnaBridge | 161:aa5281ff4a02 | 1783 | |
AnnaBridge | 161:aa5281ff4a02 | 1784 | /* <-SEC M1.10.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 1785 | /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ |
AnnaBridge | 161:aa5281ff4a02 | 1786 | /* <-QAC 0857 */ |
AnnaBridge | 161:aa5281ff4a02 | 1787 | /* <-QAC 0639 */ |
AnnaBridge | 161:aa5281ff4a02 | 1788 | #endif |