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TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/ins_tc3.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | * \file |
AnnaBridge | 171:3a7713b1edbc | 3 | * |
AnnaBridge | 171:3a7713b1edbc | 4 | * \brief Instance description for TC3 |
AnnaBridge | 171:3a7713b1edbc | 5 | * |
AnnaBridge | 171:3a7713b1edbc | 6 | * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. |
AnnaBridge | 171:3a7713b1edbc | 7 | * |
AnnaBridge | 171:3a7713b1edbc | 8 | * \asf_license_start |
AnnaBridge | 171:3a7713b1edbc | 9 | * |
AnnaBridge | 171:3a7713b1edbc | 10 | * \page License |
AnnaBridge | 171:3a7713b1edbc | 11 | * |
AnnaBridge | 171:3a7713b1edbc | 12 | * Redistribution and use in source and binary forms, with or without |
AnnaBridge | 171:3a7713b1edbc | 13 | * modification, are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 14 | * |
AnnaBridge | 171:3a7713b1edbc | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 17 | * |
AnnaBridge | 171:3a7713b1edbc | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 19 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 20 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
AnnaBridge | 171:3a7713b1edbc | 23 | * from this software without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 24 | * |
AnnaBridge | 171:3a7713b1edbc | 25 | * 4. This software may only be redistributed and used in connection with an |
AnnaBridge | 171:3a7713b1edbc | 26 | * Atmel microcontroller product. |
AnnaBridge | 171:3a7713b1edbc | 27 | * |
AnnaBridge | 171:3a7713b1edbc | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
AnnaBridge | 171:3a7713b1edbc | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
AnnaBridge | 171:3a7713b1edbc | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
AnnaBridge | 171:3a7713b1edbc | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
AnnaBridge | 171:3a7713b1edbc | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
AnnaBridge | 171:3a7713b1edbc | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
AnnaBridge | 171:3a7713b1edbc | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
AnnaBridge | 171:3a7713b1edbc | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
AnnaBridge | 171:3a7713b1edbc | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
AnnaBridge | 171:3a7713b1edbc | 38 | * POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 39 | * |
AnnaBridge | 171:3a7713b1edbc | 40 | * \asf_license_stop |
AnnaBridge | 171:3a7713b1edbc | 41 | * |
AnnaBridge | 171:3a7713b1edbc | 42 | */ |
AnnaBridge | 171:3a7713b1edbc | 43 | /* |
AnnaBridge | 171:3a7713b1edbc | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
AnnaBridge | 171:3a7713b1edbc | 45 | */ |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | #ifndef _SAMD21_TC3_INSTANCE_ |
AnnaBridge | 171:3a7713b1edbc | 48 | #define _SAMD21_TC3_INSTANCE_ |
AnnaBridge | 171:3a7713b1edbc | 49 | |
AnnaBridge | 171:3a7713b1edbc | 50 | /* ========== Register definition for TC3 peripheral ========== */ |
AnnaBridge | 171:3a7713b1edbc | 51 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 52 | #define REG_TC3_CTRLA (0x42002C00U) /**< \brief (TC3) Control A */ |
AnnaBridge | 171:3a7713b1edbc | 53 | #define REG_TC3_READREQ (0x42002C02U) /**< \brief (TC3) Read Request */ |
AnnaBridge | 171:3a7713b1edbc | 54 | #define REG_TC3_CTRLBCLR (0x42002C04U) /**< \brief (TC3) Control B Clear */ |
AnnaBridge | 171:3a7713b1edbc | 55 | #define REG_TC3_CTRLBSET (0x42002C05U) /**< \brief (TC3) Control B Set */ |
AnnaBridge | 171:3a7713b1edbc | 56 | #define REG_TC3_CTRLC (0x42002C06U) /**< \brief (TC3) Control C */ |
AnnaBridge | 171:3a7713b1edbc | 57 | #define REG_TC3_DBGCTRL (0x42002C08U) /**< \brief (TC3) Debug Control */ |
AnnaBridge | 171:3a7713b1edbc | 58 | #define REG_TC3_EVCTRL (0x42002C0AU) /**< \brief (TC3) Event Control */ |
AnnaBridge | 171:3a7713b1edbc | 59 | #define REG_TC3_INTENCLR (0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 60 | #define REG_TC3_INTENSET (0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 61 | #define REG_TC3_INTFLAG (0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 62 | #define REG_TC3_STATUS (0x42002C0FU) /**< \brief (TC3) Status */ |
AnnaBridge | 171:3a7713b1edbc | 63 | #define REG_TC3_COUNT16_COUNT (0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */ |
AnnaBridge | 171:3a7713b1edbc | 64 | #define REG_TC3_COUNT16_CC0 (0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */ |
AnnaBridge | 171:3a7713b1edbc | 65 | #define REG_TC3_COUNT16_CC1 (0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */ |
AnnaBridge | 171:3a7713b1edbc | 66 | #define REG_TC3_COUNT32_COUNT (0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */ |
AnnaBridge | 171:3a7713b1edbc | 67 | #define REG_TC3_COUNT32_CC0 (0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */ |
AnnaBridge | 171:3a7713b1edbc | 68 | #define REG_TC3_COUNT32_CC1 (0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */ |
AnnaBridge | 171:3a7713b1edbc | 69 | #define REG_TC3_COUNT8_COUNT (0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */ |
AnnaBridge | 171:3a7713b1edbc | 70 | #define REG_TC3_COUNT8_PER (0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */ |
AnnaBridge | 171:3a7713b1edbc | 71 | #define REG_TC3_COUNT8_CC0 (0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */ |
AnnaBridge | 171:3a7713b1edbc | 72 | #define REG_TC3_COUNT8_CC1 (0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */ |
AnnaBridge | 171:3a7713b1edbc | 73 | #else |
AnnaBridge | 171:3a7713b1edbc | 74 | #define REG_TC3_CTRLA (*(RwReg16*)0x42002C00U) /**< \brief (TC3) Control A */ |
AnnaBridge | 171:3a7713b1edbc | 75 | #define REG_TC3_READREQ (*(RwReg16*)0x42002C02U) /**< \brief (TC3) Read Request */ |
AnnaBridge | 171:3a7713b1edbc | 76 | #define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04U) /**< \brief (TC3) Control B Clear */ |
AnnaBridge | 171:3a7713b1edbc | 77 | #define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05U) /**< \brief (TC3) Control B Set */ |
AnnaBridge | 171:3a7713b1edbc | 78 | #define REG_TC3_CTRLC (*(RwReg8 *)0x42002C06U) /**< \brief (TC3) Control C */ |
AnnaBridge | 171:3a7713b1edbc | 79 | #define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C08U) /**< \brief (TC3) Debug Control */ |
AnnaBridge | 171:3a7713b1edbc | 80 | #define REG_TC3_EVCTRL (*(RwReg16*)0x42002C0AU) /**< \brief (TC3) Event Control */ |
AnnaBridge | 171:3a7713b1edbc | 81 | #define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 82 | #define REG_TC3_INTENSET (*(RwReg8 *)0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 83 | #define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 84 | #define REG_TC3_STATUS (*(RoReg8 *)0x42002C0FU) /**< \brief (TC3) Status */ |
AnnaBridge | 171:3a7713b1edbc | 85 | #define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */ |
AnnaBridge | 171:3a7713b1edbc | 86 | #define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */ |
AnnaBridge | 171:3a7713b1edbc | 87 | #define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */ |
AnnaBridge | 171:3a7713b1edbc | 88 | #define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */ |
AnnaBridge | 171:3a7713b1edbc | 89 | #define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */ |
AnnaBridge | 171:3a7713b1edbc | 90 | #define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */ |
AnnaBridge | 171:3a7713b1edbc | 91 | #define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */ |
AnnaBridge | 171:3a7713b1edbc | 92 | #define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */ |
AnnaBridge | 171:3a7713b1edbc | 93 | #define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */ |
AnnaBridge | 171:3a7713b1edbc | 94 | #define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */ |
AnnaBridge | 171:3a7713b1edbc | 95 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 96 | |
AnnaBridge | 171:3a7713b1edbc | 97 | /* ========== Instance parameters for TC3 peripheral ========== */ |
AnnaBridge | 171:3a7713b1edbc | 98 | #define TC3_CC8_NUM 2 // Number of 8-bit Counters |
AnnaBridge | 171:3a7713b1edbc | 99 | #define TC3_CC16_NUM 2 // Number of 16-bit Counters |
AnnaBridge | 171:3a7713b1edbc | 100 | #define TC3_CC32_NUM 2 // Number of 32-bit Counters |
AnnaBridge | 171:3a7713b1edbc | 101 | #define TC3_DITHERING_EXT 0 // Dithering feature implemented |
AnnaBridge | 171:3a7713b1edbc | 102 | #define TC3_DMAC_ID_MC_0 25 |
AnnaBridge | 171:3a7713b1edbc | 103 | #define TC3_DMAC_ID_MC_1 26 |
AnnaBridge | 171:3a7713b1edbc | 104 | #define TC3_DMAC_ID_MC_LSB 25 |
AnnaBridge | 171:3a7713b1edbc | 105 | #define TC3_DMAC_ID_MC_MSB 26 |
AnnaBridge | 171:3a7713b1edbc | 106 | #define TC3_DMAC_ID_MC_SIZE 2 |
AnnaBridge | 171:3a7713b1edbc | 107 | #define TC3_DMAC_ID_OVF 24 // Indexes of DMA Overflow trigger |
AnnaBridge | 171:3a7713b1edbc | 108 | #define TC3_GCLK_ID 27 // Index of Generic Clock |
AnnaBridge | 171:3a7713b1edbc | 109 | #define TC3_MASTER 0 |
AnnaBridge | 171:3a7713b1edbc | 110 | #define TC3_OW_NUM 2 // Number of Output Waveforms |
AnnaBridge | 171:3a7713b1edbc | 111 | #define TC3_PERIOD_EXT 0 // Period feature implemented |
AnnaBridge | 171:3a7713b1edbc | 112 | #define TC3_SHADOW_EXT 0 // Shadow feature implemented |
AnnaBridge | 171:3a7713b1edbc | 113 | |
AnnaBridge | 171:3a7713b1edbc | 114 | #endif /* _SAMD21_TC3_INSTANCE_ */ |