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TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/ins_pm.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | * \file |
AnnaBridge | 171:3a7713b1edbc | 3 | * |
AnnaBridge | 171:3a7713b1edbc | 4 | * \brief Instance description for PM |
AnnaBridge | 171:3a7713b1edbc | 5 | * |
AnnaBridge | 171:3a7713b1edbc | 6 | * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. |
AnnaBridge | 171:3a7713b1edbc | 7 | * |
AnnaBridge | 171:3a7713b1edbc | 8 | * \asf_license_start |
AnnaBridge | 171:3a7713b1edbc | 9 | * |
AnnaBridge | 171:3a7713b1edbc | 10 | * \page License |
AnnaBridge | 171:3a7713b1edbc | 11 | * |
AnnaBridge | 171:3a7713b1edbc | 12 | * Redistribution and use in source and binary forms, with or without |
AnnaBridge | 171:3a7713b1edbc | 13 | * modification, are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 14 | * |
AnnaBridge | 171:3a7713b1edbc | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 17 | * |
AnnaBridge | 171:3a7713b1edbc | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 19 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 20 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
AnnaBridge | 171:3a7713b1edbc | 23 | * from this software without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 24 | * |
AnnaBridge | 171:3a7713b1edbc | 25 | * 4. This software may only be redistributed and used in connection with an |
AnnaBridge | 171:3a7713b1edbc | 26 | * Atmel microcontroller product. |
AnnaBridge | 171:3a7713b1edbc | 27 | * |
AnnaBridge | 171:3a7713b1edbc | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
AnnaBridge | 171:3a7713b1edbc | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
AnnaBridge | 171:3a7713b1edbc | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
AnnaBridge | 171:3a7713b1edbc | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
AnnaBridge | 171:3a7713b1edbc | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
AnnaBridge | 171:3a7713b1edbc | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
AnnaBridge | 171:3a7713b1edbc | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
AnnaBridge | 171:3a7713b1edbc | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
AnnaBridge | 171:3a7713b1edbc | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
AnnaBridge | 171:3a7713b1edbc | 38 | * POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 39 | * |
AnnaBridge | 171:3a7713b1edbc | 40 | * \asf_license_stop |
AnnaBridge | 171:3a7713b1edbc | 41 | * |
AnnaBridge | 171:3a7713b1edbc | 42 | */ |
AnnaBridge | 171:3a7713b1edbc | 43 | /* |
AnnaBridge | 171:3a7713b1edbc | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
AnnaBridge | 171:3a7713b1edbc | 45 | */ |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | #ifndef _SAMD21_PM_INSTANCE_ |
AnnaBridge | 171:3a7713b1edbc | 48 | #define _SAMD21_PM_INSTANCE_ |
AnnaBridge | 171:3a7713b1edbc | 49 | |
AnnaBridge | 171:3a7713b1edbc | 50 | /* ========== Register definition for PM peripheral ========== */ |
AnnaBridge | 171:3a7713b1edbc | 51 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 52 | #define REG_PM_CTRL (0x40000400U) /**< \brief (PM) Control */ |
AnnaBridge | 171:3a7713b1edbc | 53 | #define REG_PM_SLEEP (0x40000401U) /**< \brief (PM) Sleep Mode */ |
AnnaBridge | 171:3a7713b1edbc | 54 | #define REG_PM_EXTCTRL (0x40000402U) /**< \brief (PM) External Reset Controller */ |
AnnaBridge | 171:3a7713b1edbc | 55 | #define REG_PM_CPUSEL (0x40000408U) /**< \brief (PM) CPU Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 56 | #define REG_PM_APBASEL (0x40000409U) /**< \brief (PM) APBA Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 57 | #define REG_PM_APBBSEL (0x4000040AU) /**< \brief (PM) APBB Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 58 | #define REG_PM_APBCSEL (0x4000040BU) /**< \brief (PM) APBC Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 59 | #define REG_PM_AHBMASK (0x40000414U) /**< \brief (PM) AHB Mask */ |
AnnaBridge | 171:3a7713b1edbc | 60 | #define REG_PM_APBAMASK (0x40000418U) /**< \brief (PM) APBA Mask */ |
AnnaBridge | 171:3a7713b1edbc | 61 | #define REG_PM_APBBMASK (0x4000041CU) /**< \brief (PM) APBB Mask */ |
AnnaBridge | 171:3a7713b1edbc | 62 | #define REG_PM_APBCMASK (0x40000420U) /**< \brief (PM) APBC Mask */ |
AnnaBridge | 171:3a7713b1edbc | 63 | #define REG_PM_INTENCLR (0x40000434U) /**< \brief (PM) Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 64 | #define REG_PM_INTENSET (0x40000435U) /**< \brief (PM) Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 65 | #define REG_PM_INTFLAG (0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 66 | #define REG_PM_RCAUSE (0x40000438U) /**< \brief (PM) Reset Cause */ |
AnnaBridge | 171:3a7713b1edbc | 67 | #else |
AnnaBridge | 171:3a7713b1edbc | 68 | #define REG_PM_CTRL (*(RwReg8 *)0x40000400U) /**< \brief (PM) Control */ |
AnnaBridge | 171:3a7713b1edbc | 69 | #define REG_PM_SLEEP (*(RwReg8 *)0x40000401U) /**< \brief (PM) Sleep Mode */ |
AnnaBridge | 171:3a7713b1edbc | 70 | #define REG_PM_EXTCTRL (*(RwReg8 *)0x40000402U) /**< \brief (PM) External Reset Controller */ |
AnnaBridge | 171:3a7713b1edbc | 71 | #define REG_PM_CPUSEL (*(RwReg8 *)0x40000408U) /**< \brief (PM) CPU Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 72 | #define REG_PM_APBASEL (*(RwReg8 *)0x40000409U) /**< \brief (PM) APBA Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 73 | #define REG_PM_APBBSEL (*(RwReg8 *)0x4000040AU) /**< \brief (PM) APBB Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 74 | #define REG_PM_APBCSEL (*(RwReg8 *)0x4000040BU) /**< \brief (PM) APBC Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 75 | #define REG_PM_AHBMASK (*(RwReg *)0x40000414U) /**< \brief (PM) AHB Mask */ |
AnnaBridge | 171:3a7713b1edbc | 76 | #define REG_PM_APBAMASK (*(RwReg *)0x40000418U) /**< \brief (PM) APBA Mask */ |
AnnaBridge | 171:3a7713b1edbc | 77 | #define REG_PM_APBBMASK (*(RwReg *)0x4000041CU) /**< \brief (PM) APBB Mask */ |
AnnaBridge | 171:3a7713b1edbc | 78 | #define REG_PM_APBCMASK (*(RwReg *)0x40000420U) /**< \brief (PM) APBC Mask */ |
AnnaBridge | 171:3a7713b1edbc | 79 | #define REG_PM_INTENCLR (*(RwReg8 *)0x40000434U) /**< \brief (PM) Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 80 | #define REG_PM_INTENSET (*(RwReg8 *)0x40000435U) /**< \brief (PM) Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 81 | #define REG_PM_INTFLAG (*(RwReg8 *)0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 82 | #define REG_PM_RCAUSE (*(RoReg8 *)0x40000438U) /**< \brief (PM) Reset Cause */ |
AnnaBridge | 171:3a7713b1edbc | 83 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 84 | |
AnnaBridge | 171:3a7713b1edbc | 85 | /* ========== Instance parameters for PM peripheral ========== */ |
AnnaBridge | 171:3a7713b1edbc | 86 | #define PM_CTRL_MCSEL_DFLL48M 3 |
AnnaBridge | 171:3a7713b1edbc | 87 | #define PM_CTRL_MCSEL_GCLK 0 |
AnnaBridge | 171:3a7713b1edbc | 88 | #define PM_CTRL_MCSEL_OSC8M 1 |
AnnaBridge | 171:3a7713b1edbc | 89 | #define PM_CTRL_MCSEL_XOSC 2 |
AnnaBridge | 171:3a7713b1edbc | 90 | #define PM_PM_CLK_APB_NUM 2 |
AnnaBridge | 171:3a7713b1edbc | 91 | |
AnnaBridge | 171:3a7713b1edbc | 92 | #endif /* _SAMD21_PM_INSTANCE_ */ |