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TARGET_SAMD21J18A/TOOLCHAIN_ARM_STD/ins_rtc.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | * \file |
AnnaBridge | 171:3a7713b1edbc | 3 | * |
AnnaBridge | 171:3a7713b1edbc | 4 | * \brief Instance description for RTC |
AnnaBridge | 171:3a7713b1edbc | 5 | * |
AnnaBridge | 171:3a7713b1edbc | 6 | * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. |
AnnaBridge | 171:3a7713b1edbc | 7 | * |
AnnaBridge | 171:3a7713b1edbc | 8 | * \asf_license_start |
AnnaBridge | 171:3a7713b1edbc | 9 | * |
AnnaBridge | 171:3a7713b1edbc | 10 | * \page License |
AnnaBridge | 171:3a7713b1edbc | 11 | * |
AnnaBridge | 171:3a7713b1edbc | 12 | * Redistribution and use in source and binary forms, with or without |
AnnaBridge | 171:3a7713b1edbc | 13 | * modification, are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 14 | * |
AnnaBridge | 171:3a7713b1edbc | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 17 | * |
AnnaBridge | 171:3a7713b1edbc | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 19 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 20 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
AnnaBridge | 171:3a7713b1edbc | 23 | * from this software without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 24 | * |
AnnaBridge | 171:3a7713b1edbc | 25 | * 4. This software may only be redistributed and used in connection with an |
AnnaBridge | 171:3a7713b1edbc | 26 | * Atmel microcontroller product. |
AnnaBridge | 171:3a7713b1edbc | 27 | * |
AnnaBridge | 171:3a7713b1edbc | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
AnnaBridge | 171:3a7713b1edbc | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
AnnaBridge | 171:3a7713b1edbc | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
AnnaBridge | 171:3a7713b1edbc | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
AnnaBridge | 171:3a7713b1edbc | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
AnnaBridge | 171:3a7713b1edbc | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
AnnaBridge | 171:3a7713b1edbc | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
AnnaBridge | 171:3a7713b1edbc | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
AnnaBridge | 171:3a7713b1edbc | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
AnnaBridge | 171:3a7713b1edbc | 38 | * POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 39 | * |
AnnaBridge | 171:3a7713b1edbc | 40 | * \asf_license_stop |
AnnaBridge | 171:3a7713b1edbc | 41 | * |
AnnaBridge | 171:3a7713b1edbc | 42 | */ |
AnnaBridge | 171:3a7713b1edbc | 43 | /* |
AnnaBridge | 171:3a7713b1edbc | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
AnnaBridge | 171:3a7713b1edbc | 45 | */ |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | #ifndef _SAMD21_RTC_INSTANCE_ |
AnnaBridge | 171:3a7713b1edbc | 48 | #define _SAMD21_RTC_INSTANCE_ |
AnnaBridge | 171:3a7713b1edbc | 49 | |
AnnaBridge | 171:3a7713b1edbc | 50 | /* ========== Register definition for RTC peripheral ========== */ |
AnnaBridge | 171:3a7713b1edbc | 51 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 52 | #define REG_RTC_READREQ (0x40001402U) /**< \brief (RTC) Read Request */ |
AnnaBridge | 171:3a7713b1edbc | 53 | #define REG_RTC_STATUS (0x4000140AU) /**< \brief (RTC) Status */ |
AnnaBridge | 171:3a7713b1edbc | 54 | #define REG_RTC_DBGCTRL (0x4000140BU) /**< \brief (RTC) Debug Control */ |
AnnaBridge | 171:3a7713b1edbc | 55 | #define REG_RTC_FREQCORR (0x4000140CU) /**< \brief (RTC) Frequency Correction */ |
AnnaBridge | 171:3a7713b1edbc | 56 | #define REG_RTC_MODE0_CTRL (0x40001400U) /**< \brief (RTC) MODE0 Control */ |
AnnaBridge | 171:3a7713b1edbc | 57 | #define REG_RTC_MODE0_EVCTRL (0x40001404U) /**< \brief (RTC) MODE0 Event Control */ |
AnnaBridge | 171:3a7713b1edbc | 58 | #define REG_RTC_MODE0_INTENCLR (0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 59 | #define REG_RTC_MODE0_INTENSET (0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 60 | #define REG_RTC_MODE0_INTFLAG (0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 61 | #define REG_RTC_MODE0_COUNT (0x40001410U) /**< \brief (RTC) MODE0 Counter Value */ |
AnnaBridge | 171:3a7713b1edbc | 62 | #define REG_RTC_MODE0_COMP0 (0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */ |
AnnaBridge | 171:3a7713b1edbc | 63 | #define REG_RTC_MODE1_CTRL (0x40001400U) /**< \brief (RTC) MODE1 Control */ |
AnnaBridge | 171:3a7713b1edbc | 64 | #define REG_RTC_MODE1_EVCTRL (0x40001404U) /**< \brief (RTC) MODE1 Event Control */ |
AnnaBridge | 171:3a7713b1edbc | 65 | #define REG_RTC_MODE1_INTENCLR (0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 66 | #define REG_RTC_MODE1_INTENSET (0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 67 | #define REG_RTC_MODE1_INTFLAG (0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 68 | #define REG_RTC_MODE1_COUNT (0x40001410U) /**< \brief (RTC) MODE1 Counter Value */ |
AnnaBridge | 171:3a7713b1edbc | 69 | #define REG_RTC_MODE1_PER (0x40001414U) /**< \brief (RTC) MODE1 Counter Period */ |
AnnaBridge | 171:3a7713b1edbc | 70 | #define REG_RTC_MODE1_COMP0 (0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */ |
AnnaBridge | 171:3a7713b1edbc | 71 | #define REG_RTC_MODE1_COMP1 (0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */ |
AnnaBridge | 171:3a7713b1edbc | 72 | #define REG_RTC_MODE2_CTRL (0x40001400U) /**< \brief (RTC) MODE2 Control */ |
AnnaBridge | 171:3a7713b1edbc | 73 | #define REG_RTC_MODE2_EVCTRL (0x40001404U) /**< \brief (RTC) MODE2 Event Control */ |
AnnaBridge | 171:3a7713b1edbc | 74 | #define REG_RTC_MODE2_INTENCLR (0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 75 | #define REG_RTC_MODE2_INTENSET (0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 76 | #define REG_RTC_MODE2_INTFLAG (0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 77 | #define REG_RTC_MODE2_CLOCK (0x40001410U) /**< \brief (RTC) MODE2 Clock Value */ |
AnnaBridge | 171:3a7713b1edbc | 78 | #define REG_RTC_MODE2_ALARM_ALARM0 (0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ |
AnnaBridge | 171:3a7713b1edbc | 79 | #define REG_RTC_MODE2_ALARM_MASK0 (0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ |
AnnaBridge | 171:3a7713b1edbc | 80 | #else |
AnnaBridge | 171:3a7713b1edbc | 81 | #define REG_RTC_READREQ (*(RwReg16*)0x40001402U) /**< \brief (RTC) Read Request */ |
AnnaBridge | 171:3a7713b1edbc | 82 | #define REG_RTC_STATUS (*(RwReg8 *)0x4000140AU) /**< \brief (RTC) Status */ |
AnnaBridge | 171:3a7713b1edbc | 83 | #define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000140BU) /**< \brief (RTC) Debug Control */ |
AnnaBridge | 171:3a7713b1edbc | 84 | #define REG_RTC_FREQCORR (*(RwReg8 *)0x4000140CU) /**< \brief (RTC) Frequency Correction */ |
AnnaBridge | 171:3a7713b1edbc | 85 | #define REG_RTC_MODE0_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE0 Control */ |
AnnaBridge | 171:3a7713b1edbc | 86 | #define REG_RTC_MODE0_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE0 Event Control */ |
AnnaBridge | 171:3a7713b1edbc | 87 | #define REG_RTC_MODE0_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 88 | #define REG_RTC_MODE0_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 89 | #define REG_RTC_MODE0_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 90 | #define REG_RTC_MODE0_COUNT (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE0 Counter Value */ |
AnnaBridge | 171:3a7713b1edbc | 91 | #define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */ |
AnnaBridge | 171:3a7713b1edbc | 92 | #define REG_RTC_MODE1_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE1 Control */ |
AnnaBridge | 171:3a7713b1edbc | 93 | #define REG_RTC_MODE1_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE1 Event Control */ |
AnnaBridge | 171:3a7713b1edbc | 94 | #define REG_RTC_MODE1_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 95 | #define REG_RTC_MODE1_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 96 | #define REG_RTC_MODE1_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 97 | #define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40001410U) /**< \brief (RTC) MODE1 Counter Value */ |
AnnaBridge | 171:3a7713b1edbc | 98 | #define REG_RTC_MODE1_PER (*(RwReg16*)0x40001414U) /**< \brief (RTC) MODE1 Counter Period */ |
AnnaBridge | 171:3a7713b1edbc | 99 | #define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */ |
AnnaBridge | 171:3a7713b1edbc | 100 | #define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */ |
AnnaBridge | 171:3a7713b1edbc | 101 | #define REG_RTC_MODE2_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE2 Control */ |
AnnaBridge | 171:3a7713b1edbc | 102 | #define REG_RTC_MODE2_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE2 Event Control */ |
AnnaBridge | 171:3a7713b1edbc | 103 | #define REG_RTC_MODE2_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 104 | #define REG_RTC_MODE2_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 105 | #define REG_RTC_MODE2_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 106 | #define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE2 Clock Value */ |
AnnaBridge | 171:3a7713b1edbc | 107 | #define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ |
AnnaBridge | 171:3a7713b1edbc | 108 | #define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg *)0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ |
AnnaBridge | 171:3a7713b1edbc | 109 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 110 | |
AnnaBridge | 171:3a7713b1edbc | 111 | /* ========== Instance parameters for RTC peripheral ========== */ |
AnnaBridge | 171:3a7713b1edbc | 112 | #define RTC_ALARM_NUM 1 // Number of Alarms |
AnnaBridge | 171:3a7713b1edbc | 113 | #define RTC_COMP16_NUM 2 // Number of 16-bit Comparators |
AnnaBridge | 171:3a7713b1edbc | 114 | #define RTC_COMP32_NUM 1 // Number of 32-bit Comparators |
AnnaBridge | 171:3a7713b1edbc | 115 | #define RTC_GCLK_ID 4 // Index of Generic Clock |
AnnaBridge | 171:3a7713b1edbc | 116 | #define RTC_NUM_OF_ALARMS 1 // Number of Alarms (obsolete) |
AnnaBridge | 171:3a7713b1edbc | 117 | #define RTC_NUM_OF_COMP16 2 // Number of 16-bit Comparators (obsolete) |
AnnaBridge | 171:3a7713b1edbc | 118 | #define RTC_NUM_OF_COMP32 1 // Number of 32-bit Comparators (obsolete) |
AnnaBridge | 171:3a7713b1edbc | 119 | |
AnnaBridge | 171:3a7713b1edbc | 120 | #endif /* _SAMD21_RTC_INSTANCE_ */ |