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TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/scux_iodefine.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 161:aa5281ff4a02 | 1 | /******************************************************************************* |
AnnaBridge | 161:aa5281ff4a02 | 2 | * DISCLAIMER |
AnnaBridge | 161:aa5281ff4a02 | 3 | * This software is supplied by Renesas Electronics Corporation and is only |
AnnaBridge | 161:aa5281ff4a02 | 4 | * intended for use with Renesas products. No other uses are authorized. This |
AnnaBridge | 161:aa5281ff4a02 | 5 | * software is owned by Renesas Electronics Corporation and is protected under |
AnnaBridge | 161:aa5281ff4a02 | 6 | * all applicable laws, including copyright laws. |
AnnaBridge | 161:aa5281ff4a02 | 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING |
AnnaBridge | 161:aa5281ff4a02 | 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT |
AnnaBridge | 161:aa5281ff4a02 | 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE |
AnnaBridge | 161:aa5281ff4a02 | 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. |
AnnaBridge | 161:aa5281ff4a02 | 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS |
AnnaBridge | 161:aa5281ff4a02 | 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE |
AnnaBridge | 161:aa5281ff4a02 | 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR |
AnnaBridge | 161:aa5281ff4a02 | 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE |
AnnaBridge | 161:aa5281ff4a02 | 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
AnnaBridge | 161:aa5281ff4a02 | 16 | * Renesas reserves the right, without notice, to make changes to this software |
AnnaBridge | 161:aa5281ff4a02 | 17 | * and to discontinue the availability of this software. By using this software, |
AnnaBridge | 161:aa5281ff4a02 | 18 | * you agree to the additional terms and conditions found by accessing the |
AnnaBridge | 161:aa5281ff4a02 | 19 | * following link: |
AnnaBridge | 161:aa5281ff4a02 | 20 | * http://www.renesas.com/disclaimer* |
AnnaBridge | 161:aa5281ff4a02 | 21 | * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. |
AnnaBridge | 161:aa5281ff4a02 | 22 | *******************************************************************************/ |
AnnaBridge | 161:aa5281ff4a02 | 23 | /******************************************************************************* |
AnnaBridge | 161:aa5281ff4a02 | 24 | * File Name : scux_iodefine.h |
AnnaBridge | 161:aa5281ff4a02 | 25 | * $Rev: $ |
AnnaBridge | 161:aa5281ff4a02 | 26 | * $Date:: $ |
AnnaBridge | 161:aa5281ff4a02 | 27 | * Description : Definition of I/O Register for RZ/A1H,M (V2.00h) |
AnnaBridge | 161:aa5281ff4a02 | 28 | ******************************************************************************/ |
AnnaBridge | 161:aa5281ff4a02 | 29 | #ifndef SCUX_IODEFINE_H |
AnnaBridge | 161:aa5281ff4a02 | 30 | #define SCUX_IODEFINE_H |
AnnaBridge | 161:aa5281ff4a02 | 31 | /* ->QAC 0639 : Over 127 members (C90) */ |
AnnaBridge | 161:aa5281ff4a02 | 32 | /* ->QAC 0857 : Over 1024 #define (C90) */ |
AnnaBridge | 161:aa5281ff4a02 | 33 | /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ |
AnnaBridge | 161:aa5281ff4a02 | 34 | /* ->SEC M1.10.1 : Not magic number */ |
AnnaBridge | 161:aa5281ff4a02 | 35 | |
AnnaBridge | 161:aa5281ff4a02 | 36 | #define SCUX (*(struct st_scux *)0xE8208000uL) /* SCUX */ |
AnnaBridge | 161:aa5281ff4a02 | 37 | |
AnnaBridge | 161:aa5281ff4a02 | 38 | |
AnnaBridge | 161:aa5281ff4a02 | 39 | /* Start of channel array defines of SCUX */ |
AnnaBridge | 161:aa5281ff4a02 | 40 | |
AnnaBridge | 161:aa5281ff4a02 | 41 | /* Channel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */ |
AnnaBridge | 161:aa5281ff4a02 | 42 | /*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */ |
AnnaBridge | 161:aa5281ff4a02 | 43 | #define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT (4) |
AnnaBridge | 161:aa5281ff4a02 | 44 | #define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \ |
AnnaBridge | 161:aa5281ff4a02 | 45 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
AnnaBridge | 161:aa5281ff4a02 | 46 | &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \ |
AnnaBridge | 161:aa5281ff4a02 | 47 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
AnnaBridge | 161:aa5281ff4a02 | 48 | #define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 49 | #define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 50 | #define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 51 | #define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 52 | |
AnnaBridge | 161:aa5281ff4a02 | 53 | |
AnnaBridge | 161:aa5281ff4a02 | 54 | /* Channel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */ |
AnnaBridge | 161:aa5281ff4a02 | 55 | /*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */ |
AnnaBridge | 161:aa5281ff4a02 | 56 | #define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT (2) |
AnnaBridge | 161:aa5281ff4a02 | 57 | #define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \ |
AnnaBridge | 161:aa5281ff4a02 | 58 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
AnnaBridge | 161:aa5281ff4a02 | 59 | &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \ |
AnnaBridge | 161:aa5281ff4a02 | 60 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
AnnaBridge | 161:aa5281ff4a02 | 61 | #define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 62 | #define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 63 | |
AnnaBridge | 161:aa5281ff4a02 | 64 | |
AnnaBridge | 161:aa5281ff4a02 | 65 | /* Channel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */ |
AnnaBridge | 161:aa5281ff4a02 | 66 | /*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */ |
AnnaBridge | 161:aa5281ff4a02 | 67 | #define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT (4) |
AnnaBridge | 161:aa5281ff4a02 | 68 | #define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \ |
AnnaBridge | 161:aa5281ff4a02 | 69 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
AnnaBridge | 161:aa5281ff4a02 | 70 | &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \ |
AnnaBridge | 161:aa5281ff4a02 | 71 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
AnnaBridge | 161:aa5281ff4a02 | 72 | #define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 73 | #define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 74 | #define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 75 | #define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 76 | |
AnnaBridge | 161:aa5281ff4a02 | 77 | |
AnnaBridge | 161:aa5281ff4a02 | 78 | /* Channel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */ |
AnnaBridge | 161:aa5281ff4a02 | 79 | /*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */ |
AnnaBridge | 161:aa5281ff4a02 | 80 | #define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT (4) |
AnnaBridge | 161:aa5281ff4a02 | 81 | #define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \ |
AnnaBridge | 161:aa5281ff4a02 | 82 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
AnnaBridge | 161:aa5281ff4a02 | 83 | &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \ |
AnnaBridge | 161:aa5281ff4a02 | 84 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
AnnaBridge | 161:aa5281ff4a02 | 85 | #define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 86 | #define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 87 | #define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 88 | #define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 89 | |
AnnaBridge | 161:aa5281ff4a02 | 90 | |
AnnaBridge | 161:aa5281ff4a02 | 91 | /* Channel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */ |
AnnaBridge | 161:aa5281ff4a02 | 92 | /*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */ |
AnnaBridge | 161:aa5281ff4a02 | 93 | #define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT (4) |
AnnaBridge | 161:aa5281ff4a02 | 94 | #define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \ |
AnnaBridge | 161:aa5281ff4a02 | 95 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
AnnaBridge | 161:aa5281ff4a02 | 96 | &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \ |
AnnaBridge | 161:aa5281ff4a02 | 97 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
AnnaBridge | 161:aa5281ff4a02 | 98 | #define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 99 | #define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 100 | #define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 101 | #define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 102 | |
AnnaBridge | 161:aa5281ff4a02 | 103 | |
AnnaBridge | 161:aa5281ff4a02 | 104 | /* Channel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */ |
AnnaBridge | 161:aa5281ff4a02 | 105 | /*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */ |
AnnaBridge | 161:aa5281ff4a02 | 106 | #define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT (4) |
AnnaBridge | 161:aa5281ff4a02 | 107 | #define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \ |
AnnaBridge | 161:aa5281ff4a02 | 108 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
AnnaBridge | 161:aa5281ff4a02 | 109 | &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \ |
AnnaBridge | 161:aa5281ff4a02 | 110 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
AnnaBridge | 161:aa5281ff4a02 | 111 | #define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 112 | #define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 113 | #define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 114 | #define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 115 | |
AnnaBridge | 161:aa5281ff4a02 | 116 | /* End of channel array defines of SCUX */ |
AnnaBridge | 161:aa5281ff4a02 | 117 | |
AnnaBridge | 161:aa5281ff4a02 | 118 | |
AnnaBridge | 161:aa5281ff4a02 | 119 | #define SCUXIPCIR_IPC0_0 (SCUX.IPCIR_IPC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 120 | #define SCUXIPSLR_IPC0_0 (SCUX.IPSLR_IPC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 121 | #define SCUXIPCIR_IPC0_1 (SCUX.IPCIR_IPC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 122 | #define SCUXIPSLR_IPC0_1 (SCUX.IPSLR_IPC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 123 | #define SCUXIPCIR_IPC0_2 (SCUX.IPCIR_IPC0_2) |
AnnaBridge | 161:aa5281ff4a02 | 124 | #define SCUXIPSLR_IPC0_2 (SCUX.IPSLR_IPC0_2) |
AnnaBridge | 161:aa5281ff4a02 | 125 | #define SCUXIPCIR_IPC0_3 (SCUX.IPCIR_IPC0_3) |
AnnaBridge | 161:aa5281ff4a02 | 126 | #define SCUXIPSLR_IPC0_3 (SCUX.IPSLR_IPC0_3) |
AnnaBridge | 161:aa5281ff4a02 | 127 | #define SCUXOPCIR_OPC0_0 (SCUX.OPCIR_OPC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 128 | #define SCUXOPSLR_OPC0_0 (SCUX.OPSLR_OPC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 129 | #define SCUXOPCIR_OPC0_1 (SCUX.OPCIR_OPC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 130 | #define SCUXOPSLR_OPC0_1 (SCUX.OPSLR_OPC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 131 | #define SCUXOPCIR_OPC0_2 (SCUX.OPCIR_OPC0_2) |
AnnaBridge | 161:aa5281ff4a02 | 132 | #define SCUXOPSLR_OPC0_2 (SCUX.OPSLR_OPC0_2) |
AnnaBridge | 161:aa5281ff4a02 | 133 | #define SCUXOPCIR_OPC0_3 (SCUX.OPCIR_OPC0_3) |
AnnaBridge | 161:aa5281ff4a02 | 134 | #define SCUXOPSLR_OPC0_3 (SCUX.OPSLR_OPC0_3) |
AnnaBridge | 161:aa5281ff4a02 | 135 | #define SCUXFFDIR_FFD0_0 (SCUX.FFDIR_FFD0_0) |
AnnaBridge | 161:aa5281ff4a02 | 136 | #define SCUXFDAIR_FFD0_0 (SCUX.FDAIR_FFD0_0) |
AnnaBridge | 161:aa5281ff4a02 | 137 | #define SCUXDRQSR_FFD0_0 (SCUX.DRQSR_FFD0_0) |
AnnaBridge | 161:aa5281ff4a02 | 138 | #define SCUXFFDPR_FFD0_0 (SCUX.FFDPR_FFD0_0) |
AnnaBridge | 161:aa5281ff4a02 | 139 | #define SCUXFFDBR_FFD0_0 (SCUX.FFDBR_FFD0_0) |
AnnaBridge | 161:aa5281ff4a02 | 140 | #define SCUXDEVMR_FFD0_0 (SCUX.DEVMR_FFD0_0) |
AnnaBridge | 161:aa5281ff4a02 | 141 | #define SCUXDEVCR_FFD0_0 (SCUX.DEVCR_FFD0_0) |
AnnaBridge | 161:aa5281ff4a02 | 142 | #define SCUXFFDIR_FFD0_1 (SCUX.FFDIR_FFD0_1) |
AnnaBridge | 161:aa5281ff4a02 | 143 | #define SCUXFDAIR_FFD0_1 (SCUX.FDAIR_FFD0_1) |
AnnaBridge | 161:aa5281ff4a02 | 144 | #define SCUXDRQSR_FFD0_1 (SCUX.DRQSR_FFD0_1) |
AnnaBridge | 161:aa5281ff4a02 | 145 | #define SCUXFFDPR_FFD0_1 (SCUX.FFDPR_FFD0_1) |
AnnaBridge | 161:aa5281ff4a02 | 146 | #define SCUXFFDBR_FFD0_1 (SCUX.FFDBR_FFD0_1) |
AnnaBridge | 161:aa5281ff4a02 | 147 | #define SCUXDEVMR_FFD0_1 (SCUX.DEVMR_FFD0_1) |
AnnaBridge | 161:aa5281ff4a02 | 148 | #define SCUXDEVCR_FFD0_1 (SCUX.DEVCR_FFD0_1) |
AnnaBridge | 161:aa5281ff4a02 | 149 | #define SCUXFFDIR_FFD0_2 (SCUX.FFDIR_FFD0_2) |
AnnaBridge | 161:aa5281ff4a02 | 150 | #define SCUXFDAIR_FFD0_2 (SCUX.FDAIR_FFD0_2) |
AnnaBridge | 161:aa5281ff4a02 | 151 | #define SCUXDRQSR_FFD0_2 (SCUX.DRQSR_FFD0_2) |
AnnaBridge | 161:aa5281ff4a02 | 152 | #define SCUXFFDPR_FFD0_2 (SCUX.FFDPR_FFD0_2) |
AnnaBridge | 161:aa5281ff4a02 | 153 | #define SCUXFFDBR_FFD0_2 (SCUX.FFDBR_FFD0_2) |
AnnaBridge | 161:aa5281ff4a02 | 154 | #define SCUXDEVMR_FFD0_2 (SCUX.DEVMR_FFD0_2) |
AnnaBridge | 161:aa5281ff4a02 | 155 | #define SCUXDEVCR_FFD0_2 (SCUX.DEVCR_FFD0_2) |
AnnaBridge | 161:aa5281ff4a02 | 156 | #define SCUXFFDIR_FFD0_3 (SCUX.FFDIR_FFD0_3) |
AnnaBridge | 161:aa5281ff4a02 | 157 | #define SCUXFDAIR_FFD0_3 (SCUX.FDAIR_FFD0_3) |
AnnaBridge | 161:aa5281ff4a02 | 158 | #define SCUXDRQSR_FFD0_3 (SCUX.DRQSR_FFD0_3) |
AnnaBridge | 161:aa5281ff4a02 | 159 | #define SCUXFFDPR_FFD0_3 (SCUX.FFDPR_FFD0_3) |
AnnaBridge | 161:aa5281ff4a02 | 160 | #define SCUXFFDBR_FFD0_3 (SCUX.FFDBR_FFD0_3) |
AnnaBridge | 161:aa5281ff4a02 | 161 | #define SCUXDEVMR_FFD0_3 (SCUX.DEVMR_FFD0_3) |
AnnaBridge | 161:aa5281ff4a02 | 162 | #define SCUXDEVCR_FFD0_3 (SCUX.DEVCR_FFD0_3) |
AnnaBridge | 161:aa5281ff4a02 | 163 | #define SCUXFFUIR_FFU0_0 (SCUX.FFUIR_FFU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 164 | #define SCUXFUAIR_FFU0_0 (SCUX.FUAIR_FFU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 165 | #define SCUXURQSR_FFU0_0 (SCUX.URQSR_FFU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 166 | #define SCUXFFUPR_FFU0_0 (SCUX.FFUPR_FFU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 167 | #define SCUXUEVMR_FFU0_0 (SCUX.UEVMR_FFU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 168 | #define SCUXUEVCR_FFU0_0 (SCUX.UEVCR_FFU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 169 | #define SCUXFFUIR_FFU0_1 (SCUX.FFUIR_FFU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 170 | #define SCUXFUAIR_FFU0_1 (SCUX.FUAIR_FFU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 171 | #define SCUXURQSR_FFU0_1 (SCUX.URQSR_FFU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 172 | #define SCUXFFUPR_FFU0_1 (SCUX.FFUPR_FFU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 173 | #define SCUXUEVMR_FFU0_1 (SCUX.UEVMR_FFU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 174 | #define SCUXUEVCR_FFU0_1 (SCUX.UEVCR_FFU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 175 | #define SCUXFFUIR_FFU0_2 (SCUX.FFUIR_FFU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 176 | #define SCUXFUAIR_FFU0_2 (SCUX.FUAIR_FFU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 177 | #define SCUXURQSR_FFU0_2 (SCUX.URQSR_FFU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 178 | #define SCUXFFUPR_FFU0_2 (SCUX.FFUPR_FFU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 179 | #define SCUXUEVMR_FFU0_2 (SCUX.UEVMR_FFU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 180 | #define SCUXUEVCR_FFU0_2 (SCUX.UEVCR_FFU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 181 | #define SCUXFFUIR_FFU0_3 (SCUX.FFUIR_FFU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 182 | #define SCUXFUAIR_FFU0_3 (SCUX.FUAIR_FFU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 183 | #define SCUXURQSR_FFU0_3 (SCUX.URQSR_FFU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 184 | #define SCUXFFUPR_FFU0_3 (SCUX.FFUPR_FFU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 185 | #define SCUXUEVMR_FFU0_3 (SCUX.UEVMR_FFU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 186 | #define SCUXUEVCR_FFU0_3 (SCUX.UEVCR_FFU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 187 | #define SCUXSRCIR0_2SRC0_0 (SCUX.SRCIR0_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 188 | #define SCUXSADIR0_2SRC0_0 (SCUX.SADIR0_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 189 | #define SCUXSRCBR0_2SRC0_0 (SCUX.SRCBR0_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 190 | #define SCUXIFSCR0_2SRC0_0 (SCUX.IFSCR0_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 191 | #define SCUXIFSVR0_2SRC0_0 (SCUX.IFSVR0_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 192 | #define SCUXSRCCR0_2SRC0_0 (SCUX.SRCCR0_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 193 | #define SCUXMNFSR0_2SRC0_0 (SCUX.MNFSR0_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 194 | #define SCUXBFSSR0_2SRC0_0 (SCUX.BFSSR0_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 195 | #define SCUXSC2SR0_2SRC0_0 (SCUX.SC2SR0_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 196 | #define SCUXWATSR0_2SRC0_0 (SCUX.WATSR0_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 197 | #define SCUXSEVMR0_2SRC0_0 (SCUX.SEVMR0_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 198 | #define SCUXSEVCR0_2SRC0_0 (SCUX.SEVCR0_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 199 | #define SCUXSRCIR1_2SRC0_0 (SCUX.SRCIR1_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 200 | #define SCUXSADIR1_2SRC0_0 (SCUX.SADIR1_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 201 | #define SCUXSRCBR1_2SRC0_0 (SCUX.SRCBR1_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 202 | #define SCUXIFSCR1_2SRC0_0 (SCUX.IFSCR1_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 203 | #define SCUXIFSVR1_2SRC0_0 (SCUX.IFSVR1_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 204 | #define SCUXSRCCR1_2SRC0_0 (SCUX.SRCCR1_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 205 | #define SCUXMNFSR1_2SRC0_0 (SCUX.MNFSR1_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 206 | #define SCUXBFSSR1_2SRC0_0 (SCUX.BFSSR1_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 207 | #define SCUXSC2SR1_2SRC0_0 (SCUX.SC2SR1_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 208 | #define SCUXWATSR1_2SRC0_0 (SCUX.WATSR1_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 209 | #define SCUXSEVMR1_2SRC0_0 (SCUX.SEVMR1_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 210 | #define SCUXSEVCR1_2SRC0_0 (SCUX.SEVCR1_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 211 | #define SCUXSRCIRR_2SRC0_0 (SCUX.SRCIRR_2SRC0_0) |
AnnaBridge | 161:aa5281ff4a02 | 212 | #define SCUXSRCIR0_2SRC0_1 (SCUX.SRCIR0_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 213 | #define SCUXSADIR0_2SRC0_1 (SCUX.SADIR0_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 214 | #define SCUXSRCBR0_2SRC0_1 (SCUX.SRCBR0_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 215 | #define SCUXIFSCR0_2SRC0_1 (SCUX.IFSCR0_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 216 | #define SCUXIFSVR0_2SRC0_1 (SCUX.IFSVR0_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 217 | #define SCUXSRCCR0_2SRC0_1 (SCUX.SRCCR0_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 218 | #define SCUXMNFSR0_2SRC0_1 (SCUX.MNFSR0_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 219 | #define SCUXBFSSR0_2SRC0_1 (SCUX.BFSSR0_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 220 | #define SCUXSC2SR0_2SRC0_1 (SCUX.SC2SR0_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 221 | #define SCUXWATSR0_2SRC0_1 (SCUX.WATSR0_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 222 | #define SCUXSEVMR0_2SRC0_1 (SCUX.SEVMR0_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 223 | #define SCUXSEVCR0_2SRC0_1 (SCUX.SEVCR0_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 224 | #define SCUXSRCIR1_2SRC0_1 (SCUX.SRCIR1_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 225 | #define SCUXSADIR1_2SRC0_1 (SCUX.SADIR1_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 226 | #define SCUXSRCBR1_2SRC0_1 (SCUX.SRCBR1_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 227 | #define SCUXIFSCR1_2SRC0_1 (SCUX.IFSCR1_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 228 | #define SCUXIFSVR1_2SRC0_1 (SCUX.IFSVR1_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 229 | #define SCUXSRCCR1_2SRC0_1 (SCUX.SRCCR1_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 230 | #define SCUXMNFSR1_2SRC0_1 (SCUX.MNFSR1_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 231 | #define SCUXBFSSR1_2SRC0_1 (SCUX.BFSSR1_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 232 | #define SCUXSC2SR1_2SRC0_1 (SCUX.SC2SR1_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 233 | #define SCUXWATSR1_2SRC0_1 (SCUX.WATSR1_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 234 | #define SCUXSEVMR1_2SRC0_1 (SCUX.SEVMR1_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 235 | #define SCUXSEVCR1_2SRC0_1 (SCUX.SEVCR1_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 236 | #define SCUXSRCIRR_2SRC0_1 (SCUX.SRCIRR_2SRC0_1) |
AnnaBridge | 161:aa5281ff4a02 | 237 | #define SCUXDVUIR_DVU0_0 (SCUX.DVUIR_DVU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 238 | #define SCUXVADIR_DVU0_0 (SCUX.VADIR_DVU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 239 | #define SCUXDVUBR_DVU0_0 (SCUX.DVUBR_DVU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 240 | #define SCUXDVUCR_DVU0_0 (SCUX.DVUCR_DVU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 241 | #define SCUXZCMCR_DVU0_0 (SCUX.ZCMCR_DVU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 242 | #define SCUXVRCTR_DVU0_0 (SCUX.VRCTR_DVU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 243 | #define SCUXVRPDR_DVU0_0 (SCUX.VRPDR_DVU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 244 | #define SCUXVRDBR_DVU0_0 (SCUX.VRDBR_DVU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 245 | #define SCUXVRWTR_DVU0_0 (SCUX.VRWTR_DVU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 246 | #define SCUXVOL0R_DVU0_0 (SCUX.VOL0R_DVU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 247 | #define SCUXVOL1R_DVU0_0 (SCUX.VOL1R_DVU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 248 | #define SCUXVOL2R_DVU0_0 (SCUX.VOL2R_DVU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 249 | #define SCUXVOL3R_DVU0_0 (SCUX.VOL3R_DVU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 250 | #define SCUXVOL4R_DVU0_0 (SCUX.VOL4R_DVU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 251 | #define SCUXVOL5R_DVU0_0 (SCUX.VOL5R_DVU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 252 | #define SCUXVOL6R_DVU0_0 (SCUX.VOL6R_DVU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 253 | #define SCUXVOL7R_DVU0_0 (SCUX.VOL7R_DVU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 254 | #define SCUXDVUER_DVU0_0 (SCUX.DVUER_DVU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 255 | #define SCUXDVUSR_DVU0_0 (SCUX.DVUSR_DVU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 256 | #define SCUXVEVMR_DVU0_0 (SCUX.VEVMR_DVU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 257 | #define SCUXVEVCR_DVU0_0 (SCUX.VEVCR_DVU0_0) |
AnnaBridge | 161:aa5281ff4a02 | 258 | #define SCUXDVUIR_DVU0_1 (SCUX.DVUIR_DVU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 259 | #define SCUXVADIR_DVU0_1 (SCUX.VADIR_DVU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 260 | #define SCUXDVUBR_DVU0_1 (SCUX.DVUBR_DVU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 261 | #define SCUXDVUCR_DVU0_1 (SCUX.DVUCR_DVU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 262 | #define SCUXZCMCR_DVU0_1 (SCUX.ZCMCR_DVU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 263 | #define SCUXVRCTR_DVU0_1 (SCUX.VRCTR_DVU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 264 | #define SCUXVRPDR_DVU0_1 (SCUX.VRPDR_DVU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 265 | #define SCUXVRDBR_DVU0_1 (SCUX.VRDBR_DVU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 266 | #define SCUXVRWTR_DVU0_1 (SCUX.VRWTR_DVU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 267 | #define SCUXVOL0R_DVU0_1 (SCUX.VOL0R_DVU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 268 | #define SCUXVOL1R_DVU0_1 (SCUX.VOL1R_DVU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 269 | #define SCUXVOL2R_DVU0_1 (SCUX.VOL2R_DVU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 270 | #define SCUXVOL3R_DVU0_1 (SCUX.VOL3R_DVU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 271 | #define SCUXVOL4R_DVU0_1 (SCUX.VOL4R_DVU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 272 | #define SCUXVOL5R_DVU0_1 (SCUX.VOL5R_DVU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 273 | #define SCUXVOL6R_DVU0_1 (SCUX.VOL6R_DVU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 274 | #define SCUXVOL7R_DVU0_1 (SCUX.VOL7R_DVU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 275 | #define SCUXDVUER_DVU0_1 (SCUX.DVUER_DVU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 276 | #define SCUXDVUSR_DVU0_1 (SCUX.DVUSR_DVU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 277 | #define SCUXVEVMR_DVU0_1 (SCUX.VEVMR_DVU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 278 | #define SCUXVEVCR_DVU0_1 (SCUX.VEVCR_DVU0_1) |
AnnaBridge | 161:aa5281ff4a02 | 279 | #define SCUXDVUIR_DVU0_2 (SCUX.DVUIR_DVU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 280 | #define SCUXVADIR_DVU0_2 (SCUX.VADIR_DVU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 281 | #define SCUXDVUBR_DVU0_2 (SCUX.DVUBR_DVU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 282 | #define SCUXDVUCR_DVU0_2 (SCUX.DVUCR_DVU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 283 | #define SCUXZCMCR_DVU0_2 (SCUX.ZCMCR_DVU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 284 | #define SCUXVRCTR_DVU0_2 (SCUX.VRCTR_DVU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 285 | #define SCUXVRPDR_DVU0_2 (SCUX.VRPDR_DVU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 286 | #define SCUXVRDBR_DVU0_2 (SCUX.VRDBR_DVU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 287 | #define SCUXVRWTR_DVU0_2 (SCUX.VRWTR_DVU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 288 | #define SCUXVOL0R_DVU0_2 (SCUX.VOL0R_DVU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 289 | #define SCUXVOL1R_DVU0_2 (SCUX.VOL1R_DVU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 290 | #define SCUXVOL2R_DVU0_2 (SCUX.VOL2R_DVU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 291 | #define SCUXVOL3R_DVU0_2 (SCUX.VOL3R_DVU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 292 | #define SCUXVOL4R_DVU0_2 (SCUX.VOL4R_DVU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 293 | #define SCUXVOL5R_DVU0_2 (SCUX.VOL5R_DVU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 294 | #define SCUXVOL6R_DVU0_2 (SCUX.VOL6R_DVU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 295 | #define SCUXVOL7R_DVU0_2 (SCUX.VOL7R_DVU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 296 | #define SCUXDVUER_DVU0_2 (SCUX.DVUER_DVU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 297 | #define SCUXDVUSR_DVU0_2 (SCUX.DVUSR_DVU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 298 | #define SCUXVEVMR_DVU0_2 (SCUX.VEVMR_DVU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 299 | #define SCUXVEVCR_DVU0_2 (SCUX.VEVCR_DVU0_2) |
AnnaBridge | 161:aa5281ff4a02 | 300 | #define SCUXDVUIR_DVU0_3 (SCUX.DVUIR_DVU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 301 | #define SCUXVADIR_DVU0_3 (SCUX.VADIR_DVU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 302 | #define SCUXDVUBR_DVU0_3 (SCUX.DVUBR_DVU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 303 | #define SCUXDVUCR_DVU0_3 (SCUX.DVUCR_DVU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 304 | #define SCUXZCMCR_DVU0_3 (SCUX.ZCMCR_DVU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 305 | #define SCUXVRCTR_DVU0_3 (SCUX.VRCTR_DVU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 306 | #define SCUXVRPDR_DVU0_3 (SCUX.VRPDR_DVU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 307 | #define SCUXVRDBR_DVU0_3 (SCUX.VRDBR_DVU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 308 | #define SCUXVRWTR_DVU0_3 (SCUX.VRWTR_DVU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 309 | #define SCUXVOL0R_DVU0_3 (SCUX.VOL0R_DVU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 310 | #define SCUXVOL1R_DVU0_3 (SCUX.VOL1R_DVU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 311 | #define SCUXVOL2R_DVU0_3 (SCUX.VOL2R_DVU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 312 | #define SCUXVOL3R_DVU0_3 (SCUX.VOL3R_DVU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 313 | #define SCUXVOL4R_DVU0_3 (SCUX.VOL4R_DVU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 314 | #define SCUXVOL5R_DVU0_3 (SCUX.VOL5R_DVU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 315 | #define SCUXVOL6R_DVU0_3 (SCUX.VOL6R_DVU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 316 | #define SCUXVOL7R_DVU0_3 (SCUX.VOL7R_DVU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 317 | #define SCUXDVUER_DVU0_3 (SCUX.DVUER_DVU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 318 | #define SCUXDVUSR_DVU0_3 (SCUX.DVUSR_DVU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 319 | #define SCUXVEVMR_DVU0_3 (SCUX.VEVMR_DVU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 320 | #define SCUXVEVCR_DVU0_3 (SCUX.VEVCR_DVU0_3) |
AnnaBridge | 161:aa5281ff4a02 | 321 | #define SCUXMIXIR_MIX0_0 (SCUX.MIXIR_MIX0_0) |
AnnaBridge | 161:aa5281ff4a02 | 322 | #define SCUXMADIR_MIX0_0 (SCUX.MADIR_MIX0_0) |
AnnaBridge | 161:aa5281ff4a02 | 323 | #define SCUXMIXBR_MIX0_0 (SCUX.MIXBR_MIX0_0) |
AnnaBridge | 161:aa5281ff4a02 | 324 | #define SCUXMIXMR_MIX0_0 (SCUX.MIXMR_MIX0_0) |
AnnaBridge | 161:aa5281ff4a02 | 325 | #define SCUXMVPDR_MIX0_0 (SCUX.MVPDR_MIX0_0) |
AnnaBridge | 161:aa5281ff4a02 | 326 | #define SCUXMDBAR_MIX0_0 (SCUX.MDBAR_MIX0_0) |
AnnaBridge | 161:aa5281ff4a02 | 327 | #define SCUXMDBBR_MIX0_0 (SCUX.MDBBR_MIX0_0) |
AnnaBridge | 161:aa5281ff4a02 | 328 | #define SCUXMDBCR_MIX0_0 (SCUX.MDBCR_MIX0_0) |
AnnaBridge | 161:aa5281ff4a02 | 329 | #define SCUXMDBDR_MIX0_0 (SCUX.MDBDR_MIX0_0) |
AnnaBridge | 161:aa5281ff4a02 | 330 | #define SCUXMDBER_MIX0_0 (SCUX.MDBER_MIX0_0) |
AnnaBridge | 161:aa5281ff4a02 | 331 | #define SCUXMIXSR_MIX0_0 (SCUX.MIXSR_MIX0_0) |
AnnaBridge | 161:aa5281ff4a02 | 332 | #define SCUXSWRSR_CIM (SCUX.SWRSR_CIM) |
AnnaBridge | 161:aa5281ff4a02 | 333 | #define SCUXDMACR_CIM (SCUX.DMACR_CIM) |
AnnaBridge | 161:aa5281ff4a02 | 334 | #define SCUXDMATD0_CIM (SCUX.DMATD0_CIM.UINT32) |
AnnaBridge | 161:aa5281ff4a02 | 335 | #define SCUXDMATD0_CIML (SCUX.DMATD0_CIM.UINT16[R_IO_L]) |
AnnaBridge | 161:aa5281ff4a02 | 336 | #define SCUXDMATD0_CIMH (SCUX.DMATD0_CIM.UINT16[R_IO_H]) |
AnnaBridge | 161:aa5281ff4a02 | 337 | #define SCUXDMATD1_CIM (SCUX.DMATD1_CIM.UINT32) |
AnnaBridge | 161:aa5281ff4a02 | 338 | #define SCUXDMATD1_CIML (SCUX.DMATD1_CIM.UINT16[R_IO_L]) |
AnnaBridge | 161:aa5281ff4a02 | 339 | #define SCUXDMATD1_CIMH (SCUX.DMATD1_CIM.UINT16[R_IO_H]) |
AnnaBridge | 161:aa5281ff4a02 | 340 | #define SCUXDMATD2_CIM (SCUX.DMATD2_CIM.UINT32) |
AnnaBridge | 161:aa5281ff4a02 | 341 | #define SCUXDMATD2_CIML (SCUX.DMATD2_CIM.UINT16[R_IO_L]) |
AnnaBridge | 161:aa5281ff4a02 | 342 | #define SCUXDMATD2_CIMH (SCUX.DMATD2_CIM.UINT16[R_IO_H]) |
AnnaBridge | 161:aa5281ff4a02 | 343 | #define SCUXDMATD3_CIM (SCUX.DMATD3_CIM.UINT32) |
AnnaBridge | 161:aa5281ff4a02 | 344 | #define SCUXDMATD3_CIML (SCUX.DMATD3_CIM.UINT16[R_IO_L]) |
AnnaBridge | 161:aa5281ff4a02 | 345 | #define SCUXDMATD3_CIMH (SCUX.DMATD3_CIM.UINT16[R_IO_H]) |
AnnaBridge | 161:aa5281ff4a02 | 346 | #define SCUXDMATU0_CIM (SCUX.DMATU0_CIM.UINT32) |
AnnaBridge | 161:aa5281ff4a02 | 347 | #define SCUXDMATU0_CIML (SCUX.DMATU0_CIM.UINT16[R_IO_L]) |
AnnaBridge | 161:aa5281ff4a02 | 348 | #define SCUXDMATU0_CIMH (SCUX.DMATU0_CIM.UINT16[R_IO_H]) |
AnnaBridge | 161:aa5281ff4a02 | 349 | #define SCUXDMATU1_CIM (SCUX.DMATU1_CIM.UINT32) |
AnnaBridge | 161:aa5281ff4a02 | 350 | #define SCUXDMATU1_CIML (SCUX.DMATU1_CIM.UINT16[R_IO_L]) |
AnnaBridge | 161:aa5281ff4a02 | 351 | #define SCUXDMATU1_CIMH (SCUX.DMATU1_CIM.UINT16[R_IO_H]) |
AnnaBridge | 161:aa5281ff4a02 | 352 | #define SCUXDMATU2_CIM (SCUX.DMATU2_CIM.UINT32) |
AnnaBridge | 161:aa5281ff4a02 | 353 | #define SCUXDMATU2_CIML (SCUX.DMATU2_CIM.UINT16[R_IO_L]) |
AnnaBridge | 161:aa5281ff4a02 | 354 | #define SCUXDMATU2_CIMH (SCUX.DMATU2_CIM.UINT16[R_IO_H]) |
AnnaBridge | 161:aa5281ff4a02 | 355 | #define SCUXDMATU3_CIM (SCUX.DMATU3_CIM.UINT32) |
AnnaBridge | 161:aa5281ff4a02 | 356 | #define SCUXDMATU3_CIML (SCUX.DMATU3_CIM.UINT16[R_IO_L]) |
AnnaBridge | 161:aa5281ff4a02 | 357 | #define SCUXDMATU3_CIMH (SCUX.DMATU3_CIM.UINT16[R_IO_H]) |
AnnaBridge | 161:aa5281ff4a02 | 358 | #define SCUXSSIRSEL_CIM (SCUX.SSIRSEL_CIM) |
AnnaBridge | 161:aa5281ff4a02 | 359 | #define SCUXFDTSEL0_CIM (SCUX.FDTSEL0_CIM) |
AnnaBridge | 161:aa5281ff4a02 | 360 | #define SCUXFDTSEL1_CIM (SCUX.FDTSEL1_CIM) |
AnnaBridge | 161:aa5281ff4a02 | 361 | #define SCUXFDTSEL2_CIM (SCUX.FDTSEL2_CIM) |
AnnaBridge | 161:aa5281ff4a02 | 362 | #define SCUXFDTSEL3_CIM (SCUX.FDTSEL3_CIM) |
AnnaBridge | 161:aa5281ff4a02 | 363 | #define SCUXFUTSEL0_CIM (SCUX.FUTSEL0_CIM) |
AnnaBridge | 161:aa5281ff4a02 | 364 | #define SCUXFUTSEL1_CIM (SCUX.FUTSEL1_CIM) |
AnnaBridge | 161:aa5281ff4a02 | 365 | #define SCUXFUTSEL2_CIM (SCUX.FUTSEL2_CIM) |
AnnaBridge | 161:aa5281ff4a02 | 366 | #define SCUXFUTSEL3_CIM (SCUX.FUTSEL3_CIM) |
AnnaBridge | 161:aa5281ff4a02 | 367 | #define SCUXSSIPMD_CIM (SCUX.SSIPMD_CIM) |
AnnaBridge | 161:aa5281ff4a02 | 368 | #define SCUXSSICTRL_CIM (SCUX.SSICTRL_CIM) |
AnnaBridge | 161:aa5281ff4a02 | 369 | #define SCUXSRCRSEL0_CIM (SCUX.SRCRSEL0_CIM) |
AnnaBridge | 161:aa5281ff4a02 | 370 | #define SCUXSRCRSEL1_CIM (SCUX.SRCRSEL1_CIM) |
AnnaBridge | 161:aa5281ff4a02 | 371 | #define SCUXSRCRSEL2_CIM (SCUX.SRCRSEL2_CIM) |
AnnaBridge | 161:aa5281ff4a02 | 372 | #define SCUXSRCRSEL3_CIM (SCUX.SRCRSEL3_CIM) |
AnnaBridge | 161:aa5281ff4a02 | 373 | #define SCUXMIXRSEL_CIM (SCUX.MIXRSEL_CIM) |
AnnaBridge | 161:aa5281ff4a02 | 374 | |
AnnaBridge | 161:aa5281ff4a02 | 375 | #define SCUX_DMATDnCIM_COUNT (4) |
AnnaBridge | 161:aa5281ff4a02 | 376 | #define SCUX_DMATUnCIM_COUNT (4) |
AnnaBridge | 161:aa5281ff4a02 | 377 | #define SCUX_FDTSELnCIM_COUNT (4) |
AnnaBridge | 161:aa5281ff4a02 | 378 | #define SCUX_FUTSELnCIM_COUNT (4) |
AnnaBridge | 161:aa5281ff4a02 | 379 | #define SCUX_SRCRSELnCIM_COUNT (4) |
AnnaBridge | 161:aa5281ff4a02 | 380 | |
AnnaBridge | 161:aa5281ff4a02 | 381 | |
AnnaBridge | 161:aa5281ff4a02 | 382 | typedef struct st_scux |
AnnaBridge | 161:aa5281ff4a02 | 383 | { |
AnnaBridge | 161:aa5281ff4a02 | 384 | /* SCUX */ |
AnnaBridge | 161:aa5281ff4a02 | 385 | |
AnnaBridge | 161:aa5281ff4a02 | 386 | /* start of struct st_scux_from_ipcir_ipc0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 387 | volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 388 | volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 389 | volatile uint8_t dummy259[248]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 390 | |
AnnaBridge | 161:aa5281ff4a02 | 391 | /* end of struct st_scux_from_ipcir_ipc0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 392 | |
AnnaBridge | 161:aa5281ff4a02 | 393 | /* start of struct st_scux_from_ipcir_ipc0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 394 | volatile uint32_t IPCIR_IPC0_1; /* IPCIR_IPC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 395 | volatile uint32_t IPSLR_IPC0_1; /* IPSLR_IPC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 396 | volatile uint8_t dummy260[248]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 397 | |
AnnaBridge | 161:aa5281ff4a02 | 398 | /* end of struct st_scux_from_ipcir_ipc0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 399 | |
AnnaBridge | 161:aa5281ff4a02 | 400 | /* start of struct st_scux_from_ipcir_ipc0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 401 | volatile uint32_t IPCIR_IPC0_2; /* IPCIR_IPC0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 402 | volatile uint32_t IPSLR_IPC0_2; /* IPSLR_IPC0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 403 | volatile uint8_t dummy261[248]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 404 | |
AnnaBridge | 161:aa5281ff4a02 | 405 | /* end of struct st_scux_from_ipcir_ipc0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 406 | |
AnnaBridge | 161:aa5281ff4a02 | 407 | /* start of struct st_scux_from_ipcir_ipc0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 408 | volatile uint32_t IPCIR_IPC0_3; /* IPCIR_IPC0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 409 | volatile uint32_t IPSLR_IPC0_3; /* IPSLR_IPC0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 410 | volatile uint8_t dummy262[248]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 411 | |
AnnaBridge | 161:aa5281ff4a02 | 412 | /* end of struct st_scux_from_ipcir_ipc0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 413 | |
AnnaBridge | 161:aa5281ff4a02 | 414 | /* start of struct st_scux_from_opcir_opc0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 415 | volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 416 | volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 417 | volatile uint8_t dummy263[248]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 418 | |
AnnaBridge | 161:aa5281ff4a02 | 419 | /* end of struct st_scux_from_opcir_opc0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 420 | |
AnnaBridge | 161:aa5281ff4a02 | 421 | /* start of struct st_scux_from_opcir_opc0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 422 | volatile uint32_t OPCIR_OPC0_1; /* OPCIR_OPC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 423 | volatile uint32_t OPSLR_OPC0_1; /* OPSLR_OPC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 424 | volatile uint8_t dummy264[248]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 425 | |
AnnaBridge | 161:aa5281ff4a02 | 426 | /* end of struct st_scux_from_opcir_opc0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 427 | |
AnnaBridge | 161:aa5281ff4a02 | 428 | /* start of struct st_scux_from_opcir_opc0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 429 | volatile uint32_t OPCIR_OPC0_2; /* OPCIR_OPC0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 430 | volatile uint32_t OPSLR_OPC0_2; /* OPSLR_OPC0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 431 | volatile uint8_t dummy265[248]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 432 | |
AnnaBridge | 161:aa5281ff4a02 | 433 | /* end of struct st_scux_from_opcir_opc0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 434 | |
AnnaBridge | 161:aa5281ff4a02 | 435 | /* start of struct st_scux_from_opcir_opc0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 436 | volatile uint32_t OPCIR_OPC0_3; /* OPCIR_OPC0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 437 | volatile uint32_t OPSLR_OPC0_3; /* OPSLR_OPC0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 438 | volatile uint8_t dummy266[248]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 439 | |
AnnaBridge | 161:aa5281ff4a02 | 440 | /* end of struct st_scux_from_opcir_opc0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 441 | |
AnnaBridge | 161:aa5281ff4a02 | 442 | /* start of struct st_scux_from_ffdir_ffd0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 443 | volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 444 | volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 445 | volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 446 | volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 447 | volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 448 | volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 449 | volatile uint8_t dummy267[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 450 | volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 451 | |
AnnaBridge | 161:aa5281ff4a02 | 452 | /* end of struct st_scux_from_ffdir_ffd0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 453 | volatile uint8_t dummy268[224]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 454 | |
AnnaBridge | 161:aa5281ff4a02 | 455 | /* start of struct st_scux_from_ffdir_ffd0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 456 | volatile uint32_t FFDIR_FFD0_1; /* FFDIR_FFD0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 457 | volatile uint32_t FDAIR_FFD0_1; /* FDAIR_FFD0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 458 | volatile uint32_t DRQSR_FFD0_1; /* DRQSR_FFD0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 459 | volatile uint32_t FFDPR_FFD0_1; /* FFDPR_FFD0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 460 | volatile uint32_t FFDBR_FFD0_1; /* FFDBR_FFD0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 461 | volatile uint32_t DEVMR_FFD0_1; /* DEVMR_FFD0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 462 | volatile uint8_t dummy269[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 463 | volatile uint32_t DEVCR_FFD0_1; /* DEVCR_FFD0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 464 | |
AnnaBridge | 161:aa5281ff4a02 | 465 | /* end of struct st_scux_from_ffdir_ffd0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 466 | volatile uint8_t dummy270[224]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 467 | |
AnnaBridge | 161:aa5281ff4a02 | 468 | /* start of struct st_scux_from_ffdir_ffd0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 469 | volatile uint32_t FFDIR_FFD0_2; /* FFDIR_FFD0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 470 | volatile uint32_t FDAIR_FFD0_2; /* FDAIR_FFD0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 471 | volatile uint32_t DRQSR_FFD0_2; /* DRQSR_FFD0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 472 | volatile uint32_t FFDPR_FFD0_2; /* FFDPR_FFD0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 473 | volatile uint32_t FFDBR_FFD0_2; /* FFDBR_FFD0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 474 | volatile uint32_t DEVMR_FFD0_2; /* DEVMR_FFD0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 475 | volatile uint8_t dummy271[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 476 | volatile uint32_t DEVCR_FFD0_2; /* DEVCR_FFD0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 477 | |
AnnaBridge | 161:aa5281ff4a02 | 478 | /* end of struct st_scux_from_ffdir_ffd0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 479 | volatile uint8_t dummy272[224]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 480 | |
AnnaBridge | 161:aa5281ff4a02 | 481 | /* start of struct st_scux_from_ffdir_ffd0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 482 | volatile uint32_t FFDIR_FFD0_3; /* FFDIR_FFD0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 483 | volatile uint32_t FDAIR_FFD0_3; /* FDAIR_FFD0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 484 | volatile uint32_t DRQSR_FFD0_3; /* DRQSR_FFD0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 485 | volatile uint32_t FFDPR_FFD0_3; /* FFDPR_FFD0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 486 | volatile uint32_t FFDBR_FFD0_3; /* FFDBR_FFD0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 487 | volatile uint32_t DEVMR_FFD0_3; /* DEVMR_FFD0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 488 | volatile uint8_t dummy273[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 489 | volatile uint32_t DEVCR_FFD0_3; /* DEVCR_FFD0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 490 | |
AnnaBridge | 161:aa5281ff4a02 | 491 | /* end of struct st_scux_from_ffdir_ffd0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 492 | volatile uint8_t dummy274[224]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 493 | |
AnnaBridge | 161:aa5281ff4a02 | 494 | /* start of struct st_scux_from_ffuir_ffu0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 495 | volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 496 | volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 497 | volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 498 | volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 499 | volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 500 | volatile uint8_t dummy275[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 501 | volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 502 | |
AnnaBridge | 161:aa5281ff4a02 | 503 | /* end of struct st_scux_from_ffuir_ffu0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 504 | volatile uint8_t dummy276[228]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 505 | |
AnnaBridge | 161:aa5281ff4a02 | 506 | /* start of struct st_scux_from_ffuir_ffu0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 507 | volatile uint32_t FFUIR_FFU0_1; /* FFUIR_FFU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 508 | volatile uint32_t FUAIR_FFU0_1; /* FUAIR_FFU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 509 | volatile uint32_t URQSR_FFU0_1; /* URQSR_FFU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 510 | volatile uint32_t FFUPR_FFU0_1; /* FFUPR_FFU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 511 | volatile uint32_t UEVMR_FFU0_1; /* UEVMR_FFU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 512 | volatile uint8_t dummy277[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 513 | volatile uint32_t UEVCR_FFU0_1; /* UEVCR_FFU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 514 | |
AnnaBridge | 161:aa5281ff4a02 | 515 | /* end of struct st_scux_from_ffuir_ffu0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 516 | volatile uint8_t dummy278[228]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 517 | |
AnnaBridge | 161:aa5281ff4a02 | 518 | /* start of struct st_scux_from_ffuir_ffu0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 519 | volatile uint32_t FFUIR_FFU0_2; /* FFUIR_FFU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 520 | volatile uint32_t FUAIR_FFU0_2; /* FUAIR_FFU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 521 | volatile uint32_t URQSR_FFU0_2; /* URQSR_FFU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 522 | volatile uint32_t FFUPR_FFU0_2; /* FFUPR_FFU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 523 | volatile uint32_t UEVMR_FFU0_2; /* UEVMR_FFU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 524 | volatile uint8_t dummy279[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 525 | volatile uint32_t UEVCR_FFU0_2; /* UEVCR_FFU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 526 | |
AnnaBridge | 161:aa5281ff4a02 | 527 | /* end of struct st_scux_from_ffuir_ffu0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 528 | volatile uint8_t dummy280[228]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 529 | |
AnnaBridge | 161:aa5281ff4a02 | 530 | /* start of struct st_scux_from_ffuir_ffu0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 531 | volatile uint32_t FFUIR_FFU0_3; /* FFUIR_FFU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 532 | volatile uint32_t FUAIR_FFU0_3; /* FUAIR_FFU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 533 | volatile uint32_t URQSR_FFU0_3; /* URQSR_FFU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 534 | volatile uint32_t FFUPR_FFU0_3; /* FFUPR_FFU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 535 | volatile uint32_t UEVMR_FFU0_3; /* UEVMR_FFU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 536 | volatile uint8_t dummy281[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 537 | volatile uint32_t UEVCR_FFU0_3; /* UEVCR_FFU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 538 | |
AnnaBridge | 161:aa5281ff4a02 | 539 | /* end of struct st_scux_from_ffuir_ffu0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 540 | volatile uint8_t dummy282[228]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 541 | |
AnnaBridge | 161:aa5281ff4a02 | 542 | /* start of struct st_scux_from_srcir0_2src0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 543 | volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 544 | volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 545 | volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 546 | volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 547 | volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 548 | volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 549 | volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 550 | volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 551 | volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 552 | volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 553 | volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 554 | volatile uint8_t dummy283[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 555 | volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 556 | volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 557 | volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 558 | volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 559 | volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 560 | volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 561 | volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 562 | volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 563 | volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 564 | volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 565 | volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 566 | volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 567 | volatile uint8_t dummy284[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 568 | volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 569 | volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 570 | |
AnnaBridge | 161:aa5281ff4a02 | 571 | /* end of struct st_scux_from_srcir0_2src0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 572 | volatile uint8_t dummy285[148]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 573 | |
AnnaBridge | 161:aa5281ff4a02 | 574 | /* start of struct st_scux_from_srcir0_2src0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 575 | volatile uint32_t SRCIR0_2SRC0_1; /* SRCIR0_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 576 | volatile uint32_t SADIR0_2SRC0_1; /* SADIR0_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 577 | volatile uint32_t SRCBR0_2SRC0_1; /* SRCBR0_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 578 | volatile uint32_t IFSCR0_2SRC0_1; /* IFSCR0_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 579 | volatile uint32_t IFSVR0_2SRC0_1; /* IFSVR0_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 580 | volatile uint32_t SRCCR0_2SRC0_1; /* SRCCR0_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 581 | volatile uint32_t MNFSR0_2SRC0_1; /* MNFSR0_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 582 | volatile uint32_t BFSSR0_2SRC0_1; /* BFSSR0_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 583 | volatile uint32_t SC2SR0_2SRC0_1; /* SC2SR0_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 584 | volatile uint32_t WATSR0_2SRC0_1; /* WATSR0_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 585 | volatile uint32_t SEVMR0_2SRC0_1; /* SEVMR0_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 586 | volatile uint8_t dummy286[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 587 | volatile uint32_t SEVCR0_2SRC0_1; /* SEVCR0_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 588 | volatile uint32_t SRCIR1_2SRC0_1; /* SRCIR1_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 589 | volatile uint32_t SADIR1_2SRC0_1; /* SADIR1_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 590 | volatile uint32_t SRCBR1_2SRC0_1; /* SRCBR1_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 591 | volatile uint32_t IFSCR1_2SRC0_1; /* IFSCR1_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 592 | volatile uint32_t IFSVR1_2SRC0_1; /* IFSVR1_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 593 | volatile uint32_t SRCCR1_2SRC0_1; /* SRCCR1_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 594 | volatile uint32_t MNFSR1_2SRC0_1; /* MNFSR1_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 595 | volatile uint32_t BFSSR1_2SRC0_1; /* BFSSR1_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 596 | volatile uint32_t SC2SR1_2SRC0_1; /* SC2SR1_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 597 | volatile uint32_t WATSR1_2SRC0_1; /* WATSR1_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 598 | volatile uint32_t SEVMR1_2SRC0_1; /* SEVMR1_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 599 | volatile uint8_t dummy287[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 600 | volatile uint32_t SEVCR1_2SRC0_1; /* SEVCR1_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 601 | volatile uint32_t SRCIRR_2SRC0_1; /* SRCIRR_2SRC0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 602 | |
AnnaBridge | 161:aa5281ff4a02 | 603 | /* end of struct st_scux_from_srcir0_2src0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 604 | volatile uint8_t dummy288[148]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 605 | |
AnnaBridge | 161:aa5281ff4a02 | 606 | /* start of struct st_scux_from_dvuir_dvu0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 607 | volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 608 | volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 609 | volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 610 | volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 611 | volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 612 | volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 613 | volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 614 | volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 615 | volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 616 | volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 617 | volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 618 | volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 619 | volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 620 | volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 621 | volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 622 | volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 623 | volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 624 | volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 625 | volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 626 | volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 627 | volatile uint8_t dummy289[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 628 | volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 629 | |
AnnaBridge | 161:aa5281ff4a02 | 630 | /* end of struct st_scux_from_dvuir_dvu0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 631 | volatile uint8_t dummy290[168]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 632 | |
AnnaBridge | 161:aa5281ff4a02 | 633 | /* start of struct st_scux_from_dvuir_dvu0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 634 | volatile uint32_t DVUIR_DVU0_1; /* DVUIR_DVU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 635 | volatile uint32_t VADIR_DVU0_1; /* VADIR_DVU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 636 | volatile uint32_t DVUBR_DVU0_1; /* DVUBR_DVU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 637 | volatile uint32_t DVUCR_DVU0_1; /* DVUCR_DVU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 638 | volatile uint32_t ZCMCR_DVU0_1; /* ZCMCR_DVU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 639 | volatile uint32_t VRCTR_DVU0_1; /* VRCTR_DVU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 640 | volatile uint32_t VRPDR_DVU0_1; /* VRPDR_DVU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 641 | volatile uint32_t VRDBR_DVU0_1; /* VRDBR_DVU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 642 | volatile uint32_t VRWTR_DVU0_1; /* VRWTR_DVU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 643 | volatile uint32_t VOL0R_DVU0_1; /* VOL0R_DVU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 644 | volatile uint32_t VOL1R_DVU0_1; /* VOL1R_DVU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 645 | volatile uint32_t VOL2R_DVU0_1; /* VOL2R_DVU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 646 | volatile uint32_t VOL3R_DVU0_1; /* VOL3R_DVU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 647 | volatile uint32_t VOL4R_DVU0_1; /* VOL4R_DVU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 648 | volatile uint32_t VOL5R_DVU0_1; /* VOL5R_DVU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 649 | volatile uint32_t VOL6R_DVU0_1; /* VOL6R_DVU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 650 | volatile uint32_t VOL7R_DVU0_1; /* VOL7R_DVU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 651 | volatile uint32_t DVUER_DVU0_1; /* DVUER_DVU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 652 | volatile uint32_t DVUSR_DVU0_1; /* DVUSR_DVU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 653 | volatile uint32_t VEVMR_DVU0_1; /* VEVMR_DVU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 654 | volatile uint8_t dummy291[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 655 | volatile uint32_t VEVCR_DVU0_1; /* VEVCR_DVU0_1 */ |
AnnaBridge | 161:aa5281ff4a02 | 656 | |
AnnaBridge | 161:aa5281ff4a02 | 657 | /* end of struct st_scux_from_dvuir_dvu0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 658 | volatile uint8_t dummy292[168]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 659 | |
AnnaBridge | 161:aa5281ff4a02 | 660 | /* start of struct st_scux_from_dvuir_dvu0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 661 | volatile uint32_t DVUIR_DVU0_2; /* DVUIR_DVU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 662 | volatile uint32_t VADIR_DVU0_2; /* VADIR_DVU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 663 | volatile uint32_t DVUBR_DVU0_2; /* DVUBR_DVU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 664 | volatile uint32_t DVUCR_DVU0_2; /* DVUCR_DVU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 665 | volatile uint32_t ZCMCR_DVU0_2; /* ZCMCR_DVU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 666 | volatile uint32_t VRCTR_DVU0_2; /* VRCTR_DVU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 667 | volatile uint32_t VRPDR_DVU0_2; /* VRPDR_DVU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 668 | volatile uint32_t VRDBR_DVU0_2; /* VRDBR_DVU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 669 | volatile uint32_t VRWTR_DVU0_2; /* VRWTR_DVU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 670 | volatile uint32_t VOL0R_DVU0_2; /* VOL0R_DVU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 671 | volatile uint32_t VOL1R_DVU0_2; /* VOL1R_DVU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 672 | volatile uint32_t VOL2R_DVU0_2; /* VOL2R_DVU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 673 | volatile uint32_t VOL3R_DVU0_2; /* VOL3R_DVU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 674 | volatile uint32_t VOL4R_DVU0_2; /* VOL4R_DVU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 675 | volatile uint32_t VOL5R_DVU0_2; /* VOL5R_DVU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 676 | volatile uint32_t VOL6R_DVU0_2; /* VOL6R_DVU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 677 | volatile uint32_t VOL7R_DVU0_2; /* VOL7R_DVU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 678 | volatile uint32_t DVUER_DVU0_2; /* DVUER_DVU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 679 | volatile uint32_t DVUSR_DVU0_2; /* DVUSR_DVU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 680 | volatile uint32_t VEVMR_DVU0_2; /* VEVMR_DVU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 681 | volatile uint8_t dummy293[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 682 | volatile uint32_t VEVCR_DVU0_2; /* VEVCR_DVU0_2 */ |
AnnaBridge | 161:aa5281ff4a02 | 683 | |
AnnaBridge | 161:aa5281ff4a02 | 684 | /* end of struct st_scux_from_dvuir_dvu0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 685 | volatile uint8_t dummy294[168]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 686 | |
AnnaBridge | 161:aa5281ff4a02 | 687 | /* start of struct st_scux_from_dvuir_dvu0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 688 | volatile uint32_t DVUIR_DVU0_3; /* DVUIR_DVU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 689 | volatile uint32_t VADIR_DVU0_3; /* VADIR_DVU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 690 | volatile uint32_t DVUBR_DVU0_3; /* DVUBR_DVU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 691 | volatile uint32_t DVUCR_DVU0_3; /* DVUCR_DVU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 692 | volatile uint32_t ZCMCR_DVU0_3; /* ZCMCR_DVU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 693 | volatile uint32_t VRCTR_DVU0_3; /* VRCTR_DVU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 694 | volatile uint32_t VRPDR_DVU0_3; /* VRPDR_DVU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 695 | volatile uint32_t VRDBR_DVU0_3; /* VRDBR_DVU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 696 | volatile uint32_t VRWTR_DVU0_3; /* VRWTR_DVU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 697 | volatile uint32_t VOL0R_DVU0_3; /* VOL0R_DVU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 698 | volatile uint32_t VOL1R_DVU0_3; /* VOL1R_DVU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 699 | volatile uint32_t VOL2R_DVU0_3; /* VOL2R_DVU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 700 | volatile uint32_t VOL3R_DVU0_3; /* VOL3R_DVU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 701 | volatile uint32_t VOL4R_DVU0_3; /* VOL4R_DVU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 702 | volatile uint32_t VOL5R_DVU0_3; /* VOL5R_DVU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 703 | volatile uint32_t VOL6R_DVU0_3; /* VOL6R_DVU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 704 | volatile uint32_t VOL7R_DVU0_3; /* VOL7R_DVU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 705 | volatile uint32_t DVUER_DVU0_3; /* DVUER_DVU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 706 | volatile uint32_t DVUSR_DVU0_3; /* DVUSR_DVU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 707 | volatile uint32_t VEVMR_DVU0_3; /* VEVMR_DVU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 708 | volatile uint8_t dummy295[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 709 | volatile uint32_t VEVCR_DVU0_3; /* VEVCR_DVU0_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 710 | |
AnnaBridge | 161:aa5281ff4a02 | 711 | /* end of struct st_scux_from_dvuir_dvu0_n */ |
AnnaBridge | 161:aa5281ff4a02 | 712 | volatile uint8_t dummy296[168]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 713 | volatile uint32_t MIXIR_MIX0_0; /* MIXIR_MIX0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 714 | volatile uint32_t MADIR_MIX0_0; /* MADIR_MIX0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 715 | volatile uint32_t MIXBR_MIX0_0; /* MIXBR_MIX0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 716 | volatile uint32_t MIXMR_MIX0_0; /* MIXMR_MIX0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 717 | volatile uint32_t MVPDR_MIX0_0; /* MVPDR_MIX0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 718 | volatile uint32_t MDBAR_MIX0_0; /* MDBAR_MIX0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 719 | volatile uint32_t MDBBR_MIX0_0; /* MDBBR_MIX0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 720 | volatile uint32_t MDBCR_MIX0_0; /* MDBCR_MIX0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 721 | volatile uint32_t MDBDR_MIX0_0; /* MDBDR_MIX0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 722 | volatile uint32_t MDBER_MIX0_0; /* MDBER_MIX0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 723 | volatile uint32_t MIXSR_MIX0_0; /* MIXSR_MIX0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 724 | volatile uint8_t dummy297[212]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 725 | volatile uint32_t SWRSR_CIM; /* SWRSR_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 726 | volatile uint32_t DMACR_CIM; /* DMACR_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 727 | |
AnnaBridge | 161:aa5281ff4a02 | 728 | /* #define SCUX_DMATDnCIM_COUNT (4) */ |
AnnaBridge | 161:aa5281ff4a02 | 729 | union iodefine_reg32_16_t DMATD0_CIM; /* DMATD0_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 730 | union iodefine_reg32_16_t DMATD1_CIM; /* DMATD1_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 731 | union iodefine_reg32_16_t DMATD2_CIM; /* DMATD2_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 732 | union iodefine_reg32_16_t DMATD3_CIM; /* DMATD3_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 733 | |
AnnaBridge | 161:aa5281ff4a02 | 734 | /* #define SCUX_DMATUnCIM_COUNT (4) */ |
AnnaBridge | 161:aa5281ff4a02 | 735 | union iodefine_reg32_16_t DMATU0_CIM; /* DMATU0_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 736 | union iodefine_reg32_16_t DMATU1_CIM; /* DMATU1_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 737 | union iodefine_reg32_16_t DMATU2_CIM; /* DMATU2_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 738 | union iodefine_reg32_16_t DMATU3_CIM; /* DMATU3_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 739 | |
AnnaBridge | 161:aa5281ff4a02 | 740 | volatile uint8_t dummy298[16]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 741 | volatile uint32_t SSIRSEL_CIM; /* SSIRSEL_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 742 | |
AnnaBridge | 161:aa5281ff4a02 | 743 | /* #define SCUX_FDTSELnCIM_COUNT (4) */ |
AnnaBridge | 161:aa5281ff4a02 | 744 | volatile uint32_t FDTSEL0_CIM; /* FDTSEL0_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 745 | volatile uint32_t FDTSEL1_CIM; /* FDTSEL1_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 746 | volatile uint32_t FDTSEL2_CIM; /* FDTSEL2_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 747 | volatile uint32_t FDTSEL3_CIM; /* FDTSEL3_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 748 | |
AnnaBridge | 161:aa5281ff4a02 | 749 | /* #define SCUX_FUTSELnCIM_COUNT (4) */ |
AnnaBridge | 161:aa5281ff4a02 | 750 | volatile uint32_t FUTSEL0_CIM; /* FUTSEL0_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 751 | volatile uint32_t FUTSEL1_CIM; /* FUTSEL1_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 752 | volatile uint32_t FUTSEL2_CIM; /* FUTSEL2_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 753 | volatile uint32_t FUTSEL3_CIM; /* FUTSEL3_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 754 | volatile uint32_t SSIPMD_CIM; /* SSIPMD_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 755 | volatile uint32_t SSICTRL_CIM; /* SSICTRL_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 756 | |
AnnaBridge | 161:aa5281ff4a02 | 757 | /* #define SCUX_SRCRSELnCIM_COUNT (4) */ |
AnnaBridge | 161:aa5281ff4a02 | 758 | volatile uint32_t SRCRSEL0_CIM; /* SRCRSEL0_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 759 | volatile uint32_t SRCRSEL1_CIM; /* SRCRSEL1_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 760 | volatile uint32_t SRCRSEL2_CIM; /* SRCRSEL2_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 761 | volatile uint32_t SRCRSEL3_CIM; /* SRCRSEL3_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 762 | volatile uint32_t MIXRSEL_CIM; /* MIXRSEL_CIM */ |
AnnaBridge | 161:aa5281ff4a02 | 763 | } r_io_scux_t; |
AnnaBridge | 161:aa5281ff4a02 | 764 | |
AnnaBridge | 161:aa5281ff4a02 | 765 | |
AnnaBridge | 161:aa5281ff4a02 | 766 | typedef struct st_scux_from_ipcir_ipc0_n |
AnnaBridge | 161:aa5281ff4a02 | 767 | { |
AnnaBridge | 161:aa5281ff4a02 | 768 | |
AnnaBridge | 161:aa5281ff4a02 | 769 | volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 770 | volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 771 | volatile uint8_t dummy1[248]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 772 | } r_io_scux_from_ipcir_ipc0_n_t; |
AnnaBridge | 161:aa5281ff4a02 | 773 | |
AnnaBridge | 161:aa5281ff4a02 | 774 | |
AnnaBridge | 161:aa5281ff4a02 | 775 | typedef struct st_scux_from_opcir_opc0_n |
AnnaBridge | 161:aa5281ff4a02 | 776 | { |
AnnaBridge | 161:aa5281ff4a02 | 777 | |
AnnaBridge | 161:aa5281ff4a02 | 778 | volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 779 | volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 780 | volatile uint8_t dummy1[248]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 781 | } r_io_scux_from_opcir_opc0_n_t; |
AnnaBridge | 161:aa5281ff4a02 | 782 | |
AnnaBridge | 161:aa5281ff4a02 | 783 | |
AnnaBridge | 161:aa5281ff4a02 | 784 | typedef struct st_scux_from_ffdir_ffd0_n |
AnnaBridge | 161:aa5281ff4a02 | 785 | { |
AnnaBridge | 161:aa5281ff4a02 | 786 | |
AnnaBridge | 161:aa5281ff4a02 | 787 | volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 788 | volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 789 | volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 790 | volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 791 | volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 792 | volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 793 | volatile uint8_t dummy1[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 794 | volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 795 | } r_io_scux_from_ffdir_ffd0_n_t; |
AnnaBridge | 161:aa5281ff4a02 | 796 | |
AnnaBridge | 161:aa5281ff4a02 | 797 | |
AnnaBridge | 161:aa5281ff4a02 | 798 | typedef struct st_scux_from_ffuir_ffu0_n |
AnnaBridge | 161:aa5281ff4a02 | 799 | { |
AnnaBridge | 161:aa5281ff4a02 | 800 | |
AnnaBridge | 161:aa5281ff4a02 | 801 | volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 802 | volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 803 | volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 804 | volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 805 | volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 806 | volatile uint8_t dummy1[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 807 | volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 808 | } r_io_scux_from_ffuir_ffu0_n_t; |
AnnaBridge | 161:aa5281ff4a02 | 809 | |
AnnaBridge | 161:aa5281ff4a02 | 810 | |
AnnaBridge | 161:aa5281ff4a02 | 811 | typedef struct st_scux_from_srcir0_2src0_n |
AnnaBridge | 161:aa5281ff4a02 | 812 | { |
AnnaBridge | 161:aa5281ff4a02 | 813 | |
AnnaBridge | 161:aa5281ff4a02 | 814 | volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 815 | volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 816 | volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 817 | volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 818 | volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 819 | volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 820 | volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 821 | volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 822 | volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 823 | volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 824 | volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 825 | volatile uint8_t dummy1[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 826 | volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 827 | volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 828 | volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 829 | volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 830 | volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 831 | volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 832 | volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 833 | volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 834 | volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 835 | volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 836 | volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 837 | volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 838 | volatile uint8_t dummy2[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 839 | volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 840 | volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 841 | } r_io_scux_from_srcir0_2src0_n_t; |
AnnaBridge | 161:aa5281ff4a02 | 842 | |
AnnaBridge | 161:aa5281ff4a02 | 843 | |
AnnaBridge | 161:aa5281ff4a02 | 844 | typedef struct st_scux_from_dvuir_dvu0_n |
AnnaBridge | 161:aa5281ff4a02 | 845 | { |
AnnaBridge | 161:aa5281ff4a02 | 846 | |
AnnaBridge | 161:aa5281ff4a02 | 847 | volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 848 | volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 849 | volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 850 | volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 851 | volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 852 | volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 853 | volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 854 | volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 855 | volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 856 | volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 857 | volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 858 | volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 859 | volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 860 | volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 861 | volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 862 | volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 863 | volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 864 | volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 865 | volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 866 | volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 867 | volatile uint8_t dummy1[4]; /* */ |
AnnaBridge | 161:aa5281ff4a02 | 868 | volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */ |
AnnaBridge | 161:aa5281ff4a02 | 869 | } r_io_scux_from_dvuir_dvu0_n_t; |
AnnaBridge | 161:aa5281ff4a02 | 870 | |
AnnaBridge | 161:aa5281ff4a02 | 871 | |
AnnaBridge | 161:aa5281ff4a02 | 872 | /* Channel array defines of SCUX (2)*/ |
AnnaBridge | 161:aa5281ff4a02 | 873 | #ifdef DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS |
AnnaBridge | 161:aa5281ff4a02 | 874 | volatile struct st_scux_from_dvuir_dvu0_n* SCUX_FROM_DVUIR_DVU0_0_ARRAY[ SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT ] = |
AnnaBridge | 161:aa5281ff4a02 | 875 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 876 | SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST; |
AnnaBridge | 161:aa5281ff4a02 | 877 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 878 | #endif /* DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS */ |
AnnaBridge | 161:aa5281ff4a02 | 879 | |
AnnaBridge | 161:aa5281ff4a02 | 880 | #ifdef DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS |
AnnaBridge | 161:aa5281ff4a02 | 881 | volatile struct st_scux_from_srcir0_2src0_n* SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT ] = |
AnnaBridge | 161:aa5281ff4a02 | 882 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 883 | SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST; |
AnnaBridge | 161:aa5281ff4a02 | 884 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 885 | #endif /* DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS */ |
AnnaBridge | 161:aa5281ff4a02 | 886 | |
AnnaBridge | 161:aa5281ff4a02 | 887 | #ifdef DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS |
AnnaBridge | 161:aa5281ff4a02 | 888 | volatile struct st_scux_from_ffuir_ffu0_n* SCUX_FROM_FFUIR_FFU0_0_ARRAY[ SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT ] = |
AnnaBridge | 161:aa5281ff4a02 | 889 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 890 | SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST; |
AnnaBridge | 161:aa5281ff4a02 | 891 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 892 | #endif /* DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS */ |
AnnaBridge | 161:aa5281ff4a02 | 893 | |
AnnaBridge | 161:aa5281ff4a02 | 894 | #ifdef DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS |
AnnaBridge | 161:aa5281ff4a02 | 895 | volatile struct st_scux_from_ffdir_ffd0_n* SCUX_FROM_FFDIR_FFD0_0_ARRAY[ SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT ] = |
AnnaBridge | 161:aa5281ff4a02 | 896 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 897 | SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST; |
AnnaBridge | 161:aa5281ff4a02 | 898 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 899 | #endif /* DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS */ |
AnnaBridge | 161:aa5281ff4a02 | 900 | |
AnnaBridge | 161:aa5281ff4a02 | 901 | #ifdef DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS |
AnnaBridge | 161:aa5281ff4a02 | 902 | volatile struct st_scux_from_opcir_opc0_n* SCUX_FROM_OPCIR_OPC0_0_ARRAY[ SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT ] = |
AnnaBridge | 161:aa5281ff4a02 | 903 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 904 | SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST; |
AnnaBridge | 161:aa5281ff4a02 | 905 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 906 | #endif /* DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS */ |
AnnaBridge | 161:aa5281ff4a02 | 907 | |
AnnaBridge | 161:aa5281ff4a02 | 908 | #ifdef DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS |
AnnaBridge | 161:aa5281ff4a02 | 909 | volatile struct st_scux_from_ipcir_ipc0_n* SCUX_FROM_IPCIR_IPC0_0_ARRAY[ SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT ] = |
AnnaBridge | 161:aa5281ff4a02 | 910 | /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 911 | SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST; |
AnnaBridge | 161:aa5281ff4a02 | 912 | /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 913 | #endif /* DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS */ |
AnnaBridge | 161:aa5281ff4a02 | 914 | /* End of channel array defines of SCUX (2)*/ |
AnnaBridge | 161:aa5281ff4a02 | 915 | |
AnnaBridge | 161:aa5281ff4a02 | 916 | |
AnnaBridge | 161:aa5281ff4a02 | 917 | /* <-SEC M1.10.1 */ |
AnnaBridge | 161:aa5281ff4a02 | 918 | /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ |
AnnaBridge | 161:aa5281ff4a02 | 919 | /* <-QAC 0857 */ |
AnnaBridge | 161:aa5281ff4a02 | 920 | /* <-QAC 0639 */ |
AnnaBridge | 161:aa5281ff4a02 | 921 | #endif |