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TARGET_RO359B/TOOLCHAIN_IAR/MK24F12_features.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	143:86740a56073b	1	/*
AnnaBridge	143:86740a56073b	2	** ###################################################################
AnnaBridge	143:86740a56073b	3	** Version: rev. 2.14, 2016-03-21
AnnaBridge	143:86740a56073b	4	** Build: b170228
AnnaBridge	143:86740a56073b	5	**
AnnaBridge	143:86740a56073b	6	** Abstract:
AnnaBridge	143:86740a56073b	7	** Chip specific module features.
AnnaBridge	143:86740a56073b	8	**
AnnaBridge	143:86740a56073b	9	** Copyright 2016 Freescale Semiconductor, Inc.
AnnaBridge	143:86740a56073b	10	** Copyright 2016-2017 NXP
AnnaBridge	143:86740a56073b	11	** Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	143:86740a56073b	12	** are permitted provided that the following conditions are met:
AnnaBridge	143:86740a56073b	13	**
AnnaBridge	143:86740a56073b	14	** o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge	143:86740a56073b	15	** of conditions and the following disclaimer.
AnnaBridge	143:86740a56073b	16	**
AnnaBridge	143:86740a56073b	17	** o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge	143:86740a56073b	18	** list of conditions and the following disclaimer in the documentation and/or
AnnaBridge	143:86740a56073b	19	** other materials provided with the distribution.
AnnaBridge	143:86740a56073b	20	**
AnnaBridge	143:86740a56073b	21	** o Neither the name of the copyright holder nor the names of its
AnnaBridge	143:86740a56073b	22	** contributors may be used to endorse or promote products derived from this
AnnaBridge	143:86740a56073b	23	** software without specific prior written permission.
AnnaBridge	143:86740a56073b	24	**
AnnaBridge	143:86740a56073b	25	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge	143:86740a56073b	26	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge	143:86740a56073b	27	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	143:86740a56073b	28	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge	143:86740a56073b	29	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge	143:86740a56073b	30	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge	143:86740a56073b	31	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge	143:86740a56073b	32	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge	143:86740a56073b	33	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge	143:86740a56073b	34	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	143:86740a56073b	35	**
AnnaBridge	143:86740a56073b	36	** http: www.nxp.com
AnnaBridge	143:86740a56073b	37	** mail: support@nxp.com
AnnaBridge	143:86740a56073b	38	**
AnnaBridge	143:86740a56073b	39	** Revisions:
AnnaBridge	143:86740a56073b	40	** - rev. 1.0 (2013-08-12)
AnnaBridge	143:86740a56073b	41	** Initial version.
AnnaBridge	143:86740a56073b	42	** - rev. 2.0 (2013-10-29)
AnnaBridge	143:86740a56073b	43	** Register accessor macros added to the memory map.
AnnaBridge	143:86740a56073b	44	** Symbols for Processor Expert memory map compatibility added to the memory map.
AnnaBridge	143:86740a56073b	45	** Startup file for gcc has been updated according to CMSIS 3.2.
AnnaBridge	143:86740a56073b	46	** System initialization updated.
AnnaBridge	143:86740a56073b	47	** MCG - registers updated.
AnnaBridge	143:86740a56073b	48	** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
AnnaBridge	143:86740a56073b	49	** - rev. 2.1 (2013-10-30)
AnnaBridge	143:86740a56073b	50	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
AnnaBridge	143:86740a56073b	51	** - rev. 2.2 (2013-12-09)
AnnaBridge	143:86740a56073b	52	** DMA - EARS register removed.
AnnaBridge	143:86740a56073b	53	** AIPS0, AIPS1 - MPRA register updated.
AnnaBridge	143:86740a56073b	54	** - rev. 2.3 (2014-01-24)
AnnaBridge	143:86740a56073b	55	** Update according to reference manual rev. 2
AnnaBridge	143:86740a56073b	56	** ENET, MCG, MCM, SIM, USB - registers updated
AnnaBridge	143:86740a56073b	57	** - rev. 2.4 (2014-01-30)
AnnaBridge	143:86740a56073b	58	** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum.
AnnaBridge	143:86740a56073b	59	** - rev. 2.5 (2014-02-10)
AnnaBridge	143:86740a56073b	60	** The declaration of clock configurations has been moved to separate header file system_MK24F12.h
AnnaBridge	143:86740a56073b	61	** Update of SystemInit() and SystemCoreClockUpdate() functions.
AnnaBridge	143:86740a56073b	62	** Module access macro module_BASES replaced by module_BASE_PTRS.
AnnaBridge	143:86740a56073b	63	** - rev. 2.6 (2014-08-28)
AnnaBridge	143:86740a56073b	64	** Update of system files - default clock configuration changed.
AnnaBridge	143:86740a56073b	65	** Update of startup files - possibility to override DefaultISR added.
AnnaBridge	143:86740a56073b	66	** - rev. 2.7 (2014-10-14)
AnnaBridge	143:86740a56073b	67	** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
AnnaBridge	143:86740a56073b	68	** - rev. 2.8 (2015-01-21)
AnnaBridge	143:86740a56073b	69	** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances
AnnaBridge	143:86740a56073b	70	** - rev. 2.9 (2015-02-19)
AnnaBridge	143:86740a56073b	71	** Renamed interrupt vector LLW to LLWU.
AnnaBridge	143:86740a56073b	72	** - rev. 2.10 (2015-05-19)
AnnaBridge	143:86740a56073b	73	** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT.
AnnaBridge	143:86740a56073b	74	** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC.
AnnaBridge	143:86740a56073b	75	** Added features for PDB and PORT.
AnnaBridge	143:86740a56073b	76	** - rev. 2.11 (2015-05-25)
AnnaBridge	143:86740a56073b	77	** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
AnnaBridge	143:86740a56073b	78	** - rev. 2.12 (2015-05-27)
AnnaBridge	143:86740a56073b	79	** Several USB features added.
AnnaBridge	143:86740a56073b	80	** - rev. 2.13 (2015-06-08)
AnnaBridge	143:86740a56073b	81	** FTM features BUS_CLOCK and FAST_CLOCK removed.
AnnaBridge	143:86740a56073b	82	** - rev. 2.14 (2016-03-21)
AnnaBridge	143:86740a56073b	83	** Added MK24FN1M0CAJ12 part.
AnnaBridge	143:86740a56073b	84	**
AnnaBridge	143:86740a56073b	85	** ###################################################################
AnnaBridge	143:86740a56073b	86	*/
AnnaBridge	143:86740a56073b	87
AnnaBridge	143:86740a56073b	88	#ifndef _MK24F12_FEATURES_H_
AnnaBridge	143:86740a56073b	89	#define _MK24F12_FEATURES_H_
AnnaBridge	143:86740a56073b	90
AnnaBridge	143:86740a56073b	91	/* SOC module features */
AnnaBridge	143:86740a56073b	92
AnnaBridge	143:86740a56073b	93	#if defined(CPU_MK24FN1M0CAJ12) \|\| defined(CPU_MK24FN1M0VDC12) \|\| defined(CPU_MK24FN1M0VLQ12)
AnnaBridge	143:86740a56073b	94	/* @brief ACMP availability on the SoC. */
AnnaBridge	143:86740a56073b	95	#define FSL_FEATURE_SOC_ACMP_COUNT (0)
AnnaBridge	143:86740a56073b	96	/* @brief ADC16 availability on the SoC. */
AnnaBridge	143:86740a56073b	97	#define FSL_FEATURE_SOC_ADC16_COUNT (2)
AnnaBridge	143:86740a56073b	98	/* @brief ADC12 availability on the SoC. */
AnnaBridge	143:86740a56073b	99	#define FSL_FEATURE_SOC_ADC12_COUNT (0)
AnnaBridge	143:86740a56073b	100	/* @brief AFE availability on the SoC. */
AnnaBridge	143:86740a56073b	101	#define FSL_FEATURE_SOC_AFE_COUNT (0)
AnnaBridge	143:86740a56073b	102	/* @brief AIPS availability on the SoC. */
AnnaBridge	143:86740a56073b	103	#define FSL_FEATURE_SOC_AIPS_COUNT (2)
AnnaBridge	143:86740a56073b	104	/* @brief AOI availability on the SoC. */
AnnaBridge	143:86740a56073b	105	#define FSL_FEATURE_SOC_AOI_COUNT (0)
AnnaBridge	143:86740a56073b	106	/* @brief AXBS availability on the SoC. */
AnnaBridge	143:86740a56073b	107	#define FSL_FEATURE_SOC_AXBS_COUNT (1)
AnnaBridge	143:86740a56073b	108	/* @brief ASMC availability on the SoC. */
AnnaBridge	143:86740a56073b	109	#define FSL_FEATURE_SOC_ASMC_COUNT (0)
AnnaBridge	143:86740a56073b	110	/* @brief CADC availability on the SoC. */
AnnaBridge	143:86740a56073b	111	#define FSL_FEATURE_SOC_CADC_COUNT (0)
AnnaBridge	143:86740a56073b	112	/* @brief FLEXCAN availability on the SoC. */
AnnaBridge	143:86740a56073b	113	#define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
AnnaBridge	143:86740a56073b	114	/* @brief MMCAU availability on the SoC. */
AnnaBridge	143:86740a56073b	115	#define FSL_FEATURE_SOC_MMCAU_COUNT (1)
AnnaBridge	143:86740a56073b	116	/* @brief CMP availability on the SoC. */
AnnaBridge	143:86740a56073b	117	#define FSL_FEATURE_SOC_CMP_COUNT (3)
AnnaBridge	143:86740a56073b	118	/* @brief CMT availability on the SoC. */
AnnaBridge	143:86740a56073b	119	#define FSL_FEATURE_SOC_CMT_COUNT (1)
AnnaBridge	143:86740a56073b	120	/* @brief CNC availability on the SoC. */
AnnaBridge	143:86740a56073b	121	#define FSL_FEATURE_SOC_CNC_COUNT (0)
AnnaBridge	143:86740a56073b	122	/* @brief CRC availability on the SoC. */
AnnaBridge	143:86740a56073b	123	#define FSL_FEATURE_SOC_CRC_COUNT (1)
AnnaBridge	143:86740a56073b	124	/* @brief DAC availability on the SoC. */
AnnaBridge	143:86740a56073b	125	#define FSL_FEATURE_SOC_DAC_COUNT (2)
AnnaBridge	143:86740a56073b	126	/* @brief DAC32 availability on the SoC. */
AnnaBridge	143:86740a56073b	127	#define FSL_FEATURE_SOC_DAC32_COUNT (0)
AnnaBridge	143:86740a56073b	128	/* @brief DCDC availability on the SoC. */
AnnaBridge	143:86740a56073b	129	#define FSL_FEATURE_SOC_DCDC_COUNT (0)
AnnaBridge	143:86740a56073b	130	/* @brief DDR availability on the SoC. */
AnnaBridge	143:86740a56073b	131	#define FSL_FEATURE_SOC_DDR_COUNT (0)
AnnaBridge	143:86740a56073b	132	/* @brief DMA availability on the SoC. */
AnnaBridge	143:86740a56073b	133	#define FSL_FEATURE_SOC_DMA_COUNT (0)
AnnaBridge	143:86740a56073b	134	/* @brief EDMA availability on the SoC. */
AnnaBridge	143:86740a56073b	135	#define FSL_FEATURE_SOC_EDMA_COUNT (1)
AnnaBridge	143:86740a56073b	136	/* @brief DMAMUX availability on the SoC. */
AnnaBridge	143:86740a56073b	137	#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
AnnaBridge	143:86740a56073b	138	/* @brief DRY availability on the SoC. */
AnnaBridge	143:86740a56073b	139	#define FSL_FEATURE_SOC_DRY_COUNT (0)
AnnaBridge	143:86740a56073b	140	/* @brief DSPI availability on the SoC. */
AnnaBridge	143:86740a56073b	141	#define FSL_FEATURE_SOC_DSPI_COUNT (3)
AnnaBridge	143:86740a56073b	142	/* @brief EMVSIM availability on the SoC. */
AnnaBridge	143:86740a56073b	143	#define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
AnnaBridge	143:86740a56073b	144	/* @brief ENC availability on the SoC. */
AnnaBridge	143:86740a56073b	145	#define FSL_FEATURE_SOC_ENC_COUNT (0)
AnnaBridge	143:86740a56073b	146	/* @brief ENET availability on the SoC. */
AnnaBridge	143:86740a56073b	147	#define FSL_FEATURE_SOC_ENET_COUNT (0)
AnnaBridge	143:86740a56073b	148	/* @brief EWM availability on the SoC. */
AnnaBridge	143:86740a56073b	149	#define FSL_FEATURE_SOC_EWM_COUNT (1)
AnnaBridge	143:86740a56073b	150	/* @brief FB availability on the SoC. */
AnnaBridge	143:86740a56073b	151	#define FSL_FEATURE_SOC_FB_COUNT (1)
AnnaBridge	143:86740a56073b	152	/* @brief FGPIO availability on the SoC. */
AnnaBridge	143:86740a56073b	153	#define FSL_FEATURE_SOC_FGPIO_COUNT (0)
AnnaBridge	143:86740a56073b	154	/* @brief FLEXIO availability on the SoC. */
AnnaBridge	143:86740a56073b	155	#define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
AnnaBridge	143:86740a56073b	156	/* @brief FMC availability on the SoC. */
AnnaBridge	143:86740a56073b	157	#define FSL_FEATURE_SOC_FMC_COUNT (1)
AnnaBridge	143:86740a56073b	158	/* @brief FSKDT availability on the SoC. */
AnnaBridge	143:86740a56073b	159	#define FSL_FEATURE_SOC_FSKDT_COUNT (0)
AnnaBridge	143:86740a56073b	160	/* @brief FTFA availability on the SoC. */
AnnaBridge	143:86740a56073b	161	#define FSL_FEATURE_SOC_FTFA_COUNT (0)
AnnaBridge	143:86740a56073b	162	/* @brief FTFE availability on the SoC. */
AnnaBridge	143:86740a56073b	163	#define FSL_FEATURE_SOC_FTFE_COUNT (1)
AnnaBridge	143:86740a56073b	164	/* @brief FTFL availability on the SoC. */
AnnaBridge	143:86740a56073b	165	#define FSL_FEATURE_SOC_FTFL_COUNT (0)
AnnaBridge	143:86740a56073b	166	/* @brief FTM availability on the SoC. */
AnnaBridge	143:86740a56073b	167	#define FSL_FEATURE_SOC_FTM_COUNT (4)
AnnaBridge	143:86740a56073b	168	/* @brief FTMRA availability on the SoC. */
AnnaBridge	143:86740a56073b	169	#define FSL_FEATURE_SOC_FTMRA_COUNT (0)
AnnaBridge	143:86740a56073b	170	/* @brief FTMRE availability on the SoC. */
AnnaBridge	143:86740a56073b	171	#define FSL_FEATURE_SOC_FTMRE_COUNT (0)
AnnaBridge	143:86740a56073b	172	/* @brief FTMRH availability on the SoC. */
AnnaBridge	143:86740a56073b	173	#define FSL_FEATURE_SOC_FTMRH_COUNT (0)
AnnaBridge	143:86740a56073b	174	/* @brief GPIO availability on the SoC. */
AnnaBridge	143:86740a56073b	175	#define FSL_FEATURE_SOC_GPIO_COUNT (5)
AnnaBridge	143:86740a56073b	176	/* @brief HSADC availability on the SoC. */
AnnaBridge	143:86740a56073b	177	#define FSL_FEATURE_SOC_HSADC_COUNT (0)
AnnaBridge	143:86740a56073b	178	/* @brief I2C availability on the SoC. */
AnnaBridge	143:86740a56073b	179	#define FSL_FEATURE_SOC_I2C_COUNT (3)
AnnaBridge	143:86740a56073b	180	/* @brief I2S availability on the SoC. */
AnnaBridge	143:86740a56073b	181	#define FSL_FEATURE_SOC_I2S_COUNT (1)
AnnaBridge	143:86740a56073b	182	/* @brief ICS availability on the SoC. */
AnnaBridge	143:86740a56073b	183	#define FSL_FEATURE_SOC_ICS_COUNT (0)
AnnaBridge	143:86740a56073b	184	/* @brief INTMUX availability on the SoC. */
AnnaBridge	143:86740a56073b	185	#define FSL_FEATURE_SOC_INTMUX_COUNT (0)
AnnaBridge	143:86740a56073b	186	/* @brief IRQ availability on the SoC. */
AnnaBridge	143:86740a56073b	187	#define FSL_FEATURE_SOC_IRQ_COUNT (0)
AnnaBridge	143:86740a56073b	188	/* @brief KBI availability on the SoC. */
AnnaBridge	143:86740a56073b	189	#define FSL_FEATURE_SOC_KBI_COUNT (0)
AnnaBridge	143:86740a56073b	190	/* @brief SLCD availability on the SoC. */
AnnaBridge	143:86740a56073b	191	#define FSL_FEATURE_SOC_SLCD_COUNT (0)
AnnaBridge	143:86740a56073b	192	/* @brief LCDC availability on the SoC. */
AnnaBridge	143:86740a56073b	193	#define FSL_FEATURE_SOC_LCDC_COUNT (0)
AnnaBridge	143:86740a56073b	194	/* @brief LDO availability on the SoC. */
AnnaBridge	143:86740a56073b	195	#define FSL_FEATURE_SOC_LDO_COUNT (0)
AnnaBridge	143:86740a56073b	196	/* @brief LLWU availability on the SoC. */
AnnaBridge	143:86740a56073b	197	#define FSL_FEATURE_SOC_LLWU_COUNT (1)
AnnaBridge	143:86740a56073b	198	/* @brief LMEM availability on the SoC. */
AnnaBridge	143:86740a56073b	199	#define FSL_FEATURE_SOC_LMEM_COUNT (0)
AnnaBridge	143:86740a56073b	200	/* @brief LPI2C availability on the SoC. */
AnnaBridge	143:86740a56073b	201	#define FSL_FEATURE_SOC_LPI2C_COUNT (0)
AnnaBridge	143:86740a56073b	202	/* @brief LPIT availability on the SoC. */
AnnaBridge	143:86740a56073b	203	#define FSL_FEATURE_SOC_LPIT_COUNT (0)
AnnaBridge	143:86740a56073b	204	/* @brief LPSCI availability on the SoC. */
AnnaBridge	143:86740a56073b	205	#define FSL_FEATURE_SOC_LPSCI_COUNT (0)
AnnaBridge	143:86740a56073b	206	/* @brief LPSPI availability on the SoC. */
AnnaBridge	143:86740a56073b	207	#define FSL_FEATURE_SOC_LPSPI_COUNT (0)
AnnaBridge	143:86740a56073b	208	/* @brief LPTMR availability on the SoC. */
AnnaBridge	143:86740a56073b	209	#define FSL_FEATURE_SOC_LPTMR_COUNT (1)
AnnaBridge	143:86740a56073b	210	/* @brief LPTPM availability on the SoC. */
AnnaBridge	143:86740a56073b	211	#define FSL_FEATURE_SOC_LPTPM_COUNT (0)
AnnaBridge	143:86740a56073b	212	/* @brief LPUART availability on the SoC. */
AnnaBridge	143:86740a56073b	213	#define FSL_FEATURE_SOC_LPUART_COUNT (0)
AnnaBridge	143:86740a56073b	214	/* @brief LTC availability on the SoC. */
AnnaBridge	143:86740a56073b	215	#define FSL_FEATURE_SOC_LTC_COUNT (0)
AnnaBridge	143:86740a56073b	216	/* @brief MC availability on the SoC. */
AnnaBridge	143:86740a56073b	217	#define FSL_FEATURE_SOC_MC_COUNT (0)
AnnaBridge	143:86740a56073b	218	/* @brief MCG availability on the SoC. */
AnnaBridge	143:86740a56073b	219	#define FSL_FEATURE_SOC_MCG_COUNT (1)
AnnaBridge	143:86740a56073b	220	/* @brief MCGLITE availability on the SoC. */
AnnaBridge	143:86740a56073b	221	#define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
AnnaBridge	143:86740a56073b	222	/* @brief MCM availability on the SoC. */
AnnaBridge	143:86740a56073b	223	#define FSL_FEATURE_SOC_MCM_COUNT (1)
AnnaBridge	143:86740a56073b	224	/* @brief MMAU availability on the SoC. */
AnnaBridge	143:86740a56073b	225	#define FSL_FEATURE_SOC_MMAU_COUNT (0)
AnnaBridge	143:86740a56073b	226	/* @brief MMDVSQ availability on the SoC. */
AnnaBridge	143:86740a56073b	227	#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
AnnaBridge	143:86740a56073b	228	/* @brief SYSMPU availability on the SoC. */
AnnaBridge	143:86740a56073b	229	#define FSL_FEATURE_SOC_SYSMPU_COUNT (1)
AnnaBridge	143:86740a56073b	230	/* @brief MSCAN availability on the SoC. */
AnnaBridge	143:86740a56073b	231	#define FSL_FEATURE_SOC_MSCAN_COUNT (0)
AnnaBridge	143:86740a56073b	232	/* @brief MSCM availability on the SoC. */
AnnaBridge	143:86740a56073b	233	#define FSL_FEATURE_SOC_MSCM_COUNT (0)
AnnaBridge	143:86740a56073b	234	/* @brief MTB availability on the SoC. */
AnnaBridge	143:86740a56073b	235	#define FSL_FEATURE_SOC_MTB_COUNT (0)
AnnaBridge	143:86740a56073b	236	/* @brief MTBDWT availability on the SoC. */
AnnaBridge	143:86740a56073b	237	#define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
AnnaBridge	143:86740a56073b	238	/* @brief MU availability on the SoC. */
AnnaBridge	143:86740a56073b	239	#define FSL_FEATURE_SOC_MU_COUNT (0)
AnnaBridge	143:86740a56073b	240	/* @brief NFC availability on the SoC. */
AnnaBridge	143:86740a56073b	241	#define FSL_FEATURE_SOC_NFC_COUNT (0)
AnnaBridge	143:86740a56073b	242	/* @brief OPAMP availability on the SoC. */
AnnaBridge	143:86740a56073b	243	#define FSL_FEATURE_SOC_OPAMP_COUNT (0)
AnnaBridge	143:86740a56073b	244	/* @brief OSC availability on the SoC. */
AnnaBridge	143:86740a56073b	245	#define FSL_FEATURE_SOC_OSC_COUNT (1)
AnnaBridge	143:86740a56073b	246	/* @brief OSC32 availability on the SoC. */
AnnaBridge	143:86740a56073b	247	#define FSL_FEATURE_SOC_OSC32_COUNT (0)
AnnaBridge	143:86740a56073b	248	/* @brief OTFAD availability on the SoC. */
AnnaBridge	143:86740a56073b	249	#define FSL_FEATURE_SOC_OTFAD_COUNT (0)
AnnaBridge	143:86740a56073b	250	/* @brief PDB availability on the SoC. */
AnnaBridge	143:86740a56073b	251	#define FSL_FEATURE_SOC_PDB_COUNT (1)
AnnaBridge	143:86740a56073b	252	/* @brief PCC availability on the SoC. */
AnnaBridge	143:86740a56073b	253	#define FSL_FEATURE_SOC_PCC_COUNT (0)
AnnaBridge	143:86740a56073b	254	/* @brief PGA availability on the SoC. */
AnnaBridge	143:86740a56073b	255	#define FSL_FEATURE_SOC_PGA_COUNT (0)
AnnaBridge	143:86740a56073b	256	/* @brief PIT availability on the SoC. */
AnnaBridge	143:86740a56073b	257	#define FSL_FEATURE_SOC_PIT_COUNT (1)
AnnaBridge	143:86740a56073b	258	/* @brief PMC availability on the SoC. */
AnnaBridge	143:86740a56073b	259	#define FSL_FEATURE_SOC_PMC_COUNT (1)
AnnaBridge	143:86740a56073b	260	/* @brief PORT availability on the SoC. */
AnnaBridge	143:86740a56073b	261	#define FSL_FEATURE_SOC_PORT_COUNT (5)
AnnaBridge	143:86740a56073b	262	/* @brief PWM availability on the SoC. */
AnnaBridge	143:86740a56073b	263	#define FSL_FEATURE_SOC_PWM_COUNT (0)
AnnaBridge	143:86740a56073b	264	/* @brief PWT availability on the SoC. */
AnnaBridge	143:86740a56073b	265	#define FSL_FEATURE_SOC_PWT_COUNT (0)
AnnaBridge	143:86740a56073b	266	/* @brief QuadSPI availability on the SoC. */
AnnaBridge	143:86740a56073b	267	#define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
AnnaBridge	143:86740a56073b	268	/* @brief RCM availability on the SoC. */
AnnaBridge	143:86740a56073b	269	#define FSL_FEATURE_SOC_RCM_COUNT (1)
AnnaBridge	143:86740a56073b	270	/* @brief RFSYS availability on the SoC. */
AnnaBridge	143:86740a56073b	271	#define FSL_FEATURE_SOC_RFSYS_COUNT (1)
AnnaBridge	143:86740a56073b	272	/* @brief RFVBAT availability on the SoC. */
AnnaBridge	143:86740a56073b	273	#define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
AnnaBridge	143:86740a56073b	274	/* @brief RNG availability on the SoC. */
AnnaBridge	143:86740a56073b	275	#define FSL_FEATURE_SOC_RNG_COUNT (1)
AnnaBridge	143:86740a56073b	276	/* @brief RNGB availability on the SoC. */
AnnaBridge	143:86740a56073b	277	#define FSL_FEATURE_SOC_RNGB_COUNT (0)
AnnaBridge	143:86740a56073b	278	/* @brief ROM availability on the SoC. */
AnnaBridge	143:86740a56073b	279	#define FSL_FEATURE_SOC_ROM_COUNT (0)
AnnaBridge	143:86740a56073b	280	/* @brief RSIM availability on the SoC. */
AnnaBridge	143:86740a56073b	281	#define FSL_FEATURE_SOC_RSIM_COUNT (0)
AnnaBridge	143:86740a56073b	282	/* @brief RTC availability on the SoC. */
AnnaBridge	143:86740a56073b	283	#define FSL_FEATURE_SOC_RTC_COUNT (1)
AnnaBridge	143:86740a56073b	284	/* @brief SCG availability on the SoC. */
AnnaBridge	143:86740a56073b	285	#define FSL_FEATURE_SOC_SCG_COUNT (0)
AnnaBridge	143:86740a56073b	286	/* @brief SCI availability on the SoC. */
AnnaBridge	143:86740a56073b	287	#define FSL_FEATURE_SOC_SCI_COUNT (0)
AnnaBridge	143:86740a56073b	288	/* @brief SDHC availability on the SoC. */
AnnaBridge	143:86740a56073b	289	#define FSL_FEATURE_SOC_SDHC_COUNT (1)
AnnaBridge	143:86740a56073b	290	/* @brief SDRAM availability on the SoC. */
AnnaBridge	143:86740a56073b	291	#define FSL_FEATURE_SOC_SDRAM_COUNT (0)
AnnaBridge	143:86740a56073b	292	/* @brief SEMA42 availability on the SoC. */
AnnaBridge	143:86740a56073b	293	#define FSL_FEATURE_SOC_SEMA42_COUNT (0)
AnnaBridge	143:86740a56073b	294	/* @brief SIM availability on the SoC. */
AnnaBridge	143:86740a56073b	295	#define FSL_FEATURE_SOC_SIM_COUNT (1)
AnnaBridge	143:86740a56073b	296	/* @brief SMC availability on the SoC. */
AnnaBridge	143:86740a56073b	297	#define FSL_FEATURE_SOC_SMC_COUNT (1)
AnnaBridge	143:86740a56073b	298	/* @brief SPI availability on the SoC. */
AnnaBridge	143:86740a56073b	299	#define FSL_FEATURE_SOC_SPI_COUNT (0)
AnnaBridge	143:86740a56073b	300	/* @brief TMR availability on the SoC. */
AnnaBridge	143:86740a56073b	301	#define FSL_FEATURE_SOC_TMR_COUNT (0)
AnnaBridge	143:86740a56073b	302	/* @brief TPM availability on the SoC. */
AnnaBridge	143:86740a56073b	303	#define FSL_FEATURE_SOC_TPM_COUNT (0)
AnnaBridge	143:86740a56073b	304	/* @brief TRGMUX availability on the SoC. */
AnnaBridge	143:86740a56073b	305	#define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
AnnaBridge	143:86740a56073b	306	/* @brief TRIAMP availability on the SoC. */
AnnaBridge	143:86740a56073b	307	#define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
AnnaBridge	143:86740a56073b	308	/* @brief TRNG availability on the SoC. */
AnnaBridge	143:86740a56073b	309	#define FSL_FEATURE_SOC_TRNG_COUNT (0)
AnnaBridge	143:86740a56073b	310	/* @brief TSI availability on the SoC. */
AnnaBridge	143:86740a56073b	311	#define FSL_FEATURE_SOC_TSI_COUNT (0)
AnnaBridge	143:86740a56073b	312	/* @brief TSTMR availability on the SoC. */
AnnaBridge	143:86740a56073b	313	#define FSL_FEATURE_SOC_TSTMR_COUNT (0)
AnnaBridge	143:86740a56073b	314	/* @brief UART availability on the SoC. */
AnnaBridge	143:86740a56073b	315	#define FSL_FEATURE_SOC_UART_COUNT (6)
AnnaBridge	143:86740a56073b	316	/* @brief USB availability on the SoC. */
AnnaBridge	143:86740a56073b	317	#define FSL_FEATURE_SOC_USB_COUNT (1)
AnnaBridge	143:86740a56073b	318	/* @brief USBDCD availability on the SoC. */
AnnaBridge	143:86740a56073b	319	#define FSL_FEATURE_SOC_USBDCD_COUNT (1)
AnnaBridge	143:86740a56073b	320	/* @brief USBHS availability on the SoC. */
AnnaBridge	143:86740a56073b	321	#define FSL_FEATURE_SOC_USBHS_COUNT (0)
AnnaBridge	143:86740a56073b	322	/* @brief USBHSDCD availability on the SoC. */
AnnaBridge	143:86740a56073b	323	#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
AnnaBridge	143:86740a56073b	324	/* @brief USBPHY availability on the SoC. */
AnnaBridge	143:86740a56073b	325	#define FSL_FEATURE_SOC_USBPHY_COUNT (0)
AnnaBridge	143:86740a56073b	326	/* @brief VREF availability on the SoC. */
AnnaBridge	143:86740a56073b	327	#define FSL_FEATURE_SOC_VREF_COUNT (1)
AnnaBridge	143:86740a56073b	328	/* @brief WDOG availability on the SoC. */
AnnaBridge	143:86740a56073b	329	#define FSL_FEATURE_SOC_WDOG_COUNT (1)
AnnaBridge	143:86740a56073b	330	/* @brief XBAR availability on the SoC. */
AnnaBridge	143:86740a56073b	331	#define FSL_FEATURE_SOC_XBAR_COUNT (0)
AnnaBridge	143:86740a56073b	332	/* @brief XBARA availability on the SoC. */
AnnaBridge	143:86740a56073b	333	#define FSL_FEATURE_SOC_XBARA_COUNT (0)
AnnaBridge	143:86740a56073b	334	/* @brief XBARB availability on the SoC. */
AnnaBridge	143:86740a56073b	335	#define FSL_FEATURE_SOC_XBARB_COUNT (0)
AnnaBridge	143:86740a56073b	336	/* @brief XCVR availability on the SoC. */
AnnaBridge	143:86740a56073b	337	#define FSL_FEATURE_SOC_XCVR_COUNT (0)
AnnaBridge	143:86740a56073b	338	/* @brief XRDC availability on the SoC. */
AnnaBridge	143:86740a56073b	339	#define FSL_FEATURE_SOC_XRDC_COUNT (0)
AnnaBridge	143:86740a56073b	340	/* @brief ZLL availability on the SoC. */
AnnaBridge	143:86740a56073b	341	#define FSL_FEATURE_SOC_ZLL_COUNT (0)
AnnaBridge	143:86740a56073b	342	#elif defined(CPU_MK24FN1M0VLL12)
AnnaBridge	143:86740a56073b	343	/* @brief ACMP availability on the SoC. */
AnnaBridge	143:86740a56073b	344	#define FSL_FEATURE_SOC_ACMP_COUNT (0)
AnnaBridge	143:86740a56073b	345	/* @brief ADC16 availability on the SoC. */
AnnaBridge	143:86740a56073b	346	#define FSL_FEATURE_SOC_ADC16_COUNT (2)
AnnaBridge	143:86740a56073b	347	/* @brief ADC12 availability on the SoC. */
AnnaBridge	143:86740a56073b	348	#define FSL_FEATURE_SOC_ADC12_COUNT (0)
AnnaBridge	143:86740a56073b	349	/* @brief AFE availability on the SoC. */
AnnaBridge	143:86740a56073b	350	#define FSL_FEATURE_SOC_AFE_COUNT (0)
AnnaBridge	143:86740a56073b	351	/* @brief AIPS availability on the SoC. */
AnnaBridge	143:86740a56073b	352	#define FSL_FEATURE_SOC_AIPS_COUNT (2)
AnnaBridge	143:86740a56073b	353	/* @brief AOI availability on the SoC. */
AnnaBridge	143:86740a56073b	354	#define FSL_FEATURE_SOC_AOI_COUNT (0)
AnnaBridge	143:86740a56073b	355	/* @brief AXBS availability on the SoC. */
AnnaBridge	143:86740a56073b	356	#define FSL_FEATURE_SOC_AXBS_COUNT (1)
AnnaBridge	143:86740a56073b	357	/* @brief ASMC availability on the SoC. */
AnnaBridge	143:86740a56073b	358	#define FSL_FEATURE_SOC_ASMC_COUNT (0)
AnnaBridge	143:86740a56073b	359	/* @brief CADC availability on the SoC. */
AnnaBridge	143:86740a56073b	360	#define FSL_FEATURE_SOC_CADC_COUNT (0)
AnnaBridge	143:86740a56073b	361	/* @brief FLEXCAN availability on the SoC. */
AnnaBridge	143:86740a56073b	362	#define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
AnnaBridge	143:86740a56073b	363	/* @brief MMCAU availability on the SoC. */
AnnaBridge	143:86740a56073b	364	#define FSL_FEATURE_SOC_MMCAU_COUNT (1)
AnnaBridge	143:86740a56073b	365	/* @brief CMP availability on the SoC. */
AnnaBridge	143:86740a56073b	366	#define FSL_FEATURE_SOC_CMP_COUNT (3)
AnnaBridge	143:86740a56073b	367	/* @brief CMT availability on the SoC. */
AnnaBridge	143:86740a56073b	368	#define FSL_FEATURE_SOC_CMT_COUNT (1)
AnnaBridge	143:86740a56073b	369	/* @brief CNC availability on the SoC. */
AnnaBridge	143:86740a56073b	370	#define FSL_FEATURE_SOC_CNC_COUNT (0)
AnnaBridge	143:86740a56073b	371	/* @brief CRC availability on the SoC. */
AnnaBridge	143:86740a56073b	372	#define FSL_FEATURE_SOC_CRC_COUNT (1)
AnnaBridge	143:86740a56073b	373	/* @brief DAC availability on the SoC. */
AnnaBridge	143:86740a56073b	374	#define FSL_FEATURE_SOC_DAC_COUNT (1)
AnnaBridge	143:86740a56073b	375	/* @brief DAC32 availability on the SoC. */
AnnaBridge	143:86740a56073b	376	#define FSL_FEATURE_SOC_DAC32_COUNT (0)
AnnaBridge	143:86740a56073b	377	/* @brief DCDC availability on the SoC. */
AnnaBridge	143:86740a56073b	378	#define FSL_FEATURE_SOC_DCDC_COUNT (0)
AnnaBridge	143:86740a56073b	379	/* @brief DDR availability on the SoC. */
AnnaBridge	143:86740a56073b	380	#define FSL_FEATURE_SOC_DDR_COUNT (0)
AnnaBridge	143:86740a56073b	381	/* @brief DMA availability on the SoC. */
AnnaBridge	143:86740a56073b	382	#define FSL_FEATURE_SOC_DMA_COUNT (0)
AnnaBridge	143:86740a56073b	383	/* @brief EDMA availability on the SoC. */
AnnaBridge	143:86740a56073b	384	#define FSL_FEATURE_SOC_EDMA_COUNT (1)
AnnaBridge	143:86740a56073b	385	/* @brief DMAMUX availability on the SoC. */
AnnaBridge	143:86740a56073b	386	#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
AnnaBridge	143:86740a56073b	387	/* @brief DRY availability on the SoC. */
AnnaBridge	143:86740a56073b	388	#define FSL_FEATURE_SOC_DRY_COUNT (0)
AnnaBridge	143:86740a56073b	389	/* @brief DSPI availability on the SoC. */
AnnaBridge	143:86740a56073b	390	#define FSL_FEATURE_SOC_DSPI_COUNT (3)
AnnaBridge	143:86740a56073b	391	/* @brief EMVSIM availability on the SoC. */
AnnaBridge	143:86740a56073b	392	#define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
AnnaBridge	143:86740a56073b	393	/* @brief ENC availability on the SoC. */
AnnaBridge	143:86740a56073b	394	#define FSL_FEATURE_SOC_ENC_COUNT (0)
AnnaBridge	143:86740a56073b	395	/* @brief ENET availability on the SoC. */
AnnaBridge	143:86740a56073b	396	#define FSL_FEATURE_SOC_ENET_COUNT (0)
AnnaBridge	143:86740a56073b	397	/* @brief EWM availability on the SoC. */
AnnaBridge	143:86740a56073b	398	#define FSL_FEATURE_SOC_EWM_COUNT (1)
AnnaBridge	143:86740a56073b	399	/* @brief FB availability on the SoC. */
AnnaBridge	143:86740a56073b	400	#define FSL_FEATURE_SOC_FB_COUNT (1)
AnnaBridge	143:86740a56073b	401	/* @brief FGPIO availability on the SoC. */
AnnaBridge	143:86740a56073b	402	#define FSL_FEATURE_SOC_FGPIO_COUNT (0)
AnnaBridge	143:86740a56073b	403	/* @brief FLEXIO availability on the SoC. */
AnnaBridge	143:86740a56073b	404	#define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
AnnaBridge	143:86740a56073b	405	/* @brief FMC availability on the SoC. */
AnnaBridge	143:86740a56073b	406	#define FSL_FEATURE_SOC_FMC_COUNT (1)
AnnaBridge	143:86740a56073b	407	/* @brief FSKDT availability on the SoC. */
AnnaBridge	143:86740a56073b	408	#define FSL_FEATURE_SOC_FSKDT_COUNT (0)
AnnaBridge	143:86740a56073b	409	/* @brief FTFA availability on the SoC. */
AnnaBridge	143:86740a56073b	410	#define FSL_FEATURE_SOC_FTFA_COUNT (0)
AnnaBridge	143:86740a56073b	411	/* @brief FTFE availability on the SoC. */
AnnaBridge	143:86740a56073b	412	#define FSL_FEATURE_SOC_FTFE_COUNT (1)
AnnaBridge	143:86740a56073b	413	/* @brief FTFL availability on the SoC. */
AnnaBridge	143:86740a56073b	414	#define FSL_FEATURE_SOC_FTFL_COUNT (0)
AnnaBridge	143:86740a56073b	415	/* @brief FTM availability on the SoC. */
AnnaBridge	143:86740a56073b	416	#define FSL_FEATURE_SOC_FTM_COUNT (4)
AnnaBridge	143:86740a56073b	417	/* @brief FTMRA availability on the SoC. */
AnnaBridge	143:86740a56073b	418	#define FSL_FEATURE_SOC_FTMRA_COUNT (0)
AnnaBridge	143:86740a56073b	419	/* @brief FTMRE availability on the SoC. */
AnnaBridge	143:86740a56073b	420	#define FSL_FEATURE_SOC_FTMRE_COUNT (0)
AnnaBridge	143:86740a56073b	421	/* @brief FTMRH availability on the SoC. */
AnnaBridge	143:86740a56073b	422	#define FSL_FEATURE_SOC_FTMRH_COUNT (0)
AnnaBridge	143:86740a56073b	423	/* @brief GPIO availability on the SoC. */
AnnaBridge	143:86740a56073b	424	#define FSL_FEATURE_SOC_GPIO_COUNT (5)
AnnaBridge	143:86740a56073b	425	/* @brief HSADC availability on the SoC. */
AnnaBridge	143:86740a56073b	426	#define FSL_FEATURE_SOC_HSADC_COUNT (0)
AnnaBridge	143:86740a56073b	427	/* @brief I2C availability on the SoC. */
AnnaBridge	143:86740a56073b	428	#define FSL_FEATURE_SOC_I2C_COUNT (3)
AnnaBridge	143:86740a56073b	429	/* @brief I2S availability on the SoC. */
AnnaBridge	143:86740a56073b	430	#define FSL_FEATURE_SOC_I2S_COUNT (1)
AnnaBridge	143:86740a56073b	431	/* @brief ICS availability on the SoC. */
AnnaBridge	143:86740a56073b	432	#define FSL_FEATURE_SOC_ICS_COUNT (0)
AnnaBridge	143:86740a56073b	433	/* @brief INTMUX availability on the SoC. */
AnnaBridge	143:86740a56073b	434	#define FSL_FEATURE_SOC_INTMUX_COUNT (0)
AnnaBridge	143:86740a56073b	435	/* @brief IRQ availability on the SoC. */
AnnaBridge	143:86740a56073b	436	#define FSL_FEATURE_SOC_IRQ_COUNT (0)
AnnaBridge	143:86740a56073b	437	/* @brief KBI availability on the SoC. */
AnnaBridge	143:86740a56073b	438	#define FSL_FEATURE_SOC_KBI_COUNT (0)
AnnaBridge	143:86740a56073b	439	/* @brief SLCD availability on the SoC. */
AnnaBridge	143:86740a56073b	440	#define FSL_FEATURE_SOC_SLCD_COUNT (0)
AnnaBridge	143:86740a56073b	441	/* @brief LCDC availability on the SoC. */
AnnaBridge	143:86740a56073b	442	#define FSL_FEATURE_SOC_LCDC_COUNT (0)
AnnaBridge	143:86740a56073b	443	/* @brief LDO availability on the SoC. */
AnnaBridge	143:86740a56073b	444	#define FSL_FEATURE_SOC_LDO_COUNT (0)
AnnaBridge	143:86740a56073b	445	/* @brief LLWU availability on the SoC. */
AnnaBridge	143:86740a56073b	446	#define FSL_FEATURE_SOC_LLWU_COUNT (1)
AnnaBridge	143:86740a56073b	447	/* @brief LMEM availability on the SoC. */
AnnaBridge	143:86740a56073b	448	#define FSL_FEATURE_SOC_LMEM_COUNT (0)
AnnaBridge	143:86740a56073b	449	/* @brief LPI2C availability on the SoC. */
AnnaBridge	143:86740a56073b	450	#define FSL_FEATURE_SOC_LPI2C_COUNT (0)
AnnaBridge	143:86740a56073b	451	/* @brief LPIT availability on the SoC. */
AnnaBridge	143:86740a56073b	452	#define FSL_FEATURE_SOC_LPIT_COUNT (0)
AnnaBridge	143:86740a56073b	453	/* @brief LPSCI availability on the SoC. */
AnnaBridge	143:86740a56073b	454	#define FSL_FEATURE_SOC_LPSCI_COUNT (0)
AnnaBridge	143:86740a56073b	455	/* @brief LPSPI availability on the SoC. */
AnnaBridge	143:86740a56073b	456	#define FSL_FEATURE_SOC_LPSPI_COUNT (0)
AnnaBridge	143:86740a56073b	457	/* @brief LPTMR availability on the SoC. */
AnnaBridge	143:86740a56073b	458	#define FSL_FEATURE_SOC_LPTMR_COUNT (1)
AnnaBridge	143:86740a56073b	459	/* @brief LPTPM availability on the SoC. */
AnnaBridge	143:86740a56073b	460	#define FSL_FEATURE_SOC_LPTPM_COUNT (0)
AnnaBridge	143:86740a56073b	461	/* @brief LPUART availability on the SoC. */
AnnaBridge	143:86740a56073b	462	#define FSL_FEATURE_SOC_LPUART_COUNT (0)
AnnaBridge	143:86740a56073b	463	/* @brief LTC availability on the SoC. */
AnnaBridge	143:86740a56073b	464	#define FSL_FEATURE_SOC_LTC_COUNT (0)
AnnaBridge	143:86740a56073b	465	/* @brief MC availability on the SoC. */
AnnaBridge	143:86740a56073b	466	#define FSL_FEATURE_SOC_MC_COUNT (0)
AnnaBridge	143:86740a56073b	467	/* @brief MCG availability on the SoC. */
AnnaBridge	143:86740a56073b	468	#define FSL_FEATURE_SOC_MCG_COUNT (1)
AnnaBridge	143:86740a56073b	469	/* @brief MCGLITE availability on the SoC. */
AnnaBridge	143:86740a56073b	470	#define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
AnnaBridge	143:86740a56073b	471	/* @brief MCM availability on the SoC. */
AnnaBridge	143:86740a56073b	472	#define FSL_FEATURE_SOC_MCM_COUNT (1)
AnnaBridge	143:86740a56073b	473	/* @brief MMAU availability on the SoC. */
AnnaBridge	143:86740a56073b	474	#define FSL_FEATURE_SOC_MMAU_COUNT (0)
AnnaBridge	143:86740a56073b	475	/* @brief MMDVSQ availability on the SoC. */
AnnaBridge	143:86740a56073b	476	#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
AnnaBridge	143:86740a56073b	477	/* @brief SYSMPU availability on the SoC. */
AnnaBridge	143:86740a56073b	478	#define FSL_FEATURE_SOC_SYSMPU_COUNT (1)
AnnaBridge	143:86740a56073b	479	/* @brief MSCAN availability on the SoC. */
AnnaBridge	143:86740a56073b	480	#define FSL_FEATURE_SOC_MSCAN_COUNT (0)
AnnaBridge	143:86740a56073b	481	/* @brief MSCM availability on the SoC. */
AnnaBridge	143:86740a56073b	482	#define FSL_FEATURE_SOC_MSCM_COUNT (0)
AnnaBridge	143:86740a56073b	483	/* @brief MTB availability on the SoC. */
AnnaBridge	143:86740a56073b	484	#define FSL_FEATURE_SOC_MTB_COUNT (0)
AnnaBridge	143:86740a56073b	485	/* @brief MTBDWT availability on the SoC. */
AnnaBridge	143:86740a56073b	486	#define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
AnnaBridge	143:86740a56073b	487	/* @brief MU availability on the SoC. */
AnnaBridge	143:86740a56073b	488	#define FSL_FEATURE_SOC_MU_COUNT (0)
AnnaBridge	143:86740a56073b	489	/* @brief NFC availability on the SoC. */
AnnaBridge	143:86740a56073b	490	#define FSL_FEATURE_SOC_NFC_COUNT (0)
AnnaBridge	143:86740a56073b	491	/* @brief OPAMP availability on the SoC. */
AnnaBridge	143:86740a56073b	492	#define FSL_FEATURE_SOC_OPAMP_COUNT (0)
AnnaBridge	143:86740a56073b	493	/* @brief OSC availability on the SoC. */
AnnaBridge	143:86740a56073b	494	#define FSL_FEATURE_SOC_OSC_COUNT (1)
AnnaBridge	143:86740a56073b	495	/* @brief OSC32 availability on the SoC. */
AnnaBridge	143:86740a56073b	496	#define FSL_FEATURE_SOC_OSC32_COUNT (0)
AnnaBridge	143:86740a56073b	497	/* @brief OTFAD availability on the SoC. */
AnnaBridge	143:86740a56073b	498	#define FSL_FEATURE_SOC_OTFAD_COUNT (0)
AnnaBridge	143:86740a56073b	499	/* @brief PDB availability on the SoC. */
AnnaBridge	143:86740a56073b	500	#define FSL_FEATURE_SOC_PDB_COUNT (1)
AnnaBridge	143:86740a56073b	501	/* @brief PCC availability on the SoC. */
AnnaBridge	143:86740a56073b	502	#define FSL_FEATURE_SOC_PCC_COUNT (0)
AnnaBridge	143:86740a56073b	503	/* @brief PGA availability on the SoC. */
AnnaBridge	143:86740a56073b	504	#define FSL_FEATURE_SOC_PGA_COUNT (0)
AnnaBridge	143:86740a56073b	505	/* @brief PIT availability on the SoC. */
AnnaBridge	143:86740a56073b	506	#define FSL_FEATURE_SOC_PIT_COUNT (1)
AnnaBridge	143:86740a56073b	507	/* @brief PMC availability on the SoC. */
AnnaBridge	143:86740a56073b	508	#define FSL_FEATURE_SOC_PMC_COUNT (1)
AnnaBridge	143:86740a56073b	509	/* @brief PORT availability on the SoC. */
AnnaBridge	143:86740a56073b	510	#define FSL_FEATURE_SOC_PORT_COUNT (5)
AnnaBridge	143:86740a56073b	511	/* @brief PWM availability on the SoC. */
AnnaBridge	143:86740a56073b	512	#define FSL_FEATURE_SOC_PWM_COUNT (0)
AnnaBridge	143:86740a56073b	513	/* @brief PWT availability on the SoC. */
AnnaBridge	143:86740a56073b	514	#define FSL_FEATURE_SOC_PWT_COUNT (0)
AnnaBridge	143:86740a56073b	515	/* @brief QuadSPI availability on the SoC. */
AnnaBridge	143:86740a56073b	516	#define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
AnnaBridge	143:86740a56073b	517	/* @brief RCM availability on the SoC. */
AnnaBridge	143:86740a56073b	518	#define FSL_FEATURE_SOC_RCM_COUNT (1)
AnnaBridge	143:86740a56073b	519	/* @brief RFSYS availability on the SoC. */
AnnaBridge	143:86740a56073b	520	#define FSL_FEATURE_SOC_RFSYS_COUNT (1)
AnnaBridge	143:86740a56073b	521	/* @brief RFVBAT availability on the SoC. */
AnnaBridge	143:86740a56073b	522	#define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
AnnaBridge	143:86740a56073b	523	/* @brief RNG availability on the SoC. */
AnnaBridge	143:86740a56073b	524	#define FSL_FEATURE_SOC_RNG_COUNT (1)
AnnaBridge	143:86740a56073b	525	/* @brief RNGB availability on the SoC. */
AnnaBridge	143:86740a56073b	526	#define FSL_FEATURE_SOC_RNGB_COUNT (0)
AnnaBridge	143:86740a56073b	527	/* @brief ROM availability on the SoC. */
AnnaBridge	143:86740a56073b	528	#define FSL_FEATURE_SOC_ROM_COUNT (0)
AnnaBridge	143:86740a56073b	529	/* @brief RSIM availability on the SoC. */
AnnaBridge	143:86740a56073b	530	#define FSL_FEATURE_SOC_RSIM_COUNT (0)
AnnaBridge	143:86740a56073b	531	/* @brief RTC availability on the SoC. */
AnnaBridge	143:86740a56073b	532	#define FSL_FEATURE_SOC_RTC_COUNT (1)
AnnaBridge	143:86740a56073b	533	/* @brief SCG availability on the SoC. */
AnnaBridge	143:86740a56073b	534	#define FSL_FEATURE_SOC_SCG_COUNT (0)
AnnaBridge	143:86740a56073b	535	/* @brief SCI availability on the SoC. */
AnnaBridge	143:86740a56073b	536	#define FSL_FEATURE_SOC_SCI_COUNT (0)
AnnaBridge	143:86740a56073b	537	/* @brief SDHC availability on the SoC. */
AnnaBridge	143:86740a56073b	538	#define FSL_FEATURE_SOC_SDHC_COUNT (1)
AnnaBridge	143:86740a56073b	539	/* @brief SDRAM availability on the SoC. */
AnnaBridge	143:86740a56073b	540	#define FSL_FEATURE_SOC_SDRAM_COUNT (0)
AnnaBridge	143:86740a56073b	541	/* @brief SEMA42 availability on the SoC. */
AnnaBridge	143:86740a56073b	542	#define FSL_FEATURE_SOC_SEMA42_COUNT (0)
AnnaBridge	143:86740a56073b	543	/* @brief SIM availability on the SoC. */
AnnaBridge	143:86740a56073b	544	#define FSL_FEATURE_SOC_SIM_COUNT (1)
AnnaBridge	143:86740a56073b	545	/* @brief SMC availability on the SoC. */
AnnaBridge	143:86740a56073b	546	#define FSL_FEATURE_SOC_SMC_COUNT (1)
AnnaBridge	143:86740a56073b	547	/* @brief SPI availability on the SoC. */
AnnaBridge	143:86740a56073b	548	#define FSL_FEATURE_SOC_SPI_COUNT (0)
AnnaBridge	143:86740a56073b	549	/* @brief TMR availability on the SoC. */
AnnaBridge	143:86740a56073b	550	#define FSL_FEATURE_SOC_TMR_COUNT (0)
AnnaBridge	143:86740a56073b	551	/* @brief TPM availability on the SoC. */
AnnaBridge	143:86740a56073b	552	#define FSL_FEATURE_SOC_TPM_COUNT (0)
AnnaBridge	143:86740a56073b	553	/* @brief TRGMUX availability on the SoC. */
AnnaBridge	143:86740a56073b	554	#define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
AnnaBridge	143:86740a56073b	555	/* @brief TRIAMP availability on the SoC. */
AnnaBridge	143:86740a56073b	556	#define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
AnnaBridge	143:86740a56073b	557	/* @brief TRNG availability on the SoC. */
AnnaBridge	143:86740a56073b	558	#define FSL_FEATURE_SOC_TRNG_COUNT (0)
AnnaBridge	143:86740a56073b	559	/* @brief TSI availability on the SoC. */
AnnaBridge	143:86740a56073b	560	#define FSL_FEATURE_SOC_TSI_COUNT (0)
AnnaBridge	143:86740a56073b	561	/* @brief TSTMR availability on the SoC. */
AnnaBridge	143:86740a56073b	562	#define FSL_FEATURE_SOC_TSTMR_COUNT (0)
AnnaBridge	143:86740a56073b	563	/* @brief UART availability on the SoC. */
AnnaBridge	143:86740a56073b	564	#define FSL_FEATURE_SOC_UART_COUNT (5)
AnnaBridge	143:86740a56073b	565	/* @brief USB availability on the SoC. */
AnnaBridge	143:86740a56073b	566	#define FSL_FEATURE_SOC_USB_COUNT (1)
AnnaBridge	143:86740a56073b	567	/* @brief USBDCD availability on the SoC. */
AnnaBridge	143:86740a56073b	568	#define FSL_FEATURE_SOC_USBDCD_COUNT (1)
AnnaBridge	143:86740a56073b	569	/* @brief USBHS availability on the SoC. */
AnnaBridge	143:86740a56073b	570	#define FSL_FEATURE_SOC_USBHS_COUNT (0)
AnnaBridge	143:86740a56073b	571	/* @brief USBHSDCD availability on the SoC. */
AnnaBridge	143:86740a56073b	572	#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
AnnaBridge	143:86740a56073b	573	/* @brief USBPHY availability on the SoC. */
AnnaBridge	143:86740a56073b	574	#define FSL_FEATURE_SOC_USBPHY_COUNT (0)
AnnaBridge	143:86740a56073b	575	/* @brief VREF availability on the SoC. */
AnnaBridge	143:86740a56073b	576	#define FSL_FEATURE_SOC_VREF_COUNT (1)
AnnaBridge	143:86740a56073b	577	/* @brief WDOG availability on the SoC. */
AnnaBridge	143:86740a56073b	578	#define FSL_FEATURE_SOC_WDOG_COUNT (1)
AnnaBridge	143:86740a56073b	579	/* @brief XBAR availability on the SoC. */
AnnaBridge	143:86740a56073b	580	#define FSL_FEATURE_SOC_XBAR_COUNT (0)
AnnaBridge	143:86740a56073b	581	/* @brief XBARA availability on the SoC. */
AnnaBridge	143:86740a56073b	582	#define FSL_FEATURE_SOC_XBARA_COUNT (0)
AnnaBridge	143:86740a56073b	583	/* @brief XBARB availability on the SoC. */
AnnaBridge	143:86740a56073b	584	#define FSL_FEATURE_SOC_XBARB_COUNT (0)
AnnaBridge	143:86740a56073b	585	/* @brief XCVR availability on the SoC. */
AnnaBridge	143:86740a56073b	586	#define FSL_FEATURE_SOC_XCVR_COUNT (0)
AnnaBridge	143:86740a56073b	587	/* @brief XRDC availability on the SoC. */
AnnaBridge	143:86740a56073b	588	#define FSL_FEATURE_SOC_XRDC_COUNT (0)
AnnaBridge	143:86740a56073b	589	/* @brief ZLL availability on the SoC. */
AnnaBridge	143:86740a56073b	590	#define FSL_FEATURE_SOC_ZLL_COUNT (0)
AnnaBridge	143:86740a56073b	591	#endif
AnnaBridge	143:86740a56073b	592
AnnaBridge	143:86740a56073b	593	/* ADC16 module features */
AnnaBridge	143:86740a56073b	594
AnnaBridge	143:86740a56073b	595	/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
AnnaBridge	143:86740a56073b	596	#define FSL_FEATURE_ADC16_HAS_PGA (0)
AnnaBridge	143:86740a56073b	597	/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
AnnaBridge	143:86740a56073b	598	#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
AnnaBridge	143:86740a56073b	599	/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
AnnaBridge	143:86740a56073b	600	#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
AnnaBridge	143:86740a56073b	601	/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
AnnaBridge	143:86740a56073b	602	#define FSL_FEATURE_ADC16_HAS_DMA (1)
AnnaBridge	143:86740a56073b	603	/* @brief Has differential mode (bitfield SC1x[DIFF]). */
AnnaBridge	143:86740a56073b	604	#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
AnnaBridge	143:86740a56073b	605	/* @brief Has FIFO (bit SC4[AFDEP]). */
AnnaBridge	143:86740a56073b	606	#define FSL_FEATURE_ADC16_HAS_FIFO (0)
AnnaBridge	143:86740a56073b	607	/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
AnnaBridge	143:86740a56073b	608	#define FSL_FEATURE_ADC16_FIFO_SIZE (0)
AnnaBridge	143:86740a56073b	609	/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
AnnaBridge	143:86740a56073b	610	#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
AnnaBridge	143:86740a56073b	611	/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
AnnaBridge	143:86740a56073b	612	#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
AnnaBridge	143:86740a56073b	613	/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
AnnaBridge	143:86740a56073b	614	#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
AnnaBridge	143:86740a56073b	615	/* @brief Has HW averaging (bit SC3[AVGE]). */
AnnaBridge	143:86740a56073b	616	#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
AnnaBridge	143:86740a56073b	617	/* @brief Has offset correction (register OFS). */
AnnaBridge	143:86740a56073b	618	#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
AnnaBridge	143:86740a56073b	619	/* @brief Maximum ADC resolution. */
AnnaBridge	143:86740a56073b	620	#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
AnnaBridge	143:86740a56073b	621	/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
AnnaBridge	143:86740a56073b	622	#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
AnnaBridge	143:86740a56073b	623
AnnaBridge	143:86740a56073b	624	/* FLEXCAN module features */
AnnaBridge	143:86740a56073b	625
AnnaBridge	143:86740a56073b	626	/* @brief Message buffer size */
AnnaBridge	143:86740a56073b	627	#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (16)
AnnaBridge	143:86740a56073b	628	/* @brief Has doze mode support (register bit field MCR[DOZE]). */
AnnaBridge	143:86740a56073b	629	#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
AnnaBridge	143:86740a56073b	630	/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
AnnaBridge	143:86740a56073b	631	#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
AnnaBridge	143:86740a56073b	632	/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
AnnaBridge	143:86740a56073b	633	#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0)
AnnaBridge	143:86740a56073b	634	/* @brief Has extended bit timing register (register CBT). */
AnnaBridge	143:86740a56073b	635	#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0)
AnnaBridge	143:86740a56073b	636	/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
AnnaBridge	143:86740a56073b	637	#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
AnnaBridge	143:86740a56073b	638	/* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */
AnnaBridge	143:86740a56073b	639	#define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1)
AnnaBridge	143:86740a56073b	640	/* @brief Has bitfield name BUF31TO0M. */
AnnaBridge	143:86740a56073b	641	#define FSL_FEATURE_FLEXCAN_HAS_BUF31TO0M (0)
AnnaBridge	143:86740a56073b	642	/* @brief Number of interrupt vectors. */
AnnaBridge	143:86740a56073b	643	#define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6)
AnnaBridge	143:86740a56073b	644	/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
AnnaBridge	143:86740a56073b	645	#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
AnnaBridge	143:86740a56073b	646
AnnaBridge	143:86740a56073b	647	/* CMP module features */
AnnaBridge	143:86740a56073b	648
AnnaBridge	143:86740a56073b	649	/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
AnnaBridge	143:86740a56073b	650	#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0)
AnnaBridge	143:86740a56073b	651	/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
AnnaBridge	143:86740a56073b	652	#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
AnnaBridge	143:86740a56073b	653	/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
AnnaBridge	143:86740a56073b	654	#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
AnnaBridge	143:86740a56073b	655	/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
AnnaBridge	143:86740a56073b	656	#define FSL_FEATURE_CMP_HAS_DMA (1)
AnnaBridge	143:86740a56073b	657	/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
AnnaBridge	143:86740a56073b	658	#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1)
AnnaBridge	143:86740a56073b	659	/* @brief Has DAC Test function in CMP (register DACTEST). */
AnnaBridge	143:86740a56073b	660	#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
AnnaBridge	143:86740a56073b	661
AnnaBridge	143:86740a56073b	662	/* CRC module features */
AnnaBridge	143:86740a56073b	663
AnnaBridge	143:86740a56073b	664	/* @brief Has data register with name CRC */
AnnaBridge	143:86740a56073b	665	#define FSL_FEATURE_CRC_HAS_CRC_REG (0)
AnnaBridge	143:86740a56073b	666
AnnaBridge	143:86740a56073b	667	/* DAC module features */
AnnaBridge	143:86740a56073b	668
AnnaBridge	143:86740a56073b	669	/* @brief Define the size of hardware buffer */
AnnaBridge	143:86740a56073b	670	#define FSL_FEATURE_DAC_BUFFER_SIZE (16)
AnnaBridge	143:86740a56073b	671	/* @brief Define whether the buffer supports watermark event detection or not. */
AnnaBridge	143:86740a56073b	672	#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
AnnaBridge	143:86740a56073b	673	/* @brief Define whether the buffer supports watermark selection detection or not. */
AnnaBridge	143:86740a56073b	674	#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
AnnaBridge	143:86740a56073b	675	/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
AnnaBridge	143:86740a56073b	676	#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
AnnaBridge	143:86740a56073b	677	/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
AnnaBridge	143:86740a56073b	678	#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
AnnaBridge	143:86740a56073b	679	/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
AnnaBridge	143:86740a56073b	680	#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
AnnaBridge	143:86740a56073b	681	/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
AnnaBridge	143:86740a56073b	682	#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
AnnaBridge	143:86740a56073b	683	/* @brief Define whether FIFO buffer mode is available or not. */
AnnaBridge	143:86740a56073b	684	#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0)
AnnaBridge	143:86740a56073b	685	/* @brief Define whether swing buffer mode is available or not.. */
AnnaBridge	143:86740a56073b	686	#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1)
AnnaBridge	143:86740a56073b	687
AnnaBridge	143:86740a56073b	688	/* EDMA module features */
AnnaBridge	143:86740a56073b	689
AnnaBridge	143:86740a56073b	690	/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
AnnaBridge	143:86740a56073b	691	#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16)
AnnaBridge	143:86740a56073b	692	/* @brief Total number of DMA channels on all modules. */
AnnaBridge	143:86740a56073b	693	#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 16)
AnnaBridge	143:86740a56073b	694	/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
AnnaBridge	143:86740a56073b	695	#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
AnnaBridge	143:86740a56073b	696	/* @brief Has DMA_Error interrupt vector. */
AnnaBridge	143:86740a56073b	697	#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
AnnaBridge	143:86740a56073b	698	/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
AnnaBridge	143:86740a56073b	699	#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
AnnaBridge	143:86740a56073b	700
AnnaBridge	143:86740a56073b	701	/* DMAMUX module features */
AnnaBridge	143:86740a56073b	702
AnnaBridge	143:86740a56073b	703	/* @brief Number of DMA channels (related to number of register CHCFGn). */
AnnaBridge	143:86740a56073b	704	#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16)
AnnaBridge	143:86740a56073b	705	/* @brief Total number of DMA channels on all modules. */
AnnaBridge	143:86740a56073b	706	#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 16)
AnnaBridge	143:86740a56073b	707	/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
AnnaBridge	143:86740a56073b	708	#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
AnnaBridge	143:86740a56073b	709
AnnaBridge	143:86740a56073b	710	/* EWM module features */
AnnaBridge	143:86740a56073b	711
AnnaBridge	143:86740a56073b	712	/* @brief Has clock select (register CLKCTRL). */
AnnaBridge	143:86740a56073b	713	#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0)
AnnaBridge	143:86740a56073b	714	/* @brief Has clock prescaler (register CLKPRESCALER). */
AnnaBridge	143:86740a56073b	715	#define FSL_FEATURE_EWM_HAS_PRESCALER (0)
AnnaBridge	143:86740a56073b	716
AnnaBridge	143:86740a56073b	717	/* FLEXBUS module features */
AnnaBridge	143:86740a56073b	718
AnnaBridge	143:86740a56073b	719	/* No feature definitions */
AnnaBridge	143:86740a56073b	720
AnnaBridge	143:86740a56073b	721	/* FLASH module features */
AnnaBridge	143:86740a56073b	722
AnnaBridge	143:86740a56073b	723	/* @brief Is of type FTFA. */
AnnaBridge	143:86740a56073b	724	#define FSL_FEATURE_FLASH_IS_FTFA (0)
AnnaBridge	143:86740a56073b	725	/* @brief Is of type FTFE. */
AnnaBridge	143:86740a56073b	726	#define FSL_FEATURE_FLASH_IS_FTFE (1)
AnnaBridge	143:86740a56073b	727	/* @brief Is of type FTFL. */
AnnaBridge	143:86740a56073b	728	#define FSL_FEATURE_FLASH_IS_FTFL (0)
AnnaBridge	143:86740a56073b	729	/* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
AnnaBridge	143:86740a56073b	730	#define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
AnnaBridge	143:86740a56073b	731	/* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
AnnaBridge	143:86740a56073b	732	#define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
AnnaBridge	143:86740a56073b	733	/* @brief Has EEPROM region protection (register FEPROT). */
AnnaBridge	143:86740a56073b	734	#define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
AnnaBridge	143:86740a56073b	735	/* @brief Has data flash region protection (register FDPROT). */
AnnaBridge	143:86740a56073b	736	#define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
AnnaBridge	143:86740a56073b	737	/* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
AnnaBridge	143:86740a56073b	738	#define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
AnnaBridge	143:86740a56073b	739	/* @brief Has flash cache control in FMC module. */
AnnaBridge	143:86740a56073b	740	#define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
AnnaBridge	143:86740a56073b	741	/* @brief Has flash cache control in MCM module. */
AnnaBridge	143:86740a56073b	742	#define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
AnnaBridge	143:86740a56073b	743	/* @brief Has flash cache control in MSCM module. */
AnnaBridge	143:86740a56073b	744	#define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
AnnaBridge	143:86740a56073b	745	/* @brief Has prefetch speculation control in flash, such as kv5x. */
AnnaBridge	143:86740a56073b	746	#define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
AnnaBridge	143:86740a56073b	747	/* @brief P-Flash start address. */
AnnaBridge	143:86740a56073b	748	#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
AnnaBridge	143:86740a56073b	749	/* @brief P-Flash block count. */
AnnaBridge	143:86740a56073b	750	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
AnnaBridge	143:86740a56073b	751	/* @brief P-Flash block size. */
AnnaBridge	143:86740a56073b	752	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
AnnaBridge	143:86740a56073b	753	/* @brief P-Flash sector size. */
AnnaBridge	143:86740a56073b	754	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096)
AnnaBridge	143:86740a56073b	755	/* @brief P-Flash write unit size. */
AnnaBridge	143:86740a56073b	756	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
AnnaBridge	143:86740a56073b	757	/* @brief P-Flash data path width. */
AnnaBridge	143:86740a56073b	758	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
AnnaBridge	143:86740a56073b	759	/* @brief P-Flash block swap feature. */
AnnaBridge	143:86740a56073b	760	#define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1)
AnnaBridge	143:86740a56073b	761	/* @brief P-Flash protection region count. */
AnnaBridge	143:86740a56073b	762	#define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
AnnaBridge	143:86740a56073b	763	/* @brief Has FlexNVM memory. */
AnnaBridge	143:86740a56073b	764	#define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
AnnaBridge	143:86740a56073b	765	/* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
AnnaBridge	143:86740a56073b	766	#define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
AnnaBridge	143:86740a56073b	767	/* @brief FlexNVM block count. */
AnnaBridge	143:86740a56073b	768	#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
AnnaBridge	143:86740a56073b	769	/* @brief FlexNVM block size. */
AnnaBridge	143:86740a56073b	770	#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
AnnaBridge	143:86740a56073b	771	/* @brief FlexNVM sector size. */
AnnaBridge	143:86740a56073b	772	#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
AnnaBridge	143:86740a56073b	773	/* @brief FlexNVM write unit size. */
AnnaBridge	143:86740a56073b	774	#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
AnnaBridge	143:86740a56073b	775	/* @brief FlexNVM data path width. */
AnnaBridge	143:86740a56073b	776	#define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
AnnaBridge	143:86740a56073b	777	/* @brief Has FlexRAM memory. */
AnnaBridge	143:86740a56073b	778	#define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
AnnaBridge	143:86740a56073b	779	/* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
AnnaBridge	143:86740a56073b	780	#define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
AnnaBridge	143:86740a56073b	781	/* @brief FlexRAM size. */
AnnaBridge	143:86740a56073b	782	#define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
AnnaBridge	143:86740a56073b	783	/* @brief Has 0x00 Read 1s Block command. */
AnnaBridge	143:86740a56073b	784	#define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
AnnaBridge	143:86740a56073b	785	/* @brief Has 0x01 Read 1s Section command. */
AnnaBridge	143:86740a56073b	786	#define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
AnnaBridge	143:86740a56073b	787	/* @brief Has 0x02 Program Check command. */
AnnaBridge	143:86740a56073b	788	#define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
AnnaBridge	143:86740a56073b	789	/* @brief Has 0x03 Read Resource command. */
AnnaBridge	143:86740a56073b	790	#define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
AnnaBridge	143:86740a56073b	791	/* @brief Has 0x06 Program Longword command. */
AnnaBridge	143:86740a56073b	792	#define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
AnnaBridge	143:86740a56073b	793	/* @brief Has 0x07 Program Phrase command. */
AnnaBridge	143:86740a56073b	794	#define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
AnnaBridge	143:86740a56073b	795	/* @brief Has 0x08 Erase Flash Block command. */
AnnaBridge	143:86740a56073b	796	#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
AnnaBridge	143:86740a56073b	797	/* @brief Has 0x09 Erase Flash Sector command. */
AnnaBridge	143:86740a56073b	798	#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
AnnaBridge	143:86740a56073b	799	/* @brief Has 0x0B Program Section command. */
AnnaBridge	143:86740a56073b	800	#define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
AnnaBridge	143:86740a56073b	801	/* @brief Has 0x40 Read 1s All Blocks command. */
AnnaBridge	143:86740a56073b	802	#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
AnnaBridge	143:86740a56073b	803	/* @brief Has 0x41 Read Once command. */
AnnaBridge	143:86740a56073b	804	#define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
AnnaBridge	143:86740a56073b	805	/* @brief Has 0x43 Program Once command. */
AnnaBridge	143:86740a56073b	806	#define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
AnnaBridge	143:86740a56073b	807	/* @brief Has 0x44 Erase All Blocks command. */
AnnaBridge	143:86740a56073b	808	#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
AnnaBridge	143:86740a56073b	809	/* @brief Has 0x45 Verify Backdoor Access Key command. */
AnnaBridge	143:86740a56073b	810	#define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
AnnaBridge	143:86740a56073b	811	/* @brief Has 0x46 Swap Control command. */
AnnaBridge	143:86740a56073b	812	#define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1)
AnnaBridge	143:86740a56073b	813	/* @brief Has 0x49 Erase All Blocks Unsecure command. */
AnnaBridge	143:86740a56073b	814	#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
AnnaBridge	143:86740a56073b	815	/* @brief Has 0x4A Read 1s All Execute-only Segments command. */
AnnaBridge	143:86740a56073b	816	#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
AnnaBridge	143:86740a56073b	817	/* @brief Has 0x4B Erase All Execute-only Segments command. */
AnnaBridge	143:86740a56073b	818	#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
AnnaBridge	143:86740a56073b	819	/* @brief Has 0x80 Program Partition command. */
AnnaBridge	143:86740a56073b	820	#define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
AnnaBridge	143:86740a56073b	821	/* @brief Has 0x81 Set FlexRAM Function command. */
AnnaBridge	143:86740a56073b	822	#define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
AnnaBridge	143:86740a56073b	823	/* @brief P-Flash Erase/Read 1st all block command address alignment. */
AnnaBridge	143:86740a56073b	824	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
AnnaBridge	143:86740a56073b	825	/* @brief P-Flash Erase sector command address alignment. */
AnnaBridge	143:86740a56073b	826	#define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16)
AnnaBridge	143:86740a56073b	827	/* @brief P-Flash Rrogram/Verify section command address alignment. */
AnnaBridge	143:86740a56073b	828	#define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16)
AnnaBridge	143:86740a56073b	829	/* @brief P-Flash Read resource command address alignment. */
AnnaBridge	143:86740a56073b	830	#define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
AnnaBridge	143:86740a56073b	831	/* @brief P-Flash Program check command address alignment. */
AnnaBridge	143:86740a56073b	832	#define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
AnnaBridge	143:86740a56073b	833	/* @brief P-Flash Program check command address alignment. */
AnnaBridge	143:86740a56073b	834	#define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16)
AnnaBridge	143:86740a56073b	835	/* @brief FlexNVM Erase/Read 1st all block command address alignment. */
AnnaBridge	143:86740a56073b	836	#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge	143:86740a56073b	837	/* @brief FlexNVM Erase sector command address alignment. */
AnnaBridge	143:86740a56073b	838	#define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge	143:86740a56073b	839	/* @brief FlexNVM Rrogram/Verify section command address alignment. */
AnnaBridge	143:86740a56073b	840	#define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge	143:86740a56073b	841	/* @brief FlexNVM Read resource command address alignment. */
AnnaBridge	143:86740a56073b	842	#define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge	143:86740a56073b	843	/* @brief FlexNVM Program check command address alignment. */
AnnaBridge	143:86740a56073b	844	#define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge	143:86740a56073b	845	/* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	143:86740a56073b	846	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
AnnaBridge	143:86740a56073b	847	/* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	143:86740a56073b	848	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
AnnaBridge	143:86740a56073b	849	/* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	143:86740a56073b	850	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
AnnaBridge	143:86740a56073b	851	/* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	143:86740a56073b	852	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
AnnaBridge	143:86740a56073b	853	/* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	143:86740a56073b	854	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
AnnaBridge	143:86740a56073b	855	/* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	143:86740a56073b	856	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
AnnaBridge	143:86740a56073b	857	/* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	143:86740a56073b	858	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
AnnaBridge	143:86740a56073b	859	/* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	143:86740a56073b	860	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
AnnaBridge	143:86740a56073b	861	/* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	143:86740a56073b	862	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
AnnaBridge	143:86740a56073b	863	/* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	143:86740a56073b	864	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
AnnaBridge	143:86740a56073b	865	/* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	143:86740a56073b	866	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
AnnaBridge	143:86740a56073b	867	/* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	143:86740a56073b	868	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
AnnaBridge	143:86740a56073b	869	/* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	143:86740a56073b	870	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
AnnaBridge	143:86740a56073b	871	/* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	143:86740a56073b	872	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
AnnaBridge	143:86740a56073b	873	/* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	143:86740a56073b	874	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
AnnaBridge	143:86740a56073b	875	/* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	143:86740a56073b	876	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
AnnaBridge	143:86740a56073b	877	/* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	143:86740a56073b	878	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
AnnaBridge	143:86740a56073b	879	/* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	143:86740a56073b	880	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
AnnaBridge	143:86740a56073b	881	/* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	143:86740a56073b	882	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
AnnaBridge	143:86740a56073b	883	/* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	143:86740a56073b	884	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
AnnaBridge	143:86740a56073b	885	/* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	143:86740a56073b	886	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
AnnaBridge	143:86740a56073b	887	/* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	143:86740a56073b	888	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
AnnaBridge	143:86740a56073b	889	/* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	143:86740a56073b	890	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
AnnaBridge	143:86740a56073b	891	/* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	143:86740a56073b	892	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
AnnaBridge	143:86740a56073b	893	/* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	143:86740a56073b	894	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
AnnaBridge	143:86740a56073b	895	/* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	143:86740a56073b	896	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
AnnaBridge	143:86740a56073b	897	/* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	143:86740a56073b	898	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
AnnaBridge	143:86740a56073b	899	/* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	143:86740a56073b	900	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
AnnaBridge	143:86740a56073b	901	/* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	143:86740a56073b	902	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
AnnaBridge	143:86740a56073b	903	/* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	143:86740a56073b	904	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
AnnaBridge	143:86740a56073b	905	/* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	143:86740a56073b	906	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
AnnaBridge	143:86740a56073b	907	/* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	143:86740a56073b	908	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
AnnaBridge	143:86740a56073b	909
AnnaBridge	143:86740a56073b	910	/* FTM module features */
AnnaBridge	143:86740a56073b	911
AnnaBridge	143:86740a56073b	912	/* @brief Number of channels. */
AnnaBridge	143:86740a56073b	913	#define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
AnnaBridge	143:86740a56073b	914	((x) == FTM0 ? (8) : \
AnnaBridge	143:86740a56073b	915	((x) == FTM1 ? (2) : \
AnnaBridge	143:86740a56073b	916	((x) == FTM2 ? (2) : \
AnnaBridge	143:86740a56073b	917	((x) == FTM3 ? (8) : (-1)))))
AnnaBridge	143:86740a56073b	918	/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
AnnaBridge	143:86740a56073b	919	#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
AnnaBridge	143:86740a56073b	920	/* @brief Has extended deadtime value. */
AnnaBridge	143:86740a56073b	921	#define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0)
AnnaBridge	143:86740a56073b	922	/* @brief Enable pwm output for the module. */
AnnaBridge	143:86740a56073b	923	#define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0)
AnnaBridge	143:86740a56073b	924	/* @brief Has half-cycle reload for the module. */
AnnaBridge	143:86740a56073b	925	#define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0)
AnnaBridge	143:86740a56073b	926	/* @brief Has reload interrupt. */
AnnaBridge	143:86740a56073b	927	#define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0)
AnnaBridge	143:86740a56073b	928	/* @brief Has reload initialization trigger. */
AnnaBridge	143:86740a56073b	929	#define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0)
AnnaBridge	143:86740a56073b	930
AnnaBridge	143:86740a56073b	931	/* GPIO module features */
AnnaBridge	143:86740a56073b	932
AnnaBridge	143:86740a56073b	933	/* @brief Has fast (single cycle) access capability via a dedicated memory region. */
AnnaBridge	143:86740a56073b	934	#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
AnnaBridge	143:86740a56073b	935	/* @brief Has port input disable register (PIDR). */
AnnaBridge	143:86740a56073b	936	#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
AnnaBridge	143:86740a56073b	937	/* @brief Has dedicated interrupt vector. */
AnnaBridge	143:86740a56073b	938	#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1)
AnnaBridge	143:86740a56073b	939
AnnaBridge	143:86740a56073b	940	/* I2C module features */
AnnaBridge	143:86740a56073b	941
AnnaBridge	143:86740a56073b	942	/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
AnnaBridge	143:86740a56073b	943	#define FSL_FEATURE_I2C_HAS_SMBUS (1)
AnnaBridge	143:86740a56073b	944	/* @brief Maximum supported baud rate in kilobit per second. */
AnnaBridge	143:86740a56073b	945	#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
AnnaBridge	143:86740a56073b	946	/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
AnnaBridge	143:86740a56073b	947	#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
AnnaBridge	143:86740a56073b	948	/* @brief Has DMA support (register bit C1[DMAEN]). */
AnnaBridge	143:86740a56073b	949	#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
AnnaBridge	143:86740a56073b	950	/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
AnnaBridge	143:86740a56073b	951	#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
AnnaBridge	143:86740a56073b	952	/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
AnnaBridge	143:86740a56073b	953	#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
AnnaBridge	143:86740a56073b	954	/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
AnnaBridge	143:86740a56073b	955	#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
AnnaBridge	143:86740a56073b	956	/* @brief Maximum width of the glitch filter in number of bus clocks. */
AnnaBridge	143:86740a56073b	957	#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
AnnaBridge	143:86740a56073b	958	/* @brief Has control of the drive capability of the I2C pins. */
AnnaBridge	143:86740a56073b	959	#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
AnnaBridge	143:86740a56073b	960	/* @brief Has double buffering support (register S2). */
AnnaBridge	143:86740a56073b	961	#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
AnnaBridge	143:86740a56073b	962	/* @brief Has double buffer enable. */
AnnaBridge	143:86740a56073b	963	#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0)
AnnaBridge	143:86740a56073b	964
AnnaBridge	143:86740a56073b	965	/* SAI module features */
AnnaBridge	143:86740a56073b	966
AnnaBridge	143:86740a56073b	967	/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
AnnaBridge	143:86740a56073b	968	#define FSL_FEATURE_SAI_FIFO_COUNT (8)
AnnaBridge	143:86740a56073b	969	/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
AnnaBridge	143:86740a56073b	970	#define FSL_FEATURE_SAI_CHANNEL_COUNT (2)
AnnaBridge	143:86740a56073b	971	/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
AnnaBridge	143:86740a56073b	972	#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
AnnaBridge	143:86740a56073b	973	/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
AnnaBridge	143:86740a56073b	974	#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0)
AnnaBridge	143:86740a56073b	975	/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
AnnaBridge	143:86740a56073b	976	#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0)
AnnaBridge	143:86740a56073b	977	/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
AnnaBridge	143:86740a56073b	978	#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0)
AnnaBridge	143:86740a56073b	979	/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
AnnaBridge	143:86740a56073b	980	#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0)
AnnaBridge	143:86740a56073b	981	/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
AnnaBridge	143:86740a56073b	982	#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
AnnaBridge	143:86740a56073b	983	/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
AnnaBridge	143:86740a56073b	984	#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1)
AnnaBridge	143:86740a56073b	985	/* @brief Ihe interrupt source number */
AnnaBridge	143:86740a56073b	986	#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
AnnaBridge	143:86740a56073b	987	/* @brief Has register of MCR. */
AnnaBridge	143:86740a56073b	988	#define FSL_FEATURE_SAI_HAS_MCR (1)
AnnaBridge	143:86740a56073b	989	/* @brief Has register of MDR */
AnnaBridge	143:86740a56073b	990	#define FSL_FEATURE_SAI_HAS_MDR (1)
AnnaBridge	143:86740a56073b	991
AnnaBridge	143:86740a56073b	992	/* LLWU module features */
AnnaBridge	143:86740a56073b	993
AnnaBridge	143:86740a56073b	994	/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
AnnaBridge	143:86740a56073b	995	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
AnnaBridge	143:86740a56073b	996	/* @brief Has pins 8-15 connected to LLWU device. */
AnnaBridge	143:86740a56073b	997	#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
AnnaBridge	143:86740a56073b	998	/* @brief Maximum number of internal modules connected to LLWU device. */
AnnaBridge	143:86740a56073b	999	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
AnnaBridge	143:86740a56073b	1000	/* @brief Number of digital filters. */
AnnaBridge	143:86740a56073b	1001	#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
AnnaBridge	143:86740a56073b	1002	/* @brief Has MF register. */
AnnaBridge	143:86740a56073b	1003	#define FSL_FEATURE_LLWU_HAS_MF (0)
AnnaBridge	143:86740a56073b	1004	/* @brief Has PF register. */
AnnaBridge	143:86740a56073b	1005	#define FSL_FEATURE_LLWU_HAS_PF (0)
AnnaBridge	143:86740a56073b	1006	/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
AnnaBridge	143:86740a56073b	1007	#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1)
AnnaBridge	143:86740a56073b	1008	/* @brief Has no internal module wakeup flag register. */
AnnaBridge	143:86740a56073b	1009	#define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
AnnaBridge	143:86740a56073b	1010	/* @brief Has external pin 0 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1011	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
AnnaBridge	143:86740a56073b	1012	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1013	#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
AnnaBridge	143:86740a56073b	1014	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1015	#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
AnnaBridge	143:86740a56073b	1016	/* @brief Has external pin 1 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1017	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
AnnaBridge	143:86740a56073b	1018	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1019	#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
AnnaBridge	143:86740a56073b	1020	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1021	#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
AnnaBridge	143:86740a56073b	1022	/* @brief Has external pin 2 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1023	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
AnnaBridge	143:86740a56073b	1024	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1025	#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
AnnaBridge	143:86740a56073b	1026	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1027	#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
AnnaBridge	143:86740a56073b	1028	/* @brief Has external pin 3 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1029	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
AnnaBridge	143:86740a56073b	1030	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1031	#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
AnnaBridge	143:86740a56073b	1032	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1033	#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
AnnaBridge	143:86740a56073b	1034	/* @brief Has external pin 4 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1035	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
AnnaBridge	143:86740a56073b	1036	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1037	#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
AnnaBridge	143:86740a56073b	1038	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1039	#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
AnnaBridge	143:86740a56073b	1040	/* @brief Has external pin 5 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1041	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
AnnaBridge	143:86740a56073b	1042	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1043	#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
AnnaBridge	143:86740a56073b	1044	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1045	#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
AnnaBridge	143:86740a56073b	1046	/* @brief Has external pin 6 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1047	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
AnnaBridge	143:86740a56073b	1048	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1049	#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
AnnaBridge	143:86740a56073b	1050	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1051	#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
AnnaBridge	143:86740a56073b	1052	/* @brief Has external pin 7 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1053	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
AnnaBridge	143:86740a56073b	1054	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1055	#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
AnnaBridge	143:86740a56073b	1056	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1057	#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
AnnaBridge	143:86740a56073b	1058	/* @brief Has external pin 8 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1059	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
AnnaBridge	143:86740a56073b	1060	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1061	#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
AnnaBridge	143:86740a56073b	1062	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1063	#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
AnnaBridge	143:86740a56073b	1064	/* @brief Has external pin 9 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1065	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
AnnaBridge	143:86740a56073b	1066	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1067	#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
AnnaBridge	143:86740a56073b	1068	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1069	#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
AnnaBridge	143:86740a56073b	1070	/* @brief Has external pin 10 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1071	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
AnnaBridge	143:86740a56073b	1072	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1073	#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
AnnaBridge	143:86740a56073b	1074	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1075	#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
AnnaBridge	143:86740a56073b	1076	/* @brief Has external pin 11 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1077	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
AnnaBridge	143:86740a56073b	1078	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1079	#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
AnnaBridge	143:86740a56073b	1080	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1081	#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
AnnaBridge	143:86740a56073b	1082	/* @brief Has external pin 12 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1083	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
AnnaBridge	143:86740a56073b	1084	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1085	#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
AnnaBridge	143:86740a56073b	1086	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1087	#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
AnnaBridge	143:86740a56073b	1088	/* @brief Has external pin 13 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1089	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
AnnaBridge	143:86740a56073b	1090	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1091	#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
AnnaBridge	143:86740a56073b	1092	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1093	#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
AnnaBridge	143:86740a56073b	1094	/* @brief Has external pin 14 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1095	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
AnnaBridge	143:86740a56073b	1096	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1097	#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
AnnaBridge	143:86740a56073b	1098	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1099	#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
AnnaBridge	143:86740a56073b	1100	/* @brief Has external pin 15 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1101	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
AnnaBridge	143:86740a56073b	1102	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1103	#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
AnnaBridge	143:86740a56073b	1104	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1105	#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
AnnaBridge	143:86740a56073b	1106	/* @brief Has external pin 16 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1107	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
AnnaBridge	143:86740a56073b	1108	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1109	#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
AnnaBridge	143:86740a56073b	1110	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1111	#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
AnnaBridge	143:86740a56073b	1112	/* @brief Has external pin 17 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1113	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
AnnaBridge	143:86740a56073b	1114	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1115	#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
AnnaBridge	143:86740a56073b	1116	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1117	#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
AnnaBridge	143:86740a56073b	1118	/* @brief Has external pin 18 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1119	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
AnnaBridge	143:86740a56073b	1120	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1121	#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
AnnaBridge	143:86740a56073b	1122	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1123	#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
AnnaBridge	143:86740a56073b	1124	/* @brief Has external pin 19 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1125	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
AnnaBridge	143:86740a56073b	1126	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1127	#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
AnnaBridge	143:86740a56073b	1128	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1129	#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
AnnaBridge	143:86740a56073b	1130	/* @brief Has external pin 20 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1131	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
AnnaBridge	143:86740a56073b	1132	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1133	#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
AnnaBridge	143:86740a56073b	1134	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1135	#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
AnnaBridge	143:86740a56073b	1136	/* @brief Has external pin 21 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1137	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
AnnaBridge	143:86740a56073b	1138	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1139	#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
AnnaBridge	143:86740a56073b	1140	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1141	#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
AnnaBridge	143:86740a56073b	1142	/* @brief Has external pin 22 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1143	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
AnnaBridge	143:86740a56073b	1144	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1145	#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
AnnaBridge	143:86740a56073b	1146	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1147	#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
AnnaBridge	143:86740a56073b	1148	/* @brief Has external pin 23 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1149	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
AnnaBridge	143:86740a56073b	1150	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1151	#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
AnnaBridge	143:86740a56073b	1152	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1153	#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
AnnaBridge	143:86740a56073b	1154	/* @brief Has external pin 24 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1155	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
AnnaBridge	143:86740a56073b	1156	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1157	#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
AnnaBridge	143:86740a56073b	1158	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1159	#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
AnnaBridge	143:86740a56073b	1160	/* @brief Has external pin 25 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1161	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
AnnaBridge	143:86740a56073b	1162	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1163	#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
AnnaBridge	143:86740a56073b	1164	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1165	#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
AnnaBridge	143:86740a56073b	1166	/* @brief Has external pin 26 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1167	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
AnnaBridge	143:86740a56073b	1168	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1169	#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
AnnaBridge	143:86740a56073b	1170	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1171	#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
AnnaBridge	143:86740a56073b	1172	/* @brief Has external pin 27 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1173	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
AnnaBridge	143:86740a56073b	1174	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1175	#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
AnnaBridge	143:86740a56073b	1176	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1177	#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
AnnaBridge	143:86740a56073b	1178	/* @brief Has external pin 28 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1179	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
AnnaBridge	143:86740a56073b	1180	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1181	#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
AnnaBridge	143:86740a56073b	1182	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1183	#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
AnnaBridge	143:86740a56073b	1184	/* @brief Has external pin 29 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1185	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
AnnaBridge	143:86740a56073b	1186	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1187	#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
AnnaBridge	143:86740a56073b	1188	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1189	#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
AnnaBridge	143:86740a56073b	1190	/* @brief Has external pin 30 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1191	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
AnnaBridge	143:86740a56073b	1192	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1193	#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
AnnaBridge	143:86740a56073b	1194	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1195	#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
AnnaBridge	143:86740a56073b	1196	/* @brief Has external pin 31 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1197	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
AnnaBridge	143:86740a56073b	1198	/* @brief Index of port of external pin. */
AnnaBridge	143:86740a56073b	1199	#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
AnnaBridge	143:86740a56073b	1200	/* @brief Number of external pin port on specified port. */
AnnaBridge	143:86740a56073b	1201	#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
AnnaBridge	143:86740a56073b	1202	/* @brief Has internal module 0 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1203	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
AnnaBridge	143:86740a56073b	1204	/* @brief Has internal module 1 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1205	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
AnnaBridge	143:86740a56073b	1206	/* @brief Has internal module 2 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1207	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
AnnaBridge	143:86740a56073b	1208	/* @brief Has internal module 3 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1209	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
AnnaBridge	143:86740a56073b	1210	/* @brief Has internal module 4 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1211	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0)
AnnaBridge	143:86740a56073b	1212	/* @brief Has internal module 5 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1213	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
AnnaBridge	143:86740a56073b	1214	/* @brief Has internal module 6 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1215	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
AnnaBridge	143:86740a56073b	1216	/* @brief Has internal module 7 connected to LLWU device. */
AnnaBridge	143:86740a56073b	1217	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
AnnaBridge	143:86740a56073b	1218	/* @brief Has Version ID Register (LLWU_VERID). */
AnnaBridge	143:86740a56073b	1219	#define FSL_FEATURE_LLWU_HAS_VERID (0)
AnnaBridge	143:86740a56073b	1220	/* @brief Has Parameter Register (LLWU_PARAM). */
AnnaBridge	143:86740a56073b	1221	#define FSL_FEATURE_LLWU_HAS_PARAM (0)
AnnaBridge	143:86740a56073b	1222	/* @brief Width of registers of the LLWU. */
AnnaBridge	143:86740a56073b	1223	#define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
AnnaBridge	143:86740a56073b	1224	/* @brief Has DMA Enable register (LLWU_DE). */
AnnaBridge	143:86740a56073b	1225	#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
AnnaBridge	143:86740a56073b	1226
AnnaBridge	143:86740a56073b	1227	/* LPTMR module features */
AnnaBridge	143:86740a56073b	1228
AnnaBridge	143:86740a56073b	1229	/* @brief Has shared interrupt handler with another LPTMR module. */
AnnaBridge	143:86740a56073b	1230	#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
AnnaBridge	143:86740a56073b	1231	/* @brief Whether LPTMR counter is 32 bits width. */
AnnaBridge	143:86740a56073b	1232	#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0)
AnnaBridge	143:86740a56073b	1233	/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
AnnaBridge	143:86740a56073b	1234	#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0)
AnnaBridge	143:86740a56073b	1235
AnnaBridge	143:86740a56073b	1236	/* MCG module features */
AnnaBridge	143:86740a56073b	1237
AnnaBridge	143:86740a56073b	1238	/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
AnnaBridge	143:86740a56073b	1239	#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1)
AnnaBridge	143:86740a56073b	1240	/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
AnnaBridge	143:86740a56073b	1241	#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24)
AnnaBridge	143:86740a56073b	1242	/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
AnnaBridge	143:86740a56073b	1243	#define FSL_FEATURE_MCG_PLL_VDIV_BASE (24)
AnnaBridge	143:86740a56073b	1244	/* @brief PLL reference clock low range. OSCCLK/PLL_R. */
AnnaBridge	143:86740a56073b	1245	#define FSL_FEATURE_MCG_PLL_REF_MIN (2000000)
AnnaBridge	143:86740a56073b	1246	/* @brief PLL reference clock high range. OSCCLK/PLL_R. */
AnnaBridge	143:86740a56073b	1247	#define FSL_FEATURE_MCG_PLL_REF_MAX (4000000)
AnnaBridge	143:86740a56073b	1248	/* @brief The PLL clock is divided by 2 before VCO divider. */
AnnaBridge	143:86740a56073b	1249	#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0)
AnnaBridge	143:86740a56073b	1250	/* @brief FRDIV supports 1280. */
AnnaBridge	143:86740a56073b	1251	#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
AnnaBridge	143:86740a56073b	1252	/* @brief FRDIV supports 1536. */
AnnaBridge	143:86740a56073b	1253	#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
AnnaBridge	143:86740a56073b	1254	/* @brief MCGFFCLK divider. */
AnnaBridge	143:86740a56073b	1255	#define FSL_FEATURE_MCG_FFCLK_DIV (1)
AnnaBridge	143:86740a56073b	1256	/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
AnnaBridge	143:86740a56073b	1257	#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
AnnaBridge	143:86740a56073b	1258	/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
AnnaBridge	143:86740a56073b	1259	#define FSL_FEATURE_MCG_HAS_RTC_32K (1)
AnnaBridge	143:86740a56073b	1260	/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
AnnaBridge	143:86740a56073b	1261	#define FSL_FEATURE_MCG_HAS_PLL1 (0)
AnnaBridge	143:86740a56073b	1262	/* @brief Has 48MHz internal oscillator. */
AnnaBridge	143:86740a56073b	1263	#define FSL_FEATURE_MCG_HAS_IRC_48M (1)
AnnaBridge	143:86740a56073b	1264	/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
AnnaBridge	143:86740a56073b	1265	#define FSL_FEATURE_MCG_HAS_OSC1 (0)
AnnaBridge	143:86740a56073b	1266	/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
AnnaBridge	143:86740a56073b	1267	#define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
AnnaBridge	143:86740a56073b	1268	/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
AnnaBridge	143:86740a56073b	1269	#define FSL_FEATURE_MCG_HAS_LOLRE (1)
AnnaBridge	143:86740a56073b	1270	/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
AnnaBridge	143:86740a56073b	1271	#define FSL_FEATURE_MCG_USE_OSCSEL (1)
AnnaBridge	143:86740a56073b	1272	/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
AnnaBridge	143:86740a56073b	1273	#define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
AnnaBridge	143:86740a56073b	1274	/* @brief TBD */
AnnaBridge	143:86740a56073b	1275	#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
AnnaBridge	143:86740a56073b	1276	/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */
AnnaBridge	143:86740a56073b	1277	#define FSL_FEATURE_MCG_HAS_PLL (1)
AnnaBridge	143:86740a56073b	1278	/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
AnnaBridge	143:86740a56073b	1279	#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1)
AnnaBridge	143:86740a56073b	1280	/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
AnnaBridge	143:86740a56073b	1281	#define FSL_FEATURE_MCG_HAS_PLL_VDIV (1)
AnnaBridge	143:86740a56073b	1282	/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
AnnaBridge	143:86740a56073b	1283	#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
AnnaBridge	143:86740a56073b	1284	/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
AnnaBridge	143:86740a56073b	1285	#define FSL_FEATURE_MCG_HAS_FLL (1)
AnnaBridge	143:86740a56073b	1286	/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
AnnaBridge	143:86740a56073b	1287	#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
AnnaBridge	143:86740a56073b	1288	/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
AnnaBridge	143:86740a56073b	1289	#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
AnnaBridge	143:86740a56073b	1290	/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
AnnaBridge	143:86740a56073b	1291	#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
AnnaBridge	143:86740a56073b	1292	/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
AnnaBridge	143:86740a56073b	1293	#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
AnnaBridge	143:86740a56073b	1294	/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
AnnaBridge	143:86740a56073b	1295	#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
AnnaBridge	143:86740a56073b	1296	/* @brief Has external clock monitor (register bit C6[CME]). */
AnnaBridge	143:86740a56073b	1297	#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
AnnaBridge	143:86740a56073b	1298	/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
AnnaBridge	143:86740a56073b	1299	#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
AnnaBridge	143:86740a56073b	1300	/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
AnnaBridge	143:86740a56073b	1301	#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
AnnaBridge	143:86740a56073b	1302	/* @brief Has PEI mode or PBI mode. */
AnnaBridge	143:86740a56073b	1303	#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
AnnaBridge	143:86740a56073b	1304	/* @brief Reset clock mode is BLPI. */
AnnaBridge	143:86740a56073b	1305	#define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
AnnaBridge	143:86740a56073b	1306
AnnaBridge	143:86740a56073b	1307	/* interrupt module features */
AnnaBridge	143:86740a56073b	1308
AnnaBridge	143:86740a56073b	1309	/* @brief Lowest interrupt request number. */
AnnaBridge	143:86740a56073b	1310	#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
AnnaBridge	143:86740a56073b	1311	/* @brief Highest interrupt request number. */
AnnaBridge	143:86740a56073b	1312	#define FSL_FEATURE_INTERRUPT_IRQ_MAX (85)
AnnaBridge	143:86740a56073b	1313
AnnaBridge	143:86740a56073b	1314	/* OSC module features */
AnnaBridge	143:86740a56073b	1315
AnnaBridge	143:86740a56073b	1316	/* @brief Has OSC1 external oscillator. */
AnnaBridge	143:86740a56073b	1317	#define FSL_FEATURE_OSC_HAS_OSC1 (0)
AnnaBridge	143:86740a56073b	1318	/* @brief Has OSC0 external oscillator. */
AnnaBridge	143:86740a56073b	1319	#define FSL_FEATURE_OSC_HAS_OSC0 (0)
AnnaBridge	143:86740a56073b	1320	/* @brief Has OSC external oscillator (without index). */
AnnaBridge	143:86740a56073b	1321	#define FSL_FEATURE_OSC_HAS_OSC (1)
AnnaBridge	143:86740a56073b	1322	/* @brief Number of OSC external oscillators. */
AnnaBridge	143:86740a56073b	1323	#define FSL_FEATURE_OSC_OSC_COUNT (1)
AnnaBridge	143:86740a56073b	1324	/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
AnnaBridge	143:86740a56073b	1325	#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0)
AnnaBridge	143:86740a56073b	1326
AnnaBridge	143:86740a56073b	1327	/* PDB module features */
AnnaBridge	143:86740a56073b	1328
AnnaBridge	143:86740a56073b	1329	/* @brief Define the count of supporting ADC pre-trigger for each channel. */
AnnaBridge	143:86740a56073b	1330	#define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2)
AnnaBridge	143:86740a56073b	1331	/* @brief Has DAC support. */
AnnaBridge	143:86740a56073b	1332	#define FSL_FEATURE_PDB_HAS_DAC (1)
AnnaBridge	143:86740a56073b	1333	/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
AnnaBridge	143:86740a56073b	1334	#define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0)
AnnaBridge	143:86740a56073b	1335
AnnaBridge	143:86740a56073b	1336	/* PIT module features */
AnnaBridge	143:86740a56073b	1337
AnnaBridge	143:86740a56073b	1338	/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
AnnaBridge	143:86740a56073b	1339	#define FSL_FEATURE_PIT_TIMER_COUNT (4)
AnnaBridge	143:86740a56073b	1340	/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
AnnaBridge	143:86740a56073b	1341	#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0)
AnnaBridge	143:86740a56073b	1342	/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
AnnaBridge	143:86740a56073b	1343	#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
AnnaBridge	143:86740a56073b	1344	/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
AnnaBridge	143:86740a56073b	1345	#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0)
AnnaBridge	143:86740a56073b	1346
AnnaBridge	143:86740a56073b	1347	/* PMC module features */
AnnaBridge	143:86740a56073b	1348
AnnaBridge	143:86740a56073b	1349	/* @brief Has Bandgap Enable In VLPx Operation support. */
AnnaBridge	143:86740a56073b	1350	#define FSL_FEATURE_PMC_HAS_BGEN (1)
AnnaBridge	143:86740a56073b	1351	/* @brief Has Bandgap Buffer Enable. */
AnnaBridge	143:86740a56073b	1352	#define FSL_FEATURE_PMC_HAS_BGBE (1)
AnnaBridge	143:86740a56073b	1353	/* @brief Has Bandgap Buffer Drive Select. */
AnnaBridge	143:86740a56073b	1354	#define FSL_FEATURE_PMC_HAS_BGBDS (0)
AnnaBridge	143:86740a56073b	1355	/* @brief Has Low-Voltage Detect Voltage Select support. */
AnnaBridge	143:86740a56073b	1356	#define FSL_FEATURE_PMC_HAS_LVDV (1)
AnnaBridge	143:86740a56073b	1357	/* @brief Has Low-Voltage Warning Voltage Select support. */
AnnaBridge	143:86740a56073b	1358	#define FSL_FEATURE_PMC_HAS_LVWV (1)
AnnaBridge	143:86740a56073b	1359	/* @brief Has LPO. */
AnnaBridge	143:86740a56073b	1360	#define FSL_FEATURE_PMC_HAS_LPO (0)
AnnaBridge	143:86740a56073b	1361	/* @brief Has VLPx option PMC_REGSC[VLPO]. */
AnnaBridge	143:86740a56073b	1362	#define FSL_FEATURE_PMC_HAS_VLPO (0)
AnnaBridge	143:86740a56073b	1363	/* @brief Has acknowledge isolation support. */
AnnaBridge	143:86740a56073b	1364	#define FSL_FEATURE_PMC_HAS_ACKISO (1)
AnnaBridge	143:86740a56073b	1365	/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */
AnnaBridge	143:86740a56073b	1366	#define FSL_FEATURE_PMC_HAS_REGFPM (0)
AnnaBridge	143:86740a56073b	1367	/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */
AnnaBridge	143:86740a56073b	1368	#define FSL_FEATURE_PMC_HAS_REGONS (1)
AnnaBridge	143:86740a56073b	1369	/* @brief Has PMC_HVDSC1. */
AnnaBridge	143:86740a56073b	1370	#define FSL_FEATURE_PMC_HAS_HVDSC1 (0)
AnnaBridge	143:86740a56073b	1371	/* @brief Has PMC_PARAM. */
AnnaBridge	143:86740a56073b	1372	#define FSL_FEATURE_PMC_HAS_PARAM (0)
AnnaBridge	143:86740a56073b	1373	/* @brief Has PMC_VERID. */
AnnaBridge	143:86740a56073b	1374	#define FSL_FEATURE_PMC_HAS_VERID (0)
AnnaBridge	143:86740a56073b	1375
AnnaBridge	143:86740a56073b	1376	/* PORT module features */
AnnaBridge	143:86740a56073b	1377
AnnaBridge	143:86740a56073b	1378	/* @brief Has control lock (register bit PCR[LK]). */
AnnaBridge	143:86740a56073b	1379	#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
AnnaBridge	143:86740a56073b	1380	/* @brief Has open drain control (register bit PCR[ODE]). */
AnnaBridge	143:86740a56073b	1381	#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
AnnaBridge	143:86740a56073b	1382	/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
AnnaBridge	143:86740a56073b	1383	#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
AnnaBridge	143:86740a56073b	1384	/* @brief Has DMA request (register bit field PCR[IRQC] values). */
AnnaBridge	143:86740a56073b	1385	#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
AnnaBridge	143:86740a56073b	1386	/* @brief Has pull resistor selection available. */
AnnaBridge	143:86740a56073b	1387	#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
AnnaBridge	143:86740a56073b	1388	/* @brief Has pull resistor enable (register bit PCR[PE]). */
AnnaBridge	143:86740a56073b	1389	#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
AnnaBridge	143:86740a56073b	1390	/* @brief Has slew rate control (register bit PCR[SRE]). */
AnnaBridge	143:86740a56073b	1391	#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
AnnaBridge	143:86740a56073b	1392	/* @brief Has passive filter (register bit field PCR[PFE]). */
AnnaBridge	143:86740a56073b	1393	#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
AnnaBridge	143:86740a56073b	1394	/* @brief Has drive strength control (register bit PCR[DSE]). */
AnnaBridge	143:86740a56073b	1395	#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
AnnaBridge	143:86740a56073b	1396	/* @brief Has separate drive strength register (HDRVE). */
AnnaBridge	143:86740a56073b	1397	#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
AnnaBridge	143:86740a56073b	1398	/* @brief Has glitch filter (register IOFLT). */
AnnaBridge	143:86740a56073b	1399	#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
AnnaBridge	143:86740a56073b	1400	/* @brief Defines width of PCR[MUX] field. */
AnnaBridge	143:86740a56073b	1401	#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
AnnaBridge	143:86740a56073b	1402	/* @brief Has dedicated interrupt vector. */
AnnaBridge	143:86740a56073b	1403	#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
AnnaBridge	143:86740a56073b	1404	/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
AnnaBridge	143:86740a56073b	1405	#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0)
AnnaBridge	143:86740a56073b	1406	/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
AnnaBridge	143:86740a56073b	1407	#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
AnnaBridge	143:86740a56073b	1408	/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
AnnaBridge	143:86740a56073b	1409	#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
AnnaBridge	143:86740a56073b	1410
AnnaBridge	143:86740a56073b	1411	/* RCM module features */
AnnaBridge	143:86740a56073b	1412
AnnaBridge	143:86740a56073b	1413	/* @brief Has Loss-of-Lock Reset support. */
AnnaBridge	143:86740a56073b	1414	#define FSL_FEATURE_RCM_HAS_LOL (1)
AnnaBridge	143:86740a56073b	1415	/* @brief Has Loss-of-Clock Reset support. */
AnnaBridge	143:86740a56073b	1416	#define FSL_FEATURE_RCM_HAS_LOC (1)
AnnaBridge	143:86740a56073b	1417	/* @brief Has JTAG generated Reset support. */
AnnaBridge	143:86740a56073b	1418	#define FSL_FEATURE_RCM_HAS_JTAG (1)
AnnaBridge	143:86740a56073b	1419	/* @brief Has EzPort generated Reset support. */
AnnaBridge	143:86740a56073b	1420	#define FSL_FEATURE_RCM_HAS_EZPORT (1)
AnnaBridge	143:86740a56073b	1421	/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
AnnaBridge	143:86740a56073b	1422	#define FSL_FEATURE_RCM_HAS_EZPMS (1)
AnnaBridge	143:86740a56073b	1423	/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
AnnaBridge	143:86740a56073b	1424	#define FSL_FEATURE_RCM_HAS_BOOTROM (0)
AnnaBridge	143:86740a56073b	1425	/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
AnnaBridge	143:86740a56073b	1426	#define FSL_FEATURE_RCM_HAS_SSRS (0)
AnnaBridge	143:86740a56073b	1427	/* @brief Has Version ID Register (RCM_VERID). */
AnnaBridge	143:86740a56073b	1428	#define FSL_FEATURE_RCM_HAS_VERID (0)
AnnaBridge	143:86740a56073b	1429	/* @brief Has Parameter Register (RCM_PARAM). */
AnnaBridge	143:86740a56073b	1430	#define FSL_FEATURE_RCM_HAS_PARAM (0)
AnnaBridge	143:86740a56073b	1431	/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */
AnnaBridge	143:86740a56073b	1432	#define FSL_FEATURE_RCM_HAS_SRIE (0)
AnnaBridge	143:86740a56073b	1433	/* @brief Width of registers of the RCM. */
AnnaBridge	143:86740a56073b	1434	#define FSL_FEATURE_RCM_REG_WIDTH (8)
AnnaBridge	143:86740a56073b	1435	/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */
AnnaBridge	143:86740a56073b	1436	#define FSL_FEATURE_RCM_HAS_CORE1 (0)
AnnaBridge	143:86740a56073b	1437	/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */
AnnaBridge	143:86740a56073b	1438	#define FSL_FEATURE_RCM_HAS_MDM_AP (1)
AnnaBridge	143:86740a56073b	1439	/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */
AnnaBridge	143:86740a56073b	1440	#define FSL_FEATURE_RCM_HAS_WAKEUP (1)
AnnaBridge	143:86740a56073b	1441
AnnaBridge	143:86740a56073b	1442	/* RTC module features */
AnnaBridge	143:86740a56073b	1443
AnnaBridge	143:86740a56073b	1444	/* @brief Has wakeup pin. */
AnnaBridge	143:86740a56073b	1445	#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
AnnaBridge	143:86740a56073b	1446	/* @brief Has wakeup pin selection (bit field CR[WPS]). */
AnnaBridge	143:86740a56073b	1447	#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
AnnaBridge	143:86740a56073b	1448	/* @brief Has low power features (registers MER, MCLR and MCHR). */
AnnaBridge	143:86740a56073b	1449	#define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
AnnaBridge	143:86740a56073b	1450	/* @brief Has read/write access control (registers WAR and RAR). */
AnnaBridge	143:86740a56073b	1451	#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
AnnaBridge	143:86740a56073b	1452	/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
AnnaBridge	143:86740a56073b	1453	#define FSL_FEATURE_RTC_HAS_SECURITY (0)
AnnaBridge	143:86740a56073b	1454	/* @brief Has RTC_CLKIN available. */
AnnaBridge	143:86740a56073b	1455	#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
AnnaBridge	143:86740a56073b	1456	/* @brief Has prescaler adjust for LPO. */
AnnaBridge	143:86740a56073b	1457	#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
AnnaBridge	143:86740a56073b	1458	/* @brief Has Clock Pin Enable field. */
AnnaBridge	143:86740a56073b	1459	#define FSL_FEATURE_RTC_HAS_CPE (0)
AnnaBridge	143:86740a56073b	1460	/* @brief Has Timer Seconds Interrupt Configuration field. */
AnnaBridge	143:86740a56073b	1461	#define FSL_FEATURE_RTC_HAS_TSIC (0)
AnnaBridge	143:86740a56073b	1462	/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
AnnaBridge	143:86740a56073b	1463	#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
AnnaBridge	143:86740a56073b	1464
AnnaBridge	143:86740a56073b	1465	/* SDHC module features */
AnnaBridge	143:86740a56073b	1466
AnnaBridge	143:86740a56073b	1467	/* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */
AnnaBridge	143:86740a56073b	1468	#define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (1)
AnnaBridge	143:86740a56073b	1469	/* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */
AnnaBridge	143:86740a56073b	1470	#define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0)
AnnaBridge	143:86740a56073b	1471	/* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */
AnnaBridge	143:86740a56073b	1472	#define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0)
AnnaBridge	143:86740a56073b	1473
AnnaBridge	143:86740a56073b	1474	/* SIM module features */
AnnaBridge	143:86740a56073b	1475
AnnaBridge	143:86740a56073b	1476	/* @brief Has USB FS divider. */
AnnaBridge	143:86740a56073b	1477	#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
AnnaBridge	143:86740a56073b	1478	/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
AnnaBridge	143:86740a56073b	1479	#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
AnnaBridge	143:86740a56073b	1480	/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
AnnaBridge	143:86740a56073b	1481	#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
AnnaBridge	143:86740a56073b	1482	/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
AnnaBridge	143:86740a56073b	1483	#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
AnnaBridge	143:86740a56073b	1484	/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
AnnaBridge	143:86740a56073b	1485	#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
AnnaBridge	143:86740a56073b	1486	/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
AnnaBridge	143:86740a56073b	1487	#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
AnnaBridge	143:86740a56073b	1488	/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
AnnaBridge	143:86740a56073b	1489	#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
AnnaBridge	143:86740a56073b	1490	/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
AnnaBridge	143:86740a56073b	1491	#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
AnnaBridge	143:86740a56073b	1492	/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
AnnaBridge	143:86740a56073b	1493	#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
AnnaBridge	143:86740a56073b	1494	/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
AnnaBridge	143:86740a56073b	1495	#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1)
AnnaBridge	143:86740a56073b	1496	/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
AnnaBridge	143:86740a56073b	1497	#define FSL_FEATURE_SIM_OPT_HAS_FBSL (1)
AnnaBridge	143:86740a56073b	1498	/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
AnnaBridge	143:86740a56073b	1499	#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
AnnaBridge	143:86740a56073b	1500	/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
AnnaBridge	143:86740a56073b	1501	#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
AnnaBridge	143:86740a56073b	1502	/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
AnnaBridge	143:86740a56073b	1503	#define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
AnnaBridge	143:86740a56073b	1504	/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
AnnaBridge	143:86740a56073b	1505	#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
AnnaBridge	143:86740a56073b	1506	/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
AnnaBridge	143:86740a56073b	1507	#define FSL_FEATURE_SIM_OPT_UART_COUNT (4)
AnnaBridge	143:86740a56073b	1508	/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
AnnaBridge	143:86740a56073b	1509	#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
AnnaBridge	143:86740a56073b	1510	/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
AnnaBridge	143:86740a56073b	1511	#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
AnnaBridge	143:86740a56073b	1512	/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
AnnaBridge	143:86740a56073b	1513	#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
AnnaBridge	143:86740a56073b	1514	/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
AnnaBridge	143:86740a56073b	1515	#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
AnnaBridge	143:86740a56073b	1516	/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
AnnaBridge	143:86740a56073b	1517	#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
AnnaBridge	143:86740a56073b	1518	/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
AnnaBridge	143:86740a56073b	1519	#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
AnnaBridge	143:86740a56073b	1520	/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
AnnaBridge	143:86740a56073b	1521	#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
AnnaBridge	143:86740a56073b	1522	/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
AnnaBridge	143:86740a56073b	1523	#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
AnnaBridge	143:86740a56073b	1524	/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
AnnaBridge	143:86740a56073b	1525	#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
AnnaBridge	143:86740a56073b	1526	/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
AnnaBridge	143:86740a56073b	1527	#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
AnnaBridge	143:86740a56073b	1528	/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
AnnaBridge	143:86740a56073b	1529	#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
AnnaBridge	143:86740a56073b	1530	/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
AnnaBridge	143:86740a56073b	1531	#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
AnnaBridge	143:86740a56073b	1532	/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
AnnaBridge	143:86740a56073b	1533	#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
AnnaBridge	143:86740a56073b	1534	/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
AnnaBridge	143:86740a56073b	1535	#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
AnnaBridge	143:86740a56073b	1536	/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
AnnaBridge	143:86740a56073b	1537	#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
AnnaBridge	143:86740a56073b	1538	/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
AnnaBridge	143:86740a56073b	1539	#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
AnnaBridge	143:86740a56073b	1540	/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
AnnaBridge	143:86740a56073b	1541	#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
AnnaBridge	143:86740a56073b	1542	/* @brief Has FTM module(s) configuration. */
AnnaBridge	143:86740a56073b	1543	#define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
AnnaBridge	143:86740a56073b	1544	/* @brief Number of FTM modules. */
AnnaBridge	143:86740a56073b	1545	#define FSL_FEATURE_SIM_OPT_FTM_COUNT (4)
AnnaBridge	143:86740a56073b	1546	/* @brief Number of FTM triggers with selectable source. */
AnnaBridge	143:86740a56073b	1547	#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
AnnaBridge	143:86740a56073b	1548	/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
AnnaBridge	143:86740a56073b	1549	#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
AnnaBridge	143:86740a56073b	1550	/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
AnnaBridge	143:86740a56073b	1551	#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
AnnaBridge	143:86740a56073b	1552	/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
AnnaBridge	143:86740a56073b	1553	#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
AnnaBridge	143:86740a56073b	1554	/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
AnnaBridge	143:86740a56073b	1555	#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
AnnaBridge	143:86740a56073b	1556	/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
AnnaBridge	143:86740a56073b	1557	#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
AnnaBridge	143:86740a56073b	1558	/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
AnnaBridge	143:86740a56073b	1559	#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
AnnaBridge	143:86740a56073b	1560	/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
AnnaBridge	143:86740a56073b	1561	#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3)
AnnaBridge	143:86740a56073b	1562	/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
AnnaBridge	143:86740a56073b	1563	#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
AnnaBridge	143:86740a56073b	1564	/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
AnnaBridge	143:86740a56073b	1565	#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
AnnaBridge	143:86740a56073b	1566	/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
AnnaBridge	143:86740a56073b	1567	#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
AnnaBridge	143:86740a56073b	1568	/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
AnnaBridge	143:86740a56073b	1569	#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
AnnaBridge	143:86740a56073b	1570	/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
AnnaBridge	143:86740a56073b	1571	#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
AnnaBridge	143:86740a56073b	1572	/* @brief Has TPM module(s) configuration. */
AnnaBridge	143:86740a56073b	1573	#define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
AnnaBridge	143:86740a56073b	1574	/* @brief The highest TPM module index. */
AnnaBridge	143:86740a56073b	1575	#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
AnnaBridge	143:86740a56073b	1576	/* @brief Has TPM module with index 0. */
AnnaBridge	143:86740a56073b	1577	#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
AnnaBridge	143:86740a56073b	1578	/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
AnnaBridge	143:86740a56073b	1579	#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
AnnaBridge	143:86740a56073b	1580	/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
AnnaBridge	143:86740a56073b	1581	#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
AnnaBridge	143:86740a56073b	1582	/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
AnnaBridge	143:86740a56073b	1583	#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
AnnaBridge	143:86740a56073b	1584	/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
AnnaBridge	143:86740a56073b	1585	#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
AnnaBridge	143:86740a56073b	1586	/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
AnnaBridge	143:86740a56073b	1587	#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
AnnaBridge	143:86740a56073b	1588	/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
AnnaBridge	143:86740a56073b	1589	#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
AnnaBridge	143:86740a56073b	1590	/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
AnnaBridge	143:86740a56073b	1591	#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
AnnaBridge	143:86740a56073b	1592	/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
AnnaBridge	143:86740a56073b	1593	#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
AnnaBridge	143:86740a56073b	1594	/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
AnnaBridge	143:86740a56073b	1595	#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
AnnaBridge	143:86740a56073b	1596	/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
AnnaBridge	143:86740a56073b	1597	#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
AnnaBridge	143:86740a56073b	1598	/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
AnnaBridge	143:86740a56073b	1599	#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
AnnaBridge	143:86740a56073b	1600	/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
AnnaBridge	143:86740a56073b	1601	#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1)
AnnaBridge	143:86740a56073b	1602	/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
AnnaBridge	143:86740a56073b	1603	#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
AnnaBridge	143:86740a56073b	1604	/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
AnnaBridge	143:86740a56073b	1605	#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
AnnaBridge	143:86740a56073b	1606	/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
AnnaBridge	143:86740a56073b	1607	#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
AnnaBridge	143:86740a56073b	1608	/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
AnnaBridge	143:86740a56073b	1609	#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
AnnaBridge	143:86740a56073b	1610	/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
AnnaBridge	143:86740a56073b	1611	#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
AnnaBridge	143:86740a56073b	1612	/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
AnnaBridge	143:86740a56073b	1613	#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
AnnaBridge	143:86740a56073b	1614	/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
AnnaBridge	143:86740a56073b	1615	#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
AnnaBridge	143:86740a56073b	1616	/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
AnnaBridge	143:86740a56073b	1617	#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
AnnaBridge	143:86740a56073b	1618	/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
AnnaBridge	143:86740a56073b	1619	#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
AnnaBridge	143:86740a56073b	1620	/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
AnnaBridge	143:86740a56073b	1621	#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
AnnaBridge	143:86740a56073b	1622	/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
AnnaBridge	143:86740a56073b	1623	#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
AnnaBridge	143:86740a56073b	1624	/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
AnnaBridge	143:86740a56073b	1625	#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
AnnaBridge	143:86740a56073b	1626	/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
AnnaBridge	143:86740a56073b	1627	#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
AnnaBridge	143:86740a56073b	1628	/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
AnnaBridge	143:86740a56073b	1629	#define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
AnnaBridge	143:86740a56073b	1630	/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
AnnaBridge	143:86740a56073b	1631	#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1)
AnnaBridge	143:86740a56073b	1632	/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
AnnaBridge	143:86740a56073b	1633	#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (1)
AnnaBridge	143:86740a56073b	1634	/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
AnnaBridge	143:86740a56073b	1635	#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
AnnaBridge	143:86740a56073b	1636	/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
AnnaBridge	143:86740a56073b	1637	#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
AnnaBridge	143:86740a56073b	1638	/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
AnnaBridge	143:86740a56073b	1639	#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
AnnaBridge	143:86740a56073b	1640	/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
AnnaBridge	143:86740a56073b	1641	#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
AnnaBridge	143:86740a56073b	1642	/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
AnnaBridge	143:86740a56073b	1643	#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
AnnaBridge	143:86740a56073b	1644	/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
AnnaBridge	143:86740a56073b	1645	#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
AnnaBridge	143:86740a56073b	1646	/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
AnnaBridge	143:86740a56073b	1647	#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
AnnaBridge	143:86740a56073b	1648	/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
AnnaBridge	143:86740a56073b	1649	#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
AnnaBridge	143:86740a56073b	1650	/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
AnnaBridge	143:86740a56073b	1651	#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
AnnaBridge	143:86740a56073b	1652	/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
AnnaBridge	143:86740a56073b	1653	#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1)
AnnaBridge	143:86740a56073b	1654	/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
AnnaBridge	143:86740a56073b	1655	#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
AnnaBridge	143:86740a56073b	1656	/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
AnnaBridge	143:86740a56073b	1657	#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
AnnaBridge	143:86740a56073b	1658	/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
AnnaBridge	143:86740a56073b	1659	#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
AnnaBridge	143:86740a56073b	1660	/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
AnnaBridge	143:86740a56073b	1661	#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
AnnaBridge	143:86740a56073b	1662	/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
AnnaBridge	143:86740a56073b	1663	#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
AnnaBridge	143:86740a56073b	1664	/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
AnnaBridge	143:86740a56073b	1665	#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
AnnaBridge	143:86740a56073b	1666	/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
AnnaBridge	143:86740a56073b	1667	#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
AnnaBridge	143:86740a56073b	1668	/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
AnnaBridge	143:86740a56073b	1669	#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
AnnaBridge	143:86740a56073b	1670	/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
AnnaBridge	143:86740a56073b	1671	#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
AnnaBridge	143:86740a56073b	1672	/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
AnnaBridge	143:86740a56073b	1673	#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
AnnaBridge	143:86740a56073b	1674	/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
AnnaBridge	143:86740a56073b	1675	#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
AnnaBridge	143:86740a56073b	1676	/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
AnnaBridge	143:86740a56073b	1677	#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
AnnaBridge	143:86740a56073b	1678	/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
AnnaBridge	143:86740a56073b	1679	#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
AnnaBridge	143:86740a56073b	1680	/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
AnnaBridge	143:86740a56073b	1681	#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
AnnaBridge	143:86740a56073b	1682	/* @brief Has device die ID (register bit field SDID[DIEID]). */
AnnaBridge	143:86740a56073b	1683	#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
AnnaBridge	143:86740a56073b	1684	/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
AnnaBridge	143:86740a56073b	1685	#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
AnnaBridge	143:86740a56073b	1686	/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
AnnaBridge	143:86740a56073b	1687	#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
AnnaBridge	143:86740a56073b	1688	/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
AnnaBridge	143:86740a56073b	1689	#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
AnnaBridge	143:86740a56073b	1690	/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
AnnaBridge	143:86740a56073b	1691	#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
AnnaBridge	143:86740a56073b	1692	/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
AnnaBridge	143:86740a56073b	1693	#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1)
AnnaBridge	143:86740a56073b	1694	/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
AnnaBridge	143:86740a56073b	1695	#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1)
AnnaBridge	143:86740a56073b	1696	/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
AnnaBridge	143:86740a56073b	1697	#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1)
AnnaBridge	143:86740a56073b	1698	/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
AnnaBridge	143:86740a56073b	1699	#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
AnnaBridge	143:86740a56073b	1700	/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
AnnaBridge	143:86740a56073b	1701	#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
AnnaBridge	143:86740a56073b	1702	/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
AnnaBridge	143:86740a56073b	1703	#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
AnnaBridge	143:86740a56073b	1704	/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
AnnaBridge	143:86740a56073b	1705	#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
AnnaBridge	143:86740a56073b	1706	/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
AnnaBridge	143:86740a56073b	1707	#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1)
AnnaBridge	143:86740a56073b	1708	/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
AnnaBridge	143:86740a56073b	1709	#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
AnnaBridge	143:86740a56073b	1710	/* @brief Has miscellanious control register (register MCR). */
AnnaBridge	143:86740a56073b	1711	#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
AnnaBridge	143:86740a56073b	1712	/* @brief Has COP watchdog (registers COPC and SRVCOP). */
AnnaBridge	143:86740a56073b	1713	#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
AnnaBridge	143:86740a56073b	1714	/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
AnnaBridge	143:86740a56073b	1715	#define FSL_FEATURE_SIM_HAS_COP_STOP (0)
AnnaBridge	143:86740a56073b	1716	/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
AnnaBridge	143:86740a56073b	1717	#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
AnnaBridge	143:86740a56073b	1718
AnnaBridge	143:86740a56073b	1719	/* SMC module features */
AnnaBridge	143:86740a56073b	1720
AnnaBridge	143:86740a56073b	1721	/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
AnnaBridge	143:86740a56073b	1722	#define FSL_FEATURE_SMC_HAS_PSTOPO (0)
AnnaBridge	143:86740a56073b	1723	/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
AnnaBridge	143:86740a56073b	1724	#define FSL_FEATURE_SMC_HAS_LPOPO (0)
AnnaBridge	143:86740a56073b	1725	/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
AnnaBridge	143:86740a56073b	1726	#define FSL_FEATURE_SMC_HAS_PORPO (1)
AnnaBridge	143:86740a56073b	1727	/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
AnnaBridge	143:86740a56073b	1728	#define FSL_FEATURE_SMC_HAS_LPWUI (1)
AnnaBridge	143:86740a56073b	1729	/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
AnnaBridge	143:86740a56073b	1730	#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
AnnaBridge	143:86740a56073b	1731	/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
AnnaBridge	143:86740a56073b	1732	#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1)
AnnaBridge	143:86740a56073b	1733	/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
AnnaBridge	143:86740a56073b	1734	#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
AnnaBridge	143:86740a56073b	1735	/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
AnnaBridge	143:86740a56073b	1736	#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
AnnaBridge	143:86740a56073b	1737	/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
AnnaBridge	143:86740a56073b	1738	#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
AnnaBridge	143:86740a56073b	1739	/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
AnnaBridge	143:86740a56073b	1740	#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
AnnaBridge	143:86740a56073b	1741	/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
AnnaBridge	143:86740a56073b	1742	#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
AnnaBridge	143:86740a56073b	1743	/* @brief Has stop submode. */
AnnaBridge	143:86740a56073b	1744	#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
AnnaBridge	143:86740a56073b	1745	/* @brief Has stop submode 0(VLLS0). */
AnnaBridge	143:86740a56073b	1746	#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
AnnaBridge	143:86740a56073b	1747	/* @brief Has stop submode 2(VLLS2). */
AnnaBridge	143:86740a56073b	1748	#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
AnnaBridge	143:86740a56073b	1749	/* @brief Has SMC_PARAM. */
AnnaBridge	143:86740a56073b	1750	#define FSL_FEATURE_SMC_HAS_PARAM (0)
AnnaBridge	143:86740a56073b	1751	/* @brief Has SMC_VERID. */
AnnaBridge	143:86740a56073b	1752	#define FSL_FEATURE_SMC_HAS_VERID (0)
AnnaBridge	143:86740a56073b	1753	/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
AnnaBridge	143:86740a56073b	1754	#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1)
AnnaBridge	143:86740a56073b	1755	/* @brief Has tamper reset (register bit SRS[TAMPER]). */
AnnaBridge	143:86740a56073b	1756	#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
AnnaBridge	143:86740a56073b	1757	/* @brief Has security violation reset (register bit SRS[SECVIO]). */
AnnaBridge	143:86740a56073b	1758	#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
AnnaBridge	143:86740a56073b	1759
AnnaBridge	143:86740a56073b	1760	/* DSPI module features */
AnnaBridge	143:86740a56073b	1761
AnnaBridge	143:86740a56073b	1762	/* @brief Receive/transmit FIFO size in number of items. */
AnnaBridge	143:86740a56073b	1763	#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
AnnaBridge	143:86740a56073b	1764	((x) == DSPI0 ? (4) : \
AnnaBridge	143:86740a56073b	1765	((x) == DSPI1 ? (1) : \
AnnaBridge	143:86740a56073b	1766	((x) == DSPI2 ? (1) : (-1))))
AnnaBridge	143:86740a56073b	1767	/* @brief Maximum transfer data width in bits. */
AnnaBridge	143:86740a56073b	1768	#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
AnnaBridge	143:86740a56073b	1769	/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
AnnaBridge	143:86740a56073b	1770	#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
AnnaBridge	143:86740a56073b	1771	/* @brief Number of chip select pins. */
AnnaBridge	143:86740a56073b	1772	#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
AnnaBridge	143:86740a56073b	1773	/* @brief Has chip select strobe capability on the PCS5 pin. */
AnnaBridge	143:86740a56073b	1774	#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
AnnaBridge	143:86740a56073b	1775	/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
AnnaBridge	143:86740a56073b	1776	#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
AnnaBridge	143:86740a56073b	1777	/* @brief Has 16-bit data transfer support. */
AnnaBridge	143:86740a56073b	1778	#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
AnnaBridge	143:86740a56073b	1779	/* @brief Has separate DMA RX and TX requests. */
AnnaBridge	143:86740a56073b	1780	#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
AnnaBridge	143:86740a56073b	1781	((x) == DSPI0 ? (1) : \
AnnaBridge	143:86740a56073b	1782	((x) == DSPI1 ? (0) : \
AnnaBridge	143:86740a56073b	1783	((x) == DSPI2 ? (0) : (-1))))
AnnaBridge	143:86740a56073b	1784
AnnaBridge	143:86740a56073b	1785	/* SYSMPU module features */
AnnaBridge	143:86740a56073b	1786
AnnaBridge	143:86740a56073b	1787	/* @brief Specifies number of descriptors available. */
AnnaBridge	143:86740a56073b	1788	#define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (12)
AnnaBridge	143:86740a56073b	1789	/* @brief Has process identifier support. */
AnnaBridge	143:86740a56073b	1790	#define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1)
AnnaBridge	143:86740a56073b	1791	/* @brief Total number of MPU slave. */
AnnaBridge	143:86740a56073b	1792	#define FSL_FEATURE_SYSMPU_SLAVE_COUNT (5)
AnnaBridge	143:86740a56073b	1793	/* @brief Total number of MPU master. */
AnnaBridge	143:86740a56073b	1794	#define FSL_FEATURE_SYSMPU_MASTER_COUNT (6)
AnnaBridge	143:86740a56073b	1795
AnnaBridge	143:86740a56073b	1796	/* SysTick module features */
AnnaBridge	143:86740a56073b	1797
AnnaBridge	143:86740a56073b	1798	/* @brief Systick has external reference clock. */
AnnaBridge	143:86740a56073b	1799	#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
AnnaBridge	143:86740a56073b	1800	/* @brief Systick external reference clock is core clock divided by this value. */
AnnaBridge	143:86740a56073b	1801	#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
AnnaBridge	143:86740a56073b	1802
AnnaBridge	143:86740a56073b	1803	/* UART module features */
AnnaBridge	143:86740a56073b	1804
AnnaBridge	143:86740a56073b	1805	#if defined(CPU_MK24FN1M0CAJ12) \|\| defined(CPU_MK24FN1M0VDC12) \|\| defined(CPU_MK24FN1M0VLQ12)
AnnaBridge	143:86740a56073b	1806	/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
AnnaBridge	143:86740a56073b	1807	#define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
AnnaBridge	143:86740a56073b	1808	/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
AnnaBridge	143:86740a56073b	1809	#define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
AnnaBridge	143:86740a56073b	1810	/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
AnnaBridge	143:86740a56073b	1811	#define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
AnnaBridge	143:86740a56073b	1812	/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
AnnaBridge	143:86740a56073b	1813	#define FSL_FEATURE_UART_HAS_FIFO (1)
AnnaBridge	143:86740a56073b	1814	/* @brief Hardware flow control (RTS, CTS) is supported. */
AnnaBridge	143:86740a56073b	1815	#define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
AnnaBridge	143:86740a56073b	1816	/* @brief Infrared (modulation) is supported. */
AnnaBridge	143:86740a56073b	1817	#define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
AnnaBridge	143:86740a56073b	1818	/* @brief 2 bits long stop bit is available. */
AnnaBridge	143:86740a56073b	1819	#define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
AnnaBridge	143:86740a56073b	1820	/* @brief If 10-bit mode is supported. */
AnnaBridge	143:86740a56073b	1821	#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1)
AnnaBridge	143:86740a56073b	1822	/* @brief Baud rate fine adjustment is available. */
AnnaBridge	143:86740a56073b	1823	#define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
AnnaBridge	143:86740a56073b	1824	/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
AnnaBridge	143:86740a56073b	1825	#define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
AnnaBridge	143:86740a56073b	1826	/* @brief Baud rate oversampling is available. */
AnnaBridge	143:86740a56073b	1827	#define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
AnnaBridge	143:86740a56073b	1828	/* @brief Baud rate oversampling is available. */
AnnaBridge	143:86740a56073b	1829	#define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
AnnaBridge	143:86740a56073b	1830	/* @brief Peripheral type. */
AnnaBridge	143:86740a56073b	1831	#define FSL_FEATURE_UART_IS_SCI (0)
AnnaBridge	143:86740a56073b	1832	/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
AnnaBridge	143:86740a56073b	1833	#define FSL_FEATURE_UART_FIFO_SIZEn(x) \
AnnaBridge	143:86740a56073b	1834	((x) == UART0 ? (8) : \
AnnaBridge	143:86740a56073b	1835	((x) == UART1 ? (8) : \
AnnaBridge	143:86740a56073b	1836	((x) == UART2 ? (1) : \
AnnaBridge	143:86740a56073b	1837	((x) == UART3 ? (1) : \
AnnaBridge	143:86740a56073b	1838	((x) == UART4 ? (1) : \
AnnaBridge	143:86740a56073b	1839	((x) == UART5 ? (1) : (-1)))))))
AnnaBridge	143:86740a56073b	1840	/* @brief Maximal data width without parity bit. */
AnnaBridge	143:86740a56073b	1841	#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
AnnaBridge	143:86740a56073b	1842	/* @brief Maximal data width with parity bit. */
AnnaBridge	143:86740a56073b	1843	#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
AnnaBridge	143:86740a56073b	1844	/* @brief Supports two match addresses to filter incoming frames. */
AnnaBridge	143:86740a56073b	1845	#define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
AnnaBridge	143:86740a56073b	1846	/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
AnnaBridge	143:86740a56073b	1847	#define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
AnnaBridge	143:86740a56073b	1848	/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
AnnaBridge	143:86740a56073b	1849	#define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
AnnaBridge	143:86740a56073b	1850	/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
AnnaBridge	143:86740a56073b	1851	#define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
AnnaBridge	143:86740a56073b	1852	/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
AnnaBridge	143:86740a56073b	1853	#define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
AnnaBridge	143:86740a56073b	1854	/* @brief Has improved smart card (ISO7816 protocol) support. */
AnnaBridge	143:86740a56073b	1855	#define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
AnnaBridge	143:86740a56073b	1856	/* @brief Has local operation network (CEA709.1-B protocol) support. */
AnnaBridge	143:86740a56073b	1857	#define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
AnnaBridge	143:86740a56073b	1858	/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
AnnaBridge	143:86740a56073b	1859	#define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
AnnaBridge	143:86740a56073b	1860	/* @brief Lin break detect available (has bit BDH[LBKDIE]). */
AnnaBridge	143:86740a56073b	1861	#define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
AnnaBridge	143:86740a56073b	1862	/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
AnnaBridge	143:86740a56073b	1863	#define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
AnnaBridge	143:86740a56073b	1864	/* @brief Has separate DMA RX and TX requests. */
AnnaBridge	143:86740a56073b	1865	#define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
AnnaBridge	143:86740a56073b	1866	((x) == UART0 ? (1) : \
AnnaBridge	143:86740a56073b	1867	((x) == UART1 ? (1) : \
AnnaBridge	143:86740a56073b	1868	((x) == UART2 ? (1) : \
AnnaBridge	143:86740a56073b	1869	((x) == UART3 ? (1) : \
AnnaBridge	143:86740a56073b	1870	((x) == UART4 ? (0) : \
AnnaBridge	143:86740a56073b	1871	((x) == UART5 ? (0) : (-1)))))))
AnnaBridge	143:86740a56073b	1872	#elif defined(CPU_MK24FN1M0VLL12)
AnnaBridge	143:86740a56073b	1873	/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
AnnaBridge	143:86740a56073b	1874	#define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
AnnaBridge	143:86740a56073b	1875	/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
AnnaBridge	143:86740a56073b	1876	#define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
AnnaBridge	143:86740a56073b	1877	/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
AnnaBridge	143:86740a56073b	1878	#define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
AnnaBridge	143:86740a56073b	1879	/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
AnnaBridge	143:86740a56073b	1880	#define FSL_FEATURE_UART_HAS_FIFO (1)
AnnaBridge	143:86740a56073b	1881	/* @brief Hardware flow control (RTS, CTS) is supported. */
AnnaBridge	143:86740a56073b	1882	#define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
AnnaBridge	143:86740a56073b	1883	/* @brief Infrared (modulation) is supported. */
AnnaBridge	143:86740a56073b	1884	#define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
AnnaBridge	143:86740a56073b	1885	/* @brief 2 bits long stop bit is available. */
AnnaBridge	143:86740a56073b	1886	#define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
AnnaBridge	143:86740a56073b	1887	/* @brief If 10-bit mode is supported. */
AnnaBridge	143:86740a56073b	1888	#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1)
AnnaBridge	143:86740a56073b	1889	/* @brief Baud rate fine adjustment is available. */
AnnaBridge	143:86740a56073b	1890	#define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
AnnaBridge	143:86740a56073b	1891	/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
AnnaBridge	143:86740a56073b	1892	#define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
AnnaBridge	143:86740a56073b	1893	/* @brief Baud rate oversampling is available. */
AnnaBridge	143:86740a56073b	1894	#define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
AnnaBridge	143:86740a56073b	1895	/* @brief Baud rate oversampling is available. */
AnnaBridge	143:86740a56073b	1896	#define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
AnnaBridge	143:86740a56073b	1897	/* @brief Peripheral type. */
AnnaBridge	143:86740a56073b	1898	#define FSL_FEATURE_UART_IS_SCI (0)
AnnaBridge	143:86740a56073b	1899	/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
AnnaBridge	143:86740a56073b	1900	#define FSL_FEATURE_UART_FIFO_SIZEn(x) \
AnnaBridge	143:86740a56073b	1901	((x) == UART0 ? (8) : \
AnnaBridge	143:86740a56073b	1902	((x) == UART1 ? (8) : \
AnnaBridge	143:86740a56073b	1903	((x) == UART2 ? (1) : \
AnnaBridge	143:86740a56073b	1904	((x) == UART3 ? (1) : \
AnnaBridge	143:86740a56073b	1905	((x) == UART4 ? (1) : (-1))))))
AnnaBridge	143:86740a56073b	1906	/* @brief Maximal data width without parity bit. */
AnnaBridge	143:86740a56073b	1907	#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
AnnaBridge	143:86740a56073b	1908	/* @brief Maximal data width with parity bit. */
AnnaBridge	143:86740a56073b	1909	#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
AnnaBridge	143:86740a56073b	1910	/* @brief Supports two match addresses to filter incoming frames. */
AnnaBridge	143:86740a56073b	1911	#define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
AnnaBridge	143:86740a56073b	1912	/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
AnnaBridge	143:86740a56073b	1913	#define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
AnnaBridge	143:86740a56073b	1914	/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
AnnaBridge	143:86740a56073b	1915	#define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
AnnaBridge	143:86740a56073b	1916	/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
AnnaBridge	143:86740a56073b	1917	#define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
AnnaBridge	143:86740a56073b	1918	/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
AnnaBridge	143:86740a56073b	1919	#define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
AnnaBridge	143:86740a56073b	1920	/* @brief Has improved smart card (ISO7816 protocol) support. */
AnnaBridge	143:86740a56073b	1921	#define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
AnnaBridge	143:86740a56073b	1922	/* @brief Has local operation network (CEA709.1-B protocol) support. */
AnnaBridge	143:86740a56073b	1923	#define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
AnnaBridge	143:86740a56073b	1924	/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
AnnaBridge	143:86740a56073b	1925	#define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
AnnaBridge	143:86740a56073b	1926	/* @brief Lin break detect available (has bit BDH[LBKDIE]). */
AnnaBridge	143:86740a56073b	1927	#define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
AnnaBridge	143:86740a56073b	1928	/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
AnnaBridge	143:86740a56073b	1929	#define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
AnnaBridge	143:86740a56073b	1930	/* @brief Has separate DMA RX and TX requests. */
AnnaBridge	143:86740a56073b	1931	#define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
AnnaBridge	143:86740a56073b	1932	((x) == UART0 ? (1) : \
AnnaBridge	143:86740a56073b	1933	((x) == UART1 ? (1) : \
AnnaBridge	143:86740a56073b	1934	((x) == UART2 ? (1) : \
AnnaBridge	143:86740a56073b	1935	((x) == UART3 ? (1) : \
AnnaBridge	143:86740a56073b	1936	((x) == UART4 ? (0) : (-1))))))
AnnaBridge	143:86740a56073b	1937	#endif /* defined(CPU_MK24FN1M0CAJ12) \|\| defined(CPU_MK24FN1M0VDC12) \|\| defined(CPU_MK24FN1M0VLQ12) */
AnnaBridge	143:86740a56073b	1938
AnnaBridge	143:86740a56073b	1939	/* USB module features */
AnnaBridge	143:86740a56073b	1940
AnnaBridge	143:86740a56073b	1941	/* @brief KHCI module instance count */
AnnaBridge	143:86740a56073b	1942	#define FSL_FEATURE_USB_KHCI_COUNT (1)
AnnaBridge	143:86740a56073b	1943	/* @brief HOST mode enabled */
AnnaBridge	143:86740a56073b	1944	#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1)
AnnaBridge	143:86740a56073b	1945	/* @brief OTG mode enabled */
AnnaBridge	143:86740a56073b	1946	#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1)
AnnaBridge	143:86740a56073b	1947	/* @brief Size of the USB dedicated RAM */
AnnaBridge	143:86740a56073b	1948	#define FSL_FEATURE_USB_KHCI_USB_RAM (0)
AnnaBridge	143:86740a56073b	1949	/* @brief Has KEEP_ALIVE_CTRL register */
AnnaBridge	143:86740a56073b	1950	#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0)
AnnaBridge	143:86740a56073b	1951	/* @brief Has the Dynamic SOF threshold compare support */
AnnaBridge	143:86740a56073b	1952	#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0)
AnnaBridge	143:86740a56073b	1953	/* @brief Has the VBUS detect support */
AnnaBridge	143:86740a56073b	1954	#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0)
AnnaBridge	143:86740a56073b	1955	/* @brief Has the IRC48M module clock support */
AnnaBridge	143:86740a56073b	1956	#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
AnnaBridge	143:86740a56073b	1957	/* @brief Number of endpoints supported */
AnnaBridge	143:86740a56073b	1958	#define FSL_FEATURE_USB_ENDPT_COUNT (16)
AnnaBridge	143:86740a56073b	1959
AnnaBridge	143:86740a56073b	1960	/* VREF module features */
AnnaBridge	143:86740a56073b	1961
AnnaBridge	143:86740a56073b	1962	/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
AnnaBridge	143:86740a56073b	1963	#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
AnnaBridge	143:86740a56073b	1964	/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
AnnaBridge	143:86740a56073b	1965	#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
AnnaBridge	143:86740a56073b	1966	/* @brief If high/low buffer mode supported */
AnnaBridge	143:86740a56073b	1967	#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
AnnaBridge	143:86740a56073b	1968	/* @brief Module has also low reference (registers VREFL/VREFH) */
AnnaBridge	143:86740a56073b	1969	#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
AnnaBridge	143:86740a56073b	1970	/* @brief Has VREF_TRM4. */
AnnaBridge	143:86740a56073b	1971	#define FSL_FEATURE_VREF_HAS_TRM4 (0)
AnnaBridge	143:86740a56073b	1972
AnnaBridge	143:86740a56073b	1973	/* WDOG module features */
AnnaBridge	143:86740a56073b	1974
AnnaBridge	143:86740a56073b	1975	/* @brief Watchdog is available. */
AnnaBridge	143:86740a56073b	1976	#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
AnnaBridge	143:86740a56073b	1977	/* @brief Has Wait mode support. */
AnnaBridge	143:86740a56073b	1978	#define FSL_FEATURE_WDOG_HAS_WAITEN (1)
AnnaBridge	143:86740a56073b	1979
AnnaBridge	143:86740a56073b	1980	#endif /* _MK24F12_FEATURES_H_ */
AnnaBridge	143:86740a56073b	1981