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TARGET_NUCLEO_L496ZG/TOOLCHAIN_ARM_STD/stm32l4xx_hal_tim.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
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AnnaBridge | 145:64910690c574 | 1 | /** |
AnnaBridge | 145:64910690c574 | 2 | ****************************************************************************** |
AnnaBridge | 145:64910690c574 | 3 | * @file stm32l4xx_hal_tim.h |
AnnaBridge | 145:64910690c574 | 4 | * @author MCD Application Team |
AnnaBridge | 145:64910690c574 | 5 | * @brief Header file of TIM HAL module. |
AnnaBridge | 145:64910690c574 | 6 | ****************************************************************************** |
AnnaBridge | 145:64910690c574 | 7 | * @attention |
AnnaBridge | 145:64910690c574 | 8 | * |
AnnaBridge | 145:64910690c574 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
AnnaBridge | 145:64910690c574 | 10 | * |
AnnaBridge | 145:64910690c574 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 145:64910690c574 | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 145:64910690c574 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 145:64910690c574 | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 145:64910690c574 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 145:64910690c574 | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 145:64910690c574 | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 145:64910690c574 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 145:64910690c574 | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 145:64910690c574 | 20 | * without specific prior written permission. |
AnnaBridge | 145:64910690c574 | 21 | * |
AnnaBridge | 145:64910690c574 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 145:64910690c574 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 145:64910690c574 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 145:64910690c574 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 145:64910690c574 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 145:64910690c574 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 145:64910690c574 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 145:64910690c574 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 145:64910690c574 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 145:64910690c574 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 145:64910690c574 | 32 | * |
AnnaBridge | 145:64910690c574 | 33 | ****************************************************************************** |
AnnaBridge | 145:64910690c574 | 34 | */ |
AnnaBridge | 145:64910690c574 | 35 | |
AnnaBridge | 145:64910690c574 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 37 | #ifndef __STM32L4xx_HAL_TIM_H |
AnnaBridge | 145:64910690c574 | 38 | #define __STM32L4xx_HAL_TIM_H |
AnnaBridge | 145:64910690c574 | 39 | |
AnnaBridge | 145:64910690c574 | 40 | #ifdef __cplusplus |
AnnaBridge | 145:64910690c574 | 41 | extern "C" { |
AnnaBridge | 145:64910690c574 | 42 | #endif |
AnnaBridge | 145:64910690c574 | 43 | |
AnnaBridge | 145:64910690c574 | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 45 | #include "stm32l4xx_hal_def.h" |
AnnaBridge | 145:64910690c574 | 46 | |
AnnaBridge | 145:64910690c574 | 47 | /** @addtogroup STM32L4xx_HAL_Driver |
AnnaBridge | 145:64910690c574 | 48 | * @{ |
AnnaBridge | 145:64910690c574 | 49 | */ |
AnnaBridge | 145:64910690c574 | 50 | |
AnnaBridge | 145:64910690c574 | 51 | /** @addtogroup TIM |
AnnaBridge | 145:64910690c574 | 52 | * @{ |
AnnaBridge | 145:64910690c574 | 53 | */ |
AnnaBridge | 145:64910690c574 | 54 | |
AnnaBridge | 145:64910690c574 | 55 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 56 | /** @defgroup TIM_Exported_Types TIM Exported Types |
AnnaBridge | 145:64910690c574 | 57 | * @{ |
AnnaBridge | 145:64910690c574 | 58 | */ |
AnnaBridge | 145:64910690c574 | 59 | |
AnnaBridge | 145:64910690c574 | 60 | /** |
AnnaBridge | 145:64910690c574 | 61 | * @brief TIM Time base Configuration Structure definition |
AnnaBridge | 145:64910690c574 | 62 | */ |
AnnaBridge | 145:64910690c574 | 63 | typedef struct |
AnnaBridge | 145:64910690c574 | 64 | { |
AnnaBridge | 145:64910690c574 | 65 | uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
AnnaBridge | 145:64910690c574 | 66 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
AnnaBridge | 145:64910690c574 | 67 | |
AnnaBridge | 145:64910690c574 | 68 | uint32_t CounterMode; /*!< Specifies the counter mode. |
AnnaBridge | 145:64910690c574 | 69 | This parameter can be a value of @ref TIM_Counter_Mode */ |
AnnaBridge | 145:64910690c574 | 70 | |
AnnaBridge | 145:64910690c574 | 71 | uint32_t Period; /*!< Specifies the period value to be loaded into the active |
AnnaBridge | 145:64910690c574 | 72 | Auto-Reload Register at the next update event. |
AnnaBridge | 145:64910690c574 | 73 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ |
AnnaBridge | 145:64910690c574 | 74 | |
AnnaBridge | 145:64910690c574 | 75 | uint32_t ClockDivision; /*!< Specifies the clock division. |
AnnaBridge | 145:64910690c574 | 76 | This parameter can be a value of @ref TIM_ClockDivision */ |
AnnaBridge | 145:64910690c574 | 77 | |
AnnaBridge | 145:64910690c574 | 78 | uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter |
AnnaBridge | 145:64910690c574 | 79 | reaches zero, an update event is generated and counting restarts |
AnnaBridge | 145:64910690c574 | 80 | from the RCR value (N). |
AnnaBridge | 145:64910690c574 | 81 | This means in PWM mode that (N+1) corresponds to: |
AnnaBridge | 145:64910690c574 | 82 | - the number of PWM periods in edge-aligned mode |
AnnaBridge | 145:64910690c574 | 83 | - the number of half PWM period in center-aligned mode |
AnnaBridge | 145:64910690c574 | 84 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. |
AnnaBridge | 145:64910690c574 | 85 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 161:aa5281ff4a02 | 86 | |
AnnaBridge | 161:aa5281ff4a02 | 87 | uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. |
AnnaBridge | 161:aa5281ff4a02 | 88 | This parameter can be a value of @ref TIM_AutoReloadPreload */ |
AnnaBridge | 145:64910690c574 | 89 | } TIM_Base_InitTypeDef; |
AnnaBridge | 145:64910690c574 | 90 | |
AnnaBridge | 145:64910690c574 | 91 | /** |
AnnaBridge | 145:64910690c574 | 92 | * @brief TIM Output Compare Configuration Structure definition |
AnnaBridge | 145:64910690c574 | 93 | */ |
AnnaBridge | 145:64910690c574 | 94 | typedef struct |
AnnaBridge | 145:64910690c574 | 95 | { |
AnnaBridge | 145:64910690c574 | 96 | uint32_t OCMode; /*!< Specifies the TIM mode. |
AnnaBridge | 145:64910690c574 | 97 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
AnnaBridge | 145:64910690c574 | 98 | |
AnnaBridge | 145:64910690c574 | 99 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
AnnaBridge | 145:64910690c574 | 100 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
AnnaBridge | 145:64910690c574 | 101 | |
AnnaBridge | 145:64910690c574 | 102 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
AnnaBridge | 145:64910690c574 | 103 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
AnnaBridge | 145:64910690c574 | 104 | |
AnnaBridge | 145:64910690c574 | 105 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
AnnaBridge | 145:64910690c574 | 106 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
AnnaBridge | 145:64910690c574 | 107 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 145:64910690c574 | 108 | |
AnnaBridge | 145:64910690c574 | 109 | uint32_t OCFastMode; /*!< Specifies the Fast mode state. |
AnnaBridge | 145:64910690c574 | 110 | This parameter can be a value of @ref TIM_Output_Fast_State |
AnnaBridge | 145:64910690c574 | 111 | @note This parameter is valid only in PWM1 and PWM2 mode. */ |
AnnaBridge | 145:64910690c574 | 112 | |
AnnaBridge | 145:64910690c574 | 113 | |
AnnaBridge | 145:64910690c574 | 114 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
AnnaBridge | 145:64910690c574 | 115 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
AnnaBridge | 145:64910690c574 | 116 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 145:64910690c574 | 117 | |
AnnaBridge | 145:64910690c574 | 118 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
AnnaBridge | 145:64910690c574 | 119 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
AnnaBridge | 145:64910690c574 | 120 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 145:64910690c574 | 121 | } TIM_OC_InitTypeDef; |
AnnaBridge | 145:64910690c574 | 122 | |
AnnaBridge | 145:64910690c574 | 123 | /** |
AnnaBridge | 145:64910690c574 | 124 | * @brief TIM One Pulse Mode Configuration Structure definition |
AnnaBridge | 145:64910690c574 | 125 | */ |
AnnaBridge | 145:64910690c574 | 126 | typedef struct |
AnnaBridge | 145:64910690c574 | 127 | { |
AnnaBridge | 145:64910690c574 | 128 | uint32_t OCMode; /*!< Specifies the TIM mode. |
AnnaBridge | 145:64910690c574 | 129 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
AnnaBridge | 145:64910690c574 | 130 | |
AnnaBridge | 145:64910690c574 | 131 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
AnnaBridge | 145:64910690c574 | 132 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
AnnaBridge | 145:64910690c574 | 133 | |
AnnaBridge | 145:64910690c574 | 134 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
AnnaBridge | 145:64910690c574 | 135 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
AnnaBridge | 145:64910690c574 | 136 | |
AnnaBridge | 145:64910690c574 | 137 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
AnnaBridge | 145:64910690c574 | 138 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
AnnaBridge | 145:64910690c574 | 139 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 145:64910690c574 | 140 | |
AnnaBridge | 145:64910690c574 | 141 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
AnnaBridge | 145:64910690c574 | 142 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
AnnaBridge | 145:64910690c574 | 143 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 145:64910690c574 | 144 | |
AnnaBridge | 145:64910690c574 | 145 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
AnnaBridge | 145:64910690c574 | 146 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
AnnaBridge | 145:64910690c574 | 147 | @note This parameter is valid only for TIM1 and TIM8. */ |
AnnaBridge | 145:64910690c574 | 148 | |
AnnaBridge | 145:64910690c574 | 149 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 145:64910690c574 | 150 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
AnnaBridge | 145:64910690c574 | 151 | |
AnnaBridge | 145:64910690c574 | 152 | uint32_t ICSelection; /*!< Specifies the input. |
AnnaBridge | 145:64910690c574 | 153 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
AnnaBridge | 145:64910690c574 | 154 | |
AnnaBridge | 145:64910690c574 | 155 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
AnnaBridge | 145:64910690c574 | 156 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 145:64910690c574 | 157 | } TIM_OnePulse_InitTypeDef; |
AnnaBridge | 145:64910690c574 | 158 | |
AnnaBridge | 145:64910690c574 | 159 | |
AnnaBridge | 145:64910690c574 | 160 | /** |
AnnaBridge | 145:64910690c574 | 161 | * @brief TIM Input Capture Configuration Structure definition |
AnnaBridge | 145:64910690c574 | 162 | */ |
AnnaBridge | 145:64910690c574 | 163 | typedef struct |
AnnaBridge | 145:64910690c574 | 164 | { |
AnnaBridge | 145:64910690c574 | 165 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 145:64910690c574 | 166 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
AnnaBridge | 145:64910690c574 | 167 | |
AnnaBridge | 145:64910690c574 | 168 | uint32_t ICSelection; /*!< Specifies the input. |
AnnaBridge | 145:64910690c574 | 169 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
AnnaBridge | 145:64910690c574 | 170 | |
AnnaBridge | 145:64910690c574 | 171 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
AnnaBridge | 145:64910690c574 | 172 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
AnnaBridge | 145:64910690c574 | 173 | |
AnnaBridge | 145:64910690c574 | 174 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
AnnaBridge | 145:64910690c574 | 175 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 145:64910690c574 | 176 | } TIM_IC_InitTypeDef; |
AnnaBridge | 145:64910690c574 | 177 | |
AnnaBridge | 145:64910690c574 | 178 | /** |
AnnaBridge | 145:64910690c574 | 179 | * @brief TIM Encoder Configuration Structure definition |
AnnaBridge | 145:64910690c574 | 180 | */ |
AnnaBridge | 145:64910690c574 | 181 | typedef struct |
AnnaBridge | 145:64910690c574 | 182 | { |
AnnaBridge | 145:64910690c574 | 183 | uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 145:64910690c574 | 184 | This parameter can be a value of @ref TIM_Encoder_Mode */ |
AnnaBridge | 145:64910690c574 | 185 | |
AnnaBridge | 145:64910690c574 | 186 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 145:64910690c574 | 187 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
AnnaBridge | 145:64910690c574 | 188 | |
AnnaBridge | 145:64910690c574 | 189 | uint32_t IC1Selection; /*!< Specifies the input. |
AnnaBridge | 145:64910690c574 | 190 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
AnnaBridge | 145:64910690c574 | 191 | |
AnnaBridge | 145:64910690c574 | 192 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. |
AnnaBridge | 145:64910690c574 | 193 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
AnnaBridge | 145:64910690c574 | 194 | |
AnnaBridge | 145:64910690c574 | 195 | uint32_t IC1Filter; /*!< Specifies the input capture filter. |
AnnaBridge | 145:64910690c574 | 196 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 145:64910690c574 | 197 | |
AnnaBridge | 145:64910690c574 | 198 | uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 145:64910690c574 | 199 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
AnnaBridge | 145:64910690c574 | 200 | |
AnnaBridge | 145:64910690c574 | 201 | uint32_t IC2Selection; /*!< Specifies the input. |
AnnaBridge | 145:64910690c574 | 202 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
AnnaBridge | 145:64910690c574 | 203 | |
AnnaBridge | 145:64910690c574 | 204 | uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. |
AnnaBridge | 145:64910690c574 | 205 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
AnnaBridge | 145:64910690c574 | 206 | |
AnnaBridge | 145:64910690c574 | 207 | uint32_t IC2Filter; /*!< Specifies the input capture filter. |
AnnaBridge | 145:64910690c574 | 208 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 145:64910690c574 | 209 | } TIM_Encoder_InitTypeDef; |
AnnaBridge | 145:64910690c574 | 210 | |
AnnaBridge | 145:64910690c574 | 211 | |
AnnaBridge | 145:64910690c574 | 212 | /** |
AnnaBridge | 145:64910690c574 | 213 | * @brief Clock Configuration Handle Structure definition |
AnnaBridge | 145:64910690c574 | 214 | */ |
AnnaBridge | 145:64910690c574 | 215 | typedef struct |
AnnaBridge | 145:64910690c574 | 216 | { |
AnnaBridge | 145:64910690c574 | 217 | uint32_t ClockSource; /*!< TIM clock sources |
AnnaBridge | 145:64910690c574 | 218 | This parameter can be a value of @ref TIM_Clock_Source */ |
AnnaBridge | 145:64910690c574 | 219 | uint32_t ClockPolarity; /*!< TIM clock polarity |
AnnaBridge | 145:64910690c574 | 220 | This parameter can be a value of @ref TIM_Clock_Polarity */ |
AnnaBridge | 145:64910690c574 | 221 | uint32_t ClockPrescaler; /*!< TIM clock prescaler |
AnnaBridge | 145:64910690c574 | 222 | This parameter can be a value of @ref TIM_Clock_Prescaler */ |
AnnaBridge | 145:64910690c574 | 223 | uint32_t ClockFilter; /*!< TIM clock filter |
AnnaBridge | 145:64910690c574 | 224 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 145:64910690c574 | 225 | }TIM_ClockConfigTypeDef; |
AnnaBridge | 145:64910690c574 | 226 | |
AnnaBridge | 145:64910690c574 | 227 | /** |
AnnaBridge | 145:64910690c574 | 228 | * @brief Clear Input Configuration Handle Structure definition |
AnnaBridge | 145:64910690c574 | 229 | */ |
AnnaBridge | 145:64910690c574 | 230 | typedef struct |
AnnaBridge | 145:64910690c574 | 231 | { |
AnnaBridge | 145:64910690c574 | 232 | uint32_t ClearInputState; /*!< TIM clear Input state |
AnnaBridge | 145:64910690c574 | 233 | This parameter can be ENABLE or DISABLE */ |
AnnaBridge | 145:64910690c574 | 234 | uint32_t ClearInputSource; /*!< TIM clear Input sources |
AnnaBridge | 145:64910690c574 | 235 | This parameter can be a value of @ref TIM_ClearInput_Source */ |
AnnaBridge | 145:64910690c574 | 236 | uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity |
AnnaBridge | 145:64910690c574 | 237 | This parameter can be a value of @ref TIM_ClearInput_Polarity */ |
AnnaBridge | 145:64910690c574 | 238 | uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler |
AnnaBridge | 145:64910690c574 | 239 | This parameter can be a value of @ref TIM_ClearInput_Prescaler */ |
AnnaBridge | 145:64910690c574 | 240 | uint32_t ClearInputFilter; /*!< TIM Clear Input filter |
AnnaBridge | 145:64910690c574 | 241 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 145:64910690c574 | 242 | }TIM_ClearInputConfigTypeDef; |
AnnaBridge | 145:64910690c574 | 243 | |
AnnaBridge | 145:64910690c574 | 244 | /** |
AnnaBridge | 145:64910690c574 | 245 | * @brief TIM Master configuration Structure definition |
AnnaBridge | 145:64910690c574 | 246 | * @note Advanced timers provide TRGO2 internal line which is redirected |
AnnaBridge | 145:64910690c574 | 247 | * to the ADC |
AnnaBridge | 145:64910690c574 | 248 | */ |
AnnaBridge | 145:64910690c574 | 249 | typedef struct { |
AnnaBridge | 145:64910690c574 | 250 | uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection |
AnnaBridge | 145:64910690c574 | 251 | This parameter can be a value of @ref TIM_Master_Mode_Selection */ |
AnnaBridge | 145:64910690c574 | 252 | uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection |
AnnaBridge | 145:64910690c574 | 253 | This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ |
AnnaBridge | 145:64910690c574 | 254 | uint32_t MasterSlaveMode; /*!< Master/slave mode selection |
AnnaBridge | 145:64910690c574 | 255 | This parameter can be a value of @ref TIM_Master_Slave_Mode */ |
AnnaBridge | 145:64910690c574 | 256 | }TIM_MasterConfigTypeDef; |
AnnaBridge | 145:64910690c574 | 257 | |
AnnaBridge | 145:64910690c574 | 258 | /** |
AnnaBridge | 145:64910690c574 | 259 | * @brief TIM Slave configuration Structure definition |
AnnaBridge | 145:64910690c574 | 260 | */ |
AnnaBridge | 145:64910690c574 | 261 | typedef struct { |
AnnaBridge | 145:64910690c574 | 262 | uint32_t SlaveMode; /*!< Slave mode selection |
AnnaBridge | 145:64910690c574 | 263 | This parameter can be a value of @ref TIM_Slave_Mode */ |
AnnaBridge | 145:64910690c574 | 264 | uint32_t InputTrigger; /*!< Input Trigger source |
AnnaBridge | 145:64910690c574 | 265 | This parameter can be a value of @ref TIM_Trigger_Selection */ |
AnnaBridge | 145:64910690c574 | 266 | uint32_t TriggerPolarity; /*!< Input Trigger polarity |
AnnaBridge | 145:64910690c574 | 267 | This parameter can be a value of @ref TIM_Trigger_Polarity */ |
AnnaBridge | 145:64910690c574 | 268 | uint32_t TriggerPrescaler; /*!< Input trigger prescaler |
AnnaBridge | 145:64910690c574 | 269 | This parameter can be a value of @ref TIM_Trigger_Prescaler */ |
AnnaBridge | 145:64910690c574 | 270 | uint32_t TriggerFilter; /*!< Input trigger filter |
AnnaBridge | 145:64910690c574 | 271 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 145:64910690c574 | 272 | |
AnnaBridge | 145:64910690c574 | 273 | }TIM_SlaveConfigTypeDef; |
AnnaBridge | 145:64910690c574 | 274 | |
AnnaBridge | 145:64910690c574 | 275 | /** |
AnnaBridge | 145:64910690c574 | 276 | * @brief TIM Break input(s) and Dead time configuration Structure definition |
AnnaBridge | 145:64910690c574 | 277 | * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable |
AnnaBridge | 145:64910690c574 | 278 | * filter and polarity. |
AnnaBridge | 145:64910690c574 | 279 | */ |
AnnaBridge | 145:64910690c574 | 280 | typedef struct |
AnnaBridge | 145:64910690c574 | 281 | { |
AnnaBridge | 145:64910690c574 | 282 | uint32_t OffStateRunMode; /*!< TIM off state in run mode |
AnnaBridge | 145:64910690c574 | 283 | This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ |
AnnaBridge | 145:64910690c574 | 284 | uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode |
AnnaBridge | 145:64910690c574 | 285 | This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ |
AnnaBridge | 145:64910690c574 | 286 | uint32_t LockLevel; /*!< TIM Lock level |
AnnaBridge | 145:64910690c574 | 287 | This parameter can be a value of @ref TIM_Lock_level */ |
AnnaBridge | 145:64910690c574 | 288 | uint32_t DeadTime; /*!< TIM dead Time |
AnnaBridge | 145:64910690c574 | 289 | This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ |
AnnaBridge | 145:64910690c574 | 290 | uint32_t BreakState; /*!< TIM Break State |
AnnaBridge | 145:64910690c574 | 291 | This parameter can be a value of @ref TIM_Break_Input_enable_disable */ |
AnnaBridge | 145:64910690c574 | 292 | uint32_t BreakPolarity; /*!< TIM Break input polarity |
AnnaBridge | 145:64910690c574 | 293 | This parameter can be a value of @ref TIM_Break_Polarity */ |
AnnaBridge | 145:64910690c574 | 294 | uint32_t BreakFilter; /*!< Specifies the break input filter. |
AnnaBridge | 145:64910690c574 | 295 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 145:64910690c574 | 296 | uint32_t Break2State; /*!< TIM Break2 State |
AnnaBridge | 145:64910690c574 | 297 | This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ |
AnnaBridge | 145:64910690c574 | 298 | uint32_t Break2Polarity; /*!< TIM Break2 input polarity |
AnnaBridge | 145:64910690c574 | 299 | This parameter can be a value of @ref TIM_Break2_Polarity */ |
AnnaBridge | 145:64910690c574 | 300 | uint32_t Break2Filter; /*!< TIM break2 input filter. |
AnnaBridge | 145:64910690c574 | 301 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 145:64910690c574 | 302 | uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state |
AnnaBridge | 145:64910690c574 | 303 | This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ |
AnnaBridge | 145:64910690c574 | 304 | } TIM_BreakDeadTimeConfigTypeDef; |
AnnaBridge | 145:64910690c574 | 305 | |
AnnaBridge | 145:64910690c574 | 306 | /** |
AnnaBridge | 145:64910690c574 | 307 | * @brief HAL State structures definition |
AnnaBridge | 145:64910690c574 | 308 | */ |
AnnaBridge | 145:64910690c574 | 309 | typedef enum |
AnnaBridge | 145:64910690c574 | 310 | { |
AnnaBridge | 145:64910690c574 | 311 | HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ |
AnnaBridge | 145:64910690c574 | 312 | HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ |
AnnaBridge | 145:64910690c574 | 313 | HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ |
AnnaBridge | 145:64910690c574 | 314 | HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ |
AnnaBridge | 145:64910690c574 | 315 | HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ |
AnnaBridge | 145:64910690c574 | 316 | }HAL_TIM_StateTypeDef; |
AnnaBridge | 145:64910690c574 | 317 | |
AnnaBridge | 145:64910690c574 | 318 | /** |
AnnaBridge | 145:64910690c574 | 319 | * @brief HAL Active channel structures definition |
AnnaBridge | 145:64910690c574 | 320 | */ |
AnnaBridge | 145:64910690c574 | 321 | typedef enum |
AnnaBridge | 145:64910690c574 | 322 | { |
AnnaBridge | 145:64910690c574 | 323 | HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ |
AnnaBridge | 145:64910690c574 | 324 | HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ |
AnnaBridge | 145:64910690c574 | 325 | HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ |
AnnaBridge | 145:64910690c574 | 326 | HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ |
AnnaBridge | 145:64910690c574 | 327 | HAL_TIM_ACTIVE_CHANNEL_5 = 0x10, /*!< The active channel is 5 */ |
AnnaBridge | 145:64910690c574 | 328 | HAL_TIM_ACTIVE_CHANNEL_6 = 0x20, /*!< The active channel is 6 */ |
AnnaBridge | 145:64910690c574 | 329 | HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ |
AnnaBridge | 145:64910690c574 | 330 | }HAL_TIM_ActiveChannel; |
AnnaBridge | 145:64910690c574 | 331 | |
AnnaBridge | 145:64910690c574 | 332 | /** |
AnnaBridge | 145:64910690c574 | 333 | * @brief TIM Time Base Handle Structure definition |
AnnaBridge | 145:64910690c574 | 334 | */ |
AnnaBridge | 145:64910690c574 | 335 | typedef struct |
AnnaBridge | 145:64910690c574 | 336 | { |
AnnaBridge | 145:64910690c574 | 337 | TIM_TypeDef *Instance; /*!< Register base address */ |
AnnaBridge | 145:64910690c574 | 338 | TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ |
AnnaBridge | 145:64910690c574 | 339 | HAL_TIM_ActiveChannel Channel; /*!< Active channel */ |
AnnaBridge | 145:64910690c574 | 340 | DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array |
AnnaBridge | 145:64910690c574 | 341 | This array is accessed by a @ref DMA_Handle_index */ |
AnnaBridge | 145:64910690c574 | 342 | HAL_LockTypeDef Lock; /*!< Locking object */ |
AnnaBridge | 145:64910690c574 | 343 | __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ |
AnnaBridge | 145:64910690c574 | 344 | }TIM_HandleTypeDef; |
AnnaBridge | 145:64910690c574 | 345 | |
AnnaBridge | 145:64910690c574 | 346 | /** |
AnnaBridge | 145:64910690c574 | 347 | * @} |
AnnaBridge | 145:64910690c574 | 348 | */ |
AnnaBridge | 145:64910690c574 | 349 | /* End of exported types -----------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 350 | |
AnnaBridge | 145:64910690c574 | 351 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 352 | /** @defgroup TIM_Exported_Constants TIM Exported Constants |
AnnaBridge | 145:64910690c574 | 353 | * @{ |
AnnaBridge | 145:64910690c574 | 354 | */ |
AnnaBridge | 145:64910690c574 | 355 | |
AnnaBridge | 145:64910690c574 | 356 | /** @defgroup TIM_ClearInput_Source TIM Clear Input Source |
AnnaBridge | 145:64910690c574 | 357 | * @{ |
AnnaBridge | 145:64910690c574 | 358 | */ |
AnnaBridge | 145:64910690c574 | 359 | #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) |
AnnaBridge | 145:64910690c574 | 360 | #define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002) |
AnnaBridge | 145:64910690c574 | 361 | #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 362 | /** |
AnnaBridge | 145:64910690c574 | 363 | * @} |
AnnaBridge | 145:64910690c574 | 364 | */ |
AnnaBridge | 145:64910690c574 | 365 | |
AnnaBridge | 145:64910690c574 | 366 | /** @defgroup TIM_DMA_Base_address TIM DMA Base Address |
AnnaBridge | 145:64910690c574 | 367 | * @{ |
AnnaBridge | 145:64910690c574 | 368 | */ |
AnnaBridge | 145:64910690c574 | 369 | #define TIM_DMABASE_CR1 (0x00000000) |
AnnaBridge | 145:64910690c574 | 370 | #define TIM_DMABASE_CR2 (0x00000001) |
AnnaBridge | 145:64910690c574 | 371 | #define TIM_DMABASE_SMCR (0x00000002) |
AnnaBridge | 145:64910690c574 | 372 | #define TIM_DMABASE_DIER (0x00000003) |
AnnaBridge | 145:64910690c574 | 373 | #define TIM_DMABASE_SR (0x00000004) |
AnnaBridge | 145:64910690c574 | 374 | #define TIM_DMABASE_EGR (0x00000005) |
AnnaBridge | 145:64910690c574 | 375 | #define TIM_DMABASE_CCMR1 (0x00000006) |
AnnaBridge | 145:64910690c574 | 376 | #define TIM_DMABASE_CCMR2 (0x00000007) |
AnnaBridge | 145:64910690c574 | 377 | #define TIM_DMABASE_CCER (0x00000008) |
AnnaBridge | 145:64910690c574 | 378 | #define TIM_DMABASE_CNT (0x00000009) |
AnnaBridge | 145:64910690c574 | 379 | #define TIM_DMABASE_PSC (0x0000000A) |
AnnaBridge | 145:64910690c574 | 380 | #define TIM_DMABASE_ARR (0x0000000B) |
AnnaBridge | 145:64910690c574 | 381 | #define TIM_DMABASE_RCR (0x0000000C) |
AnnaBridge | 145:64910690c574 | 382 | #define TIM_DMABASE_CCR1 (0x0000000D) |
AnnaBridge | 145:64910690c574 | 383 | #define TIM_DMABASE_CCR2 (0x0000000E) |
AnnaBridge | 145:64910690c574 | 384 | #define TIM_DMABASE_CCR3 (0x0000000F) |
AnnaBridge | 145:64910690c574 | 385 | #define TIM_DMABASE_CCR4 (0x00000010) |
AnnaBridge | 145:64910690c574 | 386 | #define TIM_DMABASE_BDTR (0x00000011) |
AnnaBridge | 145:64910690c574 | 387 | #define TIM_DMABASE_DCR (0x00000012) |
AnnaBridge | 145:64910690c574 | 388 | #define TIM_DMABASE_DMAR (0x00000013) |
AnnaBridge | 145:64910690c574 | 389 | #define TIM_DMABASE_OR1 (0x00000014) |
AnnaBridge | 145:64910690c574 | 390 | #define TIM_DMABASE_CCMR3 (0x00000015) |
AnnaBridge | 145:64910690c574 | 391 | #define TIM_DMABASE_CCR5 (0x00000016) |
AnnaBridge | 145:64910690c574 | 392 | #define TIM_DMABASE_CCR6 (0x00000017) |
AnnaBridge | 145:64910690c574 | 393 | #define TIM_DMABASE_OR2 (0x00000018) |
AnnaBridge | 145:64910690c574 | 394 | #define TIM_DMABASE_OR3 (0x00000019) |
AnnaBridge | 145:64910690c574 | 395 | /** |
AnnaBridge | 145:64910690c574 | 396 | * @} |
AnnaBridge | 145:64910690c574 | 397 | */ |
AnnaBridge | 145:64910690c574 | 398 | |
AnnaBridge | 145:64910690c574 | 399 | /** @defgroup TIM_Event_Source TIM Extended Event Source |
AnnaBridge | 145:64910690c574 | 400 | * @{ |
AnnaBridge | 145:64910690c574 | 401 | */ |
AnnaBridge | 145:64910690c574 | 402 | #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ |
AnnaBridge | 145:64910690c574 | 403 | #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ |
AnnaBridge | 145:64910690c574 | 404 | #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ |
AnnaBridge | 145:64910690c574 | 405 | #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ |
AnnaBridge | 145:64910690c574 | 406 | #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ |
AnnaBridge | 145:64910690c574 | 407 | #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ |
AnnaBridge | 145:64910690c574 | 408 | #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ |
AnnaBridge | 145:64910690c574 | 409 | #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ |
AnnaBridge | 145:64910690c574 | 410 | #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ |
AnnaBridge | 145:64910690c574 | 411 | /** |
AnnaBridge | 145:64910690c574 | 412 | * @} |
AnnaBridge | 145:64910690c574 | 413 | */ |
AnnaBridge | 145:64910690c574 | 414 | |
AnnaBridge | 145:64910690c574 | 415 | /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity |
AnnaBridge | 145:64910690c574 | 416 | * @{ |
AnnaBridge | 145:64910690c574 | 417 | */ |
AnnaBridge | 145:64910690c574 | 418 | #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ |
AnnaBridge | 145:64910690c574 | 419 | #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ |
AnnaBridge | 145:64910690c574 | 420 | #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ |
AnnaBridge | 145:64910690c574 | 421 | /** |
AnnaBridge | 145:64910690c574 | 422 | * @} |
AnnaBridge | 145:64910690c574 | 423 | */ |
AnnaBridge | 145:64910690c574 | 424 | |
AnnaBridge | 145:64910690c574 | 425 | /** @defgroup TIM_ETR_Polarity TIM ETR Polarity |
AnnaBridge | 145:64910690c574 | 426 | * @{ |
AnnaBridge | 145:64910690c574 | 427 | */ |
AnnaBridge | 145:64910690c574 | 428 | #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ |
AnnaBridge | 145:64910690c574 | 429 | #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ |
AnnaBridge | 145:64910690c574 | 430 | /** |
AnnaBridge | 145:64910690c574 | 431 | * @} |
AnnaBridge | 145:64910690c574 | 432 | */ |
AnnaBridge | 145:64910690c574 | 433 | |
AnnaBridge | 145:64910690c574 | 434 | /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler |
AnnaBridge | 145:64910690c574 | 435 | * @{ |
AnnaBridge | 145:64910690c574 | 436 | */ |
AnnaBridge | 145:64910690c574 | 437 | #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ |
AnnaBridge | 145:64910690c574 | 438 | #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ |
AnnaBridge | 145:64910690c574 | 439 | #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ |
AnnaBridge | 145:64910690c574 | 440 | #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ |
AnnaBridge | 145:64910690c574 | 441 | /** |
AnnaBridge | 145:64910690c574 | 442 | * @} |
AnnaBridge | 145:64910690c574 | 443 | */ |
AnnaBridge | 145:64910690c574 | 444 | |
AnnaBridge | 145:64910690c574 | 445 | /** @defgroup TIM_Counter_Mode TIM Counter Mode |
AnnaBridge | 145:64910690c574 | 446 | * @{ |
AnnaBridge | 145:64910690c574 | 447 | */ |
AnnaBridge | 145:64910690c574 | 448 | #define TIM_COUNTERMODE_UP ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 449 | #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR |
AnnaBridge | 145:64910690c574 | 450 | #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 |
AnnaBridge | 145:64910690c574 | 451 | #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 |
AnnaBridge | 145:64910690c574 | 452 | #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS |
AnnaBridge | 145:64910690c574 | 453 | /** |
AnnaBridge | 145:64910690c574 | 454 | * @} |
AnnaBridge | 145:64910690c574 | 455 | */ |
AnnaBridge | 145:64910690c574 | 456 | |
AnnaBridge | 145:64910690c574 | 457 | /** @defgroup TIM_ClockDivision TIM Clock Division |
AnnaBridge | 145:64910690c574 | 458 | * @{ |
AnnaBridge | 145:64910690c574 | 459 | */ |
AnnaBridge | 145:64910690c574 | 460 | #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 461 | #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) |
AnnaBridge | 145:64910690c574 | 462 | #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) |
AnnaBridge | 145:64910690c574 | 463 | /** |
AnnaBridge | 145:64910690c574 | 464 | * @} |
AnnaBridge | 145:64910690c574 | 465 | */ |
AnnaBridge | 145:64910690c574 | 466 | |
AnnaBridge | 161:aa5281ff4a02 | 467 | /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload |
AnnaBridge | 161:aa5281ff4a02 | 468 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 469 | */ |
AnnaBridge | 161:aa5281ff4a02 | 470 | #define TIM_AUTORELOAD_PRELOAD_DISABLE ((uint32_t)0x0000) /*!< TIMx_ARR register is not buffered */ |
AnnaBridge | 161:aa5281ff4a02 | 471 | #define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */ |
AnnaBridge | 161:aa5281ff4a02 | 472 | /** |
AnnaBridge | 161:aa5281ff4a02 | 473 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 474 | */ |
AnnaBridge | 161:aa5281ff4a02 | 475 | |
AnnaBridge | 145:64910690c574 | 476 | /** @defgroup TIM_Output_Compare_State TIM Output Compare State |
AnnaBridge | 145:64910690c574 | 477 | * @{ |
AnnaBridge | 145:64910690c574 | 478 | */ |
AnnaBridge | 145:64910690c574 | 479 | #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 480 | #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) |
AnnaBridge | 145:64910690c574 | 481 | /** |
AnnaBridge | 145:64910690c574 | 482 | * @} |
AnnaBridge | 145:64910690c574 | 483 | */ |
AnnaBridge | 145:64910690c574 | 484 | |
AnnaBridge | 161:aa5281ff4a02 | 485 | /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State |
AnnaBridge | 161:aa5281ff4a02 | 486 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 487 | */ |
AnnaBridge | 161:aa5281ff4a02 | 488 | #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) |
AnnaBridge | 161:aa5281ff4a02 | 489 | #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) |
AnnaBridge | 161:aa5281ff4a02 | 490 | /** |
AnnaBridge | 161:aa5281ff4a02 | 491 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 492 | */ |
AnnaBridge | 161:aa5281ff4a02 | 493 | |
AnnaBridge | 145:64910690c574 | 494 | /** @defgroup TIM_Output_Fast_State TIM Output Fast State |
AnnaBridge | 145:64910690c574 | 495 | * @{ |
AnnaBridge | 145:64910690c574 | 496 | */ |
AnnaBridge | 145:64910690c574 | 497 | #define TIM_OCFAST_DISABLE ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 498 | #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) |
AnnaBridge | 145:64910690c574 | 499 | /** |
AnnaBridge | 145:64910690c574 | 500 | * @} |
AnnaBridge | 145:64910690c574 | 501 | */ |
AnnaBridge | 145:64910690c574 | 502 | |
AnnaBridge | 145:64910690c574 | 503 | /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity |
AnnaBridge | 145:64910690c574 | 504 | * @{ |
AnnaBridge | 145:64910690c574 | 505 | */ |
AnnaBridge | 145:64910690c574 | 506 | #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 507 | #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) |
AnnaBridge | 145:64910690c574 | 508 | /** |
AnnaBridge | 145:64910690c574 | 509 | * @} |
AnnaBridge | 145:64910690c574 | 510 | */ |
AnnaBridge | 145:64910690c574 | 511 | |
AnnaBridge | 145:64910690c574 | 512 | /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity |
AnnaBridge | 145:64910690c574 | 513 | * @{ |
AnnaBridge | 145:64910690c574 | 514 | */ |
AnnaBridge | 145:64910690c574 | 515 | #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 516 | #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) |
AnnaBridge | 145:64910690c574 | 517 | /** |
AnnaBridge | 145:64910690c574 | 518 | * @} |
AnnaBridge | 145:64910690c574 | 519 | */ |
AnnaBridge | 145:64910690c574 | 520 | |
AnnaBridge | 145:64910690c574 | 521 | /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State |
AnnaBridge | 145:64910690c574 | 522 | * @{ |
AnnaBridge | 145:64910690c574 | 523 | */ |
AnnaBridge | 145:64910690c574 | 524 | #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) |
AnnaBridge | 145:64910690c574 | 525 | #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 526 | /** |
AnnaBridge | 145:64910690c574 | 527 | * @} |
AnnaBridge | 145:64910690c574 | 528 | */ |
AnnaBridge | 145:64910690c574 | 529 | |
AnnaBridge | 145:64910690c574 | 530 | /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State |
AnnaBridge | 145:64910690c574 | 531 | * @{ |
AnnaBridge | 145:64910690c574 | 532 | */ |
AnnaBridge | 145:64910690c574 | 533 | #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) |
AnnaBridge | 145:64910690c574 | 534 | #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 535 | /** |
AnnaBridge | 145:64910690c574 | 536 | * @} |
AnnaBridge | 145:64910690c574 | 537 | */ |
AnnaBridge | 145:64910690c574 | 538 | |
AnnaBridge | 145:64910690c574 | 539 | /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity |
AnnaBridge | 145:64910690c574 | 540 | * @{ |
AnnaBridge | 145:64910690c574 | 541 | */ |
AnnaBridge | 145:64910690c574 | 542 | #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING |
AnnaBridge | 145:64910690c574 | 543 | #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING |
AnnaBridge | 145:64910690c574 | 544 | #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE |
AnnaBridge | 145:64910690c574 | 545 | /** |
AnnaBridge | 145:64910690c574 | 546 | * @} |
AnnaBridge | 145:64910690c574 | 547 | */ |
AnnaBridge | 145:64910690c574 | 548 | |
AnnaBridge | 145:64910690c574 | 549 | /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection |
AnnaBridge | 145:64910690c574 | 550 | * @{ |
AnnaBridge | 145:64910690c574 | 551 | */ |
AnnaBridge | 145:64910690c574 | 552 | #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
AnnaBridge | 145:64910690c574 | 553 | connected to IC1, IC2, IC3 or IC4, respectively */ |
AnnaBridge | 145:64910690c574 | 554 | #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
AnnaBridge | 145:64910690c574 | 555 | connected to IC2, IC1, IC4 or IC3, respectively */ |
AnnaBridge | 145:64910690c574 | 556 | #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ |
AnnaBridge | 145:64910690c574 | 557 | /** |
AnnaBridge | 145:64910690c574 | 558 | * @} |
AnnaBridge | 145:64910690c574 | 559 | */ |
AnnaBridge | 145:64910690c574 | 560 | |
AnnaBridge | 145:64910690c574 | 561 | /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler |
AnnaBridge | 145:64910690c574 | 562 | * @{ |
AnnaBridge | 145:64910690c574 | 563 | */ |
AnnaBridge | 145:64910690c574 | 564 | #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ |
AnnaBridge | 145:64910690c574 | 565 | #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ |
AnnaBridge | 145:64910690c574 | 566 | #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ |
AnnaBridge | 145:64910690c574 | 567 | #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ |
AnnaBridge | 145:64910690c574 | 568 | /** |
AnnaBridge | 145:64910690c574 | 569 | * @} |
AnnaBridge | 145:64910690c574 | 570 | */ |
AnnaBridge | 145:64910690c574 | 571 | |
AnnaBridge | 145:64910690c574 | 572 | /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode |
AnnaBridge | 145:64910690c574 | 573 | * @{ |
AnnaBridge | 145:64910690c574 | 574 | */ |
AnnaBridge | 145:64910690c574 | 575 | #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) |
AnnaBridge | 145:64910690c574 | 576 | #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 577 | /** |
AnnaBridge | 145:64910690c574 | 578 | * @} |
AnnaBridge | 145:64910690c574 | 579 | */ |
AnnaBridge | 145:64910690c574 | 580 | |
AnnaBridge | 145:64910690c574 | 581 | /** @defgroup TIM_Encoder_Mode TIM Encoder Mode |
AnnaBridge | 145:64910690c574 | 582 | * @{ |
AnnaBridge | 145:64910690c574 | 583 | */ |
AnnaBridge | 145:64910690c574 | 584 | #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) |
AnnaBridge | 145:64910690c574 | 585 | #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) |
AnnaBridge | 145:64910690c574 | 586 | #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) |
AnnaBridge | 145:64910690c574 | 587 | /** |
AnnaBridge | 145:64910690c574 | 588 | * @} |
AnnaBridge | 145:64910690c574 | 589 | */ |
AnnaBridge | 145:64910690c574 | 590 | |
AnnaBridge | 145:64910690c574 | 591 | /** @defgroup TIM_Interrupt_definition TIM interrupt Definition |
AnnaBridge | 145:64910690c574 | 592 | * @{ |
AnnaBridge | 145:64910690c574 | 593 | */ |
AnnaBridge | 145:64910690c574 | 594 | #define TIM_IT_UPDATE (TIM_DIER_UIE) |
AnnaBridge | 145:64910690c574 | 595 | #define TIM_IT_CC1 (TIM_DIER_CC1IE) |
AnnaBridge | 145:64910690c574 | 596 | #define TIM_IT_CC2 (TIM_DIER_CC2IE) |
AnnaBridge | 145:64910690c574 | 597 | #define TIM_IT_CC3 (TIM_DIER_CC3IE) |
AnnaBridge | 145:64910690c574 | 598 | #define TIM_IT_CC4 (TIM_DIER_CC4IE) |
AnnaBridge | 145:64910690c574 | 599 | #define TIM_IT_COM (TIM_DIER_COMIE) |
AnnaBridge | 145:64910690c574 | 600 | #define TIM_IT_TRIGGER (TIM_DIER_TIE) |
AnnaBridge | 145:64910690c574 | 601 | #define TIM_IT_BREAK (TIM_DIER_BIE) |
AnnaBridge | 145:64910690c574 | 602 | /** |
AnnaBridge | 145:64910690c574 | 603 | * @} |
AnnaBridge | 145:64910690c574 | 604 | */ |
AnnaBridge | 145:64910690c574 | 605 | |
AnnaBridge | 161:aa5281ff4a02 | 606 | /** @defgroup TIM_Commutation_Source TIM Commutation Source |
AnnaBridge | 145:64910690c574 | 607 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 608 | */ |
AnnaBridge | 145:64910690c574 | 609 | #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) |
AnnaBridge | 145:64910690c574 | 610 | #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 611 | /** |
AnnaBridge | 145:64910690c574 | 612 | * @} |
AnnaBridge | 145:64910690c574 | 613 | */ |
AnnaBridge | 145:64910690c574 | 614 | |
AnnaBridge | 145:64910690c574 | 615 | /** @defgroup TIM_DMA_sources TIM DMA Sources |
AnnaBridge | 145:64910690c574 | 616 | * @{ |
AnnaBridge | 145:64910690c574 | 617 | */ |
AnnaBridge | 145:64910690c574 | 618 | #define TIM_DMA_UPDATE (TIM_DIER_UDE) |
AnnaBridge | 145:64910690c574 | 619 | #define TIM_DMA_CC1 (TIM_DIER_CC1DE) |
AnnaBridge | 145:64910690c574 | 620 | #define TIM_DMA_CC2 (TIM_DIER_CC2DE) |
AnnaBridge | 145:64910690c574 | 621 | #define TIM_DMA_CC3 (TIM_DIER_CC3DE) |
AnnaBridge | 145:64910690c574 | 622 | #define TIM_DMA_CC4 (TIM_DIER_CC4DE) |
AnnaBridge | 145:64910690c574 | 623 | #define TIM_DMA_COM (TIM_DIER_COMDE) |
AnnaBridge | 145:64910690c574 | 624 | #define TIM_DMA_TRIGGER (TIM_DIER_TDE) |
AnnaBridge | 145:64910690c574 | 625 | /** |
AnnaBridge | 145:64910690c574 | 626 | * @} |
AnnaBridge | 145:64910690c574 | 627 | */ |
AnnaBridge | 145:64910690c574 | 628 | |
AnnaBridge | 145:64910690c574 | 629 | /** @defgroup TIM_Flag_definition TIM Flag Definition |
AnnaBridge | 145:64910690c574 | 630 | * @{ |
AnnaBridge | 145:64910690c574 | 631 | */ |
AnnaBridge | 145:64910690c574 | 632 | #define TIM_FLAG_UPDATE (TIM_SR_UIF) |
AnnaBridge | 145:64910690c574 | 633 | #define TIM_FLAG_CC1 (TIM_SR_CC1IF) |
AnnaBridge | 145:64910690c574 | 634 | #define TIM_FLAG_CC2 (TIM_SR_CC2IF) |
AnnaBridge | 145:64910690c574 | 635 | #define TIM_FLAG_CC3 (TIM_SR_CC3IF) |
AnnaBridge | 145:64910690c574 | 636 | #define TIM_FLAG_CC4 (TIM_SR_CC4IF) |
AnnaBridge | 145:64910690c574 | 637 | #define TIM_FLAG_CC5 (TIM_SR_CC5IF) |
AnnaBridge | 145:64910690c574 | 638 | #define TIM_FLAG_CC6 (TIM_SR_CC6IF) |
AnnaBridge | 145:64910690c574 | 639 | #define TIM_FLAG_COM (TIM_SR_COMIF) |
AnnaBridge | 145:64910690c574 | 640 | #define TIM_FLAG_TRIGGER (TIM_SR_TIF) |
AnnaBridge | 145:64910690c574 | 641 | #define TIM_FLAG_BREAK (TIM_SR_BIF) |
AnnaBridge | 145:64910690c574 | 642 | #define TIM_FLAG_BREAK2 (TIM_SR_B2IF) |
AnnaBridge | 145:64910690c574 | 643 | #define TIM_FLAG_SYSTEM_BREAK (TIM_SR_SBIF) |
AnnaBridge | 145:64910690c574 | 644 | #define TIM_FLAG_CC1OF (TIM_SR_CC1OF) |
AnnaBridge | 145:64910690c574 | 645 | #define TIM_FLAG_CC2OF (TIM_SR_CC2OF) |
AnnaBridge | 145:64910690c574 | 646 | #define TIM_FLAG_CC3OF (TIM_SR_CC3OF) |
AnnaBridge | 145:64910690c574 | 647 | #define TIM_FLAG_CC4OF (TIM_SR_CC4OF) |
AnnaBridge | 145:64910690c574 | 648 | /** |
AnnaBridge | 145:64910690c574 | 649 | * @} |
AnnaBridge | 145:64910690c574 | 650 | */ |
AnnaBridge | 145:64910690c574 | 651 | |
AnnaBridge | 145:64910690c574 | 652 | /** @defgroup TIM_Channel TIM Channel |
AnnaBridge | 145:64910690c574 | 653 | * @{ |
AnnaBridge | 145:64910690c574 | 654 | */ |
AnnaBridge | 145:64910690c574 | 655 | #define TIM_CHANNEL_1 ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 656 | #define TIM_CHANNEL_2 ((uint32_t)0x0004) |
AnnaBridge | 145:64910690c574 | 657 | #define TIM_CHANNEL_3 ((uint32_t)0x0008) |
AnnaBridge | 145:64910690c574 | 658 | #define TIM_CHANNEL_4 ((uint32_t)0x000C) |
AnnaBridge | 145:64910690c574 | 659 | #define TIM_CHANNEL_5 ((uint32_t)0x0010) |
AnnaBridge | 145:64910690c574 | 660 | #define TIM_CHANNEL_6 ((uint32_t)0x0014) |
AnnaBridge | 145:64910690c574 | 661 | #define TIM_CHANNEL_ALL ((uint32_t)0x003C) |
AnnaBridge | 145:64910690c574 | 662 | /** |
AnnaBridge | 145:64910690c574 | 663 | * @} |
AnnaBridge | 145:64910690c574 | 664 | */ |
AnnaBridge | 145:64910690c574 | 665 | |
AnnaBridge | 145:64910690c574 | 666 | /** @defgroup TIM_Clock_Source TIM Clock Source |
AnnaBridge | 145:64910690c574 | 667 | * @{ |
AnnaBridge | 145:64910690c574 | 668 | */ |
AnnaBridge | 161:aa5281ff4a02 | 669 | #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) |
AnnaBridge | 161:aa5281ff4a02 | 670 | #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) |
AnnaBridge | 161:aa5281ff4a02 | 671 | #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) |
AnnaBridge | 161:aa5281ff4a02 | 672 | #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) |
AnnaBridge | 161:aa5281ff4a02 | 673 | #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) |
AnnaBridge | 161:aa5281ff4a02 | 674 | #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) |
AnnaBridge | 161:aa5281ff4a02 | 675 | #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) |
AnnaBridge | 161:aa5281ff4a02 | 676 | #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) |
AnnaBridge | 161:aa5281ff4a02 | 677 | #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) |
AnnaBridge | 161:aa5281ff4a02 | 678 | #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) |
AnnaBridge | 145:64910690c574 | 679 | /** |
AnnaBridge | 145:64910690c574 | 680 | * @} |
AnnaBridge | 145:64910690c574 | 681 | */ |
AnnaBridge | 145:64910690c574 | 682 | |
AnnaBridge | 145:64910690c574 | 683 | /** @defgroup TIM_Clock_Polarity TIM Clock Polarity |
AnnaBridge | 145:64910690c574 | 684 | * @{ |
AnnaBridge | 145:64910690c574 | 685 | */ |
AnnaBridge | 145:64910690c574 | 686 | #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ |
AnnaBridge | 145:64910690c574 | 687 | #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ |
AnnaBridge | 145:64910690c574 | 688 | #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ |
AnnaBridge | 145:64910690c574 | 689 | #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ |
AnnaBridge | 145:64910690c574 | 690 | #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ |
AnnaBridge | 145:64910690c574 | 691 | /** |
AnnaBridge | 145:64910690c574 | 692 | * @} |
AnnaBridge | 145:64910690c574 | 693 | */ |
AnnaBridge | 145:64910690c574 | 694 | |
AnnaBridge | 145:64910690c574 | 695 | /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler |
AnnaBridge | 145:64910690c574 | 696 | * @{ |
AnnaBridge | 145:64910690c574 | 697 | */ |
AnnaBridge | 145:64910690c574 | 698 | #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
AnnaBridge | 145:64910690c574 | 699 | #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ |
AnnaBridge | 145:64910690c574 | 700 | #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ |
AnnaBridge | 145:64910690c574 | 701 | #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ |
AnnaBridge | 145:64910690c574 | 702 | /** |
AnnaBridge | 145:64910690c574 | 703 | * @} |
AnnaBridge | 145:64910690c574 | 704 | */ |
AnnaBridge | 145:64910690c574 | 705 | |
AnnaBridge | 145:64910690c574 | 706 | /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity |
AnnaBridge | 145:64910690c574 | 707 | * @{ |
AnnaBridge | 145:64910690c574 | 708 | */ |
AnnaBridge | 145:64910690c574 | 709 | #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ |
AnnaBridge | 145:64910690c574 | 710 | #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ |
AnnaBridge | 145:64910690c574 | 711 | /** |
AnnaBridge | 145:64910690c574 | 712 | * @} |
AnnaBridge | 145:64910690c574 | 713 | */ |
AnnaBridge | 145:64910690c574 | 714 | |
AnnaBridge | 145:64910690c574 | 715 | /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler |
AnnaBridge | 145:64910690c574 | 716 | * @{ |
AnnaBridge | 145:64910690c574 | 717 | */ |
AnnaBridge | 145:64910690c574 | 718 | #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
AnnaBridge | 145:64910690c574 | 719 | #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ |
AnnaBridge | 145:64910690c574 | 720 | #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ |
AnnaBridge | 145:64910690c574 | 721 | #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ |
AnnaBridge | 145:64910690c574 | 722 | /** |
AnnaBridge | 145:64910690c574 | 723 | * @} |
AnnaBridge | 145:64910690c574 | 724 | */ |
AnnaBridge | 145:64910690c574 | 725 | |
AnnaBridge | 145:64910690c574 | 726 | /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state |
AnnaBridge | 145:64910690c574 | 727 | * @{ |
AnnaBridge | 145:64910690c574 | 728 | */ |
AnnaBridge | 145:64910690c574 | 729 | #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) |
AnnaBridge | 145:64910690c574 | 730 | #define TIM_OSSR_DISABLE ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 731 | /** |
AnnaBridge | 145:64910690c574 | 732 | * @} |
AnnaBridge | 145:64910690c574 | 733 | */ |
AnnaBridge | 145:64910690c574 | 734 | |
AnnaBridge | 145:64910690c574 | 735 | /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state |
AnnaBridge | 145:64910690c574 | 736 | * @{ |
AnnaBridge | 145:64910690c574 | 737 | */ |
AnnaBridge | 145:64910690c574 | 738 | #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) |
AnnaBridge | 145:64910690c574 | 739 | #define TIM_OSSI_DISABLE ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 740 | /** |
AnnaBridge | 145:64910690c574 | 741 | * @} |
AnnaBridge | 145:64910690c574 | 742 | */ |
AnnaBridge | 145:64910690c574 | 743 | /** @defgroup TIM_Lock_level TIM Lock level |
AnnaBridge | 145:64910690c574 | 744 | * @{ |
AnnaBridge | 145:64910690c574 | 745 | */ |
AnnaBridge | 145:64910690c574 | 746 | #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 747 | #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) |
AnnaBridge | 145:64910690c574 | 748 | #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) |
AnnaBridge | 145:64910690c574 | 749 | #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) |
AnnaBridge | 145:64910690c574 | 750 | /** |
AnnaBridge | 145:64910690c574 | 751 | * @} |
AnnaBridge | 145:64910690c574 | 752 | */ |
AnnaBridge | 145:64910690c574 | 753 | |
AnnaBridge | 145:64910690c574 | 754 | /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable |
AnnaBridge | 145:64910690c574 | 755 | * @{ |
AnnaBridge | 145:64910690c574 | 756 | */ |
AnnaBridge | 145:64910690c574 | 757 | #define TIM_BREAK_ENABLE (TIM_BDTR_BKE) |
AnnaBridge | 145:64910690c574 | 758 | #define TIM_BREAK_DISABLE ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 759 | /** |
AnnaBridge | 145:64910690c574 | 760 | * @} |
AnnaBridge | 145:64910690c574 | 761 | */ |
AnnaBridge | 145:64910690c574 | 762 | |
AnnaBridge | 145:64910690c574 | 763 | /** @defgroup TIM_Break_Polarity TIM Break Input Polarity |
AnnaBridge | 145:64910690c574 | 764 | * @{ |
AnnaBridge | 145:64910690c574 | 765 | */ |
AnnaBridge | 145:64910690c574 | 766 | #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 767 | #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) |
AnnaBridge | 145:64910690c574 | 768 | /** |
AnnaBridge | 145:64910690c574 | 769 | * @} |
AnnaBridge | 145:64910690c574 | 770 | */ |
AnnaBridge | 145:64910690c574 | 771 | |
AnnaBridge | 145:64910690c574 | 772 | /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable |
AnnaBridge | 145:64910690c574 | 773 | * @{ |
AnnaBridge | 145:64910690c574 | 774 | */ |
AnnaBridge | 145:64910690c574 | 775 | #define TIM_BREAK2_DISABLE ((uint32_t)0x00000000) |
AnnaBridge | 145:64910690c574 | 776 | #define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E) |
AnnaBridge | 145:64910690c574 | 777 | /** |
AnnaBridge | 145:64910690c574 | 778 | * @} |
AnnaBridge | 145:64910690c574 | 779 | */ |
AnnaBridge | 145:64910690c574 | 780 | |
AnnaBridge | 145:64910690c574 | 781 | /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity |
AnnaBridge | 145:64910690c574 | 782 | * @{ |
AnnaBridge | 145:64910690c574 | 783 | */ |
AnnaBridge | 145:64910690c574 | 784 | #define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000) |
AnnaBridge | 145:64910690c574 | 785 | #define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P) |
AnnaBridge | 145:64910690c574 | 786 | /** |
AnnaBridge | 145:64910690c574 | 787 | * @} |
AnnaBridge | 145:64910690c574 | 788 | */ |
AnnaBridge | 145:64910690c574 | 789 | |
AnnaBridge | 145:64910690c574 | 790 | /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable |
AnnaBridge | 145:64910690c574 | 791 | * @{ |
AnnaBridge | 145:64910690c574 | 792 | */ |
AnnaBridge | 145:64910690c574 | 793 | #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) |
AnnaBridge | 161:aa5281ff4a02 | 794 | #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 795 | /** |
AnnaBridge | 145:64910690c574 | 796 | * @} |
AnnaBridge | 145:64910690c574 | 797 | */ |
AnnaBridge | 145:64910690c574 | 798 | |
AnnaBridge | 145:64910690c574 | 799 | /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 |
AnnaBridge | 145:64910690c574 | 800 | * @{ |
AnnaBridge | 145:64910690c574 | 801 | */ |
AnnaBridge | 145:64910690c574 | 802 | #define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ |
AnnaBridge | 145:64910690c574 | 803 | #define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ |
AnnaBridge | 145:64910690c574 | 804 | #define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ |
AnnaBridge | 145:64910690c574 | 805 | #define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ |
AnnaBridge | 145:64910690c574 | 806 | /** |
AnnaBridge | 145:64910690c574 | 807 | * @} |
AnnaBridge | 145:64910690c574 | 808 | */ |
AnnaBridge | 145:64910690c574 | 809 | |
AnnaBridge | 145:64910690c574 | 810 | /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection |
AnnaBridge | 145:64910690c574 | 811 | * @{ |
AnnaBridge | 145:64910690c574 | 812 | */ |
AnnaBridge | 161:aa5281ff4a02 | 813 | #define TIM_TRGO_RESET ((uint32_t)0x0000) |
AnnaBridge | 161:aa5281ff4a02 | 814 | #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) |
AnnaBridge | 161:aa5281ff4a02 | 815 | #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) |
AnnaBridge | 161:aa5281ff4a02 | 816 | #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
AnnaBridge | 161:aa5281ff4a02 | 817 | #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) |
AnnaBridge | 161:aa5281ff4a02 | 818 | #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) |
AnnaBridge | 161:aa5281ff4a02 | 819 | #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) |
AnnaBridge | 161:aa5281ff4a02 | 820 | #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
AnnaBridge | 145:64910690c574 | 821 | /** |
AnnaBridge | 145:64910690c574 | 822 | * @} |
AnnaBridge | 145:64910690c574 | 823 | */ |
AnnaBridge | 145:64910690c574 | 824 | |
AnnaBridge | 145:64910690c574 | 825 | /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) |
AnnaBridge | 145:64910690c574 | 826 | * @{ |
AnnaBridge | 145:64910690c574 | 827 | */ |
AnnaBridge | 161:aa5281ff4a02 | 828 | #define TIM_TRGO2_RESET ((uint32_t)0x00000000) |
AnnaBridge | 161:aa5281ff4a02 | 829 | #define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0)) |
AnnaBridge | 161:aa5281ff4a02 | 830 | #define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1)) |
AnnaBridge | 161:aa5281ff4a02 | 831 | #define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) |
AnnaBridge | 161:aa5281ff4a02 | 832 | #define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2)) |
AnnaBridge | 161:aa5281ff4a02 | 833 | #define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) |
AnnaBridge | 161:aa5281ff4a02 | 834 | #define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)) |
AnnaBridge | 161:aa5281ff4a02 | 835 | #define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) |
AnnaBridge | 161:aa5281ff4a02 | 836 | #define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3)) |
AnnaBridge | 161:aa5281ff4a02 | 837 | #define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)) |
AnnaBridge | 161:aa5281ff4a02 | 838 | #define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)) |
AnnaBridge | 161:aa5281ff4a02 | 839 | #define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) |
AnnaBridge | 161:aa5281ff4a02 | 840 | #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)) |
AnnaBridge | 161:aa5281ff4a02 | 841 | #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) |
AnnaBridge | 161:aa5281ff4a02 | 842 | #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)) |
AnnaBridge | 161:aa5281ff4a02 | 843 | #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) |
AnnaBridge | 145:64910690c574 | 844 | /** |
AnnaBridge | 145:64910690c574 | 845 | * @} |
AnnaBridge | 145:64910690c574 | 846 | */ |
AnnaBridge | 145:64910690c574 | 847 | |
AnnaBridge | 145:64910690c574 | 848 | /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode |
AnnaBridge | 145:64910690c574 | 849 | * @{ |
AnnaBridge | 145:64910690c574 | 850 | */ |
AnnaBridge | 145:64910690c574 | 851 | #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) |
AnnaBridge | 145:64910690c574 | 852 | #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 853 | /** |
AnnaBridge | 145:64910690c574 | 854 | * @} |
AnnaBridge | 145:64910690c574 | 855 | */ |
AnnaBridge | 145:64910690c574 | 856 | |
AnnaBridge | 145:64910690c574 | 857 | /** @defgroup TIM_Slave_Mode TIM Slave mode |
AnnaBridge | 145:64910690c574 | 858 | * @{ |
AnnaBridge | 145:64910690c574 | 859 | */ |
AnnaBridge | 145:64910690c574 | 860 | #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 861 | #define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2)) |
AnnaBridge | 145:64910690c574 | 862 | #define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)) |
AnnaBridge | 145:64910690c574 | 863 | #define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)) |
AnnaBridge | 145:64910690c574 | 864 | #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)) |
AnnaBridge | 145:64910690c574 | 865 | #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3)) |
AnnaBridge | 145:64910690c574 | 866 | /** |
AnnaBridge | 145:64910690c574 | 867 | * @} |
AnnaBridge | 145:64910690c574 | 868 | */ |
AnnaBridge | 145:64910690c574 | 869 | |
AnnaBridge | 145:64910690c574 | 870 | /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes |
AnnaBridge | 145:64910690c574 | 871 | * @{ |
AnnaBridge | 145:64910690c574 | 872 | */ |
AnnaBridge | 145:64910690c574 | 873 | #define TIM_OCMODE_TIMING ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 874 | #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0) |
AnnaBridge | 145:64910690c574 | 875 | #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1) |
AnnaBridge | 145:64910690c574 | 876 | #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) |
AnnaBridge | 145:64910690c574 | 877 | #define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) |
AnnaBridge | 145:64910690c574 | 878 | #define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) |
AnnaBridge | 145:64910690c574 | 879 | #define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) |
AnnaBridge | 145:64910690c574 | 880 | #define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2) |
AnnaBridge | 145:64910690c574 | 881 | |
AnnaBridge | 145:64910690c574 | 882 | #define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3) |
AnnaBridge | 145:64910690c574 | 883 | #define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) |
AnnaBridge | 145:64910690c574 | 884 | #define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) |
AnnaBridge | 145:64910690c574 | 885 | #define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) |
AnnaBridge | 145:64910690c574 | 886 | #define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) |
AnnaBridge | 145:64910690c574 | 887 | #define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) |
AnnaBridge | 145:64910690c574 | 888 | /** |
AnnaBridge | 145:64910690c574 | 889 | * @} |
AnnaBridge | 145:64910690c574 | 890 | */ |
AnnaBridge | 145:64910690c574 | 891 | |
AnnaBridge | 145:64910690c574 | 892 | /** @defgroup TIM_Trigger_Selection TIM Trigger Selection |
AnnaBridge | 145:64910690c574 | 893 | * @{ |
AnnaBridge | 145:64910690c574 | 894 | */ |
AnnaBridge | 145:64910690c574 | 895 | #define TIM_TS_ITR0 ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 896 | #define TIM_TS_ITR1 ((uint32_t)0x0010) |
AnnaBridge | 145:64910690c574 | 897 | #define TIM_TS_ITR2 ((uint32_t)0x0020) |
AnnaBridge | 145:64910690c574 | 898 | #define TIM_TS_ITR3 ((uint32_t)0x0030) |
AnnaBridge | 145:64910690c574 | 899 | #define TIM_TS_TI1F_ED ((uint32_t)0x0040) |
AnnaBridge | 145:64910690c574 | 900 | #define TIM_TS_TI1FP1 ((uint32_t)0x0050) |
AnnaBridge | 145:64910690c574 | 901 | #define TIM_TS_TI2FP2 ((uint32_t)0x0060) |
AnnaBridge | 145:64910690c574 | 902 | #define TIM_TS_ETRF ((uint32_t)0x0070) |
AnnaBridge | 145:64910690c574 | 903 | #define TIM_TS_NONE ((uint32_t)0xFFFF) |
AnnaBridge | 145:64910690c574 | 904 | /** |
AnnaBridge | 145:64910690c574 | 905 | * @} |
AnnaBridge | 145:64910690c574 | 906 | */ |
AnnaBridge | 145:64910690c574 | 907 | |
AnnaBridge | 145:64910690c574 | 908 | /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity |
AnnaBridge | 145:64910690c574 | 909 | * @{ |
AnnaBridge | 145:64910690c574 | 910 | */ |
AnnaBridge | 145:64910690c574 | 911 | #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ |
AnnaBridge | 145:64910690c574 | 912 | #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ |
AnnaBridge | 145:64910690c574 | 913 | #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
AnnaBridge | 145:64910690c574 | 914 | #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
AnnaBridge | 145:64910690c574 | 915 | #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
AnnaBridge | 145:64910690c574 | 916 | /** |
AnnaBridge | 145:64910690c574 | 917 | * @} |
AnnaBridge | 145:64910690c574 | 918 | */ |
AnnaBridge | 145:64910690c574 | 919 | |
AnnaBridge | 145:64910690c574 | 920 | /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler |
AnnaBridge | 145:64910690c574 | 921 | * @{ |
AnnaBridge | 145:64910690c574 | 922 | */ |
AnnaBridge | 145:64910690c574 | 923 | #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
AnnaBridge | 145:64910690c574 | 924 | #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ |
AnnaBridge | 145:64910690c574 | 925 | #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ |
AnnaBridge | 145:64910690c574 | 926 | #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ |
AnnaBridge | 145:64910690c574 | 927 | /** |
AnnaBridge | 145:64910690c574 | 928 | * @} |
AnnaBridge | 145:64910690c574 | 929 | */ |
AnnaBridge | 145:64910690c574 | 930 | |
AnnaBridge | 145:64910690c574 | 931 | /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection |
AnnaBridge | 145:64910690c574 | 932 | * @{ |
AnnaBridge | 145:64910690c574 | 933 | */ |
AnnaBridge | 145:64910690c574 | 934 | #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 935 | #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) |
AnnaBridge | 145:64910690c574 | 936 | /** |
AnnaBridge | 145:64910690c574 | 937 | * @} |
AnnaBridge | 145:64910690c574 | 938 | */ |
AnnaBridge | 145:64910690c574 | 939 | |
AnnaBridge | 145:64910690c574 | 940 | /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length |
AnnaBridge | 145:64910690c574 | 941 | * @{ |
AnnaBridge | 145:64910690c574 | 942 | */ |
AnnaBridge | 145:64910690c574 | 943 | #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) |
AnnaBridge | 145:64910690c574 | 944 | #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) |
AnnaBridge | 145:64910690c574 | 945 | #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) |
AnnaBridge | 145:64910690c574 | 946 | #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) |
AnnaBridge | 145:64910690c574 | 947 | #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) |
AnnaBridge | 145:64910690c574 | 948 | #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) |
AnnaBridge | 145:64910690c574 | 949 | #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) |
AnnaBridge | 145:64910690c574 | 950 | #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) |
AnnaBridge | 145:64910690c574 | 951 | #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) |
AnnaBridge | 145:64910690c574 | 952 | #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) |
AnnaBridge | 145:64910690c574 | 953 | #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) |
AnnaBridge | 145:64910690c574 | 954 | #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) |
AnnaBridge | 145:64910690c574 | 955 | #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) |
AnnaBridge | 145:64910690c574 | 956 | #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) |
AnnaBridge | 145:64910690c574 | 957 | #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) |
AnnaBridge | 145:64910690c574 | 958 | #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) |
AnnaBridge | 145:64910690c574 | 959 | #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) |
AnnaBridge | 145:64910690c574 | 960 | #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) |
AnnaBridge | 145:64910690c574 | 961 | /** |
AnnaBridge | 145:64910690c574 | 962 | * @} |
AnnaBridge | 145:64910690c574 | 963 | */ |
AnnaBridge | 145:64910690c574 | 964 | |
AnnaBridge | 145:64910690c574 | 965 | /** @defgroup DMA_Handle_index TIM DMA Handle Index |
AnnaBridge | 145:64910690c574 | 966 | * @{ |
AnnaBridge | 145:64910690c574 | 967 | */ |
AnnaBridge | 145:64910690c574 | 968 | #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ |
AnnaBridge | 145:64910690c574 | 969 | #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ |
AnnaBridge | 145:64910690c574 | 970 | #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ |
AnnaBridge | 145:64910690c574 | 971 | #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ |
AnnaBridge | 145:64910690c574 | 972 | #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ |
AnnaBridge | 145:64910690c574 | 973 | #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */ |
AnnaBridge | 145:64910690c574 | 974 | #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ |
AnnaBridge | 145:64910690c574 | 975 | /** |
AnnaBridge | 145:64910690c574 | 976 | * @} |
AnnaBridge | 145:64910690c574 | 977 | */ |
AnnaBridge | 145:64910690c574 | 978 | |
AnnaBridge | 145:64910690c574 | 979 | /** @defgroup Channel_CC_State TIM Capture/Compare Channel State |
AnnaBridge | 145:64910690c574 | 980 | * @{ |
AnnaBridge | 145:64910690c574 | 981 | */ |
AnnaBridge | 145:64910690c574 | 982 | #define TIM_CCx_ENABLE ((uint32_t)0x0001) |
AnnaBridge | 145:64910690c574 | 983 | #define TIM_CCx_DISABLE ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 984 | #define TIM_CCxN_ENABLE ((uint32_t)0x0004) |
AnnaBridge | 145:64910690c574 | 985 | #define TIM_CCxN_DISABLE ((uint32_t)0x0000) |
AnnaBridge | 145:64910690c574 | 986 | /** |
AnnaBridge | 145:64910690c574 | 987 | * @} |
AnnaBridge | 145:64910690c574 | 988 | */ |
AnnaBridge | 145:64910690c574 | 989 | |
AnnaBridge | 145:64910690c574 | 990 | /** @defgroup TIM_Break_System TIM Break System |
AnnaBridge | 145:64910690c574 | 991 | * @{ |
AnnaBridge | 145:64910690c574 | 992 | */ |
AnnaBridge | 145:64910690c574 | 993 | #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */ |
AnnaBridge | 145:64910690c574 | 994 | #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ |
AnnaBridge | 145:64910690c574 | 995 | #define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */ |
AnnaBridge | 145:64910690c574 | 996 | #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17 */ |
AnnaBridge | 145:64910690c574 | 997 | /** |
AnnaBridge | 145:64910690c574 | 998 | * @} |
AnnaBridge | 145:64910690c574 | 999 | */ |
AnnaBridge | 145:64910690c574 | 1000 | |
AnnaBridge | 145:64910690c574 | 1001 | /** |
AnnaBridge | 145:64910690c574 | 1002 | * @} |
AnnaBridge | 145:64910690c574 | 1003 | */ |
AnnaBridge | 145:64910690c574 | 1004 | /* End of exported constants -------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 1005 | |
AnnaBridge | 145:64910690c574 | 1006 | /* Exported macros -----------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 1007 | /** @defgroup TIM_Exported_Macros TIM Exported Macros |
AnnaBridge | 145:64910690c574 | 1008 | * @{ |
AnnaBridge | 145:64910690c574 | 1009 | */ |
AnnaBridge | 145:64910690c574 | 1010 | |
AnnaBridge | 145:64910690c574 | 1011 | /** @brief Reset TIM handle state. |
AnnaBridge | 161:aa5281ff4a02 | 1012 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 145:64910690c574 | 1013 | * @retval None |
AnnaBridge | 145:64910690c574 | 1014 | */ |
AnnaBridge | 145:64910690c574 | 1015 | #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) |
AnnaBridge | 145:64910690c574 | 1016 | |
AnnaBridge | 145:64910690c574 | 1017 | /** |
AnnaBridge | 145:64910690c574 | 1018 | * @brief Enable the TIM peripheral. |
AnnaBridge | 161:aa5281ff4a02 | 1019 | * @param __HANDLE__ TIM handle |
AnnaBridge | 145:64910690c574 | 1020 | * @retval None |
AnnaBridge | 145:64910690c574 | 1021 | */ |
AnnaBridge | 145:64910690c574 | 1022 | #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) |
AnnaBridge | 145:64910690c574 | 1023 | |
AnnaBridge | 145:64910690c574 | 1024 | /** |
AnnaBridge | 145:64910690c574 | 1025 | * @brief Enable the TIM main Output. |
AnnaBridge | 161:aa5281ff4a02 | 1026 | * @param __HANDLE__ TIM handle |
AnnaBridge | 145:64910690c574 | 1027 | * @retval None |
AnnaBridge | 145:64910690c574 | 1028 | */ |
AnnaBridge | 145:64910690c574 | 1029 | #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) |
AnnaBridge | 145:64910690c574 | 1030 | |
AnnaBridge | 145:64910690c574 | 1031 | /** |
AnnaBridge | 145:64910690c574 | 1032 | * @brief Disable the TIM peripheral. |
AnnaBridge | 161:aa5281ff4a02 | 1033 | * @param __HANDLE__ TIM handle |
AnnaBridge | 145:64910690c574 | 1034 | * @retval None |
AnnaBridge | 145:64910690c574 | 1035 | */ |
AnnaBridge | 145:64910690c574 | 1036 | #define __HAL_TIM_DISABLE(__HANDLE__) \ |
AnnaBridge | 145:64910690c574 | 1037 | do { \ |
AnnaBridge | 145:64910690c574 | 1038 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ |
AnnaBridge | 145:64910690c574 | 1039 | { \ |
AnnaBridge | 145:64910690c574 | 1040 | if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ |
AnnaBridge | 145:64910690c574 | 1041 | { \ |
AnnaBridge | 145:64910690c574 | 1042 | (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ |
AnnaBridge | 145:64910690c574 | 1043 | } \ |
AnnaBridge | 145:64910690c574 | 1044 | } \ |
AnnaBridge | 145:64910690c574 | 1045 | } while(0) |
AnnaBridge | 145:64910690c574 | 1046 | |
AnnaBridge | 145:64910690c574 | 1047 | /** |
AnnaBridge | 145:64910690c574 | 1048 | * @brief Disable the TIM main Output. |
AnnaBridge | 161:aa5281ff4a02 | 1049 | * @param __HANDLE__ TIM handle |
AnnaBridge | 145:64910690c574 | 1050 | * @retval None |
AnnaBridge | 145:64910690c574 | 1051 | * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled |
AnnaBridge | 145:64910690c574 | 1052 | */ |
AnnaBridge | 145:64910690c574 | 1053 | #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ |
AnnaBridge | 145:64910690c574 | 1054 | do { \ |
AnnaBridge | 145:64910690c574 | 1055 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ |
AnnaBridge | 145:64910690c574 | 1056 | { \ |
AnnaBridge | 145:64910690c574 | 1057 | if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ |
AnnaBridge | 145:64910690c574 | 1058 | { \ |
AnnaBridge | 145:64910690c574 | 1059 | (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ |
AnnaBridge | 145:64910690c574 | 1060 | } \ |
AnnaBridge | 145:64910690c574 | 1061 | } \ |
AnnaBridge | 145:64910690c574 | 1062 | } while(0) |
AnnaBridge | 145:64910690c574 | 1063 | |
AnnaBridge | 145:64910690c574 | 1064 | /** |
AnnaBridge | 145:64910690c574 | 1065 | * @brief Disable the TIM main Output. |
AnnaBridge | 161:aa5281ff4a02 | 1066 | * @param __HANDLE__ TIM handle |
AnnaBridge | 145:64910690c574 | 1067 | * @retval None |
AnnaBridge | 145:64910690c574 | 1068 | * @note The Main Output Enable of a timer instance is disabled unconditionally |
AnnaBridge | 145:64910690c574 | 1069 | */ |
AnnaBridge | 145:64910690c574 | 1070 | #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) |
AnnaBridge | 145:64910690c574 | 1071 | |
AnnaBridge | 145:64910690c574 | 1072 | /** @brief Enable the specified TIM interrupt. |
AnnaBridge | 161:aa5281ff4a02 | 1073 | * @param __HANDLE__ specifies the TIM Handle. |
AnnaBridge | 161:aa5281ff4a02 | 1074 | * @param __INTERRUPT__ specifies the TIM interrupt source to enable. |
AnnaBridge | 145:64910690c574 | 1075 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1076 | * @arg TIM_IT_UPDATE: Update interrupt |
AnnaBridge | 145:64910690c574 | 1077 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
AnnaBridge | 145:64910690c574 | 1078 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
AnnaBridge | 145:64910690c574 | 1079 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
AnnaBridge | 145:64910690c574 | 1080 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
AnnaBridge | 145:64910690c574 | 1081 | * @arg TIM_IT_COM: Commutation interrupt |
AnnaBridge | 145:64910690c574 | 1082 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
AnnaBridge | 145:64910690c574 | 1083 | * @arg TIM_IT_BREAK: Break interrupt |
AnnaBridge | 145:64910690c574 | 1084 | * @retval None |
AnnaBridge | 145:64910690c574 | 1085 | */ |
AnnaBridge | 145:64910690c574 | 1086 | #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) |
AnnaBridge | 145:64910690c574 | 1087 | |
AnnaBridge | 145:64910690c574 | 1088 | |
AnnaBridge | 145:64910690c574 | 1089 | /** @brief Disable the specified TIM interrupt. |
AnnaBridge | 161:aa5281ff4a02 | 1090 | * @param __HANDLE__ specifies the TIM Handle. |
AnnaBridge | 161:aa5281ff4a02 | 1091 | * @param __INTERRUPT__ specifies the TIM interrupt source to disable. |
AnnaBridge | 145:64910690c574 | 1092 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1093 | * @arg TIM_IT_UPDATE: Update interrupt |
AnnaBridge | 145:64910690c574 | 1094 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
AnnaBridge | 145:64910690c574 | 1095 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
AnnaBridge | 145:64910690c574 | 1096 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
AnnaBridge | 145:64910690c574 | 1097 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
AnnaBridge | 145:64910690c574 | 1098 | * @arg TIM_IT_COM: Commutation interrupt |
AnnaBridge | 145:64910690c574 | 1099 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
AnnaBridge | 145:64910690c574 | 1100 | * @arg TIM_IT_BREAK: Break interrupt |
AnnaBridge | 145:64910690c574 | 1101 | * @retval None |
AnnaBridge | 145:64910690c574 | 1102 | */ |
AnnaBridge | 145:64910690c574 | 1103 | #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) |
AnnaBridge | 145:64910690c574 | 1104 | |
AnnaBridge | 145:64910690c574 | 1105 | /** @brief Enable the specified DMA request. |
AnnaBridge | 161:aa5281ff4a02 | 1106 | * @param __HANDLE__ specifies the TIM Handle. |
AnnaBridge | 161:aa5281ff4a02 | 1107 | * @param __DMA__ specifies the TIM DMA request to enable. |
AnnaBridge | 145:64910690c574 | 1108 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1109 | * @arg TIM_DMA_UPDATE: Update DMA request |
AnnaBridge | 145:64910690c574 | 1110 | * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request |
AnnaBridge | 145:64910690c574 | 1111 | * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request |
AnnaBridge | 145:64910690c574 | 1112 | * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request |
AnnaBridge | 145:64910690c574 | 1113 | * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request |
AnnaBridge | 145:64910690c574 | 1114 | * @arg TIM_DMA_COM: Commutation DMA request |
AnnaBridge | 145:64910690c574 | 1115 | * @arg TIM_DMA_TRIGGER: Trigger DMA request |
AnnaBridge | 145:64910690c574 | 1116 | * @retval None |
AnnaBridge | 145:64910690c574 | 1117 | */ |
AnnaBridge | 145:64910690c574 | 1118 | #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) |
AnnaBridge | 145:64910690c574 | 1119 | |
AnnaBridge | 145:64910690c574 | 1120 | /** @brief Disable the specified DMA request. |
AnnaBridge | 161:aa5281ff4a02 | 1121 | * @param __HANDLE__ specifies the TIM Handle. |
AnnaBridge | 161:aa5281ff4a02 | 1122 | * @param __DMA__ specifies the TIM DMA request to disable. |
AnnaBridge | 145:64910690c574 | 1123 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1124 | * @arg TIM_DMA_UPDATE: Update DMA request |
AnnaBridge | 145:64910690c574 | 1125 | * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request |
AnnaBridge | 145:64910690c574 | 1126 | * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request |
AnnaBridge | 145:64910690c574 | 1127 | * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request |
AnnaBridge | 145:64910690c574 | 1128 | * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request |
AnnaBridge | 145:64910690c574 | 1129 | * @arg TIM_DMA_COM: Commutation DMA request |
AnnaBridge | 145:64910690c574 | 1130 | * @arg TIM_DMA_TRIGGER: Trigger DMA request |
AnnaBridge | 145:64910690c574 | 1131 | * @retval None |
AnnaBridge | 145:64910690c574 | 1132 | */ |
AnnaBridge | 145:64910690c574 | 1133 | #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) |
AnnaBridge | 145:64910690c574 | 1134 | |
AnnaBridge | 145:64910690c574 | 1135 | /** @brief Check whether the specified TIM interrupt flag is set or not. |
AnnaBridge | 161:aa5281ff4a02 | 1136 | * @param __HANDLE__ specifies the TIM Handle. |
AnnaBridge | 161:aa5281ff4a02 | 1137 | * @param __FLAG__ specifies the TIM interrupt flag to check. |
AnnaBridge | 145:64910690c574 | 1138 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1139 | * @arg TIM_FLAG_UPDATE: Update interrupt flag |
AnnaBridge | 145:64910690c574 | 1140 | * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag |
AnnaBridge | 145:64910690c574 | 1141 | * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag |
AnnaBridge | 145:64910690c574 | 1142 | * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag |
AnnaBridge | 145:64910690c574 | 1143 | * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag |
AnnaBridge | 145:64910690c574 | 1144 | * @arg TIM_FLAG_CC5: Compare 5 interrupt flag |
AnnaBridge | 161:aa5281ff4a02 | 1145 | * @arg TIM_FLAG_CC6: Compare 6 interrupt flag |
AnnaBridge | 145:64910690c574 | 1146 | * @arg TIM_FLAG_COM: Commutation interrupt flag |
AnnaBridge | 145:64910690c574 | 1147 | * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag |
AnnaBridge | 161:aa5281ff4a02 | 1148 | * @arg TIM_FLAG_BREAK: Break interrupt flag |
AnnaBridge | 161:aa5281ff4a02 | 1149 | * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag |
AnnaBridge | 145:64910690c574 | 1150 | * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag |
AnnaBridge | 145:64910690c574 | 1151 | * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag |
AnnaBridge | 145:64910690c574 | 1152 | * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag |
AnnaBridge | 145:64910690c574 | 1153 | * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag |
AnnaBridge | 145:64910690c574 | 1154 | * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag |
AnnaBridge | 145:64910690c574 | 1155 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
AnnaBridge | 145:64910690c574 | 1156 | */ |
AnnaBridge | 145:64910690c574 | 1157 | #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) |
AnnaBridge | 145:64910690c574 | 1158 | |
AnnaBridge | 145:64910690c574 | 1159 | /** @brief Clear the specified TIM interrupt flag. |
AnnaBridge | 161:aa5281ff4a02 | 1160 | * @param __HANDLE__ specifies the TIM Handle. |
AnnaBridge | 161:aa5281ff4a02 | 1161 | * @param __FLAG__ specifies the TIM interrupt flag to clear. |
AnnaBridge | 145:64910690c574 | 1162 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1163 | * @arg TIM_FLAG_UPDATE: Update interrupt flag |
AnnaBridge | 145:64910690c574 | 1164 | * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag |
AnnaBridge | 145:64910690c574 | 1165 | * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag |
AnnaBridge | 145:64910690c574 | 1166 | * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag |
AnnaBridge | 145:64910690c574 | 1167 | * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag |
AnnaBridge | 145:64910690c574 | 1168 | * @arg TIM_FLAG_CC5: Compare 5 interrupt flag |
AnnaBridge | 161:aa5281ff4a02 | 1169 | * @arg TIM_FLAG_CC6: Compare 6 interrupt flag |
AnnaBridge | 145:64910690c574 | 1170 | * @arg TIM_FLAG_COM: Commutation interrupt flag |
AnnaBridge | 145:64910690c574 | 1171 | * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag |
AnnaBridge | 161:aa5281ff4a02 | 1172 | * @arg TIM_FLAG_BREAK: Break interrupt flag |
AnnaBridge | 161:aa5281ff4a02 | 1173 | * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag |
AnnaBridge | 145:64910690c574 | 1174 | * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag |
AnnaBridge | 145:64910690c574 | 1175 | * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag |
AnnaBridge | 145:64910690c574 | 1176 | * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag |
AnnaBridge | 145:64910690c574 | 1177 | * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag |
AnnaBridge | 145:64910690c574 | 1178 | * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag |
AnnaBridge | 145:64910690c574 | 1179 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
AnnaBridge | 145:64910690c574 | 1180 | */ |
AnnaBridge | 145:64910690c574 | 1181 | #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) |
AnnaBridge | 145:64910690c574 | 1182 | |
AnnaBridge | 145:64910690c574 | 1183 | /** |
AnnaBridge | 145:64910690c574 | 1184 | * @brief Check whether the specified TIM interrupt source is enabled or not. |
AnnaBridge | 161:aa5281ff4a02 | 1185 | * @param __HANDLE__ TIM handle |
AnnaBridge | 161:aa5281ff4a02 | 1186 | * @param __INTERRUPT__ specifies the TIM interrupt source to check. |
AnnaBridge | 145:64910690c574 | 1187 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1188 | * @arg TIM_IT_UPDATE: Update interrupt |
AnnaBridge | 145:64910690c574 | 1189 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
AnnaBridge | 145:64910690c574 | 1190 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
AnnaBridge | 145:64910690c574 | 1191 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
AnnaBridge | 145:64910690c574 | 1192 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
AnnaBridge | 145:64910690c574 | 1193 | * @arg TIM_IT_COM: Commutation interrupt |
AnnaBridge | 145:64910690c574 | 1194 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
AnnaBridge | 145:64910690c574 | 1195 | * @arg TIM_IT_BREAK: Break interrupt |
AnnaBridge | 145:64910690c574 | 1196 | * @retval The state of TIM_IT (SET or RESET). |
AnnaBridge | 145:64910690c574 | 1197 | */ |
AnnaBridge | 145:64910690c574 | 1198 | #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
AnnaBridge | 145:64910690c574 | 1199 | |
AnnaBridge | 145:64910690c574 | 1200 | /** @brief Clear the TIM interrupt pending bits. |
AnnaBridge | 161:aa5281ff4a02 | 1201 | * @param __HANDLE__ TIM handle |
AnnaBridge | 161:aa5281ff4a02 | 1202 | * @param __INTERRUPT__ specifies the interrupt pending bit to clear. |
AnnaBridge | 145:64910690c574 | 1203 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1204 | * @arg TIM_IT_UPDATE: Update interrupt |
AnnaBridge | 145:64910690c574 | 1205 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
AnnaBridge | 145:64910690c574 | 1206 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
AnnaBridge | 145:64910690c574 | 1207 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
AnnaBridge | 145:64910690c574 | 1208 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
AnnaBridge | 145:64910690c574 | 1209 | * @arg TIM_IT_COM: Commutation interrupt |
AnnaBridge | 145:64910690c574 | 1210 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
AnnaBridge | 145:64910690c574 | 1211 | * @arg TIM_IT_BREAK: Break interrupt |
AnnaBridge | 145:64910690c574 | 1212 | * @retval None |
AnnaBridge | 145:64910690c574 | 1213 | */ |
AnnaBridge | 145:64910690c574 | 1214 | #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) |
AnnaBridge | 145:64910690c574 | 1215 | |
AnnaBridge | 145:64910690c574 | 1216 | /** |
AnnaBridge | 145:64910690c574 | 1217 | * @brief Indicates whether or not the TIM Counter is used as downcounter. |
AnnaBridge | 161:aa5281ff4a02 | 1218 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 145:64910690c574 | 1219 | * @retval False (Counter used as upcounter) or True (Counter used as downcounter) |
AnnaBridge | 145:64910690c574 | 1220 | * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder |
AnnaBridge | 145:64910690c574 | 1221 | mode. |
AnnaBridge | 145:64910690c574 | 1222 | */ |
AnnaBridge | 145:64910690c574 | 1223 | #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) |
AnnaBridge | 145:64910690c574 | 1224 | |
AnnaBridge | 145:64910690c574 | 1225 | |
AnnaBridge | 145:64910690c574 | 1226 | /** |
AnnaBridge | 145:64910690c574 | 1227 | * @brief Set the TIM Prescaler on runtime. |
AnnaBridge | 161:aa5281ff4a02 | 1228 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 161:aa5281ff4a02 | 1229 | * @param __PRESC__ specifies the Prescaler new value. |
AnnaBridge | 145:64910690c574 | 1230 | * @retval None |
AnnaBridge | 145:64910690c574 | 1231 | */ |
AnnaBridge | 145:64910690c574 | 1232 | #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) |
AnnaBridge | 145:64910690c574 | 1233 | |
AnnaBridge | 145:64910690c574 | 1234 | /** |
AnnaBridge | 145:64910690c574 | 1235 | * @brief Set the TIM Counter Register value on runtime. |
AnnaBridge | 161:aa5281ff4a02 | 1236 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 161:aa5281ff4a02 | 1237 | * @param __COUNTER__ specifies the Counter register new value. |
AnnaBridge | 145:64910690c574 | 1238 | * @retval None |
AnnaBridge | 145:64910690c574 | 1239 | */ |
AnnaBridge | 145:64910690c574 | 1240 | #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) |
AnnaBridge | 145:64910690c574 | 1241 | |
AnnaBridge | 145:64910690c574 | 1242 | /** |
AnnaBridge | 145:64910690c574 | 1243 | * @brief Get the TIM Counter Register value on runtime. |
AnnaBridge | 161:aa5281ff4a02 | 1244 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 161:aa5281ff4a02 | 1245 | * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) |
AnnaBridge | 145:64910690c574 | 1246 | */ |
AnnaBridge | 145:64910690c574 | 1247 | #define __HAL_TIM_GET_COUNTER(__HANDLE__) \ |
AnnaBridge | 145:64910690c574 | 1248 | ((__HANDLE__)->Instance->CNT) |
AnnaBridge | 145:64910690c574 | 1249 | |
AnnaBridge | 145:64910690c574 | 1250 | /** |
AnnaBridge | 145:64910690c574 | 1251 | * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. |
AnnaBridge | 161:aa5281ff4a02 | 1252 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 161:aa5281ff4a02 | 1253 | * @param __AUTORELOAD__ specifies the Counter register new value. |
AnnaBridge | 145:64910690c574 | 1254 | * @retval None |
AnnaBridge | 145:64910690c574 | 1255 | */ |
AnnaBridge | 145:64910690c574 | 1256 | #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ |
AnnaBridge | 145:64910690c574 | 1257 | do{ \ |
AnnaBridge | 145:64910690c574 | 1258 | (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ |
AnnaBridge | 145:64910690c574 | 1259 | (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ |
AnnaBridge | 145:64910690c574 | 1260 | } while(0) |
AnnaBridge | 145:64910690c574 | 1261 | |
AnnaBridge | 145:64910690c574 | 1262 | /** |
AnnaBridge | 145:64910690c574 | 1263 | * @brief Get the TIM Autoreload Register value on runtime. |
AnnaBridge | 161:aa5281ff4a02 | 1264 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 161:aa5281ff4a02 | 1265 | * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) |
AnnaBridge | 145:64910690c574 | 1266 | */ |
AnnaBridge | 145:64910690c574 | 1267 | #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ |
AnnaBridge | 145:64910690c574 | 1268 | ((__HANDLE__)->Instance->ARR) |
AnnaBridge | 145:64910690c574 | 1269 | |
AnnaBridge | 145:64910690c574 | 1270 | /** |
AnnaBridge | 145:64910690c574 | 1271 | * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. |
AnnaBridge | 161:aa5281ff4a02 | 1272 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 161:aa5281ff4a02 | 1273 | * @param __CKD__ specifies the clock division value. |
AnnaBridge | 145:64910690c574 | 1274 | * This parameter can be one of the following value: |
AnnaBridge | 161:aa5281ff4a02 | 1275 | * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT |
AnnaBridge | 161:aa5281ff4a02 | 1276 | * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT |
AnnaBridge | 161:aa5281ff4a02 | 1277 | * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT |
AnnaBridge | 145:64910690c574 | 1278 | * @retval None |
AnnaBridge | 145:64910690c574 | 1279 | */ |
AnnaBridge | 145:64910690c574 | 1280 | #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ |
AnnaBridge | 145:64910690c574 | 1281 | do{ \ |
AnnaBridge | 145:64910690c574 | 1282 | (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ |
AnnaBridge | 145:64910690c574 | 1283 | (__HANDLE__)->Instance->CR1 |= (__CKD__); \ |
AnnaBridge | 145:64910690c574 | 1284 | (__HANDLE__)->Init.ClockDivision = (__CKD__); \ |
AnnaBridge | 145:64910690c574 | 1285 | } while(0) |
AnnaBridge | 145:64910690c574 | 1286 | |
AnnaBridge | 145:64910690c574 | 1287 | /** |
AnnaBridge | 145:64910690c574 | 1288 | * @brief Get the TIM Clock Division value on runtime. |
AnnaBridge | 161:aa5281ff4a02 | 1289 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 161:aa5281ff4a02 | 1290 | * @retval The clock division can be one of the following values: |
AnnaBridge | 161:aa5281ff4a02 | 1291 | * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT |
AnnaBridge | 161:aa5281ff4a02 | 1292 | * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT |
AnnaBridge | 161:aa5281ff4a02 | 1293 | * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT |
AnnaBridge | 145:64910690c574 | 1294 | */ |
AnnaBridge | 145:64910690c574 | 1295 | #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ |
AnnaBridge | 145:64910690c574 | 1296 | ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) |
AnnaBridge | 145:64910690c574 | 1297 | |
AnnaBridge | 145:64910690c574 | 1298 | /** |
AnnaBridge | 145:64910690c574 | 1299 | * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. |
AnnaBridge | 161:aa5281ff4a02 | 1300 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 161:aa5281ff4a02 | 1301 | * @param __CHANNEL__ TIM Channels to be configured. |
AnnaBridge | 145:64910690c574 | 1302 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1303 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
AnnaBridge | 145:64910690c574 | 1304 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
AnnaBridge | 145:64910690c574 | 1305 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
AnnaBridge | 145:64910690c574 | 1306 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
AnnaBridge | 161:aa5281ff4a02 | 1307 | * @param __ICPSC__ specifies the Input Capture4 prescaler new value. |
AnnaBridge | 145:64910690c574 | 1308 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1309 | * @arg TIM_ICPSC_DIV1: no prescaler |
AnnaBridge | 145:64910690c574 | 1310 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
AnnaBridge | 145:64910690c574 | 1311 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
AnnaBridge | 145:64910690c574 | 1312 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
AnnaBridge | 145:64910690c574 | 1313 | * @retval None |
AnnaBridge | 145:64910690c574 | 1314 | */ |
AnnaBridge | 145:64910690c574 | 1315 | #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
AnnaBridge | 145:64910690c574 | 1316 | do{ \ |
AnnaBridge | 145:64910690c574 | 1317 | TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ |
AnnaBridge | 145:64910690c574 | 1318 | TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ |
AnnaBridge | 145:64910690c574 | 1319 | } while(0) |
AnnaBridge | 145:64910690c574 | 1320 | |
AnnaBridge | 145:64910690c574 | 1321 | /** |
AnnaBridge | 145:64910690c574 | 1322 | * @brief Get the TIM Input Capture prescaler on runtime. |
AnnaBridge | 161:aa5281ff4a02 | 1323 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 161:aa5281ff4a02 | 1324 | * @param __CHANNEL__ TIM Channels to be configured. |
AnnaBridge | 145:64910690c574 | 1325 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1326 | * @arg TIM_CHANNEL_1: get input capture 1 prescaler value |
AnnaBridge | 145:64910690c574 | 1327 | * @arg TIM_CHANNEL_2: get input capture 2 prescaler value |
AnnaBridge | 145:64910690c574 | 1328 | * @arg TIM_CHANNEL_3: get input capture 3 prescaler value |
AnnaBridge | 145:64910690c574 | 1329 | * @arg TIM_CHANNEL_4: get input capture 4 prescaler value |
AnnaBridge | 161:aa5281ff4a02 | 1330 | * @retval The input capture prescaler can be one of the following values: |
AnnaBridge | 161:aa5281ff4a02 | 1331 | * @arg TIM_ICPSC_DIV1: no prescaler |
AnnaBridge | 161:aa5281ff4a02 | 1332 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
AnnaBridge | 161:aa5281ff4a02 | 1333 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
AnnaBridge | 161:aa5281ff4a02 | 1334 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
AnnaBridge | 145:64910690c574 | 1335 | */ |
AnnaBridge | 145:64910690c574 | 1336 | #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ |
AnnaBridge | 145:64910690c574 | 1337 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ |
AnnaBridge | 145:64910690c574 | 1338 | ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ |
AnnaBridge | 145:64910690c574 | 1339 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ |
AnnaBridge | 145:64910690c574 | 1340 | (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) |
AnnaBridge | 145:64910690c574 | 1341 | |
AnnaBridge | 145:64910690c574 | 1342 | /** |
AnnaBridge | 145:64910690c574 | 1343 | * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. |
AnnaBridge | 161:aa5281ff4a02 | 1344 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 161:aa5281ff4a02 | 1345 | * @param __CHANNEL__ TIM Channels to be configured. |
AnnaBridge | 145:64910690c574 | 1346 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1347 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
AnnaBridge | 145:64910690c574 | 1348 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
AnnaBridge | 145:64910690c574 | 1349 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
AnnaBridge | 145:64910690c574 | 1350 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
AnnaBridge | 145:64910690c574 | 1351 | * @arg TIM_CHANNEL_5: TIM Channel 5 selected |
AnnaBridge | 145:64910690c574 | 1352 | * @arg TIM_CHANNEL_6: TIM Channel 6 selected |
AnnaBridge | 161:aa5281ff4a02 | 1353 | * @param __COMPARE__ specifies the Capture Compare register new value. |
AnnaBridge | 145:64910690c574 | 1354 | * @retval None |
AnnaBridge | 145:64910690c574 | 1355 | */ |
AnnaBridge | 145:64910690c574 | 1356 | #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ |
AnnaBridge | 145:64910690c574 | 1357 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ |
AnnaBridge | 145:64910690c574 | 1358 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ |
AnnaBridge | 145:64910690c574 | 1359 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ |
AnnaBridge | 145:64910690c574 | 1360 | ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ |
AnnaBridge | 145:64910690c574 | 1361 | ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ |
AnnaBridge | 145:64910690c574 | 1362 | ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) |
AnnaBridge | 145:64910690c574 | 1363 | |
AnnaBridge | 145:64910690c574 | 1364 | /** |
AnnaBridge | 145:64910690c574 | 1365 | * @brief Get the TIM Capture Compare Register value on runtime. |
AnnaBridge | 161:aa5281ff4a02 | 1366 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 161:aa5281ff4a02 | 1367 | * @param __CHANNEL__ TIM Channel associated with the capture compare register |
AnnaBridge | 145:64910690c574 | 1368 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1369 | * @arg TIM_CHANNEL_1: get capture/compare 1 register value |
AnnaBridge | 145:64910690c574 | 1370 | * @arg TIM_CHANNEL_2: get capture/compare 2 register value |
AnnaBridge | 145:64910690c574 | 1371 | * @arg TIM_CHANNEL_3: get capture/compare 3 register value |
AnnaBridge | 145:64910690c574 | 1372 | * @arg TIM_CHANNEL_4: get capture/compare 4 register value |
AnnaBridge | 145:64910690c574 | 1373 | * @arg TIM_CHANNEL_5: get capture/compare 5 register value |
AnnaBridge | 145:64910690c574 | 1374 | * @arg TIM_CHANNEL_6: get capture/compare 6 register value |
AnnaBridge | 161:aa5281ff4a02 | 1375 | * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) |
AnnaBridge | 145:64910690c574 | 1376 | */ |
AnnaBridge | 145:64910690c574 | 1377 | #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ |
AnnaBridge | 145:64910690c574 | 1378 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ |
AnnaBridge | 145:64910690c574 | 1379 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ |
AnnaBridge | 145:64910690c574 | 1380 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ |
AnnaBridge | 145:64910690c574 | 1381 | ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ |
AnnaBridge | 145:64910690c574 | 1382 | ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ |
AnnaBridge | 145:64910690c574 | 1383 | ((__HANDLE__)->Instance->CCR6)) |
AnnaBridge | 145:64910690c574 | 1384 | |
AnnaBridge | 145:64910690c574 | 1385 | /** |
AnnaBridge | 161:aa5281ff4a02 | 1386 | * @brief Set the TIM Output compare preload. |
AnnaBridge | 161:aa5281ff4a02 | 1387 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 161:aa5281ff4a02 | 1388 | * @param __CHANNEL__ TIM Channels to be configured. |
AnnaBridge | 161:aa5281ff4a02 | 1389 | * This parameter can be one of the following values: |
AnnaBridge | 161:aa5281ff4a02 | 1390 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
AnnaBridge | 161:aa5281ff4a02 | 1391 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
AnnaBridge | 161:aa5281ff4a02 | 1392 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
AnnaBridge | 161:aa5281ff4a02 | 1393 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
AnnaBridge | 161:aa5281ff4a02 | 1394 | * @arg TIM_CHANNEL_5: TIM Channel 5 selected |
AnnaBridge | 161:aa5281ff4a02 | 1395 | * @arg TIM_CHANNEL_6: TIM Channel 6 selected |
AnnaBridge | 161:aa5281ff4a02 | 1396 | * @retval None |
AnnaBridge | 161:aa5281ff4a02 | 1397 | */ |
AnnaBridge | 161:aa5281ff4a02 | 1398 | #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ |
AnnaBridge | 161:aa5281ff4a02 | 1399 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ |
AnnaBridge | 161:aa5281ff4a02 | 1400 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ |
AnnaBridge | 161:aa5281ff4a02 | 1401 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ |
AnnaBridge | 161:aa5281ff4a02 | 1402 | ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ |
AnnaBridge | 161:aa5281ff4a02 | 1403 | ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ |
AnnaBridge | 161:aa5281ff4a02 | 1404 | ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) |
AnnaBridge | 161:aa5281ff4a02 | 1405 | |
AnnaBridge | 161:aa5281ff4a02 | 1406 | /** |
AnnaBridge | 161:aa5281ff4a02 | 1407 | * @brief Reset the TIM Output compare preload. |
AnnaBridge | 161:aa5281ff4a02 | 1408 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 161:aa5281ff4a02 | 1409 | * @param __CHANNEL__ TIM Channels to be configured. |
AnnaBridge | 161:aa5281ff4a02 | 1410 | * This parameter can be one of the following values: |
AnnaBridge | 161:aa5281ff4a02 | 1411 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
AnnaBridge | 161:aa5281ff4a02 | 1412 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
AnnaBridge | 161:aa5281ff4a02 | 1413 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
AnnaBridge | 161:aa5281ff4a02 | 1414 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
AnnaBridge | 161:aa5281ff4a02 | 1415 | * @arg TIM_CHANNEL_5: TIM Channel 5 selected |
AnnaBridge | 161:aa5281ff4a02 | 1416 | * @arg TIM_CHANNEL_6: TIM Channel 6 selected |
AnnaBridge | 161:aa5281ff4a02 | 1417 | * @retval None |
AnnaBridge | 161:aa5281ff4a02 | 1418 | */ |
AnnaBridge | 161:aa5281ff4a02 | 1419 | #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ |
AnnaBridge | 161:aa5281ff4a02 | 1420 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ |
AnnaBridge | 161:aa5281ff4a02 | 1421 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ |
AnnaBridge | 161:aa5281ff4a02 | 1422 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ |
AnnaBridge | 161:aa5281ff4a02 | 1423 | ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\ |
AnnaBridge | 161:aa5281ff4a02 | 1424 | ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\ |
AnnaBridge | 161:aa5281ff4a02 | 1425 | ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE)) |
AnnaBridge | 161:aa5281ff4a02 | 1426 | |
AnnaBridge | 161:aa5281ff4a02 | 1427 | /** |
AnnaBridge | 145:64910690c574 | 1428 | * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. |
AnnaBridge | 161:aa5281ff4a02 | 1429 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 161:aa5281ff4a02 | 1430 | * @note When the USR bit of the TIMx_CR1 register is set, only counter |
AnnaBridge | 145:64910690c574 | 1431 | * overflow/underflow generates an update interrupt or DMA request (if |
AnnaBridge | 145:64910690c574 | 1432 | * enabled) |
AnnaBridge | 145:64910690c574 | 1433 | * @retval None |
AnnaBridge | 145:64910690c574 | 1434 | */ |
AnnaBridge | 145:64910690c574 | 1435 | #define __HAL_TIM_URS_ENABLE(__HANDLE__) \ |
AnnaBridge | 145:64910690c574 | 1436 | ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS)) |
AnnaBridge | 145:64910690c574 | 1437 | |
AnnaBridge | 145:64910690c574 | 1438 | /** |
AnnaBridge | 145:64910690c574 | 1439 | * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. |
AnnaBridge | 161:aa5281ff4a02 | 1440 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 161:aa5281ff4a02 | 1441 | * @note When the USR bit of the TIMx_CR1 register is reset, any of the |
AnnaBridge | 161:aa5281ff4a02 | 1442 | * following events generate an update interrupt or DMA request (if |
AnnaBridge | 145:64910690c574 | 1443 | * enabled): |
AnnaBridge | 145:64910690c574 | 1444 | * _ Counter overflow underflow |
AnnaBridge | 145:64910690c574 | 1445 | * _ Setting the UG bit |
AnnaBridge | 145:64910690c574 | 1446 | * _ Update generation through the slave mode controller |
AnnaBridge | 145:64910690c574 | 1447 | * @retval None |
AnnaBridge | 145:64910690c574 | 1448 | */ |
AnnaBridge | 145:64910690c574 | 1449 | #define __HAL_TIM_URS_DISABLE(__HANDLE__) \ |
AnnaBridge | 145:64910690c574 | 1450 | ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) |
AnnaBridge | 161:aa5281ff4a02 | 1451 | |
AnnaBridge | 145:64910690c574 | 1452 | /** |
AnnaBridge | 145:64910690c574 | 1453 | * @brief Set the TIM Capture x input polarity on runtime. |
AnnaBridge | 161:aa5281ff4a02 | 1454 | * @param __HANDLE__ TIM handle. |
AnnaBridge | 161:aa5281ff4a02 | 1455 | * @param __CHANNEL__ TIM Channels to be configured. |
AnnaBridge | 145:64910690c574 | 1456 | * This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1457 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
AnnaBridge | 145:64910690c574 | 1458 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
AnnaBridge | 145:64910690c574 | 1459 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
AnnaBridge | 145:64910690c574 | 1460 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
AnnaBridge | 161:aa5281ff4a02 | 1461 | * @param __POLARITY__ Polarity for TIx source |
AnnaBridge | 145:64910690c574 | 1462 | * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge |
AnnaBridge | 145:64910690c574 | 1463 | * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge |
AnnaBridge | 145:64910690c574 | 1464 | * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge |
AnnaBridge | 145:64910690c574 | 1465 | * @retval None |
AnnaBridge | 145:64910690c574 | 1466 | */ |
AnnaBridge | 145:64910690c574 | 1467 | #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
AnnaBridge | 145:64910690c574 | 1468 | do{ \ |
AnnaBridge | 145:64910690c574 | 1469 | TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ |
AnnaBridge | 145:64910690c574 | 1470 | TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ |
AnnaBridge | 145:64910690c574 | 1471 | }while(0) |
AnnaBridge | 161:aa5281ff4a02 | 1472 | |
AnnaBridge | 145:64910690c574 | 1473 | /** |
AnnaBridge | 145:64910690c574 | 1474 | * @} |
AnnaBridge | 145:64910690c574 | 1475 | */ |
AnnaBridge | 145:64910690c574 | 1476 | /* End of exported macros ----------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 1477 | |
AnnaBridge | 145:64910690c574 | 1478 | /* Private constants ---------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 1479 | /** @defgroup TIM_Private_Constants TIM Private Constants |
AnnaBridge | 145:64910690c574 | 1480 | * @{ |
AnnaBridge | 145:64910690c574 | 1481 | */ |
AnnaBridge | 145:64910690c574 | 1482 | /* The counter of a timer instance is disabled only if all the CCx and CCxN |
AnnaBridge | 145:64910690c574 | 1483 | channels have been disabled */ |
AnnaBridge | 145:64910690c574 | 1484 | #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) |
AnnaBridge | 145:64910690c574 | 1485 | #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) |
AnnaBridge | 145:64910690c574 | 1486 | /** |
AnnaBridge | 145:64910690c574 | 1487 | * @} |
AnnaBridge | 145:64910690c574 | 1488 | */ |
AnnaBridge | 145:64910690c574 | 1489 | /* End of private constants --------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 1490 | |
AnnaBridge | 145:64910690c574 | 1491 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 1492 | /** @defgroup TIM_Private_Macros TIM Private Macros |
AnnaBridge | 145:64910690c574 | 1493 | * @{ |
AnnaBridge | 145:64910690c574 | 1494 | */ |
AnnaBridge | 145:64910690c574 | 1495 | |
AnnaBridge | 145:64910690c574 | 1496 | #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ |
AnnaBridge | 145:64910690c574 | 1497 | ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ |
AnnaBridge | 145:64910690c574 | 1498 | ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) |
AnnaBridge | 145:64910690c574 | 1499 | |
AnnaBridge | 145:64910690c574 | 1500 | #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ |
AnnaBridge | 145:64910690c574 | 1501 | ((__BASE__) == TIM_DMABASE_CR2) || \ |
AnnaBridge | 145:64910690c574 | 1502 | ((__BASE__) == TIM_DMABASE_SMCR) || \ |
AnnaBridge | 145:64910690c574 | 1503 | ((__BASE__) == TIM_DMABASE_DIER) || \ |
AnnaBridge | 145:64910690c574 | 1504 | ((__BASE__) == TIM_DMABASE_SR) || \ |
AnnaBridge | 145:64910690c574 | 1505 | ((__BASE__) == TIM_DMABASE_EGR) || \ |
AnnaBridge | 145:64910690c574 | 1506 | ((__BASE__) == TIM_DMABASE_CCMR1) || \ |
AnnaBridge | 145:64910690c574 | 1507 | ((__BASE__) == TIM_DMABASE_CCMR2) || \ |
AnnaBridge | 145:64910690c574 | 1508 | ((__BASE__) == TIM_DMABASE_CCER) || \ |
AnnaBridge | 145:64910690c574 | 1509 | ((__BASE__) == TIM_DMABASE_CNT) || \ |
AnnaBridge | 145:64910690c574 | 1510 | ((__BASE__) == TIM_DMABASE_PSC) || \ |
AnnaBridge | 145:64910690c574 | 1511 | ((__BASE__) == TIM_DMABASE_ARR) || \ |
AnnaBridge | 145:64910690c574 | 1512 | ((__BASE__) == TIM_DMABASE_RCR) || \ |
AnnaBridge | 145:64910690c574 | 1513 | ((__BASE__) == TIM_DMABASE_CCR1) || \ |
AnnaBridge | 145:64910690c574 | 1514 | ((__BASE__) == TIM_DMABASE_CCR2) || \ |
AnnaBridge | 145:64910690c574 | 1515 | ((__BASE__) == TIM_DMABASE_CCR3) || \ |
AnnaBridge | 145:64910690c574 | 1516 | ((__BASE__) == TIM_DMABASE_CCR4) || \ |
AnnaBridge | 145:64910690c574 | 1517 | ((__BASE__) == TIM_DMABASE_BDTR) || \ |
AnnaBridge | 145:64910690c574 | 1518 | ((__BASE__) == TIM_DMABASE_CCMR3) || \ |
AnnaBridge | 145:64910690c574 | 1519 | ((__BASE__) == TIM_DMABASE_CCR5) || \ |
AnnaBridge | 145:64910690c574 | 1520 | ((__BASE__) == TIM_DMABASE_CCR6) || \ |
AnnaBridge | 145:64910690c574 | 1521 | ((__BASE__) == TIM_DMABASE_OR1) || \ |
AnnaBridge | 145:64910690c574 | 1522 | ((__BASE__) == TIM_DMABASE_OR2) || \ |
AnnaBridge | 145:64910690c574 | 1523 | ((__BASE__) == TIM_DMABASE_OR3)) |
AnnaBridge | 145:64910690c574 | 1524 | |
AnnaBridge | 145:64910690c574 | 1525 | |
AnnaBridge | 161:aa5281ff4a02 | 1526 | #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) |
AnnaBridge | 145:64910690c574 | 1527 | |
AnnaBridge | 145:64910690c574 | 1528 | |
AnnaBridge | 145:64910690c574 | 1529 | #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ |
AnnaBridge | 145:64910690c574 | 1530 | ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ |
AnnaBridge | 145:64910690c574 | 1531 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ |
AnnaBridge | 145:64910690c574 | 1532 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ |
AnnaBridge | 145:64910690c574 | 1533 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) |
AnnaBridge | 145:64910690c574 | 1534 | |
AnnaBridge | 145:64910690c574 | 1535 | #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ |
AnnaBridge | 145:64910690c574 | 1536 | ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ |
AnnaBridge | 145:64910690c574 | 1537 | ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) |
AnnaBridge | 145:64910690c574 | 1538 | |
AnnaBridge | 161:aa5281ff4a02 | 1539 | #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ |
AnnaBridge | 161:aa5281ff4a02 | 1540 | ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) |
AnnaBridge | 161:aa5281ff4a02 | 1541 | |
AnnaBridge | 145:64910690c574 | 1542 | #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ |
AnnaBridge | 145:64910690c574 | 1543 | ((__STATE__) == TIM_OCFAST_ENABLE)) |
AnnaBridge | 145:64910690c574 | 1544 | |
AnnaBridge | 145:64910690c574 | 1545 | #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ |
AnnaBridge | 145:64910690c574 | 1546 | ((__POLARITY__) == TIM_OCPOLARITY_LOW)) |
AnnaBridge | 145:64910690c574 | 1547 | |
AnnaBridge | 145:64910690c574 | 1548 | #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ |
AnnaBridge | 145:64910690c574 | 1549 | ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) |
AnnaBridge | 145:64910690c574 | 1550 | |
AnnaBridge | 145:64910690c574 | 1551 | #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ |
AnnaBridge | 145:64910690c574 | 1552 | ((__STATE__) == TIM_OCIDLESTATE_RESET)) |
AnnaBridge | 145:64910690c574 | 1553 | |
AnnaBridge | 145:64910690c574 | 1554 | #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ |
AnnaBridge | 145:64910690c574 | 1555 | ((__STATE__) == TIM_OCNIDLESTATE_RESET)) |
AnnaBridge | 145:64910690c574 | 1556 | |
AnnaBridge | 145:64910690c574 | 1557 | #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ |
AnnaBridge | 145:64910690c574 | 1558 | ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ |
AnnaBridge | 145:64910690c574 | 1559 | ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) |
AnnaBridge | 145:64910690c574 | 1560 | |
AnnaBridge | 145:64910690c574 | 1561 | #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ |
AnnaBridge | 145:64910690c574 | 1562 | ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ |
AnnaBridge | 145:64910690c574 | 1563 | ((__SELECTION__) == TIM_ICSELECTION_TRC)) |
AnnaBridge | 145:64910690c574 | 1564 | |
AnnaBridge | 145:64910690c574 | 1565 | #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ |
AnnaBridge | 145:64910690c574 | 1566 | ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ |
AnnaBridge | 145:64910690c574 | 1567 | ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ |
AnnaBridge | 145:64910690c574 | 1568 | ((__PRESCALER__) == TIM_ICPSC_DIV8)) |
AnnaBridge | 145:64910690c574 | 1569 | |
AnnaBridge | 145:64910690c574 | 1570 | #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ |
AnnaBridge | 145:64910690c574 | 1571 | ((__MODE__) == TIM_OPMODE_REPETITIVE)) |
AnnaBridge | 145:64910690c574 | 1572 | |
AnnaBridge | 145:64910690c574 | 1573 | #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ |
AnnaBridge | 145:64910690c574 | 1574 | ((__MODE__) == TIM_ENCODERMODE_TI2) || \ |
AnnaBridge | 145:64910690c574 | 1575 | ((__MODE__) == TIM_ENCODERMODE_TI12)) |
AnnaBridge | 145:64910690c574 | 1576 | |
AnnaBridge | 161:aa5281ff4a02 | 1577 | #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) |
AnnaBridge | 145:64910690c574 | 1578 | |
AnnaBridge | 145:64910690c574 | 1579 | #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ |
AnnaBridge | 145:64910690c574 | 1580 | ((__CHANNEL__) == TIM_CHANNEL_2) || \ |
AnnaBridge | 145:64910690c574 | 1581 | ((__CHANNEL__) == TIM_CHANNEL_3) || \ |
AnnaBridge | 145:64910690c574 | 1582 | ((__CHANNEL__) == TIM_CHANNEL_4) || \ |
AnnaBridge | 145:64910690c574 | 1583 | ((__CHANNEL__) == TIM_CHANNEL_5) || \ |
AnnaBridge | 145:64910690c574 | 1584 | ((__CHANNEL__) == TIM_CHANNEL_6) || \ |
AnnaBridge | 145:64910690c574 | 1585 | ((__CHANNEL__) == TIM_CHANNEL_ALL)) |
AnnaBridge | 145:64910690c574 | 1586 | |
AnnaBridge | 145:64910690c574 | 1587 | #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ |
AnnaBridge | 145:64910690c574 | 1588 | ((__CHANNEL__) == TIM_CHANNEL_2)) |
AnnaBridge | 145:64910690c574 | 1589 | |
AnnaBridge | 145:64910690c574 | 1590 | #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ |
AnnaBridge | 145:64910690c574 | 1591 | ((__CHANNEL__) == TIM_CHANNEL_2) || \ |
AnnaBridge | 145:64910690c574 | 1592 | ((__CHANNEL__) == TIM_CHANNEL_3)) |
AnnaBridge | 145:64910690c574 | 1593 | |
AnnaBridge | 145:64910690c574 | 1594 | #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ |
AnnaBridge | 145:64910690c574 | 1595 | ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ |
AnnaBridge | 145:64910690c574 | 1596 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ |
AnnaBridge | 145:64910690c574 | 1597 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ |
AnnaBridge | 145:64910690c574 | 1598 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ |
AnnaBridge | 145:64910690c574 | 1599 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ |
AnnaBridge | 145:64910690c574 | 1600 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ |
AnnaBridge | 145:64910690c574 | 1601 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ |
AnnaBridge | 145:64910690c574 | 1602 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ |
AnnaBridge | 145:64910690c574 | 1603 | ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) |
AnnaBridge | 145:64910690c574 | 1604 | |
AnnaBridge | 145:64910690c574 | 1605 | #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ |
AnnaBridge | 145:64910690c574 | 1606 | ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ |
AnnaBridge | 145:64910690c574 | 1607 | ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ |
AnnaBridge | 145:64910690c574 | 1608 | ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ |
AnnaBridge | 145:64910690c574 | 1609 | ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) |
AnnaBridge | 145:64910690c574 | 1610 | |
AnnaBridge | 145:64910690c574 | 1611 | #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ |
AnnaBridge | 145:64910690c574 | 1612 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ |
AnnaBridge | 145:64910690c574 | 1613 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ |
AnnaBridge | 145:64910690c574 | 1614 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) |
AnnaBridge | 145:64910690c574 | 1615 | |
AnnaBridge | 145:64910690c574 | 1616 | #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) |
AnnaBridge | 145:64910690c574 | 1617 | |
AnnaBridge | 145:64910690c574 | 1618 | #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ |
AnnaBridge | 145:64910690c574 | 1619 | ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) |
AnnaBridge | 145:64910690c574 | 1620 | |
AnnaBridge | 145:64910690c574 | 1621 | #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ |
AnnaBridge | 145:64910690c574 | 1622 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ |
AnnaBridge | 145:64910690c574 | 1623 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ |
AnnaBridge | 145:64910690c574 | 1624 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) |
AnnaBridge | 145:64910690c574 | 1625 | |
AnnaBridge | 145:64910690c574 | 1626 | #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) |
AnnaBridge | 145:64910690c574 | 1627 | |
AnnaBridge | 145:64910690c574 | 1628 | |
AnnaBridge | 145:64910690c574 | 1629 | #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ |
AnnaBridge | 145:64910690c574 | 1630 | ((__STATE__) == TIM_OSSR_DISABLE)) |
AnnaBridge | 145:64910690c574 | 1631 | |
AnnaBridge | 145:64910690c574 | 1632 | #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ |
AnnaBridge | 145:64910690c574 | 1633 | ((__STATE__) == TIM_OSSI_DISABLE)) |
AnnaBridge | 145:64910690c574 | 1634 | |
AnnaBridge | 145:64910690c574 | 1635 | #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ |
AnnaBridge | 145:64910690c574 | 1636 | ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ |
AnnaBridge | 145:64910690c574 | 1637 | ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ |
AnnaBridge | 145:64910690c574 | 1638 | ((__LEVEL__) == TIM_LOCKLEVEL_3)) |
AnnaBridge | 145:64910690c574 | 1639 | |
AnnaBridge | 145:64910690c574 | 1640 | #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xF) |
AnnaBridge | 145:64910690c574 | 1641 | |
AnnaBridge | 145:64910690c574 | 1642 | |
AnnaBridge | 145:64910690c574 | 1643 | #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ |
AnnaBridge | 145:64910690c574 | 1644 | ((__STATE__) == TIM_BREAK_DISABLE)) |
AnnaBridge | 145:64910690c574 | 1645 | |
AnnaBridge | 145:64910690c574 | 1646 | #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ |
AnnaBridge | 145:64910690c574 | 1647 | ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) |
AnnaBridge | 145:64910690c574 | 1648 | |
AnnaBridge | 145:64910690c574 | 1649 | #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ |
AnnaBridge | 145:64910690c574 | 1650 | ((__STATE__) == TIM_BREAK2_DISABLE)) |
AnnaBridge | 145:64910690c574 | 1651 | |
AnnaBridge | 145:64910690c574 | 1652 | #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ |
AnnaBridge | 145:64910690c574 | 1653 | ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) |
AnnaBridge | 145:64910690c574 | 1654 | |
AnnaBridge | 145:64910690c574 | 1655 | #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ |
AnnaBridge | 145:64910690c574 | 1656 | ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) |
AnnaBridge | 145:64910690c574 | 1657 | |
AnnaBridge | 145:64910690c574 | 1658 | #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFF) == 0x00000000)) |
AnnaBridge | 145:64910690c574 | 1659 | |
AnnaBridge | 145:64910690c574 | 1660 | #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ |
AnnaBridge | 145:64910690c574 | 1661 | ((__SOURCE__) == TIM_TRGO_ENABLE) || \ |
AnnaBridge | 145:64910690c574 | 1662 | ((__SOURCE__) == TIM_TRGO_UPDATE) || \ |
AnnaBridge | 145:64910690c574 | 1663 | ((__SOURCE__) == TIM_TRGO_OC1) || \ |
AnnaBridge | 145:64910690c574 | 1664 | ((__SOURCE__) == TIM_TRGO_OC1REF) || \ |
AnnaBridge | 145:64910690c574 | 1665 | ((__SOURCE__) == TIM_TRGO_OC2REF) || \ |
AnnaBridge | 145:64910690c574 | 1666 | ((__SOURCE__) == TIM_TRGO_OC3REF) || \ |
AnnaBridge | 145:64910690c574 | 1667 | ((__SOURCE__) == TIM_TRGO_OC4REF)) |
AnnaBridge | 145:64910690c574 | 1668 | |
AnnaBridge | 145:64910690c574 | 1669 | #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ |
AnnaBridge | 145:64910690c574 | 1670 | ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ |
AnnaBridge | 145:64910690c574 | 1671 | ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ |
AnnaBridge | 145:64910690c574 | 1672 | ((__SOURCE__) == TIM_TRGO2_OC1) || \ |
AnnaBridge | 145:64910690c574 | 1673 | ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ |
AnnaBridge | 145:64910690c574 | 1674 | ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ |
AnnaBridge | 145:64910690c574 | 1675 | ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ |
AnnaBridge | 145:64910690c574 | 1676 | ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ |
AnnaBridge | 145:64910690c574 | 1677 | ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ |
AnnaBridge | 145:64910690c574 | 1678 | ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ |
AnnaBridge | 145:64910690c574 | 1679 | ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ |
AnnaBridge | 145:64910690c574 | 1680 | ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ |
AnnaBridge | 145:64910690c574 | 1681 | ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ |
AnnaBridge | 145:64910690c574 | 1682 | ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ |
AnnaBridge | 145:64910690c574 | 1683 | ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ |
AnnaBridge | 145:64910690c574 | 1684 | ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ |
AnnaBridge | 145:64910690c574 | 1685 | ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) |
AnnaBridge | 145:64910690c574 | 1686 | |
AnnaBridge | 145:64910690c574 | 1687 | #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ |
AnnaBridge | 145:64910690c574 | 1688 | ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) |
AnnaBridge | 145:64910690c574 | 1689 | |
AnnaBridge | 145:64910690c574 | 1690 | #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ |
AnnaBridge | 145:64910690c574 | 1691 | ((__MODE__) == TIM_SLAVEMODE_RESET) || \ |
AnnaBridge | 145:64910690c574 | 1692 | ((__MODE__) == TIM_SLAVEMODE_GATED) || \ |
AnnaBridge | 145:64910690c574 | 1693 | ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ |
AnnaBridge | 145:64910690c574 | 1694 | ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ |
AnnaBridge | 145:64910690c574 | 1695 | ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) |
AnnaBridge | 145:64910690c574 | 1696 | |
AnnaBridge | 145:64910690c574 | 1697 | #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ |
AnnaBridge | 145:64910690c574 | 1698 | ((__MODE__) == TIM_OCMODE_PWM2) || \ |
AnnaBridge | 145:64910690c574 | 1699 | ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ |
AnnaBridge | 145:64910690c574 | 1700 | ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ |
AnnaBridge | 145:64910690c574 | 1701 | ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ |
AnnaBridge | 145:64910690c574 | 1702 | ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) |
AnnaBridge | 145:64910690c574 | 1703 | |
AnnaBridge | 145:64910690c574 | 1704 | #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ |
AnnaBridge | 145:64910690c574 | 1705 | ((__MODE__) == TIM_OCMODE_ACTIVE) || \ |
AnnaBridge | 145:64910690c574 | 1706 | ((__MODE__) == TIM_OCMODE_INACTIVE) || \ |
AnnaBridge | 145:64910690c574 | 1707 | ((__MODE__) == TIM_OCMODE_TOGGLE) || \ |
AnnaBridge | 145:64910690c574 | 1708 | ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ |
AnnaBridge | 145:64910690c574 | 1709 | ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ |
AnnaBridge | 145:64910690c574 | 1710 | ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ |
AnnaBridge | 145:64910690c574 | 1711 | ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) |
AnnaBridge | 145:64910690c574 | 1712 | |
AnnaBridge | 145:64910690c574 | 1713 | #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ |
AnnaBridge | 145:64910690c574 | 1714 | ((__SELECTION__) == TIM_TS_ITR1) || \ |
AnnaBridge | 145:64910690c574 | 1715 | ((__SELECTION__) == TIM_TS_ITR2) || \ |
AnnaBridge | 145:64910690c574 | 1716 | ((__SELECTION__) == TIM_TS_ITR3) || \ |
AnnaBridge | 145:64910690c574 | 1717 | ((__SELECTION__) == TIM_TS_TI1F_ED) || \ |
AnnaBridge | 145:64910690c574 | 1718 | ((__SELECTION__) == TIM_TS_TI1FP1) || \ |
AnnaBridge | 145:64910690c574 | 1719 | ((__SELECTION__) == TIM_TS_TI2FP2) || \ |
AnnaBridge | 145:64910690c574 | 1720 | ((__SELECTION__) == TIM_TS_ETRF)) |
AnnaBridge | 145:64910690c574 | 1721 | |
AnnaBridge | 145:64910690c574 | 1722 | #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ |
AnnaBridge | 145:64910690c574 | 1723 | ((__SELECTION__) == TIM_TS_ITR1) || \ |
AnnaBridge | 145:64910690c574 | 1724 | ((__SELECTION__) == TIM_TS_ITR2) || \ |
AnnaBridge | 145:64910690c574 | 1725 | ((__SELECTION__) == TIM_TS_ITR3) || \ |
AnnaBridge | 145:64910690c574 | 1726 | ((__SELECTION__) == TIM_TS_NONE)) |
AnnaBridge | 145:64910690c574 | 1727 | |
AnnaBridge | 145:64910690c574 | 1728 | |
AnnaBridge | 145:64910690c574 | 1729 | #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ |
AnnaBridge | 145:64910690c574 | 1730 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ |
AnnaBridge | 145:64910690c574 | 1731 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ |
AnnaBridge | 145:64910690c574 | 1732 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ |
AnnaBridge | 145:64910690c574 | 1733 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) |
AnnaBridge | 145:64910690c574 | 1734 | |
AnnaBridge | 145:64910690c574 | 1735 | #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ |
AnnaBridge | 145:64910690c574 | 1736 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ |
AnnaBridge | 145:64910690c574 | 1737 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ |
AnnaBridge | 145:64910690c574 | 1738 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) |
AnnaBridge | 145:64910690c574 | 1739 | |
AnnaBridge | 145:64910690c574 | 1740 | #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) |
AnnaBridge | 145:64910690c574 | 1741 | |
AnnaBridge | 145:64910690c574 | 1742 | #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ |
AnnaBridge | 145:64910690c574 | 1743 | ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) |
AnnaBridge | 145:64910690c574 | 1744 | |
AnnaBridge | 145:64910690c574 | 1745 | #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ |
AnnaBridge | 145:64910690c574 | 1746 | ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ |
AnnaBridge | 145:64910690c574 | 1747 | ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ |
AnnaBridge | 145:64910690c574 | 1748 | ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ |
AnnaBridge | 145:64910690c574 | 1749 | ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ |
AnnaBridge | 145:64910690c574 | 1750 | ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ |
AnnaBridge | 145:64910690c574 | 1751 | ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ |
AnnaBridge | 145:64910690c574 | 1752 | ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ |
AnnaBridge | 145:64910690c574 | 1753 | ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ |
AnnaBridge | 145:64910690c574 | 1754 | ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ |
AnnaBridge | 145:64910690c574 | 1755 | ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ |
AnnaBridge | 145:64910690c574 | 1756 | ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ |
AnnaBridge | 145:64910690c574 | 1757 | ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ |
AnnaBridge | 145:64910690c574 | 1758 | ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ |
AnnaBridge | 145:64910690c574 | 1759 | ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ |
AnnaBridge | 145:64910690c574 | 1760 | ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ |
AnnaBridge | 145:64910690c574 | 1761 | ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ |
AnnaBridge | 145:64910690c574 | 1762 | ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) |
AnnaBridge | 145:64910690c574 | 1763 | |
AnnaBridge | 145:64910690c574 | 1764 | #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) |
AnnaBridge | 145:64910690c574 | 1765 | |
AnnaBridge | 145:64910690c574 | 1766 | #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFF) |
AnnaBridge | 145:64910690c574 | 1767 | |
AnnaBridge | 145:64910690c574 | 1768 | #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ |
AnnaBridge | 145:64910690c574 | 1769 | ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ |
AnnaBridge | 145:64910690c574 | 1770 | ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR) || \ |
AnnaBridge | 145:64910690c574 | 1771 | ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) |
AnnaBridge | 145:64910690c574 | 1772 | |
AnnaBridge | 145:64910690c574 | 1773 | #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
AnnaBridge | 145:64910690c574 | 1774 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ |
AnnaBridge | 145:64910690c574 | 1775 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ |
AnnaBridge | 145:64910690c574 | 1776 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ |
AnnaBridge | 145:64910690c574 | 1777 | ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) |
AnnaBridge | 145:64910690c574 | 1778 | |
AnnaBridge | 145:64910690c574 | 1779 | #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ |
AnnaBridge | 145:64910690c574 | 1780 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ |
AnnaBridge | 145:64910690c574 | 1781 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ |
AnnaBridge | 145:64910690c574 | 1782 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ |
AnnaBridge | 145:64910690c574 | 1783 | ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) |
AnnaBridge | 145:64910690c574 | 1784 | |
AnnaBridge | 145:64910690c574 | 1785 | #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
AnnaBridge | 145:64910690c574 | 1786 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ |
AnnaBridge | 145:64910690c574 | 1787 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\ |
AnnaBridge | 145:64910690c574 | 1788 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\ |
AnnaBridge | 145:64910690c574 | 1789 | ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12)))) |
AnnaBridge | 145:64910690c574 | 1790 | |
AnnaBridge | 145:64910690c574 | 1791 | #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ |
AnnaBridge | 145:64910690c574 | 1792 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ |
AnnaBridge | 145:64910690c574 | 1793 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ |
AnnaBridge | 145:64910690c574 | 1794 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ |
AnnaBridge | 145:64910690c574 | 1795 | ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) |
AnnaBridge | 145:64910690c574 | 1796 | |
AnnaBridge | 145:64910690c574 | 1797 | /** |
AnnaBridge | 145:64910690c574 | 1798 | * @} |
AnnaBridge | 145:64910690c574 | 1799 | */ |
AnnaBridge | 145:64910690c574 | 1800 | /* End of private macros -----------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 1801 | |
AnnaBridge | 145:64910690c574 | 1802 | /* Include TIM HAL Extended module */ |
AnnaBridge | 145:64910690c574 | 1803 | #include "stm32l4xx_hal_tim_ex.h" |
AnnaBridge | 145:64910690c574 | 1804 | |
AnnaBridge | 145:64910690c574 | 1805 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 1806 | /** @addtogroup TIM_Exported_Functions TIM Exported Functions |
AnnaBridge | 145:64910690c574 | 1807 | * @{ |
AnnaBridge | 145:64910690c574 | 1808 | */ |
AnnaBridge | 145:64910690c574 | 1809 | |
AnnaBridge | 145:64910690c574 | 1810 | /** @addtogroup TIM_Exported_Functions_Group1 Time Base functions |
AnnaBridge | 145:64910690c574 | 1811 | * @brief Time Base functions |
AnnaBridge | 145:64910690c574 | 1812 | * @{ |
AnnaBridge | 145:64910690c574 | 1813 | */ |
AnnaBridge | 145:64910690c574 | 1814 | /* Time Base functions ********************************************************/ |
AnnaBridge | 145:64910690c574 | 1815 | HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1816 | HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1817 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1818 | void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1819 | /* Blocking mode: Polling */ |
AnnaBridge | 145:64910690c574 | 1820 | HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1821 | HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1822 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 145:64910690c574 | 1823 | HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1824 | HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1825 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 145:64910690c574 | 1826 | HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); |
AnnaBridge | 145:64910690c574 | 1827 | HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1828 | /** |
AnnaBridge | 145:64910690c574 | 1829 | * @} |
AnnaBridge | 145:64910690c574 | 1830 | */ |
AnnaBridge | 145:64910690c574 | 1831 | |
AnnaBridge | 145:64910690c574 | 1832 | /** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions |
AnnaBridge | 145:64910690c574 | 1833 | * @brief Time Output Compare functions |
AnnaBridge | 145:64910690c574 | 1834 | * @{ |
AnnaBridge | 145:64910690c574 | 1835 | */ |
AnnaBridge | 145:64910690c574 | 1836 | /* Timer Output Compare functions *********************************************/ |
AnnaBridge | 145:64910690c574 | 1837 | HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1838 | HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1839 | void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1840 | void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1841 | /* Blocking mode: Polling */ |
AnnaBridge | 145:64910690c574 | 1842 | HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1843 | HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1844 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 145:64910690c574 | 1845 | HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1846 | HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1847 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 145:64910690c574 | 1848 | HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
AnnaBridge | 145:64910690c574 | 1849 | HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1850 | /** |
AnnaBridge | 145:64910690c574 | 1851 | * @} |
AnnaBridge | 145:64910690c574 | 1852 | */ |
AnnaBridge | 145:64910690c574 | 1853 | |
AnnaBridge | 145:64910690c574 | 1854 | /** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions |
AnnaBridge | 145:64910690c574 | 1855 | * @brief Time PWM functions |
AnnaBridge | 145:64910690c574 | 1856 | * @{ |
AnnaBridge | 145:64910690c574 | 1857 | */ |
AnnaBridge | 145:64910690c574 | 1858 | /* Timer PWM functions ********************************************************/ |
AnnaBridge | 145:64910690c574 | 1859 | HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1860 | HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1861 | void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1862 | void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1863 | /* Blocking mode: Polling */ |
AnnaBridge | 145:64910690c574 | 1864 | HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1865 | HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1866 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 145:64910690c574 | 1867 | HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1868 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1869 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 145:64910690c574 | 1870 | HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
AnnaBridge | 145:64910690c574 | 1871 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1872 | /** |
AnnaBridge | 145:64910690c574 | 1873 | * @} |
AnnaBridge | 145:64910690c574 | 1874 | */ |
AnnaBridge | 145:64910690c574 | 1875 | |
AnnaBridge | 145:64910690c574 | 1876 | /** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions |
AnnaBridge | 145:64910690c574 | 1877 | * @brief Time Input Capture functions |
AnnaBridge | 145:64910690c574 | 1878 | * @{ |
AnnaBridge | 145:64910690c574 | 1879 | */ |
AnnaBridge | 145:64910690c574 | 1880 | /* Timer Input Capture functions **********************************************/ |
AnnaBridge | 145:64910690c574 | 1881 | HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1882 | HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1883 | void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1884 | void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1885 | /* Blocking mode: Polling */ |
AnnaBridge | 145:64910690c574 | 1886 | HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1887 | HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1888 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 145:64910690c574 | 1889 | HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1890 | HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1891 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 145:64910690c574 | 1892 | HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
AnnaBridge | 145:64910690c574 | 1893 | HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1894 | /** |
AnnaBridge | 145:64910690c574 | 1895 | * @} |
AnnaBridge | 145:64910690c574 | 1896 | */ |
AnnaBridge | 145:64910690c574 | 1897 | |
AnnaBridge | 145:64910690c574 | 1898 | /** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions |
AnnaBridge | 145:64910690c574 | 1899 | * @brief Time One Pulse functions |
AnnaBridge | 145:64910690c574 | 1900 | * @{ |
AnnaBridge | 145:64910690c574 | 1901 | */ |
AnnaBridge | 145:64910690c574 | 1902 | /* Timer One Pulse functions **************************************************/ |
AnnaBridge | 145:64910690c574 | 1903 | HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); |
AnnaBridge | 145:64910690c574 | 1904 | HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1905 | void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1906 | void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1907 | /* Blocking mode: Polling */ |
AnnaBridge | 145:64910690c574 | 1908 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
AnnaBridge | 145:64910690c574 | 1909 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
AnnaBridge | 145:64910690c574 | 1910 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 145:64910690c574 | 1911 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
AnnaBridge | 145:64910690c574 | 1912 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
AnnaBridge | 145:64910690c574 | 1913 | /** |
AnnaBridge | 145:64910690c574 | 1914 | * @} |
AnnaBridge | 145:64910690c574 | 1915 | */ |
AnnaBridge | 145:64910690c574 | 1916 | |
AnnaBridge | 145:64910690c574 | 1917 | /** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions |
AnnaBridge | 145:64910690c574 | 1918 | * @brief Time Encoder functions |
AnnaBridge | 145:64910690c574 | 1919 | * @{ |
AnnaBridge | 145:64910690c574 | 1920 | */ |
AnnaBridge | 145:64910690c574 | 1921 | /* Timer Encoder functions ****************************************************/ |
AnnaBridge | 145:64910690c574 | 1922 | HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); |
AnnaBridge | 145:64910690c574 | 1923 | HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1924 | void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1925 | void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1926 | /* Blocking mode: Polling */ |
AnnaBridge | 145:64910690c574 | 1927 | HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1928 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1929 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 145:64910690c574 | 1930 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1931 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1932 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 145:64910690c574 | 1933 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); |
AnnaBridge | 145:64910690c574 | 1934 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1935 | /** |
AnnaBridge | 145:64910690c574 | 1936 | * @} |
AnnaBridge | 145:64910690c574 | 1937 | */ |
AnnaBridge | 145:64910690c574 | 1938 | |
AnnaBridge | 145:64910690c574 | 1939 | /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management |
AnnaBridge | 145:64910690c574 | 1940 | * @brief IRQ handler management |
AnnaBridge | 145:64910690c574 | 1941 | * @{ |
AnnaBridge | 145:64910690c574 | 1942 | */ |
AnnaBridge | 145:64910690c574 | 1943 | /* Interrupt Handler functions ***********************************************/ |
AnnaBridge | 145:64910690c574 | 1944 | void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1945 | /** |
AnnaBridge | 145:64910690c574 | 1946 | * @} |
AnnaBridge | 145:64910690c574 | 1947 | */ |
AnnaBridge | 145:64910690c574 | 1948 | |
AnnaBridge | 145:64910690c574 | 1949 | /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions |
AnnaBridge | 145:64910690c574 | 1950 | * @brief Peripheral Control functions |
AnnaBridge | 145:64910690c574 | 1951 | * @{ |
AnnaBridge | 145:64910690c574 | 1952 | */ |
AnnaBridge | 145:64910690c574 | 1953 | /* Control functions *********************************************************/ |
AnnaBridge | 145:64910690c574 | 1954 | HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1955 | HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1956 | HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1957 | HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); |
AnnaBridge | 145:64910690c574 | 1958 | HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1959 | HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); |
AnnaBridge | 145:64910690c574 | 1960 | HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); |
AnnaBridge | 145:64910690c574 | 1961 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); |
AnnaBridge | 145:64910690c574 | 1962 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); |
AnnaBridge | 145:64910690c574 | 1963 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
AnnaBridge | 145:64910690c574 | 1964 | uint32_t *BurstBuffer, uint32_t BurstLength); |
AnnaBridge | 145:64910690c574 | 1965 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
AnnaBridge | 145:64910690c574 | 1966 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
AnnaBridge | 145:64910690c574 | 1967 | uint32_t *BurstBuffer, uint32_t BurstLength); |
AnnaBridge | 145:64910690c574 | 1968 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
AnnaBridge | 145:64910690c574 | 1969 | HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); |
AnnaBridge | 145:64910690c574 | 1970 | uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 1971 | /** |
AnnaBridge | 145:64910690c574 | 1972 | * @} |
AnnaBridge | 145:64910690c574 | 1973 | */ |
AnnaBridge | 145:64910690c574 | 1974 | |
AnnaBridge | 145:64910690c574 | 1975 | /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions |
AnnaBridge | 145:64910690c574 | 1976 | * @brief TIM Callbacks functions |
AnnaBridge | 145:64910690c574 | 1977 | * @{ |
AnnaBridge | 145:64910690c574 | 1978 | */ |
AnnaBridge | 145:64910690c574 | 1979 | /* Callback in non blocking modes (Interrupt and DMA) *************************/ |
AnnaBridge | 145:64910690c574 | 1980 | void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1981 | void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1982 | void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1983 | void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1984 | void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1985 | void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1986 | /** |
AnnaBridge | 145:64910690c574 | 1987 | * @} |
AnnaBridge | 145:64910690c574 | 1988 | */ |
AnnaBridge | 145:64910690c574 | 1989 | |
AnnaBridge | 145:64910690c574 | 1990 | /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions |
AnnaBridge | 145:64910690c574 | 1991 | * @brief Peripheral State functions |
AnnaBridge | 145:64910690c574 | 1992 | * @{ |
AnnaBridge | 145:64910690c574 | 1993 | */ |
AnnaBridge | 145:64910690c574 | 1994 | /* Peripheral State functions ************************************************/ |
AnnaBridge | 145:64910690c574 | 1995 | HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1996 | HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1997 | HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1998 | HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 1999 | HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 2000 | HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 145:64910690c574 | 2001 | /** |
AnnaBridge | 145:64910690c574 | 2002 | * @} |
AnnaBridge | 145:64910690c574 | 2003 | */ |
AnnaBridge | 145:64910690c574 | 2004 | |
AnnaBridge | 145:64910690c574 | 2005 | /** |
AnnaBridge | 145:64910690c574 | 2006 | * @} |
AnnaBridge | 145:64910690c574 | 2007 | */ |
AnnaBridge | 145:64910690c574 | 2008 | /* End of exported functions -------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 2009 | |
AnnaBridge | 145:64910690c574 | 2010 | /* Private functions----------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 2011 | /** @defgroup TIM_Private_Functions TIM Private Functions |
AnnaBridge | 145:64910690c574 | 2012 | * @{ |
AnnaBridge | 145:64910690c574 | 2013 | */ |
AnnaBridge | 145:64910690c574 | 2014 | void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); |
AnnaBridge | 145:64910690c574 | 2015 | void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); |
AnnaBridge | 145:64910690c574 | 2016 | void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
AnnaBridge | 145:64910690c574 | 2017 | void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, |
AnnaBridge | 145:64910690c574 | 2018 | uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); |
AnnaBridge | 145:64910690c574 | 2019 | |
AnnaBridge | 145:64910690c574 | 2020 | void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); |
AnnaBridge | 145:64910690c574 | 2021 | void TIM_DMAError(DMA_HandleTypeDef *hdma); |
AnnaBridge | 145:64910690c574 | 2022 | void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); |
AnnaBridge | 145:64910690c574 | 2023 | void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); |
AnnaBridge | 145:64910690c574 | 2024 | /** |
AnnaBridge | 145:64910690c574 | 2025 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 2026 | */ |
AnnaBridge | 145:64910690c574 | 2027 | /* End of private functions --------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 2028 | |
AnnaBridge | 145:64910690c574 | 2029 | /** |
AnnaBridge | 145:64910690c574 | 2030 | * @} |
AnnaBridge | 145:64910690c574 | 2031 | */ |
AnnaBridge | 145:64910690c574 | 2032 | |
AnnaBridge | 145:64910690c574 | 2033 | /** |
AnnaBridge | 145:64910690c574 | 2034 | * @} |
AnnaBridge | 145:64910690c574 | 2035 | */ |
AnnaBridge | 145:64910690c574 | 2036 | |
AnnaBridge | 145:64910690c574 | 2037 | #ifdef __cplusplus |
AnnaBridge | 145:64910690c574 | 2038 | } |
AnnaBridge | 145:64910690c574 | 2039 | #endif |
AnnaBridge | 145:64910690c574 | 2040 | |
AnnaBridge | 145:64910690c574 | 2041 | #endif /* __STM32L4xx_HAL_TIM_H */ |
AnnaBridge | 145:64910690c574 | 2042 | |
AnnaBridge | 145:64910690c574 | 2043 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |