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TARGET_NUCLEO_L433RC_P/TOOLCHAIN_ARM_MICRO/stm32l4xx_ll_dma.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 145:64910690c574 | 1 | /** |
AnnaBridge | 145:64910690c574 | 2 | ****************************************************************************** |
AnnaBridge | 145:64910690c574 | 3 | * @file stm32l4xx_ll_dma.h |
AnnaBridge | 145:64910690c574 | 4 | * @author MCD Application Team |
AnnaBridge | 145:64910690c574 | 5 | * @brief Header file of DMA LL module. |
AnnaBridge | 145:64910690c574 | 6 | ****************************************************************************** |
AnnaBridge | 145:64910690c574 | 7 | * @attention |
AnnaBridge | 145:64910690c574 | 8 | * |
AnnaBridge | 145:64910690c574 | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
AnnaBridge | 145:64910690c574 | 10 | * |
AnnaBridge | 145:64910690c574 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 145:64910690c574 | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 145:64910690c574 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 145:64910690c574 | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 145:64910690c574 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 145:64910690c574 | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 145:64910690c574 | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 145:64910690c574 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 145:64910690c574 | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 145:64910690c574 | 20 | * without specific prior written permission. |
AnnaBridge | 145:64910690c574 | 21 | * |
AnnaBridge | 145:64910690c574 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 145:64910690c574 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 145:64910690c574 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 145:64910690c574 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 145:64910690c574 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 145:64910690c574 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 145:64910690c574 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 145:64910690c574 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 145:64910690c574 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 145:64910690c574 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 145:64910690c574 | 32 | * |
AnnaBridge | 145:64910690c574 | 33 | ****************************************************************************** |
AnnaBridge | 145:64910690c574 | 34 | */ |
AnnaBridge | 145:64910690c574 | 35 | |
AnnaBridge | 145:64910690c574 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 37 | #ifndef __STM32L4xx_LL_DMA_H |
AnnaBridge | 145:64910690c574 | 38 | #define __STM32L4xx_LL_DMA_H |
AnnaBridge | 145:64910690c574 | 39 | |
AnnaBridge | 145:64910690c574 | 40 | #ifdef __cplusplus |
AnnaBridge | 145:64910690c574 | 41 | extern "C" { |
AnnaBridge | 145:64910690c574 | 42 | #endif |
AnnaBridge | 145:64910690c574 | 43 | |
AnnaBridge | 145:64910690c574 | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 45 | #include "stm32l4xx.h" |
AnnaBridge | 161:aa5281ff4a02 | 46 | #if defined(DMAMUX1) |
AnnaBridge | 161:aa5281ff4a02 | 47 | #include "stm32l4xx_ll_dmamux.h" |
AnnaBridge | 161:aa5281ff4a02 | 48 | #endif /* DMAMUX1 */ |
AnnaBridge | 145:64910690c574 | 49 | |
AnnaBridge | 145:64910690c574 | 50 | /** @addtogroup STM32L4xx_LL_Driver |
AnnaBridge | 145:64910690c574 | 51 | * @{ |
AnnaBridge | 145:64910690c574 | 52 | */ |
AnnaBridge | 145:64910690c574 | 53 | |
AnnaBridge | 145:64910690c574 | 54 | #if defined (DMA1) || defined (DMA2) |
AnnaBridge | 145:64910690c574 | 55 | |
AnnaBridge | 145:64910690c574 | 56 | /** @defgroup DMA_LL DMA |
AnnaBridge | 145:64910690c574 | 57 | * @{ |
AnnaBridge | 145:64910690c574 | 58 | */ |
AnnaBridge | 145:64910690c574 | 59 | |
AnnaBridge | 145:64910690c574 | 60 | /* Private types -------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 61 | /* Private variables ---------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 62 | /** @defgroup DMA_LL_Private_Variables DMA Private Variables |
AnnaBridge | 145:64910690c574 | 63 | * @{ |
AnnaBridge | 145:64910690c574 | 64 | */ |
AnnaBridge | 145:64910690c574 | 65 | /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ |
AnnaBridge | 145:64910690c574 | 66 | static const uint8_t CHANNEL_OFFSET_TAB[] = |
AnnaBridge | 145:64910690c574 | 67 | { |
AnnaBridge | 145:64910690c574 | 68 | (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), |
AnnaBridge | 145:64910690c574 | 69 | (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), |
AnnaBridge | 145:64910690c574 | 70 | (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), |
AnnaBridge | 145:64910690c574 | 71 | (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), |
AnnaBridge | 145:64910690c574 | 72 | (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), |
AnnaBridge | 145:64910690c574 | 73 | (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), |
AnnaBridge | 145:64910690c574 | 74 | (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) |
AnnaBridge | 145:64910690c574 | 75 | }; |
AnnaBridge | 145:64910690c574 | 76 | /** |
AnnaBridge | 145:64910690c574 | 77 | * @} |
AnnaBridge | 145:64910690c574 | 78 | */ |
AnnaBridge | 145:64910690c574 | 79 | |
AnnaBridge | 145:64910690c574 | 80 | /* Private constants ---------------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 81 | #if defined(DMAMUX1) |
AnnaBridge | 161:aa5281ff4a02 | 82 | #else |
AnnaBridge | 145:64910690c574 | 83 | /** @defgroup DMA_LL_Private_Constants DMA Private Constants |
AnnaBridge | 145:64910690c574 | 84 | * @{ |
AnnaBridge | 145:64910690c574 | 85 | */ |
AnnaBridge | 145:64910690c574 | 86 | /* Define used to get CSELR register offset */ |
AnnaBridge | 145:64910690c574 | 87 | #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE) |
AnnaBridge | 145:64910690c574 | 88 | |
AnnaBridge | 145:64910690c574 | 89 | /* Defines used for the bit position in the register and perform offsets */ |
AnnaBridge | 145:64910690c574 | 90 | #define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U)) |
AnnaBridge | 145:64910690c574 | 91 | /** |
AnnaBridge | 145:64910690c574 | 92 | * @} |
AnnaBridge | 145:64910690c574 | 93 | */ |
AnnaBridge | 161:aa5281ff4a02 | 94 | #endif /* DMAMUX1 */ |
AnnaBridge | 145:64910690c574 | 95 | |
AnnaBridge | 145:64910690c574 | 96 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 97 | #if defined(DMAMUX1) |
AnnaBridge | 161:aa5281ff4a02 | 98 | /** @defgroup DMA_LL_Private_Macros DMA Private Macros |
AnnaBridge | 161:aa5281ff4a02 | 99 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 100 | */ |
AnnaBridge | 161:aa5281ff4a02 | 101 | /** |
AnnaBridge | 161:aa5281ff4a02 | 102 | * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel |
AnnaBridge | 161:aa5281ff4a02 | 103 | * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. |
AnnaBridge | 161:aa5281ff4a02 | 104 | * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. |
AnnaBridge | 161:aa5281ff4a02 | 105 | * @param __DMA_INSTANCE__ DMAx |
AnnaBridge | 161:aa5281ff4a02 | 106 | * @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0). |
AnnaBridge | 161:aa5281ff4a02 | 107 | */ |
AnnaBridge | 161:aa5281ff4a02 | 108 | #define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \ |
AnnaBridge | 161:aa5281ff4a02 | 109 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7) |
AnnaBridge | 161:aa5281ff4a02 | 110 | |
AnnaBridge | 161:aa5281ff4a02 | 111 | /** |
AnnaBridge | 161:aa5281ff4a02 | 112 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 113 | */ |
AnnaBridge | 161:aa5281ff4a02 | 114 | #else |
AnnaBridge | 145:64910690c574 | 115 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 145:64910690c574 | 116 | /** @defgroup DMA_LL_Private_Macros DMA Private Macros |
AnnaBridge | 145:64910690c574 | 117 | * @{ |
AnnaBridge | 145:64910690c574 | 118 | */ |
AnnaBridge | 145:64910690c574 | 119 | /** |
AnnaBridge | 145:64910690c574 | 120 | * @} |
AnnaBridge | 145:64910690c574 | 121 | */ |
AnnaBridge | 145:64910690c574 | 122 | #endif /*USE_FULL_LL_DRIVER*/ |
AnnaBridge | 161:aa5281ff4a02 | 123 | #endif /* DMAMUX1 */ |
AnnaBridge | 145:64910690c574 | 124 | |
AnnaBridge | 145:64910690c574 | 125 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 126 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 145:64910690c574 | 127 | /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure |
AnnaBridge | 145:64910690c574 | 128 | * @{ |
AnnaBridge | 145:64910690c574 | 129 | */ |
AnnaBridge | 145:64910690c574 | 130 | typedef struct |
AnnaBridge | 145:64910690c574 | 131 | { |
AnnaBridge | 145:64910690c574 | 132 | uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer |
AnnaBridge | 145:64910690c574 | 133 | or as Source base address in case of memory to memory transfer direction. |
AnnaBridge | 145:64910690c574 | 134 | |
AnnaBridge | 145:64910690c574 | 135 | This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ |
AnnaBridge | 145:64910690c574 | 136 | |
AnnaBridge | 145:64910690c574 | 137 | uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer |
AnnaBridge | 145:64910690c574 | 138 | or as Destination base address in case of memory to memory transfer direction. |
AnnaBridge | 145:64910690c574 | 139 | |
AnnaBridge | 145:64910690c574 | 140 | This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ |
AnnaBridge | 145:64910690c574 | 141 | |
AnnaBridge | 145:64910690c574 | 142 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
AnnaBridge | 145:64910690c574 | 143 | from memory to memory or from peripheral to memory. |
AnnaBridge | 145:64910690c574 | 144 | This parameter can be a value of @ref DMA_LL_EC_DIRECTION |
AnnaBridge | 145:64910690c574 | 145 | |
AnnaBridge | 145:64910690c574 | 146 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ |
AnnaBridge | 145:64910690c574 | 147 | |
AnnaBridge | 145:64910690c574 | 148 | uint32_t Mode; /*!< Specifies the normal or circular operation mode. |
AnnaBridge | 145:64910690c574 | 149 | This parameter can be a value of @ref DMA_LL_EC_MODE |
AnnaBridge | 145:64910690c574 | 150 | @note: The circular buffer mode cannot be used if the memory to memory |
AnnaBridge | 145:64910690c574 | 151 | data transfer direction is configured on the selected Channel |
AnnaBridge | 145:64910690c574 | 152 | |
AnnaBridge | 145:64910690c574 | 153 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ |
AnnaBridge | 145:64910690c574 | 154 | |
AnnaBridge | 145:64910690c574 | 155 | uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction |
AnnaBridge | 145:64910690c574 | 156 | is incremented or not. |
AnnaBridge | 145:64910690c574 | 157 | This parameter can be a value of @ref DMA_LL_EC_PERIPH |
AnnaBridge | 145:64910690c574 | 158 | |
AnnaBridge | 145:64910690c574 | 159 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ |
AnnaBridge | 145:64910690c574 | 160 | |
AnnaBridge | 145:64910690c574 | 161 | uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction |
AnnaBridge | 145:64910690c574 | 162 | is incremented or not. |
AnnaBridge | 145:64910690c574 | 163 | This parameter can be a value of @ref DMA_LL_EC_MEMORY |
AnnaBridge | 145:64910690c574 | 164 | |
AnnaBridge | 145:64910690c574 | 165 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ |
AnnaBridge | 145:64910690c574 | 166 | |
AnnaBridge | 145:64910690c574 | 167 | uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) |
AnnaBridge | 145:64910690c574 | 168 | in case of memory to memory transfer direction. |
AnnaBridge | 145:64910690c574 | 169 | This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN |
AnnaBridge | 145:64910690c574 | 170 | |
AnnaBridge | 145:64910690c574 | 171 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ |
AnnaBridge | 145:64910690c574 | 172 | |
AnnaBridge | 145:64910690c574 | 173 | uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) |
AnnaBridge | 145:64910690c574 | 174 | in case of memory to memory transfer direction. |
AnnaBridge | 145:64910690c574 | 175 | This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN |
AnnaBridge | 145:64910690c574 | 176 | |
AnnaBridge | 145:64910690c574 | 177 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ |
AnnaBridge | 145:64910690c574 | 178 | |
AnnaBridge | 145:64910690c574 | 179 | uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. |
AnnaBridge | 145:64910690c574 | 180 | The data unit is equal to the source buffer configuration set in PeripheralSize |
AnnaBridge | 145:64910690c574 | 181 | or MemorySize parameters depending in the transfer direction. |
AnnaBridge | 145:64910690c574 | 182 | This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF |
AnnaBridge | 145:64910690c574 | 183 | |
AnnaBridge | 145:64910690c574 | 184 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ |
AnnaBridge | 161:aa5281ff4a02 | 185 | #if defined(DMAMUX1) |
AnnaBridge | 161:aa5281ff4a02 | 186 | |
AnnaBridge | 161:aa5281ff4a02 | 187 | uint32_t PeriphRequest; /*!< Specifies the peripheral request. |
AnnaBridge | 161:aa5281ff4a02 | 188 | This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST |
AnnaBridge | 161:aa5281ff4a02 | 189 | |
AnnaBridge | 161:aa5281ff4a02 | 190 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ |
AnnaBridge | 161:aa5281ff4a02 | 191 | #else |
AnnaBridge | 145:64910690c574 | 192 | |
AnnaBridge | 145:64910690c574 | 193 | uint32_t PeriphRequest; /*!< Specifies the peripheral request. |
AnnaBridge | 145:64910690c574 | 194 | This parameter can be a value of @ref DMA_LL_EC_REQUEST |
AnnaBridge | 145:64910690c574 | 195 | |
AnnaBridge | 145:64910690c574 | 196 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ |
AnnaBridge | 161:aa5281ff4a02 | 197 | #endif /* DMAMUX1 */ |
AnnaBridge | 145:64910690c574 | 198 | |
AnnaBridge | 145:64910690c574 | 199 | uint32_t Priority; /*!< Specifies the channel priority level. |
AnnaBridge | 145:64910690c574 | 200 | This parameter can be a value of @ref DMA_LL_EC_PRIORITY |
AnnaBridge | 145:64910690c574 | 201 | |
AnnaBridge | 145:64910690c574 | 202 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ |
AnnaBridge | 145:64910690c574 | 203 | |
AnnaBridge | 145:64910690c574 | 204 | } LL_DMA_InitTypeDef; |
AnnaBridge | 145:64910690c574 | 205 | /** |
AnnaBridge | 145:64910690c574 | 206 | * @} |
AnnaBridge | 145:64910690c574 | 207 | */ |
AnnaBridge | 145:64910690c574 | 208 | #endif /*USE_FULL_LL_DRIVER*/ |
AnnaBridge | 145:64910690c574 | 209 | |
AnnaBridge | 145:64910690c574 | 210 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 211 | /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants |
AnnaBridge | 145:64910690c574 | 212 | * @{ |
AnnaBridge | 145:64910690c574 | 213 | */ |
AnnaBridge | 145:64910690c574 | 214 | /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines |
AnnaBridge | 145:64910690c574 | 215 | * @brief Flags defines which can be used with LL_DMA_WriteReg function |
AnnaBridge | 145:64910690c574 | 216 | * @{ |
AnnaBridge | 145:64910690c574 | 217 | */ |
AnnaBridge | 145:64910690c574 | 218 | #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ |
AnnaBridge | 145:64910690c574 | 219 | #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ |
AnnaBridge | 145:64910690c574 | 220 | #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ |
AnnaBridge | 145:64910690c574 | 221 | #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ |
AnnaBridge | 145:64910690c574 | 222 | #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ |
AnnaBridge | 145:64910690c574 | 223 | #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ |
AnnaBridge | 145:64910690c574 | 224 | #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ |
AnnaBridge | 145:64910690c574 | 225 | #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ |
AnnaBridge | 145:64910690c574 | 226 | #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ |
AnnaBridge | 145:64910690c574 | 227 | #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ |
AnnaBridge | 145:64910690c574 | 228 | #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ |
AnnaBridge | 145:64910690c574 | 229 | #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ |
AnnaBridge | 145:64910690c574 | 230 | #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ |
AnnaBridge | 145:64910690c574 | 231 | #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ |
AnnaBridge | 145:64910690c574 | 232 | #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ |
AnnaBridge | 145:64910690c574 | 233 | #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ |
AnnaBridge | 145:64910690c574 | 234 | #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ |
AnnaBridge | 145:64910690c574 | 235 | #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ |
AnnaBridge | 145:64910690c574 | 236 | #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ |
AnnaBridge | 145:64910690c574 | 237 | #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ |
AnnaBridge | 145:64910690c574 | 238 | #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ |
AnnaBridge | 145:64910690c574 | 239 | #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ |
AnnaBridge | 145:64910690c574 | 240 | #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ |
AnnaBridge | 145:64910690c574 | 241 | #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ |
AnnaBridge | 145:64910690c574 | 242 | #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ |
AnnaBridge | 145:64910690c574 | 243 | #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ |
AnnaBridge | 145:64910690c574 | 244 | #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ |
AnnaBridge | 145:64910690c574 | 245 | #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ |
AnnaBridge | 145:64910690c574 | 246 | /** |
AnnaBridge | 145:64910690c574 | 247 | * @} |
AnnaBridge | 145:64910690c574 | 248 | */ |
AnnaBridge | 145:64910690c574 | 249 | |
AnnaBridge | 145:64910690c574 | 250 | /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines |
AnnaBridge | 145:64910690c574 | 251 | * @brief Flags defines which can be used with LL_DMA_ReadReg function |
AnnaBridge | 145:64910690c574 | 252 | * @{ |
AnnaBridge | 145:64910690c574 | 253 | */ |
AnnaBridge | 145:64910690c574 | 254 | #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ |
AnnaBridge | 145:64910690c574 | 255 | #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ |
AnnaBridge | 145:64910690c574 | 256 | #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ |
AnnaBridge | 145:64910690c574 | 257 | #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ |
AnnaBridge | 145:64910690c574 | 258 | #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ |
AnnaBridge | 145:64910690c574 | 259 | #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ |
AnnaBridge | 145:64910690c574 | 260 | #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ |
AnnaBridge | 145:64910690c574 | 261 | #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ |
AnnaBridge | 145:64910690c574 | 262 | #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ |
AnnaBridge | 145:64910690c574 | 263 | #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ |
AnnaBridge | 145:64910690c574 | 264 | #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ |
AnnaBridge | 145:64910690c574 | 265 | #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ |
AnnaBridge | 145:64910690c574 | 266 | #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ |
AnnaBridge | 145:64910690c574 | 267 | #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ |
AnnaBridge | 145:64910690c574 | 268 | #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ |
AnnaBridge | 145:64910690c574 | 269 | #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ |
AnnaBridge | 145:64910690c574 | 270 | #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ |
AnnaBridge | 145:64910690c574 | 271 | #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ |
AnnaBridge | 145:64910690c574 | 272 | #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ |
AnnaBridge | 145:64910690c574 | 273 | #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ |
AnnaBridge | 145:64910690c574 | 274 | #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ |
AnnaBridge | 145:64910690c574 | 275 | #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ |
AnnaBridge | 145:64910690c574 | 276 | #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ |
AnnaBridge | 145:64910690c574 | 277 | #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ |
AnnaBridge | 145:64910690c574 | 278 | #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ |
AnnaBridge | 145:64910690c574 | 279 | #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ |
AnnaBridge | 145:64910690c574 | 280 | #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ |
AnnaBridge | 145:64910690c574 | 281 | #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ |
AnnaBridge | 145:64910690c574 | 282 | /** |
AnnaBridge | 145:64910690c574 | 283 | * @} |
AnnaBridge | 145:64910690c574 | 284 | */ |
AnnaBridge | 145:64910690c574 | 285 | |
AnnaBridge | 145:64910690c574 | 286 | /** @defgroup DMA_LL_EC_IT IT Defines |
AnnaBridge | 145:64910690c574 | 287 | * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions |
AnnaBridge | 145:64910690c574 | 288 | * @{ |
AnnaBridge | 145:64910690c574 | 289 | */ |
AnnaBridge | 145:64910690c574 | 290 | #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ |
AnnaBridge | 145:64910690c574 | 291 | #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ |
AnnaBridge | 145:64910690c574 | 292 | #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ |
AnnaBridge | 145:64910690c574 | 293 | /** |
AnnaBridge | 145:64910690c574 | 294 | * @} |
AnnaBridge | 145:64910690c574 | 295 | */ |
AnnaBridge | 145:64910690c574 | 296 | |
AnnaBridge | 145:64910690c574 | 297 | /** @defgroup DMA_LL_EC_CHANNEL CHANNEL |
AnnaBridge | 145:64910690c574 | 298 | * @{ |
AnnaBridge | 145:64910690c574 | 299 | */ |
AnnaBridge | 161:aa5281ff4a02 | 300 | #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ |
AnnaBridge | 161:aa5281ff4a02 | 301 | #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ |
AnnaBridge | 161:aa5281ff4a02 | 302 | #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ |
AnnaBridge | 161:aa5281ff4a02 | 303 | #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ |
AnnaBridge | 161:aa5281ff4a02 | 304 | #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ |
AnnaBridge | 161:aa5281ff4a02 | 305 | #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ |
AnnaBridge | 161:aa5281ff4a02 | 306 | #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ |
AnnaBridge | 145:64910690c574 | 307 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 161:aa5281ff4a02 | 308 | #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ |
AnnaBridge | 145:64910690c574 | 309 | #endif /*USE_FULL_LL_DRIVER*/ |
AnnaBridge | 145:64910690c574 | 310 | /** |
AnnaBridge | 145:64910690c574 | 311 | * @} |
AnnaBridge | 145:64910690c574 | 312 | */ |
AnnaBridge | 145:64910690c574 | 313 | |
AnnaBridge | 145:64910690c574 | 314 | /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction |
AnnaBridge | 145:64910690c574 | 315 | * @{ |
AnnaBridge | 145:64910690c574 | 316 | */ |
AnnaBridge | 161:aa5281ff4a02 | 317 | #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ |
AnnaBridge | 145:64910690c574 | 318 | #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ |
AnnaBridge | 145:64910690c574 | 319 | #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ |
AnnaBridge | 145:64910690c574 | 320 | /** |
AnnaBridge | 145:64910690c574 | 321 | * @} |
AnnaBridge | 145:64910690c574 | 322 | */ |
AnnaBridge | 145:64910690c574 | 323 | |
AnnaBridge | 145:64910690c574 | 324 | /** @defgroup DMA_LL_EC_MODE Transfer mode |
AnnaBridge | 145:64910690c574 | 325 | * @{ |
AnnaBridge | 145:64910690c574 | 326 | */ |
AnnaBridge | 161:aa5281ff4a02 | 327 | #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ |
AnnaBridge | 145:64910690c574 | 328 | #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ |
AnnaBridge | 145:64910690c574 | 329 | /** |
AnnaBridge | 145:64910690c574 | 330 | * @} |
AnnaBridge | 145:64910690c574 | 331 | */ |
AnnaBridge | 145:64910690c574 | 332 | |
AnnaBridge | 145:64910690c574 | 333 | /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode |
AnnaBridge | 145:64910690c574 | 334 | * @{ |
AnnaBridge | 145:64910690c574 | 335 | */ |
AnnaBridge | 145:64910690c574 | 336 | #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ |
AnnaBridge | 161:aa5281ff4a02 | 337 | #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ |
AnnaBridge | 145:64910690c574 | 338 | /** |
AnnaBridge | 145:64910690c574 | 339 | * @} |
AnnaBridge | 145:64910690c574 | 340 | */ |
AnnaBridge | 145:64910690c574 | 341 | |
AnnaBridge | 145:64910690c574 | 342 | /** @defgroup DMA_LL_EC_MEMORY Memory increment mode |
AnnaBridge | 145:64910690c574 | 343 | * @{ |
AnnaBridge | 145:64910690c574 | 344 | */ |
AnnaBridge | 145:64910690c574 | 345 | #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ |
AnnaBridge | 161:aa5281ff4a02 | 346 | #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ |
AnnaBridge | 145:64910690c574 | 347 | /** |
AnnaBridge | 145:64910690c574 | 348 | * @} |
AnnaBridge | 145:64910690c574 | 349 | */ |
AnnaBridge | 145:64910690c574 | 350 | |
AnnaBridge | 145:64910690c574 | 351 | /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment |
AnnaBridge | 145:64910690c574 | 352 | * @{ |
AnnaBridge | 145:64910690c574 | 353 | */ |
AnnaBridge | 161:aa5281ff4a02 | 354 | #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ |
AnnaBridge | 145:64910690c574 | 355 | #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ |
AnnaBridge | 145:64910690c574 | 356 | #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ |
AnnaBridge | 145:64910690c574 | 357 | /** |
AnnaBridge | 145:64910690c574 | 358 | * @} |
AnnaBridge | 145:64910690c574 | 359 | */ |
AnnaBridge | 145:64910690c574 | 360 | |
AnnaBridge | 145:64910690c574 | 361 | /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment |
AnnaBridge | 145:64910690c574 | 362 | * @{ |
AnnaBridge | 145:64910690c574 | 363 | */ |
AnnaBridge | 161:aa5281ff4a02 | 364 | #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ |
AnnaBridge | 145:64910690c574 | 365 | #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ |
AnnaBridge | 145:64910690c574 | 366 | #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ |
AnnaBridge | 145:64910690c574 | 367 | /** |
AnnaBridge | 145:64910690c574 | 368 | * @} |
AnnaBridge | 145:64910690c574 | 369 | */ |
AnnaBridge | 145:64910690c574 | 370 | |
AnnaBridge | 145:64910690c574 | 371 | /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level |
AnnaBridge | 145:64910690c574 | 372 | * @{ |
AnnaBridge | 145:64910690c574 | 373 | */ |
AnnaBridge | 161:aa5281ff4a02 | 374 | #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ |
AnnaBridge | 145:64910690c574 | 375 | #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ |
AnnaBridge | 145:64910690c574 | 376 | #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ |
AnnaBridge | 145:64910690c574 | 377 | #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ |
AnnaBridge | 145:64910690c574 | 378 | /** |
AnnaBridge | 145:64910690c574 | 379 | * @} |
AnnaBridge | 145:64910690c574 | 380 | */ |
AnnaBridge | 145:64910690c574 | 381 | |
AnnaBridge | 161:aa5281ff4a02 | 382 | #if defined(DMAMUX1) |
AnnaBridge | 161:aa5281ff4a02 | 383 | /** @defgroup DMAMUX_LL_EC_REQUEST Transfer request |
AnnaBridge | 161:aa5281ff4a02 | 384 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 385 | */ |
AnnaBridge | 161:aa5281ff4a02 | 386 | #define LL_DMAMUX_REQUEST_MEM2MEM 0U /*!< Memory to memory transfer */ |
AnnaBridge | 161:aa5281ff4a02 | 387 | #define LL_DMAMUX_REQUEST_GENERATOR0 1U /*!< DMAMUX request generator 0 */ |
AnnaBridge | 161:aa5281ff4a02 | 388 | #define LL_DMAMUX_REQUEST_GENERATOR1 2U /*!< DMAMUX request generator 1 */ |
AnnaBridge | 161:aa5281ff4a02 | 389 | #define LL_DMAMUX_REQUEST_GENERATOR2 3U /*!< DMAMUX request generator 2 */ |
AnnaBridge | 161:aa5281ff4a02 | 390 | #define LL_DMAMUX_REQUEST_GENERATOR3 4U /*!< DMAMUX request generator 3 */ |
AnnaBridge | 161:aa5281ff4a02 | 391 | #define LL_DMAMUX_REQUEST_ADC1 5U /*!< DMAMUX ADC1 request */ |
AnnaBridge | 161:aa5281ff4a02 | 392 | #define LL_DMAMUX_REQUEST_DAC1_CH1 6U /*!< DMAMUX DAC1 CH1 request */ |
AnnaBridge | 161:aa5281ff4a02 | 393 | #define LL_DMAMUX_REQUEST_DAC1_CH2 7U /*!< DMAMUX DAC1 CH2 request */ |
AnnaBridge | 161:aa5281ff4a02 | 394 | #define LL_DMAMUX_REQUEST_TIM6_UP 8U /*!< DMAMUX TIM6 UP request */ |
AnnaBridge | 161:aa5281ff4a02 | 395 | #define LL_DMAMUX_REQUEST_TIM7_UP 9U /*!< DMAMUX TIM7 UP request */ |
AnnaBridge | 161:aa5281ff4a02 | 396 | #define LL_DMAMUX_REQUEST_SPI1_RX 10U /*!< DMAMUX SPI1 RX request */ |
AnnaBridge | 161:aa5281ff4a02 | 397 | #define LL_DMAMUX_REQUEST_SPI1_TX 11U /*!< DMAMUX SPI1 TX request */ |
AnnaBridge | 161:aa5281ff4a02 | 398 | #define LL_DMAMUX_REQUEST_SPI2_RX 12U /*!< DMAMUX SPI2 RX request */ |
AnnaBridge | 161:aa5281ff4a02 | 399 | #define LL_DMAMUX_REQUEST_SPI2_TX 13U /*!< DMAMUX SPI2 TX request */ |
AnnaBridge | 161:aa5281ff4a02 | 400 | #define LL_DMAMUX_REQUEST_SPI3_RX 14U /*!< DMAMUX SPI3 RX request */ |
AnnaBridge | 161:aa5281ff4a02 | 401 | #define LL_DMAMUX_REQUEST_SPI3_TX 15U /*!< DMAMUX SPI3 TX request */ |
AnnaBridge | 161:aa5281ff4a02 | 402 | #define LL_DMAMUX_REQUEST_I2C1_RX 16U /*!< DMAMUX I2C1 RX request */ |
AnnaBridge | 161:aa5281ff4a02 | 403 | #define LL_DMAMUX_REQUEST_I2C1_TX 17U /*!< DMAMUX I2C1 TX request */ |
AnnaBridge | 161:aa5281ff4a02 | 404 | #define LL_DMAMUX_REQUEST_I2C2_RX 18U /*!< DMAMUX I2C2 RX request */ |
AnnaBridge | 161:aa5281ff4a02 | 405 | #define LL_DMAMUX_REQUEST_I2C2_TX 19U /*!< DMAMUX I2C2 TX request */ |
AnnaBridge | 161:aa5281ff4a02 | 406 | #define LL_DMAMUX_REQUEST_I2C3_RX 20U /*!< DMAMUX I2C3 RX request */ |
AnnaBridge | 161:aa5281ff4a02 | 407 | #define LL_DMAMUX_REQUEST_I2C3_TX 21U /*!< DMAMUX I2C3 TX request */ |
AnnaBridge | 161:aa5281ff4a02 | 408 | #define LL_DMAMUX_REQUEST_I2C4_RX 22U /*!< DMAMUX I2C4 RX request */ |
AnnaBridge | 161:aa5281ff4a02 | 409 | #define LL_DMAMUX_REQUEST_I2C4_TX 23U /*!< DMAMUX I2C4 TX request */ |
AnnaBridge | 161:aa5281ff4a02 | 410 | #define LL_DMAMUX_REQUEST_USART1_RX 24U /*!< DMAMUX USART1 RX request */ |
AnnaBridge | 161:aa5281ff4a02 | 411 | #define LL_DMAMUX_REQUEST_USART1_TX 25U /*!< DMAMUX USART1 TX request */ |
AnnaBridge | 161:aa5281ff4a02 | 412 | #define LL_DMAMUX_REQUEST_USART2_RX 26U /*!< DMAMUX USART2 RX request */ |
AnnaBridge | 161:aa5281ff4a02 | 413 | #define LL_DMAMUX_REQUEST_USART2_TX 27U /*!< DMAMUX USART2 TX request */ |
AnnaBridge | 161:aa5281ff4a02 | 414 | #define LL_DMAMUX_REQUEST_USART3_RX 28U /*!< DMAMUX USART3 RX request */ |
AnnaBridge | 161:aa5281ff4a02 | 415 | #define LL_DMAMUX_REQUEST_USART3_TX 29U /*!< DMAMUX USART3 TX request */ |
AnnaBridge | 161:aa5281ff4a02 | 416 | #define LL_DMAMUX_REQUEST_UART4_RX 30U /*!< DMAMUX UART4 RX request */ |
AnnaBridge | 161:aa5281ff4a02 | 417 | #define LL_DMAMUX_REQUEST_UART4_TX 31U /*!< DMAMUX UART4 TX request */ |
AnnaBridge | 161:aa5281ff4a02 | 418 | #define LL_DMAMUX_REQUEST_UART5_RX 32U /*!< DMAMUX UART5 RX request */ |
AnnaBridge | 161:aa5281ff4a02 | 419 | #define LL_DMAMUX_REQUEST_UART5_TX 33U /*!< DMAMUX UART5 TX request */ |
AnnaBridge | 161:aa5281ff4a02 | 420 | #define LL_DMAMUX_REQUEST_LPUART1_RX 34U /*!< DMAMUX LPUART1 RX request */ |
AnnaBridge | 161:aa5281ff4a02 | 421 | #define LL_DMAMUX_REQUEST_LPUART1_TX 35U /*!< DMAMUX LPUART1 TX request */ |
AnnaBridge | 161:aa5281ff4a02 | 422 | #define LL_DMAMUX_REQUEST_SAI1_A 36U /*!< DMAMUX SAI1 A request */ |
AnnaBridge | 161:aa5281ff4a02 | 423 | #define LL_DMAMUX_REQUEST_SAI1_B 37U /*!< DMAMUX SAI1 B request */ |
AnnaBridge | 161:aa5281ff4a02 | 424 | #define LL_DMAMUX_REQUEST_SAI2_A 38U /*!< DMAMUX SAI2 A request */ |
AnnaBridge | 161:aa5281ff4a02 | 425 | #define LL_DMAMUX_REQUEST_SAI2_B 39U /*!< DMAMUX SAI2 B request */ |
AnnaBridge | 161:aa5281ff4a02 | 426 | #define LL_DMAMUX_REQUEST_OSPI1 40U /*!< DMAMUX OCTOSPI1 request */ |
AnnaBridge | 161:aa5281ff4a02 | 427 | #define LL_DMAMUX_REQUEST_OSPI2 41U /*!< DMAMUX OCTOSPI2 request */ |
AnnaBridge | 161:aa5281ff4a02 | 428 | #define LL_DMAMUX_REQUEST_TIM1_CH1 42U /*!< DMAMUX TIM1 CH1 request */ |
AnnaBridge | 161:aa5281ff4a02 | 429 | #define LL_DMAMUX_REQUEST_TIM1_CH2 43U /*!< DMAMUX TIM1 CH2 request */ |
AnnaBridge | 161:aa5281ff4a02 | 430 | #define LL_DMAMUX_REQUEST_TIM1_CH3 44U /*!< DMAMUX TIM1 CH3 request */ |
AnnaBridge | 161:aa5281ff4a02 | 431 | #define LL_DMAMUX_REQUEST_TIM1_CH4 45U /*!< DMAMUX TIM1 CH4 request */ |
AnnaBridge | 161:aa5281ff4a02 | 432 | #define LL_DMAMUX_REQUEST_TIM1_UP 46U /*!< DMAMUX TIM1 UP request */ |
AnnaBridge | 161:aa5281ff4a02 | 433 | #define LL_DMAMUX_REQUEST_TIM1_TRIG 47U /*!< DMAMUX TIM1 TRIG request */ |
AnnaBridge | 161:aa5281ff4a02 | 434 | #define LL_DMAMUX_REQUEST_TIM1_COM 48U /*!< DMAMUX TIM1 COM request */ |
AnnaBridge | 161:aa5281ff4a02 | 435 | #define LL_DMAMUX_REQUEST_TIM8_CH1 49U /*!< DMAMUX TIM8 CH1 request */ |
AnnaBridge | 161:aa5281ff4a02 | 436 | #define LL_DMAMUX_REQUEST_TIM8_CH2 50U /*!< DMAMUX TIM8 CH2 request */ |
AnnaBridge | 161:aa5281ff4a02 | 437 | #define LL_DMAMUX_REQUEST_TIM8_CH3 51U /*!< DMAMUX TIM8 CH3 request */ |
AnnaBridge | 161:aa5281ff4a02 | 438 | #define LL_DMAMUX_REQUEST_TIM8_CH4 52U /*!< DMAMUX TIM8 CH4 request */ |
AnnaBridge | 161:aa5281ff4a02 | 439 | #define LL_DMAMUX_REQUEST_TIM8_UP 53U /*!< DMAMUX TIM8 UP request */ |
AnnaBridge | 161:aa5281ff4a02 | 440 | #define LL_DMAMUX_REQUEST_TIM8_TRIG 54U /*!< DMAMUX TIM8 TRIG request */ |
AnnaBridge | 161:aa5281ff4a02 | 441 | #define LL_DMAMUX_REQUEST_TIM8_COM 55U /*!< DMAMUX TIM8 COM request */ |
AnnaBridge | 161:aa5281ff4a02 | 442 | #define LL_DMAMUX_REQUEST_TIM2_CH1 56U /*!< DMAMUX TIM2 CH1 request */ |
AnnaBridge | 161:aa5281ff4a02 | 443 | #define LL_DMAMUX_REQUEST_TIM2_CH2 57U /*!< DMAMUX TIM2 CH2 request */ |
AnnaBridge | 161:aa5281ff4a02 | 444 | #define LL_DMAMUX_REQUEST_TIM2_CH3 58U /*!< DMAMUX TIM2 CH3 request */ |
AnnaBridge | 161:aa5281ff4a02 | 445 | #define LL_DMAMUX_REQUEST_TIM2_CH4 59U /*!< DMAMUX TIM2 CH4 request */ |
AnnaBridge | 161:aa5281ff4a02 | 446 | #define LL_DMAMUX_REQUEST_TIM2_UP 60U /*!< DMAMUX TIM2 UP request */ |
AnnaBridge | 161:aa5281ff4a02 | 447 | #define LL_DMAMUX_REQUEST_TIM3_CH1 61U /*!< DMAMUX TIM3 CH1 request */ |
AnnaBridge | 161:aa5281ff4a02 | 448 | #define LL_DMAMUX_REQUEST_TIM3_CH2 62U /*!< DMAMUX TIM3 CH2 request */ |
AnnaBridge | 161:aa5281ff4a02 | 449 | #define LL_DMAMUX_REQUEST_TIM3_CH3 63U /*!< DMAMUX TIM3 CH3 request */ |
AnnaBridge | 161:aa5281ff4a02 | 450 | #define LL_DMAMUX_REQUEST_TIM3_CH4 64U /*!< DMAMUX TIM3 CH4 request */ |
AnnaBridge | 161:aa5281ff4a02 | 451 | #define LL_DMAMUX_REQUEST_TIM3_UP 65U /*!< DMAMUX TIM3 UP request */ |
AnnaBridge | 161:aa5281ff4a02 | 452 | #define LL_DMAMUX_REQUEST_TIM3_TRIG 66U /*!< DMAMUX TIM3 TRIG request */ |
AnnaBridge | 161:aa5281ff4a02 | 453 | #define LL_DMAMUX_REQUEST_TIM4_CH1 67U /*!< DMAMUX TIM4 CH1 request */ |
AnnaBridge | 161:aa5281ff4a02 | 454 | #define LL_DMAMUX_REQUEST_TIM4_CH2 68U /*!< DMAMUX TIM4 CH2 request */ |
AnnaBridge | 161:aa5281ff4a02 | 455 | #define LL_DMAMUX_REQUEST_TIM4_CH3 69U /*!< DMAMUX TIM4 CH3 request */ |
AnnaBridge | 161:aa5281ff4a02 | 456 | #define LL_DMAMUX_REQUEST_TIM4_CH4 70U /*!< DMAMUX TIM4 CH4 request */ |
AnnaBridge | 161:aa5281ff4a02 | 457 | #define LL_DMAMUX_REQUEST_TIM4_UP 71U /*!< DMAMUX TIM4 UP request */ |
AnnaBridge | 161:aa5281ff4a02 | 458 | #define LL_DMAMUX_REQUEST_TIM5_CH1 72U /*!< DMAMUX TIM5 CH1 request */ |
AnnaBridge | 161:aa5281ff4a02 | 459 | #define LL_DMAMUX_REQUEST_TIM5_CH2 73U /*!< DMAMUX TIM5 CH2 request */ |
AnnaBridge | 161:aa5281ff4a02 | 460 | #define LL_DMAMUX_REQUEST_TIM5_CH3 74U /*!< DMAMUX TIM5 CH3 request */ |
AnnaBridge | 161:aa5281ff4a02 | 461 | #define LL_DMAMUX_REQUEST_TIM5_CH4 75U /*!< DMAMUX TIM5 CH4 request */ |
AnnaBridge | 161:aa5281ff4a02 | 462 | #define LL_DMAMUX_REQUEST_TIM5_UP 76U /*!< DMAMUX TIM5 UP request */ |
AnnaBridge | 161:aa5281ff4a02 | 463 | #define LL_DMAMUX_REQUEST_TIM5_TRIG 77U /*!< DMAMUX TIM5 TRIG request */ |
AnnaBridge | 161:aa5281ff4a02 | 464 | #define LL_DMAMUX_REQUEST_TIM15_CH1 78U /*!< DMAMUX TIM15 CH1 request */ |
AnnaBridge | 161:aa5281ff4a02 | 465 | #define LL_DMAMUX_REQUEST_TIM15_UP 79U /*!< DMAMUX TIM15 UP request */ |
AnnaBridge | 161:aa5281ff4a02 | 466 | #define LL_DMAMUX_REQUEST_TIM15_TRIG 80U /*!< DMAMUX TIM15 TRIG request */ |
AnnaBridge | 161:aa5281ff4a02 | 467 | #define LL_DMAMUX_REQUEST_TIM15_COM 81U /*!< DMAMUX TIM15 COM request */ |
AnnaBridge | 161:aa5281ff4a02 | 468 | #define LL_DMAMUX_REQUEST_TIM16_CH1 82U /*!< DMAMUX TIM16 CH1 request */ |
AnnaBridge | 161:aa5281ff4a02 | 469 | #define LL_DMAMUX_REQUEST_TIM16_UP 83U /*!< DMAMUX TIM16 UP request */ |
AnnaBridge | 161:aa5281ff4a02 | 470 | #define LL_DMAMUX_REQUEST_TIM17_CH1 84U /*!< DMAMUX TIM17 CH1 request */ |
AnnaBridge | 161:aa5281ff4a02 | 471 | #define LL_DMAMUX_REQUEST_TIM17_UP 85U /*!< DMAMUX TIM17 UP request */ |
AnnaBridge | 161:aa5281ff4a02 | 472 | #define LL_DMAMUX_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX DFSDM1_FLT0 request */ |
AnnaBridge | 161:aa5281ff4a02 | 473 | #define LL_DMAMUX_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX DFSDM1_FLT1 request */ |
AnnaBridge | 161:aa5281ff4a02 | 474 | #define LL_DMAMUX_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX DFSDM1_FLT2 request */ |
AnnaBridge | 161:aa5281ff4a02 | 475 | #define LL_DMAMUX_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX DFSDM1_FLT3 request */ |
AnnaBridge | 161:aa5281ff4a02 | 476 | #define LL_DMAMUX_REQUEST_DCMI 90U /*!< DMAMUX DCMI request */ |
AnnaBridge | 161:aa5281ff4a02 | 477 | #define LL_DMAMUX_REQUEST_AES_IN 91U /*!< DMAMUX AES_IN request */ |
AnnaBridge | 161:aa5281ff4a02 | 478 | #define LL_DMAMUX_REQUEST_AES_OUT 92U /*!< DMAMUX AES_OUT request */ |
AnnaBridge | 161:aa5281ff4a02 | 479 | #define LL_DMAMUX_REQUEST_HASH_IN 93U /*!< DMAMUX HASH_IN request */ |
AnnaBridge | 161:aa5281ff4a02 | 480 | /** |
AnnaBridge | 161:aa5281ff4a02 | 481 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 482 | */ |
AnnaBridge | 161:aa5281ff4a02 | 483 | #else |
AnnaBridge | 145:64910690c574 | 484 | /** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request |
AnnaBridge | 145:64910690c574 | 485 | * @{ |
AnnaBridge | 145:64910690c574 | 486 | */ |
AnnaBridge | 161:aa5281ff4a02 | 487 | #define LL_DMA_REQUEST_0 0x00000000U /*!< DMA peripheral request 0 */ |
AnnaBridge | 161:aa5281ff4a02 | 488 | #define LL_DMA_REQUEST_1 0x00000001U /*!< DMA peripheral request 1 */ |
AnnaBridge | 161:aa5281ff4a02 | 489 | #define LL_DMA_REQUEST_2 0x00000002U /*!< DMA peripheral request 2 */ |
AnnaBridge | 161:aa5281ff4a02 | 490 | #define LL_DMA_REQUEST_3 0x00000003U /*!< DMA peripheral request 3 */ |
AnnaBridge | 161:aa5281ff4a02 | 491 | #define LL_DMA_REQUEST_4 0x00000004U /*!< DMA peripheral request 4 */ |
AnnaBridge | 161:aa5281ff4a02 | 492 | #define LL_DMA_REQUEST_5 0x00000005U /*!< DMA peripheral request 5 */ |
AnnaBridge | 161:aa5281ff4a02 | 493 | #define LL_DMA_REQUEST_6 0x00000006U /*!< DMA peripheral request 6 */ |
AnnaBridge | 161:aa5281ff4a02 | 494 | #define LL_DMA_REQUEST_7 0x00000007U /*!< DMA peripheral request 7 */ |
AnnaBridge | 145:64910690c574 | 495 | /** |
AnnaBridge | 145:64910690c574 | 496 | * @} |
AnnaBridge | 145:64910690c574 | 497 | */ |
AnnaBridge | 161:aa5281ff4a02 | 498 | #endif /* DMAMUX1 */ |
AnnaBridge | 145:64910690c574 | 499 | |
AnnaBridge | 145:64910690c574 | 500 | /** |
AnnaBridge | 145:64910690c574 | 501 | * @} |
AnnaBridge | 145:64910690c574 | 502 | */ |
AnnaBridge | 145:64910690c574 | 503 | |
AnnaBridge | 145:64910690c574 | 504 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 505 | /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros |
AnnaBridge | 145:64910690c574 | 506 | * @{ |
AnnaBridge | 145:64910690c574 | 507 | */ |
AnnaBridge | 145:64910690c574 | 508 | |
AnnaBridge | 145:64910690c574 | 509 | /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros |
AnnaBridge | 145:64910690c574 | 510 | * @{ |
AnnaBridge | 145:64910690c574 | 511 | */ |
AnnaBridge | 145:64910690c574 | 512 | /** |
AnnaBridge | 145:64910690c574 | 513 | * @brief Write a value in DMA register |
AnnaBridge | 145:64910690c574 | 514 | * @param __INSTANCE__ DMA Instance |
AnnaBridge | 145:64910690c574 | 515 | * @param __REG__ Register to be written |
AnnaBridge | 145:64910690c574 | 516 | * @param __VALUE__ Value to be written in the register |
AnnaBridge | 145:64910690c574 | 517 | * @retval None |
AnnaBridge | 145:64910690c574 | 518 | */ |
AnnaBridge | 145:64910690c574 | 519 | #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
AnnaBridge | 145:64910690c574 | 520 | |
AnnaBridge | 145:64910690c574 | 521 | /** |
AnnaBridge | 145:64910690c574 | 522 | * @brief Read a value in DMA register |
AnnaBridge | 145:64910690c574 | 523 | * @param __INSTANCE__ DMA Instance |
AnnaBridge | 145:64910690c574 | 524 | * @param __REG__ Register to be read |
AnnaBridge | 145:64910690c574 | 525 | * @retval Register value |
AnnaBridge | 145:64910690c574 | 526 | */ |
AnnaBridge | 145:64910690c574 | 527 | #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
AnnaBridge | 145:64910690c574 | 528 | /** |
AnnaBridge | 145:64910690c574 | 529 | * @} |
AnnaBridge | 145:64910690c574 | 530 | */ |
AnnaBridge | 145:64910690c574 | 531 | |
AnnaBridge | 145:64910690c574 | 532 | /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely |
AnnaBridge | 145:64910690c574 | 533 | * @{ |
AnnaBridge | 145:64910690c574 | 534 | */ |
AnnaBridge | 145:64910690c574 | 535 | /** |
AnnaBridge | 145:64910690c574 | 536 | * @brief Convert DMAx_Channely into DMAx |
AnnaBridge | 145:64910690c574 | 537 | * @param __CHANNEL_INSTANCE__ DMAx_Channely |
AnnaBridge | 145:64910690c574 | 538 | * @retval DMAx |
AnnaBridge | 145:64910690c574 | 539 | */ |
AnnaBridge | 145:64910690c574 | 540 | #if defined(DMA2) |
AnnaBridge | 145:64910690c574 | 541 | #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ |
AnnaBridge | 145:64910690c574 | 542 | (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) |
AnnaBridge | 145:64910690c574 | 543 | #else |
AnnaBridge | 145:64910690c574 | 544 | #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) |
AnnaBridge | 145:64910690c574 | 545 | #endif |
AnnaBridge | 145:64910690c574 | 546 | |
AnnaBridge | 145:64910690c574 | 547 | /** |
AnnaBridge | 145:64910690c574 | 548 | * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y |
AnnaBridge | 145:64910690c574 | 549 | * @param __CHANNEL_INSTANCE__ DMAx_Channely |
AnnaBridge | 145:64910690c574 | 550 | * @retval LL_DMA_CHANNEL_y |
AnnaBridge | 145:64910690c574 | 551 | */ |
AnnaBridge | 145:64910690c574 | 552 | #if defined (DMA2) |
AnnaBridge | 145:64910690c574 | 553 | #if defined (DMA2_Channel6) && defined (DMA2_Channel7) |
AnnaBridge | 145:64910690c574 | 554 | #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ |
AnnaBridge | 145:64910690c574 | 555 | (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ |
AnnaBridge | 145:64910690c574 | 556 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ |
AnnaBridge | 145:64910690c574 | 557 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ |
AnnaBridge | 145:64910690c574 | 558 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ |
AnnaBridge | 145:64910690c574 | 559 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ |
AnnaBridge | 145:64910690c574 | 560 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ |
AnnaBridge | 145:64910690c574 | 561 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ |
AnnaBridge | 145:64910690c574 | 562 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ |
AnnaBridge | 145:64910690c574 | 563 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ |
AnnaBridge | 145:64910690c574 | 564 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ |
AnnaBridge | 145:64910690c574 | 565 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ |
AnnaBridge | 145:64910690c574 | 566 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \ |
AnnaBridge | 145:64910690c574 | 567 | LL_DMA_CHANNEL_7) |
AnnaBridge | 145:64910690c574 | 568 | #else |
AnnaBridge | 145:64910690c574 | 569 | #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ |
AnnaBridge | 145:64910690c574 | 570 | (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ |
AnnaBridge | 145:64910690c574 | 571 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ |
AnnaBridge | 145:64910690c574 | 572 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ |
AnnaBridge | 145:64910690c574 | 573 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ |
AnnaBridge | 145:64910690c574 | 574 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ |
AnnaBridge | 145:64910690c574 | 575 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ |
AnnaBridge | 145:64910690c574 | 576 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ |
AnnaBridge | 145:64910690c574 | 577 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ |
AnnaBridge | 145:64910690c574 | 578 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ |
AnnaBridge | 145:64910690c574 | 579 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ |
AnnaBridge | 145:64910690c574 | 580 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ |
AnnaBridge | 145:64910690c574 | 581 | LL_DMA_CHANNEL_7) |
AnnaBridge | 145:64910690c574 | 582 | #endif |
AnnaBridge | 145:64910690c574 | 583 | #else |
AnnaBridge | 145:64910690c574 | 584 | #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ |
AnnaBridge | 145:64910690c574 | 585 | (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ |
AnnaBridge | 145:64910690c574 | 586 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ |
AnnaBridge | 145:64910690c574 | 587 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ |
AnnaBridge | 145:64910690c574 | 588 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ |
AnnaBridge | 145:64910690c574 | 589 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ |
AnnaBridge | 145:64910690c574 | 590 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ |
AnnaBridge | 145:64910690c574 | 591 | LL_DMA_CHANNEL_7) |
AnnaBridge | 145:64910690c574 | 592 | #endif |
AnnaBridge | 145:64910690c574 | 593 | |
AnnaBridge | 145:64910690c574 | 594 | /** |
AnnaBridge | 145:64910690c574 | 595 | * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely |
AnnaBridge | 145:64910690c574 | 596 | * @param __DMA_INSTANCE__ DMAx |
AnnaBridge | 145:64910690c574 | 597 | * @param __CHANNEL__ LL_DMA_CHANNEL_y |
AnnaBridge | 145:64910690c574 | 598 | * @retval DMAx_Channely |
AnnaBridge | 145:64910690c574 | 599 | */ |
AnnaBridge | 145:64910690c574 | 600 | #if defined (DMA2) |
AnnaBridge | 145:64910690c574 | 601 | #if defined (DMA2_Channel6) && defined (DMA2_Channel7) |
AnnaBridge | 145:64910690c574 | 602 | #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ |
AnnaBridge | 145:64910690c574 | 603 | ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ |
AnnaBridge | 145:64910690c574 | 604 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ |
AnnaBridge | 145:64910690c574 | 605 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ |
AnnaBridge | 145:64910690c574 | 606 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ |
AnnaBridge | 145:64910690c574 | 607 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ |
AnnaBridge | 145:64910690c574 | 608 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ |
AnnaBridge | 145:64910690c574 | 609 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ |
AnnaBridge | 145:64910690c574 | 610 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ |
AnnaBridge | 145:64910690c574 | 611 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ |
AnnaBridge | 145:64910690c574 | 612 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ |
AnnaBridge | 145:64910690c574 | 613 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ |
AnnaBridge | 145:64910690c574 | 614 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \ |
AnnaBridge | 145:64910690c574 | 615 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \ |
AnnaBridge | 145:64910690c574 | 616 | DMA2_Channel7) |
AnnaBridge | 145:64910690c574 | 617 | #else |
AnnaBridge | 145:64910690c574 | 618 | #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ |
AnnaBridge | 145:64910690c574 | 619 | ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ |
AnnaBridge | 145:64910690c574 | 620 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ |
AnnaBridge | 145:64910690c574 | 621 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ |
AnnaBridge | 145:64910690c574 | 622 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ |
AnnaBridge | 145:64910690c574 | 623 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ |
AnnaBridge | 145:64910690c574 | 624 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ |
AnnaBridge | 145:64910690c574 | 625 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ |
AnnaBridge | 145:64910690c574 | 626 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ |
AnnaBridge | 145:64910690c574 | 627 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ |
AnnaBridge | 145:64910690c574 | 628 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ |
AnnaBridge | 145:64910690c574 | 629 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ |
AnnaBridge | 145:64910690c574 | 630 | DMA1_Channel7) |
AnnaBridge | 145:64910690c574 | 631 | #endif |
AnnaBridge | 145:64910690c574 | 632 | #else |
AnnaBridge | 145:64910690c574 | 633 | #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ |
AnnaBridge | 145:64910690c574 | 634 | ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ |
AnnaBridge | 145:64910690c574 | 635 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ |
AnnaBridge | 145:64910690c574 | 636 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ |
AnnaBridge | 145:64910690c574 | 637 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ |
AnnaBridge | 145:64910690c574 | 638 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ |
AnnaBridge | 145:64910690c574 | 639 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ |
AnnaBridge | 145:64910690c574 | 640 | DMA1_Channel7) |
AnnaBridge | 145:64910690c574 | 641 | #endif |
AnnaBridge | 145:64910690c574 | 642 | |
AnnaBridge | 145:64910690c574 | 643 | /** |
AnnaBridge | 145:64910690c574 | 644 | * @} |
AnnaBridge | 145:64910690c574 | 645 | */ |
AnnaBridge | 145:64910690c574 | 646 | |
AnnaBridge | 145:64910690c574 | 647 | /** |
AnnaBridge | 145:64910690c574 | 648 | * @} |
AnnaBridge | 145:64910690c574 | 649 | */ |
AnnaBridge | 145:64910690c574 | 650 | |
AnnaBridge | 145:64910690c574 | 651 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 145:64910690c574 | 652 | /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions |
AnnaBridge | 145:64910690c574 | 653 | * @{ |
AnnaBridge | 145:64910690c574 | 654 | */ |
AnnaBridge | 145:64910690c574 | 655 | |
AnnaBridge | 145:64910690c574 | 656 | /** @defgroup DMA_LL_EF_Configuration Configuration |
AnnaBridge | 145:64910690c574 | 657 | * @{ |
AnnaBridge | 145:64910690c574 | 658 | */ |
AnnaBridge | 145:64910690c574 | 659 | /** |
AnnaBridge | 145:64910690c574 | 660 | * @brief Enable DMA channel. |
AnnaBridge | 145:64910690c574 | 661 | * @rmtoll CCR EN LL_DMA_EnableChannel |
AnnaBridge | 145:64910690c574 | 662 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 663 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 664 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 665 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 666 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 667 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 668 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 669 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 670 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 671 | * @retval None |
AnnaBridge | 145:64910690c574 | 672 | */ |
AnnaBridge | 145:64910690c574 | 673 | __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 674 | { |
AnnaBridge | 145:64910690c574 | 675 | SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); |
AnnaBridge | 145:64910690c574 | 676 | } |
AnnaBridge | 145:64910690c574 | 677 | |
AnnaBridge | 145:64910690c574 | 678 | /** |
AnnaBridge | 145:64910690c574 | 679 | * @brief Disable DMA channel. |
AnnaBridge | 145:64910690c574 | 680 | * @rmtoll CCR EN LL_DMA_DisableChannel |
AnnaBridge | 145:64910690c574 | 681 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 682 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 683 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 684 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 685 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 686 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 687 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 688 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 689 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 690 | * @retval None |
AnnaBridge | 145:64910690c574 | 691 | */ |
AnnaBridge | 145:64910690c574 | 692 | __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 693 | { |
AnnaBridge | 145:64910690c574 | 694 | CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); |
AnnaBridge | 145:64910690c574 | 695 | } |
AnnaBridge | 145:64910690c574 | 696 | |
AnnaBridge | 145:64910690c574 | 697 | /** |
AnnaBridge | 145:64910690c574 | 698 | * @brief Check if DMA channel is enabled or disabled. |
AnnaBridge | 145:64910690c574 | 699 | * @rmtoll CCR EN LL_DMA_IsEnabledChannel |
AnnaBridge | 145:64910690c574 | 700 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 701 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 702 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 703 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 704 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 705 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 706 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 707 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 708 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 709 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 710 | */ |
AnnaBridge | 145:64910690c574 | 711 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 712 | { |
AnnaBridge | 145:64910690c574 | 713 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 145:64910690c574 | 714 | DMA_CCR_EN) == (DMA_CCR_EN)); |
AnnaBridge | 145:64910690c574 | 715 | } |
AnnaBridge | 145:64910690c574 | 716 | |
AnnaBridge | 145:64910690c574 | 717 | /** |
AnnaBridge | 145:64910690c574 | 718 | * @brief Configure all parameters link to DMA transfer. |
AnnaBridge | 145:64910690c574 | 719 | * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n |
AnnaBridge | 145:64910690c574 | 720 | * CCR MEM2MEM LL_DMA_ConfigTransfer\n |
AnnaBridge | 145:64910690c574 | 721 | * CCR CIRC LL_DMA_ConfigTransfer\n |
AnnaBridge | 145:64910690c574 | 722 | * CCR PINC LL_DMA_ConfigTransfer\n |
AnnaBridge | 145:64910690c574 | 723 | * CCR MINC LL_DMA_ConfigTransfer\n |
AnnaBridge | 145:64910690c574 | 724 | * CCR PSIZE LL_DMA_ConfigTransfer\n |
AnnaBridge | 145:64910690c574 | 725 | * CCR MSIZE LL_DMA_ConfigTransfer\n |
AnnaBridge | 145:64910690c574 | 726 | * CCR PL LL_DMA_ConfigTransfer |
AnnaBridge | 145:64910690c574 | 727 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 728 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 729 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 730 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 731 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 732 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 733 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 734 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 735 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 736 | * @param Configuration This parameter must be a combination of all the following values: |
AnnaBridge | 145:64910690c574 | 737 | * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY |
AnnaBridge | 145:64910690c574 | 738 | * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR |
AnnaBridge | 145:64910690c574 | 739 | * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT |
AnnaBridge | 145:64910690c574 | 740 | * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT |
AnnaBridge | 145:64910690c574 | 741 | * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD |
AnnaBridge | 145:64910690c574 | 742 | * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD |
AnnaBridge | 145:64910690c574 | 743 | * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH |
AnnaBridge | 145:64910690c574 | 744 | * @retval None |
AnnaBridge | 145:64910690c574 | 745 | */ |
AnnaBridge | 145:64910690c574 | 746 | __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) |
AnnaBridge | 145:64910690c574 | 747 | { |
AnnaBridge | 145:64910690c574 | 748 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 145:64910690c574 | 749 | DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, |
AnnaBridge | 145:64910690c574 | 750 | Configuration); |
AnnaBridge | 145:64910690c574 | 751 | } |
AnnaBridge | 145:64910690c574 | 752 | |
AnnaBridge | 145:64910690c574 | 753 | /** |
AnnaBridge | 145:64910690c574 | 754 | * @brief Set Data transfer direction (read from peripheral or from memory). |
AnnaBridge | 145:64910690c574 | 755 | * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n |
AnnaBridge | 145:64910690c574 | 756 | * CCR MEM2MEM LL_DMA_SetDataTransferDirection |
AnnaBridge | 145:64910690c574 | 757 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 758 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 759 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 760 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 761 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 762 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 763 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 764 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 765 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 766 | * @param Direction This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 767 | * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY |
AnnaBridge | 145:64910690c574 | 768 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH |
AnnaBridge | 145:64910690c574 | 769 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY |
AnnaBridge | 145:64910690c574 | 770 | * @retval None |
AnnaBridge | 145:64910690c574 | 771 | */ |
AnnaBridge | 145:64910690c574 | 772 | __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) |
AnnaBridge | 145:64910690c574 | 773 | { |
AnnaBridge | 145:64910690c574 | 774 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 145:64910690c574 | 775 | DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); |
AnnaBridge | 145:64910690c574 | 776 | } |
AnnaBridge | 145:64910690c574 | 777 | |
AnnaBridge | 145:64910690c574 | 778 | /** |
AnnaBridge | 145:64910690c574 | 779 | * @brief Get Data transfer direction (read from peripheral or from memory). |
AnnaBridge | 145:64910690c574 | 780 | * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n |
AnnaBridge | 145:64910690c574 | 781 | * CCR MEM2MEM LL_DMA_GetDataTransferDirection |
AnnaBridge | 145:64910690c574 | 782 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 783 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 784 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 785 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 786 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 787 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 788 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 789 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 790 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 791 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 792 | * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY |
AnnaBridge | 145:64910690c574 | 793 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH |
AnnaBridge | 145:64910690c574 | 794 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY |
AnnaBridge | 145:64910690c574 | 795 | */ |
AnnaBridge | 145:64910690c574 | 796 | __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 797 | { |
AnnaBridge | 145:64910690c574 | 798 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 145:64910690c574 | 799 | DMA_CCR_DIR | DMA_CCR_MEM2MEM)); |
AnnaBridge | 145:64910690c574 | 800 | } |
AnnaBridge | 145:64910690c574 | 801 | |
AnnaBridge | 145:64910690c574 | 802 | /** |
AnnaBridge | 145:64910690c574 | 803 | * @brief Set DMA mode circular or normal. |
AnnaBridge | 145:64910690c574 | 804 | * @note The circular buffer mode cannot be used if the memory-to-memory |
AnnaBridge | 145:64910690c574 | 805 | * data transfer is configured on the selected Channel. |
AnnaBridge | 145:64910690c574 | 806 | * @rmtoll CCR CIRC LL_DMA_SetMode |
AnnaBridge | 145:64910690c574 | 807 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 808 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 809 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 810 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 811 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 812 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 813 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 814 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 815 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 816 | * @param Mode This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 817 | * @arg @ref LL_DMA_MODE_NORMAL |
AnnaBridge | 145:64910690c574 | 818 | * @arg @ref LL_DMA_MODE_CIRCULAR |
AnnaBridge | 145:64910690c574 | 819 | * @retval None |
AnnaBridge | 145:64910690c574 | 820 | */ |
AnnaBridge | 145:64910690c574 | 821 | __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) |
AnnaBridge | 145:64910690c574 | 822 | { |
AnnaBridge | 145:64910690c574 | 823 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, |
AnnaBridge | 145:64910690c574 | 824 | Mode); |
AnnaBridge | 145:64910690c574 | 825 | } |
AnnaBridge | 145:64910690c574 | 826 | |
AnnaBridge | 145:64910690c574 | 827 | /** |
AnnaBridge | 145:64910690c574 | 828 | * @brief Get DMA mode circular or normal. |
AnnaBridge | 145:64910690c574 | 829 | * @rmtoll CCR CIRC LL_DMA_GetMode |
AnnaBridge | 145:64910690c574 | 830 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 831 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 832 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 833 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 834 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 835 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 836 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 837 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 838 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 839 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 840 | * @arg @ref LL_DMA_MODE_NORMAL |
AnnaBridge | 145:64910690c574 | 841 | * @arg @ref LL_DMA_MODE_CIRCULAR |
AnnaBridge | 145:64910690c574 | 842 | */ |
AnnaBridge | 145:64910690c574 | 843 | __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 844 | { |
AnnaBridge | 145:64910690c574 | 845 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 145:64910690c574 | 846 | DMA_CCR_CIRC)); |
AnnaBridge | 145:64910690c574 | 847 | } |
AnnaBridge | 145:64910690c574 | 848 | |
AnnaBridge | 145:64910690c574 | 849 | /** |
AnnaBridge | 145:64910690c574 | 850 | * @brief Set Peripheral increment mode. |
AnnaBridge | 145:64910690c574 | 851 | * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode |
AnnaBridge | 145:64910690c574 | 852 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 853 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 854 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 855 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 856 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 857 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 858 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 859 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 860 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 861 | * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 862 | * @arg @ref LL_DMA_PERIPH_INCREMENT |
AnnaBridge | 145:64910690c574 | 863 | * @arg @ref LL_DMA_PERIPH_NOINCREMENT |
AnnaBridge | 145:64910690c574 | 864 | * @retval None |
AnnaBridge | 145:64910690c574 | 865 | */ |
AnnaBridge | 145:64910690c574 | 866 | __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) |
AnnaBridge | 145:64910690c574 | 867 | { |
AnnaBridge | 145:64910690c574 | 868 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, |
AnnaBridge | 145:64910690c574 | 869 | PeriphOrM2MSrcIncMode); |
AnnaBridge | 145:64910690c574 | 870 | } |
AnnaBridge | 145:64910690c574 | 871 | |
AnnaBridge | 145:64910690c574 | 872 | /** |
AnnaBridge | 145:64910690c574 | 873 | * @brief Get Peripheral increment mode. |
AnnaBridge | 145:64910690c574 | 874 | * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode |
AnnaBridge | 145:64910690c574 | 875 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 876 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 877 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 878 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 879 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 880 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 881 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 882 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 883 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 884 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 885 | * @arg @ref LL_DMA_PERIPH_INCREMENT |
AnnaBridge | 145:64910690c574 | 886 | * @arg @ref LL_DMA_PERIPH_NOINCREMENT |
AnnaBridge | 145:64910690c574 | 887 | */ |
AnnaBridge | 145:64910690c574 | 888 | __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 889 | { |
AnnaBridge | 145:64910690c574 | 890 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 145:64910690c574 | 891 | DMA_CCR_PINC)); |
AnnaBridge | 145:64910690c574 | 892 | } |
AnnaBridge | 145:64910690c574 | 893 | |
AnnaBridge | 145:64910690c574 | 894 | /** |
AnnaBridge | 145:64910690c574 | 895 | * @brief Set Memory increment mode. |
AnnaBridge | 145:64910690c574 | 896 | * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode |
AnnaBridge | 145:64910690c574 | 897 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 898 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 899 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 900 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 901 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 902 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 903 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 904 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 905 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 906 | * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 907 | * @arg @ref LL_DMA_MEMORY_INCREMENT |
AnnaBridge | 145:64910690c574 | 908 | * @arg @ref LL_DMA_MEMORY_NOINCREMENT |
AnnaBridge | 145:64910690c574 | 909 | * @retval None |
AnnaBridge | 145:64910690c574 | 910 | */ |
AnnaBridge | 145:64910690c574 | 911 | __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) |
AnnaBridge | 145:64910690c574 | 912 | { |
AnnaBridge | 145:64910690c574 | 913 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, |
AnnaBridge | 145:64910690c574 | 914 | MemoryOrM2MDstIncMode); |
AnnaBridge | 145:64910690c574 | 915 | } |
AnnaBridge | 145:64910690c574 | 916 | |
AnnaBridge | 145:64910690c574 | 917 | /** |
AnnaBridge | 145:64910690c574 | 918 | * @brief Get Memory increment mode. |
AnnaBridge | 145:64910690c574 | 919 | * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode |
AnnaBridge | 145:64910690c574 | 920 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 921 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 922 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 923 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 924 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 925 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 926 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 927 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 928 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 929 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 930 | * @arg @ref LL_DMA_MEMORY_INCREMENT |
AnnaBridge | 145:64910690c574 | 931 | * @arg @ref LL_DMA_MEMORY_NOINCREMENT |
AnnaBridge | 145:64910690c574 | 932 | */ |
AnnaBridge | 145:64910690c574 | 933 | __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 934 | { |
AnnaBridge | 145:64910690c574 | 935 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 145:64910690c574 | 936 | DMA_CCR_MINC)); |
AnnaBridge | 145:64910690c574 | 937 | } |
AnnaBridge | 145:64910690c574 | 938 | |
AnnaBridge | 145:64910690c574 | 939 | /** |
AnnaBridge | 145:64910690c574 | 940 | * @brief Set Peripheral size. |
AnnaBridge | 145:64910690c574 | 941 | * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize |
AnnaBridge | 145:64910690c574 | 942 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 943 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 944 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 945 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 946 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 947 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 948 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 949 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 950 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 951 | * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 952 | * @arg @ref LL_DMA_PDATAALIGN_BYTE |
AnnaBridge | 145:64910690c574 | 953 | * @arg @ref LL_DMA_PDATAALIGN_HALFWORD |
AnnaBridge | 145:64910690c574 | 954 | * @arg @ref LL_DMA_PDATAALIGN_WORD |
AnnaBridge | 145:64910690c574 | 955 | * @retval None |
AnnaBridge | 145:64910690c574 | 956 | */ |
AnnaBridge | 145:64910690c574 | 957 | __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) |
AnnaBridge | 145:64910690c574 | 958 | { |
AnnaBridge | 145:64910690c574 | 959 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, |
AnnaBridge | 145:64910690c574 | 960 | PeriphOrM2MSrcDataSize); |
AnnaBridge | 145:64910690c574 | 961 | } |
AnnaBridge | 145:64910690c574 | 962 | |
AnnaBridge | 145:64910690c574 | 963 | /** |
AnnaBridge | 145:64910690c574 | 964 | * @brief Get Peripheral size. |
AnnaBridge | 145:64910690c574 | 965 | * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize |
AnnaBridge | 145:64910690c574 | 966 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 967 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 968 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 969 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 970 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 971 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 972 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 973 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 974 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 975 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 976 | * @arg @ref LL_DMA_PDATAALIGN_BYTE |
AnnaBridge | 145:64910690c574 | 977 | * @arg @ref LL_DMA_PDATAALIGN_HALFWORD |
AnnaBridge | 145:64910690c574 | 978 | * @arg @ref LL_DMA_PDATAALIGN_WORD |
AnnaBridge | 145:64910690c574 | 979 | */ |
AnnaBridge | 145:64910690c574 | 980 | __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 981 | { |
AnnaBridge | 145:64910690c574 | 982 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 145:64910690c574 | 983 | DMA_CCR_PSIZE)); |
AnnaBridge | 145:64910690c574 | 984 | } |
AnnaBridge | 145:64910690c574 | 985 | |
AnnaBridge | 145:64910690c574 | 986 | /** |
AnnaBridge | 145:64910690c574 | 987 | * @brief Set Memory size. |
AnnaBridge | 145:64910690c574 | 988 | * @rmtoll CCR MSIZE LL_DMA_SetMemorySize |
AnnaBridge | 145:64910690c574 | 989 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 990 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 991 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 992 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 993 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 994 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 995 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 996 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 997 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 998 | * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 999 | * @arg @ref LL_DMA_MDATAALIGN_BYTE |
AnnaBridge | 145:64910690c574 | 1000 | * @arg @ref LL_DMA_MDATAALIGN_HALFWORD |
AnnaBridge | 145:64910690c574 | 1001 | * @arg @ref LL_DMA_MDATAALIGN_WORD |
AnnaBridge | 145:64910690c574 | 1002 | * @retval None |
AnnaBridge | 145:64910690c574 | 1003 | */ |
AnnaBridge | 145:64910690c574 | 1004 | __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) |
AnnaBridge | 145:64910690c574 | 1005 | { |
AnnaBridge | 145:64910690c574 | 1006 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, |
AnnaBridge | 145:64910690c574 | 1007 | MemoryOrM2MDstDataSize); |
AnnaBridge | 145:64910690c574 | 1008 | } |
AnnaBridge | 145:64910690c574 | 1009 | |
AnnaBridge | 145:64910690c574 | 1010 | /** |
AnnaBridge | 145:64910690c574 | 1011 | * @brief Get Memory size. |
AnnaBridge | 145:64910690c574 | 1012 | * @rmtoll CCR MSIZE LL_DMA_GetMemorySize |
AnnaBridge | 145:64910690c574 | 1013 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1014 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1015 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 1016 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 1017 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 1018 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 1019 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 1020 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 1021 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 1022 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1023 | * @arg @ref LL_DMA_MDATAALIGN_BYTE |
AnnaBridge | 145:64910690c574 | 1024 | * @arg @ref LL_DMA_MDATAALIGN_HALFWORD |
AnnaBridge | 145:64910690c574 | 1025 | * @arg @ref LL_DMA_MDATAALIGN_WORD |
AnnaBridge | 145:64910690c574 | 1026 | */ |
AnnaBridge | 145:64910690c574 | 1027 | __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 1028 | { |
AnnaBridge | 145:64910690c574 | 1029 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 145:64910690c574 | 1030 | DMA_CCR_MSIZE)); |
AnnaBridge | 145:64910690c574 | 1031 | } |
AnnaBridge | 145:64910690c574 | 1032 | |
AnnaBridge | 145:64910690c574 | 1033 | /** |
AnnaBridge | 145:64910690c574 | 1034 | * @brief Set Channel priority level. |
AnnaBridge | 145:64910690c574 | 1035 | * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel |
AnnaBridge | 145:64910690c574 | 1036 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1037 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1038 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 1039 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 1040 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 1041 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 1042 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 1043 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 1044 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 1045 | * @param Priority This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1046 | * @arg @ref LL_DMA_PRIORITY_LOW |
AnnaBridge | 145:64910690c574 | 1047 | * @arg @ref LL_DMA_PRIORITY_MEDIUM |
AnnaBridge | 145:64910690c574 | 1048 | * @arg @ref LL_DMA_PRIORITY_HIGH |
AnnaBridge | 145:64910690c574 | 1049 | * @arg @ref LL_DMA_PRIORITY_VERYHIGH |
AnnaBridge | 145:64910690c574 | 1050 | * @retval None |
AnnaBridge | 145:64910690c574 | 1051 | */ |
AnnaBridge | 145:64910690c574 | 1052 | __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) |
AnnaBridge | 145:64910690c574 | 1053 | { |
AnnaBridge | 145:64910690c574 | 1054 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, |
AnnaBridge | 145:64910690c574 | 1055 | Priority); |
AnnaBridge | 145:64910690c574 | 1056 | } |
AnnaBridge | 145:64910690c574 | 1057 | |
AnnaBridge | 145:64910690c574 | 1058 | /** |
AnnaBridge | 145:64910690c574 | 1059 | * @brief Get Channel priority level. |
AnnaBridge | 145:64910690c574 | 1060 | * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel |
AnnaBridge | 145:64910690c574 | 1061 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1062 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1063 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 1064 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 1065 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 1066 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 1067 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 1068 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 1069 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 1070 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1071 | * @arg @ref LL_DMA_PRIORITY_LOW |
AnnaBridge | 145:64910690c574 | 1072 | * @arg @ref LL_DMA_PRIORITY_MEDIUM |
AnnaBridge | 145:64910690c574 | 1073 | * @arg @ref LL_DMA_PRIORITY_HIGH |
AnnaBridge | 145:64910690c574 | 1074 | * @arg @ref LL_DMA_PRIORITY_VERYHIGH |
AnnaBridge | 145:64910690c574 | 1075 | */ |
AnnaBridge | 145:64910690c574 | 1076 | __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 1077 | { |
AnnaBridge | 145:64910690c574 | 1078 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 145:64910690c574 | 1079 | DMA_CCR_PL)); |
AnnaBridge | 145:64910690c574 | 1080 | } |
AnnaBridge | 145:64910690c574 | 1081 | |
AnnaBridge | 145:64910690c574 | 1082 | /** |
AnnaBridge | 145:64910690c574 | 1083 | * @brief Set Number of data to transfer. |
AnnaBridge | 145:64910690c574 | 1084 | * @note This action has no effect if |
AnnaBridge | 145:64910690c574 | 1085 | * channel is enabled. |
AnnaBridge | 145:64910690c574 | 1086 | * @rmtoll CNDTR NDT LL_DMA_SetDataLength |
AnnaBridge | 145:64910690c574 | 1087 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1088 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1089 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 1090 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 1091 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 1092 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 1093 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 1094 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 1095 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 1096 | * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF |
AnnaBridge | 145:64910690c574 | 1097 | * @retval None |
AnnaBridge | 145:64910690c574 | 1098 | */ |
AnnaBridge | 145:64910690c574 | 1099 | __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) |
AnnaBridge | 145:64910690c574 | 1100 | { |
AnnaBridge | 145:64910690c574 | 1101 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, |
AnnaBridge | 145:64910690c574 | 1102 | DMA_CNDTR_NDT, NbData); |
AnnaBridge | 145:64910690c574 | 1103 | } |
AnnaBridge | 145:64910690c574 | 1104 | |
AnnaBridge | 145:64910690c574 | 1105 | /** |
AnnaBridge | 145:64910690c574 | 1106 | * @brief Get Number of data to transfer. |
AnnaBridge | 145:64910690c574 | 1107 | * @note Once the channel is enabled, the return value indicate the |
AnnaBridge | 145:64910690c574 | 1108 | * remaining bytes to be transmitted. |
AnnaBridge | 145:64910690c574 | 1109 | * @rmtoll CNDTR NDT LL_DMA_GetDataLength |
AnnaBridge | 145:64910690c574 | 1110 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1111 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1112 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 1113 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 1114 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 1115 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 1116 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 1117 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 1118 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 1119 | * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1120 | */ |
AnnaBridge | 145:64910690c574 | 1121 | __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 1122 | { |
AnnaBridge | 145:64910690c574 | 1123 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, |
AnnaBridge | 145:64910690c574 | 1124 | DMA_CNDTR_NDT)); |
AnnaBridge | 145:64910690c574 | 1125 | } |
AnnaBridge | 145:64910690c574 | 1126 | |
AnnaBridge | 145:64910690c574 | 1127 | /** |
AnnaBridge | 145:64910690c574 | 1128 | * @brief Configure the Source and Destination addresses. |
AnnaBridge | 145:64910690c574 | 1129 | * @note This API must not be called when the DMA channel is enabled. |
AnnaBridge | 145:64910690c574 | 1130 | * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). |
AnnaBridge | 145:64910690c574 | 1131 | * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n |
AnnaBridge | 145:64910690c574 | 1132 | * CMAR MA LL_DMA_ConfigAddresses |
AnnaBridge | 145:64910690c574 | 1133 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1134 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1135 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 1136 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 1137 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 1138 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 1139 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 1140 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 1141 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 1142 | * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1143 | * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1144 | * @param Direction This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1145 | * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY |
AnnaBridge | 145:64910690c574 | 1146 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH |
AnnaBridge | 145:64910690c574 | 1147 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY |
AnnaBridge | 145:64910690c574 | 1148 | * @retval None |
AnnaBridge | 145:64910690c574 | 1149 | */ |
AnnaBridge | 145:64910690c574 | 1150 | __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, |
AnnaBridge | 145:64910690c574 | 1151 | uint32_t DstAddress, uint32_t Direction) |
AnnaBridge | 145:64910690c574 | 1152 | { |
AnnaBridge | 145:64910690c574 | 1153 | /* Direction Memory to Periph */ |
AnnaBridge | 145:64910690c574 | 1154 | if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) |
AnnaBridge | 145:64910690c574 | 1155 | { |
AnnaBridge | 145:64910690c574 | 1156 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); |
AnnaBridge | 145:64910690c574 | 1157 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); |
AnnaBridge | 145:64910690c574 | 1158 | } |
AnnaBridge | 145:64910690c574 | 1159 | /* Direction Periph to Memory and Memory to Memory */ |
AnnaBridge | 145:64910690c574 | 1160 | else |
AnnaBridge | 145:64910690c574 | 1161 | { |
AnnaBridge | 145:64910690c574 | 1162 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); |
AnnaBridge | 145:64910690c574 | 1163 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); |
AnnaBridge | 145:64910690c574 | 1164 | } |
AnnaBridge | 145:64910690c574 | 1165 | } |
AnnaBridge | 145:64910690c574 | 1166 | |
AnnaBridge | 145:64910690c574 | 1167 | /** |
AnnaBridge | 145:64910690c574 | 1168 | * @brief Set the Memory address. |
AnnaBridge | 145:64910690c574 | 1169 | * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. |
AnnaBridge | 145:64910690c574 | 1170 | * @note This API must not be called when the DMA channel is enabled. |
AnnaBridge | 145:64910690c574 | 1171 | * @rmtoll CMAR MA LL_DMA_SetMemoryAddress |
AnnaBridge | 145:64910690c574 | 1172 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1173 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1174 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 1175 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 1176 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 1177 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 1178 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 1179 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 1180 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 1181 | * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1182 | * @retval None |
AnnaBridge | 145:64910690c574 | 1183 | */ |
AnnaBridge | 145:64910690c574 | 1184 | __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) |
AnnaBridge | 145:64910690c574 | 1185 | { |
AnnaBridge | 145:64910690c574 | 1186 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); |
AnnaBridge | 145:64910690c574 | 1187 | } |
AnnaBridge | 145:64910690c574 | 1188 | |
AnnaBridge | 145:64910690c574 | 1189 | /** |
AnnaBridge | 145:64910690c574 | 1190 | * @brief Set the Peripheral address. |
AnnaBridge | 145:64910690c574 | 1191 | * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. |
AnnaBridge | 145:64910690c574 | 1192 | * @note This API must not be called when the DMA channel is enabled. |
AnnaBridge | 145:64910690c574 | 1193 | * @rmtoll CPAR PA LL_DMA_SetPeriphAddress |
AnnaBridge | 145:64910690c574 | 1194 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1195 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1196 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 1197 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 1198 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 1199 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 1200 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 1201 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 1202 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 1203 | * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1204 | * @retval None |
AnnaBridge | 145:64910690c574 | 1205 | */ |
AnnaBridge | 145:64910690c574 | 1206 | __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) |
AnnaBridge | 145:64910690c574 | 1207 | { |
AnnaBridge | 145:64910690c574 | 1208 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); |
AnnaBridge | 145:64910690c574 | 1209 | } |
AnnaBridge | 145:64910690c574 | 1210 | |
AnnaBridge | 145:64910690c574 | 1211 | /** |
AnnaBridge | 145:64910690c574 | 1212 | * @brief Get Memory address. |
AnnaBridge | 145:64910690c574 | 1213 | * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. |
AnnaBridge | 145:64910690c574 | 1214 | * @rmtoll CMAR MA LL_DMA_GetMemoryAddress |
AnnaBridge | 145:64910690c574 | 1215 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1216 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1217 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 1218 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 1219 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 1220 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 1221 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 1222 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 1223 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 1224 | * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1225 | */ |
AnnaBridge | 145:64910690c574 | 1226 | __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 1227 | { |
AnnaBridge | 145:64910690c574 | 1228 | return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); |
AnnaBridge | 145:64910690c574 | 1229 | } |
AnnaBridge | 145:64910690c574 | 1230 | |
AnnaBridge | 145:64910690c574 | 1231 | /** |
AnnaBridge | 145:64910690c574 | 1232 | * @brief Get Peripheral address. |
AnnaBridge | 145:64910690c574 | 1233 | * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. |
AnnaBridge | 145:64910690c574 | 1234 | * @rmtoll CPAR PA LL_DMA_GetPeriphAddress |
AnnaBridge | 145:64910690c574 | 1235 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1236 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1237 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 1238 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 1239 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 1240 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 1241 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 1242 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 1243 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 1244 | * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1245 | */ |
AnnaBridge | 145:64910690c574 | 1246 | __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 1247 | { |
AnnaBridge | 145:64910690c574 | 1248 | return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); |
AnnaBridge | 145:64910690c574 | 1249 | } |
AnnaBridge | 145:64910690c574 | 1250 | |
AnnaBridge | 145:64910690c574 | 1251 | /** |
AnnaBridge | 145:64910690c574 | 1252 | * @brief Set the Memory to Memory Source address. |
AnnaBridge | 145:64910690c574 | 1253 | * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. |
AnnaBridge | 145:64910690c574 | 1254 | * @note This API must not be called when the DMA channel is enabled. |
AnnaBridge | 145:64910690c574 | 1255 | * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress |
AnnaBridge | 145:64910690c574 | 1256 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1257 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1258 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 1259 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 1260 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 1261 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 1262 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 1263 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 1264 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 1265 | * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1266 | * @retval None |
AnnaBridge | 145:64910690c574 | 1267 | */ |
AnnaBridge | 145:64910690c574 | 1268 | __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) |
AnnaBridge | 145:64910690c574 | 1269 | { |
AnnaBridge | 145:64910690c574 | 1270 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); |
AnnaBridge | 145:64910690c574 | 1271 | } |
AnnaBridge | 145:64910690c574 | 1272 | |
AnnaBridge | 145:64910690c574 | 1273 | /** |
AnnaBridge | 145:64910690c574 | 1274 | * @brief Set the Memory to Memory Destination address. |
AnnaBridge | 145:64910690c574 | 1275 | * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. |
AnnaBridge | 145:64910690c574 | 1276 | * @note This API must not be called when the DMA channel is enabled. |
AnnaBridge | 145:64910690c574 | 1277 | * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress |
AnnaBridge | 145:64910690c574 | 1278 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1279 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1280 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 1281 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 1282 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 1283 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 1284 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 1285 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 1286 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 1287 | * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1288 | * @retval None |
AnnaBridge | 145:64910690c574 | 1289 | */ |
AnnaBridge | 145:64910690c574 | 1290 | __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) |
AnnaBridge | 145:64910690c574 | 1291 | { |
AnnaBridge | 145:64910690c574 | 1292 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); |
AnnaBridge | 145:64910690c574 | 1293 | } |
AnnaBridge | 145:64910690c574 | 1294 | |
AnnaBridge | 145:64910690c574 | 1295 | /** |
AnnaBridge | 145:64910690c574 | 1296 | * @brief Get the Memory to Memory Source address. |
AnnaBridge | 145:64910690c574 | 1297 | * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. |
AnnaBridge | 145:64910690c574 | 1298 | * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress |
AnnaBridge | 145:64910690c574 | 1299 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1300 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1301 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 1302 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 1303 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 1304 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 1305 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 1306 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 1307 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 1308 | * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1309 | */ |
AnnaBridge | 145:64910690c574 | 1310 | __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 1311 | { |
AnnaBridge | 145:64910690c574 | 1312 | return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); |
AnnaBridge | 145:64910690c574 | 1313 | } |
AnnaBridge | 145:64910690c574 | 1314 | |
AnnaBridge | 145:64910690c574 | 1315 | /** |
AnnaBridge | 145:64910690c574 | 1316 | * @brief Get the Memory to Memory Destination address. |
AnnaBridge | 145:64910690c574 | 1317 | * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. |
AnnaBridge | 145:64910690c574 | 1318 | * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress |
AnnaBridge | 145:64910690c574 | 1319 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1320 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1321 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 1322 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 1323 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 1324 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 1325 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 1326 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 1327 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 1328 | * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
AnnaBridge | 145:64910690c574 | 1329 | */ |
AnnaBridge | 145:64910690c574 | 1330 | __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 1331 | { |
AnnaBridge | 145:64910690c574 | 1332 | return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); |
AnnaBridge | 145:64910690c574 | 1333 | } |
AnnaBridge | 145:64910690c574 | 1334 | |
AnnaBridge | 161:aa5281ff4a02 | 1335 | #if defined(DMAMUX1) |
AnnaBridge | 161:aa5281ff4a02 | 1336 | /** |
AnnaBridge | 161:aa5281ff4a02 | 1337 | * @brief Set DMA request for DMA Channels on DMAMUX Channel x. |
AnnaBridge | 161:aa5281ff4a02 | 1338 | * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. |
AnnaBridge | 161:aa5281ff4a02 | 1339 | * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. |
AnnaBridge | 161:aa5281ff4a02 | 1340 | * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest |
AnnaBridge | 161:aa5281ff4a02 | 1341 | * @param DMAx DMAx Instance |
AnnaBridge | 161:aa5281ff4a02 | 1342 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 161:aa5281ff4a02 | 1343 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 161:aa5281ff4a02 | 1344 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 161:aa5281ff4a02 | 1345 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 161:aa5281ff4a02 | 1346 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 161:aa5281ff4a02 | 1347 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 161:aa5281ff4a02 | 1348 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 161:aa5281ff4a02 | 1349 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 161:aa5281ff4a02 | 1350 | * @param Request This parameter can be one of the following values: |
AnnaBridge | 161:aa5281ff4a02 | 1351 | * @arg @ref LL_DMAMUX_REQUEST_MEM2MEM |
AnnaBridge | 161:aa5281ff4a02 | 1352 | * @arg @ref LL_DMAMUX_REQUEST_GENERATOR0 |
AnnaBridge | 161:aa5281ff4a02 | 1353 | * @arg @ref LL_DMAMUX_REQUEST_GENERATOR1 |
AnnaBridge | 161:aa5281ff4a02 | 1354 | * @arg @ref LL_DMAMUX_REQUEST_GENERATOR2 |
AnnaBridge | 161:aa5281ff4a02 | 1355 | * @arg @ref LL_DMAMUX_REQUEST_GENERATOR3 |
AnnaBridge | 161:aa5281ff4a02 | 1356 | * @arg @ref LL_DMAMUX_REQUEST_ADC1 |
AnnaBridge | 161:aa5281ff4a02 | 1357 | * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH1 |
AnnaBridge | 161:aa5281ff4a02 | 1358 | * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH2 |
AnnaBridge | 161:aa5281ff4a02 | 1359 | * @arg @ref LL_DMAMUX_REQUEST_TIM6_UP |
AnnaBridge | 161:aa5281ff4a02 | 1360 | * @arg @ref LL_DMAMUX_REQUEST_TIM7_UP |
AnnaBridge | 161:aa5281ff4a02 | 1361 | * @arg @ref LL_DMAMUX_REQUEST_SPI1_RX |
AnnaBridge | 161:aa5281ff4a02 | 1362 | * @arg @ref LL_DMAMUX_REQUEST_SPI1_TX |
AnnaBridge | 161:aa5281ff4a02 | 1363 | * @arg @ref LL_DMAMUX_REQUEST_SPI2_RX |
AnnaBridge | 161:aa5281ff4a02 | 1364 | * @arg @ref LL_DMAMUX_REQUEST_SPI2_TX |
AnnaBridge | 161:aa5281ff4a02 | 1365 | * @arg @ref LL_DMAMUX_REQUEST_SPI3_RX |
AnnaBridge | 161:aa5281ff4a02 | 1366 | * @arg @ref LL_DMAMUX_REQUEST_SPI3_TX |
AnnaBridge | 161:aa5281ff4a02 | 1367 | * @arg @ref LL_DMAMUX_REQUEST_I2C1_RX |
AnnaBridge | 161:aa5281ff4a02 | 1368 | * @arg @ref LL_DMAMUX_REQUEST_I2C1_TX |
AnnaBridge | 161:aa5281ff4a02 | 1369 | * @arg @ref LL_DMAMUX_REQUEST_I2C2_RX |
AnnaBridge | 161:aa5281ff4a02 | 1370 | * @arg @ref LL_DMAMUX_REQUEST_I2C2_TX |
AnnaBridge | 161:aa5281ff4a02 | 1371 | * @arg @ref LL_DMAMUX_REQUEST_I2C3_RX |
AnnaBridge | 161:aa5281ff4a02 | 1372 | * @arg @ref LL_DMAMUX_REQUEST_I2C3_TX |
AnnaBridge | 161:aa5281ff4a02 | 1373 | * @arg @ref LL_DMAMUX_REQUEST_I2C4_RX |
AnnaBridge | 161:aa5281ff4a02 | 1374 | * @arg @ref LL_DMAMUX_REQUEST_I2C4_TX |
AnnaBridge | 161:aa5281ff4a02 | 1375 | * @arg @ref LL_DMAMUX_REQUEST_USART1_RX |
AnnaBridge | 161:aa5281ff4a02 | 1376 | * @arg @ref LL_DMAMUX_REQUEST_USART1_TX |
AnnaBridge | 161:aa5281ff4a02 | 1377 | * @arg @ref LL_DMAMUX_REQUEST_USART2_RX |
AnnaBridge | 161:aa5281ff4a02 | 1378 | * @arg @ref LL_DMAMUX_REQUEST_USART2_TX |
AnnaBridge | 161:aa5281ff4a02 | 1379 | * @arg @ref LL_DMAMUX_REQUEST_USART3_RX |
AnnaBridge | 161:aa5281ff4a02 | 1380 | * @arg @ref LL_DMAMUX_REQUEST_USART3_TX |
AnnaBridge | 161:aa5281ff4a02 | 1381 | * @arg @ref LL_DMAMUX_REQUEST_UART4_RX |
AnnaBridge | 161:aa5281ff4a02 | 1382 | * @arg @ref LL_DMAMUX_REQUEST_UART4_TX |
AnnaBridge | 161:aa5281ff4a02 | 1383 | * @arg @ref LL_DMAMUX_REQUEST_UART5_RX |
AnnaBridge | 161:aa5281ff4a02 | 1384 | * @arg @ref LL_DMAMUX_REQUEST_UART5_TX |
AnnaBridge | 161:aa5281ff4a02 | 1385 | * @arg @ref LL_DMAMUX_REQUEST_LPUART1_RX |
AnnaBridge | 161:aa5281ff4a02 | 1386 | * @arg @ref LL_DMAMUX_REQUEST_LPUART1_TX |
AnnaBridge | 161:aa5281ff4a02 | 1387 | * @arg @ref LL_DMAMUX_REQUEST_SAI1_A |
AnnaBridge | 161:aa5281ff4a02 | 1388 | * @arg @ref LL_DMAMUX_REQUEST_SAI1_B |
AnnaBridge | 161:aa5281ff4a02 | 1389 | * @arg @ref LL_DMAMUX_REQUEST_SAI2_A |
AnnaBridge | 161:aa5281ff4a02 | 1390 | * @arg @ref LL_DMAMUX_REQUEST_SAI2_B |
AnnaBridge | 161:aa5281ff4a02 | 1391 | * @arg @ref LL_DMAMUX_REQUEST_OSPI1 |
AnnaBridge | 161:aa5281ff4a02 | 1392 | * @arg @ref LL_DMAMUX_REQUEST_OSPI2 |
AnnaBridge | 161:aa5281ff4a02 | 1393 | * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH1 |
AnnaBridge | 161:aa5281ff4a02 | 1394 | * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH2 |
AnnaBridge | 161:aa5281ff4a02 | 1395 | * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH3 |
AnnaBridge | 161:aa5281ff4a02 | 1396 | * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH4 |
AnnaBridge | 161:aa5281ff4a02 | 1397 | * @arg @ref LL_DMAMUX_REQUEST_TIM1_UP |
AnnaBridge | 161:aa5281ff4a02 | 1398 | * @arg @ref LL_DMAMUX_REQUEST_TIM1_TRIG |
AnnaBridge | 161:aa5281ff4a02 | 1399 | * @arg @ref LL_DMAMUX_REQUEST_TIM1_COM |
AnnaBridge | 161:aa5281ff4a02 | 1400 | * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH1 |
AnnaBridge | 161:aa5281ff4a02 | 1401 | * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH2 |
AnnaBridge | 161:aa5281ff4a02 | 1402 | * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH3 |
AnnaBridge | 161:aa5281ff4a02 | 1403 | * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH4 |
AnnaBridge | 161:aa5281ff4a02 | 1404 | * @arg @ref LL_DMAMUX_REQUEST_TIM8_UP |
AnnaBridge | 161:aa5281ff4a02 | 1405 | * @arg @ref LL_DMAMUX_REQUEST_TIM8_TRIG |
AnnaBridge | 161:aa5281ff4a02 | 1406 | * @arg @ref LL_DMAMUX_REQUEST_TIM8_COM |
AnnaBridge | 161:aa5281ff4a02 | 1407 | * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH1 |
AnnaBridge | 161:aa5281ff4a02 | 1408 | * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH2 |
AnnaBridge | 161:aa5281ff4a02 | 1409 | * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH3 |
AnnaBridge | 161:aa5281ff4a02 | 1410 | * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH4 |
AnnaBridge | 161:aa5281ff4a02 | 1411 | * @arg @ref LL_DMAMUX_REQUEST_TIM2_UP |
AnnaBridge | 161:aa5281ff4a02 | 1412 | * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH1 |
AnnaBridge | 161:aa5281ff4a02 | 1413 | * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH2 |
AnnaBridge | 161:aa5281ff4a02 | 1414 | * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH3 |
AnnaBridge | 161:aa5281ff4a02 | 1415 | * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH4 |
AnnaBridge | 161:aa5281ff4a02 | 1416 | * @arg @ref LL_DMAMUX_REQUEST_TIM3_UP |
AnnaBridge | 161:aa5281ff4a02 | 1417 | * @arg @ref LL_DMAMUX_REQUEST_TIM3_TRIG |
AnnaBridge | 161:aa5281ff4a02 | 1418 | * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH1 |
AnnaBridge | 161:aa5281ff4a02 | 1419 | * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH2 |
AnnaBridge | 161:aa5281ff4a02 | 1420 | * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH3 |
AnnaBridge | 161:aa5281ff4a02 | 1421 | * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH4 |
AnnaBridge | 161:aa5281ff4a02 | 1422 | * @arg @ref LL_DMAMUX_REQUEST_TIM4_UP |
AnnaBridge | 161:aa5281ff4a02 | 1423 | * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH1 |
AnnaBridge | 161:aa5281ff4a02 | 1424 | * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH2 |
AnnaBridge | 161:aa5281ff4a02 | 1425 | * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH3 |
AnnaBridge | 161:aa5281ff4a02 | 1426 | * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH4 |
AnnaBridge | 161:aa5281ff4a02 | 1427 | * @arg @ref LL_DMAMUX_REQUEST_TIM5_UP |
AnnaBridge | 161:aa5281ff4a02 | 1428 | * @arg @ref LL_DMAMUX_REQUEST_TIM5_TRIG |
AnnaBridge | 161:aa5281ff4a02 | 1429 | * @arg @ref LL_DMAMUX_REQUEST_TIM15_CH1 |
AnnaBridge | 161:aa5281ff4a02 | 1430 | * @arg @ref LL_DMAMUX_REQUEST_TIM15_UP |
AnnaBridge | 161:aa5281ff4a02 | 1431 | * @arg @ref LL_DMAMUX_REQUEST_TIM15_TRIG |
AnnaBridge | 161:aa5281ff4a02 | 1432 | * @arg @ref LL_DMAMUX_REQUEST_TIM15_COM |
AnnaBridge | 161:aa5281ff4a02 | 1433 | * @arg @ref LL_DMAMUX_REQUEST_TIM16_CH1 |
AnnaBridge | 161:aa5281ff4a02 | 1434 | * @arg @ref LL_DMAMUX_REQUEST_TIM16_UP |
AnnaBridge | 161:aa5281ff4a02 | 1435 | * @arg @ref LL_DMAMUX_REQUEST_TIM17_CH1 |
AnnaBridge | 161:aa5281ff4a02 | 1436 | * @arg @ref LL_DMAMUX_REQUEST_TIM17_UP |
AnnaBridge | 161:aa5281ff4a02 | 1437 | * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT0 |
AnnaBridge | 161:aa5281ff4a02 | 1438 | * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT1 |
AnnaBridge | 161:aa5281ff4a02 | 1439 | * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT2 |
AnnaBridge | 161:aa5281ff4a02 | 1440 | * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT3 |
AnnaBridge | 161:aa5281ff4a02 | 1441 | * @arg @ref LL_DMAMUX_REQUEST_DCMI |
AnnaBridge | 161:aa5281ff4a02 | 1442 | * @arg @ref LL_DMAMUX_REQUEST_AES_IN |
AnnaBridge | 161:aa5281ff4a02 | 1443 | * @arg @ref LL_DMAMUX_REQUEST_AES_OUT |
AnnaBridge | 161:aa5281ff4a02 | 1444 | * @arg @ref LL_DMAMUX_REQUEST_HASH_IN |
AnnaBridge | 161:aa5281ff4a02 | 1445 | * @retval None |
AnnaBridge | 161:aa5281ff4a02 | 1446 | */ |
AnnaBridge | 161:aa5281ff4a02 | 1447 | __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) |
AnnaBridge | 161:aa5281ff4a02 | 1448 | { |
AnnaBridge | 161:aa5281ff4a02 | 1449 | MODIFY_REG(((DMAMUX_Channel_TypeDef*)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE*(Channel-1U)) + (uint32_t)(DMAMUX_CCR_SIZE*__LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); |
AnnaBridge | 161:aa5281ff4a02 | 1450 | } |
AnnaBridge | 161:aa5281ff4a02 | 1451 | |
AnnaBridge | 161:aa5281ff4a02 | 1452 | /** |
AnnaBridge | 161:aa5281ff4a02 | 1453 | * @brief Get DMA request for DMA Channels on DMAMUX Channel x. |
AnnaBridge | 161:aa5281ff4a02 | 1454 | * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. |
AnnaBridge | 161:aa5281ff4a02 | 1455 | * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. |
AnnaBridge | 161:aa5281ff4a02 | 1456 | * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest |
AnnaBridge | 161:aa5281ff4a02 | 1457 | * @param DMAx DMAx Instance |
AnnaBridge | 161:aa5281ff4a02 | 1458 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 161:aa5281ff4a02 | 1459 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 161:aa5281ff4a02 | 1460 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 161:aa5281ff4a02 | 1461 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 161:aa5281ff4a02 | 1462 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 161:aa5281ff4a02 | 1463 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 161:aa5281ff4a02 | 1464 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 161:aa5281ff4a02 | 1465 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 161:aa5281ff4a02 | 1466 | * @retval Returned value can be one of the following values: |
AnnaBridge | 161:aa5281ff4a02 | 1467 | * @arg @ref LL_DMAMUX_REQUEST_MEM2MEM |
AnnaBridge | 161:aa5281ff4a02 | 1468 | * @arg @ref LL_DMAMUX_REQUEST_GENERATOR0 |
AnnaBridge | 161:aa5281ff4a02 | 1469 | * @arg @ref LL_DMAMUX_REQUEST_GENERATOR1 |
AnnaBridge | 161:aa5281ff4a02 | 1470 | * @arg @ref LL_DMAMUX_REQUEST_GENERATOR2 |
AnnaBridge | 161:aa5281ff4a02 | 1471 | * @arg @ref LL_DMAMUX_REQUEST_GENERATOR3 |
AnnaBridge | 161:aa5281ff4a02 | 1472 | * @arg @ref LL_DMAMUX_REQUEST_ADC1 |
AnnaBridge | 161:aa5281ff4a02 | 1473 | * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH1 |
AnnaBridge | 161:aa5281ff4a02 | 1474 | * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH2 |
AnnaBridge | 161:aa5281ff4a02 | 1475 | * @arg @ref LL_DMAMUX_REQUEST_TIM6_UP |
AnnaBridge | 161:aa5281ff4a02 | 1476 | * @arg @ref LL_DMAMUX_REQUEST_TIM7_UP |
AnnaBridge | 161:aa5281ff4a02 | 1477 | * @arg @ref LL_DMAMUX_REQUEST_SPI1_RX |
AnnaBridge | 161:aa5281ff4a02 | 1478 | * @arg @ref LL_DMAMUX_REQUEST_SPI1_TX |
AnnaBridge | 161:aa5281ff4a02 | 1479 | * @arg @ref LL_DMAMUX_REQUEST_SPI2_RX |
AnnaBridge | 161:aa5281ff4a02 | 1480 | * @arg @ref LL_DMAMUX_REQUEST_SPI2_TX |
AnnaBridge | 161:aa5281ff4a02 | 1481 | * @arg @ref LL_DMAMUX_REQUEST_SPI3_RX |
AnnaBridge | 161:aa5281ff4a02 | 1482 | * @arg @ref LL_DMAMUX_REQUEST_SPI3_TX |
AnnaBridge | 161:aa5281ff4a02 | 1483 | * @arg @ref LL_DMAMUX_REQUEST_I2C1_RX |
AnnaBridge | 161:aa5281ff4a02 | 1484 | * @arg @ref LL_DMAMUX_REQUEST_I2C1_TX |
AnnaBridge | 161:aa5281ff4a02 | 1485 | * @arg @ref LL_DMAMUX_REQUEST_I2C2_RX |
AnnaBridge | 161:aa5281ff4a02 | 1486 | * @arg @ref LL_DMAMUX_REQUEST_I2C2_TX |
AnnaBridge | 161:aa5281ff4a02 | 1487 | * @arg @ref LL_DMAMUX_REQUEST_I2C3_RX |
AnnaBridge | 161:aa5281ff4a02 | 1488 | * @arg @ref LL_DMAMUX_REQUEST_I2C3_TX |
AnnaBridge | 161:aa5281ff4a02 | 1489 | * @arg @ref LL_DMAMUX_REQUEST_I2C4_RX |
AnnaBridge | 161:aa5281ff4a02 | 1490 | * @arg @ref LL_DMAMUX_REQUEST_I2C4_TX |
AnnaBridge | 161:aa5281ff4a02 | 1491 | * @arg @ref LL_DMAMUX_REQUEST_USART1_RX |
AnnaBridge | 161:aa5281ff4a02 | 1492 | * @arg @ref LL_DMAMUX_REQUEST_USART1_TX |
AnnaBridge | 161:aa5281ff4a02 | 1493 | * @arg @ref LL_DMAMUX_REQUEST_USART2_RX |
AnnaBridge | 161:aa5281ff4a02 | 1494 | * @arg @ref LL_DMAMUX_REQUEST_USART2_TX |
AnnaBridge | 161:aa5281ff4a02 | 1495 | * @arg @ref LL_DMAMUX_REQUEST_USART3_RX |
AnnaBridge | 161:aa5281ff4a02 | 1496 | * @arg @ref LL_DMAMUX_REQUEST_USART3_TX |
AnnaBridge | 161:aa5281ff4a02 | 1497 | * @arg @ref LL_DMAMUX_REQUEST_UART4_RX |
AnnaBridge | 161:aa5281ff4a02 | 1498 | * @arg @ref LL_DMAMUX_REQUEST_UART4_TX |
AnnaBridge | 161:aa5281ff4a02 | 1499 | * @arg @ref LL_DMAMUX_REQUEST_UART5_RX |
AnnaBridge | 161:aa5281ff4a02 | 1500 | * @arg @ref LL_DMAMUX_REQUEST_UART5_TX |
AnnaBridge | 161:aa5281ff4a02 | 1501 | * @arg @ref LL_DMAMUX_REQUEST_LPUART1_RX |
AnnaBridge | 161:aa5281ff4a02 | 1502 | * @arg @ref LL_DMAMUX_REQUEST_LPUART1_TX |
AnnaBridge | 161:aa5281ff4a02 | 1503 | * @arg @ref LL_DMAMUX_REQUEST_SAI1_A |
AnnaBridge | 161:aa5281ff4a02 | 1504 | * @arg @ref LL_DMAMUX_REQUEST_SAI1_B |
AnnaBridge | 161:aa5281ff4a02 | 1505 | * @arg @ref LL_DMAMUX_REQUEST_SAI2_A |
AnnaBridge | 161:aa5281ff4a02 | 1506 | * @arg @ref LL_DMAMUX_REQUEST_SAI2_B |
AnnaBridge | 161:aa5281ff4a02 | 1507 | * @arg @ref LL_DMAMUX_REQUEST_OSPI1 |
AnnaBridge | 161:aa5281ff4a02 | 1508 | * @arg @ref LL_DMAMUX_REQUEST_OSPI2 |
AnnaBridge | 161:aa5281ff4a02 | 1509 | * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH1 |
AnnaBridge | 161:aa5281ff4a02 | 1510 | * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH2 |
AnnaBridge | 161:aa5281ff4a02 | 1511 | * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH3 |
AnnaBridge | 161:aa5281ff4a02 | 1512 | * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH4 |
AnnaBridge | 161:aa5281ff4a02 | 1513 | * @arg @ref LL_DMAMUX_REQUEST_TIM1_UP |
AnnaBridge | 161:aa5281ff4a02 | 1514 | * @arg @ref LL_DMAMUX_REQUEST_TIM1_TRIG |
AnnaBridge | 161:aa5281ff4a02 | 1515 | * @arg @ref LL_DMAMUX_REQUEST_TIM1_COM |
AnnaBridge | 161:aa5281ff4a02 | 1516 | * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH1 |
AnnaBridge | 161:aa5281ff4a02 | 1517 | * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH2 |
AnnaBridge | 161:aa5281ff4a02 | 1518 | * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH3 |
AnnaBridge | 161:aa5281ff4a02 | 1519 | * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH4 |
AnnaBridge | 161:aa5281ff4a02 | 1520 | * @arg @ref LL_DMAMUX_REQUEST_TIM8_UP |
AnnaBridge | 161:aa5281ff4a02 | 1521 | * @arg @ref LL_DMAMUX_REQUEST_TIM8_TRIG |
AnnaBridge | 161:aa5281ff4a02 | 1522 | * @arg @ref LL_DMAMUX_REQUEST_TIM8_COM |
AnnaBridge | 161:aa5281ff4a02 | 1523 | * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH1 |
AnnaBridge | 161:aa5281ff4a02 | 1524 | * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH2 |
AnnaBridge | 161:aa5281ff4a02 | 1525 | * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH3 |
AnnaBridge | 161:aa5281ff4a02 | 1526 | * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH4 |
AnnaBridge | 161:aa5281ff4a02 | 1527 | * @arg @ref LL_DMAMUX_REQUEST_TIM2_UP |
AnnaBridge | 161:aa5281ff4a02 | 1528 | * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH1 |
AnnaBridge | 161:aa5281ff4a02 | 1529 | * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH2 |
AnnaBridge | 161:aa5281ff4a02 | 1530 | * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH3 |
AnnaBridge | 161:aa5281ff4a02 | 1531 | * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH4 |
AnnaBridge | 161:aa5281ff4a02 | 1532 | * @arg @ref LL_DMAMUX_REQUEST_TIM3_UP |
AnnaBridge | 161:aa5281ff4a02 | 1533 | * @arg @ref LL_DMAMUX_REQUEST_TIM3_TRIG |
AnnaBridge | 161:aa5281ff4a02 | 1534 | * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH1 |
AnnaBridge | 161:aa5281ff4a02 | 1535 | * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH2 |
AnnaBridge | 161:aa5281ff4a02 | 1536 | * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH3 |
AnnaBridge | 161:aa5281ff4a02 | 1537 | * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH4 |
AnnaBridge | 161:aa5281ff4a02 | 1538 | * @arg @ref LL_DMAMUX_REQUEST_TIM4_UP |
AnnaBridge | 161:aa5281ff4a02 | 1539 | * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH1 |
AnnaBridge | 161:aa5281ff4a02 | 1540 | * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH2 |
AnnaBridge | 161:aa5281ff4a02 | 1541 | * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH3 |
AnnaBridge | 161:aa5281ff4a02 | 1542 | * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH4 |
AnnaBridge | 161:aa5281ff4a02 | 1543 | * @arg @ref LL_DMAMUX_REQUEST_TIM5_UP |
AnnaBridge | 161:aa5281ff4a02 | 1544 | * @arg @ref LL_DMAMUX_REQUEST_TIM5_TRIG |
AnnaBridge | 161:aa5281ff4a02 | 1545 | * @arg @ref LL_DMAMUX_REQUEST_TIM15_CH1 |
AnnaBridge | 161:aa5281ff4a02 | 1546 | * @arg @ref LL_DMAMUX_REQUEST_TIM15_UP |
AnnaBridge | 161:aa5281ff4a02 | 1547 | * @arg @ref LL_DMAMUX_REQUEST_TIM15_TRIG |
AnnaBridge | 161:aa5281ff4a02 | 1548 | * @arg @ref LL_DMAMUX_REQUEST_TIM15_COM |
AnnaBridge | 161:aa5281ff4a02 | 1549 | * @arg @ref LL_DMAMUX_REQUEST_TIM16_CH1 |
AnnaBridge | 161:aa5281ff4a02 | 1550 | * @arg @ref LL_DMAMUX_REQUEST_TIM16_UP |
AnnaBridge | 161:aa5281ff4a02 | 1551 | * @arg @ref LL_DMAMUX_REQUEST_TIM17_CH1 |
AnnaBridge | 161:aa5281ff4a02 | 1552 | * @arg @ref LL_DMAMUX_REQUEST_TIM17_UP |
AnnaBridge | 161:aa5281ff4a02 | 1553 | * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT0 |
AnnaBridge | 161:aa5281ff4a02 | 1554 | * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT1 |
AnnaBridge | 161:aa5281ff4a02 | 1555 | * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT2 |
AnnaBridge | 161:aa5281ff4a02 | 1556 | * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT3 |
AnnaBridge | 161:aa5281ff4a02 | 1557 | * @arg @ref LL_DMAMUX_REQUEST_DCMI |
AnnaBridge | 161:aa5281ff4a02 | 1558 | * @arg @ref LL_DMAMUX_REQUEST_AES_IN |
AnnaBridge | 161:aa5281ff4a02 | 1559 | * @arg @ref LL_DMAMUX_REQUEST_AES_OUT |
AnnaBridge | 161:aa5281ff4a02 | 1560 | * @arg @ref LL_DMAMUX_REQUEST_HASH_IN |
AnnaBridge | 161:aa5281ff4a02 | 1561 | */ |
AnnaBridge | 161:aa5281ff4a02 | 1562 | __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 161:aa5281ff4a02 | 1563 | { |
AnnaBridge | 161:aa5281ff4a02 | 1564 | return (READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE*(Channel-1U)) + (uint32_t)(DMAMUX_CCR_SIZE*__LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); |
AnnaBridge | 161:aa5281ff4a02 | 1565 | } |
AnnaBridge | 161:aa5281ff4a02 | 1566 | #else |
AnnaBridge | 145:64910690c574 | 1567 | /** |
AnnaBridge | 145:64910690c574 | 1568 | * @brief Set DMA request for DMA instance on Channel x. |
AnnaBridge | 145:64910690c574 | 1569 | * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection. |
AnnaBridge | 145:64910690c574 | 1570 | * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n |
AnnaBridge | 145:64910690c574 | 1571 | * CSELR C2S LL_DMA_SetPeriphRequest\n |
AnnaBridge | 145:64910690c574 | 1572 | * CSELR C3S LL_DMA_SetPeriphRequest\n |
AnnaBridge | 145:64910690c574 | 1573 | * CSELR C4S LL_DMA_SetPeriphRequest\n |
AnnaBridge | 145:64910690c574 | 1574 | * CSELR C5S LL_DMA_SetPeriphRequest\n |
AnnaBridge | 145:64910690c574 | 1575 | * CSELR C6S LL_DMA_SetPeriphRequest\n |
AnnaBridge | 145:64910690c574 | 1576 | * CSELR C7S LL_DMA_SetPeriphRequest |
AnnaBridge | 145:64910690c574 | 1577 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1578 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1579 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 1580 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 1581 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 1582 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 1583 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 1584 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 1585 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 1586 | * @param PeriphRequest This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1587 | * @arg @ref LL_DMA_REQUEST_0 |
AnnaBridge | 145:64910690c574 | 1588 | * @arg @ref LL_DMA_REQUEST_1 |
AnnaBridge | 145:64910690c574 | 1589 | * @arg @ref LL_DMA_REQUEST_2 |
AnnaBridge | 145:64910690c574 | 1590 | * @arg @ref LL_DMA_REQUEST_3 |
AnnaBridge | 145:64910690c574 | 1591 | * @arg @ref LL_DMA_REQUEST_4 |
AnnaBridge | 145:64910690c574 | 1592 | * @arg @ref LL_DMA_REQUEST_5 |
AnnaBridge | 145:64910690c574 | 1593 | * @arg @ref LL_DMA_REQUEST_6 |
AnnaBridge | 145:64910690c574 | 1594 | * @arg @ref LL_DMA_REQUEST_7 |
AnnaBridge | 145:64910690c574 | 1595 | * @retval None |
AnnaBridge | 145:64910690c574 | 1596 | */ |
AnnaBridge | 145:64910690c574 | 1597 | __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest) |
AnnaBridge | 145:64910690c574 | 1598 | { |
AnnaBridge | 145:64910690c574 | 1599 | MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, |
AnnaBridge | 145:64910690c574 | 1600 | DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS); |
AnnaBridge | 145:64910690c574 | 1601 | } |
AnnaBridge | 145:64910690c574 | 1602 | |
AnnaBridge | 145:64910690c574 | 1603 | /** |
AnnaBridge | 145:64910690c574 | 1604 | * @brief Get DMA request for DMA instance on Channel x. |
AnnaBridge | 145:64910690c574 | 1605 | * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n |
AnnaBridge | 145:64910690c574 | 1606 | * CSELR C2S LL_DMA_GetPeriphRequest\n |
AnnaBridge | 145:64910690c574 | 1607 | * CSELR C3S LL_DMA_GetPeriphRequest\n |
AnnaBridge | 145:64910690c574 | 1608 | * CSELR C4S LL_DMA_GetPeriphRequest\n |
AnnaBridge | 145:64910690c574 | 1609 | * CSELR C5S LL_DMA_GetPeriphRequest\n |
AnnaBridge | 145:64910690c574 | 1610 | * CSELR C6S LL_DMA_GetPeriphRequest\n |
AnnaBridge | 145:64910690c574 | 1611 | * CSELR C7S LL_DMA_GetPeriphRequest |
AnnaBridge | 145:64910690c574 | 1612 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1613 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1614 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 1615 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 1616 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 1617 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 1618 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 1619 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 1620 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 1621 | * @retval Returned value can be one of the following values: |
AnnaBridge | 145:64910690c574 | 1622 | * @arg @ref LL_DMA_REQUEST_0 |
AnnaBridge | 145:64910690c574 | 1623 | * @arg @ref LL_DMA_REQUEST_1 |
AnnaBridge | 145:64910690c574 | 1624 | * @arg @ref LL_DMA_REQUEST_2 |
AnnaBridge | 145:64910690c574 | 1625 | * @arg @ref LL_DMA_REQUEST_3 |
AnnaBridge | 145:64910690c574 | 1626 | * @arg @ref LL_DMA_REQUEST_4 |
AnnaBridge | 145:64910690c574 | 1627 | * @arg @ref LL_DMA_REQUEST_5 |
AnnaBridge | 145:64910690c574 | 1628 | * @arg @ref LL_DMA_REQUEST_6 |
AnnaBridge | 145:64910690c574 | 1629 | * @arg @ref LL_DMA_REQUEST_7 |
AnnaBridge | 145:64910690c574 | 1630 | */ |
AnnaBridge | 145:64910690c574 | 1631 | __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 1632 | { |
AnnaBridge | 145:64910690c574 | 1633 | return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, |
AnnaBridge | 145:64910690c574 | 1634 | DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS); |
AnnaBridge | 145:64910690c574 | 1635 | } |
AnnaBridge | 161:aa5281ff4a02 | 1636 | #endif /* DMAMUX1 */ |
AnnaBridge | 145:64910690c574 | 1637 | |
AnnaBridge | 145:64910690c574 | 1638 | /** |
AnnaBridge | 145:64910690c574 | 1639 | * @} |
AnnaBridge | 145:64910690c574 | 1640 | */ |
AnnaBridge | 145:64910690c574 | 1641 | |
AnnaBridge | 145:64910690c574 | 1642 | /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management |
AnnaBridge | 145:64910690c574 | 1643 | * @{ |
AnnaBridge | 145:64910690c574 | 1644 | */ |
AnnaBridge | 145:64910690c574 | 1645 | |
AnnaBridge | 145:64910690c574 | 1646 | /** |
AnnaBridge | 145:64910690c574 | 1647 | * @brief Get Channel 1 global interrupt flag. |
AnnaBridge | 145:64910690c574 | 1648 | * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 |
AnnaBridge | 145:64910690c574 | 1649 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1650 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1651 | */ |
AnnaBridge | 145:64910690c574 | 1652 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1653 | { |
AnnaBridge | 145:64910690c574 | 1654 | return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); |
AnnaBridge | 145:64910690c574 | 1655 | } |
AnnaBridge | 145:64910690c574 | 1656 | |
AnnaBridge | 145:64910690c574 | 1657 | /** |
AnnaBridge | 145:64910690c574 | 1658 | * @brief Get Channel 2 global interrupt flag. |
AnnaBridge | 145:64910690c574 | 1659 | * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 |
AnnaBridge | 145:64910690c574 | 1660 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1661 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1662 | */ |
AnnaBridge | 145:64910690c574 | 1663 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1664 | { |
AnnaBridge | 145:64910690c574 | 1665 | return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); |
AnnaBridge | 145:64910690c574 | 1666 | } |
AnnaBridge | 145:64910690c574 | 1667 | |
AnnaBridge | 145:64910690c574 | 1668 | /** |
AnnaBridge | 145:64910690c574 | 1669 | * @brief Get Channel 3 global interrupt flag. |
AnnaBridge | 145:64910690c574 | 1670 | * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 |
AnnaBridge | 145:64910690c574 | 1671 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1672 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1673 | */ |
AnnaBridge | 145:64910690c574 | 1674 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1675 | { |
AnnaBridge | 145:64910690c574 | 1676 | return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); |
AnnaBridge | 145:64910690c574 | 1677 | } |
AnnaBridge | 145:64910690c574 | 1678 | |
AnnaBridge | 145:64910690c574 | 1679 | /** |
AnnaBridge | 145:64910690c574 | 1680 | * @brief Get Channel 4 global interrupt flag. |
AnnaBridge | 145:64910690c574 | 1681 | * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 |
AnnaBridge | 145:64910690c574 | 1682 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1683 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1684 | */ |
AnnaBridge | 145:64910690c574 | 1685 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1686 | { |
AnnaBridge | 145:64910690c574 | 1687 | return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)); |
AnnaBridge | 145:64910690c574 | 1688 | } |
AnnaBridge | 145:64910690c574 | 1689 | |
AnnaBridge | 145:64910690c574 | 1690 | /** |
AnnaBridge | 145:64910690c574 | 1691 | * @brief Get Channel 5 global interrupt flag. |
AnnaBridge | 145:64910690c574 | 1692 | * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 |
AnnaBridge | 145:64910690c574 | 1693 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1694 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1695 | */ |
AnnaBridge | 145:64910690c574 | 1696 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1697 | { |
AnnaBridge | 145:64910690c574 | 1698 | return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)); |
AnnaBridge | 145:64910690c574 | 1699 | } |
AnnaBridge | 145:64910690c574 | 1700 | |
AnnaBridge | 145:64910690c574 | 1701 | /** |
AnnaBridge | 145:64910690c574 | 1702 | * @brief Get Channel 6 global interrupt flag. |
AnnaBridge | 145:64910690c574 | 1703 | * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 |
AnnaBridge | 145:64910690c574 | 1704 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1705 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1706 | */ |
AnnaBridge | 145:64910690c574 | 1707 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1708 | { |
AnnaBridge | 145:64910690c574 | 1709 | return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)); |
AnnaBridge | 145:64910690c574 | 1710 | } |
AnnaBridge | 145:64910690c574 | 1711 | |
AnnaBridge | 145:64910690c574 | 1712 | /** |
AnnaBridge | 145:64910690c574 | 1713 | * @brief Get Channel 7 global interrupt flag. |
AnnaBridge | 145:64910690c574 | 1714 | * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 |
AnnaBridge | 145:64910690c574 | 1715 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1716 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1717 | */ |
AnnaBridge | 145:64910690c574 | 1718 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1719 | { |
AnnaBridge | 145:64910690c574 | 1720 | return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)); |
AnnaBridge | 145:64910690c574 | 1721 | } |
AnnaBridge | 145:64910690c574 | 1722 | |
AnnaBridge | 145:64910690c574 | 1723 | /** |
AnnaBridge | 145:64910690c574 | 1724 | * @brief Get Channel 1 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 1725 | * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 |
AnnaBridge | 145:64910690c574 | 1726 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1727 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1728 | */ |
AnnaBridge | 145:64910690c574 | 1729 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1730 | { |
AnnaBridge | 145:64910690c574 | 1731 | return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); |
AnnaBridge | 145:64910690c574 | 1732 | } |
AnnaBridge | 145:64910690c574 | 1733 | |
AnnaBridge | 145:64910690c574 | 1734 | /** |
AnnaBridge | 145:64910690c574 | 1735 | * @brief Get Channel 2 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 1736 | * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 |
AnnaBridge | 145:64910690c574 | 1737 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1738 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1739 | */ |
AnnaBridge | 145:64910690c574 | 1740 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1741 | { |
AnnaBridge | 145:64910690c574 | 1742 | return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); |
AnnaBridge | 145:64910690c574 | 1743 | } |
AnnaBridge | 145:64910690c574 | 1744 | |
AnnaBridge | 145:64910690c574 | 1745 | /** |
AnnaBridge | 145:64910690c574 | 1746 | * @brief Get Channel 3 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 1747 | * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 |
AnnaBridge | 145:64910690c574 | 1748 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1749 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1750 | */ |
AnnaBridge | 145:64910690c574 | 1751 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1752 | { |
AnnaBridge | 145:64910690c574 | 1753 | return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); |
AnnaBridge | 145:64910690c574 | 1754 | } |
AnnaBridge | 145:64910690c574 | 1755 | |
AnnaBridge | 145:64910690c574 | 1756 | /** |
AnnaBridge | 145:64910690c574 | 1757 | * @brief Get Channel 4 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 1758 | * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 |
AnnaBridge | 145:64910690c574 | 1759 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1760 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1761 | */ |
AnnaBridge | 145:64910690c574 | 1762 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1763 | { |
AnnaBridge | 145:64910690c574 | 1764 | return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)); |
AnnaBridge | 145:64910690c574 | 1765 | } |
AnnaBridge | 145:64910690c574 | 1766 | |
AnnaBridge | 145:64910690c574 | 1767 | /** |
AnnaBridge | 145:64910690c574 | 1768 | * @brief Get Channel 5 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 1769 | * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 |
AnnaBridge | 145:64910690c574 | 1770 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1771 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1772 | */ |
AnnaBridge | 145:64910690c574 | 1773 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1774 | { |
AnnaBridge | 145:64910690c574 | 1775 | return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)); |
AnnaBridge | 145:64910690c574 | 1776 | } |
AnnaBridge | 145:64910690c574 | 1777 | |
AnnaBridge | 145:64910690c574 | 1778 | /** |
AnnaBridge | 145:64910690c574 | 1779 | * @brief Get Channel 6 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 1780 | * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 |
AnnaBridge | 145:64910690c574 | 1781 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1782 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1783 | */ |
AnnaBridge | 145:64910690c574 | 1784 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1785 | { |
AnnaBridge | 145:64910690c574 | 1786 | return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)); |
AnnaBridge | 145:64910690c574 | 1787 | } |
AnnaBridge | 145:64910690c574 | 1788 | |
AnnaBridge | 145:64910690c574 | 1789 | /** |
AnnaBridge | 145:64910690c574 | 1790 | * @brief Get Channel 7 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 1791 | * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 |
AnnaBridge | 145:64910690c574 | 1792 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1793 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1794 | */ |
AnnaBridge | 145:64910690c574 | 1795 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1796 | { |
AnnaBridge | 145:64910690c574 | 1797 | return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)); |
AnnaBridge | 145:64910690c574 | 1798 | } |
AnnaBridge | 145:64910690c574 | 1799 | |
AnnaBridge | 145:64910690c574 | 1800 | /** |
AnnaBridge | 145:64910690c574 | 1801 | * @brief Get Channel 1 half transfer flag. |
AnnaBridge | 145:64910690c574 | 1802 | * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 |
AnnaBridge | 145:64910690c574 | 1803 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1804 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1805 | */ |
AnnaBridge | 145:64910690c574 | 1806 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1807 | { |
AnnaBridge | 145:64910690c574 | 1808 | return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); |
AnnaBridge | 145:64910690c574 | 1809 | } |
AnnaBridge | 145:64910690c574 | 1810 | |
AnnaBridge | 145:64910690c574 | 1811 | /** |
AnnaBridge | 145:64910690c574 | 1812 | * @brief Get Channel 2 half transfer flag. |
AnnaBridge | 145:64910690c574 | 1813 | * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 |
AnnaBridge | 145:64910690c574 | 1814 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1815 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1816 | */ |
AnnaBridge | 145:64910690c574 | 1817 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1818 | { |
AnnaBridge | 145:64910690c574 | 1819 | return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); |
AnnaBridge | 145:64910690c574 | 1820 | } |
AnnaBridge | 145:64910690c574 | 1821 | |
AnnaBridge | 145:64910690c574 | 1822 | /** |
AnnaBridge | 145:64910690c574 | 1823 | * @brief Get Channel 3 half transfer flag. |
AnnaBridge | 145:64910690c574 | 1824 | * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 |
AnnaBridge | 145:64910690c574 | 1825 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1826 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1827 | */ |
AnnaBridge | 145:64910690c574 | 1828 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1829 | { |
AnnaBridge | 145:64910690c574 | 1830 | return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); |
AnnaBridge | 145:64910690c574 | 1831 | } |
AnnaBridge | 145:64910690c574 | 1832 | |
AnnaBridge | 145:64910690c574 | 1833 | /** |
AnnaBridge | 145:64910690c574 | 1834 | * @brief Get Channel 4 half transfer flag. |
AnnaBridge | 145:64910690c574 | 1835 | * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 |
AnnaBridge | 145:64910690c574 | 1836 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1837 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1838 | */ |
AnnaBridge | 145:64910690c574 | 1839 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1840 | { |
AnnaBridge | 145:64910690c574 | 1841 | return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)); |
AnnaBridge | 145:64910690c574 | 1842 | } |
AnnaBridge | 145:64910690c574 | 1843 | |
AnnaBridge | 145:64910690c574 | 1844 | /** |
AnnaBridge | 145:64910690c574 | 1845 | * @brief Get Channel 5 half transfer flag. |
AnnaBridge | 145:64910690c574 | 1846 | * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 |
AnnaBridge | 145:64910690c574 | 1847 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1848 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1849 | */ |
AnnaBridge | 145:64910690c574 | 1850 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1851 | { |
AnnaBridge | 145:64910690c574 | 1852 | return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)); |
AnnaBridge | 145:64910690c574 | 1853 | } |
AnnaBridge | 145:64910690c574 | 1854 | |
AnnaBridge | 145:64910690c574 | 1855 | /** |
AnnaBridge | 145:64910690c574 | 1856 | * @brief Get Channel 6 half transfer flag. |
AnnaBridge | 145:64910690c574 | 1857 | * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 |
AnnaBridge | 145:64910690c574 | 1858 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1859 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1860 | */ |
AnnaBridge | 145:64910690c574 | 1861 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1862 | { |
AnnaBridge | 145:64910690c574 | 1863 | return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)); |
AnnaBridge | 145:64910690c574 | 1864 | } |
AnnaBridge | 145:64910690c574 | 1865 | |
AnnaBridge | 145:64910690c574 | 1866 | /** |
AnnaBridge | 145:64910690c574 | 1867 | * @brief Get Channel 7 half transfer flag. |
AnnaBridge | 145:64910690c574 | 1868 | * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 |
AnnaBridge | 145:64910690c574 | 1869 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1870 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1871 | */ |
AnnaBridge | 145:64910690c574 | 1872 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1873 | { |
AnnaBridge | 145:64910690c574 | 1874 | return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)); |
AnnaBridge | 145:64910690c574 | 1875 | } |
AnnaBridge | 145:64910690c574 | 1876 | |
AnnaBridge | 145:64910690c574 | 1877 | /** |
AnnaBridge | 145:64910690c574 | 1878 | * @brief Get Channel 1 transfer error flag. |
AnnaBridge | 145:64910690c574 | 1879 | * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 |
AnnaBridge | 145:64910690c574 | 1880 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1881 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1882 | */ |
AnnaBridge | 145:64910690c574 | 1883 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1884 | { |
AnnaBridge | 145:64910690c574 | 1885 | return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); |
AnnaBridge | 145:64910690c574 | 1886 | } |
AnnaBridge | 145:64910690c574 | 1887 | |
AnnaBridge | 145:64910690c574 | 1888 | /** |
AnnaBridge | 145:64910690c574 | 1889 | * @brief Get Channel 2 transfer error flag. |
AnnaBridge | 145:64910690c574 | 1890 | * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 |
AnnaBridge | 145:64910690c574 | 1891 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1892 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1893 | */ |
AnnaBridge | 145:64910690c574 | 1894 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1895 | { |
AnnaBridge | 145:64910690c574 | 1896 | return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); |
AnnaBridge | 145:64910690c574 | 1897 | } |
AnnaBridge | 145:64910690c574 | 1898 | |
AnnaBridge | 145:64910690c574 | 1899 | /** |
AnnaBridge | 145:64910690c574 | 1900 | * @brief Get Channel 3 transfer error flag. |
AnnaBridge | 145:64910690c574 | 1901 | * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 |
AnnaBridge | 145:64910690c574 | 1902 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1903 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1904 | */ |
AnnaBridge | 145:64910690c574 | 1905 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1906 | { |
AnnaBridge | 145:64910690c574 | 1907 | return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); |
AnnaBridge | 145:64910690c574 | 1908 | } |
AnnaBridge | 145:64910690c574 | 1909 | |
AnnaBridge | 145:64910690c574 | 1910 | /** |
AnnaBridge | 145:64910690c574 | 1911 | * @brief Get Channel 4 transfer error flag. |
AnnaBridge | 145:64910690c574 | 1912 | * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 |
AnnaBridge | 145:64910690c574 | 1913 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1914 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1915 | */ |
AnnaBridge | 145:64910690c574 | 1916 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1917 | { |
AnnaBridge | 145:64910690c574 | 1918 | return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)); |
AnnaBridge | 145:64910690c574 | 1919 | } |
AnnaBridge | 145:64910690c574 | 1920 | |
AnnaBridge | 145:64910690c574 | 1921 | /** |
AnnaBridge | 145:64910690c574 | 1922 | * @brief Get Channel 5 transfer error flag. |
AnnaBridge | 145:64910690c574 | 1923 | * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 |
AnnaBridge | 145:64910690c574 | 1924 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1925 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1926 | */ |
AnnaBridge | 145:64910690c574 | 1927 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1928 | { |
AnnaBridge | 145:64910690c574 | 1929 | return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)); |
AnnaBridge | 145:64910690c574 | 1930 | } |
AnnaBridge | 145:64910690c574 | 1931 | |
AnnaBridge | 145:64910690c574 | 1932 | /** |
AnnaBridge | 145:64910690c574 | 1933 | * @brief Get Channel 6 transfer error flag. |
AnnaBridge | 145:64910690c574 | 1934 | * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 |
AnnaBridge | 145:64910690c574 | 1935 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1936 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1937 | */ |
AnnaBridge | 145:64910690c574 | 1938 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1939 | { |
AnnaBridge | 145:64910690c574 | 1940 | return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)); |
AnnaBridge | 145:64910690c574 | 1941 | } |
AnnaBridge | 145:64910690c574 | 1942 | |
AnnaBridge | 145:64910690c574 | 1943 | /** |
AnnaBridge | 145:64910690c574 | 1944 | * @brief Get Channel 7 transfer error flag. |
AnnaBridge | 145:64910690c574 | 1945 | * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 |
AnnaBridge | 145:64910690c574 | 1946 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1947 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 1948 | */ |
AnnaBridge | 145:64910690c574 | 1949 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1950 | { |
AnnaBridge | 145:64910690c574 | 1951 | return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)); |
AnnaBridge | 145:64910690c574 | 1952 | } |
AnnaBridge | 145:64910690c574 | 1953 | |
AnnaBridge | 145:64910690c574 | 1954 | /** |
AnnaBridge | 145:64910690c574 | 1955 | * @brief Clear Channel 1 global interrupt flag. |
AnnaBridge | 145:64910690c574 | 1956 | * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 |
AnnaBridge | 145:64910690c574 | 1957 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1958 | * @retval None |
AnnaBridge | 145:64910690c574 | 1959 | */ |
AnnaBridge | 145:64910690c574 | 1960 | __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1961 | { |
AnnaBridge | 145:64910690c574 | 1962 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); |
AnnaBridge | 145:64910690c574 | 1963 | } |
AnnaBridge | 145:64910690c574 | 1964 | |
AnnaBridge | 145:64910690c574 | 1965 | /** |
AnnaBridge | 145:64910690c574 | 1966 | * @brief Clear Channel 2 global interrupt flag. |
AnnaBridge | 145:64910690c574 | 1967 | * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 |
AnnaBridge | 145:64910690c574 | 1968 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1969 | * @retval None |
AnnaBridge | 145:64910690c574 | 1970 | */ |
AnnaBridge | 145:64910690c574 | 1971 | __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1972 | { |
AnnaBridge | 145:64910690c574 | 1973 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); |
AnnaBridge | 145:64910690c574 | 1974 | } |
AnnaBridge | 145:64910690c574 | 1975 | |
AnnaBridge | 145:64910690c574 | 1976 | /** |
AnnaBridge | 145:64910690c574 | 1977 | * @brief Clear Channel 3 global interrupt flag. |
AnnaBridge | 145:64910690c574 | 1978 | * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 |
AnnaBridge | 145:64910690c574 | 1979 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1980 | * @retval None |
AnnaBridge | 145:64910690c574 | 1981 | */ |
AnnaBridge | 145:64910690c574 | 1982 | __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1983 | { |
AnnaBridge | 145:64910690c574 | 1984 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); |
AnnaBridge | 145:64910690c574 | 1985 | } |
AnnaBridge | 145:64910690c574 | 1986 | |
AnnaBridge | 145:64910690c574 | 1987 | /** |
AnnaBridge | 145:64910690c574 | 1988 | * @brief Clear Channel 4 global interrupt flag. |
AnnaBridge | 145:64910690c574 | 1989 | * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 |
AnnaBridge | 145:64910690c574 | 1990 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 1991 | * @retval None |
AnnaBridge | 145:64910690c574 | 1992 | */ |
AnnaBridge | 145:64910690c574 | 1993 | __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 1994 | { |
AnnaBridge | 145:64910690c574 | 1995 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); |
AnnaBridge | 145:64910690c574 | 1996 | } |
AnnaBridge | 145:64910690c574 | 1997 | |
AnnaBridge | 145:64910690c574 | 1998 | /** |
AnnaBridge | 145:64910690c574 | 1999 | * @brief Clear Channel 5 global interrupt flag. |
AnnaBridge | 145:64910690c574 | 2000 | * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 |
AnnaBridge | 145:64910690c574 | 2001 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2002 | * @retval None |
AnnaBridge | 145:64910690c574 | 2003 | */ |
AnnaBridge | 145:64910690c574 | 2004 | __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2005 | { |
AnnaBridge | 145:64910690c574 | 2006 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); |
AnnaBridge | 145:64910690c574 | 2007 | } |
AnnaBridge | 145:64910690c574 | 2008 | |
AnnaBridge | 145:64910690c574 | 2009 | /** |
AnnaBridge | 145:64910690c574 | 2010 | * @brief Clear Channel 6 global interrupt flag. |
AnnaBridge | 145:64910690c574 | 2011 | * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 |
AnnaBridge | 145:64910690c574 | 2012 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2013 | * @retval None |
AnnaBridge | 145:64910690c574 | 2014 | */ |
AnnaBridge | 145:64910690c574 | 2015 | __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2016 | { |
AnnaBridge | 145:64910690c574 | 2017 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); |
AnnaBridge | 145:64910690c574 | 2018 | } |
AnnaBridge | 145:64910690c574 | 2019 | |
AnnaBridge | 145:64910690c574 | 2020 | /** |
AnnaBridge | 145:64910690c574 | 2021 | * @brief Clear Channel 7 global interrupt flag. |
AnnaBridge | 145:64910690c574 | 2022 | * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 |
AnnaBridge | 145:64910690c574 | 2023 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2024 | * @retval None |
AnnaBridge | 145:64910690c574 | 2025 | */ |
AnnaBridge | 145:64910690c574 | 2026 | __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2027 | { |
AnnaBridge | 145:64910690c574 | 2028 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); |
AnnaBridge | 145:64910690c574 | 2029 | } |
AnnaBridge | 145:64910690c574 | 2030 | |
AnnaBridge | 145:64910690c574 | 2031 | /** |
AnnaBridge | 145:64910690c574 | 2032 | * @brief Clear Channel 1 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 2033 | * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 |
AnnaBridge | 145:64910690c574 | 2034 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2035 | * @retval None |
AnnaBridge | 145:64910690c574 | 2036 | */ |
AnnaBridge | 145:64910690c574 | 2037 | __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2038 | { |
AnnaBridge | 145:64910690c574 | 2039 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); |
AnnaBridge | 145:64910690c574 | 2040 | } |
AnnaBridge | 145:64910690c574 | 2041 | |
AnnaBridge | 145:64910690c574 | 2042 | /** |
AnnaBridge | 145:64910690c574 | 2043 | * @brief Clear Channel 2 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 2044 | * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 |
AnnaBridge | 145:64910690c574 | 2045 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2046 | * @retval None |
AnnaBridge | 145:64910690c574 | 2047 | */ |
AnnaBridge | 145:64910690c574 | 2048 | __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2049 | { |
AnnaBridge | 145:64910690c574 | 2050 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); |
AnnaBridge | 145:64910690c574 | 2051 | } |
AnnaBridge | 145:64910690c574 | 2052 | |
AnnaBridge | 145:64910690c574 | 2053 | /** |
AnnaBridge | 145:64910690c574 | 2054 | * @brief Clear Channel 3 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 2055 | * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 |
AnnaBridge | 145:64910690c574 | 2056 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2057 | * @retval None |
AnnaBridge | 145:64910690c574 | 2058 | */ |
AnnaBridge | 145:64910690c574 | 2059 | __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2060 | { |
AnnaBridge | 145:64910690c574 | 2061 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); |
AnnaBridge | 145:64910690c574 | 2062 | } |
AnnaBridge | 145:64910690c574 | 2063 | |
AnnaBridge | 145:64910690c574 | 2064 | /** |
AnnaBridge | 145:64910690c574 | 2065 | * @brief Clear Channel 4 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 2066 | * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 |
AnnaBridge | 145:64910690c574 | 2067 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2068 | * @retval None |
AnnaBridge | 145:64910690c574 | 2069 | */ |
AnnaBridge | 145:64910690c574 | 2070 | __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2071 | { |
AnnaBridge | 145:64910690c574 | 2072 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); |
AnnaBridge | 145:64910690c574 | 2073 | } |
AnnaBridge | 145:64910690c574 | 2074 | |
AnnaBridge | 145:64910690c574 | 2075 | /** |
AnnaBridge | 145:64910690c574 | 2076 | * @brief Clear Channel 5 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 2077 | * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 |
AnnaBridge | 145:64910690c574 | 2078 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2079 | * @retval None |
AnnaBridge | 145:64910690c574 | 2080 | */ |
AnnaBridge | 145:64910690c574 | 2081 | __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2082 | { |
AnnaBridge | 145:64910690c574 | 2083 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); |
AnnaBridge | 145:64910690c574 | 2084 | } |
AnnaBridge | 145:64910690c574 | 2085 | |
AnnaBridge | 145:64910690c574 | 2086 | /** |
AnnaBridge | 145:64910690c574 | 2087 | * @brief Clear Channel 6 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 2088 | * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 |
AnnaBridge | 145:64910690c574 | 2089 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2090 | * @retval None |
AnnaBridge | 145:64910690c574 | 2091 | */ |
AnnaBridge | 145:64910690c574 | 2092 | __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2093 | { |
AnnaBridge | 145:64910690c574 | 2094 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); |
AnnaBridge | 145:64910690c574 | 2095 | } |
AnnaBridge | 145:64910690c574 | 2096 | |
AnnaBridge | 145:64910690c574 | 2097 | /** |
AnnaBridge | 145:64910690c574 | 2098 | * @brief Clear Channel 7 transfer complete flag. |
AnnaBridge | 145:64910690c574 | 2099 | * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 |
AnnaBridge | 145:64910690c574 | 2100 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2101 | * @retval None |
AnnaBridge | 145:64910690c574 | 2102 | */ |
AnnaBridge | 145:64910690c574 | 2103 | __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2104 | { |
AnnaBridge | 145:64910690c574 | 2105 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); |
AnnaBridge | 145:64910690c574 | 2106 | } |
AnnaBridge | 145:64910690c574 | 2107 | |
AnnaBridge | 145:64910690c574 | 2108 | /** |
AnnaBridge | 145:64910690c574 | 2109 | * @brief Clear Channel 1 half transfer flag. |
AnnaBridge | 145:64910690c574 | 2110 | * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 |
AnnaBridge | 145:64910690c574 | 2111 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2112 | * @retval None |
AnnaBridge | 145:64910690c574 | 2113 | */ |
AnnaBridge | 145:64910690c574 | 2114 | __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2115 | { |
AnnaBridge | 145:64910690c574 | 2116 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); |
AnnaBridge | 145:64910690c574 | 2117 | } |
AnnaBridge | 145:64910690c574 | 2118 | |
AnnaBridge | 145:64910690c574 | 2119 | /** |
AnnaBridge | 145:64910690c574 | 2120 | * @brief Clear Channel 2 half transfer flag. |
AnnaBridge | 145:64910690c574 | 2121 | * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 |
AnnaBridge | 145:64910690c574 | 2122 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2123 | * @retval None |
AnnaBridge | 145:64910690c574 | 2124 | */ |
AnnaBridge | 145:64910690c574 | 2125 | __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2126 | { |
AnnaBridge | 145:64910690c574 | 2127 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); |
AnnaBridge | 145:64910690c574 | 2128 | } |
AnnaBridge | 145:64910690c574 | 2129 | |
AnnaBridge | 145:64910690c574 | 2130 | /** |
AnnaBridge | 145:64910690c574 | 2131 | * @brief Clear Channel 3 half transfer flag. |
AnnaBridge | 145:64910690c574 | 2132 | * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 |
AnnaBridge | 145:64910690c574 | 2133 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2134 | * @retval None |
AnnaBridge | 145:64910690c574 | 2135 | */ |
AnnaBridge | 145:64910690c574 | 2136 | __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2137 | { |
AnnaBridge | 145:64910690c574 | 2138 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); |
AnnaBridge | 145:64910690c574 | 2139 | } |
AnnaBridge | 145:64910690c574 | 2140 | |
AnnaBridge | 145:64910690c574 | 2141 | /** |
AnnaBridge | 145:64910690c574 | 2142 | * @brief Clear Channel 4 half transfer flag. |
AnnaBridge | 145:64910690c574 | 2143 | * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 |
AnnaBridge | 145:64910690c574 | 2144 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2145 | * @retval None |
AnnaBridge | 145:64910690c574 | 2146 | */ |
AnnaBridge | 145:64910690c574 | 2147 | __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2148 | { |
AnnaBridge | 145:64910690c574 | 2149 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); |
AnnaBridge | 145:64910690c574 | 2150 | } |
AnnaBridge | 145:64910690c574 | 2151 | |
AnnaBridge | 145:64910690c574 | 2152 | /** |
AnnaBridge | 145:64910690c574 | 2153 | * @brief Clear Channel 5 half transfer flag. |
AnnaBridge | 145:64910690c574 | 2154 | * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 |
AnnaBridge | 145:64910690c574 | 2155 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2156 | * @retval None |
AnnaBridge | 145:64910690c574 | 2157 | */ |
AnnaBridge | 145:64910690c574 | 2158 | __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2159 | { |
AnnaBridge | 145:64910690c574 | 2160 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); |
AnnaBridge | 145:64910690c574 | 2161 | } |
AnnaBridge | 145:64910690c574 | 2162 | |
AnnaBridge | 145:64910690c574 | 2163 | /** |
AnnaBridge | 145:64910690c574 | 2164 | * @brief Clear Channel 6 half transfer flag. |
AnnaBridge | 145:64910690c574 | 2165 | * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 |
AnnaBridge | 145:64910690c574 | 2166 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2167 | * @retval None |
AnnaBridge | 145:64910690c574 | 2168 | */ |
AnnaBridge | 145:64910690c574 | 2169 | __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2170 | { |
AnnaBridge | 145:64910690c574 | 2171 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); |
AnnaBridge | 145:64910690c574 | 2172 | } |
AnnaBridge | 145:64910690c574 | 2173 | |
AnnaBridge | 145:64910690c574 | 2174 | /** |
AnnaBridge | 145:64910690c574 | 2175 | * @brief Clear Channel 7 half transfer flag. |
AnnaBridge | 145:64910690c574 | 2176 | * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 |
AnnaBridge | 145:64910690c574 | 2177 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2178 | * @retval None |
AnnaBridge | 145:64910690c574 | 2179 | */ |
AnnaBridge | 145:64910690c574 | 2180 | __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2181 | { |
AnnaBridge | 145:64910690c574 | 2182 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); |
AnnaBridge | 145:64910690c574 | 2183 | } |
AnnaBridge | 145:64910690c574 | 2184 | |
AnnaBridge | 145:64910690c574 | 2185 | /** |
AnnaBridge | 145:64910690c574 | 2186 | * @brief Clear Channel 1 transfer error flag. |
AnnaBridge | 145:64910690c574 | 2187 | * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 |
AnnaBridge | 145:64910690c574 | 2188 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2189 | * @retval None |
AnnaBridge | 145:64910690c574 | 2190 | */ |
AnnaBridge | 145:64910690c574 | 2191 | __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2192 | { |
AnnaBridge | 145:64910690c574 | 2193 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); |
AnnaBridge | 145:64910690c574 | 2194 | } |
AnnaBridge | 145:64910690c574 | 2195 | |
AnnaBridge | 145:64910690c574 | 2196 | /** |
AnnaBridge | 145:64910690c574 | 2197 | * @brief Clear Channel 2 transfer error flag. |
AnnaBridge | 145:64910690c574 | 2198 | * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 |
AnnaBridge | 145:64910690c574 | 2199 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2200 | * @retval None |
AnnaBridge | 145:64910690c574 | 2201 | */ |
AnnaBridge | 145:64910690c574 | 2202 | __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2203 | { |
AnnaBridge | 145:64910690c574 | 2204 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); |
AnnaBridge | 145:64910690c574 | 2205 | } |
AnnaBridge | 145:64910690c574 | 2206 | |
AnnaBridge | 145:64910690c574 | 2207 | /** |
AnnaBridge | 145:64910690c574 | 2208 | * @brief Clear Channel 3 transfer error flag. |
AnnaBridge | 145:64910690c574 | 2209 | * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 |
AnnaBridge | 145:64910690c574 | 2210 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2211 | * @retval None |
AnnaBridge | 145:64910690c574 | 2212 | */ |
AnnaBridge | 145:64910690c574 | 2213 | __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2214 | { |
AnnaBridge | 145:64910690c574 | 2215 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); |
AnnaBridge | 145:64910690c574 | 2216 | } |
AnnaBridge | 145:64910690c574 | 2217 | |
AnnaBridge | 145:64910690c574 | 2218 | /** |
AnnaBridge | 145:64910690c574 | 2219 | * @brief Clear Channel 4 transfer error flag. |
AnnaBridge | 145:64910690c574 | 2220 | * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 |
AnnaBridge | 145:64910690c574 | 2221 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2222 | * @retval None |
AnnaBridge | 145:64910690c574 | 2223 | */ |
AnnaBridge | 145:64910690c574 | 2224 | __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2225 | { |
AnnaBridge | 145:64910690c574 | 2226 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); |
AnnaBridge | 145:64910690c574 | 2227 | } |
AnnaBridge | 145:64910690c574 | 2228 | |
AnnaBridge | 145:64910690c574 | 2229 | /** |
AnnaBridge | 145:64910690c574 | 2230 | * @brief Clear Channel 5 transfer error flag. |
AnnaBridge | 145:64910690c574 | 2231 | * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 |
AnnaBridge | 145:64910690c574 | 2232 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2233 | * @retval None |
AnnaBridge | 145:64910690c574 | 2234 | */ |
AnnaBridge | 145:64910690c574 | 2235 | __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2236 | { |
AnnaBridge | 145:64910690c574 | 2237 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); |
AnnaBridge | 145:64910690c574 | 2238 | } |
AnnaBridge | 145:64910690c574 | 2239 | |
AnnaBridge | 145:64910690c574 | 2240 | /** |
AnnaBridge | 145:64910690c574 | 2241 | * @brief Clear Channel 6 transfer error flag. |
AnnaBridge | 145:64910690c574 | 2242 | * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 |
AnnaBridge | 145:64910690c574 | 2243 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2244 | * @retval None |
AnnaBridge | 145:64910690c574 | 2245 | */ |
AnnaBridge | 145:64910690c574 | 2246 | __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2247 | { |
AnnaBridge | 145:64910690c574 | 2248 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); |
AnnaBridge | 145:64910690c574 | 2249 | } |
AnnaBridge | 145:64910690c574 | 2250 | |
AnnaBridge | 145:64910690c574 | 2251 | /** |
AnnaBridge | 145:64910690c574 | 2252 | * @brief Clear Channel 7 transfer error flag. |
AnnaBridge | 145:64910690c574 | 2253 | * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 |
AnnaBridge | 145:64910690c574 | 2254 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2255 | * @retval None |
AnnaBridge | 145:64910690c574 | 2256 | */ |
AnnaBridge | 145:64910690c574 | 2257 | __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) |
AnnaBridge | 145:64910690c574 | 2258 | { |
AnnaBridge | 145:64910690c574 | 2259 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); |
AnnaBridge | 145:64910690c574 | 2260 | } |
AnnaBridge | 145:64910690c574 | 2261 | |
AnnaBridge | 145:64910690c574 | 2262 | /** |
AnnaBridge | 145:64910690c574 | 2263 | * @} |
AnnaBridge | 145:64910690c574 | 2264 | */ |
AnnaBridge | 145:64910690c574 | 2265 | |
AnnaBridge | 145:64910690c574 | 2266 | /** @defgroup DMA_LL_EF_IT_Management IT_Management |
AnnaBridge | 145:64910690c574 | 2267 | * @{ |
AnnaBridge | 145:64910690c574 | 2268 | */ |
AnnaBridge | 145:64910690c574 | 2269 | /** |
AnnaBridge | 145:64910690c574 | 2270 | * @brief Enable Transfer complete interrupt. |
AnnaBridge | 145:64910690c574 | 2271 | * @rmtoll CCR TCIE LL_DMA_EnableIT_TC |
AnnaBridge | 145:64910690c574 | 2272 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2273 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2274 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 2275 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 2276 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 2277 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 2278 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 2279 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 2280 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 2281 | * @retval None |
AnnaBridge | 145:64910690c574 | 2282 | */ |
AnnaBridge | 145:64910690c574 | 2283 | __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 2284 | { |
AnnaBridge | 145:64910690c574 | 2285 | SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); |
AnnaBridge | 145:64910690c574 | 2286 | } |
AnnaBridge | 145:64910690c574 | 2287 | |
AnnaBridge | 145:64910690c574 | 2288 | /** |
AnnaBridge | 145:64910690c574 | 2289 | * @brief Enable Half transfer interrupt. |
AnnaBridge | 145:64910690c574 | 2290 | * @rmtoll CCR HTIE LL_DMA_EnableIT_HT |
AnnaBridge | 145:64910690c574 | 2291 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2292 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2293 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 2294 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 2295 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 2296 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 2297 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 2298 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 2299 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 2300 | * @retval None |
AnnaBridge | 145:64910690c574 | 2301 | */ |
AnnaBridge | 145:64910690c574 | 2302 | __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 2303 | { |
AnnaBridge | 145:64910690c574 | 2304 | SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); |
AnnaBridge | 145:64910690c574 | 2305 | } |
AnnaBridge | 145:64910690c574 | 2306 | |
AnnaBridge | 145:64910690c574 | 2307 | /** |
AnnaBridge | 145:64910690c574 | 2308 | * @brief Enable Transfer error interrupt. |
AnnaBridge | 145:64910690c574 | 2309 | * @rmtoll CCR TEIE LL_DMA_EnableIT_TE |
AnnaBridge | 145:64910690c574 | 2310 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2311 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2312 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 2313 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 2314 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 2315 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 2316 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 2317 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 2318 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 2319 | * @retval None |
AnnaBridge | 145:64910690c574 | 2320 | */ |
AnnaBridge | 145:64910690c574 | 2321 | __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 2322 | { |
AnnaBridge | 145:64910690c574 | 2323 | SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); |
AnnaBridge | 145:64910690c574 | 2324 | } |
AnnaBridge | 145:64910690c574 | 2325 | |
AnnaBridge | 145:64910690c574 | 2326 | /** |
AnnaBridge | 145:64910690c574 | 2327 | * @brief Disable Transfer complete interrupt. |
AnnaBridge | 145:64910690c574 | 2328 | * @rmtoll CCR TCIE LL_DMA_DisableIT_TC |
AnnaBridge | 145:64910690c574 | 2329 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2330 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2331 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 2332 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 2333 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 2334 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 2335 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 2336 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 2337 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 2338 | * @retval None |
AnnaBridge | 145:64910690c574 | 2339 | */ |
AnnaBridge | 145:64910690c574 | 2340 | __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 2341 | { |
AnnaBridge | 145:64910690c574 | 2342 | CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); |
AnnaBridge | 145:64910690c574 | 2343 | } |
AnnaBridge | 145:64910690c574 | 2344 | |
AnnaBridge | 145:64910690c574 | 2345 | /** |
AnnaBridge | 145:64910690c574 | 2346 | * @brief Disable Half transfer interrupt. |
AnnaBridge | 145:64910690c574 | 2347 | * @rmtoll CCR HTIE LL_DMA_DisableIT_HT |
AnnaBridge | 145:64910690c574 | 2348 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2349 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2350 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 2351 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 2352 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 2353 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 2354 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 2355 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 2356 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 2357 | * @retval None |
AnnaBridge | 145:64910690c574 | 2358 | */ |
AnnaBridge | 145:64910690c574 | 2359 | __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 2360 | { |
AnnaBridge | 145:64910690c574 | 2361 | CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); |
AnnaBridge | 145:64910690c574 | 2362 | } |
AnnaBridge | 145:64910690c574 | 2363 | |
AnnaBridge | 145:64910690c574 | 2364 | /** |
AnnaBridge | 145:64910690c574 | 2365 | * @brief Disable Transfer error interrupt. |
AnnaBridge | 145:64910690c574 | 2366 | * @rmtoll CCR TEIE LL_DMA_DisableIT_TE |
AnnaBridge | 145:64910690c574 | 2367 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2368 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2369 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 2370 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 2371 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 2372 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 2373 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 2374 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 2375 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 2376 | * @retval None |
AnnaBridge | 145:64910690c574 | 2377 | */ |
AnnaBridge | 145:64910690c574 | 2378 | __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 2379 | { |
AnnaBridge | 145:64910690c574 | 2380 | CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); |
AnnaBridge | 145:64910690c574 | 2381 | } |
AnnaBridge | 145:64910690c574 | 2382 | |
AnnaBridge | 145:64910690c574 | 2383 | /** |
AnnaBridge | 145:64910690c574 | 2384 | * @brief Check if Transfer complete Interrupt is enabled. |
AnnaBridge | 145:64910690c574 | 2385 | * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC |
AnnaBridge | 145:64910690c574 | 2386 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2387 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2388 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 2389 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 2390 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 2391 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 2392 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 2393 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 2394 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 2395 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 2396 | */ |
AnnaBridge | 145:64910690c574 | 2397 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 2398 | { |
AnnaBridge | 145:64910690c574 | 2399 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 145:64910690c574 | 2400 | DMA_CCR_TCIE) == (DMA_CCR_TCIE)); |
AnnaBridge | 145:64910690c574 | 2401 | } |
AnnaBridge | 145:64910690c574 | 2402 | |
AnnaBridge | 145:64910690c574 | 2403 | /** |
AnnaBridge | 145:64910690c574 | 2404 | * @brief Check if Half transfer Interrupt is enabled. |
AnnaBridge | 145:64910690c574 | 2405 | * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT |
AnnaBridge | 145:64910690c574 | 2406 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2407 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2408 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 2409 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 2410 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 2411 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 2412 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 2413 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 2414 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 2415 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 2416 | */ |
AnnaBridge | 145:64910690c574 | 2417 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 2418 | { |
AnnaBridge | 145:64910690c574 | 2419 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 145:64910690c574 | 2420 | DMA_CCR_HTIE) == (DMA_CCR_HTIE)); |
AnnaBridge | 145:64910690c574 | 2421 | } |
AnnaBridge | 145:64910690c574 | 2422 | |
AnnaBridge | 145:64910690c574 | 2423 | /** |
AnnaBridge | 145:64910690c574 | 2424 | * @brief Check if Transfer error Interrupt is enabled. |
AnnaBridge | 145:64910690c574 | 2425 | * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE |
AnnaBridge | 145:64910690c574 | 2426 | * @param DMAx DMAx Instance |
AnnaBridge | 145:64910690c574 | 2427 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 145:64910690c574 | 2428 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 145:64910690c574 | 2429 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 145:64910690c574 | 2430 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 145:64910690c574 | 2431 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 145:64910690c574 | 2432 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 145:64910690c574 | 2433 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 145:64910690c574 | 2434 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 145:64910690c574 | 2435 | * @retval State of bit (1 or 0). |
AnnaBridge | 145:64910690c574 | 2436 | */ |
AnnaBridge | 145:64910690c574 | 2437 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 145:64910690c574 | 2438 | { |
AnnaBridge | 145:64910690c574 | 2439 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 145:64910690c574 | 2440 | DMA_CCR_TEIE) == (DMA_CCR_TEIE)); |
AnnaBridge | 145:64910690c574 | 2441 | } |
AnnaBridge | 145:64910690c574 | 2442 | |
AnnaBridge | 145:64910690c574 | 2443 | /** |
AnnaBridge | 145:64910690c574 | 2444 | * @} |
AnnaBridge | 145:64910690c574 | 2445 | */ |
AnnaBridge | 145:64910690c574 | 2446 | |
AnnaBridge | 145:64910690c574 | 2447 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 145:64910690c574 | 2448 | /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions |
AnnaBridge | 145:64910690c574 | 2449 | * @{ |
AnnaBridge | 145:64910690c574 | 2450 | */ |
AnnaBridge | 145:64910690c574 | 2451 | |
AnnaBridge | 145:64910690c574 | 2452 | uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); |
AnnaBridge | 145:64910690c574 | 2453 | uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); |
AnnaBridge | 145:64910690c574 | 2454 | void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); |
AnnaBridge | 145:64910690c574 | 2455 | |
AnnaBridge | 145:64910690c574 | 2456 | /** |
AnnaBridge | 145:64910690c574 | 2457 | * @} |
AnnaBridge | 145:64910690c574 | 2458 | */ |
AnnaBridge | 145:64910690c574 | 2459 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 145:64910690c574 | 2460 | |
AnnaBridge | 145:64910690c574 | 2461 | /** |
AnnaBridge | 145:64910690c574 | 2462 | * @} |
AnnaBridge | 145:64910690c574 | 2463 | */ |
AnnaBridge | 145:64910690c574 | 2464 | |
AnnaBridge | 145:64910690c574 | 2465 | /** |
AnnaBridge | 145:64910690c574 | 2466 | * @} |
AnnaBridge | 145:64910690c574 | 2467 | */ |
AnnaBridge | 145:64910690c574 | 2468 | |
AnnaBridge | 145:64910690c574 | 2469 | #endif /* DMA1 || DMA2 */ |
AnnaBridge | 145:64910690c574 | 2470 | |
AnnaBridge | 145:64910690c574 | 2471 | /** |
AnnaBridge | 145:64910690c574 | 2472 | * @} |
AnnaBridge | 145:64910690c574 | 2473 | */ |
AnnaBridge | 145:64910690c574 | 2474 | |
AnnaBridge | 145:64910690c574 | 2475 | #ifdef __cplusplus |
AnnaBridge | 145:64910690c574 | 2476 | } |
AnnaBridge | 145:64910690c574 | 2477 | #endif |
AnnaBridge | 145:64910690c574 | 2478 | |
AnnaBridge | 145:64910690c574 | 2479 | #endif /* __STM32L4xx_LL_DMA_H */ |
AnnaBridge | 145:64910690c574 | 2480 | |
AnnaBridge | 145:64910690c574 | 2481 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |