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TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_hal_sram.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32l1xx_hal_sram.h |
AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of SRAM HAL module. |
AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
AnnaBridge | 171:3a7713b1edbc | 8 | * |
AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
AnnaBridge | 171:3a7713b1edbc | 10 | * |
AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 32 | * |
AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 34 | */ |
AnnaBridge | 171:3a7713b1edbc | 35 | |
AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32L1xx_HAL_SRAM_H |
AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32L1xx_HAL_SRAM_H |
AnnaBridge | 171:3a7713b1edbc | 39 | |
AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
AnnaBridge | 171:3a7713b1edbc | 43 | |
AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32l1xx_ll_fsmc.h" |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32L1xx_HAL_Driver |
AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 49 | */ |
AnnaBridge | 171:3a7713b1edbc | 50 | |
AnnaBridge | 171:3a7713b1edbc | 51 | #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) |
AnnaBridge | 171:3a7713b1edbc | 52 | |
AnnaBridge | 171:3a7713b1edbc | 53 | /** @addtogroup SRAM |
AnnaBridge | 171:3a7713b1edbc | 54 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 55 | */ |
AnnaBridge | 171:3a7713b1edbc | 56 | |
AnnaBridge | 171:3a7713b1edbc | 57 | /* Exported typedef ----------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 58 | |
AnnaBridge | 171:3a7713b1edbc | 59 | /** @defgroup SRAM_Exported_Types SRAM Exported Types |
AnnaBridge | 171:3a7713b1edbc | 60 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 61 | */ |
AnnaBridge | 171:3a7713b1edbc | 62 | /** |
AnnaBridge | 171:3a7713b1edbc | 63 | * @brief HAL SRAM State structures definition |
AnnaBridge | 171:3a7713b1edbc | 64 | */ |
AnnaBridge | 171:3a7713b1edbc | 65 | typedef enum |
AnnaBridge | 171:3a7713b1edbc | 66 | { |
AnnaBridge | 171:3a7713b1edbc | 67 | HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */ |
AnnaBridge | 171:3a7713b1edbc | 68 | HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */ |
AnnaBridge | 171:3a7713b1edbc | 69 | HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */ |
AnnaBridge | 171:3a7713b1edbc | 70 | HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */ |
AnnaBridge | 171:3a7713b1edbc | 71 | HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */ |
AnnaBridge | 171:3a7713b1edbc | 72 | |
AnnaBridge | 171:3a7713b1edbc | 73 | }HAL_SRAM_StateTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 74 | |
AnnaBridge | 171:3a7713b1edbc | 75 | /** |
AnnaBridge | 171:3a7713b1edbc | 76 | * @brief SRAM handle Structure definition |
AnnaBridge | 171:3a7713b1edbc | 77 | */ |
AnnaBridge | 171:3a7713b1edbc | 78 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 79 | { |
AnnaBridge | 171:3a7713b1edbc | 80 | FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ |
AnnaBridge | 171:3a7713b1edbc | 81 | |
AnnaBridge | 171:3a7713b1edbc | 82 | FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ |
AnnaBridge | 171:3a7713b1edbc | 83 | |
AnnaBridge | 171:3a7713b1edbc | 84 | FSMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ |
AnnaBridge | 171:3a7713b1edbc | 85 | |
AnnaBridge | 171:3a7713b1edbc | 86 | HAL_LockTypeDef Lock; /*!< SRAM locking object */ |
AnnaBridge | 171:3a7713b1edbc | 87 | |
AnnaBridge | 171:3a7713b1edbc | 88 | __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ |
AnnaBridge | 171:3a7713b1edbc | 89 | |
AnnaBridge | 171:3a7713b1edbc | 90 | DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ |
AnnaBridge | 171:3a7713b1edbc | 91 | |
AnnaBridge | 171:3a7713b1edbc | 92 | }SRAM_HandleTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 93 | |
AnnaBridge | 171:3a7713b1edbc | 94 | /** |
AnnaBridge | 171:3a7713b1edbc | 95 | * @} |
AnnaBridge | 171:3a7713b1edbc | 96 | */ |
AnnaBridge | 171:3a7713b1edbc | 97 | |
AnnaBridge | 171:3a7713b1edbc | 98 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 99 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 100 | |
AnnaBridge | 171:3a7713b1edbc | 101 | /** @defgroup SRAM_Exported_Macros SRAM Exported Macros |
AnnaBridge | 171:3a7713b1edbc | 102 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 103 | */ |
AnnaBridge | 171:3a7713b1edbc | 104 | |
AnnaBridge | 171:3a7713b1edbc | 105 | /** @brief Reset SRAM handle state |
AnnaBridge | 171:3a7713b1edbc | 106 | * @param __HANDLE__: SRAM handle |
AnnaBridge | 171:3a7713b1edbc | 107 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 108 | */ |
AnnaBridge | 171:3a7713b1edbc | 109 | #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) |
AnnaBridge | 171:3a7713b1edbc | 110 | |
AnnaBridge | 171:3a7713b1edbc | 111 | /** |
AnnaBridge | 171:3a7713b1edbc | 112 | * @} |
AnnaBridge | 171:3a7713b1edbc | 113 | */ |
AnnaBridge | 171:3a7713b1edbc | 114 | |
AnnaBridge | 171:3a7713b1edbc | 115 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 116 | |
AnnaBridge | 171:3a7713b1edbc | 117 | /** @addtogroup SRAM_Exported_Functions |
AnnaBridge | 171:3a7713b1edbc | 118 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 119 | */ |
AnnaBridge | 171:3a7713b1edbc | 120 | |
AnnaBridge | 171:3a7713b1edbc | 121 | /** @addtogroup SRAM_Exported_Functions_Group1 |
AnnaBridge | 171:3a7713b1edbc | 122 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 123 | */ |
AnnaBridge | 171:3a7713b1edbc | 124 | |
AnnaBridge | 171:3a7713b1edbc | 125 | /* Initialization/de-initialization functions **********************************/ |
AnnaBridge | 171:3a7713b1edbc | 126 | HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming); |
AnnaBridge | 171:3a7713b1edbc | 127 | HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); |
AnnaBridge | 171:3a7713b1edbc | 128 | void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); |
AnnaBridge | 171:3a7713b1edbc | 129 | void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); |
AnnaBridge | 171:3a7713b1edbc | 130 | |
AnnaBridge | 171:3a7713b1edbc | 131 | void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); |
AnnaBridge | 171:3a7713b1edbc | 132 | void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); |
AnnaBridge | 171:3a7713b1edbc | 133 | |
AnnaBridge | 171:3a7713b1edbc | 134 | /** |
AnnaBridge | 171:3a7713b1edbc | 135 | * @} |
AnnaBridge | 171:3a7713b1edbc | 136 | */ |
AnnaBridge | 171:3a7713b1edbc | 137 | |
AnnaBridge | 171:3a7713b1edbc | 138 | /** @addtogroup SRAM_Exported_Functions_Group2 |
AnnaBridge | 171:3a7713b1edbc | 139 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 140 | */ |
AnnaBridge | 171:3a7713b1edbc | 141 | |
AnnaBridge | 171:3a7713b1edbc | 142 | /* I/O operation functions *****************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 143 | HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize); |
AnnaBridge | 171:3a7713b1edbc | 144 | HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize); |
AnnaBridge | 171:3a7713b1edbc | 145 | HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize); |
AnnaBridge | 171:3a7713b1edbc | 146 | HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize); |
AnnaBridge | 171:3a7713b1edbc | 147 | HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); |
AnnaBridge | 171:3a7713b1edbc | 148 | HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); |
AnnaBridge | 171:3a7713b1edbc | 149 | HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); |
AnnaBridge | 171:3a7713b1edbc | 150 | HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); |
AnnaBridge | 171:3a7713b1edbc | 151 | |
AnnaBridge | 171:3a7713b1edbc | 152 | /** |
AnnaBridge | 171:3a7713b1edbc | 153 | * @} |
AnnaBridge | 171:3a7713b1edbc | 154 | */ |
AnnaBridge | 171:3a7713b1edbc | 155 | |
AnnaBridge | 171:3a7713b1edbc | 156 | /** @addtogroup SRAM_Exported_Functions_Group3 |
AnnaBridge | 171:3a7713b1edbc | 157 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 158 | */ |
AnnaBridge | 171:3a7713b1edbc | 159 | |
AnnaBridge | 171:3a7713b1edbc | 160 | /* SRAM Control functions ******************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 161 | HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); |
AnnaBridge | 171:3a7713b1edbc | 162 | HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); |
AnnaBridge | 171:3a7713b1edbc | 163 | |
AnnaBridge | 171:3a7713b1edbc | 164 | /** |
AnnaBridge | 171:3a7713b1edbc | 165 | * @} |
AnnaBridge | 171:3a7713b1edbc | 166 | */ |
AnnaBridge | 171:3a7713b1edbc | 167 | |
AnnaBridge | 171:3a7713b1edbc | 168 | /** @addtogroup SRAM_Exported_Functions_Group4 |
AnnaBridge | 171:3a7713b1edbc | 169 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 170 | */ |
AnnaBridge | 171:3a7713b1edbc | 171 | |
AnnaBridge | 171:3a7713b1edbc | 172 | /* SRAM State functions *********************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 173 | HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); |
AnnaBridge | 171:3a7713b1edbc | 174 | |
AnnaBridge | 171:3a7713b1edbc | 175 | /** |
AnnaBridge | 171:3a7713b1edbc | 176 | * @} |
AnnaBridge | 171:3a7713b1edbc | 177 | */ |
AnnaBridge | 171:3a7713b1edbc | 178 | |
AnnaBridge | 171:3a7713b1edbc | 179 | /** |
AnnaBridge | 171:3a7713b1edbc | 180 | * @} |
AnnaBridge | 171:3a7713b1edbc | 181 | */ |
AnnaBridge | 171:3a7713b1edbc | 182 | |
AnnaBridge | 171:3a7713b1edbc | 183 | /** |
AnnaBridge | 171:3a7713b1edbc | 184 | * @} |
AnnaBridge | 171:3a7713b1edbc | 185 | */ |
AnnaBridge | 171:3a7713b1edbc | 186 | |
AnnaBridge | 171:3a7713b1edbc | 187 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
AnnaBridge | 171:3a7713b1edbc | 188 | |
AnnaBridge | 171:3a7713b1edbc | 189 | /** |
AnnaBridge | 171:3a7713b1edbc | 190 | * @} |
AnnaBridge | 171:3a7713b1edbc | 191 | */ |
AnnaBridge | 171:3a7713b1edbc | 192 | |
AnnaBridge | 171:3a7713b1edbc | 193 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 194 | } |
AnnaBridge | 171:3a7713b1edbc | 195 | #endif |
AnnaBridge | 171:3a7713b1edbc | 196 | |
AnnaBridge | 171:3a7713b1edbc | 197 | #endif /* __STM32L1xx_HAL_SRAM_H */ |
AnnaBridge | 171:3a7713b1edbc | 198 | |
AnnaBridge | 171:3a7713b1edbc | 199 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |