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TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l1xx_hal_rcc_ex.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32l1xx_hal_rcc_ex.h |
AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of RCC HAL Extension module. |
AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
AnnaBridge | 171:3a7713b1edbc | 8 | * |
AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
AnnaBridge | 171:3a7713b1edbc | 10 | * |
AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 32 | * |
AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 34 | */ |
AnnaBridge | 171:3a7713b1edbc | 35 | |
AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32L1xx_HAL_RCC_EX_H |
AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32L1xx_HAL_RCC_EX_H |
AnnaBridge | 171:3a7713b1edbc | 39 | |
AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
AnnaBridge | 171:3a7713b1edbc | 43 | |
AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32l1xx_hal_def.h" |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32L1xx_HAL_Driver |
AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 49 | */ |
AnnaBridge | 171:3a7713b1edbc | 50 | |
AnnaBridge | 171:3a7713b1edbc | 51 | /** @addtogroup RCCEx |
AnnaBridge | 171:3a7713b1edbc | 52 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 53 | */ |
AnnaBridge | 171:3a7713b1edbc | 54 | |
AnnaBridge | 171:3a7713b1edbc | 55 | /** @addtogroup RCCEx_Private_Constants |
AnnaBridge | 171:3a7713b1edbc | 56 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 57 | */ |
AnnaBridge | 171:3a7713b1edbc | 58 | |
AnnaBridge | 171:3a7713b1edbc | 59 | #define LSI_VALUE (37000U) /* ~37kHz */ |
AnnaBridge | 171:3a7713b1edbc | 60 | |
AnnaBridge | 171:3a7713b1edbc | 61 | #if defined(STM32L100xBA) || defined(STM32L151xBA) || defined(STM32L152xBA)\ |
AnnaBridge | 171:3a7713b1edbc | 62 | || defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
AnnaBridge | 171:3a7713b1edbc | 63 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
AnnaBridge | 171:3a7713b1edbc | 64 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 65 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 66 | || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 67 | |
AnnaBridge | 171:3a7713b1edbc | 68 | /* Alias word address of LSECSSON bit */ |
AnnaBridge | 171:3a7713b1edbc | 69 | #define LSECSSON_BITNUMBER POSITION_VAL(RCC_CSR_LSECSSON) |
AnnaBridge | 171:3a7713b1edbc | 70 | #define CSR_LSECSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (LSECSSON_BITNUMBER * 4U))) |
AnnaBridge | 171:3a7713b1edbc | 71 | |
AnnaBridge | 171:3a7713b1edbc | 72 | #endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX*/ |
AnnaBridge | 171:3a7713b1edbc | 73 | |
AnnaBridge | 171:3a7713b1edbc | 74 | /** |
AnnaBridge | 171:3a7713b1edbc | 75 | * @} |
AnnaBridge | 171:3a7713b1edbc | 76 | */ |
AnnaBridge | 171:3a7713b1edbc | 77 | |
AnnaBridge | 171:3a7713b1edbc | 78 | /** @addtogroup RCCEx_Private_Macros |
AnnaBridge | 171:3a7713b1edbc | 79 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 80 | */ |
AnnaBridge | 171:3a7713b1edbc | 81 | #if defined(LCD) |
AnnaBridge | 171:3a7713b1edbc | 82 | |
AnnaBridge | 171:3a7713b1edbc | 83 | #define IS_RCC_PERIPHCLOCK(__CLK__) ((RCC_PERIPHCLK_RTC <= (__CLK__)) && ((__CLK__) <= RCC_PERIPHCLK_LCD)) |
AnnaBridge | 171:3a7713b1edbc | 84 | |
AnnaBridge | 171:3a7713b1edbc | 85 | #else /* Not LCD LINE */ |
AnnaBridge | 171:3a7713b1edbc | 86 | |
AnnaBridge | 171:3a7713b1edbc | 87 | #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) == RCC_PERIPHCLK_RTC) |
AnnaBridge | 171:3a7713b1edbc | 88 | |
AnnaBridge | 171:3a7713b1edbc | 89 | #endif /* LCD */ |
AnnaBridge | 171:3a7713b1edbc | 90 | |
AnnaBridge | 171:3a7713b1edbc | 91 | /** |
AnnaBridge | 171:3a7713b1edbc | 92 | * @} |
AnnaBridge | 171:3a7713b1edbc | 93 | */ |
AnnaBridge | 171:3a7713b1edbc | 94 | |
AnnaBridge | 171:3a7713b1edbc | 95 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 96 | |
AnnaBridge | 171:3a7713b1edbc | 97 | /** @defgroup RCCEx_Exported_Types RCCEx Exported Types |
AnnaBridge | 171:3a7713b1edbc | 98 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 99 | */ |
AnnaBridge | 171:3a7713b1edbc | 100 | |
AnnaBridge | 171:3a7713b1edbc | 101 | /** |
AnnaBridge | 171:3a7713b1edbc | 102 | * @brief RCC extended clocks structure definition |
AnnaBridge | 171:3a7713b1edbc | 103 | */ |
AnnaBridge | 171:3a7713b1edbc | 104 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 105 | { |
AnnaBridge | 171:3a7713b1edbc | 106 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
AnnaBridge | 171:3a7713b1edbc | 107 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
AnnaBridge | 171:3a7713b1edbc | 108 | |
AnnaBridge | 171:3a7713b1edbc | 109 | uint32_t RTCClockSelection; /*!< specifies the RTC clock source. |
AnnaBridge | 171:3a7713b1edbc | 110 | This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 111 | |
AnnaBridge | 171:3a7713b1edbc | 112 | #if defined(LCD) |
AnnaBridge | 171:3a7713b1edbc | 113 | |
AnnaBridge | 171:3a7713b1edbc | 114 | uint32_t LCDClockSelection; /*!< specifies the LCD clock source. |
AnnaBridge | 171:3a7713b1edbc | 115 | This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 116 | |
AnnaBridge | 171:3a7713b1edbc | 117 | #endif /* LCD */ |
AnnaBridge | 171:3a7713b1edbc | 118 | } RCC_PeriphCLKInitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 119 | |
AnnaBridge | 171:3a7713b1edbc | 120 | /** |
AnnaBridge | 171:3a7713b1edbc | 121 | * @} |
AnnaBridge | 171:3a7713b1edbc | 122 | */ |
AnnaBridge | 171:3a7713b1edbc | 123 | |
AnnaBridge | 171:3a7713b1edbc | 124 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 125 | |
AnnaBridge | 171:3a7713b1edbc | 126 | /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants |
AnnaBridge | 171:3a7713b1edbc | 127 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 128 | */ |
AnnaBridge | 171:3a7713b1edbc | 129 | |
AnnaBridge | 171:3a7713b1edbc | 130 | /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection |
AnnaBridge | 171:3a7713b1edbc | 131 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 132 | */ |
AnnaBridge | 171:3a7713b1edbc | 133 | #define RCC_PERIPHCLK_RTC (0x00000001U) |
AnnaBridge | 171:3a7713b1edbc | 134 | |
AnnaBridge | 171:3a7713b1edbc | 135 | #if defined(LCD) |
AnnaBridge | 171:3a7713b1edbc | 136 | |
AnnaBridge | 171:3a7713b1edbc | 137 | #define RCC_PERIPHCLK_LCD (0x00000002U) |
AnnaBridge | 171:3a7713b1edbc | 138 | |
AnnaBridge | 171:3a7713b1edbc | 139 | #endif /* LCD */ |
AnnaBridge | 171:3a7713b1edbc | 140 | |
AnnaBridge | 171:3a7713b1edbc | 141 | /** |
AnnaBridge | 171:3a7713b1edbc | 142 | * @} |
AnnaBridge | 171:3a7713b1edbc | 143 | */ |
AnnaBridge | 171:3a7713b1edbc | 144 | |
AnnaBridge | 171:3a7713b1edbc | 145 | #if defined(RCC_LSECSS_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 146 | /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line |
AnnaBridge | 171:3a7713b1edbc | 147 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 148 | */ |
AnnaBridge | 171:3a7713b1edbc | 149 | #define RCC_EXTI_LINE_LSECSS (EXTI_IMR_IM19) /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */ |
AnnaBridge | 171:3a7713b1edbc | 150 | /** |
AnnaBridge | 171:3a7713b1edbc | 151 | * @} |
AnnaBridge | 171:3a7713b1edbc | 152 | */ |
AnnaBridge | 171:3a7713b1edbc | 153 | #endif /* RCC_LSECSS_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 154 | |
AnnaBridge | 171:3a7713b1edbc | 155 | /** |
AnnaBridge | 171:3a7713b1edbc | 156 | * @} |
AnnaBridge | 171:3a7713b1edbc | 157 | */ |
AnnaBridge | 171:3a7713b1edbc | 158 | |
AnnaBridge | 171:3a7713b1edbc | 159 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 160 | /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros |
AnnaBridge | 171:3a7713b1edbc | 161 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 162 | */ |
AnnaBridge | 171:3a7713b1edbc | 163 | |
AnnaBridge | 171:3a7713b1edbc | 164 | /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable |
AnnaBridge | 171:3a7713b1edbc | 165 | * @brief Enables or disables the AHB1 peripheral clock. |
AnnaBridge | 171:3a7713b1edbc | 166 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 171:3a7713b1edbc | 167 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 171:3a7713b1edbc | 168 | * using it. |
AnnaBridge | 171:3a7713b1edbc | 169 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 170 | */ |
AnnaBridge | 171:3a7713b1edbc | 171 | #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ |
AnnaBridge | 171:3a7713b1edbc | 172 | || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ |
AnnaBridge | 171:3a7713b1edbc | 173 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
AnnaBridge | 171:3a7713b1edbc | 174 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 175 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 176 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 177 | |
AnnaBridge | 171:3a7713b1edbc | 178 | #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 179 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 180 | SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ |
AnnaBridge | 171:3a7713b1edbc | 181 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 182 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ |
AnnaBridge | 171:3a7713b1edbc | 183 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 184 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 185 | #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) |
AnnaBridge | 171:3a7713b1edbc | 186 | |
AnnaBridge | 171:3a7713b1edbc | 187 | #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 188 | |
AnnaBridge | 171:3a7713b1edbc | 189 | #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 190 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 191 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 192 | |
AnnaBridge | 171:3a7713b1edbc | 193 | #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 194 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 195 | SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ |
AnnaBridge | 171:3a7713b1edbc | 196 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 197 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ |
AnnaBridge | 171:3a7713b1edbc | 198 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 199 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 200 | #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 201 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 202 | SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\ |
AnnaBridge | 171:3a7713b1edbc | 203 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 204 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\ |
AnnaBridge | 171:3a7713b1edbc | 205 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 206 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 207 | |
AnnaBridge | 171:3a7713b1edbc | 208 | #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) |
AnnaBridge | 171:3a7713b1edbc | 209 | #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN)) |
AnnaBridge | 171:3a7713b1edbc | 210 | |
AnnaBridge | 171:3a7713b1edbc | 211 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 212 | |
AnnaBridge | 171:3a7713b1edbc | 213 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
AnnaBridge | 171:3a7713b1edbc | 214 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
AnnaBridge | 171:3a7713b1edbc | 215 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 216 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 217 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 218 | |
AnnaBridge | 171:3a7713b1edbc | 219 | #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 220 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 221 | SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 222 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 223 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 224 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 225 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 226 | |
AnnaBridge | 171:3a7713b1edbc | 227 | #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) |
AnnaBridge | 171:3a7713b1edbc | 228 | |
AnnaBridge | 171:3a7713b1edbc | 229 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 230 | |
AnnaBridge | 171:3a7713b1edbc | 231 | #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 232 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 233 | |
AnnaBridge | 171:3a7713b1edbc | 234 | #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 235 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 236 | SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\ |
AnnaBridge | 171:3a7713b1edbc | 237 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 238 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\ |
AnnaBridge | 171:3a7713b1edbc | 239 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 240 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 241 | #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_AESEN)) |
AnnaBridge | 171:3a7713b1edbc | 242 | |
AnnaBridge | 171:3a7713b1edbc | 243 | #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 244 | |
AnnaBridge | 171:3a7713b1edbc | 245 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
AnnaBridge | 171:3a7713b1edbc | 246 | |
AnnaBridge | 171:3a7713b1edbc | 247 | #define __HAL_RCC_FSMC_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 248 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 249 | SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ |
AnnaBridge | 171:3a7713b1edbc | 250 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 251 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ |
AnnaBridge | 171:3a7713b1edbc | 252 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 253 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 254 | #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) |
AnnaBridge | 171:3a7713b1edbc | 255 | |
AnnaBridge | 171:3a7713b1edbc | 256 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
AnnaBridge | 171:3a7713b1edbc | 257 | |
AnnaBridge | 171:3a7713b1edbc | 258 | #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ |
AnnaBridge | 171:3a7713b1edbc | 259 | || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ |
AnnaBridge | 171:3a7713b1edbc | 260 | || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ |
AnnaBridge | 171:3a7713b1edbc | 261 | || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 262 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 263 | |
AnnaBridge | 171:3a7713b1edbc | 264 | #define __HAL_RCC_LCD_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 265 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 266 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\ |
AnnaBridge | 171:3a7713b1edbc | 267 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 268 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\ |
AnnaBridge | 171:3a7713b1edbc | 269 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 270 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 271 | #define __HAL_RCC_LCD_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN)) |
AnnaBridge | 171:3a7713b1edbc | 272 | |
AnnaBridge | 171:3a7713b1edbc | 273 | #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 274 | |
AnnaBridge | 171:3a7713b1edbc | 275 | /** @brief Enables or disables the Low Speed APB (APB1) peripheral clock. |
AnnaBridge | 171:3a7713b1edbc | 276 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 171:3a7713b1edbc | 277 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 171:3a7713b1edbc | 278 | * using it. |
AnnaBridge | 171:3a7713b1edbc | 279 | */ |
AnnaBridge | 171:3a7713b1edbc | 280 | #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ |
AnnaBridge | 171:3a7713b1edbc | 281 | || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 282 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 283 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 284 | |
AnnaBridge | 171:3a7713b1edbc | 285 | #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 286 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 287 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ |
AnnaBridge | 171:3a7713b1edbc | 288 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 289 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ |
AnnaBridge | 171:3a7713b1edbc | 290 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 291 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 292 | #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) |
AnnaBridge | 171:3a7713b1edbc | 293 | |
AnnaBridge | 171:3a7713b1edbc | 294 | #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 295 | |
AnnaBridge | 171:3a7713b1edbc | 296 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
AnnaBridge | 171:3a7713b1edbc | 297 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
AnnaBridge | 171:3a7713b1edbc | 298 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 299 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 300 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 301 | |
AnnaBridge | 171:3a7713b1edbc | 302 | #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 303 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 304 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ |
AnnaBridge | 171:3a7713b1edbc | 305 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 306 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ |
AnnaBridge | 171:3a7713b1edbc | 307 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 308 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 309 | #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) |
AnnaBridge | 171:3a7713b1edbc | 310 | |
AnnaBridge | 171:3a7713b1edbc | 311 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 312 | |
AnnaBridge | 171:3a7713b1edbc | 313 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 314 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 315 | |
AnnaBridge | 171:3a7713b1edbc | 316 | #define __HAL_RCC_UART4_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 317 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 318 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ |
AnnaBridge | 171:3a7713b1edbc | 319 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 320 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ |
AnnaBridge | 171:3a7713b1edbc | 321 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 322 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 323 | #define __HAL_RCC_UART5_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 324 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 325 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ |
AnnaBridge | 171:3a7713b1edbc | 326 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 327 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ |
AnnaBridge | 171:3a7713b1edbc | 328 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 329 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 330 | |
AnnaBridge | 171:3a7713b1edbc | 331 | #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) |
AnnaBridge | 171:3a7713b1edbc | 332 | #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) |
AnnaBridge | 171:3a7713b1edbc | 333 | |
AnnaBridge | 171:3a7713b1edbc | 334 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD || (...) || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 335 | |
AnnaBridge | 171:3a7713b1edbc | 336 | #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 337 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 338 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE)\ |
AnnaBridge | 171:3a7713b1edbc | 339 | || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 340 | || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) |
AnnaBridge | 171:3a7713b1edbc | 341 | |
AnnaBridge | 171:3a7713b1edbc | 342 | #define __HAL_RCC_OPAMP_CLK_ENABLE() __HAL_RCC_COMP_CLK_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */ |
AnnaBridge | 171:3a7713b1edbc | 343 | #define __HAL_RCC_OPAMP_CLK_DISABLE() __HAL_RCC_COMP_CLK_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */ |
AnnaBridge | 171:3a7713b1edbc | 344 | |
AnnaBridge | 171:3a7713b1edbc | 345 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || (...) || STM32L162xC || STM32L152xC || STM32L151xC */ |
AnnaBridge | 171:3a7713b1edbc | 346 | |
AnnaBridge | 171:3a7713b1edbc | 347 | /** @brief Enables or disables the High Speed APB (APB2) peripheral clock. |
AnnaBridge | 171:3a7713b1edbc | 348 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 171:3a7713b1edbc | 349 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 171:3a7713b1edbc | 350 | * using it. |
AnnaBridge | 171:3a7713b1edbc | 351 | */ |
AnnaBridge | 171:3a7713b1edbc | 352 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
AnnaBridge | 171:3a7713b1edbc | 353 | |
AnnaBridge | 171:3a7713b1edbc | 354 | #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 355 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 356 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ |
AnnaBridge | 171:3a7713b1edbc | 357 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 358 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ |
AnnaBridge | 171:3a7713b1edbc | 359 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 360 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 361 | #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) |
AnnaBridge | 171:3a7713b1edbc | 362 | |
AnnaBridge | 171:3a7713b1edbc | 363 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
AnnaBridge | 171:3a7713b1edbc | 364 | |
AnnaBridge | 171:3a7713b1edbc | 365 | /** |
AnnaBridge | 171:3a7713b1edbc | 366 | * @} |
AnnaBridge | 171:3a7713b1edbc | 367 | */ |
AnnaBridge | 171:3a7713b1edbc | 368 | |
AnnaBridge | 171:3a7713b1edbc | 369 | |
AnnaBridge | 171:3a7713b1edbc | 370 | /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset |
AnnaBridge | 171:3a7713b1edbc | 371 | * @brief Forces or releases AHB peripheral reset. |
AnnaBridge | 171:3a7713b1edbc | 372 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 373 | */ |
AnnaBridge | 171:3a7713b1edbc | 374 | #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ |
AnnaBridge | 171:3a7713b1edbc | 375 | || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ |
AnnaBridge | 171:3a7713b1edbc | 376 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
AnnaBridge | 171:3a7713b1edbc | 377 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 378 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 379 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 380 | |
AnnaBridge | 171:3a7713b1edbc | 381 | #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) |
AnnaBridge | 171:3a7713b1edbc | 382 | #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) |
AnnaBridge | 171:3a7713b1edbc | 383 | |
AnnaBridge | 171:3a7713b1edbc | 384 | #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 385 | |
AnnaBridge | 171:3a7713b1edbc | 386 | #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 387 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 388 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 389 | |
AnnaBridge | 171:3a7713b1edbc | 390 | #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) |
AnnaBridge | 171:3a7713b1edbc | 391 | #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST)) |
AnnaBridge | 171:3a7713b1edbc | 392 | |
AnnaBridge | 171:3a7713b1edbc | 393 | #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) |
AnnaBridge | 171:3a7713b1edbc | 394 | #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST)) |
AnnaBridge | 171:3a7713b1edbc | 395 | |
AnnaBridge | 171:3a7713b1edbc | 396 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 397 | |
AnnaBridge | 171:3a7713b1edbc | 398 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
AnnaBridge | 171:3a7713b1edbc | 399 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
AnnaBridge | 171:3a7713b1edbc | 400 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 401 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 402 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 403 | |
AnnaBridge | 171:3a7713b1edbc | 404 | #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA2RST)) |
AnnaBridge | 171:3a7713b1edbc | 405 | #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA2RST)) |
AnnaBridge | 171:3a7713b1edbc | 406 | |
AnnaBridge | 171:3a7713b1edbc | 407 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 408 | |
AnnaBridge | 171:3a7713b1edbc | 409 | #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 410 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 411 | |
AnnaBridge | 171:3a7713b1edbc | 412 | #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_AESRST)) |
AnnaBridge | 171:3a7713b1edbc | 413 | #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_AESRST)) |
AnnaBridge | 171:3a7713b1edbc | 414 | |
AnnaBridge | 171:3a7713b1edbc | 415 | #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 416 | |
AnnaBridge | 171:3a7713b1edbc | 417 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
AnnaBridge | 171:3a7713b1edbc | 418 | |
AnnaBridge | 171:3a7713b1edbc | 419 | #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FSMCRST)) |
AnnaBridge | 171:3a7713b1edbc | 420 | #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FSMCRST)) |
AnnaBridge | 171:3a7713b1edbc | 421 | |
AnnaBridge | 171:3a7713b1edbc | 422 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
AnnaBridge | 171:3a7713b1edbc | 423 | |
AnnaBridge | 171:3a7713b1edbc | 424 | #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ |
AnnaBridge | 171:3a7713b1edbc | 425 | || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ |
AnnaBridge | 171:3a7713b1edbc | 426 | || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ |
AnnaBridge | 171:3a7713b1edbc | 427 | || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 428 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 429 | |
AnnaBridge | 171:3a7713b1edbc | 430 | #define __HAL_RCC_LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST)) |
AnnaBridge | 171:3a7713b1edbc | 431 | #define __HAL_RCC_LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LCDRST)) |
AnnaBridge | 171:3a7713b1edbc | 432 | |
AnnaBridge | 171:3a7713b1edbc | 433 | #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 434 | |
AnnaBridge | 171:3a7713b1edbc | 435 | /** @brief Forces or releases APB1 peripheral reset. |
AnnaBridge | 171:3a7713b1edbc | 436 | */ |
AnnaBridge | 171:3a7713b1edbc | 437 | #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ |
AnnaBridge | 171:3a7713b1edbc | 438 | || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 439 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 440 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 441 | |
AnnaBridge | 171:3a7713b1edbc | 442 | #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) |
AnnaBridge | 171:3a7713b1edbc | 443 | #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) |
AnnaBridge | 171:3a7713b1edbc | 444 | |
AnnaBridge | 171:3a7713b1edbc | 445 | #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 446 | |
AnnaBridge | 171:3a7713b1edbc | 447 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
AnnaBridge | 171:3a7713b1edbc | 448 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
AnnaBridge | 171:3a7713b1edbc | 449 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 450 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 451 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 452 | |
AnnaBridge | 171:3a7713b1edbc | 453 | #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) |
AnnaBridge | 171:3a7713b1edbc | 454 | #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) |
AnnaBridge | 171:3a7713b1edbc | 455 | |
AnnaBridge | 171:3a7713b1edbc | 456 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 457 | |
AnnaBridge | 171:3a7713b1edbc | 458 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 459 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 460 | |
AnnaBridge | 171:3a7713b1edbc | 461 | #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) |
AnnaBridge | 171:3a7713b1edbc | 462 | #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) |
AnnaBridge | 171:3a7713b1edbc | 463 | |
AnnaBridge | 171:3a7713b1edbc | 464 | #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) |
AnnaBridge | 171:3a7713b1edbc | 465 | #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) |
AnnaBridge | 171:3a7713b1edbc | 466 | |
AnnaBridge | 171:3a7713b1edbc | 467 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 468 | |
AnnaBridge | 171:3a7713b1edbc | 469 | #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 470 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 471 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 472 | || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) |
AnnaBridge | 171:3a7713b1edbc | 473 | |
AnnaBridge | 171:3a7713b1edbc | 474 | #define __HAL_RCC_OPAMP_FORCE_RESET() __HAL_RCC_COMP_FORCE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */ |
AnnaBridge | 171:3a7713b1edbc | 475 | #define __HAL_RCC_OPAMP_RELEASE_RESET() __HAL_RCC_COMP_RELEASE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */ |
AnnaBridge | 171:3a7713b1edbc | 476 | |
AnnaBridge | 171:3a7713b1edbc | 477 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ |
AnnaBridge | 171:3a7713b1edbc | 478 | |
AnnaBridge | 171:3a7713b1edbc | 479 | /** @brief Forces or releases APB2 peripheral reset. |
AnnaBridge | 171:3a7713b1edbc | 480 | */ |
AnnaBridge | 171:3a7713b1edbc | 481 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
AnnaBridge | 171:3a7713b1edbc | 482 | |
AnnaBridge | 171:3a7713b1edbc | 483 | #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) |
AnnaBridge | 171:3a7713b1edbc | 484 | #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) |
AnnaBridge | 171:3a7713b1edbc | 485 | |
AnnaBridge | 171:3a7713b1edbc | 486 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
AnnaBridge | 171:3a7713b1edbc | 487 | |
AnnaBridge | 171:3a7713b1edbc | 488 | /** |
AnnaBridge | 171:3a7713b1edbc | 489 | * @} |
AnnaBridge | 171:3a7713b1edbc | 490 | */ |
AnnaBridge | 171:3a7713b1edbc | 491 | |
AnnaBridge | 171:3a7713b1edbc | 492 | /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable |
AnnaBridge | 171:3a7713b1edbc | 493 | * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. |
AnnaBridge | 171:3a7713b1edbc | 494 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 171:3a7713b1edbc | 495 | * power consumption. |
AnnaBridge | 171:3a7713b1edbc | 496 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 171:3a7713b1edbc | 497 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 171:3a7713b1edbc | 498 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 499 | */ |
AnnaBridge | 171:3a7713b1edbc | 500 | #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ |
AnnaBridge | 171:3a7713b1edbc | 501 | || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ |
AnnaBridge | 171:3a7713b1edbc | 502 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
AnnaBridge | 171:3a7713b1edbc | 503 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 504 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 505 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 506 | |
AnnaBridge | 171:3a7713b1edbc | 507 | #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOELPEN)) |
AnnaBridge | 171:3a7713b1edbc | 508 | #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOELPEN)) |
AnnaBridge | 171:3a7713b1edbc | 509 | |
AnnaBridge | 171:3a7713b1edbc | 510 | #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 511 | |
AnnaBridge | 171:3a7713b1edbc | 512 | #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 513 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 514 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 515 | |
AnnaBridge | 171:3a7713b1edbc | 516 | #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOFLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 517 | #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOGLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 518 | |
AnnaBridge | 171:3a7713b1edbc | 519 | #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOFLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 520 | #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOGLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 521 | |
AnnaBridge | 171:3a7713b1edbc | 522 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 523 | |
AnnaBridge | 171:3a7713b1edbc | 524 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
AnnaBridge | 171:3a7713b1edbc | 525 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
AnnaBridge | 171:3a7713b1edbc | 526 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 527 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 528 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 529 | |
AnnaBridge | 171:3a7713b1edbc | 530 | #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA2LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 531 | #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA2LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 532 | |
AnnaBridge | 171:3a7713b1edbc | 533 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 534 | |
AnnaBridge | 171:3a7713b1edbc | 535 | #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 536 | |
AnnaBridge | 171:3a7713b1edbc | 537 | #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_AESLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 538 | #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_AESLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 539 | |
AnnaBridge | 171:3a7713b1edbc | 540 | #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 541 | |
AnnaBridge | 171:3a7713b1edbc | 542 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
AnnaBridge | 171:3a7713b1edbc | 543 | |
AnnaBridge | 171:3a7713b1edbc | 544 | #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FSMCLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 545 | #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FSMCLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 546 | |
AnnaBridge | 171:3a7713b1edbc | 547 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
AnnaBridge | 171:3a7713b1edbc | 548 | |
AnnaBridge | 171:3a7713b1edbc | 549 | #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ |
AnnaBridge | 171:3a7713b1edbc | 550 | || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ |
AnnaBridge | 171:3a7713b1edbc | 551 | || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ |
AnnaBridge | 171:3a7713b1edbc | 552 | || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 553 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 554 | |
AnnaBridge | 171:3a7713b1edbc | 555 | #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LCDLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 556 | #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LCDLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 557 | |
AnnaBridge | 171:3a7713b1edbc | 558 | #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 559 | |
AnnaBridge | 171:3a7713b1edbc | 560 | /** @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. |
AnnaBridge | 171:3a7713b1edbc | 561 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 171:3a7713b1edbc | 562 | * power consumption. |
AnnaBridge | 171:3a7713b1edbc | 563 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 171:3a7713b1edbc | 564 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 171:3a7713b1edbc | 565 | */ |
AnnaBridge | 171:3a7713b1edbc | 566 | #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ |
AnnaBridge | 171:3a7713b1edbc | 567 | || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 568 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 569 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 570 | |
AnnaBridge | 171:3a7713b1edbc | 571 | #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 572 | #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 573 | |
AnnaBridge | 171:3a7713b1edbc | 574 | #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 575 | |
AnnaBridge | 171:3a7713b1edbc | 576 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
AnnaBridge | 171:3a7713b1edbc | 577 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
AnnaBridge | 171:3a7713b1edbc | 578 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 579 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 580 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 581 | |
AnnaBridge | 171:3a7713b1edbc | 582 | #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 583 | #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 584 | |
AnnaBridge | 171:3a7713b1edbc | 585 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 586 | |
AnnaBridge | 171:3a7713b1edbc | 587 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 588 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 589 | |
AnnaBridge | 171:3a7713b1edbc | 590 | #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 591 | #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 592 | |
AnnaBridge | 171:3a7713b1edbc | 593 | #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 594 | #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 595 | |
AnnaBridge | 171:3a7713b1edbc | 596 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 597 | |
AnnaBridge | 171:3a7713b1edbc | 598 | #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 599 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 600 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 601 | || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) |
AnnaBridge | 171:3a7713b1edbc | 602 | |
AnnaBridge | 171:3a7713b1edbc | 603 | #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() __HAL_RCC_COMP_CLK_SLEEP_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */ |
AnnaBridge | 171:3a7713b1edbc | 604 | #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() __HAL_RCC_COMP_CLK_SLEEP_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */ |
AnnaBridge | 171:3a7713b1edbc | 605 | |
AnnaBridge | 171:3a7713b1edbc | 606 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ |
AnnaBridge | 171:3a7713b1edbc | 607 | |
AnnaBridge | 171:3a7713b1edbc | 608 | /** @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. |
AnnaBridge | 171:3a7713b1edbc | 609 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 171:3a7713b1edbc | 610 | * power consumption. |
AnnaBridge | 171:3a7713b1edbc | 611 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 171:3a7713b1edbc | 612 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 171:3a7713b1edbc | 613 | */ |
AnnaBridge | 171:3a7713b1edbc | 614 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
AnnaBridge | 171:3a7713b1edbc | 615 | |
AnnaBridge | 171:3a7713b1edbc | 616 | #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 617 | #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 618 | |
AnnaBridge | 171:3a7713b1edbc | 619 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
AnnaBridge | 171:3a7713b1edbc | 620 | |
AnnaBridge | 171:3a7713b1edbc | 621 | /** |
AnnaBridge | 171:3a7713b1edbc | 622 | * @} |
AnnaBridge | 171:3a7713b1edbc | 623 | */ |
AnnaBridge | 171:3a7713b1edbc | 624 | |
AnnaBridge | 171:3a7713b1edbc | 625 | /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status |
AnnaBridge | 171:3a7713b1edbc | 626 | * @brief Get the enable or disable status of peripheral clock. |
AnnaBridge | 171:3a7713b1edbc | 627 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 171:3a7713b1edbc | 628 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 171:3a7713b1edbc | 629 | * using it. |
AnnaBridge | 171:3a7713b1edbc | 630 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 631 | */ |
AnnaBridge | 171:3a7713b1edbc | 632 | |
AnnaBridge | 171:3a7713b1edbc | 633 | #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ |
AnnaBridge | 171:3a7713b1edbc | 634 | || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ |
AnnaBridge | 171:3a7713b1edbc | 635 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
AnnaBridge | 171:3a7713b1edbc | 636 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 637 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 638 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 639 | |
AnnaBridge | 171:3a7713b1edbc | 640 | #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 641 | #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 642 | |
AnnaBridge | 171:3a7713b1edbc | 643 | #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 644 | |
AnnaBridge | 171:3a7713b1edbc | 645 | #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 646 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 647 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 648 | |
AnnaBridge | 171:3a7713b1edbc | 649 | #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 650 | #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 651 | #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 652 | #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 653 | |
AnnaBridge | 171:3a7713b1edbc | 654 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 655 | |
AnnaBridge | 171:3a7713b1edbc | 656 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
AnnaBridge | 171:3a7713b1edbc | 657 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
AnnaBridge | 171:3a7713b1edbc | 658 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 659 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 660 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 661 | |
AnnaBridge | 171:3a7713b1edbc | 662 | #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 663 | #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 664 | |
AnnaBridge | 171:3a7713b1edbc | 665 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 666 | |
AnnaBridge | 171:3a7713b1edbc | 667 | #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 668 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 669 | |
AnnaBridge | 171:3a7713b1edbc | 670 | #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_AESEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 671 | #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_AESEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 672 | |
AnnaBridge | 171:3a7713b1edbc | 673 | #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 674 | |
AnnaBridge | 171:3a7713b1edbc | 675 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
AnnaBridge | 171:3a7713b1edbc | 676 | |
AnnaBridge | 171:3a7713b1edbc | 677 | #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 678 | #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 679 | |
AnnaBridge | 171:3a7713b1edbc | 680 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
AnnaBridge | 171:3a7713b1edbc | 681 | |
AnnaBridge | 171:3a7713b1edbc | 682 | #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ |
AnnaBridge | 171:3a7713b1edbc | 683 | || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ |
AnnaBridge | 171:3a7713b1edbc | 684 | || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ |
AnnaBridge | 171:3a7713b1edbc | 685 | || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 686 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 687 | |
AnnaBridge | 171:3a7713b1edbc | 688 | #define __HAL_RCC_LCD_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 689 | #define __HAL_RCC_LCD_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 690 | |
AnnaBridge | 171:3a7713b1edbc | 691 | #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 692 | |
AnnaBridge | 171:3a7713b1edbc | 693 | #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ |
AnnaBridge | 171:3a7713b1edbc | 694 | || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 695 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 696 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 697 | |
AnnaBridge | 171:3a7713b1edbc | 698 | #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 699 | #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 700 | |
AnnaBridge | 171:3a7713b1edbc | 701 | #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 702 | |
AnnaBridge | 171:3a7713b1edbc | 703 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
AnnaBridge | 171:3a7713b1edbc | 704 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
AnnaBridge | 171:3a7713b1edbc | 705 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 706 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 707 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 708 | |
AnnaBridge | 171:3a7713b1edbc | 709 | #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 710 | #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 711 | |
AnnaBridge | 171:3a7713b1edbc | 712 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 713 | |
AnnaBridge | 171:3a7713b1edbc | 714 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 715 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 716 | |
AnnaBridge | 171:3a7713b1edbc | 717 | #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 718 | #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 719 | #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 720 | #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 721 | |
AnnaBridge | 171:3a7713b1edbc | 722 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 723 | |
AnnaBridge | 171:3a7713b1edbc | 724 | #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 725 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 726 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 727 | || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) |
AnnaBridge | 171:3a7713b1edbc | 728 | |
AnnaBridge | 171:3a7713b1edbc | 729 | #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() __HAL_RCC_COMP_IS_CLK_ENABLED() |
AnnaBridge | 171:3a7713b1edbc | 730 | #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() __HAL_RCC_COMP_IS_CLK_DISABLED() |
AnnaBridge | 171:3a7713b1edbc | 731 | |
AnnaBridge | 171:3a7713b1edbc | 732 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ |
AnnaBridge | 171:3a7713b1edbc | 733 | |
AnnaBridge | 171:3a7713b1edbc | 734 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
AnnaBridge | 171:3a7713b1edbc | 735 | |
AnnaBridge | 171:3a7713b1edbc | 736 | #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 737 | #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 738 | |
AnnaBridge | 171:3a7713b1edbc | 739 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
AnnaBridge | 171:3a7713b1edbc | 740 | |
AnnaBridge | 171:3a7713b1edbc | 741 | /** |
AnnaBridge | 171:3a7713b1edbc | 742 | * @} |
AnnaBridge | 171:3a7713b1edbc | 743 | */ |
AnnaBridge | 171:3a7713b1edbc | 744 | |
AnnaBridge | 171:3a7713b1edbc | 745 | /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable_Status Peripheral Clock Sleep Enable Disable Status |
AnnaBridge | 171:3a7713b1edbc | 746 | * @brief Get the enable or disable status of peripheral clock during Low Power (Sleep) mode. |
AnnaBridge | 171:3a7713b1edbc | 747 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 171:3a7713b1edbc | 748 | * power consumption. |
AnnaBridge | 171:3a7713b1edbc | 749 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 171:3a7713b1edbc | 750 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 171:3a7713b1edbc | 751 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 752 | */ |
AnnaBridge | 171:3a7713b1edbc | 753 | |
AnnaBridge | 171:3a7713b1edbc | 754 | #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ |
AnnaBridge | 171:3a7713b1edbc | 755 | || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ |
AnnaBridge | 171:3a7713b1edbc | 756 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
AnnaBridge | 171:3a7713b1edbc | 757 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 758 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 759 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 760 | |
AnnaBridge | 171:3a7713b1edbc | 761 | #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 762 | #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 763 | |
AnnaBridge | 171:3a7713b1edbc | 764 | #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 765 | |
AnnaBridge | 171:3a7713b1edbc | 766 | #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 767 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 768 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 769 | |
AnnaBridge | 171:3a7713b1edbc | 770 | #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 771 | #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 772 | #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 773 | #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 774 | |
AnnaBridge | 171:3a7713b1edbc | 775 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 776 | |
AnnaBridge | 171:3a7713b1edbc | 777 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
AnnaBridge | 171:3a7713b1edbc | 778 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
AnnaBridge | 171:3a7713b1edbc | 779 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 780 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 781 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 782 | |
AnnaBridge | 171:3a7713b1edbc | 783 | #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 784 | #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 785 | |
AnnaBridge | 171:3a7713b1edbc | 786 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 787 | |
AnnaBridge | 171:3a7713b1edbc | 788 | #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 789 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 790 | |
AnnaBridge | 171:3a7713b1edbc | 791 | #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 792 | #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 793 | |
AnnaBridge | 171:3a7713b1edbc | 794 | #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 795 | |
AnnaBridge | 171:3a7713b1edbc | 796 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
AnnaBridge | 171:3a7713b1edbc | 797 | |
AnnaBridge | 171:3a7713b1edbc | 798 | #define __HAL_RCC_FSMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 799 | #define __HAL_RCC_FSMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 800 | |
AnnaBridge | 171:3a7713b1edbc | 801 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
AnnaBridge | 171:3a7713b1edbc | 802 | |
AnnaBridge | 171:3a7713b1edbc | 803 | #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ |
AnnaBridge | 171:3a7713b1edbc | 804 | || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ |
AnnaBridge | 171:3a7713b1edbc | 805 | || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ |
AnnaBridge | 171:3a7713b1edbc | 806 | || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 807 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 808 | |
AnnaBridge | 171:3a7713b1edbc | 809 | #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 810 | #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 811 | |
AnnaBridge | 171:3a7713b1edbc | 812 | #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 813 | |
AnnaBridge | 171:3a7713b1edbc | 814 | #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ |
AnnaBridge | 171:3a7713b1edbc | 815 | || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 816 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 817 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 818 | |
AnnaBridge | 171:3a7713b1edbc | 819 | #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 820 | #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 821 | |
AnnaBridge | 171:3a7713b1edbc | 822 | #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 823 | |
AnnaBridge | 171:3a7713b1edbc | 824 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
AnnaBridge | 171:3a7713b1edbc | 825 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
AnnaBridge | 171:3a7713b1edbc | 826 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 827 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 828 | || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 829 | |
AnnaBridge | 171:3a7713b1edbc | 830 | #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 831 | #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 832 | |
AnnaBridge | 171:3a7713b1edbc | 833 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 834 | |
AnnaBridge | 171:3a7713b1edbc | 835 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 836 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
AnnaBridge | 171:3a7713b1edbc | 837 | |
AnnaBridge | 171:3a7713b1edbc | 838 | #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 839 | #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 840 | #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 841 | #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 842 | |
AnnaBridge | 171:3a7713b1edbc | 843 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
AnnaBridge | 171:3a7713b1edbc | 844 | |
AnnaBridge | 171:3a7713b1edbc | 845 | #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
AnnaBridge | 171:3a7713b1edbc | 846 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
AnnaBridge | 171:3a7713b1edbc | 847 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ |
AnnaBridge | 171:3a7713b1edbc | 848 | || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) |
AnnaBridge | 171:3a7713b1edbc | 849 | |
AnnaBridge | 171:3a7713b1edbc | 850 | #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED() |
AnnaBridge | 171:3a7713b1edbc | 851 | #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED() |
AnnaBridge | 171:3a7713b1edbc | 852 | |
AnnaBridge | 171:3a7713b1edbc | 853 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ |
AnnaBridge | 171:3a7713b1edbc | 854 | |
AnnaBridge | 171:3a7713b1edbc | 855 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
AnnaBridge | 171:3a7713b1edbc | 856 | |
AnnaBridge | 171:3a7713b1edbc | 857 | #define __HAL_RCC_SDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 858 | #define __HAL_RCC_SDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 859 | |
AnnaBridge | 171:3a7713b1edbc | 860 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
AnnaBridge | 171:3a7713b1edbc | 861 | |
AnnaBridge | 171:3a7713b1edbc | 862 | /** |
AnnaBridge | 171:3a7713b1edbc | 863 | * @} |
AnnaBridge | 171:3a7713b1edbc | 864 | */ |
AnnaBridge | 171:3a7713b1edbc | 865 | |
AnnaBridge | 171:3a7713b1edbc | 866 | |
AnnaBridge | 171:3a7713b1edbc | 867 | #if defined(RCC_LSECSS_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 868 | |
AnnaBridge | 171:3a7713b1edbc | 869 | /** |
AnnaBridge | 171:3a7713b1edbc | 870 | * @brief Enable interrupt on RCC LSE CSS EXTI Line 19. |
AnnaBridge | 171:3a7713b1edbc | 871 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 872 | */ |
AnnaBridge | 171:3a7713b1edbc | 873 | #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS) |
AnnaBridge | 171:3a7713b1edbc | 874 | |
AnnaBridge | 171:3a7713b1edbc | 875 | /** |
AnnaBridge | 171:3a7713b1edbc | 876 | * @brief Disable interrupt on RCC LSE CSS EXTI Line 19. |
AnnaBridge | 171:3a7713b1edbc | 877 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 878 | */ |
AnnaBridge | 171:3a7713b1edbc | 879 | #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS) |
AnnaBridge | 171:3a7713b1edbc | 880 | |
AnnaBridge | 171:3a7713b1edbc | 881 | /** |
AnnaBridge | 171:3a7713b1edbc | 882 | * @brief Enable event on RCC LSE CSS EXTI Line 19. |
AnnaBridge | 171:3a7713b1edbc | 883 | * @retval None. |
AnnaBridge | 171:3a7713b1edbc | 884 | */ |
AnnaBridge | 171:3a7713b1edbc | 885 | #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS) |
AnnaBridge | 171:3a7713b1edbc | 886 | |
AnnaBridge | 171:3a7713b1edbc | 887 | /** |
AnnaBridge | 171:3a7713b1edbc | 888 | * @brief Disable event on RCC LSE CSS EXTI Line 19. |
AnnaBridge | 171:3a7713b1edbc | 889 | * @retval None. |
AnnaBridge | 171:3a7713b1edbc | 890 | */ |
AnnaBridge | 171:3a7713b1edbc | 891 | #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS) |
AnnaBridge | 171:3a7713b1edbc | 892 | |
AnnaBridge | 171:3a7713b1edbc | 893 | |
AnnaBridge | 171:3a7713b1edbc | 894 | /** |
AnnaBridge | 171:3a7713b1edbc | 895 | * @brief RCC LSE CSS EXTI line configuration: set falling edge trigger. |
AnnaBridge | 171:3a7713b1edbc | 896 | * @retval None. |
AnnaBridge | 171:3a7713b1edbc | 897 | */ |
AnnaBridge | 171:3a7713b1edbc | 898 | #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS) |
AnnaBridge | 171:3a7713b1edbc | 899 | |
AnnaBridge | 171:3a7713b1edbc | 900 | |
AnnaBridge | 171:3a7713b1edbc | 901 | /** |
AnnaBridge | 171:3a7713b1edbc | 902 | * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. |
AnnaBridge | 171:3a7713b1edbc | 903 | * @retval None. |
AnnaBridge | 171:3a7713b1edbc | 904 | */ |
AnnaBridge | 171:3a7713b1edbc | 905 | #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS) |
AnnaBridge | 171:3a7713b1edbc | 906 | |
AnnaBridge | 171:3a7713b1edbc | 907 | |
AnnaBridge | 171:3a7713b1edbc | 908 | /** |
AnnaBridge | 171:3a7713b1edbc | 909 | * @brief RCC LSE CSS EXTI line configuration: set rising edge trigger. |
AnnaBridge | 171:3a7713b1edbc | 910 | * @retval None. |
AnnaBridge | 171:3a7713b1edbc | 911 | */ |
AnnaBridge | 171:3a7713b1edbc | 912 | #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS) |
AnnaBridge | 171:3a7713b1edbc | 913 | |
AnnaBridge | 171:3a7713b1edbc | 914 | /** |
AnnaBridge | 171:3a7713b1edbc | 915 | * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. |
AnnaBridge | 171:3a7713b1edbc | 916 | * @retval None. |
AnnaBridge | 171:3a7713b1edbc | 917 | */ |
AnnaBridge | 171:3a7713b1edbc | 918 | #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS) |
AnnaBridge | 171:3a7713b1edbc | 919 | |
AnnaBridge | 171:3a7713b1edbc | 920 | /** |
AnnaBridge | 171:3a7713b1edbc | 921 | * @brief RCC LSE CSS EXTI line configuration: set rising & falling edge trigger. |
AnnaBridge | 171:3a7713b1edbc | 922 | * @retval None. |
AnnaBridge | 171:3a7713b1edbc | 923 | */ |
AnnaBridge | 171:3a7713b1edbc | 924 | #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ |
AnnaBridge | 171:3a7713b1edbc | 925 | do { \ |
AnnaBridge | 171:3a7713b1edbc | 926 | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ |
AnnaBridge | 171:3a7713b1edbc | 927 | __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ |
AnnaBridge | 171:3a7713b1edbc | 928 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 929 | |
AnnaBridge | 171:3a7713b1edbc | 930 | /** |
AnnaBridge | 171:3a7713b1edbc | 931 | * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. |
AnnaBridge | 171:3a7713b1edbc | 932 | * @retval None. |
AnnaBridge | 171:3a7713b1edbc | 933 | */ |
AnnaBridge | 171:3a7713b1edbc | 934 | #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ |
AnnaBridge | 171:3a7713b1edbc | 935 | do { \ |
AnnaBridge | 171:3a7713b1edbc | 936 | __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ |
AnnaBridge | 171:3a7713b1edbc | 937 | __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ |
AnnaBridge | 171:3a7713b1edbc | 938 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 939 | |
AnnaBridge | 171:3a7713b1edbc | 940 | /** |
AnnaBridge | 171:3a7713b1edbc | 941 | * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. |
AnnaBridge | 171:3a7713b1edbc | 942 | * @retval EXTI RCC LSE CSS Line Status. |
AnnaBridge | 171:3a7713b1edbc | 943 | */ |
AnnaBridge | 171:3a7713b1edbc | 944 | #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (EXTI->PR & (RCC_EXTI_LINE_LSECSS)) |
AnnaBridge | 171:3a7713b1edbc | 945 | |
AnnaBridge | 171:3a7713b1edbc | 946 | /** |
AnnaBridge | 171:3a7713b1edbc | 947 | * @brief Clear the RCC LSE CSS EXTI flag. |
AnnaBridge | 171:3a7713b1edbc | 948 | * @retval None. |
AnnaBridge | 171:3a7713b1edbc | 949 | */ |
AnnaBridge | 171:3a7713b1edbc | 950 | #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() (EXTI->PR = (RCC_EXTI_LINE_LSECSS)) |
AnnaBridge | 171:3a7713b1edbc | 951 | |
AnnaBridge | 171:3a7713b1edbc | 952 | /** |
AnnaBridge | 171:3a7713b1edbc | 953 | * @brief Generate a Software interrupt on selected EXTI line. |
AnnaBridge | 171:3a7713b1edbc | 954 | * @retval None. |
AnnaBridge | 171:3a7713b1edbc | 955 | */ |
AnnaBridge | 171:3a7713b1edbc | 956 | #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS) |
AnnaBridge | 171:3a7713b1edbc | 957 | |
AnnaBridge | 171:3a7713b1edbc | 958 | #endif /* RCC_LSECSS_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 959 | |
AnnaBridge | 171:3a7713b1edbc | 960 | #if defined(LCD) |
AnnaBridge | 171:3a7713b1edbc | 961 | |
AnnaBridge | 171:3a7713b1edbc | 962 | /** @defgroup RCCEx_LCD_Configuration LCD Configuration |
AnnaBridge | 171:3a7713b1edbc | 963 | * @brief Macros to configure clock source of LCD peripherals. |
AnnaBridge | 171:3a7713b1edbc | 964 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 965 | */ |
AnnaBridge | 171:3a7713b1edbc | 966 | |
AnnaBridge | 171:3a7713b1edbc | 967 | /** @brief Macro to configures LCD clock (LCDCLK). |
AnnaBridge | 171:3a7713b1edbc | 968 | * @note LCD and RTC use the same configuration |
AnnaBridge | 171:3a7713b1edbc | 969 | * @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the |
AnnaBridge | 171:3a7713b1edbc | 970 | * LCD clock source. |
AnnaBridge | 171:3a7713b1edbc | 971 | * |
AnnaBridge | 171:3a7713b1edbc | 972 | * @param __LCD_CLKSOURCE__ specifies the LCD clock source. |
AnnaBridge | 171:3a7713b1edbc | 973 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 974 | * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock |
AnnaBridge | 171:3a7713b1edbc | 975 | * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock |
AnnaBridge | 171:3a7713b1edbc | 976 | * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock |
AnnaBridge | 171:3a7713b1edbc | 977 | * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as LCD clock |
AnnaBridge | 171:3a7713b1edbc | 978 | * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as LCD clock |
AnnaBridge | 171:3a7713b1edbc | 979 | * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as LCD clock |
AnnaBridge | 171:3a7713b1edbc | 980 | */ |
AnnaBridge | 171:3a7713b1edbc | 981 | #define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__) |
AnnaBridge | 171:3a7713b1edbc | 982 | |
AnnaBridge | 171:3a7713b1edbc | 983 | /** @brief Macro to get the LCD clock source. |
AnnaBridge | 171:3a7713b1edbc | 984 | */ |
AnnaBridge | 171:3a7713b1edbc | 985 | #define __HAL_RCC_GET_LCD_SOURCE() __HAL_RCC_GET_RTC_SOURCE() |
AnnaBridge | 171:3a7713b1edbc | 986 | |
AnnaBridge | 171:3a7713b1edbc | 987 | /** @brief Macro to get the LCD clock pre-scaler. |
AnnaBridge | 171:3a7713b1edbc | 988 | */ |
AnnaBridge | 171:3a7713b1edbc | 989 | #define __HAL_RCC_GET_LCD_HSE_PRESCALER() __HAL_RCC_GET_RTC_HSE_PRESCALER() |
AnnaBridge | 171:3a7713b1edbc | 990 | |
AnnaBridge | 171:3a7713b1edbc | 991 | /** |
AnnaBridge | 171:3a7713b1edbc | 992 | * @} |
AnnaBridge | 171:3a7713b1edbc | 993 | */ |
AnnaBridge | 171:3a7713b1edbc | 994 | |
AnnaBridge | 171:3a7713b1edbc | 995 | #endif /* LCD */ |
AnnaBridge | 171:3a7713b1edbc | 996 | |
AnnaBridge | 171:3a7713b1edbc | 997 | |
AnnaBridge | 171:3a7713b1edbc | 998 | /** |
AnnaBridge | 171:3a7713b1edbc | 999 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1000 | */ |
AnnaBridge | 171:3a7713b1edbc | 1001 | |
AnnaBridge | 171:3a7713b1edbc | 1002 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 1003 | /** @addtogroup RCCEx_Exported_Functions |
AnnaBridge | 171:3a7713b1edbc | 1004 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1005 | */ |
AnnaBridge | 171:3a7713b1edbc | 1006 | |
AnnaBridge | 171:3a7713b1edbc | 1007 | /** @addtogroup RCCEx_Exported_Functions_Group1 |
AnnaBridge | 171:3a7713b1edbc | 1008 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1009 | */ |
AnnaBridge | 171:3a7713b1edbc | 1010 | |
AnnaBridge | 171:3a7713b1edbc | 1011 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
AnnaBridge | 171:3a7713b1edbc | 1012 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
AnnaBridge | 171:3a7713b1edbc | 1013 | uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); |
AnnaBridge | 171:3a7713b1edbc | 1014 | |
AnnaBridge | 171:3a7713b1edbc | 1015 | #if defined(RCC_LSECSS_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 1016 | |
AnnaBridge | 171:3a7713b1edbc | 1017 | void HAL_RCCEx_EnableLSECSS(void); |
AnnaBridge | 171:3a7713b1edbc | 1018 | void HAL_RCCEx_DisableLSECSS(void); |
AnnaBridge | 171:3a7713b1edbc | 1019 | void HAL_RCCEx_EnableLSECSS_IT(void); |
AnnaBridge | 171:3a7713b1edbc | 1020 | void HAL_RCCEx_LSECSS_IRQHandler(void); |
AnnaBridge | 171:3a7713b1edbc | 1021 | void HAL_RCCEx_LSECSS_Callback(void); |
AnnaBridge | 171:3a7713b1edbc | 1022 | |
AnnaBridge | 171:3a7713b1edbc | 1023 | #endif /* RCC_LSECSS_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 1024 | |
AnnaBridge | 171:3a7713b1edbc | 1025 | /** |
AnnaBridge | 171:3a7713b1edbc | 1026 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1027 | */ |
AnnaBridge | 171:3a7713b1edbc | 1028 | |
AnnaBridge | 171:3a7713b1edbc | 1029 | /** |
AnnaBridge | 171:3a7713b1edbc | 1030 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1031 | */ |
AnnaBridge | 171:3a7713b1edbc | 1032 | |
AnnaBridge | 171:3a7713b1edbc | 1033 | /** |
AnnaBridge | 171:3a7713b1edbc | 1034 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1035 | */ |
AnnaBridge | 171:3a7713b1edbc | 1036 | |
AnnaBridge | 171:3a7713b1edbc | 1037 | /** |
AnnaBridge | 171:3a7713b1edbc | 1038 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1039 | */ |
AnnaBridge | 171:3a7713b1edbc | 1040 | |
AnnaBridge | 171:3a7713b1edbc | 1041 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 1042 | } |
AnnaBridge | 171:3a7713b1edbc | 1043 | #endif |
AnnaBridge | 171:3a7713b1edbc | 1044 | |
AnnaBridge | 171:3a7713b1edbc | 1045 | #endif /* __STM32L1xx_HAL_RCC_EX_H */ |
AnnaBridge | 171:3a7713b1edbc | 1046 | |
AnnaBridge | 171:3a7713b1edbc | 1047 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
AnnaBridge | 171:3a7713b1edbc | 1048 |