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TARGET_NUCLEO_L073RZ/TOOLCHAIN_ARM_STD/stm32l0xx_ll_tim.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
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AnnaBridge | 143:86740a56073b | 1 | /** |
AnnaBridge | 143:86740a56073b | 2 | ****************************************************************************** |
AnnaBridge | 143:86740a56073b | 3 | * @file stm32l0xx_ll_tim.h |
AnnaBridge | 143:86740a56073b | 4 | * @author MCD Application Team |
AnnaBridge | 143:86740a56073b | 5 | * @brief Header file of TIM LL module. |
AnnaBridge | 143:86740a56073b | 6 | ****************************************************************************** |
AnnaBridge | 143:86740a56073b | 7 | * @attention |
AnnaBridge | 143:86740a56073b | 8 | * |
AnnaBridge | 143:86740a56073b | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
AnnaBridge | 143:86740a56073b | 10 | * |
AnnaBridge | 143:86740a56073b | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 143:86740a56073b | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 143:86740a56073b | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 143:86740a56073b | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 143:86740a56073b | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 143:86740a56073b | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 143:86740a56073b | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 143:86740a56073b | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 143:86740a56073b | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 143:86740a56073b | 20 | * without specific prior written permission. |
AnnaBridge | 143:86740a56073b | 21 | * |
AnnaBridge | 143:86740a56073b | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 143:86740a56073b | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 143:86740a56073b | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 143:86740a56073b | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 143:86740a56073b | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 143:86740a56073b | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 143:86740a56073b | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 143:86740a56073b | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 143:86740a56073b | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 143:86740a56073b | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 143:86740a56073b | 32 | * |
AnnaBridge | 143:86740a56073b | 33 | ****************************************************************************** |
AnnaBridge | 143:86740a56073b | 34 | */ |
AnnaBridge | 143:86740a56073b | 35 | |
AnnaBridge | 143:86740a56073b | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 37 | #ifndef __STM32L0xx_LL_TIM_H |
AnnaBridge | 143:86740a56073b | 38 | #define __STM32L0xx_LL_TIM_H |
AnnaBridge | 143:86740a56073b | 39 | |
AnnaBridge | 143:86740a56073b | 40 | #ifdef __cplusplus |
AnnaBridge | 143:86740a56073b | 41 | extern "C" { |
AnnaBridge | 143:86740a56073b | 42 | #endif |
AnnaBridge | 143:86740a56073b | 43 | |
AnnaBridge | 143:86740a56073b | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 45 | #include "stm32l0xx.h" |
AnnaBridge | 143:86740a56073b | 46 | |
AnnaBridge | 143:86740a56073b | 47 | /** @addtogroup STM32L0xx_LL_Driver |
AnnaBridge | 143:86740a56073b | 48 | * @{ |
AnnaBridge | 143:86740a56073b | 49 | */ |
AnnaBridge | 143:86740a56073b | 50 | |
AnnaBridge | 143:86740a56073b | 51 | #if defined (TIM2) || defined (TIM3) || defined (TIM21) || defined (TIM22) || defined (TIM6) || defined (TIM7) |
AnnaBridge | 143:86740a56073b | 52 | |
AnnaBridge | 143:86740a56073b | 53 | /** @defgroup TIM_LL TIM |
AnnaBridge | 143:86740a56073b | 54 | * @{ |
AnnaBridge | 143:86740a56073b | 55 | */ |
AnnaBridge | 143:86740a56073b | 56 | |
AnnaBridge | 143:86740a56073b | 57 | /* Private types -------------------------------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 58 | /* Private variables ---------------------------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 59 | /** @defgroup TIM_LL_Private_Variables TIM Private Variables |
AnnaBridge | 143:86740a56073b | 60 | * @{ |
AnnaBridge | 143:86740a56073b | 61 | */ |
AnnaBridge | 167:84c0a372a020 | 62 | static const uint8_t OFFSET_TAB_CCMRx[] = |
AnnaBridge | 167:84c0a372a020 | 63 | { |
AnnaBridge | 167:84c0a372a020 | 64 | 0x00U, /* 0: TIMx_CH1 */ |
AnnaBridge | 167:84c0a372a020 | 65 | 0x00U, /* 1: NA */ |
AnnaBridge | 167:84c0a372a020 | 66 | 0x00U, /* 2: TIMx_CH2 */ |
AnnaBridge | 167:84c0a372a020 | 67 | 0x00U, /* 3: NA */ |
AnnaBridge | 167:84c0a372a020 | 68 | 0x04U, /* 4: TIMx_CH3 */ |
AnnaBridge | 167:84c0a372a020 | 69 | 0x00U, /* 5: NA */ |
AnnaBridge | 167:84c0a372a020 | 70 | 0x04U /* 6: TIMx_CH4 */ |
AnnaBridge | 167:84c0a372a020 | 71 | }; |
AnnaBridge | 143:86740a56073b | 72 | |
AnnaBridge | 143:86740a56073b | 73 | static const uint8_t SHIFT_TAB_OCxx[] = |
AnnaBridge | 143:86740a56073b | 74 | { |
AnnaBridge | 143:86740a56073b | 75 | 0U, /* 0: OC1M, OC1FE, OC1PE */ |
AnnaBridge | 143:86740a56073b | 76 | 0U, /* 1: - NA */ |
AnnaBridge | 143:86740a56073b | 77 | 8U, /* 2: OC2M, OC2FE, OC2PE */ |
AnnaBridge | 143:86740a56073b | 78 | 0U, /* 3: - NA */ |
AnnaBridge | 143:86740a56073b | 79 | 0U, /* 4: OC3M, OC3FE, OC3PE */ |
AnnaBridge | 143:86740a56073b | 80 | 0U, /* 5: - NA */ |
AnnaBridge | 143:86740a56073b | 81 | 8U /* 6: OC4M, OC4FE, OC4PE */ |
AnnaBridge | 143:86740a56073b | 82 | }; |
AnnaBridge | 143:86740a56073b | 83 | |
AnnaBridge | 143:86740a56073b | 84 | static const uint8_t SHIFT_TAB_ICxx[] = |
AnnaBridge | 143:86740a56073b | 85 | { |
AnnaBridge | 143:86740a56073b | 86 | 0U, /* 0: CC1S, IC1PSC, IC1F */ |
AnnaBridge | 143:86740a56073b | 87 | 0U, /* 1: - NA */ |
AnnaBridge | 143:86740a56073b | 88 | 8U, /* 2: CC2S, IC2PSC, IC2F */ |
AnnaBridge | 143:86740a56073b | 89 | 0U, /* 3: - NA */ |
AnnaBridge | 143:86740a56073b | 90 | 0U, /* 4: CC3S, IC3PSC, IC3F */ |
AnnaBridge | 143:86740a56073b | 91 | 0U, /* 5: - NA */ |
AnnaBridge | 143:86740a56073b | 92 | 8U /* 6: CC4S, IC4PSC, IC4F */ |
AnnaBridge | 143:86740a56073b | 93 | }; |
AnnaBridge | 143:86740a56073b | 94 | |
AnnaBridge | 143:86740a56073b | 95 | static const uint8_t SHIFT_TAB_CCxP[] = |
AnnaBridge | 143:86740a56073b | 96 | { |
AnnaBridge | 143:86740a56073b | 97 | 0U, /* 0: CC1P */ |
AnnaBridge | 143:86740a56073b | 98 | 0U, /* 1: NA */ |
AnnaBridge | 143:86740a56073b | 99 | 4U, /* 2: CC2P */ |
AnnaBridge | 143:86740a56073b | 100 | 0U, /* 3: NA */ |
AnnaBridge | 143:86740a56073b | 101 | 8U, /* 4: CC3P */ |
AnnaBridge | 143:86740a56073b | 102 | 0U, /* 5: NA */ |
AnnaBridge | 143:86740a56073b | 103 | 12U /* 6: CC4P */ |
AnnaBridge | 143:86740a56073b | 104 | }; |
AnnaBridge | 143:86740a56073b | 105 | |
AnnaBridge | 143:86740a56073b | 106 | /** |
AnnaBridge | 143:86740a56073b | 107 | * @} |
AnnaBridge | 143:86740a56073b | 108 | */ |
AnnaBridge | 143:86740a56073b | 109 | |
AnnaBridge | 143:86740a56073b | 110 | |
AnnaBridge | 143:86740a56073b | 111 | /* Private constants ---------------------------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 112 | /** @defgroup TIM_LL_Private_Constants TIM Private Constants |
AnnaBridge | 143:86740a56073b | 113 | * @{ |
AnnaBridge | 143:86740a56073b | 114 | */ |
AnnaBridge | 143:86740a56073b | 115 | |
AnnaBridge | 143:86740a56073b | 116 | |
AnnaBridge | 143:86740a56073b | 117 | /* Remap mask definitions */ |
AnnaBridge | 143:86740a56073b | 118 | #define TIMx_OR_RMP_SHIFT ((uint32_t)16U) |
AnnaBridge | 143:86740a56073b | 119 | #define TIMx_OR_RMP_MASK ((uint32_t)0x0000FFFFU) |
AnnaBridge | 143:86740a56073b | 120 | #define TIM2_OR_RMP_MASK ((uint32_t)((TIM2_OR_ETR_RMP | TIM2_OR_TI4_RMP ) << TIMx_OR_RMP_SHIFT)) |
AnnaBridge | 143:86740a56073b | 121 | #define TIM21_OR_RMP_MASK ((uint32_t)((TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP) << TIMx_OR_RMP_SHIFT)) |
AnnaBridge | 143:86740a56073b | 122 | #define TIM22_OR_RMP_MASK ((uint32_t)((TIM22_OR_ETR_RMP | TIM22_OR_TI1_RMP) << TIMx_OR_RMP_SHIFT)) |
AnnaBridge | 143:86740a56073b | 123 | #if defined(TIM3) |
AnnaBridge | 143:86740a56073b | 124 | #define TIM3_OR_RMP_MASK ((uint32_t)((TIM3_OR_ETR_RMP | TIM3_OR_TI1_RMP | TIM3_OR_TI2_RMP | TIM3_OR_TI4_RMP) << TIMx_OR_RMP_SHIFT)) |
AnnaBridge | 143:86740a56073b | 125 | #endif /* TIM3 */ |
AnnaBridge | 143:86740a56073b | 126 | |
AnnaBridge | 143:86740a56073b | 127 | |
AnnaBridge | 143:86740a56073b | 128 | |
AnnaBridge | 143:86740a56073b | 129 | /** |
AnnaBridge | 143:86740a56073b | 130 | * @} |
AnnaBridge | 143:86740a56073b | 131 | */ |
AnnaBridge | 143:86740a56073b | 132 | |
AnnaBridge | 143:86740a56073b | 133 | |
AnnaBridge | 143:86740a56073b | 134 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 135 | /** @defgroup TIM_LL_Private_Macros TIM Private Macros |
AnnaBridge | 143:86740a56073b | 136 | * @{ |
AnnaBridge | 143:86740a56073b | 137 | */ |
AnnaBridge | 143:86740a56073b | 138 | /** @brief Convert channel id into channel index. |
AnnaBridge | 167:84c0a372a020 | 139 | * @param __CHANNEL__ This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 140 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 141 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 142 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 143 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 144 | * @retval none |
AnnaBridge | 143:86740a56073b | 145 | */ |
AnnaBridge | 143:86740a56073b | 146 | #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ |
AnnaBridge | 143:86740a56073b | 147 | (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ |
AnnaBridge | 143:86740a56073b | 148 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ |
AnnaBridge | 143:86740a56073b | 149 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U : 6U) |
AnnaBridge | 143:86740a56073b | 150 | |
AnnaBridge | 143:86740a56073b | 151 | /** |
AnnaBridge | 143:86740a56073b | 152 | * @} |
AnnaBridge | 143:86740a56073b | 153 | */ |
AnnaBridge | 143:86740a56073b | 154 | |
AnnaBridge | 143:86740a56073b | 155 | |
AnnaBridge | 143:86740a56073b | 156 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 157 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 143:86740a56073b | 158 | /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure |
AnnaBridge | 143:86740a56073b | 159 | * @{ |
AnnaBridge | 143:86740a56073b | 160 | */ |
AnnaBridge | 143:86740a56073b | 161 | |
AnnaBridge | 167:84c0a372a020 | 162 | /** |
AnnaBridge | 167:84c0a372a020 | 163 | * @brief TIM Time Base configuration structure definition. |
AnnaBridge | 143:86740a56073b | 164 | */ |
AnnaBridge | 143:86740a56073b | 165 | typedef struct |
AnnaBridge | 143:86740a56073b | 166 | { |
AnnaBridge | 143:86740a56073b | 167 | uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
AnnaBridge | 167:84c0a372a020 | 168 | This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
AnnaBridge | 143:86740a56073b | 169 | |
AnnaBridge | 143:86740a56073b | 170 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/ |
AnnaBridge | 143:86740a56073b | 171 | |
AnnaBridge | 143:86740a56073b | 172 | uint32_t CounterMode; /*!< Specifies the counter mode. |
AnnaBridge | 143:86740a56073b | 173 | This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. |
AnnaBridge | 143:86740a56073b | 174 | |
AnnaBridge | 143:86740a56073b | 175 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/ |
AnnaBridge | 143:86740a56073b | 176 | |
AnnaBridge | 143:86740a56073b | 177 | uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active |
AnnaBridge | 143:86740a56073b | 178 | Auto-Reload Register at the next update event. |
AnnaBridge | 167:84c0a372a020 | 179 | This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
AnnaBridge | 167:84c0a372a020 | 180 | Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF. |
AnnaBridge | 167:84c0a372a020 | 181 | |
AnnaBridge | 167:84c0a372a020 | 182 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/ |
AnnaBridge | 143:86740a56073b | 183 | |
AnnaBridge | 143:86740a56073b | 184 | uint32_t ClockDivision; /*!< Specifies the clock division. |
AnnaBridge | 167:84c0a372a020 | 185 | This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. |
AnnaBridge | 167:84c0a372a020 | 186 | |
AnnaBridge | 143:86740a56073b | 187 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ |
AnnaBridge | 167:84c0a372a020 | 188 | } LL_TIM_InitTypeDef; |
AnnaBridge | 167:84c0a372a020 | 189 | |
AnnaBridge | 167:84c0a372a020 | 190 | /** |
AnnaBridge | 167:84c0a372a020 | 191 | * @brief TIM Output Compare configuration structure definition. |
AnnaBridge | 143:86740a56073b | 192 | */ |
AnnaBridge | 143:86740a56073b | 193 | typedef struct |
AnnaBridge | 143:86740a56073b | 194 | { |
AnnaBridge | 143:86740a56073b | 195 | uint32_t OCMode; /*!< Specifies the output mode. |
AnnaBridge | 143:86740a56073b | 196 | This parameter can be a value of @ref TIM_LL_EC_OCMODE. |
AnnaBridge | 143:86740a56073b | 197 | |
AnnaBridge | 143:86740a56073b | 198 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/ |
AnnaBridge | 143:86740a56073b | 199 | |
AnnaBridge | 143:86740a56073b | 200 | uint32_t OCState; /*!< Specifies the TIM Output Compare state. |
AnnaBridge | 143:86740a56073b | 201 | This parameter can be a value of @ref TIM_LL_EC_OCSTATE. |
AnnaBridge | 143:86740a56073b | 202 | |
AnnaBridge | 143:86740a56073b | 203 | This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ |
AnnaBridge | 143:86740a56073b | 204 | |
AnnaBridge | 143:86740a56073b | 205 | uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. |
AnnaBridge | 167:84c0a372a020 | 206 | This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
AnnaBridge | 143:86740a56073b | 207 | |
AnnaBridge | 143:86740a56073b | 208 | This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/ |
AnnaBridge | 143:86740a56073b | 209 | |
AnnaBridge | 143:86740a56073b | 210 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
AnnaBridge | 143:86740a56073b | 211 | This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. |
AnnaBridge | 143:86740a56073b | 212 | |
AnnaBridge | 143:86740a56073b | 213 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ |
AnnaBridge | 143:86740a56073b | 214 | |
AnnaBridge | 143:86740a56073b | 215 | } LL_TIM_OC_InitTypeDef; |
AnnaBridge | 143:86740a56073b | 216 | |
AnnaBridge | 167:84c0a372a020 | 217 | /** |
AnnaBridge | 167:84c0a372a020 | 218 | * @brief TIM Input Capture configuration structure definition. |
AnnaBridge | 143:86740a56073b | 219 | */ |
AnnaBridge | 143:86740a56073b | 220 | |
AnnaBridge | 143:86740a56073b | 221 | typedef struct |
AnnaBridge | 143:86740a56073b | 222 | { |
AnnaBridge | 143:86740a56073b | 223 | |
AnnaBridge | 143:86740a56073b | 224 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 143:86740a56073b | 225 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
AnnaBridge | 143:86740a56073b | 226 | |
AnnaBridge | 143:86740a56073b | 227 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ |
AnnaBridge | 143:86740a56073b | 228 | |
AnnaBridge | 143:86740a56073b | 229 | uint32_t ICActiveInput; /*!< Specifies the input. |
AnnaBridge | 143:86740a56073b | 230 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
AnnaBridge | 143:86740a56073b | 231 | |
AnnaBridge | 143:86740a56073b | 232 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ |
AnnaBridge | 143:86740a56073b | 233 | |
AnnaBridge | 143:86740a56073b | 234 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
AnnaBridge | 143:86740a56073b | 235 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
AnnaBridge | 143:86740a56073b | 236 | |
AnnaBridge | 143:86740a56073b | 237 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ |
AnnaBridge | 143:86740a56073b | 238 | |
AnnaBridge | 143:86740a56073b | 239 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
AnnaBridge | 143:86740a56073b | 240 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
AnnaBridge | 143:86740a56073b | 241 | |
AnnaBridge | 143:86740a56073b | 242 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ |
AnnaBridge | 143:86740a56073b | 243 | } LL_TIM_IC_InitTypeDef; |
AnnaBridge | 143:86740a56073b | 244 | |
AnnaBridge | 143:86740a56073b | 245 | |
AnnaBridge | 143:86740a56073b | 246 | /** |
AnnaBridge | 143:86740a56073b | 247 | * @brief TIM Encoder interface configuration structure definition. |
AnnaBridge | 143:86740a56073b | 248 | */ |
AnnaBridge | 143:86740a56073b | 249 | typedef struct |
AnnaBridge | 143:86740a56073b | 250 | { |
AnnaBridge | 143:86740a56073b | 251 | uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). |
AnnaBridge | 143:86740a56073b | 252 | This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. |
AnnaBridge | 143:86740a56073b | 253 | |
AnnaBridge | 143:86740a56073b | 254 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/ |
AnnaBridge | 143:86740a56073b | 255 | |
AnnaBridge | 143:86740a56073b | 256 | uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. |
AnnaBridge | 143:86740a56073b | 257 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
AnnaBridge | 143:86740a56073b | 258 | |
AnnaBridge | 143:86740a56073b | 259 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ |
AnnaBridge | 143:86740a56073b | 260 | |
AnnaBridge | 143:86740a56073b | 261 | uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source |
AnnaBridge | 143:86740a56073b | 262 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
AnnaBridge | 143:86740a56073b | 263 | |
AnnaBridge | 143:86740a56073b | 264 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ |
AnnaBridge | 143:86740a56073b | 265 | |
AnnaBridge | 143:86740a56073b | 266 | uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. |
AnnaBridge | 143:86740a56073b | 267 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
AnnaBridge | 143:86740a56073b | 268 | |
AnnaBridge | 143:86740a56073b | 269 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ |
AnnaBridge | 143:86740a56073b | 270 | |
AnnaBridge | 143:86740a56073b | 271 | uint32_t IC1Filter; /*!< Specifies the TI1 input filter. |
AnnaBridge | 143:86740a56073b | 272 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
AnnaBridge | 143:86740a56073b | 273 | |
AnnaBridge | 143:86740a56073b | 274 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ |
AnnaBridge | 143:86740a56073b | 275 | |
AnnaBridge | 143:86740a56073b | 276 | uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. |
AnnaBridge | 143:86740a56073b | 277 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
AnnaBridge | 143:86740a56073b | 278 | |
AnnaBridge | 143:86740a56073b | 279 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ |
AnnaBridge | 143:86740a56073b | 280 | |
AnnaBridge | 143:86740a56073b | 281 | uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source |
AnnaBridge | 143:86740a56073b | 282 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
AnnaBridge | 143:86740a56073b | 283 | |
AnnaBridge | 143:86740a56073b | 284 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ |
AnnaBridge | 143:86740a56073b | 285 | |
AnnaBridge | 143:86740a56073b | 286 | uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. |
AnnaBridge | 143:86740a56073b | 287 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
AnnaBridge | 143:86740a56073b | 288 | |
AnnaBridge | 143:86740a56073b | 289 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ |
AnnaBridge | 143:86740a56073b | 290 | |
AnnaBridge | 143:86740a56073b | 291 | uint32_t IC2Filter; /*!< Specifies the TI2 input filter. |
AnnaBridge | 143:86740a56073b | 292 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
AnnaBridge | 143:86740a56073b | 293 | |
AnnaBridge | 143:86740a56073b | 294 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ |
AnnaBridge | 143:86740a56073b | 295 | |
AnnaBridge | 143:86740a56073b | 296 | } LL_TIM_ENCODER_InitTypeDef; |
AnnaBridge | 143:86740a56073b | 297 | |
AnnaBridge | 143:86740a56073b | 298 | |
AnnaBridge | 143:86740a56073b | 299 | /** |
AnnaBridge | 143:86740a56073b | 300 | * @} |
AnnaBridge | 143:86740a56073b | 301 | */ |
AnnaBridge | 143:86740a56073b | 302 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 143:86740a56073b | 303 | |
AnnaBridge | 143:86740a56073b | 304 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 305 | /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants |
AnnaBridge | 143:86740a56073b | 306 | * @{ |
AnnaBridge | 143:86740a56073b | 307 | */ |
AnnaBridge | 167:84c0a372a020 | 308 | |
AnnaBridge | 143:86740a56073b | 309 | /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines |
AnnaBridge | 143:86740a56073b | 310 | * @brief Flags defines which can be used with LL_TIM_ReadReg function. |
AnnaBridge | 143:86740a56073b | 311 | * @{ |
AnnaBridge | 143:86740a56073b | 312 | */ |
AnnaBridge | 143:86740a56073b | 313 | #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ |
AnnaBridge | 143:86740a56073b | 314 | #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ |
AnnaBridge | 143:86740a56073b | 315 | #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ |
AnnaBridge | 143:86740a56073b | 316 | #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ |
AnnaBridge | 143:86740a56073b | 317 | #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ |
AnnaBridge | 143:86740a56073b | 318 | #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ |
AnnaBridge | 143:86740a56073b | 319 | #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ |
AnnaBridge | 143:86740a56073b | 320 | #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ |
AnnaBridge | 143:86740a56073b | 321 | #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ |
AnnaBridge | 143:86740a56073b | 322 | #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ |
AnnaBridge | 143:86740a56073b | 323 | /** |
AnnaBridge | 143:86740a56073b | 324 | * @} |
AnnaBridge | 143:86740a56073b | 325 | */ |
AnnaBridge | 143:86740a56073b | 326 | |
AnnaBridge | 143:86740a56073b | 327 | /** @defgroup TIM_LL_EC_IT IT Defines |
AnnaBridge | 143:86740a56073b | 328 | * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. |
AnnaBridge | 143:86740a56073b | 329 | * @{ |
AnnaBridge | 143:86740a56073b | 330 | */ |
AnnaBridge | 143:86740a56073b | 331 | #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ |
AnnaBridge | 143:86740a56073b | 332 | #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ |
AnnaBridge | 143:86740a56073b | 333 | #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ |
AnnaBridge | 143:86740a56073b | 334 | #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ |
AnnaBridge | 143:86740a56073b | 335 | #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ |
AnnaBridge | 143:86740a56073b | 336 | #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ |
AnnaBridge | 143:86740a56073b | 337 | /** |
AnnaBridge | 143:86740a56073b | 338 | * @} |
AnnaBridge | 143:86740a56073b | 339 | */ |
AnnaBridge | 143:86740a56073b | 340 | |
AnnaBridge | 143:86740a56073b | 341 | /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source |
AnnaBridge | 143:86740a56073b | 342 | * @{ |
AnnaBridge | 143:86740a56073b | 343 | */ |
AnnaBridge | 167:84c0a372a020 | 344 | #define LL_TIM_UPDATESOURCE_REGULAR ((uint32_t)0x00000000U) /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ |
AnnaBridge | 167:84c0a372a020 | 345 | #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ |
AnnaBridge | 143:86740a56073b | 346 | /** |
AnnaBridge | 143:86740a56073b | 347 | * @} |
AnnaBridge | 143:86740a56073b | 348 | */ |
AnnaBridge | 143:86740a56073b | 349 | |
AnnaBridge | 143:86740a56073b | 350 | /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode |
AnnaBridge | 143:86740a56073b | 351 | * @{ |
AnnaBridge | 143:86740a56073b | 352 | */ |
AnnaBridge | 167:84c0a372a020 | 353 | #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ |
AnnaBridge | 167:84c0a372a020 | 354 | #define LL_TIM_ONEPULSEMODE_REPETITIVE ((uint32_t)0x00000000U) /*!< Counter stops counting at the next update event */ |
AnnaBridge | 143:86740a56073b | 355 | /** |
AnnaBridge | 143:86740a56073b | 356 | * @} |
AnnaBridge | 143:86740a56073b | 357 | */ |
AnnaBridge | 143:86740a56073b | 358 | |
AnnaBridge | 143:86740a56073b | 359 | /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode |
AnnaBridge | 143:86740a56073b | 360 | * @{ |
AnnaBridge | 143:86740a56073b | 361 | */ |
AnnaBridge | 167:84c0a372a020 | 362 | #define LL_TIM_COUNTERMODE_UP ((uint32_t)0x00000000U) /*!<Counter used as upcounter */ |
AnnaBridge | 167:84c0a372a020 | 363 | #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ |
AnnaBridge | 167:84c0a372a020 | 364 | #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ |
AnnaBridge | 167:84c0a372a020 | 365 | #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ |
AnnaBridge | 167:84c0a372a020 | 366 | #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ |
AnnaBridge | 143:86740a56073b | 367 | /** |
AnnaBridge | 143:86740a56073b | 368 | * @} |
AnnaBridge | 143:86740a56073b | 369 | */ |
AnnaBridge | 143:86740a56073b | 370 | |
AnnaBridge | 143:86740a56073b | 371 | /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division |
AnnaBridge | 143:86740a56073b | 372 | * @{ |
AnnaBridge | 143:86740a56073b | 373 | */ |
AnnaBridge | 167:84c0a372a020 | 374 | #define LL_TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x00000000U) /*!< tDTS=tCK_INT */ |
AnnaBridge | 167:84c0a372a020 | 375 | #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ |
AnnaBridge | 167:84c0a372a020 | 376 | #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ |
AnnaBridge | 143:86740a56073b | 377 | /** |
AnnaBridge | 143:86740a56073b | 378 | * @} |
AnnaBridge | 143:86740a56073b | 379 | */ |
AnnaBridge | 143:86740a56073b | 380 | |
AnnaBridge | 143:86740a56073b | 381 | /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction |
AnnaBridge | 143:86740a56073b | 382 | * @{ |
AnnaBridge | 143:86740a56073b | 383 | */ |
AnnaBridge | 143:86740a56073b | 384 | #define LL_TIM_COUNTERDIRECTION_UP ((uint32_t)0x00000000U) /*!< Timer counter counts up */ |
AnnaBridge | 143:86740a56073b | 385 | #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ |
AnnaBridge | 143:86740a56073b | 386 | /** |
AnnaBridge | 143:86740a56073b | 387 | * @} |
AnnaBridge | 143:86740a56073b | 388 | */ |
AnnaBridge | 143:86740a56073b | 389 | |
AnnaBridge | 143:86740a56073b | 390 | |
AnnaBridge | 143:86740a56073b | 391 | /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request |
AnnaBridge | 143:86740a56073b | 392 | * @{ |
AnnaBridge | 143:86740a56073b | 393 | */ |
AnnaBridge | 167:84c0a372a020 | 394 | #define LL_TIM_CCDMAREQUEST_CC ((uint32_t)0x00000000U) /*!< CCx DMA request sent when CCx event occurs */ |
AnnaBridge | 167:84c0a372a020 | 395 | #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ |
AnnaBridge | 143:86740a56073b | 396 | /** |
AnnaBridge | 143:86740a56073b | 397 | * @} |
AnnaBridge | 143:86740a56073b | 398 | */ |
AnnaBridge | 143:86740a56073b | 399 | |
AnnaBridge | 143:86740a56073b | 400 | |
AnnaBridge | 143:86740a56073b | 401 | /** @defgroup TIM_LL_EC_CHANNEL Channel |
AnnaBridge | 143:86740a56073b | 402 | * @{ |
AnnaBridge | 143:86740a56073b | 403 | */ |
AnnaBridge | 143:86740a56073b | 404 | #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ |
AnnaBridge | 143:86740a56073b | 405 | #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ |
AnnaBridge | 143:86740a56073b | 406 | #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ |
AnnaBridge | 143:86740a56073b | 407 | #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ |
AnnaBridge | 143:86740a56073b | 408 | /** |
AnnaBridge | 143:86740a56073b | 409 | * @} |
AnnaBridge | 143:86740a56073b | 410 | */ |
AnnaBridge | 143:86740a56073b | 411 | |
AnnaBridge | 143:86740a56073b | 412 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 143:86740a56073b | 413 | /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State |
AnnaBridge | 143:86740a56073b | 414 | * @{ |
AnnaBridge | 143:86740a56073b | 415 | */ |
AnnaBridge | 167:84c0a372a020 | 416 | #define LL_TIM_OCSTATE_DISABLE ((uint32_t)0x00000000U) /*!< OCx is not active */ |
AnnaBridge | 167:84c0a372a020 | 417 | #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ |
AnnaBridge | 143:86740a56073b | 418 | /** |
AnnaBridge | 143:86740a56073b | 419 | * @} |
AnnaBridge | 143:86740a56073b | 420 | */ |
AnnaBridge | 143:86740a56073b | 421 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 143:86740a56073b | 422 | |
AnnaBridge | 143:86740a56073b | 423 | /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode |
AnnaBridge | 143:86740a56073b | 424 | * @{ |
AnnaBridge | 143:86740a56073b | 425 | */ |
AnnaBridge | 167:84c0a372a020 | 426 | #define LL_TIM_OCMODE_FROZEN ((uint32_t)0x00000000U) /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */ |
AnnaBridge | 167:84c0a372a020 | 427 | #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/ |
AnnaBridge | 167:84c0a372a020 | 428 | #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/ |
AnnaBridge | 167:84c0a372a020 | 429 | #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/ |
AnnaBridge | 167:84c0a372a020 | 430 | #define LL_TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) /*!<OCyREF is forced low*/ |
AnnaBridge | 167:84c0a372a020 | 431 | #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/ |
AnnaBridge | 167:84c0a372a020 | 432 | #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/ |
AnnaBridge | 167:84c0a372a020 | 433 | #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/ |
AnnaBridge | 143:86740a56073b | 434 | /** |
AnnaBridge | 143:86740a56073b | 435 | * @} |
AnnaBridge | 143:86740a56073b | 436 | */ |
AnnaBridge | 143:86740a56073b | 437 | |
AnnaBridge | 143:86740a56073b | 438 | /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity |
AnnaBridge | 143:86740a56073b | 439 | * @{ |
AnnaBridge | 143:86740a56073b | 440 | */ |
AnnaBridge | 167:84c0a372a020 | 441 | #define LL_TIM_OCPOLARITY_HIGH ((uint32_t)0x00000000U) /*!< OCxactive high*/ |
AnnaBridge | 167:84c0a372a020 | 442 | #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ |
AnnaBridge | 143:86740a56073b | 443 | /** |
AnnaBridge | 143:86740a56073b | 444 | * @} |
AnnaBridge | 143:86740a56073b | 445 | */ |
AnnaBridge | 143:86740a56073b | 446 | |
AnnaBridge | 143:86740a56073b | 447 | |
AnnaBridge | 143:86740a56073b | 448 | |
AnnaBridge | 143:86740a56073b | 449 | /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection |
AnnaBridge | 143:86740a56073b | 450 | * @{ |
AnnaBridge | 143:86740a56073b | 451 | */ |
AnnaBridge | 167:84c0a372a020 | 452 | #define LL_TIM_ACTIVEINPUT_DIRECTTI (uint32_t)(TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */ |
AnnaBridge | 167:84c0a372a020 | 453 | #define LL_TIM_ACTIVEINPUT_INDIRECTTI (uint32_t)(TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */ |
AnnaBridge | 167:84c0a372a020 | 454 | #define LL_TIM_ACTIVEINPUT_TRC (uint32_t)(TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */ |
AnnaBridge | 143:86740a56073b | 455 | /** |
AnnaBridge | 143:86740a56073b | 456 | * @} |
AnnaBridge | 143:86740a56073b | 457 | */ |
AnnaBridge | 143:86740a56073b | 458 | |
AnnaBridge | 143:86740a56073b | 459 | /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler |
AnnaBridge | 143:86740a56073b | 460 | * @{ |
AnnaBridge | 143:86740a56073b | 461 | */ |
AnnaBridge | 167:84c0a372a020 | 462 | #define LL_TIM_ICPSC_DIV1 ((uint32_t)0x00000000U) /*!< No prescaler, capture is done each time an edge is detected on the capture input */ |
AnnaBridge | 167:84c0a372a020 | 463 | #define LL_TIM_ICPSC_DIV2 (uint32_t)(TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */ |
AnnaBridge | 167:84c0a372a020 | 464 | #define LL_TIM_ICPSC_DIV4 (uint32_t)(TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */ |
AnnaBridge | 167:84c0a372a020 | 465 | #define LL_TIM_ICPSC_DIV8 (uint32_t)(TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */ |
AnnaBridge | 143:86740a56073b | 466 | /** |
AnnaBridge | 143:86740a56073b | 467 | * @} |
AnnaBridge | 143:86740a56073b | 468 | */ |
AnnaBridge | 143:86740a56073b | 469 | |
AnnaBridge | 143:86740a56073b | 470 | /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter |
AnnaBridge | 143:86740a56073b | 471 | * @{ |
AnnaBridge | 143:86740a56073b | 472 | */ |
AnnaBridge | 167:84c0a372a020 | 473 | #define LL_TIM_IC_FILTER_FDIV1 ((uint32_t)0x00000000U) /*!< No filter, sampling is done at fDTS */ |
AnnaBridge | 167:84c0a372a020 | 474 | #define LL_TIM_IC_FILTER_FDIV1_N2 (uint32_t)(TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */ |
AnnaBridge | 167:84c0a372a020 | 475 | #define LL_TIM_IC_FILTER_FDIV1_N4 (uint32_t)(TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */ |
AnnaBridge | 167:84c0a372a020 | 476 | #define LL_TIM_IC_FILTER_FDIV1_N8 (uint32_t)((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */ |
AnnaBridge | 167:84c0a372a020 | 477 | #define LL_TIM_IC_FILTER_FDIV2_N6 (uint32_t)(TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */ |
AnnaBridge | 167:84c0a372a020 | 478 | #define LL_TIM_IC_FILTER_FDIV2_N8 (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */ |
AnnaBridge | 167:84c0a372a020 | 479 | #define LL_TIM_IC_FILTER_FDIV4_N6 (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */ |
AnnaBridge | 167:84c0a372a020 | 480 | #define LL_TIM_IC_FILTER_FDIV4_N8 (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */ |
AnnaBridge | 167:84c0a372a020 | 481 | #define LL_TIM_IC_FILTER_FDIV8_N6 (uint32_t)(TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */ |
AnnaBridge | 167:84c0a372a020 | 482 | #define LL_TIM_IC_FILTER_FDIV8_N8 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */ |
AnnaBridge | 167:84c0a372a020 | 483 | #define LL_TIM_IC_FILTER_FDIV16_N5 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */ |
AnnaBridge | 167:84c0a372a020 | 484 | #define LL_TIM_IC_FILTER_FDIV16_N6 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */ |
AnnaBridge | 167:84c0a372a020 | 485 | #define LL_TIM_IC_FILTER_FDIV16_N8 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */ |
AnnaBridge | 167:84c0a372a020 | 486 | #define LL_TIM_IC_FILTER_FDIV32_N5 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */ |
AnnaBridge | 167:84c0a372a020 | 487 | #define LL_TIM_IC_FILTER_FDIV32_N6 (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */ |
AnnaBridge | 167:84c0a372a020 | 488 | #define LL_TIM_IC_FILTER_FDIV32_N8 (uint32_t)(TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */ |
AnnaBridge | 143:86740a56073b | 489 | /** |
AnnaBridge | 143:86740a56073b | 490 | * @} |
AnnaBridge | 143:86740a56073b | 491 | */ |
AnnaBridge | 143:86740a56073b | 492 | |
AnnaBridge | 143:86740a56073b | 493 | /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity |
AnnaBridge | 143:86740a56073b | 494 | * @{ |
AnnaBridge | 143:86740a56073b | 495 | */ |
AnnaBridge | 167:84c0a372a020 | 496 | #define LL_TIM_IC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */ |
AnnaBridge | 167:84c0a372a020 | 497 | #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */ |
AnnaBridge | 167:84c0a372a020 | 498 | #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */ |
AnnaBridge | 143:86740a56073b | 499 | /** |
AnnaBridge | 143:86740a56073b | 500 | * @} |
AnnaBridge | 143:86740a56073b | 501 | */ |
AnnaBridge | 143:86740a56073b | 502 | |
AnnaBridge | 143:86740a56073b | 503 | /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source |
AnnaBridge | 143:86740a56073b | 504 | * @{ |
AnnaBridge | 143:86740a56073b | 505 | */ |
AnnaBridge | 143:86740a56073b | 506 | #define LL_TIM_CLOCKSOURCE_INTERNAL ((uint32_t)0x00000000U) /*!< The timer is clocked by the internal clock provided from the RCC */ |
AnnaBridge | 143:86740a56073b | 507 | #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0 ) /*!< Counter counts at each rising or falling edge on a selected inpu t*/ |
AnnaBridge | 143:86740a56073b | 508 | #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */ |
AnnaBridge | 143:86740a56073b | 509 | /** |
AnnaBridge | 143:86740a56073b | 510 | * @} |
AnnaBridge | 143:86740a56073b | 511 | */ |
AnnaBridge | 143:86740a56073b | 512 | |
AnnaBridge | 143:86740a56073b | 513 | /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode |
AnnaBridge | 143:86740a56073b | 514 | * @{ |
AnnaBridge | 143:86740a56073b | 515 | */ |
AnnaBridge | 167:84c0a372a020 | 516 | #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ |
AnnaBridge | 167:84c0a372a020 | 517 | #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ |
AnnaBridge | 143:86740a56073b | 518 | #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */ |
AnnaBridge | 143:86740a56073b | 519 | /** |
AnnaBridge | 143:86740a56073b | 520 | * @} |
AnnaBridge | 143:86740a56073b | 521 | */ |
AnnaBridge | 143:86740a56073b | 522 | |
AnnaBridge | 143:86740a56073b | 523 | /** @defgroup TIM_LL_EC_TRGO Trigger Output |
AnnaBridge | 143:86740a56073b | 524 | * @{ |
AnnaBridge | 143:86740a56073b | 525 | */ |
AnnaBridge | 167:84c0a372a020 | 526 | #define LL_TIM_TRGO_RESET ((uint32_t)0x00000000U) /*!< UG bit from the TIMx_EGR register is used as trigger output */ |
AnnaBridge | 167:84c0a372a020 | 527 | #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */ |
AnnaBridge | 167:84c0a372a020 | 528 | #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */ |
AnnaBridge | 167:84c0a372a020 | 529 | #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */ |
AnnaBridge | 167:84c0a372a020 | 530 | #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */ |
AnnaBridge | 167:84c0a372a020 | 531 | #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */ |
AnnaBridge | 167:84c0a372a020 | 532 | #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */ |
AnnaBridge | 167:84c0a372a020 | 533 | #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */ |
AnnaBridge | 143:86740a56073b | 534 | /** |
AnnaBridge | 143:86740a56073b | 535 | * @} |
AnnaBridge | 143:86740a56073b | 536 | */ |
AnnaBridge | 143:86740a56073b | 537 | |
AnnaBridge | 143:86740a56073b | 538 | |
AnnaBridge | 143:86740a56073b | 539 | /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode |
AnnaBridge | 143:86740a56073b | 540 | * @{ |
AnnaBridge | 143:86740a56073b | 541 | */ |
AnnaBridge | 167:84c0a372a020 | 542 | #define LL_TIM_SLAVEMODE_DISABLED ((uint32_t)0x00000000U) /*!< Slave mode disabled */ |
AnnaBridge | 167:84c0a372a020 | 543 | #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */ |
AnnaBridge | 167:84c0a372a020 | 544 | #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */ |
AnnaBridge | 167:84c0a372a020 | 545 | #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */ |
AnnaBridge | 143:86740a56073b | 546 | /** |
AnnaBridge | 143:86740a56073b | 547 | * @} |
AnnaBridge | 143:86740a56073b | 548 | */ |
AnnaBridge | 143:86740a56073b | 549 | |
AnnaBridge | 143:86740a56073b | 550 | /** @defgroup TIM_LL_EC_TS Trigger Selection |
AnnaBridge | 143:86740a56073b | 551 | * @{ |
AnnaBridge | 143:86740a56073b | 552 | */ |
AnnaBridge | 167:84c0a372a020 | 553 | #define LL_TIM_TS_ITR0 ((uint32_t)0x00000000U) /*!< Internal Trigger 0 (ITR0) is used as trigger input */ |
AnnaBridge | 167:84c0a372a020 | 554 | #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ |
AnnaBridge | 167:84c0a372a020 | 555 | #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ |
AnnaBridge | 167:84c0a372a020 | 556 | #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ |
AnnaBridge | 167:84c0a372a020 | 557 | #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ |
AnnaBridge | 167:84c0a372a020 | 558 | #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ |
AnnaBridge | 167:84c0a372a020 | 559 | #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ |
AnnaBridge | 167:84c0a372a020 | 560 | #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ |
AnnaBridge | 143:86740a56073b | 561 | /** |
AnnaBridge | 143:86740a56073b | 562 | * @} |
AnnaBridge | 143:86740a56073b | 563 | */ |
AnnaBridge | 143:86740a56073b | 564 | |
AnnaBridge | 143:86740a56073b | 565 | /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity |
AnnaBridge | 143:86740a56073b | 566 | * @{ |
AnnaBridge | 143:86740a56073b | 567 | */ |
AnnaBridge | 167:84c0a372a020 | 568 | #define LL_TIM_ETR_POLARITY_NONINVERTED ((uint32_t)0x00000000U) /*!< ETR is non-inverted, active at high level or rising edge */ |
AnnaBridge | 167:84c0a372a020 | 569 | #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */ |
AnnaBridge | 143:86740a56073b | 570 | /** |
AnnaBridge | 143:86740a56073b | 571 | * @} |
AnnaBridge | 143:86740a56073b | 572 | */ |
AnnaBridge | 143:86740a56073b | 573 | |
AnnaBridge | 143:86740a56073b | 574 | /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler |
AnnaBridge | 143:86740a56073b | 575 | * @{ |
AnnaBridge | 143:86740a56073b | 576 | */ |
AnnaBridge | 167:84c0a372a020 | 577 | #define LL_TIM_ETR_PRESCALER_DIV1 ((uint32_t)0x00000000U) /*!< ETR prescaler OFF */ |
AnnaBridge | 167:84c0a372a020 | 578 | #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */ |
AnnaBridge | 167:84c0a372a020 | 579 | #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */ |
AnnaBridge | 167:84c0a372a020 | 580 | #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */ |
AnnaBridge | 143:86740a56073b | 581 | /** |
AnnaBridge | 143:86740a56073b | 582 | * @} |
AnnaBridge | 143:86740a56073b | 583 | */ |
AnnaBridge | 143:86740a56073b | 584 | |
AnnaBridge | 143:86740a56073b | 585 | /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter |
AnnaBridge | 143:86740a56073b | 586 | * @{ |
AnnaBridge | 143:86740a56073b | 587 | */ |
AnnaBridge | 167:84c0a372a020 | 588 | #define LL_TIM_ETR_FILTER_FDIV1 ((uint32_t)0x00000000U) /*!< No filter, sampling is done at fDTS */ |
AnnaBridge | 167:84c0a372a020 | 589 | #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */ |
AnnaBridge | 167:84c0a372a020 | 590 | #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */ |
AnnaBridge | 167:84c0a372a020 | 591 | #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */ |
AnnaBridge | 167:84c0a372a020 | 592 | #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */ |
AnnaBridge | 167:84c0a372a020 | 593 | #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */ |
AnnaBridge | 167:84c0a372a020 | 594 | #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 ) /*!< fSAMPLING=fDTS/4, N=6 */ |
AnnaBridge | 167:84c0a372a020 | 595 | #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */ |
AnnaBridge | 167:84c0a372a020 | 596 | #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */ |
AnnaBridge | 167:84c0a372a020 | 597 | #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */ |
AnnaBridge | 167:84c0a372a020 | 598 | #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 ) /*!< fSAMPLING=fDTS/16, N=6 */ |
AnnaBridge | 167:84c0a372a020 | 599 | #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */ |
AnnaBridge | 167:84c0a372a020 | 600 | #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 ) /*!< fSAMPLING=fDTS/16, N=5 */ |
AnnaBridge | 167:84c0a372a020 | 601 | #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */ |
AnnaBridge | 167:84c0a372a020 | 602 | #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */ |
AnnaBridge | 167:84c0a372a020 | 603 | #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */ |
AnnaBridge | 143:86740a56073b | 604 | /** |
AnnaBridge | 143:86740a56073b | 605 | * @} |
AnnaBridge | 143:86740a56073b | 606 | */ |
AnnaBridge | 143:86740a56073b | 607 | |
AnnaBridge | 143:86740a56073b | 608 | |
AnnaBridge | 143:86740a56073b | 609 | |
AnnaBridge | 143:86740a56073b | 610 | |
AnnaBridge | 143:86740a56073b | 611 | |
AnnaBridge | 143:86740a56073b | 612 | |
AnnaBridge | 143:86740a56073b | 613 | |
AnnaBridge | 143:86740a56073b | 614 | /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address |
AnnaBridge | 143:86740a56073b | 615 | * @{ |
AnnaBridge | 143:86740a56073b | 616 | */ |
AnnaBridge | 167:84c0a372a020 | 617 | #define LL_TIM_DMABURST_BASEADDR_CR1 ((uint32_t)0x00000000U) /*!< TIMx_CR1 register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 618 | #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 619 | #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 620 | #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 621 | #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 622 | #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 623 | #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 624 | #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 625 | #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 626 | #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 627 | #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 628 | #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 629 | #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 630 | #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 631 | #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 632 | #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 633 | #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 634 | #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 635 | #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 636 | #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 637 | #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 638 | #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_OR1 register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 639 | #define LL_TIM_DMABURST_BASEADDR_OR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_OR2 register is the DMA base address for DMA burst */ |
AnnaBridge | 167:84c0a372a020 | 640 | #define LL_TIM_DMABURST_BASEADDR_OR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_OR3 register is the DMA base address for DMA burst */ |
AnnaBridge | 143:86740a56073b | 641 | /** |
AnnaBridge | 143:86740a56073b | 642 | * @} |
AnnaBridge | 143:86740a56073b | 643 | */ |
AnnaBridge | 143:86740a56073b | 644 | |
AnnaBridge | 143:86740a56073b | 645 | /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length |
AnnaBridge | 143:86740a56073b | 646 | * @{ |
AnnaBridge | 143:86740a56073b | 647 | */ |
AnnaBridge | 167:84c0a372a020 | 648 | #define LL_TIM_DMABURST_LENGTH_1TRANSFER ((uint32_t)0x00000000U) /*!< Transfer is done to 1 register starting from the DMA burst base address */ |
AnnaBridge | 167:84c0a372a020 | 649 | #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */ |
AnnaBridge | 167:84c0a372a020 | 650 | #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */ |
AnnaBridge | 167:84c0a372a020 | 651 | #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */ |
AnnaBridge | 167:84c0a372a020 | 652 | #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */ |
AnnaBridge | 167:84c0a372a020 | 653 | #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */ |
AnnaBridge | 167:84c0a372a020 | 654 | #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */ |
AnnaBridge | 167:84c0a372a020 | 655 | #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */ |
AnnaBridge | 167:84c0a372a020 | 656 | #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */ |
AnnaBridge | 167:84c0a372a020 | 657 | #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */ |
AnnaBridge | 167:84c0a372a020 | 658 | #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */ |
AnnaBridge | 167:84c0a372a020 | 659 | #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */ |
AnnaBridge | 167:84c0a372a020 | 660 | #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */ |
AnnaBridge | 167:84c0a372a020 | 661 | #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */ |
AnnaBridge | 167:84c0a372a020 | 662 | #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */ |
AnnaBridge | 167:84c0a372a020 | 663 | #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */ |
AnnaBridge | 167:84c0a372a020 | 664 | #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */ |
AnnaBridge | 167:84c0a372a020 | 665 | #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */ |
AnnaBridge | 143:86740a56073b | 666 | /** |
AnnaBridge | 143:86740a56073b | 667 | * @} |
AnnaBridge | 143:86740a56073b | 668 | */ |
AnnaBridge | 143:86740a56073b | 669 | |
AnnaBridge | 143:86740a56073b | 670 | |
AnnaBridge | 167:84c0a372a020 | 671 | /** @defgroup TIM_LL_EC_TIM2_ETR_RMP TIM2 External Trigger Remap |
AnnaBridge | 143:86740a56073b | 672 | * @{ |
AnnaBridge | 143:86740a56073b | 673 | */ |
AnnaBridge | 167:84c0a372a020 | 674 | #define LL_TIM_TIM2_ETR_RMP_GPIO ((uint32_t)0x00000000U | TIM2_OR_RMP_MASK) /*!< TIM2_ETR is connected to Ored GPIO */ |
AnnaBridge | 143:86740a56073b | 675 | #if defined(TIM_TIM2_REMAP_HSI_SUPPORT) |
AnnaBridge | 167:84c0a372a020 | 676 | #define LL_TIM_TIM2_ETR_RMP_HSI (TIM2_OR_ETR_RMP_1 | TIM2_OR_ETR_RMP_0 | TIM2_OR_RMP_MASK) /*!< TIM2_ETR is connected to HSI */ |
AnnaBridge | 143:86740a56073b | 677 | #endif /* defined(TIM_TIM2_REMAP_HSI_SUPPORT) */ |
AnnaBridge | 143:86740a56073b | 678 | #if defined(TIM_TIM2_REMAP_HSI48_SUPPORT) |
AnnaBridge | 167:84c0a372a020 | 679 | #define LL_TIM_TIM2_ETR_RMP_HSI48 (TIM2_OR_ETR_RMP_2 | TIM2_OR_RMP_MASK) /*!< TIM2_ETR is connected to HSI48 */ |
AnnaBridge | 143:86740a56073b | 680 | #endif /* defined(TIM_TIM2_REMAP_HSI48_SUPPORT) */ |
AnnaBridge | 167:84c0a372a020 | 681 | #define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0 | TIM2_OR_RMP_MASK) /*!< TIM2_ETR is connected to LSE */ |
AnnaBridge | 167:84c0a372a020 | 682 | #define LL_TIM_TIM2_ETR_RMP_COMP2 (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1 | TIM2_OR_RMP_MASK) /*!< TIM2_ETR is connected to COMP2_OUT */ |
AnnaBridge | 167:84c0a372a020 | 683 | #define LL_TIM_TIM2_ETR_RMP_COMP1 (TIM2_OR_ETR_RMP | TIM2_OR_RMP_MASK) /*!< TIM2_ETR is connected to COMP1_OUT */ |
AnnaBridge | 143:86740a56073b | 684 | |
AnnaBridge | 143:86740a56073b | 685 | /** |
AnnaBridge | 143:86740a56073b | 686 | * @} |
AnnaBridge | 143:86740a56073b | 687 | */ |
AnnaBridge | 167:84c0a372a020 | 688 | |
AnnaBridge | 143:86740a56073b | 689 | /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 Timer Input Ch4 Remap |
AnnaBridge | 143:86740a56073b | 690 | * @{ |
AnnaBridge | 143:86740a56073b | 691 | */ |
AnnaBridge | 167:84c0a372a020 | 692 | #define LL_TIM_TIM2_TI4_RMP_GPIO ((uint32_t)0x00000000U | TIM2_OR_RMP_MASK) /*!< TIM2 input capture 4 is connected to GPIO */ |
AnnaBridge | 167:84c0a372a020 | 693 | #define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR_TI4_RMP_0 | TIM2_OR_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP2_OUT */ |
AnnaBridge | 167:84c0a372a020 | 694 | #define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR_TI4_RMP_1 | TIM2_OR_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP1_OUT */ |
AnnaBridge | 143:86740a56073b | 695 | /** |
AnnaBridge | 143:86740a56073b | 696 | * @} |
AnnaBridge | 143:86740a56073b | 697 | */ |
AnnaBridge | 143:86740a56073b | 698 | |
AnnaBridge | 143:86740a56073b | 699 | #if defined(TIM3_OR_ETR_RMP) |
AnnaBridge | 167:84c0a372a020 | 700 | /** @defgroup TIM_LL_EC_TIM3_ETR_RMP TIM3 External Trigger Remap |
AnnaBridge | 143:86740a56073b | 701 | * @{ |
AnnaBridge | 143:86740a56073b | 702 | */ |
AnnaBridge | 167:84c0a372a020 | 703 | #define LL_TIM_TIM3_ETR_RMP_GPIO ((uint32_t)0x00000000U | TIM3_OR_RMP_MASK) /*!< TIM3_ETR is connected to GPIO */ |
AnnaBridge | 167:84c0a372a020 | 704 | #define LL_TIM_TIM3_ETR_RMP_HSI48DIV6 (TIM3_OR_ETR_RMP_1 | TIM3_OR_RMP_MASK) /*!< TIM3_ETR is connected to HSI48 divided by 6 */ |
AnnaBridge | 143:86740a56073b | 705 | /** |
AnnaBridge | 143:86740a56073b | 706 | * @} |
AnnaBridge | 143:86740a56073b | 707 | */ |
AnnaBridge | 167:84c0a372a020 | 708 | #endif /* defined(TIM3_OR_ETR_RMP) */ |
AnnaBridge | 167:84c0a372a020 | 709 | |
AnnaBridge | 167:84c0a372a020 | 710 | #if defined(TIM3_OR_TI1_RMP) || defined(TIM3_OR_TI2_RMP) || defined(TIM3_OR_TI4_RMP) |
AnnaBridge | 143:86740a56073b | 711 | /** @defgroup TIM_LL_EC_TIM3_TI_RMP TIM3 External Inputs Remap |
AnnaBridge | 143:86740a56073b | 712 | * @{ |
AnnaBridge | 143:86740a56073b | 713 | */ |
AnnaBridge | 167:84c0a372a020 | 714 | #define LL_TIM_TIM3_TI_RMP_TI1_USB_SOF ((uint32_t)0x00000000U | TIM3_OR_RMP_MASK) /*!< TIM3_TI1 input is connected to USB_SOF */ |
AnnaBridge | 167:84c0a372a020 | 715 | #define LL_TIM_TIM3_TI_RMP_TI1_GPIO (TIM3_OR_TI1_RMP | TIM3_OR_RMP_MASK) /*!< TIM3_TI1 input is connected to PE3, PA6, PC6 or PB4 */ |
AnnaBridge | 167:84c0a372a020 | 716 | |
AnnaBridge | 167:84c0a372a020 | 717 | #define LL_TIM_TIM3_TI_RMP_TI2_GPIO_DEF ((uint32_t)0x00000000U | TIM3_OR_RMP_MASK) /*!< Mapping PB5 to TIM22_CH2 */ |
AnnaBridge | 167:84c0a372a020 | 718 | #define LL_TIM_TIM3_TI_RMP_TI2_GPIOB5_AF4 (TIM3_OR_TI2_RMP | TIM3_OR_RMP_MASK) /*!< Mapping PB5 to TIM3_CH2 */ |
AnnaBridge | 167:84c0a372a020 | 719 | |
AnnaBridge | 167:84c0a372a020 | 720 | #define LL_TIM_TIM3_TI_RMP_TI4_GPIO_DEF ((uint32_t)0x00000000U | TIM3_OR_RMP_MASK) /*!< Mapping PC9 to USB_OE */ |
AnnaBridge | 167:84c0a372a020 | 721 | #define LL_TIM_TIM3_TI_RMP_TI4_GPIOC9_AF2 (TIM3_OR_TI4_RMP | TIM3_OR_RMP_MASK) /*!< Mapping PC9 to TIM3_CH4 */ |
AnnaBridge | 143:86740a56073b | 722 | /** |
AnnaBridge | 143:86740a56073b | 723 | * @} |
AnnaBridge | 143:86740a56073b | 724 | */ |
AnnaBridge | 143:86740a56073b | 725 | #endif /*defined(TIM3_OR_TI1_RMP) or defined(TIM3_OR_TI2_RMP) or defined(TIM3_OR_TI4_RMP)*/ |
AnnaBridge | 143:86740a56073b | 726 | |
AnnaBridge | 167:84c0a372a020 | 727 | /** @defgroup TIM_LL_EC_TIM21_ETR_RMP TIM21 External Trigger Remap |
AnnaBridge | 143:86740a56073b | 728 | * @{ |
AnnaBridge | 143:86740a56073b | 729 | */ |
AnnaBridge | 167:84c0a372a020 | 730 | #define LL_TIM_TIM21_ETR_RMP_GPIO ((uint32_t)0x00000000U | TIM21_OR_RMP_MASK) /*!< TIM21_ETR is connected to Ored GPIO1 */ |
AnnaBridge | 167:84c0a372a020 | 731 | #define LL_TIM_TIM21_ETR_RMP_COMP2 (TIM21_OR_ETR_RMP_0 | TIM21_OR_RMP_MASK) /*!< TIM21_ETR is connected to COMP2_OUT */ |
AnnaBridge | 167:84c0a372a020 | 732 | #define LL_TIM_TIM21_ETR_RMP_COMP1 (TIM21_OR_ETR_RMP_1 | TIM21_OR_RMP_MASK) /*!< TIM21_ETR is connected to COMP1_OUT */ |
AnnaBridge | 167:84c0a372a020 | 733 | #define LL_TIM_TIM21_ETR_RMP_LSE (TIM21_OR_ETR_RMP | TIM21_OR_RMP_MASK) /*!< TIM21_ETR is connected to LSE */ |
AnnaBridge | 143:86740a56073b | 734 | /** |
AnnaBridge | 143:86740a56073b | 735 | * @} |
AnnaBridge | 143:86740a56073b | 736 | */ |
AnnaBridge | 143:86740a56073b | 737 | |
AnnaBridge | 167:84c0a372a020 | 738 | /** @defgroup TIM_LL_EC_TIM21_TI1_RMP TIM21 External Input Ch1 Remap |
AnnaBridge | 143:86740a56073b | 739 | * @{ |
AnnaBridge | 143:86740a56073b | 740 | */ |
AnnaBridge | 167:84c0a372a020 | 741 | #define LL_TIM_TIM21_TI1_RMP_GPIO ((uint32_t)0x00000000U | TIM21_OR_RMP_MASK) /*!< TIM21_TI1 is connected to Ored GPIO1 */ |
AnnaBridge | 167:84c0a372a020 | 742 | #define LL_TIM_TIM21_TI1_RMP_RTC_WK (TIM21_OR_TI1_RMP_0 | TIM21_OR_RMP_MASK) /*!< TIM21_TI1 is connected to RTC_WAKEUP */ |
AnnaBridge | 167:84c0a372a020 | 743 | #define LL_TIM_TIM21_TI1_RMP_HSE_RTC (TIM21_OR_TI1_RMP_1 | TIM21_OR_RMP_MASK) /*!< TIM21_TI1 is connected to HSE_RTC */ |
AnnaBridge | 167:84c0a372a020 | 744 | #define LL_TIM_TIM21_TI1_RMP_MSI (TIM21_OR_TI1_RMP_1 | TIM21_OR_TI1_RMP_0 | TIM21_OR_RMP_MASK) /*!< TIM21_TI1 is connected to MSI */ |
AnnaBridge | 167:84c0a372a020 | 745 | #define LL_TIM_TIM21_TI1_RMP_LSE (TIM21_OR_TI1_RMP_2 | TIM21_OR_RMP_MASK) /*!< TIM21_TI1 is connected to LSE */ |
AnnaBridge | 167:84c0a372a020 | 746 | #define LL_TIM_TIM21_TI1_RMP_LSI (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_0 | TIM21_OR_RMP_MASK) /*!< TIM21_TI1 is connected to LSI */ |
AnnaBridge | 167:84c0a372a020 | 747 | #define LL_TIM_TIM21_TI1_RMP_COMP1 (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_1 | TIM21_OR_RMP_MASK) /*!< TIM21_TI1 is connected to COMP1_OUT */ |
AnnaBridge | 167:84c0a372a020 | 748 | #define LL_TIM_TIM21_TI1_RMP_MCO (TIM21_OR_TI1_RMP | TIM21_OR_RMP_MASK) /*!< TIM21_TI1 is connected to MCO */ |
AnnaBridge | 143:86740a56073b | 749 | /** |
AnnaBridge | 143:86740a56073b | 750 | * @} |
AnnaBridge | 143:86740a56073b | 751 | */ |
AnnaBridge | 143:86740a56073b | 752 | |
AnnaBridge | 167:84c0a372a020 | 753 | /** @defgroup TIM_LL_EC_TIM21_TI2_RMP TIM21 External Input Ch2 Remap |
AnnaBridge | 143:86740a56073b | 754 | * @{ |
AnnaBridge | 143:86740a56073b | 755 | */ |
AnnaBridge | 167:84c0a372a020 | 756 | #define LL_TIM_TIM21_TI2_RMP_GPIO ((uint32_t)0x00000000U | TIM21_OR_RMP_MASK) /*!< TIM21_TI2 is connected to Ored GPIO1 */ |
AnnaBridge | 167:84c0a372a020 | 757 | #define LL_TIM_TIM21_TI2_RMP_COMP2 (TIM21_OR_TI2_RMP | TIM21_OR_RMP_MASK) /*!< TIM21_TI2 is connected to COMP2_OUT */ |
AnnaBridge | 143:86740a56073b | 758 | /** |
AnnaBridge | 143:86740a56073b | 759 | * @} |
AnnaBridge | 143:86740a56073b | 760 | */ |
AnnaBridge | 143:86740a56073b | 761 | |
AnnaBridge | 167:84c0a372a020 | 762 | #if defined(TIM22_OR_ETR_RMP) |
AnnaBridge | 167:84c0a372a020 | 763 | |
AnnaBridge | 167:84c0a372a020 | 764 | /** @defgroup TIM_LL_EC_TIM22_ETR_RMP TIM22 External Trigger Remap |
AnnaBridge | 143:86740a56073b | 765 | * @{ |
AnnaBridge | 143:86740a56073b | 766 | */ |
AnnaBridge | 167:84c0a372a020 | 767 | #define LL_TIM_TIM22_ETR_RMP_GPIO ((uint32_t)0x00000000U | TIM22_OR_RMP_MASK) /*!< TIM22_ETR is connected to GPIO */ |
AnnaBridge | 167:84c0a372a020 | 768 | #define LL_TIM_TIM22_ETR_RMP_COMP2 (TIM22_OR_ETR_RMP_0 | TIM22_OR_RMP_MASK) /*!< TIM22_ETR is connected to COMP2_OUT */ |
AnnaBridge | 167:84c0a372a020 | 769 | #define LL_TIM_TIM22_ETR_RMP_COMP1 (TIM22_OR_ETR_RMP_1 | TIM22_OR_RMP_MASK) /*!< TIM22_ETR is connected to COMP1_OUT */ |
AnnaBridge | 167:84c0a372a020 | 770 | #define LL_TIM_TIM22_ETR_RMP_LSE (TIM22_OR_ETR_RMP | TIM22_OR_RMP_MASK) /*!< TIM22_ETR is connected to LSE */ |
AnnaBridge | 143:86740a56073b | 771 | /** |
AnnaBridge | 143:86740a56073b | 772 | * @} |
AnnaBridge | 143:86740a56073b | 773 | */ |
AnnaBridge | 167:84c0a372a020 | 774 | #endif /* defined(TIM22_OR_ETR_RMP) */ |
AnnaBridge | 167:84c0a372a020 | 775 | |
AnnaBridge | 167:84c0a372a020 | 776 | #if defined(TIM22_OR_TI1_RMP) |
AnnaBridge | 167:84c0a372a020 | 777 | /** @defgroup TIM_LL_EC_TIM22_TI1_RMP TIM22 External Input Ch1 Remap |
AnnaBridge | 143:86740a56073b | 778 | * @{ |
AnnaBridge | 143:86740a56073b | 779 | */ |
AnnaBridge | 167:84c0a372a020 | 780 | #define LL_TIM_TIM22_TI1_RMP_GPIO1 ((uint32_t)0x00000000U | TIM22_OR_RMP_MASK) /*!< TIM22_TI1 is connected to GPIO1 */ |
AnnaBridge | 167:84c0a372a020 | 781 | #define LL_TIM_TIM22_TI1_RMP_COMP2 (TIM22_OR_TI1_RMP_0 | TIM22_OR_RMP_MASK) /*!< TIM22_TI1 is connected to COMP2_OUT */ |
AnnaBridge | 167:84c0a372a020 | 782 | #define LL_TIM_TIM22_TI1_RMP_COMP1 (TIM22_OR_TI1_RMP_1 | TIM22_OR_RMP_MASK) /*!< TIM22_TI1 is connected to COMP1_OUT */ |
AnnaBridge | 167:84c0a372a020 | 783 | #define LL_TIM_TIM22_TI1_RMP_GPIO2 (TIM22_OR_TI1_RMP | TIM22_OR_RMP_MASK) /*!< TIM22_TI1 is connected to GPIO2 */ |
AnnaBridge | 143:86740a56073b | 784 | /** |
AnnaBridge | 143:86740a56073b | 785 | * @} |
AnnaBridge | 143:86740a56073b | 786 | */ |
AnnaBridge | 167:84c0a372a020 | 787 | #endif /* defined(TIM22_OR_TI1_RMP) */ |
AnnaBridge | 143:86740a56073b | 788 | |
AnnaBridge | 143:86740a56073b | 789 | |
AnnaBridge | 143:86740a56073b | 790 | /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection |
AnnaBridge | 143:86740a56073b | 791 | * @{ |
AnnaBridge | 143:86740a56073b | 792 | */ |
AnnaBridge | 167:84c0a372a020 | 793 | #define LL_TIM_OCREF_CLR_INT_NC ((uint32_t)0x00000000U ) /*!< OCREF_CLR_INT is not connected */ |
AnnaBridge | 167:84c0a372a020 | 794 | #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */ |
AnnaBridge | 143:86740a56073b | 795 | /** |
AnnaBridge | 143:86740a56073b | 796 | * @} |
AnnaBridge | 143:86740a56073b | 797 | */ |
AnnaBridge | 143:86740a56073b | 798 | |
AnnaBridge | 143:86740a56073b | 799 | /** |
AnnaBridge | 143:86740a56073b | 800 | * @} |
AnnaBridge | 143:86740a56073b | 801 | */ |
AnnaBridge | 167:84c0a372a020 | 802 | |
AnnaBridge | 143:86740a56073b | 803 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 804 | /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros |
AnnaBridge | 143:86740a56073b | 805 | * @{ |
AnnaBridge | 143:86740a56073b | 806 | */ |
AnnaBridge | 143:86740a56073b | 807 | |
AnnaBridge | 143:86740a56073b | 808 | /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros |
AnnaBridge | 143:86740a56073b | 809 | * @{ |
AnnaBridge | 143:86740a56073b | 810 | */ |
AnnaBridge | 143:86740a56073b | 811 | /** |
AnnaBridge | 143:86740a56073b | 812 | * @brief Write a value in TIM register. |
AnnaBridge | 143:86740a56073b | 813 | * @param __INSTANCE__ TIM Instance |
AnnaBridge | 143:86740a56073b | 814 | * @param __REG__ Register to be written |
AnnaBridge | 143:86740a56073b | 815 | * @param __VALUE__ Value to be written in the register |
AnnaBridge | 143:86740a56073b | 816 | * @retval None |
AnnaBridge | 143:86740a56073b | 817 | */ |
AnnaBridge | 143:86740a56073b | 818 | #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
AnnaBridge | 143:86740a56073b | 819 | |
AnnaBridge | 143:86740a56073b | 820 | /** |
AnnaBridge | 143:86740a56073b | 821 | * @brief Read a value in TIM register. |
AnnaBridge | 143:86740a56073b | 822 | * @param __INSTANCE__ TIM Instance |
AnnaBridge | 143:86740a56073b | 823 | * @param __REG__ Register to be read |
AnnaBridge | 143:86740a56073b | 824 | * @retval Register value |
AnnaBridge | 143:86740a56073b | 825 | */ |
AnnaBridge | 143:86740a56073b | 826 | #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
AnnaBridge | 143:86740a56073b | 827 | /** |
AnnaBridge | 143:86740a56073b | 828 | * @} |
AnnaBridge | 143:86740a56073b | 829 | */ |
AnnaBridge | 143:86740a56073b | 830 | |
AnnaBridge | 143:86740a56073b | 831 | /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros |
AnnaBridge | 143:86740a56073b | 832 | * @{ |
AnnaBridge | 143:86740a56073b | 833 | */ |
AnnaBridge | 143:86740a56073b | 834 | |
AnnaBridge | 143:86740a56073b | 835 | |
AnnaBridge | 143:86740a56073b | 836 | /** |
AnnaBridge | 143:86740a56073b | 837 | * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. |
AnnaBridge | 143:86740a56073b | 838 | * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); |
AnnaBridge | 143:86740a56073b | 839 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
AnnaBridge | 143:86740a56073b | 840 | * @param __CNTCLK__ counter clock frequency (in Hz) |
AnnaBridge | 143:86740a56073b | 841 | * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 143:86740a56073b | 842 | */ |
AnnaBridge | 143:86740a56073b | 843 | #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ |
AnnaBridge | 143:86740a56073b | 844 | ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U |
AnnaBridge | 143:86740a56073b | 845 | |
AnnaBridge | 143:86740a56073b | 846 | /** |
AnnaBridge | 143:86740a56073b | 847 | * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. |
AnnaBridge | 143:86740a56073b | 848 | * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); |
AnnaBridge | 143:86740a56073b | 849 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
AnnaBridge | 143:86740a56073b | 850 | * @param __PSC__ prescaler |
AnnaBridge | 143:86740a56073b | 851 | * @param __FREQ__ output signal frequency (in Hz) |
AnnaBridge | 143:86740a56073b | 852 | * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 143:86740a56073b | 853 | */ |
AnnaBridge | 143:86740a56073b | 854 | #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ |
AnnaBridge | 143:86740a56073b | 855 | (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U |
AnnaBridge | 143:86740a56073b | 856 | |
AnnaBridge | 143:86740a56073b | 857 | /** |
AnnaBridge | 143:86740a56073b | 858 | * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. |
AnnaBridge | 143:86740a56073b | 859 | * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); |
AnnaBridge | 143:86740a56073b | 860 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
AnnaBridge | 143:86740a56073b | 861 | * @param __PSC__ prescaler |
AnnaBridge | 143:86740a56073b | 862 | * @param __DELAY__ timer output compare active/inactive delay (in us) |
AnnaBridge | 143:86740a56073b | 863 | * @retval Compare value (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 143:86740a56073b | 864 | */ |
AnnaBridge | 143:86740a56073b | 865 | #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ |
AnnaBridge | 143:86740a56073b | 866 | ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ |
AnnaBridge | 143:86740a56073b | 867 | / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) |
AnnaBridge | 143:86740a56073b | 868 | |
AnnaBridge | 143:86740a56073b | 869 | /** |
AnnaBridge | 143:86740a56073b | 870 | * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). |
AnnaBridge | 143:86740a56073b | 871 | * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); |
AnnaBridge | 143:86740a56073b | 872 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
AnnaBridge | 143:86740a56073b | 873 | * @param __PSC__ prescaler |
AnnaBridge | 143:86740a56073b | 874 | * @param __DELAY__ timer output compare active/inactive delay (in us) |
AnnaBridge | 143:86740a56073b | 875 | * @param __PULSE__ pulse duration (in us) |
AnnaBridge | 143:86740a56073b | 876 | * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 143:86740a56073b | 877 | */ |
AnnaBridge | 143:86740a56073b | 878 | #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ |
AnnaBridge | 143:86740a56073b | 879 | ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ |
AnnaBridge | 143:86740a56073b | 880 | + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) |
AnnaBridge | 143:86740a56073b | 881 | |
AnnaBridge | 143:86740a56073b | 882 | /** |
AnnaBridge | 167:84c0a372a020 | 883 | * @brief HELPER macro retrieving the ratio of the input capture prescaler |
AnnaBridge | 143:86740a56073b | 884 | * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); |
AnnaBridge | 143:86740a56073b | 885 | * @param __ICPSC__ This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 886 | * @arg @ref LL_TIM_ICPSC_DIV1 |
AnnaBridge | 143:86740a56073b | 887 | * @arg @ref LL_TIM_ICPSC_DIV2 |
AnnaBridge | 143:86740a56073b | 888 | * @arg @ref LL_TIM_ICPSC_DIV4 |
AnnaBridge | 143:86740a56073b | 889 | * @arg @ref LL_TIM_ICPSC_DIV8 |
AnnaBridge | 143:86740a56073b | 890 | * @retval Input capture prescaler ratio (1, 2, 4 or 8) |
AnnaBridge | 143:86740a56073b | 891 | */ |
AnnaBridge | 143:86740a56073b | 892 | #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ |
AnnaBridge | 167:84c0a372a020 | 893 | ((uint32_t)((uint32_t)0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) |
AnnaBridge | 167:84c0a372a020 | 894 | |
AnnaBridge | 167:84c0a372a020 | 895 | |
AnnaBridge | 143:86740a56073b | 896 | /** |
AnnaBridge | 143:86740a56073b | 897 | * @} |
AnnaBridge | 143:86740a56073b | 898 | */ |
AnnaBridge | 143:86740a56073b | 899 | |
AnnaBridge | 143:86740a56073b | 900 | |
AnnaBridge | 143:86740a56073b | 901 | /** |
AnnaBridge | 143:86740a56073b | 902 | * @} |
AnnaBridge | 143:86740a56073b | 903 | */ |
AnnaBridge | 143:86740a56073b | 904 | |
AnnaBridge | 143:86740a56073b | 905 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 906 | /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions |
AnnaBridge | 143:86740a56073b | 907 | * @{ |
AnnaBridge | 143:86740a56073b | 908 | */ |
AnnaBridge | 167:84c0a372a020 | 909 | |
AnnaBridge | 143:86740a56073b | 910 | /** @defgroup TIM_LL_EF_Time_Base Time Base configuration |
AnnaBridge | 143:86740a56073b | 911 | * @{ |
AnnaBridge | 143:86740a56073b | 912 | */ |
AnnaBridge | 143:86740a56073b | 913 | /** |
AnnaBridge | 143:86740a56073b | 914 | * @brief Enable timer counter. |
AnnaBridge | 143:86740a56073b | 915 | * @rmtoll CR1 CEN LL_TIM_EnableCounter |
AnnaBridge | 143:86740a56073b | 916 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 917 | * @retval None |
AnnaBridge | 143:86740a56073b | 918 | */ |
AnnaBridge | 167:84c0a372a020 | 919 | __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 920 | { |
AnnaBridge | 143:86740a56073b | 921 | SET_BIT(TIMx->CR1, TIM_CR1_CEN); |
AnnaBridge | 143:86740a56073b | 922 | } |
AnnaBridge | 143:86740a56073b | 923 | |
AnnaBridge | 143:86740a56073b | 924 | /** |
AnnaBridge | 143:86740a56073b | 925 | * @brief Disable timer counter. |
AnnaBridge | 143:86740a56073b | 926 | * @rmtoll CR1 CEN LL_TIM_DisableCounter |
AnnaBridge | 143:86740a56073b | 927 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 928 | * @retval None |
AnnaBridge | 143:86740a56073b | 929 | */ |
AnnaBridge | 167:84c0a372a020 | 930 | __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 931 | { |
AnnaBridge | 143:86740a56073b | 932 | CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); |
AnnaBridge | 143:86740a56073b | 933 | } |
AnnaBridge | 143:86740a56073b | 934 | |
AnnaBridge | 143:86740a56073b | 935 | /** |
AnnaBridge | 143:86740a56073b | 936 | * @brief Indicates whether the timer counter is enabled. |
AnnaBridge | 143:86740a56073b | 937 | * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter |
AnnaBridge | 143:86740a56073b | 938 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 939 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 940 | */ |
AnnaBridge | 167:84c0a372a020 | 941 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 942 | { |
AnnaBridge | 143:86740a56073b | 943 | return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)); |
AnnaBridge | 143:86740a56073b | 944 | } |
AnnaBridge | 143:86740a56073b | 945 | |
AnnaBridge | 143:86740a56073b | 946 | /** |
AnnaBridge | 143:86740a56073b | 947 | * @brief Enable update event generation. |
AnnaBridge | 143:86740a56073b | 948 | * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent |
AnnaBridge | 143:86740a56073b | 949 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 950 | * @retval None |
AnnaBridge | 143:86740a56073b | 951 | */ |
AnnaBridge | 167:84c0a372a020 | 952 | __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 953 | { |
AnnaBridge | 143:86740a56073b | 954 | SET_BIT(TIMx->CR1, TIM_CR1_UDIS); |
AnnaBridge | 143:86740a56073b | 955 | } |
AnnaBridge | 143:86740a56073b | 956 | |
AnnaBridge | 143:86740a56073b | 957 | /** |
AnnaBridge | 143:86740a56073b | 958 | * @brief Disable update event generation. |
AnnaBridge | 143:86740a56073b | 959 | * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent |
AnnaBridge | 143:86740a56073b | 960 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 961 | * @retval None |
AnnaBridge | 143:86740a56073b | 962 | */ |
AnnaBridge | 167:84c0a372a020 | 963 | __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 964 | { |
AnnaBridge | 143:86740a56073b | 965 | CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); |
AnnaBridge | 143:86740a56073b | 966 | } |
AnnaBridge | 143:86740a56073b | 967 | |
AnnaBridge | 143:86740a56073b | 968 | /** |
AnnaBridge | 143:86740a56073b | 969 | * @brief Indicates whether update event generation is enabled. |
AnnaBridge | 143:86740a56073b | 970 | * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent |
AnnaBridge | 143:86740a56073b | 971 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 972 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 973 | */ |
AnnaBridge | 167:84c0a372a020 | 974 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 975 | { |
AnnaBridge | 143:86740a56073b | 976 | return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS)); |
AnnaBridge | 143:86740a56073b | 977 | } |
AnnaBridge | 143:86740a56073b | 978 | |
AnnaBridge | 143:86740a56073b | 979 | /** |
AnnaBridge | 143:86740a56073b | 980 | * @brief Set update event source |
AnnaBridge | 167:84c0a372a020 | 981 | * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events |
AnnaBridge | 143:86740a56073b | 982 | * generate an update interrupt or DMA request if enabled: |
AnnaBridge | 143:86740a56073b | 983 | * - Counter overflow/underflow |
AnnaBridge | 143:86740a56073b | 984 | * - Setting the UG bit |
AnnaBridge | 143:86740a56073b | 985 | * - Update generation through the slave mode controller |
AnnaBridge | 167:84c0a372a020 | 986 | * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter |
AnnaBridge | 143:86740a56073b | 987 | * overflow/underflow generates an update interrupt or DMA request if enabled. |
AnnaBridge | 143:86740a56073b | 988 | * @rmtoll CR1 URS LL_TIM_SetUpdateSource |
AnnaBridge | 143:86740a56073b | 989 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 990 | * @param UpdateSource This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 991 | * @arg @ref LL_TIM_UPDATESOURCE_REGULAR |
AnnaBridge | 143:86740a56073b | 992 | * @arg @ref LL_TIM_UPDATESOURCE_COUNTER |
AnnaBridge | 143:86740a56073b | 993 | * @retval None |
AnnaBridge | 143:86740a56073b | 994 | */ |
AnnaBridge | 167:84c0a372a020 | 995 | __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) |
AnnaBridge | 143:86740a56073b | 996 | { |
AnnaBridge | 143:86740a56073b | 997 | MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); |
AnnaBridge | 143:86740a56073b | 998 | } |
AnnaBridge | 143:86740a56073b | 999 | |
AnnaBridge | 143:86740a56073b | 1000 | /** |
AnnaBridge | 143:86740a56073b | 1001 | * @brief Get actual event update source |
AnnaBridge | 143:86740a56073b | 1002 | * @rmtoll CR1 URS LL_TIM_GetUpdateSource |
AnnaBridge | 143:86740a56073b | 1003 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1004 | * @retval Returned value can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1005 | * @arg @ref LL_TIM_UPDATESOURCE_REGULAR |
AnnaBridge | 143:86740a56073b | 1006 | * @arg @ref LL_TIM_UPDATESOURCE_COUNTER |
AnnaBridge | 143:86740a56073b | 1007 | */ |
AnnaBridge | 167:84c0a372a020 | 1008 | __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 1009 | { |
AnnaBridge | 143:86740a56073b | 1010 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); |
AnnaBridge | 143:86740a56073b | 1011 | } |
AnnaBridge | 143:86740a56073b | 1012 | |
AnnaBridge | 143:86740a56073b | 1013 | /** |
AnnaBridge | 143:86740a56073b | 1014 | * @brief Set one pulse mode (one shot v.s. repetitive). |
AnnaBridge | 143:86740a56073b | 1015 | * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode |
AnnaBridge | 143:86740a56073b | 1016 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1017 | * @param OnePulseMode This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1018 | * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE |
AnnaBridge | 143:86740a56073b | 1019 | * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE |
AnnaBridge | 143:86740a56073b | 1020 | * @retval None |
AnnaBridge | 143:86740a56073b | 1021 | */ |
AnnaBridge | 167:84c0a372a020 | 1022 | __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) |
AnnaBridge | 143:86740a56073b | 1023 | { |
AnnaBridge | 143:86740a56073b | 1024 | MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); |
AnnaBridge | 143:86740a56073b | 1025 | } |
AnnaBridge | 143:86740a56073b | 1026 | |
AnnaBridge | 143:86740a56073b | 1027 | /** |
AnnaBridge | 143:86740a56073b | 1028 | * @brief Get actual one pulse mode. |
AnnaBridge | 143:86740a56073b | 1029 | * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode |
AnnaBridge | 143:86740a56073b | 1030 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1031 | * @retval Returned value can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1032 | * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE |
AnnaBridge | 143:86740a56073b | 1033 | * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE |
AnnaBridge | 143:86740a56073b | 1034 | */ |
AnnaBridge | 167:84c0a372a020 | 1035 | __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 1036 | { |
AnnaBridge | 143:86740a56073b | 1037 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); |
AnnaBridge | 143:86740a56073b | 1038 | } |
AnnaBridge | 143:86740a56073b | 1039 | |
AnnaBridge | 143:86740a56073b | 1040 | /** |
AnnaBridge | 143:86740a56073b | 1041 | * @brief Set the timer counter counting mode. |
AnnaBridge | 143:86740a56073b | 1042 | * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to |
AnnaBridge | 167:84c0a372a020 | 1043 | * check whether or not the counter mode selection feature is supported |
AnnaBridge | 143:86740a56073b | 1044 | * by a timer instance. |
AnnaBridge | 143:86740a56073b | 1045 | * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n |
AnnaBridge | 143:86740a56073b | 1046 | * CR1 CMS LL_TIM_SetCounterMode |
AnnaBridge | 143:86740a56073b | 1047 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1048 | * @param CounterMode This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1049 | * @arg @ref LL_TIM_COUNTERMODE_UP |
AnnaBridge | 143:86740a56073b | 1050 | * @arg @ref LL_TIM_COUNTERMODE_DOWN |
AnnaBridge | 143:86740a56073b | 1051 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP |
AnnaBridge | 143:86740a56073b | 1052 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN |
AnnaBridge | 143:86740a56073b | 1053 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN |
AnnaBridge | 143:86740a56073b | 1054 | * @retval None |
AnnaBridge | 143:86740a56073b | 1055 | */ |
AnnaBridge | 167:84c0a372a020 | 1056 | __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) |
AnnaBridge | 143:86740a56073b | 1057 | { |
AnnaBridge | 143:86740a56073b | 1058 | MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode); |
AnnaBridge | 143:86740a56073b | 1059 | } |
AnnaBridge | 143:86740a56073b | 1060 | |
AnnaBridge | 143:86740a56073b | 1061 | /** |
AnnaBridge | 143:86740a56073b | 1062 | * @brief Get actual counter mode. |
AnnaBridge | 143:86740a56073b | 1063 | * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to |
AnnaBridge | 167:84c0a372a020 | 1064 | * check whether or not the counter mode selection feature is supported |
AnnaBridge | 143:86740a56073b | 1065 | * by a timer instance. |
AnnaBridge | 143:86740a56073b | 1066 | * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n |
AnnaBridge | 143:86740a56073b | 1067 | * CR1 CMS LL_TIM_GetCounterMode |
AnnaBridge | 143:86740a56073b | 1068 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1069 | * @retval Returned value can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1070 | * @arg @ref LL_TIM_COUNTERMODE_UP |
AnnaBridge | 143:86740a56073b | 1071 | * @arg @ref LL_TIM_COUNTERMODE_DOWN |
AnnaBridge | 143:86740a56073b | 1072 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP |
AnnaBridge | 143:86740a56073b | 1073 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN |
AnnaBridge | 143:86740a56073b | 1074 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN |
AnnaBridge | 143:86740a56073b | 1075 | */ |
AnnaBridge | 167:84c0a372a020 | 1076 | __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 1077 | { |
AnnaBridge | 143:86740a56073b | 1078 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS)); |
AnnaBridge | 143:86740a56073b | 1079 | } |
AnnaBridge | 143:86740a56073b | 1080 | |
AnnaBridge | 143:86740a56073b | 1081 | /** |
AnnaBridge | 143:86740a56073b | 1082 | * @brief Enable auto-reload (ARR) preload. |
AnnaBridge | 143:86740a56073b | 1083 | * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload |
AnnaBridge | 143:86740a56073b | 1084 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1085 | * @retval None |
AnnaBridge | 143:86740a56073b | 1086 | */ |
AnnaBridge | 167:84c0a372a020 | 1087 | __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 1088 | { |
AnnaBridge | 143:86740a56073b | 1089 | SET_BIT(TIMx->CR1, TIM_CR1_ARPE); |
AnnaBridge | 143:86740a56073b | 1090 | } |
AnnaBridge | 143:86740a56073b | 1091 | |
AnnaBridge | 143:86740a56073b | 1092 | /** |
AnnaBridge | 143:86740a56073b | 1093 | * @brief Disable auto-reload (ARR) preload. |
AnnaBridge | 143:86740a56073b | 1094 | * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload |
AnnaBridge | 143:86740a56073b | 1095 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1096 | * @retval None |
AnnaBridge | 143:86740a56073b | 1097 | */ |
AnnaBridge | 167:84c0a372a020 | 1098 | __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 1099 | { |
AnnaBridge | 143:86740a56073b | 1100 | CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); |
AnnaBridge | 143:86740a56073b | 1101 | } |
AnnaBridge | 143:86740a56073b | 1102 | |
AnnaBridge | 143:86740a56073b | 1103 | /** |
AnnaBridge | 143:86740a56073b | 1104 | * @brief Indicates whether auto-reload (ARR) preload is enabled. |
AnnaBridge | 143:86740a56073b | 1105 | * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload |
AnnaBridge | 143:86740a56073b | 1106 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1107 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 1108 | */ |
AnnaBridge | 167:84c0a372a020 | 1109 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 1110 | { |
AnnaBridge | 143:86740a56073b | 1111 | return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)); |
AnnaBridge | 143:86740a56073b | 1112 | } |
AnnaBridge | 143:86740a56073b | 1113 | |
AnnaBridge | 143:86740a56073b | 1114 | /** |
AnnaBridge | 143:86740a56073b | 1115 | * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. |
AnnaBridge | 167:84c0a372a020 | 1116 | * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check |
AnnaBridge | 143:86740a56073b | 1117 | * whether or not the clock division feature is supported by the timer |
AnnaBridge | 143:86740a56073b | 1118 | * instance. |
AnnaBridge | 143:86740a56073b | 1119 | * @rmtoll CR1 CKD LL_TIM_SetClockDivision |
AnnaBridge | 143:86740a56073b | 1120 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1121 | * @param ClockDivision This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1122 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
AnnaBridge | 143:86740a56073b | 1123 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
AnnaBridge | 143:86740a56073b | 1124 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
AnnaBridge | 143:86740a56073b | 1125 | * @retval None |
AnnaBridge | 143:86740a56073b | 1126 | */ |
AnnaBridge | 167:84c0a372a020 | 1127 | __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) |
AnnaBridge | 143:86740a56073b | 1128 | { |
AnnaBridge | 143:86740a56073b | 1129 | MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); |
AnnaBridge | 143:86740a56073b | 1130 | } |
AnnaBridge | 143:86740a56073b | 1131 | |
AnnaBridge | 143:86740a56073b | 1132 | /** |
AnnaBridge | 143:86740a56073b | 1133 | * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. |
AnnaBridge | 167:84c0a372a020 | 1134 | * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check |
AnnaBridge | 143:86740a56073b | 1135 | * whether or not the clock division feature is supported by the timer |
AnnaBridge | 143:86740a56073b | 1136 | * instance. |
AnnaBridge | 143:86740a56073b | 1137 | * @rmtoll CR1 CKD LL_TIM_GetClockDivision |
AnnaBridge | 143:86740a56073b | 1138 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1139 | * @retval Returned value can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1140 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
AnnaBridge | 143:86740a56073b | 1141 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
AnnaBridge | 143:86740a56073b | 1142 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
AnnaBridge | 143:86740a56073b | 1143 | */ |
AnnaBridge | 167:84c0a372a020 | 1144 | __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 1145 | { |
AnnaBridge | 143:86740a56073b | 1146 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); |
AnnaBridge | 143:86740a56073b | 1147 | } |
AnnaBridge | 143:86740a56073b | 1148 | |
AnnaBridge | 143:86740a56073b | 1149 | /** |
AnnaBridge | 143:86740a56073b | 1150 | * @brief Set the counter value. |
AnnaBridge | 143:86740a56073b | 1151 | * @rmtoll CNT CNT LL_TIM_SetCounter |
AnnaBridge | 143:86740a56073b | 1152 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1153 | * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF) |
AnnaBridge | 143:86740a56073b | 1154 | * @retval None |
AnnaBridge | 143:86740a56073b | 1155 | */ |
AnnaBridge | 167:84c0a372a020 | 1156 | __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) |
AnnaBridge | 143:86740a56073b | 1157 | { |
AnnaBridge | 143:86740a56073b | 1158 | WRITE_REG(TIMx->CNT, Counter); |
AnnaBridge | 143:86740a56073b | 1159 | } |
AnnaBridge | 143:86740a56073b | 1160 | |
AnnaBridge | 143:86740a56073b | 1161 | /** |
AnnaBridge | 143:86740a56073b | 1162 | * @brief Get the counter value. |
AnnaBridge | 143:86740a56073b | 1163 | * @rmtoll CNT CNT LL_TIM_GetCounter |
AnnaBridge | 143:86740a56073b | 1164 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1165 | * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF) |
AnnaBridge | 143:86740a56073b | 1166 | */ |
AnnaBridge | 167:84c0a372a020 | 1167 | __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 1168 | { |
AnnaBridge | 143:86740a56073b | 1169 | return (uint32_t)(READ_REG(TIMx->CNT)); |
AnnaBridge | 143:86740a56073b | 1170 | } |
AnnaBridge | 143:86740a56073b | 1171 | |
AnnaBridge | 143:86740a56073b | 1172 | /** |
AnnaBridge | 143:86740a56073b | 1173 | * @brief Get the current direction of the counter |
AnnaBridge | 143:86740a56073b | 1174 | * @rmtoll CR1 DIR LL_TIM_GetDirection |
AnnaBridge | 143:86740a56073b | 1175 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1176 | * @retval Returned value can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1177 | * @arg @ref LL_TIM_COUNTERDIRECTION_UP |
AnnaBridge | 143:86740a56073b | 1178 | * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN |
AnnaBridge | 143:86740a56073b | 1179 | */ |
AnnaBridge | 167:84c0a372a020 | 1180 | __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 1181 | { |
AnnaBridge | 143:86740a56073b | 1182 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); |
AnnaBridge | 143:86740a56073b | 1183 | } |
AnnaBridge | 143:86740a56073b | 1184 | |
AnnaBridge | 143:86740a56073b | 1185 | /** |
AnnaBridge | 143:86740a56073b | 1186 | * @brief Set the prescaler value. |
AnnaBridge | 143:86740a56073b | 1187 | * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). |
AnnaBridge | 143:86740a56073b | 1188 | * @note The prescaler can be changed on the fly as this control register is buffered. The new |
AnnaBridge | 143:86740a56073b | 1189 | * prescaler ratio is taken into account at the next update event. |
AnnaBridge | 143:86740a56073b | 1190 | * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter |
AnnaBridge | 143:86740a56073b | 1191 | * @rmtoll PSC PSC LL_TIM_SetPrescaler |
AnnaBridge | 143:86740a56073b | 1192 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1193 | * @param Prescaler between Min_Data=0 and Max_Data=65535 |
AnnaBridge | 143:86740a56073b | 1194 | * @retval None |
AnnaBridge | 143:86740a56073b | 1195 | */ |
AnnaBridge | 167:84c0a372a020 | 1196 | __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) |
AnnaBridge | 143:86740a56073b | 1197 | { |
AnnaBridge | 143:86740a56073b | 1198 | WRITE_REG(TIMx->PSC, Prescaler); |
AnnaBridge | 143:86740a56073b | 1199 | } |
AnnaBridge | 143:86740a56073b | 1200 | |
AnnaBridge | 143:86740a56073b | 1201 | /** |
AnnaBridge | 143:86740a56073b | 1202 | * @brief Get the prescaler value. |
AnnaBridge | 143:86740a56073b | 1203 | * @rmtoll PSC PSC LL_TIM_GetPrescaler |
AnnaBridge | 143:86740a56073b | 1204 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1205 | * @retval Prescaler value between Min_Data=0 and Max_Data=65535 |
AnnaBridge | 143:86740a56073b | 1206 | */ |
AnnaBridge | 167:84c0a372a020 | 1207 | __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 1208 | { |
AnnaBridge | 143:86740a56073b | 1209 | return (uint32_t)(READ_REG(TIMx->PSC)); |
AnnaBridge | 143:86740a56073b | 1210 | } |
AnnaBridge | 143:86740a56073b | 1211 | |
AnnaBridge | 143:86740a56073b | 1212 | /** |
AnnaBridge | 143:86740a56073b | 1213 | * @brief Set the auto-reload value. |
AnnaBridge | 143:86740a56073b | 1214 | * @note The counter is blocked while the auto-reload value is null. |
AnnaBridge | 143:86740a56073b | 1215 | * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter |
AnnaBridge | 143:86740a56073b | 1216 | * @rmtoll ARR ARR LL_TIM_SetAutoReload |
AnnaBridge | 143:86740a56073b | 1217 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1218 | * @param AutoReload between Min_Data=0 and Max_Data=65535 |
AnnaBridge | 143:86740a56073b | 1219 | * @retval None |
AnnaBridge | 143:86740a56073b | 1220 | */ |
AnnaBridge | 167:84c0a372a020 | 1221 | __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) |
AnnaBridge | 143:86740a56073b | 1222 | { |
AnnaBridge | 143:86740a56073b | 1223 | WRITE_REG(TIMx->ARR, AutoReload); |
AnnaBridge | 143:86740a56073b | 1224 | } |
AnnaBridge | 143:86740a56073b | 1225 | |
AnnaBridge | 143:86740a56073b | 1226 | /** |
AnnaBridge | 143:86740a56073b | 1227 | * @brief Get the auto-reload value. |
AnnaBridge | 143:86740a56073b | 1228 | * @rmtoll ARR ARR LL_TIM_GetAutoReload |
AnnaBridge | 143:86740a56073b | 1229 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1230 | * @retval Auto-reload value |
AnnaBridge | 143:86740a56073b | 1231 | */ |
AnnaBridge | 167:84c0a372a020 | 1232 | __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 1233 | { |
AnnaBridge | 143:86740a56073b | 1234 | return (uint32_t)(READ_REG(TIMx->ARR)); |
AnnaBridge | 143:86740a56073b | 1235 | } |
AnnaBridge | 143:86740a56073b | 1236 | |
AnnaBridge | 143:86740a56073b | 1237 | /** |
AnnaBridge | 143:86740a56073b | 1238 | * @} |
AnnaBridge | 143:86740a56073b | 1239 | */ |
AnnaBridge | 143:86740a56073b | 1240 | |
AnnaBridge | 143:86740a56073b | 1241 | /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration |
AnnaBridge | 143:86740a56073b | 1242 | * @{ |
AnnaBridge | 143:86740a56073b | 1243 | */ |
AnnaBridge | 143:86740a56073b | 1244 | /** |
AnnaBridge | 143:86740a56073b | 1245 | * @brief Set the trigger of the capture/compare DMA request. |
AnnaBridge | 143:86740a56073b | 1246 | * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger |
AnnaBridge | 143:86740a56073b | 1247 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1248 | * @param DMAReqTrigger This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1249 | * @arg @ref LL_TIM_CCDMAREQUEST_CC |
AnnaBridge | 143:86740a56073b | 1250 | * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE |
AnnaBridge | 143:86740a56073b | 1251 | * @retval None |
AnnaBridge | 143:86740a56073b | 1252 | */ |
AnnaBridge | 167:84c0a372a020 | 1253 | __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) |
AnnaBridge | 143:86740a56073b | 1254 | { |
AnnaBridge | 143:86740a56073b | 1255 | MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); |
AnnaBridge | 143:86740a56073b | 1256 | } |
AnnaBridge | 143:86740a56073b | 1257 | |
AnnaBridge | 143:86740a56073b | 1258 | /** |
AnnaBridge | 143:86740a56073b | 1259 | * @brief Get actual trigger of the capture/compare DMA request. |
AnnaBridge | 143:86740a56073b | 1260 | * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger |
AnnaBridge | 143:86740a56073b | 1261 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1262 | * @retval Returned value can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1263 | * @arg @ref LL_TIM_CCDMAREQUEST_CC |
AnnaBridge | 143:86740a56073b | 1264 | * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE |
AnnaBridge | 143:86740a56073b | 1265 | */ |
AnnaBridge | 167:84c0a372a020 | 1266 | __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 1267 | { |
AnnaBridge | 143:86740a56073b | 1268 | return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); |
AnnaBridge | 143:86740a56073b | 1269 | } |
AnnaBridge | 143:86740a56073b | 1270 | |
AnnaBridge | 143:86740a56073b | 1271 | /** |
AnnaBridge | 143:86740a56073b | 1272 | * @brief Enable capture/compare channels. |
AnnaBridge | 143:86740a56073b | 1273 | * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n |
AnnaBridge | 143:86740a56073b | 1274 | * CCER CC2E LL_TIM_CC_EnableChannel\n |
AnnaBridge | 143:86740a56073b | 1275 | * CCER CC3E LL_TIM_CC_EnableChannel\n |
AnnaBridge | 143:86740a56073b | 1276 | * CCER CC4E LL_TIM_CC_EnableChannel |
AnnaBridge | 143:86740a56073b | 1277 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1278 | * @param Channels This parameter can be a combination of the following values: |
AnnaBridge | 143:86740a56073b | 1279 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1280 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1281 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1282 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1283 | * @retval None |
AnnaBridge | 143:86740a56073b | 1284 | */ |
AnnaBridge | 167:84c0a372a020 | 1285 | __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) |
AnnaBridge | 143:86740a56073b | 1286 | { |
AnnaBridge | 143:86740a56073b | 1287 | SET_BIT(TIMx->CCER, Channels); |
AnnaBridge | 143:86740a56073b | 1288 | } |
AnnaBridge | 143:86740a56073b | 1289 | |
AnnaBridge | 143:86740a56073b | 1290 | /** |
AnnaBridge | 143:86740a56073b | 1291 | * @brief Disable capture/compare channels. |
AnnaBridge | 143:86740a56073b | 1292 | * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n |
AnnaBridge | 143:86740a56073b | 1293 | * CCER CC2E LL_TIM_CC_DisableChannel\n |
AnnaBridge | 143:86740a56073b | 1294 | * CCER CC3E LL_TIM_CC_DisableChannel\n |
AnnaBridge | 143:86740a56073b | 1295 | * CCER CC4E LL_TIM_CC_DisableChannel |
AnnaBridge | 143:86740a56073b | 1296 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1297 | * @param Channels This parameter can be a combination of the following values: |
AnnaBridge | 143:86740a56073b | 1298 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1299 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1300 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1301 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1302 | * @retval None |
AnnaBridge | 143:86740a56073b | 1303 | */ |
AnnaBridge | 167:84c0a372a020 | 1304 | __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) |
AnnaBridge | 143:86740a56073b | 1305 | { |
AnnaBridge | 143:86740a56073b | 1306 | CLEAR_BIT(TIMx->CCER, Channels); |
AnnaBridge | 143:86740a56073b | 1307 | } |
AnnaBridge | 143:86740a56073b | 1308 | |
AnnaBridge | 143:86740a56073b | 1309 | /** |
AnnaBridge | 143:86740a56073b | 1310 | * @brief Indicate whether channel(s) is(are) enabled. |
AnnaBridge | 143:86740a56073b | 1311 | * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n |
AnnaBridge | 143:86740a56073b | 1312 | * CCER CC2E LL_TIM_CC_IsEnabledChannel\n |
AnnaBridge | 143:86740a56073b | 1313 | * CCER CC3E LL_TIM_CC_IsEnabledChannel\n |
AnnaBridge | 143:86740a56073b | 1314 | * CCER CC4E LL_TIM_CC_IsEnabledChannel |
AnnaBridge | 143:86740a56073b | 1315 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1316 | * @param Channels This parameter can be a combination of the following values: |
AnnaBridge | 143:86740a56073b | 1317 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1318 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1319 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1320 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1321 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 1322 | */ |
AnnaBridge | 167:84c0a372a020 | 1323 | __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) |
AnnaBridge | 143:86740a56073b | 1324 | { |
AnnaBridge | 167:84c0a372a020 | 1325 | return (READ_BIT(TIMx->CCER, Channels) == (Channels)); |
AnnaBridge | 143:86740a56073b | 1326 | } |
AnnaBridge | 143:86740a56073b | 1327 | |
AnnaBridge | 143:86740a56073b | 1328 | /** |
AnnaBridge | 143:86740a56073b | 1329 | * @} |
AnnaBridge | 143:86740a56073b | 1330 | */ |
AnnaBridge | 143:86740a56073b | 1331 | |
AnnaBridge | 143:86740a56073b | 1332 | /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration |
AnnaBridge | 143:86740a56073b | 1333 | * @{ |
AnnaBridge | 143:86740a56073b | 1334 | */ |
AnnaBridge | 143:86740a56073b | 1335 | /** |
AnnaBridge | 143:86740a56073b | 1336 | * @brief Configure an output channel. |
AnnaBridge | 143:86740a56073b | 1337 | * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 143:86740a56073b | 1338 | * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 143:86740a56073b | 1339 | * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 143:86740a56073b | 1340 | * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 143:86740a56073b | 1341 | * CCER CC1P LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 143:86740a56073b | 1342 | * CCER CC2P LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 143:86740a56073b | 1343 | * CCER CC3P LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 143:86740a56073b | 1344 | * CCER CC4P LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 143:86740a56073b | 1345 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1346 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1347 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1348 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1349 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1350 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1351 | * @param Configuration This parameter must be a combination of all the following values: |
AnnaBridge | 143:86740a56073b | 1352 | * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW |
AnnaBridge | 143:86740a56073b | 1353 | * @retval None |
AnnaBridge | 143:86740a56073b | 1354 | */ |
AnnaBridge | 167:84c0a372a020 | 1355 | __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) |
AnnaBridge | 143:86740a56073b | 1356 | { |
AnnaBridge | 143:86740a56073b | 1357 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 167:84c0a372a020 | 1358 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 143:86740a56073b | 1359 | CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); |
AnnaBridge | 167:84c0a372a020 | 1360 | MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), |
AnnaBridge | 167:84c0a372a020 | 1361 | (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); |
AnnaBridge | 143:86740a56073b | 1362 | } |
AnnaBridge | 143:86740a56073b | 1363 | |
AnnaBridge | 143:86740a56073b | 1364 | /** |
AnnaBridge | 143:86740a56073b | 1365 | * @brief Define the behavior of the output reference signal OCxREF from which |
AnnaBridge | 143:86740a56073b | 1366 | * OCx and OCxN (when relevant) are derived. |
AnnaBridge | 143:86740a56073b | 1367 | * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n |
AnnaBridge | 143:86740a56073b | 1368 | * CCMR1 OC2M LL_TIM_OC_SetMode\n |
AnnaBridge | 143:86740a56073b | 1369 | * CCMR2 OC3M LL_TIM_OC_SetMode\n |
AnnaBridge | 143:86740a56073b | 1370 | * CCMR2 OC4M LL_TIM_OC_SetMode |
AnnaBridge | 143:86740a56073b | 1371 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1372 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1373 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1374 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1375 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1376 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1377 | * @param Mode This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1378 | * @arg @ref LL_TIM_OCMODE_FROZEN |
AnnaBridge | 143:86740a56073b | 1379 | * @arg @ref LL_TIM_OCMODE_ACTIVE |
AnnaBridge | 143:86740a56073b | 1380 | * @arg @ref LL_TIM_OCMODE_INACTIVE |
AnnaBridge | 143:86740a56073b | 1381 | * @arg @ref LL_TIM_OCMODE_TOGGLE |
AnnaBridge | 143:86740a56073b | 1382 | * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE |
AnnaBridge | 143:86740a56073b | 1383 | * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE |
AnnaBridge | 143:86740a56073b | 1384 | * @arg @ref LL_TIM_OCMODE_PWM1 |
AnnaBridge | 143:86740a56073b | 1385 | * @arg @ref LL_TIM_OCMODE_PWM2 |
AnnaBridge | 143:86740a56073b | 1386 | * @retval None |
AnnaBridge | 143:86740a56073b | 1387 | */ |
AnnaBridge | 167:84c0a372a020 | 1388 | __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) |
AnnaBridge | 143:86740a56073b | 1389 | { |
AnnaBridge | 143:86740a56073b | 1390 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 167:84c0a372a020 | 1391 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 143:86740a56073b | 1392 | MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); |
AnnaBridge | 143:86740a56073b | 1393 | } |
AnnaBridge | 143:86740a56073b | 1394 | |
AnnaBridge | 143:86740a56073b | 1395 | /** |
AnnaBridge | 143:86740a56073b | 1396 | * @brief Get the output compare mode of an output channel. |
AnnaBridge | 143:86740a56073b | 1397 | * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n |
AnnaBridge | 143:86740a56073b | 1398 | * CCMR1 OC2M LL_TIM_OC_GetMode\n |
AnnaBridge | 143:86740a56073b | 1399 | * CCMR2 OC3M LL_TIM_OC_GetMode\n |
AnnaBridge | 143:86740a56073b | 1400 | * CCMR2 OC4M LL_TIM_OC_GetMode |
AnnaBridge | 143:86740a56073b | 1401 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1402 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1403 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1404 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1405 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1406 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1407 | * @retval Returned value can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1408 | * @arg @ref LL_TIM_OCMODE_FROZEN |
AnnaBridge | 143:86740a56073b | 1409 | * @arg @ref LL_TIM_OCMODE_ACTIVE |
AnnaBridge | 143:86740a56073b | 1410 | * @arg @ref LL_TIM_OCMODE_INACTIVE |
AnnaBridge | 143:86740a56073b | 1411 | * @arg @ref LL_TIM_OCMODE_TOGGLE |
AnnaBridge | 143:86740a56073b | 1412 | * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE |
AnnaBridge | 143:86740a56073b | 1413 | * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE |
AnnaBridge | 143:86740a56073b | 1414 | * @arg @ref LL_TIM_OCMODE_PWM1 |
AnnaBridge | 143:86740a56073b | 1415 | * @arg @ref LL_TIM_OCMODE_PWM2 |
AnnaBridge | 143:86740a56073b | 1416 | */ |
AnnaBridge | 167:84c0a372a020 | 1417 | __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 143:86740a56073b | 1418 | { |
AnnaBridge | 143:86740a56073b | 1419 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 167:84c0a372a020 | 1420 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 143:86740a56073b | 1421 | return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); |
AnnaBridge | 143:86740a56073b | 1422 | } |
AnnaBridge | 143:86740a56073b | 1423 | |
AnnaBridge | 143:86740a56073b | 1424 | /** |
AnnaBridge | 143:86740a56073b | 1425 | * @brief Set the polarity of an output channel. |
AnnaBridge | 143:86740a56073b | 1426 | * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n |
AnnaBridge | 143:86740a56073b | 1427 | * CCER CC2P LL_TIM_OC_SetPolarity\n |
AnnaBridge | 143:86740a56073b | 1428 | * CCER CC3P LL_TIM_OC_SetPolarity\n |
AnnaBridge | 143:86740a56073b | 1429 | * CCER CC4P LL_TIM_OC_SetPolarity |
AnnaBridge | 143:86740a56073b | 1430 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1431 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1432 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1433 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1434 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1435 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1436 | * @param Polarity This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1437 | * @arg @ref LL_TIM_OCPOLARITY_HIGH |
AnnaBridge | 143:86740a56073b | 1438 | * @arg @ref LL_TIM_OCPOLARITY_LOW |
AnnaBridge | 143:86740a56073b | 1439 | * @retval None |
AnnaBridge | 143:86740a56073b | 1440 | */ |
AnnaBridge | 167:84c0a372a020 | 1441 | __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) |
AnnaBridge | 143:86740a56073b | 1442 | { |
AnnaBridge | 143:86740a56073b | 1443 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 143:86740a56073b | 1444 | MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); |
AnnaBridge | 143:86740a56073b | 1445 | } |
AnnaBridge | 143:86740a56073b | 1446 | |
AnnaBridge | 143:86740a56073b | 1447 | /** |
AnnaBridge | 143:86740a56073b | 1448 | * @brief Get the polarity of an output channel. |
AnnaBridge | 143:86740a56073b | 1449 | * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n |
AnnaBridge | 143:86740a56073b | 1450 | * CCER CC2P LL_TIM_OC_GetPolarity\n |
AnnaBridge | 143:86740a56073b | 1451 | * CCER CC3P LL_TIM_OC_GetPolarity\n |
AnnaBridge | 143:86740a56073b | 1452 | * CCER CC4P LL_TIM_OC_GetPolarity |
AnnaBridge | 143:86740a56073b | 1453 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1454 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1455 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1456 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1457 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1458 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1459 | * @retval Returned value can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1460 | * @arg @ref LL_TIM_OCPOLARITY_HIGH |
AnnaBridge | 143:86740a56073b | 1461 | * @arg @ref LL_TIM_OCPOLARITY_LOW |
AnnaBridge | 143:86740a56073b | 1462 | */ |
AnnaBridge | 167:84c0a372a020 | 1463 | __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 143:86740a56073b | 1464 | { |
AnnaBridge | 143:86740a56073b | 1465 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 143:86740a56073b | 1466 | return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); |
AnnaBridge | 143:86740a56073b | 1467 | } |
AnnaBridge | 143:86740a56073b | 1468 | |
AnnaBridge | 143:86740a56073b | 1469 | /** |
AnnaBridge | 143:86740a56073b | 1470 | * @brief Enable fast mode for the output channel. |
AnnaBridge | 143:86740a56073b | 1471 | * @note Acts only if the channel is configured in PWM1 or PWM2 mode. |
AnnaBridge | 143:86740a56073b | 1472 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n |
AnnaBridge | 143:86740a56073b | 1473 | * CCMR1 OC2FE LL_TIM_OC_EnableFast\n |
AnnaBridge | 143:86740a56073b | 1474 | * CCMR2 OC3FE LL_TIM_OC_EnableFast\n |
AnnaBridge | 143:86740a56073b | 1475 | * CCMR2 OC4FE LL_TIM_OC_EnableFast |
AnnaBridge | 143:86740a56073b | 1476 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1477 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1478 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1479 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1480 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1481 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1482 | * @retval None |
AnnaBridge | 143:86740a56073b | 1483 | */ |
AnnaBridge | 167:84c0a372a020 | 1484 | __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 143:86740a56073b | 1485 | { |
AnnaBridge | 143:86740a56073b | 1486 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 167:84c0a372a020 | 1487 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 143:86740a56073b | 1488 | SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); |
AnnaBridge | 143:86740a56073b | 1489 | |
AnnaBridge | 143:86740a56073b | 1490 | } |
AnnaBridge | 143:86740a56073b | 1491 | |
AnnaBridge | 143:86740a56073b | 1492 | /** |
AnnaBridge | 143:86740a56073b | 1493 | * @brief Disable fast mode for the output channel. |
AnnaBridge | 143:86740a56073b | 1494 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n |
AnnaBridge | 143:86740a56073b | 1495 | * CCMR1 OC2FE LL_TIM_OC_DisableFast\n |
AnnaBridge | 143:86740a56073b | 1496 | * CCMR2 OC3FE LL_TIM_OC_DisableFast\n |
AnnaBridge | 143:86740a56073b | 1497 | * CCMR2 OC4FE LL_TIM_OC_DisableFast |
AnnaBridge | 143:86740a56073b | 1498 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1499 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1500 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1501 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1502 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1503 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1504 | * @retval None |
AnnaBridge | 143:86740a56073b | 1505 | */ |
AnnaBridge | 167:84c0a372a020 | 1506 | __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 143:86740a56073b | 1507 | { |
AnnaBridge | 143:86740a56073b | 1508 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 167:84c0a372a020 | 1509 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 143:86740a56073b | 1510 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); |
AnnaBridge | 143:86740a56073b | 1511 | |
AnnaBridge | 143:86740a56073b | 1512 | } |
AnnaBridge | 143:86740a56073b | 1513 | |
AnnaBridge | 143:86740a56073b | 1514 | /** |
AnnaBridge | 143:86740a56073b | 1515 | * @brief Indicates whether fast mode is enabled for the output channel. |
AnnaBridge | 143:86740a56073b | 1516 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n |
AnnaBridge | 143:86740a56073b | 1517 | * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n |
AnnaBridge | 143:86740a56073b | 1518 | * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n |
AnnaBridge | 143:86740a56073b | 1519 | * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n |
AnnaBridge | 143:86740a56073b | 1520 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1521 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1522 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1523 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1524 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1525 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1526 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 1527 | */ |
AnnaBridge | 167:84c0a372a020 | 1528 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 143:86740a56073b | 1529 | { |
AnnaBridge | 143:86740a56073b | 1530 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 167:84c0a372a020 | 1531 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 143:86740a56073b | 1532 | register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; |
AnnaBridge | 143:86740a56073b | 1533 | return (READ_BIT(*pReg, bitfield) == bitfield); |
AnnaBridge | 143:86740a56073b | 1534 | } |
AnnaBridge | 143:86740a56073b | 1535 | |
AnnaBridge | 143:86740a56073b | 1536 | /** |
AnnaBridge | 143:86740a56073b | 1537 | * @brief Enable compare register (TIMx_CCRx) preload for the output channel. |
AnnaBridge | 143:86740a56073b | 1538 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n |
AnnaBridge | 143:86740a56073b | 1539 | * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n |
AnnaBridge | 143:86740a56073b | 1540 | * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n |
AnnaBridge | 143:86740a56073b | 1541 | * CCMR2 OC4PE LL_TIM_OC_EnablePreload |
AnnaBridge | 143:86740a56073b | 1542 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1543 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1544 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1545 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1546 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1547 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1548 | * @retval None |
AnnaBridge | 143:86740a56073b | 1549 | */ |
AnnaBridge | 167:84c0a372a020 | 1550 | __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 143:86740a56073b | 1551 | { |
AnnaBridge | 143:86740a56073b | 1552 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 167:84c0a372a020 | 1553 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 143:86740a56073b | 1554 | SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); |
AnnaBridge | 143:86740a56073b | 1555 | } |
AnnaBridge | 143:86740a56073b | 1556 | |
AnnaBridge | 143:86740a56073b | 1557 | /** |
AnnaBridge | 143:86740a56073b | 1558 | * @brief Disable compare register (TIMx_CCRx) preload for the output channel. |
AnnaBridge | 143:86740a56073b | 1559 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n |
AnnaBridge | 143:86740a56073b | 1560 | * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n |
AnnaBridge | 143:86740a56073b | 1561 | * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n |
AnnaBridge | 143:86740a56073b | 1562 | * CCMR2 OC4PE LL_TIM_OC_DisablePreload |
AnnaBridge | 143:86740a56073b | 1563 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1564 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1565 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1566 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1567 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1568 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1569 | * @retval None |
AnnaBridge | 143:86740a56073b | 1570 | */ |
AnnaBridge | 167:84c0a372a020 | 1571 | __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 143:86740a56073b | 1572 | { |
AnnaBridge | 143:86740a56073b | 1573 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 167:84c0a372a020 | 1574 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 143:86740a56073b | 1575 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); |
AnnaBridge | 143:86740a56073b | 1576 | } |
AnnaBridge | 143:86740a56073b | 1577 | |
AnnaBridge | 143:86740a56073b | 1578 | /** |
AnnaBridge | 143:86740a56073b | 1579 | * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. |
AnnaBridge | 143:86740a56073b | 1580 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n |
AnnaBridge | 143:86740a56073b | 1581 | * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n |
AnnaBridge | 143:86740a56073b | 1582 | * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n |
AnnaBridge | 143:86740a56073b | 1583 | * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n |
AnnaBridge | 143:86740a56073b | 1584 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1585 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1586 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1587 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1588 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1589 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1590 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 1591 | */ |
AnnaBridge | 167:84c0a372a020 | 1592 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 143:86740a56073b | 1593 | { |
AnnaBridge | 143:86740a56073b | 1594 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 167:84c0a372a020 | 1595 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 143:86740a56073b | 1596 | register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; |
AnnaBridge | 143:86740a56073b | 1597 | return (READ_BIT(*pReg, bitfield) == bitfield); |
AnnaBridge | 143:86740a56073b | 1598 | } |
AnnaBridge | 143:86740a56073b | 1599 | |
AnnaBridge | 143:86740a56073b | 1600 | /** |
AnnaBridge | 143:86740a56073b | 1601 | * @brief Enable clearing the output channel on an external event. |
AnnaBridge | 143:86740a56073b | 1602 | * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. |
AnnaBridge | 143:86740a56073b | 1603 | * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
AnnaBridge | 143:86740a56073b | 1604 | * or not a timer instance can clear the OCxREF signal on an external event. |
AnnaBridge | 143:86740a56073b | 1605 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n |
AnnaBridge | 143:86740a56073b | 1606 | * CCMR1 OC2CE LL_TIM_OC_EnableClear\n |
AnnaBridge | 143:86740a56073b | 1607 | * CCMR2 OC3CE LL_TIM_OC_EnableClear\n |
AnnaBridge | 143:86740a56073b | 1608 | * CCMR2 OC4CE LL_TIM_OC_EnableClear |
AnnaBridge | 143:86740a56073b | 1609 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1610 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1611 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1612 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1613 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1614 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1615 | * @retval None |
AnnaBridge | 143:86740a56073b | 1616 | */ |
AnnaBridge | 167:84c0a372a020 | 1617 | __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 143:86740a56073b | 1618 | { |
AnnaBridge | 143:86740a56073b | 1619 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 167:84c0a372a020 | 1620 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 143:86740a56073b | 1621 | SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); |
AnnaBridge | 143:86740a56073b | 1622 | } |
AnnaBridge | 143:86740a56073b | 1623 | |
AnnaBridge | 143:86740a56073b | 1624 | /** |
AnnaBridge | 143:86740a56073b | 1625 | * @brief Disable clearing the output channel on an external event. |
AnnaBridge | 143:86740a56073b | 1626 | * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
AnnaBridge | 143:86740a56073b | 1627 | * or not a timer instance can clear the OCxREF signal on an external event. |
AnnaBridge | 143:86740a56073b | 1628 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n |
AnnaBridge | 143:86740a56073b | 1629 | * CCMR1 OC2CE LL_TIM_OC_DisableClear\n |
AnnaBridge | 143:86740a56073b | 1630 | * CCMR2 OC3CE LL_TIM_OC_DisableClear\n |
AnnaBridge | 143:86740a56073b | 1631 | * CCMR2 OC4CE LL_TIM_OC_DisableClear |
AnnaBridge | 143:86740a56073b | 1632 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1633 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1634 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1635 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1636 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1637 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1638 | * @retval None |
AnnaBridge | 143:86740a56073b | 1639 | */ |
AnnaBridge | 167:84c0a372a020 | 1640 | __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 143:86740a56073b | 1641 | { |
AnnaBridge | 143:86740a56073b | 1642 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 167:84c0a372a020 | 1643 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 143:86740a56073b | 1644 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); |
AnnaBridge | 143:86740a56073b | 1645 | } |
AnnaBridge | 143:86740a56073b | 1646 | |
AnnaBridge | 143:86740a56073b | 1647 | /** |
AnnaBridge | 143:86740a56073b | 1648 | * @brief Indicates clearing the output channel on an external event is enabled for the output channel. |
AnnaBridge | 143:86740a56073b | 1649 | * @note This function enables clearing the output channel on an external event. |
AnnaBridge | 143:86740a56073b | 1650 | * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. |
AnnaBridge | 143:86740a56073b | 1651 | * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
AnnaBridge | 143:86740a56073b | 1652 | * or not a timer instance can clear the OCxREF signal on an external event. |
AnnaBridge | 143:86740a56073b | 1653 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n |
AnnaBridge | 143:86740a56073b | 1654 | * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n |
AnnaBridge | 143:86740a56073b | 1655 | * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n |
AnnaBridge | 143:86740a56073b | 1656 | * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n |
AnnaBridge | 143:86740a56073b | 1657 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1658 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1659 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1660 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1661 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1662 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1663 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 1664 | */ |
AnnaBridge | 167:84c0a372a020 | 1665 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 143:86740a56073b | 1666 | { |
AnnaBridge | 143:86740a56073b | 1667 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 167:84c0a372a020 | 1668 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 143:86740a56073b | 1669 | register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; |
AnnaBridge | 143:86740a56073b | 1670 | return (READ_BIT(*pReg, bitfield) == bitfield); |
AnnaBridge | 143:86740a56073b | 1671 | } |
AnnaBridge | 143:86740a56073b | 1672 | |
AnnaBridge | 143:86740a56073b | 1673 | /** |
AnnaBridge | 143:86740a56073b | 1674 | * @brief Set compare value for output channel 1 (TIMx_CCR1). |
AnnaBridge | 143:86740a56073b | 1675 | * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 143:86740a56073b | 1676 | * output channel 1 is supported by a timer instance. |
AnnaBridge | 143:86740a56073b | 1677 | * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 |
AnnaBridge | 143:86740a56073b | 1678 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1679 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
AnnaBridge | 143:86740a56073b | 1680 | * @retval None |
AnnaBridge | 143:86740a56073b | 1681 | */ |
AnnaBridge | 167:84c0a372a020 | 1682 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) |
AnnaBridge | 143:86740a56073b | 1683 | { |
AnnaBridge | 143:86740a56073b | 1684 | WRITE_REG(TIMx->CCR1, CompareValue); |
AnnaBridge | 143:86740a56073b | 1685 | } |
AnnaBridge | 143:86740a56073b | 1686 | |
AnnaBridge | 143:86740a56073b | 1687 | /** |
AnnaBridge | 143:86740a56073b | 1688 | * @brief Set compare value for output channel 2 (TIMx_CCR2). |
AnnaBridge | 143:86740a56073b | 1689 | * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 143:86740a56073b | 1690 | * output channel 2 is supported by a timer instance. |
AnnaBridge | 143:86740a56073b | 1691 | * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 |
AnnaBridge | 143:86740a56073b | 1692 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1693 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
AnnaBridge | 143:86740a56073b | 1694 | * @retval None |
AnnaBridge | 143:86740a56073b | 1695 | */ |
AnnaBridge | 167:84c0a372a020 | 1696 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) |
AnnaBridge | 143:86740a56073b | 1697 | { |
AnnaBridge | 143:86740a56073b | 1698 | WRITE_REG(TIMx->CCR2, CompareValue); |
AnnaBridge | 143:86740a56073b | 1699 | } |
AnnaBridge | 143:86740a56073b | 1700 | |
AnnaBridge | 143:86740a56073b | 1701 | /** |
AnnaBridge | 143:86740a56073b | 1702 | * @brief Set compare value for output channel 3 (TIMx_CCR3). |
AnnaBridge | 143:86740a56073b | 1703 | * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 143:86740a56073b | 1704 | * output channel is supported by a timer instance. |
AnnaBridge | 143:86740a56073b | 1705 | * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 |
AnnaBridge | 143:86740a56073b | 1706 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1707 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
AnnaBridge | 143:86740a56073b | 1708 | * @retval None |
AnnaBridge | 143:86740a56073b | 1709 | */ |
AnnaBridge | 167:84c0a372a020 | 1710 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) |
AnnaBridge | 143:86740a56073b | 1711 | { |
AnnaBridge | 143:86740a56073b | 1712 | WRITE_REG(TIMx->CCR3, CompareValue); |
AnnaBridge | 143:86740a56073b | 1713 | } |
AnnaBridge | 143:86740a56073b | 1714 | |
AnnaBridge | 143:86740a56073b | 1715 | /** |
AnnaBridge | 143:86740a56073b | 1716 | * @brief Set compare value for output channel 4 (TIMx_CCR4). |
AnnaBridge | 143:86740a56073b | 1717 | * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 143:86740a56073b | 1718 | * output channel 4 is supported by a timer instance. |
AnnaBridge | 143:86740a56073b | 1719 | * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 |
AnnaBridge | 143:86740a56073b | 1720 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1721 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
AnnaBridge | 143:86740a56073b | 1722 | * @retval None |
AnnaBridge | 143:86740a56073b | 1723 | */ |
AnnaBridge | 167:84c0a372a020 | 1724 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) |
AnnaBridge | 143:86740a56073b | 1725 | { |
AnnaBridge | 143:86740a56073b | 1726 | WRITE_REG(TIMx->CCR4, CompareValue); |
AnnaBridge | 143:86740a56073b | 1727 | } |
AnnaBridge | 143:86740a56073b | 1728 | |
AnnaBridge | 143:86740a56073b | 1729 | /** |
AnnaBridge | 143:86740a56073b | 1730 | * @brief Get compare value (TIMx_CCR1) set for output channel 1. |
AnnaBridge | 143:86740a56073b | 1731 | * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 143:86740a56073b | 1732 | * output channel 1 is supported by a timer instance. |
AnnaBridge | 143:86740a56073b | 1733 | * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 |
AnnaBridge | 143:86740a56073b | 1734 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1735 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 143:86740a56073b | 1736 | */ |
AnnaBridge | 167:84c0a372a020 | 1737 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 1738 | { |
AnnaBridge | 143:86740a56073b | 1739 | return (uint32_t)(READ_REG(TIMx->CCR1)); |
AnnaBridge | 143:86740a56073b | 1740 | } |
AnnaBridge | 143:86740a56073b | 1741 | |
AnnaBridge | 143:86740a56073b | 1742 | /** |
AnnaBridge | 143:86740a56073b | 1743 | * @brief Get compare value (TIMx_CCR2) set for output channel 2. |
AnnaBridge | 143:86740a56073b | 1744 | * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 143:86740a56073b | 1745 | * output channel 2 is supported by a timer instance. |
AnnaBridge | 143:86740a56073b | 1746 | * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 |
AnnaBridge | 143:86740a56073b | 1747 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1748 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 143:86740a56073b | 1749 | */ |
AnnaBridge | 167:84c0a372a020 | 1750 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 1751 | { |
AnnaBridge | 143:86740a56073b | 1752 | return (uint32_t)(READ_REG(TIMx->CCR2)); |
AnnaBridge | 143:86740a56073b | 1753 | } |
AnnaBridge | 143:86740a56073b | 1754 | |
AnnaBridge | 143:86740a56073b | 1755 | /** |
AnnaBridge | 143:86740a56073b | 1756 | * @brief Get compare value (TIMx_CCR3) set for output channel 3. |
AnnaBridge | 143:86740a56073b | 1757 | * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 143:86740a56073b | 1758 | * output channel 3 is supported by a timer instance. |
AnnaBridge | 143:86740a56073b | 1759 | * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 |
AnnaBridge | 143:86740a56073b | 1760 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1761 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 143:86740a56073b | 1762 | */ |
AnnaBridge | 167:84c0a372a020 | 1763 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 1764 | { |
AnnaBridge | 143:86740a56073b | 1765 | return (uint32_t)(READ_REG(TIMx->CCR3)); |
AnnaBridge | 143:86740a56073b | 1766 | } |
AnnaBridge | 143:86740a56073b | 1767 | |
AnnaBridge | 143:86740a56073b | 1768 | /** |
AnnaBridge | 143:86740a56073b | 1769 | * @brief Get compare value (TIMx_CCR4) set for output channel 4. |
AnnaBridge | 143:86740a56073b | 1770 | * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 143:86740a56073b | 1771 | * output channel 4 is supported by a timer instance. |
AnnaBridge | 143:86740a56073b | 1772 | * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 |
AnnaBridge | 143:86740a56073b | 1773 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1774 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 143:86740a56073b | 1775 | */ |
AnnaBridge | 167:84c0a372a020 | 1776 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 1777 | { |
AnnaBridge | 143:86740a56073b | 1778 | return (uint32_t)(READ_REG(TIMx->CCR4)); |
AnnaBridge | 143:86740a56073b | 1779 | } |
AnnaBridge | 143:86740a56073b | 1780 | |
AnnaBridge | 143:86740a56073b | 1781 | /** |
AnnaBridge | 143:86740a56073b | 1782 | * @} |
AnnaBridge | 143:86740a56073b | 1783 | */ |
AnnaBridge | 143:86740a56073b | 1784 | |
AnnaBridge | 143:86740a56073b | 1785 | /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration |
AnnaBridge | 143:86740a56073b | 1786 | * @{ |
AnnaBridge | 143:86740a56073b | 1787 | */ |
AnnaBridge | 143:86740a56073b | 1788 | /** |
AnnaBridge | 143:86740a56073b | 1789 | * @brief Configure input channel. |
AnnaBridge | 143:86740a56073b | 1790 | * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n |
AnnaBridge | 143:86740a56073b | 1791 | * CCMR1 IC1PSC LL_TIM_IC_Config\n |
AnnaBridge | 143:86740a56073b | 1792 | * CCMR1 IC1F LL_TIM_IC_Config\n |
AnnaBridge | 143:86740a56073b | 1793 | * CCMR1 CC2S LL_TIM_IC_Config\n |
AnnaBridge | 143:86740a56073b | 1794 | * CCMR1 IC2PSC LL_TIM_IC_Config\n |
AnnaBridge | 143:86740a56073b | 1795 | * CCMR1 IC2F LL_TIM_IC_Config\n |
AnnaBridge | 143:86740a56073b | 1796 | * CCMR2 CC3S LL_TIM_IC_Config\n |
AnnaBridge | 143:86740a56073b | 1797 | * CCMR2 IC3PSC LL_TIM_IC_Config\n |
AnnaBridge | 143:86740a56073b | 1798 | * CCMR2 IC3F LL_TIM_IC_Config\n |
AnnaBridge | 143:86740a56073b | 1799 | * CCMR2 CC4S LL_TIM_IC_Config\n |
AnnaBridge | 143:86740a56073b | 1800 | * CCMR2 IC4PSC LL_TIM_IC_Config\n |
AnnaBridge | 143:86740a56073b | 1801 | * CCMR2 IC4F LL_TIM_IC_Config\n |
AnnaBridge | 143:86740a56073b | 1802 | * CCER CC1P LL_TIM_IC_Config\n |
AnnaBridge | 143:86740a56073b | 1803 | * CCER CC1NP LL_TIM_IC_Config\n |
AnnaBridge | 143:86740a56073b | 1804 | * CCER CC2P LL_TIM_IC_Config\n |
AnnaBridge | 143:86740a56073b | 1805 | * CCER CC2NP LL_TIM_IC_Config\n |
AnnaBridge | 143:86740a56073b | 1806 | * CCER CC3P LL_TIM_IC_Config\n |
AnnaBridge | 143:86740a56073b | 1807 | * CCER CC3NP LL_TIM_IC_Config\n |
AnnaBridge | 143:86740a56073b | 1808 | * CCER CC4P LL_TIM_IC_Config\n |
AnnaBridge | 143:86740a56073b | 1809 | * CCER CC4NP LL_TIM_IC_Config |
AnnaBridge | 143:86740a56073b | 1810 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1811 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1812 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1813 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1814 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1815 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1816 | * @param Configuration This parameter must be a combination of all the following values: |
AnnaBridge | 143:86740a56073b | 1817 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC |
AnnaBridge | 143:86740a56073b | 1818 | * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 |
AnnaBridge | 143:86740a56073b | 1819 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 |
AnnaBridge | 143:86740a56073b | 1820 | * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE |
AnnaBridge | 143:86740a56073b | 1821 | * @retval None |
AnnaBridge | 143:86740a56073b | 1822 | */ |
AnnaBridge | 167:84c0a372a020 | 1823 | __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) |
AnnaBridge | 143:86740a56073b | 1824 | { |
AnnaBridge | 143:86740a56073b | 1825 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 167:84c0a372a020 | 1826 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 167:84c0a372a020 | 1827 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), |
AnnaBridge | 167:84c0a372a020 | 1828 | ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); |
AnnaBridge | 167:84c0a372a020 | 1829 | MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), |
AnnaBridge | 167:84c0a372a020 | 1830 | (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); |
AnnaBridge | 143:86740a56073b | 1831 | } |
AnnaBridge | 143:86740a56073b | 1832 | |
AnnaBridge | 143:86740a56073b | 1833 | /** |
AnnaBridge | 143:86740a56073b | 1834 | * @brief Set the active input. |
AnnaBridge | 143:86740a56073b | 1835 | * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n |
AnnaBridge | 143:86740a56073b | 1836 | * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n |
AnnaBridge | 143:86740a56073b | 1837 | * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n |
AnnaBridge | 143:86740a56073b | 1838 | * CCMR2 CC4S LL_TIM_IC_SetActiveInput |
AnnaBridge | 143:86740a56073b | 1839 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1840 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1841 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1842 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1843 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1844 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1845 | * @param ICActiveInput This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1846 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI |
AnnaBridge | 143:86740a56073b | 1847 | * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI |
AnnaBridge | 143:86740a56073b | 1848 | * @arg @ref LL_TIM_ACTIVEINPUT_TRC |
AnnaBridge | 143:86740a56073b | 1849 | * @retval None |
AnnaBridge | 143:86740a56073b | 1850 | */ |
AnnaBridge | 167:84c0a372a020 | 1851 | __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) |
AnnaBridge | 143:86740a56073b | 1852 | { |
AnnaBridge | 143:86740a56073b | 1853 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 167:84c0a372a020 | 1854 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 167:84c0a372a020 | 1855 | MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
AnnaBridge | 143:86740a56073b | 1856 | } |
AnnaBridge | 143:86740a56073b | 1857 | |
AnnaBridge | 143:86740a56073b | 1858 | /** |
AnnaBridge | 143:86740a56073b | 1859 | * @brief Get the current active input. |
AnnaBridge | 143:86740a56073b | 1860 | * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n |
AnnaBridge | 143:86740a56073b | 1861 | * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n |
AnnaBridge | 143:86740a56073b | 1862 | * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n |
AnnaBridge | 143:86740a56073b | 1863 | * CCMR2 CC4S LL_TIM_IC_GetActiveInput |
AnnaBridge | 143:86740a56073b | 1864 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1865 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1866 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1867 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1868 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1869 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1870 | * @retval Returned value can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1871 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI |
AnnaBridge | 143:86740a56073b | 1872 | * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI |
AnnaBridge | 143:86740a56073b | 1873 | * @arg @ref LL_TIM_ACTIVEINPUT_TRC |
AnnaBridge | 143:86740a56073b | 1874 | */ |
AnnaBridge | 167:84c0a372a020 | 1875 | __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 143:86740a56073b | 1876 | { |
AnnaBridge | 143:86740a56073b | 1877 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 167:84c0a372a020 | 1878 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 143:86740a56073b | 1879 | return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
AnnaBridge | 143:86740a56073b | 1880 | } |
AnnaBridge | 143:86740a56073b | 1881 | |
AnnaBridge | 143:86740a56073b | 1882 | /** |
AnnaBridge | 143:86740a56073b | 1883 | * @brief Set the prescaler of input channel. |
AnnaBridge | 143:86740a56073b | 1884 | * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n |
AnnaBridge | 143:86740a56073b | 1885 | * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n |
AnnaBridge | 143:86740a56073b | 1886 | * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n |
AnnaBridge | 143:86740a56073b | 1887 | * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler |
AnnaBridge | 143:86740a56073b | 1888 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1889 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1890 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1891 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1892 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1893 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1894 | * @param ICPrescaler This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1895 | * @arg @ref LL_TIM_ICPSC_DIV1 |
AnnaBridge | 143:86740a56073b | 1896 | * @arg @ref LL_TIM_ICPSC_DIV2 |
AnnaBridge | 143:86740a56073b | 1897 | * @arg @ref LL_TIM_ICPSC_DIV4 |
AnnaBridge | 143:86740a56073b | 1898 | * @arg @ref LL_TIM_ICPSC_DIV8 |
AnnaBridge | 143:86740a56073b | 1899 | * @retval None |
AnnaBridge | 143:86740a56073b | 1900 | */ |
AnnaBridge | 167:84c0a372a020 | 1901 | __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) |
AnnaBridge | 143:86740a56073b | 1902 | { |
AnnaBridge | 143:86740a56073b | 1903 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 167:84c0a372a020 | 1904 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 167:84c0a372a020 | 1905 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
AnnaBridge | 143:86740a56073b | 1906 | } |
AnnaBridge | 143:86740a56073b | 1907 | |
AnnaBridge | 143:86740a56073b | 1908 | /** |
AnnaBridge | 143:86740a56073b | 1909 | * @brief Get the current prescaler value acting on an input channel. |
AnnaBridge | 143:86740a56073b | 1910 | * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n |
AnnaBridge | 143:86740a56073b | 1911 | * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n |
AnnaBridge | 143:86740a56073b | 1912 | * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n |
AnnaBridge | 143:86740a56073b | 1913 | * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler |
AnnaBridge | 143:86740a56073b | 1914 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1915 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1916 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1917 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1918 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1919 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1920 | * @retval Returned value can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1921 | * @arg @ref LL_TIM_ICPSC_DIV1 |
AnnaBridge | 143:86740a56073b | 1922 | * @arg @ref LL_TIM_ICPSC_DIV2 |
AnnaBridge | 143:86740a56073b | 1923 | * @arg @ref LL_TIM_ICPSC_DIV4 |
AnnaBridge | 143:86740a56073b | 1924 | * @arg @ref LL_TIM_ICPSC_DIV8 |
AnnaBridge | 143:86740a56073b | 1925 | */ |
AnnaBridge | 167:84c0a372a020 | 1926 | __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 143:86740a56073b | 1927 | { |
AnnaBridge | 143:86740a56073b | 1928 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 167:84c0a372a020 | 1929 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 143:86740a56073b | 1930 | return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
AnnaBridge | 143:86740a56073b | 1931 | } |
AnnaBridge | 143:86740a56073b | 1932 | |
AnnaBridge | 143:86740a56073b | 1933 | /** |
AnnaBridge | 143:86740a56073b | 1934 | * @brief Set the input filter duration. |
AnnaBridge | 143:86740a56073b | 1935 | * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n |
AnnaBridge | 143:86740a56073b | 1936 | * CCMR1 IC2F LL_TIM_IC_SetFilter\n |
AnnaBridge | 143:86740a56073b | 1937 | * CCMR2 IC3F LL_TIM_IC_SetFilter\n |
AnnaBridge | 143:86740a56073b | 1938 | * CCMR2 IC4F LL_TIM_IC_SetFilter |
AnnaBridge | 143:86740a56073b | 1939 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1940 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1941 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1942 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1943 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1944 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1945 | * @param ICFilter This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1946 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 |
AnnaBridge | 143:86740a56073b | 1947 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 |
AnnaBridge | 143:86740a56073b | 1948 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 |
AnnaBridge | 143:86740a56073b | 1949 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 |
AnnaBridge | 143:86740a56073b | 1950 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 |
AnnaBridge | 143:86740a56073b | 1951 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 |
AnnaBridge | 143:86740a56073b | 1952 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 |
AnnaBridge | 143:86740a56073b | 1953 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 |
AnnaBridge | 143:86740a56073b | 1954 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 |
AnnaBridge | 143:86740a56073b | 1955 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 |
AnnaBridge | 143:86740a56073b | 1956 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 |
AnnaBridge | 143:86740a56073b | 1957 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 |
AnnaBridge | 143:86740a56073b | 1958 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 |
AnnaBridge | 143:86740a56073b | 1959 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 |
AnnaBridge | 143:86740a56073b | 1960 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 |
AnnaBridge | 143:86740a56073b | 1961 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 |
AnnaBridge | 143:86740a56073b | 1962 | * @retval None |
AnnaBridge | 143:86740a56073b | 1963 | */ |
AnnaBridge | 167:84c0a372a020 | 1964 | __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) |
AnnaBridge | 143:86740a56073b | 1965 | { |
AnnaBridge | 143:86740a56073b | 1966 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 167:84c0a372a020 | 1967 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 167:84c0a372a020 | 1968 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
AnnaBridge | 143:86740a56073b | 1969 | } |
AnnaBridge | 143:86740a56073b | 1970 | |
AnnaBridge | 143:86740a56073b | 1971 | /** |
AnnaBridge | 143:86740a56073b | 1972 | * @brief Get the input filter duration. |
AnnaBridge | 143:86740a56073b | 1973 | * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n |
AnnaBridge | 143:86740a56073b | 1974 | * CCMR1 IC2F LL_TIM_IC_GetFilter\n |
AnnaBridge | 143:86740a56073b | 1975 | * CCMR2 IC3F LL_TIM_IC_GetFilter\n |
AnnaBridge | 143:86740a56073b | 1976 | * CCMR2 IC4F LL_TIM_IC_GetFilter |
AnnaBridge | 143:86740a56073b | 1977 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 1978 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1979 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 1980 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 1981 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 1982 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 1983 | * @retval Returned value can be one of the following values: |
AnnaBridge | 143:86740a56073b | 1984 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 |
AnnaBridge | 143:86740a56073b | 1985 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 |
AnnaBridge | 143:86740a56073b | 1986 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 |
AnnaBridge | 143:86740a56073b | 1987 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 |
AnnaBridge | 143:86740a56073b | 1988 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 |
AnnaBridge | 143:86740a56073b | 1989 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 |
AnnaBridge | 143:86740a56073b | 1990 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 |
AnnaBridge | 143:86740a56073b | 1991 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 |
AnnaBridge | 143:86740a56073b | 1992 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 |
AnnaBridge | 143:86740a56073b | 1993 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 |
AnnaBridge | 143:86740a56073b | 1994 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 |
AnnaBridge | 143:86740a56073b | 1995 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 |
AnnaBridge | 143:86740a56073b | 1996 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 |
AnnaBridge | 143:86740a56073b | 1997 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 |
AnnaBridge | 143:86740a56073b | 1998 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 |
AnnaBridge | 143:86740a56073b | 1999 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 |
AnnaBridge | 143:86740a56073b | 2000 | */ |
AnnaBridge | 167:84c0a372a020 | 2001 | __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 143:86740a56073b | 2002 | { |
AnnaBridge | 143:86740a56073b | 2003 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 167:84c0a372a020 | 2004 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 167:84c0a372a020 | 2005 | return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
AnnaBridge | 143:86740a56073b | 2006 | } |
AnnaBridge | 143:86740a56073b | 2007 | |
AnnaBridge | 143:86740a56073b | 2008 | /** |
AnnaBridge | 143:86740a56073b | 2009 | * @brief Set the input channel polarity. |
AnnaBridge | 143:86740a56073b | 2010 | * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n |
AnnaBridge | 143:86740a56073b | 2011 | * CCER CC1NP LL_TIM_IC_SetPolarity\n |
AnnaBridge | 143:86740a56073b | 2012 | * CCER CC2P LL_TIM_IC_SetPolarity\n |
AnnaBridge | 143:86740a56073b | 2013 | * CCER CC2NP LL_TIM_IC_SetPolarity\n |
AnnaBridge | 143:86740a56073b | 2014 | * CCER CC3P LL_TIM_IC_SetPolarity\n |
AnnaBridge | 143:86740a56073b | 2015 | * CCER CC3NP LL_TIM_IC_SetPolarity\n |
AnnaBridge | 143:86740a56073b | 2016 | * CCER CC4P LL_TIM_IC_SetPolarity\n |
AnnaBridge | 143:86740a56073b | 2017 | * CCER CC4NP LL_TIM_IC_SetPolarity |
AnnaBridge | 143:86740a56073b | 2018 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2019 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 2020 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 2021 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 2022 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 2023 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 2024 | * @param ICPolarity This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 2025 | * @arg @ref LL_TIM_IC_POLARITY_RISING |
AnnaBridge | 143:86740a56073b | 2026 | * @arg @ref LL_TIM_IC_POLARITY_FALLING |
AnnaBridge | 143:86740a56073b | 2027 | * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE |
AnnaBridge | 143:86740a56073b | 2028 | * @retval None |
AnnaBridge | 143:86740a56073b | 2029 | */ |
AnnaBridge | 167:84c0a372a020 | 2030 | __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) |
AnnaBridge | 143:86740a56073b | 2031 | { |
AnnaBridge | 143:86740a56073b | 2032 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 167:84c0a372a020 | 2033 | MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), |
AnnaBridge | 167:84c0a372a020 | 2034 | ICPolarity << SHIFT_TAB_CCxP[iChannel]); |
AnnaBridge | 143:86740a56073b | 2035 | } |
AnnaBridge | 143:86740a56073b | 2036 | |
AnnaBridge | 143:86740a56073b | 2037 | /** |
AnnaBridge | 143:86740a56073b | 2038 | * @brief Get the current input channel polarity. |
AnnaBridge | 143:86740a56073b | 2039 | * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n |
AnnaBridge | 143:86740a56073b | 2040 | * CCER CC1NP LL_TIM_IC_GetPolarity\n |
AnnaBridge | 143:86740a56073b | 2041 | * CCER CC2P LL_TIM_IC_GetPolarity\n |
AnnaBridge | 143:86740a56073b | 2042 | * CCER CC2NP LL_TIM_IC_GetPolarity\n |
AnnaBridge | 143:86740a56073b | 2043 | * CCER CC3P LL_TIM_IC_GetPolarity\n |
AnnaBridge | 143:86740a56073b | 2044 | * CCER CC3NP LL_TIM_IC_GetPolarity\n |
AnnaBridge | 143:86740a56073b | 2045 | * CCER CC4P LL_TIM_IC_GetPolarity\n |
AnnaBridge | 143:86740a56073b | 2046 | * CCER CC4NP LL_TIM_IC_GetPolarity |
AnnaBridge | 143:86740a56073b | 2047 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2048 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 2049 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 143:86740a56073b | 2050 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 143:86740a56073b | 2051 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 143:86740a56073b | 2052 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 143:86740a56073b | 2053 | * @retval Returned value can be one of the following values: |
AnnaBridge | 143:86740a56073b | 2054 | * @arg @ref LL_TIM_IC_POLARITY_RISING |
AnnaBridge | 143:86740a56073b | 2055 | * @arg @ref LL_TIM_IC_POLARITY_FALLING |
AnnaBridge | 143:86740a56073b | 2056 | * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE |
AnnaBridge | 143:86740a56073b | 2057 | */ |
AnnaBridge | 167:84c0a372a020 | 2058 | __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 143:86740a56073b | 2059 | { |
AnnaBridge | 143:86740a56073b | 2060 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 167:84c0a372a020 | 2061 | return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> |
AnnaBridge | 167:84c0a372a020 | 2062 | SHIFT_TAB_CCxP[iChannel]); |
AnnaBridge | 143:86740a56073b | 2063 | } |
AnnaBridge | 143:86740a56073b | 2064 | |
AnnaBridge | 143:86740a56073b | 2065 | /** |
AnnaBridge | 143:86740a56073b | 2066 | * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). |
AnnaBridge | 143:86740a56073b | 2067 | * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 143:86740a56073b | 2068 | * a timer instance provides an XOR input. |
AnnaBridge | 143:86740a56073b | 2069 | * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination |
AnnaBridge | 143:86740a56073b | 2070 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2071 | * @retval None |
AnnaBridge | 143:86740a56073b | 2072 | */ |
AnnaBridge | 167:84c0a372a020 | 2073 | __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2074 | { |
AnnaBridge | 143:86740a56073b | 2075 | SET_BIT(TIMx->CR2, TIM_CR2_TI1S); |
AnnaBridge | 143:86740a56073b | 2076 | } |
AnnaBridge | 143:86740a56073b | 2077 | |
AnnaBridge | 143:86740a56073b | 2078 | /** |
AnnaBridge | 143:86740a56073b | 2079 | * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. |
AnnaBridge | 143:86740a56073b | 2080 | * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 143:86740a56073b | 2081 | * a timer instance provides an XOR input. |
AnnaBridge | 143:86740a56073b | 2082 | * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination |
AnnaBridge | 143:86740a56073b | 2083 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2084 | * @retval None |
AnnaBridge | 143:86740a56073b | 2085 | */ |
AnnaBridge | 167:84c0a372a020 | 2086 | __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2087 | { |
AnnaBridge | 143:86740a56073b | 2088 | CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); |
AnnaBridge | 143:86740a56073b | 2089 | } |
AnnaBridge | 143:86740a56073b | 2090 | |
AnnaBridge | 143:86740a56073b | 2091 | /** |
AnnaBridge | 143:86740a56073b | 2092 | * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. |
AnnaBridge | 143:86740a56073b | 2093 | * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 143:86740a56073b | 2094 | * a timer instance provides an XOR input. |
AnnaBridge | 143:86740a56073b | 2095 | * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination |
AnnaBridge | 143:86740a56073b | 2096 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2097 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 2098 | */ |
AnnaBridge | 167:84c0a372a020 | 2099 | __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2100 | { |
AnnaBridge | 143:86740a56073b | 2101 | return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)); |
AnnaBridge | 143:86740a56073b | 2102 | } |
AnnaBridge | 143:86740a56073b | 2103 | |
AnnaBridge | 143:86740a56073b | 2104 | /** |
AnnaBridge | 143:86740a56073b | 2105 | * @brief Get captured value for input channel 1. |
AnnaBridge | 143:86740a56073b | 2106 | * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 143:86740a56073b | 2107 | * input channel 1 is supported by a timer instance. |
AnnaBridge | 143:86740a56073b | 2108 | * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 |
AnnaBridge | 143:86740a56073b | 2109 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2110 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 143:86740a56073b | 2111 | */ |
AnnaBridge | 167:84c0a372a020 | 2112 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2113 | { |
AnnaBridge | 143:86740a56073b | 2114 | return (uint32_t)(READ_REG(TIMx->CCR1)); |
AnnaBridge | 143:86740a56073b | 2115 | } |
AnnaBridge | 143:86740a56073b | 2116 | |
AnnaBridge | 143:86740a56073b | 2117 | /** |
AnnaBridge | 143:86740a56073b | 2118 | * @brief Get captured value for input channel 2. |
AnnaBridge | 143:86740a56073b | 2119 | * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 143:86740a56073b | 2120 | * input channel 2 is supported by a timer instance. |
AnnaBridge | 143:86740a56073b | 2121 | * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 |
AnnaBridge | 143:86740a56073b | 2122 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2123 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 143:86740a56073b | 2124 | */ |
AnnaBridge | 167:84c0a372a020 | 2125 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2126 | { |
AnnaBridge | 143:86740a56073b | 2127 | return (uint32_t)(READ_REG(TIMx->CCR2)); |
AnnaBridge | 143:86740a56073b | 2128 | } |
AnnaBridge | 143:86740a56073b | 2129 | |
AnnaBridge | 143:86740a56073b | 2130 | /** |
AnnaBridge | 143:86740a56073b | 2131 | * @brief Get captured value for input channel 3. |
AnnaBridge | 143:86740a56073b | 2132 | * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 143:86740a56073b | 2133 | * input channel 3 is supported by a timer instance. |
AnnaBridge | 143:86740a56073b | 2134 | * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 |
AnnaBridge | 143:86740a56073b | 2135 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2136 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 143:86740a56073b | 2137 | */ |
AnnaBridge | 167:84c0a372a020 | 2138 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2139 | { |
AnnaBridge | 143:86740a56073b | 2140 | return (uint32_t)(READ_REG(TIMx->CCR3)); |
AnnaBridge | 143:86740a56073b | 2141 | } |
AnnaBridge | 143:86740a56073b | 2142 | |
AnnaBridge | 143:86740a56073b | 2143 | /** |
AnnaBridge | 143:86740a56073b | 2144 | * @brief Get captured value for input channel 4. |
AnnaBridge | 143:86740a56073b | 2145 | * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 143:86740a56073b | 2146 | * input channel 4 is supported by a timer instance. |
AnnaBridge | 143:86740a56073b | 2147 | * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 |
AnnaBridge | 143:86740a56073b | 2148 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2149 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 143:86740a56073b | 2150 | */ |
AnnaBridge | 167:84c0a372a020 | 2151 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2152 | { |
AnnaBridge | 143:86740a56073b | 2153 | return (uint32_t)(READ_REG(TIMx->CCR4)); |
AnnaBridge | 143:86740a56073b | 2154 | } |
AnnaBridge | 143:86740a56073b | 2155 | |
AnnaBridge | 143:86740a56073b | 2156 | /** |
AnnaBridge | 143:86740a56073b | 2157 | * @} |
AnnaBridge | 143:86740a56073b | 2158 | */ |
AnnaBridge | 143:86740a56073b | 2159 | |
AnnaBridge | 143:86740a56073b | 2160 | /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection |
AnnaBridge | 143:86740a56073b | 2161 | * @{ |
AnnaBridge | 143:86740a56073b | 2162 | */ |
AnnaBridge | 143:86740a56073b | 2163 | /** |
AnnaBridge | 143:86740a56073b | 2164 | * @brief Enable external clock mode 2. |
AnnaBridge | 143:86740a56073b | 2165 | * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. |
AnnaBridge | 167:84c0a372a020 | 2166 | * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
AnnaBridge | 143:86740a56073b | 2167 | * whether or not a timer instance supports external clock mode2. |
AnnaBridge | 143:86740a56073b | 2168 | * @rmtoll SMCR ECE LL_TIM_EnableExternalClock |
AnnaBridge | 143:86740a56073b | 2169 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2170 | * @retval None |
AnnaBridge | 143:86740a56073b | 2171 | */ |
AnnaBridge | 167:84c0a372a020 | 2172 | __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2173 | { |
AnnaBridge | 143:86740a56073b | 2174 | SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); |
AnnaBridge | 143:86740a56073b | 2175 | } |
AnnaBridge | 143:86740a56073b | 2176 | |
AnnaBridge | 143:86740a56073b | 2177 | /** |
AnnaBridge | 143:86740a56073b | 2178 | * @brief Disable external clock mode 2. |
AnnaBridge | 167:84c0a372a020 | 2179 | * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
AnnaBridge | 143:86740a56073b | 2180 | * whether or not a timer instance supports external clock mode2. |
AnnaBridge | 143:86740a56073b | 2181 | * @rmtoll SMCR ECE LL_TIM_DisableExternalClock |
AnnaBridge | 143:86740a56073b | 2182 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2183 | * @retval None |
AnnaBridge | 143:86740a56073b | 2184 | */ |
AnnaBridge | 167:84c0a372a020 | 2185 | __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2186 | { |
AnnaBridge | 143:86740a56073b | 2187 | CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); |
AnnaBridge | 143:86740a56073b | 2188 | } |
AnnaBridge | 143:86740a56073b | 2189 | |
AnnaBridge | 143:86740a56073b | 2190 | /** |
AnnaBridge | 143:86740a56073b | 2191 | * @brief Indicate whether external clock mode 2 is enabled. |
AnnaBridge | 167:84c0a372a020 | 2192 | * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
AnnaBridge | 143:86740a56073b | 2193 | * whether or not a timer instance supports external clock mode2. |
AnnaBridge | 143:86740a56073b | 2194 | * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock |
AnnaBridge | 143:86740a56073b | 2195 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2196 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 2197 | */ |
AnnaBridge | 167:84c0a372a020 | 2198 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2199 | { |
AnnaBridge | 143:86740a56073b | 2200 | return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)); |
AnnaBridge | 143:86740a56073b | 2201 | } |
AnnaBridge | 143:86740a56073b | 2202 | |
AnnaBridge | 143:86740a56073b | 2203 | /** |
AnnaBridge | 143:86740a56073b | 2204 | * @brief Set the clock source of the counter clock. |
AnnaBridge | 167:84c0a372a020 | 2205 | * @note when selected clock source is external clock mode 1, the timer input |
AnnaBridge | 167:84c0a372a020 | 2206 | * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() |
AnnaBridge | 167:84c0a372a020 | 2207 | * function. This timer input must be configured by calling |
AnnaBridge | 143:86740a56073b | 2208 | * the @ref LL_TIM_IC_Config() function. |
AnnaBridge | 167:84c0a372a020 | 2209 | * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check |
AnnaBridge | 143:86740a56073b | 2210 | * whether or not a timer instance supports external clock mode1. |
AnnaBridge | 167:84c0a372a020 | 2211 | * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
AnnaBridge | 143:86740a56073b | 2212 | * whether or not a timer instance supports external clock mode2. |
AnnaBridge | 143:86740a56073b | 2213 | * @rmtoll SMCR SMS LL_TIM_SetClockSource\n |
AnnaBridge | 143:86740a56073b | 2214 | * SMCR ECE LL_TIM_SetClockSource |
AnnaBridge | 143:86740a56073b | 2215 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2216 | * @param ClockSource This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 2217 | * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL |
AnnaBridge | 143:86740a56073b | 2218 | * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 |
AnnaBridge | 143:86740a56073b | 2219 | * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 |
AnnaBridge | 143:86740a56073b | 2220 | * @retval None |
AnnaBridge | 143:86740a56073b | 2221 | */ |
AnnaBridge | 167:84c0a372a020 | 2222 | __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) |
AnnaBridge | 143:86740a56073b | 2223 | { |
AnnaBridge | 143:86740a56073b | 2224 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); |
AnnaBridge | 143:86740a56073b | 2225 | } |
AnnaBridge | 143:86740a56073b | 2226 | |
AnnaBridge | 143:86740a56073b | 2227 | /** |
AnnaBridge | 143:86740a56073b | 2228 | * @brief Set the encoder interface mode. |
AnnaBridge | 167:84c0a372a020 | 2229 | * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check |
AnnaBridge | 143:86740a56073b | 2230 | * whether or not a timer instance supports the encoder mode. |
AnnaBridge | 143:86740a56073b | 2231 | * @rmtoll SMCR SMS LL_TIM_SetEncoderMode |
AnnaBridge | 143:86740a56073b | 2232 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2233 | * @param EncoderMode This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 2234 | * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 |
AnnaBridge | 143:86740a56073b | 2235 | * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 |
AnnaBridge | 143:86740a56073b | 2236 | * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 |
AnnaBridge | 143:86740a56073b | 2237 | * @retval None |
AnnaBridge | 143:86740a56073b | 2238 | */ |
AnnaBridge | 167:84c0a372a020 | 2239 | __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) |
AnnaBridge | 143:86740a56073b | 2240 | { |
AnnaBridge | 143:86740a56073b | 2241 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); |
AnnaBridge | 143:86740a56073b | 2242 | } |
AnnaBridge | 143:86740a56073b | 2243 | |
AnnaBridge | 143:86740a56073b | 2244 | /** |
AnnaBridge | 143:86740a56073b | 2245 | * @} |
AnnaBridge | 143:86740a56073b | 2246 | */ |
AnnaBridge | 143:86740a56073b | 2247 | |
AnnaBridge | 143:86740a56073b | 2248 | /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration |
AnnaBridge | 143:86740a56073b | 2249 | * @{ |
AnnaBridge | 143:86740a56073b | 2250 | */ |
AnnaBridge | 143:86740a56073b | 2251 | /** |
AnnaBridge | 143:86740a56073b | 2252 | * @brief Set the trigger output (TRGO) used for timer synchronization . |
AnnaBridge | 167:84c0a372a020 | 2253 | * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check |
AnnaBridge | 143:86740a56073b | 2254 | * whether or not a timer instance can operate as a master timer. |
AnnaBridge | 143:86740a56073b | 2255 | * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput |
AnnaBridge | 143:86740a56073b | 2256 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2257 | * @param TimerSynchronization This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 2258 | * @arg @ref LL_TIM_TRGO_RESET |
AnnaBridge | 143:86740a56073b | 2259 | * @arg @ref LL_TIM_TRGO_ENABLE |
AnnaBridge | 143:86740a56073b | 2260 | * @arg @ref LL_TIM_TRGO_UPDATE |
AnnaBridge | 143:86740a56073b | 2261 | * @arg @ref LL_TIM_TRGO_CC1IF |
AnnaBridge | 143:86740a56073b | 2262 | * @arg @ref LL_TIM_TRGO_OC1REF |
AnnaBridge | 143:86740a56073b | 2263 | * @arg @ref LL_TIM_TRGO_OC2REF |
AnnaBridge | 143:86740a56073b | 2264 | * @arg @ref LL_TIM_TRGO_OC3REF |
AnnaBridge | 143:86740a56073b | 2265 | * @arg @ref LL_TIM_TRGO_OC4REF |
AnnaBridge | 143:86740a56073b | 2266 | * @retval None |
AnnaBridge | 143:86740a56073b | 2267 | */ |
AnnaBridge | 167:84c0a372a020 | 2268 | __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) |
AnnaBridge | 143:86740a56073b | 2269 | { |
AnnaBridge | 143:86740a56073b | 2270 | MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); |
AnnaBridge | 143:86740a56073b | 2271 | } |
AnnaBridge | 143:86740a56073b | 2272 | |
AnnaBridge | 143:86740a56073b | 2273 | /** |
AnnaBridge | 143:86740a56073b | 2274 | * @brief Set the synchronization mode of a slave timer. |
AnnaBridge | 167:84c0a372a020 | 2275 | * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 143:86740a56073b | 2276 | * a timer instance can operate as a slave timer. |
AnnaBridge | 143:86740a56073b | 2277 | * @rmtoll SMCR SMS LL_TIM_SetSlaveMode |
AnnaBridge | 143:86740a56073b | 2278 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2279 | * @param SlaveMode This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 2280 | * @arg @ref LL_TIM_SLAVEMODE_DISABLED |
AnnaBridge | 143:86740a56073b | 2281 | * @arg @ref LL_TIM_SLAVEMODE_RESET |
AnnaBridge | 143:86740a56073b | 2282 | * @arg @ref LL_TIM_SLAVEMODE_GATED |
AnnaBridge | 143:86740a56073b | 2283 | * @arg @ref LL_TIM_SLAVEMODE_TRIGGER |
AnnaBridge | 143:86740a56073b | 2284 | * @retval None |
AnnaBridge | 143:86740a56073b | 2285 | */ |
AnnaBridge | 167:84c0a372a020 | 2286 | __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) |
AnnaBridge | 143:86740a56073b | 2287 | { |
AnnaBridge | 143:86740a56073b | 2288 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); |
AnnaBridge | 143:86740a56073b | 2289 | } |
AnnaBridge | 143:86740a56073b | 2290 | |
AnnaBridge | 143:86740a56073b | 2291 | /** |
AnnaBridge | 143:86740a56073b | 2292 | * @brief Set the selects the trigger input to be used to synchronize the counter. |
AnnaBridge | 167:84c0a372a020 | 2293 | * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 143:86740a56073b | 2294 | * a timer instance can operate as a slave timer. |
AnnaBridge | 143:86740a56073b | 2295 | * @rmtoll SMCR TS LL_TIM_SetTriggerInput |
AnnaBridge | 143:86740a56073b | 2296 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2297 | * @param TriggerInput This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 2298 | * @arg @ref LL_TIM_TS_ITR0 |
AnnaBridge | 143:86740a56073b | 2299 | * @arg @ref LL_TIM_TS_ITR1 |
AnnaBridge | 143:86740a56073b | 2300 | * @arg @ref LL_TIM_TS_ITR2 |
AnnaBridge | 143:86740a56073b | 2301 | * @arg @ref LL_TIM_TS_ITR3 |
AnnaBridge | 143:86740a56073b | 2302 | * @arg @ref LL_TIM_TS_TI1F_ED |
AnnaBridge | 143:86740a56073b | 2303 | * @arg @ref LL_TIM_TS_TI1FP1 |
AnnaBridge | 143:86740a56073b | 2304 | * @arg @ref LL_TIM_TS_TI2FP2 |
AnnaBridge | 143:86740a56073b | 2305 | * @arg @ref LL_TIM_TS_ETRF |
AnnaBridge | 143:86740a56073b | 2306 | * @retval None |
AnnaBridge | 143:86740a56073b | 2307 | */ |
AnnaBridge | 167:84c0a372a020 | 2308 | __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) |
AnnaBridge | 143:86740a56073b | 2309 | { |
AnnaBridge | 143:86740a56073b | 2310 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); |
AnnaBridge | 143:86740a56073b | 2311 | } |
AnnaBridge | 143:86740a56073b | 2312 | |
AnnaBridge | 143:86740a56073b | 2313 | /** |
AnnaBridge | 143:86740a56073b | 2314 | * @brief Enable the Master/Slave mode. |
AnnaBridge | 167:84c0a372a020 | 2315 | * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 143:86740a56073b | 2316 | * a timer instance can operate as a slave timer. |
AnnaBridge | 143:86740a56073b | 2317 | * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode |
AnnaBridge | 143:86740a56073b | 2318 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2319 | * @retval None |
AnnaBridge | 143:86740a56073b | 2320 | */ |
AnnaBridge | 167:84c0a372a020 | 2321 | __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2322 | { |
AnnaBridge | 143:86740a56073b | 2323 | SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); |
AnnaBridge | 143:86740a56073b | 2324 | } |
AnnaBridge | 143:86740a56073b | 2325 | |
AnnaBridge | 143:86740a56073b | 2326 | /** |
AnnaBridge | 143:86740a56073b | 2327 | * @brief Disable the Master/Slave mode. |
AnnaBridge | 167:84c0a372a020 | 2328 | * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 143:86740a56073b | 2329 | * a timer instance can operate as a slave timer. |
AnnaBridge | 143:86740a56073b | 2330 | * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode |
AnnaBridge | 143:86740a56073b | 2331 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2332 | * @retval None |
AnnaBridge | 143:86740a56073b | 2333 | */ |
AnnaBridge | 167:84c0a372a020 | 2334 | __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2335 | { |
AnnaBridge | 143:86740a56073b | 2336 | CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); |
AnnaBridge | 143:86740a56073b | 2337 | } |
AnnaBridge | 143:86740a56073b | 2338 | |
AnnaBridge | 143:86740a56073b | 2339 | /** |
AnnaBridge | 143:86740a56073b | 2340 | * @brief Indicates whether the Master/Slave mode is enabled. |
AnnaBridge | 167:84c0a372a020 | 2341 | * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 143:86740a56073b | 2342 | * a timer instance can operate as a slave timer. |
AnnaBridge | 143:86740a56073b | 2343 | * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode |
AnnaBridge | 143:86740a56073b | 2344 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2345 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 2346 | */ |
AnnaBridge | 167:84c0a372a020 | 2347 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2348 | { |
AnnaBridge | 143:86740a56073b | 2349 | return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)); |
AnnaBridge | 143:86740a56073b | 2350 | } |
AnnaBridge | 143:86740a56073b | 2351 | |
AnnaBridge | 143:86740a56073b | 2352 | /** |
AnnaBridge | 143:86740a56073b | 2353 | * @brief Configure the external trigger (ETR) input. |
AnnaBridge | 167:84c0a372a020 | 2354 | * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 143:86740a56073b | 2355 | * a timer instance provides an external trigger input. |
AnnaBridge | 143:86740a56073b | 2356 | * @rmtoll SMCR ETP LL_TIM_ConfigETR\n |
AnnaBridge | 143:86740a56073b | 2357 | * SMCR ETPS LL_TIM_ConfigETR\n |
AnnaBridge | 143:86740a56073b | 2358 | * SMCR ETF LL_TIM_ConfigETR |
AnnaBridge | 143:86740a56073b | 2359 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2360 | * @param ETRPolarity This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 2361 | * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED |
AnnaBridge | 143:86740a56073b | 2362 | * @arg @ref LL_TIM_ETR_POLARITY_INVERTED |
AnnaBridge | 143:86740a56073b | 2363 | * @param ETRPrescaler This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 2364 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 |
AnnaBridge | 143:86740a56073b | 2365 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 |
AnnaBridge | 143:86740a56073b | 2366 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 |
AnnaBridge | 143:86740a56073b | 2367 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 |
AnnaBridge | 143:86740a56073b | 2368 | * @param ETRFilter This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 2369 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1 |
AnnaBridge | 143:86740a56073b | 2370 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 |
AnnaBridge | 143:86740a56073b | 2371 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 |
AnnaBridge | 143:86740a56073b | 2372 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 |
AnnaBridge | 143:86740a56073b | 2373 | * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 |
AnnaBridge | 143:86740a56073b | 2374 | * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 |
AnnaBridge | 143:86740a56073b | 2375 | * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 |
AnnaBridge | 143:86740a56073b | 2376 | * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 |
AnnaBridge | 143:86740a56073b | 2377 | * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 |
AnnaBridge | 143:86740a56073b | 2378 | * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 |
AnnaBridge | 143:86740a56073b | 2379 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 |
AnnaBridge | 143:86740a56073b | 2380 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 |
AnnaBridge | 143:86740a56073b | 2381 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 |
AnnaBridge | 143:86740a56073b | 2382 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 |
AnnaBridge | 143:86740a56073b | 2383 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 |
AnnaBridge | 143:86740a56073b | 2384 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 |
AnnaBridge | 143:86740a56073b | 2385 | * @retval None |
AnnaBridge | 143:86740a56073b | 2386 | */ |
AnnaBridge | 167:84c0a372a020 | 2387 | __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, |
AnnaBridge | 167:84c0a372a020 | 2388 | uint32_t ETRFilter) |
AnnaBridge | 143:86740a56073b | 2389 | { |
AnnaBridge | 143:86740a56073b | 2390 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); |
AnnaBridge | 143:86740a56073b | 2391 | } |
AnnaBridge | 143:86740a56073b | 2392 | |
AnnaBridge | 143:86740a56073b | 2393 | /** |
AnnaBridge | 143:86740a56073b | 2394 | * @} |
AnnaBridge | 143:86740a56073b | 2395 | */ |
AnnaBridge | 143:86740a56073b | 2396 | |
AnnaBridge | 143:86740a56073b | 2397 | /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration |
AnnaBridge | 143:86740a56073b | 2398 | * @{ |
AnnaBridge | 143:86740a56073b | 2399 | */ |
AnnaBridge | 143:86740a56073b | 2400 | /** |
AnnaBridge | 143:86740a56073b | 2401 | * @brief Configures the timer DMA burst feature. |
AnnaBridge | 143:86740a56073b | 2402 | * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or |
AnnaBridge | 143:86740a56073b | 2403 | * not a timer instance supports the DMA burst mode. |
AnnaBridge | 143:86740a56073b | 2404 | * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n |
AnnaBridge | 143:86740a56073b | 2405 | * DCR DBA LL_TIM_ConfigDMABurst |
AnnaBridge | 143:86740a56073b | 2406 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2407 | * @param DMABurstBaseAddress This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 2408 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 |
AnnaBridge | 143:86740a56073b | 2409 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 |
AnnaBridge | 143:86740a56073b | 2410 | * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR |
AnnaBridge | 143:86740a56073b | 2411 | * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER |
AnnaBridge | 143:86740a56073b | 2412 | * @arg @ref LL_TIM_DMABURST_BASEADDR_SR |
AnnaBridge | 143:86740a56073b | 2413 | * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR |
AnnaBridge | 143:86740a56073b | 2414 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 |
AnnaBridge | 143:86740a56073b | 2415 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 |
AnnaBridge | 143:86740a56073b | 2416 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER |
AnnaBridge | 143:86740a56073b | 2417 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT |
AnnaBridge | 143:86740a56073b | 2418 | * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC |
AnnaBridge | 143:86740a56073b | 2419 | * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR |
AnnaBridge | 143:86740a56073b | 2420 | * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR |
AnnaBridge | 143:86740a56073b | 2421 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 |
AnnaBridge | 143:86740a56073b | 2422 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 |
AnnaBridge | 143:86740a56073b | 2423 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 |
AnnaBridge | 143:86740a56073b | 2424 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 |
AnnaBridge | 143:86740a56073b | 2425 | * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR |
AnnaBridge | 143:86740a56073b | 2426 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 |
AnnaBridge | 143:86740a56073b | 2427 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 |
AnnaBridge | 143:86740a56073b | 2428 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 |
AnnaBridge | 143:86740a56073b | 2429 | * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1 |
AnnaBridge | 143:86740a56073b | 2430 | * @arg @ref LL_TIM_DMABURST_BASEADDR_OR2 |
AnnaBridge | 143:86740a56073b | 2431 | * @arg @ref LL_TIM_DMABURST_BASEADDR_OR3 |
AnnaBridge | 143:86740a56073b | 2432 | * @param DMABurstLength This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 2433 | * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER |
AnnaBridge | 143:86740a56073b | 2434 | * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS |
AnnaBridge | 143:86740a56073b | 2435 | * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS |
AnnaBridge | 143:86740a56073b | 2436 | * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS |
AnnaBridge | 143:86740a56073b | 2437 | * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS |
AnnaBridge | 143:86740a56073b | 2438 | * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS |
AnnaBridge | 143:86740a56073b | 2439 | * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS |
AnnaBridge | 143:86740a56073b | 2440 | * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS |
AnnaBridge | 143:86740a56073b | 2441 | * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS |
AnnaBridge | 143:86740a56073b | 2442 | * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS |
AnnaBridge | 143:86740a56073b | 2443 | * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS |
AnnaBridge | 143:86740a56073b | 2444 | * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS |
AnnaBridge | 143:86740a56073b | 2445 | * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS |
AnnaBridge | 143:86740a56073b | 2446 | * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS |
AnnaBridge | 143:86740a56073b | 2447 | * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS |
AnnaBridge | 143:86740a56073b | 2448 | * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS |
AnnaBridge | 143:86740a56073b | 2449 | * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS |
AnnaBridge | 143:86740a56073b | 2450 | * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS |
AnnaBridge | 143:86740a56073b | 2451 | * @retval None |
AnnaBridge | 143:86740a56073b | 2452 | */ |
AnnaBridge | 167:84c0a372a020 | 2453 | __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) |
AnnaBridge | 143:86740a56073b | 2454 | { |
AnnaBridge | 143:86740a56073b | 2455 | MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength); |
AnnaBridge | 143:86740a56073b | 2456 | } |
AnnaBridge | 143:86740a56073b | 2457 | |
AnnaBridge | 143:86740a56073b | 2458 | /** |
AnnaBridge | 143:86740a56073b | 2459 | * @} |
AnnaBridge | 143:86740a56073b | 2460 | */ |
AnnaBridge | 143:86740a56073b | 2461 | |
AnnaBridge | 143:86740a56073b | 2462 | /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping |
AnnaBridge | 143:86740a56073b | 2463 | * @{ |
AnnaBridge | 143:86740a56073b | 2464 | */ |
AnnaBridge | 143:86740a56073b | 2465 | /** |
AnnaBridge | 143:86740a56073b | 2466 | * @brief Remap TIM inputs (input channel, internal/external triggers). |
AnnaBridge | 143:86740a56073b | 2467 | * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 143:86740a56073b | 2468 | * a some timer inputs can be remapped. |
AnnaBridge | 143:86740a56073b | 2469 | * @rmtoll TIM2_OR ETR_RMP LL_TIM_SetRemap\n |
AnnaBridge | 143:86740a56073b | 2470 | * TIM2_OR TI4_RMP LL_TIM_SetRemap\n |
AnnaBridge | 143:86740a56073b | 2471 | * TIM21_OR ETR_RMP LL_TIM_SetRemap\n |
AnnaBridge | 143:86740a56073b | 2472 | * TIM21_OR TI1_RMP LL_TIM_SetRemap\n |
AnnaBridge | 143:86740a56073b | 2473 | * TIM21_OR TI2_RMP LL_TIM_SetRemap\n |
AnnaBridge | 143:86740a56073b | 2474 | * TIM22_OR ETR_RMP LL_TIM_SetRemap\n |
AnnaBridge | 143:86740a56073b | 2475 | * TIM22_OR TI1_RMP LL_TIM_SetRemap\n |
AnnaBridge | 143:86740a56073b | 2476 | * TIM3_OR ETR_RMP LL_TIM_SetRemap\n |
AnnaBridge | 143:86740a56073b | 2477 | * TIM3_OR TI1_RMP LL_TIM_SetRemap\n |
AnnaBridge | 143:86740a56073b | 2478 | * TIM3_OR TI2_RMP LL_TIM_SetRemap\n |
AnnaBridge | 143:86740a56073b | 2479 | * TIM3_OR TI4_RMP LL_TIM_SetRemap |
AnnaBridge | 167:84c0a372a020 | 2480 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2481 | * @param Remap Remap params depends on the TIMx. Description available only |
AnnaBridge | 167:84c0a372a020 | 2482 | * in CHM version of the User Manual (not in .pdf). |
AnnaBridge | 143:86740a56073b | 2483 | * Otherwise see Reference Manual description of OR registers. |
AnnaBridge | 143:86740a56073b | 2484 | * |
AnnaBridge | 167:84c0a372a020 | 2485 | * Below description summarizes "Timer Instance" and "Remap" param combinations: |
AnnaBridge | 143:86740a56073b | 2486 | * |
AnnaBridge | 143:86740a56073b | 2487 | * TIM2: any combination of ETR_RMP, TI4_RMP where |
AnnaBridge | 143:86740a56073b | 2488 | * |
AnnaBridge | 143:86740a56073b | 2489 | * . . ETR_RMP can be one of the following values |
AnnaBridge | 143:86740a56073b | 2490 | * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO |
AnnaBridge | 143:86740a56073b | 2491 | * @arg @ref LL_TIM_TIM2_ETR_RMP_HSI (*) |
AnnaBridge | 143:86740a56073b | 2492 | * @arg @ref LL_TIM_TIM2_ETR_RMP_HSI48 (*) |
AnnaBridge | 143:86740a56073b | 2493 | * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE |
AnnaBridge | 143:86740a56073b | 2494 | * @arg @ref LL_TIM_TIM2_ETR_RMP_COMP2 |
AnnaBridge | 143:86740a56073b | 2495 | * @arg @ref LL_TIM_TIM2_ETR_RMP_COMP1 |
AnnaBridge | 143:86740a56073b | 2496 | * |
AnnaBridge | 143:86740a56073b | 2497 | * . . TI4_RMP can be one of the following values |
AnnaBridge | 143:86740a56073b | 2498 | * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO |
AnnaBridge | 143:86740a56073b | 2499 | * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1 |
AnnaBridge | 143:86740a56073b | 2500 | * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2 |
AnnaBridge | 143:86740a56073b | 2501 | * |
AnnaBridge | 143:86740a56073b | 2502 | * TIM3: any combination of the following values (**) |
AnnaBridge | 143:86740a56073b | 2503 | * |
AnnaBridge | 143:86740a56073b | 2504 | * . . ETR_RMP can be one of the following values (**) |
AnnaBridge | 143:86740a56073b | 2505 | * @arg @ref LL_TIM_TIM3_ETR_RMP_GPIO |
AnnaBridge | 167:84c0a372a020 | 2506 | * @arg @ref LL_TIM_TIM3_ETR_RMP_HSI48DIV6 |
AnnaBridge | 143:86740a56073b | 2507 | * |
AnnaBridge | 143:86740a56073b | 2508 | * . . TI_RMP_TI1 can be one of the following values (**) |
AnnaBridge | 143:86740a56073b | 2509 | * @arg @ref LL_TIM_TIM3_TI_RMP_TI1_USB_SOF |
AnnaBridge | 167:84c0a372a020 | 2510 | * @arg @ref LL_TIM_TIM3_TI_RMP_TI1_GPIO |
AnnaBridge | 143:86740a56073b | 2511 | * |
AnnaBridge | 143:86740a56073b | 2512 | * . . TI_RMP_TI2 can be one of the following values (**) |
AnnaBridge | 143:86740a56073b | 2513 | * @arg @ref LL_TIM_TIM3_TI_RMP_TI2_GPIO_DEF |
AnnaBridge | 167:84c0a372a020 | 2514 | * @arg @ref LL_TIM_TIM3_TI_RMP_TI2_GPIOB5_AF4 |
AnnaBridge | 143:86740a56073b | 2515 | * |
AnnaBridge | 143:86740a56073b | 2516 | * . . TI_RMP_TI4 can be one of the following values (**) |
AnnaBridge | 143:86740a56073b | 2517 | * @arg @ref LL_TIM_TIM3_TI_RMP_TI4_GPIO_DEF |
AnnaBridge | 167:84c0a372a020 | 2518 | * @arg @ref LL_TIM_TIM3_TI_RMP_TI4_GPIOC9_AF2 |
AnnaBridge | 143:86740a56073b | 2519 | * |
AnnaBridge | 143:86740a56073b | 2520 | * TIM21: any combination of ETR_RMP, TI1_RMP, TI2_RMP where |
AnnaBridge | 167:84c0a372a020 | 2521 | * |
AnnaBridge | 143:86740a56073b | 2522 | * . . ETR_RMP can be one of the following values |
AnnaBridge | 143:86740a56073b | 2523 | * @arg @ref LL_TIM_TIM21_ETR_RMP_GPIO |
AnnaBridge | 143:86740a56073b | 2524 | * @arg @ref LL_TIM_TIM21_ETR_RMP_COMP2 |
AnnaBridge | 143:86740a56073b | 2525 | * @arg @ref LL_TIM_TIM21_ETR_RMP_COMP1 |
AnnaBridge | 143:86740a56073b | 2526 | * @arg @ref LL_TIM_TIM21_ETR_RMP_LSE |
AnnaBridge | 143:86740a56073b | 2527 | * |
AnnaBridge | 143:86740a56073b | 2528 | * . . TI1_RMP can be one of the following values |
AnnaBridge | 143:86740a56073b | 2529 | * @arg @ref LL_TIM_TIM21_TI1_RMP_GPIO |
AnnaBridge | 143:86740a56073b | 2530 | * @arg @ref LL_TIM_TIM21_TI1_RMP_RTC_WK |
AnnaBridge | 143:86740a56073b | 2531 | * @arg @ref LL_TIM_TIM21_TI1_RMP_HSE_RTC |
AnnaBridge | 143:86740a56073b | 2532 | * @arg @ref LL_TIM_TIM21_TI1_RMP_MSI |
AnnaBridge | 143:86740a56073b | 2533 | * @arg @ref LL_TIM_TIM21_TI1_RMP_LSE |
AnnaBridge | 143:86740a56073b | 2534 | * @arg @ref LL_TIM_TIM21_TI1_RMP_LSI |
AnnaBridge | 143:86740a56073b | 2535 | * @arg @ref LL_TIM_TIM21_TI1_RMP_COMP1 |
AnnaBridge | 143:86740a56073b | 2536 | * @arg @ref LL_TIM_TIM21_TI1_RMP_MCO |
AnnaBridge | 143:86740a56073b | 2537 | * |
AnnaBridge | 143:86740a56073b | 2538 | * . . TI2_RMP can be one of the following values |
AnnaBridge | 143:86740a56073b | 2539 | * @arg @ref LL_TIM_TIM21_TI2_RMP_GPIO |
AnnaBridge | 143:86740a56073b | 2540 | * @arg @ref LL_TIM_TIM21_TI2_RMP_COMP2 |
AnnaBridge | 143:86740a56073b | 2541 | * |
AnnaBridge | 143:86740a56073b | 2542 | * TIM22: any combination of ETR_RMP, TI1_RMP where (**) |
AnnaBridge | 143:86740a56073b | 2543 | * |
AnnaBridge | 143:86740a56073b | 2544 | * . . ETR_RMP can be one of the following values (**) |
AnnaBridge | 167:84c0a372a020 | 2545 | * @arg @ref LL_TIM_TIM22_ETR_RMP_GPIO |
AnnaBridge | 167:84c0a372a020 | 2546 | * @arg @ref LL_TIM_TIM22_ETR_RMP_COMP2 |
AnnaBridge | 167:84c0a372a020 | 2547 | * @arg @ref LL_TIM_TIM22_ETR_RMP_COMP1 |
AnnaBridge | 167:84c0a372a020 | 2548 | * @arg @ref LL_TIM_TIM22_ETR_RMP_LSE |
AnnaBridge | 143:86740a56073b | 2549 | * |
AnnaBridge | 143:86740a56073b | 2550 | * . . TI1_RMP can be one of the following values (**) |
AnnaBridge | 167:84c0a372a020 | 2551 | * @arg @ref LL_TIM_TIM22_TI1_RMP_GPIO1 |
AnnaBridge | 167:84c0a372a020 | 2552 | * @arg @ref LL_TIM_TIM22_TI1_RMP_COMP2 |
AnnaBridge | 167:84c0a372a020 | 2553 | * @arg @ref LL_TIM_TIM22_TI1_RMP_COMP1 |
AnnaBridge | 167:84c0a372a020 | 2554 | * @arg @ref LL_TIM_TIM22_TI1_RMP_GPIO2 |
AnnaBridge | 143:86740a56073b | 2555 | * |
AnnaBridge | 143:86740a56073b | 2556 | * (*) Value not defined in all devices. \n |
AnnaBridge | 143:86740a56073b | 2557 | * (*) Register not available in all devices. |
AnnaBridge | 143:86740a56073b | 2558 | * @retval None |
AnnaBridge | 143:86740a56073b | 2559 | */ |
AnnaBridge | 167:84c0a372a020 | 2560 | __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) |
AnnaBridge | 143:86740a56073b | 2561 | { |
AnnaBridge | 143:86740a56073b | 2562 | MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); |
AnnaBridge | 143:86740a56073b | 2563 | } |
AnnaBridge | 143:86740a56073b | 2564 | |
AnnaBridge | 143:86740a56073b | 2565 | /** |
AnnaBridge | 143:86740a56073b | 2566 | * @} |
AnnaBridge | 143:86740a56073b | 2567 | */ |
AnnaBridge | 143:86740a56073b | 2568 | |
AnnaBridge | 143:86740a56073b | 2569 | /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management |
AnnaBridge | 143:86740a56073b | 2570 | * @{ |
AnnaBridge | 143:86740a56073b | 2571 | */ |
AnnaBridge | 143:86740a56073b | 2572 | /** |
AnnaBridge | 167:84c0a372a020 | 2573 | * @brief Set the OCREF clear input source |
AnnaBridge | 143:86740a56073b | 2574 | * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT |
AnnaBridge | 143:86740a56073b | 2575 | * @note This function can only be used in Output compare and PWM modes. |
AnnaBridge | 167:84c0a372a020 | 2576 | * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource |
AnnaBridge | 143:86740a56073b | 2577 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2578 | * @param OCRefClearInputSource This parameter can be one of the following values: |
AnnaBridge | 143:86740a56073b | 2579 | * @arg @ref LL_TIM_OCREF_CLR_INT_NC |
AnnaBridge | 143:86740a56073b | 2580 | * @arg @ref LL_TIM_OCREF_CLR_INT_ETR |
AnnaBridge | 143:86740a56073b | 2581 | * @retval None |
AnnaBridge | 143:86740a56073b | 2582 | */ |
AnnaBridge | 167:84c0a372a020 | 2583 | __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource) |
AnnaBridge | 143:86740a56073b | 2584 | { |
AnnaBridge | 143:86740a56073b | 2585 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource); |
AnnaBridge | 143:86740a56073b | 2586 | } |
AnnaBridge | 143:86740a56073b | 2587 | /** |
AnnaBridge | 143:86740a56073b | 2588 | * @} |
AnnaBridge | 143:86740a56073b | 2589 | */ |
AnnaBridge | 143:86740a56073b | 2590 | |
AnnaBridge | 143:86740a56073b | 2591 | /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management |
AnnaBridge | 143:86740a56073b | 2592 | * @{ |
AnnaBridge | 143:86740a56073b | 2593 | */ |
AnnaBridge | 143:86740a56073b | 2594 | /** |
AnnaBridge | 143:86740a56073b | 2595 | * @brief Clear the update interrupt flag (UIF). |
AnnaBridge | 143:86740a56073b | 2596 | * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE |
AnnaBridge | 143:86740a56073b | 2597 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2598 | * @retval None |
AnnaBridge | 143:86740a56073b | 2599 | */ |
AnnaBridge | 167:84c0a372a020 | 2600 | __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2601 | { |
AnnaBridge | 143:86740a56073b | 2602 | WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); |
AnnaBridge | 143:86740a56073b | 2603 | } |
AnnaBridge | 143:86740a56073b | 2604 | |
AnnaBridge | 143:86740a56073b | 2605 | /** |
AnnaBridge | 143:86740a56073b | 2606 | * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). |
AnnaBridge | 143:86740a56073b | 2607 | * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE |
AnnaBridge | 143:86740a56073b | 2608 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2609 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 2610 | */ |
AnnaBridge | 167:84c0a372a020 | 2611 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2612 | { |
AnnaBridge | 143:86740a56073b | 2613 | return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)); |
AnnaBridge | 143:86740a56073b | 2614 | } |
AnnaBridge | 143:86740a56073b | 2615 | |
AnnaBridge | 143:86740a56073b | 2616 | /** |
AnnaBridge | 143:86740a56073b | 2617 | * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). |
AnnaBridge | 143:86740a56073b | 2618 | * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 |
AnnaBridge | 143:86740a56073b | 2619 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2620 | * @retval None |
AnnaBridge | 143:86740a56073b | 2621 | */ |
AnnaBridge | 167:84c0a372a020 | 2622 | __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2623 | { |
AnnaBridge | 143:86740a56073b | 2624 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); |
AnnaBridge | 143:86740a56073b | 2625 | } |
AnnaBridge | 143:86740a56073b | 2626 | |
AnnaBridge | 143:86740a56073b | 2627 | /** |
AnnaBridge | 143:86740a56073b | 2628 | * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). |
AnnaBridge | 143:86740a56073b | 2629 | * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 |
AnnaBridge | 143:86740a56073b | 2630 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2631 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 2632 | */ |
AnnaBridge | 167:84c0a372a020 | 2633 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2634 | { |
AnnaBridge | 143:86740a56073b | 2635 | return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)); |
AnnaBridge | 143:86740a56073b | 2636 | } |
AnnaBridge | 143:86740a56073b | 2637 | |
AnnaBridge | 143:86740a56073b | 2638 | /** |
AnnaBridge | 143:86740a56073b | 2639 | * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). |
AnnaBridge | 143:86740a56073b | 2640 | * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 |
AnnaBridge | 143:86740a56073b | 2641 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2642 | * @retval None |
AnnaBridge | 143:86740a56073b | 2643 | */ |
AnnaBridge | 167:84c0a372a020 | 2644 | __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2645 | { |
AnnaBridge | 143:86740a56073b | 2646 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); |
AnnaBridge | 143:86740a56073b | 2647 | } |
AnnaBridge | 143:86740a56073b | 2648 | |
AnnaBridge | 143:86740a56073b | 2649 | /** |
AnnaBridge | 143:86740a56073b | 2650 | * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). |
AnnaBridge | 143:86740a56073b | 2651 | * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 |
AnnaBridge | 143:86740a56073b | 2652 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2653 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 2654 | */ |
AnnaBridge | 167:84c0a372a020 | 2655 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2656 | { |
AnnaBridge | 143:86740a56073b | 2657 | return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)); |
AnnaBridge | 143:86740a56073b | 2658 | } |
AnnaBridge | 143:86740a56073b | 2659 | |
AnnaBridge | 143:86740a56073b | 2660 | /** |
AnnaBridge | 143:86740a56073b | 2661 | * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). |
AnnaBridge | 143:86740a56073b | 2662 | * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 |
AnnaBridge | 143:86740a56073b | 2663 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2664 | * @retval None |
AnnaBridge | 143:86740a56073b | 2665 | */ |
AnnaBridge | 167:84c0a372a020 | 2666 | __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2667 | { |
AnnaBridge | 143:86740a56073b | 2668 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); |
AnnaBridge | 143:86740a56073b | 2669 | } |
AnnaBridge | 143:86740a56073b | 2670 | |
AnnaBridge | 143:86740a56073b | 2671 | /** |
AnnaBridge | 143:86740a56073b | 2672 | * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). |
AnnaBridge | 143:86740a56073b | 2673 | * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 |
AnnaBridge | 143:86740a56073b | 2674 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2675 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 2676 | */ |
AnnaBridge | 167:84c0a372a020 | 2677 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2678 | { |
AnnaBridge | 143:86740a56073b | 2679 | return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)); |
AnnaBridge | 143:86740a56073b | 2680 | } |
AnnaBridge | 143:86740a56073b | 2681 | |
AnnaBridge | 143:86740a56073b | 2682 | /** |
AnnaBridge | 143:86740a56073b | 2683 | * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). |
AnnaBridge | 143:86740a56073b | 2684 | * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 |
AnnaBridge | 143:86740a56073b | 2685 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2686 | * @retval None |
AnnaBridge | 143:86740a56073b | 2687 | */ |
AnnaBridge | 167:84c0a372a020 | 2688 | __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2689 | { |
AnnaBridge | 143:86740a56073b | 2690 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); |
AnnaBridge | 143:86740a56073b | 2691 | } |
AnnaBridge | 143:86740a56073b | 2692 | |
AnnaBridge | 143:86740a56073b | 2693 | /** |
AnnaBridge | 143:86740a56073b | 2694 | * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). |
AnnaBridge | 143:86740a56073b | 2695 | * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 |
AnnaBridge | 143:86740a56073b | 2696 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2697 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 2698 | */ |
AnnaBridge | 167:84c0a372a020 | 2699 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2700 | { |
AnnaBridge | 143:86740a56073b | 2701 | return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)); |
AnnaBridge | 143:86740a56073b | 2702 | } |
AnnaBridge | 143:86740a56073b | 2703 | |
AnnaBridge | 143:86740a56073b | 2704 | /** |
AnnaBridge | 143:86740a56073b | 2705 | * @brief Clear the trigger interrupt flag (TIF). |
AnnaBridge | 143:86740a56073b | 2706 | * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG |
AnnaBridge | 143:86740a56073b | 2707 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2708 | * @retval None |
AnnaBridge | 143:86740a56073b | 2709 | */ |
AnnaBridge | 167:84c0a372a020 | 2710 | __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2711 | { |
AnnaBridge | 143:86740a56073b | 2712 | WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); |
AnnaBridge | 143:86740a56073b | 2713 | } |
AnnaBridge | 143:86740a56073b | 2714 | |
AnnaBridge | 143:86740a56073b | 2715 | /** |
AnnaBridge | 143:86740a56073b | 2716 | * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). |
AnnaBridge | 143:86740a56073b | 2717 | * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG |
AnnaBridge | 143:86740a56073b | 2718 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2719 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 2720 | */ |
AnnaBridge | 167:84c0a372a020 | 2721 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2722 | { |
AnnaBridge | 143:86740a56073b | 2723 | return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)); |
AnnaBridge | 143:86740a56073b | 2724 | } |
AnnaBridge | 143:86740a56073b | 2725 | |
AnnaBridge | 143:86740a56073b | 2726 | /** |
AnnaBridge | 143:86740a56073b | 2727 | * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). |
AnnaBridge | 143:86740a56073b | 2728 | * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR |
AnnaBridge | 143:86740a56073b | 2729 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2730 | * @retval None |
AnnaBridge | 143:86740a56073b | 2731 | */ |
AnnaBridge | 167:84c0a372a020 | 2732 | __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2733 | { |
AnnaBridge | 143:86740a56073b | 2734 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); |
AnnaBridge | 143:86740a56073b | 2735 | } |
AnnaBridge | 143:86740a56073b | 2736 | |
AnnaBridge | 143:86740a56073b | 2737 | /** |
AnnaBridge | 143:86740a56073b | 2738 | * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending). |
AnnaBridge | 143:86740a56073b | 2739 | * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR |
AnnaBridge | 143:86740a56073b | 2740 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2741 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 2742 | */ |
AnnaBridge | 167:84c0a372a020 | 2743 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2744 | { |
AnnaBridge | 143:86740a56073b | 2745 | return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)); |
AnnaBridge | 143:86740a56073b | 2746 | } |
AnnaBridge | 143:86740a56073b | 2747 | |
AnnaBridge | 143:86740a56073b | 2748 | /** |
AnnaBridge | 143:86740a56073b | 2749 | * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). |
AnnaBridge | 143:86740a56073b | 2750 | * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR |
AnnaBridge | 143:86740a56073b | 2751 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2752 | * @retval None |
AnnaBridge | 143:86740a56073b | 2753 | */ |
AnnaBridge | 167:84c0a372a020 | 2754 | __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2755 | { |
AnnaBridge | 143:86740a56073b | 2756 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); |
AnnaBridge | 143:86740a56073b | 2757 | } |
AnnaBridge | 143:86740a56073b | 2758 | |
AnnaBridge | 143:86740a56073b | 2759 | /** |
AnnaBridge | 143:86740a56073b | 2760 | * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending). |
AnnaBridge | 143:86740a56073b | 2761 | * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR |
AnnaBridge | 143:86740a56073b | 2762 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2763 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 2764 | */ |
AnnaBridge | 167:84c0a372a020 | 2765 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2766 | { |
AnnaBridge | 143:86740a56073b | 2767 | return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)); |
AnnaBridge | 143:86740a56073b | 2768 | } |
AnnaBridge | 143:86740a56073b | 2769 | |
AnnaBridge | 143:86740a56073b | 2770 | /** |
AnnaBridge | 143:86740a56073b | 2771 | * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). |
AnnaBridge | 143:86740a56073b | 2772 | * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR |
AnnaBridge | 143:86740a56073b | 2773 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2774 | * @retval None |
AnnaBridge | 143:86740a56073b | 2775 | */ |
AnnaBridge | 167:84c0a372a020 | 2776 | __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2777 | { |
AnnaBridge | 143:86740a56073b | 2778 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); |
AnnaBridge | 143:86740a56073b | 2779 | } |
AnnaBridge | 143:86740a56073b | 2780 | |
AnnaBridge | 143:86740a56073b | 2781 | /** |
AnnaBridge | 143:86740a56073b | 2782 | * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending). |
AnnaBridge | 143:86740a56073b | 2783 | * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR |
AnnaBridge | 143:86740a56073b | 2784 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2785 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 2786 | */ |
AnnaBridge | 167:84c0a372a020 | 2787 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2788 | { |
AnnaBridge | 143:86740a56073b | 2789 | return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)); |
AnnaBridge | 143:86740a56073b | 2790 | } |
AnnaBridge | 143:86740a56073b | 2791 | |
AnnaBridge | 143:86740a56073b | 2792 | /** |
AnnaBridge | 143:86740a56073b | 2793 | * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). |
AnnaBridge | 143:86740a56073b | 2794 | * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR |
AnnaBridge | 143:86740a56073b | 2795 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2796 | * @retval None |
AnnaBridge | 143:86740a56073b | 2797 | */ |
AnnaBridge | 167:84c0a372a020 | 2798 | __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2799 | { |
AnnaBridge | 143:86740a56073b | 2800 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); |
AnnaBridge | 143:86740a56073b | 2801 | } |
AnnaBridge | 143:86740a56073b | 2802 | |
AnnaBridge | 143:86740a56073b | 2803 | /** |
AnnaBridge | 143:86740a56073b | 2804 | * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending). |
AnnaBridge | 143:86740a56073b | 2805 | * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR |
AnnaBridge | 143:86740a56073b | 2806 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2807 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 2808 | */ |
AnnaBridge | 167:84c0a372a020 | 2809 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2810 | { |
AnnaBridge | 143:86740a56073b | 2811 | return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)); |
AnnaBridge | 143:86740a56073b | 2812 | } |
AnnaBridge | 143:86740a56073b | 2813 | |
AnnaBridge | 143:86740a56073b | 2814 | /** |
AnnaBridge | 143:86740a56073b | 2815 | * @} |
AnnaBridge | 143:86740a56073b | 2816 | */ |
AnnaBridge | 143:86740a56073b | 2817 | |
AnnaBridge | 143:86740a56073b | 2818 | /** @defgroup TIM_LL_EF_IT_Management IT-Management |
AnnaBridge | 143:86740a56073b | 2819 | * @{ |
AnnaBridge | 143:86740a56073b | 2820 | */ |
AnnaBridge | 143:86740a56073b | 2821 | /** |
AnnaBridge | 143:86740a56073b | 2822 | * @brief Enable update interrupt (UIE). |
AnnaBridge | 143:86740a56073b | 2823 | * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE |
AnnaBridge | 143:86740a56073b | 2824 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2825 | * @retval None |
AnnaBridge | 143:86740a56073b | 2826 | */ |
AnnaBridge | 167:84c0a372a020 | 2827 | __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2828 | { |
AnnaBridge | 143:86740a56073b | 2829 | SET_BIT(TIMx->DIER, TIM_DIER_UIE); |
AnnaBridge | 143:86740a56073b | 2830 | } |
AnnaBridge | 143:86740a56073b | 2831 | |
AnnaBridge | 143:86740a56073b | 2832 | /** |
AnnaBridge | 143:86740a56073b | 2833 | * @brief Disable update interrupt (UIE). |
AnnaBridge | 143:86740a56073b | 2834 | * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE |
AnnaBridge | 143:86740a56073b | 2835 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2836 | * @retval None |
AnnaBridge | 143:86740a56073b | 2837 | */ |
AnnaBridge | 167:84c0a372a020 | 2838 | __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2839 | { |
AnnaBridge | 143:86740a56073b | 2840 | CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); |
AnnaBridge | 143:86740a56073b | 2841 | } |
AnnaBridge | 143:86740a56073b | 2842 | |
AnnaBridge | 143:86740a56073b | 2843 | /** |
AnnaBridge | 143:86740a56073b | 2844 | * @brief Indicates whether the update interrupt (UIE) is enabled. |
AnnaBridge | 143:86740a56073b | 2845 | * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE |
AnnaBridge | 143:86740a56073b | 2846 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2847 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 2848 | */ |
AnnaBridge | 167:84c0a372a020 | 2849 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2850 | { |
AnnaBridge | 143:86740a56073b | 2851 | return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)); |
AnnaBridge | 143:86740a56073b | 2852 | } |
AnnaBridge | 143:86740a56073b | 2853 | |
AnnaBridge | 143:86740a56073b | 2854 | /** |
AnnaBridge | 143:86740a56073b | 2855 | * @brief Enable capture/compare 1 interrupt (CC1IE). |
AnnaBridge | 143:86740a56073b | 2856 | * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 |
AnnaBridge | 143:86740a56073b | 2857 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2858 | * @retval None |
AnnaBridge | 143:86740a56073b | 2859 | */ |
AnnaBridge | 167:84c0a372a020 | 2860 | __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2861 | { |
AnnaBridge | 143:86740a56073b | 2862 | SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); |
AnnaBridge | 143:86740a56073b | 2863 | } |
AnnaBridge | 143:86740a56073b | 2864 | |
AnnaBridge | 143:86740a56073b | 2865 | /** |
AnnaBridge | 143:86740a56073b | 2866 | * @brief Disable capture/compare 1 interrupt (CC1IE). |
AnnaBridge | 143:86740a56073b | 2867 | * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 |
AnnaBridge | 143:86740a56073b | 2868 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2869 | * @retval None |
AnnaBridge | 143:86740a56073b | 2870 | */ |
AnnaBridge | 167:84c0a372a020 | 2871 | __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2872 | { |
AnnaBridge | 143:86740a56073b | 2873 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); |
AnnaBridge | 143:86740a56073b | 2874 | } |
AnnaBridge | 143:86740a56073b | 2875 | |
AnnaBridge | 143:86740a56073b | 2876 | /** |
AnnaBridge | 143:86740a56073b | 2877 | * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. |
AnnaBridge | 143:86740a56073b | 2878 | * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 |
AnnaBridge | 143:86740a56073b | 2879 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2880 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 2881 | */ |
AnnaBridge | 167:84c0a372a020 | 2882 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2883 | { |
AnnaBridge | 143:86740a56073b | 2884 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)); |
AnnaBridge | 143:86740a56073b | 2885 | } |
AnnaBridge | 143:86740a56073b | 2886 | |
AnnaBridge | 143:86740a56073b | 2887 | /** |
AnnaBridge | 143:86740a56073b | 2888 | * @brief Enable capture/compare 2 interrupt (CC2IE). |
AnnaBridge | 143:86740a56073b | 2889 | * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 |
AnnaBridge | 143:86740a56073b | 2890 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2891 | * @retval None |
AnnaBridge | 143:86740a56073b | 2892 | */ |
AnnaBridge | 167:84c0a372a020 | 2893 | __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2894 | { |
AnnaBridge | 143:86740a56073b | 2895 | SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); |
AnnaBridge | 143:86740a56073b | 2896 | } |
AnnaBridge | 143:86740a56073b | 2897 | |
AnnaBridge | 143:86740a56073b | 2898 | /** |
AnnaBridge | 143:86740a56073b | 2899 | * @brief Disable capture/compare 2 interrupt (CC2IE). |
AnnaBridge | 143:86740a56073b | 2900 | * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 |
AnnaBridge | 143:86740a56073b | 2901 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2902 | * @retval None |
AnnaBridge | 143:86740a56073b | 2903 | */ |
AnnaBridge | 167:84c0a372a020 | 2904 | __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2905 | { |
AnnaBridge | 143:86740a56073b | 2906 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); |
AnnaBridge | 143:86740a56073b | 2907 | } |
AnnaBridge | 143:86740a56073b | 2908 | |
AnnaBridge | 143:86740a56073b | 2909 | /** |
AnnaBridge | 143:86740a56073b | 2910 | * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. |
AnnaBridge | 143:86740a56073b | 2911 | * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 |
AnnaBridge | 143:86740a56073b | 2912 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2913 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 2914 | */ |
AnnaBridge | 167:84c0a372a020 | 2915 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2916 | { |
AnnaBridge | 143:86740a56073b | 2917 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)); |
AnnaBridge | 143:86740a56073b | 2918 | } |
AnnaBridge | 143:86740a56073b | 2919 | |
AnnaBridge | 143:86740a56073b | 2920 | /** |
AnnaBridge | 143:86740a56073b | 2921 | * @brief Enable capture/compare 3 interrupt (CC3IE). |
AnnaBridge | 143:86740a56073b | 2922 | * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 |
AnnaBridge | 143:86740a56073b | 2923 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2924 | * @retval None |
AnnaBridge | 143:86740a56073b | 2925 | */ |
AnnaBridge | 167:84c0a372a020 | 2926 | __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2927 | { |
AnnaBridge | 143:86740a56073b | 2928 | SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); |
AnnaBridge | 143:86740a56073b | 2929 | } |
AnnaBridge | 143:86740a56073b | 2930 | |
AnnaBridge | 143:86740a56073b | 2931 | /** |
AnnaBridge | 143:86740a56073b | 2932 | * @brief Disable capture/compare 3 interrupt (CC3IE). |
AnnaBridge | 143:86740a56073b | 2933 | * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 |
AnnaBridge | 143:86740a56073b | 2934 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2935 | * @retval None |
AnnaBridge | 143:86740a56073b | 2936 | */ |
AnnaBridge | 167:84c0a372a020 | 2937 | __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2938 | { |
AnnaBridge | 143:86740a56073b | 2939 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); |
AnnaBridge | 143:86740a56073b | 2940 | } |
AnnaBridge | 143:86740a56073b | 2941 | |
AnnaBridge | 143:86740a56073b | 2942 | /** |
AnnaBridge | 143:86740a56073b | 2943 | * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. |
AnnaBridge | 143:86740a56073b | 2944 | * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 |
AnnaBridge | 143:86740a56073b | 2945 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2946 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 2947 | */ |
AnnaBridge | 167:84c0a372a020 | 2948 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2949 | { |
AnnaBridge | 143:86740a56073b | 2950 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)); |
AnnaBridge | 143:86740a56073b | 2951 | } |
AnnaBridge | 143:86740a56073b | 2952 | |
AnnaBridge | 143:86740a56073b | 2953 | /** |
AnnaBridge | 143:86740a56073b | 2954 | * @brief Enable capture/compare 4 interrupt (CC4IE). |
AnnaBridge | 143:86740a56073b | 2955 | * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 |
AnnaBridge | 143:86740a56073b | 2956 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2957 | * @retval None |
AnnaBridge | 143:86740a56073b | 2958 | */ |
AnnaBridge | 167:84c0a372a020 | 2959 | __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2960 | { |
AnnaBridge | 143:86740a56073b | 2961 | SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); |
AnnaBridge | 143:86740a56073b | 2962 | } |
AnnaBridge | 143:86740a56073b | 2963 | |
AnnaBridge | 143:86740a56073b | 2964 | /** |
AnnaBridge | 143:86740a56073b | 2965 | * @brief Disable capture/compare 4 interrupt (CC4IE). |
AnnaBridge | 143:86740a56073b | 2966 | * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 |
AnnaBridge | 143:86740a56073b | 2967 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2968 | * @retval None |
AnnaBridge | 143:86740a56073b | 2969 | */ |
AnnaBridge | 167:84c0a372a020 | 2970 | __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2971 | { |
AnnaBridge | 143:86740a56073b | 2972 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); |
AnnaBridge | 143:86740a56073b | 2973 | } |
AnnaBridge | 143:86740a56073b | 2974 | |
AnnaBridge | 143:86740a56073b | 2975 | /** |
AnnaBridge | 143:86740a56073b | 2976 | * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. |
AnnaBridge | 143:86740a56073b | 2977 | * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 |
AnnaBridge | 143:86740a56073b | 2978 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2979 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 2980 | */ |
AnnaBridge | 167:84c0a372a020 | 2981 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2982 | { |
AnnaBridge | 143:86740a56073b | 2983 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)); |
AnnaBridge | 143:86740a56073b | 2984 | } |
AnnaBridge | 143:86740a56073b | 2985 | |
AnnaBridge | 143:86740a56073b | 2986 | /** |
AnnaBridge | 143:86740a56073b | 2987 | * @brief Enable trigger interrupt (TIE). |
AnnaBridge | 143:86740a56073b | 2988 | * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG |
AnnaBridge | 143:86740a56073b | 2989 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 2990 | * @retval None |
AnnaBridge | 143:86740a56073b | 2991 | */ |
AnnaBridge | 167:84c0a372a020 | 2992 | __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 2993 | { |
AnnaBridge | 143:86740a56073b | 2994 | SET_BIT(TIMx->DIER, TIM_DIER_TIE); |
AnnaBridge | 143:86740a56073b | 2995 | } |
AnnaBridge | 143:86740a56073b | 2996 | |
AnnaBridge | 143:86740a56073b | 2997 | /** |
AnnaBridge | 143:86740a56073b | 2998 | * @brief Disable trigger interrupt (TIE). |
AnnaBridge | 143:86740a56073b | 2999 | * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG |
AnnaBridge | 143:86740a56073b | 3000 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3001 | * @retval None |
AnnaBridge | 143:86740a56073b | 3002 | */ |
AnnaBridge | 167:84c0a372a020 | 3003 | __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3004 | { |
AnnaBridge | 143:86740a56073b | 3005 | CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); |
AnnaBridge | 143:86740a56073b | 3006 | } |
AnnaBridge | 143:86740a56073b | 3007 | |
AnnaBridge | 143:86740a56073b | 3008 | /** |
AnnaBridge | 143:86740a56073b | 3009 | * @brief Indicates whether the trigger interrupt (TIE) is enabled. |
AnnaBridge | 143:86740a56073b | 3010 | * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG |
AnnaBridge | 143:86740a56073b | 3011 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3012 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 3013 | */ |
AnnaBridge | 167:84c0a372a020 | 3014 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3015 | { |
AnnaBridge | 143:86740a56073b | 3016 | return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)); |
AnnaBridge | 143:86740a56073b | 3017 | } |
AnnaBridge | 143:86740a56073b | 3018 | |
AnnaBridge | 143:86740a56073b | 3019 | /** |
AnnaBridge | 143:86740a56073b | 3020 | * @} |
AnnaBridge | 143:86740a56073b | 3021 | */ |
AnnaBridge | 143:86740a56073b | 3022 | |
AnnaBridge | 143:86740a56073b | 3023 | /** @defgroup TIM_LL_EF_DMA_Management DMA-Management |
AnnaBridge | 143:86740a56073b | 3024 | * @{ |
AnnaBridge | 143:86740a56073b | 3025 | */ |
AnnaBridge | 143:86740a56073b | 3026 | /** |
AnnaBridge | 143:86740a56073b | 3027 | * @brief Enable update DMA request (UDE). |
AnnaBridge | 143:86740a56073b | 3028 | * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE |
AnnaBridge | 143:86740a56073b | 3029 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3030 | * @retval None |
AnnaBridge | 143:86740a56073b | 3031 | */ |
AnnaBridge | 167:84c0a372a020 | 3032 | __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3033 | { |
AnnaBridge | 143:86740a56073b | 3034 | SET_BIT(TIMx->DIER, TIM_DIER_UDE); |
AnnaBridge | 143:86740a56073b | 3035 | } |
AnnaBridge | 143:86740a56073b | 3036 | |
AnnaBridge | 143:86740a56073b | 3037 | /** |
AnnaBridge | 143:86740a56073b | 3038 | * @brief Disable update DMA request (UDE). |
AnnaBridge | 143:86740a56073b | 3039 | * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE |
AnnaBridge | 143:86740a56073b | 3040 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3041 | * @retval None |
AnnaBridge | 143:86740a56073b | 3042 | */ |
AnnaBridge | 167:84c0a372a020 | 3043 | __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3044 | { |
AnnaBridge | 143:86740a56073b | 3045 | CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); |
AnnaBridge | 143:86740a56073b | 3046 | } |
AnnaBridge | 143:86740a56073b | 3047 | |
AnnaBridge | 143:86740a56073b | 3048 | /** |
AnnaBridge | 143:86740a56073b | 3049 | * @brief Indicates whether the update DMA request (UDE) is enabled. |
AnnaBridge | 143:86740a56073b | 3050 | * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE |
AnnaBridge | 143:86740a56073b | 3051 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3052 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 3053 | */ |
AnnaBridge | 167:84c0a372a020 | 3054 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3055 | { |
AnnaBridge | 143:86740a56073b | 3056 | return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)); |
AnnaBridge | 143:86740a56073b | 3057 | } |
AnnaBridge | 143:86740a56073b | 3058 | |
AnnaBridge | 143:86740a56073b | 3059 | /** |
AnnaBridge | 143:86740a56073b | 3060 | * @brief Enable capture/compare 1 DMA request (CC1DE). |
AnnaBridge | 143:86740a56073b | 3061 | * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 |
AnnaBridge | 143:86740a56073b | 3062 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3063 | * @retval None |
AnnaBridge | 143:86740a56073b | 3064 | */ |
AnnaBridge | 167:84c0a372a020 | 3065 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3066 | { |
AnnaBridge | 143:86740a56073b | 3067 | SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); |
AnnaBridge | 143:86740a56073b | 3068 | } |
AnnaBridge | 143:86740a56073b | 3069 | |
AnnaBridge | 143:86740a56073b | 3070 | /** |
AnnaBridge | 143:86740a56073b | 3071 | * @brief Disable capture/compare 1 DMA request (CC1DE). |
AnnaBridge | 143:86740a56073b | 3072 | * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 |
AnnaBridge | 143:86740a56073b | 3073 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3074 | * @retval None |
AnnaBridge | 143:86740a56073b | 3075 | */ |
AnnaBridge | 167:84c0a372a020 | 3076 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3077 | { |
AnnaBridge | 143:86740a56073b | 3078 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); |
AnnaBridge | 143:86740a56073b | 3079 | } |
AnnaBridge | 143:86740a56073b | 3080 | |
AnnaBridge | 143:86740a56073b | 3081 | /** |
AnnaBridge | 143:86740a56073b | 3082 | * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. |
AnnaBridge | 143:86740a56073b | 3083 | * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 |
AnnaBridge | 143:86740a56073b | 3084 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3085 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 3086 | */ |
AnnaBridge | 167:84c0a372a020 | 3087 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3088 | { |
AnnaBridge | 143:86740a56073b | 3089 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)); |
AnnaBridge | 143:86740a56073b | 3090 | } |
AnnaBridge | 143:86740a56073b | 3091 | |
AnnaBridge | 143:86740a56073b | 3092 | /** |
AnnaBridge | 143:86740a56073b | 3093 | * @brief Enable capture/compare 2 DMA request (CC2DE). |
AnnaBridge | 143:86740a56073b | 3094 | * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 |
AnnaBridge | 143:86740a56073b | 3095 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3096 | * @retval None |
AnnaBridge | 143:86740a56073b | 3097 | */ |
AnnaBridge | 167:84c0a372a020 | 3098 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3099 | { |
AnnaBridge | 143:86740a56073b | 3100 | SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); |
AnnaBridge | 143:86740a56073b | 3101 | } |
AnnaBridge | 143:86740a56073b | 3102 | |
AnnaBridge | 143:86740a56073b | 3103 | /** |
AnnaBridge | 143:86740a56073b | 3104 | * @brief Disable capture/compare 2 DMA request (CC2DE). |
AnnaBridge | 143:86740a56073b | 3105 | * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 |
AnnaBridge | 143:86740a56073b | 3106 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3107 | * @retval None |
AnnaBridge | 143:86740a56073b | 3108 | */ |
AnnaBridge | 167:84c0a372a020 | 3109 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3110 | { |
AnnaBridge | 143:86740a56073b | 3111 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); |
AnnaBridge | 143:86740a56073b | 3112 | } |
AnnaBridge | 143:86740a56073b | 3113 | |
AnnaBridge | 143:86740a56073b | 3114 | /** |
AnnaBridge | 143:86740a56073b | 3115 | * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. |
AnnaBridge | 143:86740a56073b | 3116 | * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 |
AnnaBridge | 143:86740a56073b | 3117 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3118 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 3119 | */ |
AnnaBridge | 167:84c0a372a020 | 3120 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3121 | { |
AnnaBridge | 143:86740a56073b | 3122 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)); |
AnnaBridge | 143:86740a56073b | 3123 | } |
AnnaBridge | 143:86740a56073b | 3124 | |
AnnaBridge | 143:86740a56073b | 3125 | /** |
AnnaBridge | 143:86740a56073b | 3126 | * @brief Enable capture/compare 3 DMA request (CC3DE). |
AnnaBridge | 143:86740a56073b | 3127 | * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 |
AnnaBridge | 143:86740a56073b | 3128 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3129 | * @retval None |
AnnaBridge | 143:86740a56073b | 3130 | */ |
AnnaBridge | 167:84c0a372a020 | 3131 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3132 | { |
AnnaBridge | 143:86740a56073b | 3133 | SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); |
AnnaBridge | 143:86740a56073b | 3134 | } |
AnnaBridge | 143:86740a56073b | 3135 | |
AnnaBridge | 143:86740a56073b | 3136 | /** |
AnnaBridge | 143:86740a56073b | 3137 | * @brief Disable capture/compare 3 DMA request (CC3DE). |
AnnaBridge | 143:86740a56073b | 3138 | * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 |
AnnaBridge | 143:86740a56073b | 3139 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3140 | * @retval None |
AnnaBridge | 143:86740a56073b | 3141 | */ |
AnnaBridge | 167:84c0a372a020 | 3142 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3143 | { |
AnnaBridge | 143:86740a56073b | 3144 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); |
AnnaBridge | 143:86740a56073b | 3145 | } |
AnnaBridge | 143:86740a56073b | 3146 | |
AnnaBridge | 143:86740a56073b | 3147 | /** |
AnnaBridge | 143:86740a56073b | 3148 | * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. |
AnnaBridge | 143:86740a56073b | 3149 | * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 |
AnnaBridge | 143:86740a56073b | 3150 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3151 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 3152 | */ |
AnnaBridge | 167:84c0a372a020 | 3153 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3154 | { |
AnnaBridge | 143:86740a56073b | 3155 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)); |
AnnaBridge | 143:86740a56073b | 3156 | } |
AnnaBridge | 143:86740a56073b | 3157 | |
AnnaBridge | 143:86740a56073b | 3158 | /** |
AnnaBridge | 143:86740a56073b | 3159 | * @brief Enable capture/compare 4 DMA request (CC4DE). |
AnnaBridge | 143:86740a56073b | 3160 | * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 |
AnnaBridge | 143:86740a56073b | 3161 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3162 | * @retval None |
AnnaBridge | 143:86740a56073b | 3163 | */ |
AnnaBridge | 167:84c0a372a020 | 3164 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3165 | { |
AnnaBridge | 143:86740a56073b | 3166 | SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); |
AnnaBridge | 143:86740a56073b | 3167 | } |
AnnaBridge | 143:86740a56073b | 3168 | |
AnnaBridge | 143:86740a56073b | 3169 | /** |
AnnaBridge | 143:86740a56073b | 3170 | * @brief Disable capture/compare 4 DMA request (CC4DE). |
AnnaBridge | 143:86740a56073b | 3171 | * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 |
AnnaBridge | 143:86740a56073b | 3172 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3173 | * @retval None |
AnnaBridge | 143:86740a56073b | 3174 | */ |
AnnaBridge | 167:84c0a372a020 | 3175 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3176 | { |
AnnaBridge | 143:86740a56073b | 3177 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); |
AnnaBridge | 143:86740a56073b | 3178 | } |
AnnaBridge | 143:86740a56073b | 3179 | |
AnnaBridge | 143:86740a56073b | 3180 | /** |
AnnaBridge | 143:86740a56073b | 3181 | * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. |
AnnaBridge | 143:86740a56073b | 3182 | * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 |
AnnaBridge | 143:86740a56073b | 3183 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3184 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 3185 | */ |
AnnaBridge | 167:84c0a372a020 | 3186 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3187 | { |
AnnaBridge | 143:86740a56073b | 3188 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)); |
AnnaBridge | 143:86740a56073b | 3189 | } |
AnnaBridge | 143:86740a56073b | 3190 | |
AnnaBridge | 143:86740a56073b | 3191 | /** |
AnnaBridge | 143:86740a56073b | 3192 | * @brief Enable trigger interrupt (TDE). |
AnnaBridge | 143:86740a56073b | 3193 | * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG |
AnnaBridge | 143:86740a56073b | 3194 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3195 | * @retval None |
AnnaBridge | 143:86740a56073b | 3196 | */ |
AnnaBridge | 167:84c0a372a020 | 3197 | __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3198 | { |
AnnaBridge | 143:86740a56073b | 3199 | SET_BIT(TIMx->DIER, TIM_DIER_TDE); |
AnnaBridge | 143:86740a56073b | 3200 | } |
AnnaBridge | 143:86740a56073b | 3201 | |
AnnaBridge | 143:86740a56073b | 3202 | /** |
AnnaBridge | 143:86740a56073b | 3203 | * @brief Disable trigger interrupt (TDE). |
AnnaBridge | 143:86740a56073b | 3204 | * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG |
AnnaBridge | 143:86740a56073b | 3205 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3206 | * @retval None |
AnnaBridge | 143:86740a56073b | 3207 | */ |
AnnaBridge | 167:84c0a372a020 | 3208 | __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3209 | { |
AnnaBridge | 143:86740a56073b | 3210 | CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); |
AnnaBridge | 143:86740a56073b | 3211 | } |
AnnaBridge | 143:86740a56073b | 3212 | |
AnnaBridge | 143:86740a56073b | 3213 | /** |
AnnaBridge | 143:86740a56073b | 3214 | * @brief Indicates whether the trigger interrupt (TDE) is enabled. |
AnnaBridge | 143:86740a56073b | 3215 | * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG |
AnnaBridge | 143:86740a56073b | 3216 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3217 | * @retval State of bit (1 or 0). |
AnnaBridge | 143:86740a56073b | 3218 | */ |
AnnaBridge | 167:84c0a372a020 | 3219 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3220 | { |
AnnaBridge | 143:86740a56073b | 3221 | return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)); |
AnnaBridge | 143:86740a56073b | 3222 | } |
AnnaBridge | 143:86740a56073b | 3223 | |
AnnaBridge | 143:86740a56073b | 3224 | /** |
AnnaBridge | 143:86740a56073b | 3225 | * @} |
AnnaBridge | 143:86740a56073b | 3226 | */ |
AnnaBridge | 143:86740a56073b | 3227 | |
AnnaBridge | 143:86740a56073b | 3228 | /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management |
AnnaBridge | 143:86740a56073b | 3229 | * @{ |
AnnaBridge | 143:86740a56073b | 3230 | */ |
AnnaBridge | 143:86740a56073b | 3231 | /** |
AnnaBridge | 143:86740a56073b | 3232 | * @brief Generate an update event. |
AnnaBridge | 143:86740a56073b | 3233 | * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE |
AnnaBridge | 143:86740a56073b | 3234 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3235 | * @retval None |
AnnaBridge | 143:86740a56073b | 3236 | */ |
AnnaBridge | 167:84c0a372a020 | 3237 | __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3238 | { |
AnnaBridge | 143:86740a56073b | 3239 | SET_BIT(TIMx->EGR, TIM_EGR_UG); |
AnnaBridge | 143:86740a56073b | 3240 | } |
AnnaBridge | 143:86740a56073b | 3241 | |
AnnaBridge | 143:86740a56073b | 3242 | /** |
AnnaBridge | 143:86740a56073b | 3243 | * @brief Generate Capture/Compare 1 event. |
AnnaBridge | 143:86740a56073b | 3244 | * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 |
AnnaBridge | 143:86740a56073b | 3245 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3246 | * @retval None |
AnnaBridge | 143:86740a56073b | 3247 | */ |
AnnaBridge | 167:84c0a372a020 | 3248 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3249 | { |
AnnaBridge | 143:86740a56073b | 3250 | SET_BIT(TIMx->EGR, TIM_EGR_CC1G); |
AnnaBridge | 143:86740a56073b | 3251 | } |
AnnaBridge | 143:86740a56073b | 3252 | |
AnnaBridge | 143:86740a56073b | 3253 | /** |
AnnaBridge | 143:86740a56073b | 3254 | * @brief Generate Capture/Compare 2 event. |
AnnaBridge | 143:86740a56073b | 3255 | * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 |
AnnaBridge | 143:86740a56073b | 3256 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3257 | * @retval None |
AnnaBridge | 143:86740a56073b | 3258 | */ |
AnnaBridge | 167:84c0a372a020 | 3259 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3260 | { |
AnnaBridge | 143:86740a56073b | 3261 | SET_BIT(TIMx->EGR, TIM_EGR_CC2G); |
AnnaBridge | 143:86740a56073b | 3262 | } |
AnnaBridge | 143:86740a56073b | 3263 | |
AnnaBridge | 143:86740a56073b | 3264 | /** |
AnnaBridge | 143:86740a56073b | 3265 | * @brief Generate Capture/Compare 3 event. |
AnnaBridge | 143:86740a56073b | 3266 | * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 |
AnnaBridge | 143:86740a56073b | 3267 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3268 | * @retval None |
AnnaBridge | 143:86740a56073b | 3269 | */ |
AnnaBridge | 167:84c0a372a020 | 3270 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3271 | { |
AnnaBridge | 143:86740a56073b | 3272 | SET_BIT(TIMx->EGR, TIM_EGR_CC3G); |
AnnaBridge | 143:86740a56073b | 3273 | } |
AnnaBridge | 143:86740a56073b | 3274 | |
AnnaBridge | 143:86740a56073b | 3275 | /** |
AnnaBridge | 143:86740a56073b | 3276 | * @brief Generate Capture/Compare 4 event. |
AnnaBridge | 143:86740a56073b | 3277 | * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 |
AnnaBridge | 143:86740a56073b | 3278 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3279 | * @retval None |
AnnaBridge | 143:86740a56073b | 3280 | */ |
AnnaBridge | 167:84c0a372a020 | 3281 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3282 | { |
AnnaBridge | 143:86740a56073b | 3283 | SET_BIT(TIMx->EGR, TIM_EGR_CC4G); |
AnnaBridge | 143:86740a56073b | 3284 | } |
AnnaBridge | 143:86740a56073b | 3285 | |
AnnaBridge | 143:86740a56073b | 3286 | /** |
AnnaBridge | 143:86740a56073b | 3287 | * @brief Generate trigger event. |
AnnaBridge | 143:86740a56073b | 3288 | * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG |
AnnaBridge | 143:86740a56073b | 3289 | * @param TIMx Timer instance |
AnnaBridge | 143:86740a56073b | 3290 | * @retval None |
AnnaBridge | 143:86740a56073b | 3291 | */ |
AnnaBridge | 167:84c0a372a020 | 3292 | __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) |
AnnaBridge | 143:86740a56073b | 3293 | { |
AnnaBridge | 143:86740a56073b | 3294 | SET_BIT(TIMx->EGR, TIM_EGR_TG); |
AnnaBridge | 143:86740a56073b | 3295 | } |
AnnaBridge | 143:86740a56073b | 3296 | |
AnnaBridge | 143:86740a56073b | 3297 | /** |
AnnaBridge | 143:86740a56073b | 3298 | * @} |
AnnaBridge | 143:86740a56073b | 3299 | */ |
AnnaBridge | 143:86740a56073b | 3300 | |
AnnaBridge | 143:86740a56073b | 3301 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 143:86740a56073b | 3302 | /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions |
AnnaBridge | 143:86740a56073b | 3303 | * @{ |
AnnaBridge | 143:86740a56073b | 3304 | */ |
AnnaBridge | 167:84c0a372a020 | 3305 | |
AnnaBridge | 167:84c0a372a020 | 3306 | ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); |
AnnaBridge | 167:84c0a372a020 | 3307 | void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); |
AnnaBridge | 167:84c0a372a020 | 3308 | ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); |
AnnaBridge | 167:84c0a372a020 | 3309 | void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); |
AnnaBridge | 167:84c0a372a020 | 3310 | ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); |
AnnaBridge | 167:84c0a372a020 | 3311 | void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); |
AnnaBridge | 167:84c0a372a020 | 3312 | ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); |
AnnaBridge | 167:84c0a372a020 | 3313 | void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); |
AnnaBridge | 167:84c0a372a020 | 3314 | ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); |
AnnaBridge | 143:86740a56073b | 3315 | /** |
AnnaBridge | 143:86740a56073b | 3316 | * @} |
AnnaBridge | 143:86740a56073b | 3317 | */ |
AnnaBridge | 143:86740a56073b | 3318 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 143:86740a56073b | 3319 | |
AnnaBridge | 143:86740a56073b | 3320 | /** |
AnnaBridge | 143:86740a56073b | 3321 | * @} |
AnnaBridge | 143:86740a56073b | 3322 | */ |
AnnaBridge | 143:86740a56073b | 3323 | |
AnnaBridge | 143:86740a56073b | 3324 | /** |
AnnaBridge | 143:86740a56073b | 3325 | * @} |
AnnaBridge | 143:86740a56073b | 3326 | */ |
AnnaBridge | 143:86740a56073b | 3327 | |
AnnaBridge | 143:86740a56073b | 3328 | #endif /* TIM1 || TIM3 || TIM21 || TIM22 || TIM6 || TIM7 */ |
AnnaBridge | 143:86740a56073b | 3329 | |
AnnaBridge | 143:86740a56073b | 3330 | /** |
AnnaBridge | 143:86740a56073b | 3331 | * @} |
AnnaBridge | 143:86740a56073b | 3332 | */ |
AnnaBridge | 143:86740a56073b | 3333 | |
AnnaBridge | 143:86740a56073b | 3334 | #ifdef __cplusplus |
AnnaBridge | 143:86740a56073b | 3335 | } |
AnnaBridge | 143:86740a56073b | 3336 | #endif |
AnnaBridge | 143:86740a56073b | 3337 | |
AnnaBridge | 143:86740a56073b | 3338 | #endif /* __STM32L0xx_LL_TIM_H */ |
AnnaBridge | 143:86740a56073b | 3339 | |
AnnaBridge | 143:86740a56073b | 3340 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |