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TARGET_NUCLEO_F756ZG/TOOLCHAIN_ARM_MICRO/stm32f7xx_hal_rcc_ex.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f7xx_hal_rcc_ex.h |
AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of RCC HAL Extension module. |
AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
AnnaBridge | 171:3a7713b1edbc | 8 | * |
AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
AnnaBridge | 171:3a7713b1edbc | 10 | * |
AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 32 | * |
AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 34 | */ |
AnnaBridge | 171:3a7713b1edbc | 35 | |
AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F7xx_HAL_RCC_EX_H |
AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F7xx_HAL_RCC_EX_H |
AnnaBridge | 171:3a7713b1edbc | 39 | |
AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
AnnaBridge | 171:3a7713b1edbc | 43 | |
AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f7xx_hal_def.h" |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32F7xx_HAL_Driver |
AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 49 | */ |
AnnaBridge | 171:3a7713b1edbc | 50 | |
AnnaBridge | 171:3a7713b1edbc | 51 | /** @addtogroup RCCEx |
AnnaBridge | 171:3a7713b1edbc | 52 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 53 | */ |
AnnaBridge | 171:3a7713b1edbc | 54 | |
AnnaBridge | 171:3a7713b1edbc | 55 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 56 | /** @defgroup RCCEx_Exported_Types RCCEx Exported Types |
AnnaBridge | 171:3a7713b1edbc | 57 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 58 | */ |
AnnaBridge | 171:3a7713b1edbc | 59 | |
AnnaBridge | 171:3a7713b1edbc | 60 | /** |
AnnaBridge | 171:3a7713b1edbc | 61 | * @brief RCC PLL configuration structure definition |
AnnaBridge | 171:3a7713b1edbc | 62 | */ |
AnnaBridge | 171:3a7713b1edbc | 63 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 64 | { |
AnnaBridge | 171:3a7713b1edbc | 65 | uint32_t PLLState; /*!< The new state of the PLL. |
AnnaBridge | 171:3a7713b1edbc | 66 | This parameter can be a value of @ref RCC_PLL_Config */ |
AnnaBridge | 171:3a7713b1edbc | 67 | |
AnnaBridge | 171:3a7713b1edbc | 68 | uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. |
AnnaBridge | 171:3a7713b1edbc | 69 | This parameter must be a value of @ref RCC_PLL_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 70 | |
AnnaBridge | 171:3a7713b1edbc | 71 | uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. |
AnnaBridge | 171:3a7713b1edbc | 72 | This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ |
AnnaBridge | 171:3a7713b1edbc | 73 | |
AnnaBridge | 171:3a7713b1edbc | 74 | uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. |
AnnaBridge | 171:3a7713b1edbc | 75 | This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ |
AnnaBridge | 171:3a7713b1edbc | 76 | |
AnnaBridge | 171:3a7713b1edbc | 77 | uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). |
AnnaBridge | 171:3a7713b1edbc | 78 | This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ |
AnnaBridge | 171:3a7713b1edbc | 79 | |
AnnaBridge | 171:3a7713b1edbc | 80 | uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks. |
AnnaBridge | 171:3a7713b1edbc | 81 | This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ |
AnnaBridge | 171:3a7713b1edbc | 82 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 83 | uint32_t PLLR; /*!< PLLR: Division factor for DSI clock. |
AnnaBridge | 171:3a7713b1edbc | 84 | This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ |
AnnaBridge | 171:3a7713b1edbc | 85 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 86 | |
AnnaBridge | 171:3a7713b1edbc | 87 | }RCC_PLLInitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 88 | |
AnnaBridge | 171:3a7713b1edbc | 89 | /** |
AnnaBridge | 171:3a7713b1edbc | 90 | * @brief PLLI2S Clock structure definition |
AnnaBridge | 171:3a7713b1edbc | 91 | */ |
AnnaBridge | 171:3a7713b1edbc | 92 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 93 | { |
AnnaBridge | 171:3a7713b1edbc | 94 | uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. |
AnnaBridge | 171:3a7713b1edbc | 95 | This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
AnnaBridge | 171:3a7713b1edbc | 96 | This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ |
AnnaBridge | 171:3a7713b1edbc | 97 | |
AnnaBridge | 171:3a7713b1edbc | 98 | uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. |
AnnaBridge | 171:3a7713b1edbc | 99 | This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
AnnaBridge | 171:3a7713b1edbc | 100 | This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ |
AnnaBridge | 171:3a7713b1edbc | 101 | |
AnnaBridge | 171:3a7713b1edbc | 102 | uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. |
AnnaBridge | 171:3a7713b1edbc | 103 | This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
AnnaBridge | 171:3a7713b1edbc | 104 | This parameter will be used only when PLLI2S is selected as Clock Source SAI */ |
AnnaBridge | 171:3a7713b1edbc | 105 | |
AnnaBridge | 171:3a7713b1edbc | 106 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ |
AnnaBridge | 171:3a7713b1edbc | 107 | defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 108 | uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock. |
AnnaBridge | 171:3a7713b1edbc | 109 | This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider. |
AnnaBridge | 171:3a7713b1edbc | 110 | This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */ |
AnnaBridge | 171:3a7713b1edbc | 111 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 112 | }RCC_PLLI2SInitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 113 | |
AnnaBridge | 171:3a7713b1edbc | 114 | /** |
AnnaBridge | 171:3a7713b1edbc | 115 | * @brief PLLSAI Clock structure definition |
AnnaBridge | 171:3a7713b1edbc | 116 | */ |
AnnaBridge | 171:3a7713b1edbc | 117 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 118 | { |
AnnaBridge | 171:3a7713b1edbc | 119 | uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. |
AnnaBridge | 171:3a7713b1edbc | 120 | This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
AnnaBridge | 171:3a7713b1edbc | 121 | This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ |
AnnaBridge | 171:3a7713b1edbc | 122 | |
AnnaBridge | 171:3a7713b1edbc | 123 | uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. |
AnnaBridge | 171:3a7713b1edbc | 124 | This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
AnnaBridge | 171:3a7713b1edbc | 125 | This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ |
AnnaBridge | 171:3a7713b1edbc | 126 | |
AnnaBridge | 171:3a7713b1edbc | 127 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ |
AnnaBridge | 171:3a7713b1edbc | 128 | defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 129 | uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock |
AnnaBridge | 171:3a7713b1edbc | 130 | This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
AnnaBridge | 171:3a7713b1edbc | 131 | This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ |
AnnaBridge | 171:3a7713b1edbc | 132 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 133 | |
AnnaBridge | 171:3a7713b1edbc | 134 | uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock. |
AnnaBridge | 171:3a7713b1edbc | 135 | This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider |
AnnaBridge | 171:3a7713b1edbc | 136 | This parameter will be used only when PLLSAI is disabled */ |
AnnaBridge | 171:3a7713b1edbc | 137 | }RCC_PLLSAIInitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 138 | |
AnnaBridge | 171:3a7713b1edbc | 139 | /** |
AnnaBridge | 171:3a7713b1edbc | 140 | * @brief RCC extended clocks structure definition |
AnnaBridge | 171:3a7713b1edbc | 141 | */ |
AnnaBridge | 171:3a7713b1edbc | 142 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 143 | { |
AnnaBridge | 171:3a7713b1edbc | 144 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
AnnaBridge | 171:3a7713b1edbc | 145 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
AnnaBridge | 171:3a7713b1edbc | 146 | |
AnnaBridge | 171:3a7713b1edbc | 147 | RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. |
AnnaBridge | 171:3a7713b1edbc | 148 | This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ |
AnnaBridge | 171:3a7713b1edbc | 149 | |
AnnaBridge | 171:3a7713b1edbc | 150 | RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. |
AnnaBridge | 171:3a7713b1edbc | 151 | This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ |
AnnaBridge | 171:3a7713b1edbc | 152 | |
AnnaBridge | 171:3a7713b1edbc | 153 | uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. |
AnnaBridge | 171:3a7713b1edbc | 154 | This parameter must be a number between Min_Data = 1 and Max_Data = 32 |
AnnaBridge | 171:3a7713b1edbc | 155 | This parameter will be used only when PLLI2S is selected as Clock Source SAI */ |
AnnaBridge | 171:3a7713b1edbc | 156 | |
AnnaBridge | 171:3a7713b1edbc | 157 | uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. |
AnnaBridge | 171:3a7713b1edbc | 158 | This parameter must be a number between Min_Data = 1 and Max_Data = 32 |
AnnaBridge | 171:3a7713b1edbc | 159 | This parameter will be used only when PLLSAI is selected as Clock Source SAI */ |
AnnaBridge | 171:3a7713b1edbc | 160 | |
AnnaBridge | 171:3a7713b1edbc | 161 | uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. |
AnnaBridge | 171:3a7713b1edbc | 162 | This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ |
AnnaBridge | 171:3a7713b1edbc | 163 | |
AnnaBridge | 171:3a7713b1edbc | 164 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection. |
AnnaBridge | 171:3a7713b1edbc | 165 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 166 | |
AnnaBridge | 171:3a7713b1edbc | 167 | uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection. |
AnnaBridge | 171:3a7713b1edbc | 168 | This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 169 | |
AnnaBridge | 171:3a7713b1edbc | 170 | uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. |
AnnaBridge | 171:3a7713b1edbc | 171 | This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ |
AnnaBridge | 171:3a7713b1edbc | 172 | |
AnnaBridge | 171:3a7713b1edbc | 173 | uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection |
AnnaBridge | 171:3a7713b1edbc | 174 | This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 175 | |
AnnaBridge | 171:3a7713b1edbc | 176 | uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection |
AnnaBridge | 171:3a7713b1edbc | 177 | This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 178 | |
AnnaBridge | 171:3a7713b1edbc | 179 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
AnnaBridge | 171:3a7713b1edbc | 180 | This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 181 | |
AnnaBridge | 171:3a7713b1edbc | 182 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
AnnaBridge | 171:3a7713b1edbc | 183 | This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 184 | |
AnnaBridge | 171:3a7713b1edbc | 185 | uint32_t Usart3ClockSelection; /*!< USART3 clock source |
AnnaBridge | 171:3a7713b1edbc | 186 | This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 187 | |
AnnaBridge | 171:3a7713b1edbc | 188 | uint32_t Uart4ClockSelection; /*!< UART4 clock source |
AnnaBridge | 171:3a7713b1edbc | 189 | This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 190 | |
AnnaBridge | 171:3a7713b1edbc | 191 | uint32_t Uart5ClockSelection; /*!< UART5 clock source |
AnnaBridge | 171:3a7713b1edbc | 192 | This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 193 | |
AnnaBridge | 171:3a7713b1edbc | 194 | uint32_t Usart6ClockSelection; /*!< USART6 clock source |
AnnaBridge | 171:3a7713b1edbc | 195 | This parameter can be a value of @ref RCCEx_USART6_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 196 | |
AnnaBridge | 171:3a7713b1edbc | 197 | uint32_t Uart7ClockSelection; /*!< UART7 clock source |
AnnaBridge | 171:3a7713b1edbc | 198 | This parameter can be a value of @ref RCCEx_UART7_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 199 | |
AnnaBridge | 171:3a7713b1edbc | 200 | uint32_t Uart8ClockSelection; /*!< UART8 clock source |
AnnaBridge | 171:3a7713b1edbc | 201 | This parameter can be a value of @ref RCCEx_UART8_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 202 | |
AnnaBridge | 171:3a7713b1edbc | 203 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
AnnaBridge | 171:3a7713b1edbc | 204 | This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 205 | |
AnnaBridge | 171:3a7713b1edbc | 206 | uint32_t I2c2ClockSelection; /*!< I2C2 clock source |
AnnaBridge | 171:3a7713b1edbc | 207 | This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 208 | |
AnnaBridge | 171:3a7713b1edbc | 209 | uint32_t I2c3ClockSelection; /*!< I2C3 clock source |
AnnaBridge | 171:3a7713b1edbc | 210 | This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 211 | |
AnnaBridge | 171:3a7713b1edbc | 212 | uint32_t I2c4ClockSelection; /*!< I2C4 clock source |
AnnaBridge | 171:3a7713b1edbc | 213 | This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 214 | |
AnnaBridge | 171:3a7713b1edbc | 215 | uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source |
AnnaBridge | 171:3a7713b1edbc | 216 | This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 217 | |
AnnaBridge | 171:3a7713b1edbc | 218 | uint32_t CecClockSelection; /*!< CEC clock source |
AnnaBridge | 171:3a7713b1edbc | 219 | This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 220 | |
AnnaBridge | 171:3a7713b1edbc | 221 | uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC |
AnnaBridge | 171:3a7713b1edbc | 222 | This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 223 | |
AnnaBridge | 171:3a7713b1edbc | 224 | uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source |
AnnaBridge | 171:3a7713b1edbc | 225 | This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 226 | |
AnnaBridge | 171:3a7713b1edbc | 227 | #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 228 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 229 | uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source |
AnnaBridge | 171:3a7713b1edbc | 230 | This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 231 | #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 232 | |
AnnaBridge | 171:3a7713b1edbc | 233 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 234 | uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source |
AnnaBridge | 171:3a7713b1edbc | 235 | This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 236 | |
AnnaBridge | 171:3a7713b1edbc | 237 | uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source |
AnnaBridge | 171:3a7713b1edbc | 238 | This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 239 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 240 | }RCC_PeriphCLKInitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 241 | /** |
AnnaBridge | 171:3a7713b1edbc | 242 | * @} |
AnnaBridge | 171:3a7713b1edbc | 243 | */ |
AnnaBridge | 171:3a7713b1edbc | 244 | |
AnnaBridge | 171:3a7713b1edbc | 245 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 246 | /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants |
AnnaBridge | 171:3a7713b1edbc | 247 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 248 | */ |
AnnaBridge | 171:3a7713b1edbc | 249 | |
AnnaBridge | 171:3a7713b1edbc | 250 | /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection |
AnnaBridge | 171:3a7713b1edbc | 251 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 252 | */ |
AnnaBridge | 171:3a7713b1edbc | 253 | #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U) |
AnnaBridge | 171:3a7713b1edbc | 254 | #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 255 | #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U) |
AnnaBridge | 171:3a7713b1edbc | 256 | #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 257 | #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U) |
AnnaBridge | 171:3a7713b1edbc | 258 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U) |
AnnaBridge | 171:3a7713b1edbc | 259 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U) |
AnnaBridge | 171:3a7713b1edbc | 260 | #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080U) |
AnnaBridge | 171:3a7713b1edbc | 261 | #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100U) |
AnnaBridge | 171:3a7713b1edbc | 262 | #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200U) |
AnnaBridge | 171:3a7713b1edbc | 263 | #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400U) |
AnnaBridge | 171:3a7713b1edbc | 264 | #define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800U) |
AnnaBridge | 171:3a7713b1edbc | 265 | #define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000U) |
AnnaBridge | 171:3a7713b1edbc | 266 | #define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000U) |
AnnaBridge | 171:3a7713b1edbc | 267 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000U) |
AnnaBridge | 171:3a7713b1edbc | 268 | #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000U) |
AnnaBridge | 171:3a7713b1edbc | 269 | #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000U) |
AnnaBridge | 171:3a7713b1edbc | 270 | #define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000U) |
AnnaBridge | 171:3a7713b1edbc | 271 | #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000U) |
AnnaBridge | 171:3a7713b1edbc | 272 | #define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000U) |
AnnaBridge | 171:3a7713b1edbc | 273 | #define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000U) |
AnnaBridge | 171:3a7713b1edbc | 274 | #define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000U) |
AnnaBridge | 171:3a7713b1edbc | 275 | #define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000U) |
AnnaBridge | 171:3a7713b1edbc | 276 | #define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000U) |
AnnaBridge | 171:3a7713b1edbc | 277 | #define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U) |
AnnaBridge | 171:3a7713b1edbc | 278 | #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U) |
AnnaBridge | 171:3a7713b1edbc | 279 | #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 280 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 281 | #define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U) |
AnnaBridge | 171:3a7713b1edbc | 282 | #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 283 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 284 | #define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U) |
AnnaBridge | 171:3a7713b1edbc | 285 | #define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 286 | #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 287 | |
AnnaBridge | 171:3a7713b1edbc | 288 | /** |
AnnaBridge | 171:3a7713b1edbc | 289 | * @} |
AnnaBridge | 171:3a7713b1edbc | 290 | */ |
AnnaBridge | 171:3a7713b1edbc | 291 | |
AnnaBridge | 171:3a7713b1edbc | 292 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ |
AnnaBridge | 171:3a7713b1edbc | 293 | defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 294 | /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider |
AnnaBridge | 171:3a7713b1edbc | 295 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 296 | */ |
AnnaBridge | 171:3a7713b1edbc | 297 | #define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 298 | #define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001U) |
AnnaBridge | 171:3a7713b1edbc | 299 | #define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002U) |
AnnaBridge | 171:3a7713b1edbc | 300 | #define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003U) |
AnnaBridge | 171:3a7713b1edbc | 301 | /** |
AnnaBridge | 171:3a7713b1edbc | 302 | * @} |
AnnaBridge | 171:3a7713b1edbc | 303 | */ |
AnnaBridge | 171:3a7713b1edbc | 304 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 305 | |
AnnaBridge | 171:3a7713b1edbc | 306 | /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider |
AnnaBridge | 171:3a7713b1edbc | 307 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 308 | */ |
AnnaBridge | 171:3a7713b1edbc | 309 | #define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 310 | #define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001U) |
AnnaBridge | 171:3a7713b1edbc | 311 | #define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002U) |
AnnaBridge | 171:3a7713b1edbc | 312 | #define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003U) |
AnnaBridge | 171:3a7713b1edbc | 313 | /** |
AnnaBridge | 171:3a7713b1edbc | 314 | * @} |
AnnaBridge | 171:3a7713b1edbc | 315 | */ |
AnnaBridge | 171:3a7713b1edbc | 316 | |
AnnaBridge | 171:3a7713b1edbc | 317 | /** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR |
AnnaBridge | 171:3a7713b1edbc | 318 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 319 | */ |
AnnaBridge | 171:3a7713b1edbc | 320 | #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 321 | #define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0 |
AnnaBridge | 171:3a7713b1edbc | 322 | #define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1 |
AnnaBridge | 171:3a7713b1edbc | 323 | #define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR |
AnnaBridge | 171:3a7713b1edbc | 324 | /** |
AnnaBridge | 171:3a7713b1edbc | 325 | * @} |
AnnaBridge | 171:3a7713b1edbc | 326 | */ |
AnnaBridge | 171:3a7713b1edbc | 327 | |
AnnaBridge | 171:3a7713b1edbc | 328 | /** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source |
AnnaBridge | 171:3a7713b1edbc | 329 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 330 | */ |
AnnaBridge | 171:3a7713b1edbc | 331 | #define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 332 | #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC |
AnnaBridge | 171:3a7713b1edbc | 333 | |
AnnaBridge | 171:3a7713b1edbc | 334 | /** |
AnnaBridge | 171:3a7713b1edbc | 335 | * @} |
AnnaBridge | 171:3a7713b1edbc | 336 | */ |
AnnaBridge | 171:3a7713b1edbc | 337 | |
AnnaBridge | 171:3a7713b1edbc | 338 | |
AnnaBridge | 171:3a7713b1edbc | 339 | /** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source |
AnnaBridge | 171:3a7713b1edbc | 340 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 341 | */ |
AnnaBridge | 171:3a7713b1edbc | 342 | #define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 343 | #define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0 |
AnnaBridge | 171:3a7713b1edbc | 344 | #define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1 |
AnnaBridge | 171:3a7713b1edbc | 345 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 346 | #define RCC_SAI1CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI1SEL |
AnnaBridge | 171:3a7713b1edbc | 347 | #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 348 | /** |
AnnaBridge | 171:3a7713b1edbc | 349 | * @} |
AnnaBridge | 171:3a7713b1edbc | 350 | */ |
AnnaBridge | 171:3a7713b1edbc | 351 | |
AnnaBridge | 171:3a7713b1edbc | 352 | /** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source |
AnnaBridge | 171:3a7713b1edbc | 353 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 354 | */ |
AnnaBridge | 171:3a7713b1edbc | 355 | #define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 356 | #define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0 |
AnnaBridge | 171:3a7713b1edbc | 357 | #define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1 |
AnnaBridge | 171:3a7713b1edbc | 358 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 359 | #define RCC_SAI2CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI2SEL |
AnnaBridge | 171:3a7713b1edbc | 360 | #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 361 | /** |
AnnaBridge | 171:3a7713b1edbc | 362 | * @} |
AnnaBridge | 171:3a7713b1edbc | 363 | */ |
AnnaBridge | 171:3a7713b1edbc | 364 | |
AnnaBridge | 171:3a7713b1edbc | 365 | /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source |
AnnaBridge | 171:3a7713b1edbc | 366 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 367 | */ |
AnnaBridge | 171:3a7713b1edbc | 368 | #define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 369 | #define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/ |
AnnaBridge | 171:3a7713b1edbc | 370 | /** |
AnnaBridge | 171:3a7713b1edbc | 371 | * @} |
AnnaBridge | 171:3a7713b1edbc | 372 | */ |
AnnaBridge | 171:3a7713b1edbc | 373 | |
AnnaBridge | 171:3a7713b1edbc | 374 | /** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source |
AnnaBridge | 171:3a7713b1edbc | 375 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 376 | */ |
AnnaBridge | 171:3a7713b1edbc | 377 | #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 378 | #define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0 |
AnnaBridge | 171:3a7713b1edbc | 379 | #define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1 |
AnnaBridge | 171:3a7713b1edbc | 380 | #define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL |
AnnaBridge | 171:3a7713b1edbc | 381 | /** |
AnnaBridge | 171:3a7713b1edbc | 382 | * @} |
AnnaBridge | 171:3a7713b1edbc | 383 | */ |
AnnaBridge | 171:3a7713b1edbc | 384 | |
AnnaBridge | 171:3a7713b1edbc | 385 | /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source |
AnnaBridge | 171:3a7713b1edbc | 386 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 387 | */ |
AnnaBridge | 171:3a7713b1edbc | 388 | #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 389 | #define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0 |
AnnaBridge | 171:3a7713b1edbc | 390 | #define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1 |
AnnaBridge | 171:3a7713b1edbc | 391 | #define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL |
AnnaBridge | 171:3a7713b1edbc | 392 | /** |
AnnaBridge | 171:3a7713b1edbc | 393 | * @} |
AnnaBridge | 171:3a7713b1edbc | 394 | */ |
AnnaBridge | 171:3a7713b1edbc | 395 | |
AnnaBridge | 171:3a7713b1edbc | 396 | /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source |
AnnaBridge | 171:3a7713b1edbc | 397 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 398 | */ |
AnnaBridge | 171:3a7713b1edbc | 399 | #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 400 | #define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0 |
AnnaBridge | 171:3a7713b1edbc | 401 | #define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1 |
AnnaBridge | 171:3a7713b1edbc | 402 | #define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL |
AnnaBridge | 171:3a7713b1edbc | 403 | /** |
AnnaBridge | 171:3a7713b1edbc | 404 | * @} |
AnnaBridge | 171:3a7713b1edbc | 405 | */ |
AnnaBridge | 171:3a7713b1edbc | 406 | |
AnnaBridge | 171:3a7713b1edbc | 407 | /** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source |
AnnaBridge | 171:3a7713b1edbc | 408 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 409 | */ |
AnnaBridge | 171:3a7713b1edbc | 410 | #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 411 | #define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0 |
AnnaBridge | 171:3a7713b1edbc | 412 | #define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1 |
AnnaBridge | 171:3a7713b1edbc | 413 | #define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL |
AnnaBridge | 171:3a7713b1edbc | 414 | /** |
AnnaBridge | 171:3a7713b1edbc | 415 | * @} |
AnnaBridge | 171:3a7713b1edbc | 416 | */ |
AnnaBridge | 171:3a7713b1edbc | 417 | |
AnnaBridge | 171:3a7713b1edbc | 418 | /** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source |
AnnaBridge | 171:3a7713b1edbc | 419 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 420 | */ |
AnnaBridge | 171:3a7713b1edbc | 421 | #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 422 | #define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0 |
AnnaBridge | 171:3a7713b1edbc | 423 | #define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1 |
AnnaBridge | 171:3a7713b1edbc | 424 | #define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL |
AnnaBridge | 171:3a7713b1edbc | 425 | /** |
AnnaBridge | 171:3a7713b1edbc | 426 | * @} |
AnnaBridge | 171:3a7713b1edbc | 427 | */ |
AnnaBridge | 171:3a7713b1edbc | 428 | |
AnnaBridge | 171:3a7713b1edbc | 429 | /** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source |
AnnaBridge | 171:3a7713b1edbc | 430 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 431 | */ |
AnnaBridge | 171:3a7713b1edbc | 432 | #define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 433 | #define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0 |
AnnaBridge | 171:3a7713b1edbc | 434 | #define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1 |
AnnaBridge | 171:3a7713b1edbc | 435 | #define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL |
AnnaBridge | 171:3a7713b1edbc | 436 | /** |
AnnaBridge | 171:3a7713b1edbc | 437 | * @} |
AnnaBridge | 171:3a7713b1edbc | 438 | */ |
AnnaBridge | 171:3a7713b1edbc | 439 | |
AnnaBridge | 171:3a7713b1edbc | 440 | /** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source |
AnnaBridge | 171:3a7713b1edbc | 441 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 442 | */ |
AnnaBridge | 171:3a7713b1edbc | 443 | #define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 444 | #define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0 |
AnnaBridge | 171:3a7713b1edbc | 445 | #define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1 |
AnnaBridge | 171:3a7713b1edbc | 446 | #define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL |
AnnaBridge | 171:3a7713b1edbc | 447 | /** |
AnnaBridge | 171:3a7713b1edbc | 448 | * @} |
AnnaBridge | 171:3a7713b1edbc | 449 | */ |
AnnaBridge | 171:3a7713b1edbc | 450 | |
AnnaBridge | 171:3a7713b1edbc | 451 | /** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source |
AnnaBridge | 171:3a7713b1edbc | 452 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 453 | */ |
AnnaBridge | 171:3a7713b1edbc | 454 | #define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 455 | #define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0 |
AnnaBridge | 171:3a7713b1edbc | 456 | #define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1 |
AnnaBridge | 171:3a7713b1edbc | 457 | #define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL |
AnnaBridge | 171:3a7713b1edbc | 458 | /** |
AnnaBridge | 171:3a7713b1edbc | 459 | * @} |
AnnaBridge | 171:3a7713b1edbc | 460 | */ |
AnnaBridge | 171:3a7713b1edbc | 461 | |
AnnaBridge | 171:3a7713b1edbc | 462 | /** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source |
AnnaBridge | 171:3a7713b1edbc | 463 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 464 | */ |
AnnaBridge | 171:3a7713b1edbc | 465 | #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 466 | #define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0 |
AnnaBridge | 171:3a7713b1edbc | 467 | #define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1 |
AnnaBridge | 171:3a7713b1edbc | 468 | /** |
AnnaBridge | 171:3a7713b1edbc | 469 | * @} |
AnnaBridge | 171:3a7713b1edbc | 470 | */ |
AnnaBridge | 171:3a7713b1edbc | 471 | |
AnnaBridge | 171:3a7713b1edbc | 472 | /** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source |
AnnaBridge | 171:3a7713b1edbc | 473 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 474 | */ |
AnnaBridge | 171:3a7713b1edbc | 475 | #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 476 | #define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0 |
AnnaBridge | 171:3a7713b1edbc | 477 | #define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1 |
AnnaBridge | 171:3a7713b1edbc | 478 | |
AnnaBridge | 171:3a7713b1edbc | 479 | /** |
AnnaBridge | 171:3a7713b1edbc | 480 | * @} |
AnnaBridge | 171:3a7713b1edbc | 481 | */ |
AnnaBridge | 171:3a7713b1edbc | 482 | |
AnnaBridge | 171:3a7713b1edbc | 483 | /** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source |
AnnaBridge | 171:3a7713b1edbc | 484 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 485 | */ |
AnnaBridge | 171:3a7713b1edbc | 486 | #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 487 | #define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0 |
AnnaBridge | 171:3a7713b1edbc | 488 | #define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1 |
AnnaBridge | 171:3a7713b1edbc | 489 | /** |
AnnaBridge | 171:3a7713b1edbc | 490 | * @} |
AnnaBridge | 171:3a7713b1edbc | 491 | */ |
AnnaBridge | 171:3a7713b1edbc | 492 | |
AnnaBridge | 171:3a7713b1edbc | 493 | /** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source |
AnnaBridge | 171:3a7713b1edbc | 494 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 495 | */ |
AnnaBridge | 171:3a7713b1edbc | 496 | #define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 497 | #define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0 |
AnnaBridge | 171:3a7713b1edbc | 498 | #define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1 |
AnnaBridge | 171:3a7713b1edbc | 499 | /** |
AnnaBridge | 171:3a7713b1edbc | 500 | * @} |
AnnaBridge | 171:3a7713b1edbc | 501 | */ |
AnnaBridge | 171:3a7713b1edbc | 502 | |
AnnaBridge | 171:3a7713b1edbc | 503 | /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source |
AnnaBridge | 171:3a7713b1edbc | 504 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 505 | */ |
AnnaBridge | 171:3a7713b1edbc | 506 | #define RCC_LPTIM1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 507 | #define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 |
AnnaBridge | 171:3a7713b1edbc | 508 | #define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 |
AnnaBridge | 171:3a7713b1edbc | 509 | #define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL |
AnnaBridge | 171:3a7713b1edbc | 510 | |
AnnaBridge | 171:3a7713b1edbc | 511 | /** |
AnnaBridge | 171:3a7713b1edbc | 512 | * @} |
AnnaBridge | 171:3a7713b1edbc | 513 | */ |
AnnaBridge | 171:3a7713b1edbc | 514 | |
AnnaBridge | 171:3a7713b1edbc | 515 | /** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source |
AnnaBridge | 171:3a7713b1edbc | 516 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 517 | */ |
AnnaBridge | 171:3a7713b1edbc | 518 | #define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 519 | #define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL |
AnnaBridge | 171:3a7713b1edbc | 520 | /** |
AnnaBridge | 171:3a7713b1edbc | 521 | * @} |
AnnaBridge | 171:3a7713b1edbc | 522 | */ |
AnnaBridge | 171:3a7713b1edbc | 523 | |
AnnaBridge | 171:3a7713b1edbc | 524 | /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection |
AnnaBridge | 171:3a7713b1edbc | 525 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 526 | */ |
AnnaBridge | 171:3a7713b1edbc | 527 | #define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 528 | #define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE |
AnnaBridge | 171:3a7713b1edbc | 529 | /** |
AnnaBridge | 171:3a7713b1edbc | 530 | * @} |
AnnaBridge | 171:3a7713b1edbc | 531 | */ |
AnnaBridge | 171:3a7713b1edbc | 532 | |
AnnaBridge | 171:3a7713b1edbc | 533 | /** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source |
AnnaBridge | 171:3a7713b1edbc | 534 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 535 | */ |
AnnaBridge | 171:3a7713b1edbc | 536 | #define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 537 | #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL |
AnnaBridge | 171:3a7713b1edbc | 538 | /** |
AnnaBridge | 171:3a7713b1edbc | 539 | * @} |
AnnaBridge | 171:3a7713b1edbc | 540 | */ |
AnnaBridge | 171:3a7713b1edbc | 541 | |
AnnaBridge | 171:3a7713b1edbc | 542 | #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 543 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 544 | /** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source |
AnnaBridge | 171:3a7713b1edbc | 545 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 546 | */ |
AnnaBridge | 171:3a7713b1edbc | 547 | #define RCC_SDMMC2CLKSOURCE_CLK48 ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 548 | #define RCC_SDMMC2CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC2SEL |
AnnaBridge | 171:3a7713b1edbc | 549 | /** |
AnnaBridge | 171:3a7713b1edbc | 550 | * @} |
AnnaBridge | 171:3a7713b1edbc | 551 | */ |
AnnaBridge | 171:3a7713b1edbc | 552 | #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 553 | |
AnnaBridge | 171:3a7713b1edbc | 554 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 555 | /** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source |
AnnaBridge | 171:3a7713b1edbc | 556 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 557 | */ |
AnnaBridge | 171:3a7713b1edbc | 558 | #define RCC_DFSDM1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 559 | #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL |
AnnaBridge | 171:3a7713b1edbc | 560 | /** |
AnnaBridge | 171:3a7713b1edbc | 561 | * @} |
AnnaBridge | 171:3a7713b1edbc | 562 | */ |
AnnaBridge | 171:3a7713b1edbc | 563 | |
AnnaBridge | 171:3a7713b1edbc | 564 | /** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source |
AnnaBridge | 171:3a7713b1edbc | 565 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 566 | */ |
AnnaBridge | 171:3a7713b1edbc | 567 | #define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 568 | #define RCC_DFSDM1AUDIOCLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL |
AnnaBridge | 171:3a7713b1edbc | 569 | /** |
AnnaBridge | 171:3a7713b1edbc | 570 | * @} |
AnnaBridge | 171:3a7713b1edbc | 571 | */ |
AnnaBridge | 171:3a7713b1edbc | 572 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 573 | |
AnnaBridge | 171:3a7713b1edbc | 574 | #if defined (STM32F769xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 575 | /** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source |
AnnaBridge | 171:3a7713b1edbc | 576 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 577 | */ |
AnnaBridge | 171:3a7713b1edbc | 578 | #define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 579 | #define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL) |
AnnaBridge | 171:3a7713b1edbc | 580 | /** |
AnnaBridge | 171:3a7713b1edbc | 581 | * @} |
AnnaBridge | 171:3a7713b1edbc | 582 | */ |
AnnaBridge | 171:3a7713b1edbc | 583 | #endif /* STM32F769xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 584 | |
AnnaBridge | 171:3a7713b1edbc | 585 | /** |
AnnaBridge | 171:3a7713b1edbc | 586 | * @} |
AnnaBridge | 171:3a7713b1edbc | 587 | */ |
AnnaBridge | 171:3a7713b1edbc | 588 | |
AnnaBridge | 171:3a7713b1edbc | 589 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 590 | /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros |
AnnaBridge | 171:3a7713b1edbc | 591 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 592 | */ |
AnnaBridge | 171:3a7713b1edbc | 593 | /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable |
AnnaBridge | 171:3a7713b1edbc | 594 | * @brief Enables or disables the AHB/APB peripheral clock. |
AnnaBridge | 171:3a7713b1edbc | 595 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 171:3a7713b1edbc | 596 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 171:3a7713b1edbc | 597 | * using it. |
AnnaBridge | 171:3a7713b1edbc | 598 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 599 | */ |
AnnaBridge | 171:3a7713b1edbc | 600 | |
AnnaBridge | 171:3a7713b1edbc | 601 | /** @brief Enables or disables the AHB1 peripheral clock. |
AnnaBridge | 171:3a7713b1edbc | 602 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 171:3a7713b1edbc | 603 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 171:3a7713b1edbc | 604 | * using it. |
AnnaBridge | 171:3a7713b1edbc | 605 | */ |
AnnaBridge | 171:3a7713b1edbc | 606 | #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 607 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 608 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ |
AnnaBridge | 171:3a7713b1edbc | 609 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 610 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ |
AnnaBridge | 171:3a7713b1edbc | 611 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 612 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 613 | |
AnnaBridge | 171:3a7713b1edbc | 614 | #define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 615 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 616 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ |
AnnaBridge | 171:3a7713b1edbc | 617 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 618 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ |
AnnaBridge | 171:3a7713b1edbc | 619 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 620 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 621 | |
AnnaBridge | 171:3a7713b1edbc | 622 | #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 623 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 624 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 625 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 626 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 627 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 628 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 629 | |
AnnaBridge | 171:3a7713b1edbc | 630 | #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 631 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 632 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ |
AnnaBridge | 171:3a7713b1edbc | 633 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 634 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ |
AnnaBridge | 171:3a7713b1edbc | 635 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 636 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 637 | |
AnnaBridge | 171:3a7713b1edbc | 638 | #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 639 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 640 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ |
AnnaBridge | 171:3a7713b1edbc | 641 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 642 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ |
AnnaBridge | 171:3a7713b1edbc | 643 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 644 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 645 | |
AnnaBridge | 171:3a7713b1edbc | 646 | #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 647 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 648 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ |
AnnaBridge | 171:3a7713b1edbc | 649 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 650 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ |
AnnaBridge | 171:3a7713b1edbc | 651 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 652 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 653 | |
AnnaBridge | 171:3a7713b1edbc | 654 | #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 655 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 656 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ |
AnnaBridge | 171:3a7713b1edbc | 657 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 658 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ |
AnnaBridge | 171:3a7713b1edbc | 659 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 660 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 661 | |
AnnaBridge | 171:3a7713b1edbc | 662 | #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 663 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 664 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ |
AnnaBridge | 171:3a7713b1edbc | 665 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 666 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ |
AnnaBridge | 171:3a7713b1edbc | 667 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 668 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 669 | |
AnnaBridge | 171:3a7713b1edbc | 670 | #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 671 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 672 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ |
AnnaBridge | 171:3a7713b1edbc | 673 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 674 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ |
AnnaBridge | 171:3a7713b1edbc | 675 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 676 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 677 | |
AnnaBridge | 171:3a7713b1edbc | 678 | #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 679 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 680 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ |
AnnaBridge | 171:3a7713b1edbc | 681 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 682 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ |
AnnaBridge | 171:3a7713b1edbc | 683 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 684 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 685 | |
AnnaBridge | 171:3a7713b1edbc | 686 | #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 687 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 688 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ |
AnnaBridge | 171:3a7713b1edbc | 689 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 690 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ |
AnnaBridge | 171:3a7713b1edbc | 691 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 692 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 693 | |
AnnaBridge | 171:3a7713b1edbc | 694 | #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 695 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 696 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ |
AnnaBridge | 171:3a7713b1edbc | 697 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 698 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ |
AnnaBridge | 171:3a7713b1edbc | 699 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 700 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 701 | |
AnnaBridge | 171:3a7713b1edbc | 702 | #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 703 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 704 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ |
AnnaBridge | 171:3a7713b1edbc | 705 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 706 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ |
AnnaBridge | 171:3a7713b1edbc | 707 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 708 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 709 | |
AnnaBridge | 171:3a7713b1edbc | 710 | #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 711 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 712 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ |
AnnaBridge | 171:3a7713b1edbc | 713 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 714 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ |
AnnaBridge | 171:3a7713b1edbc | 715 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 716 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 717 | |
AnnaBridge | 171:3a7713b1edbc | 718 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 719 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 720 | #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 721 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 722 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ |
AnnaBridge | 171:3a7713b1edbc | 723 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 724 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ |
AnnaBridge | 171:3a7713b1edbc | 725 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 726 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 727 | |
AnnaBridge | 171:3a7713b1edbc | 728 | #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 729 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 730 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ |
AnnaBridge | 171:3a7713b1edbc | 731 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 732 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ |
AnnaBridge | 171:3a7713b1edbc | 733 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 734 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 735 | |
AnnaBridge | 171:3a7713b1edbc | 736 | #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 737 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 738 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ |
AnnaBridge | 171:3a7713b1edbc | 739 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 740 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ |
AnnaBridge | 171:3a7713b1edbc | 741 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 742 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 743 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 744 | |
AnnaBridge | 171:3a7713b1edbc | 745 | #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) |
AnnaBridge | 171:3a7713b1edbc | 746 | #define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN)) |
AnnaBridge | 171:3a7713b1edbc | 747 | #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN)) |
AnnaBridge | 171:3a7713b1edbc | 748 | #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) |
AnnaBridge | 171:3a7713b1edbc | 749 | #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) |
AnnaBridge | 171:3a7713b1edbc | 750 | #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN)) |
AnnaBridge | 171:3a7713b1edbc | 751 | #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN)) |
AnnaBridge | 171:3a7713b1edbc | 752 | #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN)) |
AnnaBridge | 171:3a7713b1edbc | 753 | #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) |
AnnaBridge | 171:3a7713b1edbc | 754 | #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) |
AnnaBridge | 171:3a7713b1edbc | 755 | #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) |
AnnaBridge | 171:3a7713b1edbc | 756 | #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) |
AnnaBridge | 171:3a7713b1edbc | 757 | #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) |
AnnaBridge | 171:3a7713b1edbc | 758 | #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) |
AnnaBridge | 171:3a7713b1edbc | 759 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 760 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 761 | #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) |
AnnaBridge | 171:3a7713b1edbc | 762 | #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) |
AnnaBridge | 171:3a7713b1edbc | 763 | #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) |
AnnaBridge | 171:3a7713b1edbc | 764 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 765 | |
AnnaBridge | 171:3a7713b1edbc | 766 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 767 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 768 | /** |
AnnaBridge | 171:3a7713b1edbc | 769 | * @brief Enable ETHERNET clock. |
AnnaBridge | 171:3a7713b1edbc | 770 | */ |
AnnaBridge | 171:3a7713b1edbc | 771 | #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 772 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 773 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ |
AnnaBridge | 171:3a7713b1edbc | 774 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 775 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ |
AnnaBridge | 171:3a7713b1edbc | 776 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 777 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 778 | |
AnnaBridge | 171:3a7713b1edbc | 779 | #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 780 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 781 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ |
AnnaBridge | 171:3a7713b1edbc | 782 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 783 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ |
AnnaBridge | 171:3a7713b1edbc | 784 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 785 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 786 | |
AnnaBridge | 171:3a7713b1edbc | 787 | #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 788 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 789 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ |
AnnaBridge | 171:3a7713b1edbc | 790 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 791 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ |
AnnaBridge | 171:3a7713b1edbc | 792 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 793 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 794 | |
AnnaBridge | 171:3a7713b1edbc | 795 | #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 796 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 797 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ |
AnnaBridge | 171:3a7713b1edbc | 798 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 799 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ |
AnnaBridge | 171:3a7713b1edbc | 800 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 801 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 802 | |
AnnaBridge | 171:3a7713b1edbc | 803 | #define __HAL_RCC_ETH_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 804 | __HAL_RCC_ETHMAC_CLK_ENABLE(); \ |
AnnaBridge | 171:3a7713b1edbc | 805 | __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ |
AnnaBridge | 171:3a7713b1edbc | 806 | __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ |
AnnaBridge | 171:3a7713b1edbc | 807 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 808 | /** |
AnnaBridge | 171:3a7713b1edbc | 809 | * @brief Disable ETHERNET clock. |
AnnaBridge | 171:3a7713b1edbc | 810 | */ |
AnnaBridge | 171:3a7713b1edbc | 811 | #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) |
AnnaBridge | 171:3a7713b1edbc | 812 | #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) |
AnnaBridge | 171:3a7713b1edbc | 813 | #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) |
AnnaBridge | 171:3a7713b1edbc | 814 | #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) |
AnnaBridge | 171:3a7713b1edbc | 815 | #define __HAL_RCC_ETH_CLK_DISABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 816 | __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ |
AnnaBridge | 171:3a7713b1edbc | 817 | __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ |
AnnaBridge | 171:3a7713b1edbc | 818 | __HAL_RCC_ETHMAC_CLK_DISABLE(); \ |
AnnaBridge | 171:3a7713b1edbc | 819 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 820 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 821 | |
AnnaBridge | 171:3a7713b1edbc | 822 | /** @brief Enable or disable the AHB2 peripheral clock. |
AnnaBridge | 171:3a7713b1edbc | 823 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 171:3a7713b1edbc | 824 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 171:3a7713b1edbc | 825 | * using it. |
AnnaBridge | 171:3a7713b1edbc | 826 | */ |
AnnaBridge | 171:3a7713b1edbc | 827 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 828 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 829 | #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 830 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 831 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ |
AnnaBridge | 171:3a7713b1edbc | 832 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 833 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ |
AnnaBridge | 171:3a7713b1edbc | 834 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 835 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 836 | #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) |
AnnaBridge | 171:3a7713b1edbc | 837 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 838 | |
AnnaBridge | 171:3a7713b1edbc | 839 | #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 840 | #define __HAL_RCC_JPEG_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 841 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 842 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ |
AnnaBridge | 171:3a7713b1edbc | 843 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 844 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ |
AnnaBridge | 171:3a7713b1edbc | 845 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 846 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 847 | #define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN)) |
AnnaBridge | 171:3a7713b1edbc | 848 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 849 | |
AnnaBridge | 171:3a7713b1edbc | 850 | #define __HAL_RCC_RNG_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 851 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 852 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ |
AnnaBridge | 171:3a7713b1edbc | 853 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 854 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ |
AnnaBridge | 171:3a7713b1edbc | 855 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 856 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 857 | |
AnnaBridge | 171:3a7713b1edbc | 858 | #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 859 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 860 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ |
AnnaBridge | 171:3a7713b1edbc | 861 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 862 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ |
AnnaBridge | 171:3a7713b1edbc | 863 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 864 | __HAL_RCC_SYSCFG_CLK_ENABLE();\ |
AnnaBridge | 171:3a7713b1edbc | 865 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 866 | |
AnnaBridge | 171:3a7713b1edbc | 867 | #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) |
AnnaBridge | 171:3a7713b1edbc | 868 | |
AnnaBridge | 171:3a7713b1edbc | 869 | #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) |
AnnaBridge | 171:3a7713b1edbc | 870 | #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 871 | #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 872 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 873 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ |
AnnaBridge | 171:3a7713b1edbc | 874 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 875 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ |
AnnaBridge | 171:3a7713b1edbc | 876 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 877 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 878 | |
AnnaBridge | 171:3a7713b1edbc | 879 | #define __HAL_RCC_HASH_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 880 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 881 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ |
AnnaBridge | 171:3a7713b1edbc | 882 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 883 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ |
AnnaBridge | 171:3a7713b1edbc | 884 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 885 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 886 | |
AnnaBridge | 171:3a7713b1edbc | 887 | #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) |
AnnaBridge | 171:3a7713b1edbc | 888 | #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) |
AnnaBridge | 171:3a7713b1edbc | 889 | #endif /* STM32F756x || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 890 | |
AnnaBridge | 171:3a7713b1edbc | 891 | #if defined(STM32F732xx) || defined (STM32F733xx) |
AnnaBridge | 171:3a7713b1edbc | 892 | #define __HAL_RCC_AES_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 893 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 894 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ |
AnnaBridge | 171:3a7713b1edbc | 895 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 896 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ |
AnnaBridge | 171:3a7713b1edbc | 897 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 898 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 899 | |
AnnaBridge | 171:3a7713b1edbc | 900 | #define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN)) |
AnnaBridge | 171:3a7713b1edbc | 901 | #endif /* STM32F732xx || STM32F733xx */ |
AnnaBridge | 171:3a7713b1edbc | 902 | |
AnnaBridge | 171:3a7713b1edbc | 903 | /** @brief Enables or disables the AHB3 peripheral clock. |
AnnaBridge | 171:3a7713b1edbc | 904 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 171:3a7713b1edbc | 905 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 171:3a7713b1edbc | 906 | * using it. |
AnnaBridge | 171:3a7713b1edbc | 907 | */ |
AnnaBridge | 171:3a7713b1edbc | 908 | #define __HAL_RCC_FMC_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 909 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 910 | SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ |
AnnaBridge | 171:3a7713b1edbc | 911 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 912 | tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ |
AnnaBridge | 171:3a7713b1edbc | 913 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 914 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 915 | |
AnnaBridge | 171:3a7713b1edbc | 916 | #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 917 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 918 | SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ |
AnnaBridge | 171:3a7713b1edbc | 919 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 920 | tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ |
AnnaBridge | 171:3a7713b1edbc | 921 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 922 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 923 | |
AnnaBridge | 171:3a7713b1edbc | 924 | #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) |
AnnaBridge | 171:3a7713b1edbc | 925 | #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) |
AnnaBridge | 171:3a7713b1edbc | 926 | |
AnnaBridge | 171:3a7713b1edbc | 927 | /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
AnnaBridge | 171:3a7713b1edbc | 928 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 171:3a7713b1edbc | 929 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 171:3a7713b1edbc | 930 | * using it. |
AnnaBridge | 171:3a7713b1edbc | 931 | */ |
AnnaBridge | 171:3a7713b1edbc | 932 | #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 933 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 934 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 935 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 936 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 937 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 938 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 939 | |
AnnaBridge | 171:3a7713b1edbc | 940 | #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 941 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 942 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ |
AnnaBridge | 171:3a7713b1edbc | 943 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 944 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ |
AnnaBridge | 171:3a7713b1edbc | 945 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 946 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 947 | |
AnnaBridge | 171:3a7713b1edbc | 948 | #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 949 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 950 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ |
AnnaBridge | 171:3a7713b1edbc | 951 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 952 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ |
AnnaBridge | 171:3a7713b1edbc | 953 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 954 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 955 | |
AnnaBridge | 171:3a7713b1edbc | 956 | #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 957 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 958 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ |
AnnaBridge | 171:3a7713b1edbc | 959 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 960 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ |
AnnaBridge | 171:3a7713b1edbc | 961 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 962 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 963 | |
AnnaBridge | 171:3a7713b1edbc | 964 | #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 965 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 966 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ |
AnnaBridge | 171:3a7713b1edbc | 967 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 968 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ |
AnnaBridge | 171:3a7713b1edbc | 969 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 970 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 971 | |
AnnaBridge | 171:3a7713b1edbc | 972 | #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 973 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 974 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ |
AnnaBridge | 171:3a7713b1edbc | 975 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 976 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ |
AnnaBridge | 171:3a7713b1edbc | 977 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 978 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 979 | |
AnnaBridge | 171:3a7713b1edbc | 980 | #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 981 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 982 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ |
AnnaBridge | 171:3a7713b1edbc | 983 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 984 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ |
AnnaBridge | 171:3a7713b1edbc | 985 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 986 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 987 | |
AnnaBridge | 171:3a7713b1edbc | 988 | #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 989 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 990 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ |
AnnaBridge | 171:3a7713b1edbc | 991 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 992 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ |
AnnaBridge | 171:3a7713b1edbc | 993 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 994 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 995 | |
AnnaBridge | 171:3a7713b1edbc | 996 | #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 997 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 998 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ |
AnnaBridge | 171:3a7713b1edbc | 999 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1000 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1001 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1002 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1003 | |
AnnaBridge | 171:3a7713b1edbc | 1004 | #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1005 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1006 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1007 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1008 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1009 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1010 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1011 | |
AnnaBridge | 171:3a7713b1edbc | 1012 | #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 1013 | defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 1014 | defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1015 | #define __HAL_RCC_RTC_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1016 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1017 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1018 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1019 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1020 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1021 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1022 | #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || |
AnnaBridge | 171:3a7713b1edbc | 1023 | STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1024 | |
AnnaBridge | 171:3a7713b1edbc | 1025 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1026 | #define __HAL_RCC_CAN3_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1027 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1028 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1029 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1030 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1031 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1032 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1033 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1034 | |
AnnaBridge | 171:3a7713b1edbc | 1035 | #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1036 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1037 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1038 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1039 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1040 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1041 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1042 | |
AnnaBridge | 171:3a7713b1edbc | 1043 | #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1044 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1045 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1046 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1047 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1048 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1049 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1050 | |
AnnaBridge | 171:3a7713b1edbc | 1051 | #define __HAL_RCC_USART2_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1052 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1053 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1054 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1055 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1056 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1057 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1058 | |
AnnaBridge | 171:3a7713b1edbc | 1059 | #define __HAL_RCC_USART3_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1060 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1061 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1062 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1063 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1064 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1065 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1066 | |
AnnaBridge | 171:3a7713b1edbc | 1067 | #define __HAL_RCC_UART4_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1068 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1069 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1070 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1071 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1072 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1073 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1074 | |
AnnaBridge | 171:3a7713b1edbc | 1075 | #define __HAL_RCC_UART5_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1076 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1077 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1078 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1079 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1080 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1081 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1082 | |
AnnaBridge | 171:3a7713b1edbc | 1083 | #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1084 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1085 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1086 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1087 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1088 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1089 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1090 | |
AnnaBridge | 171:3a7713b1edbc | 1091 | #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1092 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1093 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1094 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1095 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1096 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1097 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1098 | |
AnnaBridge | 171:3a7713b1edbc | 1099 | #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1100 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1101 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1102 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1103 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1104 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1105 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1106 | |
AnnaBridge | 171:3a7713b1edbc | 1107 | #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1108 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1109 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1110 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1111 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1112 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1113 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1114 | |
AnnaBridge | 171:3a7713b1edbc | 1115 | #define __HAL_RCC_DAC_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1116 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1117 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1118 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1119 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1120 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1121 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1122 | |
AnnaBridge | 171:3a7713b1edbc | 1123 | #define __HAL_RCC_UART7_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1124 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1125 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1126 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1127 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1128 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1129 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1130 | |
AnnaBridge | 171:3a7713b1edbc | 1131 | #define __HAL_RCC_UART8_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1132 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1133 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1134 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1135 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1136 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1137 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1138 | |
AnnaBridge | 171:3a7713b1edbc | 1139 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 1140 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1141 | #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1142 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1143 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1144 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1145 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1146 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1147 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1148 | |
AnnaBridge | 171:3a7713b1edbc | 1149 | #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1150 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1151 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1152 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1153 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1154 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1155 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1156 | |
AnnaBridge | 171:3a7713b1edbc | 1157 | #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1158 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1159 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1160 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1161 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1162 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1163 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1164 | |
AnnaBridge | 171:3a7713b1edbc | 1165 | #define __HAL_RCC_CEC_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1166 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1167 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1168 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1169 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1170 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1171 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1172 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1173 | |
AnnaBridge | 171:3a7713b1edbc | 1174 | #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) |
AnnaBridge | 171:3a7713b1edbc | 1175 | #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) |
AnnaBridge | 171:3a7713b1edbc | 1176 | #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) |
AnnaBridge | 171:3a7713b1edbc | 1177 | #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) |
AnnaBridge | 171:3a7713b1edbc | 1178 | #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) |
AnnaBridge | 171:3a7713b1edbc | 1179 | #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) |
AnnaBridge | 171:3a7713b1edbc | 1180 | #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) |
AnnaBridge | 171:3a7713b1edbc | 1181 | #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) |
AnnaBridge | 171:3a7713b1edbc | 1182 | #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) |
AnnaBridge | 171:3a7713b1edbc | 1183 | #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) |
AnnaBridge | 171:3a7713b1edbc | 1184 | #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 1185 | defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 1186 | defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1187 | #define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN)) |
AnnaBridge | 171:3a7713b1edbc | 1188 | #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || |
AnnaBridge | 171:3a7713b1edbc | 1189 | STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1190 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1191 | #define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) |
AnnaBridge | 171:3a7713b1edbc | 1192 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1193 | #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) |
AnnaBridge | 171:3a7713b1edbc | 1194 | #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) |
AnnaBridge | 171:3a7713b1edbc | 1195 | #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) |
AnnaBridge | 171:3a7713b1edbc | 1196 | #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) |
AnnaBridge | 171:3a7713b1edbc | 1197 | #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) |
AnnaBridge | 171:3a7713b1edbc | 1198 | #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) |
AnnaBridge | 171:3a7713b1edbc | 1199 | #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) |
AnnaBridge | 171:3a7713b1edbc | 1200 | #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) |
AnnaBridge | 171:3a7713b1edbc | 1201 | #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) |
AnnaBridge | 171:3a7713b1edbc | 1202 | #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) |
AnnaBridge | 171:3a7713b1edbc | 1203 | #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) |
AnnaBridge | 171:3a7713b1edbc | 1204 | #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) |
AnnaBridge | 171:3a7713b1edbc | 1205 | #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) |
AnnaBridge | 171:3a7713b1edbc | 1206 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 1207 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1208 | #define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) |
AnnaBridge | 171:3a7713b1edbc | 1209 | #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN)) |
AnnaBridge | 171:3a7713b1edbc | 1210 | #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) |
AnnaBridge | 171:3a7713b1edbc | 1211 | #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) |
AnnaBridge | 171:3a7713b1edbc | 1212 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1213 | |
AnnaBridge | 171:3a7713b1edbc | 1214 | /** @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
AnnaBridge | 171:3a7713b1edbc | 1215 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 171:3a7713b1edbc | 1216 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 171:3a7713b1edbc | 1217 | * using it. |
AnnaBridge | 171:3a7713b1edbc | 1218 | */ |
AnnaBridge | 171:3a7713b1edbc | 1219 | #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1220 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1221 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1222 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1223 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1224 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1225 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1226 | |
AnnaBridge | 171:3a7713b1edbc | 1227 | #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1228 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1229 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1230 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1231 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1232 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1233 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1234 | |
AnnaBridge | 171:3a7713b1edbc | 1235 | #define __HAL_RCC_USART1_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1236 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1237 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1238 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1239 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1240 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1241 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1242 | |
AnnaBridge | 171:3a7713b1edbc | 1243 | #define __HAL_RCC_USART6_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1244 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1245 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1246 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1247 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1248 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1249 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1250 | |
AnnaBridge | 171:3a7713b1edbc | 1251 | #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 1252 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1253 | #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1254 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1255 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1256 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1257 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1258 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1259 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1260 | #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1261 | |
AnnaBridge | 171:3a7713b1edbc | 1262 | #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1263 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1264 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1265 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1266 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1267 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1268 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1269 | |
AnnaBridge | 171:3a7713b1edbc | 1270 | #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1271 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1272 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1273 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1274 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1275 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1276 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1277 | |
AnnaBridge | 171:3a7713b1edbc | 1278 | #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1279 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1280 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1281 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1282 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1283 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1284 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1285 | |
AnnaBridge | 171:3a7713b1edbc | 1286 | #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1287 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1288 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1289 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1290 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1291 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1292 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1293 | |
AnnaBridge | 171:3a7713b1edbc | 1294 | #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1295 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1296 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1297 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1298 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1299 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1300 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1301 | |
AnnaBridge | 171:3a7713b1edbc | 1302 | #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1303 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1304 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1305 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1306 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1307 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1308 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1309 | |
AnnaBridge | 171:3a7713b1edbc | 1310 | #define __HAL_RCC_TIM9_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1311 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1312 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1313 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1314 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1315 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1316 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1317 | |
AnnaBridge | 171:3a7713b1edbc | 1318 | #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1319 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1320 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1321 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1322 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1323 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1324 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1325 | |
AnnaBridge | 171:3a7713b1edbc | 1326 | #define __HAL_RCC_TIM11_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1327 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1328 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1329 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1330 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1331 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1332 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1333 | |
AnnaBridge | 171:3a7713b1edbc | 1334 | #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1335 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1336 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1337 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1338 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1339 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1340 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1341 | |
AnnaBridge | 171:3a7713b1edbc | 1342 | #define __HAL_RCC_SPI6_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1343 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1344 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1345 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1346 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1347 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1348 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1349 | |
AnnaBridge | 171:3a7713b1edbc | 1350 | #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1351 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1352 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1353 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1354 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1355 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1356 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1357 | |
AnnaBridge | 171:3a7713b1edbc | 1358 | #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1359 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1360 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1361 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1362 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1363 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1364 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1365 | |
AnnaBridge | 171:3a7713b1edbc | 1366 | #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1367 | #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1368 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1369 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1370 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1371 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1372 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1373 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1374 | #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1375 | |
AnnaBridge | 171:3a7713b1edbc | 1376 | #if defined (STM32F769xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1377 | #define __HAL_RCC_DSI_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1378 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1379 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1380 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1381 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1382 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1383 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1384 | #endif /* STM32F769xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1385 | |
AnnaBridge | 171:3a7713b1edbc | 1386 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1387 | #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1388 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1389 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1390 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1391 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1392 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1393 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1394 | |
AnnaBridge | 171:3a7713b1edbc | 1395 | #define __HAL_RCC_MDIO_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1396 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1397 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1398 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1399 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1400 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1401 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1402 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1403 | #if defined (STM32F723xx) || defined (STM32F733xx) |
AnnaBridge | 171:3a7713b1edbc | 1404 | #define __HAL_RCC_OTGPHYC_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1405 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1406 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1407 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1408 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1409 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1410 | } while(0) |
AnnaBridge | 171:3a7713b1edbc | 1411 | #endif /* STM32F723xx || STM32F733xx */ |
AnnaBridge | 171:3a7713b1edbc | 1412 | |
AnnaBridge | 171:3a7713b1edbc | 1413 | #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) |
AnnaBridge | 171:3a7713b1edbc | 1414 | #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) |
AnnaBridge | 171:3a7713b1edbc | 1415 | #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) |
AnnaBridge | 171:3a7713b1edbc | 1416 | #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) |
AnnaBridge | 171:3a7713b1edbc | 1417 | #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 1418 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1419 | #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN)) |
AnnaBridge | 171:3a7713b1edbc | 1420 | #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1421 | #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) |
AnnaBridge | 171:3a7713b1edbc | 1422 | #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) |
AnnaBridge | 171:3a7713b1edbc | 1423 | #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) |
AnnaBridge | 171:3a7713b1edbc | 1424 | #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN)) |
AnnaBridge | 171:3a7713b1edbc | 1425 | #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) |
AnnaBridge | 171:3a7713b1edbc | 1426 | #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) |
AnnaBridge | 171:3a7713b1edbc | 1427 | #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) |
AnnaBridge | 171:3a7713b1edbc | 1428 | #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) |
AnnaBridge | 171:3a7713b1edbc | 1429 | #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) |
AnnaBridge | 171:3a7713b1edbc | 1430 | #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) |
AnnaBridge | 171:3a7713b1edbc | 1431 | #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) |
AnnaBridge | 171:3a7713b1edbc | 1432 | #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) |
AnnaBridge | 171:3a7713b1edbc | 1433 | #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) |
AnnaBridge | 171:3a7713b1edbc | 1434 | #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1435 | #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) |
AnnaBridge | 171:3a7713b1edbc | 1436 | #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1437 | #if defined (STM32F769xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1438 | #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) |
AnnaBridge | 171:3a7713b1edbc | 1439 | #endif /* STM32F769xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1440 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1441 | #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) |
AnnaBridge | 171:3a7713b1edbc | 1442 | #define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN)) |
AnnaBridge | 171:3a7713b1edbc | 1443 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1444 | #if defined (STM32F723xx) || defined (STM32F733xx) |
AnnaBridge | 171:3a7713b1edbc | 1445 | #define __HAL_RCC_OTGPHYC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_OTGPHYCEN)) |
AnnaBridge | 171:3a7713b1edbc | 1446 | #endif /* STM32F723xx || STM32F733xx */ |
AnnaBridge | 171:3a7713b1edbc | 1447 | |
AnnaBridge | 171:3a7713b1edbc | 1448 | /** |
AnnaBridge | 171:3a7713b1edbc | 1449 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1450 | */ |
AnnaBridge | 171:3a7713b1edbc | 1451 | |
AnnaBridge | 171:3a7713b1edbc | 1452 | |
AnnaBridge | 171:3a7713b1edbc | 1453 | /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status |
AnnaBridge | 171:3a7713b1edbc | 1454 | * @brief Get the enable or disable status of the AHB/APB peripheral clock. |
AnnaBridge | 171:3a7713b1edbc | 1455 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 171:3a7713b1edbc | 1456 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 171:3a7713b1edbc | 1457 | * using it. |
AnnaBridge | 171:3a7713b1edbc | 1458 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1459 | */ |
AnnaBridge | 171:3a7713b1edbc | 1460 | |
AnnaBridge | 171:3a7713b1edbc | 1461 | /** @brief Get the enable or disable status of the AHB1 peripheral clock. |
AnnaBridge | 171:3a7713b1edbc | 1462 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 171:3a7713b1edbc | 1463 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 171:3a7713b1edbc | 1464 | * using it. |
AnnaBridge | 171:3a7713b1edbc | 1465 | */ |
AnnaBridge | 171:3a7713b1edbc | 1466 | #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1467 | #define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1468 | #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1469 | #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1470 | #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1471 | #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1472 | #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1473 | #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1474 | #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1475 | #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1476 | #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1477 | #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1478 | #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1479 | #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1480 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 1481 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1482 | #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1483 | #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1484 | #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1485 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1486 | |
AnnaBridge | 171:3a7713b1edbc | 1487 | #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1488 | #define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1489 | #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1490 | #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1491 | #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1492 | #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1493 | #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1494 | #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1495 | #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1496 | #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1497 | #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1498 | #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1499 | #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1500 | #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1501 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 1502 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1503 | #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1504 | #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1505 | #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1506 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1507 | |
AnnaBridge | 171:3a7713b1edbc | 1508 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 1509 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1510 | /** |
AnnaBridge | 171:3a7713b1edbc | 1511 | * @brief Enable ETHERNET clock. |
AnnaBridge | 171:3a7713b1edbc | 1512 | */ |
AnnaBridge | 171:3a7713b1edbc | 1513 | #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1514 | #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1515 | #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1516 | #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1517 | #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ |
AnnaBridge | 171:3a7713b1edbc | 1518 | __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ |
AnnaBridge | 171:3a7713b1edbc | 1519 | __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) |
AnnaBridge | 171:3a7713b1edbc | 1520 | |
AnnaBridge | 171:3a7713b1edbc | 1521 | /** |
AnnaBridge | 171:3a7713b1edbc | 1522 | * @brief Disable ETHERNET clock. |
AnnaBridge | 171:3a7713b1edbc | 1523 | */ |
AnnaBridge | 171:3a7713b1edbc | 1524 | #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1525 | #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1526 | #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1527 | #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1528 | #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ |
AnnaBridge | 171:3a7713b1edbc | 1529 | __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ |
AnnaBridge | 171:3a7713b1edbc | 1530 | __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) |
AnnaBridge | 171:3a7713b1edbc | 1531 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1532 | |
AnnaBridge | 171:3a7713b1edbc | 1533 | /** @brief Get the enable or disable status of the AHB2 peripheral clock. |
AnnaBridge | 171:3a7713b1edbc | 1534 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 171:3a7713b1edbc | 1535 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 171:3a7713b1edbc | 1536 | * using it. |
AnnaBridge | 171:3a7713b1edbc | 1537 | */ |
AnnaBridge | 171:3a7713b1edbc | 1538 | #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1539 | #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1540 | |
AnnaBridge | 171:3a7713b1edbc | 1541 | #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1542 | #define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1543 | |
AnnaBridge | 171:3a7713b1edbc | 1544 | #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1545 | #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1546 | #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1547 | #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1548 | #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1549 | #endif /* STM32F756xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1550 | |
AnnaBridge | 171:3a7713b1edbc | 1551 | #if defined(STM32F732xx) || defined (STM32F733xx) |
AnnaBridge | 171:3a7713b1edbc | 1552 | #define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1553 | #define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1554 | #endif /* STM32F732xx || STM32F733xx */ |
AnnaBridge | 171:3a7713b1edbc | 1555 | |
AnnaBridge | 171:3a7713b1edbc | 1556 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 1557 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1558 | #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1559 | #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1560 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1561 | |
AnnaBridge | 171:3a7713b1edbc | 1562 | #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1563 | #define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1564 | #define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1565 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1566 | |
AnnaBridge | 171:3a7713b1edbc | 1567 | /** @brief Get the enable or disable status of the AHB3 peripheral clock. |
AnnaBridge | 171:3a7713b1edbc | 1568 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 171:3a7713b1edbc | 1569 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 171:3a7713b1edbc | 1570 | * using it. |
AnnaBridge | 171:3a7713b1edbc | 1571 | */ |
AnnaBridge | 171:3a7713b1edbc | 1572 | #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1573 | #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1574 | |
AnnaBridge | 171:3a7713b1edbc | 1575 | #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1576 | #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1577 | |
AnnaBridge | 171:3a7713b1edbc | 1578 | /** @brief Get the enable or disable status of the APB1 peripheral clock. |
AnnaBridge | 171:3a7713b1edbc | 1579 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 171:3a7713b1edbc | 1580 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 171:3a7713b1edbc | 1581 | * using it. |
AnnaBridge | 171:3a7713b1edbc | 1582 | */ |
AnnaBridge | 171:3a7713b1edbc | 1583 | #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1584 | #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1585 | #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1586 | #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1587 | #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1588 | #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1589 | #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1590 | #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1591 | #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1592 | #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1593 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1594 | #define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1595 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1596 | #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1597 | #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1598 | #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1599 | #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1600 | #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1601 | #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1602 | #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1603 | #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1604 | #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1605 | #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1606 | #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1607 | #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1608 | #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1609 | |
AnnaBridge | 171:3a7713b1edbc | 1610 | #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1611 | #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1612 | #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1613 | #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1614 | #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1615 | #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1616 | #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1617 | #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1618 | #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1619 | #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1620 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1621 | #define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1622 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1623 | #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1624 | #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1625 | #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1626 | #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1627 | #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1628 | #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1629 | #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1630 | #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1631 | #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1632 | #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1633 | #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1634 | #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1635 | #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1636 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 1637 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1638 | #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1639 | #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1640 | #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1641 | #define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1642 | |
AnnaBridge | 171:3a7713b1edbc | 1643 | #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1644 | #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1645 | #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1646 | #define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1647 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1648 | |
AnnaBridge | 171:3a7713b1edbc | 1649 | #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 1650 | defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 1651 | defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1652 | #define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1653 | #define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1654 | #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || |
AnnaBridge | 171:3a7713b1edbc | 1655 | STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1656 | |
AnnaBridge | 171:3a7713b1edbc | 1657 | /** @brief Get the enable or disable status of the APB2 peripheral clock. |
AnnaBridge | 171:3a7713b1edbc | 1658 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 171:3a7713b1edbc | 1659 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 171:3a7713b1edbc | 1660 | * using it. |
AnnaBridge | 171:3a7713b1edbc | 1661 | */ |
AnnaBridge | 171:3a7713b1edbc | 1662 | #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1663 | #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1664 | #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1665 | #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1666 | #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1667 | #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1668 | #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1669 | #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1670 | #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1671 | #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1672 | #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1673 | #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1674 | #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1675 | #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1676 | #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1677 | #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1678 | #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1679 | #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1680 | #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1681 | #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1682 | #if defined (STM32F769xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1683 | #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1684 | #endif /* STM32F769xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1685 | #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 1686 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1687 | #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1688 | #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1689 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1690 | #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1691 | #define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1692 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1693 | #if defined (STM32F723xx) || defined (STM32F733xx) |
AnnaBridge | 171:3a7713b1edbc | 1694 | #define __HAL_RCC_OTGPHYC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1695 | #endif /* STM32F723xx || STM32F733xx */ |
AnnaBridge | 171:3a7713b1edbc | 1696 | |
AnnaBridge | 171:3a7713b1edbc | 1697 | #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1698 | #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1699 | #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1700 | #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1701 | #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1702 | #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1703 | #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1704 | #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1705 | #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1706 | #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1707 | #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1708 | #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1709 | #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1710 | #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1711 | #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1712 | #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1713 | #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1714 | #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1715 | #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1716 | #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1717 | #if defined (STM32F769xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1718 | #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1719 | #endif /* STM32F769xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1720 | #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 1721 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1722 | #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1723 | #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1724 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1725 | #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1726 | #define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1727 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1728 | #if defined (STM32F723xx) || defined (STM32F733xx) |
AnnaBridge | 171:3a7713b1edbc | 1729 | #define __HAL_RCC_OTGPHYC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1730 | #endif /* STM32F723xx || STM32F733xx */ |
AnnaBridge | 171:3a7713b1edbc | 1731 | |
AnnaBridge | 171:3a7713b1edbc | 1732 | /** |
AnnaBridge | 171:3a7713b1edbc | 1733 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1734 | */ |
AnnaBridge | 171:3a7713b1edbc | 1735 | |
AnnaBridge | 171:3a7713b1edbc | 1736 | /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset |
AnnaBridge | 171:3a7713b1edbc | 1737 | * @brief Forces or releases AHB/APB peripheral reset. |
AnnaBridge | 171:3a7713b1edbc | 1738 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1739 | */ |
AnnaBridge | 171:3a7713b1edbc | 1740 | |
AnnaBridge | 171:3a7713b1edbc | 1741 | /** @brief Force or release AHB1 peripheral reset. |
AnnaBridge | 171:3a7713b1edbc | 1742 | */ |
AnnaBridge | 171:3a7713b1edbc | 1743 | #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1744 | #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) |
AnnaBridge | 171:3a7713b1edbc | 1745 | #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) |
AnnaBridge | 171:3a7713b1edbc | 1746 | #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) |
AnnaBridge | 171:3a7713b1edbc | 1747 | #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)) |
AnnaBridge | 171:3a7713b1edbc | 1748 | #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) |
AnnaBridge | 171:3a7713b1edbc | 1749 | #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) |
AnnaBridge | 171:3a7713b1edbc | 1750 | #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) |
AnnaBridge | 171:3a7713b1edbc | 1751 | #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) |
AnnaBridge | 171:3a7713b1edbc | 1752 | #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST)) |
AnnaBridge | 171:3a7713b1edbc | 1753 | #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) |
AnnaBridge | 171:3a7713b1edbc | 1754 | |
AnnaBridge | 171:3a7713b1edbc | 1755 | #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1756 | #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) |
AnnaBridge | 171:3a7713b1edbc | 1757 | #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST)) |
AnnaBridge | 171:3a7713b1edbc | 1758 | #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST)) |
AnnaBridge | 171:3a7713b1edbc | 1759 | #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST)) |
AnnaBridge | 171:3a7713b1edbc | 1760 | #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) |
AnnaBridge | 171:3a7713b1edbc | 1761 | #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) |
AnnaBridge | 171:3a7713b1edbc | 1762 | #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) |
AnnaBridge | 171:3a7713b1edbc | 1763 | #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) |
AnnaBridge | 171:3a7713b1edbc | 1764 | #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST)) |
AnnaBridge | 171:3a7713b1edbc | 1765 | #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) |
AnnaBridge | 171:3a7713b1edbc | 1766 | |
AnnaBridge | 171:3a7713b1edbc | 1767 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 1768 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1769 | #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) |
AnnaBridge | 171:3a7713b1edbc | 1770 | #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) |
AnnaBridge | 171:3a7713b1edbc | 1771 | #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) |
AnnaBridge | 171:3a7713b1edbc | 1772 | #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) |
AnnaBridge | 171:3a7713b1edbc | 1773 | |
AnnaBridge | 171:3a7713b1edbc | 1774 | #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) |
AnnaBridge | 171:3a7713b1edbc | 1775 | #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) |
AnnaBridge | 171:3a7713b1edbc | 1776 | #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) |
AnnaBridge | 171:3a7713b1edbc | 1777 | #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) |
AnnaBridge | 171:3a7713b1edbc | 1778 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1779 | |
AnnaBridge | 171:3a7713b1edbc | 1780 | /** @brief Force or release AHB2 peripheral reset. |
AnnaBridge | 171:3a7713b1edbc | 1781 | */ |
AnnaBridge | 171:3a7713b1edbc | 1782 | #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 1783 | #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) |
AnnaBridge | 171:3a7713b1edbc | 1784 | #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) |
AnnaBridge | 171:3a7713b1edbc | 1785 | |
AnnaBridge | 171:3a7713b1edbc | 1786 | #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) |
AnnaBridge | 171:3a7713b1edbc | 1787 | #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) |
AnnaBridge | 171:3a7713b1edbc | 1788 | #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) |
AnnaBridge | 171:3a7713b1edbc | 1789 | |
AnnaBridge | 171:3a7713b1edbc | 1790 | #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1791 | #define __HAL_RCC_JPEG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST)) |
AnnaBridge | 171:3a7713b1edbc | 1792 | #define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST)) |
AnnaBridge | 171:3a7713b1edbc | 1793 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1794 | |
AnnaBridge | 171:3a7713b1edbc | 1795 | #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1796 | #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) |
AnnaBridge | 171:3a7713b1edbc | 1797 | #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) |
AnnaBridge | 171:3a7713b1edbc | 1798 | #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) |
AnnaBridge | 171:3a7713b1edbc | 1799 | #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) |
AnnaBridge | 171:3a7713b1edbc | 1800 | #endif /* STM32F756xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1801 | |
AnnaBridge | 171:3a7713b1edbc | 1802 | #if defined(STM32F732xx) || defined (STM32F733xx) |
AnnaBridge | 171:3a7713b1edbc | 1803 | #define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST)) |
AnnaBridge | 171:3a7713b1edbc | 1804 | #define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST)) |
AnnaBridge | 171:3a7713b1edbc | 1805 | #endif /* STM32F732xx || STM32F733xx */ |
AnnaBridge | 171:3a7713b1edbc | 1806 | |
AnnaBridge | 171:3a7713b1edbc | 1807 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 1808 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1809 | #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) |
AnnaBridge | 171:3a7713b1edbc | 1810 | #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) |
AnnaBridge | 171:3a7713b1edbc | 1811 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1812 | |
AnnaBridge | 171:3a7713b1edbc | 1813 | /** @brief Force or release AHB3 peripheral reset |
AnnaBridge | 171:3a7713b1edbc | 1814 | */ |
AnnaBridge | 171:3a7713b1edbc | 1815 | #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 1816 | #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) |
AnnaBridge | 171:3a7713b1edbc | 1817 | #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) |
AnnaBridge | 171:3a7713b1edbc | 1818 | |
AnnaBridge | 171:3a7713b1edbc | 1819 | #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) |
AnnaBridge | 171:3a7713b1edbc | 1820 | #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) |
AnnaBridge | 171:3a7713b1edbc | 1821 | #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) |
AnnaBridge | 171:3a7713b1edbc | 1822 | |
AnnaBridge | 171:3a7713b1edbc | 1823 | /** @brief Force or release APB1 peripheral reset. |
AnnaBridge | 171:3a7713b1edbc | 1824 | */ |
AnnaBridge | 171:3a7713b1edbc | 1825 | #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1826 | #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) |
AnnaBridge | 171:3a7713b1edbc | 1827 | #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) |
AnnaBridge | 171:3a7713b1edbc | 1828 | #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) |
AnnaBridge | 171:3a7713b1edbc | 1829 | #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) |
AnnaBridge | 171:3a7713b1edbc | 1830 | #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) |
AnnaBridge | 171:3a7713b1edbc | 1831 | #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) |
AnnaBridge | 171:3a7713b1edbc | 1832 | #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) |
AnnaBridge | 171:3a7713b1edbc | 1833 | #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) |
AnnaBridge | 171:3a7713b1edbc | 1834 | #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) |
AnnaBridge | 171:3a7713b1edbc | 1835 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1836 | #define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST)) |
AnnaBridge | 171:3a7713b1edbc | 1837 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1838 | #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1839 | #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) |
AnnaBridge | 171:3a7713b1edbc | 1840 | #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1841 | #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) |
AnnaBridge | 171:3a7713b1edbc | 1842 | #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) |
AnnaBridge | 171:3a7713b1edbc | 1843 | #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) |
AnnaBridge | 171:3a7713b1edbc | 1844 | #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) |
AnnaBridge | 171:3a7713b1edbc | 1845 | #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1846 | #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) |
AnnaBridge | 171:3a7713b1edbc | 1847 | #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) |
AnnaBridge | 171:3a7713b1edbc | 1848 | #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) |
AnnaBridge | 171:3a7713b1edbc | 1849 | #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) |
AnnaBridge | 171:3a7713b1edbc | 1850 | #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) |
AnnaBridge | 171:3a7713b1edbc | 1851 | |
AnnaBridge | 171:3a7713b1edbc | 1852 | #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1853 | #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) |
AnnaBridge | 171:3a7713b1edbc | 1854 | #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) |
AnnaBridge | 171:3a7713b1edbc | 1855 | #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) |
AnnaBridge | 171:3a7713b1edbc | 1856 | #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) |
AnnaBridge | 171:3a7713b1edbc | 1857 | #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) |
AnnaBridge | 171:3a7713b1edbc | 1858 | #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) |
AnnaBridge | 171:3a7713b1edbc | 1859 | #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) |
AnnaBridge | 171:3a7713b1edbc | 1860 | #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) |
AnnaBridge | 171:3a7713b1edbc | 1861 | #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) |
AnnaBridge | 171:3a7713b1edbc | 1862 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1863 | #define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST)) |
AnnaBridge | 171:3a7713b1edbc | 1864 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1865 | #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1866 | #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) |
AnnaBridge | 171:3a7713b1edbc | 1867 | #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1868 | #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) |
AnnaBridge | 171:3a7713b1edbc | 1869 | #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) |
AnnaBridge | 171:3a7713b1edbc | 1870 | #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) |
AnnaBridge | 171:3a7713b1edbc | 1871 | #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) |
AnnaBridge | 171:3a7713b1edbc | 1872 | #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1873 | #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) |
AnnaBridge | 171:3a7713b1edbc | 1874 | #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) |
AnnaBridge | 171:3a7713b1edbc | 1875 | #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) |
AnnaBridge | 171:3a7713b1edbc | 1876 | #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) |
AnnaBridge | 171:3a7713b1edbc | 1877 | #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) |
AnnaBridge | 171:3a7713b1edbc | 1878 | |
AnnaBridge | 171:3a7713b1edbc | 1879 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 1880 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1881 | #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) |
AnnaBridge | 171:3a7713b1edbc | 1882 | #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST)) |
AnnaBridge | 171:3a7713b1edbc | 1883 | #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1884 | #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) |
AnnaBridge | 171:3a7713b1edbc | 1885 | |
AnnaBridge | 171:3a7713b1edbc | 1886 | #define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) |
AnnaBridge | 171:3a7713b1edbc | 1887 | #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST)) |
AnnaBridge | 171:3a7713b1edbc | 1888 | #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1889 | #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) |
AnnaBridge | 171:3a7713b1edbc | 1890 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1891 | |
AnnaBridge | 171:3a7713b1edbc | 1892 | /** @brief Force or release APB2 peripheral reset. |
AnnaBridge | 171:3a7713b1edbc | 1893 | */ |
AnnaBridge | 171:3a7713b1edbc | 1894 | #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) |
AnnaBridge | 171:3a7713b1edbc | 1895 | #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) |
AnnaBridge | 171:3a7713b1edbc | 1896 | #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) |
AnnaBridge | 171:3a7713b1edbc | 1897 | #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) |
AnnaBridge | 171:3a7713b1edbc | 1898 | #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST)) |
AnnaBridge | 171:3a7713b1edbc | 1899 | #define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST)) |
AnnaBridge | 171:3a7713b1edbc | 1900 | #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) |
AnnaBridge | 171:3a7713b1edbc | 1901 | #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) |
AnnaBridge | 171:3a7713b1edbc | 1902 | #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) |
AnnaBridge | 171:3a7713b1edbc | 1903 | #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) |
AnnaBridge | 171:3a7713b1edbc | 1904 | #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) |
AnnaBridge | 171:3a7713b1edbc | 1905 | #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) |
AnnaBridge | 171:3a7713b1edbc | 1906 | #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) |
AnnaBridge | 171:3a7713b1edbc | 1907 | #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) |
AnnaBridge | 171:3a7713b1edbc | 1908 | #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1909 | #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1910 | #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) |
AnnaBridge | 171:3a7713b1edbc | 1911 | #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1912 | #if defined (STM32F723xx) || defined (STM32F733xx) |
AnnaBridge | 171:3a7713b1edbc | 1913 | #define __HAL_RCC_OTGPHYC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_OTGPHYCRST)) |
AnnaBridge | 171:3a7713b1edbc | 1914 | #endif /* STM32F723xx || STM32F733xx */ |
AnnaBridge | 171:3a7713b1edbc | 1915 | |
AnnaBridge | 171:3a7713b1edbc | 1916 | #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) |
AnnaBridge | 171:3a7713b1edbc | 1917 | #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) |
AnnaBridge | 171:3a7713b1edbc | 1918 | #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) |
AnnaBridge | 171:3a7713b1edbc | 1919 | #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) |
AnnaBridge | 171:3a7713b1edbc | 1920 | #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST)) |
AnnaBridge | 171:3a7713b1edbc | 1921 | #define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST)) |
AnnaBridge | 171:3a7713b1edbc | 1922 | #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) |
AnnaBridge | 171:3a7713b1edbc | 1923 | #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) |
AnnaBridge | 171:3a7713b1edbc | 1924 | #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) |
AnnaBridge | 171:3a7713b1edbc | 1925 | #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) |
AnnaBridge | 171:3a7713b1edbc | 1926 | #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) |
AnnaBridge | 171:3a7713b1edbc | 1927 | #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) |
AnnaBridge | 171:3a7713b1edbc | 1928 | #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) |
AnnaBridge | 171:3a7713b1edbc | 1929 | #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) |
AnnaBridge | 171:3a7713b1edbc | 1930 | #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1931 | #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1932 | #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) |
AnnaBridge | 171:3a7713b1edbc | 1933 | #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1934 | #if defined (STM32F723xx) || defined (STM32F733xx) |
AnnaBridge | 171:3a7713b1edbc | 1935 | #define __HAL_RCC_OTGPHYC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_OTGPHYCRST)) |
AnnaBridge | 171:3a7713b1edbc | 1936 | #endif /* STM32F723xx || STM32F733xx */ |
AnnaBridge | 171:3a7713b1edbc | 1937 | |
AnnaBridge | 171:3a7713b1edbc | 1938 | #if defined (STM32F769xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1939 | #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) |
AnnaBridge | 171:3a7713b1edbc | 1940 | #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) |
AnnaBridge | 171:3a7713b1edbc | 1941 | #endif /* STM32F769xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1942 | |
AnnaBridge | 171:3a7713b1edbc | 1943 | #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 1944 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1945 | #define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1946 | #define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1947 | #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1948 | |
AnnaBridge | 171:3a7713b1edbc | 1949 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 1950 | #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) |
AnnaBridge | 171:3a7713b1edbc | 1951 | #define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST)) |
AnnaBridge | 171:3a7713b1edbc | 1952 | #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) |
AnnaBridge | 171:3a7713b1edbc | 1953 | #define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST)) |
AnnaBridge | 171:3a7713b1edbc | 1954 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 1955 | /** |
AnnaBridge | 171:3a7713b1edbc | 1956 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1957 | */ |
AnnaBridge | 171:3a7713b1edbc | 1958 | |
AnnaBridge | 171:3a7713b1edbc | 1959 | /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable |
AnnaBridge | 171:3a7713b1edbc | 1960 | * @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode. |
AnnaBridge | 171:3a7713b1edbc | 1961 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 171:3a7713b1edbc | 1962 | * power consumption. |
AnnaBridge | 171:3a7713b1edbc | 1963 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 171:3a7713b1edbc | 1964 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 171:3a7713b1edbc | 1965 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1966 | */ |
AnnaBridge | 171:3a7713b1edbc | 1967 | |
AnnaBridge | 171:3a7713b1edbc | 1968 | /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. |
AnnaBridge | 171:3a7713b1edbc | 1969 | */ |
AnnaBridge | 171:3a7713b1edbc | 1970 | #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1971 | #define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1972 | #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1973 | #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1974 | #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1975 | #define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1976 | #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1977 | #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1978 | #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1979 | #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1980 | #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1981 | #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1982 | #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1983 | #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1984 | #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1985 | #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1986 | #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1987 | #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1988 | |
AnnaBridge | 171:3a7713b1edbc | 1989 | #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1990 | #define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1991 | #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1992 | #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1993 | #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1994 | #define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1995 | #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1996 | #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1997 | #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1998 | #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN)) |
AnnaBridge | 171:3a7713b1edbc | 1999 | #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2000 | #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2001 | #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2002 | #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2003 | #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2004 | #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2005 | #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2006 | #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2007 | |
AnnaBridge | 171:3a7713b1edbc | 2008 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 2009 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2010 | #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2011 | #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2012 | #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2013 | #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2014 | #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2015 | #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2016 | #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2017 | |
AnnaBridge | 171:3a7713b1edbc | 2018 | #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2019 | #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2020 | #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2021 | #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2022 | #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2023 | #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2024 | #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2025 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2026 | |
AnnaBridge | 171:3a7713b1edbc | 2027 | /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. |
AnnaBridge | 171:3a7713b1edbc | 2028 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 171:3a7713b1edbc | 2029 | * power consumption. |
AnnaBridge | 171:3a7713b1edbc | 2030 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 171:3a7713b1edbc | 2031 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 171:3a7713b1edbc | 2032 | */ |
AnnaBridge | 171:3a7713b1edbc | 2033 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 2034 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2035 | #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2036 | #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2037 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2038 | |
AnnaBridge | 171:3a7713b1edbc | 2039 | #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2040 | #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2041 | #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2042 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2043 | |
AnnaBridge | 171:3a7713b1edbc | 2044 | #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2045 | #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2046 | |
AnnaBridge | 171:3a7713b1edbc | 2047 | #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2048 | #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2049 | |
AnnaBridge | 171:3a7713b1edbc | 2050 | #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2051 | #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2052 | #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2053 | |
AnnaBridge | 171:3a7713b1edbc | 2054 | #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2055 | #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2056 | #endif /* STM32F756xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2057 | |
AnnaBridge | 171:3a7713b1edbc | 2058 | #if defined(STM32F732xx) || defined (STM32F733xx) |
AnnaBridge | 171:3a7713b1edbc | 2059 | #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2060 | #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2061 | #endif /* STM32F732xx || STM32F733xx */ |
AnnaBridge | 171:3a7713b1edbc | 2062 | |
AnnaBridge | 171:3a7713b1edbc | 2063 | /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. |
AnnaBridge | 171:3a7713b1edbc | 2064 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 171:3a7713b1edbc | 2065 | * power consumption. |
AnnaBridge | 171:3a7713b1edbc | 2066 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 171:3a7713b1edbc | 2067 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 171:3a7713b1edbc | 2068 | */ |
AnnaBridge | 171:3a7713b1edbc | 2069 | #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2070 | #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2071 | |
AnnaBridge | 171:3a7713b1edbc | 2072 | #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2073 | #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2074 | |
AnnaBridge | 171:3a7713b1edbc | 2075 | /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. |
AnnaBridge | 171:3a7713b1edbc | 2076 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 171:3a7713b1edbc | 2077 | * power consumption. |
AnnaBridge | 171:3a7713b1edbc | 2078 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 171:3a7713b1edbc | 2079 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 171:3a7713b1edbc | 2080 | */ |
AnnaBridge | 171:3a7713b1edbc | 2081 | #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2082 | #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2083 | #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2084 | #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2085 | #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2086 | #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2087 | #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2088 | #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2089 | #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2090 | #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2091 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2092 | #define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2093 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2094 | #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2095 | #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2096 | #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2097 | #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2098 | #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2099 | #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2100 | #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2101 | #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2102 | #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2103 | #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2104 | #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2105 | #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2106 | #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2107 | |
AnnaBridge | 171:3a7713b1edbc | 2108 | #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2109 | #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2110 | #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2111 | #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2112 | #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2113 | #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2114 | #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2115 | #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2116 | #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2117 | #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2118 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2119 | #define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2120 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2121 | #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2122 | #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2123 | #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2124 | #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2125 | #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2126 | #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2127 | #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2128 | #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2129 | #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2130 | #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2131 | #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2132 | #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2133 | #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2134 | |
AnnaBridge | 171:3a7713b1edbc | 2135 | #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 2136 | defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 2137 | defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2138 | #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2139 | #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2140 | #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || |
AnnaBridge | 171:3a7713b1edbc | 2141 | STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2142 | |
AnnaBridge | 171:3a7713b1edbc | 2143 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 2144 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2145 | #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2146 | #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2147 | #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2148 | #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2149 | |
AnnaBridge | 171:3a7713b1edbc | 2150 | #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2151 | #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2152 | #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2153 | #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2154 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2155 | |
AnnaBridge | 171:3a7713b1edbc | 2156 | /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. |
AnnaBridge | 171:3a7713b1edbc | 2157 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 171:3a7713b1edbc | 2158 | * power consumption. |
AnnaBridge | 171:3a7713b1edbc | 2159 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 171:3a7713b1edbc | 2160 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 171:3a7713b1edbc | 2161 | */ |
AnnaBridge | 171:3a7713b1edbc | 2162 | #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2163 | #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2164 | #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2165 | #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2166 | #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2167 | #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2168 | #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2169 | #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2170 | #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2171 | #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2172 | #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2173 | #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2174 | #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2175 | #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2176 | #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2177 | #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2178 | #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2179 | #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2180 | #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2181 | |
AnnaBridge | 171:3a7713b1edbc | 2182 | #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2183 | #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2184 | #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2185 | #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2186 | #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2187 | #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2188 | #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2189 | #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2190 | #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2191 | #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2192 | #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2193 | #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2194 | #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2195 | #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2196 | #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2197 | #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2198 | #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2199 | #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2200 | #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2201 | #if defined (STM32F769xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2202 | #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2203 | #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2204 | #endif /* STM32F769xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2205 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2206 | #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2207 | #define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2208 | #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2209 | #define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2210 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2211 | #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 2212 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2213 | #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2214 | #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2215 | #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2216 | |
AnnaBridge | 171:3a7713b1edbc | 2217 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 2218 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2219 | #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2220 | #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) |
AnnaBridge | 171:3a7713b1edbc | 2221 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2222 | /** |
AnnaBridge | 171:3a7713b1edbc | 2223 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2224 | */ |
AnnaBridge | 171:3a7713b1edbc | 2225 | |
AnnaBridge | 171:3a7713b1edbc | 2226 | /** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status |
AnnaBridge | 171:3a7713b1edbc | 2227 | * @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode. |
AnnaBridge | 171:3a7713b1edbc | 2228 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 171:3a7713b1edbc | 2229 | * power consumption. |
AnnaBridge | 171:3a7713b1edbc | 2230 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 171:3a7713b1edbc | 2231 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 171:3a7713b1edbc | 2232 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2233 | */ |
AnnaBridge | 171:3a7713b1edbc | 2234 | |
AnnaBridge | 171:3a7713b1edbc | 2235 | /** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode. |
AnnaBridge | 171:3a7713b1edbc | 2236 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 171:3a7713b1edbc | 2237 | * power consumption. |
AnnaBridge | 171:3a7713b1edbc | 2238 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 171:3a7713b1edbc | 2239 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 171:3a7713b1edbc | 2240 | */ |
AnnaBridge | 171:3a7713b1edbc | 2241 | #define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2242 | #define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2243 | #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2244 | #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2245 | #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2246 | #define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2247 | #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2248 | #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2249 | #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2250 | #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2251 | #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2252 | #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2253 | #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2254 | #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2255 | #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2256 | #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2257 | #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2258 | #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2259 | |
AnnaBridge | 171:3a7713b1edbc | 2260 | #define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2261 | #define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2262 | #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2263 | #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2264 | #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2265 | #define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2266 | #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2267 | #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2268 | #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2269 | #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2270 | #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2271 | #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2272 | #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2273 | #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2274 | #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2275 | #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2276 | #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2277 | #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2278 | |
AnnaBridge | 171:3a7713b1edbc | 2279 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 2280 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2281 | #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2282 | #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2283 | #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2284 | #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2285 | #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2286 | #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2287 | #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2288 | |
AnnaBridge | 171:3a7713b1edbc | 2289 | #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2290 | #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2291 | #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2292 | #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2293 | #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2294 | #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2295 | #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2296 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2297 | |
AnnaBridge | 171:3a7713b1edbc | 2298 | /** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode. |
AnnaBridge | 171:3a7713b1edbc | 2299 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 171:3a7713b1edbc | 2300 | * power consumption. |
AnnaBridge | 171:3a7713b1edbc | 2301 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 171:3a7713b1edbc | 2302 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 171:3a7713b1edbc | 2303 | */ |
AnnaBridge | 171:3a7713b1edbc | 2304 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 2305 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2306 | #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2307 | #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2308 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2309 | |
AnnaBridge | 171:3a7713b1edbc | 2310 | #if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2311 | #define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2312 | #define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2313 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2314 | |
AnnaBridge | 171:3a7713b1edbc | 2315 | #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2316 | #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2317 | |
AnnaBridge | 171:3a7713b1edbc | 2318 | #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2319 | #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2320 | |
AnnaBridge | 171:3a7713b1edbc | 2321 | #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2322 | #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2323 | #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2324 | |
AnnaBridge | 171:3a7713b1edbc | 2325 | #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2326 | #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2327 | #endif /* STM32F756xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2328 | |
AnnaBridge | 171:3a7713b1edbc | 2329 | #if defined(STM32F732xx) || defined (STM32F733xx) |
AnnaBridge | 171:3a7713b1edbc | 2330 | #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2331 | #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2332 | #endif /* STM32F732xx || STM32F733xx */ |
AnnaBridge | 171:3a7713b1edbc | 2333 | |
AnnaBridge | 171:3a7713b1edbc | 2334 | /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode. |
AnnaBridge | 171:3a7713b1edbc | 2335 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 171:3a7713b1edbc | 2336 | * power consumption. |
AnnaBridge | 171:3a7713b1edbc | 2337 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 171:3a7713b1edbc | 2338 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 171:3a7713b1edbc | 2339 | */ |
AnnaBridge | 171:3a7713b1edbc | 2340 | #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2341 | #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2342 | |
AnnaBridge | 171:3a7713b1edbc | 2343 | #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2344 | #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2345 | |
AnnaBridge | 171:3a7713b1edbc | 2346 | /** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. |
AnnaBridge | 171:3a7713b1edbc | 2347 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 171:3a7713b1edbc | 2348 | * power consumption. |
AnnaBridge | 171:3a7713b1edbc | 2349 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 171:3a7713b1edbc | 2350 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 171:3a7713b1edbc | 2351 | */ |
AnnaBridge | 171:3a7713b1edbc | 2352 | #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2353 | #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2354 | #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2355 | #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2356 | #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2357 | #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2358 | #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2359 | #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2360 | #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2361 | #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2362 | #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 2363 | defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 2364 | defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2365 | #define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2366 | #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || |
AnnaBridge | 171:3a7713b1edbc | 2367 | STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2368 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2369 | #define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2370 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2371 | #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2372 | #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2373 | #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2374 | #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2375 | #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2376 | #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2377 | #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2378 | #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2379 | #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2380 | #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2381 | #define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2382 | #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2383 | #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2384 | |
AnnaBridge | 171:3a7713b1edbc | 2385 | #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2386 | #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2387 | #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2388 | #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2389 | #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2390 | #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2391 | #define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2392 | #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2393 | #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2394 | #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2395 | #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 2396 | defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 2397 | defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2398 | #define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2399 | #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || |
AnnaBridge | 171:3a7713b1edbc | 2400 | STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2401 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2402 | #define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2403 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2404 | #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2405 | #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2406 | #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2407 | #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2408 | #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2409 | #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2410 | #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2411 | #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2412 | #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2413 | #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2414 | #define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2415 | #define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2416 | #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2417 | |
AnnaBridge | 171:3a7713b1edbc | 2418 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 2419 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2420 | #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2421 | #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2422 | #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2423 | #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2424 | |
AnnaBridge | 171:3a7713b1edbc | 2425 | #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2426 | #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2427 | #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2428 | #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2429 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2430 | |
AnnaBridge | 171:3a7713b1edbc | 2431 | /** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. |
AnnaBridge | 171:3a7713b1edbc | 2432 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
AnnaBridge | 171:3a7713b1edbc | 2433 | * power consumption. |
AnnaBridge | 171:3a7713b1edbc | 2434 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
AnnaBridge | 171:3a7713b1edbc | 2435 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
AnnaBridge | 171:3a7713b1edbc | 2436 | */ |
AnnaBridge | 171:3a7713b1edbc | 2437 | #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2438 | #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2439 | #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2440 | #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2441 | #define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2442 | #define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2443 | #define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2444 | #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2445 | #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2446 | #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2447 | #define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2448 | #define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2449 | #define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2450 | #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2451 | #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2452 | #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2453 | #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2454 | #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2455 | #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2456 | #if defined (STM32F769xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2457 | #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2458 | #endif /* STM32F769xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2459 | #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 2460 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2461 | #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2462 | #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2463 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2464 | #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2465 | #define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2466 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2467 | |
AnnaBridge | 171:3a7713b1edbc | 2468 | #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2469 | #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2470 | #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2471 | #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2472 | #define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2473 | #define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2474 | #define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2475 | #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2476 | #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2477 | #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2478 | #define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2479 | #define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2480 | #define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2481 | #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2482 | #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2483 | #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2484 | #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2485 | #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2486 | #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2487 | #if defined (STM32F769xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2488 | #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2489 | #endif /* STM32F769xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2490 | #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 2491 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2492 | #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2493 | #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2494 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2495 | #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2496 | #define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2497 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2498 | |
AnnaBridge | 171:3a7713b1edbc | 2499 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 2500 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2501 | #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 2502 | #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 2503 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2504 | /** |
AnnaBridge | 171:3a7713b1edbc | 2505 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2506 | */ |
AnnaBridge | 171:3a7713b1edbc | 2507 | |
AnnaBridge | 171:3a7713b1edbc | 2508 | /*------------------------------- PLL Configuration --------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 2509 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2510 | /** @brief Macro to configure the main PLL clock source, multiplication and division factors. |
AnnaBridge | 171:3a7713b1edbc | 2511 | * @note This function must be used only when the main PLL is disabled. |
AnnaBridge | 171:3a7713b1edbc | 2512 | * @param __RCC_PLLSource__ specifies the PLL entry clock source. |
AnnaBridge | 171:3a7713b1edbc | 2513 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2514 | * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry |
AnnaBridge | 171:3a7713b1edbc | 2515 | * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry |
AnnaBridge | 171:3a7713b1edbc | 2516 | * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. |
AnnaBridge | 171:3a7713b1edbc | 2517 | * @param __PLLM__ specifies the division factor for PLL VCO input clock |
AnnaBridge | 171:3a7713b1edbc | 2518 | * This parameter must be a number between Min_Data = 2 and Max_Data = 63. |
AnnaBridge | 171:3a7713b1edbc | 2519 | * @note You have to set the PLLM parameter correctly to ensure that the VCO input |
AnnaBridge | 171:3a7713b1edbc | 2520 | * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency |
AnnaBridge | 171:3a7713b1edbc | 2521 | * of 2 MHz to limit PLL jitter. |
AnnaBridge | 171:3a7713b1edbc | 2522 | * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock |
AnnaBridge | 171:3a7713b1edbc | 2523 | * This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
AnnaBridge | 171:3a7713b1edbc | 2524 | * @note You have to set the PLLN parameter correctly to ensure that the VCO |
AnnaBridge | 171:3a7713b1edbc | 2525 | * output frequency is between 100 and 432 MHz. |
AnnaBridge | 171:3a7713b1edbc | 2526 | * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) |
AnnaBridge | 171:3a7713b1edbc | 2527 | * This parameter must be a number in the range {2, 4, 6, or 8}. |
AnnaBridge | 171:3a7713b1edbc | 2528 | * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on |
AnnaBridge | 171:3a7713b1edbc | 2529 | * the System clock frequency. |
AnnaBridge | 171:3a7713b1edbc | 2530 | * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks |
AnnaBridge | 171:3a7713b1edbc | 2531 | * This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
AnnaBridge | 171:3a7713b1edbc | 2532 | * @note If the USB OTG FS is used in your application, you have to set the |
AnnaBridge | 171:3a7713b1edbc | 2533 | * PLLQ parameter correctly to have 48 MHz clock for the USB. However, |
AnnaBridge | 171:3a7713b1edbc | 2534 | * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work |
AnnaBridge | 171:3a7713b1edbc | 2535 | * correctly. |
AnnaBridge | 171:3a7713b1edbc | 2536 | * @param __PLLR__ specifies the division factor for DSI clock |
AnnaBridge | 171:3a7713b1edbc | 2537 | * This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
AnnaBridge | 171:3a7713b1edbc | 2538 | */ |
AnnaBridge | 171:3a7713b1edbc | 2539 | #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ |
AnnaBridge | 171:3a7713b1edbc | 2540 | (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ |
AnnaBridge | 171:3a7713b1edbc | 2541 | ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ |
AnnaBridge | 171:3a7713b1edbc | 2542 | ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \ |
AnnaBridge | 171:3a7713b1edbc | 2543 | ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \ |
AnnaBridge | 171:3a7713b1edbc | 2544 | ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 2545 | #else |
AnnaBridge | 171:3a7713b1edbc | 2546 | /** @brief Macro to configure the main PLL clock source, multiplication and division factors. |
AnnaBridge | 171:3a7713b1edbc | 2547 | * @note This function must be used only when the main PLL is disabled. |
AnnaBridge | 171:3a7713b1edbc | 2548 | * @param __RCC_PLLSource__ specifies the PLL entry clock source. |
AnnaBridge | 171:3a7713b1edbc | 2549 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2550 | * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry |
AnnaBridge | 171:3a7713b1edbc | 2551 | * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry |
AnnaBridge | 171:3a7713b1edbc | 2552 | * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. |
AnnaBridge | 171:3a7713b1edbc | 2553 | * @param __PLLM__ specifies the division factor for PLL VCO input clock |
AnnaBridge | 171:3a7713b1edbc | 2554 | * This parameter must be a number between Min_Data = 2 and Max_Data = 63. |
AnnaBridge | 171:3a7713b1edbc | 2555 | * @note You have to set the PLLM parameter correctly to ensure that the VCO input |
AnnaBridge | 171:3a7713b1edbc | 2556 | * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency |
AnnaBridge | 171:3a7713b1edbc | 2557 | * of 2 MHz to limit PLL jitter. |
AnnaBridge | 171:3a7713b1edbc | 2558 | * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock |
AnnaBridge | 171:3a7713b1edbc | 2559 | * This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
AnnaBridge | 171:3a7713b1edbc | 2560 | * @note You have to set the PLLN parameter correctly to ensure that the VCO |
AnnaBridge | 171:3a7713b1edbc | 2561 | * output frequency is between 100 and 432 MHz. |
AnnaBridge | 171:3a7713b1edbc | 2562 | * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) |
AnnaBridge | 171:3a7713b1edbc | 2563 | * This parameter must be a number in the range {2, 4, 6, or 8}. |
AnnaBridge | 171:3a7713b1edbc | 2564 | * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on |
AnnaBridge | 171:3a7713b1edbc | 2565 | * the System clock frequency. |
AnnaBridge | 171:3a7713b1edbc | 2566 | * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks |
AnnaBridge | 171:3a7713b1edbc | 2567 | * This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
AnnaBridge | 171:3a7713b1edbc | 2568 | * @note If the USB OTG FS is used in your application, you have to set the |
AnnaBridge | 171:3a7713b1edbc | 2569 | * PLLQ parameter correctly to have 48 MHz clock for the USB. However, |
AnnaBridge | 171:3a7713b1edbc | 2570 | * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work |
AnnaBridge | 171:3a7713b1edbc | 2571 | * correctly. |
AnnaBridge | 171:3a7713b1edbc | 2572 | */ |
AnnaBridge | 171:3a7713b1edbc | 2573 | #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ |
AnnaBridge | 171:3a7713b1edbc | 2574 | (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \ |
AnnaBridge | 171:3a7713b1edbc | 2575 | ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ |
AnnaBridge | 171:3a7713b1edbc | 2576 | ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \ |
AnnaBridge | 171:3a7713b1edbc | 2577 | ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 2578 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2579 | /*---------------------------------------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 2580 | |
AnnaBridge | 171:3a7713b1edbc | 2581 | /** @brief Macro to configure the Timers clocks prescalers |
AnnaBridge | 171:3a7713b1edbc | 2582 | * @param __PRESC__ specifies the Timers clocks prescalers selection |
AnnaBridge | 171:3a7713b1edbc | 2583 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2584 | * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is |
AnnaBridge | 171:3a7713b1edbc | 2585 | * equal to HPRE if PPREx is corresponding to division by 1 or 2, |
AnnaBridge | 171:3a7713b1edbc | 2586 | * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to |
AnnaBridge | 171:3a7713b1edbc | 2587 | * division by 4 or more. |
AnnaBridge | 171:3a7713b1edbc | 2588 | * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is |
AnnaBridge | 171:3a7713b1edbc | 2589 | * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, |
AnnaBridge | 171:3a7713b1edbc | 2590 | * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding |
AnnaBridge | 171:3a7713b1edbc | 2591 | * to division by 8 or more. |
AnnaBridge | 171:3a7713b1edbc | 2592 | */ |
AnnaBridge | 171:3a7713b1edbc | 2593 | #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\ |
AnnaBridge | 171:3a7713b1edbc | 2594 | RCC->DCKCFGR1 |= (__PRESC__); \ |
AnnaBridge | 171:3a7713b1edbc | 2595 | }while(0) |
AnnaBridge | 171:3a7713b1edbc | 2596 | |
AnnaBridge | 171:3a7713b1edbc | 2597 | /** @brief Macros to Enable or Disable the PLLISAI. |
AnnaBridge | 171:3a7713b1edbc | 2598 | * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. |
AnnaBridge | 171:3a7713b1edbc | 2599 | */ |
AnnaBridge | 171:3a7713b1edbc | 2600 | #define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION)) |
AnnaBridge | 171:3a7713b1edbc | 2601 | #define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION)) |
AnnaBridge | 171:3a7713b1edbc | 2602 | |
AnnaBridge | 171:3a7713b1edbc | 2603 | #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) |
AnnaBridge | 171:3a7713b1edbc | 2604 | /** @brief Macro to configure the PLLSAI clock multiplication and division factors. |
AnnaBridge | 171:3a7713b1edbc | 2605 | * @note This function must be used only when the PLLSAI is disabled. |
AnnaBridge | 171:3a7713b1edbc | 2606 | * @note PLLSAI clock source is common with the main PLL (configured in |
AnnaBridge | 171:3a7713b1edbc | 2607 | * RCC_PLLConfig function ) |
AnnaBridge | 171:3a7713b1edbc | 2608 | * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. |
AnnaBridge | 171:3a7713b1edbc | 2609 | * This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
AnnaBridge | 171:3a7713b1edbc | 2610 | * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO |
AnnaBridge | 171:3a7713b1edbc | 2611 | * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. |
AnnaBridge | 171:3a7713b1edbc | 2612 | * @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks |
AnnaBridge | 171:3a7713b1edbc | 2613 | * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. |
AnnaBridge | 171:3a7713b1edbc | 2614 | * @param __PLLSAIQ__ specifies the division factor for SAI clock |
AnnaBridge | 171:3a7713b1edbc | 2615 | * This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
AnnaBridge | 171:3a7713b1edbc | 2616 | */ |
AnnaBridge | 171:3a7713b1edbc | 2617 | #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__) \ |
AnnaBridge | 171:3a7713b1edbc | 2618 | (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ |
AnnaBridge | 171:3a7713b1edbc | 2619 | ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ |
AnnaBridge | 171:3a7713b1edbc | 2620 | ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 2621 | |
AnnaBridge | 171:3a7713b1edbc | 2622 | /** @brief Macro to configure the PLLI2S clock multiplication and division factors. |
AnnaBridge | 171:3a7713b1edbc | 2623 | * @note This macro must be used only when the PLLI2S is disabled. |
AnnaBridge | 171:3a7713b1edbc | 2624 | * @note PLLI2S clock source is common with the main PLL (configured in |
AnnaBridge | 171:3a7713b1edbc | 2625 | * HAL_RCC_ClockConfig() API) |
AnnaBridge | 171:3a7713b1edbc | 2626 | * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. |
AnnaBridge | 171:3a7713b1edbc | 2627 | * This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
AnnaBridge | 171:3a7713b1edbc | 2628 | * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO |
AnnaBridge | 171:3a7713b1edbc | 2629 | * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. |
AnnaBridge | 171:3a7713b1edbc | 2630 | * @param __PLLI2SQ__ specifies the division factor for SAI clock. |
AnnaBridge | 171:3a7713b1edbc | 2631 | * This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
AnnaBridge | 171:3a7713b1edbc | 2632 | * @param __PLLI2SR__ specifies the division factor for I2S clock |
AnnaBridge | 171:3a7713b1edbc | 2633 | * This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
AnnaBridge | 171:3a7713b1edbc | 2634 | * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz |
AnnaBridge | 171:3a7713b1edbc | 2635 | * on the I2S clock frequency. |
AnnaBridge | 171:3a7713b1edbc | 2636 | */ |
AnnaBridge | 171:3a7713b1edbc | 2637 | #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \ |
AnnaBridge | 171:3a7713b1edbc | 2638 | (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ |
AnnaBridge | 171:3a7713b1edbc | 2639 | ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ |
AnnaBridge | 171:3a7713b1edbc | 2640 | ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 2641 | #else |
AnnaBridge | 171:3a7713b1edbc | 2642 | /** @brief Macro to configure the PLLSAI clock multiplication and division factors. |
AnnaBridge | 171:3a7713b1edbc | 2643 | * @note This function must be used only when the PLLSAI is disabled. |
AnnaBridge | 171:3a7713b1edbc | 2644 | * @note PLLSAI clock source is common with the main PLL (configured in |
AnnaBridge | 171:3a7713b1edbc | 2645 | * RCC_PLLConfig function ) |
AnnaBridge | 171:3a7713b1edbc | 2646 | * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. |
AnnaBridge | 171:3a7713b1edbc | 2647 | * This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
AnnaBridge | 171:3a7713b1edbc | 2648 | * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO |
AnnaBridge | 171:3a7713b1edbc | 2649 | * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. |
AnnaBridge | 171:3a7713b1edbc | 2650 | * @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks |
AnnaBridge | 171:3a7713b1edbc | 2651 | * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. |
AnnaBridge | 171:3a7713b1edbc | 2652 | * @param __PLLSAIQ__ specifies the division factor for SAI clock |
AnnaBridge | 171:3a7713b1edbc | 2653 | * This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
AnnaBridge | 171:3a7713b1edbc | 2654 | * @param __PLLSAIR__ specifies the division factor for LTDC clock |
AnnaBridge | 171:3a7713b1edbc | 2655 | * This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
AnnaBridge | 171:3a7713b1edbc | 2656 | */ |
AnnaBridge | 171:3a7713b1edbc | 2657 | #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ |
AnnaBridge | 171:3a7713b1edbc | 2658 | (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ |
AnnaBridge | 171:3a7713b1edbc | 2659 | ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ |
AnnaBridge | 171:3a7713b1edbc | 2660 | ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\ |
AnnaBridge | 171:3a7713b1edbc | 2661 | ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 2662 | |
AnnaBridge | 171:3a7713b1edbc | 2663 | /** @brief Macro to configure the PLLI2S clock multiplication and division factors. |
AnnaBridge | 171:3a7713b1edbc | 2664 | * @note This macro must be used only when the PLLI2S is disabled. |
AnnaBridge | 171:3a7713b1edbc | 2665 | * @note PLLI2S clock source is common with the main PLL (configured in |
AnnaBridge | 171:3a7713b1edbc | 2666 | * HAL_RCC_ClockConfig() API) |
AnnaBridge | 171:3a7713b1edbc | 2667 | * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. |
AnnaBridge | 171:3a7713b1edbc | 2668 | * This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
AnnaBridge | 171:3a7713b1edbc | 2669 | * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO |
AnnaBridge | 171:3a7713b1edbc | 2670 | * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. |
AnnaBridge | 171:3a7713b1edbc | 2671 | * @param __PLLI2SP__ specifies the division factor for SPDDIF-RX clock. |
AnnaBridge | 171:3a7713b1edbc | 2672 | * This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider. |
AnnaBridge | 171:3a7713b1edbc | 2673 | * @param __PLLI2SQ__ specifies the division factor for SAI clock. |
AnnaBridge | 171:3a7713b1edbc | 2674 | * This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
AnnaBridge | 171:3a7713b1edbc | 2675 | * @param __PLLI2SR__ specifies the division factor for I2S clock |
AnnaBridge | 171:3a7713b1edbc | 2676 | * This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
AnnaBridge | 171:3a7713b1edbc | 2677 | * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz |
AnnaBridge | 171:3a7713b1edbc | 2678 | * on the I2S clock frequency. |
AnnaBridge | 171:3a7713b1edbc | 2679 | */ |
AnnaBridge | 171:3a7713b1edbc | 2680 | #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ |
AnnaBridge | 171:3a7713b1edbc | 2681 | (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ |
AnnaBridge | 171:3a7713b1edbc | 2682 | ((__PLLI2SP__) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\ |
AnnaBridge | 171:3a7713b1edbc | 2683 | ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ |
AnnaBridge | 171:3a7713b1edbc | 2684 | ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)) |
AnnaBridge | 171:3a7713b1edbc | 2685 | #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ |
AnnaBridge | 171:3a7713b1edbc | 2686 | |
AnnaBridge | 171:3a7713b1edbc | 2687 | /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. |
AnnaBridge | 171:3a7713b1edbc | 2688 | * @note This function must be called before enabling the PLLI2S. |
AnnaBridge | 171:3a7713b1edbc | 2689 | * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock . |
AnnaBridge | 171:3a7713b1edbc | 2690 | * This parameter must be a number between 1 and 32. |
AnnaBridge | 171:3a7713b1edbc | 2691 | * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ |
AnnaBridge | 171:3a7713b1edbc | 2692 | */ |
AnnaBridge | 171:3a7713b1edbc | 2693 | #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1)) |
AnnaBridge | 171:3a7713b1edbc | 2694 | |
AnnaBridge | 171:3a7713b1edbc | 2695 | /** @brief Macro to configure the SAI clock Divider coming from PLLSAI. |
AnnaBridge | 171:3a7713b1edbc | 2696 | * @note This function must be called before enabling the PLLSAI. |
AnnaBridge | 171:3a7713b1edbc | 2697 | * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock . |
AnnaBridge | 171:3a7713b1edbc | 2698 | * This parameter must be a number between Min_Data = 1 and Max_Data = 32. |
AnnaBridge | 171:3a7713b1edbc | 2699 | * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ |
AnnaBridge | 171:3a7713b1edbc | 2700 | */ |
AnnaBridge | 171:3a7713b1edbc | 2701 | #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8)) |
AnnaBridge | 171:3a7713b1edbc | 2702 | |
AnnaBridge | 171:3a7713b1edbc | 2703 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 2704 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 2705 | /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. |
AnnaBridge | 171:3a7713b1edbc | 2706 | * @note This function must be called before enabling the PLLSAI. |
AnnaBridge | 171:3a7713b1edbc | 2707 | * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . |
AnnaBridge | 171:3a7713b1edbc | 2708 | * This parameter can be a value of @ref RCCEx_PLLSAI_DIVR. |
AnnaBridge | 171:3a7713b1edbc | 2709 | * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ |
AnnaBridge | 171:3a7713b1edbc | 2710 | */ |
AnnaBridge | 171:3a7713b1edbc | 2711 | #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\ |
AnnaBridge | 171:3a7713b1edbc | 2712 | MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__)) |
AnnaBridge | 171:3a7713b1edbc | 2713 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 2714 | |
AnnaBridge | 171:3a7713b1edbc | 2715 | /** @brief Macro to configure SAI1 clock source selection. |
AnnaBridge | 171:3a7713b1edbc | 2716 | * @note This function must be called before enabling PLLSAI, PLLI2S and |
AnnaBridge | 171:3a7713b1edbc | 2717 | * the SAI clock. |
AnnaBridge | 171:3a7713b1edbc | 2718 | * @param __SOURCE__ specifies the SAI1 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2719 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2720 | * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used |
AnnaBridge | 171:3a7713b1edbc | 2721 | * as SAI1 clock. |
AnnaBridge | 171:3a7713b1edbc | 2722 | * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used |
AnnaBridge | 171:3a7713b1edbc | 2723 | * as SAI1 clock. |
AnnaBridge | 171:3a7713b1edbc | 2724 | * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin |
AnnaBridge | 171:3a7713b1edbc | 2725 | * used as SAI1 clock. |
AnnaBridge | 171:3a7713b1edbc | 2726 | * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock |
AnnaBridge | 171:3a7713b1edbc | 2727 | * used as SAI1 clock. |
AnnaBridge | 171:3a7713b1edbc | 2728 | * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices |
AnnaBridge | 171:3a7713b1edbc | 2729 | */ |
AnnaBridge | 171:3a7713b1edbc | 2730 | #define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\ |
AnnaBridge | 171:3a7713b1edbc | 2731 | MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 2732 | |
AnnaBridge | 171:3a7713b1edbc | 2733 | /** @brief Macro to get the SAI1 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2734 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2735 | * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used |
AnnaBridge | 171:3a7713b1edbc | 2736 | * as SAI1 clock. |
AnnaBridge | 171:3a7713b1edbc | 2737 | * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used |
AnnaBridge | 171:3a7713b1edbc | 2738 | * as SAI1 clock. |
AnnaBridge | 171:3a7713b1edbc | 2739 | * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin |
AnnaBridge | 171:3a7713b1edbc | 2740 | * used as SAI1 clock. |
AnnaBridge | 171:3a7713b1edbc | 2741 | * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock |
AnnaBridge | 171:3a7713b1edbc | 2742 | * used as SAI1 clock. |
AnnaBridge | 171:3a7713b1edbc | 2743 | * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices |
AnnaBridge | 171:3a7713b1edbc | 2744 | */ |
AnnaBridge | 171:3a7713b1edbc | 2745 | #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL))) |
AnnaBridge | 171:3a7713b1edbc | 2746 | |
AnnaBridge | 171:3a7713b1edbc | 2747 | |
AnnaBridge | 171:3a7713b1edbc | 2748 | /** @brief Macro to configure SAI2 clock source selection. |
AnnaBridge | 171:3a7713b1edbc | 2749 | * @note This function must be called before enabling PLLSAI, PLLI2S and |
AnnaBridge | 171:3a7713b1edbc | 2750 | * the SAI clock. |
AnnaBridge | 171:3a7713b1edbc | 2751 | * @param __SOURCE__ specifies the SAI2 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2752 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2753 | * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used |
AnnaBridge | 171:3a7713b1edbc | 2754 | * as SAI2 clock. |
AnnaBridge | 171:3a7713b1edbc | 2755 | * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used |
AnnaBridge | 171:3a7713b1edbc | 2756 | * as SAI2 clock. |
AnnaBridge | 171:3a7713b1edbc | 2757 | * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin |
AnnaBridge | 171:3a7713b1edbc | 2758 | * used as SAI2 clock. |
AnnaBridge | 171:3a7713b1edbc | 2759 | * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock |
AnnaBridge | 171:3a7713b1edbc | 2760 | * used as SAI2 clock. |
AnnaBridge | 171:3a7713b1edbc | 2761 | * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices |
AnnaBridge | 171:3a7713b1edbc | 2762 | */ |
AnnaBridge | 171:3a7713b1edbc | 2763 | #define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\ |
AnnaBridge | 171:3a7713b1edbc | 2764 | MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 2765 | |
AnnaBridge | 171:3a7713b1edbc | 2766 | |
AnnaBridge | 171:3a7713b1edbc | 2767 | /** @brief Macro to get the SAI2 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2768 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2769 | * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used |
AnnaBridge | 171:3a7713b1edbc | 2770 | * as SAI2 clock. |
AnnaBridge | 171:3a7713b1edbc | 2771 | * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used |
AnnaBridge | 171:3a7713b1edbc | 2772 | * as SAI2 clock. |
AnnaBridge | 171:3a7713b1edbc | 2773 | * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin |
AnnaBridge | 171:3a7713b1edbc | 2774 | * used as SAI2 clock. |
AnnaBridge | 171:3a7713b1edbc | 2775 | * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock |
AnnaBridge | 171:3a7713b1edbc | 2776 | * used as SAI2 clock. |
AnnaBridge | 171:3a7713b1edbc | 2777 | * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices |
AnnaBridge | 171:3a7713b1edbc | 2778 | */ |
AnnaBridge | 171:3a7713b1edbc | 2779 | #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL))) |
AnnaBridge | 171:3a7713b1edbc | 2780 | |
AnnaBridge | 171:3a7713b1edbc | 2781 | |
AnnaBridge | 171:3a7713b1edbc | 2782 | /** @brief Enable PLLSAI_RDY interrupt. |
AnnaBridge | 171:3a7713b1edbc | 2783 | */ |
AnnaBridge | 171:3a7713b1edbc | 2784 | #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) |
AnnaBridge | 171:3a7713b1edbc | 2785 | |
AnnaBridge | 171:3a7713b1edbc | 2786 | /** @brief Disable PLLSAI_RDY interrupt. |
AnnaBridge | 171:3a7713b1edbc | 2787 | */ |
AnnaBridge | 171:3a7713b1edbc | 2788 | #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) |
AnnaBridge | 171:3a7713b1edbc | 2789 | |
AnnaBridge | 171:3a7713b1edbc | 2790 | /** @brief Clear the PLLSAI RDY interrupt pending bits. |
AnnaBridge | 171:3a7713b1edbc | 2791 | */ |
AnnaBridge | 171:3a7713b1edbc | 2792 | #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) |
AnnaBridge | 171:3a7713b1edbc | 2793 | |
AnnaBridge | 171:3a7713b1edbc | 2794 | /** @brief Check the PLLSAI RDY interrupt has occurred or not. |
AnnaBridge | 171:3a7713b1edbc | 2795 | * @retval The new state (TRUE or FALSE). |
AnnaBridge | 171:3a7713b1edbc | 2796 | */ |
AnnaBridge | 171:3a7713b1edbc | 2797 | #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) |
AnnaBridge | 171:3a7713b1edbc | 2798 | |
AnnaBridge | 171:3a7713b1edbc | 2799 | /** @brief Check PLLSAI RDY flag is set or not. |
AnnaBridge | 171:3a7713b1edbc | 2800 | * @retval The new state (TRUE or FALSE). |
AnnaBridge | 171:3a7713b1edbc | 2801 | */ |
AnnaBridge | 171:3a7713b1edbc | 2802 | #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) |
AnnaBridge | 171:3a7713b1edbc | 2803 | |
AnnaBridge | 171:3a7713b1edbc | 2804 | /** @brief Macro to Get I2S clock source selection. |
AnnaBridge | 171:3a7713b1edbc | 2805 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2806 | * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. |
AnnaBridge | 171:3a7713b1edbc | 2807 | * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source |
AnnaBridge | 171:3a7713b1edbc | 2808 | */ |
AnnaBridge | 171:3a7713b1edbc | 2809 | #define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)) |
AnnaBridge | 171:3a7713b1edbc | 2810 | |
AnnaBridge | 171:3a7713b1edbc | 2811 | /** @brief Macro to configure the I2C1 clock (I2C1CLK). |
AnnaBridge | 171:3a7713b1edbc | 2812 | * |
AnnaBridge | 171:3a7713b1edbc | 2813 | * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2814 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2815 | * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock |
AnnaBridge | 171:3a7713b1edbc | 2816 | * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock |
AnnaBridge | 171:3a7713b1edbc | 2817 | * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock |
AnnaBridge | 171:3a7713b1edbc | 2818 | */ |
AnnaBridge | 171:3a7713b1edbc | 2819 | #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 2820 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 2821 | |
AnnaBridge | 171:3a7713b1edbc | 2822 | /** @brief Macro to get the I2C1 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2823 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2824 | * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock |
AnnaBridge | 171:3a7713b1edbc | 2825 | * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock |
AnnaBridge | 171:3a7713b1edbc | 2826 | * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock |
AnnaBridge | 171:3a7713b1edbc | 2827 | */ |
AnnaBridge | 171:3a7713b1edbc | 2828 | #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL))) |
AnnaBridge | 171:3a7713b1edbc | 2829 | |
AnnaBridge | 171:3a7713b1edbc | 2830 | /** @brief Macro to configure the I2C2 clock (I2C2CLK). |
AnnaBridge | 171:3a7713b1edbc | 2831 | * |
AnnaBridge | 171:3a7713b1edbc | 2832 | * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2833 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2834 | * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock |
AnnaBridge | 171:3a7713b1edbc | 2835 | * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock |
AnnaBridge | 171:3a7713b1edbc | 2836 | * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock |
AnnaBridge | 171:3a7713b1edbc | 2837 | */ |
AnnaBridge | 171:3a7713b1edbc | 2838 | #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 2839 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 2840 | |
AnnaBridge | 171:3a7713b1edbc | 2841 | /** @brief Macro to get the I2C2 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2842 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2843 | * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock |
AnnaBridge | 171:3a7713b1edbc | 2844 | * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock |
AnnaBridge | 171:3a7713b1edbc | 2845 | * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock |
AnnaBridge | 171:3a7713b1edbc | 2846 | */ |
AnnaBridge | 171:3a7713b1edbc | 2847 | #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL))) |
AnnaBridge | 171:3a7713b1edbc | 2848 | |
AnnaBridge | 171:3a7713b1edbc | 2849 | /** @brief Macro to configure the I2C3 clock (I2C3CLK). |
AnnaBridge | 171:3a7713b1edbc | 2850 | * |
AnnaBridge | 171:3a7713b1edbc | 2851 | * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2852 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2853 | * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock |
AnnaBridge | 171:3a7713b1edbc | 2854 | * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock |
AnnaBridge | 171:3a7713b1edbc | 2855 | * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock |
AnnaBridge | 171:3a7713b1edbc | 2856 | */ |
AnnaBridge | 171:3a7713b1edbc | 2857 | #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 2858 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 2859 | |
AnnaBridge | 171:3a7713b1edbc | 2860 | /** @brief macro to get the I2C3 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2861 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2862 | * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock |
AnnaBridge | 171:3a7713b1edbc | 2863 | * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock |
AnnaBridge | 171:3a7713b1edbc | 2864 | * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock |
AnnaBridge | 171:3a7713b1edbc | 2865 | */ |
AnnaBridge | 171:3a7713b1edbc | 2866 | #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL))) |
AnnaBridge | 171:3a7713b1edbc | 2867 | |
AnnaBridge | 171:3a7713b1edbc | 2868 | /** @brief Macro to configure the I2C4 clock (I2C4CLK). |
AnnaBridge | 171:3a7713b1edbc | 2869 | * |
AnnaBridge | 171:3a7713b1edbc | 2870 | * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2871 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2872 | * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock |
AnnaBridge | 171:3a7713b1edbc | 2873 | * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock |
AnnaBridge | 171:3a7713b1edbc | 2874 | * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock |
AnnaBridge | 171:3a7713b1edbc | 2875 | */ |
AnnaBridge | 171:3a7713b1edbc | 2876 | #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 2877 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 2878 | |
AnnaBridge | 171:3a7713b1edbc | 2879 | /** @brief macro to get the I2C4 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2880 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2881 | * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock |
AnnaBridge | 171:3a7713b1edbc | 2882 | * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock |
AnnaBridge | 171:3a7713b1edbc | 2883 | * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock |
AnnaBridge | 171:3a7713b1edbc | 2884 | */ |
AnnaBridge | 171:3a7713b1edbc | 2885 | #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL))) |
AnnaBridge | 171:3a7713b1edbc | 2886 | |
AnnaBridge | 171:3a7713b1edbc | 2887 | /** @brief Macro to configure the USART1 clock (USART1CLK). |
AnnaBridge | 171:3a7713b1edbc | 2888 | * |
AnnaBridge | 171:3a7713b1edbc | 2889 | * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2890 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2891 | * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock |
AnnaBridge | 171:3a7713b1edbc | 2892 | * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock |
AnnaBridge | 171:3a7713b1edbc | 2893 | * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock |
AnnaBridge | 171:3a7713b1edbc | 2894 | * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock |
AnnaBridge | 171:3a7713b1edbc | 2895 | */ |
AnnaBridge | 171:3a7713b1edbc | 2896 | #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 2897 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 2898 | |
AnnaBridge | 171:3a7713b1edbc | 2899 | /** @brief macro to get the USART1 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2900 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2901 | * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock |
AnnaBridge | 171:3a7713b1edbc | 2902 | * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock |
AnnaBridge | 171:3a7713b1edbc | 2903 | * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock |
AnnaBridge | 171:3a7713b1edbc | 2904 | * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock |
AnnaBridge | 171:3a7713b1edbc | 2905 | */ |
AnnaBridge | 171:3a7713b1edbc | 2906 | #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL))) |
AnnaBridge | 171:3a7713b1edbc | 2907 | |
AnnaBridge | 171:3a7713b1edbc | 2908 | /** @brief Macro to configure the USART2 clock (USART2CLK). |
AnnaBridge | 171:3a7713b1edbc | 2909 | * |
AnnaBridge | 171:3a7713b1edbc | 2910 | * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2911 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2912 | * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock |
AnnaBridge | 171:3a7713b1edbc | 2913 | * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock |
AnnaBridge | 171:3a7713b1edbc | 2914 | * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock |
AnnaBridge | 171:3a7713b1edbc | 2915 | * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock |
AnnaBridge | 171:3a7713b1edbc | 2916 | */ |
AnnaBridge | 171:3a7713b1edbc | 2917 | #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 2918 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 2919 | |
AnnaBridge | 171:3a7713b1edbc | 2920 | /** @brief macro to get the USART2 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2921 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2922 | * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock |
AnnaBridge | 171:3a7713b1edbc | 2923 | * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock |
AnnaBridge | 171:3a7713b1edbc | 2924 | * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock |
AnnaBridge | 171:3a7713b1edbc | 2925 | * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock |
AnnaBridge | 171:3a7713b1edbc | 2926 | */ |
AnnaBridge | 171:3a7713b1edbc | 2927 | #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL))) |
AnnaBridge | 171:3a7713b1edbc | 2928 | |
AnnaBridge | 171:3a7713b1edbc | 2929 | /** @brief Macro to configure the USART3 clock (USART3CLK). |
AnnaBridge | 171:3a7713b1edbc | 2930 | * |
AnnaBridge | 171:3a7713b1edbc | 2931 | * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2932 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2933 | * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock |
AnnaBridge | 171:3a7713b1edbc | 2934 | * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock |
AnnaBridge | 171:3a7713b1edbc | 2935 | * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock |
AnnaBridge | 171:3a7713b1edbc | 2936 | * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock |
AnnaBridge | 171:3a7713b1edbc | 2937 | */ |
AnnaBridge | 171:3a7713b1edbc | 2938 | #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 2939 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 2940 | |
AnnaBridge | 171:3a7713b1edbc | 2941 | /** @brief macro to get the USART3 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2942 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2943 | * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock |
AnnaBridge | 171:3a7713b1edbc | 2944 | * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock |
AnnaBridge | 171:3a7713b1edbc | 2945 | * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock |
AnnaBridge | 171:3a7713b1edbc | 2946 | * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock |
AnnaBridge | 171:3a7713b1edbc | 2947 | */ |
AnnaBridge | 171:3a7713b1edbc | 2948 | #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL))) |
AnnaBridge | 171:3a7713b1edbc | 2949 | |
AnnaBridge | 171:3a7713b1edbc | 2950 | /** @brief Macro to configure the UART4 clock (UART4CLK). |
AnnaBridge | 171:3a7713b1edbc | 2951 | * |
AnnaBridge | 171:3a7713b1edbc | 2952 | * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2953 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2954 | * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock |
AnnaBridge | 171:3a7713b1edbc | 2955 | * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock |
AnnaBridge | 171:3a7713b1edbc | 2956 | * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock |
AnnaBridge | 171:3a7713b1edbc | 2957 | * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock |
AnnaBridge | 171:3a7713b1edbc | 2958 | */ |
AnnaBridge | 171:3a7713b1edbc | 2959 | #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 2960 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 2961 | |
AnnaBridge | 171:3a7713b1edbc | 2962 | /** @brief macro to get the UART4 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2963 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2964 | * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock |
AnnaBridge | 171:3a7713b1edbc | 2965 | * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock |
AnnaBridge | 171:3a7713b1edbc | 2966 | * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock |
AnnaBridge | 171:3a7713b1edbc | 2967 | * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock |
AnnaBridge | 171:3a7713b1edbc | 2968 | */ |
AnnaBridge | 171:3a7713b1edbc | 2969 | #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL))) |
AnnaBridge | 171:3a7713b1edbc | 2970 | |
AnnaBridge | 171:3a7713b1edbc | 2971 | /** @brief Macro to configure the UART5 clock (UART5CLK). |
AnnaBridge | 171:3a7713b1edbc | 2972 | * |
AnnaBridge | 171:3a7713b1edbc | 2973 | * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2974 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2975 | * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock |
AnnaBridge | 171:3a7713b1edbc | 2976 | * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock |
AnnaBridge | 171:3a7713b1edbc | 2977 | * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock |
AnnaBridge | 171:3a7713b1edbc | 2978 | * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock |
AnnaBridge | 171:3a7713b1edbc | 2979 | */ |
AnnaBridge | 171:3a7713b1edbc | 2980 | #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 2981 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 2982 | |
AnnaBridge | 171:3a7713b1edbc | 2983 | /** @brief macro to get the UART5 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2984 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2985 | * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock |
AnnaBridge | 171:3a7713b1edbc | 2986 | * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock |
AnnaBridge | 171:3a7713b1edbc | 2987 | * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock |
AnnaBridge | 171:3a7713b1edbc | 2988 | * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock |
AnnaBridge | 171:3a7713b1edbc | 2989 | */ |
AnnaBridge | 171:3a7713b1edbc | 2990 | #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL))) |
AnnaBridge | 171:3a7713b1edbc | 2991 | |
AnnaBridge | 171:3a7713b1edbc | 2992 | /** @brief Macro to configure the USART6 clock (USART6CLK). |
AnnaBridge | 171:3a7713b1edbc | 2993 | * |
AnnaBridge | 171:3a7713b1edbc | 2994 | * @param __USART6_CLKSOURCE__ specifies the USART6 clock source. |
AnnaBridge | 171:3a7713b1edbc | 2995 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2996 | * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock |
AnnaBridge | 171:3a7713b1edbc | 2997 | * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock |
AnnaBridge | 171:3a7713b1edbc | 2998 | * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock |
AnnaBridge | 171:3a7713b1edbc | 2999 | * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock |
AnnaBridge | 171:3a7713b1edbc | 3000 | */ |
AnnaBridge | 171:3a7713b1edbc | 3001 | #define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 3002 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 3003 | |
AnnaBridge | 171:3a7713b1edbc | 3004 | /** @brief macro to get the USART6 clock source. |
AnnaBridge | 171:3a7713b1edbc | 3005 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3006 | * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock |
AnnaBridge | 171:3a7713b1edbc | 3007 | * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock |
AnnaBridge | 171:3a7713b1edbc | 3008 | * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock |
AnnaBridge | 171:3a7713b1edbc | 3009 | * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock |
AnnaBridge | 171:3a7713b1edbc | 3010 | */ |
AnnaBridge | 171:3a7713b1edbc | 3011 | #define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL))) |
AnnaBridge | 171:3a7713b1edbc | 3012 | |
AnnaBridge | 171:3a7713b1edbc | 3013 | /** @brief Macro to configure the UART7 clock (UART7CLK). |
AnnaBridge | 171:3a7713b1edbc | 3014 | * |
AnnaBridge | 171:3a7713b1edbc | 3015 | * @param __UART7_CLKSOURCE__ specifies the UART7 clock source. |
AnnaBridge | 171:3a7713b1edbc | 3016 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3017 | * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock |
AnnaBridge | 171:3a7713b1edbc | 3018 | * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock |
AnnaBridge | 171:3a7713b1edbc | 3019 | * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock |
AnnaBridge | 171:3a7713b1edbc | 3020 | * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock |
AnnaBridge | 171:3a7713b1edbc | 3021 | */ |
AnnaBridge | 171:3a7713b1edbc | 3022 | #define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 3023 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 3024 | |
AnnaBridge | 171:3a7713b1edbc | 3025 | /** @brief macro to get the UART7 clock source. |
AnnaBridge | 171:3a7713b1edbc | 3026 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3027 | * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock |
AnnaBridge | 171:3a7713b1edbc | 3028 | * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock |
AnnaBridge | 171:3a7713b1edbc | 3029 | * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock |
AnnaBridge | 171:3a7713b1edbc | 3030 | * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock |
AnnaBridge | 171:3a7713b1edbc | 3031 | */ |
AnnaBridge | 171:3a7713b1edbc | 3032 | #define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL))) |
AnnaBridge | 171:3a7713b1edbc | 3033 | |
AnnaBridge | 171:3a7713b1edbc | 3034 | /** @brief Macro to configure the UART8 clock (UART8CLK). |
AnnaBridge | 171:3a7713b1edbc | 3035 | * |
AnnaBridge | 171:3a7713b1edbc | 3036 | * @param __UART8_CLKSOURCE__ specifies the UART8 clock source. |
AnnaBridge | 171:3a7713b1edbc | 3037 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3038 | * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock |
AnnaBridge | 171:3a7713b1edbc | 3039 | * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock |
AnnaBridge | 171:3a7713b1edbc | 3040 | * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock |
AnnaBridge | 171:3a7713b1edbc | 3041 | * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock |
AnnaBridge | 171:3a7713b1edbc | 3042 | */ |
AnnaBridge | 171:3a7713b1edbc | 3043 | #define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 3044 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 3045 | |
AnnaBridge | 171:3a7713b1edbc | 3046 | /** @brief macro to get the UART8 clock source. |
AnnaBridge | 171:3a7713b1edbc | 3047 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3048 | * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock |
AnnaBridge | 171:3a7713b1edbc | 3049 | * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock |
AnnaBridge | 171:3a7713b1edbc | 3050 | * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock |
AnnaBridge | 171:3a7713b1edbc | 3051 | * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock |
AnnaBridge | 171:3a7713b1edbc | 3052 | */ |
AnnaBridge | 171:3a7713b1edbc | 3053 | #define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL))) |
AnnaBridge | 171:3a7713b1edbc | 3054 | |
AnnaBridge | 171:3a7713b1edbc | 3055 | /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). |
AnnaBridge | 171:3a7713b1edbc | 3056 | * |
AnnaBridge | 171:3a7713b1edbc | 3057 | * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. |
AnnaBridge | 171:3a7713b1edbc | 3058 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3059 | * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock |
AnnaBridge | 171:3a7713b1edbc | 3060 | * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock |
AnnaBridge | 171:3a7713b1edbc | 3061 | * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock |
AnnaBridge | 171:3a7713b1edbc | 3062 | * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock |
AnnaBridge | 171:3a7713b1edbc | 3063 | */ |
AnnaBridge | 171:3a7713b1edbc | 3064 | #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 3065 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 3066 | |
AnnaBridge | 171:3a7713b1edbc | 3067 | /** @brief macro to get the LPTIM1 clock source. |
AnnaBridge | 171:3a7713b1edbc | 3068 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3069 | * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock |
AnnaBridge | 171:3a7713b1edbc | 3070 | * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock |
AnnaBridge | 171:3a7713b1edbc | 3071 | * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock |
AnnaBridge | 171:3a7713b1edbc | 3072 | * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock |
AnnaBridge | 171:3a7713b1edbc | 3073 | */ |
AnnaBridge | 171:3a7713b1edbc | 3074 | #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))) |
AnnaBridge | 171:3a7713b1edbc | 3075 | |
AnnaBridge | 171:3a7713b1edbc | 3076 | /** @brief Macro to configure the CEC clock (CECCLK). |
AnnaBridge | 171:3a7713b1edbc | 3077 | * |
AnnaBridge | 171:3a7713b1edbc | 3078 | * @param __CEC_CLKSOURCE__ specifies the CEC clock source. |
AnnaBridge | 171:3a7713b1edbc | 3079 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3080 | * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock |
AnnaBridge | 171:3a7713b1edbc | 3081 | * @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock |
AnnaBridge | 171:3a7713b1edbc | 3082 | */ |
AnnaBridge | 171:3a7713b1edbc | 3083 | #define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 3084 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 3085 | |
AnnaBridge | 171:3a7713b1edbc | 3086 | /** @brief macro to get the CEC clock source. |
AnnaBridge | 171:3a7713b1edbc | 3087 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3088 | * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock |
AnnaBridge | 171:3a7713b1edbc | 3089 | * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock |
AnnaBridge | 171:3a7713b1edbc | 3090 | */ |
AnnaBridge | 171:3a7713b1edbc | 3091 | #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))) |
AnnaBridge | 171:3a7713b1edbc | 3092 | |
AnnaBridge | 171:3a7713b1edbc | 3093 | /** @brief Macro to configure the CLK48 source (CLK48CLK). |
AnnaBridge | 171:3a7713b1edbc | 3094 | * |
AnnaBridge | 171:3a7713b1edbc | 3095 | * @param __CLK48_SOURCE__ specifies the CLK48 clock source. |
AnnaBridge | 171:3a7713b1edbc | 3096 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3097 | * @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source |
AnnaBridge | 171:3a7713b1edbc | 3098 | * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source |
AnnaBridge | 171:3a7713b1edbc | 3099 | */ |
AnnaBridge | 171:3a7713b1edbc | 3100 | #define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 3101 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 3102 | |
AnnaBridge | 171:3a7713b1edbc | 3103 | /** @brief macro to get the CLK48 source. |
AnnaBridge | 171:3a7713b1edbc | 3104 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3105 | * @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source |
AnnaBridge | 171:3a7713b1edbc | 3106 | * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source |
AnnaBridge | 171:3a7713b1edbc | 3107 | */ |
AnnaBridge | 171:3a7713b1edbc | 3108 | #define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))) |
AnnaBridge | 171:3a7713b1edbc | 3109 | |
AnnaBridge | 171:3a7713b1edbc | 3110 | /** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK). |
AnnaBridge | 171:3a7713b1edbc | 3111 | * |
AnnaBridge | 171:3a7713b1edbc | 3112 | * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source. |
AnnaBridge | 171:3a7713b1edbc | 3113 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3114 | * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock |
AnnaBridge | 171:3a7713b1edbc | 3115 | * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock |
AnnaBridge | 171:3a7713b1edbc | 3116 | */ |
AnnaBridge | 171:3a7713b1edbc | 3117 | #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 3118 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 3119 | |
AnnaBridge | 171:3a7713b1edbc | 3120 | /** @brief macro to get the SDMMC1 clock source. |
AnnaBridge | 171:3a7713b1edbc | 3121 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3122 | * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock |
AnnaBridge | 171:3a7713b1edbc | 3123 | * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock |
AnnaBridge | 171:3a7713b1edbc | 3124 | */ |
AnnaBridge | 171:3a7713b1edbc | 3125 | #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL))) |
AnnaBridge | 171:3a7713b1edbc | 3126 | |
AnnaBridge | 171:3a7713b1edbc | 3127 | #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 3128 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 3129 | /** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK). |
AnnaBridge | 171:3a7713b1edbc | 3130 | * @param __SDMMC2_CLKSOURCE__ specifies the SDMMC2 clock source. |
AnnaBridge | 171:3a7713b1edbc | 3131 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3132 | * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock |
AnnaBridge | 171:3a7713b1edbc | 3133 | * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock |
AnnaBridge | 171:3a7713b1edbc | 3134 | */ |
AnnaBridge | 171:3a7713b1edbc | 3135 | #define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 3136 | MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 3137 | |
AnnaBridge | 171:3a7713b1edbc | 3138 | /** @brief macro to get the SDMMC2 clock source. |
AnnaBridge | 171:3a7713b1edbc | 3139 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3140 | * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock |
AnnaBridge | 171:3a7713b1edbc | 3141 | * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock |
AnnaBridge | 171:3a7713b1edbc | 3142 | */ |
AnnaBridge | 171:3a7713b1edbc | 3143 | #define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL))) |
AnnaBridge | 171:3a7713b1edbc | 3144 | #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 3145 | |
AnnaBridge | 171:3a7713b1edbc | 3146 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 3147 | /** @brief Macro to configure the DFSDM1 clock |
AnnaBridge | 171:3a7713b1edbc | 3148 | * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. |
AnnaBridge | 171:3a7713b1edbc | 3149 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3150 | * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM clock |
AnnaBridge | 171:3a7713b1edbc | 3151 | * @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock |
AnnaBridge | 171:3a7713b1edbc | 3152 | */ |
AnnaBridge | 171:3a7713b1edbc | 3153 | #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 3154 | MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 3155 | |
AnnaBridge | 171:3a7713b1edbc | 3156 | /** @brief Macro to get the DFSDM1 clock source. |
AnnaBridge | 171:3a7713b1edbc | 3157 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3158 | * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM1 clock |
AnnaBridge | 171:3a7713b1edbc | 3159 | * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System Clock selected as DFSDM1 clock |
AnnaBridge | 171:3a7713b1edbc | 3160 | */ |
AnnaBridge | 171:3a7713b1edbc | 3161 | #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL))) |
AnnaBridge | 171:3a7713b1edbc | 3162 | |
AnnaBridge | 171:3a7713b1edbc | 3163 | /** @brief Macro to configure the DFSDM1 Audio clock |
AnnaBridge | 171:3a7713b1edbc | 3164 | * @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 Audio clock source. |
AnnaBridge | 171:3a7713b1edbc | 3165 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3166 | * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock |
AnnaBridge | 171:3a7713b1edbc | 3167 | * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock |
AnnaBridge | 171:3a7713b1edbc | 3168 | */ |
AnnaBridge | 171:3a7713b1edbc | 3169 | #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 3170 | MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 3171 | |
AnnaBridge | 171:3a7713b1edbc | 3172 | /** @brief Macro to get the DFSDM1 Audio clock source. |
AnnaBridge | 171:3a7713b1edbc | 3173 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3174 | * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock |
AnnaBridge | 171:3a7713b1edbc | 3175 | * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock |
AnnaBridge | 171:3a7713b1edbc | 3176 | */ |
AnnaBridge | 171:3a7713b1edbc | 3177 | #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL))) |
AnnaBridge | 171:3a7713b1edbc | 3178 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 3179 | |
AnnaBridge | 171:3a7713b1edbc | 3180 | #if defined (STM32F769xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 3181 | /** @brief Macro to configure the DSI clock. |
AnnaBridge | 171:3a7713b1edbc | 3182 | * @param __DSI_CLKSOURCE__ specifies the DSI clock source. |
AnnaBridge | 171:3a7713b1edbc | 3183 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3184 | * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. |
AnnaBridge | 171:3a7713b1edbc | 3185 | * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. |
AnnaBridge | 171:3a7713b1edbc | 3186 | */ |
AnnaBridge | 171:3a7713b1edbc | 3187 | #define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__))) |
AnnaBridge | 171:3a7713b1edbc | 3188 | |
AnnaBridge | 171:3a7713b1edbc | 3189 | /** @brief Macro to Get the DSI clock. |
AnnaBridge | 171:3a7713b1edbc | 3190 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3191 | * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. |
AnnaBridge | 171:3a7713b1edbc | 3192 | * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. |
AnnaBridge | 171:3a7713b1edbc | 3193 | */ |
AnnaBridge | 171:3a7713b1edbc | 3194 | #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL)) |
AnnaBridge | 171:3a7713b1edbc | 3195 | #endif /* STM32F769xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 3196 | /** |
AnnaBridge | 171:3a7713b1edbc | 3197 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3198 | */ |
AnnaBridge | 171:3a7713b1edbc | 3199 | |
AnnaBridge | 171:3a7713b1edbc | 3200 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 3201 | /** @addtogroup RCCEx_Exported_Functions_Group1 |
AnnaBridge | 171:3a7713b1edbc | 3202 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3203 | */ |
AnnaBridge | 171:3a7713b1edbc | 3204 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
AnnaBridge | 171:3a7713b1edbc | 3205 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
AnnaBridge | 171:3a7713b1edbc | 3206 | uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); |
AnnaBridge | 171:3a7713b1edbc | 3207 | HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); |
AnnaBridge | 171:3a7713b1edbc | 3208 | HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); |
AnnaBridge | 171:3a7713b1edbc | 3209 | HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); |
AnnaBridge | 171:3a7713b1edbc | 3210 | HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); |
AnnaBridge | 171:3a7713b1edbc | 3211 | /** |
AnnaBridge | 171:3a7713b1edbc | 3212 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3213 | */ |
AnnaBridge | 171:3a7713b1edbc | 3214 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 3215 | /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros |
AnnaBridge | 171:3a7713b1edbc | 3216 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3217 | */ |
AnnaBridge | 171:3a7713b1edbc | 3218 | /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters |
AnnaBridge | 171:3a7713b1edbc | 3219 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3220 | */ |
AnnaBridge | 171:3a7713b1edbc | 3221 | #if defined(STM32F756xx) || defined(STM32F746xx) |
AnnaBridge | 171:3a7713b1edbc | 3222 | #define IS_RCC_PERIPHCLOCK(SELECTION) \ |
AnnaBridge | 171:3a7713b1edbc | 3223 | ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ |
AnnaBridge | 171:3a7713b1edbc | 3224 | (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ |
AnnaBridge | 171:3a7713b1edbc | 3225 | (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ |
AnnaBridge | 171:3a7713b1edbc | 3226 | (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3227 | (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
AnnaBridge | 171:3a7713b1edbc | 3228 | (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
AnnaBridge | 171:3a7713b1edbc | 3229 | (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
AnnaBridge | 171:3a7713b1edbc | 3230 | (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ |
AnnaBridge | 171:3a7713b1edbc | 3231 | (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ |
AnnaBridge | 171:3a7713b1edbc | 3232 | (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ |
AnnaBridge | 171:3a7713b1edbc | 3233 | (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ |
AnnaBridge | 171:3a7713b1edbc | 3234 | (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3235 | (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
AnnaBridge | 171:3a7713b1edbc | 3236 | (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
AnnaBridge | 171:3a7713b1edbc | 3237 | (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ |
AnnaBridge | 171:3a7713b1edbc | 3238 | (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3239 | (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3240 | (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ |
AnnaBridge | 171:3a7713b1edbc | 3241 | (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ |
AnnaBridge | 171:3a7713b1edbc | 3242 | (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ |
AnnaBridge | 171:3a7713b1edbc | 3243 | (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3244 | (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ |
AnnaBridge | 171:3a7713b1edbc | 3245 | (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) |
AnnaBridge | 171:3a7713b1edbc | 3246 | #elif defined(STM32F745xx) |
AnnaBridge | 171:3a7713b1edbc | 3247 | #define IS_RCC_PERIPHCLOCK(SELECTION) \ |
AnnaBridge | 171:3a7713b1edbc | 3248 | ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ |
AnnaBridge | 171:3a7713b1edbc | 3249 | (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ |
AnnaBridge | 171:3a7713b1edbc | 3250 | (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3251 | (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
AnnaBridge | 171:3a7713b1edbc | 3252 | (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
AnnaBridge | 171:3a7713b1edbc | 3253 | (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
AnnaBridge | 171:3a7713b1edbc | 3254 | (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ |
AnnaBridge | 171:3a7713b1edbc | 3255 | (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ |
AnnaBridge | 171:3a7713b1edbc | 3256 | (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ |
AnnaBridge | 171:3a7713b1edbc | 3257 | (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ |
AnnaBridge | 171:3a7713b1edbc | 3258 | (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3259 | (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
AnnaBridge | 171:3a7713b1edbc | 3260 | (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
AnnaBridge | 171:3a7713b1edbc | 3261 | (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ |
AnnaBridge | 171:3a7713b1edbc | 3262 | (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3263 | (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3264 | (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ |
AnnaBridge | 171:3a7713b1edbc | 3265 | (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ |
AnnaBridge | 171:3a7713b1edbc | 3266 | (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ |
AnnaBridge | 171:3a7713b1edbc | 3267 | (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3268 | (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ |
AnnaBridge | 171:3a7713b1edbc | 3269 | (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) |
AnnaBridge | 171:3a7713b1edbc | 3270 | #elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 3271 | #define IS_RCC_PERIPHCLOCK(SELECTION) \ |
AnnaBridge | 171:3a7713b1edbc | 3272 | ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ |
AnnaBridge | 171:3a7713b1edbc | 3273 | (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ |
AnnaBridge | 171:3a7713b1edbc | 3274 | (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ |
AnnaBridge | 171:3a7713b1edbc | 3275 | (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3276 | (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
AnnaBridge | 171:3a7713b1edbc | 3277 | (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
AnnaBridge | 171:3a7713b1edbc | 3278 | (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
AnnaBridge | 171:3a7713b1edbc | 3279 | (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ |
AnnaBridge | 171:3a7713b1edbc | 3280 | (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ |
AnnaBridge | 171:3a7713b1edbc | 3281 | (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ |
AnnaBridge | 171:3a7713b1edbc | 3282 | (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ |
AnnaBridge | 171:3a7713b1edbc | 3283 | (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3284 | (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
AnnaBridge | 171:3a7713b1edbc | 3285 | (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
AnnaBridge | 171:3a7713b1edbc | 3286 | (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ |
AnnaBridge | 171:3a7713b1edbc | 3287 | (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3288 | (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3289 | (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ |
AnnaBridge | 171:3a7713b1edbc | 3290 | (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ |
AnnaBridge | 171:3a7713b1edbc | 3291 | (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ |
AnnaBridge | 171:3a7713b1edbc | 3292 | (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3293 | (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ |
AnnaBridge | 171:3a7713b1edbc | 3294 | (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3295 | (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ |
AnnaBridge | 171:3a7713b1edbc | 3296 | (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ |
AnnaBridge | 171:3a7713b1edbc | 3297 | (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) |
AnnaBridge | 171:3a7713b1edbc | 3298 | #elif defined (STM32F765xx) |
AnnaBridge | 171:3a7713b1edbc | 3299 | #define IS_RCC_PERIPHCLOCK(SELECTION) \ |
AnnaBridge | 171:3a7713b1edbc | 3300 | ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ |
AnnaBridge | 171:3a7713b1edbc | 3301 | (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ |
AnnaBridge | 171:3a7713b1edbc | 3302 | (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3303 | (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
AnnaBridge | 171:3a7713b1edbc | 3304 | (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
AnnaBridge | 171:3a7713b1edbc | 3305 | (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
AnnaBridge | 171:3a7713b1edbc | 3306 | (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ |
AnnaBridge | 171:3a7713b1edbc | 3307 | (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ |
AnnaBridge | 171:3a7713b1edbc | 3308 | (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ |
AnnaBridge | 171:3a7713b1edbc | 3309 | (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ |
AnnaBridge | 171:3a7713b1edbc | 3310 | (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3311 | (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
AnnaBridge | 171:3a7713b1edbc | 3312 | (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
AnnaBridge | 171:3a7713b1edbc | 3313 | (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ |
AnnaBridge | 171:3a7713b1edbc | 3314 | (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3315 | (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3316 | (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ |
AnnaBridge | 171:3a7713b1edbc | 3317 | (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ |
AnnaBridge | 171:3a7713b1edbc | 3318 | (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ |
AnnaBridge | 171:3a7713b1edbc | 3319 | (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3320 | (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ |
AnnaBridge | 171:3a7713b1edbc | 3321 | (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3322 | (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ |
AnnaBridge | 171:3a7713b1edbc | 3323 | (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ |
AnnaBridge | 171:3a7713b1edbc | 3324 | (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) |
AnnaBridge | 171:3a7713b1edbc | 3325 | #elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) |
AnnaBridge | 171:3a7713b1edbc | 3326 | #define IS_RCC_PERIPHCLOCK(SELECTION) \ |
AnnaBridge | 171:3a7713b1edbc | 3327 | ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ |
AnnaBridge | 171:3a7713b1edbc | 3328 | (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ |
AnnaBridge | 171:3a7713b1edbc | 3329 | (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3330 | (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
AnnaBridge | 171:3a7713b1edbc | 3331 | (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
AnnaBridge | 171:3a7713b1edbc | 3332 | (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
AnnaBridge | 171:3a7713b1edbc | 3333 | (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ |
AnnaBridge | 171:3a7713b1edbc | 3334 | (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ |
AnnaBridge | 171:3a7713b1edbc | 3335 | (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ |
AnnaBridge | 171:3a7713b1edbc | 3336 | (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ |
AnnaBridge | 171:3a7713b1edbc | 3337 | (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3338 | (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
AnnaBridge | 171:3a7713b1edbc | 3339 | (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
AnnaBridge | 171:3a7713b1edbc | 3340 | (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3341 | (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3342 | (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ |
AnnaBridge | 171:3a7713b1edbc | 3343 | (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ |
AnnaBridge | 171:3a7713b1edbc | 3344 | (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3345 | (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ |
AnnaBridge | 171:3a7713b1edbc | 3346 | (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) |
AnnaBridge | 171:3a7713b1edbc | 3347 | #endif /* STM32F746xx || STM32F756xx */ |
AnnaBridge | 171:3a7713b1edbc | 3348 | #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) |
AnnaBridge | 171:3a7713b1edbc | 3349 | #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ |
AnnaBridge | 171:3a7713b1edbc | 3350 | defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 3351 | #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ |
AnnaBridge | 171:3a7713b1edbc | 3352 | ((VALUE) == RCC_PLLI2SP_DIV4) ||\ |
AnnaBridge | 171:3a7713b1edbc | 3353 | ((VALUE) == RCC_PLLI2SP_DIV6) ||\ |
AnnaBridge | 171:3a7713b1edbc | 3354 | ((VALUE) == RCC_PLLI2SP_DIV8)) |
AnnaBridge | 171:3a7713b1edbc | 3355 | #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 3356 | #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) |
AnnaBridge | 171:3a7713b1edbc | 3357 | #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) |
AnnaBridge | 171:3a7713b1edbc | 3358 | |
AnnaBridge | 171:3a7713b1edbc | 3359 | #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) |
AnnaBridge | 171:3a7713b1edbc | 3360 | #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ |
AnnaBridge | 171:3a7713b1edbc | 3361 | ((VALUE) == RCC_PLLSAIP_DIV4) ||\ |
AnnaBridge | 171:3a7713b1edbc | 3362 | ((VALUE) == RCC_PLLSAIP_DIV6) ||\ |
AnnaBridge | 171:3a7713b1edbc | 3363 | ((VALUE) == RCC_PLLSAIP_DIV8)) |
AnnaBridge | 171:3a7713b1edbc | 3364 | #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) |
AnnaBridge | 171:3a7713b1edbc | 3365 | #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) |
AnnaBridge | 171:3a7713b1edbc | 3366 | |
AnnaBridge | 171:3a7713b1edbc | 3367 | #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) |
AnnaBridge | 171:3a7713b1edbc | 3368 | |
AnnaBridge | 171:3a7713b1edbc | 3369 | #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) |
AnnaBridge | 171:3a7713b1edbc | 3370 | |
AnnaBridge | 171:3a7713b1edbc | 3371 | #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\ |
AnnaBridge | 171:3a7713b1edbc | 3372 | ((VALUE) == RCC_PLLSAIDIVR_4) ||\ |
AnnaBridge | 171:3a7713b1edbc | 3373 | ((VALUE) == RCC_PLLSAIDIVR_8) ||\ |
AnnaBridge | 171:3a7713b1edbc | 3374 | ((VALUE) == RCC_PLLSAIDIVR_16)) |
AnnaBridge | 171:3a7713b1edbc | 3375 | #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \ |
AnnaBridge | 171:3a7713b1edbc | 3376 | ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) |
AnnaBridge | 171:3a7713b1edbc | 3377 | |
AnnaBridge | 171:3a7713b1edbc | 3378 | #define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \ |
AnnaBridge | 171:3a7713b1edbc | 3379 | ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48)) |
AnnaBridge | 171:3a7713b1edbc | 3380 | |
AnnaBridge | 171:3a7713b1edbc | 3381 | #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ |
AnnaBridge | 171:3a7713b1edbc | 3382 | ((SOURCE) == RCC_CECCLKSOURCE_LSE)) |
AnnaBridge | 171:3a7713b1edbc | 3383 | #define IS_RCC_USART1CLKSOURCE(SOURCE) \ |
AnnaBridge | 171:3a7713b1edbc | 3384 | (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ |
AnnaBridge | 171:3a7713b1edbc | 3385 | ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ |
AnnaBridge | 171:3a7713b1edbc | 3386 | ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 3387 | ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) |
AnnaBridge | 171:3a7713b1edbc | 3388 | |
AnnaBridge | 171:3a7713b1edbc | 3389 | #define IS_RCC_USART2CLKSOURCE(SOURCE) \ |
AnnaBridge | 171:3a7713b1edbc | 3390 | (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3391 | ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ |
AnnaBridge | 171:3a7713b1edbc | 3392 | ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 3393 | ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) |
AnnaBridge | 171:3a7713b1edbc | 3394 | #define IS_RCC_USART3CLKSOURCE(SOURCE) \ |
AnnaBridge | 171:3a7713b1edbc | 3395 | (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3396 | ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \ |
AnnaBridge | 171:3a7713b1edbc | 3397 | ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 3398 | ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) |
AnnaBridge | 171:3a7713b1edbc | 3399 | |
AnnaBridge | 171:3a7713b1edbc | 3400 | #define IS_RCC_UART4CLKSOURCE(SOURCE) \ |
AnnaBridge | 171:3a7713b1edbc | 3401 | (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3402 | ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \ |
AnnaBridge | 171:3a7713b1edbc | 3403 | ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 3404 | ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) |
AnnaBridge | 171:3a7713b1edbc | 3405 | |
AnnaBridge | 171:3a7713b1edbc | 3406 | #define IS_RCC_UART5CLKSOURCE(SOURCE) \ |
AnnaBridge | 171:3a7713b1edbc | 3407 | (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3408 | ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \ |
AnnaBridge | 171:3a7713b1edbc | 3409 | ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 3410 | ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) |
AnnaBridge | 171:3a7713b1edbc | 3411 | |
AnnaBridge | 171:3a7713b1edbc | 3412 | #define IS_RCC_USART6CLKSOURCE(SOURCE) \ |
AnnaBridge | 171:3a7713b1edbc | 3413 | (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \ |
AnnaBridge | 171:3a7713b1edbc | 3414 | ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \ |
AnnaBridge | 171:3a7713b1edbc | 3415 | ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 3416 | ((SOURCE) == RCC_USART6CLKSOURCE_HSI)) |
AnnaBridge | 171:3a7713b1edbc | 3417 | |
AnnaBridge | 171:3a7713b1edbc | 3418 | #define IS_RCC_UART7CLKSOURCE(SOURCE) \ |
AnnaBridge | 171:3a7713b1edbc | 3419 | (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3420 | ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \ |
AnnaBridge | 171:3a7713b1edbc | 3421 | ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 3422 | ((SOURCE) == RCC_UART7CLKSOURCE_HSI)) |
AnnaBridge | 171:3a7713b1edbc | 3423 | |
AnnaBridge | 171:3a7713b1edbc | 3424 | #define IS_RCC_UART8CLKSOURCE(SOURCE) \ |
AnnaBridge | 171:3a7713b1edbc | 3425 | (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3426 | ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \ |
AnnaBridge | 171:3a7713b1edbc | 3427 | ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 3428 | ((SOURCE) == RCC_UART8CLKSOURCE_HSI)) |
AnnaBridge | 171:3a7713b1edbc | 3429 | #define IS_RCC_I2C1CLKSOURCE(SOURCE) \ |
AnnaBridge | 171:3a7713b1edbc | 3430 | (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3431 | ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ |
AnnaBridge | 171:3a7713b1edbc | 3432 | ((SOURCE) == RCC_I2C1CLKSOURCE_HSI)) |
AnnaBridge | 171:3a7713b1edbc | 3433 | #define IS_RCC_I2C2CLKSOURCE(SOURCE) \ |
AnnaBridge | 171:3a7713b1edbc | 3434 | (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3435 | ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ |
AnnaBridge | 171:3a7713b1edbc | 3436 | ((SOURCE) == RCC_I2C2CLKSOURCE_HSI)) |
AnnaBridge | 171:3a7713b1edbc | 3437 | |
AnnaBridge | 171:3a7713b1edbc | 3438 | #define IS_RCC_I2C3CLKSOURCE(SOURCE) \ |
AnnaBridge | 171:3a7713b1edbc | 3439 | (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3440 | ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ |
AnnaBridge | 171:3a7713b1edbc | 3441 | ((SOURCE) == RCC_I2C3CLKSOURCE_HSI)) |
AnnaBridge | 171:3a7713b1edbc | 3442 | #define IS_RCC_I2C4CLKSOURCE(SOURCE) \ |
AnnaBridge | 171:3a7713b1edbc | 3443 | (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3444 | ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ |
AnnaBridge | 171:3a7713b1edbc | 3445 | ((SOURCE) == RCC_I2C4CLKSOURCE_HSI)) |
AnnaBridge | 171:3a7713b1edbc | 3446 | #define IS_RCC_LPTIM1CLK(SOURCE) \ |
AnnaBridge | 171:3a7713b1edbc | 3447 | (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3448 | ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \ |
AnnaBridge | 171:3a7713b1edbc | 3449 | ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \ |
AnnaBridge | 171:3a7713b1edbc | 3450 | ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) |
AnnaBridge | 171:3a7713b1edbc | 3451 | #define IS_RCC_CLK48SOURCE(SOURCE) \ |
AnnaBridge | 171:3a7713b1edbc | 3452 | (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \ |
AnnaBridge | 171:3a7713b1edbc | 3453 | ((SOURCE) == RCC_CLK48SOURCE_PLL)) |
AnnaBridge | 171:3a7713b1edbc | 3454 | #define IS_RCC_TIMPRES(VALUE) \ |
AnnaBridge | 171:3a7713b1edbc | 3455 | (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \ |
AnnaBridge | 171:3a7713b1edbc | 3456 | ((VALUE) == RCC_TIMPRES_ACTIVATED)) |
AnnaBridge | 171:3a7713b1edbc | 3457 | |
AnnaBridge | 171:3a7713b1edbc | 3458 | #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F745xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 3459 | defined (STM32F746xx) || defined (STM32F756xx) |
AnnaBridge | 171:3a7713b1edbc | 3460 | #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ |
AnnaBridge | 171:3a7713b1edbc | 3461 | ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ |
AnnaBridge | 171:3a7713b1edbc | 3462 | ((SOURCE) == RCC_SAI1CLKSOURCE_PIN)) |
AnnaBridge | 171:3a7713b1edbc | 3463 | #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ |
AnnaBridge | 171:3a7713b1edbc | 3464 | ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ |
AnnaBridge | 171:3a7713b1edbc | 3465 | ((SOURCE) == RCC_SAI2CLKSOURCE_PIN)) |
AnnaBridge | 171:3a7713b1edbc | 3466 | #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F745xx || STM32F746xx || STM32F756xx */ |
AnnaBridge | 171:3a7713b1edbc | 3467 | |
AnnaBridge | 171:3a7713b1edbc | 3468 | #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 3469 | #define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) |
AnnaBridge | 171:3a7713b1edbc | 3470 | |
AnnaBridge | 171:3a7713b1edbc | 3471 | #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ |
AnnaBridge | 171:3a7713b1edbc | 3472 | ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ |
AnnaBridge | 171:3a7713b1edbc | 3473 | ((SOURCE) == RCC_SAI1CLKSOURCE_PIN) || \ |
AnnaBridge | 171:3a7713b1edbc | 3474 | ((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC)) |
AnnaBridge | 171:3a7713b1edbc | 3475 | |
AnnaBridge | 171:3a7713b1edbc | 3476 | #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ |
AnnaBridge | 171:3a7713b1edbc | 3477 | ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ |
AnnaBridge | 171:3a7713b1edbc | 3478 | ((SOURCE) == RCC_SAI2CLKSOURCE_PIN) || \ |
AnnaBridge | 171:3a7713b1edbc | 3479 | ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC)) |
AnnaBridge | 171:3a7713b1edbc | 3480 | |
AnnaBridge | 171:3a7713b1edbc | 3481 | #define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ |
AnnaBridge | 171:3a7713b1edbc | 3482 | ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK)) |
AnnaBridge | 171:3a7713b1edbc | 3483 | |
AnnaBridge | 171:3a7713b1edbc | 3484 | #define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ |
AnnaBridge | 171:3a7713b1edbc | 3485 | ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2)) |
AnnaBridge | 171:3a7713b1edbc | 3486 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 3487 | |
AnnaBridge | 171:3a7713b1edbc | 3488 | #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ |
AnnaBridge | 171:3a7713b1edbc | 3489 | defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 3490 | #define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \ |
AnnaBridge | 171:3a7713b1edbc | 3491 | ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48)) |
AnnaBridge | 171:3a7713b1edbc | 3492 | #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 3493 | |
AnnaBridge | 171:3a7713b1edbc | 3494 | #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) |
AnnaBridge | 171:3a7713b1edbc | 3495 | #define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ |
AnnaBridge | 171:3a7713b1edbc | 3496 | ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) |
AnnaBridge | 171:3a7713b1edbc | 3497 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
AnnaBridge | 171:3a7713b1edbc | 3498 | |
AnnaBridge | 171:3a7713b1edbc | 3499 | /** |
AnnaBridge | 171:3a7713b1edbc | 3500 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3501 | */ |
AnnaBridge | 171:3a7713b1edbc | 3502 | |
AnnaBridge | 171:3a7713b1edbc | 3503 | /** |
AnnaBridge | 171:3a7713b1edbc | 3504 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3505 | */ |
AnnaBridge | 171:3a7713b1edbc | 3506 | |
AnnaBridge | 171:3a7713b1edbc | 3507 | /** |
AnnaBridge | 171:3a7713b1edbc | 3508 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3509 | */ |
AnnaBridge | 171:3a7713b1edbc | 3510 | |
AnnaBridge | 171:3a7713b1edbc | 3511 | /** |
AnnaBridge | 171:3a7713b1edbc | 3512 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3513 | */ |
AnnaBridge | 171:3a7713b1edbc | 3514 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 3515 | } |
AnnaBridge | 171:3a7713b1edbc | 3516 | #endif |
AnnaBridge | 171:3a7713b1edbc | 3517 | |
AnnaBridge | 171:3a7713b1edbc | 3518 | #endif /* __STM32F7xx_HAL_RCC_EX_H */ |
AnnaBridge | 171:3a7713b1edbc | 3519 | |
AnnaBridge | 171:3a7713b1edbc | 3520 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |