The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
mbed 2
This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.
TARGET_NUCLEO_F446RE/TOOLCHAIN_ARM_MICRO/stm32_hal_legacy.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 165:d1b4690b3f8b | 1 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2 | ****************************************************************************** |
AnnaBridge | 165:d1b4690b3f8b | 3 | * @file stm32_hal_legacy.h |
AnnaBridge | 165:d1b4690b3f8b | 4 | * @author MCD Application Team |
AnnaBridge | 165:d1b4690b3f8b | 5 | * @brief This file contains aliases definition for the STM32Cube HAL constants |
AnnaBridge | 165:d1b4690b3f8b | 6 | * macros and functions maintained for legacy purpose. |
AnnaBridge | 165:d1b4690b3f8b | 7 | ****************************************************************************** |
AnnaBridge | 165:d1b4690b3f8b | 8 | * @attention |
AnnaBridge | 165:d1b4690b3f8b | 9 | * |
AnnaBridge | 165:d1b4690b3f8b | 10 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
AnnaBridge | 165:d1b4690b3f8b | 11 | * |
AnnaBridge | 165:d1b4690b3f8b | 12 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 165:d1b4690b3f8b | 13 | * are permitted provided that the following conditions are met: |
AnnaBridge | 165:d1b4690b3f8b | 14 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 165:d1b4690b3f8b | 15 | * this list of conditions and the following disclaimer. |
AnnaBridge | 165:d1b4690b3f8b | 16 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 165:d1b4690b3f8b | 17 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 165:d1b4690b3f8b | 18 | * and/or other materials provided with the distribution. |
AnnaBridge | 165:d1b4690b3f8b | 19 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 165:d1b4690b3f8b | 20 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 165:d1b4690b3f8b | 21 | * without specific prior written permission. |
AnnaBridge | 165:d1b4690b3f8b | 22 | * |
AnnaBridge | 165:d1b4690b3f8b | 23 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 165:d1b4690b3f8b | 24 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 165:d1b4690b3f8b | 25 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 165:d1b4690b3f8b | 26 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 165:d1b4690b3f8b | 27 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 165:d1b4690b3f8b | 28 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 165:d1b4690b3f8b | 29 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 165:d1b4690b3f8b | 30 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 165:d1b4690b3f8b | 31 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 165:d1b4690b3f8b | 32 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 165:d1b4690b3f8b | 33 | * |
AnnaBridge | 165:d1b4690b3f8b | 34 | ****************************************************************************** |
AnnaBridge | 165:d1b4690b3f8b | 35 | */ |
AnnaBridge | 165:d1b4690b3f8b | 36 | |
AnnaBridge | 165:d1b4690b3f8b | 37 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 165:d1b4690b3f8b | 38 | #ifndef __STM32_HAL_LEGACY |
AnnaBridge | 165:d1b4690b3f8b | 39 | #define __STM32_HAL_LEGACY |
AnnaBridge | 165:d1b4690b3f8b | 40 | |
AnnaBridge | 165:d1b4690b3f8b | 41 | #ifdef __cplusplus |
AnnaBridge | 165:d1b4690b3f8b | 42 | extern "C" { |
AnnaBridge | 165:d1b4690b3f8b | 43 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 44 | |
AnnaBridge | 165:d1b4690b3f8b | 45 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 165:d1b4690b3f8b | 46 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 165:d1b4690b3f8b | 47 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 165:d1b4690b3f8b | 48 | |
AnnaBridge | 165:d1b4690b3f8b | 49 | /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 50 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 51 | */ |
AnnaBridge | 165:d1b4690b3f8b | 52 | #define AES_FLAG_RDERR CRYP_FLAG_RDERR |
AnnaBridge | 165:d1b4690b3f8b | 53 | #define AES_FLAG_WRERR CRYP_FLAG_WRERR |
AnnaBridge | 165:d1b4690b3f8b | 54 | #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF |
AnnaBridge | 165:d1b4690b3f8b | 55 | #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR |
AnnaBridge | 165:d1b4690b3f8b | 56 | #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR |
AnnaBridge | 165:d1b4690b3f8b | 57 | |
AnnaBridge | 165:d1b4690b3f8b | 58 | /** |
AnnaBridge | 165:d1b4690b3f8b | 59 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 60 | */ |
AnnaBridge | 165:d1b4690b3f8b | 61 | |
AnnaBridge | 165:d1b4690b3f8b | 62 | /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 63 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 64 | */ |
AnnaBridge | 165:d1b4690b3f8b | 65 | #define ADC_RESOLUTION12b ADC_RESOLUTION_12B |
AnnaBridge | 165:d1b4690b3f8b | 66 | #define ADC_RESOLUTION10b ADC_RESOLUTION_10B |
AnnaBridge | 165:d1b4690b3f8b | 67 | #define ADC_RESOLUTION8b ADC_RESOLUTION_8B |
AnnaBridge | 165:d1b4690b3f8b | 68 | #define ADC_RESOLUTION6b ADC_RESOLUTION_6B |
AnnaBridge | 165:d1b4690b3f8b | 69 | #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN |
AnnaBridge | 165:d1b4690b3f8b | 70 | #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED |
AnnaBridge | 165:d1b4690b3f8b | 71 | #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV |
AnnaBridge | 165:d1b4690b3f8b | 72 | #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV |
AnnaBridge | 165:d1b4690b3f8b | 73 | #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV |
AnnaBridge | 165:d1b4690b3f8b | 74 | #define REGULAR_GROUP ADC_REGULAR_GROUP |
AnnaBridge | 165:d1b4690b3f8b | 75 | #define INJECTED_GROUP ADC_INJECTED_GROUP |
AnnaBridge | 165:d1b4690b3f8b | 76 | #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP |
AnnaBridge | 165:d1b4690b3f8b | 77 | #define AWD_EVENT ADC_AWD_EVENT |
AnnaBridge | 165:d1b4690b3f8b | 78 | #define AWD1_EVENT ADC_AWD1_EVENT |
AnnaBridge | 165:d1b4690b3f8b | 79 | #define AWD2_EVENT ADC_AWD2_EVENT |
AnnaBridge | 165:d1b4690b3f8b | 80 | #define AWD3_EVENT ADC_AWD3_EVENT |
AnnaBridge | 165:d1b4690b3f8b | 81 | #define OVR_EVENT ADC_OVR_EVENT |
AnnaBridge | 165:d1b4690b3f8b | 82 | #define JQOVF_EVENT ADC_JQOVF_EVENT |
AnnaBridge | 165:d1b4690b3f8b | 83 | #define ALL_CHANNELS ADC_ALL_CHANNELS |
AnnaBridge | 165:d1b4690b3f8b | 84 | #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS |
AnnaBridge | 165:d1b4690b3f8b | 85 | #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS |
AnnaBridge | 165:d1b4690b3f8b | 86 | #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR |
AnnaBridge | 165:d1b4690b3f8b | 87 | #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT |
AnnaBridge | 165:d1b4690b3f8b | 88 | #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 |
AnnaBridge | 165:d1b4690b3f8b | 89 | #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 |
AnnaBridge | 165:d1b4690b3f8b | 90 | #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 |
AnnaBridge | 165:d1b4690b3f8b | 91 | #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 |
AnnaBridge | 165:d1b4690b3f8b | 92 | #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 |
AnnaBridge | 165:d1b4690b3f8b | 93 | #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO |
AnnaBridge | 165:d1b4690b3f8b | 94 | #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 |
AnnaBridge | 165:d1b4690b3f8b | 95 | #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO |
AnnaBridge | 165:d1b4690b3f8b | 96 | #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 |
AnnaBridge | 165:d1b4690b3f8b | 97 | #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO |
AnnaBridge | 165:d1b4690b3f8b | 98 | #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 |
AnnaBridge | 165:d1b4690b3f8b | 99 | #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 |
AnnaBridge | 165:d1b4690b3f8b | 100 | #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE |
AnnaBridge | 165:d1b4690b3f8b | 101 | #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING |
AnnaBridge | 165:d1b4690b3f8b | 102 | #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING |
AnnaBridge | 165:d1b4690b3f8b | 103 | #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING |
AnnaBridge | 165:d1b4690b3f8b | 104 | #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 |
AnnaBridge | 165:d1b4690b3f8b | 105 | |
AnnaBridge | 165:d1b4690b3f8b | 106 | #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY |
AnnaBridge | 165:d1b4690b3f8b | 107 | #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY |
AnnaBridge | 165:d1b4690b3f8b | 108 | #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC |
AnnaBridge | 165:d1b4690b3f8b | 109 | #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC |
AnnaBridge | 165:d1b4690b3f8b | 110 | #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL |
AnnaBridge | 165:d1b4690b3f8b | 111 | #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL |
AnnaBridge | 165:d1b4690b3f8b | 112 | #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 |
AnnaBridge | 165:d1b4690b3f8b | 113 | /** |
AnnaBridge | 165:d1b4690b3f8b | 114 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 115 | */ |
AnnaBridge | 165:d1b4690b3f8b | 116 | |
AnnaBridge | 165:d1b4690b3f8b | 117 | /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 118 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 119 | */ |
AnnaBridge | 165:d1b4690b3f8b | 120 | |
AnnaBridge | 165:d1b4690b3f8b | 121 | #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG |
AnnaBridge | 165:d1b4690b3f8b | 122 | |
AnnaBridge | 165:d1b4690b3f8b | 123 | /** |
AnnaBridge | 165:d1b4690b3f8b | 124 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 125 | */ |
AnnaBridge | 165:d1b4690b3f8b | 126 | |
AnnaBridge | 165:d1b4690b3f8b | 127 | /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 128 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 129 | */ |
AnnaBridge | 165:d1b4690b3f8b | 130 | #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 131 | #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 132 | #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 |
AnnaBridge | 165:d1b4690b3f8b | 133 | #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 |
AnnaBridge | 165:d1b4690b3f8b | 134 | #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 |
AnnaBridge | 165:d1b4690b3f8b | 135 | #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 |
AnnaBridge | 165:d1b4690b3f8b | 136 | #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 |
AnnaBridge | 165:d1b4690b3f8b | 137 | #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 |
AnnaBridge | 165:d1b4690b3f8b | 138 | #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 |
AnnaBridge | 165:d1b4690b3f8b | 139 | #if defined(STM32L0) |
AnnaBridge | 165:d1b4690b3f8b | 140 | #define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ |
AnnaBridge | 165:d1b4690b3f8b | 141 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 142 | #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR |
AnnaBridge | 165:d1b4690b3f8b | 143 | #if defined(STM32F373xC) || defined(STM32F378xx) |
AnnaBridge | 165:d1b4690b3f8b | 144 | #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 |
AnnaBridge | 165:d1b4690b3f8b | 145 | #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR |
AnnaBridge | 165:d1b4690b3f8b | 146 | #endif /* STM32F373xC || STM32F378xx */ |
AnnaBridge | 165:d1b4690b3f8b | 147 | |
AnnaBridge | 165:d1b4690b3f8b | 148 | #if defined(STM32L0) || defined(STM32L4) |
AnnaBridge | 165:d1b4690b3f8b | 149 | #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON |
AnnaBridge | 165:d1b4690b3f8b | 150 | |
AnnaBridge | 165:d1b4690b3f8b | 151 | #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 |
AnnaBridge | 165:d1b4690b3f8b | 152 | #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 |
AnnaBridge | 165:d1b4690b3f8b | 153 | #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 |
AnnaBridge | 165:d1b4690b3f8b | 154 | #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 |
AnnaBridge | 165:d1b4690b3f8b | 155 | #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 |
AnnaBridge | 165:d1b4690b3f8b | 156 | #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 |
AnnaBridge | 165:d1b4690b3f8b | 157 | |
AnnaBridge | 165:d1b4690b3f8b | 158 | #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT |
AnnaBridge | 165:d1b4690b3f8b | 159 | #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT |
AnnaBridge | 165:d1b4690b3f8b | 160 | #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT |
AnnaBridge | 165:d1b4690b3f8b | 161 | #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT |
AnnaBridge | 165:d1b4690b3f8b | 162 | #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 |
AnnaBridge | 165:d1b4690b3f8b | 163 | #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 |
AnnaBridge | 165:d1b4690b3f8b | 164 | #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 |
AnnaBridge | 165:d1b4690b3f8b | 165 | #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 |
AnnaBridge | 165:d1b4690b3f8b | 166 | #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 |
AnnaBridge | 165:d1b4690b3f8b | 167 | #if defined(STM32L0) |
AnnaBridge | 165:d1b4690b3f8b | 168 | /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ |
AnnaBridge | 165:d1b4690b3f8b | 169 | /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ |
AnnaBridge | 165:d1b4690b3f8b | 170 | /* to the second dedicated IO (only for COMP2). */ |
AnnaBridge | 165:d1b4690b3f8b | 171 | #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 |
AnnaBridge | 165:d1b4690b3f8b | 172 | #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 |
AnnaBridge | 165:d1b4690b3f8b | 173 | #else |
AnnaBridge | 165:d1b4690b3f8b | 174 | #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 |
AnnaBridge | 165:d1b4690b3f8b | 175 | #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 |
AnnaBridge | 165:d1b4690b3f8b | 176 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 177 | #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 |
AnnaBridge | 165:d1b4690b3f8b | 178 | #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 |
AnnaBridge | 165:d1b4690b3f8b | 179 | |
AnnaBridge | 165:d1b4690b3f8b | 180 | #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW |
AnnaBridge | 165:d1b4690b3f8b | 181 | #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH |
AnnaBridge | 165:d1b4690b3f8b | 182 | |
AnnaBridge | 165:d1b4690b3f8b | 183 | /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ |
AnnaBridge | 165:d1b4690b3f8b | 184 | /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ |
AnnaBridge | 165:d1b4690b3f8b | 185 | #if defined(COMP_CSR_LOCK) |
AnnaBridge | 165:d1b4690b3f8b | 186 | #define COMP_FLAG_LOCK COMP_CSR_LOCK |
AnnaBridge | 165:d1b4690b3f8b | 187 | #elif defined(COMP_CSR_COMP1LOCK) |
AnnaBridge | 165:d1b4690b3f8b | 188 | #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK |
AnnaBridge | 165:d1b4690b3f8b | 189 | #elif defined(COMP_CSR_COMPxLOCK) |
AnnaBridge | 165:d1b4690b3f8b | 190 | #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK |
AnnaBridge | 165:d1b4690b3f8b | 191 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 192 | |
AnnaBridge | 165:d1b4690b3f8b | 193 | #if defined(STM32L4) |
AnnaBridge | 165:d1b4690b3f8b | 194 | #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 |
AnnaBridge | 165:d1b4690b3f8b | 195 | #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 |
AnnaBridge | 165:d1b4690b3f8b | 196 | #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 |
AnnaBridge | 165:d1b4690b3f8b | 197 | #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 |
AnnaBridge | 165:d1b4690b3f8b | 198 | #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 |
AnnaBridge | 165:d1b4690b3f8b | 199 | #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 |
AnnaBridge | 165:d1b4690b3f8b | 200 | #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE |
AnnaBridge | 165:d1b4690b3f8b | 201 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 202 | |
AnnaBridge | 165:d1b4690b3f8b | 203 | #if defined(STM32L0) |
AnnaBridge | 165:d1b4690b3f8b | 204 | #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED |
AnnaBridge | 165:d1b4690b3f8b | 205 | #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER |
AnnaBridge | 165:d1b4690b3f8b | 206 | #else |
AnnaBridge | 165:d1b4690b3f8b | 207 | #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED |
AnnaBridge | 165:d1b4690b3f8b | 208 | #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED |
AnnaBridge | 165:d1b4690b3f8b | 209 | #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER |
AnnaBridge | 165:d1b4690b3f8b | 210 | #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER |
AnnaBridge | 165:d1b4690b3f8b | 211 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 212 | |
AnnaBridge | 165:d1b4690b3f8b | 213 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 214 | /** |
AnnaBridge | 165:d1b4690b3f8b | 215 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 216 | */ |
AnnaBridge | 165:d1b4690b3f8b | 217 | |
AnnaBridge | 165:d1b4690b3f8b | 218 | /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 219 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 220 | */ |
AnnaBridge | 165:d1b4690b3f8b | 221 | #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig |
AnnaBridge | 165:d1b4690b3f8b | 222 | /** |
AnnaBridge | 165:d1b4690b3f8b | 223 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 224 | */ |
AnnaBridge | 165:d1b4690b3f8b | 225 | |
AnnaBridge | 165:d1b4690b3f8b | 226 | /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 227 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 228 | */ |
AnnaBridge | 165:d1b4690b3f8b | 229 | |
AnnaBridge | 165:d1b4690b3f8b | 230 | #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 231 | #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 232 | |
AnnaBridge | 165:d1b4690b3f8b | 233 | /** |
AnnaBridge | 165:d1b4690b3f8b | 234 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 235 | */ |
AnnaBridge | 165:d1b4690b3f8b | 236 | |
AnnaBridge | 165:d1b4690b3f8b | 237 | /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 238 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 239 | */ |
AnnaBridge | 165:d1b4690b3f8b | 240 | |
AnnaBridge | 165:d1b4690b3f8b | 241 | #define DAC1_CHANNEL_1 DAC_CHANNEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 242 | #define DAC1_CHANNEL_2 DAC_CHANNEL_2 |
AnnaBridge | 165:d1b4690b3f8b | 243 | #define DAC2_CHANNEL_1 DAC_CHANNEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 244 | #define DAC_WAVE_NONE 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 245 | #define DAC_WAVE_NOISE DAC_CR_WAVE1_0 |
AnnaBridge | 165:d1b4690b3f8b | 246 | #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 |
AnnaBridge | 165:d1b4690b3f8b | 247 | #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE |
AnnaBridge | 165:d1b4690b3f8b | 248 | #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE |
AnnaBridge | 165:d1b4690b3f8b | 249 | #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE |
AnnaBridge | 165:d1b4690b3f8b | 250 | |
AnnaBridge | 165:d1b4690b3f8b | 251 | /** |
AnnaBridge | 165:d1b4690b3f8b | 252 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 253 | */ |
AnnaBridge | 165:d1b4690b3f8b | 254 | |
AnnaBridge | 165:d1b4690b3f8b | 255 | /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 256 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 257 | */ |
AnnaBridge | 165:d1b4690b3f8b | 258 | #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 |
AnnaBridge | 165:d1b4690b3f8b | 259 | #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 |
AnnaBridge | 165:d1b4690b3f8b | 260 | #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 |
AnnaBridge | 165:d1b4690b3f8b | 261 | #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 |
AnnaBridge | 165:d1b4690b3f8b | 262 | #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 |
AnnaBridge | 165:d1b4690b3f8b | 263 | #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 |
AnnaBridge | 165:d1b4690b3f8b | 264 | #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 |
AnnaBridge | 165:d1b4690b3f8b | 265 | #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 |
AnnaBridge | 165:d1b4690b3f8b | 266 | #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 |
AnnaBridge | 165:d1b4690b3f8b | 267 | #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 |
AnnaBridge | 165:d1b4690b3f8b | 268 | #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 |
AnnaBridge | 165:d1b4690b3f8b | 269 | #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 |
AnnaBridge | 165:d1b4690b3f8b | 270 | #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 |
AnnaBridge | 165:d1b4690b3f8b | 271 | #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 |
AnnaBridge | 165:d1b4690b3f8b | 272 | |
AnnaBridge | 165:d1b4690b3f8b | 273 | #define IS_HAL_REMAPDMA IS_DMA_REMAP |
AnnaBridge | 165:d1b4690b3f8b | 274 | #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 275 | #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 276 | |
AnnaBridge | 165:d1b4690b3f8b | 277 | |
AnnaBridge | 165:d1b4690b3f8b | 278 | |
AnnaBridge | 165:d1b4690b3f8b | 279 | /** |
AnnaBridge | 165:d1b4690b3f8b | 280 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 281 | */ |
AnnaBridge | 165:d1b4690b3f8b | 282 | |
AnnaBridge | 165:d1b4690b3f8b | 283 | /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 284 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 285 | */ |
AnnaBridge | 165:d1b4690b3f8b | 286 | |
AnnaBridge | 165:d1b4690b3f8b | 287 | #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE |
AnnaBridge | 165:d1b4690b3f8b | 288 | #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD |
AnnaBridge | 165:d1b4690b3f8b | 289 | #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD |
AnnaBridge | 165:d1b4690b3f8b | 290 | #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD |
AnnaBridge | 165:d1b4690b3f8b | 291 | #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS |
AnnaBridge | 165:d1b4690b3f8b | 292 | #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES |
AnnaBridge | 165:d1b4690b3f8b | 293 | #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES |
AnnaBridge | 165:d1b4690b3f8b | 294 | #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE |
AnnaBridge | 165:d1b4690b3f8b | 295 | #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 296 | #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 297 | #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE |
AnnaBridge | 165:d1b4690b3f8b | 298 | #define OBEX_PCROP OPTIONBYTE_PCROP |
AnnaBridge | 165:d1b4690b3f8b | 299 | #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG |
AnnaBridge | 165:d1b4690b3f8b | 300 | #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 301 | #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 302 | #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE |
AnnaBridge | 165:d1b4690b3f8b | 303 | #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD |
AnnaBridge | 165:d1b4690b3f8b | 304 | #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD |
AnnaBridge | 165:d1b4690b3f8b | 305 | #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE |
AnnaBridge | 165:d1b4690b3f8b | 306 | #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD |
AnnaBridge | 165:d1b4690b3f8b | 307 | #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD |
AnnaBridge | 165:d1b4690b3f8b | 308 | #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE |
AnnaBridge | 165:d1b4690b3f8b | 309 | #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD |
AnnaBridge | 165:d1b4690b3f8b | 310 | #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD |
AnnaBridge | 165:d1b4690b3f8b | 311 | #define PAGESIZE FLASH_PAGE_SIZE |
AnnaBridge | 165:d1b4690b3f8b | 312 | #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE |
AnnaBridge | 165:d1b4690b3f8b | 313 | #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD |
AnnaBridge | 165:d1b4690b3f8b | 314 | #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD |
AnnaBridge | 165:d1b4690b3f8b | 315 | #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 |
AnnaBridge | 165:d1b4690b3f8b | 316 | #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 |
AnnaBridge | 165:d1b4690b3f8b | 317 | #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 |
AnnaBridge | 165:d1b4690b3f8b | 318 | #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 |
AnnaBridge | 165:d1b4690b3f8b | 319 | #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST |
AnnaBridge | 165:d1b4690b3f8b | 320 | #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST |
AnnaBridge | 165:d1b4690b3f8b | 321 | #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA |
AnnaBridge | 165:d1b4690b3f8b | 322 | #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB |
AnnaBridge | 165:d1b4690b3f8b | 323 | #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA |
AnnaBridge | 165:d1b4690b3f8b | 324 | #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB |
AnnaBridge | 165:d1b4690b3f8b | 325 | #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE |
AnnaBridge | 165:d1b4690b3f8b | 326 | #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN |
AnnaBridge | 165:d1b4690b3f8b | 327 | #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE |
AnnaBridge | 165:d1b4690b3f8b | 328 | #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN |
AnnaBridge | 165:d1b4690b3f8b | 329 | #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE |
AnnaBridge | 165:d1b4690b3f8b | 330 | #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD |
AnnaBridge | 165:d1b4690b3f8b | 331 | #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG |
AnnaBridge | 165:d1b4690b3f8b | 332 | #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS |
AnnaBridge | 165:d1b4690b3f8b | 333 | #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP |
AnnaBridge | 165:d1b4690b3f8b | 334 | #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV |
AnnaBridge | 165:d1b4690b3f8b | 335 | #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR |
AnnaBridge | 165:d1b4690b3f8b | 336 | #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG |
AnnaBridge | 165:d1b4690b3f8b | 337 | #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION |
AnnaBridge | 165:d1b4690b3f8b | 338 | #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA |
AnnaBridge | 165:d1b4690b3f8b | 339 | #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE |
AnnaBridge | 165:d1b4690b3f8b | 340 | #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE |
AnnaBridge | 165:d1b4690b3f8b | 341 | #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS |
AnnaBridge | 165:d1b4690b3f8b | 342 | #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS |
AnnaBridge | 165:d1b4690b3f8b | 343 | #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST |
AnnaBridge | 165:d1b4690b3f8b | 344 | #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR |
AnnaBridge | 165:d1b4690b3f8b | 345 | #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO |
AnnaBridge | 165:d1b4690b3f8b | 346 | #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION |
AnnaBridge | 165:d1b4690b3f8b | 347 | #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS |
AnnaBridge | 165:d1b4690b3f8b | 348 | #define OB_WDG_SW OB_IWDG_SW |
AnnaBridge | 165:d1b4690b3f8b | 349 | #define OB_WDG_HW OB_IWDG_HW |
AnnaBridge | 165:d1b4690b3f8b | 350 | #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET |
AnnaBridge | 165:d1b4690b3f8b | 351 | #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET |
AnnaBridge | 165:d1b4690b3f8b | 352 | #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET |
AnnaBridge | 165:d1b4690b3f8b | 353 | #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET |
AnnaBridge | 165:d1b4690b3f8b | 354 | #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR |
AnnaBridge | 165:d1b4690b3f8b | 355 | #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 |
AnnaBridge | 165:d1b4690b3f8b | 356 | #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 357 | #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 |
AnnaBridge | 165:d1b4690b3f8b | 358 | |
AnnaBridge | 165:d1b4690b3f8b | 359 | /** |
AnnaBridge | 165:d1b4690b3f8b | 360 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 361 | */ |
AnnaBridge | 165:d1b4690b3f8b | 362 | |
AnnaBridge | 165:d1b4690b3f8b | 363 | /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 364 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 365 | */ |
AnnaBridge | 165:d1b4690b3f8b | 366 | |
AnnaBridge | 165:d1b4690b3f8b | 367 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 |
AnnaBridge | 165:d1b4690b3f8b | 368 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 |
AnnaBridge | 165:d1b4690b3f8b | 369 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 |
AnnaBridge | 165:d1b4690b3f8b | 370 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 |
AnnaBridge | 165:d1b4690b3f8b | 371 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 |
AnnaBridge | 165:d1b4690b3f8b | 372 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 |
AnnaBridge | 165:d1b4690b3f8b | 373 | #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 |
AnnaBridge | 165:d1b4690b3f8b | 374 | #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 |
AnnaBridge | 165:d1b4690b3f8b | 375 | #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 |
AnnaBridge | 165:d1b4690b3f8b | 376 | /** |
AnnaBridge | 165:d1b4690b3f8b | 377 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 378 | */ |
AnnaBridge | 165:d1b4690b3f8b | 379 | |
AnnaBridge | 165:d1b4690b3f8b | 380 | |
AnnaBridge | 165:d1b4690b3f8b | 381 | /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose |
AnnaBridge | 165:d1b4690b3f8b | 382 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 383 | */ |
AnnaBridge | 165:d1b4690b3f8b | 384 | #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) |
AnnaBridge | 165:d1b4690b3f8b | 385 | #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 386 | #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 387 | #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 |
AnnaBridge | 165:d1b4690b3f8b | 388 | #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 |
AnnaBridge | 165:d1b4690b3f8b | 389 | #else |
AnnaBridge | 165:d1b4690b3f8b | 390 | #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 391 | #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 392 | #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 |
AnnaBridge | 165:d1b4690b3f8b | 393 | #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 |
AnnaBridge | 165:d1b4690b3f8b | 394 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 395 | /** |
AnnaBridge | 165:d1b4690b3f8b | 396 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 397 | */ |
AnnaBridge | 165:d1b4690b3f8b | 398 | |
AnnaBridge | 165:d1b4690b3f8b | 399 | /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 400 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 401 | */ |
AnnaBridge | 165:d1b4690b3f8b | 402 | |
AnnaBridge | 165:d1b4690b3f8b | 403 | #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef |
AnnaBridge | 165:d1b4690b3f8b | 404 | #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef |
AnnaBridge | 165:d1b4690b3f8b | 405 | /** |
AnnaBridge | 165:d1b4690b3f8b | 406 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 407 | */ |
AnnaBridge | 165:d1b4690b3f8b | 408 | |
AnnaBridge | 165:d1b4690b3f8b | 409 | /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 410 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 411 | */ |
AnnaBridge | 165:d1b4690b3f8b | 412 | #define GET_GPIO_SOURCE GPIO_GET_INDEX |
AnnaBridge | 165:d1b4690b3f8b | 413 | #define GET_GPIO_INDEX GPIO_GET_INDEX |
AnnaBridge | 165:d1b4690b3f8b | 414 | |
AnnaBridge | 165:d1b4690b3f8b | 415 | #if defined(STM32F4) |
AnnaBridge | 165:d1b4690b3f8b | 416 | #define GPIO_AF12_SDMMC GPIO_AF12_SDIO |
AnnaBridge | 165:d1b4690b3f8b | 417 | #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO |
AnnaBridge | 165:d1b4690b3f8b | 418 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 419 | |
AnnaBridge | 165:d1b4690b3f8b | 420 | #if defined(STM32F7) |
AnnaBridge | 165:d1b4690b3f8b | 421 | #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 |
AnnaBridge | 165:d1b4690b3f8b | 422 | #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 |
AnnaBridge | 165:d1b4690b3f8b | 423 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 424 | |
AnnaBridge | 165:d1b4690b3f8b | 425 | #if defined(STM32L4) |
AnnaBridge | 165:d1b4690b3f8b | 426 | #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 |
AnnaBridge | 165:d1b4690b3f8b | 427 | #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 |
AnnaBridge | 165:d1b4690b3f8b | 428 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 429 | |
AnnaBridge | 165:d1b4690b3f8b | 430 | #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 |
AnnaBridge | 165:d1b4690b3f8b | 431 | #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 |
AnnaBridge | 165:d1b4690b3f8b | 432 | #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 |
AnnaBridge | 165:d1b4690b3f8b | 433 | |
AnnaBridge | 165:d1b4690b3f8b | 434 | #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) |
AnnaBridge | 165:d1b4690b3f8b | 435 | #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW |
AnnaBridge | 165:d1b4690b3f8b | 436 | #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM |
AnnaBridge | 165:d1b4690b3f8b | 437 | #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH |
AnnaBridge | 165:d1b4690b3f8b | 438 | #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH |
AnnaBridge | 165:d1b4690b3f8b | 439 | #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */ |
AnnaBridge | 165:d1b4690b3f8b | 440 | |
AnnaBridge | 165:d1b4690b3f8b | 441 | #if defined(STM32L1) |
AnnaBridge | 165:d1b4690b3f8b | 442 | #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW |
AnnaBridge | 165:d1b4690b3f8b | 443 | #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM |
AnnaBridge | 165:d1b4690b3f8b | 444 | #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH |
AnnaBridge | 165:d1b4690b3f8b | 445 | #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH |
AnnaBridge | 165:d1b4690b3f8b | 446 | #endif /* STM32L1 */ |
AnnaBridge | 165:d1b4690b3f8b | 447 | |
AnnaBridge | 165:d1b4690b3f8b | 448 | #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) |
AnnaBridge | 165:d1b4690b3f8b | 449 | #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW |
AnnaBridge | 165:d1b4690b3f8b | 450 | #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM |
AnnaBridge | 165:d1b4690b3f8b | 451 | #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH |
AnnaBridge | 165:d1b4690b3f8b | 452 | #endif /* STM32F0 || STM32F3 || STM32F1 */ |
AnnaBridge | 165:d1b4690b3f8b | 453 | |
AnnaBridge | 165:d1b4690b3f8b | 454 | #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 |
AnnaBridge | 165:d1b4690b3f8b | 455 | /** |
AnnaBridge | 165:d1b4690b3f8b | 456 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 457 | */ |
AnnaBridge | 165:d1b4690b3f8b | 458 | |
AnnaBridge | 165:d1b4690b3f8b | 459 | /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 460 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 461 | */ |
AnnaBridge | 165:d1b4690b3f8b | 462 | |
AnnaBridge | 165:d1b4690b3f8b | 463 | #if defined(STM32H7) |
AnnaBridge | 165:d1b4690b3f8b | 464 | #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 465 | #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 466 | #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 467 | #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 468 | #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 469 | #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 470 | |
AnnaBridge | 165:d1b4690b3f8b | 471 | #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 |
AnnaBridge | 165:d1b4690b3f8b | 472 | #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 |
AnnaBridge | 165:d1b4690b3f8b | 473 | |
AnnaBridge | 165:d1b4690b3f8b | 474 | #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX |
AnnaBridge | 165:d1b4690b3f8b | 475 | #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX |
AnnaBridge | 165:d1b4690b3f8b | 476 | |
AnnaBridge | 165:d1b4690b3f8b | 477 | #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT |
AnnaBridge | 165:d1b4690b3f8b | 478 | #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT |
AnnaBridge | 165:d1b4690b3f8b | 479 | #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT |
AnnaBridge | 165:d1b4690b3f8b | 480 | #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT |
AnnaBridge | 165:d1b4690b3f8b | 481 | #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT |
AnnaBridge | 165:d1b4690b3f8b | 482 | #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT |
AnnaBridge | 165:d1b4690b3f8b | 483 | #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 |
AnnaBridge | 165:d1b4690b3f8b | 484 | #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO |
AnnaBridge | 165:d1b4690b3f8b | 485 | |
AnnaBridge | 165:d1b4690b3f8b | 486 | #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT |
AnnaBridge | 165:d1b4690b3f8b | 487 | #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT |
AnnaBridge | 165:d1b4690b3f8b | 488 | #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT |
AnnaBridge | 165:d1b4690b3f8b | 489 | #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT |
AnnaBridge | 165:d1b4690b3f8b | 490 | #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT |
AnnaBridge | 165:d1b4690b3f8b | 491 | #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT |
AnnaBridge | 165:d1b4690b3f8b | 492 | #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT |
AnnaBridge | 165:d1b4690b3f8b | 493 | #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP |
AnnaBridge | 165:d1b4690b3f8b | 494 | #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP |
AnnaBridge | 165:d1b4690b3f8b | 495 | #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP |
AnnaBridge | 165:d1b4690b3f8b | 496 | #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT |
AnnaBridge | 165:d1b4690b3f8b | 497 | #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP |
AnnaBridge | 165:d1b4690b3f8b | 498 | #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT |
AnnaBridge | 165:d1b4690b3f8b | 499 | #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP |
AnnaBridge | 165:d1b4690b3f8b | 500 | #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP |
AnnaBridge | 165:d1b4690b3f8b | 501 | #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP |
AnnaBridge | 165:d1b4690b3f8b | 502 | #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP |
AnnaBridge | 165:d1b4690b3f8b | 503 | #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT |
AnnaBridge | 165:d1b4690b3f8b | 504 | #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT |
AnnaBridge | 165:d1b4690b3f8b | 505 | #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP |
AnnaBridge | 165:d1b4690b3f8b | 506 | #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 |
AnnaBridge | 165:d1b4690b3f8b | 507 | #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 |
AnnaBridge | 165:d1b4690b3f8b | 508 | #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT |
AnnaBridge | 165:d1b4690b3f8b | 509 | #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT |
AnnaBridge | 165:d1b4690b3f8b | 510 | #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT |
AnnaBridge | 165:d1b4690b3f8b | 511 | #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT |
AnnaBridge | 165:d1b4690b3f8b | 512 | #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT |
AnnaBridge | 165:d1b4690b3f8b | 513 | #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT |
AnnaBridge | 165:d1b4690b3f8b | 514 | #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT |
AnnaBridge | 165:d1b4690b3f8b | 515 | #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT |
AnnaBridge | 165:d1b4690b3f8b | 516 | |
AnnaBridge | 165:d1b4690b3f8b | 517 | #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT |
AnnaBridge | 165:d1b4690b3f8b | 518 | #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING |
AnnaBridge | 165:d1b4690b3f8b | 519 | #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING |
AnnaBridge | 165:d1b4690b3f8b | 520 | #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING |
AnnaBridge | 165:d1b4690b3f8b | 521 | |
AnnaBridge | 165:d1b4690b3f8b | 522 | |
AnnaBridge | 165:d1b4690b3f8b | 523 | #endif /* STM32H7 */ |
AnnaBridge | 165:d1b4690b3f8b | 524 | |
AnnaBridge | 165:d1b4690b3f8b | 525 | |
AnnaBridge | 165:d1b4690b3f8b | 526 | /** |
AnnaBridge | 165:d1b4690b3f8b | 527 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 528 | */ |
AnnaBridge | 165:d1b4690b3f8b | 529 | |
AnnaBridge | 165:d1b4690b3f8b | 530 | |
AnnaBridge | 165:d1b4690b3f8b | 531 | /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 532 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 533 | */ |
AnnaBridge | 165:d1b4690b3f8b | 534 | #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 535 | #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 |
AnnaBridge | 165:d1b4690b3f8b | 536 | #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 |
AnnaBridge | 165:d1b4690b3f8b | 537 | #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 |
AnnaBridge | 165:d1b4690b3f8b | 538 | #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 |
AnnaBridge | 165:d1b4690b3f8b | 539 | #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 |
AnnaBridge | 165:d1b4690b3f8b | 540 | #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 |
AnnaBridge | 165:d1b4690b3f8b | 541 | #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 |
AnnaBridge | 165:d1b4690b3f8b | 542 | #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 |
AnnaBridge | 165:d1b4690b3f8b | 543 | |
AnnaBridge | 165:d1b4690b3f8b | 544 | #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER |
AnnaBridge | 165:d1b4690b3f8b | 545 | #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER |
AnnaBridge | 165:d1b4690b3f8b | 546 | #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD |
AnnaBridge | 165:d1b4690b3f8b | 547 | #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD |
AnnaBridge | 165:d1b4690b3f8b | 548 | #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER |
AnnaBridge | 165:d1b4690b3f8b | 549 | #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER |
AnnaBridge | 165:d1b4690b3f8b | 550 | #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE |
AnnaBridge | 165:d1b4690b3f8b | 551 | #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE |
AnnaBridge | 165:d1b4690b3f8b | 552 | /** |
AnnaBridge | 165:d1b4690b3f8b | 553 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 554 | */ |
AnnaBridge | 165:d1b4690b3f8b | 555 | |
AnnaBridge | 165:d1b4690b3f8b | 556 | /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 557 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 558 | */ |
AnnaBridge | 165:d1b4690b3f8b | 559 | #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 560 | #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 561 | #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 562 | #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 563 | #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 564 | #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 565 | #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 566 | #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 567 | #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) |
AnnaBridge | 165:d1b4690b3f8b | 568 | #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX |
AnnaBridge | 165:d1b4690b3f8b | 569 | #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX |
AnnaBridge | 165:d1b4690b3f8b | 570 | #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX |
AnnaBridge | 165:d1b4690b3f8b | 571 | #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX |
AnnaBridge | 165:d1b4690b3f8b | 572 | #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX |
AnnaBridge | 165:d1b4690b3f8b | 573 | #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX |
AnnaBridge | 165:d1b4690b3f8b | 574 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 575 | /** |
AnnaBridge | 165:d1b4690b3f8b | 576 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 577 | */ |
AnnaBridge | 165:d1b4690b3f8b | 578 | |
AnnaBridge | 165:d1b4690b3f8b | 579 | /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 580 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 581 | */ |
AnnaBridge | 165:d1b4690b3f8b | 582 | #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 583 | #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 584 | |
AnnaBridge | 165:d1b4690b3f8b | 585 | /** |
AnnaBridge | 165:d1b4690b3f8b | 586 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 587 | */ |
AnnaBridge | 165:d1b4690b3f8b | 588 | |
AnnaBridge | 165:d1b4690b3f8b | 589 | /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 590 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 591 | */ |
AnnaBridge | 165:d1b4690b3f8b | 592 | #define KR_KEY_RELOAD IWDG_KEY_RELOAD |
AnnaBridge | 165:d1b4690b3f8b | 593 | #define KR_KEY_ENABLE IWDG_KEY_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 594 | #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 595 | #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 596 | /** |
AnnaBridge | 165:d1b4690b3f8b | 597 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 598 | */ |
AnnaBridge | 165:d1b4690b3f8b | 599 | |
AnnaBridge | 165:d1b4690b3f8b | 600 | /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 601 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 602 | */ |
AnnaBridge | 165:d1b4690b3f8b | 603 | |
AnnaBridge | 165:d1b4690b3f8b | 604 | #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION |
AnnaBridge | 165:d1b4690b3f8b | 605 | #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS |
AnnaBridge | 165:d1b4690b3f8b | 606 | #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS |
AnnaBridge | 165:d1b4690b3f8b | 607 | #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS |
AnnaBridge | 165:d1b4690b3f8b | 608 | |
AnnaBridge | 165:d1b4690b3f8b | 609 | #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING |
AnnaBridge | 165:d1b4690b3f8b | 610 | #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING |
AnnaBridge | 165:d1b4690b3f8b | 611 | #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING |
AnnaBridge | 165:d1b4690b3f8b | 612 | |
AnnaBridge | 165:d1b4690b3f8b | 613 | #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION |
AnnaBridge | 165:d1b4690b3f8b | 614 | #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS |
AnnaBridge | 165:d1b4690b3f8b | 615 | #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS |
AnnaBridge | 165:d1b4690b3f8b | 616 | #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS |
AnnaBridge | 165:d1b4690b3f8b | 617 | |
AnnaBridge | 165:d1b4690b3f8b | 618 | /* The following 3 definition have also been present in a temporary version of lptim.h */ |
AnnaBridge | 165:d1b4690b3f8b | 619 | /* They need to be renamed also to the right name, just in case */ |
AnnaBridge | 165:d1b4690b3f8b | 620 | #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS |
AnnaBridge | 165:d1b4690b3f8b | 621 | #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS |
AnnaBridge | 165:d1b4690b3f8b | 622 | #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS |
AnnaBridge | 165:d1b4690b3f8b | 623 | |
AnnaBridge | 165:d1b4690b3f8b | 624 | /** |
AnnaBridge | 165:d1b4690b3f8b | 625 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 626 | */ |
AnnaBridge | 165:d1b4690b3f8b | 627 | |
AnnaBridge | 165:d1b4690b3f8b | 628 | /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 629 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 630 | */ |
AnnaBridge | 165:d1b4690b3f8b | 631 | #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b |
AnnaBridge | 165:d1b4690b3f8b | 632 | #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b |
AnnaBridge | 165:d1b4690b3f8b | 633 | #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b |
AnnaBridge | 165:d1b4690b3f8b | 634 | #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b |
AnnaBridge | 165:d1b4690b3f8b | 635 | |
AnnaBridge | 165:d1b4690b3f8b | 636 | #define NAND_AddressTypedef NAND_AddressTypeDef |
AnnaBridge | 165:d1b4690b3f8b | 637 | |
AnnaBridge | 165:d1b4690b3f8b | 638 | #define __ARRAY_ADDRESS ARRAY_ADDRESS |
AnnaBridge | 165:d1b4690b3f8b | 639 | #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE |
AnnaBridge | 165:d1b4690b3f8b | 640 | #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE |
AnnaBridge | 165:d1b4690b3f8b | 641 | #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE |
AnnaBridge | 165:d1b4690b3f8b | 642 | #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE |
AnnaBridge | 165:d1b4690b3f8b | 643 | /** |
AnnaBridge | 165:d1b4690b3f8b | 644 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 645 | */ |
AnnaBridge | 165:d1b4690b3f8b | 646 | |
AnnaBridge | 165:d1b4690b3f8b | 647 | /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 648 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 649 | */ |
AnnaBridge | 165:d1b4690b3f8b | 650 | #define NOR_StatusTypedef HAL_NOR_StatusTypeDef |
AnnaBridge | 165:d1b4690b3f8b | 651 | #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS |
AnnaBridge | 165:d1b4690b3f8b | 652 | #define NOR_ONGOING HAL_NOR_STATUS_ONGOING |
AnnaBridge | 165:d1b4690b3f8b | 653 | #define NOR_ERROR HAL_NOR_STATUS_ERROR |
AnnaBridge | 165:d1b4690b3f8b | 654 | #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT |
AnnaBridge | 165:d1b4690b3f8b | 655 | |
AnnaBridge | 165:d1b4690b3f8b | 656 | #define __NOR_WRITE NOR_WRITE |
AnnaBridge | 165:d1b4690b3f8b | 657 | #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT |
AnnaBridge | 165:d1b4690b3f8b | 658 | /** |
AnnaBridge | 165:d1b4690b3f8b | 659 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 660 | */ |
AnnaBridge | 165:d1b4690b3f8b | 661 | |
AnnaBridge | 165:d1b4690b3f8b | 662 | /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 663 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 664 | */ |
AnnaBridge | 165:d1b4690b3f8b | 665 | |
AnnaBridge | 165:d1b4690b3f8b | 666 | #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 |
AnnaBridge | 165:d1b4690b3f8b | 667 | #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 |
AnnaBridge | 165:d1b4690b3f8b | 668 | #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 |
AnnaBridge | 165:d1b4690b3f8b | 669 | #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 |
AnnaBridge | 165:d1b4690b3f8b | 670 | |
AnnaBridge | 165:d1b4690b3f8b | 671 | #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 |
AnnaBridge | 165:d1b4690b3f8b | 672 | #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 |
AnnaBridge | 165:d1b4690b3f8b | 673 | #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 |
AnnaBridge | 165:d1b4690b3f8b | 674 | #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 |
AnnaBridge | 165:d1b4690b3f8b | 675 | |
AnnaBridge | 165:d1b4690b3f8b | 676 | #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 |
AnnaBridge | 165:d1b4690b3f8b | 677 | #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 |
AnnaBridge | 165:d1b4690b3f8b | 678 | |
AnnaBridge | 165:d1b4690b3f8b | 679 | #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 |
AnnaBridge | 165:d1b4690b3f8b | 680 | #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 |
AnnaBridge | 165:d1b4690b3f8b | 681 | |
AnnaBridge | 165:d1b4690b3f8b | 682 | #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 |
AnnaBridge | 165:d1b4690b3f8b | 683 | #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 |
AnnaBridge | 165:d1b4690b3f8b | 684 | |
AnnaBridge | 165:d1b4690b3f8b | 685 | #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 |
AnnaBridge | 165:d1b4690b3f8b | 686 | |
AnnaBridge | 165:d1b4690b3f8b | 687 | #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO |
AnnaBridge | 165:d1b4690b3f8b | 688 | #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 |
AnnaBridge | 165:d1b4690b3f8b | 689 | #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 |
AnnaBridge | 165:d1b4690b3f8b | 690 | |
AnnaBridge | 165:d1b4690b3f8b | 691 | /** |
AnnaBridge | 165:d1b4690b3f8b | 692 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 693 | */ |
AnnaBridge | 165:d1b4690b3f8b | 694 | |
AnnaBridge | 165:d1b4690b3f8b | 695 | /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 696 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 697 | */ |
AnnaBridge | 165:d1b4690b3f8b | 698 | #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS |
AnnaBridge | 165:d1b4690b3f8b | 699 | #if defined(STM32F7) |
AnnaBridge | 165:d1b4690b3f8b | 700 | #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL |
AnnaBridge | 165:d1b4690b3f8b | 701 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 702 | /** |
AnnaBridge | 165:d1b4690b3f8b | 703 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 704 | */ |
AnnaBridge | 165:d1b4690b3f8b | 705 | |
AnnaBridge | 165:d1b4690b3f8b | 706 | /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 707 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 708 | */ |
AnnaBridge | 165:d1b4690b3f8b | 709 | |
AnnaBridge | 165:d1b4690b3f8b | 710 | /* Compact Flash-ATA registers description */ |
AnnaBridge | 165:d1b4690b3f8b | 711 | #define CF_DATA ATA_DATA |
AnnaBridge | 165:d1b4690b3f8b | 712 | #define CF_SECTOR_COUNT ATA_SECTOR_COUNT |
AnnaBridge | 165:d1b4690b3f8b | 713 | #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 714 | #define CF_CYLINDER_LOW ATA_CYLINDER_LOW |
AnnaBridge | 165:d1b4690b3f8b | 715 | #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH |
AnnaBridge | 165:d1b4690b3f8b | 716 | #define CF_CARD_HEAD ATA_CARD_HEAD |
AnnaBridge | 165:d1b4690b3f8b | 717 | #define CF_STATUS_CMD ATA_STATUS_CMD |
AnnaBridge | 165:d1b4690b3f8b | 718 | #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE |
AnnaBridge | 165:d1b4690b3f8b | 719 | #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA |
AnnaBridge | 165:d1b4690b3f8b | 720 | |
AnnaBridge | 165:d1b4690b3f8b | 721 | /* Compact Flash-ATA commands */ |
AnnaBridge | 165:d1b4690b3f8b | 722 | #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD |
AnnaBridge | 165:d1b4690b3f8b | 723 | #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD |
AnnaBridge | 165:d1b4690b3f8b | 724 | #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD |
AnnaBridge | 165:d1b4690b3f8b | 725 | #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD |
AnnaBridge | 165:d1b4690b3f8b | 726 | |
AnnaBridge | 165:d1b4690b3f8b | 727 | #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef |
AnnaBridge | 165:d1b4690b3f8b | 728 | #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS |
AnnaBridge | 165:d1b4690b3f8b | 729 | #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING |
AnnaBridge | 165:d1b4690b3f8b | 730 | #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR |
AnnaBridge | 165:d1b4690b3f8b | 731 | #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT |
AnnaBridge | 165:d1b4690b3f8b | 732 | /** |
AnnaBridge | 165:d1b4690b3f8b | 733 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 734 | */ |
AnnaBridge | 165:d1b4690b3f8b | 735 | |
AnnaBridge | 165:d1b4690b3f8b | 736 | /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 737 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 738 | */ |
AnnaBridge | 165:d1b4690b3f8b | 739 | |
AnnaBridge | 165:d1b4690b3f8b | 740 | #define FORMAT_BIN RTC_FORMAT_BIN |
AnnaBridge | 165:d1b4690b3f8b | 741 | #define FORMAT_BCD RTC_FORMAT_BCD |
AnnaBridge | 165:d1b4690b3f8b | 742 | |
AnnaBridge | 165:d1b4690b3f8b | 743 | #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE |
AnnaBridge | 165:d1b4690b3f8b | 744 | #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 745 | #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 746 | #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 747 | |
AnnaBridge | 165:d1b4690b3f8b | 748 | #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 749 | #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 750 | #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 751 | #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT |
AnnaBridge | 165:d1b4690b3f8b | 752 | #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT |
AnnaBridge | 165:d1b4690b3f8b | 753 | |
AnnaBridge | 165:d1b4690b3f8b | 754 | #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT |
AnnaBridge | 165:d1b4690b3f8b | 755 | #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 |
AnnaBridge | 165:d1b4690b3f8b | 756 | #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 |
AnnaBridge | 165:d1b4690b3f8b | 757 | #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 |
AnnaBridge | 165:d1b4690b3f8b | 758 | |
AnnaBridge | 165:d1b4690b3f8b | 759 | #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE |
AnnaBridge | 165:d1b4690b3f8b | 760 | #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 |
AnnaBridge | 165:d1b4690b3f8b | 761 | #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 |
AnnaBridge | 165:d1b4690b3f8b | 762 | |
AnnaBridge | 165:d1b4690b3f8b | 763 | #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT |
AnnaBridge | 165:d1b4690b3f8b | 764 | #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 |
AnnaBridge | 165:d1b4690b3f8b | 765 | #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 |
AnnaBridge | 165:d1b4690b3f8b | 766 | |
AnnaBridge | 165:d1b4690b3f8b | 767 | /** |
AnnaBridge | 165:d1b4690b3f8b | 768 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 769 | */ |
AnnaBridge | 165:d1b4690b3f8b | 770 | |
AnnaBridge | 165:d1b4690b3f8b | 771 | |
AnnaBridge | 165:d1b4690b3f8b | 772 | /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 773 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 774 | */ |
AnnaBridge | 165:d1b4690b3f8b | 775 | #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 776 | #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 777 | |
AnnaBridge | 165:d1b4690b3f8b | 778 | #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 779 | #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 780 | #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 781 | #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 782 | |
AnnaBridge | 165:d1b4690b3f8b | 783 | #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 784 | #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 785 | |
AnnaBridge | 165:d1b4690b3f8b | 786 | #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 787 | #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 788 | /** |
AnnaBridge | 165:d1b4690b3f8b | 789 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 790 | */ |
AnnaBridge | 165:d1b4690b3f8b | 791 | |
AnnaBridge | 165:d1b4690b3f8b | 792 | |
AnnaBridge | 165:d1b4690b3f8b | 793 | /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 794 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 795 | */ |
AnnaBridge | 165:d1b4690b3f8b | 796 | #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 797 | #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 798 | #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 799 | #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 800 | #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 801 | #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 802 | #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 803 | #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 804 | #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 805 | #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 806 | #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN |
AnnaBridge | 165:d1b4690b3f8b | 807 | /** |
AnnaBridge | 165:d1b4690b3f8b | 808 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 809 | */ |
AnnaBridge | 165:d1b4690b3f8b | 810 | |
AnnaBridge | 165:d1b4690b3f8b | 811 | /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 812 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 813 | */ |
AnnaBridge | 165:d1b4690b3f8b | 814 | #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 815 | #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 816 | |
AnnaBridge | 165:d1b4690b3f8b | 817 | #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 818 | #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 819 | |
AnnaBridge | 165:d1b4690b3f8b | 820 | #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 821 | #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 822 | |
AnnaBridge | 165:d1b4690b3f8b | 823 | /** |
AnnaBridge | 165:d1b4690b3f8b | 824 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 825 | */ |
AnnaBridge | 165:d1b4690b3f8b | 826 | |
AnnaBridge | 165:d1b4690b3f8b | 827 | /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 828 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 829 | */ |
AnnaBridge | 165:d1b4690b3f8b | 830 | #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK |
AnnaBridge | 165:d1b4690b3f8b | 831 | #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK |
AnnaBridge | 165:d1b4690b3f8b | 832 | |
AnnaBridge | 165:d1b4690b3f8b | 833 | #define TIM_DMABase_CR1 TIM_DMABASE_CR1 |
AnnaBridge | 165:d1b4690b3f8b | 834 | #define TIM_DMABase_CR2 TIM_DMABASE_CR2 |
AnnaBridge | 165:d1b4690b3f8b | 835 | #define TIM_DMABase_SMCR TIM_DMABASE_SMCR |
AnnaBridge | 165:d1b4690b3f8b | 836 | #define TIM_DMABase_DIER TIM_DMABASE_DIER |
AnnaBridge | 165:d1b4690b3f8b | 837 | #define TIM_DMABase_SR TIM_DMABASE_SR |
AnnaBridge | 165:d1b4690b3f8b | 838 | #define TIM_DMABase_EGR TIM_DMABASE_EGR |
AnnaBridge | 165:d1b4690b3f8b | 839 | #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 |
AnnaBridge | 165:d1b4690b3f8b | 840 | #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 |
AnnaBridge | 165:d1b4690b3f8b | 841 | #define TIM_DMABase_CCER TIM_DMABASE_CCER |
AnnaBridge | 165:d1b4690b3f8b | 842 | #define TIM_DMABase_CNT TIM_DMABASE_CNT |
AnnaBridge | 165:d1b4690b3f8b | 843 | #define TIM_DMABase_PSC TIM_DMABASE_PSC |
AnnaBridge | 165:d1b4690b3f8b | 844 | #define TIM_DMABase_ARR TIM_DMABASE_ARR |
AnnaBridge | 165:d1b4690b3f8b | 845 | #define TIM_DMABase_RCR TIM_DMABASE_RCR |
AnnaBridge | 165:d1b4690b3f8b | 846 | #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 |
AnnaBridge | 165:d1b4690b3f8b | 847 | #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 |
AnnaBridge | 165:d1b4690b3f8b | 848 | #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 |
AnnaBridge | 165:d1b4690b3f8b | 849 | #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 |
AnnaBridge | 165:d1b4690b3f8b | 850 | #define TIM_DMABase_BDTR TIM_DMABASE_BDTR |
AnnaBridge | 165:d1b4690b3f8b | 851 | #define TIM_DMABase_DCR TIM_DMABASE_DCR |
AnnaBridge | 165:d1b4690b3f8b | 852 | #define TIM_DMABase_DMAR TIM_DMABASE_DMAR |
AnnaBridge | 165:d1b4690b3f8b | 853 | #define TIM_DMABase_OR1 TIM_DMABASE_OR1 |
AnnaBridge | 165:d1b4690b3f8b | 854 | #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 |
AnnaBridge | 165:d1b4690b3f8b | 855 | #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 |
AnnaBridge | 165:d1b4690b3f8b | 856 | #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 |
AnnaBridge | 165:d1b4690b3f8b | 857 | #define TIM_DMABase_OR2 TIM_DMABASE_OR2 |
AnnaBridge | 165:d1b4690b3f8b | 858 | #define TIM_DMABase_OR3 TIM_DMABASE_OR3 |
AnnaBridge | 165:d1b4690b3f8b | 859 | #define TIM_DMABase_OR TIM_DMABASE_OR |
AnnaBridge | 165:d1b4690b3f8b | 860 | |
AnnaBridge | 165:d1b4690b3f8b | 861 | #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE |
AnnaBridge | 165:d1b4690b3f8b | 862 | #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 |
AnnaBridge | 165:d1b4690b3f8b | 863 | #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 |
AnnaBridge | 165:d1b4690b3f8b | 864 | #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 |
AnnaBridge | 165:d1b4690b3f8b | 865 | #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 |
AnnaBridge | 165:d1b4690b3f8b | 866 | #define TIM_EventSource_COM TIM_EVENTSOURCE_COM |
AnnaBridge | 165:d1b4690b3f8b | 867 | #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER |
AnnaBridge | 165:d1b4690b3f8b | 868 | #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK |
AnnaBridge | 165:d1b4690b3f8b | 869 | #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 |
AnnaBridge | 165:d1b4690b3f8b | 870 | |
AnnaBridge | 165:d1b4690b3f8b | 871 | #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER |
AnnaBridge | 165:d1b4690b3f8b | 872 | #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS |
AnnaBridge | 165:d1b4690b3f8b | 873 | #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS |
AnnaBridge | 165:d1b4690b3f8b | 874 | #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS |
AnnaBridge | 165:d1b4690b3f8b | 875 | #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS |
AnnaBridge | 165:d1b4690b3f8b | 876 | #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS |
AnnaBridge | 165:d1b4690b3f8b | 877 | #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS |
AnnaBridge | 165:d1b4690b3f8b | 878 | #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS |
AnnaBridge | 165:d1b4690b3f8b | 879 | #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS |
AnnaBridge | 165:d1b4690b3f8b | 880 | #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS |
AnnaBridge | 165:d1b4690b3f8b | 881 | #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS |
AnnaBridge | 165:d1b4690b3f8b | 882 | #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS |
AnnaBridge | 165:d1b4690b3f8b | 883 | #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS |
AnnaBridge | 165:d1b4690b3f8b | 884 | #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS |
AnnaBridge | 165:d1b4690b3f8b | 885 | #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS |
AnnaBridge | 165:d1b4690b3f8b | 886 | #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS |
AnnaBridge | 165:d1b4690b3f8b | 887 | #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS |
AnnaBridge | 165:d1b4690b3f8b | 888 | #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS |
AnnaBridge | 165:d1b4690b3f8b | 889 | |
AnnaBridge | 165:d1b4690b3f8b | 890 | /** |
AnnaBridge | 165:d1b4690b3f8b | 891 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 892 | */ |
AnnaBridge | 165:d1b4690b3f8b | 893 | |
AnnaBridge | 165:d1b4690b3f8b | 894 | /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 895 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 896 | */ |
AnnaBridge | 165:d1b4690b3f8b | 897 | #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING |
AnnaBridge | 165:d1b4690b3f8b | 898 | #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING |
AnnaBridge | 165:d1b4690b3f8b | 899 | /** |
AnnaBridge | 165:d1b4690b3f8b | 900 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 901 | */ |
AnnaBridge | 165:d1b4690b3f8b | 902 | |
AnnaBridge | 165:d1b4690b3f8b | 903 | /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 904 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 905 | */ |
AnnaBridge | 165:d1b4690b3f8b | 906 | #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 907 | #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 908 | #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 909 | #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 910 | |
AnnaBridge | 165:d1b4690b3f8b | 911 | #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 912 | #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 913 | |
AnnaBridge | 165:d1b4690b3f8b | 914 | #define __DIV_SAMPLING16 UART_DIV_SAMPLING16 |
AnnaBridge | 165:d1b4690b3f8b | 915 | #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 |
AnnaBridge | 165:d1b4690b3f8b | 916 | #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 |
AnnaBridge | 165:d1b4690b3f8b | 917 | #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 |
AnnaBridge | 165:d1b4690b3f8b | 918 | |
AnnaBridge | 165:d1b4690b3f8b | 919 | #define __DIV_SAMPLING8 UART_DIV_SAMPLING8 |
AnnaBridge | 165:d1b4690b3f8b | 920 | #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 |
AnnaBridge | 165:d1b4690b3f8b | 921 | #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 |
AnnaBridge | 165:d1b4690b3f8b | 922 | #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 |
AnnaBridge | 165:d1b4690b3f8b | 923 | |
AnnaBridge | 165:d1b4690b3f8b | 924 | #define __DIV_LPUART UART_DIV_LPUART |
AnnaBridge | 165:d1b4690b3f8b | 925 | |
AnnaBridge | 165:d1b4690b3f8b | 926 | #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE |
AnnaBridge | 165:d1b4690b3f8b | 927 | #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK |
AnnaBridge | 165:d1b4690b3f8b | 928 | |
AnnaBridge | 165:d1b4690b3f8b | 929 | /** |
AnnaBridge | 165:d1b4690b3f8b | 930 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 931 | */ |
AnnaBridge | 165:d1b4690b3f8b | 932 | |
AnnaBridge | 165:d1b4690b3f8b | 933 | |
AnnaBridge | 165:d1b4690b3f8b | 934 | /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 935 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 936 | */ |
AnnaBridge | 165:d1b4690b3f8b | 937 | |
AnnaBridge | 165:d1b4690b3f8b | 938 | #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 939 | #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 940 | |
AnnaBridge | 165:d1b4690b3f8b | 941 | #define USARTNACK_ENABLED USART_NACK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 942 | #define USARTNACK_DISABLED USART_NACK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 943 | /** |
AnnaBridge | 165:d1b4690b3f8b | 944 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 945 | */ |
AnnaBridge | 165:d1b4690b3f8b | 946 | |
AnnaBridge | 165:d1b4690b3f8b | 947 | /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 948 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 949 | */ |
AnnaBridge | 165:d1b4690b3f8b | 950 | #define CFR_BASE WWDG_CFR_BASE |
AnnaBridge | 165:d1b4690b3f8b | 951 | |
AnnaBridge | 165:d1b4690b3f8b | 952 | /** |
AnnaBridge | 165:d1b4690b3f8b | 953 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 954 | */ |
AnnaBridge | 165:d1b4690b3f8b | 955 | |
AnnaBridge | 165:d1b4690b3f8b | 956 | /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 957 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 958 | */ |
AnnaBridge | 165:d1b4690b3f8b | 959 | #define CAN_FilterFIFO0 CAN_FILTER_FIFO0 |
AnnaBridge | 165:d1b4690b3f8b | 960 | #define CAN_FilterFIFO1 CAN_FILTER_FIFO1 |
AnnaBridge | 165:d1b4690b3f8b | 961 | #define CAN_IT_RQCP0 CAN_IT_TME |
AnnaBridge | 165:d1b4690b3f8b | 962 | #define CAN_IT_RQCP1 CAN_IT_TME |
AnnaBridge | 165:d1b4690b3f8b | 963 | #define CAN_IT_RQCP2 CAN_IT_TME |
AnnaBridge | 165:d1b4690b3f8b | 964 | #define INAK_TIMEOUT CAN_TIMEOUT_VALUE |
AnnaBridge | 165:d1b4690b3f8b | 965 | #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE |
AnnaBridge | 165:d1b4690b3f8b | 966 | #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) |
AnnaBridge | 165:d1b4690b3f8b | 967 | #define CAN_TXSTATUS_OK ((uint8_t)0x01U) |
AnnaBridge | 165:d1b4690b3f8b | 968 | #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) |
AnnaBridge | 165:d1b4690b3f8b | 969 | |
AnnaBridge | 165:d1b4690b3f8b | 970 | /** |
AnnaBridge | 165:d1b4690b3f8b | 971 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 972 | */ |
AnnaBridge | 165:d1b4690b3f8b | 973 | |
AnnaBridge | 165:d1b4690b3f8b | 974 | /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 975 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 976 | */ |
AnnaBridge | 165:d1b4690b3f8b | 977 | |
AnnaBridge | 165:d1b4690b3f8b | 978 | #define VLAN_TAG ETH_VLAN_TAG |
AnnaBridge | 165:d1b4690b3f8b | 979 | #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD |
AnnaBridge | 165:d1b4690b3f8b | 980 | #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD |
AnnaBridge | 165:d1b4690b3f8b | 981 | #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD |
AnnaBridge | 165:d1b4690b3f8b | 982 | #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK |
AnnaBridge | 165:d1b4690b3f8b | 983 | #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK |
AnnaBridge | 165:d1b4690b3f8b | 984 | #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK |
AnnaBridge | 165:d1b4690b3f8b | 985 | #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK |
AnnaBridge | 165:d1b4690b3f8b | 986 | |
AnnaBridge | 165:d1b4690b3f8b | 987 | #define ETH_MMCCR 0x00000100U |
AnnaBridge | 165:d1b4690b3f8b | 988 | #define ETH_MMCRIR 0x00000104U |
AnnaBridge | 165:d1b4690b3f8b | 989 | #define ETH_MMCTIR 0x00000108U |
AnnaBridge | 165:d1b4690b3f8b | 990 | #define ETH_MMCRIMR 0x0000010CU |
AnnaBridge | 165:d1b4690b3f8b | 991 | #define ETH_MMCTIMR 0x00000110U |
AnnaBridge | 165:d1b4690b3f8b | 992 | #define ETH_MMCTGFSCCR 0x0000014CU |
AnnaBridge | 165:d1b4690b3f8b | 993 | #define ETH_MMCTGFMSCCR 0x00000150U |
AnnaBridge | 165:d1b4690b3f8b | 994 | #define ETH_MMCTGFCR 0x00000168U |
AnnaBridge | 165:d1b4690b3f8b | 995 | #define ETH_MMCRFCECR 0x00000194U |
AnnaBridge | 165:d1b4690b3f8b | 996 | #define ETH_MMCRFAECR 0x00000198U |
AnnaBridge | 165:d1b4690b3f8b | 997 | #define ETH_MMCRGUFCR 0x000001C4U |
AnnaBridge | 165:d1b4690b3f8b | 998 | |
AnnaBridge | 165:d1b4690b3f8b | 999 | #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ |
AnnaBridge | 165:d1b4690b3f8b | 1000 | #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ |
AnnaBridge | 165:d1b4690b3f8b | 1001 | #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ |
AnnaBridge | 165:d1b4690b3f8b | 1002 | #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ |
AnnaBridge | 165:d1b4690b3f8b | 1003 | #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ |
AnnaBridge | 165:d1b4690b3f8b | 1004 | #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ |
AnnaBridge | 165:d1b4690b3f8b | 1005 | #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ |
AnnaBridge | 165:d1b4690b3f8b | 1006 | #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ |
AnnaBridge | 165:d1b4690b3f8b | 1007 | #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ |
AnnaBridge | 165:d1b4690b3f8b | 1008 | #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ |
AnnaBridge | 165:d1b4690b3f8b | 1009 | #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ |
AnnaBridge | 165:d1b4690b3f8b | 1010 | #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ |
AnnaBridge | 165:d1b4690b3f8b | 1011 | #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ |
AnnaBridge | 165:d1b4690b3f8b | 1012 | #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ |
AnnaBridge | 165:d1b4690b3f8b | 1013 | #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ |
AnnaBridge | 165:d1b4690b3f8b | 1014 | #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ |
AnnaBridge | 165:d1b4690b3f8b | 1015 | #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ |
AnnaBridge | 165:d1b4690b3f8b | 1016 | #if defined(STM32F1) |
AnnaBridge | 165:d1b4690b3f8b | 1017 | #else |
AnnaBridge | 165:d1b4690b3f8b | 1018 | #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ |
AnnaBridge | 165:d1b4690b3f8b | 1019 | #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ |
AnnaBridge | 165:d1b4690b3f8b | 1020 | #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ |
AnnaBridge | 165:d1b4690b3f8b | 1021 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 1022 | #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ |
AnnaBridge | 165:d1b4690b3f8b | 1023 | #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ |
AnnaBridge | 165:d1b4690b3f8b | 1024 | #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ |
AnnaBridge | 165:d1b4690b3f8b | 1025 | #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ |
AnnaBridge | 165:d1b4690b3f8b | 1026 | #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ |
AnnaBridge | 165:d1b4690b3f8b | 1027 | #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ |
AnnaBridge | 165:d1b4690b3f8b | 1028 | #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ |
AnnaBridge | 165:d1b4690b3f8b | 1029 | |
AnnaBridge | 165:d1b4690b3f8b | 1030 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1031 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1032 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1033 | |
AnnaBridge | 165:d1b4690b3f8b | 1034 | /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1035 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1036 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1037 | #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR |
AnnaBridge | 165:d1b4690b3f8b | 1038 | #define DCMI_IT_OVF DCMI_IT_OVR |
AnnaBridge | 165:d1b4690b3f8b | 1039 | #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI |
AnnaBridge | 165:d1b4690b3f8b | 1040 | #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI |
AnnaBridge | 165:d1b4690b3f8b | 1041 | |
AnnaBridge | 165:d1b4690b3f8b | 1042 | #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop |
AnnaBridge | 165:d1b4690b3f8b | 1043 | #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop |
AnnaBridge | 165:d1b4690b3f8b | 1044 | #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop |
AnnaBridge | 165:d1b4690b3f8b | 1045 | |
AnnaBridge | 165:d1b4690b3f8b | 1046 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1047 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1048 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1049 | |
AnnaBridge | 165:d1b4690b3f8b | 1050 | #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ |
AnnaBridge | 165:d1b4690b3f8b | 1051 | defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) |
AnnaBridge | 165:d1b4690b3f8b | 1052 | /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1053 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1054 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1055 | #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 |
AnnaBridge | 165:d1b4690b3f8b | 1056 | #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 |
AnnaBridge | 165:d1b4690b3f8b | 1057 | #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 |
AnnaBridge | 165:d1b4690b3f8b | 1058 | #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 |
AnnaBridge | 165:d1b4690b3f8b | 1059 | #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 |
AnnaBridge | 165:d1b4690b3f8b | 1060 | |
AnnaBridge | 165:d1b4690b3f8b | 1061 | #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 |
AnnaBridge | 165:d1b4690b3f8b | 1062 | #define CM_RGB888 DMA2D_INPUT_RGB888 |
AnnaBridge | 165:d1b4690b3f8b | 1063 | #define CM_RGB565 DMA2D_INPUT_RGB565 |
AnnaBridge | 165:d1b4690b3f8b | 1064 | #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 |
AnnaBridge | 165:d1b4690b3f8b | 1065 | #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 |
AnnaBridge | 165:d1b4690b3f8b | 1066 | #define CM_L8 DMA2D_INPUT_L8 |
AnnaBridge | 165:d1b4690b3f8b | 1067 | #define CM_AL44 DMA2D_INPUT_AL44 |
AnnaBridge | 165:d1b4690b3f8b | 1068 | #define CM_AL88 DMA2D_INPUT_AL88 |
AnnaBridge | 165:d1b4690b3f8b | 1069 | #define CM_L4 DMA2D_INPUT_L4 |
AnnaBridge | 165:d1b4690b3f8b | 1070 | #define CM_A8 DMA2D_INPUT_A8 |
AnnaBridge | 165:d1b4690b3f8b | 1071 | #define CM_A4 DMA2D_INPUT_A4 |
AnnaBridge | 165:d1b4690b3f8b | 1072 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1073 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1074 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1075 | #endif /* STM32L4 || STM32F7*/ |
AnnaBridge | 165:d1b4690b3f8b | 1076 | |
AnnaBridge | 165:d1b4690b3f8b | 1077 | /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1078 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1079 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1080 | |
AnnaBridge | 165:d1b4690b3f8b | 1081 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1082 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1083 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1084 | |
AnnaBridge | 165:d1b4690b3f8b | 1085 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 165:d1b4690b3f8b | 1086 | |
AnnaBridge | 165:d1b4690b3f8b | 1087 | /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1088 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1089 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1090 | #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback |
AnnaBridge | 165:d1b4690b3f8b | 1091 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1092 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1093 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1094 | |
AnnaBridge | 165:d1b4690b3f8b | 1095 | /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1096 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1097 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1098 | #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef |
AnnaBridge | 165:d1b4690b3f8b | 1099 | #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef |
AnnaBridge | 165:d1b4690b3f8b | 1100 | #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish |
AnnaBridge | 165:d1b4690b3f8b | 1101 | #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish |
AnnaBridge | 165:d1b4690b3f8b | 1102 | #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish |
AnnaBridge | 165:d1b4690b3f8b | 1103 | #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish |
AnnaBridge | 165:d1b4690b3f8b | 1104 | |
AnnaBridge | 165:d1b4690b3f8b | 1105 | /*HASH Algorithm Selection*/ |
AnnaBridge | 165:d1b4690b3f8b | 1106 | |
AnnaBridge | 165:d1b4690b3f8b | 1107 | #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 |
AnnaBridge | 165:d1b4690b3f8b | 1108 | #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 |
AnnaBridge | 165:d1b4690b3f8b | 1109 | #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 |
AnnaBridge | 165:d1b4690b3f8b | 1110 | #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 |
AnnaBridge | 165:d1b4690b3f8b | 1111 | |
AnnaBridge | 165:d1b4690b3f8b | 1112 | #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH |
AnnaBridge | 165:d1b4690b3f8b | 1113 | #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC |
AnnaBridge | 165:d1b4690b3f8b | 1114 | |
AnnaBridge | 165:d1b4690b3f8b | 1115 | #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY |
AnnaBridge | 165:d1b4690b3f8b | 1116 | #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY |
AnnaBridge | 165:d1b4690b3f8b | 1117 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1118 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1119 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1120 | |
AnnaBridge | 165:d1b4690b3f8b | 1121 | /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1122 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1123 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1124 | #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode |
AnnaBridge | 165:d1b4690b3f8b | 1125 | #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode |
AnnaBridge | 165:d1b4690b3f8b | 1126 | #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode |
AnnaBridge | 165:d1b4690b3f8b | 1127 | #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode |
AnnaBridge | 165:d1b4690b3f8b | 1128 | #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode |
AnnaBridge | 165:d1b4690b3f8b | 1129 | #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode |
AnnaBridge | 165:d1b4690b3f8b | 1130 | #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) |
AnnaBridge | 165:d1b4690b3f8b | 1131 | #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect |
AnnaBridge | 165:d1b4690b3f8b | 1132 | #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) |
AnnaBridge | 165:d1b4690b3f8b | 1133 | #if defined(STM32L0) |
AnnaBridge | 165:d1b4690b3f8b | 1134 | #else |
AnnaBridge | 165:d1b4690b3f8b | 1135 | #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) |
AnnaBridge | 165:d1b4690b3f8b | 1136 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 1137 | #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) |
AnnaBridge | 165:d1b4690b3f8b | 1138 | #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) |
AnnaBridge | 165:d1b4690b3f8b | 1139 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1140 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1141 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1142 | |
AnnaBridge | 165:d1b4690b3f8b | 1143 | /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1144 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1145 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1146 | #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram |
AnnaBridge | 165:d1b4690b3f8b | 1147 | #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown |
AnnaBridge | 165:d1b4690b3f8b | 1148 | #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown |
AnnaBridge | 165:d1b4690b3f8b | 1149 | #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock |
AnnaBridge | 165:d1b4690b3f8b | 1150 | #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock |
AnnaBridge | 165:d1b4690b3f8b | 1151 | #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase |
AnnaBridge | 165:d1b4690b3f8b | 1152 | #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program |
AnnaBridge | 165:d1b4690b3f8b | 1153 | |
AnnaBridge | 165:d1b4690b3f8b | 1154 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1155 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1156 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1157 | |
AnnaBridge | 165:d1b4690b3f8b | 1158 | /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1159 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1160 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1161 | #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter |
AnnaBridge | 165:d1b4690b3f8b | 1162 | #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter |
AnnaBridge | 165:d1b4690b3f8b | 1163 | #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter |
AnnaBridge | 165:d1b4690b3f8b | 1164 | #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter |
AnnaBridge | 165:d1b4690b3f8b | 1165 | |
AnnaBridge | 165:d1b4690b3f8b | 1166 | #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) |
AnnaBridge | 165:d1b4690b3f8b | 1167 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1168 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1169 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1170 | |
AnnaBridge | 165:d1b4690b3f8b | 1171 | /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1172 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1173 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1174 | #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD |
AnnaBridge | 165:d1b4690b3f8b | 1175 | #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg |
AnnaBridge | 165:d1b4690b3f8b | 1176 | #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown |
AnnaBridge | 165:d1b4690b3f8b | 1177 | #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor |
AnnaBridge | 165:d1b4690b3f8b | 1178 | #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg |
AnnaBridge | 165:d1b4690b3f8b | 1179 | #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown |
AnnaBridge | 165:d1b4690b3f8b | 1180 | #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor |
AnnaBridge | 165:d1b4690b3f8b | 1181 | #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler |
AnnaBridge | 165:d1b4690b3f8b | 1182 | #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD |
AnnaBridge | 165:d1b4690b3f8b | 1183 | #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler |
AnnaBridge | 165:d1b4690b3f8b | 1184 | #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback |
AnnaBridge | 165:d1b4690b3f8b | 1185 | #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive |
AnnaBridge | 165:d1b4690b3f8b | 1186 | #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive |
AnnaBridge | 165:d1b4690b3f8b | 1187 | #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC |
AnnaBridge | 165:d1b4690b3f8b | 1188 | #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC |
AnnaBridge | 165:d1b4690b3f8b | 1189 | #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM |
AnnaBridge | 165:d1b4690b3f8b | 1190 | |
AnnaBridge | 165:d1b4690b3f8b | 1191 | #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL |
AnnaBridge | 165:d1b4690b3f8b | 1192 | #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING |
AnnaBridge | 165:d1b4690b3f8b | 1193 | #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING |
AnnaBridge | 165:d1b4690b3f8b | 1194 | #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING |
AnnaBridge | 165:d1b4690b3f8b | 1195 | #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING |
AnnaBridge | 165:d1b4690b3f8b | 1196 | #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING |
AnnaBridge | 165:d1b4690b3f8b | 1197 | #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING |
AnnaBridge | 165:d1b4690b3f8b | 1198 | |
AnnaBridge | 165:d1b4690b3f8b | 1199 | #define CR_OFFSET_BB PWR_CR_OFFSET_BB |
AnnaBridge | 165:d1b4690b3f8b | 1200 | #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB |
AnnaBridge | 165:d1b4690b3f8b | 1201 | #define PMODE_BIT_NUMBER VOS_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 1202 | #define CR_PMODE_BB CR_VOS_BB |
AnnaBridge | 165:d1b4690b3f8b | 1203 | |
AnnaBridge | 165:d1b4690b3f8b | 1204 | #define DBP_BitNumber DBP_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 1205 | #define PVDE_BitNumber PVDE_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 1206 | #define PMODE_BitNumber PMODE_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 1207 | #define EWUP_BitNumber EWUP_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 1208 | #define FPDS_BitNumber FPDS_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 1209 | #define ODEN_BitNumber ODEN_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 1210 | #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 1211 | #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 1212 | #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 1213 | #define BRE_BitNumber BRE_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 1214 | |
AnnaBridge | 165:d1b4690b3f8b | 1215 | #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL |
AnnaBridge | 165:d1b4690b3f8b | 1216 | |
AnnaBridge | 165:d1b4690b3f8b | 1217 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1218 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1219 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1220 | |
AnnaBridge | 165:d1b4690b3f8b | 1221 | /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1222 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1223 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1224 | #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT |
AnnaBridge | 165:d1b4690b3f8b | 1225 | #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback |
AnnaBridge | 165:d1b4690b3f8b | 1226 | #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback |
AnnaBridge | 165:d1b4690b3f8b | 1227 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1228 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1229 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1230 | |
AnnaBridge | 165:d1b4690b3f8b | 1231 | /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1232 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1233 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1234 | #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo |
AnnaBridge | 165:d1b4690b3f8b | 1235 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1236 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1237 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1238 | |
AnnaBridge | 165:d1b4690b3f8b | 1239 | /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1240 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1241 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1242 | #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt |
AnnaBridge | 165:d1b4690b3f8b | 1243 | #define HAL_TIM_DMAError TIM_DMAError |
AnnaBridge | 165:d1b4690b3f8b | 1244 | #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt |
AnnaBridge | 165:d1b4690b3f8b | 1245 | #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt |
AnnaBridge | 165:d1b4690b3f8b | 1246 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1247 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1248 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1249 | |
AnnaBridge | 165:d1b4690b3f8b | 1250 | /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1251 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1252 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1253 | #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback |
AnnaBridge | 165:d1b4690b3f8b | 1254 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1255 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1256 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1257 | |
AnnaBridge | 165:d1b4690b3f8b | 1258 | /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1259 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1260 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1261 | #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback |
AnnaBridge | 165:d1b4690b3f8b | 1262 | #define HAL_LTDC_Relaod HAL_LTDC_Reload |
AnnaBridge | 165:d1b4690b3f8b | 1263 | #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig |
AnnaBridge | 165:d1b4690b3f8b | 1264 | #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig |
AnnaBridge | 165:d1b4690b3f8b | 1265 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1266 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1267 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1268 | |
AnnaBridge | 165:d1b4690b3f8b | 1269 | |
AnnaBridge | 165:d1b4690b3f8b | 1270 | /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1271 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1272 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1273 | |
AnnaBridge | 165:d1b4690b3f8b | 1274 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1275 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1276 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1277 | |
AnnaBridge | 165:d1b4690b3f8b | 1278 | /* Exported macros ------------------------------------------------------------*/ |
AnnaBridge | 165:d1b4690b3f8b | 1279 | |
AnnaBridge | 165:d1b4690b3f8b | 1280 | /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1281 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1282 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1283 | #define AES_IT_CC CRYP_IT_CC |
AnnaBridge | 165:d1b4690b3f8b | 1284 | #define AES_IT_ERR CRYP_IT_ERR |
AnnaBridge | 165:d1b4690b3f8b | 1285 | #define AES_FLAG_CCF CRYP_FLAG_CCF |
AnnaBridge | 165:d1b4690b3f8b | 1286 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1287 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1288 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1289 | |
AnnaBridge | 165:d1b4690b3f8b | 1290 | /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1291 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1292 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1293 | #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE |
AnnaBridge | 165:d1b4690b3f8b | 1294 | #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH |
AnnaBridge | 165:d1b4690b3f8b | 1295 | #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH |
AnnaBridge | 165:d1b4690b3f8b | 1296 | #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM |
AnnaBridge | 165:d1b4690b3f8b | 1297 | #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC |
AnnaBridge | 165:d1b4690b3f8b | 1298 | #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM |
AnnaBridge | 165:d1b4690b3f8b | 1299 | #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC |
AnnaBridge | 165:d1b4690b3f8b | 1300 | #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI |
AnnaBridge | 165:d1b4690b3f8b | 1301 | #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK |
AnnaBridge | 165:d1b4690b3f8b | 1302 | #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG |
AnnaBridge | 165:d1b4690b3f8b | 1303 | #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG |
AnnaBridge | 165:d1b4690b3f8b | 1304 | #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1305 | #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1306 | #define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1307 | |
AnnaBridge | 165:d1b4690b3f8b | 1308 | #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY |
AnnaBridge | 165:d1b4690b3f8b | 1309 | #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 |
AnnaBridge | 165:d1b4690b3f8b | 1310 | #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS |
AnnaBridge | 165:d1b4690b3f8b | 1311 | #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 1312 | #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 1313 | |
AnnaBridge | 165:d1b4690b3f8b | 1314 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1315 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1316 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1317 | |
AnnaBridge | 165:d1b4690b3f8b | 1318 | |
AnnaBridge | 165:d1b4690b3f8b | 1319 | /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1320 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1321 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1322 | #define __ADC_ENABLE __HAL_ADC_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1323 | #define __ADC_DISABLE __HAL_ADC_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1324 | #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS |
AnnaBridge | 165:d1b4690b3f8b | 1325 | #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS |
AnnaBridge | 165:d1b4690b3f8b | 1326 | #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1327 | #define __ADC_IS_ENABLED ADC_IS_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1328 | #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR |
AnnaBridge | 165:d1b4690b3f8b | 1329 | #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED |
AnnaBridge | 165:d1b4690b3f8b | 1330 | #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED |
AnnaBridge | 165:d1b4690b3f8b | 1331 | #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR |
AnnaBridge | 165:d1b4690b3f8b | 1332 | #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED |
AnnaBridge | 165:d1b4690b3f8b | 1333 | #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING |
AnnaBridge | 165:d1b4690b3f8b | 1334 | #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE |
AnnaBridge | 165:d1b4690b3f8b | 1335 | |
AnnaBridge | 165:d1b4690b3f8b | 1336 | #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION |
AnnaBridge | 165:d1b4690b3f8b | 1337 | #define __HAL_ADC_JSQR_RK ADC_JSQR_RK |
AnnaBridge | 165:d1b4690b3f8b | 1338 | #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT |
AnnaBridge | 165:d1b4690b3f8b | 1339 | #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR |
AnnaBridge | 165:d1b4690b3f8b | 1340 | #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION |
AnnaBridge | 165:d1b4690b3f8b | 1341 | #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE |
AnnaBridge | 165:d1b4690b3f8b | 1342 | #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS |
AnnaBridge | 165:d1b4690b3f8b | 1343 | #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS |
AnnaBridge | 165:d1b4690b3f8b | 1344 | #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM |
AnnaBridge | 165:d1b4690b3f8b | 1345 | #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT |
AnnaBridge | 165:d1b4690b3f8b | 1346 | #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS |
AnnaBridge | 165:d1b4690b3f8b | 1347 | #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN |
AnnaBridge | 165:d1b4690b3f8b | 1348 | #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ |
AnnaBridge | 165:d1b4690b3f8b | 1349 | #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET |
AnnaBridge | 165:d1b4690b3f8b | 1350 | #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET |
AnnaBridge | 165:d1b4690b3f8b | 1351 | #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL |
AnnaBridge | 165:d1b4690b3f8b | 1352 | #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL |
AnnaBridge | 165:d1b4690b3f8b | 1353 | #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET |
AnnaBridge | 165:d1b4690b3f8b | 1354 | #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET |
AnnaBridge | 165:d1b4690b3f8b | 1355 | #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD |
AnnaBridge | 165:d1b4690b3f8b | 1356 | |
AnnaBridge | 165:d1b4690b3f8b | 1357 | #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION |
AnnaBridge | 165:d1b4690b3f8b | 1358 | #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION |
AnnaBridge | 165:d1b4690b3f8b | 1359 | #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION |
AnnaBridge | 165:d1b4690b3f8b | 1360 | #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER |
AnnaBridge | 165:d1b4690b3f8b | 1361 | #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI |
AnnaBridge | 165:d1b4690b3f8b | 1362 | #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1363 | #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1364 | #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER |
AnnaBridge | 165:d1b4690b3f8b | 1365 | #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER |
AnnaBridge | 165:d1b4690b3f8b | 1366 | #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE |
AnnaBridge | 165:d1b4690b3f8b | 1367 | |
AnnaBridge | 165:d1b4690b3f8b | 1368 | #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT |
AnnaBridge | 165:d1b4690b3f8b | 1369 | #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT |
AnnaBridge | 165:d1b4690b3f8b | 1370 | #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL |
AnnaBridge | 165:d1b4690b3f8b | 1371 | #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM |
AnnaBridge | 165:d1b4690b3f8b | 1372 | #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET |
AnnaBridge | 165:d1b4690b3f8b | 1373 | #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE |
AnnaBridge | 165:d1b4690b3f8b | 1374 | #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE |
AnnaBridge | 165:d1b4690b3f8b | 1375 | #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER |
AnnaBridge | 165:d1b4690b3f8b | 1376 | |
AnnaBridge | 165:d1b4690b3f8b | 1377 | #define __HAL_ADC_SQR1 ADC_SQR1 |
AnnaBridge | 165:d1b4690b3f8b | 1378 | #define __HAL_ADC_SMPR1 ADC_SMPR1 |
AnnaBridge | 165:d1b4690b3f8b | 1379 | #define __HAL_ADC_SMPR2 ADC_SMPR2 |
AnnaBridge | 165:d1b4690b3f8b | 1380 | #define __HAL_ADC_SQR3_RK ADC_SQR3_RK |
AnnaBridge | 165:d1b4690b3f8b | 1381 | #define __HAL_ADC_SQR2_RK ADC_SQR2_RK |
AnnaBridge | 165:d1b4690b3f8b | 1382 | #define __HAL_ADC_SQR1_RK ADC_SQR1_RK |
AnnaBridge | 165:d1b4690b3f8b | 1383 | #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS |
AnnaBridge | 165:d1b4690b3f8b | 1384 | #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS |
AnnaBridge | 165:d1b4690b3f8b | 1385 | #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV |
AnnaBridge | 165:d1b4690b3f8b | 1386 | #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection |
AnnaBridge | 165:d1b4690b3f8b | 1387 | #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq |
AnnaBridge | 165:d1b4690b3f8b | 1388 | #define __HAL_ADC_JSQR ADC_JSQR |
AnnaBridge | 165:d1b4690b3f8b | 1389 | |
AnnaBridge | 165:d1b4690b3f8b | 1390 | #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL |
AnnaBridge | 165:d1b4690b3f8b | 1391 | #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS |
AnnaBridge | 165:d1b4690b3f8b | 1392 | #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF |
AnnaBridge | 165:d1b4690b3f8b | 1393 | #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT |
AnnaBridge | 165:d1b4690b3f8b | 1394 | #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS |
AnnaBridge | 165:d1b4690b3f8b | 1395 | #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN |
AnnaBridge | 165:d1b4690b3f8b | 1396 | #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR |
AnnaBridge | 165:d1b4690b3f8b | 1397 | #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ |
AnnaBridge | 165:d1b4690b3f8b | 1398 | |
AnnaBridge | 165:d1b4690b3f8b | 1399 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1400 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1401 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1402 | |
AnnaBridge | 165:d1b4690b3f8b | 1403 | /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1404 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1405 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1406 | #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT |
AnnaBridge | 165:d1b4690b3f8b | 1407 | #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT |
AnnaBridge | 165:d1b4690b3f8b | 1408 | #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT |
AnnaBridge | 165:d1b4690b3f8b | 1409 | #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE |
AnnaBridge | 165:d1b4690b3f8b | 1410 | |
AnnaBridge | 165:d1b4690b3f8b | 1411 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1412 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1413 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1414 | |
AnnaBridge | 165:d1b4690b3f8b | 1415 | /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1416 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1417 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1418 | #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 |
AnnaBridge | 165:d1b4690b3f8b | 1419 | #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 |
AnnaBridge | 165:d1b4690b3f8b | 1420 | #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 |
AnnaBridge | 165:d1b4690b3f8b | 1421 | #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 |
AnnaBridge | 165:d1b4690b3f8b | 1422 | #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 |
AnnaBridge | 165:d1b4690b3f8b | 1423 | #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 |
AnnaBridge | 165:d1b4690b3f8b | 1424 | #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 |
AnnaBridge | 165:d1b4690b3f8b | 1425 | #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 |
AnnaBridge | 165:d1b4690b3f8b | 1426 | #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 |
AnnaBridge | 165:d1b4690b3f8b | 1427 | #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 |
AnnaBridge | 165:d1b4690b3f8b | 1428 | #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 |
AnnaBridge | 165:d1b4690b3f8b | 1429 | #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 |
AnnaBridge | 165:d1b4690b3f8b | 1430 | #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 |
AnnaBridge | 165:d1b4690b3f8b | 1431 | #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 |
AnnaBridge | 165:d1b4690b3f8b | 1432 | #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 |
AnnaBridge | 165:d1b4690b3f8b | 1433 | #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 |
AnnaBridge | 165:d1b4690b3f8b | 1434 | |
AnnaBridge | 165:d1b4690b3f8b | 1435 | #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 |
AnnaBridge | 165:d1b4690b3f8b | 1436 | #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 |
AnnaBridge | 165:d1b4690b3f8b | 1437 | #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 |
AnnaBridge | 165:d1b4690b3f8b | 1438 | #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 |
AnnaBridge | 165:d1b4690b3f8b | 1439 | #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 |
AnnaBridge | 165:d1b4690b3f8b | 1440 | #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 |
AnnaBridge | 165:d1b4690b3f8b | 1441 | #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 |
AnnaBridge | 165:d1b4690b3f8b | 1442 | #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 |
AnnaBridge | 165:d1b4690b3f8b | 1443 | #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 |
AnnaBridge | 165:d1b4690b3f8b | 1444 | #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 |
AnnaBridge | 165:d1b4690b3f8b | 1445 | #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 |
AnnaBridge | 165:d1b4690b3f8b | 1446 | #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 |
AnnaBridge | 165:d1b4690b3f8b | 1447 | #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 |
AnnaBridge | 165:d1b4690b3f8b | 1448 | #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 |
AnnaBridge | 165:d1b4690b3f8b | 1449 | |
AnnaBridge | 165:d1b4690b3f8b | 1450 | |
AnnaBridge | 165:d1b4690b3f8b | 1451 | #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 |
AnnaBridge | 165:d1b4690b3f8b | 1452 | #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 |
AnnaBridge | 165:d1b4690b3f8b | 1453 | #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 |
AnnaBridge | 165:d1b4690b3f8b | 1454 | #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 |
AnnaBridge | 165:d1b4690b3f8b | 1455 | #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 |
AnnaBridge | 165:d1b4690b3f8b | 1456 | #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 |
AnnaBridge | 165:d1b4690b3f8b | 1457 | #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC |
AnnaBridge | 165:d1b4690b3f8b | 1458 | #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC |
AnnaBridge | 165:d1b4690b3f8b | 1459 | #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG |
AnnaBridge | 165:d1b4690b3f8b | 1460 | #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG |
AnnaBridge | 165:d1b4690b3f8b | 1461 | #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG |
AnnaBridge | 165:d1b4690b3f8b | 1462 | #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG |
AnnaBridge | 165:d1b4690b3f8b | 1463 | #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT |
AnnaBridge | 165:d1b4690b3f8b | 1464 | #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT |
AnnaBridge | 165:d1b4690b3f8b | 1465 | #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT |
AnnaBridge | 165:d1b4690b3f8b | 1466 | #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT |
AnnaBridge | 165:d1b4690b3f8b | 1467 | #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT |
AnnaBridge | 165:d1b4690b3f8b | 1468 | #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT |
AnnaBridge | 165:d1b4690b3f8b | 1469 | #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 |
AnnaBridge | 165:d1b4690b3f8b | 1470 | #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 |
AnnaBridge | 165:d1b4690b3f8b | 1471 | #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 |
AnnaBridge | 165:d1b4690b3f8b | 1472 | #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 |
AnnaBridge | 165:d1b4690b3f8b | 1473 | #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 |
AnnaBridge | 165:d1b4690b3f8b | 1474 | #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 |
AnnaBridge | 165:d1b4690b3f8b | 1475 | |
AnnaBridge | 165:d1b4690b3f8b | 1476 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1477 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1478 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1479 | |
AnnaBridge | 165:d1b4690b3f8b | 1480 | /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1481 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1482 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1483 | #if defined(STM32F3) |
AnnaBridge | 165:d1b4690b3f8b | 1484 | #define COMP_START __HAL_COMP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1485 | #define COMP_STOP __HAL_COMP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1486 | #define COMP_LOCK __HAL_COMP_LOCK |
AnnaBridge | 165:d1b4690b3f8b | 1487 | |
AnnaBridge | 165:d1b4690b3f8b | 1488 | #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) |
AnnaBridge | 165:d1b4690b3f8b | 1489 | #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1490 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1491 | __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) |
AnnaBridge | 165:d1b4690b3f8b | 1492 | #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1493 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1494 | __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) |
AnnaBridge | 165:d1b4690b3f8b | 1495 | #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1496 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1497 | __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) |
AnnaBridge | 165:d1b4690b3f8b | 1498 | #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1499 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1500 | __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) |
AnnaBridge | 165:d1b4690b3f8b | 1501 | #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1502 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1503 | __HAL_COMP_COMP6_EXTI_ENABLE_IT()) |
AnnaBridge | 165:d1b4690b3f8b | 1504 | #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1505 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1506 | __HAL_COMP_COMP6_EXTI_DISABLE_IT()) |
AnnaBridge | 165:d1b4690b3f8b | 1507 | #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1508 | ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1509 | __HAL_COMP_COMP6_EXTI_GET_FLAG()) |
AnnaBridge | 165:d1b4690b3f8b | 1510 | #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1511 | ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1512 | __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) |
AnnaBridge | 165:d1b4690b3f8b | 1513 | # endif |
AnnaBridge | 165:d1b4690b3f8b | 1514 | # if defined(STM32F302xE) || defined(STM32F302xC) |
AnnaBridge | 165:d1b4690b3f8b | 1515 | #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1516 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1517 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1518 | __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) |
AnnaBridge | 165:d1b4690b3f8b | 1519 | #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1520 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1521 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1522 | __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) |
AnnaBridge | 165:d1b4690b3f8b | 1523 | #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1524 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1525 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1526 | __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) |
AnnaBridge | 165:d1b4690b3f8b | 1527 | #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1528 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1529 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1530 | __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) |
AnnaBridge | 165:d1b4690b3f8b | 1531 | #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1532 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1533 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1534 | __HAL_COMP_COMP6_EXTI_ENABLE_IT()) |
AnnaBridge | 165:d1b4690b3f8b | 1535 | #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1536 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1537 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1538 | __HAL_COMP_COMP6_EXTI_DISABLE_IT()) |
AnnaBridge | 165:d1b4690b3f8b | 1539 | #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1540 | ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1541 | ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1542 | __HAL_COMP_COMP6_EXTI_GET_FLAG()) |
AnnaBridge | 165:d1b4690b3f8b | 1543 | #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1544 | ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1545 | ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1546 | __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) |
AnnaBridge | 165:d1b4690b3f8b | 1547 | # endif |
AnnaBridge | 165:d1b4690b3f8b | 1548 | # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) |
AnnaBridge | 165:d1b4690b3f8b | 1549 | #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1550 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1551 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1552 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1553 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1554 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1555 | __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) |
AnnaBridge | 165:d1b4690b3f8b | 1556 | #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1557 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1558 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1559 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1560 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1561 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1562 | __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) |
AnnaBridge | 165:d1b4690b3f8b | 1563 | #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1564 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1565 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1566 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1567 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1568 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1569 | __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) |
AnnaBridge | 165:d1b4690b3f8b | 1570 | #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1571 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1572 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1573 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1574 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1575 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1576 | __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) |
AnnaBridge | 165:d1b4690b3f8b | 1577 | #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1578 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1579 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1580 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1581 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1582 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1583 | __HAL_COMP_COMP7_EXTI_ENABLE_IT()) |
AnnaBridge | 165:d1b4690b3f8b | 1584 | #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1585 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1586 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1587 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1588 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1589 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1590 | __HAL_COMP_COMP7_EXTI_DISABLE_IT()) |
AnnaBridge | 165:d1b4690b3f8b | 1591 | #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1592 | ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1593 | ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1594 | ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1595 | ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1596 | ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1597 | __HAL_COMP_COMP7_EXTI_GET_FLAG()) |
AnnaBridge | 165:d1b4690b3f8b | 1598 | #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1599 | ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1600 | ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1601 | ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1602 | ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1603 | ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1604 | __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) |
AnnaBridge | 165:d1b4690b3f8b | 1605 | # endif |
AnnaBridge | 165:d1b4690b3f8b | 1606 | # if defined(STM32F373xC) ||defined(STM32F378xx) |
AnnaBridge | 165:d1b4690b3f8b | 1607 | #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1608 | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) |
AnnaBridge | 165:d1b4690b3f8b | 1609 | #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1610 | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) |
AnnaBridge | 165:d1b4690b3f8b | 1611 | #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1612 | __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) |
AnnaBridge | 165:d1b4690b3f8b | 1613 | #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1614 | __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) |
AnnaBridge | 165:d1b4690b3f8b | 1615 | #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1616 | __HAL_COMP_COMP2_EXTI_ENABLE_IT()) |
AnnaBridge | 165:d1b4690b3f8b | 1617 | #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1618 | __HAL_COMP_COMP2_EXTI_DISABLE_IT()) |
AnnaBridge | 165:d1b4690b3f8b | 1619 | #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1620 | __HAL_COMP_COMP2_EXTI_GET_FLAG()) |
AnnaBridge | 165:d1b4690b3f8b | 1621 | #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1622 | __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) |
AnnaBridge | 165:d1b4690b3f8b | 1623 | # endif |
AnnaBridge | 165:d1b4690b3f8b | 1624 | #else |
AnnaBridge | 165:d1b4690b3f8b | 1625 | #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1626 | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) |
AnnaBridge | 165:d1b4690b3f8b | 1627 | #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1628 | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) |
AnnaBridge | 165:d1b4690b3f8b | 1629 | #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1630 | __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) |
AnnaBridge | 165:d1b4690b3f8b | 1631 | #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1632 | __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) |
AnnaBridge | 165:d1b4690b3f8b | 1633 | #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1634 | __HAL_COMP_COMP2_EXTI_ENABLE_IT()) |
AnnaBridge | 165:d1b4690b3f8b | 1635 | #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1636 | __HAL_COMP_COMP2_EXTI_DISABLE_IT()) |
AnnaBridge | 165:d1b4690b3f8b | 1637 | #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1638 | __HAL_COMP_COMP2_EXTI_GET_FLAG()) |
AnnaBridge | 165:d1b4690b3f8b | 1639 | #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 1640 | __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) |
AnnaBridge | 165:d1b4690b3f8b | 1641 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 1642 | |
AnnaBridge | 165:d1b4690b3f8b | 1643 | #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE |
AnnaBridge | 165:d1b4690b3f8b | 1644 | |
AnnaBridge | 165:d1b4690b3f8b | 1645 | #if defined(STM32L0) || defined(STM32L4) |
AnnaBridge | 165:d1b4690b3f8b | 1646 | /* Note: On these STM32 families, the only argument of this macro */ |
AnnaBridge | 165:d1b4690b3f8b | 1647 | /* is COMP_FLAG_LOCK. */ |
AnnaBridge | 165:d1b4690b3f8b | 1648 | /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ |
AnnaBridge | 165:d1b4690b3f8b | 1649 | /* argument. */ |
AnnaBridge | 165:d1b4690b3f8b | 1650 | #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1651 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 1652 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1653 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1654 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1655 | |
AnnaBridge | 165:d1b4690b3f8b | 1656 | #if defined(STM32L0) || defined(STM32L4) |
AnnaBridge | 165:d1b4690b3f8b | 1657 | /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1658 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1659 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1660 | #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ |
AnnaBridge | 165:d1b4690b3f8b | 1661 | #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ |
AnnaBridge | 165:d1b4690b3f8b | 1662 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1663 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1664 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1665 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 1666 | |
AnnaBridge | 165:d1b4690b3f8b | 1667 | /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1668 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1669 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1670 | |
AnnaBridge | 165:d1b4690b3f8b | 1671 | #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ |
AnnaBridge | 165:d1b4690b3f8b | 1672 | ((WAVE) == DAC_WAVE_NOISE)|| \ |
AnnaBridge | 165:d1b4690b3f8b | 1673 | ((WAVE) == DAC_WAVE_TRIANGLE)) |
AnnaBridge | 165:d1b4690b3f8b | 1674 | |
AnnaBridge | 165:d1b4690b3f8b | 1675 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1676 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1677 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1678 | |
AnnaBridge | 165:d1b4690b3f8b | 1679 | /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1680 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1681 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1682 | |
AnnaBridge | 165:d1b4690b3f8b | 1683 | #define IS_WRPAREA IS_OB_WRPAREA |
AnnaBridge | 165:d1b4690b3f8b | 1684 | #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM |
AnnaBridge | 165:d1b4690b3f8b | 1685 | #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM |
AnnaBridge | 165:d1b4690b3f8b | 1686 | #define IS_TYPEERASE IS_FLASH_TYPEERASE |
AnnaBridge | 165:d1b4690b3f8b | 1687 | #define IS_NBSECTORS IS_FLASH_NBSECTORS |
AnnaBridge | 165:d1b4690b3f8b | 1688 | #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE |
AnnaBridge | 165:d1b4690b3f8b | 1689 | |
AnnaBridge | 165:d1b4690b3f8b | 1690 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1691 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1692 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1693 | |
AnnaBridge | 165:d1b4690b3f8b | 1694 | /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1695 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1696 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1697 | |
AnnaBridge | 165:d1b4690b3f8b | 1698 | #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 |
AnnaBridge | 165:d1b4690b3f8b | 1699 | #define __HAL_I2C_GENERATE_START I2C_GENERATE_START |
AnnaBridge | 165:d1b4690b3f8b | 1700 | #if defined(STM32F1) |
AnnaBridge | 165:d1b4690b3f8b | 1701 | #define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE |
AnnaBridge | 165:d1b4690b3f8b | 1702 | #else |
AnnaBridge | 165:d1b4690b3f8b | 1703 | #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE |
AnnaBridge | 165:d1b4690b3f8b | 1704 | #endif /* STM32F1 */ |
AnnaBridge | 165:d1b4690b3f8b | 1705 | #define __HAL_I2C_RISE_TIME I2C_RISE_TIME |
AnnaBridge | 165:d1b4690b3f8b | 1706 | #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD |
AnnaBridge | 165:d1b4690b3f8b | 1707 | #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST |
AnnaBridge | 165:d1b4690b3f8b | 1708 | #define __HAL_I2C_SPEED I2C_SPEED |
AnnaBridge | 165:d1b4690b3f8b | 1709 | #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE |
AnnaBridge | 165:d1b4690b3f8b | 1710 | #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ |
AnnaBridge | 165:d1b4690b3f8b | 1711 | #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS |
AnnaBridge | 165:d1b4690b3f8b | 1712 | #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE |
AnnaBridge | 165:d1b4690b3f8b | 1713 | #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ |
AnnaBridge | 165:d1b4690b3f8b | 1714 | #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB |
AnnaBridge | 165:d1b4690b3f8b | 1715 | #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB |
AnnaBridge | 165:d1b4690b3f8b | 1716 | #define __HAL_I2C_FREQRANGE I2C_FREQRANGE |
AnnaBridge | 165:d1b4690b3f8b | 1717 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1718 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1719 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1720 | |
AnnaBridge | 165:d1b4690b3f8b | 1721 | /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1722 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1723 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1724 | |
AnnaBridge | 165:d1b4690b3f8b | 1725 | #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE |
AnnaBridge | 165:d1b4690b3f8b | 1726 | #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT |
AnnaBridge | 165:d1b4690b3f8b | 1727 | |
AnnaBridge | 165:d1b4690b3f8b | 1728 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1729 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1730 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1731 | |
AnnaBridge | 165:d1b4690b3f8b | 1732 | /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1733 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1734 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1735 | |
AnnaBridge | 165:d1b4690b3f8b | 1736 | #define __IRDA_DISABLE __HAL_IRDA_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1737 | #define __IRDA_ENABLE __HAL_IRDA_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1738 | |
AnnaBridge | 165:d1b4690b3f8b | 1739 | #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE |
AnnaBridge | 165:d1b4690b3f8b | 1740 | #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION |
AnnaBridge | 165:d1b4690b3f8b | 1741 | #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE |
AnnaBridge | 165:d1b4690b3f8b | 1742 | #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION |
AnnaBridge | 165:d1b4690b3f8b | 1743 | |
AnnaBridge | 165:d1b4690b3f8b | 1744 | #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE |
AnnaBridge | 165:d1b4690b3f8b | 1745 | |
AnnaBridge | 165:d1b4690b3f8b | 1746 | |
AnnaBridge | 165:d1b4690b3f8b | 1747 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1748 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1749 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1750 | |
AnnaBridge | 165:d1b4690b3f8b | 1751 | |
AnnaBridge | 165:d1b4690b3f8b | 1752 | /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1753 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1754 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1755 | #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS |
AnnaBridge | 165:d1b4690b3f8b | 1756 | #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS |
AnnaBridge | 165:d1b4690b3f8b | 1757 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1758 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1759 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1760 | |
AnnaBridge | 165:d1b4690b3f8b | 1761 | |
AnnaBridge | 165:d1b4690b3f8b | 1762 | /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1763 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1764 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1765 | |
AnnaBridge | 165:d1b4690b3f8b | 1766 | #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT |
AnnaBridge | 165:d1b4690b3f8b | 1767 | #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT |
AnnaBridge | 165:d1b4690b3f8b | 1768 | #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE |
AnnaBridge | 165:d1b4690b3f8b | 1769 | |
AnnaBridge | 165:d1b4690b3f8b | 1770 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1771 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1772 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1773 | |
AnnaBridge | 165:d1b4690b3f8b | 1774 | |
AnnaBridge | 165:d1b4690b3f8b | 1775 | /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1776 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1777 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1778 | #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD |
AnnaBridge | 165:d1b4690b3f8b | 1779 | #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX |
AnnaBridge | 165:d1b4690b3f8b | 1780 | #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX |
AnnaBridge | 165:d1b4690b3f8b | 1781 | #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX |
AnnaBridge | 165:d1b4690b3f8b | 1782 | #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX |
AnnaBridge | 165:d1b4690b3f8b | 1783 | #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L |
AnnaBridge | 165:d1b4690b3f8b | 1784 | #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H |
AnnaBridge | 165:d1b4690b3f8b | 1785 | #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM |
AnnaBridge | 165:d1b4690b3f8b | 1786 | #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES |
AnnaBridge | 165:d1b4690b3f8b | 1787 | #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX |
AnnaBridge | 165:d1b4690b3f8b | 1788 | #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT |
AnnaBridge | 165:d1b4690b3f8b | 1789 | #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION |
AnnaBridge | 165:d1b4690b3f8b | 1790 | #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET |
AnnaBridge | 165:d1b4690b3f8b | 1791 | |
AnnaBridge | 165:d1b4690b3f8b | 1792 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1793 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1794 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1795 | |
AnnaBridge | 165:d1b4690b3f8b | 1796 | |
AnnaBridge | 165:d1b4690b3f8b | 1797 | /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1798 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1799 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1800 | #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT |
AnnaBridge | 165:d1b4690b3f8b | 1801 | #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT |
AnnaBridge | 165:d1b4690b3f8b | 1802 | #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 1803 | #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 1804 | #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 1805 | #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 1806 | #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1807 | #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1808 | #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1809 | #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1810 | #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1811 | #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1812 | #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine |
AnnaBridge | 165:d1b4690b3f8b | 1813 | #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine |
AnnaBridge | 165:d1b4690b3f8b | 1814 | #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig |
AnnaBridge | 165:d1b4690b3f8b | 1815 | #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig |
AnnaBridge | 165:d1b4690b3f8b | 1816 | #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) |
AnnaBridge | 165:d1b4690b3f8b | 1817 | #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT |
AnnaBridge | 165:d1b4690b3f8b | 1818 | #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT |
AnnaBridge | 165:d1b4690b3f8b | 1819 | #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 1820 | #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 1821 | #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 1822 | #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 1823 | #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 1824 | #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 1825 | #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) |
AnnaBridge | 165:d1b4690b3f8b | 1826 | #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) |
AnnaBridge | 165:d1b4690b3f8b | 1827 | #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention |
AnnaBridge | 165:d1b4690b3f8b | 1828 | #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention |
AnnaBridge | 165:d1b4690b3f8b | 1829 | #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 |
AnnaBridge | 165:d1b4690b3f8b | 1830 | #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 |
AnnaBridge | 165:d1b4690b3f8b | 1831 | #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 1832 | #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 1833 | #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB |
AnnaBridge | 165:d1b4690b3f8b | 1834 | #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB |
AnnaBridge | 165:d1b4690b3f8b | 1835 | |
AnnaBridge | 165:d1b4690b3f8b | 1836 | #if defined (STM32F4) |
AnnaBridge | 165:d1b4690b3f8b | 1837 | #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() |
AnnaBridge | 165:d1b4690b3f8b | 1838 | #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() |
AnnaBridge | 165:d1b4690b3f8b | 1839 | #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() |
AnnaBridge | 165:d1b4690b3f8b | 1840 | #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() |
AnnaBridge | 165:d1b4690b3f8b | 1841 | #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() |
AnnaBridge | 165:d1b4690b3f8b | 1842 | #else |
AnnaBridge | 165:d1b4690b3f8b | 1843 | #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG |
AnnaBridge | 165:d1b4690b3f8b | 1844 | #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT |
AnnaBridge | 165:d1b4690b3f8b | 1845 | #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT |
AnnaBridge | 165:d1b4690b3f8b | 1846 | #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT |
AnnaBridge | 165:d1b4690b3f8b | 1847 | #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG |
AnnaBridge | 165:d1b4690b3f8b | 1848 | #endif /* STM32F4 */ |
AnnaBridge | 165:d1b4690b3f8b | 1849 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1850 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 1851 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1852 | |
AnnaBridge | 165:d1b4690b3f8b | 1853 | |
AnnaBridge | 165:d1b4690b3f8b | 1854 | /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 1855 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 1856 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1857 | |
AnnaBridge | 165:d1b4690b3f8b | 1858 | #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI |
AnnaBridge | 165:d1b4690b3f8b | 1859 | #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI |
AnnaBridge | 165:d1b4690b3f8b | 1860 | |
AnnaBridge | 165:d1b4690b3f8b | 1861 | #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback |
AnnaBridge | 165:d1b4690b3f8b | 1862 | #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) |
AnnaBridge | 165:d1b4690b3f8b | 1863 | |
AnnaBridge | 165:d1b4690b3f8b | 1864 | #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1865 | #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1866 | #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1867 | #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1868 | #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1869 | #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1870 | #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1871 | #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1872 | #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1873 | #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1874 | #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1875 | #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1876 | #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1877 | #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1878 | #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1879 | #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1880 | #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1881 | #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1882 | #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1883 | #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1884 | #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1885 | #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1886 | #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1887 | #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1888 | #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1889 | #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1890 | #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1891 | #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1892 | #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1893 | #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1894 | #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1895 | #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1896 | #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1897 | #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1898 | #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1899 | #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1900 | #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1901 | #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1902 | #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1903 | #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1904 | #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1905 | #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1906 | #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1907 | #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1908 | #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1909 | #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1910 | #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1911 | #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1912 | #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1913 | #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1914 | #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1915 | #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1916 | #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1917 | #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1918 | #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1919 | #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1920 | #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1921 | #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1922 | #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1923 | #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1924 | #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1925 | #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1926 | #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1927 | #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1928 | #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1929 | #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1930 | #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1931 | #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1932 | #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1933 | #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1934 | #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1935 | #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1936 | #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1937 | #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1938 | #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1939 | #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1940 | #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1941 | #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1942 | #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1943 | #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1944 | #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1945 | #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1946 | #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1947 | #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1948 | #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1949 | #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1950 | #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1951 | #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1952 | #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1953 | #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1954 | #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1955 | #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1956 | #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1957 | #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1958 | #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1959 | #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1960 | #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1961 | #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1962 | #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1963 | #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1964 | #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1965 | #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1966 | #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1967 | #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1968 | #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1969 | #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1970 | #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1971 | #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1972 | #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1973 | #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1974 | #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1975 | #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1976 | #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1977 | #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1978 | #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1979 | #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1980 | #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1981 | #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1982 | #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1983 | #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1984 | #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1985 | #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1986 | #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1987 | #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1988 | #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1989 | #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1990 | #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1991 | #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1992 | #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1993 | #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1994 | #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 1995 | #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1996 | #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1997 | #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 1998 | #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 1999 | #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2000 | #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2001 | #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2002 | #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2003 | #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2004 | #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2005 | #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2006 | #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2007 | #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2008 | #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2009 | #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2010 | #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2011 | #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2012 | #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2013 | #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2014 | #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2015 | #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2016 | #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2017 | #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2018 | #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2019 | #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2020 | #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2021 | #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2022 | #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2023 | #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2024 | #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2025 | #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2026 | #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2027 | #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2028 | #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2029 | #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2030 | #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2031 | #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2032 | #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2033 | #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2034 | #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2035 | #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2036 | #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2037 | #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2038 | #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2039 | #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2040 | #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2041 | #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2042 | #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2043 | #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2044 | #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2045 | #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2046 | #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2047 | #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2048 | #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2049 | #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2050 | #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2051 | #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2052 | #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2053 | #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2054 | #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2055 | #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2056 | #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2057 | #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2058 | #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2059 | #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2060 | #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2061 | #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2062 | #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2063 | #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2064 | #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2065 | #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2066 | #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2067 | #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2068 | #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2069 | #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2070 | #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2071 | #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2072 | #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2073 | #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2074 | #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2075 | #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2076 | #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2077 | #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2078 | #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2079 | #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2080 | #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2081 | #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2082 | #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2083 | #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2084 | #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2085 | #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2086 | #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2087 | #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2088 | #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2089 | #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2090 | #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2091 | #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2092 | #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2093 | #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2094 | #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2095 | #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2096 | #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2097 | #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2098 | #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2099 | #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2100 | #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2101 | #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2102 | #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2103 | #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2104 | #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2105 | #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2106 | #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2107 | #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2108 | #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2109 | #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2110 | #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2111 | #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2112 | #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2113 | #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2114 | #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2115 | #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2116 | #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2117 | #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2118 | #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2119 | #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2120 | #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2121 | #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2122 | |
AnnaBridge | 165:d1b4690b3f8b | 2123 | #if defined(STM32WB) |
AnnaBridge | 165:d1b4690b3f8b | 2124 | #define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2125 | #define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2126 | #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2127 | #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2128 | #define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2129 | #define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2130 | #define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2131 | #define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2132 | #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2133 | #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2134 | #define QSPI_IRQHandler QUADSPI_IRQHandler |
AnnaBridge | 165:d1b4690b3f8b | 2135 | #endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ |
AnnaBridge | 165:d1b4690b3f8b | 2136 | |
AnnaBridge | 165:d1b4690b3f8b | 2137 | #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2138 | #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2139 | #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2140 | #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2141 | #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2142 | #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2143 | #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2144 | #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2145 | #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2146 | #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2147 | #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2148 | #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2149 | #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2150 | #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2151 | #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2152 | #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2153 | #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2154 | #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2155 | #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2156 | #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2157 | #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2158 | #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2159 | #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2160 | #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2161 | #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2162 | #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2163 | #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2164 | #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2165 | #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2166 | #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2167 | #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2168 | #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2169 | #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2170 | #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2171 | #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2172 | #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2173 | #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2174 | #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2175 | #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2176 | #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2177 | #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2178 | #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2179 | #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2180 | #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2181 | #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2182 | #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2183 | #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2184 | #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2185 | #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2186 | #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2187 | #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2188 | #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2189 | #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2190 | #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2191 | #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2192 | #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2193 | #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2194 | #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2195 | #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2196 | #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2197 | #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2198 | #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2199 | #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2200 | #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2201 | #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2202 | #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2203 | #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2204 | #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2205 | #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2206 | #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2207 | #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2208 | #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2209 | #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2210 | #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2211 | #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2212 | #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2213 | #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2214 | #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2215 | #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2216 | #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2217 | #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2218 | #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2219 | #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2220 | #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2221 | #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2222 | #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2223 | #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2224 | #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2225 | #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2226 | #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2227 | #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2228 | #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2229 | #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2230 | #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2231 | #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2232 | #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2233 | #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2234 | #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2235 | #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2236 | #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2237 | #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2238 | #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2239 | #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2240 | #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2241 | #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2242 | #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2243 | #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2244 | #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2245 | #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2246 | #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2247 | #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2248 | #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2249 | #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2250 | #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2251 | #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2252 | #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2253 | #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2254 | #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2255 | #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2256 | #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2257 | #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2258 | #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2259 | #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2260 | #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2261 | #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2262 | #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2263 | #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2264 | #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2265 | #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2266 | #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2267 | #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2268 | #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2269 | #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2270 | #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2271 | #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2272 | #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2273 | #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2274 | #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2275 | #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2276 | #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2277 | #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2278 | #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2279 | #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2280 | #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2281 | #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2282 | #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2283 | #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2284 | #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2285 | #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2286 | #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2287 | #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2288 | #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2289 | #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2290 | #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2291 | #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2292 | #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2293 | #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2294 | #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2295 | #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2296 | #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2297 | #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2298 | #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2299 | #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2300 | #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2301 | #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2302 | #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2303 | #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2304 | #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2305 | #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2306 | #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2307 | #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2308 | #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2309 | #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2310 | #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2311 | #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2312 | #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2313 | #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2314 | #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2315 | #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2316 | #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2317 | #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2318 | #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2319 | #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2320 | #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2321 | #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2322 | #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2323 | #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2324 | #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2325 | #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2326 | #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2327 | #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2328 | #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2329 | #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2330 | #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2331 | #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2332 | #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2333 | #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2334 | #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2335 | #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2336 | #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2337 | #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2338 | #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2339 | #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2340 | #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2341 | #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2342 | #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2343 | #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2344 | #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2345 | #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2346 | #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2347 | #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2348 | #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2349 | #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2350 | #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2351 | #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2352 | #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2353 | #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2354 | #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2355 | #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2356 | #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2357 | #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2358 | #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2359 | #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2360 | #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2361 | #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2362 | #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2363 | #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2364 | #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2365 | #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2366 | #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2367 | #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2368 | #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2369 | #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2370 | #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2371 | #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2372 | #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2373 | #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2374 | #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2375 | #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2376 | #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2377 | #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE |
AnnaBridge | 165:d1b4690b3f8b | 2378 | #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE |
AnnaBridge | 165:d1b4690b3f8b | 2379 | |
AnnaBridge | 165:d1b4690b3f8b | 2380 | #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2381 | #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2382 | #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2383 | #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2384 | #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2385 | #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2386 | #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2387 | #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2388 | #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2389 | #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2390 | #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2391 | #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2392 | #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2393 | #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2394 | #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2395 | #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2396 | #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2397 | #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2398 | #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2399 | #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2400 | #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2401 | #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2402 | #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2403 | #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2404 | #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2405 | #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2406 | #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2407 | #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2408 | #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2409 | #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2410 | #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2411 | #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2412 | #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2413 | #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2414 | #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2415 | #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2416 | #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2417 | #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2418 | #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2419 | #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2420 | #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2421 | #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2422 | #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2423 | #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2424 | #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2425 | #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2426 | #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2427 | #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2428 | #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2429 | #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2430 | #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2431 | #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2432 | #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2433 | #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2434 | #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2435 | #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2436 | #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2437 | #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2438 | #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2439 | #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2440 | #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2441 | #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2442 | #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2443 | #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2444 | #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2445 | #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2446 | #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2447 | #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2448 | #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2449 | #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2450 | #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2451 | #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2452 | #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2453 | #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2454 | #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2455 | #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2456 | #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2457 | #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2458 | #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2459 | #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2460 | #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2461 | #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2462 | #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2463 | #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2464 | #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2465 | #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2466 | #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2467 | #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2468 | #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2469 | #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2470 | #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2471 | #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2472 | #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2473 | #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2474 | #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2475 | #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2476 | #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2477 | #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2478 | #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2479 | #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2480 | #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2481 | #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2482 | #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2483 | #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2484 | #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2485 | #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2486 | #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2487 | #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2488 | #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2489 | #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2490 | #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2491 | #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2492 | #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2493 | #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2494 | #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2495 | #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2496 | #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2497 | #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2498 | #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2499 | #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2500 | #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2501 | #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2502 | #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2503 | #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2504 | #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2505 | #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2506 | #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2507 | #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2508 | #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2509 | #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2510 | #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2511 | #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2512 | #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2513 | #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2514 | #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2515 | #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2516 | #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2517 | #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2518 | #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2519 | #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2520 | #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2521 | #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2522 | #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2523 | #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2524 | #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2525 | #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2526 | #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2527 | |
AnnaBridge | 165:d1b4690b3f8b | 2528 | /* alias define maintained for legacy */ |
AnnaBridge | 165:d1b4690b3f8b | 2529 | #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2530 | #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2531 | |
AnnaBridge | 165:d1b4690b3f8b | 2532 | #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2533 | #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2534 | #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2535 | #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2536 | #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2537 | #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2538 | #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2539 | #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2540 | #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2541 | #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2542 | #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2543 | #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2544 | #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2545 | #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2546 | #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2547 | #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2548 | #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2549 | #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2550 | #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2551 | #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2552 | |
AnnaBridge | 165:d1b4690b3f8b | 2553 | #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2554 | #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2555 | #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2556 | #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2557 | #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2558 | #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2559 | #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2560 | #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2561 | #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2562 | #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2563 | #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2564 | #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2565 | #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2566 | #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2567 | #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2568 | #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2569 | #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2570 | #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2571 | #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2572 | #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2573 | |
AnnaBridge | 165:d1b4690b3f8b | 2574 | #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2575 | #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2576 | #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2577 | #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2578 | #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2579 | #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2580 | #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2581 | #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2582 | #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2583 | #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2584 | #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2585 | #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2586 | #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2587 | #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2588 | #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2589 | #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2590 | #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2591 | #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2592 | #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2593 | #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2594 | #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2595 | #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2596 | #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2597 | #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2598 | #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2599 | #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2600 | #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2601 | #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2602 | #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2603 | #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2604 | #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2605 | #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2606 | #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2607 | #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2608 | #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2609 | #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2610 | #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2611 | #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2612 | #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2613 | #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2614 | #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2615 | #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2616 | #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2617 | #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2618 | #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2619 | #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2620 | #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2621 | #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2622 | #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2623 | #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2624 | #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2625 | #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2626 | #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2627 | #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2628 | #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2629 | #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2630 | #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2631 | #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2632 | #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2633 | #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2634 | #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2635 | #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2636 | #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2637 | #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2638 | #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2639 | #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2640 | #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2641 | #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2642 | #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2643 | #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2644 | #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2645 | #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2646 | #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2647 | #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2648 | #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2649 | #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2650 | #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2651 | #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2652 | #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2653 | #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2654 | #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2655 | #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2656 | #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2657 | #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2658 | #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2659 | #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2660 | #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2661 | #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2662 | #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2663 | #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2664 | #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2665 | #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2666 | #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2667 | #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2668 | #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2669 | #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2670 | #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2671 | #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2672 | #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2673 | #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2674 | #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2675 | #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2676 | #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2677 | #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2678 | #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2679 | #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2680 | #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2681 | #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2682 | #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2683 | #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2684 | #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2685 | #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2686 | #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2687 | #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2688 | #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2689 | #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2690 | |
AnnaBridge | 165:d1b4690b3f8b | 2691 | #if defined(STM32F4) |
AnnaBridge | 165:d1b4690b3f8b | 2692 | #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2693 | #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2694 | #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2695 | #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2696 | #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2697 | #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2698 | #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2699 | #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2700 | #define Sdmmc1ClockSelection SdioClockSelection |
AnnaBridge | 165:d1b4690b3f8b | 2701 | #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO |
AnnaBridge | 165:d1b4690b3f8b | 2702 | #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 |
AnnaBridge | 165:d1b4690b3f8b | 2703 | #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK |
AnnaBridge | 165:d1b4690b3f8b | 2704 | #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG |
AnnaBridge | 165:d1b4690b3f8b | 2705 | #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE |
AnnaBridge | 165:d1b4690b3f8b | 2706 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 2707 | |
AnnaBridge | 165:d1b4690b3f8b | 2708 | #if defined(STM32F7) || defined(STM32L4) |
AnnaBridge | 165:d1b4690b3f8b | 2709 | #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2710 | #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2711 | #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2712 | #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2713 | #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2714 | #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2715 | #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2716 | #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2717 | #define SdioClockSelection Sdmmc1ClockSelection |
AnnaBridge | 165:d1b4690b3f8b | 2718 | #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 |
AnnaBridge | 165:d1b4690b3f8b | 2719 | #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG |
AnnaBridge | 165:d1b4690b3f8b | 2720 | #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE |
AnnaBridge | 165:d1b4690b3f8b | 2721 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 2722 | |
AnnaBridge | 165:d1b4690b3f8b | 2723 | #if defined(STM32F7) |
AnnaBridge | 165:d1b4690b3f8b | 2724 | #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 |
AnnaBridge | 165:d1b4690b3f8b | 2725 | #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK |
AnnaBridge | 165:d1b4690b3f8b | 2726 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 2727 | |
AnnaBridge | 165:d1b4690b3f8b | 2728 | #if defined(STM32H7) |
AnnaBridge | 165:d1b4690b3f8b | 2729 | #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() |
AnnaBridge | 165:d1b4690b3f8b | 2730 | #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() |
AnnaBridge | 165:d1b4690b3f8b | 2731 | #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() |
AnnaBridge | 165:d1b4690b3f8b | 2732 | #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() |
AnnaBridge | 165:d1b4690b3f8b | 2733 | #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() |
AnnaBridge | 165:d1b4690b3f8b | 2734 | #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() |
AnnaBridge | 165:d1b4690b3f8b | 2735 | #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() |
AnnaBridge | 165:d1b4690b3f8b | 2736 | #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() |
AnnaBridge | 165:d1b4690b3f8b | 2737 | #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() |
AnnaBridge | 165:d1b4690b3f8b | 2738 | #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() |
AnnaBridge | 165:d1b4690b3f8b | 2739 | |
AnnaBridge | 165:d1b4690b3f8b | 2740 | #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() |
AnnaBridge | 165:d1b4690b3f8b | 2741 | #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() |
AnnaBridge | 165:d1b4690b3f8b | 2742 | #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() |
AnnaBridge | 165:d1b4690b3f8b | 2743 | #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() |
AnnaBridge | 165:d1b4690b3f8b | 2744 | #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() |
AnnaBridge | 165:d1b4690b3f8b | 2745 | #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() |
AnnaBridge | 165:d1b4690b3f8b | 2746 | #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() |
AnnaBridge | 165:d1b4690b3f8b | 2747 | #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() |
AnnaBridge | 165:d1b4690b3f8b | 2748 | #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() |
AnnaBridge | 165:d1b4690b3f8b | 2749 | #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() |
AnnaBridge | 165:d1b4690b3f8b | 2750 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 2751 | |
AnnaBridge | 165:d1b4690b3f8b | 2752 | #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG |
AnnaBridge | 165:d1b4690b3f8b | 2753 | #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG |
AnnaBridge | 165:d1b4690b3f8b | 2754 | |
AnnaBridge | 165:d1b4690b3f8b | 2755 | #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE |
AnnaBridge | 165:d1b4690b3f8b | 2756 | |
AnnaBridge | 165:d1b4690b3f8b | 2757 | #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE |
AnnaBridge | 165:d1b4690b3f8b | 2758 | #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE |
AnnaBridge | 165:d1b4690b3f8b | 2759 | #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK |
AnnaBridge | 165:d1b4690b3f8b | 2760 | #define IS_RCC_HCLK_DIV IS_RCC_PCLK |
AnnaBridge | 165:d1b4690b3f8b | 2761 | #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK |
AnnaBridge | 165:d1b4690b3f8b | 2762 | |
AnnaBridge | 165:d1b4690b3f8b | 2763 | #define RCC_IT_HSI14 RCC_IT_HSI14RDY |
AnnaBridge | 165:d1b4690b3f8b | 2764 | |
AnnaBridge | 165:d1b4690b3f8b | 2765 | #define RCC_IT_CSSLSE RCC_IT_LSECSS |
AnnaBridge | 165:d1b4690b3f8b | 2766 | #define RCC_IT_CSSHSE RCC_IT_CSS |
AnnaBridge | 165:d1b4690b3f8b | 2767 | |
AnnaBridge | 165:d1b4690b3f8b | 2768 | #define RCC_PLLMUL_3 RCC_PLL_MUL3 |
AnnaBridge | 165:d1b4690b3f8b | 2769 | #define RCC_PLLMUL_4 RCC_PLL_MUL4 |
AnnaBridge | 165:d1b4690b3f8b | 2770 | #define RCC_PLLMUL_6 RCC_PLL_MUL6 |
AnnaBridge | 165:d1b4690b3f8b | 2771 | #define RCC_PLLMUL_8 RCC_PLL_MUL8 |
AnnaBridge | 165:d1b4690b3f8b | 2772 | #define RCC_PLLMUL_12 RCC_PLL_MUL12 |
AnnaBridge | 165:d1b4690b3f8b | 2773 | #define RCC_PLLMUL_16 RCC_PLL_MUL16 |
AnnaBridge | 165:d1b4690b3f8b | 2774 | #define RCC_PLLMUL_24 RCC_PLL_MUL24 |
AnnaBridge | 165:d1b4690b3f8b | 2775 | #define RCC_PLLMUL_32 RCC_PLL_MUL32 |
AnnaBridge | 165:d1b4690b3f8b | 2776 | #define RCC_PLLMUL_48 RCC_PLL_MUL48 |
AnnaBridge | 165:d1b4690b3f8b | 2777 | |
AnnaBridge | 165:d1b4690b3f8b | 2778 | #define RCC_PLLDIV_2 RCC_PLL_DIV2 |
AnnaBridge | 165:d1b4690b3f8b | 2779 | #define RCC_PLLDIV_3 RCC_PLL_DIV3 |
AnnaBridge | 165:d1b4690b3f8b | 2780 | #define RCC_PLLDIV_4 RCC_PLL_DIV4 |
AnnaBridge | 165:d1b4690b3f8b | 2781 | |
AnnaBridge | 165:d1b4690b3f8b | 2782 | #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE |
AnnaBridge | 165:d1b4690b3f8b | 2783 | #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG |
AnnaBridge | 165:d1b4690b3f8b | 2784 | #define RCC_MCO_NODIV RCC_MCODIV_1 |
AnnaBridge | 165:d1b4690b3f8b | 2785 | #define RCC_MCO_DIV1 RCC_MCODIV_1 |
AnnaBridge | 165:d1b4690b3f8b | 2786 | #define RCC_MCO_DIV2 RCC_MCODIV_2 |
AnnaBridge | 165:d1b4690b3f8b | 2787 | #define RCC_MCO_DIV4 RCC_MCODIV_4 |
AnnaBridge | 165:d1b4690b3f8b | 2788 | #define RCC_MCO_DIV8 RCC_MCODIV_8 |
AnnaBridge | 165:d1b4690b3f8b | 2789 | #define RCC_MCO_DIV16 RCC_MCODIV_16 |
AnnaBridge | 165:d1b4690b3f8b | 2790 | #define RCC_MCO_DIV32 RCC_MCODIV_32 |
AnnaBridge | 165:d1b4690b3f8b | 2791 | #define RCC_MCO_DIV64 RCC_MCODIV_64 |
AnnaBridge | 165:d1b4690b3f8b | 2792 | #define RCC_MCO_DIV128 RCC_MCODIV_128 |
AnnaBridge | 165:d1b4690b3f8b | 2793 | #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK |
AnnaBridge | 165:d1b4690b3f8b | 2794 | #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI |
AnnaBridge | 165:d1b4690b3f8b | 2795 | #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE |
AnnaBridge | 165:d1b4690b3f8b | 2796 | #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK |
AnnaBridge | 165:d1b4690b3f8b | 2797 | #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI |
AnnaBridge | 165:d1b4690b3f8b | 2798 | #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 |
AnnaBridge | 165:d1b4690b3f8b | 2799 | #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 |
AnnaBridge | 165:d1b4690b3f8b | 2800 | #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE |
AnnaBridge | 165:d1b4690b3f8b | 2801 | #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK |
AnnaBridge | 165:d1b4690b3f8b | 2802 | #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK |
AnnaBridge | 165:d1b4690b3f8b | 2803 | #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 |
AnnaBridge | 165:d1b4690b3f8b | 2804 | |
AnnaBridge | 165:d1b4690b3f8b | 2805 | #if defined(STM32L4) |
AnnaBridge | 165:d1b4690b3f8b | 2806 | #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE |
AnnaBridge | 165:d1b4690b3f8b | 2807 | #elif defined(STM32WB) || defined(STM32G0) |
AnnaBridge | 165:d1b4690b3f8b | 2808 | #else |
AnnaBridge | 165:d1b4690b3f8b | 2809 | #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK |
AnnaBridge | 165:d1b4690b3f8b | 2810 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 2811 | |
AnnaBridge | 165:d1b4690b3f8b | 2812 | #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 |
AnnaBridge | 165:d1b4690b3f8b | 2813 | #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL |
AnnaBridge | 165:d1b4690b3f8b | 2814 | #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI |
AnnaBridge | 165:d1b4690b3f8b | 2815 | #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL |
AnnaBridge | 165:d1b4690b3f8b | 2816 | #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL |
AnnaBridge | 165:d1b4690b3f8b | 2817 | #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 |
AnnaBridge | 165:d1b4690b3f8b | 2818 | #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 |
AnnaBridge | 165:d1b4690b3f8b | 2819 | #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 |
AnnaBridge | 165:d1b4690b3f8b | 2820 | |
AnnaBridge | 165:d1b4690b3f8b | 2821 | #define HSION_BitNumber RCC_HSION_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2822 | #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2823 | #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2824 | #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2825 | #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2826 | #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2827 | #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2828 | #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2829 | #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2830 | #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2831 | #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2832 | #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2833 | #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2834 | #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2835 | #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2836 | #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2837 | #define LSION_BitNumber RCC_LSION_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2838 | #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2839 | #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2840 | #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2841 | #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2842 | #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2843 | #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2844 | #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2845 | #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2846 | #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER |
AnnaBridge | 165:d1b4690b3f8b | 2847 | #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS |
AnnaBridge | 165:d1b4690b3f8b | 2848 | #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS |
AnnaBridge | 165:d1b4690b3f8b | 2849 | #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS |
AnnaBridge | 165:d1b4690b3f8b | 2850 | #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS |
AnnaBridge | 165:d1b4690b3f8b | 2851 | #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE |
AnnaBridge | 165:d1b4690b3f8b | 2852 | #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE |
AnnaBridge | 165:d1b4690b3f8b | 2853 | |
AnnaBridge | 165:d1b4690b3f8b | 2854 | #define CR_HSION_BB RCC_CR_HSION_BB |
AnnaBridge | 165:d1b4690b3f8b | 2855 | #define CR_CSSON_BB RCC_CR_CSSON_BB |
AnnaBridge | 165:d1b4690b3f8b | 2856 | #define CR_PLLON_BB RCC_CR_PLLON_BB |
AnnaBridge | 165:d1b4690b3f8b | 2857 | #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB |
AnnaBridge | 165:d1b4690b3f8b | 2858 | #define CR_MSION_BB RCC_CR_MSION_BB |
AnnaBridge | 165:d1b4690b3f8b | 2859 | #define CSR_LSION_BB RCC_CSR_LSION_BB |
AnnaBridge | 165:d1b4690b3f8b | 2860 | #define CSR_LSEON_BB RCC_CSR_LSEON_BB |
AnnaBridge | 165:d1b4690b3f8b | 2861 | #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB |
AnnaBridge | 165:d1b4690b3f8b | 2862 | #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB |
AnnaBridge | 165:d1b4690b3f8b | 2863 | #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB |
AnnaBridge | 165:d1b4690b3f8b | 2864 | #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB |
AnnaBridge | 165:d1b4690b3f8b | 2865 | #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB |
AnnaBridge | 165:d1b4690b3f8b | 2866 | #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB |
AnnaBridge | 165:d1b4690b3f8b | 2867 | #define CR_HSEON_BB RCC_CR_HSEON_BB |
AnnaBridge | 165:d1b4690b3f8b | 2868 | #define CSR_RMVF_BB RCC_CSR_RMVF_BB |
AnnaBridge | 165:d1b4690b3f8b | 2869 | #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB |
AnnaBridge | 165:d1b4690b3f8b | 2870 | #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB |
AnnaBridge | 165:d1b4690b3f8b | 2871 | |
AnnaBridge | 165:d1b4690b3f8b | 2872 | #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2873 | #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2874 | #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2875 | #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2876 | #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE |
AnnaBridge | 165:d1b4690b3f8b | 2877 | |
AnnaBridge | 165:d1b4690b3f8b | 2878 | #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT |
AnnaBridge | 165:d1b4690b3f8b | 2879 | |
AnnaBridge | 165:d1b4690b3f8b | 2880 | #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN |
AnnaBridge | 165:d1b4690b3f8b | 2881 | #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF |
AnnaBridge | 165:d1b4690b3f8b | 2882 | |
AnnaBridge | 165:d1b4690b3f8b | 2883 | #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 |
AnnaBridge | 165:d1b4690b3f8b | 2884 | #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ |
AnnaBridge | 165:d1b4690b3f8b | 2885 | #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP |
AnnaBridge | 165:d1b4690b3f8b | 2886 | #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ |
AnnaBridge | 165:d1b4690b3f8b | 2887 | #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE |
AnnaBridge | 165:d1b4690b3f8b | 2888 | #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 |
AnnaBridge | 165:d1b4690b3f8b | 2889 | |
AnnaBridge | 165:d1b4690b3f8b | 2890 | #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2891 | #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2892 | #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2893 | #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2894 | #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2895 | #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET |
AnnaBridge | 165:d1b4690b3f8b | 2896 | #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2897 | #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2898 | #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 2899 | #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 2900 | #define DfsdmClockSelection Dfsdm1ClockSelection |
AnnaBridge | 165:d1b4690b3f8b | 2901 | #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 |
AnnaBridge | 165:d1b4690b3f8b | 2902 | #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 |
AnnaBridge | 165:d1b4690b3f8b | 2903 | #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK |
AnnaBridge | 165:d1b4690b3f8b | 2904 | #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG |
AnnaBridge | 165:d1b4690b3f8b | 2905 | #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE |
AnnaBridge | 165:d1b4690b3f8b | 2906 | #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 |
AnnaBridge | 165:d1b4690b3f8b | 2907 | #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 |
AnnaBridge | 165:d1b4690b3f8b | 2908 | #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 |
AnnaBridge | 165:d1b4690b3f8b | 2909 | #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 |
AnnaBridge | 165:d1b4690b3f8b | 2910 | |
AnnaBridge | 165:d1b4690b3f8b | 2911 | #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 |
AnnaBridge | 165:d1b4690b3f8b | 2912 | #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 |
AnnaBridge | 165:d1b4690b3f8b | 2913 | #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 |
AnnaBridge | 165:d1b4690b3f8b | 2914 | #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 |
AnnaBridge | 165:d1b4690b3f8b | 2915 | #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 |
AnnaBridge | 165:d1b4690b3f8b | 2916 | #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 |
AnnaBridge | 165:d1b4690b3f8b | 2917 | #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 |
AnnaBridge | 165:d1b4690b3f8b | 2918 | |
AnnaBridge | 165:d1b4690b3f8b | 2919 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2920 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 2921 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2922 | |
AnnaBridge | 165:d1b4690b3f8b | 2923 | /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 2924 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 2925 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2926 | #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) |
AnnaBridge | 165:d1b4690b3f8b | 2927 | |
AnnaBridge | 165:d1b4690b3f8b | 2928 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2929 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 2930 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2931 | |
AnnaBridge | 165:d1b4690b3f8b | 2932 | /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 2933 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 2934 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2935 | #if defined (STM32G0) |
AnnaBridge | 165:d1b4690b3f8b | 2936 | #else |
AnnaBridge | 165:d1b4690b3f8b | 2937 | #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG |
AnnaBridge | 165:d1b4690b3f8b | 2938 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 2939 | #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT |
AnnaBridge | 165:d1b4690b3f8b | 2940 | #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT |
AnnaBridge | 165:d1b4690b3f8b | 2941 | |
AnnaBridge | 165:d1b4690b3f8b | 2942 | #if defined (STM32F1) |
AnnaBridge | 165:d1b4690b3f8b | 2943 | #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() |
AnnaBridge | 165:d1b4690b3f8b | 2944 | |
AnnaBridge | 165:d1b4690b3f8b | 2945 | #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() |
AnnaBridge | 165:d1b4690b3f8b | 2946 | |
AnnaBridge | 165:d1b4690b3f8b | 2947 | #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() |
AnnaBridge | 165:d1b4690b3f8b | 2948 | |
AnnaBridge | 165:d1b4690b3f8b | 2949 | #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() |
AnnaBridge | 165:d1b4690b3f8b | 2950 | |
AnnaBridge | 165:d1b4690b3f8b | 2951 | #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() |
AnnaBridge | 165:d1b4690b3f8b | 2952 | #else |
AnnaBridge | 165:d1b4690b3f8b | 2953 | #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 2954 | (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 2955 | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) |
AnnaBridge | 165:d1b4690b3f8b | 2956 | #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 2957 | (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 2958 | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) |
AnnaBridge | 165:d1b4690b3f8b | 2959 | #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 2960 | (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 2961 | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) |
AnnaBridge | 165:d1b4690b3f8b | 2962 | #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 2963 | (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ |
AnnaBridge | 165:d1b4690b3f8b | 2964 | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) |
AnnaBridge | 165:d1b4690b3f8b | 2965 | #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 2966 | (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ |
AnnaBridge | 165:d1b4690b3f8b | 2967 | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) |
AnnaBridge | 165:d1b4690b3f8b | 2968 | #endif /* STM32F1 */ |
AnnaBridge | 165:d1b4690b3f8b | 2969 | |
AnnaBridge | 165:d1b4690b3f8b | 2970 | #define IS_ALARM IS_RTC_ALARM |
AnnaBridge | 165:d1b4690b3f8b | 2971 | #define IS_ALARM_MASK IS_RTC_ALARM_MASK |
AnnaBridge | 165:d1b4690b3f8b | 2972 | #define IS_TAMPER IS_RTC_TAMPER |
AnnaBridge | 165:d1b4690b3f8b | 2973 | #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE |
AnnaBridge | 165:d1b4690b3f8b | 2974 | #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER |
AnnaBridge | 165:d1b4690b3f8b | 2975 | #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT |
AnnaBridge | 165:d1b4690b3f8b | 2976 | #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE |
AnnaBridge | 165:d1b4690b3f8b | 2977 | #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION |
AnnaBridge | 165:d1b4690b3f8b | 2978 | #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE |
AnnaBridge | 165:d1b4690b3f8b | 2979 | #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ |
AnnaBridge | 165:d1b4690b3f8b | 2980 | #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION |
AnnaBridge | 165:d1b4690b3f8b | 2981 | #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER |
AnnaBridge | 165:d1b4690b3f8b | 2982 | #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK |
AnnaBridge | 165:d1b4690b3f8b | 2983 | #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER |
AnnaBridge | 165:d1b4690b3f8b | 2984 | |
AnnaBridge | 165:d1b4690b3f8b | 2985 | #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 2986 | #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 2987 | |
AnnaBridge | 165:d1b4690b3f8b | 2988 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2989 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 2990 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2991 | |
AnnaBridge | 165:d1b4690b3f8b | 2992 | /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 2993 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 2994 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2995 | |
AnnaBridge | 165:d1b4690b3f8b | 2996 | #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE |
AnnaBridge | 165:d1b4690b3f8b | 2997 | #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS |
AnnaBridge | 165:d1b4690b3f8b | 2998 | |
AnnaBridge | 165:d1b4690b3f8b | 2999 | #if defined(STM32F4) || defined(STM32F2) |
AnnaBridge | 165:d1b4690b3f8b | 3000 | #define SD_SDMMC_DISABLED SD_SDIO_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 3001 | #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY |
AnnaBridge | 165:d1b4690b3f8b | 3002 | #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED |
AnnaBridge | 165:d1b4690b3f8b | 3003 | #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION |
AnnaBridge | 165:d1b4690b3f8b | 3004 | #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND |
AnnaBridge | 165:d1b4690b3f8b | 3005 | #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT |
AnnaBridge | 165:d1b4690b3f8b | 3006 | #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED |
AnnaBridge | 165:d1b4690b3f8b | 3007 | #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 3008 | #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 3009 | #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 3010 | #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL |
AnnaBridge | 165:d1b4690b3f8b | 3011 | #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT |
AnnaBridge | 165:d1b4690b3f8b | 3012 | #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT |
AnnaBridge | 165:d1b4690b3f8b | 3013 | #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG |
AnnaBridge | 165:d1b4690b3f8b | 3014 | #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG |
AnnaBridge | 165:d1b4690b3f8b | 3015 | #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT |
AnnaBridge | 165:d1b4690b3f8b | 3016 | #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT |
AnnaBridge | 165:d1b4690b3f8b | 3017 | #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS |
AnnaBridge | 165:d1b4690b3f8b | 3018 | #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT |
AnnaBridge | 165:d1b4690b3f8b | 3019 | #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND |
AnnaBridge | 165:d1b4690b3f8b | 3020 | /* alias CMSIS */ |
AnnaBridge | 165:d1b4690b3f8b | 3021 | #define SDMMC1_IRQn SDIO_IRQn |
AnnaBridge | 165:d1b4690b3f8b | 3022 | #define SDMMC1_IRQHandler SDIO_IRQHandler |
AnnaBridge | 165:d1b4690b3f8b | 3023 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 3024 | |
AnnaBridge | 165:d1b4690b3f8b | 3025 | #if defined(STM32F7) || defined(STM32L4) |
AnnaBridge | 165:d1b4690b3f8b | 3026 | #define SD_SDIO_DISABLED SD_SDMMC_DISABLED |
AnnaBridge | 165:d1b4690b3f8b | 3027 | #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY |
AnnaBridge | 165:d1b4690b3f8b | 3028 | #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED |
AnnaBridge | 165:d1b4690b3f8b | 3029 | #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION |
AnnaBridge | 165:d1b4690b3f8b | 3030 | #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND |
AnnaBridge | 165:d1b4690b3f8b | 3031 | #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT |
AnnaBridge | 165:d1b4690b3f8b | 3032 | #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED |
AnnaBridge | 165:d1b4690b3f8b | 3033 | #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 3034 | #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 3035 | #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 3036 | #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 3037 | #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT |
AnnaBridge | 165:d1b4690b3f8b | 3038 | #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT |
AnnaBridge | 165:d1b4690b3f8b | 3039 | #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG |
AnnaBridge | 165:d1b4690b3f8b | 3040 | #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG |
AnnaBridge | 165:d1b4690b3f8b | 3041 | #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT |
AnnaBridge | 165:d1b4690b3f8b | 3042 | #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT |
AnnaBridge | 165:d1b4690b3f8b | 3043 | #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS |
AnnaBridge | 165:d1b4690b3f8b | 3044 | #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT |
AnnaBridge | 165:d1b4690b3f8b | 3045 | #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND |
AnnaBridge | 165:d1b4690b3f8b | 3046 | /* alias CMSIS for compatibilities */ |
AnnaBridge | 165:d1b4690b3f8b | 3047 | #define SDIO_IRQn SDMMC1_IRQn |
AnnaBridge | 165:d1b4690b3f8b | 3048 | #define SDIO_IRQHandler SDMMC1_IRQHandler |
AnnaBridge | 165:d1b4690b3f8b | 3049 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 3050 | |
AnnaBridge | 165:d1b4690b3f8b | 3051 | #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) |
AnnaBridge | 165:d1b4690b3f8b | 3052 | #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef |
AnnaBridge | 165:d1b4690b3f8b | 3053 | #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef |
AnnaBridge | 165:d1b4690b3f8b | 3054 | #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef |
AnnaBridge | 165:d1b4690b3f8b | 3055 | #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef |
AnnaBridge | 165:d1b4690b3f8b | 3056 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 3057 | |
AnnaBridge | 165:d1b4690b3f8b | 3058 | #if defined(STM32H7) |
AnnaBridge | 165:d1b4690b3f8b | 3059 | #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback |
AnnaBridge | 165:d1b4690b3f8b | 3060 | #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback |
AnnaBridge | 165:d1b4690b3f8b | 3061 | #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback |
AnnaBridge | 165:d1b4690b3f8b | 3062 | #define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback |
AnnaBridge | 165:d1b4690b3f8b | 3063 | #define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback |
AnnaBridge | 165:d1b4690b3f8b | 3064 | #define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback |
AnnaBridge | 165:d1b4690b3f8b | 3065 | #define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback |
AnnaBridge | 165:d1b4690b3f8b | 3066 | #define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback |
AnnaBridge | 165:d1b4690b3f8b | 3067 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 3068 | /** |
AnnaBridge | 165:d1b4690b3f8b | 3069 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 3070 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3071 | |
AnnaBridge | 165:d1b4690b3f8b | 3072 | /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 3073 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 3074 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3075 | |
AnnaBridge | 165:d1b4690b3f8b | 3076 | #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT |
AnnaBridge | 165:d1b4690b3f8b | 3077 | #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT |
AnnaBridge | 165:d1b4690b3f8b | 3078 | #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 3079 | #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 3080 | #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 3081 | #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 3082 | |
AnnaBridge | 165:d1b4690b3f8b | 3083 | #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE |
AnnaBridge | 165:d1b4690b3f8b | 3084 | #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE |
AnnaBridge | 165:d1b4690b3f8b | 3085 | |
AnnaBridge | 165:d1b4690b3f8b | 3086 | #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE |
AnnaBridge | 165:d1b4690b3f8b | 3087 | |
AnnaBridge | 165:d1b4690b3f8b | 3088 | /** |
AnnaBridge | 165:d1b4690b3f8b | 3089 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 3090 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3091 | |
AnnaBridge | 165:d1b4690b3f8b | 3092 | /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 3093 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 3094 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3095 | #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 |
AnnaBridge | 165:d1b4690b3f8b | 3096 | #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 |
AnnaBridge | 165:d1b4690b3f8b | 3097 | #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START |
AnnaBridge | 165:d1b4690b3f8b | 3098 | #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH |
AnnaBridge | 165:d1b4690b3f8b | 3099 | #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR |
AnnaBridge | 165:d1b4690b3f8b | 3100 | #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE |
AnnaBridge | 165:d1b4690b3f8b | 3101 | #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE |
AnnaBridge | 165:d1b4690b3f8b | 3102 | #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED |
AnnaBridge | 165:d1b4690b3f8b | 3103 | /** |
AnnaBridge | 165:d1b4690b3f8b | 3104 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 3105 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3106 | |
AnnaBridge | 165:d1b4690b3f8b | 3107 | /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 3108 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 3109 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3110 | |
AnnaBridge | 165:d1b4690b3f8b | 3111 | #define __HAL_SPI_1LINE_TX SPI_1LINE_TX |
AnnaBridge | 165:d1b4690b3f8b | 3112 | #define __HAL_SPI_1LINE_RX SPI_1LINE_RX |
AnnaBridge | 165:d1b4690b3f8b | 3113 | #define __HAL_SPI_RESET_CRC SPI_RESET_CRC |
AnnaBridge | 165:d1b4690b3f8b | 3114 | |
AnnaBridge | 165:d1b4690b3f8b | 3115 | /** |
AnnaBridge | 165:d1b4690b3f8b | 3116 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 3117 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3118 | |
AnnaBridge | 165:d1b4690b3f8b | 3119 | /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 3120 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 3121 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3122 | |
AnnaBridge | 165:d1b4690b3f8b | 3123 | #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE |
AnnaBridge | 165:d1b4690b3f8b | 3124 | #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION |
AnnaBridge | 165:d1b4690b3f8b | 3125 | #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE |
AnnaBridge | 165:d1b4690b3f8b | 3126 | #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION |
AnnaBridge | 165:d1b4690b3f8b | 3127 | |
AnnaBridge | 165:d1b4690b3f8b | 3128 | #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD |
AnnaBridge | 165:d1b4690b3f8b | 3129 | |
AnnaBridge | 165:d1b4690b3f8b | 3130 | #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE |
AnnaBridge | 165:d1b4690b3f8b | 3131 | #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE |
AnnaBridge | 165:d1b4690b3f8b | 3132 | |
AnnaBridge | 165:d1b4690b3f8b | 3133 | /** |
AnnaBridge | 165:d1b4690b3f8b | 3134 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 3135 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3136 | |
AnnaBridge | 165:d1b4690b3f8b | 3137 | |
AnnaBridge | 165:d1b4690b3f8b | 3138 | /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 3139 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 3140 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3141 | |
AnnaBridge | 165:d1b4690b3f8b | 3142 | #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT |
AnnaBridge | 165:d1b4690b3f8b | 3143 | #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT |
AnnaBridge | 165:d1b4690b3f8b | 3144 | #define __USART_ENABLE __HAL_USART_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 3145 | #define __USART_DISABLE __HAL_USART_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 3146 | |
AnnaBridge | 165:d1b4690b3f8b | 3147 | #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE |
AnnaBridge | 165:d1b4690b3f8b | 3148 | #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE |
AnnaBridge | 165:d1b4690b3f8b | 3149 | |
AnnaBridge | 165:d1b4690b3f8b | 3150 | /** |
AnnaBridge | 165:d1b4690b3f8b | 3151 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 3152 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3153 | |
AnnaBridge | 165:d1b4690b3f8b | 3154 | /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 3155 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 3156 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3157 | #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE |
AnnaBridge | 165:d1b4690b3f8b | 3158 | |
AnnaBridge | 165:d1b4690b3f8b | 3159 | #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 3160 | #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 3161 | #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 3162 | #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE |
AnnaBridge | 165:d1b4690b3f8b | 3163 | |
AnnaBridge | 165:d1b4690b3f8b | 3164 | #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 3165 | #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 3166 | #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 3167 | #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE |
AnnaBridge | 165:d1b4690b3f8b | 3168 | |
AnnaBridge | 165:d1b4690b3f8b | 3169 | #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT |
AnnaBridge | 165:d1b4690b3f8b | 3170 | #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT |
AnnaBridge | 165:d1b4690b3f8b | 3171 | #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG |
AnnaBridge | 165:d1b4690b3f8b | 3172 | #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG |
AnnaBridge | 165:d1b4690b3f8b | 3173 | #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 3174 | #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 3175 | #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 3176 | |
AnnaBridge | 165:d1b4690b3f8b | 3177 | #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT |
AnnaBridge | 165:d1b4690b3f8b | 3178 | #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT |
AnnaBridge | 165:d1b4690b3f8b | 3179 | #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG |
AnnaBridge | 165:d1b4690b3f8b | 3180 | #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG |
AnnaBridge | 165:d1b4690b3f8b | 3181 | #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 3182 | #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 3183 | #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 3184 | #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT |
AnnaBridge | 165:d1b4690b3f8b | 3185 | |
AnnaBridge | 165:d1b4690b3f8b | 3186 | #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT |
AnnaBridge | 165:d1b4690b3f8b | 3187 | #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT |
AnnaBridge | 165:d1b4690b3f8b | 3188 | #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG |
AnnaBridge | 165:d1b4690b3f8b | 3189 | #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG |
AnnaBridge | 165:d1b4690b3f8b | 3190 | #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 3191 | #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 3192 | #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE |
AnnaBridge | 165:d1b4690b3f8b | 3193 | #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT |
AnnaBridge | 165:d1b4690b3f8b | 3194 | |
AnnaBridge | 165:d1b4690b3f8b | 3195 | #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup |
AnnaBridge | 165:d1b4690b3f8b | 3196 | #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup |
AnnaBridge | 165:d1b4690b3f8b | 3197 | |
AnnaBridge | 165:d1b4690b3f8b | 3198 | #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo |
AnnaBridge | 165:d1b4690b3f8b | 3199 | #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo |
AnnaBridge | 165:d1b4690b3f8b | 3200 | /** |
AnnaBridge | 165:d1b4690b3f8b | 3201 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 3202 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3203 | |
AnnaBridge | 165:d1b4690b3f8b | 3204 | /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 3205 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 3206 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3207 | #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE |
AnnaBridge | 165:d1b4690b3f8b | 3208 | #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE |
AnnaBridge | 165:d1b4690b3f8b | 3209 | |
AnnaBridge | 165:d1b4690b3f8b | 3210 | #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE |
AnnaBridge | 165:d1b4690b3f8b | 3211 | #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT |
AnnaBridge | 165:d1b4690b3f8b | 3212 | |
AnnaBridge | 165:d1b4690b3f8b | 3213 | #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE |
AnnaBridge | 165:d1b4690b3f8b | 3214 | |
AnnaBridge | 165:d1b4690b3f8b | 3215 | #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN |
AnnaBridge | 165:d1b4690b3f8b | 3216 | #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER |
AnnaBridge | 165:d1b4690b3f8b | 3217 | #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER |
AnnaBridge | 165:d1b4690b3f8b | 3218 | #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER |
AnnaBridge | 165:d1b4690b3f8b | 3219 | #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD |
AnnaBridge | 165:d1b4690b3f8b | 3220 | #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD |
AnnaBridge | 165:d1b4690b3f8b | 3221 | #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION |
AnnaBridge | 165:d1b4690b3f8b | 3222 | #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION |
AnnaBridge | 165:d1b4690b3f8b | 3223 | #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER |
AnnaBridge | 165:d1b4690b3f8b | 3224 | #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER |
AnnaBridge | 165:d1b4690b3f8b | 3225 | #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE |
AnnaBridge | 165:d1b4690b3f8b | 3226 | #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE |
AnnaBridge | 165:d1b4690b3f8b | 3227 | |
AnnaBridge | 165:d1b4690b3f8b | 3228 | #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 |
AnnaBridge | 165:d1b4690b3f8b | 3229 | /** |
AnnaBridge | 165:d1b4690b3f8b | 3230 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 3231 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3232 | |
AnnaBridge | 165:d1b4690b3f8b | 3233 | /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 3234 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 3235 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3236 | |
AnnaBridge | 165:d1b4690b3f8b | 3237 | #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT |
AnnaBridge | 165:d1b4690b3f8b | 3238 | #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT |
AnnaBridge | 165:d1b4690b3f8b | 3239 | #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG |
AnnaBridge | 165:d1b4690b3f8b | 3240 | #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG |
AnnaBridge | 165:d1b4690b3f8b | 3241 | #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER |
AnnaBridge | 165:d1b4690b3f8b | 3242 | #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER |
AnnaBridge | 165:d1b4690b3f8b | 3243 | #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER |
AnnaBridge | 165:d1b4690b3f8b | 3244 | |
AnnaBridge | 165:d1b4690b3f8b | 3245 | #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 3246 | #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 3247 | #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE |
AnnaBridge | 165:d1b4690b3f8b | 3248 | /** |
AnnaBridge | 165:d1b4690b3f8b | 3249 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 3250 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3251 | |
AnnaBridge | 165:d1b4690b3f8b | 3252 | /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 3253 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 3254 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3255 | #define __HAL_LTDC_LAYER LTDC_LAYER |
AnnaBridge | 165:d1b4690b3f8b | 3256 | #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG |
AnnaBridge | 165:d1b4690b3f8b | 3257 | /** |
AnnaBridge | 165:d1b4690b3f8b | 3258 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 3259 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3260 | |
AnnaBridge | 165:d1b4690b3f8b | 3261 | /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 3262 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 3263 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3264 | #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 3265 | #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 3266 | #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 3267 | #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE |
AnnaBridge | 165:d1b4690b3f8b | 3268 | #define SAI_STREOMODE SAI_STEREOMODE |
AnnaBridge | 165:d1b4690b3f8b | 3269 | #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY |
AnnaBridge | 165:d1b4690b3f8b | 3270 | #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL |
AnnaBridge | 165:d1b4690b3f8b | 3271 | #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL |
AnnaBridge | 165:d1b4690b3f8b | 3272 | #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL |
AnnaBridge | 165:d1b4690b3f8b | 3273 | #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL |
AnnaBridge | 165:d1b4690b3f8b | 3274 | #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL |
AnnaBridge | 165:d1b4690b3f8b | 3275 | #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE |
AnnaBridge | 165:d1b4690b3f8b | 3276 | #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 |
AnnaBridge | 165:d1b4690b3f8b | 3277 | #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE |
AnnaBridge | 165:d1b4690b3f8b | 3278 | /** |
AnnaBridge | 165:d1b4690b3f8b | 3279 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 3280 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3281 | |
AnnaBridge | 165:d1b4690b3f8b | 3282 | /** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 3283 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 3284 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3285 | #if defined(STM32H7) |
AnnaBridge | 165:d1b4690b3f8b | 3286 | #define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow |
AnnaBridge | 165:d1b4690b3f8b | 3287 | #define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT |
AnnaBridge | 165:d1b4690b3f8b | 3288 | #define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA |
AnnaBridge | 165:d1b4690b3f8b | 3289 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 3290 | /** |
AnnaBridge | 165:d1b4690b3f8b | 3291 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 3292 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3293 | |
AnnaBridge | 165:d1b4690b3f8b | 3294 | /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose |
AnnaBridge | 165:d1b4690b3f8b | 3295 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 3296 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3297 | |
AnnaBridge | 165:d1b4690b3f8b | 3298 | /** |
AnnaBridge | 165:d1b4690b3f8b | 3299 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 3300 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3301 | |
AnnaBridge | 165:d1b4690b3f8b | 3302 | #ifdef __cplusplus |
AnnaBridge | 165:d1b4690b3f8b | 3303 | } |
AnnaBridge | 165:d1b4690b3f8b | 3304 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 3305 | |
AnnaBridge | 165:d1b4690b3f8b | 3306 | #endif /* ___STM32_HAL_LEGACY */ |
AnnaBridge | 165:d1b4690b3f8b | 3307 | |
AnnaBridge | 165:d1b4690b3f8b | 3308 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
AnnaBridge | 165:d1b4690b3f8b | 3309 |