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TARGET_NUCLEO_F091RC/TOOLCHAIN_IAR/stm32f0xx_ll_dma.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f0xx_ll_dma.h |
AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of DMA LL module. |
AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
AnnaBridge | 171:3a7713b1edbc | 8 | * |
AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
AnnaBridge | 171:3a7713b1edbc | 10 | * |
AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 32 | * |
AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 34 | */ |
AnnaBridge | 171:3a7713b1edbc | 35 | |
AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F0xx_LL_DMA_H |
AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F0xx_LL_DMA_H |
AnnaBridge | 171:3a7713b1edbc | 39 | |
AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
AnnaBridge | 171:3a7713b1edbc | 43 | |
AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f0xx.h" |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32F0xx_LL_Driver |
AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 49 | */ |
AnnaBridge | 171:3a7713b1edbc | 50 | |
AnnaBridge | 171:3a7713b1edbc | 51 | #if defined (DMA1) || defined (DMA2) |
AnnaBridge | 171:3a7713b1edbc | 52 | |
AnnaBridge | 171:3a7713b1edbc | 53 | /** @defgroup DMA_LL DMA |
AnnaBridge | 171:3a7713b1edbc | 54 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 55 | */ |
AnnaBridge | 171:3a7713b1edbc | 56 | |
AnnaBridge | 171:3a7713b1edbc | 57 | /* Private types -------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 58 | /* Private variables ---------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 59 | /** @defgroup DMA_LL_Private_Variables DMA Private Variables |
AnnaBridge | 171:3a7713b1edbc | 60 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 61 | */ |
AnnaBridge | 171:3a7713b1edbc | 62 | /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ |
AnnaBridge | 171:3a7713b1edbc | 63 | static const uint8_t CHANNEL_OFFSET_TAB[] = |
AnnaBridge | 171:3a7713b1edbc | 64 | { |
AnnaBridge | 171:3a7713b1edbc | 65 | (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), |
AnnaBridge | 171:3a7713b1edbc | 66 | (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), |
AnnaBridge | 171:3a7713b1edbc | 67 | (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), |
AnnaBridge | 171:3a7713b1edbc | 68 | (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), |
AnnaBridge | 171:3a7713b1edbc | 69 | (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), |
AnnaBridge | 171:3a7713b1edbc | 70 | #if defined(DMA1_Channel6) |
AnnaBridge | 171:3a7713b1edbc | 71 | (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), |
AnnaBridge | 171:3a7713b1edbc | 72 | #endif /*DMA1_Channel6*/ |
AnnaBridge | 171:3a7713b1edbc | 73 | #if defined(DMA1_Channel7) |
AnnaBridge | 171:3a7713b1edbc | 74 | (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) |
AnnaBridge | 171:3a7713b1edbc | 75 | #endif /*DMA1_Channel7*/ |
AnnaBridge | 171:3a7713b1edbc | 76 | }; |
AnnaBridge | 171:3a7713b1edbc | 77 | /** |
AnnaBridge | 171:3a7713b1edbc | 78 | * @} |
AnnaBridge | 171:3a7713b1edbc | 79 | */ |
AnnaBridge | 171:3a7713b1edbc | 80 | |
AnnaBridge | 171:3a7713b1edbc | 81 | /* Private constants ---------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 82 | /** @defgroup DMA_LL_Private_Constants DMA Private Constants |
AnnaBridge | 171:3a7713b1edbc | 83 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 84 | */ |
AnnaBridge | 171:3a7713b1edbc | 85 | /* Define used to get CSELR register offset */ |
AnnaBridge | 171:3a7713b1edbc | 86 | #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE) |
AnnaBridge | 171:3a7713b1edbc | 87 | |
AnnaBridge | 171:3a7713b1edbc | 88 | /* Defines used for the bit position in the register and perform offsets */ |
AnnaBridge | 171:3a7713b1edbc | 89 | #define DMA_POSITION_CSELR_CXS ((Channel-1U)*4U) |
AnnaBridge | 171:3a7713b1edbc | 90 | /** |
AnnaBridge | 171:3a7713b1edbc | 91 | * @} |
AnnaBridge | 171:3a7713b1edbc | 92 | */ |
AnnaBridge | 171:3a7713b1edbc | 93 | |
AnnaBridge | 171:3a7713b1edbc | 94 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 95 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 96 | /** @defgroup DMA_LL_Private_Macros DMA Private Macros |
AnnaBridge | 171:3a7713b1edbc | 97 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 98 | */ |
AnnaBridge | 171:3a7713b1edbc | 99 | /** |
AnnaBridge | 171:3a7713b1edbc | 100 | * @} |
AnnaBridge | 171:3a7713b1edbc | 101 | */ |
AnnaBridge | 171:3a7713b1edbc | 102 | #endif /*USE_FULL_LL_DRIVER*/ |
AnnaBridge | 171:3a7713b1edbc | 103 | |
AnnaBridge | 171:3a7713b1edbc | 104 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 105 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 106 | /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure |
AnnaBridge | 171:3a7713b1edbc | 107 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 108 | */ |
AnnaBridge | 171:3a7713b1edbc | 109 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 110 | { |
AnnaBridge | 171:3a7713b1edbc | 111 | uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer |
AnnaBridge | 171:3a7713b1edbc | 112 | or as Source base address in case of memory to memory transfer direction. |
AnnaBridge | 171:3a7713b1edbc | 113 | |
AnnaBridge | 171:3a7713b1edbc | 114 | This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ |
AnnaBridge | 171:3a7713b1edbc | 115 | |
AnnaBridge | 171:3a7713b1edbc | 116 | uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer |
AnnaBridge | 171:3a7713b1edbc | 117 | or as Destination base address in case of memory to memory transfer direction. |
AnnaBridge | 171:3a7713b1edbc | 118 | |
AnnaBridge | 171:3a7713b1edbc | 119 | This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ |
AnnaBridge | 171:3a7713b1edbc | 120 | |
AnnaBridge | 171:3a7713b1edbc | 121 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
AnnaBridge | 171:3a7713b1edbc | 122 | from memory to memory or from peripheral to memory. |
AnnaBridge | 171:3a7713b1edbc | 123 | This parameter can be a value of @ref DMA_LL_EC_DIRECTION |
AnnaBridge | 171:3a7713b1edbc | 124 | |
AnnaBridge | 171:3a7713b1edbc | 125 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ |
AnnaBridge | 171:3a7713b1edbc | 126 | |
AnnaBridge | 171:3a7713b1edbc | 127 | uint32_t Mode; /*!< Specifies the normal or circular operation mode. |
AnnaBridge | 171:3a7713b1edbc | 128 | This parameter can be a value of @ref DMA_LL_EC_MODE |
AnnaBridge | 171:3a7713b1edbc | 129 | @note: The circular buffer mode cannot be used if the memory to memory |
AnnaBridge | 171:3a7713b1edbc | 130 | data transfer direction is configured on the selected Channel |
AnnaBridge | 171:3a7713b1edbc | 131 | |
AnnaBridge | 171:3a7713b1edbc | 132 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ |
AnnaBridge | 171:3a7713b1edbc | 133 | |
AnnaBridge | 171:3a7713b1edbc | 134 | uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction |
AnnaBridge | 171:3a7713b1edbc | 135 | is incremented or not. |
AnnaBridge | 171:3a7713b1edbc | 136 | This parameter can be a value of @ref DMA_LL_EC_PERIPH |
AnnaBridge | 171:3a7713b1edbc | 137 | |
AnnaBridge | 171:3a7713b1edbc | 138 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ |
AnnaBridge | 171:3a7713b1edbc | 139 | |
AnnaBridge | 171:3a7713b1edbc | 140 | uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction |
AnnaBridge | 171:3a7713b1edbc | 141 | is incremented or not. |
AnnaBridge | 171:3a7713b1edbc | 142 | This parameter can be a value of @ref DMA_LL_EC_MEMORY |
AnnaBridge | 171:3a7713b1edbc | 143 | |
AnnaBridge | 171:3a7713b1edbc | 144 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ |
AnnaBridge | 171:3a7713b1edbc | 145 | |
AnnaBridge | 171:3a7713b1edbc | 146 | uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) |
AnnaBridge | 171:3a7713b1edbc | 147 | in case of memory to memory transfer direction. |
AnnaBridge | 171:3a7713b1edbc | 148 | This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN |
AnnaBridge | 171:3a7713b1edbc | 149 | |
AnnaBridge | 171:3a7713b1edbc | 150 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ |
AnnaBridge | 171:3a7713b1edbc | 151 | |
AnnaBridge | 171:3a7713b1edbc | 152 | uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) |
AnnaBridge | 171:3a7713b1edbc | 153 | in case of memory to memory transfer direction. |
AnnaBridge | 171:3a7713b1edbc | 154 | This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN |
AnnaBridge | 171:3a7713b1edbc | 155 | |
AnnaBridge | 171:3a7713b1edbc | 156 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ |
AnnaBridge | 171:3a7713b1edbc | 157 | |
AnnaBridge | 171:3a7713b1edbc | 158 | uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. |
AnnaBridge | 171:3a7713b1edbc | 159 | The data unit is equal to the source buffer configuration set in PeripheralSize |
AnnaBridge | 171:3a7713b1edbc | 160 | or MemorySize parameters depending in the transfer direction. |
AnnaBridge | 171:3a7713b1edbc | 161 | This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF |
AnnaBridge | 171:3a7713b1edbc | 162 | |
AnnaBridge | 171:3a7713b1edbc | 163 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ |
AnnaBridge | 171:3a7713b1edbc | 164 | #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) |
AnnaBridge | 171:3a7713b1edbc | 165 | |
AnnaBridge | 171:3a7713b1edbc | 166 | uint32_t PeriphRequest; /*!< Specifies the peripheral request. |
AnnaBridge | 171:3a7713b1edbc | 167 | This parameter can be a value of @ref DMA_LL_EC_REQUEST |
AnnaBridge | 171:3a7713b1edbc | 168 | |
AnnaBridge | 171:3a7713b1edbc | 169 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ |
AnnaBridge | 171:3a7713b1edbc | 170 | #endif |
AnnaBridge | 171:3a7713b1edbc | 171 | |
AnnaBridge | 171:3a7713b1edbc | 172 | uint32_t Priority; /*!< Specifies the channel priority level. |
AnnaBridge | 171:3a7713b1edbc | 173 | This parameter can be a value of @ref DMA_LL_EC_PRIORITY |
AnnaBridge | 171:3a7713b1edbc | 174 | |
AnnaBridge | 171:3a7713b1edbc | 175 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ |
AnnaBridge | 171:3a7713b1edbc | 176 | |
AnnaBridge | 171:3a7713b1edbc | 177 | } LL_DMA_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 178 | /** |
AnnaBridge | 171:3a7713b1edbc | 179 | * @} |
AnnaBridge | 171:3a7713b1edbc | 180 | */ |
AnnaBridge | 171:3a7713b1edbc | 181 | #endif /*USE_FULL_LL_DRIVER*/ |
AnnaBridge | 171:3a7713b1edbc | 182 | |
AnnaBridge | 171:3a7713b1edbc | 183 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 184 | /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants |
AnnaBridge | 171:3a7713b1edbc | 185 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 186 | */ |
AnnaBridge | 171:3a7713b1edbc | 187 | /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines |
AnnaBridge | 171:3a7713b1edbc | 188 | * @brief Flags defines which can be used with LL_DMA_WriteReg function |
AnnaBridge | 171:3a7713b1edbc | 189 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 190 | */ |
AnnaBridge | 171:3a7713b1edbc | 191 | #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ |
AnnaBridge | 171:3a7713b1edbc | 192 | #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ |
AnnaBridge | 171:3a7713b1edbc | 193 | #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ |
AnnaBridge | 171:3a7713b1edbc | 194 | #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ |
AnnaBridge | 171:3a7713b1edbc | 195 | #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ |
AnnaBridge | 171:3a7713b1edbc | 196 | #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ |
AnnaBridge | 171:3a7713b1edbc | 197 | #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ |
AnnaBridge | 171:3a7713b1edbc | 198 | #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ |
AnnaBridge | 171:3a7713b1edbc | 199 | #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ |
AnnaBridge | 171:3a7713b1edbc | 200 | #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ |
AnnaBridge | 171:3a7713b1edbc | 201 | #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ |
AnnaBridge | 171:3a7713b1edbc | 202 | #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ |
AnnaBridge | 171:3a7713b1edbc | 203 | #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ |
AnnaBridge | 171:3a7713b1edbc | 204 | #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ |
AnnaBridge | 171:3a7713b1edbc | 205 | #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ |
AnnaBridge | 171:3a7713b1edbc | 206 | #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ |
AnnaBridge | 171:3a7713b1edbc | 207 | #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ |
AnnaBridge | 171:3a7713b1edbc | 208 | #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ |
AnnaBridge | 171:3a7713b1edbc | 209 | #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ |
AnnaBridge | 171:3a7713b1edbc | 210 | #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ |
AnnaBridge | 171:3a7713b1edbc | 211 | #if defined(DMA1_Channel6) |
AnnaBridge | 171:3a7713b1edbc | 212 | #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ |
AnnaBridge | 171:3a7713b1edbc | 213 | #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ |
AnnaBridge | 171:3a7713b1edbc | 214 | #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ |
AnnaBridge | 171:3a7713b1edbc | 215 | #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ |
AnnaBridge | 171:3a7713b1edbc | 216 | #endif |
AnnaBridge | 171:3a7713b1edbc | 217 | #if defined(DMA1_Channel7) |
AnnaBridge | 171:3a7713b1edbc | 218 | #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ |
AnnaBridge | 171:3a7713b1edbc | 219 | #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ |
AnnaBridge | 171:3a7713b1edbc | 220 | #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ |
AnnaBridge | 171:3a7713b1edbc | 221 | #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ |
AnnaBridge | 171:3a7713b1edbc | 222 | #endif |
AnnaBridge | 171:3a7713b1edbc | 223 | /** |
AnnaBridge | 171:3a7713b1edbc | 224 | * @} |
AnnaBridge | 171:3a7713b1edbc | 225 | */ |
AnnaBridge | 171:3a7713b1edbc | 226 | |
AnnaBridge | 171:3a7713b1edbc | 227 | /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines |
AnnaBridge | 171:3a7713b1edbc | 228 | * @brief Flags defines which can be used with LL_DMA_ReadReg function |
AnnaBridge | 171:3a7713b1edbc | 229 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 230 | */ |
AnnaBridge | 171:3a7713b1edbc | 231 | #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ |
AnnaBridge | 171:3a7713b1edbc | 232 | #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ |
AnnaBridge | 171:3a7713b1edbc | 233 | #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ |
AnnaBridge | 171:3a7713b1edbc | 234 | #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ |
AnnaBridge | 171:3a7713b1edbc | 235 | #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ |
AnnaBridge | 171:3a7713b1edbc | 236 | #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ |
AnnaBridge | 171:3a7713b1edbc | 237 | #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ |
AnnaBridge | 171:3a7713b1edbc | 238 | #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ |
AnnaBridge | 171:3a7713b1edbc | 239 | #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ |
AnnaBridge | 171:3a7713b1edbc | 240 | #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ |
AnnaBridge | 171:3a7713b1edbc | 241 | #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ |
AnnaBridge | 171:3a7713b1edbc | 242 | #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ |
AnnaBridge | 171:3a7713b1edbc | 243 | #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ |
AnnaBridge | 171:3a7713b1edbc | 244 | #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ |
AnnaBridge | 171:3a7713b1edbc | 245 | #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ |
AnnaBridge | 171:3a7713b1edbc | 246 | #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ |
AnnaBridge | 171:3a7713b1edbc | 247 | #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ |
AnnaBridge | 171:3a7713b1edbc | 248 | #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ |
AnnaBridge | 171:3a7713b1edbc | 249 | #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ |
AnnaBridge | 171:3a7713b1edbc | 250 | #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ |
AnnaBridge | 171:3a7713b1edbc | 251 | #if defined(DMA1_Channel6) |
AnnaBridge | 171:3a7713b1edbc | 252 | #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ |
AnnaBridge | 171:3a7713b1edbc | 253 | #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ |
AnnaBridge | 171:3a7713b1edbc | 254 | #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ |
AnnaBridge | 171:3a7713b1edbc | 255 | #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ |
AnnaBridge | 171:3a7713b1edbc | 256 | #endif |
AnnaBridge | 171:3a7713b1edbc | 257 | #if defined(DMA1_Channel7) |
AnnaBridge | 171:3a7713b1edbc | 258 | #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ |
AnnaBridge | 171:3a7713b1edbc | 259 | #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ |
AnnaBridge | 171:3a7713b1edbc | 260 | #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ |
AnnaBridge | 171:3a7713b1edbc | 261 | #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ |
AnnaBridge | 171:3a7713b1edbc | 262 | #endif |
AnnaBridge | 171:3a7713b1edbc | 263 | /** |
AnnaBridge | 171:3a7713b1edbc | 264 | * @} |
AnnaBridge | 171:3a7713b1edbc | 265 | */ |
AnnaBridge | 171:3a7713b1edbc | 266 | |
AnnaBridge | 171:3a7713b1edbc | 267 | /** @defgroup DMA_LL_EC_IT IT Defines |
AnnaBridge | 171:3a7713b1edbc | 268 | * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions |
AnnaBridge | 171:3a7713b1edbc | 269 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 270 | */ |
AnnaBridge | 171:3a7713b1edbc | 271 | #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 272 | #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 273 | #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 274 | /** |
AnnaBridge | 171:3a7713b1edbc | 275 | * @} |
AnnaBridge | 171:3a7713b1edbc | 276 | */ |
AnnaBridge | 171:3a7713b1edbc | 277 | |
AnnaBridge | 171:3a7713b1edbc | 278 | /** @defgroup DMA_LL_EC_CHANNEL CHANNEL |
AnnaBridge | 171:3a7713b1edbc | 279 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 280 | */ |
AnnaBridge | 171:3a7713b1edbc | 281 | #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 282 | #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 283 | #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 284 | #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 285 | #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 286 | #if defined(DMA1_Channel6) |
AnnaBridge | 171:3a7713b1edbc | 287 | #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ |
AnnaBridge | 171:3a7713b1edbc | 288 | #endif |
AnnaBridge | 171:3a7713b1edbc | 289 | #if defined(DMA1_Channel7) |
AnnaBridge | 171:3a7713b1edbc | 290 | #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ |
AnnaBridge | 171:3a7713b1edbc | 291 | #endif |
AnnaBridge | 171:3a7713b1edbc | 292 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 293 | #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ |
AnnaBridge | 171:3a7713b1edbc | 294 | #endif /*USE_FULL_LL_DRIVER*/ |
AnnaBridge | 171:3a7713b1edbc | 295 | /** |
AnnaBridge | 171:3a7713b1edbc | 296 | * @} |
AnnaBridge | 171:3a7713b1edbc | 297 | */ |
AnnaBridge | 171:3a7713b1edbc | 298 | |
AnnaBridge | 171:3a7713b1edbc | 299 | /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction |
AnnaBridge | 171:3a7713b1edbc | 300 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 301 | */ |
AnnaBridge | 171:3a7713b1edbc | 302 | #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ |
AnnaBridge | 171:3a7713b1edbc | 303 | #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ |
AnnaBridge | 171:3a7713b1edbc | 304 | #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ |
AnnaBridge | 171:3a7713b1edbc | 305 | /** |
AnnaBridge | 171:3a7713b1edbc | 306 | * @} |
AnnaBridge | 171:3a7713b1edbc | 307 | */ |
AnnaBridge | 171:3a7713b1edbc | 308 | |
AnnaBridge | 171:3a7713b1edbc | 309 | /** @defgroup DMA_LL_EC_MODE Transfer mode |
AnnaBridge | 171:3a7713b1edbc | 310 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 311 | */ |
AnnaBridge | 171:3a7713b1edbc | 312 | #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ |
AnnaBridge | 171:3a7713b1edbc | 313 | #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ |
AnnaBridge | 171:3a7713b1edbc | 314 | /** |
AnnaBridge | 171:3a7713b1edbc | 315 | * @} |
AnnaBridge | 171:3a7713b1edbc | 316 | */ |
AnnaBridge | 171:3a7713b1edbc | 317 | |
AnnaBridge | 171:3a7713b1edbc | 318 | /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode |
AnnaBridge | 171:3a7713b1edbc | 319 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 320 | */ |
AnnaBridge | 171:3a7713b1edbc | 321 | #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ |
AnnaBridge | 171:3a7713b1edbc | 322 | #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ |
AnnaBridge | 171:3a7713b1edbc | 323 | /** |
AnnaBridge | 171:3a7713b1edbc | 324 | * @} |
AnnaBridge | 171:3a7713b1edbc | 325 | */ |
AnnaBridge | 171:3a7713b1edbc | 326 | |
AnnaBridge | 171:3a7713b1edbc | 327 | /** @defgroup DMA_LL_EC_MEMORY Memory increment mode |
AnnaBridge | 171:3a7713b1edbc | 328 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 329 | */ |
AnnaBridge | 171:3a7713b1edbc | 330 | #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ |
AnnaBridge | 171:3a7713b1edbc | 331 | #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ |
AnnaBridge | 171:3a7713b1edbc | 332 | /** |
AnnaBridge | 171:3a7713b1edbc | 333 | * @} |
AnnaBridge | 171:3a7713b1edbc | 334 | */ |
AnnaBridge | 171:3a7713b1edbc | 335 | |
AnnaBridge | 171:3a7713b1edbc | 336 | /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment |
AnnaBridge | 171:3a7713b1edbc | 337 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 338 | */ |
AnnaBridge | 171:3a7713b1edbc | 339 | #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ |
AnnaBridge | 171:3a7713b1edbc | 340 | #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ |
AnnaBridge | 171:3a7713b1edbc | 341 | #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ |
AnnaBridge | 171:3a7713b1edbc | 342 | /** |
AnnaBridge | 171:3a7713b1edbc | 343 | * @} |
AnnaBridge | 171:3a7713b1edbc | 344 | */ |
AnnaBridge | 171:3a7713b1edbc | 345 | |
AnnaBridge | 171:3a7713b1edbc | 346 | /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment |
AnnaBridge | 171:3a7713b1edbc | 347 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 348 | */ |
AnnaBridge | 171:3a7713b1edbc | 349 | #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ |
AnnaBridge | 171:3a7713b1edbc | 350 | #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ |
AnnaBridge | 171:3a7713b1edbc | 351 | #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ |
AnnaBridge | 171:3a7713b1edbc | 352 | /** |
AnnaBridge | 171:3a7713b1edbc | 353 | * @} |
AnnaBridge | 171:3a7713b1edbc | 354 | */ |
AnnaBridge | 171:3a7713b1edbc | 355 | |
AnnaBridge | 171:3a7713b1edbc | 356 | /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level |
AnnaBridge | 171:3a7713b1edbc | 357 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 358 | */ |
AnnaBridge | 171:3a7713b1edbc | 359 | #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ |
AnnaBridge | 171:3a7713b1edbc | 360 | #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ |
AnnaBridge | 171:3a7713b1edbc | 361 | #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ |
AnnaBridge | 171:3a7713b1edbc | 362 | #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ |
AnnaBridge | 171:3a7713b1edbc | 363 | /** |
AnnaBridge | 171:3a7713b1edbc | 364 | * @} |
AnnaBridge | 171:3a7713b1edbc | 365 | */ |
AnnaBridge | 171:3a7713b1edbc | 366 | |
AnnaBridge | 171:3a7713b1edbc | 367 | #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) |
AnnaBridge | 171:3a7713b1edbc | 368 | /** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request |
AnnaBridge | 171:3a7713b1edbc | 369 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 370 | */ |
AnnaBridge | 171:3a7713b1edbc | 371 | #define LL_DMA_REQUEST_0 0x00000000U /*!< DMA peripheral request 0 */ |
AnnaBridge | 171:3a7713b1edbc | 372 | #define LL_DMA_REQUEST_1 0x00000001U /*!< DMA peripheral request 1 */ |
AnnaBridge | 171:3a7713b1edbc | 373 | #define LL_DMA_REQUEST_2 0x00000002U /*!< DMA peripheral request 2 */ |
AnnaBridge | 171:3a7713b1edbc | 374 | #define LL_DMA_REQUEST_3 0x00000003U /*!< DMA peripheral request 3 */ |
AnnaBridge | 171:3a7713b1edbc | 375 | #define LL_DMA_REQUEST_4 0x00000004U /*!< DMA peripheral request 4 */ |
AnnaBridge | 171:3a7713b1edbc | 376 | #define LL_DMA_REQUEST_5 0x00000005U /*!< DMA peripheral request 5 */ |
AnnaBridge | 171:3a7713b1edbc | 377 | #define LL_DMA_REQUEST_6 0x00000006U /*!< DMA peripheral request 6 */ |
AnnaBridge | 171:3a7713b1edbc | 378 | #define LL_DMA_REQUEST_7 0x00000007U /*!< DMA peripheral request 7 */ |
AnnaBridge | 171:3a7713b1edbc | 379 | #define LL_DMA_REQUEST_8 0x00000008U /*!< DMA peripheral request 8 */ |
AnnaBridge | 171:3a7713b1edbc | 380 | #define LL_DMA_REQUEST_9 0x00000009U /*!< DMA peripheral request 9 */ |
AnnaBridge | 171:3a7713b1edbc | 381 | #define LL_DMA_REQUEST_10 0x0000000AU /*!< DMA peripheral request 10 */ |
AnnaBridge | 171:3a7713b1edbc | 382 | #define LL_DMA_REQUEST_11 0x0000000BU /*!< DMA peripheral request 11 */ |
AnnaBridge | 171:3a7713b1edbc | 383 | #define LL_DMA_REQUEST_12 0x0000000CU /*!< DMA peripheral request 12 */ |
AnnaBridge | 171:3a7713b1edbc | 384 | #define LL_DMA_REQUEST_13 0x0000000DU /*!< DMA peripheral request 13 */ |
AnnaBridge | 171:3a7713b1edbc | 385 | #define LL_DMA_REQUEST_14 0x0000000EU /*!< DMA peripheral request 14 */ |
AnnaBridge | 171:3a7713b1edbc | 386 | #define LL_DMA_REQUEST_15 0x0000000FU /*!< DMA peripheral request 15 */ |
AnnaBridge | 171:3a7713b1edbc | 387 | /** |
AnnaBridge | 171:3a7713b1edbc | 388 | * @} |
AnnaBridge | 171:3a7713b1edbc | 389 | */ |
AnnaBridge | 171:3a7713b1edbc | 390 | #endif |
AnnaBridge | 171:3a7713b1edbc | 391 | |
AnnaBridge | 171:3a7713b1edbc | 392 | /** |
AnnaBridge | 171:3a7713b1edbc | 393 | * @} |
AnnaBridge | 171:3a7713b1edbc | 394 | */ |
AnnaBridge | 171:3a7713b1edbc | 395 | |
AnnaBridge | 171:3a7713b1edbc | 396 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 397 | /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros |
AnnaBridge | 171:3a7713b1edbc | 398 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 399 | */ |
AnnaBridge | 171:3a7713b1edbc | 400 | |
AnnaBridge | 171:3a7713b1edbc | 401 | /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros |
AnnaBridge | 171:3a7713b1edbc | 402 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 403 | */ |
AnnaBridge | 171:3a7713b1edbc | 404 | /** |
AnnaBridge | 171:3a7713b1edbc | 405 | * @brief Write a value in DMA register |
AnnaBridge | 171:3a7713b1edbc | 406 | * @param __INSTANCE__ DMA Instance |
AnnaBridge | 171:3a7713b1edbc | 407 | * @param __REG__ Register to be written |
AnnaBridge | 171:3a7713b1edbc | 408 | * @param __VALUE__ Value to be written in the register |
AnnaBridge | 171:3a7713b1edbc | 409 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 410 | */ |
AnnaBridge | 171:3a7713b1edbc | 411 | #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
AnnaBridge | 171:3a7713b1edbc | 412 | |
AnnaBridge | 171:3a7713b1edbc | 413 | /** |
AnnaBridge | 171:3a7713b1edbc | 414 | * @brief Read a value in DMA register |
AnnaBridge | 171:3a7713b1edbc | 415 | * @param __INSTANCE__ DMA Instance |
AnnaBridge | 171:3a7713b1edbc | 416 | * @param __REG__ Register to be read |
AnnaBridge | 171:3a7713b1edbc | 417 | * @retval Register value |
AnnaBridge | 171:3a7713b1edbc | 418 | */ |
AnnaBridge | 171:3a7713b1edbc | 419 | #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
AnnaBridge | 171:3a7713b1edbc | 420 | /** |
AnnaBridge | 171:3a7713b1edbc | 421 | * @} |
AnnaBridge | 171:3a7713b1edbc | 422 | */ |
AnnaBridge | 171:3a7713b1edbc | 423 | |
AnnaBridge | 171:3a7713b1edbc | 424 | /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely |
AnnaBridge | 171:3a7713b1edbc | 425 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 426 | */ |
AnnaBridge | 171:3a7713b1edbc | 427 | /** |
AnnaBridge | 171:3a7713b1edbc | 428 | * @brief Convert DMAx_Channely into DMAx |
AnnaBridge | 171:3a7713b1edbc | 429 | * @param __CHANNEL_INSTANCE__ DMAx_Channely |
AnnaBridge | 171:3a7713b1edbc | 430 | * @retval DMAx |
AnnaBridge | 171:3a7713b1edbc | 431 | */ |
AnnaBridge | 171:3a7713b1edbc | 432 | #if defined(DMA2) |
AnnaBridge | 171:3a7713b1edbc | 433 | #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 434 | (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) |
AnnaBridge | 171:3a7713b1edbc | 435 | #else |
AnnaBridge | 171:3a7713b1edbc | 436 | #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) |
AnnaBridge | 171:3a7713b1edbc | 437 | #endif |
AnnaBridge | 171:3a7713b1edbc | 438 | |
AnnaBridge | 171:3a7713b1edbc | 439 | /** |
AnnaBridge | 171:3a7713b1edbc | 440 | * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y |
AnnaBridge | 171:3a7713b1edbc | 441 | * @param __CHANNEL_INSTANCE__ DMAx_Channely |
AnnaBridge | 171:3a7713b1edbc | 442 | * @retval LL_DMA_CHANNEL_y |
AnnaBridge | 171:3a7713b1edbc | 443 | */ |
AnnaBridge | 171:3a7713b1edbc | 444 | #if defined (DMA2) |
AnnaBridge | 171:3a7713b1edbc | 445 | #if defined (DMA2_Channel6) && defined (DMA2_Channel7) |
AnnaBridge | 171:3a7713b1edbc | 446 | #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 447 | (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ |
AnnaBridge | 171:3a7713b1edbc | 448 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ |
AnnaBridge | 171:3a7713b1edbc | 449 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ |
AnnaBridge | 171:3a7713b1edbc | 450 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ |
AnnaBridge | 171:3a7713b1edbc | 451 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ |
AnnaBridge | 171:3a7713b1edbc | 452 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ |
AnnaBridge | 171:3a7713b1edbc | 453 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ |
AnnaBridge | 171:3a7713b1edbc | 454 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ |
AnnaBridge | 171:3a7713b1edbc | 455 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ |
AnnaBridge | 171:3a7713b1edbc | 456 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ |
AnnaBridge | 171:3a7713b1edbc | 457 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ |
AnnaBridge | 171:3a7713b1edbc | 458 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \ |
AnnaBridge | 171:3a7713b1edbc | 459 | LL_DMA_CHANNEL_7) |
AnnaBridge | 171:3a7713b1edbc | 460 | #else |
AnnaBridge | 171:3a7713b1edbc | 461 | #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 462 | (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ |
AnnaBridge | 171:3a7713b1edbc | 463 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ |
AnnaBridge | 171:3a7713b1edbc | 464 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ |
AnnaBridge | 171:3a7713b1edbc | 465 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ |
AnnaBridge | 171:3a7713b1edbc | 466 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ |
AnnaBridge | 171:3a7713b1edbc | 467 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ |
AnnaBridge | 171:3a7713b1edbc | 468 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ |
AnnaBridge | 171:3a7713b1edbc | 469 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ |
AnnaBridge | 171:3a7713b1edbc | 470 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ |
AnnaBridge | 171:3a7713b1edbc | 471 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ |
AnnaBridge | 171:3a7713b1edbc | 472 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ |
AnnaBridge | 171:3a7713b1edbc | 473 | LL_DMA_CHANNEL_7) |
AnnaBridge | 171:3a7713b1edbc | 474 | #endif |
AnnaBridge | 171:3a7713b1edbc | 475 | #else |
AnnaBridge | 171:3a7713b1edbc | 476 | #if defined (DMA1_Channel6) && defined (DMA1_Channel7) |
AnnaBridge | 171:3a7713b1edbc | 477 | #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 478 | (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ |
AnnaBridge | 171:3a7713b1edbc | 479 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ |
AnnaBridge | 171:3a7713b1edbc | 480 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ |
AnnaBridge | 171:3a7713b1edbc | 481 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ |
AnnaBridge | 171:3a7713b1edbc | 482 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ |
AnnaBridge | 171:3a7713b1edbc | 483 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ |
AnnaBridge | 171:3a7713b1edbc | 484 | LL_DMA_CHANNEL_7) |
AnnaBridge | 171:3a7713b1edbc | 485 | #elif defined (DMA1_Channel6) |
AnnaBridge | 171:3a7713b1edbc | 486 | #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 487 | (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ |
AnnaBridge | 171:3a7713b1edbc | 488 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ |
AnnaBridge | 171:3a7713b1edbc | 489 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ |
AnnaBridge | 171:3a7713b1edbc | 490 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ |
AnnaBridge | 171:3a7713b1edbc | 491 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ |
AnnaBridge | 171:3a7713b1edbc | 492 | LL_DMA_CHANNEL_6) |
AnnaBridge | 171:3a7713b1edbc | 493 | #else |
AnnaBridge | 171:3a7713b1edbc | 494 | #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 495 | (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ |
AnnaBridge | 171:3a7713b1edbc | 496 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ |
AnnaBridge | 171:3a7713b1edbc | 497 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ |
AnnaBridge | 171:3a7713b1edbc | 498 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ |
AnnaBridge | 171:3a7713b1edbc | 499 | LL_DMA_CHANNEL_5) |
AnnaBridge | 171:3a7713b1edbc | 500 | #endif /* DMA1_Channel6 && DMA1_Channel7 */ |
AnnaBridge | 171:3a7713b1edbc | 501 | #endif |
AnnaBridge | 171:3a7713b1edbc | 502 | |
AnnaBridge | 171:3a7713b1edbc | 503 | /** |
AnnaBridge | 171:3a7713b1edbc | 504 | * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely |
AnnaBridge | 171:3a7713b1edbc | 505 | * @param __DMA_INSTANCE__ DMAx |
AnnaBridge | 171:3a7713b1edbc | 506 | * @param __CHANNEL__ LL_DMA_CHANNEL_y |
AnnaBridge | 171:3a7713b1edbc | 507 | * @retval DMAx_Channely |
AnnaBridge | 171:3a7713b1edbc | 508 | */ |
AnnaBridge | 171:3a7713b1edbc | 509 | #if defined (DMA2) |
AnnaBridge | 171:3a7713b1edbc | 510 | #if defined (DMA2_Channel6) && defined (DMA2_Channel7) |
AnnaBridge | 171:3a7713b1edbc | 511 | #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ |
AnnaBridge | 171:3a7713b1edbc | 512 | ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ |
AnnaBridge | 171:3a7713b1edbc | 513 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ |
AnnaBridge | 171:3a7713b1edbc | 514 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ |
AnnaBridge | 171:3a7713b1edbc | 515 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ |
AnnaBridge | 171:3a7713b1edbc | 516 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ |
AnnaBridge | 171:3a7713b1edbc | 517 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ |
AnnaBridge | 171:3a7713b1edbc | 518 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ |
AnnaBridge | 171:3a7713b1edbc | 519 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ |
AnnaBridge | 171:3a7713b1edbc | 520 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ |
AnnaBridge | 171:3a7713b1edbc | 521 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ |
AnnaBridge | 171:3a7713b1edbc | 522 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ |
AnnaBridge | 171:3a7713b1edbc | 523 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \ |
AnnaBridge | 171:3a7713b1edbc | 524 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \ |
AnnaBridge | 171:3a7713b1edbc | 525 | DMA2_Channel7) |
AnnaBridge | 171:3a7713b1edbc | 526 | #else |
AnnaBridge | 171:3a7713b1edbc | 527 | #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ |
AnnaBridge | 171:3a7713b1edbc | 528 | ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ |
AnnaBridge | 171:3a7713b1edbc | 529 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ |
AnnaBridge | 171:3a7713b1edbc | 530 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ |
AnnaBridge | 171:3a7713b1edbc | 531 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ |
AnnaBridge | 171:3a7713b1edbc | 532 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ |
AnnaBridge | 171:3a7713b1edbc | 533 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ |
AnnaBridge | 171:3a7713b1edbc | 534 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ |
AnnaBridge | 171:3a7713b1edbc | 535 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ |
AnnaBridge | 171:3a7713b1edbc | 536 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ |
AnnaBridge | 171:3a7713b1edbc | 537 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ |
AnnaBridge | 171:3a7713b1edbc | 538 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ |
AnnaBridge | 171:3a7713b1edbc | 539 | DMA1_Channel7) |
AnnaBridge | 171:3a7713b1edbc | 540 | #endif |
AnnaBridge | 171:3a7713b1edbc | 541 | #else |
AnnaBridge | 171:3a7713b1edbc | 542 | #if defined (DMA1_Channel6) && defined (DMA1_Channel7) |
AnnaBridge | 171:3a7713b1edbc | 543 | #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ |
AnnaBridge | 171:3a7713b1edbc | 544 | ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ |
AnnaBridge | 171:3a7713b1edbc | 545 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ |
AnnaBridge | 171:3a7713b1edbc | 546 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ |
AnnaBridge | 171:3a7713b1edbc | 547 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ |
AnnaBridge | 171:3a7713b1edbc | 548 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ |
AnnaBridge | 171:3a7713b1edbc | 549 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ |
AnnaBridge | 171:3a7713b1edbc | 550 | DMA1_Channel7) |
AnnaBridge | 171:3a7713b1edbc | 551 | #elif defined (DMA1_Channel6) |
AnnaBridge | 171:3a7713b1edbc | 552 | #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ |
AnnaBridge | 171:3a7713b1edbc | 553 | ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ |
AnnaBridge | 171:3a7713b1edbc | 554 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ |
AnnaBridge | 171:3a7713b1edbc | 555 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ |
AnnaBridge | 171:3a7713b1edbc | 556 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ |
AnnaBridge | 171:3a7713b1edbc | 557 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ |
AnnaBridge | 171:3a7713b1edbc | 558 | DMA1_Channel6) |
AnnaBridge | 171:3a7713b1edbc | 559 | #else |
AnnaBridge | 171:3a7713b1edbc | 560 | #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ |
AnnaBridge | 171:3a7713b1edbc | 561 | ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ |
AnnaBridge | 171:3a7713b1edbc | 562 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ |
AnnaBridge | 171:3a7713b1edbc | 563 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ |
AnnaBridge | 171:3a7713b1edbc | 564 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ |
AnnaBridge | 171:3a7713b1edbc | 565 | DMA1_Channel5) |
AnnaBridge | 171:3a7713b1edbc | 566 | #endif /* DMA1_Channel6 && DMA1_Channel7 */ |
AnnaBridge | 171:3a7713b1edbc | 567 | #endif |
AnnaBridge | 171:3a7713b1edbc | 568 | |
AnnaBridge | 171:3a7713b1edbc | 569 | /** |
AnnaBridge | 171:3a7713b1edbc | 570 | * @} |
AnnaBridge | 171:3a7713b1edbc | 571 | */ |
AnnaBridge | 171:3a7713b1edbc | 572 | |
AnnaBridge | 171:3a7713b1edbc | 573 | /** |
AnnaBridge | 171:3a7713b1edbc | 574 | * @} |
AnnaBridge | 171:3a7713b1edbc | 575 | */ |
AnnaBridge | 171:3a7713b1edbc | 576 | |
AnnaBridge | 171:3a7713b1edbc | 577 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 578 | /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions |
AnnaBridge | 171:3a7713b1edbc | 579 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 580 | */ |
AnnaBridge | 171:3a7713b1edbc | 581 | |
AnnaBridge | 171:3a7713b1edbc | 582 | /** @defgroup DMA_LL_EF_Configuration Configuration |
AnnaBridge | 171:3a7713b1edbc | 583 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 584 | */ |
AnnaBridge | 171:3a7713b1edbc | 585 | /** |
AnnaBridge | 171:3a7713b1edbc | 586 | * @brief Enable DMA channel. |
AnnaBridge | 171:3a7713b1edbc | 587 | * @rmtoll CCR EN LL_DMA_EnableChannel |
AnnaBridge | 171:3a7713b1edbc | 588 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 589 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 590 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 591 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 592 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 593 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 594 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 595 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 596 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 597 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 598 | */ |
AnnaBridge | 171:3a7713b1edbc | 599 | __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 600 | { |
AnnaBridge | 171:3a7713b1edbc | 601 | SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); |
AnnaBridge | 171:3a7713b1edbc | 602 | } |
AnnaBridge | 171:3a7713b1edbc | 603 | |
AnnaBridge | 171:3a7713b1edbc | 604 | /** |
AnnaBridge | 171:3a7713b1edbc | 605 | * @brief Disable DMA channel. |
AnnaBridge | 171:3a7713b1edbc | 606 | * @rmtoll CCR EN LL_DMA_DisableChannel |
AnnaBridge | 171:3a7713b1edbc | 607 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 608 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 609 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 610 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 611 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 612 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 613 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 614 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 615 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 616 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 617 | */ |
AnnaBridge | 171:3a7713b1edbc | 618 | __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 619 | { |
AnnaBridge | 171:3a7713b1edbc | 620 | CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); |
AnnaBridge | 171:3a7713b1edbc | 621 | } |
AnnaBridge | 171:3a7713b1edbc | 622 | |
AnnaBridge | 171:3a7713b1edbc | 623 | /** |
AnnaBridge | 171:3a7713b1edbc | 624 | * @brief Check if DMA channel is enabled or disabled. |
AnnaBridge | 171:3a7713b1edbc | 625 | * @rmtoll CCR EN LL_DMA_IsEnabledChannel |
AnnaBridge | 171:3a7713b1edbc | 626 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 627 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 628 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 629 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 630 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 631 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 632 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 633 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 634 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 635 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 636 | */ |
AnnaBridge | 171:3a7713b1edbc | 637 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 638 | { |
AnnaBridge | 171:3a7713b1edbc | 639 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 171:3a7713b1edbc | 640 | DMA_CCR_EN) == (DMA_CCR_EN)); |
AnnaBridge | 171:3a7713b1edbc | 641 | } |
AnnaBridge | 171:3a7713b1edbc | 642 | |
AnnaBridge | 171:3a7713b1edbc | 643 | /** |
AnnaBridge | 171:3a7713b1edbc | 644 | * @brief Configure all parameters link to DMA transfer. |
AnnaBridge | 171:3a7713b1edbc | 645 | * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n |
AnnaBridge | 171:3a7713b1edbc | 646 | * CCR MEM2MEM LL_DMA_ConfigTransfer\n |
AnnaBridge | 171:3a7713b1edbc | 647 | * CCR CIRC LL_DMA_ConfigTransfer\n |
AnnaBridge | 171:3a7713b1edbc | 648 | * CCR PINC LL_DMA_ConfigTransfer\n |
AnnaBridge | 171:3a7713b1edbc | 649 | * CCR MINC LL_DMA_ConfigTransfer\n |
AnnaBridge | 171:3a7713b1edbc | 650 | * CCR PSIZE LL_DMA_ConfigTransfer\n |
AnnaBridge | 171:3a7713b1edbc | 651 | * CCR MSIZE LL_DMA_ConfigTransfer\n |
AnnaBridge | 171:3a7713b1edbc | 652 | * CCR PL LL_DMA_ConfigTransfer |
AnnaBridge | 171:3a7713b1edbc | 653 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 654 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 655 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 656 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 657 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 658 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 659 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 660 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 661 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 662 | * @param Configuration This parameter must be a combination of all the following values: |
AnnaBridge | 171:3a7713b1edbc | 663 | * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY |
AnnaBridge | 171:3a7713b1edbc | 664 | * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR |
AnnaBridge | 171:3a7713b1edbc | 665 | * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT |
AnnaBridge | 171:3a7713b1edbc | 666 | * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT |
AnnaBridge | 171:3a7713b1edbc | 667 | * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD |
AnnaBridge | 171:3a7713b1edbc | 668 | * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD |
AnnaBridge | 171:3a7713b1edbc | 669 | * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH |
AnnaBridge | 171:3a7713b1edbc | 670 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 671 | */ |
AnnaBridge | 171:3a7713b1edbc | 672 | __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) |
AnnaBridge | 171:3a7713b1edbc | 673 | { |
AnnaBridge | 171:3a7713b1edbc | 674 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 171:3a7713b1edbc | 675 | DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, |
AnnaBridge | 171:3a7713b1edbc | 676 | Configuration); |
AnnaBridge | 171:3a7713b1edbc | 677 | } |
AnnaBridge | 171:3a7713b1edbc | 678 | |
AnnaBridge | 171:3a7713b1edbc | 679 | /** |
AnnaBridge | 171:3a7713b1edbc | 680 | * @brief Set Data transfer direction (read from peripheral or from memory). |
AnnaBridge | 171:3a7713b1edbc | 681 | * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n |
AnnaBridge | 171:3a7713b1edbc | 682 | * CCR MEM2MEM LL_DMA_SetDataTransferDirection |
AnnaBridge | 171:3a7713b1edbc | 683 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 684 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 685 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 686 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 687 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 688 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 689 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 690 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 691 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 692 | * @param Direction This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 693 | * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY |
AnnaBridge | 171:3a7713b1edbc | 694 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH |
AnnaBridge | 171:3a7713b1edbc | 695 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY |
AnnaBridge | 171:3a7713b1edbc | 696 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 697 | */ |
AnnaBridge | 171:3a7713b1edbc | 698 | __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) |
AnnaBridge | 171:3a7713b1edbc | 699 | { |
AnnaBridge | 171:3a7713b1edbc | 700 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 171:3a7713b1edbc | 701 | DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); |
AnnaBridge | 171:3a7713b1edbc | 702 | } |
AnnaBridge | 171:3a7713b1edbc | 703 | |
AnnaBridge | 171:3a7713b1edbc | 704 | /** |
AnnaBridge | 171:3a7713b1edbc | 705 | * @brief Get Data transfer direction (read from peripheral or from memory). |
AnnaBridge | 171:3a7713b1edbc | 706 | * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n |
AnnaBridge | 171:3a7713b1edbc | 707 | * CCR MEM2MEM LL_DMA_GetDataTransferDirection |
AnnaBridge | 171:3a7713b1edbc | 708 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 709 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 710 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 711 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 712 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 713 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 714 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 715 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 716 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 717 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 718 | * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY |
AnnaBridge | 171:3a7713b1edbc | 719 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH |
AnnaBridge | 171:3a7713b1edbc | 720 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY |
AnnaBridge | 171:3a7713b1edbc | 721 | */ |
AnnaBridge | 171:3a7713b1edbc | 722 | __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 723 | { |
AnnaBridge | 171:3a7713b1edbc | 724 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 171:3a7713b1edbc | 725 | DMA_CCR_DIR | DMA_CCR_MEM2MEM)); |
AnnaBridge | 171:3a7713b1edbc | 726 | } |
AnnaBridge | 171:3a7713b1edbc | 727 | |
AnnaBridge | 171:3a7713b1edbc | 728 | /** |
AnnaBridge | 171:3a7713b1edbc | 729 | * @brief Set DMA mode circular or normal. |
AnnaBridge | 171:3a7713b1edbc | 730 | * @note The circular buffer mode cannot be used if the memory-to-memory |
AnnaBridge | 171:3a7713b1edbc | 731 | * data transfer is configured on the selected Channel. |
AnnaBridge | 171:3a7713b1edbc | 732 | * @rmtoll CCR CIRC LL_DMA_SetMode |
AnnaBridge | 171:3a7713b1edbc | 733 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 734 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 735 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 736 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 737 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 738 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 739 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 740 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 741 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 742 | * @param Mode This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 743 | * @arg @ref LL_DMA_MODE_NORMAL |
AnnaBridge | 171:3a7713b1edbc | 744 | * @arg @ref LL_DMA_MODE_CIRCULAR |
AnnaBridge | 171:3a7713b1edbc | 745 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 746 | */ |
AnnaBridge | 171:3a7713b1edbc | 747 | __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) |
AnnaBridge | 171:3a7713b1edbc | 748 | { |
AnnaBridge | 171:3a7713b1edbc | 749 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, |
AnnaBridge | 171:3a7713b1edbc | 750 | Mode); |
AnnaBridge | 171:3a7713b1edbc | 751 | } |
AnnaBridge | 171:3a7713b1edbc | 752 | |
AnnaBridge | 171:3a7713b1edbc | 753 | /** |
AnnaBridge | 171:3a7713b1edbc | 754 | * @brief Get DMA mode circular or normal. |
AnnaBridge | 171:3a7713b1edbc | 755 | * @rmtoll CCR CIRC LL_DMA_GetMode |
AnnaBridge | 171:3a7713b1edbc | 756 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 757 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 758 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 759 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 760 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 761 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 762 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 763 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 764 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 765 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 766 | * @arg @ref LL_DMA_MODE_NORMAL |
AnnaBridge | 171:3a7713b1edbc | 767 | * @arg @ref LL_DMA_MODE_CIRCULAR |
AnnaBridge | 171:3a7713b1edbc | 768 | */ |
AnnaBridge | 171:3a7713b1edbc | 769 | __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 770 | { |
AnnaBridge | 171:3a7713b1edbc | 771 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 171:3a7713b1edbc | 772 | DMA_CCR_CIRC)); |
AnnaBridge | 171:3a7713b1edbc | 773 | } |
AnnaBridge | 171:3a7713b1edbc | 774 | |
AnnaBridge | 171:3a7713b1edbc | 775 | /** |
AnnaBridge | 171:3a7713b1edbc | 776 | * @brief Set Peripheral increment mode. |
AnnaBridge | 171:3a7713b1edbc | 777 | * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode |
AnnaBridge | 171:3a7713b1edbc | 778 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 779 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 780 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 781 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 782 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 783 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 784 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 785 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 786 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 787 | * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 788 | * @arg @ref LL_DMA_PERIPH_INCREMENT |
AnnaBridge | 171:3a7713b1edbc | 789 | * @arg @ref LL_DMA_PERIPH_NOINCREMENT |
AnnaBridge | 171:3a7713b1edbc | 790 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 791 | */ |
AnnaBridge | 171:3a7713b1edbc | 792 | __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) |
AnnaBridge | 171:3a7713b1edbc | 793 | { |
AnnaBridge | 171:3a7713b1edbc | 794 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, |
AnnaBridge | 171:3a7713b1edbc | 795 | PeriphOrM2MSrcIncMode); |
AnnaBridge | 171:3a7713b1edbc | 796 | } |
AnnaBridge | 171:3a7713b1edbc | 797 | |
AnnaBridge | 171:3a7713b1edbc | 798 | /** |
AnnaBridge | 171:3a7713b1edbc | 799 | * @brief Get Peripheral increment mode. |
AnnaBridge | 171:3a7713b1edbc | 800 | * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode |
AnnaBridge | 171:3a7713b1edbc | 801 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 802 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 803 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 804 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 805 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 806 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 807 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 808 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 809 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 810 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 811 | * @arg @ref LL_DMA_PERIPH_INCREMENT |
AnnaBridge | 171:3a7713b1edbc | 812 | * @arg @ref LL_DMA_PERIPH_NOINCREMENT |
AnnaBridge | 171:3a7713b1edbc | 813 | */ |
AnnaBridge | 171:3a7713b1edbc | 814 | __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 815 | { |
AnnaBridge | 171:3a7713b1edbc | 816 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 171:3a7713b1edbc | 817 | DMA_CCR_PINC)); |
AnnaBridge | 171:3a7713b1edbc | 818 | } |
AnnaBridge | 171:3a7713b1edbc | 819 | |
AnnaBridge | 171:3a7713b1edbc | 820 | /** |
AnnaBridge | 171:3a7713b1edbc | 821 | * @brief Set Memory increment mode. |
AnnaBridge | 171:3a7713b1edbc | 822 | * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode |
AnnaBridge | 171:3a7713b1edbc | 823 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 824 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 825 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 826 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 827 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 828 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 829 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 830 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 831 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 832 | * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 833 | * @arg @ref LL_DMA_MEMORY_INCREMENT |
AnnaBridge | 171:3a7713b1edbc | 834 | * @arg @ref LL_DMA_MEMORY_NOINCREMENT |
AnnaBridge | 171:3a7713b1edbc | 835 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 836 | */ |
AnnaBridge | 171:3a7713b1edbc | 837 | __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) |
AnnaBridge | 171:3a7713b1edbc | 838 | { |
AnnaBridge | 171:3a7713b1edbc | 839 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, |
AnnaBridge | 171:3a7713b1edbc | 840 | MemoryOrM2MDstIncMode); |
AnnaBridge | 171:3a7713b1edbc | 841 | } |
AnnaBridge | 171:3a7713b1edbc | 842 | |
AnnaBridge | 171:3a7713b1edbc | 843 | /** |
AnnaBridge | 171:3a7713b1edbc | 844 | * @brief Get Memory increment mode. |
AnnaBridge | 171:3a7713b1edbc | 845 | * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode |
AnnaBridge | 171:3a7713b1edbc | 846 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 847 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 848 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 849 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 850 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 851 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 852 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 853 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 854 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 855 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 856 | * @arg @ref LL_DMA_MEMORY_INCREMENT |
AnnaBridge | 171:3a7713b1edbc | 857 | * @arg @ref LL_DMA_MEMORY_NOINCREMENT |
AnnaBridge | 171:3a7713b1edbc | 858 | */ |
AnnaBridge | 171:3a7713b1edbc | 859 | __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 860 | { |
AnnaBridge | 171:3a7713b1edbc | 861 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 171:3a7713b1edbc | 862 | DMA_CCR_MINC)); |
AnnaBridge | 171:3a7713b1edbc | 863 | } |
AnnaBridge | 171:3a7713b1edbc | 864 | |
AnnaBridge | 171:3a7713b1edbc | 865 | /** |
AnnaBridge | 171:3a7713b1edbc | 866 | * @brief Set Peripheral size. |
AnnaBridge | 171:3a7713b1edbc | 867 | * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize |
AnnaBridge | 171:3a7713b1edbc | 868 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 869 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 870 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 871 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 872 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 873 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 874 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 875 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 876 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 877 | * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 878 | * @arg @ref LL_DMA_PDATAALIGN_BYTE |
AnnaBridge | 171:3a7713b1edbc | 879 | * @arg @ref LL_DMA_PDATAALIGN_HALFWORD |
AnnaBridge | 171:3a7713b1edbc | 880 | * @arg @ref LL_DMA_PDATAALIGN_WORD |
AnnaBridge | 171:3a7713b1edbc | 881 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 882 | */ |
AnnaBridge | 171:3a7713b1edbc | 883 | __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) |
AnnaBridge | 171:3a7713b1edbc | 884 | { |
AnnaBridge | 171:3a7713b1edbc | 885 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, |
AnnaBridge | 171:3a7713b1edbc | 886 | PeriphOrM2MSrcDataSize); |
AnnaBridge | 171:3a7713b1edbc | 887 | } |
AnnaBridge | 171:3a7713b1edbc | 888 | |
AnnaBridge | 171:3a7713b1edbc | 889 | /** |
AnnaBridge | 171:3a7713b1edbc | 890 | * @brief Get Peripheral size. |
AnnaBridge | 171:3a7713b1edbc | 891 | * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize |
AnnaBridge | 171:3a7713b1edbc | 892 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 893 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 894 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 895 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 896 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 897 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 898 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 899 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 900 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 901 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 902 | * @arg @ref LL_DMA_PDATAALIGN_BYTE |
AnnaBridge | 171:3a7713b1edbc | 903 | * @arg @ref LL_DMA_PDATAALIGN_HALFWORD |
AnnaBridge | 171:3a7713b1edbc | 904 | * @arg @ref LL_DMA_PDATAALIGN_WORD |
AnnaBridge | 171:3a7713b1edbc | 905 | */ |
AnnaBridge | 171:3a7713b1edbc | 906 | __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 907 | { |
AnnaBridge | 171:3a7713b1edbc | 908 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 171:3a7713b1edbc | 909 | DMA_CCR_PSIZE)); |
AnnaBridge | 171:3a7713b1edbc | 910 | } |
AnnaBridge | 171:3a7713b1edbc | 911 | |
AnnaBridge | 171:3a7713b1edbc | 912 | /** |
AnnaBridge | 171:3a7713b1edbc | 913 | * @brief Set Memory size. |
AnnaBridge | 171:3a7713b1edbc | 914 | * @rmtoll CCR MSIZE LL_DMA_SetMemorySize |
AnnaBridge | 171:3a7713b1edbc | 915 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 916 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 917 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 918 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 919 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 920 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 921 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 922 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 923 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 924 | * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 925 | * @arg @ref LL_DMA_MDATAALIGN_BYTE |
AnnaBridge | 171:3a7713b1edbc | 926 | * @arg @ref LL_DMA_MDATAALIGN_HALFWORD |
AnnaBridge | 171:3a7713b1edbc | 927 | * @arg @ref LL_DMA_MDATAALIGN_WORD |
AnnaBridge | 171:3a7713b1edbc | 928 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 929 | */ |
AnnaBridge | 171:3a7713b1edbc | 930 | __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) |
AnnaBridge | 171:3a7713b1edbc | 931 | { |
AnnaBridge | 171:3a7713b1edbc | 932 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, |
AnnaBridge | 171:3a7713b1edbc | 933 | MemoryOrM2MDstDataSize); |
AnnaBridge | 171:3a7713b1edbc | 934 | } |
AnnaBridge | 171:3a7713b1edbc | 935 | |
AnnaBridge | 171:3a7713b1edbc | 936 | /** |
AnnaBridge | 171:3a7713b1edbc | 937 | * @brief Get Memory size. |
AnnaBridge | 171:3a7713b1edbc | 938 | * @rmtoll CCR MSIZE LL_DMA_GetMemorySize |
AnnaBridge | 171:3a7713b1edbc | 939 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 940 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 941 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 942 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 943 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 944 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 945 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 946 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 947 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 948 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 949 | * @arg @ref LL_DMA_MDATAALIGN_BYTE |
AnnaBridge | 171:3a7713b1edbc | 950 | * @arg @ref LL_DMA_MDATAALIGN_HALFWORD |
AnnaBridge | 171:3a7713b1edbc | 951 | * @arg @ref LL_DMA_MDATAALIGN_WORD |
AnnaBridge | 171:3a7713b1edbc | 952 | */ |
AnnaBridge | 171:3a7713b1edbc | 953 | __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 954 | { |
AnnaBridge | 171:3a7713b1edbc | 955 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 171:3a7713b1edbc | 956 | DMA_CCR_MSIZE)); |
AnnaBridge | 171:3a7713b1edbc | 957 | } |
AnnaBridge | 171:3a7713b1edbc | 958 | |
AnnaBridge | 171:3a7713b1edbc | 959 | /** |
AnnaBridge | 171:3a7713b1edbc | 960 | * @brief Set Channel priority level. |
AnnaBridge | 171:3a7713b1edbc | 961 | * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel |
AnnaBridge | 171:3a7713b1edbc | 962 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 963 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 964 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 965 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 966 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 967 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 968 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 969 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 970 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 971 | * @param Priority This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 972 | * @arg @ref LL_DMA_PRIORITY_LOW |
AnnaBridge | 171:3a7713b1edbc | 973 | * @arg @ref LL_DMA_PRIORITY_MEDIUM |
AnnaBridge | 171:3a7713b1edbc | 974 | * @arg @ref LL_DMA_PRIORITY_HIGH |
AnnaBridge | 171:3a7713b1edbc | 975 | * @arg @ref LL_DMA_PRIORITY_VERYHIGH |
AnnaBridge | 171:3a7713b1edbc | 976 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 977 | */ |
AnnaBridge | 171:3a7713b1edbc | 978 | __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) |
AnnaBridge | 171:3a7713b1edbc | 979 | { |
AnnaBridge | 171:3a7713b1edbc | 980 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, |
AnnaBridge | 171:3a7713b1edbc | 981 | Priority); |
AnnaBridge | 171:3a7713b1edbc | 982 | } |
AnnaBridge | 171:3a7713b1edbc | 983 | |
AnnaBridge | 171:3a7713b1edbc | 984 | /** |
AnnaBridge | 171:3a7713b1edbc | 985 | * @brief Get Channel priority level. |
AnnaBridge | 171:3a7713b1edbc | 986 | * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel |
AnnaBridge | 171:3a7713b1edbc | 987 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 988 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 989 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 990 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 991 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 992 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 993 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 994 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 995 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 996 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 997 | * @arg @ref LL_DMA_PRIORITY_LOW |
AnnaBridge | 171:3a7713b1edbc | 998 | * @arg @ref LL_DMA_PRIORITY_MEDIUM |
AnnaBridge | 171:3a7713b1edbc | 999 | * @arg @ref LL_DMA_PRIORITY_HIGH |
AnnaBridge | 171:3a7713b1edbc | 1000 | * @arg @ref LL_DMA_PRIORITY_VERYHIGH |
AnnaBridge | 171:3a7713b1edbc | 1001 | */ |
AnnaBridge | 171:3a7713b1edbc | 1002 | __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 1003 | { |
AnnaBridge | 171:3a7713b1edbc | 1004 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 171:3a7713b1edbc | 1005 | DMA_CCR_PL)); |
AnnaBridge | 171:3a7713b1edbc | 1006 | } |
AnnaBridge | 171:3a7713b1edbc | 1007 | |
AnnaBridge | 171:3a7713b1edbc | 1008 | /** |
AnnaBridge | 171:3a7713b1edbc | 1009 | * @brief Set Number of data to transfer. |
AnnaBridge | 171:3a7713b1edbc | 1010 | * @note This action has no effect if |
AnnaBridge | 171:3a7713b1edbc | 1011 | * channel is enabled. |
AnnaBridge | 171:3a7713b1edbc | 1012 | * @rmtoll CNDTR NDT LL_DMA_SetDataLength |
AnnaBridge | 171:3a7713b1edbc | 1013 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1014 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1015 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1016 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 1017 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 1018 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 1019 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 1020 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 1021 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 1022 | * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF |
AnnaBridge | 171:3a7713b1edbc | 1023 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1024 | */ |
AnnaBridge | 171:3a7713b1edbc | 1025 | __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) |
AnnaBridge | 171:3a7713b1edbc | 1026 | { |
AnnaBridge | 171:3a7713b1edbc | 1027 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, |
AnnaBridge | 171:3a7713b1edbc | 1028 | DMA_CNDTR_NDT, NbData); |
AnnaBridge | 171:3a7713b1edbc | 1029 | } |
AnnaBridge | 171:3a7713b1edbc | 1030 | |
AnnaBridge | 171:3a7713b1edbc | 1031 | /** |
AnnaBridge | 171:3a7713b1edbc | 1032 | * @brief Get Number of data to transfer. |
AnnaBridge | 171:3a7713b1edbc | 1033 | * @note Once the channel is enabled, the return value indicate the |
AnnaBridge | 171:3a7713b1edbc | 1034 | * remaining bytes to be transmitted. |
AnnaBridge | 171:3a7713b1edbc | 1035 | * @rmtoll CNDTR NDT LL_DMA_GetDataLength |
AnnaBridge | 171:3a7713b1edbc | 1036 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1037 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1038 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1039 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 1040 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 1041 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 1042 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 1043 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 1044 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 1045 | * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1046 | */ |
AnnaBridge | 171:3a7713b1edbc | 1047 | __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 1048 | { |
AnnaBridge | 171:3a7713b1edbc | 1049 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, |
AnnaBridge | 171:3a7713b1edbc | 1050 | DMA_CNDTR_NDT)); |
AnnaBridge | 171:3a7713b1edbc | 1051 | } |
AnnaBridge | 171:3a7713b1edbc | 1052 | |
AnnaBridge | 171:3a7713b1edbc | 1053 | /** |
AnnaBridge | 171:3a7713b1edbc | 1054 | * @brief Configure the Source and Destination addresses. |
AnnaBridge | 171:3a7713b1edbc | 1055 | * @note This API must not be called when the DMA channel is enabled. |
AnnaBridge | 171:3a7713b1edbc | 1056 | * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). |
AnnaBridge | 171:3a7713b1edbc | 1057 | * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n |
AnnaBridge | 171:3a7713b1edbc | 1058 | * CMAR MA LL_DMA_ConfigAddresses |
AnnaBridge | 171:3a7713b1edbc | 1059 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1060 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1061 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1062 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 1063 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 1064 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 1065 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 1066 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 1067 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 1068 | * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1069 | * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1070 | * @param Direction This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1071 | * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY |
AnnaBridge | 171:3a7713b1edbc | 1072 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH |
AnnaBridge | 171:3a7713b1edbc | 1073 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY |
AnnaBridge | 171:3a7713b1edbc | 1074 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1075 | */ |
AnnaBridge | 171:3a7713b1edbc | 1076 | __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, |
AnnaBridge | 171:3a7713b1edbc | 1077 | uint32_t DstAddress, uint32_t Direction) |
AnnaBridge | 171:3a7713b1edbc | 1078 | { |
AnnaBridge | 171:3a7713b1edbc | 1079 | /* Direction Memory to Periph */ |
AnnaBridge | 171:3a7713b1edbc | 1080 | if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) |
AnnaBridge | 171:3a7713b1edbc | 1081 | { |
AnnaBridge | 171:3a7713b1edbc | 1082 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); |
AnnaBridge | 171:3a7713b1edbc | 1083 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); |
AnnaBridge | 171:3a7713b1edbc | 1084 | } |
AnnaBridge | 171:3a7713b1edbc | 1085 | /* Direction Periph to Memory and Memory to Memory */ |
AnnaBridge | 171:3a7713b1edbc | 1086 | else |
AnnaBridge | 171:3a7713b1edbc | 1087 | { |
AnnaBridge | 171:3a7713b1edbc | 1088 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); |
AnnaBridge | 171:3a7713b1edbc | 1089 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); |
AnnaBridge | 171:3a7713b1edbc | 1090 | } |
AnnaBridge | 171:3a7713b1edbc | 1091 | } |
AnnaBridge | 171:3a7713b1edbc | 1092 | |
AnnaBridge | 171:3a7713b1edbc | 1093 | /** |
AnnaBridge | 171:3a7713b1edbc | 1094 | * @brief Set the Memory address. |
AnnaBridge | 171:3a7713b1edbc | 1095 | * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. |
AnnaBridge | 171:3a7713b1edbc | 1096 | * @note This API must not be called when the DMA channel is enabled. |
AnnaBridge | 171:3a7713b1edbc | 1097 | * @rmtoll CMAR MA LL_DMA_SetMemoryAddress |
AnnaBridge | 171:3a7713b1edbc | 1098 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1099 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1100 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1101 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 1102 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 1103 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 1104 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 1105 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 1106 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 1107 | * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1108 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1109 | */ |
AnnaBridge | 171:3a7713b1edbc | 1110 | __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) |
AnnaBridge | 171:3a7713b1edbc | 1111 | { |
AnnaBridge | 171:3a7713b1edbc | 1112 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); |
AnnaBridge | 171:3a7713b1edbc | 1113 | } |
AnnaBridge | 171:3a7713b1edbc | 1114 | |
AnnaBridge | 171:3a7713b1edbc | 1115 | /** |
AnnaBridge | 171:3a7713b1edbc | 1116 | * @brief Set the Peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 1117 | * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. |
AnnaBridge | 171:3a7713b1edbc | 1118 | * @note This API must not be called when the DMA channel is enabled. |
AnnaBridge | 171:3a7713b1edbc | 1119 | * @rmtoll CPAR PA LL_DMA_SetPeriphAddress |
AnnaBridge | 171:3a7713b1edbc | 1120 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1121 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1122 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1123 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 1124 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 1125 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 1126 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 1127 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 1128 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 1129 | * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1130 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1131 | */ |
AnnaBridge | 171:3a7713b1edbc | 1132 | __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) |
AnnaBridge | 171:3a7713b1edbc | 1133 | { |
AnnaBridge | 171:3a7713b1edbc | 1134 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); |
AnnaBridge | 171:3a7713b1edbc | 1135 | } |
AnnaBridge | 171:3a7713b1edbc | 1136 | |
AnnaBridge | 171:3a7713b1edbc | 1137 | /** |
AnnaBridge | 171:3a7713b1edbc | 1138 | * @brief Get Memory address. |
AnnaBridge | 171:3a7713b1edbc | 1139 | * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. |
AnnaBridge | 171:3a7713b1edbc | 1140 | * @rmtoll CMAR MA LL_DMA_GetMemoryAddress |
AnnaBridge | 171:3a7713b1edbc | 1141 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1142 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1143 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1144 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 1145 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 1146 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 1147 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 1148 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 1149 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 1150 | * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1151 | */ |
AnnaBridge | 171:3a7713b1edbc | 1152 | __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 1153 | { |
AnnaBridge | 171:3a7713b1edbc | 1154 | return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); |
AnnaBridge | 171:3a7713b1edbc | 1155 | } |
AnnaBridge | 171:3a7713b1edbc | 1156 | |
AnnaBridge | 171:3a7713b1edbc | 1157 | /** |
AnnaBridge | 171:3a7713b1edbc | 1158 | * @brief Get Peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 1159 | * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. |
AnnaBridge | 171:3a7713b1edbc | 1160 | * @rmtoll CPAR PA LL_DMA_GetPeriphAddress |
AnnaBridge | 171:3a7713b1edbc | 1161 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1162 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1163 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1164 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 1165 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 1166 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 1167 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 1168 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 1169 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 1170 | * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1171 | */ |
AnnaBridge | 171:3a7713b1edbc | 1172 | __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 1173 | { |
AnnaBridge | 171:3a7713b1edbc | 1174 | return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); |
AnnaBridge | 171:3a7713b1edbc | 1175 | } |
AnnaBridge | 171:3a7713b1edbc | 1176 | |
AnnaBridge | 171:3a7713b1edbc | 1177 | /** |
AnnaBridge | 171:3a7713b1edbc | 1178 | * @brief Set the Memory to Memory Source address. |
AnnaBridge | 171:3a7713b1edbc | 1179 | * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. |
AnnaBridge | 171:3a7713b1edbc | 1180 | * @note This API must not be called when the DMA channel is enabled. |
AnnaBridge | 171:3a7713b1edbc | 1181 | * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress |
AnnaBridge | 171:3a7713b1edbc | 1182 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1183 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1184 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1185 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 1186 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 1187 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 1188 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 1189 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 1190 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 1191 | * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1192 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1193 | */ |
AnnaBridge | 171:3a7713b1edbc | 1194 | __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) |
AnnaBridge | 171:3a7713b1edbc | 1195 | { |
AnnaBridge | 171:3a7713b1edbc | 1196 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); |
AnnaBridge | 171:3a7713b1edbc | 1197 | } |
AnnaBridge | 171:3a7713b1edbc | 1198 | |
AnnaBridge | 171:3a7713b1edbc | 1199 | /** |
AnnaBridge | 171:3a7713b1edbc | 1200 | * @brief Set the Memory to Memory Destination address. |
AnnaBridge | 171:3a7713b1edbc | 1201 | * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. |
AnnaBridge | 171:3a7713b1edbc | 1202 | * @note This API must not be called when the DMA channel is enabled. |
AnnaBridge | 171:3a7713b1edbc | 1203 | * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress |
AnnaBridge | 171:3a7713b1edbc | 1204 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1205 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1206 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1207 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 1208 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 1209 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 1210 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 1211 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 1212 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 1213 | * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1214 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1215 | */ |
AnnaBridge | 171:3a7713b1edbc | 1216 | __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) |
AnnaBridge | 171:3a7713b1edbc | 1217 | { |
AnnaBridge | 171:3a7713b1edbc | 1218 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); |
AnnaBridge | 171:3a7713b1edbc | 1219 | } |
AnnaBridge | 171:3a7713b1edbc | 1220 | |
AnnaBridge | 171:3a7713b1edbc | 1221 | /** |
AnnaBridge | 171:3a7713b1edbc | 1222 | * @brief Get the Memory to Memory Source address. |
AnnaBridge | 171:3a7713b1edbc | 1223 | * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. |
AnnaBridge | 171:3a7713b1edbc | 1224 | * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress |
AnnaBridge | 171:3a7713b1edbc | 1225 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1226 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1227 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1228 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 1229 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 1230 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 1231 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 1232 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 1233 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 1234 | * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1235 | */ |
AnnaBridge | 171:3a7713b1edbc | 1236 | __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 1237 | { |
AnnaBridge | 171:3a7713b1edbc | 1238 | return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); |
AnnaBridge | 171:3a7713b1edbc | 1239 | } |
AnnaBridge | 171:3a7713b1edbc | 1240 | |
AnnaBridge | 171:3a7713b1edbc | 1241 | /** |
AnnaBridge | 171:3a7713b1edbc | 1242 | * @brief Get the Memory to Memory Destination address. |
AnnaBridge | 171:3a7713b1edbc | 1243 | * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. |
AnnaBridge | 171:3a7713b1edbc | 1244 | * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress |
AnnaBridge | 171:3a7713b1edbc | 1245 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1246 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1247 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1248 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 1249 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 1250 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 1251 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 1252 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 1253 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 1254 | * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1255 | */ |
AnnaBridge | 171:3a7713b1edbc | 1256 | __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 1257 | { |
AnnaBridge | 171:3a7713b1edbc | 1258 | return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); |
AnnaBridge | 171:3a7713b1edbc | 1259 | } |
AnnaBridge | 171:3a7713b1edbc | 1260 | |
AnnaBridge | 171:3a7713b1edbc | 1261 | #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) |
AnnaBridge | 171:3a7713b1edbc | 1262 | /** |
AnnaBridge | 171:3a7713b1edbc | 1263 | * @brief Set DMA request for DMA instance on Channel x. |
AnnaBridge | 171:3a7713b1edbc | 1264 | * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection. |
AnnaBridge | 171:3a7713b1edbc | 1265 | * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n |
AnnaBridge | 171:3a7713b1edbc | 1266 | * CSELR C2S LL_DMA_SetPeriphRequest\n |
AnnaBridge | 171:3a7713b1edbc | 1267 | * CSELR C3S LL_DMA_SetPeriphRequest\n |
AnnaBridge | 171:3a7713b1edbc | 1268 | * CSELR C4S LL_DMA_SetPeriphRequest\n |
AnnaBridge | 171:3a7713b1edbc | 1269 | * CSELR C5S LL_DMA_SetPeriphRequest\n |
AnnaBridge | 171:3a7713b1edbc | 1270 | * CSELR C6S LL_DMA_SetPeriphRequest\n |
AnnaBridge | 171:3a7713b1edbc | 1271 | * CSELR C7S LL_DMA_SetPeriphRequest |
AnnaBridge | 171:3a7713b1edbc | 1272 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1273 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1274 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1275 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 1276 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 1277 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 1278 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 1279 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 1280 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 1281 | * @param PeriphRequest This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1282 | * @arg @ref LL_DMA_REQUEST_0 |
AnnaBridge | 171:3a7713b1edbc | 1283 | * @arg @ref LL_DMA_REQUEST_1 |
AnnaBridge | 171:3a7713b1edbc | 1284 | * @arg @ref LL_DMA_REQUEST_2 |
AnnaBridge | 171:3a7713b1edbc | 1285 | * @arg @ref LL_DMA_REQUEST_3 |
AnnaBridge | 171:3a7713b1edbc | 1286 | * @arg @ref LL_DMA_REQUEST_4 |
AnnaBridge | 171:3a7713b1edbc | 1287 | * @arg @ref LL_DMA_REQUEST_5 |
AnnaBridge | 171:3a7713b1edbc | 1288 | * @arg @ref LL_DMA_REQUEST_6 |
AnnaBridge | 171:3a7713b1edbc | 1289 | * @arg @ref LL_DMA_REQUEST_7 |
AnnaBridge | 171:3a7713b1edbc | 1290 | * @arg @ref LL_DMA_REQUEST_8 |
AnnaBridge | 171:3a7713b1edbc | 1291 | * @arg @ref LL_DMA_REQUEST_9 |
AnnaBridge | 171:3a7713b1edbc | 1292 | * @arg @ref LL_DMA_REQUEST_10 |
AnnaBridge | 171:3a7713b1edbc | 1293 | * @arg @ref LL_DMA_REQUEST_11 |
AnnaBridge | 171:3a7713b1edbc | 1294 | * @arg @ref LL_DMA_REQUEST_12 |
AnnaBridge | 171:3a7713b1edbc | 1295 | * @arg @ref LL_DMA_REQUEST_13 |
AnnaBridge | 171:3a7713b1edbc | 1296 | * @arg @ref LL_DMA_REQUEST_14 |
AnnaBridge | 171:3a7713b1edbc | 1297 | * @arg @ref LL_DMA_REQUEST_15 |
AnnaBridge | 171:3a7713b1edbc | 1298 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1299 | */ |
AnnaBridge | 171:3a7713b1edbc | 1300 | __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest) |
AnnaBridge | 171:3a7713b1edbc | 1301 | { |
AnnaBridge | 171:3a7713b1edbc | 1302 | MODIFY_REG(DMAx->CSELR, |
AnnaBridge | 171:3a7713b1edbc | 1303 | DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS); |
AnnaBridge | 171:3a7713b1edbc | 1304 | } |
AnnaBridge | 171:3a7713b1edbc | 1305 | |
AnnaBridge | 171:3a7713b1edbc | 1306 | /** |
AnnaBridge | 171:3a7713b1edbc | 1307 | * @brief Get DMA request for DMA instance on Channel x. |
AnnaBridge | 171:3a7713b1edbc | 1308 | * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n |
AnnaBridge | 171:3a7713b1edbc | 1309 | * CSELR C2S LL_DMA_GetPeriphRequest\n |
AnnaBridge | 171:3a7713b1edbc | 1310 | * CSELR C3S LL_DMA_GetPeriphRequest\n |
AnnaBridge | 171:3a7713b1edbc | 1311 | * CSELR C4S LL_DMA_GetPeriphRequest\n |
AnnaBridge | 171:3a7713b1edbc | 1312 | * CSELR C5S LL_DMA_GetPeriphRequest\n |
AnnaBridge | 171:3a7713b1edbc | 1313 | * CSELR C6S LL_DMA_GetPeriphRequest\n |
AnnaBridge | 171:3a7713b1edbc | 1314 | * CSELR C7S LL_DMA_GetPeriphRequest |
AnnaBridge | 171:3a7713b1edbc | 1315 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1316 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1317 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1318 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 1319 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 1320 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 1321 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 1322 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 1323 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 1324 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1325 | * @arg @ref LL_DMA_REQUEST_0 |
AnnaBridge | 171:3a7713b1edbc | 1326 | * @arg @ref LL_DMA_REQUEST_1 |
AnnaBridge | 171:3a7713b1edbc | 1327 | * @arg @ref LL_DMA_REQUEST_2 |
AnnaBridge | 171:3a7713b1edbc | 1328 | * @arg @ref LL_DMA_REQUEST_3 |
AnnaBridge | 171:3a7713b1edbc | 1329 | * @arg @ref LL_DMA_REQUEST_4 |
AnnaBridge | 171:3a7713b1edbc | 1330 | * @arg @ref LL_DMA_REQUEST_5 |
AnnaBridge | 171:3a7713b1edbc | 1331 | * @arg @ref LL_DMA_REQUEST_6 |
AnnaBridge | 171:3a7713b1edbc | 1332 | * @arg @ref LL_DMA_REQUEST_7 |
AnnaBridge | 171:3a7713b1edbc | 1333 | * @arg @ref LL_DMA_REQUEST_8 |
AnnaBridge | 171:3a7713b1edbc | 1334 | * @arg @ref LL_DMA_REQUEST_9 |
AnnaBridge | 171:3a7713b1edbc | 1335 | * @arg @ref LL_DMA_REQUEST_10 |
AnnaBridge | 171:3a7713b1edbc | 1336 | * @arg @ref LL_DMA_REQUEST_11 |
AnnaBridge | 171:3a7713b1edbc | 1337 | * @arg @ref LL_DMA_REQUEST_12 |
AnnaBridge | 171:3a7713b1edbc | 1338 | * @arg @ref LL_DMA_REQUEST_13 |
AnnaBridge | 171:3a7713b1edbc | 1339 | * @arg @ref LL_DMA_REQUEST_14 |
AnnaBridge | 171:3a7713b1edbc | 1340 | * @arg @ref LL_DMA_REQUEST_15 |
AnnaBridge | 171:3a7713b1edbc | 1341 | */ |
AnnaBridge | 171:3a7713b1edbc | 1342 | __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 1343 | { |
AnnaBridge | 171:3a7713b1edbc | 1344 | return (READ_BIT(DMAx->CSELR, |
AnnaBridge | 171:3a7713b1edbc | 1345 | DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS); |
AnnaBridge | 171:3a7713b1edbc | 1346 | } |
AnnaBridge | 171:3a7713b1edbc | 1347 | #endif |
AnnaBridge | 171:3a7713b1edbc | 1348 | |
AnnaBridge | 171:3a7713b1edbc | 1349 | /** |
AnnaBridge | 171:3a7713b1edbc | 1350 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1351 | */ |
AnnaBridge | 171:3a7713b1edbc | 1352 | |
AnnaBridge | 171:3a7713b1edbc | 1353 | /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management |
AnnaBridge | 171:3a7713b1edbc | 1354 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1355 | */ |
AnnaBridge | 171:3a7713b1edbc | 1356 | |
AnnaBridge | 171:3a7713b1edbc | 1357 | /** |
AnnaBridge | 171:3a7713b1edbc | 1358 | * @brief Get Channel 1 global interrupt flag. |
AnnaBridge | 171:3a7713b1edbc | 1359 | * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 |
AnnaBridge | 171:3a7713b1edbc | 1360 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1361 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1362 | */ |
AnnaBridge | 171:3a7713b1edbc | 1363 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1364 | { |
AnnaBridge | 171:3a7713b1edbc | 1365 | return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); |
AnnaBridge | 171:3a7713b1edbc | 1366 | } |
AnnaBridge | 171:3a7713b1edbc | 1367 | |
AnnaBridge | 171:3a7713b1edbc | 1368 | /** |
AnnaBridge | 171:3a7713b1edbc | 1369 | * @brief Get Channel 2 global interrupt flag. |
AnnaBridge | 171:3a7713b1edbc | 1370 | * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 |
AnnaBridge | 171:3a7713b1edbc | 1371 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1372 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1373 | */ |
AnnaBridge | 171:3a7713b1edbc | 1374 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1375 | { |
AnnaBridge | 171:3a7713b1edbc | 1376 | return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); |
AnnaBridge | 171:3a7713b1edbc | 1377 | } |
AnnaBridge | 171:3a7713b1edbc | 1378 | |
AnnaBridge | 171:3a7713b1edbc | 1379 | /** |
AnnaBridge | 171:3a7713b1edbc | 1380 | * @brief Get Channel 3 global interrupt flag. |
AnnaBridge | 171:3a7713b1edbc | 1381 | * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 |
AnnaBridge | 171:3a7713b1edbc | 1382 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1383 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1384 | */ |
AnnaBridge | 171:3a7713b1edbc | 1385 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1386 | { |
AnnaBridge | 171:3a7713b1edbc | 1387 | return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); |
AnnaBridge | 171:3a7713b1edbc | 1388 | } |
AnnaBridge | 171:3a7713b1edbc | 1389 | |
AnnaBridge | 171:3a7713b1edbc | 1390 | /** |
AnnaBridge | 171:3a7713b1edbc | 1391 | * @brief Get Channel 4 global interrupt flag. |
AnnaBridge | 171:3a7713b1edbc | 1392 | * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 |
AnnaBridge | 171:3a7713b1edbc | 1393 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1394 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1395 | */ |
AnnaBridge | 171:3a7713b1edbc | 1396 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1397 | { |
AnnaBridge | 171:3a7713b1edbc | 1398 | return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)); |
AnnaBridge | 171:3a7713b1edbc | 1399 | } |
AnnaBridge | 171:3a7713b1edbc | 1400 | |
AnnaBridge | 171:3a7713b1edbc | 1401 | /** |
AnnaBridge | 171:3a7713b1edbc | 1402 | * @brief Get Channel 5 global interrupt flag. |
AnnaBridge | 171:3a7713b1edbc | 1403 | * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 |
AnnaBridge | 171:3a7713b1edbc | 1404 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1405 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1406 | */ |
AnnaBridge | 171:3a7713b1edbc | 1407 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1408 | { |
AnnaBridge | 171:3a7713b1edbc | 1409 | return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)); |
AnnaBridge | 171:3a7713b1edbc | 1410 | } |
AnnaBridge | 171:3a7713b1edbc | 1411 | |
AnnaBridge | 171:3a7713b1edbc | 1412 | #if defined(DMA1_Channel6) |
AnnaBridge | 171:3a7713b1edbc | 1413 | /** |
AnnaBridge | 171:3a7713b1edbc | 1414 | * @brief Get Channel 6 global interrupt flag. |
AnnaBridge | 171:3a7713b1edbc | 1415 | * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 |
AnnaBridge | 171:3a7713b1edbc | 1416 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1417 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1418 | */ |
AnnaBridge | 171:3a7713b1edbc | 1419 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1420 | { |
AnnaBridge | 171:3a7713b1edbc | 1421 | return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)); |
AnnaBridge | 171:3a7713b1edbc | 1422 | } |
AnnaBridge | 171:3a7713b1edbc | 1423 | #endif |
AnnaBridge | 171:3a7713b1edbc | 1424 | |
AnnaBridge | 171:3a7713b1edbc | 1425 | #if defined(DMA1_Channel7) |
AnnaBridge | 171:3a7713b1edbc | 1426 | /** |
AnnaBridge | 171:3a7713b1edbc | 1427 | * @brief Get Channel 7 global interrupt flag. |
AnnaBridge | 171:3a7713b1edbc | 1428 | * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 |
AnnaBridge | 171:3a7713b1edbc | 1429 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1430 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1431 | */ |
AnnaBridge | 171:3a7713b1edbc | 1432 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1433 | { |
AnnaBridge | 171:3a7713b1edbc | 1434 | return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)); |
AnnaBridge | 171:3a7713b1edbc | 1435 | } |
AnnaBridge | 171:3a7713b1edbc | 1436 | #endif |
AnnaBridge | 171:3a7713b1edbc | 1437 | |
AnnaBridge | 171:3a7713b1edbc | 1438 | /** |
AnnaBridge | 171:3a7713b1edbc | 1439 | * @brief Get Channel 1 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 1440 | * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 |
AnnaBridge | 171:3a7713b1edbc | 1441 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1442 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1443 | */ |
AnnaBridge | 171:3a7713b1edbc | 1444 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1445 | { |
AnnaBridge | 171:3a7713b1edbc | 1446 | return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); |
AnnaBridge | 171:3a7713b1edbc | 1447 | } |
AnnaBridge | 171:3a7713b1edbc | 1448 | |
AnnaBridge | 171:3a7713b1edbc | 1449 | /** |
AnnaBridge | 171:3a7713b1edbc | 1450 | * @brief Get Channel 2 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 1451 | * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 |
AnnaBridge | 171:3a7713b1edbc | 1452 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1453 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1454 | */ |
AnnaBridge | 171:3a7713b1edbc | 1455 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1456 | { |
AnnaBridge | 171:3a7713b1edbc | 1457 | return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); |
AnnaBridge | 171:3a7713b1edbc | 1458 | } |
AnnaBridge | 171:3a7713b1edbc | 1459 | |
AnnaBridge | 171:3a7713b1edbc | 1460 | /** |
AnnaBridge | 171:3a7713b1edbc | 1461 | * @brief Get Channel 3 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 1462 | * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 |
AnnaBridge | 171:3a7713b1edbc | 1463 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1464 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1465 | */ |
AnnaBridge | 171:3a7713b1edbc | 1466 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1467 | { |
AnnaBridge | 171:3a7713b1edbc | 1468 | return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); |
AnnaBridge | 171:3a7713b1edbc | 1469 | } |
AnnaBridge | 171:3a7713b1edbc | 1470 | |
AnnaBridge | 171:3a7713b1edbc | 1471 | /** |
AnnaBridge | 171:3a7713b1edbc | 1472 | * @brief Get Channel 4 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 1473 | * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 |
AnnaBridge | 171:3a7713b1edbc | 1474 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1475 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1476 | */ |
AnnaBridge | 171:3a7713b1edbc | 1477 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1478 | { |
AnnaBridge | 171:3a7713b1edbc | 1479 | return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)); |
AnnaBridge | 171:3a7713b1edbc | 1480 | } |
AnnaBridge | 171:3a7713b1edbc | 1481 | |
AnnaBridge | 171:3a7713b1edbc | 1482 | /** |
AnnaBridge | 171:3a7713b1edbc | 1483 | * @brief Get Channel 5 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 1484 | * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 |
AnnaBridge | 171:3a7713b1edbc | 1485 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1486 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1487 | */ |
AnnaBridge | 171:3a7713b1edbc | 1488 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1489 | { |
AnnaBridge | 171:3a7713b1edbc | 1490 | return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)); |
AnnaBridge | 171:3a7713b1edbc | 1491 | } |
AnnaBridge | 171:3a7713b1edbc | 1492 | |
AnnaBridge | 171:3a7713b1edbc | 1493 | #if defined(DMA1_Channel6) |
AnnaBridge | 171:3a7713b1edbc | 1494 | /** |
AnnaBridge | 171:3a7713b1edbc | 1495 | * @brief Get Channel 6 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 1496 | * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 |
AnnaBridge | 171:3a7713b1edbc | 1497 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1498 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1499 | */ |
AnnaBridge | 171:3a7713b1edbc | 1500 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1501 | { |
AnnaBridge | 171:3a7713b1edbc | 1502 | return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)); |
AnnaBridge | 171:3a7713b1edbc | 1503 | } |
AnnaBridge | 171:3a7713b1edbc | 1504 | #endif |
AnnaBridge | 171:3a7713b1edbc | 1505 | |
AnnaBridge | 171:3a7713b1edbc | 1506 | #if defined(DMA1_Channel7) |
AnnaBridge | 171:3a7713b1edbc | 1507 | /** |
AnnaBridge | 171:3a7713b1edbc | 1508 | * @brief Get Channel 7 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 1509 | * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 |
AnnaBridge | 171:3a7713b1edbc | 1510 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1511 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1512 | */ |
AnnaBridge | 171:3a7713b1edbc | 1513 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1514 | { |
AnnaBridge | 171:3a7713b1edbc | 1515 | return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)); |
AnnaBridge | 171:3a7713b1edbc | 1516 | } |
AnnaBridge | 171:3a7713b1edbc | 1517 | #endif |
AnnaBridge | 171:3a7713b1edbc | 1518 | |
AnnaBridge | 171:3a7713b1edbc | 1519 | /** |
AnnaBridge | 171:3a7713b1edbc | 1520 | * @brief Get Channel 1 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 1521 | * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 |
AnnaBridge | 171:3a7713b1edbc | 1522 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1523 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1524 | */ |
AnnaBridge | 171:3a7713b1edbc | 1525 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1526 | { |
AnnaBridge | 171:3a7713b1edbc | 1527 | return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); |
AnnaBridge | 171:3a7713b1edbc | 1528 | } |
AnnaBridge | 171:3a7713b1edbc | 1529 | |
AnnaBridge | 171:3a7713b1edbc | 1530 | /** |
AnnaBridge | 171:3a7713b1edbc | 1531 | * @brief Get Channel 2 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 1532 | * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 |
AnnaBridge | 171:3a7713b1edbc | 1533 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1534 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1535 | */ |
AnnaBridge | 171:3a7713b1edbc | 1536 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1537 | { |
AnnaBridge | 171:3a7713b1edbc | 1538 | return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); |
AnnaBridge | 171:3a7713b1edbc | 1539 | } |
AnnaBridge | 171:3a7713b1edbc | 1540 | |
AnnaBridge | 171:3a7713b1edbc | 1541 | /** |
AnnaBridge | 171:3a7713b1edbc | 1542 | * @brief Get Channel 3 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 1543 | * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 |
AnnaBridge | 171:3a7713b1edbc | 1544 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1545 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1546 | */ |
AnnaBridge | 171:3a7713b1edbc | 1547 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1548 | { |
AnnaBridge | 171:3a7713b1edbc | 1549 | return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); |
AnnaBridge | 171:3a7713b1edbc | 1550 | } |
AnnaBridge | 171:3a7713b1edbc | 1551 | |
AnnaBridge | 171:3a7713b1edbc | 1552 | /** |
AnnaBridge | 171:3a7713b1edbc | 1553 | * @brief Get Channel 4 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 1554 | * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 |
AnnaBridge | 171:3a7713b1edbc | 1555 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1556 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1557 | */ |
AnnaBridge | 171:3a7713b1edbc | 1558 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1559 | { |
AnnaBridge | 171:3a7713b1edbc | 1560 | return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)); |
AnnaBridge | 171:3a7713b1edbc | 1561 | } |
AnnaBridge | 171:3a7713b1edbc | 1562 | |
AnnaBridge | 171:3a7713b1edbc | 1563 | /** |
AnnaBridge | 171:3a7713b1edbc | 1564 | * @brief Get Channel 5 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 1565 | * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 |
AnnaBridge | 171:3a7713b1edbc | 1566 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1567 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1568 | */ |
AnnaBridge | 171:3a7713b1edbc | 1569 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1570 | { |
AnnaBridge | 171:3a7713b1edbc | 1571 | return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)); |
AnnaBridge | 171:3a7713b1edbc | 1572 | } |
AnnaBridge | 171:3a7713b1edbc | 1573 | |
AnnaBridge | 171:3a7713b1edbc | 1574 | #if defined(DMA1_Channel6) |
AnnaBridge | 171:3a7713b1edbc | 1575 | /** |
AnnaBridge | 171:3a7713b1edbc | 1576 | * @brief Get Channel 6 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 1577 | * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 |
AnnaBridge | 171:3a7713b1edbc | 1578 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1579 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1580 | */ |
AnnaBridge | 171:3a7713b1edbc | 1581 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1582 | { |
AnnaBridge | 171:3a7713b1edbc | 1583 | return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)); |
AnnaBridge | 171:3a7713b1edbc | 1584 | } |
AnnaBridge | 171:3a7713b1edbc | 1585 | #endif |
AnnaBridge | 171:3a7713b1edbc | 1586 | |
AnnaBridge | 171:3a7713b1edbc | 1587 | #if defined(DMA1_Channel7) |
AnnaBridge | 171:3a7713b1edbc | 1588 | /** |
AnnaBridge | 171:3a7713b1edbc | 1589 | * @brief Get Channel 7 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 1590 | * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 |
AnnaBridge | 171:3a7713b1edbc | 1591 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1592 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1593 | */ |
AnnaBridge | 171:3a7713b1edbc | 1594 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1595 | { |
AnnaBridge | 171:3a7713b1edbc | 1596 | return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)); |
AnnaBridge | 171:3a7713b1edbc | 1597 | } |
AnnaBridge | 171:3a7713b1edbc | 1598 | #endif |
AnnaBridge | 171:3a7713b1edbc | 1599 | |
AnnaBridge | 171:3a7713b1edbc | 1600 | /** |
AnnaBridge | 171:3a7713b1edbc | 1601 | * @brief Get Channel 1 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 1602 | * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 |
AnnaBridge | 171:3a7713b1edbc | 1603 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1604 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1605 | */ |
AnnaBridge | 171:3a7713b1edbc | 1606 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1607 | { |
AnnaBridge | 171:3a7713b1edbc | 1608 | return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); |
AnnaBridge | 171:3a7713b1edbc | 1609 | } |
AnnaBridge | 171:3a7713b1edbc | 1610 | |
AnnaBridge | 171:3a7713b1edbc | 1611 | /** |
AnnaBridge | 171:3a7713b1edbc | 1612 | * @brief Get Channel 2 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 1613 | * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 |
AnnaBridge | 171:3a7713b1edbc | 1614 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1615 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1616 | */ |
AnnaBridge | 171:3a7713b1edbc | 1617 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1618 | { |
AnnaBridge | 171:3a7713b1edbc | 1619 | return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); |
AnnaBridge | 171:3a7713b1edbc | 1620 | } |
AnnaBridge | 171:3a7713b1edbc | 1621 | |
AnnaBridge | 171:3a7713b1edbc | 1622 | /** |
AnnaBridge | 171:3a7713b1edbc | 1623 | * @brief Get Channel 3 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 1624 | * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 |
AnnaBridge | 171:3a7713b1edbc | 1625 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1626 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1627 | */ |
AnnaBridge | 171:3a7713b1edbc | 1628 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1629 | { |
AnnaBridge | 171:3a7713b1edbc | 1630 | return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); |
AnnaBridge | 171:3a7713b1edbc | 1631 | } |
AnnaBridge | 171:3a7713b1edbc | 1632 | |
AnnaBridge | 171:3a7713b1edbc | 1633 | /** |
AnnaBridge | 171:3a7713b1edbc | 1634 | * @brief Get Channel 4 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 1635 | * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 |
AnnaBridge | 171:3a7713b1edbc | 1636 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1637 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1638 | */ |
AnnaBridge | 171:3a7713b1edbc | 1639 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1640 | { |
AnnaBridge | 171:3a7713b1edbc | 1641 | return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)); |
AnnaBridge | 171:3a7713b1edbc | 1642 | } |
AnnaBridge | 171:3a7713b1edbc | 1643 | |
AnnaBridge | 171:3a7713b1edbc | 1644 | /** |
AnnaBridge | 171:3a7713b1edbc | 1645 | * @brief Get Channel 5 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 1646 | * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 |
AnnaBridge | 171:3a7713b1edbc | 1647 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1648 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1649 | */ |
AnnaBridge | 171:3a7713b1edbc | 1650 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1651 | { |
AnnaBridge | 171:3a7713b1edbc | 1652 | return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)); |
AnnaBridge | 171:3a7713b1edbc | 1653 | } |
AnnaBridge | 171:3a7713b1edbc | 1654 | |
AnnaBridge | 171:3a7713b1edbc | 1655 | #if defined(DMA1_Channel6) |
AnnaBridge | 171:3a7713b1edbc | 1656 | /** |
AnnaBridge | 171:3a7713b1edbc | 1657 | * @brief Get Channel 6 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 1658 | * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 |
AnnaBridge | 171:3a7713b1edbc | 1659 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1660 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1661 | */ |
AnnaBridge | 171:3a7713b1edbc | 1662 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1663 | { |
AnnaBridge | 171:3a7713b1edbc | 1664 | return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)); |
AnnaBridge | 171:3a7713b1edbc | 1665 | } |
AnnaBridge | 171:3a7713b1edbc | 1666 | #endif |
AnnaBridge | 171:3a7713b1edbc | 1667 | |
AnnaBridge | 171:3a7713b1edbc | 1668 | #if defined(DMA1_Channel7) |
AnnaBridge | 171:3a7713b1edbc | 1669 | /** |
AnnaBridge | 171:3a7713b1edbc | 1670 | * @brief Get Channel 7 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 1671 | * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 |
AnnaBridge | 171:3a7713b1edbc | 1672 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1673 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1674 | */ |
AnnaBridge | 171:3a7713b1edbc | 1675 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1676 | { |
AnnaBridge | 171:3a7713b1edbc | 1677 | return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)); |
AnnaBridge | 171:3a7713b1edbc | 1678 | } |
AnnaBridge | 171:3a7713b1edbc | 1679 | #endif |
AnnaBridge | 171:3a7713b1edbc | 1680 | |
AnnaBridge | 171:3a7713b1edbc | 1681 | /** |
AnnaBridge | 171:3a7713b1edbc | 1682 | * @brief Clear Channel 1 global interrupt flag. |
AnnaBridge | 171:3a7713b1edbc | 1683 | * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 |
AnnaBridge | 171:3a7713b1edbc | 1684 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1685 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1686 | */ |
AnnaBridge | 171:3a7713b1edbc | 1687 | __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1688 | { |
AnnaBridge | 171:3a7713b1edbc | 1689 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); |
AnnaBridge | 171:3a7713b1edbc | 1690 | } |
AnnaBridge | 171:3a7713b1edbc | 1691 | |
AnnaBridge | 171:3a7713b1edbc | 1692 | /** |
AnnaBridge | 171:3a7713b1edbc | 1693 | * @brief Clear Channel 2 global interrupt flag. |
AnnaBridge | 171:3a7713b1edbc | 1694 | * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 |
AnnaBridge | 171:3a7713b1edbc | 1695 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1696 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1697 | */ |
AnnaBridge | 171:3a7713b1edbc | 1698 | __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1699 | { |
AnnaBridge | 171:3a7713b1edbc | 1700 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); |
AnnaBridge | 171:3a7713b1edbc | 1701 | } |
AnnaBridge | 171:3a7713b1edbc | 1702 | |
AnnaBridge | 171:3a7713b1edbc | 1703 | /** |
AnnaBridge | 171:3a7713b1edbc | 1704 | * @brief Clear Channel 3 global interrupt flag. |
AnnaBridge | 171:3a7713b1edbc | 1705 | * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 |
AnnaBridge | 171:3a7713b1edbc | 1706 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1707 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1708 | */ |
AnnaBridge | 171:3a7713b1edbc | 1709 | __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1710 | { |
AnnaBridge | 171:3a7713b1edbc | 1711 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); |
AnnaBridge | 171:3a7713b1edbc | 1712 | } |
AnnaBridge | 171:3a7713b1edbc | 1713 | |
AnnaBridge | 171:3a7713b1edbc | 1714 | /** |
AnnaBridge | 171:3a7713b1edbc | 1715 | * @brief Clear Channel 4 global interrupt flag. |
AnnaBridge | 171:3a7713b1edbc | 1716 | * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 |
AnnaBridge | 171:3a7713b1edbc | 1717 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1718 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1719 | */ |
AnnaBridge | 171:3a7713b1edbc | 1720 | __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1721 | { |
AnnaBridge | 171:3a7713b1edbc | 1722 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); |
AnnaBridge | 171:3a7713b1edbc | 1723 | } |
AnnaBridge | 171:3a7713b1edbc | 1724 | |
AnnaBridge | 171:3a7713b1edbc | 1725 | /** |
AnnaBridge | 171:3a7713b1edbc | 1726 | * @brief Clear Channel 5 global interrupt flag. |
AnnaBridge | 171:3a7713b1edbc | 1727 | * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 |
AnnaBridge | 171:3a7713b1edbc | 1728 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1729 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1730 | */ |
AnnaBridge | 171:3a7713b1edbc | 1731 | __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1732 | { |
AnnaBridge | 171:3a7713b1edbc | 1733 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); |
AnnaBridge | 171:3a7713b1edbc | 1734 | } |
AnnaBridge | 171:3a7713b1edbc | 1735 | |
AnnaBridge | 171:3a7713b1edbc | 1736 | #if defined(DMA1_Channel6) |
AnnaBridge | 171:3a7713b1edbc | 1737 | /** |
AnnaBridge | 171:3a7713b1edbc | 1738 | * @brief Clear Channel 6 global interrupt flag. |
AnnaBridge | 171:3a7713b1edbc | 1739 | * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 |
AnnaBridge | 171:3a7713b1edbc | 1740 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1741 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1742 | */ |
AnnaBridge | 171:3a7713b1edbc | 1743 | __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1744 | { |
AnnaBridge | 171:3a7713b1edbc | 1745 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); |
AnnaBridge | 171:3a7713b1edbc | 1746 | } |
AnnaBridge | 171:3a7713b1edbc | 1747 | #endif |
AnnaBridge | 171:3a7713b1edbc | 1748 | |
AnnaBridge | 171:3a7713b1edbc | 1749 | #if defined(DMA1_Channel7) |
AnnaBridge | 171:3a7713b1edbc | 1750 | /** |
AnnaBridge | 171:3a7713b1edbc | 1751 | * @brief Clear Channel 7 global interrupt flag. |
AnnaBridge | 171:3a7713b1edbc | 1752 | * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 |
AnnaBridge | 171:3a7713b1edbc | 1753 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1754 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1755 | */ |
AnnaBridge | 171:3a7713b1edbc | 1756 | __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1757 | { |
AnnaBridge | 171:3a7713b1edbc | 1758 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); |
AnnaBridge | 171:3a7713b1edbc | 1759 | } |
AnnaBridge | 171:3a7713b1edbc | 1760 | #endif |
AnnaBridge | 171:3a7713b1edbc | 1761 | |
AnnaBridge | 171:3a7713b1edbc | 1762 | /** |
AnnaBridge | 171:3a7713b1edbc | 1763 | * @brief Clear Channel 1 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 1764 | * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 |
AnnaBridge | 171:3a7713b1edbc | 1765 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1766 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1767 | */ |
AnnaBridge | 171:3a7713b1edbc | 1768 | __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1769 | { |
AnnaBridge | 171:3a7713b1edbc | 1770 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); |
AnnaBridge | 171:3a7713b1edbc | 1771 | } |
AnnaBridge | 171:3a7713b1edbc | 1772 | |
AnnaBridge | 171:3a7713b1edbc | 1773 | /** |
AnnaBridge | 171:3a7713b1edbc | 1774 | * @brief Clear Channel 2 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 1775 | * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 |
AnnaBridge | 171:3a7713b1edbc | 1776 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1777 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1778 | */ |
AnnaBridge | 171:3a7713b1edbc | 1779 | __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1780 | { |
AnnaBridge | 171:3a7713b1edbc | 1781 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); |
AnnaBridge | 171:3a7713b1edbc | 1782 | } |
AnnaBridge | 171:3a7713b1edbc | 1783 | |
AnnaBridge | 171:3a7713b1edbc | 1784 | /** |
AnnaBridge | 171:3a7713b1edbc | 1785 | * @brief Clear Channel 3 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 1786 | * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 |
AnnaBridge | 171:3a7713b1edbc | 1787 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1788 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1789 | */ |
AnnaBridge | 171:3a7713b1edbc | 1790 | __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1791 | { |
AnnaBridge | 171:3a7713b1edbc | 1792 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); |
AnnaBridge | 171:3a7713b1edbc | 1793 | } |
AnnaBridge | 171:3a7713b1edbc | 1794 | |
AnnaBridge | 171:3a7713b1edbc | 1795 | /** |
AnnaBridge | 171:3a7713b1edbc | 1796 | * @brief Clear Channel 4 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 1797 | * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 |
AnnaBridge | 171:3a7713b1edbc | 1798 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1799 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1800 | */ |
AnnaBridge | 171:3a7713b1edbc | 1801 | __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1802 | { |
AnnaBridge | 171:3a7713b1edbc | 1803 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); |
AnnaBridge | 171:3a7713b1edbc | 1804 | } |
AnnaBridge | 171:3a7713b1edbc | 1805 | |
AnnaBridge | 171:3a7713b1edbc | 1806 | /** |
AnnaBridge | 171:3a7713b1edbc | 1807 | * @brief Clear Channel 5 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 1808 | * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 |
AnnaBridge | 171:3a7713b1edbc | 1809 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1810 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1811 | */ |
AnnaBridge | 171:3a7713b1edbc | 1812 | __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1813 | { |
AnnaBridge | 171:3a7713b1edbc | 1814 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); |
AnnaBridge | 171:3a7713b1edbc | 1815 | } |
AnnaBridge | 171:3a7713b1edbc | 1816 | |
AnnaBridge | 171:3a7713b1edbc | 1817 | #if defined(DMA1_Channel6) |
AnnaBridge | 171:3a7713b1edbc | 1818 | /** |
AnnaBridge | 171:3a7713b1edbc | 1819 | * @brief Clear Channel 6 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 1820 | * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 |
AnnaBridge | 171:3a7713b1edbc | 1821 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1822 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1823 | */ |
AnnaBridge | 171:3a7713b1edbc | 1824 | __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1825 | { |
AnnaBridge | 171:3a7713b1edbc | 1826 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); |
AnnaBridge | 171:3a7713b1edbc | 1827 | } |
AnnaBridge | 171:3a7713b1edbc | 1828 | #endif |
AnnaBridge | 171:3a7713b1edbc | 1829 | |
AnnaBridge | 171:3a7713b1edbc | 1830 | #if defined(DMA1_Channel7) |
AnnaBridge | 171:3a7713b1edbc | 1831 | /** |
AnnaBridge | 171:3a7713b1edbc | 1832 | * @brief Clear Channel 7 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 1833 | * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 |
AnnaBridge | 171:3a7713b1edbc | 1834 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1835 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1836 | */ |
AnnaBridge | 171:3a7713b1edbc | 1837 | __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1838 | { |
AnnaBridge | 171:3a7713b1edbc | 1839 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); |
AnnaBridge | 171:3a7713b1edbc | 1840 | } |
AnnaBridge | 171:3a7713b1edbc | 1841 | #endif |
AnnaBridge | 171:3a7713b1edbc | 1842 | |
AnnaBridge | 171:3a7713b1edbc | 1843 | /** |
AnnaBridge | 171:3a7713b1edbc | 1844 | * @brief Clear Channel 1 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 1845 | * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 |
AnnaBridge | 171:3a7713b1edbc | 1846 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1847 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1848 | */ |
AnnaBridge | 171:3a7713b1edbc | 1849 | __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1850 | { |
AnnaBridge | 171:3a7713b1edbc | 1851 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); |
AnnaBridge | 171:3a7713b1edbc | 1852 | } |
AnnaBridge | 171:3a7713b1edbc | 1853 | |
AnnaBridge | 171:3a7713b1edbc | 1854 | /** |
AnnaBridge | 171:3a7713b1edbc | 1855 | * @brief Clear Channel 2 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 1856 | * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 |
AnnaBridge | 171:3a7713b1edbc | 1857 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1858 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1859 | */ |
AnnaBridge | 171:3a7713b1edbc | 1860 | __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1861 | { |
AnnaBridge | 171:3a7713b1edbc | 1862 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); |
AnnaBridge | 171:3a7713b1edbc | 1863 | } |
AnnaBridge | 171:3a7713b1edbc | 1864 | |
AnnaBridge | 171:3a7713b1edbc | 1865 | /** |
AnnaBridge | 171:3a7713b1edbc | 1866 | * @brief Clear Channel 3 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 1867 | * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 |
AnnaBridge | 171:3a7713b1edbc | 1868 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1869 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1870 | */ |
AnnaBridge | 171:3a7713b1edbc | 1871 | __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1872 | { |
AnnaBridge | 171:3a7713b1edbc | 1873 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); |
AnnaBridge | 171:3a7713b1edbc | 1874 | } |
AnnaBridge | 171:3a7713b1edbc | 1875 | |
AnnaBridge | 171:3a7713b1edbc | 1876 | /** |
AnnaBridge | 171:3a7713b1edbc | 1877 | * @brief Clear Channel 4 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 1878 | * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 |
AnnaBridge | 171:3a7713b1edbc | 1879 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1880 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1881 | */ |
AnnaBridge | 171:3a7713b1edbc | 1882 | __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1883 | { |
AnnaBridge | 171:3a7713b1edbc | 1884 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); |
AnnaBridge | 171:3a7713b1edbc | 1885 | } |
AnnaBridge | 171:3a7713b1edbc | 1886 | |
AnnaBridge | 171:3a7713b1edbc | 1887 | /** |
AnnaBridge | 171:3a7713b1edbc | 1888 | * @brief Clear Channel 5 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 1889 | * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 |
AnnaBridge | 171:3a7713b1edbc | 1890 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1891 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1892 | */ |
AnnaBridge | 171:3a7713b1edbc | 1893 | __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1894 | { |
AnnaBridge | 171:3a7713b1edbc | 1895 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); |
AnnaBridge | 171:3a7713b1edbc | 1896 | } |
AnnaBridge | 171:3a7713b1edbc | 1897 | |
AnnaBridge | 171:3a7713b1edbc | 1898 | #if defined(DMA1_Channel6) |
AnnaBridge | 171:3a7713b1edbc | 1899 | /** |
AnnaBridge | 171:3a7713b1edbc | 1900 | * @brief Clear Channel 6 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 1901 | * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 |
AnnaBridge | 171:3a7713b1edbc | 1902 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1903 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1904 | */ |
AnnaBridge | 171:3a7713b1edbc | 1905 | __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1906 | { |
AnnaBridge | 171:3a7713b1edbc | 1907 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); |
AnnaBridge | 171:3a7713b1edbc | 1908 | } |
AnnaBridge | 171:3a7713b1edbc | 1909 | #endif |
AnnaBridge | 171:3a7713b1edbc | 1910 | |
AnnaBridge | 171:3a7713b1edbc | 1911 | #if defined(DMA1_Channel7) |
AnnaBridge | 171:3a7713b1edbc | 1912 | /** |
AnnaBridge | 171:3a7713b1edbc | 1913 | * @brief Clear Channel 7 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 1914 | * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 |
AnnaBridge | 171:3a7713b1edbc | 1915 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1916 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1917 | */ |
AnnaBridge | 171:3a7713b1edbc | 1918 | __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1919 | { |
AnnaBridge | 171:3a7713b1edbc | 1920 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); |
AnnaBridge | 171:3a7713b1edbc | 1921 | } |
AnnaBridge | 171:3a7713b1edbc | 1922 | #endif |
AnnaBridge | 171:3a7713b1edbc | 1923 | |
AnnaBridge | 171:3a7713b1edbc | 1924 | /** |
AnnaBridge | 171:3a7713b1edbc | 1925 | * @brief Clear Channel 1 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 1926 | * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 |
AnnaBridge | 171:3a7713b1edbc | 1927 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1928 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1929 | */ |
AnnaBridge | 171:3a7713b1edbc | 1930 | __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1931 | { |
AnnaBridge | 171:3a7713b1edbc | 1932 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); |
AnnaBridge | 171:3a7713b1edbc | 1933 | } |
AnnaBridge | 171:3a7713b1edbc | 1934 | |
AnnaBridge | 171:3a7713b1edbc | 1935 | /** |
AnnaBridge | 171:3a7713b1edbc | 1936 | * @brief Clear Channel 2 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 1937 | * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 |
AnnaBridge | 171:3a7713b1edbc | 1938 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1939 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1940 | */ |
AnnaBridge | 171:3a7713b1edbc | 1941 | __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1942 | { |
AnnaBridge | 171:3a7713b1edbc | 1943 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); |
AnnaBridge | 171:3a7713b1edbc | 1944 | } |
AnnaBridge | 171:3a7713b1edbc | 1945 | |
AnnaBridge | 171:3a7713b1edbc | 1946 | /** |
AnnaBridge | 171:3a7713b1edbc | 1947 | * @brief Clear Channel 3 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 1948 | * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 |
AnnaBridge | 171:3a7713b1edbc | 1949 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1950 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1951 | */ |
AnnaBridge | 171:3a7713b1edbc | 1952 | __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1953 | { |
AnnaBridge | 171:3a7713b1edbc | 1954 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); |
AnnaBridge | 171:3a7713b1edbc | 1955 | } |
AnnaBridge | 171:3a7713b1edbc | 1956 | |
AnnaBridge | 171:3a7713b1edbc | 1957 | /** |
AnnaBridge | 171:3a7713b1edbc | 1958 | * @brief Clear Channel 4 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 1959 | * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 |
AnnaBridge | 171:3a7713b1edbc | 1960 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1961 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1962 | */ |
AnnaBridge | 171:3a7713b1edbc | 1963 | __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1964 | { |
AnnaBridge | 171:3a7713b1edbc | 1965 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); |
AnnaBridge | 171:3a7713b1edbc | 1966 | } |
AnnaBridge | 171:3a7713b1edbc | 1967 | |
AnnaBridge | 171:3a7713b1edbc | 1968 | /** |
AnnaBridge | 171:3a7713b1edbc | 1969 | * @brief Clear Channel 5 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 1970 | * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 |
AnnaBridge | 171:3a7713b1edbc | 1971 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1972 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1973 | */ |
AnnaBridge | 171:3a7713b1edbc | 1974 | __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1975 | { |
AnnaBridge | 171:3a7713b1edbc | 1976 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); |
AnnaBridge | 171:3a7713b1edbc | 1977 | } |
AnnaBridge | 171:3a7713b1edbc | 1978 | |
AnnaBridge | 171:3a7713b1edbc | 1979 | #if defined(DMA1_Channel6) |
AnnaBridge | 171:3a7713b1edbc | 1980 | /** |
AnnaBridge | 171:3a7713b1edbc | 1981 | * @brief Clear Channel 6 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 1982 | * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 |
AnnaBridge | 171:3a7713b1edbc | 1983 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1984 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1985 | */ |
AnnaBridge | 171:3a7713b1edbc | 1986 | __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1987 | { |
AnnaBridge | 171:3a7713b1edbc | 1988 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); |
AnnaBridge | 171:3a7713b1edbc | 1989 | } |
AnnaBridge | 171:3a7713b1edbc | 1990 | #endif |
AnnaBridge | 171:3a7713b1edbc | 1991 | |
AnnaBridge | 171:3a7713b1edbc | 1992 | #if defined(DMA1_Channel7) |
AnnaBridge | 171:3a7713b1edbc | 1993 | /** |
AnnaBridge | 171:3a7713b1edbc | 1994 | * @brief Clear Channel 7 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 1995 | * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 |
AnnaBridge | 171:3a7713b1edbc | 1996 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1997 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1998 | */ |
AnnaBridge | 171:3a7713b1edbc | 1999 | __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2000 | { |
AnnaBridge | 171:3a7713b1edbc | 2001 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); |
AnnaBridge | 171:3a7713b1edbc | 2002 | } |
AnnaBridge | 171:3a7713b1edbc | 2003 | #endif |
AnnaBridge | 171:3a7713b1edbc | 2004 | |
AnnaBridge | 171:3a7713b1edbc | 2005 | /** |
AnnaBridge | 171:3a7713b1edbc | 2006 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2007 | */ |
AnnaBridge | 171:3a7713b1edbc | 2008 | |
AnnaBridge | 171:3a7713b1edbc | 2009 | /** @defgroup DMA_LL_EF_IT_Management IT_Management |
AnnaBridge | 171:3a7713b1edbc | 2010 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2011 | */ |
AnnaBridge | 171:3a7713b1edbc | 2012 | /** |
AnnaBridge | 171:3a7713b1edbc | 2013 | * @brief Enable Transfer complete interrupt. |
AnnaBridge | 171:3a7713b1edbc | 2014 | * @rmtoll CCR TCIE LL_DMA_EnableIT_TC |
AnnaBridge | 171:3a7713b1edbc | 2015 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2016 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2017 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 2018 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 2019 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 2020 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 2021 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 2022 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 2023 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 2024 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2025 | */ |
AnnaBridge | 171:3a7713b1edbc | 2026 | __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2027 | { |
AnnaBridge | 171:3a7713b1edbc | 2028 | SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); |
AnnaBridge | 171:3a7713b1edbc | 2029 | } |
AnnaBridge | 171:3a7713b1edbc | 2030 | |
AnnaBridge | 171:3a7713b1edbc | 2031 | /** |
AnnaBridge | 171:3a7713b1edbc | 2032 | * @brief Enable Half transfer interrupt. |
AnnaBridge | 171:3a7713b1edbc | 2033 | * @rmtoll CCR HTIE LL_DMA_EnableIT_HT |
AnnaBridge | 171:3a7713b1edbc | 2034 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2035 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2036 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 2037 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 2038 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 2039 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 2040 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 2041 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 2042 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 2043 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2044 | */ |
AnnaBridge | 171:3a7713b1edbc | 2045 | __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2046 | { |
AnnaBridge | 171:3a7713b1edbc | 2047 | SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); |
AnnaBridge | 171:3a7713b1edbc | 2048 | } |
AnnaBridge | 171:3a7713b1edbc | 2049 | |
AnnaBridge | 171:3a7713b1edbc | 2050 | /** |
AnnaBridge | 171:3a7713b1edbc | 2051 | * @brief Enable Transfer error interrupt. |
AnnaBridge | 171:3a7713b1edbc | 2052 | * @rmtoll CCR TEIE LL_DMA_EnableIT_TE |
AnnaBridge | 171:3a7713b1edbc | 2053 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2054 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2055 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 2056 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 2057 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 2058 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 2059 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 2060 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 2061 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 2062 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2063 | */ |
AnnaBridge | 171:3a7713b1edbc | 2064 | __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2065 | { |
AnnaBridge | 171:3a7713b1edbc | 2066 | SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); |
AnnaBridge | 171:3a7713b1edbc | 2067 | } |
AnnaBridge | 171:3a7713b1edbc | 2068 | |
AnnaBridge | 171:3a7713b1edbc | 2069 | /** |
AnnaBridge | 171:3a7713b1edbc | 2070 | * @brief Disable Transfer complete interrupt. |
AnnaBridge | 171:3a7713b1edbc | 2071 | * @rmtoll CCR TCIE LL_DMA_DisableIT_TC |
AnnaBridge | 171:3a7713b1edbc | 2072 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2073 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2074 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 2075 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 2076 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 2077 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 2078 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 2079 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 2080 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 2081 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2082 | */ |
AnnaBridge | 171:3a7713b1edbc | 2083 | __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2084 | { |
AnnaBridge | 171:3a7713b1edbc | 2085 | CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); |
AnnaBridge | 171:3a7713b1edbc | 2086 | } |
AnnaBridge | 171:3a7713b1edbc | 2087 | |
AnnaBridge | 171:3a7713b1edbc | 2088 | /** |
AnnaBridge | 171:3a7713b1edbc | 2089 | * @brief Disable Half transfer interrupt. |
AnnaBridge | 171:3a7713b1edbc | 2090 | * @rmtoll CCR HTIE LL_DMA_DisableIT_HT |
AnnaBridge | 171:3a7713b1edbc | 2091 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2092 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2093 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 2094 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 2095 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 2096 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 2097 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 2098 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 2099 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 2100 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2101 | */ |
AnnaBridge | 171:3a7713b1edbc | 2102 | __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2103 | { |
AnnaBridge | 171:3a7713b1edbc | 2104 | CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); |
AnnaBridge | 171:3a7713b1edbc | 2105 | } |
AnnaBridge | 171:3a7713b1edbc | 2106 | |
AnnaBridge | 171:3a7713b1edbc | 2107 | /** |
AnnaBridge | 171:3a7713b1edbc | 2108 | * @brief Disable Transfer error interrupt. |
AnnaBridge | 171:3a7713b1edbc | 2109 | * @rmtoll CCR TEIE LL_DMA_DisableIT_TE |
AnnaBridge | 171:3a7713b1edbc | 2110 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2111 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2112 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 2113 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 2114 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 2115 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 2116 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 2117 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 2118 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 2119 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2120 | */ |
AnnaBridge | 171:3a7713b1edbc | 2121 | __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2122 | { |
AnnaBridge | 171:3a7713b1edbc | 2123 | CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); |
AnnaBridge | 171:3a7713b1edbc | 2124 | } |
AnnaBridge | 171:3a7713b1edbc | 2125 | |
AnnaBridge | 171:3a7713b1edbc | 2126 | /** |
AnnaBridge | 171:3a7713b1edbc | 2127 | * @brief Check if Transfer complete Interrupt is enabled. |
AnnaBridge | 171:3a7713b1edbc | 2128 | * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC |
AnnaBridge | 171:3a7713b1edbc | 2129 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2130 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2131 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 2132 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 2133 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 2134 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 2135 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 2136 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 2137 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 2138 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2139 | */ |
AnnaBridge | 171:3a7713b1edbc | 2140 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2141 | { |
AnnaBridge | 171:3a7713b1edbc | 2142 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 171:3a7713b1edbc | 2143 | DMA_CCR_TCIE) == (DMA_CCR_TCIE)); |
AnnaBridge | 171:3a7713b1edbc | 2144 | } |
AnnaBridge | 171:3a7713b1edbc | 2145 | |
AnnaBridge | 171:3a7713b1edbc | 2146 | /** |
AnnaBridge | 171:3a7713b1edbc | 2147 | * @brief Check if Half transfer Interrupt is enabled. |
AnnaBridge | 171:3a7713b1edbc | 2148 | * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT |
AnnaBridge | 171:3a7713b1edbc | 2149 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2150 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2151 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 2152 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 2153 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 2154 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 2155 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 2156 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 2157 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 2158 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2159 | */ |
AnnaBridge | 171:3a7713b1edbc | 2160 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2161 | { |
AnnaBridge | 171:3a7713b1edbc | 2162 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 171:3a7713b1edbc | 2163 | DMA_CCR_HTIE) == (DMA_CCR_HTIE)); |
AnnaBridge | 171:3a7713b1edbc | 2164 | } |
AnnaBridge | 171:3a7713b1edbc | 2165 | |
AnnaBridge | 171:3a7713b1edbc | 2166 | /** |
AnnaBridge | 171:3a7713b1edbc | 2167 | * @brief Check if Transfer error Interrupt is enabled. |
AnnaBridge | 171:3a7713b1edbc | 2168 | * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE |
AnnaBridge | 171:3a7713b1edbc | 2169 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2170 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2171 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 2172 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 2173 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 2174 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 2175 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 2176 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 2177 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 2178 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2179 | */ |
AnnaBridge | 171:3a7713b1edbc | 2180 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2181 | { |
AnnaBridge | 171:3a7713b1edbc | 2182 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
AnnaBridge | 171:3a7713b1edbc | 2183 | DMA_CCR_TEIE) == (DMA_CCR_TEIE)); |
AnnaBridge | 171:3a7713b1edbc | 2184 | } |
AnnaBridge | 171:3a7713b1edbc | 2185 | |
AnnaBridge | 171:3a7713b1edbc | 2186 | /** |
AnnaBridge | 171:3a7713b1edbc | 2187 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2188 | */ |
AnnaBridge | 171:3a7713b1edbc | 2189 | |
AnnaBridge | 171:3a7713b1edbc | 2190 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 2191 | /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions |
AnnaBridge | 171:3a7713b1edbc | 2192 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2193 | */ |
AnnaBridge | 171:3a7713b1edbc | 2194 | |
AnnaBridge | 171:3a7713b1edbc | 2195 | uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); |
AnnaBridge | 171:3a7713b1edbc | 2196 | uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); |
AnnaBridge | 171:3a7713b1edbc | 2197 | void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); |
AnnaBridge | 171:3a7713b1edbc | 2198 | |
AnnaBridge | 171:3a7713b1edbc | 2199 | /** |
AnnaBridge | 171:3a7713b1edbc | 2200 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2201 | */ |
AnnaBridge | 171:3a7713b1edbc | 2202 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 171:3a7713b1edbc | 2203 | |
AnnaBridge | 171:3a7713b1edbc | 2204 | /** |
AnnaBridge | 171:3a7713b1edbc | 2205 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2206 | */ |
AnnaBridge | 171:3a7713b1edbc | 2207 | |
AnnaBridge | 171:3a7713b1edbc | 2208 | /** |
AnnaBridge | 171:3a7713b1edbc | 2209 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2210 | */ |
AnnaBridge | 171:3a7713b1edbc | 2211 | |
AnnaBridge | 171:3a7713b1edbc | 2212 | #endif /* DMA1 || DMA2 */ |
AnnaBridge | 171:3a7713b1edbc | 2213 | |
AnnaBridge | 171:3a7713b1edbc | 2214 | /** |
AnnaBridge | 171:3a7713b1edbc | 2215 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2216 | */ |
AnnaBridge | 171:3a7713b1edbc | 2217 | |
AnnaBridge | 171:3a7713b1edbc | 2218 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 2219 | } |
AnnaBridge | 171:3a7713b1edbc | 2220 | #endif |
AnnaBridge | 171:3a7713b1edbc | 2221 | |
AnnaBridge | 171:3a7713b1edbc | 2222 | #endif /* __STM32F0xx_LL_DMA_H */ |
AnnaBridge | 171:3a7713b1edbc | 2223 | |
AnnaBridge | 171:3a7713b1edbc | 2224 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |