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TARGET_NUCLEO_F042K6/TOOLCHAIN_GCC_ARM/stm32f0xx_hal_rcc_ex.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f0xx_hal_rcc_ex.h |
AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of RCC HAL Extension module. |
AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
AnnaBridge | 171:3a7713b1edbc | 8 | * |
AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
AnnaBridge | 171:3a7713b1edbc | 10 | * |
AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 32 | * |
AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 34 | */ |
AnnaBridge | 171:3a7713b1edbc | 35 | |
AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F0xx_HAL_RCC_EX_H |
AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F0xx_HAL_RCC_EX_H |
AnnaBridge | 171:3a7713b1edbc | 39 | |
AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
AnnaBridge | 171:3a7713b1edbc | 43 | |
AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f0xx_hal_def.h" |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32F0xx_HAL_Driver |
AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 49 | */ |
AnnaBridge | 171:3a7713b1edbc | 50 | |
AnnaBridge | 171:3a7713b1edbc | 51 | /** @addtogroup RCC |
AnnaBridge | 171:3a7713b1edbc | 52 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 53 | */ |
AnnaBridge | 171:3a7713b1edbc | 54 | |
AnnaBridge | 171:3a7713b1edbc | 55 | /** @addtogroup RCC_Private_Macros |
AnnaBridge | 171:3a7713b1edbc | 56 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 57 | */ |
AnnaBridge | 171:3a7713b1edbc | 58 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 59 | #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ |
AnnaBridge | 171:3a7713b1edbc | 60 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 61 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ |
AnnaBridge | 171:3a7713b1edbc | 62 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ |
AnnaBridge | 171:3a7713b1edbc | 63 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 64 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \ |
AnnaBridge | 171:3a7713b1edbc | 65 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) |
AnnaBridge | 171:3a7713b1edbc | 66 | |
AnnaBridge | 171:3a7713b1edbc | 67 | #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ |
AnnaBridge | 171:3a7713b1edbc | 68 | ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 69 | ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \ |
AnnaBridge | 171:3a7713b1edbc | 70 | ((SOURCE) == RCC_SYSCLKSOURCE_HSI48)) |
AnnaBridge | 171:3a7713b1edbc | 71 | |
AnnaBridge | 171:3a7713b1edbc | 72 | #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ |
AnnaBridge | 171:3a7713b1edbc | 73 | ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 74 | ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \ |
AnnaBridge | 171:3a7713b1edbc | 75 | ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48)) |
AnnaBridge | 171:3a7713b1edbc | 76 | |
AnnaBridge | 171:3a7713b1edbc | 77 | #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ |
AnnaBridge | 171:3a7713b1edbc | 78 | ((SOURCE) == RCC_PLLSOURCE_HSI48) || \ |
AnnaBridge | 171:3a7713b1edbc | 79 | ((SOURCE) == RCC_PLLSOURCE_HSE)) |
AnnaBridge | 171:3a7713b1edbc | 80 | |
AnnaBridge | 171:3a7713b1edbc | 81 | #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON)) |
AnnaBridge | 171:3a7713b1edbc | 82 | |
AnnaBridge | 171:3a7713b1edbc | 83 | #else |
AnnaBridge | 171:3a7713b1edbc | 84 | |
AnnaBridge | 171:3a7713b1edbc | 85 | #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ |
AnnaBridge | 171:3a7713b1edbc | 86 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 87 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ |
AnnaBridge | 171:3a7713b1edbc | 88 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ |
AnnaBridge | 171:3a7713b1edbc | 89 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 90 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)) |
AnnaBridge | 171:3a7713b1edbc | 91 | #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ |
AnnaBridge | 171:3a7713b1edbc | 92 | ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 93 | ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) |
AnnaBridge | 171:3a7713b1edbc | 94 | |
AnnaBridge | 171:3a7713b1edbc | 95 | #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ |
AnnaBridge | 171:3a7713b1edbc | 96 | ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 97 | ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) |
AnnaBridge | 171:3a7713b1edbc | 98 | #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ |
AnnaBridge | 171:3a7713b1edbc | 99 | ((SOURCE) == RCC_PLLSOURCE_HSE)) |
AnnaBridge | 171:3a7713b1edbc | 100 | |
AnnaBridge | 171:3a7713b1edbc | 101 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 102 | |
AnnaBridge | 171:3a7713b1edbc | 103 | #if defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48) |
AnnaBridge | 171:3a7713b1edbc | 104 | |
AnnaBridge | 171:3a7713b1edbc | 105 | #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ |
AnnaBridge | 171:3a7713b1edbc | 106 | ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ |
AnnaBridge | 171:3a7713b1edbc | 107 | ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 108 | ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ |
AnnaBridge | 171:3a7713b1edbc | 109 | ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ |
AnnaBridge | 171:3a7713b1edbc | 110 | ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 111 | ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \ |
AnnaBridge | 171:3a7713b1edbc | 112 | ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ |
AnnaBridge | 171:3a7713b1edbc | 113 | ((SOURCE) == RCC_MCO1SOURCE_HSI14)) |
AnnaBridge | 171:3a7713b1edbc | 114 | |
AnnaBridge | 171:3a7713b1edbc | 115 | #elif defined(RCC_CFGR_PLLNODIV) && defined(RCC_CFGR_MCO_HSI48) |
AnnaBridge | 171:3a7713b1edbc | 116 | |
AnnaBridge | 171:3a7713b1edbc | 117 | #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ |
AnnaBridge | 171:3a7713b1edbc | 118 | ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ |
AnnaBridge | 171:3a7713b1edbc | 119 | ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 120 | ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ |
AnnaBridge | 171:3a7713b1edbc | 121 | ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ |
AnnaBridge | 171:3a7713b1edbc | 122 | ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 123 | ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \ |
AnnaBridge | 171:3a7713b1edbc | 124 | ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ |
AnnaBridge | 171:3a7713b1edbc | 125 | ((SOURCE) == RCC_MCO1SOURCE_HSI14) || \ |
AnnaBridge | 171:3a7713b1edbc | 126 | ((SOURCE) == RCC_MCO1SOURCE_HSI48)) |
AnnaBridge | 171:3a7713b1edbc | 127 | |
AnnaBridge | 171:3a7713b1edbc | 128 | #elif !defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48) |
AnnaBridge | 171:3a7713b1edbc | 129 | |
AnnaBridge | 171:3a7713b1edbc | 130 | #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ |
AnnaBridge | 171:3a7713b1edbc | 131 | ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ |
AnnaBridge | 171:3a7713b1edbc | 132 | ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 133 | ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ |
AnnaBridge | 171:3a7713b1edbc | 134 | ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ |
AnnaBridge | 171:3a7713b1edbc | 135 | ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 136 | ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ |
AnnaBridge | 171:3a7713b1edbc | 137 | ((SOURCE) == RCC_MCO1SOURCE_HSI14)) |
AnnaBridge | 171:3a7713b1edbc | 138 | |
AnnaBridge | 171:3a7713b1edbc | 139 | #endif /* RCC_CFGR_PLLNODIV && !RCC_CFGR_MCO_HSI48 */ |
AnnaBridge | 171:3a7713b1edbc | 140 | |
AnnaBridge | 171:3a7713b1edbc | 141 | /** |
AnnaBridge | 171:3a7713b1edbc | 142 | * @} |
AnnaBridge | 171:3a7713b1edbc | 143 | */ |
AnnaBridge | 171:3a7713b1edbc | 144 | |
AnnaBridge | 171:3a7713b1edbc | 145 | /** @addtogroup RCC_Exported_Constants |
AnnaBridge | 171:3a7713b1edbc | 146 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 147 | */ |
AnnaBridge | 171:3a7713b1edbc | 148 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 149 | |
AnnaBridge | 171:3a7713b1edbc | 150 | /** @addtogroup RCC_PLL_Clock_Source |
AnnaBridge | 171:3a7713b1edbc | 151 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 152 | */ |
AnnaBridge | 171:3a7713b1edbc | 153 | #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV |
AnnaBridge | 171:3a7713b1edbc | 154 | #define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV |
AnnaBridge | 171:3a7713b1edbc | 155 | |
AnnaBridge | 171:3a7713b1edbc | 156 | /** |
AnnaBridge | 171:3a7713b1edbc | 157 | * @} |
AnnaBridge | 171:3a7713b1edbc | 158 | */ |
AnnaBridge | 171:3a7713b1edbc | 159 | |
AnnaBridge | 171:3a7713b1edbc | 160 | /** @addtogroup RCC_Interrupt |
AnnaBridge | 171:3a7713b1edbc | 161 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 162 | */ |
AnnaBridge | 171:3a7713b1edbc | 163 | #define RCC_IT_HSI48 RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ |
AnnaBridge | 171:3a7713b1edbc | 164 | /** |
AnnaBridge | 171:3a7713b1edbc | 165 | * @} |
AnnaBridge | 171:3a7713b1edbc | 166 | */ |
AnnaBridge | 171:3a7713b1edbc | 167 | |
AnnaBridge | 171:3a7713b1edbc | 168 | /** @addtogroup RCC_Flag |
AnnaBridge | 171:3a7713b1edbc | 169 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 170 | */ |
AnnaBridge | 171:3a7713b1edbc | 171 | #define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5U) | RCC_CR2_HSI48RDY_BitNumber)) |
AnnaBridge | 171:3a7713b1edbc | 172 | /** |
AnnaBridge | 171:3a7713b1edbc | 173 | * @} |
AnnaBridge | 171:3a7713b1edbc | 174 | */ |
AnnaBridge | 171:3a7713b1edbc | 175 | |
AnnaBridge | 171:3a7713b1edbc | 176 | /** @addtogroup RCC_System_Clock_Source |
AnnaBridge | 171:3a7713b1edbc | 177 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 178 | */ |
AnnaBridge | 171:3a7713b1edbc | 179 | #define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 |
AnnaBridge | 171:3a7713b1edbc | 180 | /** |
AnnaBridge | 171:3a7713b1edbc | 181 | * @} |
AnnaBridge | 171:3a7713b1edbc | 182 | */ |
AnnaBridge | 171:3a7713b1edbc | 183 | |
AnnaBridge | 171:3a7713b1edbc | 184 | /** @addtogroup RCC_System_Clock_Source_Status |
AnnaBridge | 171:3a7713b1edbc | 185 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 186 | */ |
AnnaBridge | 171:3a7713b1edbc | 187 | #define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 |
AnnaBridge | 171:3a7713b1edbc | 188 | /** |
AnnaBridge | 171:3a7713b1edbc | 189 | * @} |
AnnaBridge | 171:3a7713b1edbc | 190 | */ |
AnnaBridge | 171:3a7713b1edbc | 191 | |
AnnaBridge | 171:3a7713b1edbc | 192 | #else |
AnnaBridge | 171:3a7713b1edbc | 193 | /** @addtogroup RCC_PLL_Clock_Source |
AnnaBridge | 171:3a7713b1edbc | 194 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 195 | */ |
AnnaBridge | 171:3a7713b1edbc | 196 | |
AnnaBridge | 171:3a7713b1edbc | 197 | #if defined(STM32F070xB) || defined(STM32F070x6) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 198 | #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV |
AnnaBridge | 171:3a7713b1edbc | 199 | #else |
AnnaBridge | 171:3a7713b1edbc | 200 | #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 |
AnnaBridge | 171:3a7713b1edbc | 201 | #endif |
AnnaBridge | 171:3a7713b1edbc | 202 | |
AnnaBridge | 171:3a7713b1edbc | 203 | /** |
AnnaBridge | 171:3a7713b1edbc | 204 | * @} |
AnnaBridge | 171:3a7713b1edbc | 205 | */ |
AnnaBridge | 171:3a7713b1edbc | 206 | |
AnnaBridge | 171:3a7713b1edbc | 207 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 208 | |
AnnaBridge | 171:3a7713b1edbc | 209 | /** @addtogroup RCC_MCO_Clock_Source |
AnnaBridge | 171:3a7713b1edbc | 210 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 211 | */ |
AnnaBridge | 171:3a7713b1edbc | 212 | |
AnnaBridge | 171:3a7713b1edbc | 213 | #if defined(RCC_CFGR_PLLNODIV) |
AnnaBridge | 171:3a7713b1edbc | 214 | |
AnnaBridge | 171:3a7713b1edbc | 215 | #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV) |
AnnaBridge | 171:3a7713b1edbc | 216 | |
AnnaBridge | 171:3a7713b1edbc | 217 | #endif /* RCC_CFGR_PLLNODIV */ |
AnnaBridge | 171:3a7713b1edbc | 218 | |
AnnaBridge | 171:3a7713b1edbc | 219 | #if defined(RCC_CFGR_MCO_HSI48) |
AnnaBridge | 171:3a7713b1edbc | 220 | |
AnnaBridge | 171:3a7713b1edbc | 221 | #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48 |
AnnaBridge | 171:3a7713b1edbc | 222 | |
AnnaBridge | 171:3a7713b1edbc | 223 | #endif /* SRCC_CFGR_MCO_HSI48 */ |
AnnaBridge | 171:3a7713b1edbc | 224 | /** |
AnnaBridge | 171:3a7713b1edbc | 225 | * @} |
AnnaBridge | 171:3a7713b1edbc | 226 | */ |
AnnaBridge | 171:3a7713b1edbc | 227 | |
AnnaBridge | 171:3a7713b1edbc | 228 | /** |
AnnaBridge | 171:3a7713b1edbc | 229 | * @} |
AnnaBridge | 171:3a7713b1edbc | 230 | */ |
AnnaBridge | 171:3a7713b1edbc | 231 | |
AnnaBridge | 171:3a7713b1edbc | 232 | /** |
AnnaBridge | 171:3a7713b1edbc | 233 | * @} |
AnnaBridge | 171:3a7713b1edbc | 234 | */ |
AnnaBridge | 171:3a7713b1edbc | 235 | |
AnnaBridge | 171:3a7713b1edbc | 236 | /** @addtogroup RCCEx |
AnnaBridge | 171:3a7713b1edbc | 237 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 238 | */ |
AnnaBridge | 171:3a7713b1edbc | 239 | |
AnnaBridge | 171:3a7713b1edbc | 240 | /* Private Constants -------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 241 | #if defined(CRS) |
AnnaBridge | 171:3a7713b1edbc | 242 | /** @addtogroup RCCEx_Private_Constants |
AnnaBridge | 171:3a7713b1edbc | 243 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 244 | */ |
AnnaBridge | 171:3a7713b1edbc | 245 | |
AnnaBridge | 171:3a7713b1edbc | 246 | /* CRS IT Error Mask */ |
AnnaBridge | 171:3a7713b1edbc | 247 | #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) |
AnnaBridge | 171:3a7713b1edbc | 248 | |
AnnaBridge | 171:3a7713b1edbc | 249 | /* CRS Flag Error Mask */ |
AnnaBridge | 171:3a7713b1edbc | 250 | #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) |
AnnaBridge | 171:3a7713b1edbc | 251 | |
AnnaBridge | 171:3a7713b1edbc | 252 | /** |
AnnaBridge | 171:3a7713b1edbc | 253 | * @} |
AnnaBridge | 171:3a7713b1edbc | 254 | */ |
AnnaBridge | 171:3a7713b1edbc | 255 | #endif /* CRS */ |
AnnaBridge | 171:3a7713b1edbc | 256 | |
AnnaBridge | 171:3a7713b1edbc | 257 | /* Private macro -------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 258 | /** @defgroup RCCEx_Private_Macros RCCEx Private Macros |
AnnaBridge | 171:3a7713b1edbc | 259 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 260 | */ |
AnnaBridge | 171:3a7713b1edbc | 261 | #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ |
AnnaBridge | 171:3a7713b1edbc | 262 | || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 263 | |
AnnaBridge | 171:3a7713b1edbc | 264 | #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ |
AnnaBridge | 171:3a7713b1edbc | 265 | RCC_PERIPHCLK_RTC)) |
AnnaBridge | 171:3a7713b1edbc | 266 | #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || |
AnnaBridge | 171:3a7713b1edbc | 267 | STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 268 | |
AnnaBridge | 171:3a7713b1edbc | 269 | #if defined(STM32F070x6) || defined(STM32F070xB) |
AnnaBridge | 171:3a7713b1edbc | 270 | |
AnnaBridge | 171:3a7713b1edbc | 271 | #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ |
AnnaBridge | 171:3a7713b1edbc | 272 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB)) |
AnnaBridge | 171:3a7713b1edbc | 273 | #endif /* STM32F070x6 || STM32F070xB */ |
AnnaBridge | 171:3a7713b1edbc | 274 | |
AnnaBridge | 171:3a7713b1edbc | 275 | #if defined(STM32F042x6) || defined(STM32F048xx) |
AnnaBridge | 171:3a7713b1edbc | 276 | |
AnnaBridge | 171:3a7713b1edbc | 277 | #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ |
AnnaBridge | 171:3a7713b1edbc | 278 | RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \ |
AnnaBridge | 171:3a7713b1edbc | 279 | RCC_PERIPHCLK_USB)) |
AnnaBridge | 171:3a7713b1edbc | 280 | #endif /* STM32F042x6 || STM32F048xx */ |
AnnaBridge | 171:3a7713b1edbc | 281 | |
AnnaBridge | 171:3a7713b1edbc | 282 | #if defined(STM32F051x8) || defined(STM32F058xx) |
AnnaBridge | 171:3a7713b1edbc | 283 | |
AnnaBridge | 171:3a7713b1edbc | 284 | #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ |
AnnaBridge | 171:3a7713b1edbc | 285 | RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC)) |
AnnaBridge | 171:3a7713b1edbc | 286 | #endif /* STM32F051x8 || STM32F058xx */ |
AnnaBridge | 171:3a7713b1edbc | 287 | |
AnnaBridge | 171:3a7713b1edbc | 288 | #if defined(STM32F071xB) |
AnnaBridge | 171:3a7713b1edbc | 289 | |
AnnaBridge | 171:3a7713b1edbc | 290 | #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ |
AnnaBridge | 171:3a7713b1edbc | 291 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ |
AnnaBridge | 171:3a7713b1edbc | 292 | RCC_PERIPHCLK_RTC)) |
AnnaBridge | 171:3a7713b1edbc | 293 | #endif /* STM32F071xB */ |
AnnaBridge | 171:3a7713b1edbc | 294 | |
AnnaBridge | 171:3a7713b1edbc | 295 | #if defined(STM32F072xB) || defined(STM32F078xx) |
AnnaBridge | 171:3a7713b1edbc | 296 | |
AnnaBridge | 171:3a7713b1edbc | 297 | #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ |
AnnaBridge | 171:3a7713b1edbc | 298 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ |
AnnaBridge | 171:3a7713b1edbc | 299 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB)) |
AnnaBridge | 171:3a7713b1edbc | 300 | #endif /* STM32F072xB || STM32F078xx */ |
AnnaBridge | 171:3a7713b1edbc | 301 | |
AnnaBridge | 171:3a7713b1edbc | 302 | #if defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 303 | |
AnnaBridge | 171:3a7713b1edbc | 304 | #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ |
AnnaBridge | 171:3a7713b1edbc | 305 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ |
AnnaBridge | 171:3a7713b1edbc | 306 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 )) |
AnnaBridge | 171:3a7713b1edbc | 307 | #endif /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 308 | |
AnnaBridge | 171:3a7713b1edbc | 309 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) |
AnnaBridge | 171:3a7713b1edbc | 310 | |
AnnaBridge | 171:3a7713b1edbc | 311 | #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \ |
AnnaBridge | 171:3a7713b1edbc | 312 | ((SOURCE) == RCC_USBCLKSOURCE_PLL)) |
AnnaBridge | 171:3a7713b1edbc | 313 | |
AnnaBridge | 171:3a7713b1edbc | 314 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */ |
AnnaBridge | 171:3a7713b1edbc | 315 | |
AnnaBridge | 171:3a7713b1edbc | 316 | #if defined(STM32F070x6) || defined(STM32F070xB) |
AnnaBridge | 171:3a7713b1edbc | 317 | |
AnnaBridge | 171:3a7713b1edbc | 318 | #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_NONE) || \ |
AnnaBridge | 171:3a7713b1edbc | 319 | ((SOURCE) == RCC_USBCLKSOURCE_PLL)) |
AnnaBridge | 171:3a7713b1edbc | 320 | |
AnnaBridge | 171:3a7713b1edbc | 321 | #endif /* STM32F070x6 || STM32F070xB */ |
AnnaBridge | 171:3a7713b1edbc | 322 | |
AnnaBridge | 171:3a7713b1edbc | 323 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
AnnaBridge | 171:3a7713b1edbc | 324 | || defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 325 | |
AnnaBridge | 171:3a7713b1edbc | 326 | #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ |
AnnaBridge | 171:3a7713b1edbc | 327 | ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ |
AnnaBridge | 171:3a7713b1edbc | 328 | ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 329 | ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) |
AnnaBridge | 171:3a7713b1edbc | 330 | |
AnnaBridge | 171:3a7713b1edbc | 331 | #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
AnnaBridge | 171:3a7713b1edbc | 332 | /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 333 | |
AnnaBridge | 171:3a7713b1edbc | 334 | #if defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 335 | |
AnnaBridge | 171:3a7713b1edbc | 336 | #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \ |
AnnaBridge | 171:3a7713b1edbc | 337 | ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \ |
AnnaBridge | 171:3a7713b1edbc | 338 | ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 339 | ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) |
AnnaBridge | 171:3a7713b1edbc | 340 | #endif /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 341 | |
AnnaBridge | 171:3a7713b1edbc | 342 | |
AnnaBridge | 171:3a7713b1edbc | 343 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
AnnaBridge | 171:3a7713b1edbc | 344 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 345 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
AnnaBridge | 171:3a7713b1edbc | 346 | || defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 347 | |
AnnaBridge | 171:3a7713b1edbc | 348 | #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ |
AnnaBridge | 171:3a7713b1edbc | 349 | ((SOURCE) == RCC_CECCLKSOURCE_LSE)) |
AnnaBridge | 171:3a7713b1edbc | 350 | #endif /* STM32F042x6 || STM32F048xx || */ |
AnnaBridge | 171:3a7713b1edbc | 351 | /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 352 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
AnnaBridge | 171:3a7713b1edbc | 353 | /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 354 | |
AnnaBridge | 171:3a7713b1edbc | 355 | #if defined(RCC_CFGR_MCOPRE) |
AnnaBridge | 171:3a7713b1edbc | 356 | |
AnnaBridge | 171:3a7713b1edbc | 357 | #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ |
AnnaBridge | 171:3a7713b1edbc | 358 | ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_8) || \ |
AnnaBridge | 171:3a7713b1edbc | 359 | ((DIV) == RCC_MCODIV_16) || ((DIV) == RCC_MCODIV_32) || \ |
AnnaBridge | 171:3a7713b1edbc | 360 | ((DIV) == RCC_MCODIV_64) || ((DIV) == RCC_MCODIV_128)) |
AnnaBridge | 171:3a7713b1edbc | 361 | #else |
AnnaBridge | 171:3a7713b1edbc | 362 | |
AnnaBridge | 171:3a7713b1edbc | 363 | #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)) |
AnnaBridge | 171:3a7713b1edbc | 364 | |
AnnaBridge | 171:3a7713b1edbc | 365 | #endif /* RCC_CFGR_MCOPRE */ |
AnnaBridge | 171:3a7713b1edbc | 366 | |
AnnaBridge | 171:3a7713b1edbc | 367 | #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ |
AnnaBridge | 171:3a7713b1edbc | 368 | ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ |
AnnaBridge | 171:3a7713b1edbc | 369 | ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ |
AnnaBridge | 171:3a7713b1edbc | 370 | ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) |
AnnaBridge | 171:3a7713b1edbc | 371 | |
AnnaBridge | 171:3a7713b1edbc | 372 | #if defined(CRS) |
AnnaBridge | 171:3a7713b1edbc | 373 | |
AnnaBridge | 171:3a7713b1edbc | 374 | #define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \ |
AnnaBridge | 171:3a7713b1edbc | 375 | ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \ |
AnnaBridge | 171:3a7713b1edbc | 376 | ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB)) |
AnnaBridge | 171:3a7713b1edbc | 377 | #define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \ |
AnnaBridge | 171:3a7713b1edbc | 378 | ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \ |
AnnaBridge | 171:3a7713b1edbc | 379 | ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \ |
AnnaBridge | 171:3a7713b1edbc | 380 | ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128)) |
AnnaBridge | 171:3a7713b1edbc | 381 | #define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \ |
AnnaBridge | 171:3a7713b1edbc | 382 | ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING)) |
AnnaBridge | 171:3a7713b1edbc | 383 | #define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFFU)) |
AnnaBridge | 171:3a7713b1edbc | 384 | #define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFFU)) |
AnnaBridge | 171:3a7713b1edbc | 385 | #define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3FU)) |
AnnaBridge | 171:3a7713b1edbc | 386 | #define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \ |
AnnaBridge | 171:3a7713b1edbc | 387 | ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN)) |
AnnaBridge | 171:3a7713b1edbc | 388 | #endif /* CRS */ |
AnnaBridge | 171:3a7713b1edbc | 389 | /** |
AnnaBridge | 171:3a7713b1edbc | 390 | * @} |
AnnaBridge | 171:3a7713b1edbc | 391 | */ |
AnnaBridge | 171:3a7713b1edbc | 392 | |
AnnaBridge | 171:3a7713b1edbc | 393 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 394 | |
AnnaBridge | 171:3a7713b1edbc | 395 | /** @defgroup RCCEx_Exported_Types RCCEx Exported Types |
AnnaBridge | 171:3a7713b1edbc | 396 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 397 | */ |
AnnaBridge | 171:3a7713b1edbc | 398 | |
AnnaBridge | 171:3a7713b1edbc | 399 | /** |
AnnaBridge | 171:3a7713b1edbc | 400 | * @brief RCC extended clocks structure definition |
AnnaBridge | 171:3a7713b1edbc | 401 | */ |
AnnaBridge | 171:3a7713b1edbc | 402 | #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ |
AnnaBridge | 171:3a7713b1edbc | 403 | || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 404 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 405 | { |
AnnaBridge | 171:3a7713b1edbc | 406 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
AnnaBridge | 171:3a7713b1edbc | 407 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
AnnaBridge | 171:3a7713b1edbc | 408 | |
AnnaBridge | 171:3a7713b1edbc | 409 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
AnnaBridge | 171:3a7713b1edbc | 410 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 411 | |
AnnaBridge | 171:3a7713b1edbc | 412 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
AnnaBridge | 171:3a7713b1edbc | 413 | This parameter can be a value of @ref RCC_USART1_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 414 | |
AnnaBridge | 171:3a7713b1edbc | 415 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
AnnaBridge | 171:3a7713b1edbc | 416 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 417 | |
AnnaBridge | 171:3a7713b1edbc | 418 | }RCC_PeriphCLKInitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 419 | #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || |
AnnaBridge | 171:3a7713b1edbc | 420 | STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 421 | |
AnnaBridge | 171:3a7713b1edbc | 422 | #if defined(STM32F070x6) || defined(STM32F070xB) |
AnnaBridge | 171:3a7713b1edbc | 423 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 424 | { |
AnnaBridge | 171:3a7713b1edbc | 425 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
AnnaBridge | 171:3a7713b1edbc | 426 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
AnnaBridge | 171:3a7713b1edbc | 427 | |
AnnaBridge | 171:3a7713b1edbc | 428 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
AnnaBridge | 171:3a7713b1edbc | 429 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 430 | |
AnnaBridge | 171:3a7713b1edbc | 431 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
AnnaBridge | 171:3a7713b1edbc | 432 | This parameter can be a value of @ref RCC_USART1_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 433 | |
AnnaBridge | 171:3a7713b1edbc | 434 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
AnnaBridge | 171:3a7713b1edbc | 435 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 436 | |
AnnaBridge | 171:3a7713b1edbc | 437 | uint32_t UsbClockSelection; /*!< USB clock source |
AnnaBridge | 171:3a7713b1edbc | 438 | This parameter can be a value of @ref RCCEx_USB_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 439 | |
AnnaBridge | 171:3a7713b1edbc | 440 | }RCC_PeriphCLKInitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 441 | #endif /* STM32F070x6 || STM32F070xB */ |
AnnaBridge | 171:3a7713b1edbc | 442 | |
AnnaBridge | 171:3a7713b1edbc | 443 | #if defined(STM32F042x6) || defined(STM32F048xx) |
AnnaBridge | 171:3a7713b1edbc | 444 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 445 | { |
AnnaBridge | 171:3a7713b1edbc | 446 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
AnnaBridge | 171:3a7713b1edbc | 447 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
AnnaBridge | 171:3a7713b1edbc | 448 | |
AnnaBridge | 171:3a7713b1edbc | 449 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
AnnaBridge | 171:3a7713b1edbc | 450 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 451 | |
AnnaBridge | 171:3a7713b1edbc | 452 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
AnnaBridge | 171:3a7713b1edbc | 453 | This parameter can be a value of @ref RCC_USART1_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 454 | |
AnnaBridge | 171:3a7713b1edbc | 455 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
AnnaBridge | 171:3a7713b1edbc | 456 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 457 | |
AnnaBridge | 171:3a7713b1edbc | 458 | uint32_t CecClockSelection; /*!< HDMI CEC clock source |
AnnaBridge | 171:3a7713b1edbc | 459 | This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 460 | |
AnnaBridge | 171:3a7713b1edbc | 461 | uint32_t UsbClockSelection; /*!< USB clock source |
AnnaBridge | 171:3a7713b1edbc | 462 | This parameter can be a value of @ref RCCEx_USB_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 463 | |
AnnaBridge | 171:3a7713b1edbc | 464 | }RCC_PeriphCLKInitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 465 | #endif /* STM32F042x6 || STM32F048xx */ |
AnnaBridge | 171:3a7713b1edbc | 466 | |
AnnaBridge | 171:3a7713b1edbc | 467 | #if defined(STM32F051x8) || defined(STM32F058xx) |
AnnaBridge | 171:3a7713b1edbc | 468 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 469 | { |
AnnaBridge | 171:3a7713b1edbc | 470 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
AnnaBridge | 171:3a7713b1edbc | 471 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
AnnaBridge | 171:3a7713b1edbc | 472 | |
AnnaBridge | 171:3a7713b1edbc | 473 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
AnnaBridge | 171:3a7713b1edbc | 474 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 475 | |
AnnaBridge | 171:3a7713b1edbc | 476 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
AnnaBridge | 171:3a7713b1edbc | 477 | This parameter can be a value of @ref RCC_USART1_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 478 | |
AnnaBridge | 171:3a7713b1edbc | 479 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
AnnaBridge | 171:3a7713b1edbc | 480 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 481 | |
AnnaBridge | 171:3a7713b1edbc | 482 | uint32_t CecClockSelection; /*!< HDMI CEC clock source |
AnnaBridge | 171:3a7713b1edbc | 483 | This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 484 | |
AnnaBridge | 171:3a7713b1edbc | 485 | }RCC_PeriphCLKInitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 486 | #endif /* STM32F051x8 || STM32F058xx */ |
AnnaBridge | 171:3a7713b1edbc | 487 | |
AnnaBridge | 171:3a7713b1edbc | 488 | #if defined(STM32F071xB) |
AnnaBridge | 171:3a7713b1edbc | 489 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 490 | { |
AnnaBridge | 171:3a7713b1edbc | 491 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
AnnaBridge | 171:3a7713b1edbc | 492 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
AnnaBridge | 171:3a7713b1edbc | 493 | |
AnnaBridge | 171:3a7713b1edbc | 494 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
AnnaBridge | 171:3a7713b1edbc | 495 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 496 | |
AnnaBridge | 171:3a7713b1edbc | 497 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
AnnaBridge | 171:3a7713b1edbc | 498 | This parameter can be a value of @ref RCC_USART1_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 499 | |
AnnaBridge | 171:3a7713b1edbc | 500 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
AnnaBridge | 171:3a7713b1edbc | 501 | This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 502 | |
AnnaBridge | 171:3a7713b1edbc | 503 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
AnnaBridge | 171:3a7713b1edbc | 504 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 505 | |
AnnaBridge | 171:3a7713b1edbc | 506 | uint32_t CecClockSelection; /*!< HDMI CEC clock source |
AnnaBridge | 171:3a7713b1edbc | 507 | This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 508 | |
AnnaBridge | 171:3a7713b1edbc | 509 | }RCC_PeriphCLKInitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 510 | #endif /* STM32F071xB */ |
AnnaBridge | 171:3a7713b1edbc | 511 | |
AnnaBridge | 171:3a7713b1edbc | 512 | #if defined(STM32F072xB) || defined(STM32F078xx) |
AnnaBridge | 171:3a7713b1edbc | 513 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 514 | { |
AnnaBridge | 171:3a7713b1edbc | 515 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
AnnaBridge | 171:3a7713b1edbc | 516 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
AnnaBridge | 171:3a7713b1edbc | 517 | |
AnnaBridge | 171:3a7713b1edbc | 518 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
AnnaBridge | 171:3a7713b1edbc | 519 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 520 | |
AnnaBridge | 171:3a7713b1edbc | 521 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
AnnaBridge | 171:3a7713b1edbc | 522 | This parameter can be a value of @ref RCC_USART1_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 523 | |
AnnaBridge | 171:3a7713b1edbc | 524 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
AnnaBridge | 171:3a7713b1edbc | 525 | This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 526 | |
AnnaBridge | 171:3a7713b1edbc | 527 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
AnnaBridge | 171:3a7713b1edbc | 528 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 529 | |
AnnaBridge | 171:3a7713b1edbc | 530 | uint32_t CecClockSelection; /*!< HDMI CEC clock source |
AnnaBridge | 171:3a7713b1edbc | 531 | This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 532 | |
AnnaBridge | 171:3a7713b1edbc | 533 | uint32_t UsbClockSelection; /*!< USB clock source |
AnnaBridge | 171:3a7713b1edbc | 534 | This parameter can be a value of @ref RCCEx_USB_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 535 | |
AnnaBridge | 171:3a7713b1edbc | 536 | }RCC_PeriphCLKInitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 537 | #endif /* STM32F072xB || STM32F078xx */ |
AnnaBridge | 171:3a7713b1edbc | 538 | |
AnnaBridge | 171:3a7713b1edbc | 539 | |
AnnaBridge | 171:3a7713b1edbc | 540 | #if defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 541 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 542 | { |
AnnaBridge | 171:3a7713b1edbc | 543 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
AnnaBridge | 171:3a7713b1edbc | 544 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
AnnaBridge | 171:3a7713b1edbc | 545 | |
AnnaBridge | 171:3a7713b1edbc | 546 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
AnnaBridge | 171:3a7713b1edbc | 547 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 548 | |
AnnaBridge | 171:3a7713b1edbc | 549 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
AnnaBridge | 171:3a7713b1edbc | 550 | This parameter can be a value of @ref RCC_USART1_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 551 | |
AnnaBridge | 171:3a7713b1edbc | 552 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
AnnaBridge | 171:3a7713b1edbc | 553 | This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 554 | |
AnnaBridge | 171:3a7713b1edbc | 555 | uint32_t Usart3ClockSelection; /*!< USART3 clock source |
AnnaBridge | 171:3a7713b1edbc | 556 | This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 557 | |
AnnaBridge | 171:3a7713b1edbc | 558 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
AnnaBridge | 171:3a7713b1edbc | 559 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 560 | |
AnnaBridge | 171:3a7713b1edbc | 561 | uint32_t CecClockSelection; /*!< HDMI CEC clock source |
AnnaBridge | 171:3a7713b1edbc | 562 | This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ |
AnnaBridge | 171:3a7713b1edbc | 563 | |
AnnaBridge | 171:3a7713b1edbc | 564 | }RCC_PeriphCLKInitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 565 | #endif /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 566 | |
AnnaBridge | 171:3a7713b1edbc | 567 | #if defined(CRS) |
AnnaBridge | 171:3a7713b1edbc | 568 | |
AnnaBridge | 171:3a7713b1edbc | 569 | /** |
AnnaBridge | 171:3a7713b1edbc | 570 | * @brief RCC_CRS Init structure definition |
AnnaBridge | 171:3a7713b1edbc | 571 | */ |
AnnaBridge | 171:3a7713b1edbc | 572 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 573 | { |
AnnaBridge | 171:3a7713b1edbc | 574 | uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. |
AnnaBridge | 171:3a7713b1edbc | 575 | This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ |
AnnaBridge | 171:3a7713b1edbc | 576 | |
AnnaBridge | 171:3a7713b1edbc | 577 | uint32_t Source; /*!< Specifies the SYNC signal source. |
AnnaBridge | 171:3a7713b1edbc | 578 | This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ |
AnnaBridge | 171:3a7713b1edbc | 579 | |
AnnaBridge | 171:3a7713b1edbc | 580 | uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. |
AnnaBridge | 171:3a7713b1edbc | 581 | This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ |
AnnaBridge | 171:3a7713b1edbc | 582 | |
AnnaBridge | 171:3a7713b1edbc | 583 | uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. |
AnnaBridge | 171:3a7713b1edbc | 584 | It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) |
AnnaBridge | 171:3a7713b1edbc | 585 | This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ |
AnnaBridge | 171:3a7713b1edbc | 586 | |
AnnaBridge | 171:3a7713b1edbc | 587 | uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. |
AnnaBridge | 171:3a7713b1edbc | 588 | This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ |
AnnaBridge | 171:3a7713b1edbc | 589 | |
AnnaBridge | 171:3a7713b1edbc | 590 | uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. |
AnnaBridge | 171:3a7713b1edbc | 591 | This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ |
AnnaBridge | 171:3a7713b1edbc | 592 | |
AnnaBridge | 171:3a7713b1edbc | 593 | }RCC_CRSInitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 594 | |
AnnaBridge | 171:3a7713b1edbc | 595 | /** |
AnnaBridge | 171:3a7713b1edbc | 596 | * @brief RCC_CRS Synchronization structure definition |
AnnaBridge | 171:3a7713b1edbc | 597 | */ |
AnnaBridge | 171:3a7713b1edbc | 598 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 599 | { |
AnnaBridge | 171:3a7713b1edbc | 600 | uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. |
AnnaBridge | 171:3a7713b1edbc | 601 | This parameter must be a number between 0 and 0xFFFFU */ |
AnnaBridge | 171:3a7713b1edbc | 602 | |
AnnaBridge | 171:3a7713b1edbc | 603 | uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. |
AnnaBridge | 171:3a7713b1edbc | 604 | This parameter must be a number between 0 and 0x3FU */ |
AnnaBridge | 171:3a7713b1edbc | 605 | |
AnnaBridge | 171:3a7713b1edbc | 606 | uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter |
AnnaBridge | 171:3a7713b1edbc | 607 | value latched in the time of the last SYNC event. |
AnnaBridge | 171:3a7713b1edbc | 608 | This parameter must be a number between 0 and 0xFFFFU */ |
AnnaBridge | 171:3a7713b1edbc | 609 | |
AnnaBridge | 171:3a7713b1edbc | 610 | uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the |
AnnaBridge | 171:3a7713b1edbc | 611 | frequency error counter latched in the time of the last SYNC event. |
AnnaBridge | 171:3a7713b1edbc | 612 | It shows whether the actual frequency is below or above the target. |
AnnaBridge | 171:3a7713b1edbc | 613 | This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ |
AnnaBridge | 171:3a7713b1edbc | 614 | |
AnnaBridge | 171:3a7713b1edbc | 615 | }RCC_CRSSynchroInfoTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 616 | |
AnnaBridge | 171:3a7713b1edbc | 617 | #endif /* CRS */ |
AnnaBridge | 171:3a7713b1edbc | 618 | |
AnnaBridge | 171:3a7713b1edbc | 619 | /** |
AnnaBridge | 171:3a7713b1edbc | 620 | * @} |
AnnaBridge | 171:3a7713b1edbc | 621 | */ |
AnnaBridge | 171:3a7713b1edbc | 622 | |
AnnaBridge | 171:3a7713b1edbc | 623 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 624 | |
AnnaBridge | 171:3a7713b1edbc | 625 | /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants |
AnnaBridge | 171:3a7713b1edbc | 626 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 627 | */ |
AnnaBridge | 171:3a7713b1edbc | 628 | |
AnnaBridge | 171:3a7713b1edbc | 629 | /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection |
AnnaBridge | 171:3a7713b1edbc | 630 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 631 | */ |
AnnaBridge | 171:3a7713b1edbc | 632 | #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ |
AnnaBridge | 171:3a7713b1edbc | 633 | || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 634 | #define RCC_PERIPHCLK_USART1 (0x00000001U) |
AnnaBridge | 171:3a7713b1edbc | 635 | #define RCC_PERIPHCLK_I2C1 (0x00000020U) |
AnnaBridge | 171:3a7713b1edbc | 636 | #define RCC_PERIPHCLK_RTC (0x00010000U) |
AnnaBridge | 171:3a7713b1edbc | 637 | |
AnnaBridge | 171:3a7713b1edbc | 638 | #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || |
AnnaBridge | 171:3a7713b1edbc | 639 | STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 640 | |
AnnaBridge | 171:3a7713b1edbc | 641 | #if defined(STM32F070x6) || defined(STM32F070xB) |
AnnaBridge | 171:3a7713b1edbc | 642 | #define RCC_PERIPHCLK_USART1 (0x00000001U) |
AnnaBridge | 171:3a7713b1edbc | 643 | #define RCC_PERIPHCLK_I2C1 (0x00000020U) |
AnnaBridge | 171:3a7713b1edbc | 644 | #define RCC_PERIPHCLK_RTC (0x00010000U) |
AnnaBridge | 171:3a7713b1edbc | 645 | #define RCC_PERIPHCLK_USB (0x00020000U) |
AnnaBridge | 171:3a7713b1edbc | 646 | |
AnnaBridge | 171:3a7713b1edbc | 647 | #endif /* STM32F070x6 || STM32F070xB */ |
AnnaBridge | 171:3a7713b1edbc | 648 | |
AnnaBridge | 171:3a7713b1edbc | 649 | #if defined(STM32F042x6) || defined(STM32F048xx) |
AnnaBridge | 171:3a7713b1edbc | 650 | #define RCC_PERIPHCLK_USART1 (0x00000001U) |
AnnaBridge | 171:3a7713b1edbc | 651 | #define RCC_PERIPHCLK_I2C1 (0x00000020U) |
AnnaBridge | 171:3a7713b1edbc | 652 | #define RCC_PERIPHCLK_CEC (0x00000400U) |
AnnaBridge | 171:3a7713b1edbc | 653 | #define RCC_PERIPHCLK_RTC (0x00010000U) |
AnnaBridge | 171:3a7713b1edbc | 654 | #define RCC_PERIPHCLK_USB (0x00020000U) |
AnnaBridge | 171:3a7713b1edbc | 655 | |
AnnaBridge | 171:3a7713b1edbc | 656 | #endif /* STM32F042x6 || STM32F048xx */ |
AnnaBridge | 171:3a7713b1edbc | 657 | |
AnnaBridge | 171:3a7713b1edbc | 658 | #if defined(STM32F051x8) || defined(STM32F058xx) |
AnnaBridge | 171:3a7713b1edbc | 659 | #define RCC_PERIPHCLK_USART1 (0x00000001U) |
AnnaBridge | 171:3a7713b1edbc | 660 | #define RCC_PERIPHCLK_I2C1 (0x00000020U) |
AnnaBridge | 171:3a7713b1edbc | 661 | #define RCC_PERIPHCLK_CEC (0x00000400U) |
AnnaBridge | 171:3a7713b1edbc | 662 | #define RCC_PERIPHCLK_RTC (0x00010000U) |
AnnaBridge | 171:3a7713b1edbc | 663 | |
AnnaBridge | 171:3a7713b1edbc | 664 | #endif /* STM32F051x8 || STM32F058xx */ |
AnnaBridge | 171:3a7713b1edbc | 665 | |
AnnaBridge | 171:3a7713b1edbc | 666 | #if defined(STM32F071xB) |
AnnaBridge | 171:3a7713b1edbc | 667 | #define RCC_PERIPHCLK_USART1 (0x00000001U) |
AnnaBridge | 171:3a7713b1edbc | 668 | #define RCC_PERIPHCLK_USART2 (0x00000002U) |
AnnaBridge | 171:3a7713b1edbc | 669 | #define RCC_PERIPHCLK_I2C1 (0x00000020U) |
AnnaBridge | 171:3a7713b1edbc | 670 | #define RCC_PERIPHCLK_CEC (0x00000400U) |
AnnaBridge | 171:3a7713b1edbc | 671 | #define RCC_PERIPHCLK_RTC (0x00010000U) |
AnnaBridge | 171:3a7713b1edbc | 672 | |
AnnaBridge | 171:3a7713b1edbc | 673 | #endif /* STM32F071xB */ |
AnnaBridge | 171:3a7713b1edbc | 674 | |
AnnaBridge | 171:3a7713b1edbc | 675 | #if defined(STM32F072xB) || defined(STM32F078xx) |
AnnaBridge | 171:3a7713b1edbc | 676 | #define RCC_PERIPHCLK_USART1 (0x00000001U) |
AnnaBridge | 171:3a7713b1edbc | 677 | #define RCC_PERIPHCLK_USART2 (0x00000002U) |
AnnaBridge | 171:3a7713b1edbc | 678 | #define RCC_PERIPHCLK_I2C1 (0x00000020U) |
AnnaBridge | 171:3a7713b1edbc | 679 | #define RCC_PERIPHCLK_CEC (0x00000400U) |
AnnaBridge | 171:3a7713b1edbc | 680 | #define RCC_PERIPHCLK_RTC (0x00010000U) |
AnnaBridge | 171:3a7713b1edbc | 681 | #define RCC_PERIPHCLK_USB (0x00020000U) |
AnnaBridge | 171:3a7713b1edbc | 682 | |
AnnaBridge | 171:3a7713b1edbc | 683 | #endif /* STM32F072xB || STM32F078xx */ |
AnnaBridge | 171:3a7713b1edbc | 684 | |
AnnaBridge | 171:3a7713b1edbc | 685 | #if defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 686 | #define RCC_PERIPHCLK_USART1 (0x00000001U) |
AnnaBridge | 171:3a7713b1edbc | 687 | #define RCC_PERIPHCLK_USART2 (0x00000002U) |
AnnaBridge | 171:3a7713b1edbc | 688 | #define RCC_PERIPHCLK_I2C1 (0x00000020U) |
AnnaBridge | 171:3a7713b1edbc | 689 | #define RCC_PERIPHCLK_CEC (0x00000400U) |
AnnaBridge | 171:3a7713b1edbc | 690 | #define RCC_PERIPHCLK_RTC (0x00010000U) |
AnnaBridge | 171:3a7713b1edbc | 691 | #define RCC_PERIPHCLK_USART3 (0x00040000U) |
AnnaBridge | 171:3a7713b1edbc | 692 | |
AnnaBridge | 171:3a7713b1edbc | 693 | #endif /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 694 | |
AnnaBridge | 171:3a7713b1edbc | 695 | /** |
AnnaBridge | 171:3a7713b1edbc | 696 | * @} |
AnnaBridge | 171:3a7713b1edbc | 697 | */ |
AnnaBridge | 171:3a7713b1edbc | 698 | |
AnnaBridge | 171:3a7713b1edbc | 699 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) |
AnnaBridge | 171:3a7713b1edbc | 700 | |
AnnaBridge | 171:3a7713b1edbc | 701 | /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source |
AnnaBridge | 171:3a7713b1edbc | 702 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 703 | */ |
AnnaBridge | 171:3a7713b1edbc | 704 | #define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /*!< HSI48 clock selected as USB clock source */ |
AnnaBridge | 171:3a7713b1edbc | 705 | #define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL clock (PLLCLK) selected as USB clock */ |
AnnaBridge | 171:3a7713b1edbc | 706 | |
AnnaBridge | 171:3a7713b1edbc | 707 | /** |
AnnaBridge | 171:3a7713b1edbc | 708 | * @} |
AnnaBridge | 171:3a7713b1edbc | 709 | */ |
AnnaBridge | 171:3a7713b1edbc | 710 | |
AnnaBridge | 171:3a7713b1edbc | 711 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */ |
AnnaBridge | 171:3a7713b1edbc | 712 | |
AnnaBridge | 171:3a7713b1edbc | 713 | #if defined(STM32F070x6) || defined(STM32F070xB) |
AnnaBridge | 171:3a7713b1edbc | 714 | |
AnnaBridge | 171:3a7713b1edbc | 715 | /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source |
AnnaBridge | 171:3a7713b1edbc | 716 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 717 | */ |
AnnaBridge | 171:3a7713b1edbc | 718 | #define RCC_USBCLKSOURCE_NONE (0x00000000U) /*!< USB clock disabled */ |
AnnaBridge | 171:3a7713b1edbc | 719 | #define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL clock (PLLCLK) selected as USB clock */ |
AnnaBridge | 171:3a7713b1edbc | 720 | |
AnnaBridge | 171:3a7713b1edbc | 721 | /** |
AnnaBridge | 171:3a7713b1edbc | 722 | * @} |
AnnaBridge | 171:3a7713b1edbc | 723 | */ |
AnnaBridge | 171:3a7713b1edbc | 724 | |
AnnaBridge | 171:3a7713b1edbc | 725 | #endif /* STM32F070x6 || STM32F070xB */ |
AnnaBridge | 171:3a7713b1edbc | 726 | |
AnnaBridge | 171:3a7713b1edbc | 727 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
AnnaBridge | 171:3a7713b1edbc | 728 | || defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 729 | |
AnnaBridge | 171:3a7713b1edbc | 730 | /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source |
AnnaBridge | 171:3a7713b1edbc | 731 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 732 | */ |
AnnaBridge | 171:3a7713b1edbc | 733 | #define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK |
AnnaBridge | 171:3a7713b1edbc | 734 | #define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK |
AnnaBridge | 171:3a7713b1edbc | 735 | #define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE |
AnnaBridge | 171:3a7713b1edbc | 736 | #define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI |
AnnaBridge | 171:3a7713b1edbc | 737 | |
AnnaBridge | 171:3a7713b1edbc | 738 | /** |
AnnaBridge | 171:3a7713b1edbc | 739 | * @} |
AnnaBridge | 171:3a7713b1edbc | 740 | */ |
AnnaBridge | 171:3a7713b1edbc | 741 | |
AnnaBridge | 171:3a7713b1edbc | 742 | #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
AnnaBridge | 171:3a7713b1edbc | 743 | /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 744 | |
AnnaBridge | 171:3a7713b1edbc | 745 | #if defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 746 | |
AnnaBridge | 171:3a7713b1edbc | 747 | /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source |
AnnaBridge | 171:3a7713b1edbc | 748 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 749 | */ |
AnnaBridge | 171:3a7713b1edbc | 750 | #define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK |
AnnaBridge | 171:3a7713b1edbc | 751 | #define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK |
AnnaBridge | 171:3a7713b1edbc | 752 | #define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE |
AnnaBridge | 171:3a7713b1edbc | 753 | #define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI |
AnnaBridge | 171:3a7713b1edbc | 754 | |
AnnaBridge | 171:3a7713b1edbc | 755 | /** |
AnnaBridge | 171:3a7713b1edbc | 756 | * @} |
AnnaBridge | 171:3a7713b1edbc | 757 | */ |
AnnaBridge | 171:3a7713b1edbc | 758 | |
AnnaBridge | 171:3a7713b1edbc | 759 | #endif /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 760 | |
AnnaBridge | 171:3a7713b1edbc | 761 | |
AnnaBridge | 171:3a7713b1edbc | 762 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
AnnaBridge | 171:3a7713b1edbc | 763 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 764 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
AnnaBridge | 171:3a7713b1edbc | 765 | || defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 766 | |
AnnaBridge | 171:3a7713b1edbc | 767 | /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source |
AnnaBridge | 171:3a7713b1edbc | 768 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 769 | */ |
AnnaBridge | 171:3a7713b1edbc | 770 | #define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244 |
AnnaBridge | 171:3a7713b1edbc | 771 | #define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE |
AnnaBridge | 171:3a7713b1edbc | 772 | |
AnnaBridge | 171:3a7713b1edbc | 773 | /** |
AnnaBridge | 171:3a7713b1edbc | 774 | * @} |
AnnaBridge | 171:3a7713b1edbc | 775 | */ |
AnnaBridge | 171:3a7713b1edbc | 776 | |
AnnaBridge | 171:3a7713b1edbc | 777 | #endif /* STM32F042x6 || STM32F048xx || */ |
AnnaBridge | 171:3a7713b1edbc | 778 | /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 779 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
AnnaBridge | 171:3a7713b1edbc | 780 | /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 781 | |
AnnaBridge | 171:3a7713b1edbc | 782 | /** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler |
AnnaBridge | 171:3a7713b1edbc | 783 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 784 | */ |
AnnaBridge | 171:3a7713b1edbc | 785 | |
AnnaBridge | 171:3a7713b1edbc | 786 | #if defined(RCC_CFGR_MCOPRE) |
AnnaBridge | 171:3a7713b1edbc | 787 | |
AnnaBridge | 171:3a7713b1edbc | 788 | #define RCC_MCODIV_1 (0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 789 | #define RCC_MCODIV_2 (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 790 | #define RCC_MCODIV_4 (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 791 | #define RCC_MCODIV_8 (0x30000000U) |
AnnaBridge | 171:3a7713b1edbc | 792 | #define RCC_MCODIV_16 (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 793 | #define RCC_MCODIV_32 (0x50000000U) |
AnnaBridge | 171:3a7713b1edbc | 794 | #define RCC_MCODIV_64 (0x60000000U) |
AnnaBridge | 171:3a7713b1edbc | 795 | #define RCC_MCODIV_128 (0x70000000U) |
AnnaBridge | 171:3a7713b1edbc | 796 | |
AnnaBridge | 171:3a7713b1edbc | 797 | #else |
AnnaBridge | 171:3a7713b1edbc | 798 | |
AnnaBridge | 171:3a7713b1edbc | 799 | #define RCC_MCODIV_1 (0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 800 | |
AnnaBridge | 171:3a7713b1edbc | 801 | #endif /* RCC_CFGR_MCOPRE */ |
AnnaBridge | 171:3a7713b1edbc | 802 | |
AnnaBridge | 171:3a7713b1edbc | 803 | /** |
AnnaBridge | 171:3a7713b1edbc | 804 | * @} |
AnnaBridge | 171:3a7713b1edbc | 805 | */ |
AnnaBridge | 171:3a7713b1edbc | 806 | |
AnnaBridge | 171:3a7713b1edbc | 807 | /** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration |
AnnaBridge | 171:3a7713b1edbc | 808 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 809 | */ |
AnnaBridge | 171:3a7713b1edbc | 810 | |
AnnaBridge | 171:3a7713b1edbc | 811 | #define RCC_LSEDRIVE_LOW (0x00000000U) /*!< Xtal mode lower driving capability */ |
AnnaBridge | 171:3a7713b1edbc | 812 | #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ |
AnnaBridge | 171:3a7713b1edbc | 813 | #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ |
AnnaBridge | 171:3a7713b1edbc | 814 | #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ |
AnnaBridge | 171:3a7713b1edbc | 815 | |
AnnaBridge | 171:3a7713b1edbc | 816 | /** |
AnnaBridge | 171:3a7713b1edbc | 817 | * @} |
AnnaBridge | 171:3a7713b1edbc | 818 | */ |
AnnaBridge | 171:3a7713b1edbc | 819 | |
AnnaBridge | 171:3a7713b1edbc | 820 | #if defined(CRS) |
AnnaBridge | 171:3a7713b1edbc | 821 | |
AnnaBridge | 171:3a7713b1edbc | 822 | /** @defgroup RCCEx_CRS_Status RCCEx CRS Status |
AnnaBridge | 171:3a7713b1edbc | 823 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 824 | */ |
AnnaBridge | 171:3a7713b1edbc | 825 | #define RCC_CRS_NONE (0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 826 | #define RCC_CRS_TIMEOUT (0x00000001U) |
AnnaBridge | 171:3a7713b1edbc | 827 | #define RCC_CRS_SYNCOK (0x00000002U) |
AnnaBridge | 171:3a7713b1edbc | 828 | #define RCC_CRS_SYNCWARN (0x00000004U) |
AnnaBridge | 171:3a7713b1edbc | 829 | #define RCC_CRS_SYNCERR (0x00000008U) |
AnnaBridge | 171:3a7713b1edbc | 830 | #define RCC_CRS_SYNCMISS (0x00000010U) |
AnnaBridge | 171:3a7713b1edbc | 831 | #define RCC_CRS_TRIMOVF (0x00000020U) |
AnnaBridge | 171:3a7713b1edbc | 832 | |
AnnaBridge | 171:3a7713b1edbc | 833 | /** |
AnnaBridge | 171:3a7713b1edbc | 834 | * @} |
AnnaBridge | 171:3a7713b1edbc | 835 | */ |
AnnaBridge | 171:3a7713b1edbc | 836 | |
AnnaBridge | 171:3a7713b1edbc | 837 | /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source |
AnnaBridge | 171:3a7713b1edbc | 838 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 839 | */ |
AnnaBridge | 171:3a7713b1edbc | 840 | #define RCC_CRS_SYNC_SOURCE_GPIO (0x00000000U) /*!< Synchro Signal source GPIO */ |
AnnaBridge | 171:3a7713b1edbc | 841 | #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ |
AnnaBridge | 171:3a7713b1edbc | 842 | #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ |
AnnaBridge | 171:3a7713b1edbc | 843 | /** |
AnnaBridge | 171:3a7713b1edbc | 844 | * @} |
AnnaBridge | 171:3a7713b1edbc | 845 | */ |
AnnaBridge | 171:3a7713b1edbc | 846 | |
AnnaBridge | 171:3a7713b1edbc | 847 | /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider |
AnnaBridge | 171:3a7713b1edbc | 848 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 849 | */ |
AnnaBridge | 171:3a7713b1edbc | 850 | #define RCC_CRS_SYNC_DIV1 (0x00000000U) /*!< Synchro Signal not divided (default) */ |
AnnaBridge | 171:3a7713b1edbc | 851 | #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ |
AnnaBridge | 171:3a7713b1edbc | 852 | #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ |
AnnaBridge | 171:3a7713b1edbc | 853 | #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ |
AnnaBridge | 171:3a7713b1edbc | 854 | #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ |
AnnaBridge | 171:3a7713b1edbc | 855 | #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ |
AnnaBridge | 171:3a7713b1edbc | 856 | #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ |
AnnaBridge | 171:3a7713b1edbc | 857 | #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ |
AnnaBridge | 171:3a7713b1edbc | 858 | /** |
AnnaBridge | 171:3a7713b1edbc | 859 | * @} |
AnnaBridge | 171:3a7713b1edbc | 860 | */ |
AnnaBridge | 171:3a7713b1edbc | 861 | |
AnnaBridge | 171:3a7713b1edbc | 862 | /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity |
AnnaBridge | 171:3a7713b1edbc | 863 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 864 | */ |
AnnaBridge | 171:3a7713b1edbc | 865 | #define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) /*!< Synchro Active on rising edge (default) */ |
AnnaBridge | 171:3a7713b1edbc | 866 | #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ |
AnnaBridge | 171:3a7713b1edbc | 867 | /** |
AnnaBridge | 171:3a7713b1edbc | 868 | * @} |
AnnaBridge | 171:3a7713b1edbc | 869 | */ |
AnnaBridge | 171:3a7713b1edbc | 870 | |
AnnaBridge | 171:3a7713b1edbc | 871 | /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value |
AnnaBridge | 171:3a7713b1edbc | 872 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 873 | */ |
AnnaBridge | 171:3a7713b1edbc | 874 | #define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds |
AnnaBridge | 171:3a7713b1edbc | 875 | to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ |
AnnaBridge | 171:3a7713b1edbc | 876 | /** |
AnnaBridge | 171:3a7713b1edbc | 877 | * @} |
AnnaBridge | 171:3a7713b1edbc | 878 | */ |
AnnaBridge | 171:3a7713b1edbc | 879 | |
AnnaBridge | 171:3a7713b1edbc | 880 | /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value |
AnnaBridge | 171:3a7713b1edbc | 881 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 882 | */ |
AnnaBridge | 171:3a7713b1edbc | 883 | #define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) /*!< Default Frequency error limit */ |
AnnaBridge | 171:3a7713b1edbc | 884 | /** |
AnnaBridge | 171:3a7713b1edbc | 885 | * @} |
AnnaBridge | 171:3a7713b1edbc | 886 | */ |
AnnaBridge | 171:3a7713b1edbc | 887 | |
AnnaBridge | 171:3a7713b1edbc | 888 | /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye |
AnnaBridge | 171:3a7713b1edbc | 889 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 890 | */ |
AnnaBridge | 171:3a7713b1edbc | 891 | #define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. |
AnnaBridge | 171:3a7713b1edbc | 892 | The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value |
AnnaBridge | 171:3a7713b1edbc | 893 | corresponds to a higher output frequency */ |
AnnaBridge | 171:3a7713b1edbc | 894 | /** |
AnnaBridge | 171:3a7713b1edbc | 895 | * @} |
AnnaBridge | 171:3a7713b1edbc | 896 | */ |
AnnaBridge | 171:3a7713b1edbc | 897 | |
AnnaBridge | 171:3a7713b1edbc | 898 | /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction |
AnnaBridge | 171:3a7713b1edbc | 899 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 900 | */ |
AnnaBridge | 171:3a7713b1edbc | 901 | #define RCC_CRS_FREQERRORDIR_UP (0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ |
AnnaBridge | 171:3a7713b1edbc | 902 | #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ |
AnnaBridge | 171:3a7713b1edbc | 903 | /** |
AnnaBridge | 171:3a7713b1edbc | 904 | * @} |
AnnaBridge | 171:3a7713b1edbc | 905 | */ |
AnnaBridge | 171:3a7713b1edbc | 906 | |
AnnaBridge | 171:3a7713b1edbc | 907 | /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources |
AnnaBridge | 171:3a7713b1edbc | 908 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 909 | */ |
AnnaBridge | 171:3a7713b1edbc | 910 | #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ |
AnnaBridge | 171:3a7713b1edbc | 911 | #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ |
AnnaBridge | 171:3a7713b1edbc | 912 | #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ |
AnnaBridge | 171:3a7713b1edbc | 913 | #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ |
AnnaBridge | 171:3a7713b1edbc | 914 | #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ |
AnnaBridge | 171:3a7713b1edbc | 915 | #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ |
AnnaBridge | 171:3a7713b1edbc | 916 | #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ |
AnnaBridge | 171:3a7713b1edbc | 917 | |
AnnaBridge | 171:3a7713b1edbc | 918 | /** |
AnnaBridge | 171:3a7713b1edbc | 919 | * @} |
AnnaBridge | 171:3a7713b1edbc | 920 | */ |
AnnaBridge | 171:3a7713b1edbc | 921 | |
AnnaBridge | 171:3a7713b1edbc | 922 | /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags |
AnnaBridge | 171:3a7713b1edbc | 923 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 924 | */ |
AnnaBridge | 171:3a7713b1edbc | 925 | #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ |
AnnaBridge | 171:3a7713b1edbc | 926 | #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ |
AnnaBridge | 171:3a7713b1edbc | 927 | #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ |
AnnaBridge | 171:3a7713b1edbc | 928 | #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ |
AnnaBridge | 171:3a7713b1edbc | 929 | #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ |
AnnaBridge | 171:3a7713b1edbc | 930 | #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ |
AnnaBridge | 171:3a7713b1edbc | 931 | #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ |
AnnaBridge | 171:3a7713b1edbc | 932 | |
AnnaBridge | 171:3a7713b1edbc | 933 | /** |
AnnaBridge | 171:3a7713b1edbc | 934 | * @} |
AnnaBridge | 171:3a7713b1edbc | 935 | */ |
AnnaBridge | 171:3a7713b1edbc | 936 | |
AnnaBridge | 171:3a7713b1edbc | 937 | #endif /* CRS */ |
AnnaBridge | 171:3a7713b1edbc | 938 | |
AnnaBridge | 171:3a7713b1edbc | 939 | /** |
AnnaBridge | 171:3a7713b1edbc | 940 | * @} |
AnnaBridge | 171:3a7713b1edbc | 941 | */ |
AnnaBridge | 171:3a7713b1edbc | 942 | |
AnnaBridge | 171:3a7713b1edbc | 943 | /* Exported macros ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 944 | /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros |
AnnaBridge | 171:3a7713b1edbc | 945 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 946 | */ |
AnnaBridge | 171:3a7713b1edbc | 947 | |
AnnaBridge | 171:3a7713b1edbc | 948 | /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable |
AnnaBridge | 171:3a7713b1edbc | 949 | * @brief Enables or disables the AHB1 peripheral clock. |
AnnaBridge | 171:3a7713b1edbc | 950 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 171:3a7713b1edbc | 951 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 171:3a7713b1edbc | 952 | * using it. |
AnnaBridge | 171:3a7713b1edbc | 953 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 954 | */ |
AnnaBridge | 171:3a7713b1edbc | 955 | #if defined(GPIOD) |
AnnaBridge | 171:3a7713b1edbc | 956 | |
AnnaBridge | 171:3a7713b1edbc | 957 | #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 958 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 959 | SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ |
AnnaBridge | 171:3a7713b1edbc | 960 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 961 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ |
AnnaBridge | 171:3a7713b1edbc | 962 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 963 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 964 | |
AnnaBridge | 171:3a7713b1edbc | 965 | #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) |
AnnaBridge | 171:3a7713b1edbc | 966 | |
AnnaBridge | 171:3a7713b1edbc | 967 | #endif /* GPIOD */ |
AnnaBridge | 171:3a7713b1edbc | 968 | |
AnnaBridge | 171:3a7713b1edbc | 969 | #if defined(GPIOE) |
AnnaBridge | 171:3a7713b1edbc | 970 | |
AnnaBridge | 171:3a7713b1edbc | 971 | #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 972 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 973 | SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ |
AnnaBridge | 171:3a7713b1edbc | 974 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 975 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ |
AnnaBridge | 171:3a7713b1edbc | 976 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 977 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 978 | |
AnnaBridge | 171:3a7713b1edbc | 979 | #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) |
AnnaBridge | 171:3a7713b1edbc | 980 | |
AnnaBridge | 171:3a7713b1edbc | 981 | #endif /* GPIOE */ |
AnnaBridge | 171:3a7713b1edbc | 982 | |
AnnaBridge | 171:3a7713b1edbc | 983 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
AnnaBridge | 171:3a7713b1edbc | 984 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 985 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
AnnaBridge | 171:3a7713b1edbc | 986 | || defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 987 | |
AnnaBridge | 171:3a7713b1edbc | 988 | #define __HAL_RCC_TSC_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 989 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 990 | SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ |
AnnaBridge | 171:3a7713b1edbc | 991 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 992 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ |
AnnaBridge | 171:3a7713b1edbc | 993 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 994 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 995 | |
AnnaBridge | 171:3a7713b1edbc | 996 | #define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN)) |
AnnaBridge | 171:3a7713b1edbc | 997 | |
AnnaBridge | 171:3a7713b1edbc | 998 | #endif /* STM32F042x6 || STM32F048xx || */ |
AnnaBridge | 171:3a7713b1edbc | 999 | /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1000 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1001 | /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 1002 | |
AnnaBridge | 171:3a7713b1edbc | 1003 | #if defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 1004 | |
AnnaBridge | 171:3a7713b1edbc | 1005 | #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1006 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1007 | SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1008 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1009 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1010 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1011 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 1012 | |
AnnaBridge | 171:3a7713b1edbc | 1013 | #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) |
AnnaBridge | 171:3a7713b1edbc | 1014 | |
AnnaBridge | 171:3a7713b1edbc | 1015 | #endif /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 1016 | |
AnnaBridge | 171:3a7713b1edbc | 1017 | /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
AnnaBridge | 171:3a7713b1edbc | 1018 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 171:3a7713b1edbc | 1019 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 171:3a7713b1edbc | 1020 | * using it. |
AnnaBridge | 171:3a7713b1edbc | 1021 | */ |
AnnaBridge | 171:3a7713b1edbc | 1022 | #if defined(STM32F030x8)\ |
AnnaBridge | 171:3a7713b1edbc | 1023 | || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ |
AnnaBridge | 171:3a7713b1edbc | 1024 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1025 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
AnnaBridge | 171:3a7713b1edbc | 1026 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 1027 | |
AnnaBridge | 171:3a7713b1edbc | 1028 | #define __HAL_RCC_USART2_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1029 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1030 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1031 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1032 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1033 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1034 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 1035 | |
AnnaBridge | 171:3a7713b1edbc | 1036 | #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) |
AnnaBridge | 171:3a7713b1edbc | 1037 | |
AnnaBridge | 171:3a7713b1edbc | 1038 | #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1039 | /* STM32F051x8 || STM32F058xx || STM32F070x6 || */ |
AnnaBridge | 171:3a7713b1edbc | 1040 | /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
AnnaBridge | 171:3a7713b1edbc | 1041 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 1042 | |
AnnaBridge | 171:3a7713b1edbc | 1043 | #if defined(STM32F030x8)\ |
AnnaBridge | 171:3a7713b1edbc | 1044 | || defined(STM32F042x6) || defined(STM32F048xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1045 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1046 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
AnnaBridge | 171:3a7713b1edbc | 1047 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 1048 | |
AnnaBridge | 171:3a7713b1edbc | 1049 | #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1050 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1051 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1052 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1053 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1054 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1055 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 1056 | |
AnnaBridge | 171:3a7713b1edbc | 1057 | #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) |
AnnaBridge | 171:3a7713b1edbc | 1058 | |
AnnaBridge | 171:3a7713b1edbc | 1059 | #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1060 | /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1061 | /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
AnnaBridge | 171:3a7713b1edbc | 1062 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 1063 | |
AnnaBridge | 171:3a7713b1edbc | 1064 | #if defined(STM32F031x6) || defined(STM32F038xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1065 | || defined(STM32F042x6) || defined(STM32F048xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1066 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1067 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1068 | || defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 1069 | |
AnnaBridge | 171:3a7713b1edbc | 1070 | #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1071 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1072 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1073 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1074 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1075 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1076 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 1077 | |
AnnaBridge | 171:3a7713b1edbc | 1078 | #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) |
AnnaBridge | 171:3a7713b1edbc | 1079 | |
AnnaBridge | 171:3a7713b1edbc | 1080 | #endif /* STM32F031x6 || STM32F038xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1081 | /* STM32F042x6 || STM32F048xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1082 | /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1083 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1084 | /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 1085 | |
AnnaBridge | 171:3a7713b1edbc | 1086 | #if defined(STM32F030x8) \ |
AnnaBridge | 171:3a7713b1edbc | 1087 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1088 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
AnnaBridge | 171:3a7713b1edbc | 1089 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 1090 | |
AnnaBridge | 171:3a7713b1edbc | 1091 | #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1092 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1093 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1094 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1095 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1096 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1097 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 1098 | #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1099 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1100 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1101 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1102 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1103 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1104 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 1105 | |
AnnaBridge | 171:3a7713b1edbc | 1106 | #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) |
AnnaBridge | 171:3a7713b1edbc | 1107 | #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) |
AnnaBridge | 171:3a7713b1edbc | 1108 | |
AnnaBridge | 171:3a7713b1edbc | 1109 | #endif /* STM32F030x8 || */ |
AnnaBridge | 171:3a7713b1edbc | 1110 | /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1111 | /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
AnnaBridge | 171:3a7713b1edbc | 1112 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 1113 | |
AnnaBridge | 171:3a7713b1edbc | 1114 | #if defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1115 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1116 | || defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 1117 | |
AnnaBridge | 171:3a7713b1edbc | 1118 | #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1119 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1120 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1121 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1122 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1123 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1124 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 1125 | |
AnnaBridge | 171:3a7713b1edbc | 1126 | #define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) |
AnnaBridge | 171:3a7713b1edbc | 1127 | |
AnnaBridge | 171:3a7713b1edbc | 1128 | #endif /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1129 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1130 | /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 1131 | |
AnnaBridge | 171:3a7713b1edbc | 1132 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1133 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1134 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1135 | || defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 1136 | |
AnnaBridge | 171:3a7713b1edbc | 1137 | #define __HAL_RCC_CEC_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1138 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1139 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1140 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1141 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1142 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1143 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 1144 | |
AnnaBridge | 171:3a7713b1edbc | 1145 | #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) |
AnnaBridge | 171:3a7713b1edbc | 1146 | |
AnnaBridge | 171:3a7713b1edbc | 1147 | #endif /* STM32F042x6 || STM32F048xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1148 | /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1149 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1150 | /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 1151 | |
AnnaBridge | 171:3a7713b1edbc | 1152 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
AnnaBridge | 171:3a7713b1edbc | 1153 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 1154 | |
AnnaBridge | 171:3a7713b1edbc | 1155 | #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1156 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1157 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1158 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1159 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1160 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1161 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 1162 | #define __HAL_RCC_USART3_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1163 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1164 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1165 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1166 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1167 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1168 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 1169 | #define __HAL_RCC_USART4_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1170 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1171 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1172 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1173 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1174 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1175 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 1176 | |
AnnaBridge | 171:3a7713b1edbc | 1177 | #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) |
AnnaBridge | 171:3a7713b1edbc | 1178 | #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) |
AnnaBridge | 171:3a7713b1edbc | 1179 | #define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN)) |
AnnaBridge | 171:3a7713b1edbc | 1180 | |
AnnaBridge | 171:3a7713b1edbc | 1181 | #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
AnnaBridge | 171:3a7713b1edbc | 1182 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 1183 | |
AnnaBridge | 171:3a7713b1edbc | 1184 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ |
AnnaBridge | 171:3a7713b1edbc | 1185 | || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) |
AnnaBridge | 171:3a7713b1edbc | 1186 | |
AnnaBridge | 171:3a7713b1edbc | 1187 | #define __HAL_RCC_USB_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1188 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1189 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1190 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1191 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1192 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1193 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 1194 | |
AnnaBridge | 171:3a7713b1edbc | 1195 | #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) |
AnnaBridge | 171:3a7713b1edbc | 1196 | |
AnnaBridge | 171:3a7713b1edbc | 1197 | #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ |
AnnaBridge | 171:3a7713b1edbc | 1198 | /* STM32F072xB || STM32F078xx || STM32F070xB */ |
AnnaBridge | 171:3a7713b1edbc | 1199 | |
AnnaBridge | 171:3a7713b1edbc | 1200 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ |
AnnaBridge | 171:3a7713b1edbc | 1201 | || defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 1202 | |
AnnaBridge | 171:3a7713b1edbc | 1203 | #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1204 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1205 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1206 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1207 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1208 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1209 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 1210 | #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN)) |
AnnaBridge | 171:3a7713b1edbc | 1211 | |
AnnaBridge | 171:3a7713b1edbc | 1212 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ |
AnnaBridge | 171:3a7713b1edbc | 1213 | /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 1214 | |
AnnaBridge | 171:3a7713b1edbc | 1215 | #if defined(CRS) |
AnnaBridge | 171:3a7713b1edbc | 1216 | |
AnnaBridge | 171:3a7713b1edbc | 1217 | #define __HAL_RCC_CRS_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1218 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1219 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1220 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1221 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\ |
AnnaBridge | 171:3a7713b1edbc | 1222 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1223 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 1224 | |
AnnaBridge | 171:3a7713b1edbc | 1225 | #define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN)) |
AnnaBridge | 171:3a7713b1edbc | 1226 | |
AnnaBridge | 171:3a7713b1edbc | 1227 | #endif /* CRS */ |
AnnaBridge | 171:3a7713b1edbc | 1228 | |
AnnaBridge | 171:3a7713b1edbc | 1229 | #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 1230 | |
AnnaBridge | 171:3a7713b1edbc | 1231 | #define __HAL_RCC_USART5_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1232 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1233 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1234 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1235 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1236 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1237 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 1238 | |
AnnaBridge | 171:3a7713b1edbc | 1239 | #define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN)) |
AnnaBridge | 171:3a7713b1edbc | 1240 | |
AnnaBridge | 171:3a7713b1edbc | 1241 | #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 1242 | |
AnnaBridge | 171:3a7713b1edbc | 1243 | /** @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
AnnaBridge | 171:3a7713b1edbc | 1244 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 171:3a7713b1edbc | 1245 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 171:3a7713b1edbc | 1246 | * using it. |
AnnaBridge | 171:3a7713b1edbc | 1247 | */ |
AnnaBridge | 171:3a7713b1edbc | 1248 | #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ |
AnnaBridge | 171:3a7713b1edbc | 1249 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1250 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
AnnaBridge | 171:3a7713b1edbc | 1251 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 1252 | |
AnnaBridge | 171:3a7713b1edbc | 1253 | #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1254 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1255 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1256 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1257 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1258 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1259 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 1260 | |
AnnaBridge | 171:3a7713b1edbc | 1261 | #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) |
AnnaBridge | 171:3a7713b1edbc | 1262 | |
AnnaBridge | 171:3a7713b1edbc | 1263 | #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ |
AnnaBridge | 171:3a7713b1edbc | 1264 | /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1265 | /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
AnnaBridge | 171:3a7713b1edbc | 1266 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 1267 | |
AnnaBridge | 171:3a7713b1edbc | 1268 | #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 1269 | |
AnnaBridge | 171:3a7713b1edbc | 1270 | #define __HAL_RCC_USART6_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1271 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1272 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1273 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1274 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1275 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1276 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 1277 | |
AnnaBridge | 171:3a7713b1edbc | 1278 | #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) |
AnnaBridge | 171:3a7713b1edbc | 1279 | |
AnnaBridge | 171:3a7713b1edbc | 1280 | #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 1281 | |
AnnaBridge | 171:3a7713b1edbc | 1282 | #if defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 1283 | |
AnnaBridge | 171:3a7713b1edbc | 1284 | #define __HAL_RCC_USART7_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1285 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1286 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1287 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1288 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1289 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1290 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 1291 | #define __HAL_RCC_USART8_CLK_ENABLE() do { \ |
AnnaBridge | 171:3a7713b1edbc | 1292 | __IO uint32_t tmpreg; \ |
AnnaBridge | 171:3a7713b1edbc | 1293 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1294 | /* Delay after an RCC peripheral clock enabling */ \ |
AnnaBridge | 171:3a7713b1edbc | 1295 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ |
AnnaBridge | 171:3a7713b1edbc | 1296 | UNUSED(tmpreg); \ |
AnnaBridge | 171:3a7713b1edbc | 1297 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 1298 | |
AnnaBridge | 171:3a7713b1edbc | 1299 | #define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN)) |
AnnaBridge | 171:3a7713b1edbc | 1300 | #define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN)) |
AnnaBridge | 171:3a7713b1edbc | 1301 | |
AnnaBridge | 171:3a7713b1edbc | 1302 | #endif /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 1303 | |
AnnaBridge | 171:3a7713b1edbc | 1304 | /** |
AnnaBridge | 171:3a7713b1edbc | 1305 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1306 | */ |
AnnaBridge | 171:3a7713b1edbc | 1307 | |
AnnaBridge | 171:3a7713b1edbc | 1308 | |
AnnaBridge | 171:3a7713b1edbc | 1309 | /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset |
AnnaBridge | 171:3a7713b1edbc | 1310 | * @brief Forces or releases peripheral reset. |
AnnaBridge | 171:3a7713b1edbc | 1311 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1312 | */ |
AnnaBridge | 171:3a7713b1edbc | 1313 | |
AnnaBridge | 171:3a7713b1edbc | 1314 | /** @brief Force or release AHB peripheral reset. |
AnnaBridge | 171:3a7713b1edbc | 1315 | */ |
AnnaBridge | 171:3a7713b1edbc | 1316 | #if defined(GPIOD) |
AnnaBridge | 171:3a7713b1edbc | 1317 | |
AnnaBridge | 171:3a7713b1edbc | 1318 | #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) |
AnnaBridge | 171:3a7713b1edbc | 1319 | |
AnnaBridge | 171:3a7713b1edbc | 1320 | #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) |
AnnaBridge | 171:3a7713b1edbc | 1321 | |
AnnaBridge | 171:3a7713b1edbc | 1322 | #endif /* GPIOD */ |
AnnaBridge | 171:3a7713b1edbc | 1323 | |
AnnaBridge | 171:3a7713b1edbc | 1324 | #if defined(GPIOE) |
AnnaBridge | 171:3a7713b1edbc | 1325 | |
AnnaBridge | 171:3a7713b1edbc | 1326 | #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) |
AnnaBridge | 171:3a7713b1edbc | 1327 | |
AnnaBridge | 171:3a7713b1edbc | 1328 | #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) |
AnnaBridge | 171:3a7713b1edbc | 1329 | |
AnnaBridge | 171:3a7713b1edbc | 1330 | #endif /* GPIOE */ |
AnnaBridge | 171:3a7713b1edbc | 1331 | |
AnnaBridge | 171:3a7713b1edbc | 1332 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1333 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1334 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1335 | || defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 1336 | |
AnnaBridge | 171:3a7713b1edbc | 1337 | #define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) |
AnnaBridge | 171:3a7713b1edbc | 1338 | |
AnnaBridge | 171:3a7713b1edbc | 1339 | #define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST)) |
AnnaBridge | 171:3a7713b1edbc | 1340 | |
AnnaBridge | 171:3a7713b1edbc | 1341 | #endif /* STM32F042x6 || STM32F048xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1342 | /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1343 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1344 | /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 1345 | |
AnnaBridge | 171:3a7713b1edbc | 1346 | /** @brief Force or release APB1 peripheral reset. |
AnnaBridge | 171:3a7713b1edbc | 1347 | */ |
AnnaBridge | 171:3a7713b1edbc | 1348 | #if defined(STM32F030x8) \ |
AnnaBridge | 171:3a7713b1edbc | 1349 | || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ |
AnnaBridge | 171:3a7713b1edbc | 1350 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1351 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
AnnaBridge | 171:3a7713b1edbc | 1352 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 1353 | |
AnnaBridge | 171:3a7713b1edbc | 1354 | #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1355 | #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1356 | |
AnnaBridge | 171:3a7713b1edbc | 1357 | #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1358 | #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1359 | |
AnnaBridge | 171:3a7713b1edbc | 1360 | #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ |
AnnaBridge | 171:3a7713b1edbc | 1361 | /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1362 | /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
AnnaBridge | 171:3a7713b1edbc | 1363 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 1364 | |
AnnaBridge | 171:3a7713b1edbc | 1365 | #if defined(STM32F031x6) || defined(STM32F038xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1366 | || defined(STM32F042x6) || defined(STM32F048xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1367 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1368 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1369 | || defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 1370 | |
AnnaBridge | 171:3a7713b1edbc | 1371 | #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1372 | |
AnnaBridge | 171:3a7713b1edbc | 1373 | #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1374 | |
AnnaBridge | 171:3a7713b1edbc | 1375 | #endif /* STM32F031x6 || STM32F038xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1376 | /* STM32F042x6 || STM32F048xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1377 | /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1378 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1379 | /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 1380 | |
AnnaBridge | 171:3a7713b1edbc | 1381 | #if defined(STM32F030x8) \ |
AnnaBridge | 171:3a7713b1edbc | 1382 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1383 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
AnnaBridge | 171:3a7713b1edbc | 1384 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 1385 | |
AnnaBridge | 171:3a7713b1edbc | 1386 | #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) |
AnnaBridge | 171:3a7713b1edbc | 1387 | #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1388 | |
AnnaBridge | 171:3a7713b1edbc | 1389 | #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) |
AnnaBridge | 171:3a7713b1edbc | 1390 | #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) |
AnnaBridge | 171:3a7713b1edbc | 1391 | |
AnnaBridge | 171:3a7713b1edbc | 1392 | #endif /* STM32F030x8 || */ |
AnnaBridge | 171:3a7713b1edbc | 1393 | /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1394 | /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
AnnaBridge | 171:3a7713b1edbc | 1395 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 1396 | |
AnnaBridge | 171:3a7713b1edbc | 1397 | #if defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1398 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1399 | || defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 1400 | |
AnnaBridge | 171:3a7713b1edbc | 1401 | #define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) |
AnnaBridge | 171:3a7713b1edbc | 1402 | |
AnnaBridge | 171:3a7713b1edbc | 1403 | #define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) |
AnnaBridge | 171:3a7713b1edbc | 1404 | |
AnnaBridge | 171:3a7713b1edbc | 1405 | #endif /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1406 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1407 | /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 1408 | |
AnnaBridge | 171:3a7713b1edbc | 1409 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1410 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1411 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1412 | || defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 1413 | |
AnnaBridge | 171:3a7713b1edbc | 1414 | #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) |
AnnaBridge | 171:3a7713b1edbc | 1415 | |
AnnaBridge | 171:3a7713b1edbc | 1416 | #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) |
AnnaBridge | 171:3a7713b1edbc | 1417 | |
AnnaBridge | 171:3a7713b1edbc | 1418 | #endif /* STM32F042x6 || STM32F048xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1419 | /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1420 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1421 | /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 1422 | |
AnnaBridge | 171:3a7713b1edbc | 1423 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
AnnaBridge | 171:3a7713b1edbc | 1424 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 1425 | |
AnnaBridge | 171:3a7713b1edbc | 1426 | #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) |
AnnaBridge | 171:3a7713b1edbc | 1427 | #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) |
AnnaBridge | 171:3a7713b1edbc | 1428 | #define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST)) |
AnnaBridge | 171:3a7713b1edbc | 1429 | |
AnnaBridge | 171:3a7713b1edbc | 1430 | #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) |
AnnaBridge | 171:3a7713b1edbc | 1431 | #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) |
AnnaBridge | 171:3a7713b1edbc | 1432 | #define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST)) |
AnnaBridge | 171:3a7713b1edbc | 1433 | |
AnnaBridge | 171:3a7713b1edbc | 1434 | #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
AnnaBridge | 171:3a7713b1edbc | 1435 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 1436 | |
AnnaBridge | 171:3a7713b1edbc | 1437 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ |
AnnaBridge | 171:3a7713b1edbc | 1438 | || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) |
AnnaBridge | 171:3a7713b1edbc | 1439 | |
AnnaBridge | 171:3a7713b1edbc | 1440 | #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) |
AnnaBridge | 171:3a7713b1edbc | 1441 | |
AnnaBridge | 171:3a7713b1edbc | 1442 | #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) |
AnnaBridge | 171:3a7713b1edbc | 1443 | |
AnnaBridge | 171:3a7713b1edbc | 1444 | #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ |
AnnaBridge | 171:3a7713b1edbc | 1445 | /* STM32F072xB || STM32F078xx || STM32F070xB */ |
AnnaBridge | 171:3a7713b1edbc | 1446 | |
AnnaBridge | 171:3a7713b1edbc | 1447 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ |
AnnaBridge | 171:3a7713b1edbc | 1448 | || defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 1449 | |
AnnaBridge | 171:3a7713b1edbc | 1450 | #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST)) |
AnnaBridge | 171:3a7713b1edbc | 1451 | |
AnnaBridge | 171:3a7713b1edbc | 1452 | #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST)) |
AnnaBridge | 171:3a7713b1edbc | 1453 | |
AnnaBridge | 171:3a7713b1edbc | 1454 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ |
AnnaBridge | 171:3a7713b1edbc | 1455 | /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 1456 | |
AnnaBridge | 171:3a7713b1edbc | 1457 | #if defined(CRS) |
AnnaBridge | 171:3a7713b1edbc | 1458 | |
AnnaBridge | 171:3a7713b1edbc | 1459 | #define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST)) |
AnnaBridge | 171:3a7713b1edbc | 1460 | |
AnnaBridge | 171:3a7713b1edbc | 1461 | #define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST)) |
AnnaBridge | 171:3a7713b1edbc | 1462 | |
AnnaBridge | 171:3a7713b1edbc | 1463 | #endif /* CRS */ |
AnnaBridge | 171:3a7713b1edbc | 1464 | |
AnnaBridge | 171:3a7713b1edbc | 1465 | #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 1466 | |
AnnaBridge | 171:3a7713b1edbc | 1467 | #define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST)) |
AnnaBridge | 171:3a7713b1edbc | 1468 | |
AnnaBridge | 171:3a7713b1edbc | 1469 | #define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST)) |
AnnaBridge | 171:3a7713b1edbc | 1470 | |
AnnaBridge | 171:3a7713b1edbc | 1471 | #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 1472 | |
AnnaBridge | 171:3a7713b1edbc | 1473 | |
AnnaBridge | 171:3a7713b1edbc | 1474 | /** @brief Force or release APB2 peripheral reset. |
AnnaBridge | 171:3a7713b1edbc | 1475 | */ |
AnnaBridge | 171:3a7713b1edbc | 1476 | #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ |
AnnaBridge | 171:3a7713b1edbc | 1477 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1478 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
AnnaBridge | 171:3a7713b1edbc | 1479 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 1480 | |
AnnaBridge | 171:3a7713b1edbc | 1481 | #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) |
AnnaBridge | 171:3a7713b1edbc | 1482 | |
AnnaBridge | 171:3a7713b1edbc | 1483 | #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) |
AnnaBridge | 171:3a7713b1edbc | 1484 | |
AnnaBridge | 171:3a7713b1edbc | 1485 | #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ |
AnnaBridge | 171:3a7713b1edbc | 1486 | /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1487 | /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
AnnaBridge | 171:3a7713b1edbc | 1488 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 1489 | |
AnnaBridge | 171:3a7713b1edbc | 1490 | #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 1491 | |
AnnaBridge | 171:3a7713b1edbc | 1492 | #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) |
AnnaBridge | 171:3a7713b1edbc | 1493 | |
AnnaBridge | 171:3a7713b1edbc | 1494 | #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) |
AnnaBridge | 171:3a7713b1edbc | 1495 | |
AnnaBridge | 171:3a7713b1edbc | 1496 | #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 1497 | |
AnnaBridge | 171:3a7713b1edbc | 1498 | #if defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 1499 | |
AnnaBridge | 171:3a7713b1edbc | 1500 | #define __HAL_RCC_USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST)) |
AnnaBridge | 171:3a7713b1edbc | 1501 | #define __HAL_RCC_USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST)) |
AnnaBridge | 171:3a7713b1edbc | 1502 | |
AnnaBridge | 171:3a7713b1edbc | 1503 | #define __HAL_RCC_USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST)) |
AnnaBridge | 171:3a7713b1edbc | 1504 | #define __HAL_RCC_USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST)) |
AnnaBridge | 171:3a7713b1edbc | 1505 | |
AnnaBridge | 171:3a7713b1edbc | 1506 | #endif /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 1507 | |
AnnaBridge | 171:3a7713b1edbc | 1508 | /** |
AnnaBridge | 171:3a7713b1edbc | 1509 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1510 | */ |
AnnaBridge | 171:3a7713b1edbc | 1511 | |
AnnaBridge | 171:3a7713b1edbc | 1512 | /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status |
AnnaBridge | 171:3a7713b1edbc | 1513 | * @brief Get the enable or disable status of peripheral clock. |
AnnaBridge | 171:3a7713b1edbc | 1514 | * @note After reset, the peripheral clock (used for registers read/write access) |
AnnaBridge | 171:3a7713b1edbc | 1515 | * is disabled and the application software has to enable this clock before |
AnnaBridge | 171:3a7713b1edbc | 1516 | * using it. |
AnnaBridge | 171:3a7713b1edbc | 1517 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1518 | */ |
AnnaBridge | 171:3a7713b1edbc | 1519 | /** @brief AHB Peripheral Clock Enable Disable Status |
AnnaBridge | 171:3a7713b1edbc | 1520 | */ |
AnnaBridge | 171:3a7713b1edbc | 1521 | #if defined(GPIOD) |
AnnaBridge | 171:3a7713b1edbc | 1522 | |
AnnaBridge | 171:3a7713b1edbc | 1523 | #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1524 | #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1525 | |
AnnaBridge | 171:3a7713b1edbc | 1526 | #endif /* GPIOD */ |
AnnaBridge | 171:3a7713b1edbc | 1527 | |
AnnaBridge | 171:3a7713b1edbc | 1528 | #if defined(GPIOE) |
AnnaBridge | 171:3a7713b1edbc | 1529 | |
AnnaBridge | 171:3a7713b1edbc | 1530 | #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1531 | #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1532 | |
AnnaBridge | 171:3a7713b1edbc | 1533 | #endif /* GPIOE */ |
AnnaBridge | 171:3a7713b1edbc | 1534 | |
AnnaBridge | 171:3a7713b1edbc | 1535 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1536 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1537 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1538 | || defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 1539 | |
AnnaBridge | 171:3a7713b1edbc | 1540 | #define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1541 | #define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1542 | |
AnnaBridge | 171:3a7713b1edbc | 1543 | #endif /* STM32F042x6 || STM32F048xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1544 | /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1545 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1546 | /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 1547 | |
AnnaBridge | 171:3a7713b1edbc | 1548 | #if defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 1549 | |
AnnaBridge | 171:3a7713b1edbc | 1550 | #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1551 | #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1552 | |
AnnaBridge | 171:3a7713b1edbc | 1553 | #endif /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 1554 | |
AnnaBridge | 171:3a7713b1edbc | 1555 | /** @brief APB1 Peripheral Clock Enable Disable Status |
AnnaBridge | 171:3a7713b1edbc | 1556 | */ |
AnnaBridge | 171:3a7713b1edbc | 1557 | #if defined(STM32F030x8)\ |
AnnaBridge | 171:3a7713b1edbc | 1558 | || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ |
AnnaBridge | 171:3a7713b1edbc | 1559 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1560 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
AnnaBridge | 171:3a7713b1edbc | 1561 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 1562 | |
AnnaBridge | 171:3a7713b1edbc | 1563 | #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1564 | #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1565 | |
AnnaBridge | 171:3a7713b1edbc | 1566 | #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1567 | /* STM32F051x8 || STM32F058xx || STM32F070x6 || */ |
AnnaBridge | 171:3a7713b1edbc | 1568 | /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
AnnaBridge | 171:3a7713b1edbc | 1569 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 1570 | |
AnnaBridge | 171:3a7713b1edbc | 1571 | #if defined(STM32F030x8)\ |
AnnaBridge | 171:3a7713b1edbc | 1572 | || defined(STM32F042x6) || defined(STM32F048xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1573 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1574 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
AnnaBridge | 171:3a7713b1edbc | 1575 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 1576 | |
AnnaBridge | 171:3a7713b1edbc | 1577 | #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1578 | #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1579 | |
AnnaBridge | 171:3a7713b1edbc | 1580 | #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1581 | /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1582 | /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
AnnaBridge | 171:3a7713b1edbc | 1583 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 1584 | |
AnnaBridge | 171:3a7713b1edbc | 1585 | #if defined(STM32F031x6) || defined(STM32F038xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1586 | || defined(STM32F042x6) || defined(STM32F048xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1587 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1588 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1589 | || defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 1590 | |
AnnaBridge | 171:3a7713b1edbc | 1591 | #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1592 | #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1593 | |
AnnaBridge | 171:3a7713b1edbc | 1594 | #endif /* STM32F031x6 || STM32F038xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1595 | /* STM32F042x6 || STM32F048xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1596 | /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1597 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1598 | /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 1599 | |
AnnaBridge | 171:3a7713b1edbc | 1600 | #if defined(STM32F030x8) \ |
AnnaBridge | 171:3a7713b1edbc | 1601 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1602 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
AnnaBridge | 171:3a7713b1edbc | 1603 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 1604 | |
AnnaBridge | 171:3a7713b1edbc | 1605 | #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1606 | #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1607 | #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1608 | #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1609 | |
AnnaBridge | 171:3a7713b1edbc | 1610 | #endif /* STM32F030x8 || */ |
AnnaBridge | 171:3a7713b1edbc | 1611 | /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1612 | /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
AnnaBridge | 171:3a7713b1edbc | 1613 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 1614 | |
AnnaBridge | 171:3a7713b1edbc | 1615 | #if defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1616 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1617 | || defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 1618 | |
AnnaBridge | 171:3a7713b1edbc | 1619 | #define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1620 | #define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1621 | |
AnnaBridge | 171:3a7713b1edbc | 1622 | #endif /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1623 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1624 | /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 1625 | |
AnnaBridge | 171:3a7713b1edbc | 1626 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1627 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1628 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1629 | || defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 1630 | |
AnnaBridge | 171:3a7713b1edbc | 1631 | #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1632 | #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1633 | |
AnnaBridge | 171:3a7713b1edbc | 1634 | #endif /* STM32F042x6 || STM32F048xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1635 | /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1636 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1637 | /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 1638 | |
AnnaBridge | 171:3a7713b1edbc | 1639 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
AnnaBridge | 171:3a7713b1edbc | 1640 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 1641 | |
AnnaBridge | 171:3a7713b1edbc | 1642 | #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1643 | #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1644 | #define __HAL_RCC_USART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1645 | #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1646 | #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1647 | #define __HAL_RCC_USART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1648 | |
AnnaBridge | 171:3a7713b1edbc | 1649 | #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
AnnaBridge | 171:3a7713b1edbc | 1650 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 1651 | |
AnnaBridge | 171:3a7713b1edbc | 1652 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ |
AnnaBridge | 171:3a7713b1edbc | 1653 | || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) |
AnnaBridge | 171:3a7713b1edbc | 1654 | |
AnnaBridge | 171:3a7713b1edbc | 1655 | #define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1656 | #define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1657 | |
AnnaBridge | 171:3a7713b1edbc | 1658 | #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ |
AnnaBridge | 171:3a7713b1edbc | 1659 | /* STM32F072xB || STM32F078xx || STM32F070xB */ |
AnnaBridge | 171:3a7713b1edbc | 1660 | |
AnnaBridge | 171:3a7713b1edbc | 1661 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ |
AnnaBridge | 171:3a7713b1edbc | 1662 | || defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 1663 | |
AnnaBridge | 171:3a7713b1edbc | 1664 | #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1665 | #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1666 | |
AnnaBridge | 171:3a7713b1edbc | 1667 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ |
AnnaBridge | 171:3a7713b1edbc | 1668 | /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 1669 | |
AnnaBridge | 171:3a7713b1edbc | 1670 | #if defined(CRS) |
AnnaBridge | 171:3a7713b1edbc | 1671 | |
AnnaBridge | 171:3a7713b1edbc | 1672 | #define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1673 | #define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1674 | |
AnnaBridge | 171:3a7713b1edbc | 1675 | #endif /* CRS */ |
AnnaBridge | 171:3a7713b1edbc | 1676 | |
AnnaBridge | 171:3a7713b1edbc | 1677 | #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 1678 | |
AnnaBridge | 171:3a7713b1edbc | 1679 | #define __HAL_RCC_USART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1680 | #define __HAL_RCC_USART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1681 | |
AnnaBridge | 171:3a7713b1edbc | 1682 | #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 1683 | |
AnnaBridge | 171:3a7713b1edbc | 1684 | /** @brief APB1 Peripheral Clock Enable Disable Status |
AnnaBridge | 171:3a7713b1edbc | 1685 | */ |
AnnaBridge | 171:3a7713b1edbc | 1686 | #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ |
AnnaBridge | 171:3a7713b1edbc | 1687 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1688 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
AnnaBridge | 171:3a7713b1edbc | 1689 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 1690 | |
AnnaBridge | 171:3a7713b1edbc | 1691 | #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1692 | #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1693 | |
AnnaBridge | 171:3a7713b1edbc | 1694 | #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ |
AnnaBridge | 171:3a7713b1edbc | 1695 | /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1696 | /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
AnnaBridge | 171:3a7713b1edbc | 1697 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 1698 | |
AnnaBridge | 171:3a7713b1edbc | 1699 | #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
AnnaBridge | 171:3a7713b1edbc | 1700 | |
AnnaBridge | 171:3a7713b1edbc | 1701 | #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1702 | #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1703 | |
AnnaBridge | 171:3a7713b1edbc | 1704 | #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ |
AnnaBridge | 171:3a7713b1edbc | 1705 | |
AnnaBridge | 171:3a7713b1edbc | 1706 | #if defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 1707 | |
AnnaBridge | 171:3a7713b1edbc | 1708 | #define __HAL_RCC_USART7_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1709 | #define __HAL_RCC_USART8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) != RESET) |
AnnaBridge | 171:3a7713b1edbc | 1710 | #define __HAL_RCC_USART7_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1711 | #define __HAL_RCC_USART8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) == RESET) |
AnnaBridge | 171:3a7713b1edbc | 1712 | |
AnnaBridge | 171:3a7713b1edbc | 1713 | #endif /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 1714 | /** |
AnnaBridge | 171:3a7713b1edbc | 1715 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1716 | */ |
AnnaBridge | 171:3a7713b1edbc | 1717 | |
AnnaBridge | 171:3a7713b1edbc | 1718 | |
AnnaBridge | 171:3a7713b1edbc | 1719 | /** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable |
AnnaBridge | 171:3a7713b1edbc | 1720 | * @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48). |
AnnaBridge | 171:3a7713b1edbc | 1721 | * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. |
AnnaBridge | 171:3a7713b1edbc | 1722 | * @note HSI48 can not be stopped if it is used as system clock source. In this case, |
AnnaBridge | 171:3a7713b1edbc | 1723 | * you have to select another source of the system clock then stop the HSI14. |
AnnaBridge | 171:3a7713b1edbc | 1724 | * @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software |
AnnaBridge | 171:3a7713b1edbc | 1725 | * should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be |
AnnaBridge | 171:3a7713b1edbc | 1726 | * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used. |
AnnaBridge | 171:3a7713b1edbc | 1727 | * @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator |
AnnaBridge | 171:3a7713b1edbc | 1728 | * clock cycles. |
AnnaBridge | 171:3a7713b1edbc | 1729 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1730 | */ |
AnnaBridge | 171:3a7713b1edbc | 1731 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 1732 | |
AnnaBridge | 171:3a7713b1edbc | 1733 | #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON) |
AnnaBridge | 171:3a7713b1edbc | 1734 | #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON) |
AnnaBridge | 171:3a7713b1edbc | 1735 | |
AnnaBridge | 171:3a7713b1edbc | 1736 | /** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state. |
AnnaBridge | 171:3a7713b1edbc | 1737 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1738 | * @arg @ref RCC_HSI48_ON HSI48 enabled |
AnnaBridge | 171:3a7713b1edbc | 1739 | * @arg @ref RCC_HSI48_OFF HSI48 disabled |
AnnaBridge | 171:3a7713b1edbc | 1740 | */ |
AnnaBridge | 171:3a7713b1edbc | 1741 | #define __HAL_RCC_GET_HSI48_STATE() \ |
AnnaBridge | 171:3a7713b1edbc | 1742 | (((uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF) |
AnnaBridge | 171:3a7713b1edbc | 1743 | |
AnnaBridge | 171:3a7713b1edbc | 1744 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 1745 | |
AnnaBridge | 171:3a7713b1edbc | 1746 | /** |
AnnaBridge | 171:3a7713b1edbc | 1747 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1748 | */ |
AnnaBridge | 171:3a7713b1edbc | 1749 | |
AnnaBridge | 171:3a7713b1edbc | 1750 | /** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config |
AnnaBridge | 171:3a7713b1edbc | 1751 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1752 | */ |
AnnaBridge | 171:3a7713b1edbc | 1753 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1754 | || defined(STM32F072xB) || defined(STM32F078xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1755 | || defined(STM32F070x6) || defined(STM32F070xB) |
AnnaBridge | 171:3a7713b1edbc | 1756 | |
AnnaBridge | 171:3a7713b1edbc | 1757 | /** @brief Macro to configure the USB clock (USBCLK). |
AnnaBridge | 171:3a7713b1edbc | 1758 | * @param __USBCLKSOURCE__ specifies the USB clock source. |
AnnaBridge | 171:3a7713b1edbc | 1759 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1760 | @if STM32F070xB |
AnnaBridge | 171:3a7713b1edbc | 1761 | @elseif STM32F070x6 |
AnnaBridge | 171:3a7713b1edbc | 1762 | @else |
AnnaBridge | 171:3a7713b1edbc | 1763 | * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock |
AnnaBridge | 171:3a7713b1edbc | 1764 | @endif |
AnnaBridge | 171:3a7713b1edbc | 1765 | * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock |
AnnaBridge | 171:3a7713b1edbc | 1766 | */ |
AnnaBridge | 171:3a7713b1edbc | 1767 | #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 1768 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 1769 | |
AnnaBridge | 171:3a7713b1edbc | 1770 | /** @brief Macro to get the USB clock source. |
AnnaBridge | 171:3a7713b1edbc | 1771 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1772 | @if STM32F070xB |
AnnaBridge | 171:3a7713b1edbc | 1773 | @elseif STM32F070x6 |
AnnaBridge | 171:3a7713b1edbc | 1774 | @else |
AnnaBridge | 171:3a7713b1edbc | 1775 | * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock |
AnnaBridge | 171:3a7713b1edbc | 1776 | @endif |
AnnaBridge | 171:3a7713b1edbc | 1777 | * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock |
AnnaBridge | 171:3a7713b1edbc | 1778 | */ |
AnnaBridge | 171:3a7713b1edbc | 1779 | #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW))) |
AnnaBridge | 171:3a7713b1edbc | 1780 | |
AnnaBridge | 171:3a7713b1edbc | 1781 | #endif /* STM32F042x6 || STM32F048xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1782 | /* STM32F072xB || STM32F078xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1783 | /* STM32F070x6 || STM32F070xB */ |
AnnaBridge | 171:3a7713b1edbc | 1784 | |
AnnaBridge | 171:3a7713b1edbc | 1785 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1786 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1787 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1788 | || defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 1789 | |
AnnaBridge | 171:3a7713b1edbc | 1790 | /** @brief Macro to configure the CEC clock. |
AnnaBridge | 171:3a7713b1edbc | 1791 | * @param __CECCLKSOURCE__ specifies the CEC clock source. |
AnnaBridge | 171:3a7713b1edbc | 1792 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1793 | * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock |
AnnaBridge | 171:3a7713b1edbc | 1794 | * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock |
AnnaBridge | 171:3a7713b1edbc | 1795 | */ |
AnnaBridge | 171:3a7713b1edbc | 1796 | #define __HAL_RCC_CEC_CONFIG(__CECCLKSOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 1797 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 1798 | |
AnnaBridge | 171:3a7713b1edbc | 1799 | /** @brief Macro to get the HDMI CEC clock source. |
AnnaBridge | 171:3a7713b1edbc | 1800 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1801 | * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock |
AnnaBridge | 171:3a7713b1edbc | 1802 | * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock |
AnnaBridge | 171:3a7713b1edbc | 1803 | */ |
AnnaBridge | 171:3a7713b1edbc | 1804 | #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW))) |
AnnaBridge | 171:3a7713b1edbc | 1805 | |
AnnaBridge | 171:3a7713b1edbc | 1806 | #endif /* STM32F042x6 || STM32F048xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1807 | /* STM32F051x8 || STM32F058xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1808 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
AnnaBridge | 171:3a7713b1edbc | 1809 | /* STM32F091xC || defined(STM32F098xx) */ |
AnnaBridge | 171:3a7713b1edbc | 1810 | |
AnnaBridge | 171:3a7713b1edbc | 1811 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
AnnaBridge | 171:3a7713b1edbc | 1812 | || defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 1813 | /** @brief Macro to configure the USART2 clock (USART2CLK). |
AnnaBridge | 171:3a7713b1edbc | 1814 | * @param __USART2CLKSOURCE__ specifies the USART2 clock source. |
AnnaBridge | 171:3a7713b1edbc | 1815 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1816 | * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock |
AnnaBridge | 171:3a7713b1edbc | 1817 | * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock |
AnnaBridge | 171:3a7713b1edbc | 1818 | * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock |
AnnaBridge | 171:3a7713b1edbc | 1819 | * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock |
AnnaBridge | 171:3a7713b1edbc | 1820 | */ |
AnnaBridge | 171:3a7713b1edbc | 1821 | #define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 1822 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 1823 | |
AnnaBridge | 171:3a7713b1edbc | 1824 | /** @brief Macro to get the USART2 clock source. |
AnnaBridge | 171:3a7713b1edbc | 1825 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1826 | * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock |
AnnaBridge | 171:3a7713b1edbc | 1827 | * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock |
AnnaBridge | 171:3a7713b1edbc | 1828 | * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock |
AnnaBridge | 171:3a7713b1edbc | 1829 | * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock |
AnnaBridge | 171:3a7713b1edbc | 1830 | */ |
AnnaBridge | 171:3a7713b1edbc | 1831 | #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW))) |
AnnaBridge | 171:3a7713b1edbc | 1832 | #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx*/ |
AnnaBridge | 171:3a7713b1edbc | 1833 | |
AnnaBridge | 171:3a7713b1edbc | 1834 | #if defined(STM32F091xC) || defined(STM32F098xx) |
AnnaBridge | 171:3a7713b1edbc | 1835 | /** @brief Macro to configure the USART3 clock (USART3CLK). |
AnnaBridge | 171:3a7713b1edbc | 1836 | * @param __USART3CLKSOURCE__ specifies the USART3 clock source. |
AnnaBridge | 171:3a7713b1edbc | 1837 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1838 | * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock |
AnnaBridge | 171:3a7713b1edbc | 1839 | * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock |
AnnaBridge | 171:3a7713b1edbc | 1840 | * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock |
AnnaBridge | 171:3a7713b1edbc | 1841 | * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock |
AnnaBridge | 171:3a7713b1edbc | 1842 | */ |
AnnaBridge | 171:3a7713b1edbc | 1843 | #define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 1844 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__)) |
AnnaBridge | 171:3a7713b1edbc | 1845 | |
AnnaBridge | 171:3a7713b1edbc | 1846 | /** @brief Macro to get the USART3 clock source. |
AnnaBridge | 171:3a7713b1edbc | 1847 | * @retval The clock source can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1848 | * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock |
AnnaBridge | 171:3a7713b1edbc | 1849 | * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock |
AnnaBridge | 171:3a7713b1edbc | 1850 | * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock |
AnnaBridge | 171:3a7713b1edbc | 1851 | * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock |
AnnaBridge | 171:3a7713b1edbc | 1852 | */ |
AnnaBridge | 171:3a7713b1edbc | 1853 | #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW))) |
AnnaBridge | 171:3a7713b1edbc | 1854 | |
AnnaBridge | 171:3a7713b1edbc | 1855 | #endif /* STM32F091xC || STM32F098xx */ |
AnnaBridge | 171:3a7713b1edbc | 1856 | /** |
AnnaBridge | 171:3a7713b1edbc | 1857 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1858 | */ |
AnnaBridge | 171:3a7713b1edbc | 1859 | |
AnnaBridge | 171:3a7713b1edbc | 1860 | /** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration |
AnnaBridge | 171:3a7713b1edbc | 1861 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1862 | */ |
AnnaBridge | 171:3a7713b1edbc | 1863 | |
AnnaBridge | 171:3a7713b1edbc | 1864 | /** |
AnnaBridge | 171:3a7713b1edbc | 1865 | * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. |
AnnaBridge | 171:3a7713b1edbc | 1866 | * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability. |
AnnaBridge | 171:3a7713b1edbc | 1867 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1868 | * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. |
AnnaBridge | 171:3a7713b1edbc | 1869 | * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. |
AnnaBridge | 171:3a7713b1edbc | 1870 | * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. |
AnnaBridge | 171:3a7713b1edbc | 1871 | * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. |
AnnaBridge | 171:3a7713b1edbc | 1872 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1873 | */ |
AnnaBridge | 171:3a7713b1edbc | 1874 | #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\ |
AnnaBridge | 171:3a7713b1edbc | 1875 | RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) |
AnnaBridge | 171:3a7713b1edbc | 1876 | |
AnnaBridge | 171:3a7713b1edbc | 1877 | /** |
AnnaBridge | 171:3a7713b1edbc | 1878 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1879 | */ |
AnnaBridge | 171:3a7713b1edbc | 1880 | |
AnnaBridge | 171:3a7713b1edbc | 1881 | #if defined(CRS) |
AnnaBridge | 171:3a7713b1edbc | 1882 | |
AnnaBridge | 171:3a7713b1edbc | 1883 | /** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag |
AnnaBridge | 171:3a7713b1edbc | 1884 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1885 | */ |
AnnaBridge | 171:3a7713b1edbc | 1886 | /* Interrupt & Flag management */ |
AnnaBridge | 171:3a7713b1edbc | 1887 | |
AnnaBridge | 171:3a7713b1edbc | 1888 | /** |
AnnaBridge | 171:3a7713b1edbc | 1889 | * @brief Enable the specified CRS interrupts. |
AnnaBridge | 171:3a7713b1edbc | 1890 | * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. |
AnnaBridge | 171:3a7713b1edbc | 1891 | * This parameter can be any combination of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1892 | * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt |
AnnaBridge | 171:3a7713b1edbc | 1893 | * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt |
AnnaBridge | 171:3a7713b1edbc | 1894 | * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt |
AnnaBridge | 171:3a7713b1edbc | 1895 | * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt |
AnnaBridge | 171:3a7713b1edbc | 1896 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1897 | */ |
AnnaBridge | 171:3a7713b1edbc | 1898 | #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) |
AnnaBridge | 171:3a7713b1edbc | 1899 | |
AnnaBridge | 171:3a7713b1edbc | 1900 | /** |
AnnaBridge | 171:3a7713b1edbc | 1901 | * @brief Disable the specified CRS interrupts. |
AnnaBridge | 171:3a7713b1edbc | 1902 | * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. |
AnnaBridge | 171:3a7713b1edbc | 1903 | * This parameter can be any combination of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1904 | * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt |
AnnaBridge | 171:3a7713b1edbc | 1905 | * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt |
AnnaBridge | 171:3a7713b1edbc | 1906 | * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt |
AnnaBridge | 171:3a7713b1edbc | 1907 | * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt |
AnnaBridge | 171:3a7713b1edbc | 1908 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1909 | */ |
AnnaBridge | 171:3a7713b1edbc | 1910 | #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) |
AnnaBridge | 171:3a7713b1edbc | 1911 | |
AnnaBridge | 171:3a7713b1edbc | 1912 | /** @brief Check whether the CRS interrupt has occurred or not. |
AnnaBridge | 171:3a7713b1edbc | 1913 | * @param __INTERRUPT__ specifies the CRS interrupt source to check. |
AnnaBridge | 171:3a7713b1edbc | 1914 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1915 | * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt |
AnnaBridge | 171:3a7713b1edbc | 1916 | * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt |
AnnaBridge | 171:3a7713b1edbc | 1917 | * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt |
AnnaBridge | 171:3a7713b1edbc | 1918 | * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt |
AnnaBridge | 171:3a7713b1edbc | 1919 | * @retval The new state of __INTERRUPT__ (SET or RESET). |
AnnaBridge | 171:3a7713b1edbc | 1920 | */ |
AnnaBridge | 171:3a7713b1edbc | 1921 | #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET) |
AnnaBridge | 171:3a7713b1edbc | 1922 | |
AnnaBridge | 171:3a7713b1edbc | 1923 | /** @brief Clear the CRS interrupt pending bits |
AnnaBridge | 171:3a7713b1edbc | 1924 | * @param __INTERRUPT__ specifies the interrupt pending bit to clear. |
AnnaBridge | 171:3a7713b1edbc | 1925 | * This parameter can be any combination of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1926 | * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt |
AnnaBridge | 171:3a7713b1edbc | 1927 | * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt |
AnnaBridge | 171:3a7713b1edbc | 1928 | * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt |
AnnaBridge | 171:3a7713b1edbc | 1929 | * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt |
AnnaBridge | 171:3a7713b1edbc | 1930 | * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt |
AnnaBridge | 171:3a7713b1edbc | 1931 | * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt |
AnnaBridge | 171:3a7713b1edbc | 1932 | * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt |
AnnaBridge | 171:3a7713b1edbc | 1933 | */ |
AnnaBridge | 171:3a7713b1edbc | 1934 | #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ |
AnnaBridge | 171:3a7713b1edbc | 1935 | if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \ |
AnnaBridge | 171:3a7713b1edbc | 1936 | { \ |
AnnaBridge | 171:3a7713b1edbc | 1937 | WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ |
AnnaBridge | 171:3a7713b1edbc | 1938 | } \ |
AnnaBridge | 171:3a7713b1edbc | 1939 | else \ |
AnnaBridge | 171:3a7713b1edbc | 1940 | { \ |
AnnaBridge | 171:3a7713b1edbc | 1941 | WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ |
AnnaBridge | 171:3a7713b1edbc | 1942 | } \ |
AnnaBridge | 171:3a7713b1edbc | 1943 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 1944 | |
AnnaBridge | 171:3a7713b1edbc | 1945 | /** |
AnnaBridge | 171:3a7713b1edbc | 1946 | * @brief Check whether the specified CRS flag is set or not. |
AnnaBridge | 171:3a7713b1edbc | 1947 | * @param __FLAG__ specifies the flag to check. |
AnnaBridge | 171:3a7713b1edbc | 1948 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1949 | * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK |
AnnaBridge | 171:3a7713b1edbc | 1950 | * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning |
AnnaBridge | 171:3a7713b1edbc | 1951 | * @arg @ref RCC_CRS_FLAG_ERR Error |
AnnaBridge | 171:3a7713b1edbc | 1952 | * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC |
AnnaBridge | 171:3a7713b1edbc | 1953 | * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow |
AnnaBridge | 171:3a7713b1edbc | 1954 | * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error |
AnnaBridge | 171:3a7713b1edbc | 1955 | * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed |
AnnaBridge | 171:3a7713b1edbc | 1956 | * @retval The new state of _FLAG_ (TRUE or FALSE). |
AnnaBridge | 171:3a7713b1edbc | 1957 | */ |
AnnaBridge | 171:3a7713b1edbc | 1958 | #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) |
AnnaBridge | 171:3a7713b1edbc | 1959 | |
AnnaBridge | 171:3a7713b1edbc | 1960 | /** |
AnnaBridge | 171:3a7713b1edbc | 1961 | * @brief Clear the CRS specified FLAG. |
AnnaBridge | 171:3a7713b1edbc | 1962 | * @param __FLAG__ specifies the flag to clear. |
AnnaBridge | 171:3a7713b1edbc | 1963 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1964 | * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK |
AnnaBridge | 171:3a7713b1edbc | 1965 | * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning |
AnnaBridge | 171:3a7713b1edbc | 1966 | * @arg @ref RCC_CRS_FLAG_ERR Error |
AnnaBridge | 171:3a7713b1edbc | 1967 | * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC |
AnnaBridge | 171:3a7713b1edbc | 1968 | * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow |
AnnaBridge | 171:3a7713b1edbc | 1969 | * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error |
AnnaBridge | 171:3a7713b1edbc | 1970 | * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed |
AnnaBridge | 171:3a7713b1edbc | 1971 | * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR |
AnnaBridge | 171:3a7713b1edbc | 1972 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1973 | */ |
AnnaBridge | 171:3a7713b1edbc | 1974 | #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ |
AnnaBridge | 171:3a7713b1edbc | 1975 | if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \ |
AnnaBridge | 171:3a7713b1edbc | 1976 | { \ |
AnnaBridge | 171:3a7713b1edbc | 1977 | WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ |
AnnaBridge | 171:3a7713b1edbc | 1978 | } \ |
AnnaBridge | 171:3a7713b1edbc | 1979 | else \ |
AnnaBridge | 171:3a7713b1edbc | 1980 | { \ |
AnnaBridge | 171:3a7713b1edbc | 1981 | WRITE_REG(CRS->ICR, (__FLAG__)); \ |
AnnaBridge | 171:3a7713b1edbc | 1982 | } \ |
AnnaBridge | 171:3a7713b1edbc | 1983 | } while(0U) |
AnnaBridge | 171:3a7713b1edbc | 1984 | |
AnnaBridge | 171:3a7713b1edbc | 1985 | /** |
AnnaBridge | 171:3a7713b1edbc | 1986 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1987 | */ |
AnnaBridge | 171:3a7713b1edbc | 1988 | |
AnnaBridge | 171:3a7713b1edbc | 1989 | /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features |
AnnaBridge | 171:3a7713b1edbc | 1990 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1991 | */ |
AnnaBridge | 171:3a7713b1edbc | 1992 | /** |
AnnaBridge | 171:3a7713b1edbc | 1993 | * @brief Enable the oscillator clock for frequency error counter. |
AnnaBridge | 171:3a7713b1edbc | 1994 | * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. |
AnnaBridge | 171:3a7713b1edbc | 1995 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1996 | */ |
AnnaBridge | 171:3a7713b1edbc | 1997 | #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) |
AnnaBridge | 171:3a7713b1edbc | 1998 | |
AnnaBridge | 171:3a7713b1edbc | 1999 | /** |
AnnaBridge | 171:3a7713b1edbc | 2000 | * @brief Disable the oscillator clock for frequency error counter. |
AnnaBridge | 171:3a7713b1edbc | 2001 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2002 | */ |
AnnaBridge | 171:3a7713b1edbc | 2003 | #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) |
AnnaBridge | 171:3a7713b1edbc | 2004 | |
AnnaBridge | 171:3a7713b1edbc | 2005 | /** |
AnnaBridge | 171:3a7713b1edbc | 2006 | * @brief Enable the automatic hardware adjustement of TRIM bits. |
AnnaBridge | 171:3a7713b1edbc | 2007 | * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. |
AnnaBridge | 171:3a7713b1edbc | 2008 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2009 | */ |
AnnaBridge | 171:3a7713b1edbc | 2010 | #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) |
AnnaBridge | 171:3a7713b1edbc | 2011 | |
AnnaBridge | 171:3a7713b1edbc | 2012 | /** |
AnnaBridge | 171:3a7713b1edbc | 2013 | * @brief Disable the automatic hardware adjustement of TRIM bits. |
AnnaBridge | 171:3a7713b1edbc | 2014 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2015 | */ |
AnnaBridge | 171:3a7713b1edbc | 2016 | #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) |
AnnaBridge | 171:3a7713b1edbc | 2017 | |
AnnaBridge | 171:3a7713b1edbc | 2018 | /** |
AnnaBridge | 171:3a7713b1edbc | 2019 | * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies |
AnnaBridge | 171:3a7713b1edbc | 2020 | * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency |
AnnaBridge | 171:3a7713b1edbc | 2021 | * of the synchronization source after prescaling. It is then decreased by one in order to |
AnnaBridge | 171:3a7713b1edbc | 2022 | * reach the expected synchronization on the zero value. The formula is the following: |
AnnaBridge | 171:3a7713b1edbc | 2023 | * RELOAD = (fTARGET / fSYNC) -1 |
AnnaBridge | 171:3a7713b1edbc | 2024 | * @param __FTARGET__ Target frequency (value in Hz) |
AnnaBridge | 171:3a7713b1edbc | 2025 | * @param __FSYNC__ Synchronization signal frequency (value in Hz) |
AnnaBridge | 171:3a7713b1edbc | 2026 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2027 | */ |
AnnaBridge | 171:3a7713b1edbc | 2028 | #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) |
AnnaBridge | 171:3a7713b1edbc | 2029 | |
AnnaBridge | 171:3a7713b1edbc | 2030 | /** |
AnnaBridge | 171:3a7713b1edbc | 2031 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2032 | */ |
AnnaBridge | 171:3a7713b1edbc | 2033 | |
AnnaBridge | 171:3a7713b1edbc | 2034 | #endif /* CRS */ |
AnnaBridge | 171:3a7713b1edbc | 2035 | |
AnnaBridge | 171:3a7713b1edbc | 2036 | /** |
AnnaBridge | 171:3a7713b1edbc | 2037 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2038 | */ |
AnnaBridge | 171:3a7713b1edbc | 2039 | |
AnnaBridge | 171:3a7713b1edbc | 2040 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 2041 | /** @addtogroup RCCEx_Exported_Functions |
AnnaBridge | 171:3a7713b1edbc | 2042 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2043 | */ |
AnnaBridge | 171:3a7713b1edbc | 2044 | |
AnnaBridge | 171:3a7713b1edbc | 2045 | /** @addtogroup RCCEx_Exported_Functions_Group1 |
AnnaBridge | 171:3a7713b1edbc | 2046 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2047 | */ |
AnnaBridge | 171:3a7713b1edbc | 2048 | |
AnnaBridge | 171:3a7713b1edbc | 2049 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
AnnaBridge | 171:3a7713b1edbc | 2050 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
AnnaBridge | 171:3a7713b1edbc | 2051 | uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); |
AnnaBridge | 171:3a7713b1edbc | 2052 | |
AnnaBridge | 171:3a7713b1edbc | 2053 | /** |
AnnaBridge | 171:3a7713b1edbc | 2054 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2055 | */ |
AnnaBridge | 171:3a7713b1edbc | 2056 | |
AnnaBridge | 171:3a7713b1edbc | 2057 | #if defined(CRS) |
AnnaBridge | 171:3a7713b1edbc | 2058 | |
AnnaBridge | 171:3a7713b1edbc | 2059 | /** @addtogroup RCCEx_Exported_Functions_Group3 |
AnnaBridge | 171:3a7713b1edbc | 2060 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2061 | */ |
AnnaBridge | 171:3a7713b1edbc | 2062 | |
AnnaBridge | 171:3a7713b1edbc | 2063 | void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); |
AnnaBridge | 171:3a7713b1edbc | 2064 | void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); |
AnnaBridge | 171:3a7713b1edbc | 2065 | void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); |
AnnaBridge | 171:3a7713b1edbc | 2066 | uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); |
AnnaBridge | 171:3a7713b1edbc | 2067 | void HAL_RCCEx_CRS_IRQHandler(void); |
AnnaBridge | 171:3a7713b1edbc | 2068 | void HAL_RCCEx_CRS_SyncOkCallback(void); |
AnnaBridge | 171:3a7713b1edbc | 2069 | void HAL_RCCEx_CRS_SyncWarnCallback(void); |
AnnaBridge | 171:3a7713b1edbc | 2070 | void HAL_RCCEx_CRS_ExpectedSyncCallback(void); |
AnnaBridge | 171:3a7713b1edbc | 2071 | void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); |
AnnaBridge | 171:3a7713b1edbc | 2072 | |
AnnaBridge | 171:3a7713b1edbc | 2073 | /** |
AnnaBridge | 171:3a7713b1edbc | 2074 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2075 | */ |
AnnaBridge | 171:3a7713b1edbc | 2076 | |
AnnaBridge | 171:3a7713b1edbc | 2077 | #endif /* CRS */ |
AnnaBridge | 171:3a7713b1edbc | 2078 | |
AnnaBridge | 171:3a7713b1edbc | 2079 | /** |
AnnaBridge | 171:3a7713b1edbc | 2080 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2081 | */ |
AnnaBridge | 171:3a7713b1edbc | 2082 | |
AnnaBridge | 171:3a7713b1edbc | 2083 | /** |
AnnaBridge | 171:3a7713b1edbc | 2084 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2085 | */ |
AnnaBridge | 171:3a7713b1edbc | 2086 | |
AnnaBridge | 171:3a7713b1edbc | 2087 | /** |
AnnaBridge | 171:3a7713b1edbc | 2088 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2089 | */ |
AnnaBridge | 171:3a7713b1edbc | 2090 | |
AnnaBridge | 171:3a7713b1edbc | 2091 | /** |
AnnaBridge | 171:3a7713b1edbc | 2092 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2093 | */ |
AnnaBridge | 171:3a7713b1edbc | 2094 | |
AnnaBridge | 171:3a7713b1edbc | 2095 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 2096 | } |
AnnaBridge | 171:3a7713b1edbc | 2097 | #endif |
AnnaBridge | 171:3a7713b1edbc | 2098 | |
AnnaBridge | 171:3a7713b1edbc | 2099 | #endif /* __STM32F0xx_HAL_RCC_EX_H */ |
AnnaBridge | 171:3a7713b1edbc | 2100 | |
AnnaBridge | 171:3a7713b1edbc | 2101 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |