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TARGET_MAX32630FTHR/TOOLCHAIN_IAR/spis_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * @file
AnnaBridge 171:3a7713b1edbc 3 * @brief Registers, Bit Masks and Bit Positions for the SPIS Peripheral Module.
AnnaBridge 171:3a7713b1edbc 4 */
AnnaBridge 171:3a7713b1edbc 5
AnnaBridge 171:3a7713b1edbc 6 /* ****************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 10 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 11 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 13 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 14 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 15 *
AnnaBridge 171:3a7713b1edbc 16 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 17 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 25 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 29 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 32 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 33 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 35 * ownership rights.
AnnaBridge 171:3a7713b1edbc 36 *
AnnaBridge 171:3a7713b1edbc 37 * $Date: 2016-10-31 17:11:01 -0500 (Mon, 31 Oct 2016) $
AnnaBridge 171:3a7713b1edbc 38 * $Revision: 24859 $
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 *************************************************************************** */
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 /* Define to prevent redundant inclusion */
AnnaBridge 171:3a7713b1edbc 43 #ifndef _MXC_SPIS_REGS_H_
AnnaBridge 171:3a7713b1edbc 44 #define _MXC_SPIS_REGS_H_
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /* **** Includes **** */
AnnaBridge 171:3a7713b1edbc 47 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 50 extern "C" {
AnnaBridge 171:3a7713b1edbc 51 #endif
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 ///@cond
AnnaBridge 171:3a7713b1edbc 54 /*
AnnaBridge 171:3a7713b1edbc 55 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 171:3a7713b1edbc 56 */
AnnaBridge 171:3a7713b1edbc 57 #ifndef __IO
AnnaBridge 171:3a7713b1edbc 58 #define __IO volatile
AnnaBridge 171:3a7713b1edbc 59 #endif
AnnaBridge 171:3a7713b1edbc 60 #ifndef __I
AnnaBridge 171:3a7713b1edbc 61 #define __I volatile const
AnnaBridge 171:3a7713b1edbc 62 #endif
AnnaBridge 171:3a7713b1edbc 63 #ifndef __O
AnnaBridge 171:3a7713b1edbc 64 #define __O volatile
AnnaBridge 171:3a7713b1edbc 65 #endif
AnnaBridge 171:3a7713b1edbc 66 #ifndef __RO
AnnaBridge 171:3a7713b1edbc 67 #define __RO volatile const
AnnaBridge 171:3a7713b1edbc 68 #endif
AnnaBridge 171:3a7713b1edbc 69 ///@endcond
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 /**
AnnaBridge 171:3a7713b1edbc 72 * @ingroup spis
AnnaBridge 171:3a7713b1edbc 73 * @defgroup spis_registers Registers
AnnaBridge 171:3a7713b1edbc 74 * @brief Registers, Bit Masks and Bit Positions for the SPIS Peripheral Module.
AnnaBridge 171:3a7713b1edbc 75 * @{
AnnaBridge 171:3a7713b1edbc 76 */
AnnaBridge 171:3a7713b1edbc 77
AnnaBridge 171:3a7713b1edbc 78 /**
AnnaBridge 171:3a7713b1edbc 79 * Structure type to access the SPI Slave Peripheral Module Registers
AnnaBridge 171:3a7713b1edbc 80 */
AnnaBridge 171:3a7713b1edbc 81 typedef struct {
AnnaBridge 171:3a7713b1edbc 82 __IO uint32_t gen_ctrl; /**< SPIS_GEN_CTRL Register - SPI Slave General Control Register */
AnnaBridge 171:3a7713b1edbc 83 __IO uint32_t fifo_ctrl; /**< SPIS_FIFO_CTRL Register - SPI Slave FIFO Control Register */
AnnaBridge 171:3a7713b1edbc 84 __IO uint32_t fifo_stat; /**< SPIS_FIFO_STAT Register - SPI Slave FIFO Status Register */
AnnaBridge 171:3a7713b1edbc 85 __IO uint32_t intfl; /**< SPIS_INTFL Register - SPI Slave Interrupt Flags */
AnnaBridge 171:3a7713b1edbc 86 __IO uint32_t inten; /**< SPIS_INTEN Register - SPI Slave Interrupt Enable/Disable Settings */
AnnaBridge 171:3a7713b1edbc 87 } mxc_spis_regs_t;
AnnaBridge 171:3a7713b1edbc 88
AnnaBridge 171:3a7713b1edbc 89
AnnaBridge 171:3a7713b1edbc 90 /**
AnnaBridge 171:3a7713b1edbc 91 * Structure type for the SPI Slave Transmit and Receive FIFOs.
AnnaBridge 171:3a7713b1edbc 92 */
AnnaBridge 171:3a7713b1edbc 93 typedef struct {
AnnaBridge 171:3a7713b1edbc 94 union { /* 0x0000-0x07FC SPI Slave FIFO TX Write Space */
AnnaBridge 171:3a7713b1edbc 95 __IO uint8_t tx_8[2048]; /**< 8-bit access to Transmit FIFO */
AnnaBridge 171:3a7713b1edbc 96 __IO uint16_t tx_16[1024]; /**< 16-bit access to Transmit FIFO */
AnnaBridge 171:3a7713b1edbc 97 __IO uint32_t tx_32[512]; /**< 32-bit access to Transmit FIFO */
AnnaBridge 171:3a7713b1edbc 98 };
AnnaBridge 171:3a7713b1edbc 99 union { /* 0x0800-0x0FFC SPI Slave FIFO RX Read Space */
AnnaBridge 171:3a7713b1edbc 100 __IO uint8_t rx_8[2048]; /**< 8-bit access to Receive FIFO */
AnnaBridge 171:3a7713b1edbc 101 __IO uint16_t rx_16[1024]; /**< 16-bit access to Receive FIFO */
AnnaBridge 171:3a7713b1edbc 102 __IO uint32_t rx_32[512]; /**< 32-bit access to Receive FIFO */
AnnaBridge 171:3a7713b1edbc 103 };
AnnaBridge 171:3a7713b1edbc 104 } mxc_spis_fifo_regs_t;
AnnaBridge 171:3a7713b1edbc 105 /**@} end of group spis_registers */
AnnaBridge 171:3a7713b1edbc 106
AnnaBridge 171:3a7713b1edbc 107 /*
AnnaBridge 171:3a7713b1edbc 108 Register offsets for module SPIS.
AnnaBridge 171:3a7713b1edbc 109 */
AnnaBridge 171:3a7713b1edbc 110 /**
AnnaBridge 171:3a7713b1edbc 111 * @ingroup spis_registers
AnnaBridge 171:3a7713b1edbc 112 * @defgroup SPIS_Register_Offsets Register Offsets
AnnaBridge 171:3a7713b1edbc 113 * @brief SPI Slave Register Offsets from the SPIS[n] Base Peripheral Address, where \c n \c = SPIS Instance Number.
AnnaBridge 171:3a7713b1edbc 114 * @{
AnnaBridge 171:3a7713b1edbc 115 */
AnnaBridge 171:3a7713b1edbc 116 #define MXC_R_SPIS_OFFS_GEN_CTRL ((uint32_t)0x00000000UL) /**< /**< Offset from SPIS[n] Base Peripheral Address: <tt>\b 0x0000</tt>*/
AnnaBridge 171:3a7713b1edbc 117 #define MXC_R_SPIS_OFFS_FIFO_CTRL ((uint32_t)0x00000004UL) /**< /**< Offset from SPIS[n] Base Peripheral Address: <tt>\b 0x0004</tt>*/
AnnaBridge 171:3a7713b1edbc 118 #define MXC_R_SPIS_OFFS_FIFO_STAT ((uint32_t)0x00000008UL) /**< /**< Offset from SPIS[n] Base Peripheral Address: <tt>\b 0x0008</tt>*/
AnnaBridge 171:3a7713b1edbc 119 #define MXC_R_SPIS_OFFS_INTFL ((uint32_t)0x0000000CUL) /**< /**< Offset from SPIS[n] Base Peripheral Address: <tt>\b 0x000C</tt>*/
AnnaBridge 171:3a7713b1edbc 120 #define MXC_R_SPIS_OFFS_INTEN ((uint32_t)0x00000010UL) /**< /**< Offset from SPIS[n] Base Peripheral Address: <tt>\b 0x0010</tt>*/
AnnaBridge 171:3a7713b1edbc 121 /**@} end of group SPIS_Register_Offsets*/
AnnaBridge 171:3a7713b1edbc 122 /**
AnnaBridge 171:3a7713b1edbc 123 * @ingroup spis_registers
AnnaBridge 171:3a7713b1edbc 124 * @defgroup SPIS_FIFO_Offsets FIFO Offsets
AnnaBridge 171:3a7713b1edbc 125 * @brief SPI Slave FIFO Offsets from the SPIS[n] Base FIFO Address, where \c n \c = SPIS Instance Number.
AnnaBridge 171:3a7713b1edbc 126 * @{
AnnaBridge 171:3a7713b1edbc 127 */
AnnaBridge 171:3a7713b1edbc 128 #define MXC_R_SPIS_FIFO_OFFS_TX ((uint32_t)0x00000000UL) /**< Offset from SPIS[n] Base FIFO Address: <tt>\b 0x0000</tt> */
AnnaBridge 171:3a7713b1edbc 129 #define MXC_R_SPIS_FIFO_OFFS_RX ((uint32_t)0x00000800UL) /**< Offset from SPIS[n] Base FIFO Address: <tt>\b 0x0800</tt> */
AnnaBridge 171:3a7713b1edbc 130 /**@} end of group SPIS_FIFO_Offsets*/
AnnaBridge 171:3a7713b1edbc 131
AnnaBridge 171:3a7713b1edbc 132
AnnaBridge 171:3a7713b1edbc 133 /*
AnnaBridge 171:3a7713b1edbc 134 Field positions and masks for module SPIS.
AnnaBridge 171:3a7713b1edbc 135 */
AnnaBridge 171:3a7713b1edbc 136 /**
AnnaBridge 171:3a7713b1edbc 137 * @ingroup spis_registers
AnnaBridge 171:3a7713b1edbc 138 * @defgroup SPIS_GEN_CTRL_Register SPIS_GEN_CTRL
AnnaBridge 171:3a7713b1edbc 139 * @brief Field Positions and Bit Masks for the SPIS_GEN_CTRL register
AnnaBridge 171:3a7713b1edbc 140 * @{
AnnaBridge 171:3a7713b1edbc 141 */
AnnaBridge 171:3a7713b1edbc 142 #define MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN_POS 0 /**< SPI_SLAVE_EN Position */
AnnaBridge 171:3a7713b1edbc 143 #define MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN_POS)) /**< SPI_SLAVE_EN Mask */
AnnaBridge 171:3a7713b1edbc 144 #define MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN_POS 1 /**< TX_FIFO_EN Position */
AnnaBridge 171:3a7713b1edbc 145 #define MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN_POS)) /**< TX_FIFO_EN Mask */
AnnaBridge 171:3a7713b1edbc 146 #define MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN_POS 2 /**< RX_FIFO_EN Position */
AnnaBridge 171:3a7713b1edbc 147 #define MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN_POS)) /**< RX_FIFO_EN Mask */
AnnaBridge 171:3a7713b1edbc 148 #define MXC_F_SPIS_GEN_CTRL_DATA_WIDTH_POS 4 /**< DATA_WIDTH Position */
AnnaBridge 171:3a7713b1edbc 149 #define MXC_F_SPIS_GEN_CTRL_DATA_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIS_GEN_CTRL_DATA_WIDTH_POS)) /**< DATA_WIDTH Mask */
AnnaBridge 171:3a7713b1edbc 150 #define MXC_F_SPIS_GEN_CTRL_SPI_MODE_POS 16 /**< SPI_MODE Position */
AnnaBridge 171:3a7713b1edbc 151 #define MXC_F_SPIS_GEN_CTRL_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIS_GEN_CTRL_SPI_MODE_POS)) /**< SPI_MODE Mask */
AnnaBridge 171:3a7713b1edbc 152 #define MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT_POS 20 /**< TX_CLK_INVERT Position */
AnnaBridge 171:3a7713b1edbc 153 #define MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT_POS)) /**< TX_CLK_INVERT Mask */
AnnaBridge 171:3a7713b1edbc 154 /**@} end of group SPIS_GEN_CTRL*/
AnnaBridge 171:3a7713b1edbc 155 /**
AnnaBridge 171:3a7713b1edbc 156 * @ingroup spis_registers
AnnaBridge 171:3a7713b1edbc 157 * @defgroup SPIS_FIFO_CTRL_Register SPIS_FIFO_CTRL
AnnaBridge 171:3a7713b1edbc 158 * @brief Field Positions and Bit Masks for the SPIS_FIFO_CTRL register
AnnaBridge 171:3a7713b1edbc 159 * @{
AnnaBridge 171:3a7713b1edbc 160 */
AnnaBridge 171:3a7713b1edbc 161 #define MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0 /**< TX_FIFO_AE_LVL Position */
AnnaBridge 171:3a7713b1edbc 162 #define MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL_POS)) /**< TX_FIFO_AE_LVL Mask */
AnnaBridge 171:3a7713b1edbc 163 #define MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL_POS 8 /**< RX_FIFO_AF_LVL Position */
AnnaBridge 171:3a7713b1edbc 164 #define MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL_POS)) /**< RX_FIFO_AF_LVL Mask */
AnnaBridge 171:3a7713b1edbc 165 /**@} end of group SPIS_FIFO_CTRL_Register*/
AnnaBridge 171:3a7713b1edbc 166 /**
AnnaBridge 171:3a7713b1edbc 167 * @ingroup spis_registers
AnnaBridge 171:3a7713b1edbc 168 * @defgroup SPIS_FIFO_STAT_Register SPIS_FIFO_STAT
AnnaBridge 171:3a7713b1edbc 169 * @brief Field Positions and Bit Masks for the SPIS_FIFO_STAT register
AnnaBridge 171:3a7713b1edbc 170 * @{
AnnaBridge 171:3a7713b1edbc 171 */
AnnaBridge 171:3a7713b1edbc 172 #define MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED_POS 0 /**< TX_FIFO_USED Position */
AnnaBridge 171:3a7713b1edbc 173 #define MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED_POS)) /**< TX_FIFO_USED Mask */
AnnaBridge 171:3a7713b1edbc 174 #define MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED_POS 8 /**< RX_FIFO_USED Position */
AnnaBridge 171:3a7713b1edbc 175 #define MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED_POS)) /**< RX_FIFO_USED Mask */
AnnaBridge 171:3a7713b1edbc 176 /**@} end of group SPIS_FIFO_STAT_Register*/
AnnaBridge 171:3a7713b1edbc 177 /**
AnnaBridge 171:3a7713b1edbc 178 * @ingroup spis_registers
AnnaBridge 171:3a7713b1edbc 179 * @defgroup SPIS_INTFL_Register SPIS_INTFL
AnnaBridge 171:3a7713b1edbc 180 * @brief Field Positions and Bit Masks for the SPIS_INTFL register
AnnaBridge 171:3a7713b1edbc 181 * @{
AnnaBridge 171:3a7713b1edbc 182 */
AnnaBridge 171:3a7713b1edbc 183 #define MXC_F_SPIS_INTFL_TX_FIFO_AE_POS 0 /**< TX_FIFO_AE Position */
AnnaBridge 171:3a7713b1edbc 184 #define MXC_F_SPIS_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_FIFO_AE_POS)) /**< TX_FIFO_AE Mask */
AnnaBridge 171:3a7713b1edbc 185 #define MXC_F_SPIS_INTFL_RX_FIFO_AF_POS 1 /**< RX_FIFO_AF Position */
AnnaBridge 171:3a7713b1edbc 186 #define MXC_F_SPIS_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_RX_FIFO_AF_POS)) /**< RX_FIFO_AF Mask */
AnnaBridge 171:3a7713b1edbc 187 #define MXC_F_SPIS_INTFL_TX_NO_DATA_POS 2 /**< TX_NO_DATA Position */
AnnaBridge 171:3a7713b1edbc 188 #define MXC_F_SPIS_INTFL_TX_NO_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_NO_DATA_POS)) /**< TX_NO_DATA Mask */
AnnaBridge 171:3a7713b1edbc 189 #define MXC_F_SPIS_INTFL_RX_LOST_DATA_POS 3 /**< RX_LOST_DATA Position */
AnnaBridge 171:3a7713b1edbc 190 #define MXC_F_SPIS_INTFL_RX_LOST_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_RX_LOST_DATA_POS)) /**< RX_LOST_DATA Mask */
AnnaBridge 171:3a7713b1edbc 191 #define MXC_F_SPIS_INTFL_TX_UNDERFLOW_POS 4 /**< TX_UNDERFLOW Position */
AnnaBridge 171:3a7713b1edbc 192 #define MXC_F_SPIS_INTFL_TX_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_UNDERFLOW_POS)) /**< TX_UNDERFLOW Mask */
AnnaBridge 171:3a7713b1edbc 193 #define MXC_F_SPIS_INTFL_SS_ASSERTED_POS 5 /**< SS_ASSERTED Position */
AnnaBridge 171:3a7713b1edbc 194 #define MXC_F_SPIS_INTFL_SS_ASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_SS_ASSERTED_POS)) /**< SS_ASSERTED Mask */
AnnaBridge 171:3a7713b1edbc 195 #define MXC_F_SPIS_INTFL_SS_DEASSERTED_POS 6 /**< SS_DEASSERTED Position */
AnnaBridge 171:3a7713b1edbc 196 #define MXC_F_SPIS_INTFL_SS_DEASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_SS_DEASSERTED_POS)) /**< SS_DEASSERTED Mask */
AnnaBridge 171:3a7713b1edbc 197 /**@} end of group SPIS_INTFL_Register*/
AnnaBridge 171:3a7713b1edbc 198 /**
AnnaBridge 171:3a7713b1edbc 199 * @ingroup spis_registers
AnnaBridge 171:3a7713b1edbc 200 * @defgroup SPIS_INTEN_Register SPIS_INTEN
AnnaBridge 171:3a7713b1edbc 201 * @brief Field Positions and Bit Masks for the SPIS_INTEN register
AnnaBridge 171:3a7713b1edbc 202 * @{
AnnaBridge 171:3a7713b1edbc 203 */
AnnaBridge 171:3a7713b1edbc 204 #define MXC_F_SPIS_INTEN_TX_FIFO_AE_POS 0 /**< TX_FIFO_AE Position */
AnnaBridge 171:3a7713b1edbc 205 #define MXC_F_SPIS_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_FIFO_AE_POS)) /**< TX_FIFO_AE Mask */
AnnaBridge 171:3a7713b1edbc 206 #define MXC_F_SPIS_INTEN_RX_FIFO_AF_POS 1 /**< RX_FIFO_AF Position */
AnnaBridge 171:3a7713b1edbc 207 #define MXC_F_SPIS_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_RX_FIFO_AF_POS)) /**< RX_FIFO_AF Mask */
AnnaBridge 171:3a7713b1edbc 208 #define MXC_F_SPIS_INTEN_TX_NO_DATA_POS 2 /**< TX_NO_DATA Position */
AnnaBridge 171:3a7713b1edbc 209 #define MXC_F_SPIS_INTEN_TX_NO_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_NO_DATA_POS)) /**< TX_NO_DATA Mask */
AnnaBridge 171:3a7713b1edbc 210 #define MXC_F_SPIS_INTEN_RX_LOST_DATA_POS 3 /**< RX_LOST_DATA Position */
AnnaBridge 171:3a7713b1edbc 211 #define MXC_F_SPIS_INTEN_RX_LOST_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_RX_LOST_DATA_POS)) /**< RX_LOST_DATA Mask */
AnnaBridge 171:3a7713b1edbc 212 #define MXC_F_SPIS_INTEN_TX_UNDERFLOW_POS 4 /**< TX_UNDERFLOW Position */
AnnaBridge 171:3a7713b1edbc 213 #define MXC_F_SPIS_INTEN_TX_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_UNDERFLOW_POS)) /**< TX_UNDERFLOW Mask */
AnnaBridge 171:3a7713b1edbc 214 #define MXC_F_SPIS_INTEN_SS_ASSERTED_POS 5 /**< SS_ASSERTED Position */
AnnaBridge 171:3a7713b1edbc 215 #define MXC_F_SPIS_INTEN_SS_ASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_SS_ASSERTED_POS)) /**< SS_ASSERTED Mask */
AnnaBridge 171:3a7713b1edbc 216 #define MXC_F_SPIS_INTEN_SS_DEASSERTED_POS 6 /**< SS_DEASSERTED Position */
AnnaBridge 171:3a7713b1edbc 217 #define MXC_F_SPIS_INTEN_SS_DEASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_SS_DEASSERTED_POS)) /**< SS_DEASSERTED Mask */
AnnaBridge 171:3a7713b1edbc 218 /**@} end of group SPIS_INTEN_Register*/
AnnaBridge 171:3a7713b1edbc 219 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 220 }
AnnaBridge 171:3a7713b1edbc 221 #endif
AnnaBridge 171:3a7713b1edbc 222
AnnaBridge 171:3a7713b1edbc 223 #endif /* _MXC_SPIS_REGS_H_ */
AnnaBridge 171:3a7713b1edbc 224