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TARGET_LPC1768/TOOLCHAIN_ARM_STD/core_cm7.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/************************************************************************//
AnnaBridge	171:3a7713b1edbc	2	* @file core_cm7.h
AnnaBridge	171:3a7713b1edbc	3	* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
AnnaBridge	171:3a7713b1edbc	4	* @version V5.0.8
AnnaBridge	171:3a7713b1edbc	5	* @date 04. June 2018
AnnaBridge	171:3a7713b1edbc	6	******************************************************************************/
AnnaBridge	171:3a7713b1edbc	7	/*
AnnaBridge	171:3a7713b1edbc	8	* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
AnnaBridge	171:3a7713b1edbc	9	*
AnnaBridge	171:3a7713b1edbc	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	171:3a7713b1edbc	11	*
AnnaBridge	171:3a7713b1edbc	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	171:3a7713b1edbc	13	* not use this file except in compliance with the License.
AnnaBridge	171:3a7713b1edbc	14	* You may obtain a copy of the License at
AnnaBridge	171:3a7713b1edbc	15	*
AnnaBridge	171:3a7713b1edbc	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	171:3a7713b1edbc	17	*
AnnaBridge	171:3a7713b1edbc	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	171:3a7713b1edbc	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	171:3a7713b1edbc	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	171:3a7713b1edbc	21	* See the License for the specific language governing permissions and
AnnaBridge	171:3a7713b1edbc	22	* limitations under the License.
AnnaBridge	171:3a7713b1edbc	23	*/
AnnaBridge	171:3a7713b1edbc	24
AnnaBridge	171:3a7713b1edbc	25	#if defined ( __ICCARM__ )
AnnaBridge	171:3a7713b1edbc	26	#pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge	171:3a7713b1edbc	27	#elif defined (__clang__)
AnnaBridge	171:3a7713b1edbc	28	#pragma clang system_header /* treat file as system include file */
AnnaBridge	171:3a7713b1edbc	29	#endif
AnnaBridge	171:3a7713b1edbc	30
AnnaBridge	171:3a7713b1edbc	31	#ifndef __CORE_CM7_H_GENERIC
AnnaBridge	171:3a7713b1edbc	32	#define __CORE_CM7_H_GENERIC
AnnaBridge	171:3a7713b1edbc	33
AnnaBridge	171:3a7713b1edbc	34	#include <stdint.h>
AnnaBridge	171:3a7713b1edbc	35
AnnaBridge	171:3a7713b1edbc	36	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	37	extern "C" {
AnnaBridge	171:3a7713b1edbc	38	#endif
AnnaBridge	171:3a7713b1edbc	39
AnnaBridge	171:3a7713b1edbc	40	/**
AnnaBridge	171:3a7713b1edbc	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge	171:3a7713b1edbc	42	CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge	171:3a7713b1edbc	43
AnnaBridge	171:3a7713b1edbc	44	\li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge	171:3a7713b1edbc	45	Function definitions in header files are used to allow 'inlining'.
AnnaBridge	171:3a7713b1edbc	46
AnnaBridge	171:3a7713b1edbc	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge	171:3a7713b1edbc	48	Unions are used for effective representation of core registers.
AnnaBridge	171:3a7713b1edbc	49
AnnaBridge	171:3a7713b1edbc	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge	171:3a7713b1edbc	51	Function-like macros are used to allow more efficient code.
AnnaBridge	171:3a7713b1edbc	52	*/
AnnaBridge	171:3a7713b1edbc	53
AnnaBridge	171:3a7713b1edbc	54
AnnaBridge	171:3a7713b1edbc	55	/*******************************************************************************
AnnaBridge	171:3a7713b1edbc	56	* CMSIS definitions
AnnaBridge	171:3a7713b1edbc	57	******************************************************************************/
AnnaBridge	171:3a7713b1edbc	58	/**
AnnaBridge	171:3a7713b1edbc	59	\ingroup Cortex_M7
AnnaBridge	171:3a7713b1edbc	60	@{
AnnaBridge	171:3a7713b1edbc	61	*/
AnnaBridge	171:3a7713b1edbc	62
AnnaBridge	171:3a7713b1edbc	63	#include "cmsis_version.h"
AnnaBridge	171:3a7713b1edbc	64
AnnaBridge	171:3a7713b1edbc	65	/* CMSIS CM7 definitions */
AnnaBridge	171:3a7713b1edbc	66	#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
AnnaBridge	171:3a7713b1edbc	67	#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
AnnaBridge	171:3a7713b1edbc	68	#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) \| \
AnnaBridge	171:3a7713b1edbc	69	__CM7_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
AnnaBridge	171:3a7713b1edbc	70
AnnaBridge	171:3a7713b1edbc	71	#define __CORTEX_M (7U) /!< Cortex-M Core /
AnnaBridge	171:3a7713b1edbc	72
AnnaBridge	171:3a7713b1edbc	73	/** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge	171:3a7713b1edbc	74	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
AnnaBridge	171:3a7713b1edbc	75	*/
AnnaBridge	171:3a7713b1edbc	76	#if defined ( __CC_ARM )
AnnaBridge	171:3a7713b1edbc	77	#if defined __TARGET_FPU_VFP
AnnaBridge	171:3a7713b1edbc	78	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	79	#define __FPU_USED 1U
AnnaBridge	171:3a7713b1edbc	80	#else
AnnaBridge	171:3a7713b1edbc	81	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	171:3a7713b1edbc	82	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	83	#endif
AnnaBridge	171:3a7713b1edbc	84	#else
AnnaBridge	171:3a7713b1edbc	85	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	86	#endif
AnnaBridge	171:3a7713b1edbc	87
AnnaBridge	171:3a7713b1edbc	88	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	172:65be27845400	89	#if defined __ARM_FP
AnnaBridge	171:3a7713b1edbc	90	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	91	#define __FPU_USED 1U
AnnaBridge	171:3a7713b1edbc	92	#else
AnnaBridge	171:3a7713b1edbc	93	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	171:3a7713b1edbc	94	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	95	#endif
AnnaBridge	171:3a7713b1edbc	96	#else
AnnaBridge	171:3a7713b1edbc	97	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	98	#endif
AnnaBridge	171:3a7713b1edbc	99
AnnaBridge	171:3a7713b1edbc	100	#elif defined ( __GNUC__ )
AnnaBridge	171:3a7713b1edbc	101	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge	171:3a7713b1edbc	102	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	103	#define __FPU_USED 1U
AnnaBridge	171:3a7713b1edbc	104	#else
AnnaBridge	171:3a7713b1edbc	105	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	171:3a7713b1edbc	106	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	107	#endif
AnnaBridge	171:3a7713b1edbc	108	#else
AnnaBridge	171:3a7713b1edbc	109	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	110	#endif
AnnaBridge	171:3a7713b1edbc	111
AnnaBridge	171:3a7713b1edbc	112	#elif defined ( __ICCARM__ )
AnnaBridge	171:3a7713b1edbc	113	#if defined __ARMVFP__
AnnaBridge	171:3a7713b1edbc	114	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	115	#define __FPU_USED 1U
AnnaBridge	171:3a7713b1edbc	116	#else
AnnaBridge	171:3a7713b1edbc	117	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	171:3a7713b1edbc	118	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	119	#endif
AnnaBridge	171:3a7713b1edbc	120	#else
AnnaBridge	171:3a7713b1edbc	121	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	122	#endif
AnnaBridge	171:3a7713b1edbc	123
AnnaBridge	171:3a7713b1edbc	124	#elif defined ( __TI_ARM__ )
AnnaBridge	171:3a7713b1edbc	125	#if defined __TI_VFP_SUPPORT__
AnnaBridge	171:3a7713b1edbc	126	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	127	#define __FPU_USED 1U
AnnaBridge	171:3a7713b1edbc	128	#else
AnnaBridge	171:3a7713b1edbc	129	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	171:3a7713b1edbc	130	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	131	#endif
AnnaBridge	171:3a7713b1edbc	132	#else
AnnaBridge	171:3a7713b1edbc	133	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	134	#endif
AnnaBridge	171:3a7713b1edbc	135
AnnaBridge	171:3a7713b1edbc	136	#elif defined ( __TASKING__ )
AnnaBridge	171:3a7713b1edbc	137	#if defined __FPU_VFP__
AnnaBridge	171:3a7713b1edbc	138	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	139	#define __FPU_USED 1U
AnnaBridge	171:3a7713b1edbc	140	#else
AnnaBridge	171:3a7713b1edbc	141	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	171:3a7713b1edbc	142	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	143	#endif
AnnaBridge	171:3a7713b1edbc	144	#else
AnnaBridge	171:3a7713b1edbc	145	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	146	#endif
AnnaBridge	171:3a7713b1edbc	147
AnnaBridge	171:3a7713b1edbc	148	#elif defined ( __CSMC__ )
AnnaBridge	171:3a7713b1edbc	149	#if ( __CSMC__ & 0x400U)
AnnaBridge	171:3a7713b1edbc	150	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	151	#define __FPU_USED 1U
AnnaBridge	171:3a7713b1edbc	152	#else
AnnaBridge	171:3a7713b1edbc	153	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	171:3a7713b1edbc	154	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	155	#endif
AnnaBridge	171:3a7713b1edbc	156	#else
AnnaBridge	171:3a7713b1edbc	157	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	158	#endif
AnnaBridge	171:3a7713b1edbc	159
AnnaBridge	171:3a7713b1edbc	160	#endif
AnnaBridge	171:3a7713b1edbc	161
AnnaBridge	171:3a7713b1edbc	162	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge	171:3a7713b1edbc	163
AnnaBridge	171:3a7713b1edbc	164
AnnaBridge	171:3a7713b1edbc	165	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	166	}
AnnaBridge	171:3a7713b1edbc	167	#endif
AnnaBridge	171:3a7713b1edbc	168
AnnaBridge	171:3a7713b1edbc	169	#endif /* __CORE_CM7_H_GENERIC */
AnnaBridge	171:3a7713b1edbc	170
AnnaBridge	171:3a7713b1edbc	171	#ifndef __CMSIS_GENERIC
AnnaBridge	171:3a7713b1edbc	172
AnnaBridge	171:3a7713b1edbc	173	#ifndef __CORE_CM7_H_DEPENDANT
AnnaBridge	171:3a7713b1edbc	174	#define __CORE_CM7_H_DEPENDANT
AnnaBridge	171:3a7713b1edbc	175
AnnaBridge	171:3a7713b1edbc	176	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	177	extern "C" {
AnnaBridge	171:3a7713b1edbc	178	#endif
AnnaBridge	171:3a7713b1edbc	179
AnnaBridge	171:3a7713b1edbc	180	/* check device defines and use defaults */
AnnaBridge	171:3a7713b1edbc	181	#if defined __CHECK_DEVICE_DEFINES
AnnaBridge	171:3a7713b1edbc	182	#ifndef __CM7_REV
AnnaBridge	171:3a7713b1edbc	183	#define __CM7_REV 0x0000U
AnnaBridge	171:3a7713b1edbc	184	#warning "__CM7_REV not defined in device header file; using default!"
AnnaBridge	171:3a7713b1edbc	185	#endif
AnnaBridge	171:3a7713b1edbc	186
AnnaBridge	171:3a7713b1edbc	187	#ifndef __FPU_PRESENT
AnnaBridge	171:3a7713b1edbc	188	#define __FPU_PRESENT 0U
AnnaBridge	171:3a7713b1edbc	189	#warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge	171:3a7713b1edbc	190	#endif
AnnaBridge	171:3a7713b1edbc	191
AnnaBridge	171:3a7713b1edbc	192	#ifndef __MPU_PRESENT
AnnaBridge	171:3a7713b1edbc	193	#define __MPU_PRESENT 0U
AnnaBridge	171:3a7713b1edbc	194	#warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge	171:3a7713b1edbc	195	#endif
AnnaBridge	171:3a7713b1edbc	196
AnnaBridge	171:3a7713b1edbc	197	#ifndef __ICACHE_PRESENT
AnnaBridge	171:3a7713b1edbc	198	#define __ICACHE_PRESENT 0U
AnnaBridge	171:3a7713b1edbc	199	#warning "__ICACHE_PRESENT not defined in device header file; using default!"
AnnaBridge	171:3a7713b1edbc	200	#endif
AnnaBridge	171:3a7713b1edbc	201
AnnaBridge	171:3a7713b1edbc	202	#ifndef __DCACHE_PRESENT
AnnaBridge	171:3a7713b1edbc	203	#define __DCACHE_PRESENT 0U
AnnaBridge	171:3a7713b1edbc	204	#warning "__DCACHE_PRESENT not defined in device header file; using default!"
AnnaBridge	171:3a7713b1edbc	205	#endif
AnnaBridge	171:3a7713b1edbc	206
AnnaBridge	171:3a7713b1edbc	207	#ifndef __DTCM_PRESENT
AnnaBridge	171:3a7713b1edbc	208	#define __DTCM_PRESENT 0U
AnnaBridge	171:3a7713b1edbc	209	#warning "__DTCM_PRESENT not defined in device header file; using default!"
AnnaBridge	171:3a7713b1edbc	210	#endif
AnnaBridge	171:3a7713b1edbc	211
AnnaBridge	171:3a7713b1edbc	212	#ifndef __NVIC_PRIO_BITS
AnnaBridge	171:3a7713b1edbc	213	#define __NVIC_PRIO_BITS 3U
AnnaBridge	171:3a7713b1edbc	214	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge	171:3a7713b1edbc	215	#endif
AnnaBridge	171:3a7713b1edbc	216
AnnaBridge	171:3a7713b1edbc	217	#ifndef __Vendor_SysTickConfig
AnnaBridge	171:3a7713b1edbc	218	#define __Vendor_SysTickConfig 0U
AnnaBridge	171:3a7713b1edbc	219	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge	171:3a7713b1edbc	220	#endif
AnnaBridge	171:3a7713b1edbc	221	#endif
AnnaBridge	171:3a7713b1edbc	222
AnnaBridge	171:3a7713b1edbc	223	/* IO definitions (access restrictions to peripheral registers) */
AnnaBridge	171:3a7713b1edbc	224	/**
AnnaBridge	171:3a7713b1edbc	225	\defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge	171:3a7713b1edbc	226
AnnaBridge	171:3a7713b1edbc	227	<strong>IO Type Qualifiers</strong> are used
AnnaBridge	171:3a7713b1edbc	228	\li to specify the access to peripheral variables.
AnnaBridge	171:3a7713b1edbc	229	\li for automatic generation of peripheral register debug information.
AnnaBridge	171:3a7713b1edbc	230	*/
AnnaBridge	171:3a7713b1edbc	231	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	232	#define __I volatile /!< Defines 'read only' permissions /
AnnaBridge	171:3a7713b1edbc	233	#else
AnnaBridge	171:3a7713b1edbc	234	#define __I volatile const /!< Defines 'read only' permissions /
AnnaBridge	171:3a7713b1edbc	235	#endif
AnnaBridge	171:3a7713b1edbc	236	#define __O volatile /!< Defines 'write only' permissions /
AnnaBridge	171:3a7713b1edbc	237	#define __IO volatile /!< Defines 'read / write' permissions /
AnnaBridge	171:3a7713b1edbc	238
AnnaBridge	171:3a7713b1edbc	239	/* following defines should be used for structure members */
AnnaBridge	171:3a7713b1edbc	240	#define __IM volatile const /! Defines 'read only' structure member permissions /
AnnaBridge	171:3a7713b1edbc	241	#define __OM volatile /! Defines 'write only' structure member permissions /
AnnaBridge	171:3a7713b1edbc	242	#define __IOM volatile /! Defines 'read / write' structure member permissions /
AnnaBridge	171:3a7713b1edbc	243
AnnaBridge	171:3a7713b1edbc	244	/@} end of group Cortex_M7 /
AnnaBridge	171:3a7713b1edbc	245
AnnaBridge	171:3a7713b1edbc	246
AnnaBridge	171:3a7713b1edbc	247
AnnaBridge	171:3a7713b1edbc	248	/*******************************************************************************
AnnaBridge	171:3a7713b1edbc	249	* Register Abstraction
AnnaBridge	171:3a7713b1edbc	250	Core Register contain:
AnnaBridge	171:3a7713b1edbc	251	- Core Register
AnnaBridge	171:3a7713b1edbc	252	- Core NVIC Register
AnnaBridge	171:3a7713b1edbc	253	- Core SCB Register
AnnaBridge	171:3a7713b1edbc	254	- Core SysTick Register
AnnaBridge	171:3a7713b1edbc	255	- Core Debug Register
AnnaBridge	171:3a7713b1edbc	256	- Core MPU Register
AnnaBridge	171:3a7713b1edbc	257	- Core FPU Register
AnnaBridge	171:3a7713b1edbc	258	******************************************************************************/
AnnaBridge	171:3a7713b1edbc	259	/**
AnnaBridge	171:3a7713b1edbc	260	\defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge	171:3a7713b1edbc	261	\brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge	171:3a7713b1edbc	262	*/
AnnaBridge	171:3a7713b1edbc	263
AnnaBridge	171:3a7713b1edbc	264	/**
AnnaBridge	171:3a7713b1edbc	265	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	266	\defgroup CMSIS_CORE Status and Control Registers
AnnaBridge	171:3a7713b1edbc	267	\brief Core Register type definitions.
AnnaBridge	171:3a7713b1edbc	268	@{
AnnaBridge	171:3a7713b1edbc	269	*/
AnnaBridge	171:3a7713b1edbc	270
AnnaBridge	171:3a7713b1edbc	271	/**
AnnaBridge	171:3a7713b1edbc	272	\brief Union type to access the Application Program Status Register (APSR).
AnnaBridge	171:3a7713b1edbc	273	*/
AnnaBridge	171:3a7713b1edbc	274	typedef union
AnnaBridge	171:3a7713b1edbc	275	{
AnnaBridge	171:3a7713b1edbc	276	struct
AnnaBridge	171:3a7713b1edbc	277	{
AnnaBridge	171:3a7713b1edbc	278	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
AnnaBridge	171:3a7713b1edbc	279	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
AnnaBridge	171:3a7713b1edbc	280	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
AnnaBridge	171:3a7713b1edbc	281	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	171:3a7713b1edbc	282	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	171:3a7713b1edbc	283	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	171:3a7713b1edbc	284	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	171:3a7713b1edbc	285	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	171:3a7713b1edbc	286	} b; /!< Structure used for bit access /
AnnaBridge	171:3a7713b1edbc	287	uint32_t w; /!< Type used for word access /
AnnaBridge	171:3a7713b1edbc	288	} APSR_Type;
AnnaBridge	171:3a7713b1edbc	289
AnnaBridge	171:3a7713b1edbc	290	/* APSR Register Definitions */
AnnaBridge	171:3a7713b1edbc	291	#define APSR_N_Pos 31U /!< APSR: N Position /
AnnaBridge	171:3a7713b1edbc	292	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
AnnaBridge	171:3a7713b1edbc	293
AnnaBridge	171:3a7713b1edbc	294	#define APSR_Z_Pos 30U /!< APSR: Z Position /
AnnaBridge	171:3a7713b1edbc	295	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
AnnaBridge	171:3a7713b1edbc	296
AnnaBridge	171:3a7713b1edbc	297	#define APSR_C_Pos 29U /!< APSR: C Position /
AnnaBridge	171:3a7713b1edbc	298	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
AnnaBridge	171:3a7713b1edbc	299
AnnaBridge	171:3a7713b1edbc	300	#define APSR_V_Pos 28U /!< APSR: V Position /
AnnaBridge	171:3a7713b1edbc	301	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
AnnaBridge	171:3a7713b1edbc	302
AnnaBridge	171:3a7713b1edbc	303	#define APSR_Q_Pos 27U /!< APSR: Q Position /
AnnaBridge	171:3a7713b1edbc	304	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
AnnaBridge	171:3a7713b1edbc	305
AnnaBridge	171:3a7713b1edbc	306	#define APSR_GE_Pos 16U /!< APSR: GE Position /
AnnaBridge	171:3a7713b1edbc	307	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
AnnaBridge	171:3a7713b1edbc	308
AnnaBridge	171:3a7713b1edbc	309
AnnaBridge	171:3a7713b1edbc	310	/**
AnnaBridge	171:3a7713b1edbc	311	\brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge	171:3a7713b1edbc	312	*/
AnnaBridge	171:3a7713b1edbc	313	typedef union
AnnaBridge	171:3a7713b1edbc	314	{
AnnaBridge	171:3a7713b1edbc	315	struct
AnnaBridge	171:3a7713b1edbc	316	{
AnnaBridge	171:3a7713b1edbc	317	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	171:3a7713b1edbc	318	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
AnnaBridge	171:3a7713b1edbc	319	} b; /!< Structure used for bit access /
AnnaBridge	171:3a7713b1edbc	320	uint32_t w; /!< Type used for word access /
AnnaBridge	171:3a7713b1edbc	321	} IPSR_Type;
AnnaBridge	171:3a7713b1edbc	322
AnnaBridge	171:3a7713b1edbc	323	/* IPSR Register Definitions */
AnnaBridge	171:3a7713b1edbc	324	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
AnnaBridge	171:3a7713b1edbc	325	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
AnnaBridge	171:3a7713b1edbc	326
AnnaBridge	171:3a7713b1edbc	327
AnnaBridge	171:3a7713b1edbc	328	/**
AnnaBridge	171:3a7713b1edbc	329	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge	171:3a7713b1edbc	330	*/
AnnaBridge	171:3a7713b1edbc	331	typedef union
AnnaBridge	171:3a7713b1edbc	332	{
AnnaBridge	171:3a7713b1edbc	333	struct
AnnaBridge	171:3a7713b1edbc	334	{
AnnaBridge	171:3a7713b1edbc	335	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	171:3a7713b1edbc	336	uint32_t _reserved0:1; /!< bit: 9 Reserved /
AnnaBridge	171:3a7713b1edbc	337	uint32_t ICI_IT_1:6; /!< bit: 10..15 ICI/IT part 1 /
AnnaBridge	171:3a7713b1edbc	338	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
AnnaBridge	171:3a7713b1edbc	339	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
AnnaBridge	171:3a7713b1edbc	340	uint32_t T:1; /!< bit: 24 Thumb bit /
AnnaBridge	171:3a7713b1edbc	341	uint32_t ICI_IT_2:2; /!< bit: 25..26 ICI/IT part 2 /
AnnaBridge	171:3a7713b1edbc	342	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	171:3a7713b1edbc	343	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	171:3a7713b1edbc	344	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	171:3a7713b1edbc	345	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	171:3a7713b1edbc	346	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	171:3a7713b1edbc	347	} b; /!< Structure used for bit access /
AnnaBridge	171:3a7713b1edbc	348	uint32_t w; /!< Type used for word access /
AnnaBridge	171:3a7713b1edbc	349	} xPSR_Type;
AnnaBridge	171:3a7713b1edbc	350
AnnaBridge	171:3a7713b1edbc	351	/* xPSR Register Definitions */
AnnaBridge	171:3a7713b1edbc	352	#define xPSR_N_Pos 31U /!< xPSR: N Position /
AnnaBridge	171:3a7713b1edbc	353	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
AnnaBridge	171:3a7713b1edbc	354
AnnaBridge	171:3a7713b1edbc	355	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
AnnaBridge	171:3a7713b1edbc	356	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
AnnaBridge	171:3a7713b1edbc	357
AnnaBridge	171:3a7713b1edbc	358	#define xPSR_C_Pos 29U /!< xPSR: C Position /
AnnaBridge	171:3a7713b1edbc	359	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
AnnaBridge	171:3a7713b1edbc	360
AnnaBridge	171:3a7713b1edbc	361	#define xPSR_V_Pos 28U /!< xPSR: V Position /
AnnaBridge	171:3a7713b1edbc	362	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
AnnaBridge	171:3a7713b1edbc	363
AnnaBridge	171:3a7713b1edbc	364	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
AnnaBridge	171:3a7713b1edbc	365	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
AnnaBridge	171:3a7713b1edbc	366
AnnaBridge	171:3a7713b1edbc	367	#define xPSR_ICI_IT_2_Pos 25U /!< xPSR: ICI/IT part 2 Position /
AnnaBridge	171:3a7713b1edbc	368	#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /!< xPSR: ICI/IT part 2 Mask /
AnnaBridge	171:3a7713b1edbc	369
AnnaBridge	171:3a7713b1edbc	370	#define xPSR_T_Pos 24U /!< xPSR: T Position /
AnnaBridge	171:3a7713b1edbc	371	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
AnnaBridge	171:3a7713b1edbc	372
AnnaBridge	171:3a7713b1edbc	373	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
AnnaBridge	171:3a7713b1edbc	374	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
AnnaBridge	171:3a7713b1edbc	375
AnnaBridge	171:3a7713b1edbc	376	#define xPSR_ICI_IT_1_Pos 10U /!< xPSR: ICI/IT part 1 Position /
AnnaBridge	171:3a7713b1edbc	377	#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /!< xPSR: ICI/IT part 1 Mask /
AnnaBridge	171:3a7713b1edbc	378
AnnaBridge	171:3a7713b1edbc	379	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
AnnaBridge	171:3a7713b1edbc	380	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
AnnaBridge	171:3a7713b1edbc	381
AnnaBridge	171:3a7713b1edbc	382
AnnaBridge	171:3a7713b1edbc	383	/**
AnnaBridge	171:3a7713b1edbc	384	\brief Union type to access the Control Registers (CONTROL).
AnnaBridge	171:3a7713b1edbc	385	*/
AnnaBridge	171:3a7713b1edbc	386	typedef union
AnnaBridge	171:3a7713b1edbc	387	{
AnnaBridge	171:3a7713b1edbc	388	struct
AnnaBridge	171:3a7713b1edbc	389	{
AnnaBridge	171:3a7713b1edbc	390	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
AnnaBridge	171:3a7713b1edbc	391	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
AnnaBridge	171:3a7713b1edbc	392	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
AnnaBridge	171:3a7713b1edbc	393	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
AnnaBridge	171:3a7713b1edbc	394	} b; /!< Structure used for bit access /
AnnaBridge	171:3a7713b1edbc	395	uint32_t w; /!< Type used for word access /
AnnaBridge	171:3a7713b1edbc	396	} CONTROL_Type;
AnnaBridge	171:3a7713b1edbc	397
AnnaBridge	171:3a7713b1edbc	398	/* CONTROL Register Definitions */
AnnaBridge	171:3a7713b1edbc	399	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
AnnaBridge	171:3a7713b1edbc	400	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
AnnaBridge	171:3a7713b1edbc	401
AnnaBridge	171:3a7713b1edbc	402	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
AnnaBridge	171:3a7713b1edbc	403	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
AnnaBridge	171:3a7713b1edbc	404
AnnaBridge	171:3a7713b1edbc	405	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
AnnaBridge	171:3a7713b1edbc	406	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
AnnaBridge	171:3a7713b1edbc	407
AnnaBridge	171:3a7713b1edbc	408	/@} end of group CMSIS_CORE /
AnnaBridge	171:3a7713b1edbc	409
AnnaBridge	171:3a7713b1edbc	410
AnnaBridge	171:3a7713b1edbc	411	/**
AnnaBridge	171:3a7713b1edbc	412	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	413	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge	171:3a7713b1edbc	414	\brief Type definitions for the NVIC Registers
AnnaBridge	171:3a7713b1edbc	415	@{
AnnaBridge	171:3a7713b1edbc	416	*/
AnnaBridge	171:3a7713b1edbc	417
AnnaBridge	171:3a7713b1edbc	418	/**
AnnaBridge	171:3a7713b1edbc	419	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge	171:3a7713b1edbc	420	*/
AnnaBridge	171:3a7713b1edbc	421	typedef struct
AnnaBridge	171:3a7713b1edbc	422	{
AnnaBridge	171:3a7713b1edbc	423	__IOM uint32_t ISER[8U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
AnnaBridge	171:3a7713b1edbc	424	uint32_t RESERVED0[24U];
AnnaBridge	171:3a7713b1edbc	425	__IOM uint32_t ICER[8U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
AnnaBridge	171:3a7713b1edbc	426	uint32_t RSERVED1[24U];
AnnaBridge	171:3a7713b1edbc	427	__IOM uint32_t ISPR[8U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
AnnaBridge	171:3a7713b1edbc	428	uint32_t RESERVED2[24U];
AnnaBridge	171:3a7713b1edbc	429	__IOM uint32_t ICPR[8U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
AnnaBridge	171:3a7713b1edbc	430	uint32_t RESERVED3[24U];
AnnaBridge	171:3a7713b1edbc	431	__IOM uint32_t IABR[8U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
AnnaBridge	171:3a7713b1edbc	432	uint32_t RESERVED4[56U];
AnnaBridge	171:3a7713b1edbc	433	__IOM uint8_t IP[240U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
AnnaBridge	171:3a7713b1edbc	434	uint32_t RESERVED5[644U];
AnnaBridge	171:3a7713b1edbc	435	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
AnnaBridge	171:3a7713b1edbc	436	} NVIC_Type;
AnnaBridge	171:3a7713b1edbc	437
AnnaBridge	171:3a7713b1edbc	438	/* Software Triggered Interrupt Register Definitions */
AnnaBridge	171:3a7713b1edbc	439	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
AnnaBridge	171:3a7713b1edbc	440	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
AnnaBridge	171:3a7713b1edbc	441
AnnaBridge	171:3a7713b1edbc	442	/@} end of group CMSIS_NVIC /
AnnaBridge	171:3a7713b1edbc	443
AnnaBridge	171:3a7713b1edbc	444
AnnaBridge	171:3a7713b1edbc	445	/**
AnnaBridge	171:3a7713b1edbc	446	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	447	\defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge	171:3a7713b1edbc	448	\brief Type definitions for the System Control Block Registers
AnnaBridge	171:3a7713b1edbc	449	@{
AnnaBridge	171:3a7713b1edbc	450	*/
AnnaBridge	171:3a7713b1edbc	451
AnnaBridge	171:3a7713b1edbc	452	/**
AnnaBridge	171:3a7713b1edbc	453	\brief Structure type to access the System Control Block (SCB).
AnnaBridge	171:3a7713b1edbc	454	*/
AnnaBridge	171:3a7713b1edbc	455	typedef struct
AnnaBridge	171:3a7713b1edbc	456	{
AnnaBridge	171:3a7713b1edbc	457	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
AnnaBridge	171:3a7713b1edbc	458	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
AnnaBridge	171:3a7713b1edbc	459	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
AnnaBridge	171:3a7713b1edbc	460	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
AnnaBridge	171:3a7713b1edbc	461	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
AnnaBridge	171:3a7713b1edbc	462	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
AnnaBridge	171:3a7713b1edbc	463	__IOM uint8_t SHPR[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
AnnaBridge	171:3a7713b1edbc	464	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
AnnaBridge	171:3a7713b1edbc	465	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
AnnaBridge	171:3a7713b1edbc	466	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
AnnaBridge	171:3a7713b1edbc	467	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
AnnaBridge	171:3a7713b1edbc	468	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
AnnaBridge	171:3a7713b1edbc	469	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
AnnaBridge	171:3a7713b1edbc	470	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
AnnaBridge	171:3a7713b1edbc	471	__IM uint32_t ID_PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
AnnaBridge	171:3a7713b1edbc	472	__IM uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
AnnaBridge	171:3a7713b1edbc	473	__IM uint32_t ID_AFR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
AnnaBridge	171:3a7713b1edbc	474	__IM uint32_t ID_MFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
AnnaBridge	171:3a7713b1edbc	475	__IM uint32_t ID_ISAR[5U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
AnnaBridge	171:3a7713b1edbc	476	uint32_t RESERVED0[1U];
AnnaBridge	171:3a7713b1edbc	477	__IM uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
AnnaBridge	171:3a7713b1edbc	478	__IM uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
AnnaBridge	171:3a7713b1edbc	479	__IM uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
AnnaBridge	171:3a7713b1edbc	480	__IOM uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
AnnaBridge	171:3a7713b1edbc	481	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
AnnaBridge	171:3a7713b1edbc	482	uint32_t RESERVED3[93U];
AnnaBridge	171:3a7713b1edbc	483	__OM uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
AnnaBridge	171:3a7713b1edbc	484	uint32_t RESERVED4[15U];
AnnaBridge	171:3a7713b1edbc	485	__IM uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
AnnaBridge	171:3a7713b1edbc	486	__IM uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
AnnaBridge	171:3a7713b1edbc	487	__IM uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 /
AnnaBridge	171:3a7713b1edbc	488	uint32_t RESERVED5[1U];
AnnaBridge	171:3a7713b1edbc	489	__OM uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
AnnaBridge	171:3a7713b1edbc	490	uint32_t RESERVED6[1U];
AnnaBridge	171:3a7713b1edbc	491	__OM uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
AnnaBridge	171:3a7713b1edbc	492	__OM uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
AnnaBridge	171:3a7713b1edbc	493	__OM uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
AnnaBridge	171:3a7713b1edbc	494	__OM uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
AnnaBridge	171:3a7713b1edbc	495	__OM uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
AnnaBridge	171:3a7713b1edbc	496	__OM uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
AnnaBridge	171:3a7713b1edbc	497	__OM uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
AnnaBridge	171:3a7713b1edbc	498	__OM uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
AnnaBridge	171:3a7713b1edbc	499	uint32_t RESERVED7[6U];
AnnaBridge	171:3a7713b1edbc	500	__IOM uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
AnnaBridge	171:3a7713b1edbc	501	__IOM uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
AnnaBridge	171:3a7713b1edbc	502	__IOM uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
AnnaBridge	171:3a7713b1edbc	503	__IOM uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
AnnaBridge	171:3a7713b1edbc	504	__IOM uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
AnnaBridge	171:3a7713b1edbc	505	uint32_t RESERVED8[1U];
AnnaBridge	171:3a7713b1edbc	506	__IOM uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
AnnaBridge	171:3a7713b1edbc	507	} SCB_Type;
AnnaBridge	171:3a7713b1edbc	508
AnnaBridge	171:3a7713b1edbc	509	/* SCB CPUID Register Definitions */
AnnaBridge	171:3a7713b1edbc	510	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
AnnaBridge	171:3a7713b1edbc	511	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
AnnaBridge	171:3a7713b1edbc	512
AnnaBridge	171:3a7713b1edbc	513	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
AnnaBridge	171:3a7713b1edbc	514	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
AnnaBridge	171:3a7713b1edbc	515
AnnaBridge	171:3a7713b1edbc	516	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
AnnaBridge	171:3a7713b1edbc	517	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
AnnaBridge	171:3a7713b1edbc	518
AnnaBridge	171:3a7713b1edbc	519	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
AnnaBridge	171:3a7713b1edbc	520	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
AnnaBridge	171:3a7713b1edbc	521
AnnaBridge	171:3a7713b1edbc	522	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
AnnaBridge	171:3a7713b1edbc	523	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
AnnaBridge	171:3a7713b1edbc	524
AnnaBridge	171:3a7713b1edbc	525	/* SCB Interrupt Control State Register Definitions */
AnnaBridge	171:3a7713b1edbc	526	#define SCB_ICSR_NMIPENDSET_Pos 31U /!< SCB ICSR: NMIPENDSET Position /
AnnaBridge	171:3a7713b1edbc	527	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
AnnaBridge	171:3a7713b1edbc	528
AnnaBridge	171:3a7713b1edbc	529	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
AnnaBridge	171:3a7713b1edbc	530	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
AnnaBridge	171:3a7713b1edbc	531
AnnaBridge	171:3a7713b1edbc	532	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
AnnaBridge	171:3a7713b1edbc	533	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
AnnaBridge	171:3a7713b1edbc	534
AnnaBridge	171:3a7713b1edbc	535	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
AnnaBridge	171:3a7713b1edbc	536	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
AnnaBridge	171:3a7713b1edbc	537
AnnaBridge	171:3a7713b1edbc	538	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
AnnaBridge	171:3a7713b1edbc	539	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
AnnaBridge	171:3a7713b1edbc	540
AnnaBridge	171:3a7713b1edbc	541	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
AnnaBridge	171:3a7713b1edbc	542	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
AnnaBridge	171:3a7713b1edbc	543
AnnaBridge	171:3a7713b1edbc	544	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
AnnaBridge	171:3a7713b1edbc	545	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
AnnaBridge	171:3a7713b1edbc	546
AnnaBridge	171:3a7713b1edbc	547	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
AnnaBridge	171:3a7713b1edbc	548	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
AnnaBridge	171:3a7713b1edbc	549
AnnaBridge	171:3a7713b1edbc	550	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
AnnaBridge	171:3a7713b1edbc	551	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
AnnaBridge	171:3a7713b1edbc	552
AnnaBridge	171:3a7713b1edbc	553	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
AnnaBridge	171:3a7713b1edbc	554	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
AnnaBridge	171:3a7713b1edbc	555
AnnaBridge	171:3a7713b1edbc	556	/* SCB Vector Table Offset Register Definitions */
AnnaBridge	171:3a7713b1edbc	557	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
AnnaBridge	171:3a7713b1edbc	558	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
AnnaBridge	171:3a7713b1edbc	559
AnnaBridge	171:3a7713b1edbc	560	/* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	561	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
AnnaBridge	171:3a7713b1edbc	562	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
AnnaBridge	171:3a7713b1edbc	563
AnnaBridge	171:3a7713b1edbc	564	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
AnnaBridge	171:3a7713b1edbc	565	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
AnnaBridge	171:3a7713b1edbc	566
AnnaBridge	171:3a7713b1edbc	567	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
AnnaBridge	171:3a7713b1edbc	568	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
AnnaBridge	171:3a7713b1edbc	569
AnnaBridge	171:3a7713b1edbc	570	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
AnnaBridge	171:3a7713b1edbc	571	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
AnnaBridge	171:3a7713b1edbc	572
AnnaBridge	171:3a7713b1edbc	573	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
AnnaBridge	171:3a7713b1edbc	574	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
AnnaBridge	171:3a7713b1edbc	575
AnnaBridge	171:3a7713b1edbc	576	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
AnnaBridge	171:3a7713b1edbc	577	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
AnnaBridge	171:3a7713b1edbc	578
AnnaBridge	171:3a7713b1edbc	579	#define SCB_AIRCR_VECTRESET_Pos 0U /!< SCB AIRCR: VECTRESET Position /
AnnaBridge	171:3a7713b1edbc	580	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
AnnaBridge	171:3a7713b1edbc	581
AnnaBridge	171:3a7713b1edbc	582	/* SCB System Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	583	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
AnnaBridge	171:3a7713b1edbc	584	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
AnnaBridge	171:3a7713b1edbc	585
AnnaBridge	171:3a7713b1edbc	586	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
AnnaBridge	171:3a7713b1edbc	587	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
AnnaBridge	171:3a7713b1edbc	588
AnnaBridge	171:3a7713b1edbc	589	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
AnnaBridge	171:3a7713b1edbc	590	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
AnnaBridge	171:3a7713b1edbc	591
AnnaBridge	171:3a7713b1edbc	592	/* SCB Configuration Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	593	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: Branch prediction enable bit Position /
AnnaBridge	171:3a7713b1edbc	594	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: Branch prediction enable bit Mask /
AnnaBridge	171:3a7713b1edbc	595
AnnaBridge	171:3a7713b1edbc	596	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: Instruction cache enable bit Position /
AnnaBridge	171:3a7713b1edbc	597	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: Instruction cache enable bit Mask /
AnnaBridge	171:3a7713b1edbc	598
AnnaBridge	171:3a7713b1edbc	599	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: Cache enable bit Position /
AnnaBridge	171:3a7713b1edbc	600	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: Cache enable bit Mask /
AnnaBridge	171:3a7713b1edbc	601
AnnaBridge	171:3a7713b1edbc	602	#define SCB_CCR_STKALIGN_Pos 9U /!< SCB CCR: STKALIGN Position /
AnnaBridge	171:3a7713b1edbc	603	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
AnnaBridge	171:3a7713b1edbc	604
AnnaBridge	171:3a7713b1edbc	605	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
AnnaBridge	171:3a7713b1edbc	606	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
AnnaBridge	171:3a7713b1edbc	607
AnnaBridge	171:3a7713b1edbc	608	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
AnnaBridge	171:3a7713b1edbc	609	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
AnnaBridge	171:3a7713b1edbc	610
AnnaBridge	171:3a7713b1edbc	611	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
AnnaBridge	171:3a7713b1edbc	612	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
AnnaBridge	171:3a7713b1edbc	613
AnnaBridge	171:3a7713b1edbc	614	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
AnnaBridge	171:3a7713b1edbc	615	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
AnnaBridge	171:3a7713b1edbc	616
AnnaBridge	171:3a7713b1edbc	617	#define SCB_CCR_NONBASETHRDENA_Pos 0U /!< SCB CCR: NONBASETHRDENA Position /
AnnaBridge	171:3a7713b1edbc	618	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
AnnaBridge	171:3a7713b1edbc	619
AnnaBridge	171:3a7713b1edbc	620	/* SCB System Handler Control and State Register Definitions */
AnnaBridge	171:3a7713b1edbc	621	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
AnnaBridge	171:3a7713b1edbc	622	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
AnnaBridge	171:3a7713b1edbc	623
AnnaBridge	171:3a7713b1edbc	624	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
AnnaBridge	171:3a7713b1edbc	625	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
AnnaBridge	171:3a7713b1edbc	626
AnnaBridge	171:3a7713b1edbc	627	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
AnnaBridge	171:3a7713b1edbc	628	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
AnnaBridge	171:3a7713b1edbc	629
AnnaBridge	171:3a7713b1edbc	630	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
AnnaBridge	171:3a7713b1edbc	631	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
AnnaBridge	171:3a7713b1edbc	632
AnnaBridge	171:3a7713b1edbc	633	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
AnnaBridge	171:3a7713b1edbc	634	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
AnnaBridge	171:3a7713b1edbc	635
AnnaBridge	171:3a7713b1edbc	636	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
AnnaBridge	171:3a7713b1edbc	637	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
AnnaBridge	171:3a7713b1edbc	638
AnnaBridge	171:3a7713b1edbc	639	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
AnnaBridge	171:3a7713b1edbc	640	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
AnnaBridge	171:3a7713b1edbc	641
AnnaBridge	171:3a7713b1edbc	642	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
AnnaBridge	171:3a7713b1edbc	643	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
AnnaBridge	171:3a7713b1edbc	644
AnnaBridge	171:3a7713b1edbc	645	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
AnnaBridge	171:3a7713b1edbc	646	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
AnnaBridge	171:3a7713b1edbc	647
AnnaBridge	171:3a7713b1edbc	648	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
AnnaBridge	171:3a7713b1edbc	649	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
AnnaBridge	171:3a7713b1edbc	650
AnnaBridge	171:3a7713b1edbc	651	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
AnnaBridge	171:3a7713b1edbc	652	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
AnnaBridge	171:3a7713b1edbc	653
AnnaBridge	171:3a7713b1edbc	654	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
AnnaBridge	171:3a7713b1edbc	655	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
AnnaBridge	171:3a7713b1edbc	656
AnnaBridge	171:3a7713b1edbc	657	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
AnnaBridge	171:3a7713b1edbc	658	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
AnnaBridge	171:3a7713b1edbc	659
AnnaBridge	171:3a7713b1edbc	660	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
AnnaBridge	171:3a7713b1edbc	661	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
AnnaBridge	171:3a7713b1edbc	662
AnnaBridge	171:3a7713b1edbc	663	/* SCB Configurable Fault Status Register Definitions */
AnnaBridge	171:3a7713b1edbc	664	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
AnnaBridge	171:3a7713b1edbc	665	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
AnnaBridge	171:3a7713b1edbc	666
AnnaBridge	171:3a7713b1edbc	667	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
AnnaBridge	171:3a7713b1edbc	668	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
AnnaBridge	171:3a7713b1edbc	669
AnnaBridge	171:3a7713b1edbc	670	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
AnnaBridge	171:3a7713b1edbc	671	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
AnnaBridge	171:3a7713b1edbc	672
AnnaBridge	171:3a7713b1edbc	673	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	171:3a7713b1edbc	674	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
AnnaBridge	171:3a7713b1edbc	675	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
AnnaBridge	171:3a7713b1edbc	676
AnnaBridge	171:3a7713b1edbc	677	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
AnnaBridge	171:3a7713b1edbc	678	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
AnnaBridge	171:3a7713b1edbc	679
AnnaBridge	171:3a7713b1edbc	680	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
AnnaBridge	171:3a7713b1edbc	681	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
AnnaBridge	171:3a7713b1edbc	682
AnnaBridge	171:3a7713b1edbc	683	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
AnnaBridge	171:3a7713b1edbc	684	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
AnnaBridge	171:3a7713b1edbc	685
AnnaBridge	171:3a7713b1edbc	686	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
AnnaBridge	171:3a7713b1edbc	687	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
AnnaBridge	171:3a7713b1edbc	688
AnnaBridge	171:3a7713b1edbc	689	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
AnnaBridge	171:3a7713b1edbc	690	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
AnnaBridge	171:3a7713b1edbc	691
AnnaBridge	171:3a7713b1edbc	692	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	171:3a7713b1edbc	693	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
AnnaBridge	171:3a7713b1edbc	694	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
AnnaBridge	171:3a7713b1edbc	695
AnnaBridge	171:3a7713b1edbc	696	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
AnnaBridge	171:3a7713b1edbc	697	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
AnnaBridge	171:3a7713b1edbc	698
AnnaBridge	171:3a7713b1edbc	699	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
AnnaBridge	171:3a7713b1edbc	700	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
AnnaBridge	171:3a7713b1edbc	701
AnnaBridge	171:3a7713b1edbc	702	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
AnnaBridge	171:3a7713b1edbc	703	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
AnnaBridge	171:3a7713b1edbc	704
AnnaBridge	171:3a7713b1edbc	705	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
AnnaBridge	171:3a7713b1edbc	706	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
AnnaBridge	171:3a7713b1edbc	707
AnnaBridge	171:3a7713b1edbc	708	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
AnnaBridge	171:3a7713b1edbc	709	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
AnnaBridge	171:3a7713b1edbc	710
AnnaBridge	171:3a7713b1edbc	711	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
AnnaBridge	171:3a7713b1edbc	712	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
AnnaBridge	171:3a7713b1edbc	713
AnnaBridge	171:3a7713b1edbc	714	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	171:3a7713b1edbc	715	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
AnnaBridge	171:3a7713b1edbc	716	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
AnnaBridge	171:3a7713b1edbc	717
AnnaBridge	171:3a7713b1edbc	718	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
AnnaBridge	171:3a7713b1edbc	719	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
AnnaBridge	171:3a7713b1edbc	720
AnnaBridge	171:3a7713b1edbc	721	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
AnnaBridge	171:3a7713b1edbc	722	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
AnnaBridge	171:3a7713b1edbc	723
AnnaBridge	171:3a7713b1edbc	724	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
AnnaBridge	171:3a7713b1edbc	725	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
AnnaBridge	171:3a7713b1edbc	726
AnnaBridge	171:3a7713b1edbc	727	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
AnnaBridge	171:3a7713b1edbc	728	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
AnnaBridge	171:3a7713b1edbc	729
AnnaBridge	171:3a7713b1edbc	730	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
AnnaBridge	171:3a7713b1edbc	731	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
AnnaBridge	171:3a7713b1edbc	732
AnnaBridge	171:3a7713b1edbc	733	/* SCB Hard Fault Status Register Definitions */
AnnaBridge	171:3a7713b1edbc	734	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
AnnaBridge	171:3a7713b1edbc	735	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
AnnaBridge	171:3a7713b1edbc	736
AnnaBridge	171:3a7713b1edbc	737	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
AnnaBridge	171:3a7713b1edbc	738	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
AnnaBridge	171:3a7713b1edbc	739
AnnaBridge	171:3a7713b1edbc	740	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
AnnaBridge	171:3a7713b1edbc	741	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
AnnaBridge	171:3a7713b1edbc	742
AnnaBridge	171:3a7713b1edbc	743	/* SCB Debug Fault Status Register Definitions */
AnnaBridge	171:3a7713b1edbc	744	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
AnnaBridge	171:3a7713b1edbc	745	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
AnnaBridge	171:3a7713b1edbc	746
AnnaBridge	171:3a7713b1edbc	747	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
AnnaBridge	171:3a7713b1edbc	748	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
AnnaBridge	171:3a7713b1edbc	749
AnnaBridge	171:3a7713b1edbc	750	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
AnnaBridge	171:3a7713b1edbc	751	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
AnnaBridge	171:3a7713b1edbc	752
AnnaBridge	171:3a7713b1edbc	753	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
AnnaBridge	171:3a7713b1edbc	754	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
AnnaBridge	171:3a7713b1edbc	755
AnnaBridge	171:3a7713b1edbc	756	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
AnnaBridge	171:3a7713b1edbc	757	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
AnnaBridge	171:3a7713b1edbc	758
AnnaBridge	171:3a7713b1edbc	759	/* SCB Cache Level ID Register Definitions */
AnnaBridge	171:3a7713b1edbc	760	#define SCB_CLIDR_LOUU_Pos 27U /!< SCB CLIDR: LoUU Position /
AnnaBridge	171:3a7713b1edbc	761	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
AnnaBridge	171:3a7713b1edbc	762
AnnaBridge	171:3a7713b1edbc	763	#define SCB_CLIDR_LOC_Pos 24U /!< SCB CLIDR: LoC Position /
AnnaBridge	171:3a7713b1edbc	764	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /!< SCB CLIDR: LoC Mask /
AnnaBridge	171:3a7713b1edbc	765
AnnaBridge	171:3a7713b1edbc	766	/* SCB Cache Type Register Definitions */
AnnaBridge	171:3a7713b1edbc	767	#define SCB_CTR_FORMAT_Pos 29U /!< SCB CTR: Format Position /
AnnaBridge	171:3a7713b1edbc	768	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
AnnaBridge	171:3a7713b1edbc	769
AnnaBridge	171:3a7713b1edbc	770	#define SCB_CTR_CWG_Pos 24U /!< SCB CTR: CWG Position /
AnnaBridge	171:3a7713b1edbc	771	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
AnnaBridge	171:3a7713b1edbc	772
AnnaBridge	171:3a7713b1edbc	773	#define SCB_CTR_ERG_Pos 20U /!< SCB CTR: ERG Position /
AnnaBridge	171:3a7713b1edbc	774	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
AnnaBridge	171:3a7713b1edbc	775
AnnaBridge	171:3a7713b1edbc	776	#define SCB_CTR_DMINLINE_Pos 16U /!< SCB CTR: DminLine Position /
AnnaBridge	171:3a7713b1edbc	777	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
AnnaBridge	171:3a7713b1edbc	778
AnnaBridge	171:3a7713b1edbc	779	#define SCB_CTR_IMINLINE_Pos 0U /!< SCB CTR: ImInLine Position /
AnnaBridge	171:3a7713b1edbc	780	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
AnnaBridge	171:3a7713b1edbc	781
AnnaBridge	171:3a7713b1edbc	782	/* SCB Cache Size ID Register Definitions */
AnnaBridge	171:3a7713b1edbc	783	#define SCB_CCSIDR_WT_Pos 31U /!< SCB CCSIDR: WT Position /
AnnaBridge	171:3a7713b1edbc	784	#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
AnnaBridge	171:3a7713b1edbc	785
AnnaBridge	171:3a7713b1edbc	786	#define SCB_CCSIDR_WB_Pos 30U /!< SCB CCSIDR: WB Position /
AnnaBridge	171:3a7713b1edbc	787	#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
AnnaBridge	171:3a7713b1edbc	788
AnnaBridge	171:3a7713b1edbc	789	#define SCB_CCSIDR_RA_Pos 29U /!< SCB CCSIDR: RA Position /
AnnaBridge	171:3a7713b1edbc	790	#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
AnnaBridge	171:3a7713b1edbc	791
AnnaBridge	171:3a7713b1edbc	792	#define SCB_CCSIDR_WA_Pos 28U /!< SCB CCSIDR: WA Position /
AnnaBridge	171:3a7713b1edbc	793	#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
AnnaBridge	171:3a7713b1edbc	794
AnnaBridge	171:3a7713b1edbc	795	#define SCB_CCSIDR_NUMSETS_Pos 13U /!< SCB CCSIDR: NumSets Position /
AnnaBridge	171:3a7713b1edbc	796	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
AnnaBridge	171:3a7713b1edbc	797
AnnaBridge	171:3a7713b1edbc	798	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /!< SCB CCSIDR: Associativity Position /
AnnaBridge	171:3a7713b1edbc	799	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
AnnaBridge	171:3a7713b1edbc	800
AnnaBridge	171:3a7713b1edbc	801	#define SCB_CCSIDR_LINESIZE_Pos 0U /!< SCB CCSIDR: LineSize Position /
AnnaBridge	171:3a7713b1edbc	802	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
AnnaBridge	171:3a7713b1edbc	803
AnnaBridge	171:3a7713b1edbc	804	/* SCB Cache Size Selection Register Definitions */
AnnaBridge	171:3a7713b1edbc	805	#define SCB_CSSELR_LEVEL_Pos 1U /!< SCB CSSELR: Level Position /
AnnaBridge	171:3a7713b1edbc	806	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
AnnaBridge	171:3a7713b1edbc	807
AnnaBridge	171:3a7713b1edbc	808	#define SCB_CSSELR_IND_Pos 0U /!< SCB CSSELR: InD Position /
AnnaBridge	171:3a7713b1edbc	809	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
AnnaBridge	171:3a7713b1edbc	810
AnnaBridge	171:3a7713b1edbc	811	/* SCB Software Triggered Interrupt Register Definitions */
AnnaBridge	171:3a7713b1edbc	812	#define SCB_STIR_INTID_Pos 0U /!< SCB STIR: INTID Position /
AnnaBridge	171:3a7713b1edbc	813	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
AnnaBridge	171:3a7713b1edbc	814
AnnaBridge	171:3a7713b1edbc	815	/* SCB D-Cache Invalidate by Set-way Register Definitions */
AnnaBridge	171:3a7713b1edbc	816	#define SCB_DCISW_WAY_Pos 30U /!< SCB DCISW: Way Position /
AnnaBridge	171:3a7713b1edbc	817	#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /!< SCB DCISW: Way Mask /
AnnaBridge	171:3a7713b1edbc	818
AnnaBridge	171:3a7713b1edbc	819	#define SCB_DCISW_SET_Pos 5U /!< SCB DCISW: Set Position /
AnnaBridge	171:3a7713b1edbc	820	#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /!< SCB DCISW: Set Mask /
AnnaBridge	171:3a7713b1edbc	821
AnnaBridge	171:3a7713b1edbc	822	/* SCB D-Cache Clean by Set-way Register Definitions */
AnnaBridge	171:3a7713b1edbc	823	#define SCB_DCCSW_WAY_Pos 30U /!< SCB DCCSW: Way Position /
AnnaBridge	171:3a7713b1edbc	824	#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /!< SCB DCCSW: Way Mask /
AnnaBridge	171:3a7713b1edbc	825
AnnaBridge	171:3a7713b1edbc	826	#define SCB_DCCSW_SET_Pos 5U /!< SCB DCCSW: Set Position /
AnnaBridge	171:3a7713b1edbc	827	#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /!< SCB DCCSW: Set Mask /
AnnaBridge	171:3a7713b1edbc	828
AnnaBridge	171:3a7713b1edbc	829	/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
AnnaBridge	171:3a7713b1edbc	830	#define SCB_DCCISW_WAY_Pos 30U /!< SCB DCCISW: Way Position /
AnnaBridge	171:3a7713b1edbc	831	#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /!< SCB DCCISW: Way Mask /
AnnaBridge	171:3a7713b1edbc	832
AnnaBridge	171:3a7713b1edbc	833	#define SCB_DCCISW_SET_Pos 5U /!< SCB DCCISW: Set Position /
AnnaBridge	171:3a7713b1edbc	834	#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /!< SCB DCCISW: Set Mask /
AnnaBridge	171:3a7713b1edbc	835
AnnaBridge	171:3a7713b1edbc	836	/* Instruction Tightly-Coupled Memory Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	837	#define SCB_ITCMCR_SZ_Pos 3U /!< SCB ITCMCR: SZ Position /
AnnaBridge	171:3a7713b1edbc	838	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
AnnaBridge	171:3a7713b1edbc	839
AnnaBridge	171:3a7713b1edbc	840	#define SCB_ITCMCR_RETEN_Pos 2U /!< SCB ITCMCR: RETEN Position /
AnnaBridge	171:3a7713b1edbc	841	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
AnnaBridge	171:3a7713b1edbc	842
AnnaBridge	171:3a7713b1edbc	843	#define SCB_ITCMCR_RMW_Pos 1U /!< SCB ITCMCR: RMW Position /
AnnaBridge	171:3a7713b1edbc	844	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
AnnaBridge	171:3a7713b1edbc	845
AnnaBridge	171:3a7713b1edbc	846	#define SCB_ITCMCR_EN_Pos 0U /!< SCB ITCMCR: EN Position /
AnnaBridge	171:3a7713b1edbc	847	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
AnnaBridge	171:3a7713b1edbc	848
AnnaBridge	171:3a7713b1edbc	849	/* Data Tightly-Coupled Memory Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	850	#define SCB_DTCMCR_SZ_Pos 3U /!< SCB DTCMCR: SZ Position /
AnnaBridge	171:3a7713b1edbc	851	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
AnnaBridge	171:3a7713b1edbc	852
AnnaBridge	171:3a7713b1edbc	853	#define SCB_DTCMCR_RETEN_Pos 2U /!< SCB DTCMCR: RETEN Position /
AnnaBridge	171:3a7713b1edbc	854	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
AnnaBridge	171:3a7713b1edbc	855
AnnaBridge	171:3a7713b1edbc	856	#define SCB_DTCMCR_RMW_Pos 1U /!< SCB DTCMCR: RMW Position /
AnnaBridge	171:3a7713b1edbc	857	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
AnnaBridge	171:3a7713b1edbc	858
AnnaBridge	171:3a7713b1edbc	859	#define SCB_DTCMCR_EN_Pos 0U /!< SCB DTCMCR: EN Position /
AnnaBridge	171:3a7713b1edbc	860	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
AnnaBridge	171:3a7713b1edbc	861
AnnaBridge	171:3a7713b1edbc	862	/* AHBP Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	863	#define SCB_AHBPCR_SZ_Pos 1U /!< SCB AHBPCR: SZ Position /
AnnaBridge	171:3a7713b1edbc	864	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
AnnaBridge	171:3a7713b1edbc	865
AnnaBridge	171:3a7713b1edbc	866	#define SCB_AHBPCR_EN_Pos 0U /!< SCB AHBPCR: EN Position /
AnnaBridge	171:3a7713b1edbc	867	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
AnnaBridge	171:3a7713b1edbc	868
AnnaBridge	171:3a7713b1edbc	869	/* L1 Cache Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	870	#define SCB_CACR_FORCEWT_Pos 2U /!< SCB CACR: FORCEWT Position /
AnnaBridge	171:3a7713b1edbc	871	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
AnnaBridge	171:3a7713b1edbc	872
AnnaBridge	171:3a7713b1edbc	873	#define SCB_CACR_ECCEN_Pos 1U /!< SCB CACR: ECCEN Position /
AnnaBridge	171:3a7713b1edbc	874	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
AnnaBridge	171:3a7713b1edbc	875
AnnaBridge	171:3a7713b1edbc	876	#define SCB_CACR_SIWT_Pos 0U /!< SCB CACR: SIWT Position /
AnnaBridge	171:3a7713b1edbc	877	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
AnnaBridge	171:3a7713b1edbc	878
AnnaBridge	171:3a7713b1edbc	879	/* AHBS Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	880	#define SCB_AHBSCR_INITCOUNT_Pos 11U /!< SCB AHBSCR: INITCOUNT Position /
AnnaBridge	171:3a7713b1edbc	881	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
AnnaBridge	171:3a7713b1edbc	882
AnnaBridge	171:3a7713b1edbc	883	#define SCB_AHBSCR_TPRI_Pos 2U /!< SCB AHBSCR: TPRI Position /
AnnaBridge	171:3a7713b1edbc	884	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
AnnaBridge	171:3a7713b1edbc	885
AnnaBridge	171:3a7713b1edbc	886	#define SCB_AHBSCR_CTL_Pos 0U /!< SCB AHBSCR: CTL Position/
AnnaBridge	171:3a7713b1edbc	887	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
AnnaBridge	171:3a7713b1edbc	888
AnnaBridge	171:3a7713b1edbc	889	/* Auxiliary Bus Fault Status Register Definitions */
AnnaBridge	171:3a7713b1edbc	890	#define SCB_ABFSR_AXIMTYPE_Pos 8U /!< SCB ABFSR: AXIMTYPE Position/
AnnaBridge	171:3a7713b1edbc	891	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
AnnaBridge	171:3a7713b1edbc	892
AnnaBridge	171:3a7713b1edbc	893	#define SCB_ABFSR_EPPB_Pos 4U /!< SCB ABFSR: EPPB Position/
AnnaBridge	171:3a7713b1edbc	894	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
AnnaBridge	171:3a7713b1edbc	895
AnnaBridge	171:3a7713b1edbc	896	#define SCB_ABFSR_AXIM_Pos 3U /!< SCB ABFSR: AXIM Position/
AnnaBridge	171:3a7713b1edbc	897	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
AnnaBridge	171:3a7713b1edbc	898
AnnaBridge	171:3a7713b1edbc	899	#define SCB_ABFSR_AHBP_Pos 2U /!< SCB ABFSR: AHBP Position/
AnnaBridge	171:3a7713b1edbc	900	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
AnnaBridge	171:3a7713b1edbc	901
AnnaBridge	171:3a7713b1edbc	902	#define SCB_ABFSR_DTCM_Pos 1U /!< SCB ABFSR: DTCM Position/
AnnaBridge	171:3a7713b1edbc	903	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
AnnaBridge	171:3a7713b1edbc	904
AnnaBridge	171:3a7713b1edbc	905	#define SCB_ABFSR_ITCM_Pos 0U /!< SCB ABFSR: ITCM Position/
AnnaBridge	171:3a7713b1edbc	906	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
AnnaBridge	171:3a7713b1edbc	907
AnnaBridge	171:3a7713b1edbc	908	/@} end of group CMSIS_SCB /
AnnaBridge	171:3a7713b1edbc	909
AnnaBridge	171:3a7713b1edbc	910
AnnaBridge	171:3a7713b1edbc	911	/**
AnnaBridge	171:3a7713b1edbc	912	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	913	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge	171:3a7713b1edbc	914	\brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge	171:3a7713b1edbc	915	@{
AnnaBridge	171:3a7713b1edbc	916	*/
AnnaBridge	171:3a7713b1edbc	917
AnnaBridge	171:3a7713b1edbc	918	/**
AnnaBridge	171:3a7713b1edbc	919	\brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge	171:3a7713b1edbc	920	*/
AnnaBridge	171:3a7713b1edbc	921	typedef struct
AnnaBridge	171:3a7713b1edbc	922	{
AnnaBridge	171:3a7713b1edbc	923	uint32_t RESERVED0[1U];
AnnaBridge	171:3a7713b1edbc	924	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
AnnaBridge	171:3a7713b1edbc	925	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
AnnaBridge	171:3a7713b1edbc	926	} SCnSCB_Type;
AnnaBridge	171:3a7713b1edbc	927
AnnaBridge	171:3a7713b1edbc	928	/* Interrupt Controller Type Register Definitions */
AnnaBridge	171:3a7713b1edbc	929	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
AnnaBridge	171:3a7713b1edbc	930	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
AnnaBridge	171:3a7713b1edbc	931
AnnaBridge	171:3a7713b1edbc	932	/* Auxiliary Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	933	#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /!< ACTLR: DISITMATBFLUSH Position /
AnnaBridge	171:3a7713b1edbc	934	#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /!< ACTLR: DISITMATBFLUSH Mask /
AnnaBridge	171:3a7713b1edbc	935
AnnaBridge	171:3a7713b1edbc	936	#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /!< ACTLR: DISRAMODE Position /
AnnaBridge	171:3a7713b1edbc	937	#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /!< ACTLR: DISRAMODE Mask /
AnnaBridge	171:3a7713b1edbc	938
AnnaBridge	171:3a7713b1edbc	939	#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /!< ACTLR: FPEXCODIS Position /
AnnaBridge	171:3a7713b1edbc	940	#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /!< ACTLR: FPEXCODIS Mask /
AnnaBridge	171:3a7713b1edbc	941
AnnaBridge	171:3a7713b1edbc	942	#define SCnSCB_ACTLR_DISFOLD_Pos 2U /!< ACTLR: DISFOLD Position /
AnnaBridge	171:3a7713b1edbc	943	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
AnnaBridge	171:3a7713b1edbc	944
AnnaBridge	171:3a7713b1edbc	945	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /!< ACTLR: DISMCYCINT Position /
AnnaBridge	171:3a7713b1edbc	946	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
AnnaBridge	171:3a7713b1edbc	947
AnnaBridge	171:3a7713b1edbc	948	/@} end of group CMSIS_SCnotSCB /
AnnaBridge	171:3a7713b1edbc	949
AnnaBridge	171:3a7713b1edbc	950
AnnaBridge	171:3a7713b1edbc	951	/**
AnnaBridge	171:3a7713b1edbc	952	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	953	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge	171:3a7713b1edbc	954	\brief Type definitions for the System Timer Registers.
AnnaBridge	171:3a7713b1edbc	955	@{
AnnaBridge	171:3a7713b1edbc	956	*/
AnnaBridge	171:3a7713b1edbc	957
AnnaBridge	171:3a7713b1edbc	958	/**
AnnaBridge	171:3a7713b1edbc	959	\brief Structure type to access the System Timer (SysTick).
AnnaBridge	171:3a7713b1edbc	960	*/
AnnaBridge	171:3a7713b1edbc	961	typedef struct
AnnaBridge	171:3a7713b1edbc	962	{
AnnaBridge	171:3a7713b1edbc	963	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
AnnaBridge	171:3a7713b1edbc	964	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
AnnaBridge	171:3a7713b1edbc	965	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
AnnaBridge	171:3a7713b1edbc	966	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
AnnaBridge	171:3a7713b1edbc	967	} SysTick_Type;
AnnaBridge	171:3a7713b1edbc	968
AnnaBridge	171:3a7713b1edbc	969	/* SysTick Control / Status Register Definitions */
AnnaBridge	171:3a7713b1edbc	970	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
AnnaBridge	171:3a7713b1edbc	971	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
AnnaBridge	171:3a7713b1edbc	972
AnnaBridge	171:3a7713b1edbc	973	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
AnnaBridge	171:3a7713b1edbc	974	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
AnnaBridge	171:3a7713b1edbc	975
AnnaBridge	171:3a7713b1edbc	976	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
AnnaBridge	171:3a7713b1edbc	977	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
AnnaBridge	171:3a7713b1edbc	978
AnnaBridge	171:3a7713b1edbc	979	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
AnnaBridge	171:3a7713b1edbc	980	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
AnnaBridge	171:3a7713b1edbc	981
AnnaBridge	171:3a7713b1edbc	982	/* SysTick Reload Register Definitions */
AnnaBridge	171:3a7713b1edbc	983	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
AnnaBridge	171:3a7713b1edbc	984	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
AnnaBridge	171:3a7713b1edbc	985
AnnaBridge	171:3a7713b1edbc	986	/* SysTick Current Register Definitions */
AnnaBridge	171:3a7713b1edbc	987	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
AnnaBridge	171:3a7713b1edbc	988	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
AnnaBridge	171:3a7713b1edbc	989
AnnaBridge	171:3a7713b1edbc	990	/* SysTick Calibration Register Definitions */
AnnaBridge	171:3a7713b1edbc	991	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
AnnaBridge	171:3a7713b1edbc	992	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
AnnaBridge	171:3a7713b1edbc	993
AnnaBridge	171:3a7713b1edbc	994	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
AnnaBridge	171:3a7713b1edbc	995	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
AnnaBridge	171:3a7713b1edbc	996
AnnaBridge	171:3a7713b1edbc	997	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
AnnaBridge	171:3a7713b1edbc	998	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
AnnaBridge	171:3a7713b1edbc	999
AnnaBridge	171:3a7713b1edbc	1000	/@} end of group CMSIS_SysTick /
AnnaBridge	171:3a7713b1edbc	1001
AnnaBridge	171:3a7713b1edbc	1002
AnnaBridge	171:3a7713b1edbc	1003	/**
AnnaBridge	171:3a7713b1edbc	1004	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	1005	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge	171:3a7713b1edbc	1006	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
AnnaBridge	171:3a7713b1edbc	1007	@{
AnnaBridge	171:3a7713b1edbc	1008	*/
AnnaBridge	171:3a7713b1edbc	1009
AnnaBridge	171:3a7713b1edbc	1010	/**
AnnaBridge	171:3a7713b1edbc	1011	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
AnnaBridge	171:3a7713b1edbc	1012	*/
AnnaBridge	171:3a7713b1edbc	1013	typedef struct
AnnaBridge	171:3a7713b1edbc	1014	{
AnnaBridge	171:3a7713b1edbc	1015	__OM union
AnnaBridge	171:3a7713b1edbc	1016	{
AnnaBridge	171:3a7713b1edbc	1017	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
AnnaBridge	171:3a7713b1edbc	1018	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
AnnaBridge	171:3a7713b1edbc	1019	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
AnnaBridge	171:3a7713b1edbc	1020	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
AnnaBridge	171:3a7713b1edbc	1021	uint32_t RESERVED0[864U];
AnnaBridge	171:3a7713b1edbc	1022	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
AnnaBridge	171:3a7713b1edbc	1023	uint32_t RESERVED1[15U];
AnnaBridge	171:3a7713b1edbc	1024	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
AnnaBridge	171:3a7713b1edbc	1025	uint32_t RESERVED2[15U];
AnnaBridge	171:3a7713b1edbc	1026	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
AnnaBridge	171:3a7713b1edbc	1027	uint32_t RESERVED3[29U];
AnnaBridge	171:3a7713b1edbc	1028	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
AnnaBridge	171:3a7713b1edbc	1029	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
AnnaBridge	171:3a7713b1edbc	1030	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
AnnaBridge	171:3a7713b1edbc	1031	uint32_t RESERVED4[43U];
AnnaBridge	171:3a7713b1edbc	1032	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
AnnaBridge	171:3a7713b1edbc	1033	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
AnnaBridge	171:3a7713b1edbc	1034	uint32_t RESERVED5[6U];
AnnaBridge	171:3a7713b1edbc	1035	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
AnnaBridge	171:3a7713b1edbc	1036	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
AnnaBridge	171:3a7713b1edbc	1037	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
AnnaBridge	171:3a7713b1edbc	1038	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
AnnaBridge	171:3a7713b1edbc	1039	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
AnnaBridge	171:3a7713b1edbc	1040	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
AnnaBridge	171:3a7713b1edbc	1041	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
AnnaBridge	171:3a7713b1edbc	1042	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
AnnaBridge	171:3a7713b1edbc	1043	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
AnnaBridge	171:3a7713b1edbc	1044	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
AnnaBridge	171:3a7713b1edbc	1045	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
AnnaBridge	171:3a7713b1edbc	1046	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
AnnaBridge	171:3a7713b1edbc	1047	} ITM_Type;
AnnaBridge	171:3a7713b1edbc	1048
AnnaBridge	171:3a7713b1edbc	1049	/* ITM Trace Privilege Register Definitions */
AnnaBridge	171:3a7713b1edbc	1050	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
AnnaBridge	171:3a7713b1edbc	1051	#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
AnnaBridge	171:3a7713b1edbc	1052
AnnaBridge	171:3a7713b1edbc	1053	/* ITM Trace Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	1054	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
AnnaBridge	171:3a7713b1edbc	1055	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
AnnaBridge	171:3a7713b1edbc	1056
AnnaBridge	171:3a7713b1edbc	1057	#define ITM_TCR_TraceBusID_Pos 16U /!< ITM TCR: ATBID Position /
AnnaBridge	171:3a7713b1edbc	1058	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
AnnaBridge	171:3a7713b1edbc	1059
AnnaBridge	171:3a7713b1edbc	1060	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
AnnaBridge	171:3a7713b1edbc	1061	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
AnnaBridge	171:3a7713b1edbc	1062
AnnaBridge	171:3a7713b1edbc	1063	#define ITM_TCR_TSPrescale_Pos 8U /!< ITM TCR: TSPrescale Position /
AnnaBridge	171:3a7713b1edbc	1064	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
AnnaBridge	171:3a7713b1edbc	1065
AnnaBridge	171:3a7713b1edbc	1066	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
AnnaBridge	171:3a7713b1edbc	1067	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
AnnaBridge	171:3a7713b1edbc	1068
AnnaBridge	171:3a7713b1edbc	1069	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
AnnaBridge	171:3a7713b1edbc	1070	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
AnnaBridge	171:3a7713b1edbc	1071
AnnaBridge	171:3a7713b1edbc	1072	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
AnnaBridge	171:3a7713b1edbc	1073	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
AnnaBridge	171:3a7713b1edbc	1074
AnnaBridge	171:3a7713b1edbc	1075	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
AnnaBridge	171:3a7713b1edbc	1076	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
AnnaBridge	171:3a7713b1edbc	1077
AnnaBridge	171:3a7713b1edbc	1078	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
AnnaBridge	171:3a7713b1edbc	1079	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
AnnaBridge	171:3a7713b1edbc	1080
AnnaBridge	171:3a7713b1edbc	1081	/* ITM Integration Write Register Definitions */
AnnaBridge	171:3a7713b1edbc	1082	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
AnnaBridge	171:3a7713b1edbc	1083	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
AnnaBridge	171:3a7713b1edbc	1084
AnnaBridge	171:3a7713b1edbc	1085	/* ITM Integration Read Register Definitions */
AnnaBridge	171:3a7713b1edbc	1086	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
AnnaBridge	171:3a7713b1edbc	1087	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
AnnaBridge	171:3a7713b1edbc	1088
AnnaBridge	171:3a7713b1edbc	1089	/* ITM Integration Mode Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	1090	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
AnnaBridge	171:3a7713b1edbc	1091	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
AnnaBridge	171:3a7713b1edbc	1092
AnnaBridge	171:3a7713b1edbc	1093	/* ITM Lock Status Register Definitions */
AnnaBridge	171:3a7713b1edbc	1094	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
AnnaBridge	171:3a7713b1edbc	1095	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
AnnaBridge	171:3a7713b1edbc	1096
AnnaBridge	171:3a7713b1edbc	1097	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
AnnaBridge	171:3a7713b1edbc	1098	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
AnnaBridge	171:3a7713b1edbc	1099
AnnaBridge	171:3a7713b1edbc	1100	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
AnnaBridge	171:3a7713b1edbc	1101	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
AnnaBridge	171:3a7713b1edbc	1102
AnnaBridge	171:3a7713b1edbc	1103	/@}/ /* end of group CMSIS_ITM */
AnnaBridge	171:3a7713b1edbc	1104
AnnaBridge	171:3a7713b1edbc	1105
AnnaBridge	171:3a7713b1edbc	1106	/**
AnnaBridge	171:3a7713b1edbc	1107	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	1108	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge	171:3a7713b1edbc	1109	\brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge	171:3a7713b1edbc	1110	@{
AnnaBridge	171:3a7713b1edbc	1111	*/
AnnaBridge	171:3a7713b1edbc	1112
AnnaBridge	171:3a7713b1edbc	1113	/**
AnnaBridge	171:3a7713b1edbc	1114	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge	171:3a7713b1edbc	1115	*/
AnnaBridge	171:3a7713b1edbc	1116	typedef struct
AnnaBridge	171:3a7713b1edbc	1117	{
AnnaBridge	171:3a7713b1edbc	1118	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
AnnaBridge	171:3a7713b1edbc	1119	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
AnnaBridge	171:3a7713b1edbc	1120	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
AnnaBridge	171:3a7713b1edbc	1121	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
AnnaBridge	171:3a7713b1edbc	1122	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
AnnaBridge	171:3a7713b1edbc	1123	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
AnnaBridge	171:3a7713b1edbc	1124	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
AnnaBridge	171:3a7713b1edbc	1125	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
AnnaBridge	171:3a7713b1edbc	1126	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
AnnaBridge	171:3a7713b1edbc	1127	__IOM uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
AnnaBridge	171:3a7713b1edbc	1128	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
AnnaBridge	171:3a7713b1edbc	1129	uint32_t RESERVED0[1U];
AnnaBridge	171:3a7713b1edbc	1130	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
AnnaBridge	171:3a7713b1edbc	1131	__IOM uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
AnnaBridge	171:3a7713b1edbc	1132	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
AnnaBridge	171:3a7713b1edbc	1133	uint32_t RESERVED1[1U];
AnnaBridge	171:3a7713b1edbc	1134	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
AnnaBridge	171:3a7713b1edbc	1135	__IOM uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
AnnaBridge	171:3a7713b1edbc	1136	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
AnnaBridge	171:3a7713b1edbc	1137	uint32_t RESERVED2[1U];
AnnaBridge	171:3a7713b1edbc	1138	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
AnnaBridge	171:3a7713b1edbc	1139	__IOM uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
AnnaBridge	171:3a7713b1edbc	1140	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
AnnaBridge	171:3a7713b1edbc	1141	uint32_t RESERVED3[981U];
AnnaBridge	171:3a7713b1edbc	1142	__OM uint32_t LAR; /!< Offset: 0xFB0 ( W) Lock Access Register /
AnnaBridge	171:3a7713b1edbc	1143	__IM uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
AnnaBridge	171:3a7713b1edbc	1144	} DWT_Type;
AnnaBridge	171:3a7713b1edbc	1145
AnnaBridge	171:3a7713b1edbc	1146	/* DWT Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	1147	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
AnnaBridge	171:3a7713b1edbc	1148	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
AnnaBridge	171:3a7713b1edbc	1149
AnnaBridge	171:3a7713b1edbc	1150	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
AnnaBridge	171:3a7713b1edbc	1151	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
AnnaBridge	171:3a7713b1edbc	1152
AnnaBridge	171:3a7713b1edbc	1153	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
AnnaBridge	171:3a7713b1edbc	1154	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
AnnaBridge	171:3a7713b1edbc	1155
AnnaBridge	171:3a7713b1edbc	1156	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
AnnaBridge	171:3a7713b1edbc	1157	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
AnnaBridge	171:3a7713b1edbc	1158
AnnaBridge	171:3a7713b1edbc	1159	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
AnnaBridge	171:3a7713b1edbc	1160	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
AnnaBridge	171:3a7713b1edbc	1161
AnnaBridge	171:3a7713b1edbc	1162	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
AnnaBridge	171:3a7713b1edbc	1163	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
AnnaBridge	171:3a7713b1edbc	1164
AnnaBridge	171:3a7713b1edbc	1165	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
AnnaBridge	171:3a7713b1edbc	1166	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
AnnaBridge	171:3a7713b1edbc	1167
AnnaBridge	171:3a7713b1edbc	1168	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
AnnaBridge	171:3a7713b1edbc	1169	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
AnnaBridge	171:3a7713b1edbc	1170
AnnaBridge	171:3a7713b1edbc	1171	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
AnnaBridge	171:3a7713b1edbc	1172	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
AnnaBridge	171:3a7713b1edbc	1173
AnnaBridge	171:3a7713b1edbc	1174	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
AnnaBridge	171:3a7713b1edbc	1175	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
AnnaBridge	171:3a7713b1edbc	1176
AnnaBridge	171:3a7713b1edbc	1177	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
AnnaBridge	171:3a7713b1edbc	1178	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
AnnaBridge	171:3a7713b1edbc	1179
AnnaBridge	171:3a7713b1edbc	1180	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
AnnaBridge	171:3a7713b1edbc	1181	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
AnnaBridge	171:3a7713b1edbc	1182
AnnaBridge	171:3a7713b1edbc	1183	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
AnnaBridge	171:3a7713b1edbc	1184	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
AnnaBridge	171:3a7713b1edbc	1185
AnnaBridge	171:3a7713b1edbc	1186	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
AnnaBridge	171:3a7713b1edbc	1187	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
AnnaBridge	171:3a7713b1edbc	1188
AnnaBridge	171:3a7713b1edbc	1189	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
AnnaBridge	171:3a7713b1edbc	1190	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
AnnaBridge	171:3a7713b1edbc	1191
AnnaBridge	171:3a7713b1edbc	1192	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
AnnaBridge	171:3a7713b1edbc	1193	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
AnnaBridge	171:3a7713b1edbc	1194
AnnaBridge	171:3a7713b1edbc	1195	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
AnnaBridge	171:3a7713b1edbc	1196	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
AnnaBridge	171:3a7713b1edbc	1197
AnnaBridge	171:3a7713b1edbc	1198	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
AnnaBridge	171:3a7713b1edbc	1199	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
AnnaBridge	171:3a7713b1edbc	1200
AnnaBridge	171:3a7713b1edbc	1201	/* DWT CPI Count Register Definitions */
AnnaBridge	171:3a7713b1edbc	1202	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
AnnaBridge	171:3a7713b1edbc	1203	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
AnnaBridge	171:3a7713b1edbc	1204
AnnaBridge	171:3a7713b1edbc	1205	/* DWT Exception Overhead Count Register Definitions */
AnnaBridge	171:3a7713b1edbc	1206	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
AnnaBridge	171:3a7713b1edbc	1207	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
AnnaBridge	171:3a7713b1edbc	1208
AnnaBridge	171:3a7713b1edbc	1209	/* DWT Sleep Count Register Definitions */
AnnaBridge	171:3a7713b1edbc	1210	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
AnnaBridge	171:3a7713b1edbc	1211	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
AnnaBridge	171:3a7713b1edbc	1212
AnnaBridge	171:3a7713b1edbc	1213	/* DWT LSU Count Register Definitions */
AnnaBridge	171:3a7713b1edbc	1214	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
AnnaBridge	171:3a7713b1edbc	1215	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
AnnaBridge	171:3a7713b1edbc	1216
AnnaBridge	171:3a7713b1edbc	1217	/* DWT Folded-instruction Count Register Definitions */
AnnaBridge	171:3a7713b1edbc	1218	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
AnnaBridge	171:3a7713b1edbc	1219	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
AnnaBridge	171:3a7713b1edbc	1220
AnnaBridge	171:3a7713b1edbc	1221	/* DWT Comparator Mask Register Definitions */
AnnaBridge	171:3a7713b1edbc	1222	#define DWT_MASK_MASK_Pos 0U /!< DWT MASK: MASK Position /
AnnaBridge	171:3a7713b1edbc	1223	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
AnnaBridge	171:3a7713b1edbc	1224
AnnaBridge	171:3a7713b1edbc	1225	/* DWT Comparator Function Register Definitions */
AnnaBridge	171:3a7713b1edbc	1226	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
AnnaBridge	171:3a7713b1edbc	1227	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
AnnaBridge	171:3a7713b1edbc	1228
AnnaBridge	171:3a7713b1edbc	1229	#define DWT_FUNCTION_DATAVADDR1_Pos 16U /!< DWT FUNCTION: DATAVADDR1 Position /
AnnaBridge	171:3a7713b1edbc	1230	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
AnnaBridge	171:3a7713b1edbc	1231
AnnaBridge	171:3a7713b1edbc	1232	#define DWT_FUNCTION_DATAVADDR0_Pos 12U /!< DWT FUNCTION: DATAVADDR0 Position /
AnnaBridge	171:3a7713b1edbc	1233	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
AnnaBridge	171:3a7713b1edbc	1234
AnnaBridge	171:3a7713b1edbc	1235	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
AnnaBridge	171:3a7713b1edbc	1236	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
AnnaBridge	171:3a7713b1edbc	1237
AnnaBridge	171:3a7713b1edbc	1238	#define DWT_FUNCTION_LNK1ENA_Pos 9U /!< DWT FUNCTION: LNK1ENA Position /
AnnaBridge	171:3a7713b1edbc	1239	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
AnnaBridge	171:3a7713b1edbc	1240
AnnaBridge	171:3a7713b1edbc	1241	#define DWT_FUNCTION_DATAVMATCH_Pos 8U /!< DWT FUNCTION: DATAVMATCH Position /
AnnaBridge	171:3a7713b1edbc	1242	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
AnnaBridge	171:3a7713b1edbc	1243
AnnaBridge	171:3a7713b1edbc	1244	#define DWT_FUNCTION_CYCMATCH_Pos 7U /!< DWT FUNCTION: CYCMATCH Position /
AnnaBridge	171:3a7713b1edbc	1245	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
AnnaBridge	171:3a7713b1edbc	1246
AnnaBridge	171:3a7713b1edbc	1247	#define DWT_FUNCTION_EMITRANGE_Pos 5U /!< DWT FUNCTION: EMITRANGE Position /
AnnaBridge	171:3a7713b1edbc	1248	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
AnnaBridge	171:3a7713b1edbc	1249
AnnaBridge	171:3a7713b1edbc	1250	#define DWT_FUNCTION_FUNCTION_Pos 0U /!< DWT FUNCTION: FUNCTION Position /
AnnaBridge	171:3a7713b1edbc	1251	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
AnnaBridge	171:3a7713b1edbc	1252
AnnaBridge	171:3a7713b1edbc	1253	/@}/ /* end of group CMSIS_DWT */
AnnaBridge	171:3a7713b1edbc	1254
AnnaBridge	171:3a7713b1edbc	1255
AnnaBridge	171:3a7713b1edbc	1256	/**
AnnaBridge	171:3a7713b1edbc	1257	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	1258	\defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge	171:3a7713b1edbc	1259	\brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge	171:3a7713b1edbc	1260	@{
AnnaBridge	171:3a7713b1edbc	1261	*/
AnnaBridge	171:3a7713b1edbc	1262
AnnaBridge	171:3a7713b1edbc	1263	/**
AnnaBridge	171:3a7713b1edbc	1264	\brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge	171:3a7713b1edbc	1265	*/
AnnaBridge	171:3a7713b1edbc	1266	typedef struct
AnnaBridge	171:3a7713b1edbc	1267	{
AnnaBridge	171:3a7713b1edbc	1268	__IM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
AnnaBridge	171:3a7713b1edbc	1269	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
AnnaBridge	171:3a7713b1edbc	1270	uint32_t RESERVED0[2U];
AnnaBridge	171:3a7713b1edbc	1271	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
AnnaBridge	171:3a7713b1edbc	1272	uint32_t RESERVED1[55U];
AnnaBridge	171:3a7713b1edbc	1273	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
AnnaBridge	171:3a7713b1edbc	1274	uint32_t RESERVED2[131U];
AnnaBridge	171:3a7713b1edbc	1275	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
AnnaBridge	171:3a7713b1edbc	1276	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
AnnaBridge	171:3a7713b1edbc	1277	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
AnnaBridge	171:3a7713b1edbc	1278	uint32_t RESERVED3[759U];
AnnaBridge	171:3a7713b1edbc	1279	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER Register /
AnnaBridge	171:3a7713b1edbc	1280	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
AnnaBridge	171:3a7713b1edbc	1281	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
AnnaBridge	171:3a7713b1edbc	1282	uint32_t RESERVED4[1U];
AnnaBridge	171:3a7713b1edbc	1283	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
AnnaBridge	171:3a7713b1edbc	1284	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
AnnaBridge	171:3a7713b1edbc	1285	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
AnnaBridge	171:3a7713b1edbc	1286	uint32_t RESERVED5[39U];
AnnaBridge	171:3a7713b1edbc	1287	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
AnnaBridge	171:3a7713b1edbc	1288	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
AnnaBridge	171:3a7713b1edbc	1289	uint32_t RESERVED7[8U];
AnnaBridge	171:3a7713b1edbc	1290	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
AnnaBridge	171:3a7713b1edbc	1291	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
AnnaBridge	171:3a7713b1edbc	1292	} TPI_Type;
AnnaBridge	171:3a7713b1edbc	1293
AnnaBridge	171:3a7713b1edbc	1294	/* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge	171:3a7713b1edbc	1295	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
AnnaBridge	171:3a7713b1edbc	1296	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
AnnaBridge	171:3a7713b1edbc	1297
AnnaBridge	171:3a7713b1edbc	1298	/* TPI Selected Pin Protocol Register Definitions */
AnnaBridge	171:3a7713b1edbc	1299	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
AnnaBridge	171:3a7713b1edbc	1300	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
AnnaBridge	171:3a7713b1edbc	1301
AnnaBridge	171:3a7713b1edbc	1302	/* TPI Formatter and Flush Status Register Definitions */
AnnaBridge	171:3a7713b1edbc	1303	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
AnnaBridge	171:3a7713b1edbc	1304	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
AnnaBridge	171:3a7713b1edbc	1305
AnnaBridge	171:3a7713b1edbc	1306	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
AnnaBridge	171:3a7713b1edbc	1307	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
AnnaBridge	171:3a7713b1edbc	1308
AnnaBridge	171:3a7713b1edbc	1309	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
AnnaBridge	171:3a7713b1edbc	1310	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
AnnaBridge	171:3a7713b1edbc	1311
AnnaBridge	171:3a7713b1edbc	1312	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
AnnaBridge	171:3a7713b1edbc	1313	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
AnnaBridge	171:3a7713b1edbc	1314
AnnaBridge	171:3a7713b1edbc	1315	/* TPI Formatter and Flush Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	1316	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
AnnaBridge	171:3a7713b1edbc	1317	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
AnnaBridge	171:3a7713b1edbc	1318
AnnaBridge	171:3a7713b1edbc	1319	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
AnnaBridge	171:3a7713b1edbc	1320	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
AnnaBridge	171:3a7713b1edbc	1321
AnnaBridge	171:3a7713b1edbc	1322	/* TPI TRIGGER Register Definitions */
AnnaBridge	171:3a7713b1edbc	1323	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
AnnaBridge	171:3a7713b1edbc	1324	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
AnnaBridge	171:3a7713b1edbc	1325
AnnaBridge	171:3a7713b1edbc	1326	/* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge	171:3a7713b1edbc	1327	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
AnnaBridge	171:3a7713b1edbc	1328	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
AnnaBridge	171:3a7713b1edbc	1329
AnnaBridge	171:3a7713b1edbc	1330	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
AnnaBridge	171:3a7713b1edbc	1331	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
AnnaBridge	171:3a7713b1edbc	1332
AnnaBridge	171:3a7713b1edbc	1333	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
AnnaBridge	171:3a7713b1edbc	1334	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
AnnaBridge	171:3a7713b1edbc	1335
AnnaBridge	171:3a7713b1edbc	1336	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
AnnaBridge	171:3a7713b1edbc	1337	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
AnnaBridge	171:3a7713b1edbc	1338
AnnaBridge	171:3a7713b1edbc	1339	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
AnnaBridge	171:3a7713b1edbc	1340	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
AnnaBridge	171:3a7713b1edbc	1341
AnnaBridge	171:3a7713b1edbc	1342	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
AnnaBridge	171:3a7713b1edbc	1343	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
AnnaBridge	171:3a7713b1edbc	1344
AnnaBridge	171:3a7713b1edbc	1345	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
AnnaBridge	171:3a7713b1edbc	1346	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
AnnaBridge	171:3a7713b1edbc	1347
AnnaBridge	171:3a7713b1edbc	1348	/* TPI ITATBCTR2 Register Definitions */
AnnaBridge	171:3a7713b1edbc	1349	#define TPI_ITATBCTR2_ATREADY2_Pos 0U /!< TPI ITATBCTR2: ATREADY2 Position /
AnnaBridge	171:3a7713b1edbc	1350	#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/) /!< TPI ITATBCTR2: ATREADY2 Mask /
AnnaBridge	171:3a7713b1edbc	1351
AnnaBridge	171:3a7713b1edbc	1352	#define TPI_ITATBCTR2_ATREADY1_Pos 0U /!< TPI ITATBCTR2: ATREADY1 Position /
AnnaBridge	171:3a7713b1edbc	1353	#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/) /!< TPI ITATBCTR2: ATREADY1 Mask /
AnnaBridge	171:3a7713b1edbc	1354
AnnaBridge	171:3a7713b1edbc	1355	/* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge	171:3a7713b1edbc	1356	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
AnnaBridge	171:3a7713b1edbc	1357	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
AnnaBridge	171:3a7713b1edbc	1358
AnnaBridge	171:3a7713b1edbc	1359	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
AnnaBridge	171:3a7713b1edbc	1360	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
AnnaBridge	171:3a7713b1edbc	1361
AnnaBridge	171:3a7713b1edbc	1362	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
AnnaBridge	171:3a7713b1edbc	1363	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
AnnaBridge	171:3a7713b1edbc	1364
AnnaBridge	171:3a7713b1edbc	1365	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
AnnaBridge	171:3a7713b1edbc	1366	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
AnnaBridge	171:3a7713b1edbc	1367
AnnaBridge	171:3a7713b1edbc	1368	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
AnnaBridge	171:3a7713b1edbc	1369	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
AnnaBridge	171:3a7713b1edbc	1370
AnnaBridge	171:3a7713b1edbc	1371	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
AnnaBridge	171:3a7713b1edbc	1372	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
AnnaBridge	171:3a7713b1edbc	1373
AnnaBridge	171:3a7713b1edbc	1374	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
AnnaBridge	171:3a7713b1edbc	1375	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
AnnaBridge	171:3a7713b1edbc	1376
AnnaBridge	171:3a7713b1edbc	1377	/* TPI ITATBCTR0 Register Definitions */
AnnaBridge	171:3a7713b1edbc	1378	#define TPI_ITATBCTR0_ATREADY2_Pos 0U /!< TPI ITATBCTR0: ATREADY2 Position /
AnnaBridge	171:3a7713b1edbc	1379	#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/) /!< TPI ITATBCTR0: ATREADY2 Mask /
AnnaBridge	171:3a7713b1edbc	1380
AnnaBridge	171:3a7713b1edbc	1381	#define TPI_ITATBCTR0_ATREADY1_Pos 0U /!< TPI ITATBCTR0: ATREADY1 Position /
AnnaBridge	171:3a7713b1edbc	1382	#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/) /!< TPI ITATBCTR0: ATREADY1 Mask /
AnnaBridge	171:3a7713b1edbc	1383
AnnaBridge	171:3a7713b1edbc	1384	/* TPI Integration Mode Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	1385	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
AnnaBridge	171:3a7713b1edbc	1386	#define TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
AnnaBridge	171:3a7713b1edbc	1387
AnnaBridge	171:3a7713b1edbc	1388	/* TPI DEVID Register Definitions */
AnnaBridge	171:3a7713b1edbc	1389	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
AnnaBridge	171:3a7713b1edbc	1390	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
AnnaBridge	171:3a7713b1edbc	1391
AnnaBridge	171:3a7713b1edbc	1392	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
AnnaBridge	171:3a7713b1edbc	1393	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
AnnaBridge	171:3a7713b1edbc	1394
AnnaBridge	171:3a7713b1edbc	1395	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
AnnaBridge	171:3a7713b1edbc	1396	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
AnnaBridge	171:3a7713b1edbc	1397
AnnaBridge	171:3a7713b1edbc	1398	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
AnnaBridge	171:3a7713b1edbc	1399	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
AnnaBridge	171:3a7713b1edbc	1400
AnnaBridge	171:3a7713b1edbc	1401	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
AnnaBridge	171:3a7713b1edbc	1402	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
AnnaBridge	171:3a7713b1edbc	1403
AnnaBridge	171:3a7713b1edbc	1404	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
AnnaBridge	171:3a7713b1edbc	1405	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
AnnaBridge	171:3a7713b1edbc	1406
AnnaBridge	171:3a7713b1edbc	1407	/* TPI DEVTYPE Register Definitions */
AnnaBridge	171:3a7713b1edbc	1408	#define TPI_DEVTYPE_SubType_Pos 4U /!< TPI DEVTYPE: SubType Position /
AnnaBridge	171:3a7713b1edbc	1409	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
AnnaBridge	171:3a7713b1edbc	1410
AnnaBridge	171:3a7713b1edbc	1411	#define TPI_DEVTYPE_MajorType_Pos 0U /!< TPI DEVTYPE: MajorType Position /
AnnaBridge	171:3a7713b1edbc	1412	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
AnnaBridge	171:3a7713b1edbc	1413
AnnaBridge	171:3a7713b1edbc	1414	/@}/ /* end of group CMSIS_TPI */
AnnaBridge	171:3a7713b1edbc	1415
AnnaBridge	171:3a7713b1edbc	1416
AnnaBridge	171:3a7713b1edbc	1417	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	1418	/**
AnnaBridge	171:3a7713b1edbc	1419	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	1420	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge	171:3a7713b1edbc	1421	\brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge	171:3a7713b1edbc	1422	@{
AnnaBridge	171:3a7713b1edbc	1423	*/
AnnaBridge	171:3a7713b1edbc	1424
AnnaBridge	171:3a7713b1edbc	1425	/**
AnnaBridge	171:3a7713b1edbc	1426	\brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge	171:3a7713b1edbc	1427	*/
AnnaBridge	171:3a7713b1edbc	1428	typedef struct
AnnaBridge	171:3a7713b1edbc	1429	{
AnnaBridge	171:3a7713b1edbc	1430	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
AnnaBridge	171:3a7713b1edbc	1431	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
AnnaBridge	171:3a7713b1edbc	1432	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
AnnaBridge	171:3a7713b1edbc	1433	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
AnnaBridge	171:3a7713b1edbc	1434	__IOM uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
AnnaBridge	171:3a7713b1edbc	1435	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
AnnaBridge	171:3a7713b1edbc	1436	__IOM uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
AnnaBridge	171:3a7713b1edbc	1437	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
AnnaBridge	171:3a7713b1edbc	1438	__IOM uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
AnnaBridge	171:3a7713b1edbc	1439	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
AnnaBridge	171:3a7713b1edbc	1440	__IOM uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
AnnaBridge	171:3a7713b1edbc	1441	} MPU_Type;
AnnaBridge	171:3a7713b1edbc	1442
AnnaBridge	171:3a7713b1edbc	1443	#define MPU_TYPE_RALIASES 4U
AnnaBridge	171:3a7713b1edbc	1444
AnnaBridge	171:3a7713b1edbc	1445	/* MPU Type Register Definitions */
AnnaBridge	171:3a7713b1edbc	1446	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
AnnaBridge	171:3a7713b1edbc	1447	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
AnnaBridge	171:3a7713b1edbc	1448
AnnaBridge	171:3a7713b1edbc	1449	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
AnnaBridge	171:3a7713b1edbc	1450	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
AnnaBridge	171:3a7713b1edbc	1451
AnnaBridge	171:3a7713b1edbc	1452	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
AnnaBridge	171:3a7713b1edbc	1453	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
AnnaBridge	171:3a7713b1edbc	1454
AnnaBridge	171:3a7713b1edbc	1455	/* MPU Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	1456	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
AnnaBridge	171:3a7713b1edbc	1457	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
AnnaBridge	171:3a7713b1edbc	1458
AnnaBridge	171:3a7713b1edbc	1459	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
AnnaBridge	171:3a7713b1edbc	1460	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
AnnaBridge	171:3a7713b1edbc	1461
AnnaBridge	171:3a7713b1edbc	1462	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
AnnaBridge	171:3a7713b1edbc	1463	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
AnnaBridge	171:3a7713b1edbc	1464
AnnaBridge	171:3a7713b1edbc	1465	/* MPU Region Number Register Definitions */
AnnaBridge	171:3a7713b1edbc	1466	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
AnnaBridge	171:3a7713b1edbc	1467	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
AnnaBridge	171:3a7713b1edbc	1468
AnnaBridge	171:3a7713b1edbc	1469	/* MPU Region Base Address Register Definitions */
AnnaBridge	171:3a7713b1edbc	1470	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
AnnaBridge	171:3a7713b1edbc	1471	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
AnnaBridge	171:3a7713b1edbc	1472
AnnaBridge	171:3a7713b1edbc	1473	#define MPU_RBAR_VALID_Pos 4U /!< MPU RBAR: VALID Position /
AnnaBridge	171:3a7713b1edbc	1474	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
AnnaBridge	171:3a7713b1edbc	1475
AnnaBridge	171:3a7713b1edbc	1476	#define MPU_RBAR_REGION_Pos 0U /!< MPU RBAR: REGION Position /
AnnaBridge	171:3a7713b1edbc	1477	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
AnnaBridge	171:3a7713b1edbc	1478
AnnaBridge	171:3a7713b1edbc	1479	/* MPU Region Attribute and Size Register Definitions */
AnnaBridge	171:3a7713b1edbc	1480	#define MPU_RASR_ATTRS_Pos 16U /!< MPU RASR: MPU Region Attribute field Position /
AnnaBridge	171:3a7713b1edbc	1481	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
AnnaBridge	171:3a7713b1edbc	1482
AnnaBridge	171:3a7713b1edbc	1483	#define MPU_RASR_XN_Pos 28U /!< MPU RASR: ATTRS.XN Position /
AnnaBridge	171:3a7713b1edbc	1484	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
AnnaBridge	171:3a7713b1edbc	1485
AnnaBridge	171:3a7713b1edbc	1486	#define MPU_RASR_AP_Pos 24U /!< MPU RASR: ATTRS.AP Position /
AnnaBridge	171:3a7713b1edbc	1487	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
AnnaBridge	171:3a7713b1edbc	1488
AnnaBridge	171:3a7713b1edbc	1489	#define MPU_RASR_TEX_Pos 19U /!< MPU RASR: ATTRS.TEX Position /
AnnaBridge	171:3a7713b1edbc	1490	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
AnnaBridge	171:3a7713b1edbc	1491
AnnaBridge	171:3a7713b1edbc	1492	#define MPU_RASR_S_Pos 18U /!< MPU RASR: ATTRS.S Position /
AnnaBridge	171:3a7713b1edbc	1493	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
AnnaBridge	171:3a7713b1edbc	1494
AnnaBridge	171:3a7713b1edbc	1495	#define MPU_RASR_C_Pos 17U /!< MPU RASR: ATTRS.C Position /
AnnaBridge	171:3a7713b1edbc	1496	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
AnnaBridge	171:3a7713b1edbc	1497
AnnaBridge	171:3a7713b1edbc	1498	#define MPU_RASR_B_Pos 16U /!< MPU RASR: ATTRS.B Position /
AnnaBridge	171:3a7713b1edbc	1499	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
AnnaBridge	171:3a7713b1edbc	1500
AnnaBridge	171:3a7713b1edbc	1501	#define MPU_RASR_SRD_Pos 8U /!< MPU RASR: Sub-Region Disable Position /
AnnaBridge	171:3a7713b1edbc	1502	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
AnnaBridge	171:3a7713b1edbc	1503
AnnaBridge	171:3a7713b1edbc	1504	#define MPU_RASR_SIZE_Pos 1U /!< MPU RASR: Region Size Field Position /
AnnaBridge	171:3a7713b1edbc	1505	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
AnnaBridge	171:3a7713b1edbc	1506
AnnaBridge	171:3a7713b1edbc	1507	#define MPU_RASR_ENABLE_Pos 0U /!< MPU RASR: Region enable bit Position /
AnnaBridge	171:3a7713b1edbc	1508	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
AnnaBridge	171:3a7713b1edbc	1509
AnnaBridge	171:3a7713b1edbc	1510	/@} end of group CMSIS_MPU /
AnnaBridge	171:3a7713b1edbc	1511	#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
AnnaBridge	171:3a7713b1edbc	1512
AnnaBridge	171:3a7713b1edbc	1513
AnnaBridge	171:3a7713b1edbc	1514	/**
AnnaBridge	171:3a7713b1edbc	1515	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	1516	\defgroup CMSIS_FPU Floating Point Unit (FPU)
AnnaBridge	171:3a7713b1edbc	1517	\brief Type definitions for the Floating Point Unit (FPU)
AnnaBridge	171:3a7713b1edbc	1518	@{
AnnaBridge	171:3a7713b1edbc	1519	*/
AnnaBridge	171:3a7713b1edbc	1520
AnnaBridge	171:3a7713b1edbc	1521	/**
AnnaBridge	171:3a7713b1edbc	1522	\brief Structure type to access the Floating Point Unit (FPU).
AnnaBridge	171:3a7713b1edbc	1523	*/
AnnaBridge	171:3a7713b1edbc	1524	typedef struct
AnnaBridge	171:3a7713b1edbc	1525	{
AnnaBridge	171:3a7713b1edbc	1526	uint32_t RESERVED0[1U];
AnnaBridge	171:3a7713b1edbc	1527	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
AnnaBridge	171:3a7713b1edbc	1528	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
AnnaBridge	171:3a7713b1edbc	1529	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
AnnaBridge	171:3a7713b1edbc	1530	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
AnnaBridge	171:3a7713b1edbc	1531	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
AnnaBridge	171:3a7713b1edbc	1532	__IM uint32_t MVFR2; /!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 /
AnnaBridge	171:3a7713b1edbc	1533	} FPU_Type;
AnnaBridge	171:3a7713b1edbc	1534
AnnaBridge	171:3a7713b1edbc	1535	/* Floating-Point Context Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	1536	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
AnnaBridge	171:3a7713b1edbc	1537	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
AnnaBridge	171:3a7713b1edbc	1538
AnnaBridge	171:3a7713b1edbc	1539	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
AnnaBridge	171:3a7713b1edbc	1540	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
AnnaBridge	171:3a7713b1edbc	1541
AnnaBridge	171:3a7713b1edbc	1542	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
AnnaBridge	171:3a7713b1edbc	1543	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
AnnaBridge	171:3a7713b1edbc	1544
AnnaBridge	171:3a7713b1edbc	1545	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
AnnaBridge	171:3a7713b1edbc	1546	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
AnnaBridge	171:3a7713b1edbc	1547
AnnaBridge	171:3a7713b1edbc	1548	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
AnnaBridge	171:3a7713b1edbc	1549	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
AnnaBridge	171:3a7713b1edbc	1550
AnnaBridge	171:3a7713b1edbc	1551	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
AnnaBridge	171:3a7713b1edbc	1552	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
AnnaBridge	171:3a7713b1edbc	1553
AnnaBridge	171:3a7713b1edbc	1554	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
AnnaBridge	171:3a7713b1edbc	1555	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
AnnaBridge	171:3a7713b1edbc	1556
AnnaBridge	171:3a7713b1edbc	1557	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
AnnaBridge	171:3a7713b1edbc	1558	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
AnnaBridge	171:3a7713b1edbc	1559
AnnaBridge	171:3a7713b1edbc	1560	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
AnnaBridge	171:3a7713b1edbc	1561	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
AnnaBridge	171:3a7713b1edbc	1562
AnnaBridge	171:3a7713b1edbc	1563	/* Floating-Point Context Address Register Definitions */
AnnaBridge	171:3a7713b1edbc	1564	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
AnnaBridge	171:3a7713b1edbc	1565	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
AnnaBridge	171:3a7713b1edbc	1566
AnnaBridge	171:3a7713b1edbc	1567	/* Floating-Point Default Status Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	1568	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
AnnaBridge	171:3a7713b1edbc	1569	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
AnnaBridge	171:3a7713b1edbc	1570
AnnaBridge	171:3a7713b1edbc	1571	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
AnnaBridge	171:3a7713b1edbc	1572	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
AnnaBridge	171:3a7713b1edbc	1573
AnnaBridge	171:3a7713b1edbc	1574	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
AnnaBridge	171:3a7713b1edbc	1575	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
AnnaBridge	171:3a7713b1edbc	1576
AnnaBridge	171:3a7713b1edbc	1577	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
AnnaBridge	171:3a7713b1edbc	1578	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
AnnaBridge	171:3a7713b1edbc	1579
AnnaBridge	171:3a7713b1edbc	1580	/* Media and FP Feature Register 0 Definitions */
AnnaBridge	171:3a7713b1edbc	1581	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
AnnaBridge	171:3a7713b1edbc	1582	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
AnnaBridge	171:3a7713b1edbc	1583
AnnaBridge	171:3a7713b1edbc	1584	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
AnnaBridge	171:3a7713b1edbc	1585	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
AnnaBridge	171:3a7713b1edbc	1586
AnnaBridge	171:3a7713b1edbc	1587	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
AnnaBridge	171:3a7713b1edbc	1588	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
AnnaBridge	171:3a7713b1edbc	1589
AnnaBridge	171:3a7713b1edbc	1590	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
AnnaBridge	171:3a7713b1edbc	1591	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
AnnaBridge	171:3a7713b1edbc	1592
AnnaBridge	171:3a7713b1edbc	1593	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
AnnaBridge	171:3a7713b1edbc	1594	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
AnnaBridge	171:3a7713b1edbc	1595
AnnaBridge	171:3a7713b1edbc	1596	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
AnnaBridge	171:3a7713b1edbc	1597	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
AnnaBridge	171:3a7713b1edbc	1598
AnnaBridge	171:3a7713b1edbc	1599	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
AnnaBridge	171:3a7713b1edbc	1600	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
AnnaBridge	171:3a7713b1edbc	1601
AnnaBridge	171:3a7713b1edbc	1602	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
AnnaBridge	171:3a7713b1edbc	1603	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
AnnaBridge	171:3a7713b1edbc	1604
AnnaBridge	171:3a7713b1edbc	1605	/* Media and FP Feature Register 1 Definitions */
AnnaBridge	171:3a7713b1edbc	1606	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
AnnaBridge	171:3a7713b1edbc	1607	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
AnnaBridge	171:3a7713b1edbc	1608
AnnaBridge	171:3a7713b1edbc	1609	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
AnnaBridge	171:3a7713b1edbc	1610	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
AnnaBridge	171:3a7713b1edbc	1611
AnnaBridge	171:3a7713b1edbc	1612	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
AnnaBridge	171:3a7713b1edbc	1613	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
AnnaBridge	171:3a7713b1edbc	1614
AnnaBridge	171:3a7713b1edbc	1615	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
AnnaBridge	171:3a7713b1edbc	1616	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
AnnaBridge	171:3a7713b1edbc	1617
AnnaBridge	171:3a7713b1edbc	1618	/* Media and FP Feature Register 2 Definitions */
AnnaBridge	171:3a7713b1edbc	1619
AnnaBridge	171:3a7713b1edbc	1620	/@} end of group CMSIS_FPU /
AnnaBridge	171:3a7713b1edbc	1621
AnnaBridge	171:3a7713b1edbc	1622
AnnaBridge	171:3a7713b1edbc	1623	/**
AnnaBridge	171:3a7713b1edbc	1624	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	1625	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge	171:3a7713b1edbc	1626	\brief Type definitions for the Core Debug Registers
AnnaBridge	171:3a7713b1edbc	1627	@{
AnnaBridge	171:3a7713b1edbc	1628	*/
AnnaBridge	171:3a7713b1edbc	1629
AnnaBridge	171:3a7713b1edbc	1630	/**
AnnaBridge	171:3a7713b1edbc	1631	\brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge	171:3a7713b1edbc	1632	*/
AnnaBridge	171:3a7713b1edbc	1633	typedef struct
AnnaBridge	171:3a7713b1edbc	1634	{
AnnaBridge	171:3a7713b1edbc	1635	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
AnnaBridge	171:3a7713b1edbc	1636	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
AnnaBridge	171:3a7713b1edbc	1637	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
AnnaBridge	171:3a7713b1edbc	1638	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
AnnaBridge	171:3a7713b1edbc	1639	} CoreDebug_Type;
AnnaBridge	171:3a7713b1edbc	1640
AnnaBridge	171:3a7713b1edbc	1641	/* Debug Halting Control and Status Register Definitions */
AnnaBridge	171:3a7713b1edbc	1642	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
AnnaBridge	171:3a7713b1edbc	1643	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
AnnaBridge	171:3a7713b1edbc	1644
AnnaBridge	171:3a7713b1edbc	1645	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
AnnaBridge	171:3a7713b1edbc	1646	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
AnnaBridge	171:3a7713b1edbc	1647
AnnaBridge	171:3a7713b1edbc	1648	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
AnnaBridge	171:3a7713b1edbc	1649	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
AnnaBridge	171:3a7713b1edbc	1650
AnnaBridge	171:3a7713b1edbc	1651	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
AnnaBridge	171:3a7713b1edbc	1652	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
AnnaBridge	171:3a7713b1edbc	1653
AnnaBridge	171:3a7713b1edbc	1654	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
AnnaBridge	171:3a7713b1edbc	1655	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
AnnaBridge	171:3a7713b1edbc	1656
AnnaBridge	171:3a7713b1edbc	1657	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
AnnaBridge	171:3a7713b1edbc	1658	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
AnnaBridge	171:3a7713b1edbc	1659
AnnaBridge	171:3a7713b1edbc	1660	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
AnnaBridge	171:3a7713b1edbc	1661	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
AnnaBridge	171:3a7713b1edbc	1662
AnnaBridge	171:3a7713b1edbc	1663	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
AnnaBridge	171:3a7713b1edbc	1664	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
AnnaBridge	171:3a7713b1edbc	1665
AnnaBridge	171:3a7713b1edbc	1666	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
AnnaBridge	171:3a7713b1edbc	1667	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
AnnaBridge	171:3a7713b1edbc	1668
AnnaBridge	171:3a7713b1edbc	1669	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
AnnaBridge	171:3a7713b1edbc	1670	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
AnnaBridge	171:3a7713b1edbc	1671
AnnaBridge	171:3a7713b1edbc	1672	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
AnnaBridge	171:3a7713b1edbc	1673	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
AnnaBridge	171:3a7713b1edbc	1674
AnnaBridge	171:3a7713b1edbc	1675	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
AnnaBridge	171:3a7713b1edbc	1676	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
AnnaBridge	171:3a7713b1edbc	1677
AnnaBridge	171:3a7713b1edbc	1678	/* Debug Core Register Selector Register Definitions */
AnnaBridge	171:3a7713b1edbc	1679	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
AnnaBridge	171:3a7713b1edbc	1680	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
AnnaBridge	171:3a7713b1edbc	1681
AnnaBridge	171:3a7713b1edbc	1682	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
AnnaBridge	171:3a7713b1edbc	1683	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
AnnaBridge	171:3a7713b1edbc	1684
AnnaBridge	171:3a7713b1edbc	1685	/* Debug Exception and Monitor Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	1686	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
AnnaBridge	171:3a7713b1edbc	1687	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
AnnaBridge	171:3a7713b1edbc	1688
AnnaBridge	171:3a7713b1edbc	1689	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
AnnaBridge	171:3a7713b1edbc	1690	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
AnnaBridge	171:3a7713b1edbc	1691
AnnaBridge	171:3a7713b1edbc	1692	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
AnnaBridge	171:3a7713b1edbc	1693	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
AnnaBridge	171:3a7713b1edbc	1694
AnnaBridge	171:3a7713b1edbc	1695	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
AnnaBridge	171:3a7713b1edbc	1696	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
AnnaBridge	171:3a7713b1edbc	1697
AnnaBridge	171:3a7713b1edbc	1698	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
AnnaBridge	171:3a7713b1edbc	1699	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
AnnaBridge	171:3a7713b1edbc	1700
AnnaBridge	171:3a7713b1edbc	1701	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
AnnaBridge	171:3a7713b1edbc	1702	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
AnnaBridge	171:3a7713b1edbc	1703
AnnaBridge	171:3a7713b1edbc	1704	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
AnnaBridge	171:3a7713b1edbc	1705	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
AnnaBridge	171:3a7713b1edbc	1706
AnnaBridge	171:3a7713b1edbc	1707	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
AnnaBridge	171:3a7713b1edbc	1708	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
AnnaBridge	171:3a7713b1edbc	1709
AnnaBridge	171:3a7713b1edbc	1710	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
AnnaBridge	171:3a7713b1edbc	1711	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
AnnaBridge	171:3a7713b1edbc	1712
AnnaBridge	171:3a7713b1edbc	1713	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
AnnaBridge	171:3a7713b1edbc	1714	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
AnnaBridge	171:3a7713b1edbc	1715
AnnaBridge	171:3a7713b1edbc	1716	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
AnnaBridge	171:3a7713b1edbc	1717	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
AnnaBridge	171:3a7713b1edbc	1718
AnnaBridge	171:3a7713b1edbc	1719	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
AnnaBridge	171:3a7713b1edbc	1720	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
AnnaBridge	171:3a7713b1edbc	1721
AnnaBridge	171:3a7713b1edbc	1722	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
AnnaBridge	171:3a7713b1edbc	1723	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
AnnaBridge	171:3a7713b1edbc	1724
AnnaBridge	171:3a7713b1edbc	1725	/@} end of group CMSIS_CoreDebug /
AnnaBridge	171:3a7713b1edbc	1726
AnnaBridge	171:3a7713b1edbc	1727
AnnaBridge	171:3a7713b1edbc	1728	/**
AnnaBridge	171:3a7713b1edbc	1729	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	1730	\defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge	171:3a7713b1edbc	1731	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge	171:3a7713b1edbc	1732	@{
AnnaBridge	171:3a7713b1edbc	1733	*/
AnnaBridge	171:3a7713b1edbc	1734
AnnaBridge	171:3a7713b1edbc	1735	/**
AnnaBridge	171:3a7713b1edbc	1736	\brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge	171:3a7713b1edbc	1737	\param[in] field Name of the register bit field.
AnnaBridge	171:3a7713b1edbc	1738	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge	171:3a7713b1edbc	1739	\return Masked and shifted value.
AnnaBridge	171:3a7713b1edbc	1740	*/
AnnaBridge	171:3a7713b1edbc	1741	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge	171:3a7713b1edbc	1742
AnnaBridge	171:3a7713b1edbc	1743	/**
AnnaBridge	171:3a7713b1edbc	1744	\brief Mask and shift a register value to extract a bit filed value.
AnnaBridge	171:3a7713b1edbc	1745	\param[in] field Name of the register bit field.
AnnaBridge	171:3a7713b1edbc	1746	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge	171:3a7713b1edbc	1747	\return Masked and shifted bit field value.
AnnaBridge	171:3a7713b1edbc	1748	*/
AnnaBridge	171:3a7713b1edbc	1749	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge	171:3a7713b1edbc	1750
AnnaBridge	171:3a7713b1edbc	1751	/@} end of group CMSIS_core_bitfield /
AnnaBridge	171:3a7713b1edbc	1752
AnnaBridge	171:3a7713b1edbc	1753
AnnaBridge	171:3a7713b1edbc	1754	/**
AnnaBridge	171:3a7713b1edbc	1755	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	1756	\defgroup CMSIS_core_base Core Definitions
AnnaBridge	171:3a7713b1edbc	1757	\brief Definitions for base addresses, unions, and structures.
AnnaBridge	171:3a7713b1edbc	1758	@{
AnnaBridge	171:3a7713b1edbc	1759	*/
AnnaBridge	171:3a7713b1edbc	1760
AnnaBridge	171:3a7713b1edbc	1761	/* Memory mapping of Core Hardware */
AnnaBridge	171:3a7713b1edbc	1762	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
AnnaBridge	171:3a7713b1edbc	1763	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
AnnaBridge	171:3a7713b1edbc	1764	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
AnnaBridge	171:3a7713b1edbc	1765	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
AnnaBridge	171:3a7713b1edbc	1766	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
AnnaBridge	171:3a7713b1edbc	1767	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
AnnaBridge	171:3a7713b1edbc	1768	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
AnnaBridge	171:3a7713b1edbc	1769	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
AnnaBridge	171:3a7713b1edbc	1770
AnnaBridge	171:3a7713b1edbc	1771	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
AnnaBridge	171:3a7713b1edbc	1772	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
AnnaBridge	171:3a7713b1edbc	1773	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
AnnaBridge	171:3a7713b1edbc	1774	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
AnnaBridge	171:3a7713b1edbc	1775	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
AnnaBridge	171:3a7713b1edbc	1776	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
AnnaBridge	171:3a7713b1edbc	1777	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
AnnaBridge	171:3a7713b1edbc	1778	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
AnnaBridge	171:3a7713b1edbc	1779
AnnaBridge	171:3a7713b1edbc	1780	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	1781	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
AnnaBridge	171:3a7713b1edbc	1782	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
AnnaBridge	171:3a7713b1edbc	1783	#endif
AnnaBridge	171:3a7713b1edbc	1784
AnnaBridge	171:3a7713b1edbc	1785	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
AnnaBridge	171:3a7713b1edbc	1786	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
AnnaBridge	171:3a7713b1edbc	1787
AnnaBridge	171:3a7713b1edbc	1788	/@} /
AnnaBridge	171:3a7713b1edbc	1789
AnnaBridge	171:3a7713b1edbc	1790
AnnaBridge	171:3a7713b1edbc	1791
AnnaBridge	171:3a7713b1edbc	1792	/*******************************************************************************
AnnaBridge	171:3a7713b1edbc	1793	* Hardware Abstraction Layer
AnnaBridge	171:3a7713b1edbc	1794	Core Function Interface contains:
AnnaBridge	171:3a7713b1edbc	1795	- Core NVIC Functions
AnnaBridge	171:3a7713b1edbc	1796	- Core SysTick Functions
AnnaBridge	171:3a7713b1edbc	1797	- Core Debug Functions
AnnaBridge	171:3a7713b1edbc	1798	- Core Register Access Functions
AnnaBridge	171:3a7713b1edbc	1799	******************************************************************************/
AnnaBridge	171:3a7713b1edbc	1800	/**
AnnaBridge	171:3a7713b1edbc	1801	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge	171:3a7713b1edbc	1802	*/
AnnaBridge	171:3a7713b1edbc	1803
AnnaBridge	171:3a7713b1edbc	1804
AnnaBridge	171:3a7713b1edbc	1805
AnnaBridge	171:3a7713b1edbc	1806	/* ########################## NVIC functions #################################### */
AnnaBridge	171:3a7713b1edbc	1807	/**
AnnaBridge	171:3a7713b1edbc	1808	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	171:3a7713b1edbc	1809	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge	171:3a7713b1edbc	1810	\brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge	171:3a7713b1edbc	1811	@{
AnnaBridge	171:3a7713b1edbc	1812	*/
AnnaBridge	171:3a7713b1edbc	1813
AnnaBridge	171:3a7713b1edbc	1814	#ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge	171:3a7713b1edbc	1815	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	171:3a7713b1edbc	1816	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge	171:3a7713b1edbc	1817	#endif
AnnaBridge	171:3a7713b1edbc	1818	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	171:3a7713b1edbc	1819	#else
AnnaBridge	171:3a7713b1edbc	1820	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
AnnaBridge	171:3a7713b1edbc	1821	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
AnnaBridge	171:3a7713b1edbc	1822	#define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge	171:3a7713b1edbc	1823	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge	171:3a7713b1edbc	1824	#define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge	171:3a7713b1edbc	1825	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge	171:3a7713b1edbc	1826	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge	171:3a7713b1edbc	1827	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge	171:3a7713b1edbc	1828	#define NVIC_GetActive __NVIC_GetActive
AnnaBridge	171:3a7713b1edbc	1829	#define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge	171:3a7713b1edbc	1830	#define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge	171:3a7713b1edbc	1831	#define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge	171:3a7713b1edbc	1832	#endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge	171:3a7713b1edbc	1833
AnnaBridge	171:3a7713b1edbc	1834	#ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge	171:3a7713b1edbc	1835	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	171:3a7713b1edbc	1836	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge	171:3a7713b1edbc	1837	#endif
AnnaBridge	171:3a7713b1edbc	1838	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	171:3a7713b1edbc	1839	#else
AnnaBridge	171:3a7713b1edbc	1840	#define NVIC_SetVector __NVIC_SetVector
AnnaBridge	171:3a7713b1edbc	1841	#define NVIC_GetVector __NVIC_GetVector
AnnaBridge	171:3a7713b1edbc	1842	#endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge	171:3a7713b1edbc	1843
AnnaBridge	171:3a7713b1edbc	1844	#define NVIC_USER_IRQ_OFFSET 16
AnnaBridge	171:3a7713b1edbc	1845
AnnaBridge	171:3a7713b1edbc	1846
AnnaBridge	171:3a7713b1edbc	1847	/* The following EXC_RETURN values are saved the LR on exception entry */
AnnaBridge	171:3a7713b1edbc	1848	#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
AnnaBridge	171:3a7713b1edbc	1849	#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
AnnaBridge	171:3a7713b1edbc	1850	#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
AnnaBridge	171:3a7713b1edbc	1851	#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
AnnaBridge	171:3a7713b1edbc	1852	#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
AnnaBridge	171:3a7713b1edbc	1853	#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
AnnaBridge	171:3a7713b1edbc	1854
AnnaBridge	171:3a7713b1edbc	1855
AnnaBridge	171:3a7713b1edbc	1856	/**
AnnaBridge	171:3a7713b1edbc	1857	\brief Set Priority Grouping
AnnaBridge	171:3a7713b1edbc	1858	\details Sets the priority grouping field using the required unlock sequence.
AnnaBridge	171:3a7713b1edbc	1859	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge	171:3a7713b1edbc	1860	Only values from 0..7 are used.
AnnaBridge	171:3a7713b1edbc	1861	In case of a conflict between priority grouping and available
AnnaBridge	171:3a7713b1edbc	1862	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	171:3a7713b1edbc	1863	\param [in] PriorityGroup Priority grouping field.
AnnaBridge	171:3a7713b1edbc	1864	*/
AnnaBridge	171:3a7713b1edbc	1865	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
AnnaBridge	171:3a7713b1edbc	1866	{
AnnaBridge	171:3a7713b1edbc	1867	uint32_t reg_value;
AnnaBridge	171:3a7713b1edbc	1868	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	171:3a7713b1edbc	1869
AnnaBridge	171:3a7713b1edbc	1870	reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge	171:3a7713b1edbc	1871	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge	171:3a7713b1edbc	1872	reg_value = (reg_value \|
AnnaBridge	171:3a7713b1edbc	1873	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	171:3a7713b1edbc	1874	(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
AnnaBridge	171:3a7713b1edbc	1875	SCB->AIRCR = reg_value;
AnnaBridge	171:3a7713b1edbc	1876	}
AnnaBridge	171:3a7713b1edbc	1877
AnnaBridge	171:3a7713b1edbc	1878
AnnaBridge	171:3a7713b1edbc	1879	/**
AnnaBridge	171:3a7713b1edbc	1880	\brief Get Priority Grouping
AnnaBridge	171:3a7713b1edbc	1881	\details Reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge	171:3a7713b1edbc	1882	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge	171:3a7713b1edbc	1883	*/
AnnaBridge	171:3a7713b1edbc	1884	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
AnnaBridge	171:3a7713b1edbc	1885	{
AnnaBridge	171:3a7713b1edbc	1886	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge	171:3a7713b1edbc	1887	}
AnnaBridge	171:3a7713b1edbc	1888
AnnaBridge	171:3a7713b1edbc	1889
AnnaBridge	171:3a7713b1edbc	1890	/**
AnnaBridge	171:3a7713b1edbc	1891	\brief Enable Interrupt
AnnaBridge	171:3a7713b1edbc	1892	\details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	171:3a7713b1edbc	1893	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1894	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1895	*/
AnnaBridge	171:3a7713b1edbc	1896	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1897	{
AnnaBridge	171:3a7713b1edbc	1898	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1899	{
AnnaBridge	171:3a7713b1edbc	1900	NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	171:3a7713b1edbc	1901	}
AnnaBridge	171:3a7713b1edbc	1902	}
AnnaBridge	171:3a7713b1edbc	1903
AnnaBridge	171:3a7713b1edbc	1904
AnnaBridge	171:3a7713b1edbc	1905	/**
AnnaBridge	171:3a7713b1edbc	1906	\brief Get Interrupt Enable status
AnnaBridge	171:3a7713b1edbc	1907	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge	171:3a7713b1edbc	1908	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1909	\return 0 Interrupt is not enabled.
AnnaBridge	171:3a7713b1edbc	1910	\return 1 Interrupt is enabled.
AnnaBridge	171:3a7713b1edbc	1911	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1912	*/
AnnaBridge	171:3a7713b1edbc	1913	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1914	{
AnnaBridge	171:3a7713b1edbc	1915	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1916	{
AnnaBridge	171:3a7713b1edbc	1917	return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	171:3a7713b1edbc	1918	}
AnnaBridge	171:3a7713b1edbc	1919	else
AnnaBridge	171:3a7713b1edbc	1920	{
AnnaBridge	171:3a7713b1edbc	1921	return(0U);
AnnaBridge	171:3a7713b1edbc	1922	}
AnnaBridge	171:3a7713b1edbc	1923	}
AnnaBridge	171:3a7713b1edbc	1924
AnnaBridge	171:3a7713b1edbc	1925
AnnaBridge	171:3a7713b1edbc	1926	/**
AnnaBridge	171:3a7713b1edbc	1927	\brief Disable Interrupt
AnnaBridge	171:3a7713b1edbc	1928	\details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	171:3a7713b1edbc	1929	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1930	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1931	*/
AnnaBridge	171:3a7713b1edbc	1932	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1933	{
AnnaBridge	171:3a7713b1edbc	1934	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1935	{
AnnaBridge	171:3a7713b1edbc	1936	NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	171:3a7713b1edbc	1937	__DSB();
AnnaBridge	171:3a7713b1edbc	1938	__ISB();
AnnaBridge	171:3a7713b1edbc	1939	}
AnnaBridge	171:3a7713b1edbc	1940	}
AnnaBridge	171:3a7713b1edbc	1941
AnnaBridge	171:3a7713b1edbc	1942
AnnaBridge	171:3a7713b1edbc	1943	/**
AnnaBridge	171:3a7713b1edbc	1944	\brief Get Pending Interrupt
AnnaBridge	171:3a7713b1edbc	1945	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge	171:3a7713b1edbc	1946	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1947	\return 0 Interrupt status is not pending.
AnnaBridge	171:3a7713b1edbc	1948	\return 1 Interrupt status is pending.
AnnaBridge	171:3a7713b1edbc	1949	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1950	*/
AnnaBridge	171:3a7713b1edbc	1951	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1952	{
AnnaBridge	171:3a7713b1edbc	1953	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1954	{
AnnaBridge	171:3a7713b1edbc	1955	return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	171:3a7713b1edbc	1956	}
AnnaBridge	171:3a7713b1edbc	1957	else
AnnaBridge	171:3a7713b1edbc	1958	{
AnnaBridge	171:3a7713b1edbc	1959	return(0U);
AnnaBridge	171:3a7713b1edbc	1960	}
AnnaBridge	171:3a7713b1edbc	1961	}
AnnaBridge	171:3a7713b1edbc	1962
AnnaBridge	171:3a7713b1edbc	1963
AnnaBridge	171:3a7713b1edbc	1964	/**
AnnaBridge	171:3a7713b1edbc	1965	\brief Set Pending Interrupt
AnnaBridge	171:3a7713b1edbc	1966	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	171:3a7713b1edbc	1967	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1968	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1969	*/
AnnaBridge	171:3a7713b1edbc	1970	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1971	{
AnnaBridge	171:3a7713b1edbc	1972	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1973	{
AnnaBridge	171:3a7713b1edbc	1974	NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	171:3a7713b1edbc	1975	}
AnnaBridge	171:3a7713b1edbc	1976	}
AnnaBridge	171:3a7713b1edbc	1977
AnnaBridge	171:3a7713b1edbc	1978
AnnaBridge	171:3a7713b1edbc	1979	/**
AnnaBridge	171:3a7713b1edbc	1980	\brief Clear Pending Interrupt
AnnaBridge	171:3a7713b1edbc	1981	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	171:3a7713b1edbc	1982	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1983	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1984	*/
AnnaBridge	171:3a7713b1edbc	1985	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1986	{
AnnaBridge	171:3a7713b1edbc	1987	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1988	{
AnnaBridge	171:3a7713b1edbc	1989	NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	171:3a7713b1edbc	1990	}
AnnaBridge	171:3a7713b1edbc	1991	}
AnnaBridge	171:3a7713b1edbc	1992
AnnaBridge	171:3a7713b1edbc	1993
AnnaBridge	171:3a7713b1edbc	1994	/**
AnnaBridge	171:3a7713b1edbc	1995	\brief Get Active Interrupt
AnnaBridge	171:3a7713b1edbc	1996	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge	171:3a7713b1edbc	1997	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1998	\return 0 Interrupt status is not active.
AnnaBridge	171:3a7713b1edbc	1999	\return 1 Interrupt status is active.
AnnaBridge	171:3a7713b1edbc	2000	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	2001	*/
AnnaBridge	171:3a7713b1edbc	2002	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	2003	{
AnnaBridge	171:3a7713b1edbc	2004	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	2005	{
AnnaBridge	171:3a7713b1edbc	2006	return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	171:3a7713b1edbc	2007	}
AnnaBridge	171:3a7713b1edbc	2008	else
AnnaBridge	171:3a7713b1edbc	2009	{
AnnaBridge	171:3a7713b1edbc	2010	return(0U);
AnnaBridge	171:3a7713b1edbc	2011	}
AnnaBridge	171:3a7713b1edbc	2012	}
AnnaBridge	171:3a7713b1edbc	2013
AnnaBridge	171:3a7713b1edbc	2014
AnnaBridge	171:3a7713b1edbc	2015	/**
AnnaBridge	171:3a7713b1edbc	2016	\brief Set Interrupt Priority
AnnaBridge	171:3a7713b1edbc	2017	\details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge	171:3a7713b1edbc	2018	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	171:3a7713b1edbc	2019	or negative to specify a processor exception.
AnnaBridge	171:3a7713b1edbc	2020	\param [in] IRQn Interrupt number.
AnnaBridge	171:3a7713b1edbc	2021	\param [in] priority Priority to set.
AnnaBridge	171:3a7713b1edbc	2022	\note The priority cannot be set for every processor exception.
AnnaBridge	171:3a7713b1edbc	2023	*/
AnnaBridge	171:3a7713b1edbc	2024	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	171:3a7713b1edbc	2025	{
AnnaBridge	171:3a7713b1edbc	2026	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	2027	{
AnnaBridge	171:3a7713b1edbc	2028	NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	171:3a7713b1edbc	2029	}
AnnaBridge	171:3a7713b1edbc	2030	else
AnnaBridge	171:3a7713b1edbc	2031	{
AnnaBridge	171:3a7713b1edbc	2032	SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	171:3a7713b1edbc	2033	}
AnnaBridge	171:3a7713b1edbc	2034	}
AnnaBridge	171:3a7713b1edbc	2035
AnnaBridge	171:3a7713b1edbc	2036
AnnaBridge	171:3a7713b1edbc	2037	/**
AnnaBridge	171:3a7713b1edbc	2038	\brief Get Interrupt Priority
AnnaBridge	171:3a7713b1edbc	2039	\details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge	171:3a7713b1edbc	2040	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	171:3a7713b1edbc	2041	or negative to specify a processor exception.
AnnaBridge	171:3a7713b1edbc	2042	\param [in] IRQn Interrupt number.
AnnaBridge	171:3a7713b1edbc	2043	\return Interrupt Priority.
AnnaBridge	171:3a7713b1edbc	2044	Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	171:3a7713b1edbc	2045	*/
AnnaBridge	171:3a7713b1edbc	2046	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	2047	{
AnnaBridge	171:3a7713b1edbc	2048
AnnaBridge	171:3a7713b1edbc	2049	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	2050	{
AnnaBridge	171:3a7713b1edbc	2051	return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	171:3a7713b1edbc	2052	}
AnnaBridge	171:3a7713b1edbc	2053	else
AnnaBridge	171:3a7713b1edbc	2054	{
AnnaBridge	171:3a7713b1edbc	2055	return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	171:3a7713b1edbc	2056	}
AnnaBridge	171:3a7713b1edbc	2057	}
AnnaBridge	171:3a7713b1edbc	2058
AnnaBridge	171:3a7713b1edbc	2059
AnnaBridge	171:3a7713b1edbc	2060	/**
AnnaBridge	171:3a7713b1edbc	2061	\brief Encode Priority
AnnaBridge	171:3a7713b1edbc	2062	\details Encodes the priority for an interrupt with the given priority group,
AnnaBridge	171:3a7713b1edbc	2063	preemptive priority value, and subpriority value.
AnnaBridge	171:3a7713b1edbc	2064	In case of a conflict between priority grouping and available
AnnaBridge	171:3a7713b1edbc	2065	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	171:3a7713b1edbc	2066	\param [in] PriorityGroup Used priority group.
AnnaBridge	171:3a7713b1edbc	2067	\param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	171:3a7713b1edbc	2068	\param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge	171:3a7713b1edbc	2069	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge	171:3a7713b1edbc	2070	*/
AnnaBridge	171:3a7713b1edbc	2071	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge	171:3a7713b1edbc	2072	{
AnnaBridge	171:3a7713b1edbc	2073	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	171:3a7713b1edbc	2074	uint32_t PreemptPriorityBits;
AnnaBridge	171:3a7713b1edbc	2075	uint32_t SubPriorityBits;
AnnaBridge	171:3a7713b1edbc	2076
AnnaBridge	171:3a7713b1edbc	2077	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	171:3a7713b1edbc	2078	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	171:3a7713b1edbc	2079
AnnaBridge	171:3a7713b1edbc	2080	return (
AnnaBridge	171:3a7713b1edbc	2081	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
AnnaBridge	171:3a7713b1edbc	2082	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge	171:3a7713b1edbc	2083	);
AnnaBridge	171:3a7713b1edbc	2084	}
AnnaBridge	171:3a7713b1edbc	2085
AnnaBridge	171:3a7713b1edbc	2086
AnnaBridge	171:3a7713b1edbc	2087	/**
AnnaBridge	171:3a7713b1edbc	2088	\brief Decode Priority
AnnaBridge	171:3a7713b1edbc	2089	\details Decodes an interrupt priority value with a given priority group to
AnnaBridge	171:3a7713b1edbc	2090	preemptive priority value and subpriority value.
AnnaBridge	171:3a7713b1edbc	2091	In case of a conflict between priority grouping and available
AnnaBridge	171:3a7713b1edbc	2092	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge	171:3a7713b1edbc	2093	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge	171:3a7713b1edbc	2094	\param [in] PriorityGroup Used priority group.
AnnaBridge	171:3a7713b1edbc	2095	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	171:3a7713b1edbc	2096	\param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge	171:3a7713b1edbc	2097	*/
AnnaBridge	171:3a7713b1edbc	2098	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
AnnaBridge	171:3a7713b1edbc	2099	{
AnnaBridge	171:3a7713b1edbc	2100	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	171:3a7713b1edbc	2101	uint32_t PreemptPriorityBits;
AnnaBridge	171:3a7713b1edbc	2102	uint32_t SubPriorityBits;
AnnaBridge	171:3a7713b1edbc	2103
AnnaBridge	171:3a7713b1edbc	2104	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	171:3a7713b1edbc	2105	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	171:3a7713b1edbc	2106
AnnaBridge	171:3a7713b1edbc	2107	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge	171:3a7713b1edbc	2108	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge	171:3a7713b1edbc	2109	}
AnnaBridge	171:3a7713b1edbc	2110
AnnaBridge	171:3a7713b1edbc	2111
AnnaBridge	171:3a7713b1edbc	2112	/**
AnnaBridge	171:3a7713b1edbc	2113	\brief Set Interrupt Vector
AnnaBridge	171:3a7713b1edbc	2114	\details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge	171:3a7713b1edbc	2115	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	171:3a7713b1edbc	2116	or negative to specify a processor exception.
AnnaBridge	171:3a7713b1edbc	2117	VTOR must been relocated to SRAM before.
AnnaBridge	171:3a7713b1edbc	2118	\param [in] IRQn Interrupt number
AnnaBridge	171:3a7713b1edbc	2119	\param [in] vector Address of interrupt handler function
AnnaBridge	171:3a7713b1edbc	2120	*/
AnnaBridge	171:3a7713b1edbc	2121	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge	171:3a7713b1edbc	2122	{
AnnaBridge	171:3a7713b1edbc	2123	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	171:3a7713b1edbc	2124	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge	171:3a7713b1edbc	2125	}
AnnaBridge	171:3a7713b1edbc	2126
AnnaBridge	171:3a7713b1edbc	2127
AnnaBridge	171:3a7713b1edbc	2128	/**
AnnaBridge	171:3a7713b1edbc	2129	\brief Get Interrupt Vector
AnnaBridge	171:3a7713b1edbc	2130	\details Reads an interrupt vector from interrupt vector table.
AnnaBridge	171:3a7713b1edbc	2131	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	171:3a7713b1edbc	2132	or negative to specify a processor exception.
AnnaBridge	171:3a7713b1edbc	2133	\param [in] IRQn Interrupt number.
AnnaBridge	171:3a7713b1edbc	2134	\return Address of interrupt handler function
AnnaBridge	171:3a7713b1edbc	2135	*/
AnnaBridge	171:3a7713b1edbc	2136	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	2137	{
AnnaBridge	171:3a7713b1edbc	2138	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	171:3a7713b1edbc	2139	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge	171:3a7713b1edbc	2140	}
AnnaBridge	171:3a7713b1edbc	2141
AnnaBridge	171:3a7713b1edbc	2142
AnnaBridge	171:3a7713b1edbc	2143	/**
AnnaBridge	171:3a7713b1edbc	2144	\brief System Reset
AnnaBridge	171:3a7713b1edbc	2145	\details Initiates a system reset request to reset the MCU.
AnnaBridge	171:3a7713b1edbc	2146	*/
AnnaBridge	171:3a7713b1edbc	2147	__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge	171:3a7713b1edbc	2148	{
AnnaBridge	171:3a7713b1edbc	2149	__DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge	171:3a7713b1edbc	2150	buffered write are completed before reset */
AnnaBridge	171:3a7713b1edbc	2151	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	171:3a7713b1edbc	2152	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
AnnaBridge	171:3a7713b1edbc	2153	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
AnnaBridge	171:3a7713b1edbc	2154	__DSB(); /* Ensure completion of memory access */
AnnaBridge	171:3a7713b1edbc	2155
AnnaBridge	171:3a7713b1edbc	2156	for(;;) /* wait until reset */
AnnaBridge	171:3a7713b1edbc	2157	{
AnnaBridge	171:3a7713b1edbc	2158	__NOP();
AnnaBridge	171:3a7713b1edbc	2159	}
AnnaBridge	171:3a7713b1edbc	2160	}
AnnaBridge	171:3a7713b1edbc	2161
AnnaBridge	171:3a7713b1edbc	2162	/@} end of CMSIS_Core_NVICFunctions /
AnnaBridge	171:3a7713b1edbc	2163
AnnaBridge	171:3a7713b1edbc	2164	/* ########################## MPU functions #################################### */
AnnaBridge	171:3a7713b1edbc	2165
AnnaBridge	171:3a7713b1edbc	2166	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	2167
AnnaBridge	171:3a7713b1edbc	2168	#include "mpu_armv7.h"
AnnaBridge	171:3a7713b1edbc	2169
AnnaBridge	171:3a7713b1edbc	2170	#endif
AnnaBridge	171:3a7713b1edbc	2171
AnnaBridge	171:3a7713b1edbc	2172	/* ########################## FPU functions #################################### */
AnnaBridge	171:3a7713b1edbc	2173	/**
AnnaBridge	171:3a7713b1edbc	2174	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	171:3a7713b1edbc	2175	\defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge	171:3a7713b1edbc	2176	\brief Function that provides FPU type.
AnnaBridge	171:3a7713b1edbc	2177	@{
AnnaBridge	171:3a7713b1edbc	2178	*/
AnnaBridge	171:3a7713b1edbc	2179
AnnaBridge	171:3a7713b1edbc	2180	/**
AnnaBridge	171:3a7713b1edbc	2181	\brief get FPU type
AnnaBridge	171:3a7713b1edbc	2182	\details returns the FPU type
AnnaBridge	171:3a7713b1edbc	2183	\returns
AnnaBridge	171:3a7713b1edbc	2184	- \b 0: No FPU
AnnaBridge	171:3a7713b1edbc	2185	- \b 1: Single precision FPU
AnnaBridge	171:3a7713b1edbc	2186	- \b 2: Double + Single precision FPU
AnnaBridge	171:3a7713b1edbc	2187	*/
AnnaBridge	171:3a7713b1edbc	2188	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge	171:3a7713b1edbc	2189	{
AnnaBridge	171:3a7713b1edbc	2190	uint32_t mvfr0;
AnnaBridge	171:3a7713b1edbc	2191
AnnaBridge	171:3a7713b1edbc	2192	mvfr0 = SCB->MVFR0;
AnnaBridge	171:3a7713b1edbc	2193	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x220U)
AnnaBridge	171:3a7713b1edbc	2194	{
AnnaBridge	171:3a7713b1edbc	2195	return 2U; /* Double + Single precision FPU */
AnnaBridge	171:3a7713b1edbc	2196	}
AnnaBridge	171:3a7713b1edbc	2197	else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
AnnaBridge	171:3a7713b1edbc	2198	{
AnnaBridge	171:3a7713b1edbc	2199	return 1U; /* Single precision FPU */
AnnaBridge	171:3a7713b1edbc	2200	}
AnnaBridge	171:3a7713b1edbc	2201	else
AnnaBridge	171:3a7713b1edbc	2202	{
AnnaBridge	171:3a7713b1edbc	2203	return 0U; /* No FPU */
AnnaBridge	171:3a7713b1edbc	2204	}
AnnaBridge	171:3a7713b1edbc	2205	}
AnnaBridge	171:3a7713b1edbc	2206
AnnaBridge	171:3a7713b1edbc	2207
AnnaBridge	171:3a7713b1edbc	2208	/@} end of CMSIS_Core_FpuFunctions /
AnnaBridge	171:3a7713b1edbc	2209
AnnaBridge	171:3a7713b1edbc	2210
AnnaBridge	171:3a7713b1edbc	2211
AnnaBridge	171:3a7713b1edbc	2212	/* ########################## Cache functions #################################### */
AnnaBridge	171:3a7713b1edbc	2213	/**
AnnaBridge	171:3a7713b1edbc	2214	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	171:3a7713b1edbc	2215	\defgroup CMSIS_Core_CacheFunctions Cache Functions
AnnaBridge	171:3a7713b1edbc	2216	\brief Functions that configure Instruction and Data cache.
AnnaBridge	171:3a7713b1edbc	2217	@{
AnnaBridge	171:3a7713b1edbc	2218	*/
AnnaBridge	171:3a7713b1edbc	2219
AnnaBridge	171:3a7713b1edbc	2220	/* Cache Size ID Register Macros */
AnnaBridge	171:3a7713b1edbc	2221	#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
AnnaBridge	171:3a7713b1edbc	2222	#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
AnnaBridge	171:3a7713b1edbc	2223
AnnaBridge	171:3a7713b1edbc	2224
AnnaBridge	171:3a7713b1edbc	2225	/**
AnnaBridge	171:3a7713b1edbc	2226	\brief Enable I-Cache
AnnaBridge	171:3a7713b1edbc	2227	\details Turns on I-Cache
AnnaBridge	171:3a7713b1edbc	2228	*/
AnnaBridge	171:3a7713b1edbc	2229	__STATIC_INLINE void SCB_EnableICache (void)
AnnaBridge	171:3a7713b1edbc	2230	{
AnnaBridge	171:3a7713b1edbc	2231	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	2232	__DSB();
AnnaBridge	171:3a7713b1edbc	2233	__ISB();
AnnaBridge	171:3a7713b1edbc	2234	SCB->ICIALLU = 0UL; /* invalidate I-Cache */
AnnaBridge	171:3a7713b1edbc	2235	__DSB();
AnnaBridge	171:3a7713b1edbc	2236	__ISB();
AnnaBridge	171:3a7713b1edbc	2237	SCB->CCR \|= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
AnnaBridge	171:3a7713b1edbc	2238	__DSB();
AnnaBridge	171:3a7713b1edbc	2239	__ISB();
AnnaBridge	171:3a7713b1edbc	2240	#endif
AnnaBridge	171:3a7713b1edbc	2241	}
AnnaBridge	171:3a7713b1edbc	2242
AnnaBridge	171:3a7713b1edbc	2243
AnnaBridge	171:3a7713b1edbc	2244	/**
AnnaBridge	171:3a7713b1edbc	2245	\brief Disable I-Cache
AnnaBridge	171:3a7713b1edbc	2246	\details Turns off I-Cache
AnnaBridge	171:3a7713b1edbc	2247	*/
AnnaBridge	171:3a7713b1edbc	2248	__STATIC_INLINE void SCB_DisableICache (void)
AnnaBridge	171:3a7713b1edbc	2249	{
AnnaBridge	171:3a7713b1edbc	2250	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	2251	__DSB();
AnnaBridge	171:3a7713b1edbc	2252	__ISB();
AnnaBridge	171:3a7713b1edbc	2253	SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
AnnaBridge	171:3a7713b1edbc	2254	SCB->ICIALLU = 0UL; /* invalidate I-Cache */
AnnaBridge	171:3a7713b1edbc	2255	__DSB();
AnnaBridge	171:3a7713b1edbc	2256	__ISB();
AnnaBridge	171:3a7713b1edbc	2257	#endif
AnnaBridge	171:3a7713b1edbc	2258	}
AnnaBridge	171:3a7713b1edbc	2259
AnnaBridge	171:3a7713b1edbc	2260
AnnaBridge	171:3a7713b1edbc	2261	/**
AnnaBridge	171:3a7713b1edbc	2262	\brief Invalidate I-Cache
AnnaBridge	171:3a7713b1edbc	2263	\details Invalidates I-Cache
AnnaBridge	171:3a7713b1edbc	2264	*/
AnnaBridge	171:3a7713b1edbc	2265	__STATIC_INLINE void SCB_InvalidateICache (void)
AnnaBridge	171:3a7713b1edbc	2266	{
AnnaBridge	171:3a7713b1edbc	2267	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	2268	__DSB();
AnnaBridge	171:3a7713b1edbc	2269	__ISB();
AnnaBridge	171:3a7713b1edbc	2270	SCB->ICIALLU = 0UL;
AnnaBridge	171:3a7713b1edbc	2271	__DSB();
AnnaBridge	171:3a7713b1edbc	2272	__ISB();
AnnaBridge	171:3a7713b1edbc	2273	#endif
AnnaBridge	171:3a7713b1edbc	2274	}
AnnaBridge	171:3a7713b1edbc	2275
AnnaBridge	171:3a7713b1edbc	2276
AnnaBridge	171:3a7713b1edbc	2277	/**
AnnaBridge	171:3a7713b1edbc	2278	\brief Enable D-Cache
AnnaBridge	171:3a7713b1edbc	2279	\details Turns on D-Cache
AnnaBridge	171:3a7713b1edbc	2280	*/
AnnaBridge	171:3a7713b1edbc	2281	__STATIC_INLINE void SCB_EnableDCache (void)
AnnaBridge	171:3a7713b1edbc	2282	{
AnnaBridge	171:3a7713b1edbc	2283	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	2284	uint32_t ccsidr;
AnnaBridge	171:3a7713b1edbc	2285	uint32_t sets;
AnnaBridge	171:3a7713b1edbc	2286	uint32_t ways;
AnnaBridge	171:3a7713b1edbc	2287
AnnaBridge	171:3a7713b1edbc	2288	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
AnnaBridge	171:3a7713b1edbc	2289	__DSB();
AnnaBridge	171:3a7713b1edbc	2290
AnnaBridge	171:3a7713b1edbc	2291	ccsidr = SCB->CCSIDR;
AnnaBridge	171:3a7713b1edbc	2292
AnnaBridge	171:3a7713b1edbc	2293	/* invalidate D-Cache */
AnnaBridge	171:3a7713b1edbc	2294	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	171:3a7713b1edbc	2295	do {
AnnaBridge	171:3a7713b1edbc	2296	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	171:3a7713b1edbc	2297	do {
AnnaBridge	171:3a7713b1edbc	2298	SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) \|
AnnaBridge	171:3a7713b1edbc	2299	((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
AnnaBridge	171:3a7713b1edbc	2300	#if defined ( __CC_ARM )
AnnaBridge	171:3a7713b1edbc	2301	__schedule_barrier();
AnnaBridge	171:3a7713b1edbc	2302	#endif
AnnaBridge	171:3a7713b1edbc	2303	} while (ways-- != 0U);
AnnaBridge	171:3a7713b1edbc	2304	} while(sets-- != 0U);
AnnaBridge	171:3a7713b1edbc	2305	__DSB();
AnnaBridge	171:3a7713b1edbc	2306
AnnaBridge	171:3a7713b1edbc	2307	SCB->CCR \|= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
AnnaBridge	171:3a7713b1edbc	2308
AnnaBridge	171:3a7713b1edbc	2309	__DSB();
AnnaBridge	171:3a7713b1edbc	2310	__ISB();
AnnaBridge	171:3a7713b1edbc	2311	#endif
AnnaBridge	171:3a7713b1edbc	2312	}
AnnaBridge	171:3a7713b1edbc	2313
AnnaBridge	171:3a7713b1edbc	2314
AnnaBridge	171:3a7713b1edbc	2315	/**
AnnaBridge	171:3a7713b1edbc	2316	\brief Disable D-Cache
AnnaBridge	171:3a7713b1edbc	2317	\details Turns off D-Cache
AnnaBridge	171:3a7713b1edbc	2318	*/
AnnaBridge	171:3a7713b1edbc	2319	__STATIC_INLINE void SCB_DisableDCache (void)
AnnaBridge	171:3a7713b1edbc	2320	{
AnnaBridge	171:3a7713b1edbc	2321	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	2322	uint32_t ccsidr;
AnnaBridge	171:3a7713b1edbc	2323	uint32_t sets;
AnnaBridge	171:3a7713b1edbc	2324	uint32_t ways;
AnnaBridge	171:3a7713b1edbc	2325
AnnaBridge	171:3a7713b1edbc	2326	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
AnnaBridge	171:3a7713b1edbc	2327	__DSB();
AnnaBridge	171:3a7713b1edbc	2328
AnnaBridge	171:3a7713b1edbc	2329	SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
AnnaBridge	171:3a7713b1edbc	2330	__DSB();
AnnaBridge	171:3a7713b1edbc	2331
AnnaBridge	171:3a7713b1edbc	2332	ccsidr = SCB->CCSIDR;
AnnaBridge	171:3a7713b1edbc	2333
AnnaBridge	171:3a7713b1edbc	2334	/* clean & invalidate D-Cache */
AnnaBridge	171:3a7713b1edbc	2335	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	171:3a7713b1edbc	2336	do {
AnnaBridge	171:3a7713b1edbc	2337	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	171:3a7713b1edbc	2338	do {
AnnaBridge	171:3a7713b1edbc	2339	SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) \|
AnnaBridge	171:3a7713b1edbc	2340	((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
AnnaBridge	171:3a7713b1edbc	2341	#if defined ( __CC_ARM )
AnnaBridge	171:3a7713b1edbc	2342	__schedule_barrier();
AnnaBridge	171:3a7713b1edbc	2343	#endif
AnnaBridge	171:3a7713b1edbc	2344	} while (ways-- != 0U);
AnnaBridge	171:3a7713b1edbc	2345	} while(sets-- != 0U);
AnnaBridge	171:3a7713b1edbc	2346
AnnaBridge	171:3a7713b1edbc	2347	__DSB();
AnnaBridge	171:3a7713b1edbc	2348	__ISB();
AnnaBridge	171:3a7713b1edbc	2349	#endif
AnnaBridge	171:3a7713b1edbc	2350	}
AnnaBridge	171:3a7713b1edbc	2351
AnnaBridge	171:3a7713b1edbc	2352
AnnaBridge	171:3a7713b1edbc	2353	/**
AnnaBridge	171:3a7713b1edbc	2354	\brief Invalidate D-Cache
AnnaBridge	171:3a7713b1edbc	2355	\details Invalidates D-Cache
AnnaBridge	171:3a7713b1edbc	2356	*/
AnnaBridge	171:3a7713b1edbc	2357	__STATIC_INLINE void SCB_InvalidateDCache (void)
AnnaBridge	171:3a7713b1edbc	2358	{
AnnaBridge	171:3a7713b1edbc	2359	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	2360	uint32_t ccsidr;
AnnaBridge	171:3a7713b1edbc	2361	uint32_t sets;
AnnaBridge	171:3a7713b1edbc	2362	uint32_t ways;
AnnaBridge	171:3a7713b1edbc	2363
AnnaBridge	171:3a7713b1edbc	2364	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
AnnaBridge	171:3a7713b1edbc	2365	__DSB();
AnnaBridge	171:3a7713b1edbc	2366
AnnaBridge	171:3a7713b1edbc	2367	ccsidr = SCB->CCSIDR;
AnnaBridge	171:3a7713b1edbc	2368
AnnaBridge	171:3a7713b1edbc	2369	/* invalidate D-Cache */
AnnaBridge	171:3a7713b1edbc	2370	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	171:3a7713b1edbc	2371	do {
AnnaBridge	171:3a7713b1edbc	2372	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	171:3a7713b1edbc	2373	do {
AnnaBridge	171:3a7713b1edbc	2374	SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) \|
AnnaBridge	171:3a7713b1edbc	2375	((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
AnnaBridge	171:3a7713b1edbc	2376	#if defined ( __CC_ARM )
AnnaBridge	171:3a7713b1edbc	2377	__schedule_barrier();
AnnaBridge	171:3a7713b1edbc	2378	#endif
AnnaBridge	171:3a7713b1edbc	2379	} while (ways-- != 0U);
AnnaBridge	171:3a7713b1edbc	2380	} while(sets-- != 0U);
AnnaBridge	171:3a7713b1edbc	2381
AnnaBridge	171:3a7713b1edbc	2382	__DSB();
AnnaBridge	171:3a7713b1edbc	2383	__ISB();
AnnaBridge	171:3a7713b1edbc	2384	#endif
AnnaBridge	171:3a7713b1edbc	2385	}
AnnaBridge	171:3a7713b1edbc	2386
AnnaBridge	171:3a7713b1edbc	2387
AnnaBridge	171:3a7713b1edbc	2388	/**
AnnaBridge	171:3a7713b1edbc	2389	\brief Clean D-Cache
AnnaBridge	171:3a7713b1edbc	2390	\details Cleans D-Cache
AnnaBridge	171:3a7713b1edbc	2391	*/
AnnaBridge	171:3a7713b1edbc	2392	__STATIC_INLINE void SCB_CleanDCache (void)
AnnaBridge	171:3a7713b1edbc	2393	{
AnnaBridge	171:3a7713b1edbc	2394	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	2395	uint32_t ccsidr;
AnnaBridge	171:3a7713b1edbc	2396	uint32_t sets;
AnnaBridge	171:3a7713b1edbc	2397	uint32_t ways;
AnnaBridge	171:3a7713b1edbc	2398
AnnaBridge	171:3a7713b1edbc	2399	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
AnnaBridge	171:3a7713b1edbc	2400	__DSB();
AnnaBridge	171:3a7713b1edbc	2401
AnnaBridge	171:3a7713b1edbc	2402	ccsidr = SCB->CCSIDR;
AnnaBridge	171:3a7713b1edbc	2403
AnnaBridge	171:3a7713b1edbc	2404	/* clean D-Cache */
AnnaBridge	171:3a7713b1edbc	2405	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	171:3a7713b1edbc	2406	do {
AnnaBridge	171:3a7713b1edbc	2407	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	171:3a7713b1edbc	2408	do {
AnnaBridge	171:3a7713b1edbc	2409	SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) \|
AnnaBridge	171:3a7713b1edbc	2410	((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
AnnaBridge	171:3a7713b1edbc	2411	#if defined ( __CC_ARM )
AnnaBridge	171:3a7713b1edbc	2412	__schedule_barrier();
AnnaBridge	171:3a7713b1edbc	2413	#endif
AnnaBridge	171:3a7713b1edbc	2414	} while (ways-- != 0U);
AnnaBridge	171:3a7713b1edbc	2415	} while(sets-- != 0U);
AnnaBridge	171:3a7713b1edbc	2416
AnnaBridge	171:3a7713b1edbc	2417	__DSB();
AnnaBridge	171:3a7713b1edbc	2418	__ISB();
AnnaBridge	171:3a7713b1edbc	2419	#endif
AnnaBridge	171:3a7713b1edbc	2420	}
AnnaBridge	171:3a7713b1edbc	2421
AnnaBridge	171:3a7713b1edbc	2422
AnnaBridge	171:3a7713b1edbc	2423	/**
AnnaBridge	171:3a7713b1edbc	2424	\brief Clean & Invalidate D-Cache
AnnaBridge	171:3a7713b1edbc	2425	\details Cleans and Invalidates D-Cache
AnnaBridge	171:3a7713b1edbc	2426	*/
AnnaBridge	171:3a7713b1edbc	2427	__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
AnnaBridge	171:3a7713b1edbc	2428	{
AnnaBridge	171:3a7713b1edbc	2429	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	2430	uint32_t ccsidr;
AnnaBridge	171:3a7713b1edbc	2431	uint32_t sets;
AnnaBridge	171:3a7713b1edbc	2432	uint32_t ways;
AnnaBridge	171:3a7713b1edbc	2433
AnnaBridge	171:3a7713b1edbc	2434	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
AnnaBridge	171:3a7713b1edbc	2435	__DSB();
AnnaBridge	171:3a7713b1edbc	2436
AnnaBridge	171:3a7713b1edbc	2437	ccsidr = SCB->CCSIDR;
AnnaBridge	171:3a7713b1edbc	2438
AnnaBridge	171:3a7713b1edbc	2439	/* clean & invalidate D-Cache */
AnnaBridge	171:3a7713b1edbc	2440	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	171:3a7713b1edbc	2441	do {
AnnaBridge	171:3a7713b1edbc	2442	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	171:3a7713b1edbc	2443	do {
AnnaBridge	171:3a7713b1edbc	2444	SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) \|
AnnaBridge	171:3a7713b1edbc	2445	((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
AnnaBridge	171:3a7713b1edbc	2446	#if defined ( __CC_ARM )
AnnaBridge	171:3a7713b1edbc	2447	__schedule_barrier();
AnnaBridge	171:3a7713b1edbc	2448	#endif
AnnaBridge	171:3a7713b1edbc	2449	} while (ways-- != 0U);
AnnaBridge	171:3a7713b1edbc	2450	} while(sets-- != 0U);
AnnaBridge	171:3a7713b1edbc	2451
AnnaBridge	171:3a7713b1edbc	2452	__DSB();
AnnaBridge	171:3a7713b1edbc	2453	__ISB();
AnnaBridge	171:3a7713b1edbc	2454	#endif
AnnaBridge	171:3a7713b1edbc	2455	}
AnnaBridge	171:3a7713b1edbc	2456
AnnaBridge	171:3a7713b1edbc	2457
AnnaBridge	171:3a7713b1edbc	2458	/**
AnnaBridge	171:3a7713b1edbc	2459	\brief D-Cache Invalidate by address
AnnaBridge	171:3a7713b1edbc	2460	\details Invalidates D-Cache for the given address
AnnaBridge	171:3a7713b1edbc	2461	\param[in] addr address (aligned to 32-byte boundary)
AnnaBridge	171:3a7713b1edbc	2462	\param[in] dsize size of memory block (in number of bytes)
AnnaBridge	171:3a7713b1edbc	2463	*/
AnnaBridge	171:3a7713b1edbc	2464	__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
AnnaBridge	171:3a7713b1edbc	2465	{
AnnaBridge	171:3a7713b1edbc	2466	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	2467	int32_t op_size = dsize;
AnnaBridge	171:3a7713b1edbc	2468	uint32_t op_addr = (uint32_t)addr;
AnnaBridge	171:3a7713b1edbc	2469	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
AnnaBridge	171:3a7713b1edbc	2470
AnnaBridge	171:3a7713b1edbc	2471	__DSB();
AnnaBridge	171:3a7713b1edbc	2472
AnnaBridge	171:3a7713b1edbc	2473	while (op_size > 0) {
AnnaBridge	171:3a7713b1edbc	2474	SCB->DCIMVAC = op_addr;
AnnaBridge	171:3a7713b1edbc	2475	op_addr += (uint32_t)linesize;
AnnaBridge	171:3a7713b1edbc	2476	op_size -= linesize;
AnnaBridge	171:3a7713b1edbc	2477	}
AnnaBridge	171:3a7713b1edbc	2478
AnnaBridge	171:3a7713b1edbc	2479	__DSB();
AnnaBridge	171:3a7713b1edbc	2480	__ISB();
AnnaBridge	171:3a7713b1edbc	2481	#endif
AnnaBridge	171:3a7713b1edbc	2482	}
AnnaBridge	171:3a7713b1edbc	2483
AnnaBridge	171:3a7713b1edbc	2484
AnnaBridge	171:3a7713b1edbc	2485	/**
AnnaBridge	171:3a7713b1edbc	2486	\brief D-Cache Clean by address
AnnaBridge	171:3a7713b1edbc	2487	\details Cleans D-Cache for the given address
AnnaBridge	171:3a7713b1edbc	2488	\param[in] addr address (aligned to 32-byte boundary)
AnnaBridge	171:3a7713b1edbc	2489	\param[in] dsize size of memory block (in number of bytes)
AnnaBridge	171:3a7713b1edbc	2490	*/
AnnaBridge	171:3a7713b1edbc	2491	__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
AnnaBridge	171:3a7713b1edbc	2492	{
AnnaBridge	171:3a7713b1edbc	2493	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	2494	int32_t op_size = dsize;
AnnaBridge	171:3a7713b1edbc	2495	uint32_t op_addr = (uint32_t) addr;
AnnaBridge	171:3a7713b1edbc	2496	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
AnnaBridge	171:3a7713b1edbc	2497
AnnaBridge	171:3a7713b1edbc	2498	__DSB();
AnnaBridge	171:3a7713b1edbc	2499
AnnaBridge	171:3a7713b1edbc	2500	while (op_size > 0) {
AnnaBridge	171:3a7713b1edbc	2501	SCB->DCCMVAC = op_addr;
AnnaBridge	171:3a7713b1edbc	2502	op_addr += (uint32_t)linesize;
AnnaBridge	171:3a7713b1edbc	2503	op_size -= linesize;
AnnaBridge	171:3a7713b1edbc	2504	}
AnnaBridge	171:3a7713b1edbc	2505
AnnaBridge	171:3a7713b1edbc	2506	__DSB();
AnnaBridge	171:3a7713b1edbc	2507	__ISB();
AnnaBridge	171:3a7713b1edbc	2508	#endif
AnnaBridge	171:3a7713b1edbc	2509	}
AnnaBridge	171:3a7713b1edbc	2510
AnnaBridge	171:3a7713b1edbc	2511
AnnaBridge	171:3a7713b1edbc	2512	/**
AnnaBridge	171:3a7713b1edbc	2513	\brief D-Cache Clean and Invalidate by address
AnnaBridge	171:3a7713b1edbc	2514	\details Cleans and invalidates D_Cache for the given address
AnnaBridge	171:3a7713b1edbc	2515	\param[in] addr address (aligned to 32-byte boundary)
AnnaBridge	171:3a7713b1edbc	2516	\param[in] dsize size of memory block (in number of bytes)
AnnaBridge	171:3a7713b1edbc	2517	*/
AnnaBridge	171:3a7713b1edbc	2518	__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
AnnaBridge	171:3a7713b1edbc	2519	{
AnnaBridge	171:3a7713b1edbc	2520	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	2521	int32_t op_size = dsize;
AnnaBridge	171:3a7713b1edbc	2522	uint32_t op_addr = (uint32_t) addr;
AnnaBridge	171:3a7713b1edbc	2523	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
AnnaBridge	171:3a7713b1edbc	2524
AnnaBridge	171:3a7713b1edbc	2525	__DSB();
AnnaBridge	171:3a7713b1edbc	2526
AnnaBridge	171:3a7713b1edbc	2527	while (op_size > 0) {
AnnaBridge	171:3a7713b1edbc	2528	SCB->DCCIMVAC = op_addr;
AnnaBridge	171:3a7713b1edbc	2529	op_addr += (uint32_t)linesize;
AnnaBridge	171:3a7713b1edbc	2530	op_size -= linesize;
AnnaBridge	171:3a7713b1edbc	2531	}
AnnaBridge	171:3a7713b1edbc	2532
AnnaBridge	171:3a7713b1edbc	2533	__DSB();
AnnaBridge	171:3a7713b1edbc	2534	__ISB();
AnnaBridge	171:3a7713b1edbc	2535	#endif
AnnaBridge	171:3a7713b1edbc	2536	}
AnnaBridge	171:3a7713b1edbc	2537
AnnaBridge	171:3a7713b1edbc	2538
AnnaBridge	171:3a7713b1edbc	2539	/@} end of CMSIS_Core_CacheFunctions /
AnnaBridge	171:3a7713b1edbc	2540
AnnaBridge	171:3a7713b1edbc	2541
AnnaBridge	171:3a7713b1edbc	2542
AnnaBridge	171:3a7713b1edbc	2543	/* ################################## SysTick function ############################################ */
AnnaBridge	171:3a7713b1edbc	2544	/**
AnnaBridge	171:3a7713b1edbc	2545	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	171:3a7713b1edbc	2546	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge	171:3a7713b1edbc	2547	\brief Functions that configure the System.
AnnaBridge	171:3a7713b1edbc	2548	@{
AnnaBridge	171:3a7713b1edbc	2549	*/
AnnaBridge	171:3a7713b1edbc	2550
AnnaBridge	171:3a7713b1edbc	2551	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge	171:3a7713b1edbc	2552
AnnaBridge	171:3a7713b1edbc	2553	/**
AnnaBridge	171:3a7713b1edbc	2554	\brief System Tick Configuration
AnnaBridge	171:3a7713b1edbc	2555	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge	171:3a7713b1edbc	2556	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	171:3a7713b1edbc	2557	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	171:3a7713b1edbc	2558	\return 0 Function succeeded.
AnnaBridge	171:3a7713b1edbc	2559	\return 1 Function failed.
AnnaBridge	171:3a7713b1edbc	2560	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	171:3a7713b1edbc	2561	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	171:3a7713b1edbc	2562	must contain a vendor-specific implementation of this function.
AnnaBridge	171:3a7713b1edbc	2563	*/
AnnaBridge	171:3a7713b1edbc	2564	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge	171:3a7713b1edbc	2565	{
AnnaBridge	171:3a7713b1edbc	2566	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	171:3a7713b1edbc	2567	{
AnnaBridge	171:3a7713b1edbc	2568	return (1UL); /* Reload value impossible */
AnnaBridge	171:3a7713b1edbc	2569	}
AnnaBridge	171:3a7713b1edbc	2570
AnnaBridge	171:3a7713b1edbc	2571	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge	171:3a7713b1edbc	2572	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge	171:3a7713b1edbc	2573	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge	171:3a7713b1edbc	2574	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
AnnaBridge	171:3a7713b1edbc	2575	SysTick_CTRL_TICKINT_Msk \|
AnnaBridge	171:3a7713b1edbc	2576	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge	171:3a7713b1edbc	2577	return (0UL); /* Function successful */
AnnaBridge	171:3a7713b1edbc	2578	}
AnnaBridge	171:3a7713b1edbc	2579
AnnaBridge	171:3a7713b1edbc	2580	#endif
AnnaBridge	171:3a7713b1edbc	2581
AnnaBridge	171:3a7713b1edbc	2582	/@} end of CMSIS_Core_SysTickFunctions /
AnnaBridge	171:3a7713b1edbc	2583
AnnaBridge	171:3a7713b1edbc	2584
AnnaBridge	171:3a7713b1edbc	2585
AnnaBridge	171:3a7713b1edbc	2586	/* ##################################### Debug In/Output function ########################################### */
AnnaBridge	171:3a7713b1edbc	2587	/**
AnnaBridge	171:3a7713b1edbc	2588	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	171:3a7713b1edbc	2589	\defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge	171:3a7713b1edbc	2590	\brief Functions that access the ITM debug interface.
AnnaBridge	171:3a7713b1edbc	2591	@{
AnnaBridge	171:3a7713b1edbc	2592	*/
AnnaBridge	171:3a7713b1edbc	2593
AnnaBridge	171:3a7713b1edbc	2594	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
AnnaBridge	171:3a7713b1edbc	2595	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
AnnaBridge	171:3a7713b1edbc	2596
AnnaBridge	171:3a7713b1edbc	2597
AnnaBridge	171:3a7713b1edbc	2598	/**
AnnaBridge	171:3a7713b1edbc	2599	\brief ITM Send Character
AnnaBridge	171:3a7713b1edbc	2600	\details Transmits a character via the ITM channel 0, and
AnnaBridge	171:3a7713b1edbc	2601	\li Just returns when no debugger is connected that has booked the output.
AnnaBridge	171:3a7713b1edbc	2602	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge	171:3a7713b1edbc	2603	\param [in] ch Character to transmit.
AnnaBridge	171:3a7713b1edbc	2604	\returns Character to transmit.
AnnaBridge	171:3a7713b1edbc	2605	*/
AnnaBridge	171:3a7713b1edbc	2606	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
AnnaBridge	171:3a7713b1edbc	2607	{
AnnaBridge	171:3a7713b1edbc	2608	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
AnnaBridge	171:3a7713b1edbc	2609	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
AnnaBridge	171:3a7713b1edbc	2610	{
AnnaBridge	171:3a7713b1edbc	2611	while (ITM->PORT[0U].u32 == 0UL)
AnnaBridge	171:3a7713b1edbc	2612	{
AnnaBridge	171:3a7713b1edbc	2613	__NOP();
AnnaBridge	171:3a7713b1edbc	2614	}
AnnaBridge	171:3a7713b1edbc	2615	ITM->PORT[0U].u8 = (uint8_t)ch;
AnnaBridge	171:3a7713b1edbc	2616	}
AnnaBridge	171:3a7713b1edbc	2617	return (ch);
AnnaBridge	171:3a7713b1edbc	2618	}
AnnaBridge	171:3a7713b1edbc	2619
AnnaBridge	171:3a7713b1edbc	2620
AnnaBridge	171:3a7713b1edbc	2621	/**
AnnaBridge	171:3a7713b1edbc	2622	\brief ITM Receive Character
AnnaBridge	171:3a7713b1edbc	2623	\details Inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge	171:3a7713b1edbc	2624	\return Received character.
AnnaBridge	171:3a7713b1edbc	2625	\return -1 No character pending.
AnnaBridge	171:3a7713b1edbc	2626	*/
AnnaBridge	171:3a7713b1edbc	2627	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
AnnaBridge	171:3a7713b1edbc	2628	{
AnnaBridge	171:3a7713b1edbc	2629	int32_t ch = -1; /* no character available */
AnnaBridge	171:3a7713b1edbc	2630
AnnaBridge	171:3a7713b1edbc	2631	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
AnnaBridge	171:3a7713b1edbc	2632	{
AnnaBridge	171:3a7713b1edbc	2633	ch = ITM_RxBuffer;
AnnaBridge	171:3a7713b1edbc	2634	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
AnnaBridge	171:3a7713b1edbc	2635	}
AnnaBridge	171:3a7713b1edbc	2636
AnnaBridge	171:3a7713b1edbc	2637	return (ch);
AnnaBridge	171:3a7713b1edbc	2638	}
AnnaBridge	171:3a7713b1edbc	2639
AnnaBridge	171:3a7713b1edbc	2640
AnnaBridge	171:3a7713b1edbc	2641	/**
AnnaBridge	171:3a7713b1edbc	2642	\brief ITM Check Character
AnnaBridge	171:3a7713b1edbc	2643	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge	171:3a7713b1edbc	2644	\return 0 No character available.
AnnaBridge	171:3a7713b1edbc	2645	\return 1 Character available.
AnnaBridge	171:3a7713b1edbc	2646	*/
AnnaBridge	171:3a7713b1edbc	2647	__STATIC_INLINE int32_t ITM_CheckChar (void)
AnnaBridge	171:3a7713b1edbc	2648	{
AnnaBridge	171:3a7713b1edbc	2649
AnnaBridge	171:3a7713b1edbc	2650	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
AnnaBridge	171:3a7713b1edbc	2651	{
AnnaBridge	171:3a7713b1edbc	2652	return (0); /* no character available */
AnnaBridge	171:3a7713b1edbc	2653	}
AnnaBridge	171:3a7713b1edbc	2654	else
AnnaBridge	171:3a7713b1edbc	2655	{
AnnaBridge	171:3a7713b1edbc	2656	return (1); /* character available */
AnnaBridge	171:3a7713b1edbc	2657	}
AnnaBridge	171:3a7713b1edbc	2658	}
AnnaBridge	171:3a7713b1edbc	2659
AnnaBridge	171:3a7713b1edbc	2660	/@} end of CMSIS_core_DebugFunctions /
AnnaBridge	171:3a7713b1edbc	2661
AnnaBridge	171:3a7713b1edbc	2662
AnnaBridge	171:3a7713b1edbc	2663
AnnaBridge	171:3a7713b1edbc	2664
AnnaBridge	171:3a7713b1edbc	2665	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	2666	}
AnnaBridge	171:3a7713b1edbc	2667	#endif
AnnaBridge	171:3a7713b1edbc	2668
AnnaBridge	171:3a7713b1edbc	2669	#endif /* __CORE_CM7_H_DEPENDANT */
AnnaBridge	171:3a7713b1edbc	2670
AnnaBridge	171:3a7713b1edbc	2671	#endif /* __CMSIS_GENERIC */