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TARGET_LPC1768/TOOLCHAIN_ARM_STD/core_cm23.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/************************************************************************//
AnnaBridge	171:3a7713b1edbc	2	* @file core_cm23.h
AnnaBridge	171:3a7713b1edbc	3	* @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
AnnaBridge	171:3a7713b1edbc	4	* @version V5.0.7
AnnaBridge	171:3a7713b1edbc	5	* @date 22. June 2018
AnnaBridge	171:3a7713b1edbc	6	******************************************************************************/
AnnaBridge	171:3a7713b1edbc	7	/*
AnnaBridge	171:3a7713b1edbc	8	* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
AnnaBridge	171:3a7713b1edbc	9	*
AnnaBridge	171:3a7713b1edbc	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	171:3a7713b1edbc	11	*
AnnaBridge	171:3a7713b1edbc	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	171:3a7713b1edbc	13	* not use this file except in compliance with the License.
AnnaBridge	171:3a7713b1edbc	14	* You may obtain a copy of the License at
AnnaBridge	171:3a7713b1edbc	15	*
AnnaBridge	171:3a7713b1edbc	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	171:3a7713b1edbc	17	*
AnnaBridge	171:3a7713b1edbc	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	171:3a7713b1edbc	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	171:3a7713b1edbc	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	171:3a7713b1edbc	21	* See the License for the specific language governing permissions and
AnnaBridge	171:3a7713b1edbc	22	* limitations under the License.
AnnaBridge	171:3a7713b1edbc	23	*/
AnnaBridge	171:3a7713b1edbc	24
AnnaBridge	171:3a7713b1edbc	25	#if defined ( __ICCARM__ )
AnnaBridge	171:3a7713b1edbc	26	#pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge	171:3a7713b1edbc	27	#elif defined (__clang__)
AnnaBridge	171:3a7713b1edbc	28	#pragma clang system_header /* treat file as system include file */
AnnaBridge	171:3a7713b1edbc	29	#endif
AnnaBridge	171:3a7713b1edbc	30
AnnaBridge	171:3a7713b1edbc	31	#ifndef __CORE_CM23_H_GENERIC
AnnaBridge	171:3a7713b1edbc	32	#define __CORE_CM23_H_GENERIC
AnnaBridge	171:3a7713b1edbc	33
AnnaBridge	171:3a7713b1edbc	34	#include <stdint.h>
AnnaBridge	171:3a7713b1edbc	35
AnnaBridge	171:3a7713b1edbc	36	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	37	extern "C" {
AnnaBridge	171:3a7713b1edbc	38	#endif
AnnaBridge	171:3a7713b1edbc	39
AnnaBridge	171:3a7713b1edbc	40	/**
AnnaBridge	171:3a7713b1edbc	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge	171:3a7713b1edbc	42	CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge	171:3a7713b1edbc	43
AnnaBridge	171:3a7713b1edbc	44	\li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge	171:3a7713b1edbc	45	Function definitions in header files are used to allow 'inlining'.
AnnaBridge	171:3a7713b1edbc	46
AnnaBridge	171:3a7713b1edbc	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge	171:3a7713b1edbc	48	Unions are used for effective representation of core registers.
AnnaBridge	171:3a7713b1edbc	49
AnnaBridge	171:3a7713b1edbc	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge	171:3a7713b1edbc	51	Function-like macros are used to allow more efficient code.
AnnaBridge	171:3a7713b1edbc	52	*/
AnnaBridge	171:3a7713b1edbc	53
AnnaBridge	171:3a7713b1edbc	54
AnnaBridge	171:3a7713b1edbc	55	/*******************************************************************************
AnnaBridge	171:3a7713b1edbc	56	* CMSIS definitions
AnnaBridge	171:3a7713b1edbc	57	******************************************************************************/
AnnaBridge	171:3a7713b1edbc	58	/**
AnnaBridge	171:3a7713b1edbc	59	\ingroup Cortex_M23
AnnaBridge	171:3a7713b1edbc	60	@{
AnnaBridge	171:3a7713b1edbc	61	*/
AnnaBridge	171:3a7713b1edbc	62
AnnaBridge	171:3a7713b1edbc	63	#include "cmsis_version.h"
AnnaBridge	171:3a7713b1edbc	64
AnnaBridge	171:3a7713b1edbc	65	/* CMSIS definitions */
AnnaBridge	171:3a7713b1edbc	66	#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
AnnaBridge	171:3a7713b1edbc	67	#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
AnnaBridge	171:3a7713b1edbc	68	#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) \| \
AnnaBridge	171:3a7713b1edbc	69	__CM23_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
AnnaBridge	171:3a7713b1edbc	70
AnnaBridge	171:3a7713b1edbc	71	#define __CORTEX_M (23U) /!< Cortex-M Core /
AnnaBridge	171:3a7713b1edbc	72
AnnaBridge	171:3a7713b1edbc	73	/** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge	171:3a7713b1edbc	74	This core does not support an FPU at all
AnnaBridge	171:3a7713b1edbc	75	*/
AnnaBridge	171:3a7713b1edbc	76	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	77
AnnaBridge	171:3a7713b1edbc	78	#if defined ( __CC_ARM )
AnnaBridge	171:3a7713b1edbc	79	#if defined __TARGET_FPU_VFP
AnnaBridge	171:3a7713b1edbc	80	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	171:3a7713b1edbc	81	#endif
AnnaBridge	171:3a7713b1edbc	82
AnnaBridge	171:3a7713b1edbc	83	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	172:65be27845400	84	#if defined __ARM_FP
AnnaBridge	171:3a7713b1edbc	85	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	171:3a7713b1edbc	86	#endif
AnnaBridge	171:3a7713b1edbc	87
AnnaBridge	171:3a7713b1edbc	88	#elif defined ( __GNUC__ )
AnnaBridge	171:3a7713b1edbc	89	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge	171:3a7713b1edbc	90	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	171:3a7713b1edbc	91	#endif
AnnaBridge	171:3a7713b1edbc	92
AnnaBridge	171:3a7713b1edbc	93	#elif defined ( __ICCARM__ )
AnnaBridge	171:3a7713b1edbc	94	#if defined __ARMVFP__
AnnaBridge	171:3a7713b1edbc	95	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	171:3a7713b1edbc	96	#endif
AnnaBridge	171:3a7713b1edbc	97
AnnaBridge	171:3a7713b1edbc	98	#elif defined ( __TI_ARM__ )
AnnaBridge	171:3a7713b1edbc	99	#if defined __TI_VFP_SUPPORT__
AnnaBridge	171:3a7713b1edbc	100	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	171:3a7713b1edbc	101	#endif
AnnaBridge	171:3a7713b1edbc	102
AnnaBridge	171:3a7713b1edbc	103	#elif defined ( __TASKING__ )
AnnaBridge	171:3a7713b1edbc	104	#if defined __FPU_VFP__
AnnaBridge	171:3a7713b1edbc	105	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	171:3a7713b1edbc	106	#endif
AnnaBridge	171:3a7713b1edbc	107
AnnaBridge	171:3a7713b1edbc	108	#elif defined ( __CSMC__ )
AnnaBridge	171:3a7713b1edbc	109	#if ( __CSMC__ & 0x400U)
AnnaBridge	171:3a7713b1edbc	110	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	171:3a7713b1edbc	111	#endif
AnnaBridge	171:3a7713b1edbc	112
AnnaBridge	171:3a7713b1edbc	113	#endif
AnnaBridge	171:3a7713b1edbc	114
AnnaBridge	171:3a7713b1edbc	115	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge	171:3a7713b1edbc	116
AnnaBridge	171:3a7713b1edbc	117
AnnaBridge	171:3a7713b1edbc	118	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	119	}
AnnaBridge	171:3a7713b1edbc	120	#endif
AnnaBridge	171:3a7713b1edbc	121
AnnaBridge	171:3a7713b1edbc	122	#endif /* __CORE_CM23_H_GENERIC */
AnnaBridge	171:3a7713b1edbc	123
AnnaBridge	171:3a7713b1edbc	124	#ifndef __CMSIS_GENERIC
AnnaBridge	171:3a7713b1edbc	125
AnnaBridge	171:3a7713b1edbc	126	#ifndef __CORE_CM23_H_DEPENDANT
AnnaBridge	171:3a7713b1edbc	127	#define __CORE_CM23_H_DEPENDANT
AnnaBridge	171:3a7713b1edbc	128
AnnaBridge	171:3a7713b1edbc	129	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	130	extern "C" {
AnnaBridge	171:3a7713b1edbc	131	#endif
AnnaBridge	171:3a7713b1edbc	132
AnnaBridge	171:3a7713b1edbc	133	/* check device defines and use defaults */
AnnaBridge	171:3a7713b1edbc	134	#if defined __CHECK_DEVICE_DEFINES
AnnaBridge	171:3a7713b1edbc	135	#ifndef __CM23_REV
AnnaBridge	171:3a7713b1edbc	136	#define __CM23_REV 0x0000U
AnnaBridge	171:3a7713b1edbc	137	#warning "__CM23_REV not defined in device header file; using default!"
AnnaBridge	171:3a7713b1edbc	138	#endif
AnnaBridge	171:3a7713b1edbc	139
AnnaBridge	171:3a7713b1edbc	140	#ifndef __FPU_PRESENT
AnnaBridge	171:3a7713b1edbc	141	#define __FPU_PRESENT 0U
AnnaBridge	171:3a7713b1edbc	142	#warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge	171:3a7713b1edbc	143	#endif
AnnaBridge	171:3a7713b1edbc	144
AnnaBridge	171:3a7713b1edbc	145	#ifndef __MPU_PRESENT
AnnaBridge	171:3a7713b1edbc	146	#define __MPU_PRESENT 0U
AnnaBridge	171:3a7713b1edbc	147	#warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge	171:3a7713b1edbc	148	#endif
AnnaBridge	171:3a7713b1edbc	149
AnnaBridge	171:3a7713b1edbc	150	#ifndef __SAUREGION_PRESENT
AnnaBridge	171:3a7713b1edbc	151	#define __SAUREGION_PRESENT 0U
AnnaBridge	171:3a7713b1edbc	152	#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
AnnaBridge	171:3a7713b1edbc	153	#endif
AnnaBridge	171:3a7713b1edbc	154
AnnaBridge	171:3a7713b1edbc	155	#ifndef __VTOR_PRESENT
AnnaBridge	171:3a7713b1edbc	156	#define __VTOR_PRESENT 0U
AnnaBridge	171:3a7713b1edbc	157	#warning "__VTOR_PRESENT not defined in device header file; using default!"
AnnaBridge	171:3a7713b1edbc	158	#endif
AnnaBridge	171:3a7713b1edbc	159
AnnaBridge	171:3a7713b1edbc	160	#ifndef __NVIC_PRIO_BITS
AnnaBridge	171:3a7713b1edbc	161	#define __NVIC_PRIO_BITS 2U
AnnaBridge	171:3a7713b1edbc	162	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge	171:3a7713b1edbc	163	#endif
AnnaBridge	171:3a7713b1edbc	164
AnnaBridge	171:3a7713b1edbc	165	#ifndef __Vendor_SysTickConfig
AnnaBridge	171:3a7713b1edbc	166	#define __Vendor_SysTickConfig 0U
AnnaBridge	171:3a7713b1edbc	167	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge	171:3a7713b1edbc	168	#endif
AnnaBridge	171:3a7713b1edbc	169
AnnaBridge	171:3a7713b1edbc	170	#ifndef __ETM_PRESENT
AnnaBridge	171:3a7713b1edbc	171	#define __ETM_PRESENT 0U
AnnaBridge	171:3a7713b1edbc	172	#warning "__ETM_PRESENT not defined in device header file; using default!"
AnnaBridge	171:3a7713b1edbc	173	#endif
AnnaBridge	171:3a7713b1edbc	174
AnnaBridge	171:3a7713b1edbc	175	#ifndef __MTB_PRESENT
AnnaBridge	171:3a7713b1edbc	176	#define __MTB_PRESENT 0U
AnnaBridge	171:3a7713b1edbc	177	#warning "__MTB_PRESENT not defined in device header file; using default!"
AnnaBridge	171:3a7713b1edbc	178	#endif
AnnaBridge	171:3a7713b1edbc	179
AnnaBridge	171:3a7713b1edbc	180	#endif
AnnaBridge	171:3a7713b1edbc	181
AnnaBridge	171:3a7713b1edbc	182	/* IO definitions (access restrictions to peripheral registers) */
AnnaBridge	171:3a7713b1edbc	183	/**
AnnaBridge	171:3a7713b1edbc	184	\defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge	171:3a7713b1edbc	185
AnnaBridge	171:3a7713b1edbc	186	<strong>IO Type Qualifiers</strong> are used
AnnaBridge	171:3a7713b1edbc	187	\li to specify the access to peripheral variables.
AnnaBridge	171:3a7713b1edbc	188	\li for automatic generation of peripheral register debug information.
AnnaBridge	171:3a7713b1edbc	189	*/
AnnaBridge	171:3a7713b1edbc	190	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	191	#define __I volatile /!< Defines 'read only' permissions /
AnnaBridge	171:3a7713b1edbc	192	#else
AnnaBridge	171:3a7713b1edbc	193	#define __I volatile const /!< Defines 'read only' permissions /
AnnaBridge	171:3a7713b1edbc	194	#endif
AnnaBridge	171:3a7713b1edbc	195	#define __O volatile /!< Defines 'write only' permissions /
AnnaBridge	171:3a7713b1edbc	196	#define __IO volatile /!< Defines 'read / write' permissions /
AnnaBridge	171:3a7713b1edbc	197
AnnaBridge	171:3a7713b1edbc	198	/* following defines should be used for structure members */
AnnaBridge	171:3a7713b1edbc	199	#define __IM volatile const /! Defines 'read only' structure member permissions /
AnnaBridge	171:3a7713b1edbc	200	#define __OM volatile /! Defines 'write only' structure member permissions /
AnnaBridge	171:3a7713b1edbc	201	#define __IOM volatile /! Defines 'read / write' structure member permissions /
AnnaBridge	171:3a7713b1edbc	202
AnnaBridge	171:3a7713b1edbc	203	/@} end of group Cortex_M23 /
AnnaBridge	171:3a7713b1edbc	204
AnnaBridge	171:3a7713b1edbc	205
AnnaBridge	171:3a7713b1edbc	206
AnnaBridge	171:3a7713b1edbc	207	/*******************************************************************************
AnnaBridge	171:3a7713b1edbc	208	* Register Abstraction
AnnaBridge	171:3a7713b1edbc	209	Core Register contain:
AnnaBridge	171:3a7713b1edbc	210	- Core Register
AnnaBridge	171:3a7713b1edbc	211	- Core NVIC Register
AnnaBridge	171:3a7713b1edbc	212	- Core SCB Register
AnnaBridge	171:3a7713b1edbc	213	- Core SysTick Register
AnnaBridge	171:3a7713b1edbc	214	- Core Debug Register
AnnaBridge	171:3a7713b1edbc	215	- Core MPU Register
AnnaBridge	171:3a7713b1edbc	216	- Core SAU Register
AnnaBridge	171:3a7713b1edbc	217	******************************************************************************/
AnnaBridge	171:3a7713b1edbc	218	/**
AnnaBridge	171:3a7713b1edbc	219	\defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge	171:3a7713b1edbc	220	\brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge	171:3a7713b1edbc	221	*/
AnnaBridge	171:3a7713b1edbc	222
AnnaBridge	171:3a7713b1edbc	223	/**
AnnaBridge	171:3a7713b1edbc	224	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	225	\defgroup CMSIS_CORE Status and Control Registers
AnnaBridge	171:3a7713b1edbc	226	\brief Core Register type definitions.
AnnaBridge	171:3a7713b1edbc	227	@{
AnnaBridge	171:3a7713b1edbc	228	*/
AnnaBridge	171:3a7713b1edbc	229
AnnaBridge	171:3a7713b1edbc	230	/**
AnnaBridge	171:3a7713b1edbc	231	\brief Union type to access the Application Program Status Register (APSR).
AnnaBridge	171:3a7713b1edbc	232	*/
AnnaBridge	171:3a7713b1edbc	233	typedef union
AnnaBridge	171:3a7713b1edbc	234	{
AnnaBridge	171:3a7713b1edbc	235	struct
AnnaBridge	171:3a7713b1edbc	236	{
AnnaBridge	171:3a7713b1edbc	237	uint32_t _reserved0:28; /!< bit: 0..27 Reserved /
AnnaBridge	171:3a7713b1edbc	238	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	171:3a7713b1edbc	239	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	171:3a7713b1edbc	240	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	171:3a7713b1edbc	241	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	171:3a7713b1edbc	242	} b; /!< Structure used for bit access /
AnnaBridge	171:3a7713b1edbc	243	uint32_t w; /!< Type used for word access /
AnnaBridge	171:3a7713b1edbc	244	} APSR_Type;
AnnaBridge	171:3a7713b1edbc	245
AnnaBridge	171:3a7713b1edbc	246	/* APSR Register Definitions */
AnnaBridge	171:3a7713b1edbc	247	#define APSR_N_Pos 31U /!< APSR: N Position /
AnnaBridge	171:3a7713b1edbc	248	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
AnnaBridge	171:3a7713b1edbc	249
AnnaBridge	171:3a7713b1edbc	250	#define APSR_Z_Pos 30U /!< APSR: Z Position /
AnnaBridge	171:3a7713b1edbc	251	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
AnnaBridge	171:3a7713b1edbc	252
AnnaBridge	171:3a7713b1edbc	253	#define APSR_C_Pos 29U /!< APSR: C Position /
AnnaBridge	171:3a7713b1edbc	254	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
AnnaBridge	171:3a7713b1edbc	255
AnnaBridge	171:3a7713b1edbc	256	#define APSR_V_Pos 28U /!< APSR: V Position /
AnnaBridge	171:3a7713b1edbc	257	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
AnnaBridge	171:3a7713b1edbc	258
AnnaBridge	171:3a7713b1edbc	259
AnnaBridge	171:3a7713b1edbc	260	/**
AnnaBridge	171:3a7713b1edbc	261	\brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge	171:3a7713b1edbc	262	*/
AnnaBridge	171:3a7713b1edbc	263	typedef union
AnnaBridge	171:3a7713b1edbc	264	{
AnnaBridge	171:3a7713b1edbc	265	struct
AnnaBridge	171:3a7713b1edbc	266	{
AnnaBridge	171:3a7713b1edbc	267	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	171:3a7713b1edbc	268	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
AnnaBridge	171:3a7713b1edbc	269	} b; /!< Structure used for bit access /
AnnaBridge	171:3a7713b1edbc	270	uint32_t w; /!< Type used for word access /
AnnaBridge	171:3a7713b1edbc	271	} IPSR_Type;
AnnaBridge	171:3a7713b1edbc	272
AnnaBridge	171:3a7713b1edbc	273	/* IPSR Register Definitions */
AnnaBridge	171:3a7713b1edbc	274	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
AnnaBridge	171:3a7713b1edbc	275	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
AnnaBridge	171:3a7713b1edbc	276
AnnaBridge	171:3a7713b1edbc	277
AnnaBridge	171:3a7713b1edbc	278	/**
AnnaBridge	171:3a7713b1edbc	279	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge	171:3a7713b1edbc	280	*/
AnnaBridge	171:3a7713b1edbc	281	typedef union
AnnaBridge	171:3a7713b1edbc	282	{
AnnaBridge	171:3a7713b1edbc	283	struct
AnnaBridge	171:3a7713b1edbc	284	{
AnnaBridge	171:3a7713b1edbc	285	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	171:3a7713b1edbc	286	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
AnnaBridge	171:3a7713b1edbc	287	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
AnnaBridge	171:3a7713b1edbc	288	uint32_t _reserved1:3; /!< bit: 25..27 Reserved /
AnnaBridge	171:3a7713b1edbc	289	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	171:3a7713b1edbc	290	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	171:3a7713b1edbc	291	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	171:3a7713b1edbc	292	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	171:3a7713b1edbc	293	} b; /!< Structure used for bit access /
AnnaBridge	171:3a7713b1edbc	294	uint32_t w; /!< Type used for word access /
AnnaBridge	171:3a7713b1edbc	295	} xPSR_Type;
AnnaBridge	171:3a7713b1edbc	296
AnnaBridge	171:3a7713b1edbc	297	/* xPSR Register Definitions */
AnnaBridge	171:3a7713b1edbc	298	#define xPSR_N_Pos 31U /!< xPSR: N Position /
AnnaBridge	171:3a7713b1edbc	299	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
AnnaBridge	171:3a7713b1edbc	300
AnnaBridge	171:3a7713b1edbc	301	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
AnnaBridge	171:3a7713b1edbc	302	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
AnnaBridge	171:3a7713b1edbc	303
AnnaBridge	171:3a7713b1edbc	304	#define xPSR_C_Pos 29U /!< xPSR: C Position /
AnnaBridge	171:3a7713b1edbc	305	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
AnnaBridge	171:3a7713b1edbc	306
AnnaBridge	171:3a7713b1edbc	307	#define xPSR_V_Pos 28U /!< xPSR: V Position /
AnnaBridge	171:3a7713b1edbc	308	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
AnnaBridge	171:3a7713b1edbc	309
AnnaBridge	171:3a7713b1edbc	310	#define xPSR_T_Pos 24U /!< xPSR: T Position /
AnnaBridge	171:3a7713b1edbc	311	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
AnnaBridge	171:3a7713b1edbc	312
AnnaBridge	171:3a7713b1edbc	313	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
AnnaBridge	171:3a7713b1edbc	314	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
AnnaBridge	171:3a7713b1edbc	315
AnnaBridge	171:3a7713b1edbc	316
AnnaBridge	171:3a7713b1edbc	317	/**
AnnaBridge	171:3a7713b1edbc	318	\brief Union type to access the Control Registers (CONTROL).
AnnaBridge	171:3a7713b1edbc	319	*/
AnnaBridge	171:3a7713b1edbc	320	typedef union
AnnaBridge	171:3a7713b1edbc	321	{
AnnaBridge	171:3a7713b1edbc	322	struct
AnnaBridge	171:3a7713b1edbc	323	{
AnnaBridge	171:3a7713b1edbc	324	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
AnnaBridge	171:3a7713b1edbc	325	uint32_t SPSEL:1; /!< bit: 1 Stack-pointer select /
AnnaBridge	171:3a7713b1edbc	326	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
AnnaBridge	171:3a7713b1edbc	327	} b; /!< Structure used for bit access /
AnnaBridge	171:3a7713b1edbc	328	uint32_t w; /!< Type used for word access /
AnnaBridge	171:3a7713b1edbc	329	} CONTROL_Type;
AnnaBridge	171:3a7713b1edbc	330
AnnaBridge	171:3a7713b1edbc	331	/* CONTROL Register Definitions */
AnnaBridge	171:3a7713b1edbc	332	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
AnnaBridge	171:3a7713b1edbc	333	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
AnnaBridge	171:3a7713b1edbc	334
AnnaBridge	171:3a7713b1edbc	335	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
AnnaBridge	171:3a7713b1edbc	336	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
AnnaBridge	171:3a7713b1edbc	337
AnnaBridge	171:3a7713b1edbc	338	/@} end of group CMSIS_CORE /
AnnaBridge	171:3a7713b1edbc	339
AnnaBridge	171:3a7713b1edbc	340
AnnaBridge	171:3a7713b1edbc	341	/**
AnnaBridge	171:3a7713b1edbc	342	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	343	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge	171:3a7713b1edbc	344	\brief Type definitions for the NVIC Registers
AnnaBridge	171:3a7713b1edbc	345	@{
AnnaBridge	171:3a7713b1edbc	346	*/
AnnaBridge	171:3a7713b1edbc	347
AnnaBridge	171:3a7713b1edbc	348	/**
AnnaBridge	171:3a7713b1edbc	349	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge	171:3a7713b1edbc	350	*/
AnnaBridge	171:3a7713b1edbc	351	typedef struct
AnnaBridge	171:3a7713b1edbc	352	{
AnnaBridge	171:3a7713b1edbc	353	__IOM uint32_t ISER[16U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
AnnaBridge	171:3a7713b1edbc	354	uint32_t RESERVED0[16U];
AnnaBridge	171:3a7713b1edbc	355	__IOM uint32_t ICER[16U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
AnnaBridge	171:3a7713b1edbc	356	uint32_t RSERVED1[16U];
AnnaBridge	171:3a7713b1edbc	357	__IOM uint32_t ISPR[16U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
AnnaBridge	171:3a7713b1edbc	358	uint32_t RESERVED2[16U];
AnnaBridge	171:3a7713b1edbc	359	__IOM uint32_t ICPR[16U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
AnnaBridge	171:3a7713b1edbc	360	uint32_t RESERVED3[16U];
AnnaBridge	171:3a7713b1edbc	361	__IOM uint32_t IABR[16U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
AnnaBridge	171:3a7713b1edbc	362	uint32_t RESERVED4[16U];
AnnaBridge	171:3a7713b1edbc	363	__IOM uint32_t ITNS[16U]; /!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register /
AnnaBridge	171:3a7713b1edbc	364	uint32_t RESERVED5[16U];
AnnaBridge	171:3a7713b1edbc	365	__IOM uint32_t IPR[124U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register /
AnnaBridge	171:3a7713b1edbc	366	} NVIC_Type;
AnnaBridge	171:3a7713b1edbc	367
AnnaBridge	171:3a7713b1edbc	368	/@} end of group CMSIS_NVIC /
AnnaBridge	171:3a7713b1edbc	369
AnnaBridge	171:3a7713b1edbc	370
AnnaBridge	171:3a7713b1edbc	371	/**
AnnaBridge	171:3a7713b1edbc	372	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	373	\defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge	171:3a7713b1edbc	374	\brief Type definitions for the System Control Block Registers
AnnaBridge	171:3a7713b1edbc	375	@{
AnnaBridge	171:3a7713b1edbc	376	*/
AnnaBridge	171:3a7713b1edbc	377
AnnaBridge	171:3a7713b1edbc	378	/**
AnnaBridge	171:3a7713b1edbc	379	\brief Structure type to access the System Control Block (SCB).
AnnaBridge	171:3a7713b1edbc	380	*/
AnnaBridge	171:3a7713b1edbc	381	typedef struct
AnnaBridge	171:3a7713b1edbc	382	{
AnnaBridge	171:3a7713b1edbc	383	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
AnnaBridge	171:3a7713b1edbc	384	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
AnnaBridge	171:3a7713b1edbc	385	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	386	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
AnnaBridge	171:3a7713b1edbc	387	#else
AnnaBridge	171:3a7713b1edbc	388	uint32_t RESERVED0;
AnnaBridge	171:3a7713b1edbc	389	#endif
AnnaBridge	171:3a7713b1edbc	390	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
AnnaBridge	171:3a7713b1edbc	391	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
AnnaBridge	171:3a7713b1edbc	392	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
AnnaBridge	171:3a7713b1edbc	393	uint32_t RESERVED1;
AnnaBridge	171:3a7713b1edbc	394	__IOM uint32_t SHPR[2U]; /!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED /
AnnaBridge	171:3a7713b1edbc	395	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
AnnaBridge	171:3a7713b1edbc	396	} SCB_Type;
AnnaBridge	171:3a7713b1edbc	397
AnnaBridge	171:3a7713b1edbc	398	/* SCB CPUID Register Definitions */
AnnaBridge	171:3a7713b1edbc	399	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
AnnaBridge	171:3a7713b1edbc	400	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
AnnaBridge	171:3a7713b1edbc	401
AnnaBridge	171:3a7713b1edbc	402	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
AnnaBridge	171:3a7713b1edbc	403	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
AnnaBridge	171:3a7713b1edbc	404
AnnaBridge	171:3a7713b1edbc	405	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
AnnaBridge	171:3a7713b1edbc	406	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
AnnaBridge	171:3a7713b1edbc	407
AnnaBridge	171:3a7713b1edbc	408	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
AnnaBridge	171:3a7713b1edbc	409	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
AnnaBridge	171:3a7713b1edbc	410
AnnaBridge	171:3a7713b1edbc	411	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
AnnaBridge	171:3a7713b1edbc	412	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
AnnaBridge	171:3a7713b1edbc	413
AnnaBridge	171:3a7713b1edbc	414	/* SCB Interrupt Control State Register Definitions */
AnnaBridge	171:3a7713b1edbc	415	#define SCB_ICSR_PENDNMISET_Pos 31U /!< SCB ICSR: PENDNMISET Position /
AnnaBridge	171:3a7713b1edbc	416	#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /!< SCB ICSR: PENDNMISET Mask /
AnnaBridge	171:3a7713b1edbc	417
AnnaBridge	171:3a7713b1edbc	418	#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /!< SCB ICSR: NMIPENDSET Position, backward compatibility /
AnnaBridge	171:3a7713b1edbc	419	#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /!< SCB ICSR: NMIPENDSET Mask, backward compatibility /
AnnaBridge	171:3a7713b1edbc	420
AnnaBridge	171:3a7713b1edbc	421	#define SCB_ICSR_PENDNMICLR_Pos 30U /!< SCB ICSR: PENDNMICLR Position /
AnnaBridge	171:3a7713b1edbc	422	#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /!< SCB ICSR: PENDNMICLR Mask /
AnnaBridge	171:3a7713b1edbc	423
AnnaBridge	171:3a7713b1edbc	424	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
AnnaBridge	171:3a7713b1edbc	425	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
AnnaBridge	171:3a7713b1edbc	426
AnnaBridge	171:3a7713b1edbc	427	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
AnnaBridge	171:3a7713b1edbc	428	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
AnnaBridge	171:3a7713b1edbc	429
AnnaBridge	171:3a7713b1edbc	430	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
AnnaBridge	171:3a7713b1edbc	431	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
AnnaBridge	171:3a7713b1edbc	432
AnnaBridge	171:3a7713b1edbc	433	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
AnnaBridge	171:3a7713b1edbc	434	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
AnnaBridge	171:3a7713b1edbc	435
AnnaBridge	171:3a7713b1edbc	436	#define SCB_ICSR_STTNS_Pos 24U /!< SCB ICSR: STTNS Position (Security Extension) /
AnnaBridge	171:3a7713b1edbc	437	#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /!< SCB ICSR: STTNS Mask (Security Extension) /
AnnaBridge	171:3a7713b1edbc	438
AnnaBridge	171:3a7713b1edbc	439	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
AnnaBridge	171:3a7713b1edbc	440	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
AnnaBridge	171:3a7713b1edbc	441
AnnaBridge	171:3a7713b1edbc	442	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
AnnaBridge	171:3a7713b1edbc	443	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
AnnaBridge	171:3a7713b1edbc	444
AnnaBridge	171:3a7713b1edbc	445	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
AnnaBridge	171:3a7713b1edbc	446	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
AnnaBridge	171:3a7713b1edbc	447
AnnaBridge	171:3a7713b1edbc	448	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
AnnaBridge	171:3a7713b1edbc	449	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
AnnaBridge	171:3a7713b1edbc	450
AnnaBridge	171:3a7713b1edbc	451	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
AnnaBridge	171:3a7713b1edbc	452	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
AnnaBridge	171:3a7713b1edbc	453
AnnaBridge	171:3a7713b1edbc	454	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	455	/* SCB Vector Table Offset Register Definitions */
AnnaBridge	171:3a7713b1edbc	456	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
AnnaBridge	171:3a7713b1edbc	457	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
AnnaBridge	171:3a7713b1edbc	458	#endif
AnnaBridge	171:3a7713b1edbc	459
AnnaBridge	171:3a7713b1edbc	460	/* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	461	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
AnnaBridge	171:3a7713b1edbc	462	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
AnnaBridge	171:3a7713b1edbc	463
AnnaBridge	171:3a7713b1edbc	464	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
AnnaBridge	171:3a7713b1edbc	465	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
AnnaBridge	171:3a7713b1edbc	466
AnnaBridge	171:3a7713b1edbc	467	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
AnnaBridge	171:3a7713b1edbc	468	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
AnnaBridge	171:3a7713b1edbc	469
AnnaBridge	171:3a7713b1edbc	470	#define SCB_AIRCR_PRIS_Pos 14U /!< SCB AIRCR: PRIS Position /
AnnaBridge	171:3a7713b1edbc	471	#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /!< SCB AIRCR: PRIS Mask /
AnnaBridge	171:3a7713b1edbc	472
AnnaBridge	171:3a7713b1edbc	473	#define SCB_AIRCR_BFHFNMINS_Pos 13U /!< SCB AIRCR: BFHFNMINS Position /
AnnaBridge	171:3a7713b1edbc	474	#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /!< SCB AIRCR: BFHFNMINS Mask /
AnnaBridge	171:3a7713b1edbc	475
AnnaBridge	171:3a7713b1edbc	476	#define SCB_AIRCR_SYSRESETREQS_Pos 3U /!< SCB AIRCR: SYSRESETREQS Position /
AnnaBridge	171:3a7713b1edbc	477	#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /!< SCB AIRCR: SYSRESETREQS Mask /
AnnaBridge	171:3a7713b1edbc	478
AnnaBridge	171:3a7713b1edbc	479	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
AnnaBridge	171:3a7713b1edbc	480	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
AnnaBridge	171:3a7713b1edbc	481
AnnaBridge	171:3a7713b1edbc	482	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
AnnaBridge	171:3a7713b1edbc	483	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
AnnaBridge	171:3a7713b1edbc	484
AnnaBridge	171:3a7713b1edbc	485	/* SCB System Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	486	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
AnnaBridge	171:3a7713b1edbc	487	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
AnnaBridge	171:3a7713b1edbc	488
AnnaBridge	171:3a7713b1edbc	489	#define SCB_SCR_SLEEPDEEPS_Pos 3U /!< SCB SCR: SLEEPDEEPS Position /
AnnaBridge	171:3a7713b1edbc	490	#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /!< SCB SCR: SLEEPDEEPS Mask /
AnnaBridge	171:3a7713b1edbc	491
AnnaBridge	171:3a7713b1edbc	492	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
AnnaBridge	171:3a7713b1edbc	493	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
AnnaBridge	171:3a7713b1edbc	494
AnnaBridge	171:3a7713b1edbc	495	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
AnnaBridge	171:3a7713b1edbc	496	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
AnnaBridge	171:3a7713b1edbc	497
AnnaBridge	171:3a7713b1edbc	498	/* SCB Configuration Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	499	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: BP Position /
AnnaBridge	171:3a7713b1edbc	500	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: BP Mask /
AnnaBridge	171:3a7713b1edbc	501
AnnaBridge	171:3a7713b1edbc	502	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: IC Position /
AnnaBridge	171:3a7713b1edbc	503	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: IC Mask /
AnnaBridge	171:3a7713b1edbc	504
AnnaBridge	171:3a7713b1edbc	505	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: DC Position /
AnnaBridge	171:3a7713b1edbc	506	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: DC Mask /
AnnaBridge	171:3a7713b1edbc	507
AnnaBridge	171:3a7713b1edbc	508	#define SCB_CCR_STKOFHFNMIGN_Pos 10U /!< SCB CCR: STKOFHFNMIGN Position /
AnnaBridge	171:3a7713b1edbc	509	#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /!< SCB CCR: STKOFHFNMIGN Mask /
AnnaBridge	171:3a7713b1edbc	510
AnnaBridge	171:3a7713b1edbc	511	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
AnnaBridge	171:3a7713b1edbc	512	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
AnnaBridge	171:3a7713b1edbc	513
AnnaBridge	171:3a7713b1edbc	514	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
AnnaBridge	171:3a7713b1edbc	515	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
AnnaBridge	171:3a7713b1edbc	516
AnnaBridge	171:3a7713b1edbc	517	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
AnnaBridge	171:3a7713b1edbc	518	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
AnnaBridge	171:3a7713b1edbc	519
AnnaBridge	171:3a7713b1edbc	520	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
AnnaBridge	171:3a7713b1edbc	521	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
AnnaBridge	171:3a7713b1edbc	522
AnnaBridge	171:3a7713b1edbc	523	/* SCB System Handler Control and State Register Definitions */
AnnaBridge	171:3a7713b1edbc	524	#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /!< SCB SHCSR: HARDFAULTPENDED Position /
AnnaBridge	171:3a7713b1edbc	525	#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /!< SCB SHCSR: HARDFAULTPENDED Mask /
AnnaBridge	171:3a7713b1edbc	526
AnnaBridge	171:3a7713b1edbc	527	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
AnnaBridge	171:3a7713b1edbc	528	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
AnnaBridge	171:3a7713b1edbc	529
AnnaBridge	171:3a7713b1edbc	530	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
AnnaBridge	171:3a7713b1edbc	531	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
AnnaBridge	171:3a7713b1edbc	532
AnnaBridge	171:3a7713b1edbc	533	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
AnnaBridge	171:3a7713b1edbc	534	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
AnnaBridge	171:3a7713b1edbc	535
AnnaBridge	171:3a7713b1edbc	536	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
AnnaBridge	171:3a7713b1edbc	537	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
AnnaBridge	171:3a7713b1edbc	538
AnnaBridge	171:3a7713b1edbc	539	#define SCB_SHCSR_NMIACT_Pos 5U /!< SCB SHCSR: NMIACT Position /
AnnaBridge	171:3a7713b1edbc	540	#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /!< SCB SHCSR: NMIACT Mask /
AnnaBridge	171:3a7713b1edbc	541
AnnaBridge	171:3a7713b1edbc	542	#define SCB_SHCSR_HARDFAULTACT_Pos 2U /!< SCB SHCSR: HARDFAULTACT Position /
AnnaBridge	171:3a7713b1edbc	543	#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /!< SCB SHCSR: HARDFAULTACT Mask /
AnnaBridge	171:3a7713b1edbc	544
AnnaBridge	171:3a7713b1edbc	545	/@} end of group CMSIS_SCB /
AnnaBridge	171:3a7713b1edbc	546
AnnaBridge	171:3a7713b1edbc	547
AnnaBridge	171:3a7713b1edbc	548	/**
AnnaBridge	171:3a7713b1edbc	549	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	550	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge	171:3a7713b1edbc	551	\brief Type definitions for the System Timer Registers.
AnnaBridge	171:3a7713b1edbc	552	@{
AnnaBridge	171:3a7713b1edbc	553	*/
AnnaBridge	171:3a7713b1edbc	554
AnnaBridge	171:3a7713b1edbc	555	/**
AnnaBridge	171:3a7713b1edbc	556	\brief Structure type to access the System Timer (SysTick).
AnnaBridge	171:3a7713b1edbc	557	*/
AnnaBridge	171:3a7713b1edbc	558	typedef struct
AnnaBridge	171:3a7713b1edbc	559	{
AnnaBridge	171:3a7713b1edbc	560	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
AnnaBridge	171:3a7713b1edbc	561	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
AnnaBridge	171:3a7713b1edbc	562	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
AnnaBridge	171:3a7713b1edbc	563	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
AnnaBridge	171:3a7713b1edbc	564	} SysTick_Type;
AnnaBridge	171:3a7713b1edbc	565
AnnaBridge	171:3a7713b1edbc	566	/* SysTick Control / Status Register Definitions */
AnnaBridge	171:3a7713b1edbc	567	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
AnnaBridge	171:3a7713b1edbc	568	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
AnnaBridge	171:3a7713b1edbc	569
AnnaBridge	171:3a7713b1edbc	570	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
AnnaBridge	171:3a7713b1edbc	571	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
AnnaBridge	171:3a7713b1edbc	572
AnnaBridge	171:3a7713b1edbc	573	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
AnnaBridge	171:3a7713b1edbc	574	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
AnnaBridge	171:3a7713b1edbc	575
AnnaBridge	171:3a7713b1edbc	576	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
AnnaBridge	171:3a7713b1edbc	577	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
AnnaBridge	171:3a7713b1edbc	578
AnnaBridge	171:3a7713b1edbc	579	/* SysTick Reload Register Definitions */
AnnaBridge	171:3a7713b1edbc	580	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
AnnaBridge	171:3a7713b1edbc	581	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
AnnaBridge	171:3a7713b1edbc	582
AnnaBridge	171:3a7713b1edbc	583	/* SysTick Current Register Definitions */
AnnaBridge	171:3a7713b1edbc	584	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
AnnaBridge	171:3a7713b1edbc	585	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
AnnaBridge	171:3a7713b1edbc	586
AnnaBridge	171:3a7713b1edbc	587	/* SysTick Calibration Register Definitions */
AnnaBridge	171:3a7713b1edbc	588	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
AnnaBridge	171:3a7713b1edbc	589	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
AnnaBridge	171:3a7713b1edbc	590
AnnaBridge	171:3a7713b1edbc	591	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
AnnaBridge	171:3a7713b1edbc	592	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
AnnaBridge	171:3a7713b1edbc	593
AnnaBridge	171:3a7713b1edbc	594	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
AnnaBridge	171:3a7713b1edbc	595	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
AnnaBridge	171:3a7713b1edbc	596
AnnaBridge	171:3a7713b1edbc	597	/@} end of group CMSIS_SysTick /
AnnaBridge	171:3a7713b1edbc	598
AnnaBridge	171:3a7713b1edbc	599
AnnaBridge	171:3a7713b1edbc	600	/**
AnnaBridge	171:3a7713b1edbc	601	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	602	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge	171:3a7713b1edbc	603	\brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge	171:3a7713b1edbc	604	@{
AnnaBridge	171:3a7713b1edbc	605	*/
AnnaBridge	171:3a7713b1edbc	606
AnnaBridge	171:3a7713b1edbc	607	/**
AnnaBridge	171:3a7713b1edbc	608	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge	171:3a7713b1edbc	609	*/
AnnaBridge	171:3a7713b1edbc	610	typedef struct
AnnaBridge	171:3a7713b1edbc	611	{
AnnaBridge	171:3a7713b1edbc	612	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
AnnaBridge	171:3a7713b1edbc	613	uint32_t RESERVED0[6U];
AnnaBridge	171:3a7713b1edbc	614	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
AnnaBridge	171:3a7713b1edbc	615	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
AnnaBridge	171:3a7713b1edbc	616	uint32_t RESERVED1[1U];
AnnaBridge	171:3a7713b1edbc	617	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
AnnaBridge	171:3a7713b1edbc	618	uint32_t RESERVED2[1U];
AnnaBridge	171:3a7713b1edbc	619	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
AnnaBridge	171:3a7713b1edbc	620	uint32_t RESERVED3[1U];
AnnaBridge	171:3a7713b1edbc	621	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
AnnaBridge	171:3a7713b1edbc	622	uint32_t RESERVED4[1U];
AnnaBridge	171:3a7713b1edbc	623	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
AnnaBridge	171:3a7713b1edbc	624	uint32_t RESERVED5[1U];
AnnaBridge	171:3a7713b1edbc	625	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
AnnaBridge	171:3a7713b1edbc	626	uint32_t RESERVED6[1U];
AnnaBridge	171:3a7713b1edbc	627	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
AnnaBridge	171:3a7713b1edbc	628	uint32_t RESERVED7[1U];
AnnaBridge	171:3a7713b1edbc	629	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
AnnaBridge	171:3a7713b1edbc	630	uint32_t RESERVED8[1U];
AnnaBridge	171:3a7713b1edbc	631	__IOM uint32_t COMP4; /!< Offset: 0x060 (R/W) Comparator Register 4 /
AnnaBridge	171:3a7713b1edbc	632	uint32_t RESERVED9[1U];
AnnaBridge	171:3a7713b1edbc	633	__IOM uint32_t FUNCTION4; /!< Offset: 0x068 (R/W) Function Register 4 /
AnnaBridge	171:3a7713b1edbc	634	uint32_t RESERVED10[1U];
AnnaBridge	171:3a7713b1edbc	635	__IOM uint32_t COMP5; /!< Offset: 0x070 (R/W) Comparator Register 5 /
AnnaBridge	171:3a7713b1edbc	636	uint32_t RESERVED11[1U];
AnnaBridge	171:3a7713b1edbc	637	__IOM uint32_t FUNCTION5; /!< Offset: 0x078 (R/W) Function Register 5 /
AnnaBridge	171:3a7713b1edbc	638	uint32_t RESERVED12[1U];
AnnaBridge	171:3a7713b1edbc	639	__IOM uint32_t COMP6; /!< Offset: 0x080 (R/W) Comparator Register 6 /
AnnaBridge	171:3a7713b1edbc	640	uint32_t RESERVED13[1U];
AnnaBridge	171:3a7713b1edbc	641	__IOM uint32_t FUNCTION6; /!< Offset: 0x088 (R/W) Function Register 6 /
AnnaBridge	171:3a7713b1edbc	642	uint32_t RESERVED14[1U];
AnnaBridge	171:3a7713b1edbc	643	__IOM uint32_t COMP7; /!< Offset: 0x090 (R/W) Comparator Register 7 /
AnnaBridge	171:3a7713b1edbc	644	uint32_t RESERVED15[1U];
AnnaBridge	171:3a7713b1edbc	645	__IOM uint32_t FUNCTION7; /!< Offset: 0x098 (R/W) Function Register 7 /
AnnaBridge	171:3a7713b1edbc	646	uint32_t RESERVED16[1U];
AnnaBridge	171:3a7713b1edbc	647	__IOM uint32_t COMP8; /!< Offset: 0x0A0 (R/W) Comparator Register 8 /
AnnaBridge	171:3a7713b1edbc	648	uint32_t RESERVED17[1U];
AnnaBridge	171:3a7713b1edbc	649	__IOM uint32_t FUNCTION8; /!< Offset: 0x0A8 (R/W) Function Register 8 /
AnnaBridge	171:3a7713b1edbc	650	uint32_t RESERVED18[1U];
AnnaBridge	171:3a7713b1edbc	651	__IOM uint32_t COMP9; /!< Offset: 0x0B0 (R/W) Comparator Register 9 /
AnnaBridge	171:3a7713b1edbc	652	uint32_t RESERVED19[1U];
AnnaBridge	171:3a7713b1edbc	653	__IOM uint32_t FUNCTION9; /!< Offset: 0x0B8 (R/W) Function Register 9 /
AnnaBridge	171:3a7713b1edbc	654	uint32_t RESERVED20[1U];
AnnaBridge	171:3a7713b1edbc	655	__IOM uint32_t COMP10; /!< Offset: 0x0C0 (R/W) Comparator Register 10 /
AnnaBridge	171:3a7713b1edbc	656	uint32_t RESERVED21[1U];
AnnaBridge	171:3a7713b1edbc	657	__IOM uint32_t FUNCTION10; /!< Offset: 0x0C8 (R/W) Function Register 10 /
AnnaBridge	171:3a7713b1edbc	658	uint32_t RESERVED22[1U];
AnnaBridge	171:3a7713b1edbc	659	__IOM uint32_t COMP11; /!< Offset: 0x0D0 (R/W) Comparator Register 11 /
AnnaBridge	171:3a7713b1edbc	660	uint32_t RESERVED23[1U];
AnnaBridge	171:3a7713b1edbc	661	__IOM uint32_t FUNCTION11; /!< Offset: 0x0D8 (R/W) Function Register 11 /
AnnaBridge	171:3a7713b1edbc	662	uint32_t RESERVED24[1U];
AnnaBridge	171:3a7713b1edbc	663	__IOM uint32_t COMP12; /!< Offset: 0x0E0 (R/W) Comparator Register 12 /
AnnaBridge	171:3a7713b1edbc	664	uint32_t RESERVED25[1U];
AnnaBridge	171:3a7713b1edbc	665	__IOM uint32_t FUNCTION12; /!< Offset: 0x0E8 (R/W) Function Register 12 /
AnnaBridge	171:3a7713b1edbc	666	uint32_t RESERVED26[1U];
AnnaBridge	171:3a7713b1edbc	667	__IOM uint32_t COMP13; /!< Offset: 0x0F0 (R/W) Comparator Register 13 /
AnnaBridge	171:3a7713b1edbc	668	uint32_t RESERVED27[1U];
AnnaBridge	171:3a7713b1edbc	669	__IOM uint32_t FUNCTION13; /!< Offset: 0x0F8 (R/W) Function Register 13 /
AnnaBridge	171:3a7713b1edbc	670	uint32_t RESERVED28[1U];
AnnaBridge	171:3a7713b1edbc	671	__IOM uint32_t COMP14; /!< Offset: 0x100 (R/W) Comparator Register 14 /
AnnaBridge	171:3a7713b1edbc	672	uint32_t RESERVED29[1U];
AnnaBridge	171:3a7713b1edbc	673	__IOM uint32_t FUNCTION14; /!< Offset: 0x108 (R/W) Function Register 14 /
AnnaBridge	171:3a7713b1edbc	674	uint32_t RESERVED30[1U];
AnnaBridge	171:3a7713b1edbc	675	__IOM uint32_t COMP15; /!< Offset: 0x110 (R/W) Comparator Register 15 /
AnnaBridge	171:3a7713b1edbc	676	uint32_t RESERVED31[1U];
AnnaBridge	171:3a7713b1edbc	677	__IOM uint32_t FUNCTION15; /!< Offset: 0x118 (R/W) Function Register 15 /
AnnaBridge	171:3a7713b1edbc	678	} DWT_Type;
AnnaBridge	171:3a7713b1edbc	679
AnnaBridge	171:3a7713b1edbc	680	/* DWT Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	681	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
AnnaBridge	171:3a7713b1edbc	682	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
AnnaBridge	171:3a7713b1edbc	683
AnnaBridge	171:3a7713b1edbc	684	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
AnnaBridge	171:3a7713b1edbc	685	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
AnnaBridge	171:3a7713b1edbc	686
AnnaBridge	171:3a7713b1edbc	687	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
AnnaBridge	171:3a7713b1edbc	688	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
AnnaBridge	171:3a7713b1edbc	689
AnnaBridge	171:3a7713b1edbc	690	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
AnnaBridge	171:3a7713b1edbc	691	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
AnnaBridge	171:3a7713b1edbc	692
AnnaBridge	171:3a7713b1edbc	693	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
AnnaBridge	171:3a7713b1edbc	694	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
AnnaBridge	171:3a7713b1edbc	695
AnnaBridge	171:3a7713b1edbc	696	/* DWT Comparator Function Register Definitions */
AnnaBridge	171:3a7713b1edbc	697	#define DWT_FUNCTION_ID_Pos 27U /!< DWT FUNCTION: ID Position /
AnnaBridge	171:3a7713b1edbc	698	#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /!< DWT FUNCTION: ID Mask /
AnnaBridge	171:3a7713b1edbc	699
AnnaBridge	171:3a7713b1edbc	700	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
AnnaBridge	171:3a7713b1edbc	701	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
AnnaBridge	171:3a7713b1edbc	702
AnnaBridge	171:3a7713b1edbc	703	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
AnnaBridge	171:3a7713b1edbc	704	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
AnnaBridge	171:3a7713b1edbc	705
AnnaBridge	171:3a7713b1edbc	706	#define DWT_FUNCTION_ACTION_Pos 4U /!< DWT FUNCTION: ACTION Position /
AnnaBridge	171:3a7713b1edbc	707	#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /!< DWT FUNCTION: ACTION Mask /
AnnaBridge	171:3a7713b1edbc	708
AnnaBridge	171:3a7713b1edbc	709	#define DWT_FUNCTION_MATCH_Pos 0U /!< DWT FUNCTION: MATCH Position /
AnnaBridge	171:3a7713b1edbc	710	#define DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/) /!< DWT FUNCTION: MATCH Mask /
AnnaBridge	171:3a7713b1edbc	711
AnnaBridge	171:3a7713b1edbc	712	/@}/ /* end of group CMSIS_DWT */
AnnaBridge	171:3a7713b1edbc	713
AnnaBridge	171:3a7713b1edbc	714
AnnaBridge	171:3a7713b1edbc	715	/**
AnnaBridge	171:3a7713b1edbc	716	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	717	\defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge	171:3a7713b1edbc	718	\brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge	171:3a7713b1edbc	719	@{
AnnaBridge	171:3a7713b1edbc	720	*/
AnnaBridge	171:3a7713b1edbc	721
AnnaBridge	171:3a7713b1edbc	722	/**
AnnaBridge	171:3a7713b1edbc	723	\brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge	171:3a7713b1edbc	724	*/
AnnaBridge	171:3a7713b1edbc	725	typedef struct
AnnaBridge	171:3a7713b1edbc	726	{
AnnaBridge	171:3a7713b1edbc	727	__IM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
AnnaBridge	171:3a7713b1edbc	728	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
AnnaBridge	171:3a7713b1edbc	729	uint32_t RESERVED0[2U];
AnnaBridge	171:3a7713b1edbc	730	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
AnnaBridge	171:3a7713b1edbc	731	uint32_t RESERVED1[55U];
AnnaBridge	171:3a7713b1edbc	732	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
AnnaBridge	171:3a7713b1edbc	733	uint32_t RESERVED2[131U];
AnnaBridge	171:3a7713b1edbc	734	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
AnnaBridge	171:3a7713b1edbc	735	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
AnnaBridge	171:3a7713b1edbc	736	__IOM uint32_t PSCR; /!< Offset: 0x308 (R/W) Periodic Synchronization Control Register /
AnnaBridge	171:3a7713b1edbc	737	uint32_t RESERVED3[759U];
AnnaBridge	171:3a7713b1edbc	738	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER Register /
AnnaBridge	171:3a7713b1edbc	739	__IM uint32_t ITFTTD0; /!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register /
AnnaBridge	171:3a7713b1edbc	740	__IOM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 /
AnnaBridge	171:3a7713b1edbc	741	uint32_t RESERVED4[1U];
AnnaBridge	171:3a7713b1edbc	742	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 /
AnnaBridge	171:3a7713b1edbc	743	__IM uint32_t ITFTTD1; /!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register /
AnnaBridge	171:3a7713b1edbc	744	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
AnnaBridge	171:3a7713b1edbc	745	uint32_t RESERVED5[39U];
AnnaBridge	171:3a7713b1edbc	746	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
AnnaBridge	171:3a7713b1edbc	747	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
AnnaBridge	171:3a7713b1edbc	748	uint32_t RESERVED7[8U];
AnnaBridge	171:3a7713b1edbc	749	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) Device Configuration Register /
AnnaBridge	171:3a7713b1edbc	750	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) Device Type Identifier Register /
AnnaBridge	171:3a7713b1edbc	751	} TPI_Type;
AnnaBridge	171:3a7713b1edbc	752
AnnaBridge	171:3a7713b1edbc	753	/* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge	171:3a7713b1edbc	754	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
AnnaBridge	171:3a7713b1edbc	755	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
AnnaBridge	171:3a7713b1edbc	756
AnnaBridge	171:3a7713b1edbc	757	/* TPI Selected Pin Protocol Register Definitions */
AnnaBridge	171:3a7713b1edbc	758	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
AnnaBridge	171:3a7713b1edbc	759	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
AnnaBridge	171:3a7713b1edbc	760
AnnaBridge	171:3a7713b1edbc	761	/* TPI Formatter and Flush Status Register Definitions */
AnnaBridge	171:3a7713b1edbc	762	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
AnnaBridge	171:3a7713b1edbc	763	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
AnnaBridge	171:3a7713b1edbc	764
AnnaBridge	171:3a7713b1edbc	765	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
AnnaBridge	171:3a7713b1edbc	766	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
AnnaBridge	171:3a7713b1edbc	767
AnnaBridge	171:3a7713b1edbc	768	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
AnnaBridge	171:3a7713b1edbc	769	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
AnnaBridge	171:3a7713b1edbc	770
AnnaBridge	171:3a7713b1edbc	771	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
AnnaBridge	171:3a7713b1edbc	772	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
AnnaBridge	171:3a7713b1edbc	773
AnnaBridge	171:3a7713b1edbc	774	/* TPI Formatter and Flush Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	775	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
AnnaBridge	171:3a7713b1edbc	776	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
AnnaBridge	171:3a7713b1edbc	777
AnnaBridge	171:3a7713b1edbc	778	#define TPI_FFCR_FOnMan_Pos 6U /!< TPI FFCR: FOnMan Position /
AnnaBridge	171:3a7713b1edbc	779	#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /!< TPI FFCR: FOnMan Mask /
AnnaBridge	171:3a7713b1edbc	780
AnnaBridge	171:3a7713b1edbc	781	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
AnnaBridge	171:3a7713b1edbc	782	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
AnnaBridge	171:3a7713b1edbc	783
AnnaBridge	171:3a7713b1edbc	784	/* TPI TRIGGER Register Definitions */
AnnaBridge	171:3a7713b1edbc	785	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
AnnaBridge	171:3a7713b1edbc	786	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
AnnaBridge	171:3a7713b1edbc	787
AnnaBridge	171:3a7713b1edbc	788	/* TPI Integration Test FIFO Test Data 0 Register Definitions */
AnnaBridge	171:3a7713b1edbc	789	#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition /
AnnaBridge	171:3a7713b1edbc	790	#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask /
AnnaBridge	171:3a7713b1edbc	791
AnnaBridge	171:3a7713b1edbc	792	#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /!< TPI ITFTTD0: ATB Interface 2 byte count Position /
AnnaBridge	171:3a7713b1edbc	793	#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /!< TPI ITFTTD0: ATB Interface 2 byte count Mask /
AnnaBridge	171:3a7713b1edbc	794
AnnaBridge	171:3a7713b1edbc	795	#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /!< TPI ITFTTD0: ATB Interface 1 ATVALID Position /
AnnaBridge	171:3a7713b1edbc	796	#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask /
AnnaBridge	171:3a7713b1edbc	797
AnnaBridge	171:3a7713b1edbc	798	#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /!< TPI ITFTTD0: ATB Interface 1 byte count Position /
AnnaBridge	171:3a7713b1edbc	799	#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /!< TPI ITFTTD0: ATB Interface 1 byte countt Mask /
AnnaBridge	171:3a7713b1edbc	800
AnnaBridge	171:3a7713b1edbc	801	#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /!< TPI ITFTTD0: ATB Interface 1 data2 Position /
AnnaBridge	171:3a7713b1edbc	802	#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /!< TPI ITFTTD0: ATB Interface 1 data2 Mask /
AnnaBridge	171:3a7713b1edbc	803
AnnaBridge	171:3a7713b1edbc	804	#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /!< TPI ITFTTD0: ATB Interface 1 data1 Position /
AnnaBridge	171:3a7713b1edbc	805	#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /!< TPI ITFTTD0: ATB Interface 1 data1 Mask /
AnnaBridge	171:3a7713b1edbc	806
AnnaBridge	171:3a7713b1edbc	807	#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /!< TPI ITFTTD0: ATB Interface 1 data0 Position /
AnnaBridge	171:3a7713b1edbc	808	#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/) /!< TPI ITFTTD0: ATB Interface 1 data0 Mask /
AnnaBridge	171:3a7713b1edbc	809
AnnaBridge	171:3a7713b1edbc	810	/* TPI Integration Test ATB Control Register 2 Register Definitions */
AnnaBridge	171:3a7713b1edbc	811	#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /!< TPI ITATBCTR2: AFVALID2S Position /
AnnaBridge	171:3a7713b1edbc	812	#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /!< TPI ITATBCTR2: AFVALID2SS Mask /
AnnaBridge	171:3a7713b1edbc	813
AnnaBridge	171:3a7713b1edbc	814	#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /!< TPI ITATBCTR2: AFVALID1S Position /
AnnaBridge	171:3a7713b1edbc	815	#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /!< TPI ITATBCTR2: AFVALID1SS Mask /
AnnaBridge	171:3a7713b1edbc	816
AnnaBridge	171:3a7713b1edbc	817	#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /!< TPI ITATBCTR2: ATREADY2S Position /
AnnaBridge	171:3a7713b1edbc	818	#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/) /!< TPI ITATBCTR2: ATREADY2S Mask /
AnnaBridge	171:3a7713b1edbc	819
AnnaBridge	171:3a7713b1edbc	820	#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /!< TPI ITATBCTR2: ATREADY1S Position /
AnnaBridge	171:3a7713b1edbc	821	#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/) /!< TPI ITATBCTR2: ATREADY1S Mask /
AnnaBridge	171:3a7713b1edbc	822
AnnaBridge	171:3a7713b1edbc	823	/* TPI Integration Test FIFO Test Data 1 Register Definitions */
AnnaBridge	171:3a7713b1edbc	824	#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /!< TPI ITFTTD1: ATB Interface 2 ATVALID Position /
AnnaBridge	171:3a7713b1edbc	825	#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask /
AnnaBridge	171:3a7713b1edbc	826
AnnaBridge	171:3a7713b1edbc	827	#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /!< TPI ITFTTD1: ATB Interface 2 byte count Position /
AnnaBridge	171:3a7713b1edbc	828	#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /!< TPI ITFTTD1: ATB Interface 2 byte count Mask /
AnnaBridge	171:3a7713b1edbc	829
AnnaBridge	171:3a7713b1edbc	830	#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /!< TPI ITFTTD1: ATB Interface 1 ATVALID Position /
AnnaBridge	171:3a7713b1edbc	831	#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask /
AnnaBridge	171:3a7713b1edbc	832
AnnaBridge	171:3a7713b1edbc	833	#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /!< TPI ITFTTD1: ATB Interface 1 byte count Position /
AnnaBridge	171:3a7713b1edbc	834	#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /!< TPI ITFTTD1: ATB Interface 1 byte countt Mask /
AnnaBridge	171:3a7713b1edbc	835
AnnaBridge	171:3a7713b1edbc	836	#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /!< TPI ITFTTD1: ATB Interface 2 data2 Position /
AnnaBridge	171:3a7713b1edbc	837	#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /!< TPI ITFTTD1: ATB Interface 2 data2 Mask /
AnnaBridge	171:3a7713b1edbc	838
AnnaBridge	171:3a7713b1edbc	839	#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /!< TPI ITFTTD1: ATB Interface 2 data1 Position /
AnnaBridge	171:3a7713b1edbc	840	#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /!< TPI ITFTTD1: ATB Interface 2 data1 Mask /
AnnaBridge	171:3a7713b1edbc	841
AnnaBridge	171:3a7713b1edbc	842	#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /!< TPI ITFTTD1: ATB Interface 2 data0 Position /
AnnaBridge	171:3a7713b1edbc	843	#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/) /!< TPI ITFTTD1: ATB Interface 2 data0 Mask /
AnnaBridge	171:3a7713b1edbc	844
AnnaBridge	171:3a7713b1edbc	845	/* TPI Integration Test ATB Control Register 0 Definitions */
AnnaBridge	171:3a7713b1edbc	846	#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /!< TPI ITATBCTR0: AFVALID2S Position /
AnnaBridge	171:3a7713b1edbc	847	#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /!< TPI ITATBCTR0: AFVALID2SS Mask /
AnnaBridge	171:3a7713b1edbc	848
AnnaBridge	171:3a7713b1edbc	849	#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /!< TPI ITATBCTR0: AFVALID1S Position /
AnnaBridge	171:3a7713b1edbc	850	#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /!< TPI ITATBCTR0: AFVALID1SS Mask /
AnnaBridge	171:3a7713b1edbc	851
AnnaBridge	171:3a7713b1edbc	852	#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /!< TPI ITATBCTR0: ATREADY2S Position /
AnnaBridge	171:3a7713b1edbc	853	#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/) /!< TPI ITATBCTR0: ATREADY2S Mask /
AnnaBridge	171:3a7713b1edbc	854
AnnaBridge	171:3a7713b1edbc	855	#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /!< TPI ITATBCTR0: ATREADY1S Position /
AnnaBridge	171:3a7713b1edbc	856	#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/) /!< TPI ITATBCTR0: ATREADY1S Mask /
AnnaBridge	171:3a7713b1edbc	857
AnnaBridge	171:3a7713b1edbc	858	/* TPI Integration Mode Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	859	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
AnnaBridge	171:3a7713b1edbc	860	#define TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
AnnaBridge	171:3a7713b1edbc	861
AnnaBridge	171:3a7713b1edbc	862	/* TPI DEVID Register Definitions */
AnnaBridge	171:3a7713b1edbc	863	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
AnnaBridge	171:3a7713b1edbc	864	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
AnnaBridge	171:3a7713b1edbc	865
AnnaBridge	171:3a7713b1edbc	866	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
AnnaBridge	171:3a7713b1edbc	867	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
AnnaBridge	171:3a7713b1edbc	868
AnnaBridge	171:3a7713b1edbc	869	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
AnnaBridge	171:3a7713b1edbc	870	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
AnnaBridge	171:3a7713b1edbc	871
AnnaBridge	171:3a7713b1edbc	872	#define TPI_DEVID_FIFOSZ_Pos 6U /!< TPI DEVID: FIFOSZ Position /
AnnaBridge	171:3a7713b1edbc	873	#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /!< TPI DEVID: FIFOSZ Mask /
AnnaBridge	171:3a7713b1edbc	874
AnnaBridge	171:3a7713b1edbc	875	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
AnnaBridge	171:3a7713b1edbc	876	#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
AnnaBridge	171:3a7713b1edbc	877
AnnaBridge	171:3a7713b1edbc	878	/* TPI DEVTYPE Register Definitions */
AnnaBridge	171:3a7713b1edbc	879	#define TPI_DEVTYPE_SubType_Pos 4U /!< TPI DEVTYPE: SubType Position /
AnnaBridge	171:3a7713b1edbc	880	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
AnnaBridge	171:3a7713b1edbc	881
AnnaBridge	171:3a7713b1edbc	882	#define TPI_DEVTYPE_MajorType_Pos 0U /!< TPI DEVTYPE: MajorType Position /
AnnaBridge	171:3a7713b1edbc	883	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
AnnaBridge	171:3a7713b1edbc	884
AnnaBridge	171:3a7713b1edbc	885	/@}/ /* end of group CMSIS_TPI */
AnnaBridge	171:3a7713b1edbc	886
AnnaBridge	171:3a7713b1edbc	887
AnnaBridge	171:3a7713b1edbc	888	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	889	/**
AnnaBridge	171:3a7713b1edbc	890	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	891	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge	171:3a7713b1edbc	892	\brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge	171:3a7713b1edbc	893	@{
AnnaBridge	171:3a7713b1edbc	894	*/
AnnaBridge	171:3a7713b1edbc	895
AnnaBridge	171:3a7713b1edbc	896	/**
AnnaBridge	171:3a7713b1edbc	897	\brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge	171:3a7713b1edbc	898	*/
AnnaBridge	171:3a7713b1edbc	899	typedef struct
AnnaBridge	171:3a7713b1edbc	900	{
AnnaBridge	171:3a7713b1edbc	901	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
AnnaBridge	171:3a7713b1edbc	902	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
AnnaBridge	171:3a7713b1edbc	903	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region Number Register /
AnnaBridge	171:3a7713b1edbc	904	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
AnnaBridge	171:3a7713b1edbc	905	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) MPU Region Limit Address Register /
AnnaBridge	171:3a7713b1edbc	906	uint32_t RESERVED0[7U];
AnnaBridge	171:3a7713b1edbc	907	union {
AnnaBridge	171:3a7713b1edbc	908	__IOM uint32_t MAIR[2];
AnnaBridge	171:3a7713b1edbc	909	struct {
AnnaBridge	171:3a7713b1edbc	910	__IOM uint32_t MAIR0; /!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 /
AnnaBridge	171:3a7713b1edbc	911	__IOM uint32_t MAIR1; /!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 /
AnnaBridge	171:3a7713b1edbc	912	};
AnnaBridge	171:3a7713b1edbc	913	};
AnnaBridge	171:3a7713b1edbc	914	} MPU_Type;
AnnaBridge	171:3a7713b1edbc	915
AnnaBridge	171:3a7713b1edbc	916	#define MPU_TYPE_RALIASES 1U
AnnaBridge	171:3a7713b1edbc	917
AnnaBridge	171:3a7713b1edbc	918	/* MPU Type Register Definitions */
AnnaBridge	171:3a7713b1edbc	919	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
AnnaBridge	171:3a7713b1edbc	920	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
AnnaBridge	171:3a7713b1edbc	921
AnnaBridge	171:3a7713b1edbc	922	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
AnnaBridge	171:3a7713b1edbc	923	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
AnnaBridge	171:3a7713b1edbc	924
AnnaBridge	171:3a7713b1edbc	925	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
AnnaBridge	171:3a7713b1edbc	926	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
AnnaBridge	171:3a7713b1edbc	927
AnnaBridge	171:3a7713b1edbc	928	/* MPU Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	929	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
AnnaBridge	171:3a7713b1edbc	930	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
AnnaBridge	171:3a7713b1edbc	931
AnnaBridge	171:3a7713b1edbc	932	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
AnnaBridge	171:3a7713b1edbc	933	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
AnnaBridge	171:3a7713b1edbc	934
AnnaBridge	171:3a7713b1edbc	935	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
AnnaBridge	171:3a7713b1edbc	936	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
AnnaBridge	171:3a7713b1edbc	937
AnnaBridge	171:3a7713b1edbc	938	/* MPU Region Number Register Definitions */
AnnaBridge	171:3a7713b1edbc	939	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
AnnaBridge	171:3a7713b1edbc	940	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
AnnaBridge	171:3a7713b1edbc	941
AnnaBridge	171:3a7713b1edbc	942	/* MPU Region Base Address Register Definitions */
AnnaBridge	171:3a7713b1edbc	943	#define MPU_RBAR_BASE_Pos 5U /!< MPU RBAR: BASE Position /
AnnaBridge	171:3a7713b1edbc	944	#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /!< MPU RBAR: BASE Mask /
AnnaBridge	171:3a7713b1edbc	945
AnnaBridge	171:3a7713b1edbc	946	#define MPU_RBAR_SH_Pos 3U /!< MPU RBAR: SH Position /
AnnaBridge	171:3a7713b1edbc	947	#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /!< MPU RBAR: SH Mask /
AnnaBridge	171:3a7713b1edbc	948
AnnaBridge	171:3a7713b1edbc	949	#define MPU_RBAR_AP_Pos 1U /!< MPU RBAR: AP Position /
AnnaBridge	171:3a7713b1edbc	950	#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /!< MPU RBAR: AP Mask /
AnnaBridge	171:3a7713b1edbc	951
AnnaBridge	171:3a7713b1edbc	952	#define MPU_RBAR_XN_Pos 0U /!< MPU RBAR: XN Position /
AnnaBridge	171:3a7713b1edbc	953	#define MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/) /!< MPU RBAR: XN Mask /
AnnaBridge	171:3a7713b1edbc	954
AnnaBridge	171:3a7713b1edbc	955	/* MPU Region Limit Address Register Definitions */
AnnaBridge	171:3a7713b1edbc	956	#define MPU_RLAR_LIMIT_Pos 5U /!< MPU RLAR: LIMIT Position /
AnnaBridge	171:3a7713b1edbc	957	#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /!< MPU RLAR: LIMIT Mask /
AnnaBridge	171:3a7713b1edbc	958
AnnaBridge	171:3a7713b1edbc	959	#define MPU_RLAR_AttrIndx_Pos 1U /!< MPU RLAR: AttrIndx Position /
AnnaBridge	171:3a7713b1edbc	960	#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /!< MPU RLAR: AttrIndx Mask /
AnnaBridge	171:3a7713b1edbc	961
AnnaBridge	171:3a7713b1edbc	962	#define MPU_RLAR_EN_Pos 0U /!< MPU RLAR: EN Position /
AnnaBridge	171:3a7713b1edbc	963	#define MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/) /!< MPU RLAR: EN Mask /
AnnaBridge	171:3a7713b1edbc	964
AnnaBridge	171:3a7713b1edbc	965	/* MPU Memory Attribute Indirection Register 0 Definitions */
AnnaBridge	171:3a7713b1edbc	966	#define MPU_MAIR0_Attr3_Pos 24U /!< MPU MAIR0: Attr3 Position /
AnnaBridge	171:3a7713b1edbc	967	#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /!< MPU MAIR0: Attr3 Mask /
AnnaBridge	171:3a7713b1edbc	968
AnnaBridge	171:3a7713b1edbc	969	#define MPU_MAIR0_Attr2_Pos 16U /!< MPU MAIR0: Attr2 Position /
AnnaBridge	171:3a7713b1edbc	970	#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /!< MPU MAIR0: Attr2 Mask /
AnnaBridge	171:3a7713b1edbc	971
AnnaBridge	171:3a7713b1edbc	972	#define MPU_MAIR0_Attr1_Pos 8U /!< MPU MAIR0: Attr1 Position /
AnnaBridge	171:3a7713b1edbc	973	#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /!< MPU MAIR0: Attr1 Mask /
AnnaBridge	171:3a7713b1edbc	974
AnnaBridge	171:3a7713b1edbc	975	#define MPU_MAIR0_Attr0_Pos 0U /!< MPU MAIR0: Attr0 Position /
AnnaBridge	171:3a7713b1edbc	976	#define MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/) /!< MPU MAIR0: Attr0 Mask /
AnnaBridge	171:3a7713b1edbc	977
AnnaBridge	171:3a7713b1edbc	978	/* MPU Memory Attribute Indirection Register 1 Definitions */
AnnaBridge	171:3a7713b1edbc	979	#define MPU_MAIR1_Attr7_Pos 24U /!< MPU MAIR1: Attr7 Position /
AnnaBridge	171:3a7713b1edbc	980	#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /!< MPU MAIR1: Attr7 Mask /
AnnaBridge	171:3a7713b1edbc	981
AnnaBridge	171:3a7713b1edbc	982	#define MPU_MAIR1_Attr6_Pos 16U /!< MPU MAIR1: Attr6 Position /
AnnaBridge	171:3a7713b1edbc	983	#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /!< MPU MAIR1: Attr6 Mask /
AnnaBridge	171:3a7713b1edbc	984
AnnaBridge	171:3a7713b1edbc	985	#define MPU_MAIR1_Attr5_Pos 8U /!< MPU MAIR1: Attr5 Position /
AnnaBridge	171:3a7713b1edbc	986	#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /!< MPU MAIR1: Attr5 Mask /
AnnaBridge	171:3a7713b1edbc	987
AnnaBridge	171:3a7713b1edbc	988	#define MPU_MAIR1_Attr4_Pos 0U /!< MPU MAIR1: Attr4 Position /
AnnaBridge	171:3a7713b1edbc	989	#define MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/) /!< MPU MAIR1: Attr4 Mask /
AnnaBridge	171:3a7713b1edbc	990
AnnaBridge	171:3a7713b1edbc	991	/@} end of group CMSIS_MPU /
AnnaBridge	171:3a7713b1edbc	992	#endif
AnnaBridge	171:3a7713b1edbc	993
AnnaBridge	171:3a7713b1edbc	994
AnnaBridge	171:3a7713b1edbc	995	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	171:3a7713b1edbc	996	/**
AnnaBridge	171:3a7713b1edbc	997	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	998	\defgroup CMSIS_SAU Security Attribution Unit (SAU)
AnnaBridge	171:3a7713b1edbc	999	\brief Type definitions for the Security Attribution Unit (SAU)
AnnaBridge	171:3a7713b1edbc	1000	@{
AnnaBridge	171:3a7713b1edbc	1001	*/
AnnaBridge	171:3a7713b1edbc	1002
AnnaBridge	171:3a7713b1edbc	1003	/**
AnnaBridge	171:3a7713b1edbc	1004	\brief Structure type to access the Security Attribution Unit (SAU).
AnnaBridge	171:3a7713b1edbc	1005	*/
AnnaBridge	171:3a7713b1edbc	1006	typedef struct
AnnaBridge	171:3a7713b1edbc	1007	{
AnnaBridge	171:3a7713b1edbc	1008	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SAU Control Register /
AnnaBridge	171:3a7713b1edbc	1009	__IM uint32_t TYPE; /!< Offset: 0x004 (R/ ) SAU Type Register /
AnnaBridge	171:3a7713b1edbc	1010	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	1011	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) SAU Region Number Register /
AnnaBridge	171:3a7713b1edbc	1012	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) SAU Region Base Address Register /
AnnaBridge	171:3a7713b1edbc	1013	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) SAU Region Limit Address Register /
AnnaBridge	171:3a7713b1edbc	1014	#endif
AnnaBridge	171:3a7713b1edbc	1015	} SAU_Type;
AnnaBridge	171:3a7713b1edbc	1016
AnnaBridge	171:3a7713b1edbc	1017	/* SAU Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	1018	#define SAU_CTRL_ALLNS_Pos 1U /!< SAU CTRL: ALLNS Position /
AnnaBridge	171:3a7713b1edbc	1019	#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /!< SAU CTRL: ALLNS Mask /
AnnaBridge	171:3a7713b1edbc	1020
AnnaBridge	171:3a7713b1edbc	1021	#define SAU_CTRL_ENABLE_Pos 0U /!< SAU CTRL: ENABLE Position /
AnnaBridge	171:3a7713b1edbc	1022	#define SAU_CTRL_ENABLE_Msk (1UL /<< SAU_CTRL_ENABLE_Pos/) /!< SAU CTRL: ENABLE Mask /
AnnaBridge	171:3a7713b1edbc	1023
AnnaBridge	171:3a7713b1edbc	1024	/* SAU Type Register Definitions */
AnnaBridge	171:3a7713b1edbc	1025	#define SAU_TYPE_SREGION_Pos 0U /!< SAU TYPE: SREGION Position /
AnnaBridge	171:3a7713b1edbc	1026	#define SAU_TYPE_SREGION_Msk (0xFFUL /<< SAU_TYPE_SREGION_Pos/) /!< SAU TYPE: SREGION Mask /
AnnaBridge	171:3a7713b1edbc	1027
AnnaBridge	171:3a7713b1edbc	1028	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	1029	/* SAU Region Number Register Definitions */
AnnaBridge	171:3a7713b1edbc	1030	#define SAU_RNR_REGION_Pos 0U /!< SAU RNR: REGION Position /
AnnaBridge	171:3a7713b1edbc	1031	#define SAU_RNR_REGION_Msk (0xFFUL /<< SAU_RNR_REGION_Pos/) /!< SAU RNR: REGION Mask /
AnnaBridge	171:3a7713b1edbc	1032
AnnaBridge	171:3a7713b1edbc	1033	/* SAU Region Base Address Register Definitions */
AnnaBridge	171:3a7713b1edbc	1034	#define SAU_RBAR_BADDR_Pos 5U /!< SAU RBAR: BADDR Position /
AnnaBridge	171:3a7713b1edbc	1035	#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /!< SAU RBAR: BADDR Mask /
AnnaBridge	171:3a7713b1edbc	1036
AnnaBridge	171:3a7713b1edbc	1037	/* SAU Region Limit Address Register Definitions */
AnnaBridge	171:3a7713b1edbc	1038	#define SAU_RLAR_LADDR_Pos 5U /!< SAU RLAR: LADDR Position /
AnnaBridge	171:3a7713b1edbc	1039	#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /!< SAU RLAR: LADDR Mask /
AnnaBridge	171:3a7713b1edbc	1040
AnnaBridge	171:3a7713b1edbc	1041	#define SAU_RLAR_NSC_Pos 1U /!< SAU RLAR: NSC Position /
AnnaBridge	171:3a7713b1edbc	1042	#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /!< SAU RLAR: NSC Mask /
AnnaBridge	171:3a7713b1edbc	1043
AnnaBridge	171:3a7713b1edbc	1044	#define SAU_RLAR_ENABLE_Pos 0U /!< SAU RLAR: ENABLE Position /
AnnaBridge	171:3a7713b1edbc	1045	#define SAU_RLAR_ENABLE_Msk (1UL /<< SAU_RLAR_ENABLE_Pos/) /!< SAU RLAR: ENABLE Mask /
AnnaBridge	171:3a7713b1edbc	1046
AnnaBridge	171:3a7713b1edbc	1047	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
AnnaBridge	171:3a7713b1edbc	1048
AnnaBridge	171:3a7713b1edbc	1049	/@} end of group CMSIS_SAU /
AnnaBridge	171:3a7713b1edbc	1050	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	171:3a7713b1edbc	1051
AnnaBridge	171:3a7713b1edbc	1052
AnnaBridge	171:3a7713b1edbc	1053	/**
AnnaBridge	171:3a7713b1edbc	1054	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	1055	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge	171:3a7713b1edbc	1056	\brief Type definitions for the Core Debug Registers
AnnaBridge	171:3a7713b1edbc	1057	@{
AnnaBridge	171:3a7713b1edbc	1058	*/
AnnaBridge	171:3a7713b1edbc	1059
AnnaBridge	171:3a7713b1edbc	1060	/**
AnnaBridge	171:3a7713b1edbc	1061	\brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge	171:3a7713b1edbc	1062	*/
AnnaBridge	171:3a7713b1edbc	1063	typedef struct
AnnaBridge	171:3a7713b1edbc	1064	{
AnnaBridge	171:3a7713b1edbc	1065	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
AnnaBridge	171:3a7713b1edbc	1066	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
AnnaBridge	171:3a7713b1edbc	1067	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
AnnaBridge	171:3a7713b1edbc	1068	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
AnnaBridge	171:3a7713b1edbc	1069	uint32_t RESERVED4[1U];
AnnaBridge	171:3a7713b1edbc	1070	__IOM uint32_t DAUTHCTRL; /!< Offset: 0x014 (R/W) Debug Authentication Control Register /
AnnaBridge	171:3a7713b1edbc	1071	__IOM uint32_t DSCSR; /!< Offset: 0x018 (R/W) Debug Security Control and Status Register /
AnnaBridge	171:3a7713b1edbc	1072	} CoreDebug_Type;
AnnaBridge	171:3a7713b1edbc	1073
AnnaBridge	171:3a7713b1edbc	1074	/* Debug Halting Control and Status Register Definitions */
AnnaBridge	171:3a7713b1edbc	1075	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
AnnaBridge	171:3a7713b1edbc	1076	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
AnnaBridge	171:3a7713b1edbc	1077
AnnaBridge	171:3a7713b1edbc	1078	#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /!< CoreDebug DHCSR: S_RESTART_ST Position /
AnnaBridge	171:3a7713b1edbc	1079	#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /!< CoreDebug DHCSR: S_RESTART_ST Mask /
AnnaBridge	171:3a7713b1edbc	1080
AnnaBridge	171:3a7713b1edbc	1081	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
AnnaBridge	171:3a7713b1edbc	1082	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
AnnaBridge	171:3a7713b1edbc	1083
AnnaBridge	171:3a7713b1edbc	1084	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
AnnaBridge	171:3a7713b1edbc	1085	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
AnnaBridge	171:3a7713b1edbc	1086
AnnaBridge	171:3a7713b1edbc	1087	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
AnnaBridge	171:3a7713b1edbc	1088	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
AnnaBridge	171:3a7713b1edbc	1089
AnnaBridge	171:3a7713b1edbc	1090	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
AnnaBridge	171:3a7713b1edbc	1091	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
AnnaBridge	171:3a7713b1edbc	1092
AnnaBridge	171:3a7713b1edbc	1093	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
AnnaBridge	171:3a7713b1edbc	1094	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
AnnaBridge	171:3a7713b1edbc	1095
AnnaBridge	171:3a7713b1edbc	1096	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
AnnaBridge	171:3a7713b1edbc	1097	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
AnnaBridge	171:3a7713b1edbc	1098
AnnaBridge	171:3a7713b1edbc	1099	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
AnnaBridge	171:3a7713b1edbc	1100	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
AnnaBridge	171:3a7713b1edbc	1101
AnnaBridge	171:3a7713b1edbc	1102	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
AnnaBridge	171:3a7713b1edbc	1103	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
AnnaBridge	171:3a7713b1edbc	1104
AnnaBridge	171:3a7713b1edbc	1105	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
AnnaBridge	171:3a7713b1edbc	1106	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
AnnaBridge	171:3a7713b1edbc	1107
AnnaBridge	171:3a7713b1edbc	1108	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
AnnaBridge	171:3a7713b1edbc	1109	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
AnnaBridge	171:3a7713b1edbc	1110
AnnaBridge	171:3a7713b1edbc	1111	/* Debug Core Register Selector Register Definitions */
AnnaBridge	171:3a7713b1edbc	1112	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
AnnaBridge	171:3a7713b1edbc	1113	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
AnnaBridge	171:3a7713b1edbc	1114
AnnaBridge	171:3a7713b1edbc	1115	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
AnnaBridge	171:3a7713b1edbc	1116	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
AnnaBridge	171:3a7713b1edbc	1117
AnnaBridge	171:3a7713b1edbc	1118	/* Debug Exception and Monitor Control Register */
AnnaBridge	171:3a7713b1edbc	1119	#define CoreDebug_DEMCR_DWTENA_Pos 24U /!< CoreDebug DEMCR: DWTENA Position /
AnnaBridge	171:3a7713b1edbc	1120	#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /!< CoreDebug DEMCR: DWTENA Mask /
AnnaBridge	171:3a7713b1edbc	1121
AnnaBridge	171:3a7713b1edbc	1122	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
AnnaBridge	171:3a7713b1edbc	1123	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
AnnaBridge	171:3a7713b1edbc	1124
AnnaBridge	171:3a7713b1edbc	1125	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
AnnaBridge	171:3a7713b1edbc	1126	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
AnnaBridge	171:3a7713b1edbc	1127
AnnaBridge	171:3a7713b1edbc	1128	/* Debug Authentication Control Register Definitions */
AnnaBridge	171:3a7713b1edbc	1129	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position /
AnnaBridge	171:3a7713b1edbc	1130	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask /
AnnaBridge	171:3a7713b1edbc	1131
AnnaBridge	171:3a7713b1edbc	1132	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /!< CoreDebug DAUTHCTRL: SPNIDENSEL Position /
AnnaBridge	171:3a7713b1edbc	1133	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask /
AnnaBridge	171:3a7713b1edbc	1134
AnnaBridge	171:3a7713b1edbc	1135	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /!< CoreDebug DAUTHCTRL: INTSPIDEN Position /
AnnaBridge	171:3a7713b1edbc	1136	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPIDEN Mask /
AnnaBridge	171:3a7713b1edbc	1137
AnnaBridge	171:3a7713b1edbc	1138	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /!< CoreDebug DAUTHCTRL: SPIDENSEL Position /
AnnaBridge	171:3a7713b1edbc	1139	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/) /!< CoreDebug DAUTHCTRL: SPIDENSEL Mask /
AnnaBridge	171:3a7713b1edbc	1140
AnnaBridge	171:3a7713b1edbc	1141	/* Debug Security Control and Status Register Definitions */
AnnaBridge	171:3a7713b1edbc	1142	#define CoreDebug_DSCSR_CDS_Pos 16U /!< CoreDebug DSCSR: CDS Position /
AnnaBridge	171:3a7713b1edbc	1143	#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /!< CoreDebug DSCSR: CDS Mask /
AnnaBridge	171:3a7713b1edbc	1144
AnnaBridge	171:3a7713b1edbc	1145	#define CoreDebug_DSCSR_SBRSEL_Pos 1U /!< CoreDebug DSCSR: SBRSEL Position /
AnnaBridge	171:3a7713b1edbc	1146	#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /!< CoreDebug DSCSR: SBRSEL Mask /
AnnaBridge	171:3a7713b1edbc	1147
AnnaBridge	171:3a7713b1edbc	1148	#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /!< CoreDebug DSCSR: SBRSELEN Position /
AnnaBridge	171:3a7713b1edbc	1149	#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/) /!< CoreDebug DSCSR: SBRSELEN Mask /
AnnaBridge	171:3a7713b1edbc	1150
AnnaBridge	171:3a7713b1edbc	1151	/@} end of group CMSIS_CoreDebug /
AnnaBridge	171:3a7713b1edbc	1152
AnnaBridge	171:3a7713b1edbc	1153
AnnaBridge	171:3a7713b1edbc	1154	/**
AnnaBridge	171:3a7713b1edbc	1155	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	1156	\defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge	171:3a7713b1edbc	1157	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge	171:3a7713b1edbc	1158	@{
AnnaBridge	171:3a7713b1edbc	1159	*/
AnnaBridge	171:3a7713b1edbc	1160
AnnaBridge	171:3a7713b1edbc	1161	/**
AnnaBridge	171:3a7713b1edbc	1162	\brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge	171:3a7713b1edbc	1163	\param[in] field Name of the register bit field.
AnnaBridge	171:3a7713b1edbc	1164	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge	171:3a7713b1edbc	1165	\return Masked and shifted value.
AnnaBridge	171:3a7713b1edbc	1166	*/
AnnaBridge	171:3a7713b1edbc	1167	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge	171:3a7713b1edbc	1168
AnnaBridge	171:3a7713b1edbc	1169	/**
AnnaBridge	171:3a7713b1edbc	1170	\brief Mask and shift a register value to extract a bit filed value.
AnnaBridge	171:3a7713b1edbc	1171	\param[in] field Name of the register bit field.
AnnaBridge	171:3a7713b1edbc	1172	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge	171:3a7713b1edbc	1173	\return Masked and shifted bit field value.
AnnaBridge	171:3a7713b1edbc	1174	*/
AnnaBridge	171:3a7713b1edbc	1175	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge	171:3a7713b1edbc	1176
AnnaBridge	171:3a7713b1edbc	1177	/@} end of group CMSIS_core_bitfield /
AnnaBridge	171:3a7713b1edbc	1178
AnnaBridge	171:3a7713b1edbc	1179
AnnaBridge	171:3a7713b1edbc	1180	/**
AnnaBridge	171:3a7713b1edbc	1181	\ingroup CMSIS_core_register
AnnaBridge	171:3a7713b1edbc	1182	\defgroup CMSIS_core_base Core Definitions
AnnaBridge	171:3a7713b1edbc	1183	\brief Definitions for base addresses, unions, and structures.
AnnaBridge	171:3a7713b1edbc	1184	@{
AnnaBridge	171:3a7713b1edbc	1185	*/
AnnaBridge	171:3a7713b1edbc	1186
AnnaBridge	171:3a7713b1edbc	1187	/* Memory mapping of Core Hardware */
AnnaBridge	171:3a7713b1edbc	1188	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
AnnaBridge	171:3a7713b1edbc	1189	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
AnnaBridge	171:3a7713b1edbc	1190	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
AnnaBridge	171:3a7713b1edbc	1191	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
AnnaBridge	171:3a7713b1edbc	1192	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
AnnaBridge	171:3a7713b1edbc	1193	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
AnnaBridge	171:3a7713b1edbc	1194	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
AnnaBridge	171:3a7713b1edbc	1195
AnnaBridge	171:3a7713b1edbc	1196
AnnaBridge	171:3a7713b1edbc	1197	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
AnnaBridge	171:3a7713b1edbc	1198	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
AnnaBridge	171:3a7713b1edbc	1199	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
AnnaBridge	171:3a7713b1edbc	1200	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
AnnaBridge	171:3a7713b1edbc	1201	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
AnnaBridge	171:3a7713b1edbc	1202	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE ) /!< Core Debug configuration struct */
AnnaBridge	171:3a7713b1edbc	1203
AnnaBridge	171:3a7713b1edbc	1204	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	1205	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
AnnaBridge	171:3a7713b1edbc	1206	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
AnnaBridge	171:3a7713b1edbc	1207	#endif
AnnaBridge	171:3a7713b1edbc	1208
AnnaBridge	171:3a7713b1edbc	1209	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	171:3a7713b1edbc	1210	#define SAU_BASE (SCS_BASE + 0x0DD0UL) /!< Security Attribution Unit /
AnnaBridge	171:3a7713b1edbc	1211	#define SAU ((SAU_Type ) SAU_BASE ) /!< Security Attribution Unit */
AnnaBridge	171:3a7713b1edbc	1212	#endif
AnnaBridge	171:3a7713b1edbc	1213
AnnaBridge	171:3a7713b1edbc	1214	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	171:3a7713b1edbc	1215	#define SCS_BASE_NS (0xE002E000UL) /!< System Control Space Base Address (non-secure address space) /
AnnaBridge	171:3a7713b1edbc	1216	#define CoreDebug_BASE_NS (0xE002EDF0UL) /!< Core Debug Base Address (non-secure address space) /
AnnaBridge	171:3a7713b1edbc	1217	#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /!< SysTick Base Address (non-secure address space) /
AnnaBridge	171:3a7713b1edbc	1218	#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /!< NVIC Base Address (non-secure address space) /
AnnaBridge	171:3a7713b1edbc	1219	#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /!< System Control Block Base Address (non-secure address space) /
AnnaBridge	171:3a7713b1edbc	1220
AnnaBridge	171:3a7713b1edbc	1221	#define SCB_NS ((SCB_Type ) SCB_BASE_NS ) /!< SCB configuration struct (non-secure address space) */
AnnaBridge	171:3a7713b1edbc	1222	#define SysTick_NS ((SysTick_Type ) SysTick_BASE_NS ) /!< SysTick configuration struct (non-secure address space) */
AnnaBridge	171:3a7713b1edbc	1223	#define NVIC_NS ((NVIC_Type ) NVIC_BASE_NS ) /!< NVIC configuration struct (non-secure address space) */
AnnaBridge	171:3a7713b1edbc	1224	#define CoreDebug_NS ((CoreDebug_Type ) CoreDebug_BASE_NS) /!< Core Debug configuration struct (non-secure address space) */
AnnaBridge	171:3a7713b1edbc	1225
AnnaBridge	171:3a7713b1edbc	1226	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	1227	#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /!< Memory Protection Unit (non-secure address space) /
AnnaBridge	171:3a7713b1edbc	1228	#define MPU_NS ((MPU_Type ) MPU_BASE_NS ) /!< Memory Protection Unit (non-secure address space) */
AnnaBridge	171:3a7713b1edbc	1229	#endif
AnnaBridge	171:3a7713b1edbc	1230
AnnaBridge	171:3a7713b1edbc	1231	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	171:3a7713b1edbc	1232	/@} /
AnnaBridge	171:3a7713b1edbc	1233
AnnaBridge	171:3a7713b1edbc	1234
AnnaBridge	171:3a7713b1edbc	1235
AnnaBridge	171:3a7713b1edbc	1236	/*******************************************************************************
AnnaBridge	171:3a7713b1edbc	1237	* Hardware Abstraction Layer
AnnaBridge	171:3a7713b1edbc	1238	Core Function Interface contains:
AnnaBridge	171:3a7713b1edbc	1239	- Core NVIC Functions
AnnaBridge	171:3a7713b1edbc	1240	- Core SysTick Functions
AnnaBridge	171:3a7713b1edbc	1241	- Core Register Access Functions
AnnaBridge	171:3a7713b1edbc	1242	******************************************************************************/
AnnaBridge	171:3a7713b1edbc	1243	/**
AnnaBridge	171:3a7713b1edbc	1244	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge	171:3a7713b1edbc	1245	*/
AnnaBridge	171:3a7713b1edbc	1246
AnnaBridge	171:3a7713b1edbc	1247
AnnaBridge	171:3a7713b1edbc	1248
AnnaBridge	171:3a7713b1edbc	1249	/* ########################## NVIC functions #################################### */
AnnaBridge	171:3a7713b1edbc	1250	/**
AnnaBridge	171:3a7713b1edbc	1251	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	171:3a7713b1edbc	1252	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge	171:3a7713b1edbc	1253	\brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge	171:3a7713b1edbc	1254	@{
AnnaBridge	171:3a7713b1edbc	1255	*/
AnnaBridge	171:3a7713b1edbc	1256
AnnaBridge	171:3a7713b1edbc	1257	#ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge	171:3a7713b1edbc	1258	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	171:3a7713b1edbc	1259	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge	171:3a7713b1edbc	1260	#endif
AnnaBridge	171:3a7713b1edbc	1261	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	171:3a7713b1edbc	1262	#else
AnnaBridge	171:3a7713b1edbc	1263	/#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 /
AnnaBridge	171:3a7713b1edbc	1264	/#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 /
AnnaBridge	171:3a7713b1edbc	1265	#define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge	171:3a7713b1edbc	1266	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge	171:3a7713b1edbc	1267	#define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge	171:3a7713b1edbc	1268	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge	171:3a7713b1edbc	1269	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge	171:3a7713b1edbc	1270	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge	171:3a7713b1edbc	1271	#define NVIC_GetActive __NVIC_GetActive
AnnaBridge	171:3a7713b1edbc	1272	#define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge	171:3a7713b1edbc	1273	#define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge	171:3a7713b1edbc	1274	#define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge	171:3a7713b1edbc	1275	#endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge	171:3a7713b1edbc	1276
AnnaBridge	171:3a7713b1edbc	1277	#ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge	171:3a7713b1edbc	1278	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	171:3a7713b1edbc	1279	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge	171:3a7713b1edbc	1280	#endif
AnnaBridge	171:3a7713b1edbc	1281	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	171:3a7713b1edbc	1282	#else
AnnaBridge	171:3a7713b1edbc	1283	#define NVIC_SetVector __NVIC_SetVector
AnnaBridge	171:3a7713b1edbc	1284	#define NVIC_GetVector __NVIC_GetVector
AnnaBridge	171:3a7713b1edbc	1285	#endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge	171:3a7713b1edbc	1286
AnnaBridge	171:3a7713b1edbc	1287	#define NVIC_USER_IRQ_OFFSET 16
AnnaBridge	171:3a7713b1edbc	1288
AnnaBridge	171:3a7713b1edbc	1289
AnnaBridge	171:3a7713b1edbc	1290	/* Special LR values for Secure/Non-Secure call handling and exception handling */
AnnaBridge	171:3a7713b1edbc	1291
AnnaBridge	171:3a7713b1edbc	1292	/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
AnnaBridge	171:3a7713b1edbc	1293	#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
AnnaBridge	171:3a7713b1edbc	1294
AnnaBridge	171:3a7713b1edbc	1295	/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
AnnaBridge	171:3a7713b1edbc	1296	#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
AnnaBridge	171:3a7713b1edbc	1297	#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
AnnaBridge	171:3a7713b1edbc	1298	#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
AnnaBridge	171:3a7713b1edbc	1299	#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
AnnaBridge	171:3a7713b1edbc	1300	#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
AnnaBridge	171:3a7713b1edbc	1301	#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
AnnaBridge	171:3a7713b1edbc	1302	#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
AnnaBridge	171:3a7713b1edbc	1303
AnnaBridge	171:3a7713b1edbc	1304	/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
AnnaBridge	171:3a7713b1edbc	1305	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
AnnaBridge	171:3a7713b1edbc	1306	#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
AnnaBridge	171:3a7713b1edbc	1307	#else
AnnaBridge	171:3a7713b1edbc	1308	#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
AnnaBridge	171:3a7713b1edbc	1309	#endif
AnnaBridge	171:3a7713b1edbc	1310
AnnaBridge	171:3a7713b1edbc	1311
AnnaBridge	171:3a7713b1edbc	1312	/* Interrupt Priorities are WORD accessible only under Armv6-M */
AnnaBridge	171:3a7713b1edbc	1313	/* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge	171:3a7713b1edbc	1314	#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge	171:3a7713b1edbc	1315	#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge	171:3a7713b1edbc	1316	#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge	171:3a7713b1edbc	1317
AnnaBridge	171:3a7713b1edbc	1318	#define __NVIC_SetPriorityGrouping(X) (void)(X)
AnnaBridge	171:3a7713b1edbc	1319	#define __NVIC_GetPriorityGrouping() (0U)
AnnaBridge	171:3a7713b1edbc	1320
AnnaBridge	171:3a7713b1edbc	1321	/**
AnnaBridge	171:3a7713b1edbc	1322	\brief Enable Interrupt
AnnaBridge	171:3a7713b1edbc	1323	\details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	171:3a7713b1edbc	1324	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1325	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1326	*/
AnnaBridge	171:3a7713b1edbc	1327	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1328	{
AnnaBridge	171:3a7713b1edbc	1329	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1330	{
AnnaBridge	171:3a7713b1edbc	1331	NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	171:3a7713b1edbc	1332	}
AnnaBridge	171:3a7713b1edbc	1333	}
AnnaBridge	171:3a7713b1edbc	1334
AnnaBridge	171:3a7713b1edbc	1335
AnnaBridge	171:3a7713b1edbc	1336	/**
AnnaBridge	171:3a7713b1edbc	1337	\brief Get Interrupt Enable status
AnnaBridge	171:3a7713b1edbc	1338	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge	171:3a7713b1edbc	1339	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1340	\return 0 Interrupt is not enabled.
AnnaBridge	171:3a7713b1edbc	1341	\return 1 Interrupt is enabled.
AnnaBridge	171:3a7713b1edbc	1342	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1343	*/
AnnaBridge	171:3a7713b1edbc	1344	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1345	{
AnnaBridge	171:3a7713b1edbc	1346	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1347	{
AnnaBridge	171:3a7713b1edbc	1348	return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	171:3a7713b1edbc	1349	}
AnnaBridge	171:3a7713b1edbc	1350	else
AnnaBridge	171:3a7713b1edbc	1351	{
AnnaBridge	171:3a7713b1edbc	1352	return(0U);
AnnaBridge	171:3a7713b1edbc	1353	}
AnnaBridge	171:3a7713b1edbc	1354	}
AnnaBridge	171:3a7713b1edbc	1355
AnnaBridge	171:3a7713b1edbc	1356
AnnaBridge	171:3a7713b1edbc	1357	/**
AnnaBridge	171:3a7713b1edbc	1358	\brief Disable Interrupt
AnnaBridge	171:3a7713b1edbc	1359	\details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	171:3a7713b1edbc	1360	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1361	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1362	*/
AnnaBridge	171:3a7713b1edbc	1363	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1364	{
AnnaBridge	171:3a7713b1edbc	1365	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1366	{
AnnaBridge	171:3a7713b1edbc	1367	NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	171:3a7713b1edbc	1368	__DSB();
AnnaBridge	171:3a7713b1edbc	1369	__ISB();
AnnaBridge	171:3a7713b1edbc	1370	}
AnnaBridge	171:3a7713b1edbc	1371	}
AnnaBridge	171:3a7713b1edbc	1372
AnnaBridge	171:3a7713b1edbc	1373
AnnaBridge	171:3a7713b1edbc	1374	/**
AnnaBridge	171:3a7713b1edbc	1375	\brief Get Pending Interrupt
AnnaBridge	171:3a7713b1edbc	1376	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge	171:3a7713b1edbc	1377	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1378	\return 0 Interrupt status is not pending.
AnnaBridge	171:3a7713b1edbc	1379	\return 1 Interrupt status is pending.
AnnaBridge	171:3a7713b1edbc	1380	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1381	*/
AnnaBridge	171:3a7713b1edbc	1382	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1383	{
AnnaBridge	171:3a7713b1edbc	1384	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1385	{
AnnaBridge	171:3a7713b1edbc	1386	return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	171:3a7713b1edbc	1387	}
AnnaBridge	171:3a7713b1edbc	1388	else
AnnaBridge	171:3a7713b1edbc	1389	{
AnnaBridge	171:3a7713b1edbc	1390	return(0U);
AnnaBridge	171:3a7713b1edbc	1391	}
AnnaBridge	171:3a7713b1edbc	1392	}
AnnaBridge	171:3a7713b1edbc	1393
AnnaBridge	171:3a7713b1edbc	1394
AnnaBridge	171:3a7713b1edbc	1395	/**
AnnaBridge	171:3a7713b1edbc	1396	\brief Set Pending Interrupt
AnnaBridge	171:3a7713b1edbc	1397	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	171:3a7713b1edbc	1398	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1399	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1400	*/
AnnaBridge	171:3a7713b1edbc	1401	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1402	{
AnnaBridge	171:3a7713b1edbc	1403	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1404	{
AnnaBridge	171:3a7713b1edbc	1405	NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	171:3a7713b1edbc	1406	}
AnnaBridge	171:3a7713b1edbc	1407	}
AnnaBridge	171:3a7713b1edbc	1408
AnnaBridge	171:3a7713b1edbc	1409
AnnaBridge	171:3a7713b1edbc	1410	/**
AnnaBridge	171:3a7713b1edbc	1411	\brief Clear Pending Interrupt
AnnaBridge	171:3a7713b1edbc	1412	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	171:3a7713b1edbc	1413	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1414	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1415	*/
AnnaBridge	171:3a7713b1edbc	1416	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1417	{
AnnaBridge	171:3a7713b1edbc	1418	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1419	{
AnnaBridge	171:3a7713b1edbc	1420	NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	171:3a7713b1edbc	1421	}
AnnaBridge	171:3a7713b1edbc	1422	}
AnnaBridge	171:3a7713b1edbc	1423
AnnaBridge	171:3a7713b1edbc	1424
AnnaBridge	171:3a7713b1edbc	1425	/**
AnnaBridge	171:3a7713b1edbc	1426	\brief Get Active Interrupt
AnnaBridge	171:3a7713b1edbc	1427	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge	171:3a7713b1edbc	1428	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1429	\return 0 Interrupt status is not active.
AnnaBridge	171:3a7713b1edbc	1430	\return 1 Interrupt status is active.
AnnaBridge	171:3a7713b1edbc	1431	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1432	*/
AnnaBridge	171:3a7713b1edbc	1433	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1434	{
AnnaBridge	171:3a7713b1edbc	1435	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1436	{
AnnaBridge	171:3a7713b1edbc	1437	return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	171:3a7713b1edbc	1438	}
AnnaBridge	171:3a7713b1edbc	1439	else
AnnaBridge	171:3a7713b1edbc	1440	{
AnnaBridge	171:3a7713b1edbc	1441	return(0U);
AnnaBridge	171:3a7713b1edbc	1442	}
AnnaBridge	171:3a7713b1edbc	1443	}
AnnaBridge	171:3a7713b1edbc	1444
AnnaBridge	171:3a7713b1edbc	1445
AnnaBridge	171:3a7713b1edbc	1446	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	171:3a7713b1edbc	1447	/**
AnnaBridge	171:3a7713b1edbc	1448	\brief Get Interrupt Target State
AnnaBridge	171:3a7713b1edbc	1449	\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge	171:3a7713b1edbc	1450	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1451	\return 0 if interrupt is assigned to Secure
AnnaBridge	171:3a7713b1edbc	1452	\return 1 if interrupt is assigned to Non Secure
AnnaBridge	171:3a7713b1edbc	1453	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1454	*/
AnnaBridge	171:3a7713b1edbc	1455	__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1456	{
AnnaBridge	171:3a7713b1edbc	1457	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1458	{
AnnaBridge	171:3a7713b1edbc	1459	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	171:3a7713b1edbc	1460	}
AnnaBridge	171:3a7713b1edbc	1461	else
AnnaBridge	171:3a7713b1edbc	1462	{
AnnaBridge	171:3a7713b1edbc	1463	return(0U);
AnnaBridge	171:3a7713b1edbc	1464	}
AnnaBridge	171:3a7713b1edbc	1465	}
AnnaBridge	171:3a7713b1edbc	1466
AnnaBridge	171:3a7713b1edbc	1467
AnnaBridge	171:3a7713b1edbc	1468	/**
AnnaBridge	171:3a7713b1edbc	1469	\brief Set Interrupt Target State
AnnaBridge	171:3a7713b1edbc	1470	\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge	171:3a7713b1edbc	1471	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1472	\return 0 if interrupt is assigned to Secure
AnnaBridge	171:3a7713b1edbc	1473	1 if interrupt is assigned to Non Secure
AnnaBridge	171:3a7713b1edbc	1474	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1475	*/
AnnaBridge	171:3a7713b1edbc	1476	__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1477	{
AnnaBridge	171:3a7713b1edbc	1478	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1479	{
AnnaBridge	171:3a7713b1edbc	1480	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] \|= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
AnnaBridge	171:3a7713b1edbc	1481	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	171:3a7713b1edbc	1482	}
AnnaBridge	171:3a7713b1edbc	1483	else
AnnaBridge	171:3a7713b1edbc	1484	{
AnnaBridge	171:3a7713b1edbc	1485	return(0U);
AnnaBridge	171:3a7713b1edbc	1486	}
AnnaBridge	171:3a7713b1edbc	1487	}
AnnaBridge	171:3a7713b1edbc	1488
AnnaBridge	171:3a7713b1edbc	1489
AnnaBridge	171:3a7713b1edbc	1490	/**
AnnaBridge	171:3a7713b1edbc	1491	\brief Clear Interrupt Target State
AnnaBridge	171:3a7713b1edbc	1492	\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge	171:3a7713b1edbc	1493	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1494	\return 0 if interrupt is assigned to Secure
AnnaBridge	171:3a7713b1edbc	1495	1 if interrupt is assigned to Non Secure
AnnaBridge	171:3a7713b1edbc	1496	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1497	*/
AnnaBridge	171:3a7713b1edbc	1498	__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1499	{
AnnaBridge	171:3a7713b1edbc	1500	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1501	{
AnnaBridge	171:3a7713b1edbc	1502	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
AnnaBridge	171:3a7713b1edbc	1503	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	171:3a7713b1edbc	1504	}
AnnaBridge	171:3a7713b1edbc	1505	else
AnnaBridge	171:3a7713b1edbc	1506	{
AnnaBridge	171:3a7713b1edbc	1507	return(0U);
AnnaBridge	171:3a7713b1edbc	1508	}
AnnaBridge	171:3a7713b1edbc	1509	}
AnnaBridge	171:3a7713b1edbc	1510	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	171:3a7713b1edbc	1511
AnnaBridge	171:3a7713b1edbc	1512
AnnaBridge	171:3a7713b1edbc	1513	/**
AnnaBridge	171:3a7713b1edbc	1514	\brief Set Interrupt Priority
AnnaBridge	171:3a7713b1edbc	1515	\details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge	171:3a7713b1edbc	1516	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	171:3a7713b1edbc	1517	or negative to specify a processor exception.
AnnaBridge	171:3a7713b1edbc	1518	\param [in] IRQn Interrupt number.
AnnaBridge	171:3a7713b1edbc	1519	\param [in] priority Priority to set.
AnnaBridge	171:3a7713b1edbc	1520	\note The priority cannot be set for every processor exception.
AnnaBridge	171:3a7713b1edbc	1521	*/
AnnaBridge	171:3a7713b1edbc	1522	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	171:3a7713b1edbc	1523	{
AnnaBridge	171:3a7713b1edbc	1524	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1525	{
AnnaBridge	171:3a7713b1edbc	1526	NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
AnnaBridge	171:3a7713b1edbc	1527	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge	171:3a7713b1edbc	1528	}
AnnaBridge	171:3a7713b1edbc	1529	else
AnnaBridge	171:3a7713b1edbc	1530	{
AnnaBridge	171:3a7713b1edbc	1531	SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
AnnaBridge	171:3a7713b1edbc	1532	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge	171:3a7713b1edbc	1533	}
AnnaBridge	171:3a7713b1edbc	1534	}
AnnaBridge	171:3a7713b1edbc	1535
AnnaBridge	171:3a7713b1edbc	1536
AnnaBridge	171:3a7713b1edbc	1537	/**
AnnaBridge	171:3a7713b1edbc	1538	\brief Get Interrupt Priority
AnnaBridge	171:3a7713b1edbc	1539	\details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge	171:3a7713b1edbc	1540	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	171:3a7713b1edbc	1541	or negative to specify a processor exception.
AnnaBridge	171:3a7713b1edbc	1542	\param [in] IRQn Interrupt number.
AnnaBridge	171:3a7713b1edbc	1543	\return Interrupt Priority.
AnnaBridge	171:3a7713b1edbc	1544	Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	171:3a7713b1edbc	1545	*/
AnnaBridge	171:3a7713b1edbc	1546	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1547	{
AnnaBridge	171:3a7713b1edbc	1548
AnnaBridge	171:3a7713b1edbc	1549	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1550	{
AnnaBridge	171:3a7713b1edbc	1551	return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	171:3a7713b1edbc	1552	}
AnnaBridge	171:3a7713b1edbc	1553	else
AnnaBridge	171:3a7713b1edbc	1554	{
AnnaBridge	171:3a7713b1edbc	1555	return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	171:3a7713b1edbc	1556	}
AnnaBridge	171:3a7713b1edbc	1557	}
AnnaBridge	171:3a7713b1edbc	1558
AnnaBridge	171:3a7713b1edbc	1559
AnnaBridge	171:3a7713b1edbc	1560	/**
AnnaBridge	171:3a7713b1edbc	1561	\brief Encode Priority
AnnaBridge	171:3a7713b1edbc	1562	\details Encodes the priority for an interrupt with the given priority group,
AnnaBridge	171:3a7713b1edbc	1563	preemptive priority value, and subpriority value.
AnnaBridge	171:3a7713b1edbc	1564	In case of a conflict between priority grouping and available
AnnaBridge	171:3a7713b1edbc	1565	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	171:3a7713b1edbc	1566	\param [in] PriorityGroup Used priority group.
AnnaBridge	171:3a7713b1edbc	1567	\param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	171:3a7713b1edbc	1568	\param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge	171:3a7713b1edbc	1569	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge	171:3a7713b1edbc	1570	*/
AnnaBridge	171:3a7713b1edbc	1571	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge	171:3a7713b1edbc	1572	{
AnnaBridge	171:3a7713b1edbc	1573	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	171:3a7713b1edbc	1574	uint32_t PreemptPriorityBits;
AnnaBridge	171:3a7713b1edbc	1575	uint32_t SubPriorityBits;
AnnaBridge	171:3a7713b1edbc	1576
AnnaBridge	171:3a7713b1edbc	1577	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	171:3a7713b1edbc	1578	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	171:3a7713b1edbc	1579
AnnaBridge	171:3a7713b1edbc	1580	return (
AnnaBridge	171:3a7713b1edbc	1581	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
AnnaBridge	171:3a7713b1edbc	1582	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge	171:3a7713b1edbc	1583	);
AnnaBridge	171:3a7713b1edbc	1584	}
AnnaBridge	171:3a7713b1edbc	1585
AnnaBridge	171:3a7713b1edbc	1586
AnnaBridge	171:3a7713b1edbc	1587	/**
AnnaBridge	171:3a7713b1edbc	1588	\brief Decode Priority
AnnaBridge	171:3a7713b1edbc	1589	\details Decodes an interrupt priority value with a given priority group to
AnnaBridge	171:3a7713b1edbc	1590	preemptive priority value and subpriority value.
AnnaBridge	171:3a7713b1edbc	1591	In case of a conflict between priority grouping and available
AnnaBridge	171:3a7713b1edbc	1592	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge	171:3a7713b1edbc	1593	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge	171:3a7713b1edbc	1594	\param [in] PriorityGroup Used priority group.
AnnaBridge	171:3a7713b1edbc	1595	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	171:3a7713b1edbc	1596	\param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge	171:3a7713b1edbc	1597	*/
AnnaBridge	171:3a7713b1edbc	1598	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
AnnaBridge	171:3a7713b1edbc	1599	{
AnnaBridge	171:3a7713b1edbc	1600	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	171:3a7713b1edbc	1601	uint32_t PreemptPriorityBits;
AnnaBridge	171:3a7713b1edbc	1602	uint32_t SubPriorityBits;
AnnaBridge	171:3a7713b1edbc	1603
AnnaBridge	171:3a7713b1edbc	1604	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	171:3a7713b1edbc	1605	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	171:3a7713b1edbc	1606
AnnaBridge	171:3a7713b1edbc	1607	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge	171:3a7713b1edbc	1608	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge	171:3a7713b1edbc	1609	}
AnnaBridge	171:3a7713b1edbc	1610
AnnaBridge	171:3a7713b1edbc	1611
AnnaBridge	171:3a7713b1edbc	1612	/**
AnnaBridge	171:3a7713b1edbc	1613	\brief Set Interrupt Vector
AnnaBridge	171:3a7713b1edbc	1614	\details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge	171:3a7713b1edbc	1615	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	171:3a7713b1edbc	1616	or negative to specify a processor exception.
AnnaBridge	171:3a7713b1edbc	1617	VTOR must been relocated to SRAM before.
AnnaBridge	171:3a7713b1edbc	1618	If VTOR is not present address 0 must be mapped to SRAM.
AnnaBridge	171:3a7713b1edbc	1619	\param [in] IRQn Interrupt number
AnnaBridge	171:3a7713b1edbc	1620	\param [in] vector Address of interrupt handler function
AnnaBridge	171:3a7713b1edbc	1621	*/
AnnaBridge	171:3a7713b1edbc	1622	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge	171:3a7713b1edbc	1623	{
AnnaBridge	171:3a7713b1edbc	1624	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	1625	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	171:3a7713b1edbc	1626	#else
AnnaBridge	171:3a7713b1edbc	1627	uint32_t vectors = (uint32_t )0x0U;
AnnaBridge	171:3a7713b1edbc	1628	#endif
AnnaBridge	171:3a7713b1edbc	1629	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge	171:3a7713b1edbc	1630	}
AnnaBridge	171:3a7713b1edbc	1631
AnnaBridge	171:3a7713b1edbc	1632
AnnaBridge	171:3a7713b1edbc	1633	/**
AnnaBridge	171:3a7713b1edbc	1634	\brief Get Interrupt Vector
AnnaBridge	171:3a7713b1edbc	1635	\details Reads an interrupt vector from interrupt vector table.
AnnaBridge	171:3a7713b1edbc	1636	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	171:3a7713b1edbc	1637	or negative to specify a processor exception.
AnnaBridge	171:3a7713b1edbc	1638	\param [in] IRQn Interrupt number.
AnnaBridge	171:3a7713b1edbc	1639	\return Address of interrupt handler function
AnnaBridge	171:3a7713b1edbc	1640	*/
AnnaBridge	171:3a7713b1edbc	1641	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1642	{
AnnaBridge	171:3a7713b1edbc	1643	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	1644	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	171:3a7713b1edbc	1645	#else
AnnaBridge	171:3a7713b1edbc	1646	uint32_t vectors = (uint32_t )0x0U;
AnnaBridge	171:3a7713b1edbc	1647	#endif
AnnaBridge	171:3a7713b1edbc	1648	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge	171:3a7713b1edbc	1649	}
AnnaBridge	171:3a7713b1edbc	1650
AnnaBridge	171:3a7713b1edbc	1651
AnnaBridge	171:3a7713b1edbc	1652	/**
AnnaBridge	171:3a7713b1edbc	1653	\brief System Reset
AnnaBridge	171:3a7713b1edbc	1654	\details Initiates a system reset request to reset the MCU.
AnnaBridge	171:3a7713b1edbc	1655	*/
AnnaBridge	171:3a7713b1edbc	1656	__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge	171:3a7713b1edbc	1657	{
AnnaBridge	171:3a7713b1edbc	1658	__DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge	171:3a7713b1edbc	1659	buffered write are completed before reset */
AnnaBridge	171:3a7713b1edbc	1660	SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	171:3a7713b1edbc	1661	SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge	171:3a7713b1edbc	1662	__DSB(); /* Ensure completion of memory access */
AnnaBridge	171:3a7713b1edbc	1663
AnnaBridge	171:3a7713b1edbc	1664	for(;;) /* wait until reset */
AnnaBridge	171:3a7713b1edbc	1665	{
AnnaBridge	171:3a7713b1edbc	1666	__NOP();
AnnaBridge	171:3a7713b1edbc	1667	}
AnnaBridge	171:3a7713b1edbc	1668	}
AnnaBridge	171:3a7713b1edbc	1669
AnnaBridge	171:3a7713b1edbc	1670	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	171:3a7713b1edbc	1671	/**
AnnaBridge	171:3a7713b1edbc	1672	\brief Enable Interrupt (non-secure)
AnnaBridge	171:3a7713b1edbc	1673	\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge	171:3a7713b1edbc	1674	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1675	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1676	*/
AnnaBridge	171:3a7713b1edbc	1677	__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1678	{
AnnaBridge	171:3a7713b1edbc	1679	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1680	{
AnnaBridge	171:3a7713b1edbc	1681	NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	171:3a7713b1edbc	1682	}
AnnaBridge	171:3a7713b1edbc	1683	}
AnnaBridge	171:3a7713b1edbc	1684
AnnaBridge	171:3a7713b1edbc	1685
AnnaBridge	171:3a7713b1edbc	1686	/**
AnnaBridge	171:3a7713b1edbc	1687	\brief Get Interrupt Enable status (non-secure)
AnnaBridge	171:3a7713b1edbc	1688	\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
AnnaBridge	171:3a7713b1edbc	1689	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1690	\return 0 Interrupt is not enabled.
AnnaBridge	171:3a7713b1edbc	1691	\return 1 Interrupt is enabled.
AnnaBridge	171:3a7713b1edbc	1692	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1693	*/
AnnaBridge	171:3a7713b1edbc	1694	__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1695	{
AnnaBridge	171:3a7713b1edbc	1696	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1697	{
AnnaBridge	171:3a7713b1edbc	1698	return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	171:3a7713b1edbc	1699	}
AnnaBridge	171:3a7713b1edbc	1700	else
AnnaBridge	171:3a7713b1edbc	1701	{
AnnaBridge	171:3a7713b1edbc	1702	return(0U);
AnnaBridge	171:3a7713b1edbc	1703	}
AnnaBridge	171:3a7713b1edbc	1704	}
AnnaBridge	171:3a7713b1edbc	1705
AnnaBridge	171:3a7713b1edbc	1706
AnnaBridge	171:3a7713b1edbc	1707	/**
AnnaBridge	171:3a7713b1edbc	1708	\brief Disable Interrupt (non-secure)
AnnaBridge	171:3a7713b1edbc	1709	\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge	171:3a7713b1edbc	1710	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1711	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1712	*/
AnnaBridge	171:3a7713b1edbc	1713	__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1714	{
AnnaBridge	171:3a7713b1edbc	1715	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1716	{
AnnaBridge	171:3a7713b1edbc	1717	NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	171:3a7713b1edbc	1718	}
AnnaBridge	171:3a7713b1edbc	1719	}
AnnaBridge	171:3a7713b1edbc	1720
AnnaBridge	171:3a7713b1edbc	1721
AnnaBridge	171:3a7713b1edbc	1722	/**
AnnaBridge	171:3a7713b1edbc	1723	\brief Get Pending Interrupt (non-secure)
AnnaBridge	171:3a7713b1edbc	1724	\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
AnnaBridge	171:3a7713b1edbc	1725	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1726	\return 0 Interrupt status is not pending.
AnnaBridge	171:3a7713b1edbc	1727	\return 1 Interrupt status is pending.
AnnaBridge	171:3a7713b1edbc	1728	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1729	*/
AnnaBridge	171:3a7713b1edbc	1730	__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1731	{
AnnaBridge	171:3a7713b1edbc	1732	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1733	{
AnnaBridge	171:3a7713b1edbc	1734	return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	171:3a7713b1edbc	1735	}
AnnaBridge	171:3a7713b1edbc	1736	else
AnnaBridge	171:3a7713b1edbc	1737	{
AnnaBridge	171:3a7713b1edbc	1738	return(0U);
AnnaBridge	171:3a7713b1edbc	1739	}
AnnaBridge	171:3a7713b1edbc	1740	}
AnnaBridge	171:3a7713b1edbc	1741
AnnaBridge	171:3a7713b1edbc	1742
AnnaBridge	171:3a7713b1edbc	1743	/**
AnnaBridge	171:3a7713b1edbc	1744	\brief Set Pending Interrupt (non-secure)
AnnaBridge	171:3a7713b1edbc	1745	\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge	171:3a7713b1edbc	1746	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1747	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1748	*/
AnnaBridge	171:3a7713b1edbc	1749	__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1750	{
AnnaBridge	171:3a7713b1edbc	1751	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1752	{
AnnaBridge	171:3a7713b1edbc	1753	NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	171:3a7713b1edbc	1754	}
AnnaBridge	171:3a7713b1edbc	1755	}
AnnaBridge	171:3a7713b1edbc	1756
AnnaBridge	171:3a7713b1edbc	1757
AnnaBridge	171:3a7713b1edbc	1758	/**
AnnaBridge	171:3a7713b1edbc	1759	\brief Clear Pending Interrupt (non-secure)
AnnaBridge	171:3a7713b1edbc	1760	\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge	171:3a7713b1edbc	1761	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1762	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1763	*/
AnnaBridge	171:3a7713b1edbc	1764	__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1765	{
AnnaBridge	171:3a7713b1edbc	1766	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1767	{
AnnaBridge	171:3a7713b1edbc	1768	NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	171:3a7713b1edbc	1769	}
AnnaBridge	171:3a7713b1edbc	1770	}
AnnaBridge	171:3a7713b1edbc	1771
AnnaBridge	171:3a7713b1edbc	1772
AnnaBridge	171:3a7713b1edbc	1773	/**
AnnaBridge	171:3a7713b1edbc	1774	\brief Get Active Interrupt (non-secure)
AnnaBridge	171:3a7713b1edbc	1775	\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
AnnaBridge	171:3a7713b1edbc	1776	\param [in] IRQn Device specific interrupt number.
AnnaBridge	171:3a7713b1edbc	1777	\return 0 Interrupt status is not active.
AnnaBridge	171:3a7713b1edbc	1778	\return 1 Interrupt status is active.
AnnaBridge	171:3a7713b1edbc	1779	\note IRQn must not be negative.
AnnaBridge	171:3a7713b1edbc	1780	*/
AnnaBridge	171:3a7713b1edbc	1781	__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1782	{
AnnaBridge	171:3a7713b1edbc	1783	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1784	{
AnnaBridge	171:3a7713b1edbc	1785	return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	171:3a7713b1edbc	1786	}
AnnaBridge	171:3a7713b1edbc	1787	else
AnnaBridge	171:3a7713b1edbc	1788	{
AnnaBridge	171:3a7713b1edbc	1789	return(0U);
AnnaBridge	171:3a7713b1edbc	1790	}
AnnaBridge	171:3a7713b1edbc	1791	}
AnnaBridge	171:3a7713b1edbc	1792
AnnaBridge	171:3a7713b1edbc	1793
AnnaBridge	171:3a7713b1edbc	1794	/**
AnnaBridge	171:3a7713b1edbc	1795	\brief Set Interrupt Priority (non-secure)
AnnaBridge	171:3a7713b1edbc	1796	\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge	171:3a7713b1edbc	1797	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	171:3a7713b1edbc	1798	or negative to specify a processor exception.
AnnaBridge	171:3a7713b1edbc	1799	\param [in] IRQn Interrupt number.
AnnaBridge	171:3a7713b1edbc	1800	\param [in] priority Priority to set.
AnnaBridge	171:3a7713b1edbc	1801	\note The priority cannot be set for every non-secure processor exception.
AnnaBridge	171:3a7713b1edbc	1802	*/
AnnaBridge	171:3a7713b1edbc	1803	__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	171:3a7713b1edbc	1804	{
AnnaBridge	171:3a7713b1edbc	1805	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1806	{
AnnaBridge	171:3a7713b1edbc	1807	NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
AnnaBridge	171:3a7713b1edbc	1808	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge	171:3a7713b1edbc	1809	}
AnnaBridge	171:3a7713b1edbc	1810	else
AnnaBridge	171:3a7713b1edbc	1811	{
AnnaBridge	171:3a7713b1edbc	1812	SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
AnnaBridge	171:3a7713b1edbc	1813	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge	171:3a7713b1edbc	1814	}
AnnaBridge	171:3a7713b1edbc	1815	}
AnnaBridge	171:3a7713b1edbc	1816
AnnaBridge	171:3a7713b1edbc	1817
AnnaBridge	171:3a7713b1edbc	1818	/**
AnnaBridge	171:3a7713b1edbc	1819	\brief Get Interrupt Priority (non-secure)
AnnaBridge	171:3a7713b1edbc	1820	\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge	171:3a7713b1edbc	1821	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	171:3a7713b1edbc	1822	or negative to specify a processor exception.
AnnaBridge	171:3a7713b1edbc	1823	\param [in] IRQn Interrupt number.
AnnaBridge	171:3a7713b1edbc	1824	\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	171:3a7713b1edbc	1825	*/
AnnaBridge	171:3a7713b1edbc	1826	__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1827	{
AnnaBridge	171:3a7713b1edbc	1828
AnnaBridge	171:3a7713b1edbc	1829	if ((int32_t)(IRQn) >= 0)
AnnaBridge	171:3a7713b1edbc	1830	{
AnnaBridge	171:3a7713b1edbc	1831	return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	171:3a7713b1edbc	1832	}
AnnaBridge	171:3a7713b1edbc	1833	else
AnnaBridge	171:3a7713b1edbc	1834	{
AnnaBridge	171:3a7713b1edbc	1835	return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	171:3a7713b1edbc	1836	}
AnnaBridge	171:3a7713b1edbc	1837	}
AnnaBridge	171:3a7713b1edbc	1838	#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	171:3a7713b1edbc	1839
AnnaBridge	171:3a7713b1edbc	1840	/@} end of CMSIS_Core_NVICFunctions /
AnnaBridge	171:3a7713b1edbc	1841
AnnaBridge	171:3a7713b1edbc	1842	/* ########################## MPU functions #################################### */
AnnaBridge	171:3a7713b1edbc	1843
AnnaBridge	171:3a7713b1edbc	1844	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	1845
AnnaBridge	171:3a7713b1edbc	1846	#include "mpu_armv8.h"
AnnaBridge	171:3a7713b1edbc	1847
AnnaBridge	171:3a7713b1edbc	1848	#endif
AnnaBridge	171:3a7713b1edbc	1849
AnnaBridge	171:3a7713b1edbc	1850	/* ########################## FPU functions #################################### */
AnnaBridge	171:3a7713b1edbc	1851	/**
AnnaBridge	171:3a7713b1edbc	1852	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	171:3a7713b1edbc	1853	\defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge	171:3a7713b1edbc	1854	\brief Function that provides FPU type.
AnnaBridge	171:3a7713b1edbc	1855	@{
AnnaBridge	171:3a7713b1edbc	1856	*/
AnnaBridge	171:3a7713b1edbc	1857
AnnaBridge	171:3a7713b1edbc	1858	/**
AnnaBridge	171:3a7713b1edbc	1859	\brief get FPU type
AnnaBridge	171:3a7713b1edbc	1860	\details returns the FPU type
AnnaBridge	171:3a7713b1edbc	1861	\returns
AnnaBridge	171:3a7713b1edbc	1862	- \b 0: No FPU
AnnaBridge	171:3a7713b1edbc	1863	- \b 1: Single precision FPU
AnnaBridge	171:3a7713b1edbc	1864	- \b 2: Double + Single precision FPU
AnnaBridge	171:3a7713b1edbc	1865	*/
AnnaBridge	171:3a7713b1edbc	1866	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge	171:3a7713b1edbc	1867	{
AnnaBridge	171:3a7713b1edbc	1868	return 0U; /* No FPU */
AnnaBridge	171:3a7713b1edbc	1869	}
AnnaBridge	171:3a7713b1edbc	1870
AnnaBridge	171:3a7713b1edbc	1871
AnnaBridge	171:3a7713b1edbc	1872	/@} end of CMSIS_Core_FpuFunctions /
AnnaBridge	171:3a7713b1edbc	1873
AnnaBridge	171:3a7713b1edbc	1874
AnnaBridge	171:3a7713b1edbc	1875
AnnaBridge	171:3a7713b1edbc	1876	/* ########################## SAU functions #################################### */
AnnaBridge	171:3a7713b1edbc	1877	/**
AnnaBridge	171:3a7713b1edbc	1878	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	171:3a7713b1edbc	1879	\defgroup CMSIS_Core_SAUFunctions SAU Functions
AnnaBridge	171:3a7713b1edbc	1880	\brief Functions that configure the SAU.
AnnaBridge	171:3a7713b1edbc	1881	@{
AnnaBridge	171:3a7713b1edbc	1882	*/
AnnaBridge	171:3a7713b1edbc	1883
AnnaBridge	171:3a7713b1edbc	1884	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	171:3a7713b1edbc	1885
AnnaBridge	171:3a7713b1edbc	1886	/**
AnnaBridge	171:3a7713b1edbc	1887	\brief Enable SAU
AnnaBridge	171:3a7713b1edbc	1888	\details Enables the Security Attribution Unit (SAU).
AnnaBridge	171:3a7713b1edbc	1889	*/
AnnaBridge	171:3a7713b1edbc	1890	__STATIC_INLINE void TZ_SAU_Enable(void)
AnnaBridge	171:3a7713b1edbc	1891	{
AnnaBridge	171:3a7713b1edbc	1892	SAU->CTRL \|= (SAU_CTRL_ENABLE_Msk);
AnnaBridge	171:3a7713b1edbc	1893	}
AnnaBridge	171:3a7713b1edbc	1894
AnnaBridge	171:3a7713b1edbc	1895
AnnaBridge	171:3a7713b1edbc	1896
AnnaBridge	171:3a7713b1edbc	1897	/**
AnnaBridge	171:3a7713b1edbc	1898	\brief Disable SAU
AnnaBridge	171:3a7713b1edbc	1899	\details Disables the Security Attribution Unit (SAU).
AnnaBridge	171:3a7713b1edbc	1900	*/
AnnaBridge	171:3a7713b1edbc	1901	__STATIC_INLINE void TZ_SAU_Disable(void)
AnnaBridge	171:3a7713b1edbc	1902	{
AnnaBridge	171:3a7713b1edbc	1903	SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
AnnaBridge	171:3a7713b1edbc	1904	}
AnnaBridge	171:3a7713b1edbc	1905
AnnaBridge	171:3a7713b1edbc	1906	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	171:3a7713b1edbc	1907
AnnaBridge	171:3a7713b1edbc	1908	/@} end of CMSIS_Core_SAUFunctions /
AnnaBridge	171:3a7713b1edbc	1909
AnnaBridge	171:3a7713b1edbc	1910
AnnaBridge	171:3a7713b1edbc	1911
AnnaBridge	171:3a7713b1edbc	1912
AnnaBridge	171:3a7713b1edbc	1913	/* ################################## SysTick function ############################################ */
AnnaBridge	171:3a7713b1edbc	1914	/**
AnnaBridge	171:3a7713b1edbc	1915	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	171:3a7713b1edbc	1916	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge	171:3a7713b1edbc	1917	\brief Functions that configure the System.
AnnaBridge	171:3a7713b1edbc	1918	@{
AnnaBridge	171:3a7713b1edbc	1919	*/
AnnaBridge	171:3a7713b1edbc	1920
AnnaBridge	171:3a7713b1edbc	1921	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge	171:3a7713b1edbc	1922
AnnaBridge	171:3a7713b1edbc	1923	/**
AnnaBridge	171:3a7713b1edbc	1924	\brief System Tick Configuration
AnnaBridge	171:3a7713b1edbc	1925	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge	171:3a7713b1edbc	1926	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	171:3a7713b1edbc	1927	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	171:3a7713b1edbc	1928	\return 0 Function succeeded.
AnnaBridge	171:3a7713b1edbc	1929	\return 1 Function failed.
AnnaBridge	171:3a7713b1edbc	1930	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	171:3a7713b1edbc	1931	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	171:3a7713b1edbc	1932	must contain a vendor-specific implementation of this function.
AnnaBridge	171:3a7713b1edbc	1933	*/
AnnaBridge	171:3a7713b1edbc	1934	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge	171:3a7713b1edbc	1935	{
AnnaBridge	171:3a7713b1edbc	1936	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	171:3a7713b1edbc	1937	{
AnnaBridge	171:3a7713b1edbc	1938	return (1UL); /* Reload value impossible */
AnnaBridge	171:3a7713b1edbc	1939	}
AnnaBridge	171:3a7713b1edbc	1940
AnnaBridge	171:3a7713b1edbc	1941	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge	171:3a7713b1edbc	1942	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge	171:3a7713b1edbc	1943	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge	171:3a7713b1edbc	1944	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
AnnaBridge	171:3a7713b1edbc	1945	SysTick_CTRL_TICKINT_Msk \|
AnnaBridge	171:3a7713b1edbc	1946	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge	171:3a7713b1edbc	1947	return (0UL); /* Function successful */
AnnaBridge	171:3a7713b1edbc	1948	}
AnnaBridge	171:3a7713b1edbc	1949
AnnaBridge	171:3a7713b1edbc	1950	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	171:3a7713b1edbc	1951	/**
AnnaBridge	171:3a7713b1edbc	1952	\brief System Tick Configuration (non-secure)
AnnaBridge	171:3a7713b1edbc	1953	\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
AnnaBridge	171:3a7713b1edbc	1954	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	171:3a7713b1edbc	1955	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	171:3a7713b1edbc	1956	\return 0 Function succeeded.
AnnaBridge	171:3a7713b1edbc	1957	\return 1 Function failed.
AnnaBridge	171:3a7713b1edbc	1958	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	171:3a7713b1edbc	1959	function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	171:3a7713b1edbc	1960	must contain a vendor-specific implementation of this function.
AnnaBridge	171:3a7713b1edbc	1961
AnnaBridge	171:3a7713b1edbc	1962	*/
AnnaBridge	171:3a7713b1edbc	1963	__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
AnnaBridge	171:3a7713b1edbc	1964	{
AnnaBridge	171:3a7713b1edbc	1965	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	171:3a7713b1edbc	1966	{
AnnaBridge	171:3a7713b1edbc	1967	return (1UL); /* Reload value impossible */
AnnaBridge	171:3a7713b1edbc	1968	}
AnnaBridge	171:3a7713b1edbc	1969
AnnaBridge	171:3a7713b1edbc	1970	SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge	171:3a7713b1edbc	1971	TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge	171:3a7713b1edbc	1972	SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge	171:3a7713b1edbc	1973	SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
AnnaBridge	171:3a7713b1edbc	1974	SysTick_CTRL_TICKINT_Msk \|
AnnaBridge	171:3a7713b1edbc	1975	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge	171:3a7713b1edbc	1976	return (0UL); /* Function successful */
AnnaBridge	171:3a7713b1edbc	1977	}
AnnaBridge	171:3a7713b1edbc	1978	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	171:3a7713b1edbc	1979
AnnaBridge	171:3a7713b1edbc	1980	#endif
AnnaBridge	171:3a7713b1edbc	1981
AnnaBridge	171:3a7713b1edbc	1982	/@} end of CMSIS_Core_SysTickFunctions /
AnnaBridge	171:3a7713b1edbc	1983
AnnaBridge	171:3a7713b1edbc	1984
AnnaBridge	171:3a7713b1edbc	1985
AnnaBridge	171:3a7713b1edbc	1986
AnnaBridge	171:3a7713b1edbc	1987	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	1988	}
AnnaBridge	171:3a7713b1edbc	1989	#endif
AnnaBridge	171:3a7713b1edbc	1990
AnnaBridge	171:3a7713b1edbc	1991	#endif /* __CORE_CM23_H_DEPENDANT */
AnnaBridge	171:3a7713b1edbc	1992
AnnaBridge	171:3a7713b1edbc	1993	#endif /* __CMSIS_GENERIC */