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TARGET_KW24D/TOOLCHAIN_IAR/fsl_clock.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge 171:3a7713b1edbc 3 * All rights reserved.
AnnaBridge 171:3a7713b1edbc 4 *
AnnaBridge 171:3a7713b1edbc 5 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 6 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 171:3a7713b1edbc 9 * of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 171:3a7713b1edbc 12 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 171:3a7713b1edbc 13 * other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge 171:3a7713b1edbc 16 * contributors may be used to endorse or promote products derived from this
AnnaBridge 171:3a7713b1edbc 17 * software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 171:3a7713b1edbc 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 171:3a7713b1edbc 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 171:3a7713b1edbc 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 171:3a7713b1edbc 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 171:3a7713b1edbc 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 171:3a7713b1edbc 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 171:3a7713b1edbc 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 29 */
AnnaBridge 171:3a7713b1edbc 30
AnnaBridge 171:3a7713b1edbc 31 #ifndef _FSL_CLOCK_H_
AnnaBridge 171:3a7713b1edbc 32 #define _FSL_CLOCK_H_
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #include "fsl_device_registers.h"
AnnaBridge 171:3a7713b1edbc 35 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 36 #include <stdbool.h>
AnnaBridge 171:3a7713b1edbc 37 #include <assert.h>
AnnaBridge 171:3a7713b1edbc 38
AnnaBridge 171:3a7713b1edbc 39 /*! @addtogroup clock */
AnnaBridge 171:3a7713b1edbc 40 /*! @{ */
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 /*! @file */
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 45 * Definitions
AnnaBridge 171:3a7713b1edbc 46 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 47
AnnaBridge 171:3a7713b1edbc 48 /*! @name Driver version */
AnnaBridge 171:3a7713b1edbc 49 /*@{*/
AnnaBridge 171:3a7713b1edbc 50 /*! @brief CLOCK driver version 2.2.0. */
AnnaBridge 171:3a7713b1edbc 51 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
AnnaBridge 171:3a7713b1edbc 52 /*@}*/
AnnaBridge 171:3a7713b1edbc 53
AnnaBridge 171:3a7713b1edbc 54 /*! @brief External XTAL0 (OSC0) clock frequency.
AnnaBridge 171:3a7713b1edbc 55 *
AnnaBridge 171:3a7713b1edbc 56 * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
AnnaBridge 171:3a7713b1edbc 57 * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
AnnaBridge 171:3a7713b1edbc 58 * if XTAL0 is 8 MHz:
AnnaBridge 171:3a7713b1edbc 59 * @code
AnnaBridge 171:3a7713b1edbc 60 * CLOCK_InitOsc0(...); // Set up the OSC0
AnnaBridge 171:3a7713b1edbc 61 * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to the clock driver.
AnnaBridge 171:3a7713b1edbc 62 * @endcode
AnnaBridge 171:3a7713b1edbc 63 *
AnnaBridge 171:3a7713b1edbc 64 * This is important for the multicore platforms where only one core needs to set up the
AnnaBridge 171:3a7713b1edbc 65 * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
AnnaBridge 171:3a7713b1edbc 66 * to get a valid clock frequency.
AnnaBridge 171:3a7713b1edbc 67 */
AnnaBridge 171:3a7713b1edbc 68 extern uint32_t g_xtal0Freq;
AnnaBridge 171:3a7713b1edbc 69
AnnaBridge 171:3a7713b1edbc 70 /*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
AnnaBridge 171:3a7713b1edbc 71 *
AnnaBridge 171:3a7713b1edbc 72 * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
AnnaBridge 171:3a7713b1edbc 73 * function CLOCK_SetXtal32Freq to set the value in the clock driver.
AnnaBridge 171:3a7713b1edbc 74 *
AnnaBridge 171:3a7713b1edbc 75 * This is important for the multicore platforms where only one core needs to set up
AnnaBridge 171:3a7713b1edbc 76 * the clock. All other cores need to call the CLOCK_SetXtal32Freq
AnnaBridge 171:3a7713b1edbc 77 * to get a valid clock frequency.
AnnaBridge 171:3a7713b1edbc 78 */
AnnaBridge 171:3a7713b1edbc 79 extern uint32_t g_xtal32Freq;
AnnaBridge 171:3a7713b1edbc 80
AnnaBridge 171:3a7713b1edbc 81 #if (defined(OSC) && !(defined(OSC0)))
AnnaBridge 171:3a7713b1edbc 82 #define OSC0 OSC
AnnaBridge 171:3a7713b1edbc 83 #endif
AnnaBridge 171:3a7713b1edbc 84
AnnaBridge 171:3a7713b1edbc 85 /*! @brief Clock ip name array for DMAMUX. */
AnnaBridge 171:3a7713b1edbc 86 #define DMAMUX_CLOCKS \
AnnaBridge 171:3a7713b1edbc 87 { \
AnnaBridge 171:3a7713b1edbc 88 kCLOCK_Dmamux0 \
AnnaBridge 171:3a7713b1edbc 89 }
AnnaBridge 171:3a7713b1edbc 90
AnnaBridge 171:3a7713b1edbc 91 /*! @brief Clock ip name array for RTC. */
AnnaBridge 171:3a7713b1edbc 92 #define RTC_CLOCKS \
AnnaBridge 171:3a7713b1edbc 93 { \
AnnaBridge 171:3a7713b1edbc 94 kCLOCK_Rtc0 \
AnnaBridge 171:3a7713b1edbc 95 }
AnnaBridge 171:3a7713b1edbc 96
AnnaBridge 171:3a7713b1edbc 97 /*! @brief Clock ip name array for SAI. */
AnnaBridge 171:3a7713b1edbc 98 #define SAI_CLOCKS \
AnnaBridge 171:3a7713b1edbc 99 { \
AnnaBridge 171:3a7713b1edbc 100 kCLOCK_Sai0 \
AnnaBridge 171:3a7713b1edbc 101 }
AnnaBridge 171:3a7713b1edbc 102
AnnaBridge 171:3a7713b1edbc 103 /*! @brief Clock ip name array for PORT. */
AnnaBridge 171:3a7713b1edbc 104 #define PORT_CLOCKS \
AnnaBridge 171:3a7713b1edbc 105 { \
AnnaBridge 171:3a7713b1edbc 106 kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
AnnaBridge 171:3a7713b1edbc 107 }
AnnaBridge 171:3a7713b1edbc 108
AnnaBridge 171:3a7713b1edbc 109 /*! @brief Clock ip name array for EWM. */
AnnaBridge 171:3a7713b1edbc 110 #define EWM_CLOCKS \
AnnaBridge 171:3a7713b1edbc 111 { \
AnnaBridge 171:3a7713b1edbc 112 kCLOCK_Ewm0 \
AnnaBridge 171:3a7713b1edbc 113 }
AnnaBridge 171:3a7713b1edbc 114
AnnaBridge 171:3a7713b1edbc 115 /*! @brief Clock ip name array for PIT. */
AnnaBridge 171:3a7713b1edbc 116 #define PIT_CLOCKS \
AnnaBridge 171:3a7713b1edbc 117 { \
AnnaBridge 171:3a7713b1edbc 118 kCLOCK_Pit0 \
AnnaBridge 171:3a7713b1edbc 119 }
AnnaBridge 171:3a7713b1edbc 120
AnnaBridge 171:3a7713b1edbc 121 /*! @brief Clock ip name array for DSPI. */
AnnaBridge 171:3a7713b1edbc 122 #define DSPI_CLOCKS \
AnnaBridge 171:3a7713b1edbc 123 { \
AnnaBridge 171:3a7713b1edbc 124 kCLOCK_Spi0, kCLOCK_Spi1 \
AnnaBridge 171:3a7713b1edbc 125 }
AnnaBridge 171:3a7713b1edbc 126
AnnaBridge 171:3a7713b1edbc 127 /*! @brief Clock ip name array for LPTMR. */
AnnaBridge 171:3a7713b1edbc 128 #define LPTMR_CLOCKS \
AnnaBridge 171:3a7713b1edbc 129 { \
AnnaBridge 171:3a7713b1edbc 130 kCLOCK_Lptmr0 \
AnnaBridge 171:3a7713b1edbc 131 }
AnnaBridge 171:3a7713b1edbc 132
AnnaBridge 171:3a7713b1edbc 133 /*! @brief Clock ip name array for FTM. */
AnnaBridge 171:3a7713b1edbc 134 #define FTM_CLOCKS \
AnnaBridge 171:3a7713b1edbc 135 { \
AnnaBridge 171:3a7713b1edbc 136 kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2 \
AnnaBridge 171:3a7713b1edbc 137 }
AnnaBridge 171:3a7713b1edbc 138
AnnaBridge 171:3a7713b1edbc 139 /*! @brief Clock ip name array for EDMA. */
AnnaBridge 171:3a7713b1edbc 140 #define EDMA_CLOCKS \
AnnaBridge 171:3a7713b1edbc 141 { \
AnnaBridge 171:3a7713b1edbc 142 kCLOCK_Dma0 \
AnnaBridge 171:3a7713b1edbc 143 }
AnnaBridge 171:3a7713b1edbc 144
AnnaBridge 171:3a7713b1edbc 145 /*! @brief Clock ip name array for ADC16. */
AnnaBridge 171:3a7713b1edbc 146 #define ADC16_CLOCKS \
AnnaBridge 171:3a7713b1edbc 147 { \
AnnaBridge 171:3a7713b1edbc 148 kCLOCK_Adc0 \
AnnaBridge 171:3a7713b1edbc 149 }
AnnaBridge 171:3a7713b1edbc 150
AnnaBridge 171:3a7713b1edbc 151 /*! @brief Clock ip name array for CMT. */
AnnaBridge 171:3a7713b1edbc 152 #define CMT_CLOCKS \
AnnaBridge 171:3a7713b1edbc 153 { \
AnnaBridge 171:3a7713b1edbc 154 kCLOCK_Cmt0 \
AnnaBridge 171:3a7713b1edbc 155 }
AnnaBridge 171:3a7713b1edbc 156
AnnaBridge 171:3a7713b1edbc 157 /*! @brief Clock ip name array for UART. */
AnnaBridge 171:3a7713b1edbc 158 #define UART_CLOCKS \
AnnaBridge 171:3a7713b1edbc 159 { \
AnnaBridge 171:3a7713b1edbc 160 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2 \
AnnaBridge 171:3a7713b1edbc 161 }
AnnaBridge 171:3a7713b1edbc 162
AnnaBridge 171:3a7713b1edbc 163 /*! @brief Clock ip name array for RNGA. */
AnnaBridge 171:3a7713b1edbc 164 #define RNGA_CLOCKS \
AnnaBridge 171:3a7713b1edbc 165 { \
AnnaBridge 171:3a7713b1edbc 166 kCLOCK_Rnga0 \
AnnaBridge 171:3a7713b1edbc 167 }
AnnaBridge 171:3a7713b1edbc 168
AnnaBridge 171:3a7713b1edbc 169 /*! @brief Clock ip name array for CRC. */
AnnaBridge 171:3a7713b1edbc 170 #define CRC_CLOCKS \
AnnaBridge 171:3a7713b1edbc 171 { \
AnnaBridge 171:3a7713b1edbc 172 kCLOCK_Crc0 \
AnnaBridge 171:3a7713b1edbc 173 }
AnnaBridge 171:3a7713b1edbc 174
AnnaBridge 171:3a7713b1edbc 175 /*! @brief Clock ip name array for I2C. */
AnnaBridge 171:3a7713b1edbc 176 #define I2C_CLOCKS \
AnnaBridge 171:3a7713b1edbc 177 { \
AnnaBridge 171:3a7713b1edbc 178 kCLOCK_I2c0, kCLOCK_I2c1 \
AnnaBridge 171:3a7713b1edbc 179 }
AnnaBridge 171:3a7713b1edbc 180
AnnaBridge 171:3a7713b1edbc 181 /*! @brief Clock ip name array for PDB. */
AnnaBridge 171:3a7713b1edbc 182 #define PDB_CLOCKS \
AnnaBridge 171:3a7713b1edbc 183 { \
AnnaBridge 171:3a7713b1edbc 184 kCLOCK_Pdb0 \
AnnaBridge 171:3a7713b1edbc 185 }
AnnaBridge 171:3a7713b1edbc 186
AnnaBridge 171:3a7713b1edbc 187 /*! @brief Clock ip name array for CMP. */
AnnaBridge 171:3a7713b1edbc 188 #define CMP_CLOCKS \
AnnaBridge 171:3a7713b1edbc 189 { \
AnnaBridge 171:3a7713b1edbc 190 kCLOCK_Cmp0, kCLOCK_Cmp1 \
AnnaBridge 171:3a7713b1edbc 191 }
AnnaBridge 171:3a7713b1edbc 192
AnnaBridge 171:3a7713b1edbc 193 /*! @brief Clock ip name array for FTF. */
AnnaBridge 171:3a7713b1edbc 194 #define FTF_CLOCKS \
AnnaBridge 171:3a7713b1edbc 195 { \
AnnaBridge 171:3a7713b1edbc 196 kCLOCK_Ftf0 \
AnnaBridge 171:3a7713b1edbc 197 }
AnnaBridge 171:3a7713b1edbc 198
AnnaBridge 171:3a7713b1edbc 199 /*!
AnnaBridge 171:3a7713b1edbc 200 * @brief LPO clock frequency.
AnnaBridge 171:3a7713b1edbc 201 */
AnnaBridge 171:3a7713b1edbc 202 #define LPO_CLK_FREQ 1000U
AnnaBridge 171:3a7713b1edbc 203
AnnaBridge 171:3a7713b1edbc 204 /*! @brief Peripherals clock source definition. */
AnnaBridge 171:3a7713b1edbc 205 #define SYS_CLK kCLOCK_CoreSysClk
AnnaBridge 171:3a7713b1edbc 206 #define BUS_CLK kCLOCK_BusClk
AnnaBridge 171:3a7713b1edbc 207 #define FAST_CLK kCLOCK_FastPeriphClk
AnnaBridge 171:3a7713b1edbc 208
AnnaBridge 171:3a7713b1edbc 209 #define I2C0_CLK_SRC BUS_CLK
AnnaBridge 171:3a7713b1edbc 210 #define I2C1_CLK_SRC BUS_CLK
AnnaBridge 171:3a7713b1edbc 211 #define DSPI0_CLK_SRC BUS_CLK
AnnaBridge 171:3a7713b1edbc 212 #define DSPI1_CLK_SRC BUS_CLK
AnnaBridge 171:3a7713b1edbc 213 #define UART0_CLK_SRC SYS_CLK
AnnaBridge 171:3a7713b1edbc 214 #define UART1_CLK_SRC SYS_CLK
AnnaBridge 171:3a7713b1edbc 215 #define UART2_CLK_SRC BUS_CLK
AnnaBridge 171:3a7713b1edbc 216
AnnaBridge 171:3a7713b1edbc 217 /*! @brief Clock name used to get clock frequency. */
AnnaBridge 171:3a7713b1edbc 218 typedef enum _clock_name
AnnaBridge 171:3a7713b1edbc 219 {
AnnaBridge 171:3a7713b1edbc 220
AnnaBridge 171:3a7713b1edbc 221 /* ----------------------------- System layer clock -------------------------------*/
AnnaBridge 171:3a7713b1edbc 222 kCLOCK_CoreSysClk, /*!< Core/system clock */
AnnaBridge 171:3a7713b1edbc 223 kCLOCK_PlatClk, /*!< Platform clock */
AnnaBridge 171:3a7713b1edbc 224 kCLOCK_BusClk, /*!< Bus clock */
AnnaBridge 171:3a7713b1edbc 225 kCLOCK_FlashClk, /*!< Flash clock */
AnnaBridge 171:3a7713b1edbc 226 kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */
AnnaBridge 171:3a7713b1edbc 227
AnnaBridge 171:3a7713b1edbc 228 /* ---------------------------------- OSC clock -----------------------------------*/
AnnaBridge 171:3a7713b1edbc 229 kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */
AnnaBridge 171:3a7713b1edbc 230 kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */
AnnaBridge 171:3a7713b1edbc 231
AnnaBridge 171:3a7713b1edbc 232 /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
AnnaBridge 171:3a7713b1edbc 233 kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */
AnnaBridge 171:3a7713b1edbc 234 kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */
AnnaBridge 171:3a7713b1edbc 235 kCLOCK_McgFllClk, /*!< MCGFLLCLK */
AnnaBridge 171:3a7713b1edbc 236 kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */
AnnaBridge 171:3a7713b1edbc 237 kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */
AnnaBridge 171:3a7713b1edbc 238 kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */
AnnaBridge 171:3a7713b1edbc 239 kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */
AnnaBridge 171:3a7713b1edbc 240
AnnaBridge 171:3a7713b1edbc 241 /* --------------------------------- Other clock ----------------------------------*/
AnnaBridge 171:3a7713b1edbc 242 kCLOCK_LpoClk, /*!< LPO clock */
AnnaBridge 171:3a7713b1edbc 243
AnnaBridge 171:3a7713b1edbc 244 } clock_name_t;
AnnaBridge 171:3a7713b1edbc 245
AnnaBridge 171:3a7713b1edbc 246 /*! @brief USB clock source definition. */
AnnaBridge 171:3a7713b1edbc 247 typedef enum _clock_usb_src
AnnaBridge 171:3a7713b1edbc 248 {
AnnaBridge 171:3a7713b1edbc 249 kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U), /*!< Use PLL0. */
AnnaBridge 171:3a7713b1edbc 250 kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) /*!< Use USB_CLKIN. */
AnnaBridge 171:3a7713b1edbc 251 } clock_usb_src_t;
AnnaBridge 171:3a7713b1edbc 252 /*------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 253
AnnaBridge 171:3a7713b1edbc 254 clock_gate_t definition:
AnnaBridge 171:3a7713b1edbc 255
AnnaBridge 171:3a7713b1edbc 256 31 16 0
AnnaBridge 171:3a7713b1edbc 257 -----------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 258 | SIM_SCGC register offset | control bit offset in SCGC |
AnnaBridge 171:3a7713b1edbc 259 -----------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 260
AnnaBridge 171:3a7713b1edbc 261 For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
AnnaBridge 171:3a7713b1edbc 262 SIM_SCGC3 offset in SIM is 0x1030, then kCLOCK_GateSdhc0 is defined as
AnnaBridge 171:3a7713b1edbc 263
AnnaBridge 171:3a7713b1edbc 264 kCLOCK_GateSdhc0 = (0x1030 << 16) | 17;
AnnaBridge 171:3a7713b1edbc 265
AnnaBridge 171:3a7713b1edbc 266 ------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 267
AnnaBridge 171:3a7713b1edbc 268 #define CLK_GATE_REG_OFFSET_SHIFT 16U
AnnaBridge 171:3a7713b1edbc 269 #define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
AnnaBridge 171:3a7713b1edbc 270 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
AnnaBridge 171:3a7713b1edbc 271 #define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
AnnaBridge 171:3a7713b1edbc 272
AnnaBridge 171:3a7713b1edbc 273 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
AnnaBridge 171:3a7713b1edbc 274 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
AnnaBridge 171:3a7713b1edbc 275 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
AnnaBridge 171:3a7713b1edbc 276
AnnaBridge 171:3a7713b1edbc 277 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
AnnaBridge 171:3a7713b1edbc 278 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
AnnaBridge 171:3a7713b1edbc 279
AnnaBridge 171:3a7713b1edbc 280 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
AnnaBridge 171:3a7713b1edbc 281 typedef enum _clock_ip_name
AnnaBridge 171:3a7713b1edbc 282 {
AnnaBridge 171:3a7713b1edbc 283 kCLOCK_IpInvalid = 0U,
AnnaBridge 171:3a7713b1edbc 284
AnnaBridge 171:3a7713b1edbc 285 kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U),
AnnaBridge 171:3a7713b1edbc 286 kCLOCK_Cmt0 = CLK_GATE_DEFINE(0x1034U, 2U),
AnnaBridge 171:3a7713b1edbc 287 kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
AnnaBridge 171:3a7713b1edbc 288 kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
AnnaBridge 171:3a7713b1edbc 289 kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U),
AnnaBridge 171:3a7713b1edbc 290 kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U),
AnnaBridge 171:3a7713b1edbc 291 kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U),
AnnaBridge 171:3a7713b1edbc 292 kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U),
AnnaBridge 171:3a7713b1edbc 293 kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
AnnaBridge 171:3a7713b1edbc 294 kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U),
AnnaBridge 171:3a7713b1edbc 295 kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
AnnaBridge 171:3a7713b1edbc 296
AnnaBridge 171:3a7713b1edbc 297 kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
AnnaBridge 171:3a7713b1edbc 298 kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
AnnaBridge 171:3a7713b1edbc 299 kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
AnnaBridge 171:3a7713b1edbc 300 kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
AnnaBridge 171:3a7713b1edbc 301 kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U),
AnnaBridge 171:3a7713b1edbc 302 kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U),
AnnaBridge 171:3a7713b1edbc 303
AnnaBridge 171:3a7713b1edbc 304 kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
AnnaBridge 171:3a7713b1edbc 305 kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
AnnaBridge 171:3a7713b1edbc 306 kCLOCK_Rnga0 = CLK_GATE_DEFINE(0x103CU, 9U),
AnnaBridge 171:3a7713b1edbc 307 kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
AnnaBridge 171:3a7713b1edbc 308 kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U),
AnnaBridge 171:3a7713b1edbc 309 kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U),
AnnaBridge 171:3a7713b1edbc 310 kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U),
AnnaBridge 171:3a7713b1edbc 311 kCLOCK_Usbdcd0 = CLK_GATE_DEFINE(0x103CU, 21U),
AnnaBridge 171:3a7713b1edbc 312 kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U),
AnnaBridge 171:3a7713b1edbc 313 kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
AnnaBridge 171:3a7713b1edbc 314 kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U),
AnnaBridge 171:3a7713b1edbc 315 kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U),
AnnaBridge 171:3a7713b1edbc 316 kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U),
AnnaBridge 171:3a7713b1edbc 317 kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
AnnaBridge 171:3a7713b1edbc 318 kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U),
AnnaBridge 171:3a7713b1edbc 319 kCLOCK_Dac0 = CLK_GATE_DEFINE(0x103CU, 31U),
AnnaBridge 171:3a7713b1edbc 320
AnnaBridge 171:3a7713b1edbc 321 kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U),
AnnaBridge 171:3a7713b1edbc 322 } clock_ip_name_t;
AnnaBridge 171:3a7713b1edbc 323
AnnaBridge 171:3a7713b1edbc 324 /*!@brief SIM configuration structure for clock setting. */
AnnaBridge 171:3a7713b1edbc 325 typedef struct _sim_clock_config
AnnaBridge 171:3a7713b1edbc 326 {
AnnaBridge 171:3a7713b1edbc 327 uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */
AnnaBridge 171:3a7713b1edbc 328 uint8_t er32kSrc; /*!< ERCLK32K source selection. */
AnnaBridge 171:3a7713b1edbc 329 uint32_t clkdiv1; /*!< SIM_CLKDIV1. */
AnnaBridge 171:3a7713b1edbc 330 } sim_clock_config_t;
AnnaBridge 171:3a7713b1edbc 331
AnnaBridge 171:3a7713b1edbc 332 /*! @brief OSC work mode. */
AnnaBridge 171:3a7713b1edbc 333 typedef enum _osc_mode
AnnaBridge 171:3a7713b1edbc 334 {
AnnaBridge 171:3a7713b1edbc 335 kOSC_ModeExt = 0U, /*!< Use an external clock. */
AnnaBridge 171:3a7713b1edbc 336 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
AnnaBridge 171:3a7713b1edbc 337 kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
AnnaBridge 171:3a7713b1edbc 338 #else
AnnaBridge 171:3a7713b1edbc 339 kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
AnnaBridge 171:3a7713b1edbc 340 #endif
AnnaBridge 171:3a7713b1edbc 341 kOSC_ModeOscHighGain = 0U
AnnaBridge 171:3a7713b1edbc 342 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
AnnaBridge 171:3a7713b1edbc 343 |
AnnaBridge 171:3a7713b1edbc 344 MCG_C2_EREFS_MASK
AnnaBridge 171:3a7713b1edbc 345 #else
AnnaBridge 171:3a7713b1edbc 346 |
AnnaBridge 171:3a7713b1edbc 347 MCG_C2_EREFS0_MASK
AnnaBridge 171:3a7713b1edbc 348 #endif
AnnaBridge 171:3a7713b1edbc 349 #if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
AnnaBridge 171:3a7713b1edbc 350 |
AnnaBridge 171:3a7713b1edbc 351 MCG_C2_HGO_MASK, /*!< Oscillator high gain. */
AnnaBridge 171:3a7713b1edbc 352 #else
AnnaBridge 171:3a7713b1edbc 353 |
AnnaBridge 171:3a7713b1edbc 354 MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
AnnaBridge 171:3a7713b1edbc 355 #endif
AnnaBridge 171:3a7713b1edbc 356 } osc_mode_t;
AnnaBridge 171:3a7713b1edbc 357
AnnaBridge 171:3a7713b1edbc 358 /*! @brief Oscillator capacitor load setting.*/
AnnaBridge 171:3a7713b1edbc 359 enum _osc_cap_load
AnnaBridge 171:3a7713b1edbc 360 {
AnnaBridge 171:3a7713b1edbc 361 kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */
AnnaBridge 171:3a7713b1edbc 362 kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */
AnnaBridge 171:3a7713b1edbc 363 kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */
AnnaBridge 171:3a7713b1edbc 364 kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */
AnnaBridge 171:3a7713b1edbc 365 };
AnnaBridge 171:3a7713b1edbc 366
AnnaBridge 171:3a7713b1edbc 367 /*! @brief OSCERCLK enable mode. */
AnnaBridge 171:3a7713b1edbc 368 enum _oscer_enable_mode
AnnaBridge 171:3a7713b1edbc 369 {
AnnaBridge 171:3a7713b1edbc 370 kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */
AnnaBridge 171:3a7713b1edbc 371 kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */
AnnaBridge 171:3a7713b1edbc 372 };
AnnaBridge 171:3a7713b1edbc 373
AnnaBridge 171:3a7713b1edbc 374 /*! @brief OSC configuration for OSCERCLK. */
AnnaBridge 171:3a7713b1edbc 375 typedef struct _oscer_config
AnnaBridge 171:3a7713b1edbc 376 {
AnnaBridge 171:3a7713b1edbc 377 uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */
AnnaBridge 171:3a7713b1edbc 378
AnnaBridge 171:3a7713b1edbc 379 } oscer_config_t;
AnnaBridge 171:3a7713b1edbc 380
AnnaBridge 171:3a7713b1edbc 381 /*!
AnnaBridge 171:3a7713b1edbc 382 * @brief OSC Initialization Configuration Structure
AnnaBridge 171:3a7713b1edbc 383 *
AnnaBridge 171:3a7713b1edbc 384 * Defines the configuration data structure to initialize the OSC.
AnnaBridge 171:3a7713b1edbc 385 * When porting to a new board, set the following members
AnnaBridge 171:3a7713b1edbc 386 * according to the board setting:
AnnaBridge 171:3a7713b1edbc 387 * 1. freq: The external frequency.
AnnaBridge 171:3a7713b1edbc 388 * 2. workMode: The OSC module mode.
AnnaBridge 171:3a7713b1edbc 389 */
AnnaBridge 171:3a7713b1edbc 390 typedef struct _osc_config
AnnaBridge 171:3a7713b1edbc 391 {
AnnaBridge 171:3a7713b1edbc 392 uint32_t freq; /*!< External clock frequency. */
AnnaBridge 171:3a7713b1edbc 393 uint8_t capLoad; /*!< Capacitor load setting. */
AnnaBridge 171:3a7713b1edbc 394 osc_mode_t workMode; /*!< OSC work mode setting. */
AnnaBridge 171:3a7713b1edbc 395 oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */
AnnaBridge 171:3a7713b1edbc 396 } osc_config_t;
AnnaBridge 171:3a7713b1edbc 397
AnnaBridge 171:3a7713b1edbc 398 /*! @brief MCG FLL reference clock source select. */
AnnaBridge 171:3a7713b1edbc 399 typedef enum _mcg_fll_src
AnnaBridge 171:3a7713b1edbc 400 {
AnnaBridge 171:3a7713b1edbc 401 kMCG_FllSrcExternal, /*!< External reference clock is selected */
AnnaBridge 171:3a7713b1edbc 402 kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */
AnnaBridge 171:3a7713b1edbc 403 } mcg_fll_src_t;
AnnaBridge 171:3a7713b1edbc 404
AnnaBridge 171:3a7713b1edbc 405 /*! @brief MCG internal reference clock select */
AnnaBridge 171:3a7713b1edbc 406 typedef enum _mcg_irc_mode
AnnaBridge 171:3a7713b1edbc 407 {
AnnaBridge 171:3a7713b1edbc 408 kMCG_IrcSlow, /*!< Slow internal reference clock selected */
AnnaBridge 171:3a7713b1edbc 409 kMCG_IrcFast /*!< Fast internal reference clock selected */
AnnaBridge 171:3a7713b1edbc 410 } mcg_irc_mode_t;
AnnaBridge 171:3a7713b1edbc 411
AnnaBridge 171:3a7713b1edbc 412 /*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
AnnaBridge 171:3a7713b1edbc 413 typedef enum _mcg_dmx32
AnnaBridge 171:3a7713b1edbc 414 {
AnnaBridge 171:3a7713b1edbc 415 kMCG_Dmx32Default, /*!< DCO has a default range of 25% */
AnnaBridge 171:3a7713b1edbc 416 kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
AnnaBridge 171:3a7713b1edbc 417 } mcg_dmx32_t;
AnnaBridge 171:3a7713b1edbc 418
AnnaBridge 171:3a7713b1edbc 419 /*! @brief MCG DCO range select */
AnnaBridge 171:3a7713b1edbc 420 typedef enum _mcg_drs
AnnaBridge 171:3a7713b1edbc 421 {
AnnaBridge 171:3a7713b1edbc 422 kMCG_DrsLow, /*!< Low frequency range */
AnnaBridge 171:3a7713b1edbc 423 kMCG_DrsMid, /*!< Mid frequency range */
AnnaBridge 171:3a7713b1edbc 424 kMCG_DrsMidHigh, /*!< Mid-High frequency range */
AnnaBridge 171:3a7713b1edbc 425 kMCG_DrsHigh /*!< High frequency range */
AnnaBridge 171:3a7713b1edbc 426 } mcg_drs_t;
AnnaBridge 171:3a7713b1edbc 427
AnnaBridge 171:3a7713b1edbc 428 /*! @brief MCG PLL reference clock select */
AnnaBridge 171:3a7713b1edbc 429 typedef enum _mcg_pll_ref_src
AnnaBridge 171:3a7713b1edbc 430 {
AnnaBridge 171:3a7713b1edbc 431 kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */
AnnaBridge 171:3a7713b1edbc 432 kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */
AnnaBridge 171:3a7713b1edbc 433 } mcg_pll_ref_src_t;
AnnaBridge 171:3a7713b1edbc 434
AnnaBridge 171:3a7713b1edbc 435 /*! @brief MCGOUT clock source. */
AnnaBridge 171:3a7713b1edbc 436 typedef enum _mcg_clkout_src
AnnaBridge 171:3a7713b1edbc 437 {
AnnaBridge 171:3a7713b1edbc 438 kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */
AnnaBridge 171:3a7713b1edbc 439 kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */
AnnaBridge 171:3a7713b1edbc 440 kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */
AnnaBridge 171:3a7713b1edbc 441 } mcg_clkout_src_t;
AnnaBridge 171:3a7713b1edbc 442
AnnaBridge 171:3a7713b1edbc 443 /*! @brief MCG Automatic Trim Machine Select */
AnnaBridge 171:3a7713b1edbc 444 typedef enum _mcg_atm_select
AnnaBridge 171:3a7713b1edbc 445 {
AnnaBridge 171:3a7713b1edbc 446 kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */
AnnaBridge 171:3a7713b1edbc 447 kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */
AnnaBridge 171:3a7713b1edbc 448 } mcg_atm_select_t;
AnnaBridge 171:3a7713b1edbc 449
AnnaBridge 171:3a7713b1edbc 450 /*! @brief MCG OSC Clock Select */
AnnaBridge 171:3a7713b1edbc 451 typedef enum _mcg_oscsel
AnnaBridge 171:3a7713b1edbc 452 {
AnnaBridge 171:3a7713b1edbc 453 kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */
AnnaBridge 171:3a7713b1edbc 454 kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */
AnnaBridge 171:3a7713b1edbc 455 } mcg_oscsel_t;
AnnaBridge 171:3a7713b1edbc 456
AnnaBridge 171:3a7713b1edbc 457 /*! @brief MCG PLLCS select */
AnnaBridge 171:3a7713b1edbc 458 typedef enum _mcg_pll_clk_select
AnnaBridge 171:3a7713b1edbc 459 {
AnnaBridge 171:3a7713b1edbc 460 kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */
AnnaBridge 171:3a7713b1edbc 461 kMCG_PllClkSelPll1 /* PLL1 output clock is selected */
AnnaBridge 171:3a7713b1edbc 462 } mcg_pll_clk_select_t;
AnnaBridge 171:3a7713b1edbc 463
AnnaBridge 171:3a7713b1edbc 464 /*! @brief MCG clock monitor mode. */
AnnaBridge 171:3a7713b1edbc 465 typedef enum _mcg_monitor_mode
AnnaBridge 171:3a7713b1edbc 466 {
AnnaBridge 171:3a7713b1edbc 467 kMCG_MonitorNone, /*!< Clock monitor is disabled. */
AnnaBridge 171:3a7713b1edbc 468 kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */
AnnaBridge 171:3a7713b1edbc 469 kMCG_MonitorReset /*!< System reset when clock lost. */
AnnaBridge 171:3a7713b1edbc 470 } mcg_monitor_mode_t;
AnnaBridge 171:3a7713b1edbc 471
AnnaBridge 171:3a7713b1edbc 472 /*! @brief MCG status. */
AnnaBridge 171:3a7713b1edbc 473 enum _mcg_status
AnnaBridge 171:3a7713b1edbc 474 {
AnnaBridge 171:3a7713b1edbc 475 kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0), /*!< Can't switch to target mode. */
AnnaBridge 171:3a7713b1edbc 476 kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1), /*!< Current mode invalid for the specific
AnnaBridge 171:3a7713b1edbc 477 function. */
AnnaBridge 171:3a7713b1edbc 478 kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2), /*!< Invalid bus clock for ATM. */
AnnaBridge 171:3a7713b1edbc 479 kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3), /*!< Invalid desired frequency for ATM. */
AnnaBridge 171:3a7713b1edbc 480 kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4), /*!< IRC is used when using ATM. */
AnnaBridge 171:3a7713b1edbc 481 kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5), /*!< Hardware fail occurs during ATM. */
AnnaBridge 171:3a7713b1edbc 482 kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6) /*!< Can't change the clock source because
AnnaBridge 171:3a7713b1edbc 483 it is in use. */
AnnaBridge 171:3a7713b1edbc 484 };
AnnaBridge 171:3a7713b1edbc 485
AnnaBridge 171:3a7713b1edbc 486 /*! @brief MCG status flags. */
AnnaBridge 171:3a7713b1edbc 487 enum _mcg_status_flags_t
AnnaBridge 171:3a7713b1edbc 488 {
AnnaBridge 171:3a7713b1edbc 489 kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */
AnnaBridge 171:3a7713b1edbc 490 kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */
AnnaBridge 171:3a7713b1edbc 491 kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */
AnnaBridge 171:3a7713b1edbc 492 kMCG_Pll0LostFlag = (1U << 5U), /*!< PLL0 lost. */
AnnaBridge 171:3a7713b1edbc 493 kMCG_Pll0LockFlag = (1U << 6U), /*!< PLL0 locked. */
AnnaBridge 171:3a7713b1edbc 494 };
AnnaBridge 171:3a7713b1edbc 495
AnnaBridge 171:3a7713b1edbc 496 /*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */
AnnaBridge 171:3a7713b1edbc 497 enum _mcg_irclk_enable_mode
AnnaBridge 171:3a7713b1edbc 498 {
AnnaBridge 171:3a7713b1edbc 499 kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */
AnnaBridge 171:3a7713b1edbc 500 kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
AnnaBridge 171:3a7713b1edbc 501 };
AnnaBridge 171:3a7713b1edbc 502
AnnaBridge 171:3a7713b1edbc 503 /*! @brief MCG PLL clock enable mode definition. */
AnnaBridge 171:3a7713b1edbc 504 enum _mcg_pll_enable_mode
AnnaBridge 171:3a7713b1edbc 505 {
AnnaBridge 171:3a7713b1edbc 506 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
AnnaBridge 171:3a7713b1edbc 507 MCG clock mode. Generally, the PLL
AnnaBridge 171:3a7713b1edbc 508 is disabled in FLL modes
AnnaBridge 171:3a7713b1edbc 509 (FEI/FBI/FEE/FBE). Setting the PLL clock
AnnaBridge 171:3a7713b1edbc 510 enable independent, enables the
AnnaBridge 171:3a7713b1edbc 511 PLL in the FLL modes. */
AnnaBridge 171:3a7713b1edbc 512 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
AnnaBridge 171:3a7713b1edbc 513 };
AnnaBridge 171:3a7713b1edbc 514
AnnaBridge 171:3a7713b1edbc 515 /*! @brief MCG mode definitions */
AnnaBridge 171:3a7713b1edbc 516 typedef enum _mcg_mode
AnnaBridge 171:3a7713b1edbc 517 {
AnnaBridge 171:3a7713b1edbc 518 kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */
AnnaBridge 171:3a7713b1edbc 519 kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */
AnnaBridge 171:3a7713b1edbc 520 kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */
AnnaBridge 171:3a7713b1edbc 521 kMCG_ModeFEE, /*!< FEE - FLL Engaged External */
AnnaBridge 171:3a7713b1edbc 522 kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */
AnnaBridge 171:3a7713b1edbc 523 kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */
AnnaBridge 171:3a7713b1edbc 524 kMCG_ModePBE, /*!< PBE - PLL Bypassed External */
AnnaBridge 171:3a7713b1edbc 525 kMCG_ModePEE, /*!< PEE - PLL Engaged External */
AnnaBridge 171:3a7713b1edbc 526 kMCG_ModeError /*!< Unknown mode */
AnnaBridge 171:3a7713b1edbc 527 } mcg_mode_t;
AnnaBridge 171:3a7713b1edbc 528
AnnaBridge 171:3a7713b1edbc 529 /*! @brief MCG PLL configuration. */
AnnaBridge 171:3a7713b1edbc 530 typedef struct _mcg_pll_config
AnnaBridge 171:3a7713b1edbc 531 {
AnnaBridge 171:3a7713b1edbc 532 uint8_t enableMode; /*!< Enable mode. OR'ed value of @ref _mcg_pll_enable_mode. */
AnnaBridge 171:3a7713b1edbc 533 uint8_t prdiv; /*!< Reference divider PRDIV. */
AnnaBridge 171:3a7713b1edbc 534 uint8_t vdiv; /*!< VCO divider VDIV. */
AnnaBridge 171:3a7713b1edbc 535 } mcg_pll_config_t;
AnnaBridge 171:3a7713b1edbc 536
AnnaBridge 171:3a7713b1edbc 537 /*! @brief MCG mode change configuration structure
AnnaBridge 171:3a7713b1edbc 538 *
AnnaBridge 171:3a7713b1edbc 539 * When porting to a new board, set the following members
AnnaBridge 171:3a7713b1edbc 540 * according to the board setting:
AnnaBridge 171:3a7713b1edbc 541 * 1. frdiv: If the FLL uses the external reference clock, set this
AnnaBridge 171:3a7713b1edbc 542 * value to ensure that the external reference clock divided by frdiv is
AnnaBridge 171:3a7713b1edbc 543 * in the 31.25 kHz to 39.0625 kHz range.
AnnaBridge 171:3a7713b1edbc 544 * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
AnnaBridge 171:3a7713b1edbc 545 * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
AnnaBridge 171:3a7713b1edbc 546 * FSL_FEATURE_MCG_PLL_REF_MAX range.
AnnaBridge 171:3a7713b1edbc 547 */
AnnaBridge 171:3a7713b1edbc 548 typedef struct _mcg_config
AnnaBridge 171:3a7713b1edbc 549 {
AnnaBridge 171:3a7713b1edbc 550 mcg_mode_t mcgMode; /*!< MCG mode. */
AnnaBridge 171:3a7713b1edbc 551
AnnaBridge 171:3a7713b1edbc 552 /* ----------------------- MCGIRCCLK settings ------------------------ */
AnnaBridge 171:3a7713b1edbc 553 uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */
AnnaBridge 171:3a7713b1edbc 554 mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */
AnnaBridge 171:3a7713b1edbc 555 uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */
AnnaBridge 171:3a7713b1edbc 556
AnnaBridge 171:3a7713b1edbc 557 /* ------------------------ MCG FLL settings ------------------------- */
AnnaBridge 171:3a7713b1edbc 558 uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */
AnnaBridge 171:3a7713b1edbc 559 mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */
AnnaBridge 171:3a7713b1edbc 560 mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */
AnnaBridge 171:3a7713b1edbc 561 mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */
AnnaBridge 171:3a7713b1edbc 562
AnnaBridge 171:3a7713b1edbc 563 /* ------------------------ MCG PLL settings ------------------------- */
AnnaBridge 171:3a7713b1edbc 564 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
AnnaBridge 171:3a7713b1edbc 565
AnnaBridge 171:3a7713b1edbc 566 } mcg_config_t;
AnnaBridge 171:3a7713b1edbc 567
AnnaBridge 171:3a7713b1edbc 568 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 569 * API
AnnaBridge 171:3a7713b1edbc 570 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 571
AnnaBridge 171:3a7713b1edbc 572 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 573 extern "C" {
AnnaBridge 171:3a7713b1edbc 574 #endif /* __cplusplus */
AnnaBridge 171:3a7713b1edbc 575
AnnaBridge 171:3a7713b1edbc 576 /*!
AnnaBridge 171:3a7713b1edbc 577 * @brief Enable the clock for specific IP.
AnnaBridge 171:3a7713b1edbc 578 *
AnnaBridge 171:3a7713b1edbc 579 * @param name Which clock to enable, see \ref clock_ip_name_t.
AnnaBridge 171:3a7713b1edbc 580 */
AnnaBridge 171:3a7713b1edbc 581 static inline void CLOCK_EnableClock(clock_ip_name_t name)
AnnaBridge 171:3a7713b1edbc 582 {
AnnaBridge 171:3a7713b1edbc 583 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
AnnaBridge 171:3a7713b1edbc 584 (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
AnnaBridge 171:3a7713b1edbc 585 }
AnnaBridge 171:3a7713b1edbc 586
AnnaBridge 171:3a7713b1edbc 587 /*!
AnnaBridge 171:3a7713b1edbc 588 * @brief Disable the clock for specific IP.
AnnaBridge 171:3a7713b1edbc 589 *
AnnaBridge 171:3a7713b1edbc 590 * @param name Which clock to disable, see \ref clock_ip_name_t.
AnnaBridge 171:3a7713b1edbc 591 */
AnnaBridge 171:3a7713b1edbc 592 static inline void CLOCK_DisableClock(clock_ip_name_t name)
AnnaBridge 171:3a7713b1edbc 593 {
AnnaBridge 171:3a7713b1edbc 594 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
AnnaBridge 171:3a7713b1edbc 595 (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
AnnaBridge 171:3a7713b1edbc 596 }
AnnaBridge 171:3a7713b1edbc 597
AnnaBridge 171:3a7713b1edbc 598 /*!
AnnaBridge 171:3a7713b1edbc 599 * @brief Set ERCLK32K source.
AnnaBridge 171:3a7713b1edbc 600 *
AnnaBridge 171:3a7713b1edbc 601 * @param src The value to set ERCLK32K clock source.
AnnaBridge 171:3a7713b1edbc 602 */
AnnaBridge 171:3a7713b1edbc 603 static inline void CLOCK_SetEr32kClock(uint32_t src)
AnnaBridge 171:3a7713b1edbc 604 {
AnnaBridge 171:3a7713b1edbc 605 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
AnnaBridge 171:3a7713b1edbc 606 }
AnnaBridge 171:3a7713b1edbc 607
AnnaBridge 171:3a7713b1edbc 608 /*!
AnnaBridge 171:3a7713b1edbc 609 * @brief Set debug trace clock source.
AnnaBridge 171:3a7713b1edbc 610 *
AnnaBridge 171:3a7713b1edbc 611 * @param src The value to set debug trace clock source.
AnnaBridge 171:3a7713b1edbc 612 */
AnnaBridge 171:3a7713b1edbc 613 static inline void CLOCK_SetTraceClock(uint32_t src)
AnnaBridge 171:3a7713b1edbc 614 {
AnnaBridge 171:3a7713b1edbc 615 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src));
AnnaBridge 171:3a7713b1edbc 616 }
AnnaBridge 171:3a7713b1edbc 617
AnnaBridge 171:3a7713b1edbc 618 /*!
AnnaBridge 171:3a7713b1edbc 619 * @brief Set PLLFLLSEL clock source.
AnnaBridge 171:3a7713b1edbc 620 *
AnnaBridge 171:3a7713b1edbc 621 * @param src The value to set PLLFLLSEL clock source.
AnnaBridge 171:3a7713b1edbc 622 */
AnnaBridge 171:3a7713b1edbc 623 static inline void CLOCK_SetPllFllSelClock(uint32_t src)
AnnaBridge 171:3a7713b1edbc 624 {
AnnaBridge 171:3a7713b1edbc 625 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src));
AnnaBridge 171:3a7713b1edbc 626 }
AnnaBridge 171:3a7713b1edbc 627
AnnaBridge 171:3a7713b1edbc 628 /*!
AnnaBridge 171:3a7713b1edbc 629 * @brief Set CLKOUT source.
AnnaBridge 171:3a7713b1edbc 630 *
AnnaBridge 171:3a7713b1edbc 631 * @param src The value to set CLKOUT source.
AnnaBridge 171:3a7713b1edbc 632 */
AnnaBridge 171:3a7713b1edbc 633 static inline void CLOCK_SetClkOutClock(uint32_t src)
AnnaBridge 171:3a7713b1edbc 634 {
AnnaBridge 171:3a7713b1edbc 635 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
AnnaBridge 171:3a7713b1edbc 636 }
AnnaBridge 171:3a7713b1edbc 637
AnnaBridge 171:3a7713b1edbc 638 /*!
AnnaBridge 171:3a7713b1edbc 639 * @brief Set RTC_CLKOUT source.
AnnaBridge 171:3a7713b1edbc 640 *
AnnaBridge 171:3a7713b1edbc 641 * @param src The value to set RTC_CLKOUT source.
AnnaBridge 171:3a7713b1edbc 642 */
AnnaBridge 171:3a7713b1edbc 643 static inline void CLOCK_SetRtcClkOutClock(uint32_t src)
AnnaBridge 171:3a7713b1edbc 644 {
AnnaBridge 171:3a7713b1edbc 645 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src));
AnnaBridge 171:3a7713b1edbc 646 }
AnnaBridge 171:3a7713b1edbc 647
AnnaBridge 171:3a7713b1edbc 648 /*! @brief Enable USB FS clock.
AnnaBridge 171:3a7713b1edbc 649 *
AnnaBridge 171:3a7713b1edbc 650 * @param src USB FS clock source.
AnnaBridge 171:3a7713b1edbc 651 * @param freq The frequency specified by src.
AnnaBridge 171:3a7713b1edbc 652 * @retval true The clock is set successfully.
AnnaBridge 171:3a7713b1edbc 653 * @retval false The clock source is invalid to get proper USB FS clock.
AnnaBridge 171:3a7713b1edbc 654 */
AnnaBridge 171:3a7713b1edbc 655 bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
AnnaBridge 171:3a7713b1edbc 656
AnnaBridge 171:3a7713b1edbc 657 /*! @brief Disable USB FS clock.
AnnaBridge 171:3a7713b1edbc 658 *
AnnaBridge 171:3a7713b1edbc 659 * Disable USB FS clock.
AnnaBridge 171:3a7713b1edbc 660 */
AnnaBridge 171:3a7713b1edbc 661 static inline void CLOCK_DisableUsbfs0Clock(void)
AnnaBridge 171:3a7713b1edbc 662 {
AnnaBridge 171:3a7713b1edbc 663 CLOCK_DisableClock(kCLOCK_Usbfs0);
AnnaBridge 171:3a7713b1edbc 664 }
AnnaBridge 171:3a7713b1edbc 665
AnnaBridge 171:3a7713b1edbc 666 /*!
AnnaBridge 171:3a7713b1edbc 667 * @brief System clock divider
AnnaBridge 171:3a7713b1edbc 668 *
AnnaBridge 171:3a7713b1edbc 669 * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV4].
AnnaBridge 171:3a7713b1edbc 670 *
AnnaBridge 171:3a7713b1edbc 671 * @param outdiv1 Clock 1 output divider value.
AnnaBridge 171:3a7713b1edbc 672 *
AnnaBridge 171:3a7713b1edbc 673 * @param outdiv2 Clock 2 output divider value.
AnnaBridge 171:3a7713b1edbc 674 *
AnnaBridge 171:3a7713b1edbc 675 * @param outdiv4 Clock 4 output divider value.
AnnaBridge 171:3a7713b1edbc 676 */
AnnaBridge 171:3a7713b1edbc 677 static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv4)
AnnaBridge 171:3a7713b1edbc 678 {
AnnaBridge 171:3a7713b1edbc 679 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV4(outdiv4);
AnnaBridge 171:3a7713b1edbc 680 }
AnnaBridge 171:3a7713b1edbc 681
AnnaBridge 171:3a7713b1edbc 682 /*!
AnnaBridge 171:3a7713b1edbc 683 * @brief Gets the clock frequency for a specific clock name.
AnnaBridge 171:3a7713b1edbc 684 *
AnnaBridge 171:3a7713b1edbc 685 * This function checks the current clock configurations and then calculates
AnnaBridge 171:3a7713b1edbc 686 * the clock frequency for a specific clock name defined in clock_name_t.
AnnaBridge 171:3a7713b1edbc 687 * The MCG must be properly configured before using this function.
AnnaBridge 171:3a7713b1edbc 688 *
AnnaBridge 171:3a7713b1edbc 689 * @param clockName Clock names defined in clock_name_t
AnnaBridge 171:3a7713b1edbc 690 * @return Clock frequency value in Hertz
AnnaBridge 171:3a7713b1edbc 691 */
AnnaBridge 171:3a7713b1edbc 692 uint32_t CLOCK_GetFreq(clock_name_t clockName);
AnnaBridge 171:3a7713b1edbc 693
AnnaBridge 171:3a7713b1edbc 694 /*!
AnnaBridge 171:3a7713b1edbc 695 * @brief Get the core clock or system clock frequency.
AnnaBridge 171:3a7713b1edbc 696 *
AnnaBridge 171:3a7713b1edbc 697 * @return Clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 698 */
AnnaBridge 171:3a7713b1edbc 699 uint32_t CLOCK_GetCoreSysClkFreq(void);
AnnaBridge 171:3a7713b1edbc 700
AnnaBridge 171:3a7713b1edbc 701 /*!
AnnaBridge 171:3a7713b1edbc 702 * @brief Get the platform clock frequency.
AnnaBridge 171:3a7713b1edbc 703 *
AnnaBridge 171:3a7713b1edbc 704 * @return Clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 705 */
AnnaBridge 171:3a7713b1edbc 706 uint32_t CLOCK_GetPlatClkFreq(void);
AnnaBridge 171:3a7713b1edbc 707
AnnaBridge 171:3a7713b1edbc 708 /*!
AnnaBridge 171:3a7713b1edbc 709 * @brief Get the bus clock frequency.
AnnaBridge 171:3a7713b1edbc 710 *
AnnaBridge 171:3a7713b1edbc 711 * @return Clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 712 */
AnnaBridge 171:3a7713b1edbc 713 uint32_t CLOCK_GetBusClkFreq(void);
AnnaBridge 171:3a7713b1edbc 714
AnnaBridge 171:3a7713b1edbc 715 /*!
AnnaBridge 171:3a7713b1edbc 716 * @brief Get the flash clock frequency.
AnnaBridge 171:3a7713b1edbc 717 *
AnnaBridge 171:3a7713b1edbc 718 * @return Clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 719 */
AnnaBridge 171:3a7713b1edbc 720 uint32_t CLOCK_GetFlashClkFreq(void);
AnnaBridge 171:3a7713b1edbc 721
AnnaBridge 171:3a7713b1edbc 722 /*!
AnnaBridge 171:3a7713b1edbc 723 * @brief Get the output clock frequency selected by SIM[PLLFLLSEL].
AnnaBridge 171:3a7713b1edbc 724 *
AnnaBridge 171:3a7713b1edbc 725 * @return Clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 726 */
AnnaBridge 171:3a7713b1edbc 727 uint32_t CLOCK_GetPllFllSelClkFreq(void);
AnnaBridge 171:3a7713b1edbc 728
AnnaBridge 171:3a7713b1edbc 729 /*!
AnnaBridge 171:3a7713b1edbc 730 * @brief Get the external reference 32K clock frequency (ERCLK32K).
AnnaBridge 171:3a7713b1edbc 731 *
AnnaBridge 171:3a7713b1edbc 732 * @return Clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 733 */
AnnaBridge 171:3a7713b1edbc 734 uint32_t CLOCK_GetEr32kClkFreq(void);
AnnaBridge 171:3a7713b1edbc 735
AnnaBridge 171:3a7713b1edbc 736 /*!
AnnaBridge 171:3a7713b1edbc 737 * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
AnnaBridge 171:3a7713b1edbc 738 *
AnnaBridge 171:3a7713b1edbc 739 * @return Clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 740 */
AnnaBridge 171:3a7713b1edbc 741 uint32_t CLOCK_GetOsc0ErClkFreq(void);
AnnaBridge 171:3a7713b1edbc 742
AnnaBridge 171:3a7713b1edbc 743 /*!
AnnaBridge 171:3a7713b1edbc 744 * @brief Set the clock configure in SIM module.
AnnaBridge 171:3a7713b1edbc 745 *
AnnaBridge 171:3a7713b1edbc 746 * This function sets system layer clock settings in SIM module.
AnnaBridge 171:3a7713b1edbc 747 *
AnnaBridge 171:3a7713b1edbc 748 * @param config Pointer to the configure structure.
AnnaBridge 171:3a7713b1edbc 749 */
AnnaBridge 171:3a7713b1edbc 750 void CLOCK_SetSimConfig(sim_clock_config_t const *config);
AnnaBridge 171:3a7713b1edbc 751
AnnaBridge 171:3a7713b1edbc 752 /*!
AnnaBridge 171:3a7713b1edbc 753 * @brief Set the system clock dividers in SIM to safe value.
AnnaBridge 171:3a7713b1edbc 754 *
AnnaBridge 171:3a7713b1edbc 755 * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
AnnaBridge 171:3a7713b1edbc 756 * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
AnnaBridge 171:3a7713b1edbc 757 * changes then the system level clocks may be out of range. This function could
AnnaBridge 171:3a7713b1edbc 758 * be used before MCG mode change, to make sure system level clocks are in allowed
AnnaBridge 171:3a7713b1edbc 759 * range.
AnnaBridge 171:3a7713b1edbc 760 *
AnnaBridge 171:3a7713b1edbc 761 * @param config Pointer to the configure structure.
AnnaBridge 171:3a7713b1edbc 762 */
AnnaBridge 171:3a7713b1edbc 763 static inline void CLOCK_SetSimSafeDivs(void)
AnnaBridge 171:3a7713b1edbc 764 {
AnnaBridge 171:3a7713b1edbc 765 SIM->CLKDIV1 = 0x00010000U;
AnnaBridge 171:3a7713b1edbc 766 }
AnnaBridge 171:3a7713b1edbc 767
AnnaBridge 171:3a7713b1edbc 768 /*! @name MCG frequency functions. */
AnnaBridge 171:3a7713b1edbc 769 /*@{*/
AnnaBridge 171:3a7713b1edbc 770
AnnaBridge 171:3a7713b1edbc 771 /*!
AnnaBridge 171:3a7713b1edbc 772 * @brief Gets the MCG output clock (MCGOUTCLK) frequency.
AnnaBridge 171:3a7713b1edbc 773 *
AnnaBridge 171:3a7713b1edbc 774 * This function gets the MCG output clock frequency in Hz based on the current MCG
AnnaBridge 171:3a7713b1edbc 775 * register value.
AnnaBridge 171:3a7713b1edbc 776 *
AnnaBridge 171:3a7713b1edbc 777 * @return The frequency of MCGOUTCLK.
AnnaBridge 171:3a7713b1edbc 778 */
AnnaBridge 171:3a7713b1edbc 779 uint32_t CLOCK_GetOutClkFreq(void);
AnnaBridge 171:3a7713b1edbc 780
AnnaBridge 171:3a7713b1edbc 781 /*!
AnnaBridge 171:3a7713b1edbc 782 * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
AnnaBridge 171:3a7713b1edbc 783 *
AnnaBridge 171:3a7713b1edbc 784 * This function gets the MCG FLL clock frequency in Hz based on the current MCG
AnnaBridge 171:3a7713b1edbc 785 * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
AnnaBridge 171:3a7713b1edbc 786 * disabled in low power state in other modes.
AnnaBridge 171:3a7713b1edbc 787 *
AnnaBridge 171:3a7713b1edbc 788 * @return The frequency of MCGFLLCLK.
AnnaBridge 171:3a7713b1edbc 789 */
AnnaBridge 171:3a7713b1edbc 790 uint32_t CLOCK_GetFllFreq(void);
AnnaBridge 171:3a7713b1edbc 791
AnnaBridge 171:3a7713b1edbc 792 /*!
AnnaBridge 171:3a7713b1edbc 793 * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
AnnaBridge 171:3a7713b1edbc 794 *
AnnaBridge 171:3a7713b1edbc 795 * This function gets the MCG internal reference clock frequency in Hz based
AnnaBridge 171:3a7713b1edbc 796 * on the current MCG register value.
AnnaBridge 171:3a7713b1edbc 797 *
AnnaBridge 171:3a7713b1edbc 798 * @return The frequency of MCGIRCLK.
AnnaBridge 171:3a7713b1edbc 799 */
AnnaBridge 171:3a7713b1edbc 800 uint32_t CLOCK_GetInternalRefClkFreq(void);
AnnaBridge 171:3a7713b1edbc 801
AnnaBridge 171:3a7713b1edbc 802 /*!
AnnaBridge 171:3a7713b1edbc 803 * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
AnnaBridge 171:3a7713b1edbc 804 *
AnnaBridge 171:3a7713b1edbc 805 * This function gets the MCG fixed frequency clock frequency in Hz based
AnnaBridge 171:3a7713b1edbc 806 * on the current MCG register value.
AnnaBridge 171:3a7713b1edbc 807 *
AnnaBridge 171:3a7713b1edbc 808 * @return The frequency of MCGFFCLK.
AnnaBridge 171:3a7713b1edbc 809 */
AnnaBridge 171:3a7713b1edbc 810 uint32_t CLOCK_GetFixedFreqClkFreq(void);
AnnaBridge 171:3a7713b1edbc 811
AnnaBridge 171:3a7713b1edbc 812 /*!
AnnaBridge 171:3a7713b1edbc 813 * @brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency.
AnnaBridge 171:3a7713b1edbc 814 *
AnnaBridge 171:3a7713b1edbc 815 * This function gets the MCG PLL0 clock frequency in Hz based on the current MCG
AnnaBridge 171:3a7713b1edbc 816 * register value.
AnnaBridge 171:3a7713b1edbc 817 *
AnnaBridge 171:3a7713b1edbc 818 * @return The frequency of MCGPLL0CLK.
AnnaBridge 171:3a7713b1edbc 819 */
AnnaBridge 171:3a7713b1edbc 820 uint32_t CLOCK_GetPll0Freq(void);
AnnaBridge 171:3a7713b1edbc 821
AnnaBridge 171:3a7713b1edbc 822 /*@}*/
AnnaBridge 171:3a7713b1edbc 823
AnnaBridge 171:3a7713b1edbc 824 /*! @name MCG clock configuration. */
AnnaBridge 171:3a7713b1edbc 825 /*@{*/
AnnaBridge 171:3a7713b1edbc 826
AnnaBridge 171:3a7713b1edbc 827 /*!
AnnaBridge 171:3a7713b1edbc 828 * @brief Enables or disables the MCG low power.
AnnaBridge 171:3a7713b1edbc 829 *
AnnaBridge 171:3a7713b1edbc 830 * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
AnnaBridge 171:3a7713b1edbc 831 * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
AnnaBridge 171:3a7713b1edbc 832 * PBI modes, enabling low power sets the MCG to BLPI mode.
AnnaBridge 171:3a7713b1edbc 833 * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
AnnaBridge 171:3a7713b1edbc 834 *
AnnaBridge 171:3a7713b1edbc 835 * @param enable True to enable MCG low power, false to disable MCG low power.
AnnaBridge 171:3a7713b1edbc 836 */
AnnaBridge 171:3a7713b1edbc 837 static inline void CLOCK_SetLowPowerEnable(bool enable)
AnnaBridge 171:3a7713b1edbc 838 {
AnnaBridge 171:3a7713b1edbc 839 if (enable)
AnnaBridge 171:3a7713b1edbc 840 {
AnnaBridge 171:3a7713b1edbc 841 MCG->C2 |= MCG_C2_LP_MASK;
AnnaBridge 171:3a7713b1edbc 842 }
AnnaBridge 171:3a7713b1edbc 843 else
AnnaBridge 171:3a7713b1edbc 844 {
AnnaBridge 171:3a7713b1edbc 845 MCG->C2 &= ~MCG_C2_LP_MASK;
AnnaBridge 171:3a7713b1edbc 846 }
AnnaBridge 171:3a7713b1edbc 847 }
AnnaBridge 171:3a7713b1edbc 848
AnnaBridge 171:3a7713b1edbc 849 /*!
AnnaBridge 171:3a7713b1edbc 850 * @brief Configures the Internal Reference clock (MCGIRCLK).
AnnaBridge 171:3a7713b1edbc 851 *
AnnaBridge 171:3a7713b1edbc 852 * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
AnnaBridge 171:3a7713b1edbc 853 * source. If the fast IRC is used, this function sets the fast IRC divider.
AnnaBridge 171:3a7713b1edbc 854 * This function also sets whether the \c MCGIRCLK is enabled in stop mode.
AnnaBridge 171:3a7713b1edbc 855 * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
AnnaBridge 171:3a7713b1edbc 856 * using the function in these modes it is not allowed.
AnnaBridge 171:3a7713b1edbc 857 *
AnnaBridge 171:3a7713b1edbc 858 * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
AnnaBridge 171:3a7713b1edbc 859 * @param ircs MCGIRCLK clock source, choose fast or slow.
AnnaBridge 171:3a7713b1edbc 860 * @param fcrdiv Fast IRC divider setting (\c FCRDIV).
AnnaBridge 171:3a7713b1edbc 861 * @retval kStatus_MCG_SourceUsed Because the internall reference clock is used as a clock source,
AnnaBridge 171:3a7713b1edbc 862 * the confuration should not be changed. Otherwise, a glitch occurs.
AnnaBridge 171:3a7713b1edbc 863 * @retval kStatus_Success MCGIRCLK configuration finished successfully.
AnnaBridge 171:3a7713b1edbc 864 */
AnnaBridge 171:3a7713b1edbc 865 status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
AnnaBridge 171:3a7713b1edbc 866
AnnaBridge 171:3a7713b1edbc 867 /*!
AnnaBridge 171:3a7713b1edbc 868 * @brief Selects the MCG external reference clock.
AnnaBridge 171:3a7713b1edbc 869 *
AnnaBridge 171:3a7713b1edbc 870 * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
AnnaBridge 171:3a7713b1edbc 871 * and waits for the clock source to be stable. Because the external reference
AnnaBridge 171:3a7713b1edbc 872 * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
AnnaBridge 171:3a7713b1edbc 873 *
AnnaBridge 171:3a7713b1edbc 874 * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
AnnaBridge 171:3a7713b1edbc 875 * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
AnnaBridge 171:3a7713b1edbc 876 * the confuration should not be changed. Otherwise, a glitch occurs.
AnnaBridge 171:3a7713b1edbc 877 * @retval kStatus_Success External reference clock set successfully.
AnnaBridge 171:3a7713b1edbc 878 */
AnnaBridge 171:3a7713b1edbc 879 status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
AnnaBridge 171:3a7713b1edbc 880
AnnaBridge 171:3a7713b1edbc 881 /*!
AnnaBridge 171:3a7713b1edbc 882 * @brief Enables the PLL0 in FLL mode.
AnnaBridge 171:3a7713b1edbc 883 *
AnnaBridge 171:3a7713b1edbc 884 * This function sets us the PLL0 in FLL mode and reconfigures
AnnaBridge 171:3a7713b1edbc 885 * the PLL0. Ensure that the PLL reference
AnnaBridge 171:3a7713b1edbc 886 * clock is enabled before calling this function and that the PLL0 is not used as a clock source.
AnnaBridge 171:3a7713b1edbc 887 * The function CLOCK_CalcPllDiv gets the correct PLL
AnnaBridge 171:3a7713b1edbc 888 * divider values.
AnnaBridge 171:3a7713b1edbc 889 *
AnnaBridge 171:3a7713b1edbc 890 * @param config Pointer to the configuration structure.
AnnaBridge 171:3a7713b1edbc 891 */
AnnaBridge 171:3a7713b1edbc 892 void CLOCK_EnablePll0(mcg_pll_config_t const *config);
AnnaBridge 171:3a7713b1edbc 893
AnnaBridge 171:3a7713b1edbc 894 /*!
AnnaBridge 171:3a7713b1edbc 895 * @brief Disables the PLL0 in FLL mode.
AnnaBridge 171:3a7713b1edbc 896 *
AnnaBridge 171:3a7713b1edbc 897 * This function disables the PLL0 in FLL mode. It should be used together with the
AnnaBridge 171:3a7713b1edbc 898 * @ref CLOCK_EnablePll0.
AnnaBridge 171:3a7713b1edbc 899 */
AnnaBridge 171:3a7713b1edbc 900 static inline void CLOCK_DisablePll0(void)
AnnaBridge 171:3a7713b1edbc 901 {
AnnaBridge 171:3a7713b1edbc 902 MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK);
AnnaBridge 171:3a7713b1edbc 903 }
AnnaBridge 171:3a7713b1edbc 904
AnnaBridge 171:3a7713b1edbc 905 /*!
AnnaBridge 171:3a7713b1edbc 906 * @brief Calculates the PLL divider setting for a desired output frequency.
AnnaBridge 171:3a7713b1edbc 907 *
AnnaBridge 171:3a7713b1edbc 908 * This function calculates the correct reference clock divider (\c PRDIV) and
AnnaBridge 171:3a7713b1edbc 909 * VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the
AnnaBridge 171:3a7713b1edbc 910 * closest frequency match with the corresponding \c PRDIV/VDIV
AnnaBridge 171:3a7713b1edbc 911 * returned from parameters. If a desired frequency is not valid, this function
AnnaBridge 171:3a7713b1edbc 912 * returns 0.
AnnaBridge 171:3a7713b1edbc 913 *
AnnaBridge 171:3a7713b1edbc 914 * @param refFreq PLL reference clock frequency.
AnnaBridge 171:3a7713b1edbc 915 * @param desireFreq Desired PLL output frequency.
AnnaBridge 171:3a7713b1edbc 916 * @param prdiv PRDIV value to generate desired PLL frequency.
AnnaBridge 171:3a7713b1edbc 917 * @param vdiv VDIV value to generate desired PLL frequency.
AnnaBridge 171:3a7713b1edbc 918 * @return Closest frequency match that the PLL was able generate.
AnnaBridge 171:3a7713b1edbc 919 */
AnnaBridge 171:3a7713b1edbc 920 uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv);
AnnaBridge 171:3a7713b1edbc 921
AnnaBridge 171:3a7713b1edbc 922 /*@}*/
AnnaBridge 171:3a7713b1edbc 923
AnnaBridge 171:3a7713b1edbc 924 /*! @name MCG clock lock monitor functions. */
AnnaBridge 171:3a7713b1edbc 925 /*@{*/
AnnaBridge 171:3a7713b1edbc 926
AnnaBridge 171:3a7713b1edbc 927 /*!
AnnaBridge 171:3a7713b1edbc 928 * @brief Sets the OSC0 clock monitor mode.
AnnaBridge 171:3a7713b1edbc 929 *
AnnaBridge 171:3a7713b1edbc 930 * This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
AnnaBridge 171:3a7713b1edbc 931 *
AnnaBridge 171:3a7713b1edbc 932 * @param mode Monitor mode to set.
AnnaBridge 171:3a7713b1edbc 933 */
AnnaBridge 171:3a7713b1edbc 934 void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
AnnaBridge 171:3a7713b1edbc 935
AnnaBridge 171:3a7713b1edbc 936 /*!
AnnaBridge 171:3a7713b1edbc 937 * @brief Sets the RTC OSC clock monitor mode.
AnnaBridge 171:3a7713b1edbc 938 *
AnnaBridge 171:3a7713b1edbc 939 * This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details.
AnnaBridge 171:3a7713b1edbc 940 *
AnnaBridge 171:3a7713b1edbc 941 * @param mode Monitor mode to set.
AnnaBridge 171:3a7713b1edbc 942 */
AnnaBridge 171:3a7713b1edbc 943 void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode);
AnnaBridge 171:3a7713b1edbc 944
AnnaBridge 171:3a7713b1edbc 945 /*!
AnnaBridge 171:3a7713b1edbc 946 * @brief Sets the PLL0 clock monitor mode.
AnnaBridge 171:3a7713b1edbc 947 *
AnnaBridge 171:3a7713b1edbc 948 * This function sets the PLL0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
AnnaBridge 171:3a7713b1edbc 949 *
AnnaBridge 171:3a7713b1edbc 950 * @param mode Monitor mode to set.
AnnaBridge 171:3a7713b1edbc 951 */
AnnaBridge 171:3a7713b1edbc 952 void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode);
AnnaBridge 171:3a7713b1edbc 953
AnnaBridge 171:3a7713b1edbc 954 /*!
AnnaBridge 171:3a7713b1edbc 955 * @brief Gets the MCG status flags.
AnnaBridge 171:3a7713b1edbc 956 *
AnnaBridge 171:3a7713b1edbc 957 * This function gets the MCG clock status flags. All status flags are
AnnaBridge 171:3a7713b1edbc 958 * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To
AnnaBridge 171:3a7713b1edbc 959 * check a specific flag, compare the return value with the flag.
AnnaBridge 171:3a7713b1edbc 960 *
AnnaBridge 171:3a7713b1edbc 961 * Example:
AnnaBridge 171:3a7713b1edbc 962 * @code
AnnaBridge 171:3a7713b1edbc 963 // To check the clock lost lock status of OSC0 and PLL0.
AnnaBridge 171:3a7713b1edbc 964 uint32_t mcgFlags;
AnnaBridge 171:3a7713b1edbc 965
AnnaBridge 171:3a7713b1edbc 966 mcgFlags = CLOCK_GetStatusFlags();
AnnaBridge 171:3a7713b1edbc 967
AnnaBridge 171:3a7713b1edbc 968 if (mcgFlags & kMCG_Osc0LostFlag)
AnnaBridge 171:3a7713b1edbc 969 {
AnnaBridge 171:3a7713b1edbc 970 // OSC0 clock lock lost. Do something.
AnnaBridge 171:3a7713b1edbc 971 }
AnnaBridge 171:3a7713b1edbc 972 if (mcgFlags & kMCG_Pll0LostFlag)
AnnaBridge 171:3a7713b1edbc 973 {
AnnaBridge 171:3a7713b1edbc 974 // PLL0 clock lock lost. Do something.
AnnaBridge 171:3a7713b1edbc 975 }
AnnaBridge 171:3a7713b1edbc 976 @endcode
AnnaBridge 171:3a7713b1edbc 977 *
AnnaBridge 171:3a7713b1edbc 978 * @return Logical OR value of the @ref _mcg_status_flags_t.
AnnaBridge 171:3a7713b1edbc 979 */
AnnaBridge 171:3a7713b1edbc 980 uint32_t CLOCK_GetStatusFlags(void);
AnnaBridge 171:3a7713b1edbc 981
AnnaBridge 171:3a7713b1edbc 982 /*!
AnnaBridge 171:3a7713b1edbc 983 * @brief Clears the MCG status flags.
AnnaBridge 171:3a7713b1edbc 984 *
AnnaBridge 171:3a7713b1edbc 985 * This function clears the MCG clock lock lost status. The parameter is a logical
AnnaBridge 171:3a7713b1edbc 986 * OR value of the flags to clear. See @ref _mcg_status_flags_t.
AnnaBridge 171:3a7713b1edbc 987 *
AnnaBridge 171:3a7713b1edbc 988 * Example:
AnnaBridge 171:3a7713b1edbc 989 * @code
AnnaBridge 171:3a7713b1edbc 990 // To clear the clock lost lock status flags of OSC0 and PLL0.
AnnaBridge 171:3a7713b1edbc 991
AnnaBridge 171:3a7713b1edbc 992 CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
AnnaBridge 171:3a7713b1edbc 993 @endcode
AnnaBridge 171:3a7713b1edbc 994 *
AnnaBridge 171:3a7713b1edbc 995 * @param mask The status flags to clear. This is a logical OR of members of the
AnnaBridge 171:3a7713b1edbc 996 * enumeration @ref _mcg_status_flags_t.
AnnaBridge 171:3a7713b1edbc 997 */
AnnaBridge 171:3a7713b1edbc 998 void CLOCK_ClearStatusFlags(uint32_t mask);
AnnaBridge 171:3a7713b1edbc 999
AnnaBridge 171:3a7713b1edbc 1000 /*@}*/
AnnaBridge 171:3a7713b1edbc 1001
AnnaBridge 171:3a7713b1edbc 1002 /*!
AnnaBridge 171:3a7713b1edbc 1003 * @name OSC configuration
AnnaBridge 171:3a7713b1edbc 1004 * @{
AnnaBridge 171:3a7713b1edbc 1005 */
AnnaBridge 171:3a7713b1edbc 1006
AnnaBridge 171:3a7713b1edbc 1007 /*!
AnnaBridge 171:3a7713b1edbc 1008 * @brief Configures the OSC external reference clock (OSCERCLK).
AnnaBridge 171:3a7713b1edbc 1009 *
AnnaBridge 171:3a7713b1edbc 1010 * This function configures the OSC external reference clock (OSCERCLK).
AnnaBridge 171:3a7713b1edbc 1011 * This is an example to enable the OSCERCLK in normal and stop modes and also set
AnnaBridge 171:3a7713b1edbc 1012 * the output divider to 1:
AnnaBridge 171:3a7713b1edbc 1013 *
AnnaBridge 171:3a7713b1edbc 1014 @code
AnnaBridge 171:3a7713b1edbc 1015 oscer_config_t config =
AnnaBridge 171:3a7713b1edbc 1016 {
AnnaBridge 171:3a7713b1edbc 1017 .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
AnnaBridge 171:3a7713b1edbc 1018 .erclkDiv = 1U,
AnnaBridge 171:3a7713b1edbc 1019 };
AnnaBridge 171:3a7713b1edbc 1020
AnnaBridge 171:3a7713b1edbc 1021 OSC_SetExtRefClkConfig(OSC, &config);
AnnaBridge 171:3a7713b1edbc 1022 @endcode
AnnaBridge 171:3a7713b1edbc 1023 *
AnnaBridge 171:3a7713b1edbc 1024 * @param base OSC peripheral address.
AnnaBridge 171:3a7713b1edbc 1025 * @param config Pointer to the configuration structure.
AnnaBridge 171:3a7713b1edbc 1026 */
AnnaBridge 171:3a7713b1edbc 1027 static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config)
AnnaBridge 171:3a7713b1edbc 1028 {
AnnaBridge 171:3a7713b1edbc 1029 uint8_t reg = base->CR;
AnnaBridge 171:3a7713b1edbc 1030
AnnaBridge 171:3a7713b1edbc 1031 reg &= ~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK);
AnnaBridge 171:3a7713b1edbc 1032 reg |= config->enableMode;
AnnaBridge 171:3a7713b1edbc 1033
AnnaBridge 171:3a7713b1edbc 1034 base->CR = reg;
AnnaBridge 171:3a7713b1edbc 1035 }
AnnaBridge 171:3a7713b1edbc 1036
AnnaBridge 171:3a7713b1edbc 1037 /*!
AnnaBridge 171:3a7713b1edbc 1038 * @brief Sets the capacitor load configuration for the oscillator.
AnnaBridge 171:3a7713b1edbc 1039 *
AnnaBridge 171:3a7713b1edbc 1040 * This function sets the specified capacitors configuration for the oscillator.
AnnaBridge 171:3a7713b1edbc 1041 * This should be done in the early system level initialization function call
AnnaBridge 171:3a7713b1edbc 1042 * based on the system configuration.
AnnaBridge 171:3a7713b1edbc 1043 *
AnnaBridge 171:3a7713b1edbc 1044 * @param base OSC peripheral address.
AnnaBridge 171:3a7713b1edbc 1045 * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
AnnaBridge 171:3a7713b1edbc 1046 *
AnnaBridge 171:3a7713b1edbc 1047 * Example:
AnnaBridge 171:3a7713b1edbc 1048 @code
AnnaBridge 171:3a7713b1edbc 1049 // To enable only 2 pF and 8 pF capacitor load, please use like this.
AnnaBridge 171:3a7713b1edbc 1050 OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P);
AnnaBridge 171:3a7713b1edbc 1051 @endcode
AnnaBridge 171:3a7713b1edbc 1052 */
AnnaBridge 171:3a7713b1edbc 1053 static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
AnnaBridge 171:3a7713b1edbc 1054 {
AnnaBridge 171:3a7713b1edbc 1055 uint8_t reg = base->CR;
AnnaBridge 171:3a7713b1edbc 1056
AnnaBridge 171:3a7713b1edbc 1057 reg &= ~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK);
AnnaBridge 171:3a7713b1edbc 1058 reg |= capLoad;
AnnaBridge 171:3a7713b1edbc 1059
AnnaBridge 171:3a7713b1edbc 1060 base->CR = reg;
AnnaBridge 171:3a7713b1edbc 1061 }
AnnaBridge 171:3a7713b1edbc 1062
AnnaBridge 171:3a7713b1edbc 1063 /*!
AnnaBridge 171:3a7713b1edbc 1064 * @brief Initializes the OSC0.
AnnaBridge 171:3a7713b1edbc 1065 *
AnnaBridge 171:3a7713b1edbc 1066 * This function initializes the OSC0 according to the board configuration.
AnnaBridge 171:3a7713b1edbc 1067 *
AnnaBridge 171:3a7713b1edbc 1068 * @param config Pointer to the OSC0 configuration structure.
AnnaBridge 171:3a7713b1edbc 1069 */
AnnaBridge 171:3a7713b1edbc 1070 void CLOCK_InitOsc0(osc_config_t const *config);
AnnaBridge 171:3a7713b1edbc 1071
AnnaBridge 171:3a7713b1edbc 1072 /*!
AnnaBridge 171:3a7713b1edbc 1073 * @brief Deinitializes the OSC0.
AnnaBridge 171:3a7713b1edbc 1074 *
AnnaBridge 171:3a7713b1edbc 1075 * This function deinitializes the OSC0.
AnnaBridge 171:3a7713b1edbc 1076 */
AnnaBridge 171:3a7713b1edbc 1077 void CLOCK_DeinitOsc0(void);
AnnaBridge 171:3a7713b1edbc 1078
AnnaBridge 171:3a7713b1edbc 1079 /* @} */
AnnaBridge 171:3a7713b1edbc 1080
AnnaBridge 171:3a7713b1edbc 1081 /*!
AnnaBridge 171:3a7713b1edbc 1082 * @name External clock frequency
AnnaBridge 171:3a7713b1edbc 1083 * @{
AnnaBridge 171:3a7713b1edbc 1084 */
AnnaBridge 171:3a7713b1edbc 1085
AnnaBridge 171:3a7713b1edbc 1086 /*!
AnnaBridge 171:3a7713b1edbc 1087 * @brief Sets the XTAL0 frequency based on board settings.
AnnaBridge 171:3a7713b1edbc 1088 *
AnnaBridge 171:3a7713b1edbc 1089 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 1090 */
AnnaBridge 171:3a7713b1edbc 1091 static inline void CLOCK_SetXtal0Freq(uint32_t freq)
AnnaBridge 171:3a7713b1edbc 1092 {
AnnaBridge 171:3a7713b1edbc 1093 g_xtal0Freq = freq;
AnnaBridge 171:3a7713b1edbc 1094 }
AnnaBridge 171:3a7713b1edbc 1095
AnnaBridge 171:3a7713b1edbc 1096 /*!
AnnaBridge 171:3a7713b1edbc 1097 * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
AnnaBridge 171:3a7713b1edbc 1098 *
AnnaBridge 171:3a7713b1edbc 1099 * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 1100 */
AnnaBridge 171:3a7713b1edbc 1101 static inline void CLOCK_SetXtal32Freq(uint32_t freq)
AnnaBridge 171:3a7713b1edbc 1102 {
AnnaBridge 171:3a7713b1edbc 1103 g_xtal32Freq = freq;
AnnaBridge 171:3a7713b1edbc 1104 }
AnnaBridge 171:3a7713b1edbc 1105 /* @} */
AnnaBridge 171:3a7713b1edbc 1106
AnnaBridge 171:3a7713b1edbc 1107 /*!
AnnaBridge 171:3a7713b1edbc 1108 * @name MCG auto-trim machine.
AnnaBridge 171:3a7713b1edbc 1109 * @{
AnnaBridge 171:3a7713b1edbc 1110 */
AnnaBridge 171:3a7713b1edbc 1111
AnnaBridge 171:3a7713b1edbc 1112 /*!
AnnaBridge 171:3a7713b1edbc 1113 * @brief Auto trims the internal reference clock.
AnnaBridge 171:3a7713b1edbc 1114 *
AnnaBridge 171:3a7713b1edbc 1115 * This function trims the internal reference clock by using the external clock. If
AnnaBridge 171:3a7713b1edbc 1116 * successful, it returns the kStatus_Success and the frequency after
AnnaBridge 171:3a7713b1edbc 1117 * trimming is received in the parameter @p actualFreq. If an error occurs,
AnnaBridge 171:3a7713b1edbc 1118 * the error code is returned.
AnnaBridge 171:3a7713b1edbc 1119 *
AnnaBridge 171:3a7713b1edbc 1120 * @param extFreq External clock frequency, which should be a bus clock.
AnnaBridge 171:3a7713b1edbc 1121 * @param desireFreq Frequency to trim to.
AnnaBridge 171:3a7713b1edbc 1122 * @param actualFreq Actual frequency after trimming.
AnnaBridge 171:3a7713b1edbc 1123 * @param atms Trim fast or slow internal reference clock.
AnnaBridge 171:3a7713b1edbc 1124 * @retval kStatus_Success ATM success.
AnnaBridge 171:3a7713b1edbc 1125 * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
AnnaBridge 171:3a7713b1edbc 1126 * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
AnnaBridge 171:3a7713b1edbc 1127 * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
AnnaBridge 171:3a7713b1edbc 1128 * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
AnnaBridge 171:3a7713b1edbc 1129 */
AnnaBridge 171:3a7713b1edbc 1130 status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
AnnaBridge 171:3a7713b1edbc 1131 /* @} */
AnnaBridge 171:3a7713b1edbc 1132
AnnaBridge 171:3a7713b1edbc 1133 /*! @name MCG mode functions. */
AnnaBridge 171:3a7713b1edbc 1134 /*@{*/
AnnaBridge 171:3a7713b1edbc 1135
AnnaBridge 171:3a7713b1edbc 1136 /*!
AnnaBridge 171:3a7713b1edbc 1137 * @brief Gets the current MCG mode.
AnnaBridge 171:3a7713b1edbc 1138 *
AnnaBridge 171:3a7713b1edbc 1139 * This function checks the MCG registers and determines the current MCG mode.
AnnaBridge 171:3a7713b1edbc 1140 *
AnnaBridge 171:3a7713b1edbc 1141 * @return Current MCG mode or error code; See @ref mcg_mode_t.
AnnaBridge 171:3a7713b1edbc 1142 */
AnnaBridge 171:3a7713b1edbc 1143 mcg_mode_t CLOCK_GetMode(void);
AnnaBridge 171:3a7713b1edbc 1144
AnnaBridge 171:3a7713b1edbc 1145 /*!
AnnaBridge 171:3a7713b1edbc 1146 * @brief Sets the MCG to FEI mode.
AnnaBridge 171:3a7713b1edbc 1147 *
AnnaBridge 171:3a7713b1edbc 1148 * This function sets the MCG to FEI mode. If setting to FEI mode fails
AnnaBridge 171:3a7713b1edbc 1149 * from the current mode, this function returns an error.
AnnaBridge 171:3a7713b1edbc 1150 *
AnnaBridge 171:3a7713b1edbc 1151 * @param dmx32 DMX32 in FEI mode.
AnnaBridge 171:3a7713b1edbc 1152 * @param drs The DCO range selection.
AnnaBridge 171:3a7713b1edbc 1153 * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing
AnnaBridge 171:3a7713b1edbc 1154 * NULL does not cause a delay.
AnnaBridge 171:3a7713b1edbc 1155 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 171:3a7713b1edbc 1156 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 1157 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
AnnaBridge 171:3a7713b1edbc 1158 * to a frequency above 32768 Hz.
AnnaBridge 171:3a7713b1edbc 1159 */
AnnaBridge 171:3a7713b1edbc 1160 status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge 171:3a7713b1edbc 1161
AnnaBridge 171:3a7713b1edbc 1162 /*!
AnnaBridge 171:3a7713b1edbc 1163 * @brief Sets the MCG to FEE mode.
AnnaBridge 171:3a7713b1edbc 1164 *
AnnaBridge 171:3a7713b1edbc 1165 * This function sets the MCG to FEE mode. If setting to FEE mode fails
AnnaBridge 171:3a7713b1edbc 1166 * from the current mode, this function returns an error.
AnnaBridge 171:3a7713b1edbc 1167 *
AnnaBridge 171:3a7713b1edbc 1168 * @param frdiv FLL reference clock divider setting, FRDIV.
AnnaBridge 171:3a7713b1edbc 1169 * @param dmx32 DMX32 in FEE mode.
AnnaBridge 171:3a7713b1edbc 1170 * @param drs The DCO range selection.
AnnaBridge 171:3a7713b1edbc 1171 * @param fllStableDelay Delay function to make sure FLL is stable. Passing
AnnaBridge 171:3a7713b1edbc 1172 * NULL does not cause a delay.
AnnaBridge 171:3a7713b1edbc 1173 *
AnnaBridge 171:3a7713b1edbc 1174 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 171:3a7713b1edbc 1175 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 1176 */
AnnaBridge 171:3a7713b1edbc 1177 status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge 171:3a7713b1edbc 1178
AnnaBridge 171:3a7713b1edbc 1179 /*!
AnnaBridge 171:3a7713b1edbc 1180 * @brief Sets the MCG to FBI mode.
AnnaBridge 171:3a7713b1edbc 1181 *
AnnaBridge 171:3a7713b1edbc 1182 * This function sets the MCG to FBI mode. If setting to FBI mode fails
AnnaBridge 171:3a7713b1edbc 1183 * from the current mode, this function returns an error.
AnnaBridge 171:3a7713b1edbc 1184 *
AnnaBridge 171:3a7713b1edbc 1185 * @param dmx32 DMX32 in FBI mode.
AnnaBridge 171:3a7713b1edbc 1186 * @param drs The DCO range selection.
AnnaBridge 171:3a7713b1edbc 1187 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
AnnaBridge 171:3a7713b1edbc 1188 * is not used in FBI mode, this parameter can be NULL. Passing
AnnaBridge 171:3a7713b1edbc 1189 * NULL does not cause a delay.
AnnaBridge 171:3a7713b1edbc 1190 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 171:3a7713b1edbc 1191 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 1192 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
AnnaBridge 171:3a7713b1edbc 1193 * to frequency above 32768 Hz.
AnnaBridge 171:3a7713b1edbc 1194 */
AnnaBridge 171:3a7713b1edbc 1195 status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge 171:3a7713b1edbc 1196
AnnaBridge 171:3a7713b1edbc 1197 /*!
AnnaBridge 171:3a7713b1edbc 1198 * @brief Sets the MCG to FBE mode.
AnnaBridge 171:3a7713b1edbc 1199 *
AnnaBridge 171:3a7713b1edbc 1200 * This function sets the MCG to FBE mode. If setting to FBE mode fails
AnnaBridge 171:3a7713b1edbc 1201 * from the current mode, this function returns an error.
AnnaBridge 171:3a7713b1edbc 1202 *
AnnaBridge 171:3a7713b1edbc 1203 * @param frdiv FLL reference clock divider setting, FRDIV.
AnnaBridge 171:3a7713b1edbc 1204 * @param dmx32 DMX32 in FBE mode.
AnnaBridge 171:3a7713b1edbc 1205 * @param drs The DCO range selection.
AnnaBridge 171:3a7713b1edbc 1206 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
AnnaBridge 171:3a7713b1edbc 1207 * is not used in FBE mode, this parameter can be NULL. Passing NULL
AnnaBridge 171:3a7713b1edbc 1208 * does not cause a delay.
AnnaBridge 171:3a7713b1edbc 1209 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 171:3a7713b1edbc 1210 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 1211 */
AnnaBridge 171:3a7713b1edbc 1212 status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge 171:3a7713b1edbc 1213
AnnaBridge 171:3a7713b1edbc 1214 /*!
AnnaBridge 171:3a7713b1edbc 1215 * @brief Sets the MCG to BLPI mode.
AnnaBridge 171:3a7713b1edbc 1216 *
AnnaBridge 171:3a7713b1edbc 1217 * This function sets the MCG to BLPI mode. If setting to BLPI mode fails
AnnaBridge 171:3a7713b1edbc 1218 * from the current mode, this function returns an error.
AnnaBridge 171:3a7713b1edbc 1219 *
AnnaBridge 171:3a7713b1edbc 1220 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 171:3a7713b1edbc 1221 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 1222 */
AnnaBridge 171:3a7713b1edbc 1223 status_t CLOCK_SetBlpiMode(void);
AnnaBridge 171:3a7713b1edbc 1224
AnnaBridge 171:3a7713b1edbc 1225 /*!
AnnaBridge 171:3a7713b1edbc 1226 * @brief Sets the MCG to BLPE mode.
AnnaBridge 171:3a7713b1edbc 1227 *
AnnaBridge 171:3a7713b1edbc 1228 * This function sets the MCG to BLPE mode. If setting to BLPE mode fails
AnnaBridge 171:3a7713b1edbc 1229 * from the current mode, this function returns an error.
AnnaBridge 171:3a7713b1edbc 1230 *
AnnaBridge 171:3a7713b1edbc 1231 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 171:3a7713b1edbc 1232 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 1233 */
AnnaBridge 171:3a7713b1edbc 1234 status_t CLOCK_SetBlpeMode(void);
AnnaBridge 171:3a7713b1edbc 1235
AnnaBridge 171:3a7713b1edbc 1236 /*!
AnnaBridge 171:3a7713b1edbc 1237 * @brief Sets the MCG to PBE mode.
AnnaBridge 171:3a7713b1edbc 1238 *
AnnaBridge 171:3a7713b1edbc 1239 * This function sets the MCG to PBE mode. If setting to PBE mode fails
AnnaBridge 171:3a7713b1edbc 1240 * from the current mode, this function returns an error.
AnnaBridge 171:3a7713b1edbc 1241 *
AnnaBridge 171:3a7713b1edbc 1242 * @param pllcs The PLL selection, PLLCS.
AnnaBridge 171:3a7713b1edbc 1243 * @param config Pointer to the PLL configuration.
AnnaBridge 171:3a7713b1edbc 1244 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 171:3a7713b1edbc 1245 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 1246 *
AnnaBridge 171:3a7713b1edbc 1247 * @note
AnnaBridge 171:3a7713b1edbc 1248 * 1. The parameter \c pllcs selects the PLL. For platforms with
AnnaBridge 171:3a7713b1edbc 1249 * only one PLL, the parameter pllcs is kept for interface compatibility.
AnnaBridge 171:3a7713b1edbc 1250 * 2. The parameter \c config is the PLL configuration structure. On some
AnnaBridge 171:3a7713b1edbc 1251 * platforms, it is possible to choose the external PLL directly, which renders the
AnnaBridge 171:3a7713b1edbc 1252 * configuration structure not necessary. In this case, pass in NULL.
AnnaBridge 171:3a7713b1edbc 1253 * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
AnnaBridge 171:3a7713b1edbc 1254 */
AnnaBridge 171:3a7713b1edbc 1255 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
AnnaBridge 171:3a7713b1edbc 1256
AnnaBridge 171:3a7713b1edbc 1257 /*!
AnnaBridge 171:3a7713b1edbc 1258 * @brief Sets the MCG to PEE mode.
AnnaBridge 171:3a7713b1edbc 1259 *
AnnaBridge 171:3a7713b1edbc 1260 * This function sets the MCG to PEE mode.
AnnaBridge 171:3a7713b1edbc 1261 *
AnnaBridge 171:3a7713b1edbc 1262 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 171:3a7713b1edbc 1263 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 1264 *
AnnaBridge 171:3a7713b1edbc 1265 * @note This function only changes the CLKS to use the PLL/FLL output. If the
AnnaBridge 171:3a7713b1edbc 1266 * PRDIV/VDIV are different than in the PBE mode, set them up
AnnaBridge 171:3a7713b1edbc 1267 * in PBE mode and wait. When the clock is stable, switch to PEE mode.
AnnaBridge 171:3a7713b1edbc 1268 */
AnnaBridge 171:3a7713b1edbc 1269 status_t CLOCK_SetPeeMode(void);
AnnaBridge 171:3a7713b1edbc 1270
AnnaBridge 171:3a7713b1edbc 1271 /*!
AnnaBridge 171:3a7713b1edbc 1272 * @brief Switches the MCG to FBE mode from the external mode.
AnnaBridge 171:3a7713b1edbc 1273 *
AnnaBridge 171:3a7713b1edbc 1274 * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
AnnaBridge 171:3a7713b1edbc 1275 * The external clock is used as the system clock souce and PLL is disabled. However,
AnnaBridge 171:3a7713b1edbc 1276 * the FLL settings are not configured. This is a lite function with a small code size, which is useful
AnnaBridge 171:3a7713b1edbc 1277 * during the mode switch. For example, to switch from PEE mode to FEI mode:
AnnaBridge 171:3a7713b1edbc 1278 *
AnnaBridge 171:3a7713b1edbc 1279 * @code
AnnaBridge 171:3a7713b1edbc 1280 * CLOCK_ExternalModeToFbeModeQuick();
AnnaBridge 171:3a7713b1edbc 1281 * CLOCK_SetFeiMode(...);
AnnaBridge 171:3a7713b1edbc 1282 * @endcode
AnnaBridge 171:3a7713b1edbc 1283 *
AnnaBridge 171:3a7713b1edbc 1284 * @retval kStatus_Success Switched successfully.
AnnaBridge 171:3a7713b1edbc 1285 * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
AnnaBridge 171:3a7713b1edbc 1286 */
AnnaBridge 171:3a7713b1edbc 1287 status_t CLOCK_ExternalModeToFbeModeQuick(void);
AnnaBridge 171:3a7713b1edbc 1288
AnnaBridge 171:3a7713b1edbc 1289 /*!
AnnaBridge 171:3a7713b1edbc 1290 * @brief Switches the MCG to FBI mode from internal modes.
AnnaBridge 171:3a7713b1edbc 1291 *
AnnaBridge 171:3a7713b1edbc 1292 * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
AnnaBridge 171:3a7713b1edbc 1293 * The MCGIRCLK is used as the system clock souce and PLL is disabled. However,
AnnaBridge 171:3a7713b1edbc 1294 * FLL settings are not configured. This is a lite function with a small code size, which is useful
AnnaBridge 171:3a7713b1edbc 1295 * during the mode switch. For example, to switch from PEI mode to FEE mode:
AnnaBridge 171:3a7713b1edbc 1296 *
AnnaBridge 171:3a7713b1edbc 1297 * @code
AnnaBridge 171:3a7713b1edbc 1298 * CLOCK_InternalModeToFbiModeQuick();
AnnaBridge 171:3a7713b1edbc 1299 * CLOCK_SetFeeMode(...);
AnnaBridge 171:3a7713b1edbc 1300 * @endcode
AnnaBridge 171:3a7713b1edbc 1301 *
AnnaBridge 171:3a7713b1edbc 1302 * @retval kStatus_Success Switched successfully.
AnnaBridge 171:3a7713b1edbc 1303 * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
AnnaBridge 171:3a7713b1edbc 1304 */
AnnaBridge 171:3a7713b1edbc 1305 status_t CLOCK_InternalModeToFbiModeQuick(void);
AnnaBridge 171:3a7713b1edbc 1306
AnnaBridge 171:3a7713b1edbc 1307 /*!
AnnaBridge 171:3a7713b1edbc 1308 * @brief Sets the MCG to FEI mode during system boot up.
AnnaBridge 171:3a7713b1edbc 1309 *
AnnaBridge 171:3a7713b1edbc 1310 * This function sets the MCG to FEI mode from the reset mode. It can also be used to
AnnaBridge 171:3a7713b1edbc 1311 * set up MCG during system boot up.
AnnaBridge 171:3a7713b1edbc 1312 *
AnnaBridge 171:3a7713b1edbc 1313 * @param dmx32 DMX32 in FEI mode.
AnnaBridge 171:3a7713b1edbc 1314 * @param drs The DCO range selection.
AnnaBridge 171:3a7713b1edbc 1315 * @param fllStableDelay Delay function to ensure that the FLL is stable.
AnnaBridge 171:3a7713b1edbc 1316 *
AnnaBridge 171:3a7713b1edbc 1317 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 171:3a7713b1edbc 1318 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 1319 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
AnnaBridge 171:3a7713b1edbc 1320 * to frequency above 32768 Hz.
AnnaBridge 171:3a7713b1edbc 1321 */
AnnaBridge 171:3a7713b1edbc 1322 status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge 171:3a7713b1edbc 1323
AnnaBridge 171:3a7713b1edbc 1324 /*!
AnnaBridge 171:3a7713b1edbc 1325 * @brief Sets the MCG to FEE mode during system bootup.
AnnaBridge 171:3a7713b1edbc 1326 *
AnnaBridge 171:3a7713b1edbc 1327 * This function sets MCG to FEE mode from the reset mode. It can also be used to
AnnaBridge 171:3a7713b1edbc 1328 * set up the MCG during system boot up.
AnnaBridge 171:3a7713b1edbc 1329 *
AnnaBridge 171:3a7713b1edbc 1330 * @param oscsel OSC clock select, OSCSEL.
AnnaBridge 171:3a7713b1edbc 1331 * @param frdiv FLL reference clock divider setting, FRDIV.
AnnaBridge 171:3a7713b1edbc 1332 * @param dmx32 DMX32 in FEE mode.
AnnaBridge 171:3a7713b1edbc 1333 * @param drs The DCO range selection.
AnnaBridge 171:3a7713b1edbc 1334 * @param fllStableDelay Delay function to ensure that the FLL is stable.
AnnaBridge 171:3a7713b1edbc 1335 *
AnnaBridge 171:3a7713b1edbc 1336 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 171:3a7713b1edbc 1337 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 1338 */
AnnaBridge 171:3a7713b1edbc 1339 status_t CLOCK_BootToFeeMode(
AnnaBridge 171:3a7713b1edbc 1340 mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge 171:3a7713b1edbc 1341
AnnaBridge 171:3a7713b1edbc 1342 /*!
AnnaBridge 171:3a7713b1edbc 1343 * @brief Sets the MCG to BLPI mode during system boot up.
AnnaBridge 171:3a7713b1edbc 1344 *
AnnaBridge 171:3a7713b1edbc 1345 * This function sets the MCG to BLPI mode from the reset mode. It can also be used to
AnnaBridge 171:3a7713b1edbc 1346 * set up the MCG during sytem boot up.
AnnaBridge 171:3a7713b1edbc 1347 *
AnnaBridge 171:3a7713b1edbc 1348 * @param fcrdiv Fast IRC divider, FCRDIV.
AnnaBridge 171:3a7713b1edbc 1349 * @param ircs The internal reference clock to select, IRCS.
AnnaBridge 171:3a7713b1edbc 1350 * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
AnnaBridge 171:3a7713b1edbc 1351 *
AnnaBridge 171:3a7713b1edbc 1352 * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
AnnaBridge 171:3a7713b1edbc 1353 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 1354 */
AnnaBridge 171:3a7713b1edbc 1355 status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
AnnaBridge 171:3a7713b1edbc 1356
AnnaBridge 171:3a7713b1edbc 1357 /*!
AnnaBridge 171:3a7713b1edbc 1358 * @brief Sets the MCG to BLPE mode during sytem boot up.
AnnaBridge 171:3a7713b1edbc 1359 *
AnnaBridge 171:3a7713b1edbc 1360 * This function sets the MCG to BLPE mode from the reset mode. It can also be used to
AnnaBridge 171:3a7713b1edbc 1361 * set up the MCG during sytem boot up.
AnnaBridge 171:3a7713b1edbc 1362 *
AnnaBridge 171:3a7713b1edbc 1363 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
AnnaBridge 171:3a7713b1edbc 1364 *
AnnaBridge 171:3a7713b1edbc 1365 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 171:3a7713b1edbc 1366 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 1367 */
AnnaBridge 171:3a7713b1edbc 1368 status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
AnnaBridge 171:3a7713b1edbc 1369
AnnaBridge 171:3a7713b1edbc 1370 /*!
AnnaBridge 171:3a7713b1edbc 1371 * @brief Sets the MCG to PEE mode during system boot up.
AnnaBridge 171:3a7713b1edbc 1372 *
AnnaBridge 171:3a7713b1edbc 1373 * This function sets the MCG to PEE mode from reset mode. It can also be used to
AnnaBridge 171:3a7713b1edbc 1374 * set up the MCG during system boot up.
AnnaBridge 171:3a7713b1edbc 1375 *
AnnaBridge 171:3a7713b1edbc 1376 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
AnnaBridge 171:3a7713b1edbc 1377 * @param pllcs The PLL selection, PLLCS.
AnnaBridge 171:3a7713b1edbc 1378 * @param config Pointer to the PLL configuration.
AnnaBridge 171:3a7713b1edbc 1379 *
AnnaBridge 171:3a7713b1edbc 1380 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 171:3a7713b1edbc 1381 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 171:3a7713b1edbc 1382 */
AnnaBridge 171:3a7713b1edbc 1383 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
AnnaBridge 171:3a7713b1edbc 1384
AnnaBridge 171:3a7713b1edbc 1385 /*!
AnnaBridge 171:3a7713b1edbc 1386 * @brief Sets the MCG to a target mode.
AnnaBridge 171:3a7713b1edbc 1387 *
AnnaBridge 171:3a7713b1edbc 1388 * This function sets MCG to a target mode defined by the configuration
AnnaBridge 171:3a7713b1edbc 1389 * structure. If switching to the target mode fails, this function
AnnaBridge 171:3a7713b1edbc 1390 * chooses the correct path.
AnnaBridge 171:3a7713b1edbc 1391 *
AnnaBridge 171:3a7713b1edbc 1392 * @param config Pointer to the target MCG mode configuration structure.
AnnaBridge 171:3a7713b1edbc 1393 * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status.
AnnaBridge 171:3a7713b1edbc 1394 *
AnnaBridge 171:3a7713b1edbc 1395 * @note If the external clock is used in the target mode, ensure that it is
AnnaBridge 171:3a7713b1edbc 1396 * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
AnnaBridge 171:3a7713b1edbc 1397 * function.
AnnaBridge 171:3a7713b1edbc 1398 */
AnnaBridge 171:3a7713b1edbc 1399 status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
AnnaBridge 171:3a7713b1edbc 1400
AnnaBridge 171:3a7713b1edbc 1401 /*@}*/
AnnaBridge 171:3a7713b1edbc 1402
AnnaBridge 171:3a7713b1edbc 1403 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 1404 }
AnnaBridge 171:3a7713b1edbc 1405 #endif /* __cplusplus */
AnnaBridge 171:3a7713b1edbc 1406
AnnaBridge 171:3a7713b1edbc 1407 /*! @} */
AnnaBridge 171:3a7713b1edbc 1408
AnnaBridge 171:3a7713b1edbc 1409 #endif /* _FSL_CLOCK_H_ */