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mbed 2

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TARGET_K66F/TOOLCHAIN_IAR/MK66F18.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 ** ###################################################################
AnnaBridge 171:3a7713b1edbc 3 ** Processors: MK66FN2M0VLQ18
AnnaBridge 171:3a7713b1edbc 4 ** MK66FN2M0VMD18
AnnaBridge 171:3a7713b1edbc 5 ** MK66FX1M0VLQ18
AnnaBridge 171:3a7713b1edbc 6 ** MK66FX1M0VMD18
AnnaBridge 171:3a7713b1edbc 7 **
AnnaBridge 171:3a7713b1edbc 8 ** Compilers: Keil ARM C/C++ Compiler
AnnaBridge 171:3a7713b1edbc 9 ** Freescale C/C++ for Embedded ARM
AnnaBridge 171:3a7713b1edbc 10 ** GNU C Compiler
AnnaBridge 171:3a7713b1edbc 11 ** IAR ANSI C/C++ Compiler for ARM
AnnaBridge 171:3a7713b1edbc 12 ** MCUXpresso Compiler
AnnaBridge 171:3a7713b1edbc 13 **
AnnaBridge 171:3a7713b1edbc 14 ** Reference manual: K66P144M180SF5RMV2, Rev. 1, Mar 2015
AnnaBridge 171:3a7713b1edbc 15 ** Version: rev. 3.0, 2015-03-25
AnnaBridge 171:3a7713b1edbc 16 ** Build: b170112
AnnaBridge 171:3a7713b1edbc 17 **
AnnaBridge 171:3a7713b1edbc 18 ** Abstract:
AnnaBridge 171:3a7713b1edbc 19 ** CMSIS Peripheral Access Layer for MK66F18
AnnaBridge 171:3a7713b1edbc 20 **
AnnaBridge 171:3a7713b1edbc 21 ** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
AnnaBridge 171:3a7713b1edbc 22 ** Copyright 2016 - 2017 NXP
AnnaBridge 171:3a7713b1edbc 23 ** Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 24 ** are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 25 **
AnnaBridge 171:3a7713b1edbc 26 ** o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 171:3a7713b1edbc 27 ** of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 28 **
AnnaBridge 171:3a7713b1edbc 29 ** o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 171:3a7713b1edbc 30 ** list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 171:3a7713b1edbc 31 ** other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 32 **
AnnaBridge 171:3a7713b1edbc 33 ** o Neither the name of the copyright holder nor the names of its
AnnaBridge 171:3a7713b1edbc 34 ** contributors may be used to endorse or promote products derived from this
AnnaBridge 171:3a7713b1edbc 35 ** software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 36 **
AnnaBridge 171:3a7713b1edbc 37 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 171:3a7713b1edbc 38 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 171:3a7713b1edbc 39 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 40 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 41 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 171:3a7713b1edbc 42 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 171:3a7713b1edbc 43 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 171:3a7713b1edbc 44 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 171:3a7713b1edbc 45 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 171:3a7713b1edbc 46 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 47 **
AnnaBridge 171:3a7713b1edbc 48 ** http: www.nxp.com
AnnaBridge 171:3a7713b1edbc 49 ** mail: support@nxp.com
AnnaBridge 171:3a7713b1edbc 50 **
AnnaBridge 171:3a7713b1edbc 51 ** Revisions:
AnnaBridge 171:3a7713b1edbc 52 ** - rev. 1.0 (2013-09-02)
AnnaBridge 171:3a7713b1edbc 53 ** Initial version.
AnnaBridge 171:3a7713b1edbc 54 ** - rev. 2.0 (2014-02-17)
AnnaBridge 171:3a7713b1edbc 55 ** Register accessor macros added to the memory map.
AnnaBridge 171:3a7713b1edbc 56 ** Symbols for Processor Expert memory map compatibility added to the memory map.
AnnaBridge 171:3a7713b1edbc 57 ** Startup file for gcc has been updated according to CMSIS 3.2.
AnnaBridge 171:3a7713b1edbc 58 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
AnnaBridge 171:3a7713b1edbc 59 ** Update according to reference manual rev. 2
AnnaBridge 171:3a7713b1edbc 60 ** - rev. 2.1 (2014-04-16)
AnnaBridge 171:3a7713b1edbc 61 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
AnnaBridge 171:3a7713b1edbc 62 ** - rev. 2.2 (2014-10-14)
AnnaBridge 171:3a7713b1edbc 63 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
AnnaBridge 171:3a7713b1edbc 64 ** - rev. 2.3 (2014-11-20)
AnnaBridge 171:3a7713b1edbc 65 ** Update according to reverence manual K65P169M180SF5RMV2_NDA, Rev. 0 Draft A, October 2014.
AnnaBridge 171:3a7713b1edbc 66 ** Update of SystemInit() to use 16MHz external crystal.
AnnaBridge 171:3a7713b1edbc 67 ** - rev. 2.4 (2015-02-19)
AnnaBridge 171:3a7713b1edbc 68 ** Renamed interrupt vector LLW to LLWU.
AnnaBridge 171:3a7713b1edbc 69 ** - rev. 3.0 (2015-03-25)
AnnaBridge 171:3a7713b1edbc 70 ** Registers updated according to the reference manual revision 1, March 2015
AnnaBridge 171:3a7713b1edbc 71 **
AnnaBridge 171:3a7713b1edbc 72 ** ###################################################################
AnnaBridge 171:3a7713b1edbc 73 */
AnnaBridge 171:3a7713b1edbc 74
AnnaBridge 171:3a7713b1edbc 75 /*!
AnnaBridge 171:3a7713b1edbc 76 * @file MK66F18.h
AnnaBridge 171:3a7713b1edbc 77 * @version 3.0
AnnaBridge 171:3a7713b1edbc 78 * @date 2015-03-25
AnnaBridge 171:3a7713b1edbc 79 * @brief CMSIS Peripheral Access Layer for MK66F18
AnnaBridge 171:3a7713b1edbc 80 *
AnnaBridge 171:3a7713b1edbc 81 * CMSIS Peripheral Access Layer for MK66F18
AnnaBridge 171:3a7713b1edbc 82 */
AnnaBridge 171:3a7713b1edbc 83
AnnaBridge 171:3a7713b1edbc 84 #ifndef _MK66F18_H_
AnnaBridge 171:3a7713b1edbc 85 #define _MK66F18_H_ /**< Symbol preventing repeated inclusion */
AnnaBridge 171:3a7713b1edbc 86
AnnaBridge 171:3a7713b1edbc 87 /** Memory map major version (memory maps with equal major version number are
AnnaBridge 171:3a7713b1edbc 88 * compatible) */
AnnaBridge 171:3a7713b1edbc 89 #define MCU_MEM_MAP_VERSION 0x0300U
AnnaBridge 171:3a7713b1edbc 90 /** Memory map minor version */
AnnaBridge 171:3a7713b1edbc 91 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U
AnnaBridge 171:3a7713b1edbc 92
AnnaBridge 171:3a7713b1edbc 93 /**
AnnaBridge 171:3a7713b1edbc 94 * @brief Macro to calculate address of an aliased word in the peripheral
AnnaBridge 171:3a7713b1edbc 95 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
AnnaBridge 171:3a7713b1edbc 96 * 0x400FFFFF).
AnnaBridge 171:3a7713b1edbc 97 * @param Reg Register to access.
AnnaBridge 171:3a7713b1edbc 98 * @param Bit Bit number to access.
AnnaBridge 171:3a7713b1edbc 99 * @return Address of the aliased word in the peripheral bitband area.
AnnaBridge 171:3a7713b1edbc 100 */
AnnaBridge 171:3a7713b1edbc 101 #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
AnnaBridge 171:3a7713b1edbc 102 /**
AnnaBridge 171:3a7713b1edbc 103 * @brief Macro to access a single bit of a peripheral register (bit band region
AnnaBridge 171:3a7713b1edbc 104 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
AnnaBridge 171:3a7713b1edbc 105 * be used for peripherals with 32bit access allowed.
AnnaBridge 171:3a7713b1edbc 106 * @param Reg Register to access.
AnnaBridge 171:3a7713b1edbc 107 * @param Bit Bit number to access.
AnnaBridge 171:3a7713b1edbc 108 * @return Value of the targeted bit in the bit band region.
AnnaBridge 171:3a7713b1edbc 109 */
AnnaBridge 171:3a7713b1edbc 110 #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
AnnaBridge 171:3a7713b1edbc 111 #define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
AnnaBridge 171:3a7713b1edbc 112 /**
AnnaBridge 171:3a7713b1edbc 113 * @brief Macro to access a single bit of a peripheral register (bit band region
AnnaBridge 171:3a7713b1edbc 114 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
AnnaBridge 171:3a7713b1edbc 115 * be used for peripherals with 16bit access allowed.
AnnaBridge 171:3a7713b1edbc 116 * @param Reg Register to access.
AnnaBridge 171:3a7713b1edbc 117 * @param Bit Bit number to access.
AnnaBridge 171:3a7713b1edbc 118 * @return Value of the targeted bit in the bit band region.
AnnaBridge 171:3a7713b1edbc 119 */
AnnaBridge 171:3a7713b1edbc 120 #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
AnnaBridge 171:3a7713b1edbc 121 /**
AnnaBridge 171:3a7713b1edbc 122 * @brief Macro to access a single bit of a peripheral register (bit band region
AnnaBridge 171:3a7713b1edbc 123 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
AnnaBridge 171:3a7713b1edbc 124 * be used for peripherals with 8bit access allowed.
AnnaBridge 171:3a7713b1edbc 125 * @param Reg Register to access.
AnnaBridge 171:3a7713b1edbc 126 * @param Bit Bit number to access.
AnnaBridge 171:3a7713b1edbc 127 * @return Value of the targeted bit in the bit band region.
AnnaBridge 171:3a7713b1edbc 128 */
AnnaBridge 171:3a7713b1edbc 129 #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
AnnaBridge 171:3a7713b1edbc 130
AnnaBridge 171:3a7713b1edbc 131 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 132 -- Interrupt vector numbers
AnnaBridge 171:3a7713b1edbc 133 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 134
AnnaBridge 171:3a7713b1edbc 135 /*!
AnnaBridge 171:3a7713b1edbc 136 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
AnnaBridge 171:3a7713b1edbc 137 * @{
AnnaBridge 171:3a7713b1edbc 138 */
AnnaBridge 171:3a7713b1edbc 139
AnnaBridge 171:3a7713b1edbc 140 /** Interrupt Number Definitions */
AnnaBridge 171:3a7713b1edbc 141 #define NUMBER_OF_INT_VECTORS 116 /**< Number of interrupts in the Vector table */
AnnaBridge 171:3a7713b1edbc 142
AnnaBridge 171:3a7713b1edbc 143 typedef enum IRQn {
AnnaBridge 171:3a7713b1edbc 144 /* Auxiliary constants */
AnnaBridge 171:3a7713b1edbc 145 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
AnnaBridge 171:3a7713b1edbc 146
AnnaBridge 171:3a7713b1edbc 147 /* Core interrupts */
AnnaBridge 171:3a7713b1edbc 148 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 149 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 150 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
AnnaBridge 171:3a7713b1edbc 151 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 152 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 153 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 154 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
AnnaBridge 171:3a7713b1edbc 155 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 156 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 157
AnnaBridge 171:3a7713b1edbc 158 /* Device specific interrupts */
AnnaBridge 171:3a7713b1edbc 159 DMA0_DMA16_IRQn = 0, /**< DMA Channel 0, 16 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 160 DMA1_DMA17_IRQn = 1, /**< DMA Channel 1, 17 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 161 DMA2_DMA18_IRQn = 2, /**< DMA Channel 2, 18 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 162 DMA3_DMA19_IRQn = 3, /**< DMA Channel 3, 19 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 163 DMA4_DMA20_IRQn = 4, /**< DMA Channel 4, 20 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 164 DMA5_DMA21_IRQn = 5, /**< DMA Channel 5, 21 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 165 DMA6_DMA22_IRQn = 6, /**< DMA Channel 6, 22 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 166 DMA7_DMA23_IRQn = 7, /**< DMA Channel 7, 23 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 167 DMA8_DMA24_IRQn = 8, /**< DMA Channel 8, 24 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 168 DMA9_DMA25_IRQn = 9, /**< DMA Channel 9, 25 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 169 DMA10_DMA26_IRQn = 10, /**< DMA Channel 10, 26 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 170 DMA11_DMA27_IRQn = 11, /**< DMA Channel 11, 27 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 171 DMA12_DMA28_IRQn = 12, /**< DMA Channel 12, 28 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 172 DMA13_DMA29_IRQn = 13, /**< DMA Channel 13, 29 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 173 DMA14_DMA30_IRQn = 14, /**< DMA Channel 14, 30 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 174 DMA15_DMA31_IRQn = 15, /**< DMA Channel 15, 31 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 175 DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
AnnaBridge 171:3a7713b1edbc 176 MCM_IRQn = 17, /**< Normal Interrupt */
AnnaBridge 171:3a7713b1edbc 177 FTFE_IRQn = 18, /**< FTFE Command complete interrupt */
AnnaBridge 171:3a7713b1edbc 178 Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
AnnaBridge 171:3a7713b1edbc 179 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
AnnaBridge 171:3a7713b1edbc 180 LLWU_IRQn = 21, /**< Low Leakage Wakeup Unit */
AnnaBridge 171:3a7713b1edbc 181 WDOG_EWM_IRQn = 22, /**< WDOG Interrupt */
AnnaBridge 171:3a7713b1edbc 182 RNG_IRQn = 23, /**< RNG Interrupt */
AnnaBridge 171:3a7713b1edbc 183 I2C0_IRQn = 24, /**< I2C0 interrupt */
AnnaBridge 171:3a7713b1edbc 184 I2C1_IRQn = 25, /**< I2C1 interrupt */
AnnaBridge 171:3a7713b1edbc 185 SPI0_IRQn = 26, /**< SPI0 Interrupt */
AnnaBridge 171:3a7713b1edbc 186 SPI1_IRQn = 27, /**< SPI1 Interrupt */
AnnaBridge 171:3a7713b1edbc 187 I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
AnnaBridge 171:3a7713b1edbc 188 I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
AnnaBridge 171:3a7713b1edbc 189 Reserved46_IRQn = 30, /**< Reserved interrupt 46 */
AnnaBridge 171:3a7713b1edbc 190 UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
AnnaBridge 171:3a7713b1edbc 191 UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
AnnaBridge 171:3a7713b1edbc 192 UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
AnnaBridge 171:3a7713b1edbc 193 UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
AnnaBridge 171:3a7713b1edbc 194 UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
AnnaBridge 171:3a7713b1edbc 195 UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
AnnaBridge 171:3a7713b1edbc 196 UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */
AnnaBridge 171:3a7713b1edbc 197 UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */
AnnaBridge 171:3a7713b1edbc 198 ADC0_IRQn = 39, /**< ADC0 interrupt */
AnnaBridge 171:3a7713b1edbc 199 CMP0_IRQn = 40, /**< CMP0 interrupt */
AnnaBridge 171:3a7713b1edbc 200 CMP1_IRQn = 41, /**< CMP1 interrupt */
AnnaBridge 171:3a7713b1edbc 201 FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
AnnaBridge 171:3a7713b1edbc 202 FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
AnnaBridge 171:3a7713b1edbc 203 FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
AnnaBridge 171:3a7713b1edbc 204 CMT_IRQn = 45, /**< CMT interrupt */
AnnaBridge 171:3a7713b1edbc 205 RTC_IRQn = 46, /**< RTC interrupt */
AnnaBridge 171:3a7713b1edbc 206 RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
AnnaBridge 171:3a7713b1edbc 207 PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
AnnaBridge 171:3a7713b1edbc 208 PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
AnnaBridge 171:3a7713b1edbc 209 PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
AnnaBridge 171:3a7713b1edbc 210 PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
AnnaBridge 171:3a7713b1edbc 211 PDB0_IRQn = 52, /**< PDB0 Interrupt */
AnnaBridge 171:3a7713b1edbc 212 USB0_IRQn = 53, /**< USB0 interrupt */
AnnaBridge 171:3a7713b1edbc 213 USBDCD_IRQn = 54, /**< USBDCD Interrupt */
AnnaBridge 171:3a7713b1edbc 214 Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
AnnaBridge 171:3a7713b1edbc 215 DAC0_IRQn = 56, /**< DAC0 interrupt */
AnnaBridge 171:3a7713b1edbc 216 MCG_IRQn = 57, /**< MCG Interrupt */
AnnaBridge 171:3a7713b1edbc 217 LPTMR0_IRQn = 58, /**< LPTimer interrupt */
AnnaBridge 171:3a7713b1edbc 218 PORTA_IRQn = 59, /**< Port A interrupt */
AnnaBridge 171:3a7713b1edbc 219 PORTB_IRQn = 60, /**< Port B interrupt */
AnnaBridge 171:3a7713b1edbc 220 PORTC_IRQn = 61, /**< Port C interrupt */
AnnaBridge 171:3a7713b1edbc 221 PORTD_IRQn = 62, /**< Port D interrupt */
AnnaBridge 171:3a7713b1edbc 222 PORTE_IRQn = 63, /**< Port E interrupt */
AnnaBridge 171:3a7713b1edbc 223 SWI_IRQn = 64, /**< Software interrupt */
AnnaBridge 171:3a7713b1edbc 224 SPI2_IRQn = 65, /**< SPI2 Interrupt */
AnnaBridge 171:3a7713b1edbc 225 UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */
AnnaBridge 171:3a7713b1edbc 226 UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */
AnnaBridge 171:3a7713b1edbc 227 Reserved84_IRQn = 68, /**< Reserved interrupt 84 */
AnnaBridge 171:3a7713b1edbc 228 Reserved85_IRQn = 69, /**< Reserved interrupt 85 */
AnnaBridge 171:3a7713b1edbc 229 CMP2_IRQn = 70, /**< CMP2 interrupt */
AnnaBridge 171:3a7713b1edbc 230 FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
AnnaBridge 171:3a7713b1edbc 231 DAC1_IRQn = 72, /**< DAC1 interrupt */
AnnaBridge 171:3a7713b1edbc 232 ADC1_IRQn = 73, /**< ADC1 interrupt */
AnnaBridge 171:3a7713b1edbc 233 I2C2_IRQn = 74, /**< I2C2 interrupt */
AnnaBridge 171:3a7713b1edbc 234 CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */
AnnaBridge 171:3a7713b1edbc 235 CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */
AnnaBridge 171:3a7713b1edbc 236 CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */
AnnaBridge 171:3a7713b1edbc 237 CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */
AnnaBridge 171:3a7713b1edbc 238 CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */
AnnaBridge 171:3a7713b1edbc 239 CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */
AnnaBridge 171:3a7713b1edbc 240 SDHC_IRQn = 81, /**< SDHC interrupt */
AnnaBridge 171:3a7713b1edbc 241 ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */
AnnaBridge 171:3a7713b1edbc 242 ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */
AnnaBridge 171:3a7713b1edbc 243 ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */
AnnaBridge 171:3a7713b1edbc 244 ENET_Error_IRQn = 85, /**< Ethernet MAC Error and miscelaneous Interrupt */
AnnaBridge 171:3a7713b1edbc 245 LPUART0_IRQn = 86, /**< LPUART0 status/error interrupt */
AnnaBridge 171:3a7713b1edbc 246 TSI0_IRQn = 87, /**< TSI0 interrupt */
AnnaBridge 171:3a7713b1edbc 247 TPM1_IRQn = 88, /**< TPM1 fault, overflow and channels interrupt */
AnnaBridge 171:3a7713b1edbc 248 TPM2_IRQn = 89, /**< TPM2 fault, overflow and channels interrupt */
AnnaBridge 171:3a7713b1edbc 249 USBHSDCD_IRQn = 90, /**< USBHSDCD, USBHS Phy Interrupt */
AnnaBridge 171:3a7713b1edbc 250 I2C3_IRQn = 91, /**< I2C3 interrupt */
AnnaBridge 171:3a7713b1edbc 251 CMP3_IRQn = 92, /**< CMP3 interrupt */
AnnaBridge 171:3a7713b1edbc 252 USBHS_IRQn = 93, /**< USB high speed OTG interrupt */
AnnaBridge 171:3a7713b1edbc 253 CAN1_ORed_Message_buffer_IRQn = 94, /**< CAN1 OR'd message buffers interrupt */
AnnaBridge 171:3a7713b1edbc 254 CAN1_Bus_Off_IRQn = 95, /**< CAN1 bus off interrupt */
AnnaBridge 171:3a7713b1edbc 255 CAN1_Error_IRQn = 96, /**< CAN1 error interrupt */
AnnaBridge 171:3a7713b1edbc 256 CAN1_Tx_Warning_IRQn = 97, /**< CAN1 Tx warning interrupt */
AnnaBridge 171:3a7713b1edbc 257 CAN1_Rx_Warning_IRQn = 98, /**< CAN1 Rx warning interrupt */
AnnaBridge 171:3a7713b1edbc 258 CAN1_Wake_Up_IRQn = 99 /**< CAN1 wake up interrupt */
AnnaBridge 171:3a7713b1edbc 259 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 260
AnnaBridge 171:3a7713b1edbc 261 /*!
AnnaBridge 171:3a7713b1edbc 262 * @}
AnnaBridge 171:3a7713b1edbc 263 */ /* end of group Interrupt_vector_numbers */
AnnaBridge 171:3a7713b1edbc 264
AnnaBridge 171:3a7713b1edbc 265
AnnaBridge 171:3a7713b1edbc 266 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 267 -- Cortex M4 Core Configuration
AnnaBridge 171:3a7713b1edbc 268 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 269
AnnaBridge 171:3a7713b1edbc 270 /*!
AnnaBridge 171:3a7713b1edbc 271 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
AnnaBridge 171:3a7713b1edbc 272 * @{
AnnaBridge 171:3a7713b1edbc 273 */
AnnaBridge 171:3a7713b1edbc 274
AnnaBridge 171:3a7713b1edbc 275 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
AnnaBridge 171:3a7713b1edbc 276 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
AnnaBridge 171:3a7713b1edbc 277 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
AnnaBridge 171:3a7713b1edbc 278 #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
AnnaBridge 171:3a7713b1edbc 279
AnnaBridge 171:3a7713b1edbc 280 #include "core_cm4.h" /* Core Peripheral Access Layer */
AnnaBridge 171:3a7713b1edbc 281 #include "system_MK66F18.h" /* Device specific configuration file */
AnnaBridge 171:3a7713b1edbc 282
AnnaBridge 171:3a7713b1edbc 283 /*!
AnnaBridge 171:3a7713b1edbc 284 * @}
AnnaBridge 171:3a7713b1edbc 285 */ /* end of group Cortex_Core_Configuration */
AnnaBridge 171:3a7713b1edbc 286
AnnaBridge 171:3a7713b1edbc 287
AnnaBridge 171:3a7713b1edbc 288 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 289 -- Mapping Information
AnnaBridge 171:3a7713b1edbc 290 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 291
AnnaBridge 171:3a7713b1edbc 292 /*!
AnnaBridge 171:3a7713b1edbc 293 * @addtogroup Mapping_Information Mapping Information
AnnaBridge 171:3a7713b1edbc 294 * @{
AnnaBridge 171:3a7713b1edbc 295 */
AnnaBridge 171:3a7713b1edbc 296
AnnaBridge 171:3a7713b1edbc 297 /** Mapping Information */
AnnaBridge 171:3a7713b1edbc 298 /*!
AnnaBridge 171:3a7713b1edbc 299 * @addtogroup edma_request
AnnaBridge 171:3a7713b1edbc 300 * @{
AnnaBridge 171:3a7713b1edbc 301 */
AnnaBridge 171:3a7713b1edbc 302
AnnaBridge 171:3a7713b1edbc 303 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 304 * Definitions
AnnaBridge 171:3a7713b1edbc 305 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 306
AnnaBridge 171:3a7713b1edbc 307 /*!
AnnaBridge 171:3a7713b1edbc 308 * @brief Structure for the DMA hardware request
AnnaBridge 171:3a7713b1edbc 309 *
AnnaBridge 171:3a7713b1edbc 310 * Defines the structure for the DMA hardware request collections. The user can configure the
AnnaBridge 171:3a7713b1edbc 311 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
AnnaBridge 171:3a7713b1edbc 312 * of the hardware request varies according to the to SoC.
AnnaBridge 171:3a7713b1edbc 313 */
AnnaBridge 171:3a7713b1edbc 314 typedef enum _dma_request_source
AnnaBridge 171:3a7713b1edbc 315 {
AnnaBridge 171:3a7713b1edbc 316 kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
AnnaBridge 171:3a7713b1edbc 317 kDmaRequestMux0TSI0 = 1|0x100U, /**< TSI0. */
AnnaBridge 171:3a7713b1edbc 318 kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */
AnnaBridge 171:3a7713b1edbc 319 kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */
AnnaBridge 171:3a7713b1edbc 320 kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */
AnnaBridge 171:3a7713b1edbc 321 kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */
AnnaBridge 171:3a7713b1edbc 322 kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */
AnnaBridge 171:3a7713b1edbc 323 kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */
AnnaBridge 171:3a7713b1edbc 324 kDmaRequestMux0UART3Rx = 8|0x100U, /**< UART3 Receive. */
AnnaBridge 171:3a7713b1edbc 325 kDmaRequestMux0UART3Tx = 9|0x100U, /**< UART3 Transmit. */
AnnaBridge 171:3a7713b1edbc 326 kDmaRequestMux0UART4 = 10|0x100U, /**< UART4 Transmit or Receive. */
AnnaBridge 171:3a7713b1edbc 327 kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */
AnnaBridge 171:3a7713b1edbc 328 kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */
AnnaBridge 171:3a7713b1edbc 329 kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */
AnnaBridge 171:3a7713b1edbc 330 kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */
AnnaBridge 171:3a7713b1edbc 331 kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */
AnnaBridge 171:3a7713b1edbc 332 kDmaRequestMux0SPI1Rx = 16|0x100U, /**< SPI1 Receive. */
AnnaBridge 171:3a7713b1edbc 333 kDmaRequestMux0SPI1Tx = 17|0x100U, /**< SPI1 Transmit. */
AnnaBridge 171:3a7713b1edbc 334 kDmaRequestMux0I2C0I2C3 = 18|0x100U, /**< I2C0 and I2C3. */
AnnaBridge 171:3a7713b1edbc 335 kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0 and I2C3. */
AnnaBridge 171:3a7713b1edbc 336 kDmaRequestMux0I2C3 = 18|0x100U, /**< I2C0 and I2C3. */
AnnaBridge 171:3a7713b1edbc 337 kDmaRequestMux0I2C1I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
AnnaBridge 171:3a7713b1edbc 338 kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1 and I2C2. */
AnnaBridge 171:3a7713b1edbc 339 kDmaRequestMux0I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
AnnaBridge 171:3a7713b1edbc 340 kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */
AnnaBridge 171:3a7713b1edbc 341 kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */
AnnaBridge 171:3a7713b1edbc 342 kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */
AnnaBridge 171:3a7713b1edbc 343 kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */
AnnaBridge 171:3a7713b1edbc 344 kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */
AnnaBridge 171:3a7713b1edbc 345 kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */
AnnaBridge 171:3a7713b1edbc 346 kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */
AnnaBridge 171:3a7713b1edbc 347 kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */
AnnaBridge 171:3a7713b1edbc 348 kDmaRequestMux0FTM1TPM1Channel0 = 28|0x100U, /**< FTM1 C0V and TPM1 C0V. */
AnnaBridge 171:3a7713b1edbc 349 kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V and TPM1 C0V. */
AnnaBridge 171:3a7713b1edbc 350 kDmaRequestMux0TPM1Channel0 = 28|0x100U, /**< FTM1 C0V and TPM1 C0V. */
AnnaBridge 171:3a7713b1edbc 351 kDmaRequestMux0FTM1TPM1Channel1 = 29|0x100U, /**< FTM1 C1V and TPM1 C1V. */
AnnaBridge 171:3a7713b1edbc 352 kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V and TPM1 C1V. */
AnnaBridge 171:3a7713b1edbc 353 kDmaRequestMux0TPM1Channel1 = 29|0x100U, /**< FTM1 C1V and TPM1 C1V. */
AnnaBridge 171:3a7713b1edbc 354 kDmaRequestMux0FTM2TPM2Channel0 = 30|0x100U, /**< FTM2 C0V and TPM2 C0V. */
AnnaBridge 171:3a7713b1edbc 355 kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V and TPM2 C0V. */
AnnaBridge 171:3a7713b1edbc 356 kDmaRequestMux0TPM2Channel0 = 30|0x100U, /**< FTM2 C0V and TPM2 C0V. */
AnnaBridge 171:3a7713b1edbc 357 kDmaRequestMux0FTM2TPM2Channel1 = 31|0x100U, /**< FTM2 C1V and TPM2 C1V. */
AnnaBridge 171:3a7713b1edbc 358 kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V and TPM2 C1V. */
AnnaBridge 171:3a7713b1edbc 359 kDmaRequestMux0TPM2Channel1 = 31|0x100U, /**< FTM2 C1V and TPM2 C1V. */
AnnaBridge 171:3a7713b1edbc 360 kDmaRequestMux0FTM3Channel0 = 32|0x100U, /**< FTM3 C0V. */
AnnaBridge 171:3a7713b1edbc 361 kDmaRequestMux0FTM3Channel1 = 33|0x100U, /**< FTM3 C1V. */
AnnaBridge 171:3a7713b1edbc 362 kDmaRequestMux0FTM3Channel2 = 34|0x100U, /**< FTM3 C2V. */
AnnaBridge 171:3a7713b1edbc 363 kDmaRequestMux0FTM3Channel3 = 35|0x100U, /**< FTM3 C3V. */
AnnaBridge 171:3a7713b1edbc 364 kDmaRequestMux0FTM3Channel4 = 36|0x100U, /**< FTM3 C4V. */
AnnaBridge 171:3a7713b1edbc 365 kDmaRequestMux0FTM3Channel5 = 37|0x100U, /**< FTM3 C5V. */
AnnaBridge 171:3a7713b1edbc 366 kDmaRequestMux0FTM3Channel6SPI2Rx = 38|0x100U, /**< FTM3 C6V and SPI2 Receive. */
AnnaBridge 171:3a7713b1edbc 367 kDmaRequestMux0FTM3Channel6 = 38|0x100U, /**< FTM3 C6V and SPI2 Receive. */
AnnaBridge 171:3a7713b1edbc 368 kDmaRequestMux0SPI2Rx = 38|0x100U, /**< FTM3 C6V and SPI2 Receive. */
AnnaBridge 171:3a7713b1edbc 369 kDmaRequestMux0FTM3Channel7SPI2Tx = 39|0x100U, /**< FTM3 C7V and SPI2 Transmit. */
AnnaBridge 171:3a7713b1edbc 370 kDmaRequestMux0FTM3Channel7 = 39|0x100U, /**< FTM3 C7V and SPI2 Transmit. */
AnnaBridge 171:3a7713b1edbc 371 kDmaRequestMux0SPI2Tx = 39|0x100U, /**< FTM3 C7V and SPI2 Transmit. */
AnnaBridge 171:3a7713b1edbc 372 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
AnnaBridge 171:3a7713b1edbc 373 kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */
AnnaBridge 171:3a7713b1edbc 374 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
AnnaBridge 171:3a7713b1edbc 375 kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */
AnnaBridge 171:3a7713b1edbc 376 kDmaRequestMux0CMP2CMP3 = 44|0x100U, /**< CMP2 and CMP3. */
AnnaBridge 171:3a7713b1edbc 377 kDmaRequestMux0CMP2 = 44|0x100U, /**< CMP2 and CMP3. */
AnnaBridge 171:3a7713b1edbc 378 kDmaRequestMux0CMP3 = 44|0x100U, /**< CMP2 and CMP3. */
AnnaBridge 171:3a7713b1edbc 379 kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */
AnnaBridge 171:3a7713b1edbc 380 kDmaRequestMux0DAC1 = 46|0x100U, /**< DAC1. */
AnnaBridge 171:3a7713b1edbc 381 kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */
AnnaBridge 171:3a7713b1edbc 382 kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */
AnnaBridge 171:3a7713b1edbc 383 kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */
AnnaBridge 171:3a7713b1edbc 384 kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */
AnnaBridge 171:3a7713b1edbc 385 kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */
AnnaBridge 171:3a7713b1edbc 386 kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */
AnnaBridge 171:3a7713b1edbc 387 kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */
AnnaBridge 171:3a7713b1edbc 388 kDmaRequestMux0IEEE1588Timer0 = 54|0x100U, /**< ENET IEEE 1588 timer 0. */
AnnaBridge 171:3a7713b1edbc 389 kDmaRequestMux0IEEE1588Timer1TPM1Overflow = 55|0x100U, /**< ENET IEEE 1588 timer 1 and TPM1. */
AnnaBridge 171:3a7713b1edbc 390 kDmaRequestMux0IEEE1588Timer1 = 55|0x100U, /**< ENET IEEE 1588 timer 1 and TPM1. */
AnnaBridge 171:3a7713b1edbc 391 kDmaRequestMux0TPM1Overflow = 55|0x100U, /**< ENET IEEE 1588 timer 1 and TPM1. */
AnnaBridge 171:3a7713b1edbc 392 kDmaRequestMux0IEEE1588Timer2TPM2Overflow = 56|0x100U, /**< ENET IEEE 1588 timer 2 and TPM2. */
AnnaBridge 171:3a7713b1edbc 393 kDmaRequestMux0IEEE1588Timer2 = 56|0x100U, /**< ENET IEEE 1588 timer 2 and TPM2. */
AnnaBridge 171:3a7713b1edbc 394 kDmaRequestMux0TPM2Overflow = 56|0x100U, /**< ENET IEEE 1588 timer 2 and TPM2. */
AnnaBridge 171:3a7713b1edbc 395 kDmaRequestMux0IEEE1588Timer3 = 57|0x100U, /**< ENET IEEE 1588 timer 3. */
AnnaBridge 171:3a7713b1edbc 396 kDmaRequestMux0LPUART0Rx = 58|0x100U, /**< LPUART0 Receive. */
AnnaBridge 171:3a7713b1edbc 397 kDmaRequestMux0LPUART0Tx = 59|0x100U, /**< LPUART0 Transmit. */
AnnaBridge 171:3a7713b1edbc 398 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 399 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 400 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 401 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 402 } dma_request_source_t;
AnnaBridge 171:3a7713b1edbc 403
AnnaBridge 171:3a7713b1edbc 404 /* @} */
AnnaBridge 171:3a7713b1edbc 405
AnnaBridge 171:3a7713b1edbc 406
AnnaBridge 171:3a7713b1edbc 407 /*!
AnnaBridge 171:3a7713b1edbc 408 * @}
AnnaBridge 171:3a7713b1edbc 409 */ /* end of group Mapping_Information */
AnnaBridge 171:3a7713b1edbc 410
AnnaBridge 171:3a7713b1edbc 411
AnnaBridge 171:3a7713b1edbc 412 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 413 -- Device Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 414 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 415
AnnaBridge 171:3a7713b1edbc 416 /*!
AnnaBridge 171:3a7713b1edbc 417 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 418 * @{
AnnaBridge 171:3a7713b1edbc 419 */
AnnaBridge 171:3a7713b1edbc 420
AnnaBridge 171:3a7713b1edbc 421
AnnaBridge 171:3a7713b1edbc 422 /*
AnnaBridge 171:3a7713b1edbc 423 ** Start of section using anonymous unions
AnnaBridge 171:3a7713b1edbc 424 */
AnnaBridge 171:3a7713b1edbc 425
AnnaBridge 171:3a7713b1edbc 426 #if defined(__ARMCC_VERSION)
AnnaBridge 171:3a7713b1edbc 427 #pragma push
AnnaBridge 171:3a7713b1edbc 428 #pragma anon_unions
AnnaBridge 171:3a7713b1edbc 429 #elif defined(__CWCC__)
AnnaBridge 171:3a7713b1edbc 430 #pragma push
AnnaBridge 171:3a7713b1edbc 431 #pragma cpp_extensions on
AnnaBridge 171:3a7713b1edbc 432 #elif defined(__GNUC__)
AnnaBridge 171:3a7713b1edbc 433 /* anonymous unions are enabled by default */
AnnaBridge 171:3a7713b1edbc 434 #elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge 171:3a7713b1edbc 435 #pragma language=extended
AnnaBridge 171:3a7713b1edbc 436 #else
AnnaBridge 171:3a7713b1edbc 437 #error Not supported compiler type
AnnaBridge 171:3a7713b1edbc 438 #endif
AnnaBridge 171:3a7713b1edbc 439
AnnaBridge 171:3a7713b1edbc 440 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 441 -- ADC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 442 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 443
AnnaBridge 171:3a7713b1edbc 444 /*!
AnnaBridge 171:3a7713b1edbc 445 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 446 * @{
AnnaBridge 171:3a7713b1edbc 447 */
AnnaBridge 171:3a7713b1edbc 448
AnnaBridge 171:3a7713b1edbc 449 /** ADC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 450 typedef struct {
AnnaBridge 171:3a7713b1edbc 451 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 452 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 453 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 454 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 455 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 456 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 457 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 458 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 459 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 460 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 461 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 462 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 463 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 464 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 465 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 466 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 467 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 468 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 469 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 470 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 471 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 472 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 473 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 474 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 475 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 476 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 477 } ADC_Type;
AnnaBridge 171:3a7713b1edbc 478
AnnaBridge 171:3a7713b1edbc 479 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 480 -- ADC Register Masks
AnnaBridge 171:3a7713b1edbc 481 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 482
AnnaBridge 171:3a7713b1edbc 483 /*!
AnnaBridge 171:3a7713b1edbc 484 * @addtogroup ADC_Register_Masks ADC Register Masks
AnnaBridge 171:3a7713b1edbc 485 * @{
AnnaBridge 171:3a7713b1edbc 486 */
AnnaBridge 171:3a7713b1edbc 487
AnnaBridge 171:3a7713b1edbc 488 /*! @name SC1 - ADC Status and Control Registers 1 */
AnnaBridge 171:3a7713b1edbc 489 #define ADC_SC1_ADCH_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 490 #define ADC_SC1_ADCH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 491 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
AnnaBridge 171:3a7713b1edbc 492 #define ADC_SC1_DIFF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 493 #define ADC_SC1_DIFF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 494 #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
AnnaBridge 171:3a7713b1edbc 495 #define ADC_SC1_AIEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 496 #define ADC_SC1_AIEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 497 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
AnnaBridge 171:3a7713b1edbc 498 #define ADC_SC1_COCO_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 499 #define ADC_SC1_COCO_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 500 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
AnnaBridge 171:3a7713b1edbc 501
AnnaBridge 171:3a7713b1edbc 502 /* The count of ADC_SC1 */
AnnaBridge 171:3a7713b1edbc 503 #define ADC_SC1_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 504
AnnaBridge 171:3a7713b1edbc 505 /*! @name CFG1 - ADC Configuration Register 1 */
AnnaBridge 171:3a7713b1edbc 506 #define ADC_CFG1_ADICLK_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 507 #define ADC_CFG1_ADICLK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 508 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
AnnaBridge 171:3a7713b1edbc 509 #define ADC_CFG1_MODE_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 510 #define ADC_CFG1_MODE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 511 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 512 #define ADC_CFG1_ADLSMP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 513 #define ADC_CFG1_ADLSMP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 514 #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
AnnaBridge 171:3a7713b1edbc 515 #define ADC_CFG1_ADIV_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 516 #define ADC_CFG1_ADIV_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 517 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
AnnaBridge 171:3a7713b1edbc 518 #define ADC_CFG1_ADLPC_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 519 #define ADC_CFG1_ADLPC_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 520 #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
AnnaBridge 171:3a7713b1edbc 521
AnnaBridge 171:3a7713b1edbc 522 /*! @name CFG2 - ADC Configuration Register 2 */
AnnaBridge 171:3a7713b1edbc 523 #define ADC_CFG2_ADLSTS_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 524 #define ADC_CFG2_ADLSTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 525 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
AnnaBridge 171:3a7713b1edbc 526 #define ADC_CFG2_ADHSC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 527 #define ADC_CFG2_ADHSC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 528 #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
AnnaBridge 171:3a7713b1edbc 529 #define ADC_CFG2_ADACKEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 530 #define ADC_CFG2_ADACKEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 531 #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
AnnaBridge 171:3a7713b1edbc 532 #define ADC_CFG2_MUXSEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 533 #define ADC_CFG2_MUXSEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 534 #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
AnnaBridge 171:3a7713b1edbc 535
AnnaBridge 171:3a7713b1edbc 536 /*! @name R - ADC Data Result Register */
AnnaBridge 171:3a7713b1edbc 537 #define ADC_R_D_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 538 #define ADC_R_D_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 539 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
AnnaBridge 171:3a7713b1edbc 540
AnnaBridge 171:3a7713b1edbc 541 /* The count of ADC_R */
AnnaBridge 171:3a7713b1edbc 542 #define ADC_R_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 543
AnnaBridge 171:3a7713b1edbc 544 /*! @name CV1 - Compare Value Registers */
AnnaBridge 171:3a7713b1edbc 545 #define ADC_CV1_CV_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 546 #define ADC_CV1_CV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 547 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
AnnaBridge 171:3a7713b1edbc 548
AnnaBridge 171:3a7713b1edbc 549 /*! @name CV2 - Compare Value Registers */
AnnaBridge 171:3a7713b1edbc 550 #define ADC_CV2_CV_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 551 #define ADC_CV2_CV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 552 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
AnnaBridge 171:3a7713b1edbc 553
AnnaBridge 171:3a7713b1edbc 554 /*! @name SC2 - Status and Control Register 2 */
AnnaBridge 171:3a7713b1edbc 555 #define ADC_SC2_REFSEL_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 556 #define ADC_SC2_REFSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 557 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
AnnaBridge 171:3a7713b1edbc 558 #define ADC_SC2_DMAEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 559 #define ADC_SC2_DMAEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 560 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 561 #define ADC_SC2_ACREN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 562 #define ADC_SC2_ACREN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 563 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
AnnaBridge 171:3a7713b1edbc 564 #define ADC_SC2_ACFGT_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 565 #define ADC_SC2_ACFGT_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 566 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
AnnaBridge 171:3a7713b1edbc 567 #define ADC_SC2_ACFE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 568 #define ADC_SC2_ACFE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 569 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
AnnaBridge 171:3a7713b1edbc 570 #define ADC_SC2_ADTRG_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 571 #define ADC_SC2_ADTRG_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 572 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
AnnaBridge 171:3a7713b1edbc 573 #define ADC_SC2_ADACT_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 574 #define ADC_SC2_ADACT_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 575 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
AnnaBridge 171:3a7713b1edbc 576
AnnaBridge 171:3a7713b1edbc 577 /*! @name SC3 - Status and Control Register 3 */
AnnaBridge 171:3a7713b1edbc 578 #define ADC_SC3_AVGS_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 579 #define ADC_SC3_AVGS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 580 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
AnnaBridge 171:3a7713b1edbc 581 #define ADC_SC3_AVGE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 582 #define ADC_SC3_AVGE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 583 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
AnnaBridge 171:3a7713b1edbc 584 #define ADC_SC3_ADCO_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 585 #define ADC_SC3_ADCO_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 586 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
AnnaBridge 171:3a7713b1edbc 587 #define ADC_SC3_CALF_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 588 #define ADC_SC3_CALF_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 589 #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
AnnaBridge 171:3a7713b1edbc 590 #define ADC_SC3_CAL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 591 #define ADC_SC3_CAL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 592 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
AnnaBridge 171:3a7713b1edbc 593
AnnaBridge 171:3a7713b1edbc 594 /*! @name OFS - ADC Offset Correction Register */
AnnaBridge 171:3a7713b1edbc 595 #define ADC_OFS_OFS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 596 #define ADC_OFS_OFS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 597 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
AnnaBridge 171:3a7713b1edbc 598
AnnaBridge 171:3a7713b1edbc 599 /*! @name PG - ADC Plus-Side Gain Register */
AnnaBridge 171:3a7713b1edbc 600 #define ADC_PG_PG_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 601 #define ADC_PG_PG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 602 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
AnnaBridge 171:3a7713b1edbc 603
AnnaBridge 171:3a7713b1edbc 604 /*! @name MG - ADC Minus-Side Gain Register */
AnnaBridge 171:3a7713b1edbc 605 #define ADC_MG_MG_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 606 #define ADC_MG_MG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 607 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
AnnaBridge 171:3a7713b1edbc 608
AnnaBridge 171:3a7713b1edbc 609 /*! @name CLPD - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 610 #define ADC_CLPD_CLPD_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 611 #define ADC_CLPD_CLPD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 612 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
AnnaBridge 171:3a7713b1edbc 613
AnnaBridge 171:3a7713b1edbc 614 /*! @name CLPS - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 615 #define ADC_CLPS_CLPS_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 616 #define ADC_CLPS_CLPS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 617 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
AnnaBridge 171:3a7713b1edbc 618
AnnaBridge 171:3a7713b1edbc 619 /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 620 #define ADC_CLP4_CLP4_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 621 #define ADC_CLP4_CLP4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 622 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
AnnaBridge 171:3a7713b1edbc 623
AnnaBridge 171:3a7713b1edbc 624 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 625 #define ADC_CLP3_CLP3_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 626 #define ADC_CLP3_CLP3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 627 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
AnnaBridge 171:3a7713b1edbc 628
AnnaBridge 171:3a7713b1edbc 629 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 630 #define ADC_CLP2_CLP2_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 631 #define ADC_CLP2_CLP2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 632 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
AnnaBridge 171:3a7713b1edbc 633
AnnaBridge 171:3a7713b1edbc 634 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 635 #define ADC_CLP1_CLP1_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 636 #define ADC_CLP1_CLP1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 637 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
AnnaBridge 171:3a7713b1edbc 638
AnnaBridge 171:3a7713b1edbc 639 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 640 #define ADC_CLP0_CLP0_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 641 #define ADC_CLP0_CLP0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 642 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
AnnaBridge 171:3a7713b1edbc 643
AnnaBridge 171:3a7713b1edbc 644 /*! @name CLMD - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 645 #define ADC_CLMD_CLMD_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 646 #define ADC_CLMD_CLMD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 647 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
AnnaBridge 171:3a7713b1edbc 648
AnnaBridge 171:3a7713b1edbc 649 /*! @name CLMS - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 650 #define ADC_CLMS_CLMS_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 651 #define ADC_CLMS_CLMS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 652 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
AnnaBridge 171:3a7713b1edbc 653
AnnaBridge 171:3a7713b1edbc 654 /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 655 #define ADC_CLM4_CLM4_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 656 #define ADC_CLM4_CLM4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 657 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
AnnaBridge 171:3a7713b1edbc 658
AnnaBridge 171:3a7713b1edbc 659 /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 660 #define ADC_CLM3_CLM3_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 661 #define ADC_CLM3_CLM3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 662 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
AnnaBridge 171:3a7713b1edbc 663
AnnaBridge 171:3a7713b1edbc 664 /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 665 #define ADC_CLM2_CLM2_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 666 #define ADC_CLM2_CLM2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 667 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
AnnaBridge 171:3a7713b1edbc 668
AnnaBridge 171:3a7713b1edbc 669 /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 670 #define ADC_CLM1_CLM1_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 671 #define ADC_CLM1_CLM1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 672 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
AnnaBridge 171:3a7713b1edbc 673
AnnaBridge 171:3a7713b1edbc 674 /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 675 #define ADC_CLM0_CLM0_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 676 #define ADC_CLM0_CLM0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 677 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
AnnaBridge 171:3a7713b1edbc 678
AnnaBridge 171:3a7713b1edbc 679
AnnaBridge 171:3a7713b1edbc 680 /*!
AnnaBridge 171:3a7713b1edbc 681 * @}
AnnaBridge 171:3a7713b1edbc 682 */ /* end of group ADC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 683
AnnaBridge 171:3a7713b1edbc 684
AnnaBridge 171:3a7713b1edbc 685 /* ADC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 686 /** Peripheral ADC0 base address */
AnnaBridge 171:3a7713b1edbc 687 #define ADC0_BASE (0x4003B000u)
AnnaBridge 171:3a7713b1edbc 688 /** Peripheral ADC0 base pointer */
AnnaBridge 171:3a7713b1edbc 689 #define ADC0 ((ADC_Type *)ADC0_BASE)
AnnaBridge 171:3a7713b1edbc 690 /** Peripheral ADC1 base address */
AnnaBridge 171:3a7713b1edbc 691 #define ADC1_BASE (0x400BB000u)
AnnaBridge 171:3a7713b1edbc 692 /** Peripheral ADC1 base pointer */
AnnaBridge 171:3a7713b1edbc 693 #define ADC1 ((ADC_Type *)ADC1_BASE)
AnnaBridge 171:3a7713b1edbc 694 /** Array initializer of ADC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 695 #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
AnnaBridge 171:3a7713b1edbc 696 /** Array initializer of ADC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 697 #define ADC_BASE_PTRS { ADC0, ADC1 }
AnnaBridge 171:3a7713b1edbc 698 /** Interrupt vectors for the ADC peripheral type */
AnnaBridge 171:3a7713b1edbc 699 #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
AnnaBridge 171:3a7713b1edbc 700
AnnaBridge 171:3a7713b1edbc 701 /*!
AnnaBridge 171:3a7713b1edbc 702 * @}
AnnaBridge 171:3a7713b1edbc 703 */ /* end of group ADC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 704
AnnaBridge 171:3a7713b1edbc 705
AnnaBridge 171:3a7713b1edbc 706 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 707 -- AIPS Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 708 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 709
AnnaBridge 171:3a7713b1edbc 710 /*!
AnnaBridge 171:3a7713b1edbc 711 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 712 * @{
AnnaBridge 171:3a7713b1edbc 713 */
AnnaBridge 171:3a7713b1edbc 714
AnnaBridge 171:3a7713b1edbc 715 /** AIPS - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 716 typedef struct {
AnnaBridge 171:3a7713b1edbc 717 __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 718 uint8_t RESERVED_0[28];
AnnaBridge 171:3a7713b1edbc 719 __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 720 __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 721 __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 722 __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 723 uint8_t RESERVED_1[16];
AnnaBridge 171:3a7713b1edbc 724 __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 725 __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 726 __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 727 __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 728 __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 729 __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 730 __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 731 __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 732 __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 733 __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 734 __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 735 __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 736 } AIPS_Type;
AnnaBridge 171:3a7713b1edbc 737
AnnaBridge 171:3a7713b1edbc 738 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 739 -- AIPS Register Masks
AnnaBridge 171:3a7713b1edbc 740 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 741
AnnaBridge 171:3a7713b1edbc 742 /*!
AnnaBridge 171:3a7713b1edbc 743 * @addtogroup AIPS_Register_Masks AIPS Register Masks
AnnaBridge 171:3a7713b1edbc 744 * @{
AnnaBridge 171:3a7713b1edbc 745 */
AnnaBridge 171:3a7713b1edbc 746
AnnaBridge 171:3a7713b1edbc 747 /*! @name MPRA - Master Privilege Register A */
AnnaBridge 171:3a7713b1edbc 748 #define AIPS_MPRA_MPL6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 749 #define AIPS_MPRA_MPL6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 750 #define AIPS_MPRA_MPL6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL6_SHIFT)) & AIPS_MPRA_MPL6_MASK)
AnnaBridge 171:3a7713b1edbc 751 #define AIPS_MPRA_MTW6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 752 #define AIPS_MPRA_MTW6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 753 #define AIPS_MPRA_MTW6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW6_SHIFT)) & AIPS_MPRA_MTW6_MASK)
AnnaBridge 171:3a7713b1edbc 754 #define AIPS_MPRA_MTR6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 755 #define AIPS_MPRA_MTR6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 756 #define AIPS_MPRA_MTR6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR6_SHIFT)) & AIPS_MPRA_MTR6_MASK)
AnnaBridge 171:3a7713b1edbc 757 #define AIPS_MPRA_MPL5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 758 #define AIPS_MPRA_MPL5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 759 #define AIPS_MPRA_MPL5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)
AnnaBridge 171:3a7713b1edbc 760 #define AIPS_MPRA_MTW5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 761 #define AIPS_MPRA_MTW5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 762 #define AIPS_MPRA_MTW5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)
AnnaBridge 171:3a7713b1edbc 763 #define AIPS_MPRA_MTR5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 764 #define AIPS_MPRA_MTR5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 765 #define AIPS_MPRA_MTR5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)
AnnaBridge 171:3a7713b1edbc 766 #define AIPS_MPRA_MPL4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 767 #define AIPS_MPRA_MPL4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 768 #define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
AnnaBridge 171:3a7713b1edbc 769 #define AIPS_MPRA_MTW4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 770 #define AIPS_MPRA_MTW4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 771 #define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
AnnaBridge 171:3a7713b1edbc 772 #define AIPS_MPRA_MTR4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 773 #define AIPS_MPRA_MTR4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 774 #define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
AnnaBridge 171:3a7713b1edbc 775 #define AIPS_MPRA_MPL3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 776 #define AIPS_MPRA_MPL3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 777 #define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
AnnaBridge 171:3a7713b1edbc 778 #define AIPS_MPRA_MTW3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 779 #define AIPS_MPRA_MTW3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 780 #define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
AnnaBridge 171:3a7713b1edbc 781 #define AIPS_MPRA_MTR3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 782 #define AIPS_MPRA_MTR3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 783 #define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
AnnaBridge 171:3a7713b1edbc 784 #define AIPS_MPRA_MPL2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 785 #define AIPS_MPRA_MPL2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 786 #define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
AnnaBridge 171:3a7713b1edbc 787 #define AIPS_MPRA_MTW2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 788 #define AIPS_MPRA_MTW2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 789 #define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
AnnaBridge 171:3a7713b1edbc 790 #define AIPS_MPRA_MTR2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 791 #define AIPS_MPRA_MTR2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 792 #define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
AnnaBridge 171:3a7713b1edbc 793 #define AIPS_MPRA_MPL1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 794 #define AIPS_MPRA_MPL1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 795 #define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
AnnaBridge 171:3a7713b1edbc 796 #define AIPS_MPRA_MTW1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 797 #define AIPS_MPRA_MTW1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 798 #define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
AnnaBridge 171:3a7713b1edbc 799 #define AIPS_MPRA_MTR1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 800 #define AIPS_MPRA_MTR1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 801 #define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
AnnaBridge 171:3a7713b1edbc 802 #define AIPS_MPRA_MPL0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 803 #define AIPS_MPRA_MPL0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 804 #define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
AnnaBridge 171:3a7713b1edbc 805 #define AIPS_MPRA_MTW0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 806 #define AIPS_MPRA_MTW0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 807 #define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
AnnaBridge 171:3a7713b1edbc 808 #define AIPS_MPRA_MTR0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 809 #define AIPS_MPRA_MTR0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 810 #define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
AnnaBridge 171:3a7713b1edbc 811
AnnaBridge 171:3a7713b1edbc 812 /*! @name PACRA - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 813 #define AIPS_PACRA_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 814 #define AIPS_PACRA_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 815 #define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 816 #define AIPS_PACRA_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 817 #define AIPS_PACRA_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 818 #define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 819 #define AIPS_PACRA_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 820 #define AIPS_PACRA_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 821 #define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 822 #define AIPS_PACRA_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 823 #define AIPS_PACRA_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 824 #define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 825 #define AIPS_PACRA_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 826 #define AIPS_PACRA_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 827 #define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 828 #define AIPS_PACRA_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 829 #define AIPS_PACRA_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 830 #define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 831 #define AIPS_PACRA_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 832 #define AIPS_PACRA_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 833 #define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 834 #define AIPS_PACRA_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 835 #define AIPS_PACRA_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 836 #define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 837 #define AIPS_PACRA_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 838 #define AIPS_PACRA_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 839 #define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 840 #define AIPS_PACRA_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 841 #define AIPS_PACRA_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 842 #define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 843 #define AIPS_PACRA_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 844 #define AIPS_PACRA_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 845 #define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 846 #define AIPS_PACRA_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 847 #define AIPS_PACRA_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 848 #define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 849 #define AIPS_PACRA_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 850 #define AIPS_PACRA_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 851 #define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 852 #define AIPS_PACRA_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 853 #define AIPS_PACRA_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 854 #define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 855 #define AIPS_PACRA_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 856 #define AIPS_PACRA_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 857 #define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 858 #define AIPS_PACRA_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 859 #define AIPS_PACRA_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 860 #define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 861 #define AIPS_PACRA_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 862 #define AIPS_PACRA_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 863 #define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 864 #define AIPS_PACRA_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 865 #define AIPS_PACRA_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 866 #define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 867 #define AIPS_PACRA_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 868 #define AIPS_PACRA_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 869 #define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 870 #define AIPS_PACRA_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 871 #define AIPS_PACRA_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 872 #define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 873 #define AIPS_PACRA_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 874 #define AIPS_PACRA_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 875 #define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 876 #define AIPS_PACRA_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 877 #define AIPS_PACRA_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 878 #define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 879 #define AIPS_PACRA_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 880 #define AIPS_PACRA_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 881 #define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 882 #define AIPS_PACRA_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 883 #define AIPS_PACRA_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 884 #define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 885
AnnaBridge 171:3a7713b1edbc 886 /*! @name PACRB - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 887 #define AIPS_PACRB_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 888 #define AIPS_PACRB_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 889 #define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 890 #define AIPS_PACRB_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 891 #define AIPS_PACRB_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 892 #define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 893 #define AIPS_PACRB_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 894 #define AIPS_PACRB_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 895 #define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 896 #define AIPS_PACRB_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 897 #define AIPS_PACRB_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 898 #define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 899 #define AIPS_PACRB_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 900 #define AIPS_PACRB_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 901 #define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 902 #define AIPS_PACRB_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 903 #define AIPS_PACRB_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 904 #define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 905 #define AIPS_PACRB_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 906 #define AIPS_PACRB_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 907 #define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 908 #define AIPS_PACRB_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 909 #define AIPS_PACRB_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 910 #define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 911 #define AIPS_PACRB_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 912 #define AIPS_PACRB_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 913 #define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 914 #define AIPS_PACRB_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 915 #define AIPS_PACRB_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 916 #define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 917 #define AIPS_PACRB_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 918 #define AIPS_PACRB_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 919 #define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 920 #define AIPS_PACRB_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 921 #define AIPS_PACRB_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 922 #define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 923 #define AIPS_PACRB_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 924 #define AIPS_PACRB_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 925 #define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 926 #define AIPS_PACRB_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 927 #define AIPS_PACRB_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 928 #define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 929 #define AIPS_PACRB_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 930 #define AIPS_PACRB_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 931 #define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 932 #define AIPS_PACRB_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 933 #define AIPS_PACRB_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 934 #define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 935 #define AIPS_PACRB_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 936 #define AIPS_PACRB_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 937 #define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 938 #define AIPS_PACRB_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 939 #define AIPS_PACRB_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 940 #define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 941 #define AIPS_PACRB_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 942 #define AIPS_PACRB_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 943 #define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 944 #define AIPS_PACRB_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 945 #define AIPS_PACRB_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 946 #define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 947 #define AIPS_PACRB_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 948 #define AIPS_PACRB_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 949 #define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 950 #define AIPS_PACRB_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 951 #define AIPS_PACRB_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 952 #define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 953 #define AIPS_PACRB_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 954 #define AIPS_PACRB_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 955 #define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 956 #define AIPS_PACRB_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 957 #define AIPS_PACRB_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 958 #define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 959
AnnaBridge 171:3a7713b1edbc 960 /*! @name PACRC - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 961 #define AIPS_PACRC_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 962 #define AIPS_PACRC_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 963 #define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 964 #define AIPS_PACRC_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 965 #define AIPS_PACRC_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 966 #define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 967 #define AIPS_PACRC_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 968 #define AIPS_PACRC_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 969 #define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 970 #define AIPS_PACRC_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 971 #define AIPS_PACRC_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 972 #define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 973 #define AIPS_PACRC_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 974 #define AIPS_PACRC_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 975 #define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 976 #define AIPS_PACRC_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 977 #define AIPS_PACRC_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 978 #define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 979 #define AIPS_PACRC_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 980 #define AIPS_PACRC_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 981 #define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 982 #define AIPS_PACRC_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 983 #define AIPS_PACRC_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 984 #define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 985 #define AIPS_PACRC_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 986 #define AIPS_PACRC_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 987 #define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 988 #define AIPS_PACRC_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 989 #define AIPS_PACRC_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 990 #define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 991 #define AIPS_PACRC_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 992 #define AIPS_PACRC_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 993 #define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 994 #define AIPS_PACRC_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 995 #define AIPS_PACRC_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 996 #define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 997 #define AIPS_PACRC_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 998 #define AIPS_PACRC_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 999 #define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1000 #define AIPS_PACRC_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1001 #define AIPS_PACRC_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1002 #define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1003 #define AIPS_PACRC_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1004 #define AIPS_PACRC_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1005 #define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1006 #define AIPS_PACRC_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1007 #define AIPS_PACRC_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1008 #define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1009 #define AIPS_PACRC_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1010 #define AIPS_PACRC_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1011 #define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1012 #define AIPS_PACRC_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1013 #define AIPS_PACRC_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1014 #define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1015 #define AIPS_PACRC_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1016 #define AIPS_PACRC_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1017 #define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1018 #define AIPS_PACRC_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1019 #define AIPS_PACRC_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1020 #define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1021 #define AIPS_PACRC_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1022 #define AIPS_PACRC_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1023 #define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1024 #define AIPS_PACRC_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1025 #define AIPS_PACRC_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1026 #define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1027 #define AIPS_PACRC_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1028 #define AIPS_PACRC_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1029 #define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1030 #define AIPS_PACRC_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1031 #define AIPS_PACRC_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1032 #define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1033
AnnaBridge 171:3a7713b1edbc 1034 /*! @name PACRD - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1035 #define AIPS_PACRD_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1036 #define AIPS_PACRD_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1037 #define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1038 #define AIPS_PACRD_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1039 #define AIPS_PACRD_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1040 #define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1041 #define AIPS_PACRD_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1042 #define AIPS_PACRD_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1043 #define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1044 #define AIPS_PACRD_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1045 #define AIPS_PACRD_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1046 #define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1047 #define AIPS_PACRD_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1048 #define AIPS_PACRD_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1049 #define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1050 #define AIPS_PACRD_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1051 #define AIPS_PACRD_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1052 #define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1053 #define AIPS_PACRD_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1054 #define AIPS_PACRD_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1055 #define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1056 #define AIPS_PACRD_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1057 #define AIPS_PACRD_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1058 #define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1059 #define AIPS_PACRD_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1060 #define AIPS_PACRD_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1061 #define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1062 #define AIPS_PACRD_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1063 #define AIPS_PACRD_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1064 #define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1065 #define AIPS_PACRD_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1066 #define AIPS_PACRD_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1067 #define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1068 #define AIPS_PACRD_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1069 #define AIPS_PACRD_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1070 #define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1071 #define AIPS_PACRD_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1072 #define AIPS_PACRD_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1073 #define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1074 #define AIPS_PACRD_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1075 #define AIPS_PACRD_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1076 #define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1077 #define AIPS_PACRD_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1078 #define AIPS_PACRD_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1079 #define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1080 #define AIPS_PACRD_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1081 #define AIPS_PACRD_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1082 #define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1083 #define AIPS_PACRD_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1084 #define AIPS_PACRD_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1085 #define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1086 #define AIPS_PACRD_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1087 #define AIPS_PACRD_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1088 #define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1089 #define AIPS_PACRD_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1090 #define AIPS_PACRD_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1091 #define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1092 #define AIPS_PACRD_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1093 #define AIPS_PACRD_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1094 #define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1095 #define AIPS_PACRD_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1096 #define AIPS_PACRD_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1097 #define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1098 #define AIPS_PACRD_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1099 #define AIPS_PACRD_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1100 #define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1101 #define AIPS_PACRD_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1102 #define AIPS_PACRD_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1103 #define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1104 #define AIPS_PACRD_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1105 #define AIPS_PACRD_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1106 #define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1107
AnnaBridge 171:3a7713b1edbc 1108 /*! @name PACRE - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1109 #define AIPS_PACRE_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1110 #define AIPS_PACRE_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1111 #define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1112 #define AIPS_PACRE_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1113 #define AIPS_PACRE_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1114 #define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1115 #define AIPS_PACRE_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1116 #define AIPS_PACRE_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1117 #define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1118 #define AIPS_PACRE_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1119 #define AIPS_PACRE_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1120 #define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1121 #define AIPS_PACRE_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1122 #define AIPS_PACRE_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1123 #define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1124 #define AIPS_PACRE_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1125 #define AIPS_PACRE_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1126 #define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1127 #define AIPS_PACRE_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1128 #define AIPS_PACRE_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1129 #define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1130 #define AIPS_PACRE_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1131 #define AIPS_PACRE_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1132 #define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1133 #define AIPS_PACRE_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1134 #define AIPS_PACRE_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1135 #define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1136 #define AIPS_PACRE_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1137 #define AIPS_PACRE_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1138 #define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1139 #define AIPS_PACRE_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1140 #define AIPS_PACRE_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1141 #define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1142 #define AIPS_PACRE_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1143 #define AIPS_PACRE_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1144 #define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1145 #define AIPS_PACRE_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1146 #define AIPS_PACRE_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1147 #define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1148 #define AIPS_PACRE_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1149 #define AIPS_PACRE_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1150 #define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1151 #define AIPS_PACRE_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1152 #define AIPS_PACRE_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1153 #define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1154 #define AIPS_PACRE_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1155 #define AIPS_PACRE_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1156 #define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1157 #define AIPS_PACRE_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1158 #define AIPS_PACRE_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1159 #define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1160 #define AIPS_PACRE_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1161 #define AIPS_PACRE_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1162 #define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1163 #define AIPS_PACRE_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1164 #define AIPS_PACRE_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1165 #define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1166 #define AIPS_PACRE_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1167 #define AIPS_PACRE_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1168 #define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1169 #define AIPS_PACRE_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1170 #define AIPS_PACRE_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1171 #define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1172 #define AIPS_PACRE_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1173 #define AIPS_PACRE_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1174 #define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1175 #define AIPS_PACRE_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1176 #define AIPS_PACRE_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1177 #define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1178 #define AIPS_PACRE_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1179 #define AIPS_PACRE_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1180 #define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1181
AnnaBridge 171:3a7713b1edbc 1182 /*! @name PACRF - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1183 #define AIPS_PACRF_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1184 #define AIPS_PACRF_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1185 #define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1186 #define AIPS_PACRF_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1187 #define AIPS_PACRF_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1188 #define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1189 #define AIPS_PACRF_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1190 #define AIPS_PACRF_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1191 #define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1192 #define AIPS_PACRF_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1193 #define AIPS_PACRF_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1194 #define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1195 #define AIPS_PACRF_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1196 #define AIPS_PACRF_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1197 #define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1198 #define AIPS_PACRF_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1199 #define AIPS_PACRF_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1200 #define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1201 #define AIPS_PACRF_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1202 #define AIPS_PACRF_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1203 #define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1204 #define AIPS_PACRF_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1205 #define AIPS_PACRF_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1206 #define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1207 #define AIPS_PACRF_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1208 #define AIPS_PACRF_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1209 #define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1210 #define AIPS_PACRF_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1211 #define AIPS_PACRF_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1212 #define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1213 #define AIPS_PACRF_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1214 #define AIPS_PACRF_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1215 #define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1216 #define AIPS_PACRF_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1217 #define AIPS_PACRF_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1218 #define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1219 #define AIPS_PACRF_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1220 #define AIPS_PACRF_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1221 #define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1222 #define AIPS_PACRF_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1223 #define AIPS_PACRF_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1224 #define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1225 #define AIPS_PACRF_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1226 #define AIPS_PACRF_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1227 #define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1228 #define AIPS_PACRF_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1229 #define AIPS_PACRF_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1230 #define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1231 #define AIPS_PACRF_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1232 #define AIPS_PACRF_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1233 #define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1234 #define AIPS_PACRF_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1235 #define AIPS_PACRF_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1236 #define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1237 #define AIPS_PACRF_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1238 #define AIPS_PACRF_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1239 #define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1240 #define AIPS_PACRF_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1241 #define AIPS_PACRF_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1242 #define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1243 #define AIPS_PACRF_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1244 #define AIPS_PACRF_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1245 #define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1246 #define AIPS_PACRF_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1247 #define AIPS_PACRF_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1248 #define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1249 #define AIPS_PACRF_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1250 #define AIPS_PACRF_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1251 #define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1252 #define AIPS_PACRF_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1253 #define AIPS_PACRF_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1254 #define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1255
AnnaBridge 171:3a7713b1edbc 1256 /*! @name PACRG - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1257 #define AIPS_PACRG_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1258 #define AIPS_PACRG_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1259 #define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1260 #define AIPS_PACRG_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1261 #define AIPS_PACRG_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1262 #define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1263 #define AIPS_PACRG_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1264 #define AIPS_PACRG_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1265 #define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1266 #define AIPS_PACRG_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1267 #define AIPS_PACRG_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1268 #define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1269 #define AIPS_PACRG_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1270 #define AIPS_PACRG_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1271 #define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1272 #define AIPS_PACRG_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1273 #define AIPS_PACRG_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1274 #define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1275 #define AIPS_PACRG_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1276 #define AIPS_PACRG_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1277 #define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1278 #define AIPS_PACRG_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1279 #define AIPS_PACRG_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1280 #define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1281 #define AIPS_PACRG_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1282 #define AIPS_PACRG_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1283 #define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1284 #define AIPS_PACRG_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1285 #define AIPS_PACRG_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1286 #define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1287 #define AIPS_PACRG_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1288 #define AIPS_PACRG_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1289 #define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1290 #define AIPS_PACRG_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1291 #define AIPS_PACRG_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1292 #define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1293 #define AIPS_PACRG_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1294 #define AIPS_PACRG_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1295 #define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1296 #define AIPS_PACRG_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1297 #define AIPS_PACRG_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1298 #define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1299 #define AIPS_PACRG_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1300 #define AIPS_PACRG_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1301 #define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1302 #define AIPS_PACRG_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1303 #define AIPS_PACRG_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1304 #define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1305 #define AIPS_PACRG_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1306 #define AIPS_PACRG_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1307 #define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1308 #define AIPS_PACRG_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1309 #define AIPS_PACRG_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1310 #define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1311 #define AIPS_PACRG_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1312 #define AIPS_PACRG_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1313 #define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1314 #define AIPS_PACRG_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1315 #define AIPS_PACRG_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1316 #define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1317 #define AIPS_PACRG_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1318 #define AIPS_PACRG_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1319 #define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1320 #define AIPS_PACRG_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1321 #define AIPS_PACRG_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1322 #define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1323 #define AIPS_PACRG_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1324 #define AIPS_PACRG_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1325 #define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1326 #define AIPS_PACRG_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1327 #define AIPS_PACRG_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1328 #define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1329
AnnaBridge 171:3a7713b1edbc 1330 /*! @name PACRH - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1331 #define AIPS_PACRH_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1332 #define AIPS_PACRH_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1333 #define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1334 #define AIPS_PACRH_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1335 #define AIPS_PACRH_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1336 #define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1337 #define AIPS_PACRH_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1338 #define AIPS_PACRH_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1339 #define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1340 #define AIPS_PACRH_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1341 #define AIPS_PACRH_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1342 #define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1343 #define AIPS_PACRH_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1344 #define AIPS_PACRH_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1345 #define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1346 #define AIPS_PACRH_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1347 #define AIPS_PACRH_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1348 #define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1349 #define AIPS_PACRH_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1350 #define AIPS_PACRH_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1351 #define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1352 #define AIPS_PACRH_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1353 #define AIPS_PACRH_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1354 #define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1355 #define AIPS_PACRH_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1356 #define AIPS_PACRH_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1357 #define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1358 #define AIPS_PACRH_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1359 #define AIPS_PACRH_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1360 #define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1361 #define AIPS_PACRH_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1362 #define AIPS_PACRH_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1363 #define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1364 #define AIPS_PACRH_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1365 #define AIPS_PACRH_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1366 #define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1367 #define AIPS_PACRH_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1368 #define AIPS_PACRH_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1369 #define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1370 #define AIPS_PACRH_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1371 #define AIPS_PACRH_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1372 #define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1373 #define AIPS_PACRH_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1374 #define AIPS_PACRH_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1375 #define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1376 #define AIPS_PACRH_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1377 #define AIPS_PACRH_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1378 #define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1379 #define AIPS_PACRH_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1380 #define AIPS_PACRH_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1381 #define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1382 #define AIPS_PACRH_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1383 #define AIPS_PACRH_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1384 #define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1385 #define AIPS_PACRH_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1386 #define AIPS_PACRH_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1387 #define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1388 #define AIPS_PACRH_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1389 #define AIPS_PACRH_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1390 #define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1391 #define AIPS_PACRH_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1392 #define AIPS_PACRH_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1393 #define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1394 #define AIPS_PACRH_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1395 #define AIPS_PACRH_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1396 #define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1397 #define AIPS_PACRH_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1398 #define AIPS_PACRH_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1399 #define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1400 #define AIPS_PACRH_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1401 #define AIPS_PACRH_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1402 #define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1403
AnnaBridge 171:3a7713b1edbc 1404 /*! @name PACRI - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1405 #define AIPS_PACRI_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1406 #define AIPS_PACRI_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1407 #define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1408 #define AIPS_PACRI_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1409 #define AIPS_PACRI_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1410 #define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1411 #define AIPS_PACRI_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1412 #define AIPS_PACRI_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1413 #define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1414 #define AIPS_PACRI_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1415 #define AIPS_PACRI_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1416 #define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1417 #define AIPS_PACRI_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1418 #define AIPS_PACRI_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1419 #define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1420 #define AIPS_PACRI_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1421 #define AIPS_PACRI_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1422 #define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1423 #define AIPS_PACRI_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1424 #define AIPS_PACRI_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1425 #define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1426 #define AIPS_PACRI_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1427 #define AIPS_PACRI_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1428 #define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1429 #define AIPS_PACRI_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1430 #define AIPS_PACRI_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1431 #define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1432 #define AIPS_PACRI_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1433 #define AIPS_PACRI_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1434 #define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1435 #define AIPS_PACRI_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1436 #define AIPS_PACRI_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1437 #define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1438 #define AIPS_PACRI_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1439 #define AIPS_PACRI_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1440 #define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1441 #define AIPS_PACRI_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1442 #define AIPS_PACRI_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1443 #define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1444 #define AIPS_PACRI_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1445 #define AIPS_PACRI_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1446 #define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1447 #define AIPS_PACRI_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1448 #define AIPS_PACRI_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1449 #define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1450 #define AIPS_PACRI_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1451 #define AIPS_PACRI_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1452 #define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1453 #define AIPS_PACRI_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1454 #define AIPS_PACRI_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1455 #define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1456 #define AIPS_PACRI_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1457 #define AIPS_PACRI_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1458 #define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1459 #define AIPS_PACRI_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1460 #define AIPS_PACRI_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1461 #define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1462 #define AIPS_PACRI_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1463 #define AIPS_PACRI_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1464 #define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1465 #define AIPS_PACRI_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1466 #define AIPS_PACRI_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1467 #define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1468 #define AIPS_PACRI_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1469 #define AIPS_PACRI_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1470 #define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1471 #define AIPS_PACRI_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1472 #define AIPS_PACRI_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1473 #define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1474 #define AIPS_PACRI_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1475 #define AIPS_PACRI_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1476 #define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1477
AnnaBridge 171:3a7713b1edbc 1478 /*! @name PACRJ - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1479 #define AIPS_PACRJ_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1480 #define AIPS_PACRJ_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1481 #define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1482 #define AIPS_PACRJ_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1483 #define AIPS_PACRJ_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1484 #define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1485 #define AIPS_PACRJ_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1486 #define AIPS_PACRJ_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1487 #define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1488 #define AIPS_PACRJ_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1489 #define AIPS_PACRJ_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1490 #define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1491 #define AIPS_PACRJ_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1492 #define AIPS_PACRJ_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1493 #define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1494 #define AIPS_PACRJ_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1495 #define AIPS_PACRJ_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1496 #define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1497 #define AIPS_PACRJ_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1498 #define AIPS_PACRJ_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1499 #define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1500 #define AIPS_PACRJ_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1501 #define AIPS_PACRJ_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1502 #define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1503 #define AIPS_PACRJ_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1504 #define AIPS_PACRJ_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1505 #define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1506 #define AIPS_PACRJ_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1507 #define AIPS_PACRJ_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1508 #define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1509 #define AIPS_PACRJ_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1510 #define AIPS_PACRJ_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1511 #define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1512 #define AIPS_PACRJ_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1513 #define AIPS_PACRJ_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1514 #define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1515 #define AIPS_PACRJ_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1516 #define AIPS_PACRJ_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1517 #define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1518 #define AIPS_PACRJ_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1519 #define AIPS_PACRJ_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1520 #define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1521 #define AIPS_PACRJ_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1522 #define AIPS_PACRJ_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1523 #define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1524 #define AIPS_PACRJ_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1525 #define AIPS_PACRJ_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1526 #define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1527 #define AIPS_PACRJ_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1528 #define AIPS_PACRJ_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1529 #define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1530 #define AIPS_PACRJ_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1531 #define AIPS_PACRJ_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1532 #define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1533 #define AIPS_PACRJ_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1534 #define AIPS_PACRJ_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1535 #define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1536 #define AIPS_PACRJ_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1537 #define AIPS_PACRJ_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1538 #define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1539 #define AIPS_PACRJ_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1540 #define AIPS_PACRJ_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1541 #define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1542 #define AIPS_PACRJ_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1543 #define AIPS_PACRJ_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1544 #define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1545 #define AIPS_PACRJ_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1546 #define AIPS_PACRJ_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1547 #define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1548 #define AIPS_PACRJ_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1549 #define AIPS_PACRJ_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1550 #define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1551
AnnaBridge 171:3a7713b1edbc 1552 /*! @name PACRK - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1553 #define AIPS_PACRK_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1554 #define AIPS_PACRK_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1555 #define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1556 #define AIPS_PACRK_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1557 #define AIPS_PACRK_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1558 #define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1559 #define AIPS_PACRK_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1560 #define AIPS_PACRK_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1561 #define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1562 #define AIPS_PACRK_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1563 #define AIPS_PACRK_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1564 #define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1565 #define AIPS_PACRK_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1566 #define AIPS_PACRK_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1567 #define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1568 #define AIPS_PACRK_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1569 #define AIPS_PACRK_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1570 #define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1571 #define AIPS_PACRK_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1572 #define AIPS_PACRK_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1573 #define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1574 #define AIPS_PACRK_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1575 #define AIPS_PACRK_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1576 #define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1577 #define AIPS_PACRK_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1578 #define AIPS_PACRK_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1579 #define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1580 #define AIPS_PACRK_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1581 #define AIPS_PACRK_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1582 #define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1583 #define AIPS_PACRK_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1584 #define AIPS_PACRK_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1585 #define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1586 #define AIPS_PACRK_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1587 #define AIPS_PACRK_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1588 #define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1589 #define AIPS_PACRK_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1590 #define AIPS_PACRK_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1591 #define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1592 #define AIPS_PACRK_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1593 #define AIPS_PACRK_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1594 #define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1595 #define AIPS_PACRK_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1596 #define AIPS_PACRK_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1597 #define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1598 #define AIPS_PACRK_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1599 #define AIPS_PACRK_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1600 #define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1601 #define AIPS_PACRK_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1602 #define AIPS_PACRK_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1603 #define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1604 #define AIPS_PACRK_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1605 #define AIPS_PACRK_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1606 #define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1607 #define AIPS_PACRK_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1608 #define AIPS_PACRK_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1609 #define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1610 #define AIPS_PACRK_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1611 #define AIPS_PACRK_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1612 #define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1613 #define AIPS_PACRK_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1614 #define AIPS_PACRK_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1615 #define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1616 #define AIPS_PACRK_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1617 #define AIPS_PACRK_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1618 #define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1619 #define AIPS_PACRK_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1620 #define AIPS_PACRK_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1621 #define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1622 #define AIPS_PACRK_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1623 #define AIPS_PACRK_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1624 #define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1625
AnnaBridge 171:3a7713b1edbc 1626 /*! @name PACRL - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1627 #define AIPS_PACRL_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1628 #define AIPS_PACRL_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1629 #define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1630 #define AIPS_PACRL_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1631 #define AIPS_PACRL_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1632 #define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1633 #define AIPS_PACRL_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1634 #define AIPS_PACRL_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1635 #define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1636 #define AIPS_PACRL_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1637 #define AIPS_PACRL_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1638 #define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1639 #define AIPS_PACRL_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1640 #define AIPS_PACRL_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1641 #define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1642 #define AIPS_PACRL_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1643 #define AIPS_PACRL_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1644 #define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1645 #define AIPS_PACRL_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1646 #define AIPS_PACRL_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1647 #define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1648 #define AIPS_PACRL_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1649 #define AIPS_PACRL_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1650 #define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1651 #define AIPS_PACRL_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1652 #define AIPS_PACRL_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1653 #define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1654 #define AIPS_PACRL_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1655 #define AIPS_PACRL_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1656 #define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1657 #define AIPS_PACRL_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1658 #define AIPS_PACRL_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1659 #define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1660 #define AIPS_PACRL_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1661 #define AIPS_PACRL_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1662 #define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1663 #define AIPS_PACRL_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1664 #define AIPS_PACRL_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1665 #define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1666 #define AIPS_PACRL_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1667 #define AIPS_PACRL_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1668 #define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1669 #define AIPS_PACRL_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1670 #define AIPS_PACRL_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1671 #define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1672 #define AIPS_PACRL_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1673 #define AIPS_PACRL_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1674 #define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1675 #define AIPS_PACRL_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1676 #define AIPS_PACRL_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1677 #define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1678 #define AIPS_PACRL_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1679 #define AIPS_PACRL_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1680 #define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1681 #define AIPS_PACRL_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1682 #define AIPS_PACRL_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1683 #define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1684 #define AIPS_PACRL_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1685 #define AIPS_PACRL_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1686 #define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1687 #define AIPS_PACRL_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1688 #define AIPS_PACRL_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1689 #define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1690 #define AIPS_PACRL_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1691 #define AIPS_PACRL_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1692 #define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1693 #define AIPS_PACRL_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1694 #define AIPS_PACRL_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1695 #define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1696 #define AIPS_PACRL_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1697 #define AIPS_PACRL_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1698 #define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1699
AnnaBridge 171:3a7713b1edbc 1700 /*! @name PACRM - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1701 #define AIPS_PACRM_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1702 #define AIPS_PACRM_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1703 #define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1704 #define AIPS_PACRM_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1705 #define AIPS_PACRM_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1706 #define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1707 #define AIPS_PACRM_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1708 #define AIPS_PACRM_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1709 #define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1710 #define AIPS_PACRM_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1711 #define AIPS_PACRM_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1712 #define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1713 #define AIPS_PACRM_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1714 #define AIPS_PACRM_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1715 #define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1716 #define AIPS_PACRM_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1717 #define AIPS_PACRM_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1718 #define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1719 #define AIPS_PACRM_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1720 #define AIPS_PACRM_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1721 #define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1722 #define AIPS_PACRM_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1723 #define AIPS_PACRM_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1724 #define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1725 #define AIPS_PACRM_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1726 #define AIPS_PACRM_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1727 #define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1728 #define AIPS_PACRM_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1729 #define AIPS_PACRM_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1730 #define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1731 #define AIPS_PACRM_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1732 #define AIPS_PACRM_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1733 #define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1734 #define AIPS_PACRM_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1735 #define AIPS_PACRM_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1736 #define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1737 #define AIPS_PACRM_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1738 #define AIPS_PACRM_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1739 #define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1740 #define AIPS_PACRM_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1741 #define AIPS_PACRM_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1742 #define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1743 #define AIPS_PACRM_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1744 #define AIPS_PACRM_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1745 #define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1746 #define AIPS_PACRM_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1747 #define AIPS_PACRM_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1748 #define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1749 #define AIPS_PACRM_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1750 #define AIPS_PACRM_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1751 #define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1752 #define AIPS_PACRM_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1753 #define AIPS_PACRM_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1754 #define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1755 #define AIPS_PACRM_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1756 #define AIPS_PACRM_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1757 #define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1758 #define AIPS_PACRM_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1759 #define AIPS_PACRM_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1760 #define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1761 #define AIPS_PACRM_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1762 #define AIPS_PACRM_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1763 #define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1764 #define AIPS_PACRM_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1765 #define AIPS_PACRM_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1766 #define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1767 #define AIPS_PACRM_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1768 #define AIPS_PACRM_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1769 #define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1770 #define AIPS_PACRM_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1771 #define AIPS_PACRM_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1772 #define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1773
AnnaBridge 171:3a7713b1edbc 1774 /*! @name PACRN - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1775 #define AIPS_PACRN_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1776 #define AIPS_PACRN_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1777 #define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1778 #define AIPS_PACRN_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1779 #define AIPS_PACRN_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1780 #define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1781 #define AIPS_PACRN_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1782 #define AIPS_PACRN_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1783 #define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1784 #define AIPS_PACRN_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1785 #define AIPS_PACRN_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1786 #define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1787 #define AIPS_PACRN_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1788 #define AIPS_PACRN_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1789 #define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1790 #define AIPS_PACRN_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1791 #define AIPS_PACRN_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1792 #define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1793 #define AIPS_PACRN_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1794 #define AIPS_PACRN_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1795 #define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1796 #define AIPS_PACRN_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1797 #define AIPS_PACRN_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1798 #define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1799 #define AIPS_PACRN_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1800 #define AIPS_PACRN_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1801 #define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1802 #define AIPS_PACRN_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1803 #define AIPS_PACRN_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1804 #define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1805 #define AIPS_PACRN_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1806 #define AIPS_PACRN_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1807 #define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1808 #define AIPS_PACRN_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1809 #define AIPS_PACRN_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1810 #define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1811 #define AIPS_PACRN_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1812 #define AIPS_PACRN_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1813 #define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1814 #define AIPS_PACRN_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1815 #define AIPS_PACRN_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1816 #define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1817 #define AIPS_PACRN_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1818 #define AIPS_PACRN_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1819 #define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1820 #define AIPS_PACRN_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1821 #define AIPS_PACRN_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1822 #define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1823 #define AIPS_PACRN_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1824 #define AIPS_PACRN_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1825 #define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1826 #define AIPS_PACRN_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1827 #define AIPS_PACRN_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1828 #define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1829 #define AIPS_PACRN_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1830 #define AIPS_PACRN_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1831 #define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1832 #define AIPS_PACRN_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1833 #define AIPS_PACRN_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1834 #define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1835 #define AIPS_PACRN_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1836 #define AIPS_PACRN_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1837 #define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1838 #define AIPS_PACRN_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1839 #define AIPS_PACRN_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1840 #define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1841 #define AIPS_PACRN_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1842 #define AIPS_PACRN_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1843 #define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1844 #define AIPS_PACRN_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1845 #define AIPS_PACRN_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1846 #define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1847
AnnaBridge 171:3a7713b1edbc 1848 /*! @name PACRO - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1849 #define AIPS_PACRO_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1850 #define AIPS_PACRO_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1851 #define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1852 #define AIPS_PACRO_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1853 #define AIPS_PACRO_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1854 #define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1855 #define AIPS_PACRO_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1856 #define AIPS_PACRO_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1857 #define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1858 #define AIPS_PACRO_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1859 #define AIPS_PACRO_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1860 #define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1861 #define AIPS_PACRO_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1862 #define AIPS_PACRO_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1863 #define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1864 #define AIPS_PACRO_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1865 #define AIPS_PACRO_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1866 #define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1867 #define AIPS_PACRO_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1868 #define AIPS_PACRO_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1869 #define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1870 #define AIPS_PACRO_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1871 #define AIPS_PACRO_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1872 #define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1873 #define AIPS_PACRO_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1874 #define AIPS_PACRO_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1875 #define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1876 #define AIPS_PACRO_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1877 #define AIPS_PACRO_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1878 #define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1879 #define AIPS_PACRO_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1880 #define AIPS_PACRO_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1881 #define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1882 #define AIPS_PACRO_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1883 #define AIPS_PACRO_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1884 #define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1885 #define AIPS_PACRO_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1886 #define AIPS_PACRO_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1887 #define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1888 #define AIPS_PACRO_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1889 #define AIPS_PACRO_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1890 #define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1891 #define AIPS_PACRO_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1892 #define AIPS_PACRO_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1893 #define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1894 #define AIPS_PACRO_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1895 #define AIPS_PACRO_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1896 #define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1897 #define AIPS_PACRO_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1898 #define AIPS_PACRO_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1899 #define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1900 #define AIPS_PACRO_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1901 #define AIPS_PACRO_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1902 #define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1903 #define AIPS_PACRO_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1904 #define AIPS_PACRO_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1905 #define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1906 #define AIPS_PACRO_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1907 #define AIPS_PACRO_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1908 #define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1909 #define AIPS_PACRO_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1910 #define AIPS_PACRO_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1911 #define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1912 #define AIPS_PACRO_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1913 #define AIPS_PACRO_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1914 #define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1915 #define AIPS_PACRO_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1916 #define AIPS_PACRO_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1917 #define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1918 #define AIPS_PACRO_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1919 #define AIPS_PACRO_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1920 #define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1921
AnnaBridge 171:3a7713b1edbc 1922 /*! @name PACRP - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1923 #define AIPS_PACRP_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1924 #define AIPS_PACRP_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1925 #define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1926 #define AIPS_PACRP_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1927 #define AIPS_PACRP_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1928 #define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1929 #define AIPS_PACRP_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1930 #define AIPS_PACRP_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1931 #define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1932 #define AIPS_PACRP_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1933 #define AIPS_PACRP_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1934 #define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1935 #define AIPS_PACRP_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1936 #define AIPS_PACRP_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1937 #define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1938 #define AIPS_PACRP_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1939 #define AIPS_PACRP_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1940 #define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1941 #define AIPS_PACRP_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1942 #define AIPS_PACRP_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1943 #define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1944 #define AIPS_PACRP_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1945 #define AIPS_PACRP_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1946 #define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1947 #define AIPS_PACRP_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1948 #define AIPS_PACRP_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1949 #define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1950 #define AIPS_PACRP_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1951 #define AIPS_PACRP_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1952 #define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1953 #define AIPS_PACRP_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1954 #define AIPS_PACRP_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1955 #define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1956 #define AIPS_PACRP_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1957 #define AIPS_PACRP_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1958 #define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1959 #define AIPS_PACRP_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1960 #define AIPS_PACRP_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1961 #define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1962 #define AIPS_PACRP_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1963 #define AIPS_PACRP_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1964 #define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1965 #define AIPS_PACRP_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1966 #define AIPS_PACRP_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1967 #define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1968 #define AIPS_PACRP_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1969 #define AIPS_PACRP_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1970 #define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1971 #define AIPS_PACRP_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1972 #define AIPS_PACRP_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1973 #define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1974 #define AIPS_PACRP_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1975 #define AIPS_PACRP_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1976 #define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1977 #define AIPS_PACRP_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1978 #define AIPS_PACRP_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1979 #define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1980 #define AIPS_PACRP_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1981 #define AIPS_PACRP_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1982 #define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1983 #define AIPS_PACRP_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1984 #define AIPS_PACRP_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1985 #define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1986 #define AIPS_PACRP_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1987 #define AIPS_PACRP_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1988 #define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1989 #define AIPS_PACRP_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1990 #define AIPS_PACRP_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1991 #define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1992 #define AIPS_PACRP_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1993 #define AIPS_PACRP_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1994 #define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1995
AnnaBridge 171:3a7713b1edbc 1996
AnnaBridge 171:3a7713b1edbc 1997 /*!
AnnaBridge 171:3a7713b1edbc 1998 * @}
AnnaBridge 171:3a7713b1edbc 1999 */ /* end of group AIPS_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2000
AnnaBridge 171:3a7713b1edbc 2001
AnnaBridge 171:3a7713b1edbc 2002 /* AIPS - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2003 /** Peripheral AIPS0 base address */
AnnaBridge 171:3a7713b1edbc 2004 #define AIPS0_BASE (0x40000000u)
AnnaBridge 171:3a7713b1edbc 2005 /** Peripheral AIPS0 base pointer */
AnnaBridge 171:3a7713b1edbc 2006 #define AIPS0 ((AIPS_Type *)AIPS0_BASE)
AnnaBridge 171:3a7713b1edbc 2007 /** Peripheral AIPS1 base address */
AnnaBridge 171:3a7713b1edbc 2008 #define AIPS1_BASE (0x40080000u)
AnnaBridge 171:3a7713b1edbc 2009 /** Peripheral AIPS1 base pointer */
AnnaBridge 171:3a7713b1edbc 2010 #define AIPS1 ((AIPS_Type *)AIPS1_BASE)
AnnaBridge 171:3a7713b1edbc 2011 /** Array initializer of AIPS peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 2012 #define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
AnnaBridge 171:3a7713b1edbc 2013 /** Array initializer of AIPS peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2014 #define AIPS_BASE_PTRS { AIPS0, AIPS1 }
AnnaBridge 171:3a7713b1edbc 2015
AnnaBridge 171:3a7713b1edbc 2016 /*!
AnnaBridge 171:3a7713b1edbc 2017 * @}
AnnaBridge 171:3a7713b1edbc 2018 */ /* end of group AIPS_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2019
AnnaBridge 171:3a7713b1edbc 2020
AnnaBridge 171:3a7713b1edbc 2021 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2022 -- AXBS Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2023 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2024
AnnaBridge 171:3a7713b1edbc 2025 /*!
AnnaBridge 171:3a7713b1edbc 2026 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2027 * @{
AnnaBridge 171:3a7713b1edbc 2028 */
AnnaBridge 171:3a7713b1edbc 2029
AnnaBridge 171:3a7713b1edbc 2030 /** AXBS - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2031 typedef struct {
AnnaBridge 171:3a7713b1edbc 2032 struct { /* offset: 0x0, array step: 0x100 */
AnnaBridge 171:3a7713b1edbc 2033 __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
AnnaBridge 171:3a7713b1edbc 2034 uint8_t RESERVED_0[12];
AnnaBridge 171:3a7713b1edbc 2035 __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
AnnaBridge 171:3a7713b1edbc 2036 uint8_t RESERVED_1[236];
AnnaBridge 171:3a7713b1edbc 2037 } SLAVE[5];
AnnaBridge 171:3a7713b1edbc 2038 uint8_t RESERVED_0[768];
AnnaBridge 171:3a7713b1edbc 2039 __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
AnnaBridge 171:3a7713b1edbc 2040 uint8_t RESERVED_1[252];
AnnaBridge 171:3a7713b1edbc 2041 __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
AnnaBridge 171:3a7713b1edbc 2042 uint8_t RESERVED_2[252];
AnnaBridge 171:3a7713b1edbc 2043 __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
AnnaBridge 171:3a7713b1edbc 2044 uint8_t RESERVED_3[252];
AnnaBridge 171:3a7713b1edbc 2045 __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
AnnaBridge 171:3a7713b1edbc 2046 uint8_t RESERVED_4[252];
AnnaBridge 171:3a7713b1edbc 2047 __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
AnnaBridge 171:3a7713b1edbc 2048 uint8_t RESERVED_5[252];
AnnaBridge 171:3a7713b1edbc 2049 __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
AnnaBridge 171:3a7713b1edbc 2050 uint8_t RESERVED_6[252];
AnnaBridge 171:3a7713b1edbc 2051 __IO uint32_t MGPCR6; /**< Master General Purpose Control Register, offset: 0xE00 */
AnnaBridge 171:3a7713b1edbc 2052 } AXBS_Type;
AnnaBridge 171:3a7713b1edbc 2053
AnnaBridge 171:3a7713b1edbc 2054 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2055 -- AXBS Register Masks
AnnaBridge 171:3a7713b1edbc 2056 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2057
AnnaBridge 171:3a7713b1edbc 2058 /*!
AnnaBridge 171:3a7713b1edbc 2059 * @addtogroup AXBS_Register_Masks AXBS Register Masks
AnnaBridge 171:3a7713b1edbc 2060 * @{
AnnaBridge 171:3a7713b1edbc 2061 */
AnnaBridge 171:3a7713b1edbc 2062
AnnaBridge 171:3a7713b1edbc 2063 /*! @name PRS - Priority Registers Slave */
AnnaBridge 171:3a7713b1edbc 2064 #define AXBS_PRS_M0_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 2065 #define AXBS_PRS_M0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2066 #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
AnnaBridge 171:3a7713b1edbc 2067 #define AXBS_PRS_M1_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 2068 #define AXBS_PRS_M1_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2069 #define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
AnnaBridge 171:3a7713b1edbc 2070 #define AXBS_PRS_M2_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 2071 #define AXBS_PRS_M2_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2072 #define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
AnnaBridge 171:3a7713b1edbc 2073 #define AXBS_PRS_M3_MASK (0x7000U)
AnnaBridge 171:3a7713b1edbc 2074 #define AXBS_PRS_M3_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 2075 #define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
AnnaBridge 171:3a7713b1edbc 2076 #define AXBS_PRS_M4_MASK (0x70000U)
AnnaBridge 171:3a7713b1edbc 2077 #define AXBS_PRS_M4_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2078 #define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
AnnaBridge 171:3a7713b1edbc 2079 #define AXBS_PRS_M5_MASK (0x700000U)
AnnaBridge 171:3a7713b1edbc 2080 #define AXBS_PRS_M5_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 2081 #define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
AnnaBridge 171:3a7713b1edbc 2082 #define AXBS_PRS_M6_MASK (0x7000000U)
AnnaBridge 171:3a7713b1edbc 2083 #define AXBS_PRS_M6_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2084 #define AXBS_PRS_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M6_SHIFT)) & AXBS_PRS_M6_MASK)
AnnaBridge 171:3a7713b1edbc 2085
AnnaBridge 171:3a7713b1edbc 2086 /* The count of AXBS_PRS */
AnnaBridge 171:3a7713b1edbc 2087 #define AXBS_PRS_COUNT (5U)
AnnaBridge 171:3a7713b1edbc 2088
AnnaBridge 171:3a7713b1edbc 2089 /*! @name CRS - Control Register */
AnnaBridge 171:3a7713b1edbc 2090 #define AXBS_CRS_PARK_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 2091 #define AXBS_CRS_PARK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2092 #define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
AnnaBridge 171:3a7713b1edbc 2093 #define AXBS_CRS_PCTL_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 2094 #define AXBS_CRS_PCTL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2095 #define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
AnnaBridge 171:3a7713b1edbc 2096 #define AXBS_CRS_ARB_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 2097 #define AXBS_CRS_ARB_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2098 #define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
AnnaBridge 171:3a7713b1edbc 2099 #define AXBS_CRS_HLP_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 2100 #define AXBS_CRS_HLP_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 2101 #define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
AnnaBridge 171:3a7713b1edbc 2102 #define AXBS_CRS_RO_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 2103 #define AXBS_CRS_RO_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 2104 #define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
AnnaBridge 171:3a7713b1edbc 2105
AnnaBridge 171:3a7713b1edbc 2106 /* The count of AXBS_CRS */
AnnaBridge 171:3a7713b1edbc 2107 #define AXBS_CRS_COUNT (5U)
AnnaBridge 171:3a7713b1edbc 2108
AnnaBridge 171:3a7713b1edbc 2109 /*! @name MGPCR0 - Master General Purpose Control Register */
AnnaBridge 171:3a7713b1edbc 2110 #define AXBS_MGPCR0_AULB_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 2111 #define AXBS_MGPCR0_AULB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2112 #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
AnnaBridge 171:3a7713b1edbc 2113
AnnaBridge 171:3a7713b1edbc 2114 /*! @name MGPCR1 - Master General Purpose Control Register */
AnnaBridge 171:3a7713b1edbc 2115 #define AXBS_MGPCR1_AULB_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 2116 #define AXBS_MGPCR1_AULB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2117 #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
AnnaBridge 171:3a7713b1edbc 2118
AnnaBridge 171:3a7713b1edbc 2119 /*! @name MGPCR2 - Master General Purpose Control Register */
AnnaBridge 171:3a7713b1edbc 2120 #define AXBS_MGPCR2_AULB_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 2121 #define AXBS_MGPCR2_AULB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2122 #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
AnnaBridge 171:3a7713b1edbc 2123
AnnaBridge 171:3a7713b1edbc 2124 /*! @name MGPCR3 - Master General Purpose Control Register */
AnnaBridge 171:3a7713b1edbc 2125 #define AXBS_MGPCR3_AULB_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 2126 #define AXBS_MGPCR3_AULB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2127 #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
AnnaBridge 171:3a7713b1edbc 2128
AnnaBridge 171:3a7713b1edbc 2129 /*! @name MGPCR4 - Master General Purpose Control Register */
AnnaBridge 171:3a7713b1edbc 2130 #define AXBS_MGPCR4_AULB_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 2131 #define AXBS_MGPCR4_AULB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2132 #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
AnnaBridge 171:3a7713b1edbc 2133
AnnaBridge 171:3a7713b1edbc 2134 /*! @name MGPCR5 - Master General Purpose Control Register */
AnnaBridge 171:3a7713b1edbc 2135 #define AXBS_MGPCR5_AULB_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 2136 #define AXBS_MGPCR5_AULB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2137 #define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
AnnaBridge 171:3a7713b1edbc 2138
AnnaBridge 171:3a7713b1edbc 2139 /*! @name MGPCR6 - Master General Purpose Control Register */
AnnaBridge 171:3a7713b1edbc 2140 #define AXBS_MGPCR6_AULB_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 2141 #define AXBS_MGPCR6_AULB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2142 #define AXBS_MGPCR6_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR6_AULB_SHIFT)) & AXBS_MGPCR6_AULB_MASK)
AnnaBridge 171:3a7713b1edbc 2143
AnnaBridge 171:3a7713b1edbc 2144
AnnaBridge 171:3a7713b1edbc 2145 /*!
AnnaBridge 171:3a7713b1edbc 2146 * @}
AnnaBridge 171:3a7713b1edbc 2147 */ /* end of group AXBS_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2148
AnnaBridge 171:3a7713b1edbc 2149
AnnaBridge 171:3a7713b1edbc 2150 /* AXBS - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2151 /** Peripheral AXBS base address */
AnnaBridge 171:3a7713b1edbc 2152 #define AXBS_BASE (0x40004000u)
AnnaBridge 171:3a7713b1edbc 2153 /** Peripheral AXBS base pointer */
AnnaBridge 171:3a7713b1edbc 2154 #define AXBS ((AXBS_Type *)AXBS_BASE)
AnnaBridge 171:3a7713b1edbc 2155 /** Array initializer of AXBS peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 2156 #define AXBS_BASE_ADDRS { AXBS_BASE }
AnnaBridge 171:3a7713b1edbc 2157 /** Array initializer of AXBS peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2158 #define AXBS_BASE_PTRS { AXBS }
AnnaBridge 171:3a7713b1edbc 2159
AnnaBridge 171:3a7713b1edbc 2160 /*!
AnnaBridge 171:3a7713b1edbc 2161 * @}
AnnaBridge 171:3a7713b1edbc 2162 */ /* end of group AXBS_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2163
AnnaBridge 171:3a7713b1edbc 2164
AnnaBridge 171:3a7713b1edbc 2165 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2166 -- CAN Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2167 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2168
AnnaBridge 171:3a7713b1edbc 2169 /*!
AnnaBridge 171:3a7713b1edbc 2170 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2171 * @{
AnnaBridge 171:3a7713b1edbc 2172 */
AnnaBridge 171:3a7713b1edbc 2173
AnnaBridge 171:3a7713b1edbc 2174 /** CAN - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2175 typedef struct {
AnnaBridge 171:3a7713b1edbc 2176 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 2177 __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 2178 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 2179 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 2180 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 2181 __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 2182 __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 2183 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 2184 __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 2185 uint8_t RESERVED_1[4];
AnnaBridge 171:3a7713b1edbc 2186 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 2187 uint8_t RESERVED_2[4];
AnnaBridge 171:3a7713b1edbc 2188 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 2189 __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 2190 __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 2191 uint8_t RESERVED_3[8];
AnnaBridge 171:3a7713b1edbc 2192 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 2193 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 2194 __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 2195 uint8_t RESERVED_4[48];
AnnaBridge 171:3a7713b1edbc 2196 struct { /* offset: 0x80, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 2197 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 2198 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 2199 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 2200 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 2201 } MB[16];
AnnaBridge 171:3a7713b1edbc 2202 uint8_t RESERVED_5[1792];
AnnaBridge 171:3a7713b1edbc 2203 __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2204 } CAN_Type;
AnnaBridge 171:3a7713b1edbc 2205
AnnaBridge 171:3a7713b1edbc 2206 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2207 -- CAN Register Masks
AnnaBridge 171:3a7713b1edbc 2208 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2209
AnnaBridge 171:3a7713b1edbc 2210 /*!
AnnaBridge 171:3a7713b1edbc 2211 * @addtogroup CAN_Register_Masks CAN Register Masks
AnnaBridge 171:3a7713b1edbc 2212 * @{
AnnaBridge 171:3a7713b1edbc 2213 */
AnnaBridge 171:3a7713b1edbc 2214
AnnaBridge 171:3a7713b1edbc 2215 /*! @name MCR - Module Configuration Register */
AnnaBridge 171:3a7713b1edbc 2216 #define CAN_MCR_MAXMB_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 2217 #define CAN_MCR_MAXMB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2218 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
AnnaBridge 171:3a7713b1edbc 2219 #define CAN_MCR_IDAM_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 2220 #define CAN_MCR_IDAM_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2221 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
AnnaBridge 171:3a7713b1edbc 2222 #define CAN_MCR_AEN_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 2223 #define CAN_MCR_AEN_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 2224 #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
AnnaBridge 171:3a7713b1edbc 2225 #define CAN_MCR_LPRIOEN_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 2226 #define CAN_MCR_LPRIOEN_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 2227 #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
AnnaBridge 171:3a7713b1edbc 2228 #define CAN_MCR_IRMQ_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 2229 #define CAN_MCR_IRMQ_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2230 #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
AnnaBridge 171:3a7713b1edbc 2231 #define CAN_MCR_SRXDIS_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 2232 #define CAN_MCR_SRXDIS_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 2233 #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
AnnaBridge 171:3a7713b1edbc 2234 #define CAN_MCR_WAKSRC_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 2235 #define CAN_MCR_WAKSRC_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 2236 #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
AnnaBridge 171:3a7713b1edbc 2237 #define CAN_MCR_LPMACK_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 2238 #define CAN_MCR_LPMACK_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 2239 #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
AnnaBridge 171:3a7713b1edbc 2240 #define CAN_MCR_WRNEN_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 2241 #define CAN_MCR_WRNEN_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 2242 #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
AnnaBridge 171:3a7713b1edbc 2243 #define CAN_MCR_SLFWAK_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 2244 #define CAN_MCR_SLFWAK_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 2245 #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
AnnaBridge 171:3a7713b1edbc 2246 #define CAN_MCR_SUPV_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 2247 #define CAN_MCR_SUPV_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 2248 #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
AnnaBridge 171:3a7713b1edbc 2249 #define CAN_MCR_FRZACK_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 2250 #define CAN_MCR_FRZACK_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2251 #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
AnnaBridge 171:3a7713b1edbc 2252 #define CAN_MCR_SOFTRST_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 2253 #define CAN_MCR_SOFTRST_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 2254 #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
AnnaBridge 171:3a7713b1edbc 2255 #define CAN_MCR_WAKMSK_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 2256 #define CAN_MCR_WAKMSK_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 2257 #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
AnnaBridge 171:3a7713b1edbc 2258 #define CAN_MCR_NOTRDY_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 2259 #define CAN_MCR_NOTRDY_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 2260 #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
AnnaBridge 171:3a7713b1edbc 2261 #define CAN_MCR_HALT_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 2262 #define CAN_MCR_HALT_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2263 #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
AnnaBridge 171:3a7713b1edbc 2264 #define CAN_MCR_RFEN_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 2265 #define CAN_MCR_RFEN_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 2266 #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
AnnaBridge 171:3a7713b1edbc 2267 #define CAN_MCR_FRZ_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 2268 #define CAN_MCR_FRZ_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 2269 #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
AnnaBridge 171:3a7713b1edbc 2270 #define CAN_MCR_MDIS_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 2271 #define CAN_MCR_MDIS_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 2272 #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
AnnaBridge 171:3a7713b1edbc 2273
AnnaBridge 171:3a7713b1edbc 2274 /*! @name CTRL1 - Control 1 register */
AnnaBridge 171:3a7713b1edbc 2275 #define CAN_CTRL1_PROPSEG_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 2276 #define CAN_CTRL1_PROPSEG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2277 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
AnnaBridge 171:3a7713b1edbc 2278 #define CAN_CTRL1_LOM_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2279 #define CAN_CTRL1_LOM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2280 #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
AnnaBridge 171:3a7713b1edbc 2281 #define CAN_CTRL1_LBUF_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 2282 #define CAN_CTRL1_LBUF_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2283 #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
AnnaBridge 171:3a7713b1edbc 2284 #define CAN_CTRL1_TSYN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 2285 #define CAN_CTRL1_TSYN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2286 #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
AnnaBridge 171:3a7713b1edbc 2287 #define CAN_CTRL1_BOFFREC_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2288 #define CAN_CTRL1_BOFFREC_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2289 #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
AnnaBridge 171:3a7713b1edbc 2290 #define CAN_CTRL1_SMP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2291 #define CAN_CTRL1_SMP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2292 #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
AnnaBridge 171:3a7713b1edbc 2293 #define CAN_CTRL1_RWRNMSK_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 2294 #define CAN_CTRL1_RWRNMSK_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 2295 #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
AnnaBridge 171:3a7713b1edbc 2296 #define CAN_CTRL1_TWRNMSK_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 2297 #define CAN_CTRL1_TWRNMSK_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 2298 #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
AnnaBridge 171:3a7713b1edbc 2299 #define CAN_CTRL1_LPB_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 2300 #define CAN_CTRL1_LPB_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 2301 #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
AnnaBridge 171:3a7713b1edbc 2302 #define CAN_CTRL1_CLKSRC_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 2303 #define CAN_CTRL1_CLKSRC_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 2304 #define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
AnnaBridge 171:3a7713b1edbc 2305 #define CAN_CTRL1_ERRMSK_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 2306 #define CAN_CTRL1_ERRMSK_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 2307 #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
AnnaBridge 171:3a7713b1edbc 2308 #define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 2309 #define CAN_CTRL1_BOFFMSK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 2310 #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
AnnaBridge 171:3a7713b1edbc 2311 #define CAN_CTRL1_PSEG2_MASK (0x70000U)
AnnaBridge 171:3a7713b1edbc 2312 #define CAN_CTRL1_PSEG2_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2313 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
AnnaBridge 171:3a7713b1edbc 2314 #define CAN_CTRL1_PSEG1_MASK (0x380000U)
AnnaBridge 171:3a7713b1edbc 2315 #define CAN_CTRL1_PSEG1_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 2316 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
AnnaBridge 171:3a7713b1edbc 2317 #define CAN_CTRL1_RJW_MASK (0xC00000U)
AnnaBridge 171:3a7713b1edbc 2318 #define CAN_CTRL1_RJW_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 2319 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
AnnaBridge 171:3a7713b1edbc 2320 #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 2321 #define CAN_CTRL1_PRESDIV_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2322 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
AnnaBridge 171:3a7713b1edbc 2323
AnnaBridge 171:3a7713b1edbc 2324 /*! @name TIMER - Free Running Timer */
AnnaBridge 171:3a7713b1edbc 2325 #define CAN_TIMER_TIMER_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 2326 #define CAN_TIMER_TIMER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2327 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
AnnaBridge 171:3a7713b1edbc 2328
AnnaBridge 171:3a7713b1edbc 2329 /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
AnnaBridge 171:3a7713b1edbc 2330 #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2331 #define CAN_RXMGMASK_MG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2332 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
AnnaBridge 171:3a7713b1edbc 2333
AnnaBridge 171:3a7713b1edbc 2334 /*! @name RX14MASK - Rx 14 Mask register */
AnnaBridge 171:3a7713b1edbc 2335 #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2336 #define CAN_RX14MASK_RX14M_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2337 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
AnnaBridge 171:3a7713b1edbc 2338
AnnaBridge 171:3a7713b1edbc 2339 /*! @name RX15MASK - Rx 15 Mask register */
AnnaBridge 171:3a7713b1edbc 2340 #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2341 #define CAN_RX15MASK_RX15M_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2342 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
AnnaBridge 171:3a7713b1edbc 2343
AnnaBridge 171:3a7713b1edbc 2344 /*! @name ECR - Error Counter */
AnnaBridge 171:3a7713b1edbc 2345 #define CAN_ECR_TXERRCNT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2346 #define CAN_ECR_TXERRCNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2347 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
AnnaBridge 171:3a7713b1edbc 2348 #define CAN_ECR_RXERRCNT_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 2349 #define CAN_ECR_RXERRCNT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2350 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
AnnaBridge 171:3a7713b1edbc 2351
AnnaBridge 171:3a7713b1edbc 2352 /*! @name ESR1 - Error and Status 1 register */
AnnaBridge 171:3a7713b1edbc 2353 #define CAN_ESR1_WAKINT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2354 #define CAN_ESR1_WAKINT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2355 #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
AnnaBridge 171:3a7713b1edbc 2356 #define CAN_ESR1_ERRINT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2357 #define CAN_ESR1_ERRINT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2358 #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
AnnaBridge 171:3a7713b1edbc 2359 #define CAN_ESR1_BOFFINT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2360 #define CAN_ESR1_BOFFINT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2361 #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
AnnaBridge 171:3a7713b1edbc 2362 #define CAN_ESR1_RX_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2363 #define CAN_ESR1_RX_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2364 #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
AnnaBridge 171:3a7713b1edbc 2365 #define CAN_ESR1_FLTCONF_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 2366 #define CAN_ESR1_FLTCONF_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2367 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
AnnaBridge 171:3a7713b1edbc 2368 #define CAN_ESR1_TX_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2369 #define CAN_ESR1_TX_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2370 #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
AnnaBridge 171:3a7713b1edbc 2371 #define CAN_ESR1_IDLE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2372 #define CAN_ESR1_IDLE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2373 #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
AnnaBridge 171:3a7713b1edbc 2374 #define CAN_ESR1_RXWRN_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 2375 #define CAN_ESR1_RXWRN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2376 #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
AnnaBridge 171:3a7713b1edbc 2377 #define CAN_ESR1_TXWRN_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 2378 #define CAN_ESR1_TXWRN_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 2379 #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
AnnaBridge 171:3a7713b1edbc 2380 #define CAN_ESR1_STFERR_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 2381 #define CAN_ESR1_STFERR_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 2382 #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
AnnaBridge 171:3a7713b1edbc 2383 #define CAN_ESR1_FRMERR_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 2384 #define CAN_ESR1_FRMERR_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 2385 #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
AnnaBridge 171:3a7713b1edbc 2386 #define CAN_ESR1_CRCERR_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 2387 #define CAN_ESR1_CRCERR_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 2388 #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
AnnaBridge 171:3a7713b1edbc 2389 #define CAN_ESR1_ACKERR_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 2390 #define CAN_ESR1_ACKERR_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 2391 #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
AnnaBridge 171:3a7713b1edbc 2392 #define CAN_ESR1_BIT0ERR_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 2393 #define CAN_ESR1_BIT0ERR_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 2394 #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
AnnaBridge 171:3a7713b1edbc 2395 #define CAN_ESR1_BIT1ERR_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 2396 #define CAN_ESR1_BIT1ERR_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 2397 #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
AnnaBridge 171:3a7713b1edbc 2398 #define CAN_ESR1_RWRNINT_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 2399 #define CAN_ESR1_RWRNINT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2400 #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
AnnaBridge 171:3a7713b1edbc 2401 #define CAN_ESR1_TWRNINT_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 2402 #define CAN_ESR1_TWRNINT_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 2403 #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
AnnaBridge 171:3a7713b1edbc 2404 #define CAN_ESR1_SYNCH_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 2405 #define CAN_ESR1_SYNCH_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 2406 #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
AnnaBridge 171:3a7713b1edbc 2407
AnnaBridge 171:3a7713b1edbc 2408 /*! @name IMASK1 - Interrupt Masks 1 register */
AnnaBridge 171:3a7713b1edbc 2409 #define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2410 #define CAN_IMASK1_BUFLM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2411 #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
AnnaBridge 171:3a7713b1edbc 2412
AnnaBridge 171:3a7713b1edbc 2413 /*! @name IFLAG1 - Interrupt Flags 1 register */
AnnaBridge 171:3a7713b1edbc 2414 #define CAN_IFLAG1_BUF0I_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2415 #define CAN_IFLAG1_BUF0I_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2416 #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
AnnaBridge 171:3a7713b1edbc 2417 #define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
AnnaBridge 171:3a7713b1edbc 2418 #define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2419 #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
AnnaBridge 171:3a7713b1edbc 2420 #define CAN_IFLAG1_BUF5I_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 2421 #define CAN_IFLAG1_BUF5I_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2422 #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
AnnaBridge 171:3a7713b1edbc 2423 #define CAN_IFLAG1_BUF6I_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2424 #define CAN_IFLAG1_BUF6I_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2425 #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
AnnaBridge 171:3a7713b1edbc 2426 #define CAN_IFLAG1_BUF7I_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2427 #define CAN_IFLAG1_BUF7I_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2428 #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
AnnaBridge 171:3a7713b1edbc 2429 #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
AnnaBridge 171:3a7713b1edbc 2430 #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2431 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
AnnaBridge 171:3a7713b1edbc 2432
AnnaBridge 171:3a7713b1edbc 2433 /*! @name CTRL2 - Control 2 register */
AnnaBridge 171:3a7713b1edbc 2434 #define CAN_CTRL2_EACEN_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 2435 #define CAN_CTRL2_EACEN_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2436 #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
AnnaBridge 171:3a7713b1edbc 2437 #define CAN_CTRL2_RRS_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 2438 #define CAN_CTRL2_RRS_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 2439 #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
AnnaBridge 171:3a7713b1edbc 2440 #define CAN_CTRL2_MRP_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 2441 #define CAN_CTRL2_MRP_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 2442 #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
AnnaBridge 171:3a7713b1edbc 2443 #define CAN_CTRL2_TASD_MASK (0xF80000U)
AnnaBridge 171:3a7713b1edbc 2444 #define CAN_CTRL2_TASD_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 2445 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
AnnaBridge 171:3a7713b1edbc 2446 #define CAN_CTRL2_RFFN_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 2447 #define CAN_CTRL2_RFFN_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2448 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
AnnaBridge 171:3a7713b1edbc 2449 #define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 2450 #define CAN_CTRL2_WRMFRZ_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2451 #define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
AnnaBridge 171:3a7713b1edbc 2452
AnnaBridge 171:3a7713b1edbc 2453 /*! @name ESR2 - Error and Status 2 register */
AnnaBridge 171:3a7713b1edbc 2454 #define CAN_ESR2_IMB_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 2455 #define CAN_ESR2_IMB_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 2456 #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
AnnaBridge 171:3a7713b1edbc 2457 #define CAN_ESR2_VPS_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 2458 #define CAN_ESR2_VPS_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 2459 #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
AnnaBridge 171:3a7713b1edbc 2460 #define CAN_ESR2_LPTM_MASK (0x7F0000U)
AnnaBridge 171:3a7713b1edbc 2461 #define CAN_ESR2_LPTM_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2462 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
AnnaBridge 171:3a7713b1edbc 2463
AnnaBridge 171:3a7713b1edbc 2464 /*! @name CRCR - CRC Register */
AnnaBridge 171:3a7713b1edbc 2465 #define CAN_CRCR_TXCRC_MASK (0x7FFFU)
AnnaBridge 171:3a7713b1edbc 2466 #define CAN_CRCR_TXCRC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2467 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
AnnaBridge 171:3a7713b1edbc 2468 #define CAN_CRCR_MBCRC_MASK (0x7F0000U)
AnnaBridge 171:3a7713b1edbc 2469 #define CAN_CRCR_MBCRC_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2470 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
AnnaBridge 171:3a7713b1edbc 2471
AnnaBridge 171:3a7713b1edbc 2472 /*! @name RXFGMASK - Rx FIFO Global Mask register */
AnnaBridge 171:3a7713b1edbc 2473 #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2474 #define CAN_RXFGMASK_FGM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2475 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
AnnaBridge 171:3a7713b1edbc 2476
AnnaBridge 171:3a7713b1edbc 2477 /*! @name RXFIR - Rx FIFO Information Register */
AnnaBridge 171:3a7713b1edbc 2478 #define CAN_RXFIR_IDHIT_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 2479 #define CAN_RXFIR_IDHIT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2480 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
AnnaBridge 171:3a7713b1edbc 2481
AnnaBridge 171:3a7713b1edbc 2482 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register */
AnnaBridge 171:3a7713b1edbc 2483 #define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 2484 #define CAN_CS_TIME_STAMP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2485 #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
AnnaBridge 171:3a7713b1edbc 2486 #define CAN_CS_DLC_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 2487 #define CAN_CS_DLC_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2488 #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
AnnaBridge 171:3a7713b1edbc 2489 #define CAN_CS_RTR_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 2490 #define CAN_CS_RTR_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 2491 #define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
AnnaBridge 171:3a7713b1edbc 2492 #define CAN_CS_IDE_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 2493 #define CAN_CS_IDE_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 2494 #define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
AnnaBridge 171:3a7713b1edbc 2495 #define CAN_CS_SRR_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 2496 #define CAN_CS_SRR_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 2497 #define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
AnnaBridge 171:3a7713b1edbc 2498 #define CAN_CS_CODE_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 2499 #define CAN_CS_CODE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2500 #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
AnnaBridge 171:3a7713b1edbc 2501
AnnaBridge 171:3a7713b1edbc 2502 /* The count of CAN_CS */
AnnaBridge 171:3a7713b1edbc 2503 #define CAN_CS_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2504
AnnaBridge 171:3a7713b1edbc 2505 /*! @name ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register */
AnnaBridge 171:3a7713b1edbc 2506 #define CAN_ID_EXT_MASK (0x3FFFFU)
AnnaBridge 171:3a7713b1edbc 2507 #define CAN_ID_EXT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2508 #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
AnnaBridge 171:3a7713b1edbc 2509 #define CAN_ID_STD_MASK (0x1FFC0000U)
AnnaBridge 171:3a7713b1edbc 2510 #define CAN_ID_STD_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 2511 #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
AnnaBridge 171:3a7713b1edbc 2512 #define CAN_ID_PRIO_MASK (0xE0000000U)
AnnaBridge 171:3a7713b1edbc 2513 #define CAN_ID_PRIO_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 2514 #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
AnnaBridge 171:3a7713b1edbc 2515
AnnaBridge 171:3a7713b1edbc 2516 /* The count of CAN_ID */
AnnaBridge 171:3a7713b1edbc 2517 #define CAN_ID_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2518
AnnaBridge 171:3a7713b1edbc 2519 /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register */
AnnaBridge 171:3a7713b1edbc 2520 #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2521 #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2522 #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
AnnaBridge 171:3a7713b1edbc 2523 #define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 2524 #define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2525 #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
AnnaBridge 171:3a7713b1edbc 2526 #define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 2527 #define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2528 #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
AnnaBridge 171:3a7713b1edbc 2529 #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 2530 #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2531 #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
AnnaBridge 171:3a7713b1edbc 2532
AnnaBridge 171:3a7713b1edbc 2533 /* The count of CAN_WORD0 */
AnnaBridge 171:3a7713b1edbc 2534 #define CAN_WORD0_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2535
AnnaBridge 171:3a7713b1edbc 2536 /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register */
AnnaBridge 171:3a7713b1edbc 2537 #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2538 #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2539 #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
AnnaBridge 171:3a7713b1edbc 2540 #define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 2541 #define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2542 #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
AnnaBridge 171:3a7713b1edbc 2543 #define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 2544 #define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2545 #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
AnnaBridge 171:3a7713b1edbc 2546 #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 2547 #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2548 #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
AnnaBridge 171:3a7713b1edbc 2549
AnnaBridge 171:3a7713b1edbc 2550 /* The count of CAN_WORD1 */
AnnaBridge 171:3a7713b1edbc 2551 #define CAN_WORD1_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2552
AnnaBridge 171:3a7713b1edbc 2553 /*! @name RXIMR - Rx Individual Mask Registers */
AnnaBridge 171:3a7713b1edbc 2554 #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2555 #define CAN_RXIMR_MI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2556 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
AnnaBridge 171:3a7713b1edbc 2557
AnnaBridge 171:3a7713b1edbc 2558 /* The count of CAN_RXIMR */
AnnaBridge 171:3a7713b1edbc 2559 #define CAN_RXIMR_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2560
AnnaBridge 171:3a7713b1edbc 2561
AnnaBridge 171:3a7713b1edbc 2562 /*!
AnnaBridge 171:3a7713b1edbc 2563 * @}
AnnaBridge 171:3a7713b1edbc 2564 */ /* end of group CAN_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2565
AnnaBridge 171:3a7713b1edbc 2566
AnnaBridge 171:3a7713b1edbc 2567 /* CAN - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2568 /** Peripheral CAN0 base address */
AnnaBridge 171:3a7713b1edbc 2569 #define CAN0_BASE (0x40024000u)
AnnaBridge 171:3a7713b1edbc 2570 /** Peripheral CAN0 base pointer */
AnnaBridge 171:3a7713b1edbc 2571 #define CAN0 ((CAN_Type *)CAN0_BASE)
AnnaBridge 171:3a7713b1edbc 2572 /** Peripheral CAN1 base address */
AnnaBridge 171:3a7713b1edbc 2573 #define CAN1_BASE (0x400A4000u)
AnnaBridge 171:3a7713b1edbc 2574 /** Peripheral CAN1 base pointer */
AnnaBridge 171:3a7713b1edbc 2575 #define CAN1 ((CAN_Type *)CAN1_BASE)
AnnaBridge 171:3a7713b1edbc 2576 /** Array initializer of CAN peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 2577 #define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }
AnnaBridge 171:3a7713b1edbc 2578 /** Array initializer of CAN peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2579 #define CAN_BASE_PTRS { CAN0, CAN1 }
AnnaBridge 171:3a7713b1edbc 2580 /** Interrupt vectors for the CAN peripheral type */
AnnaBridge 171:3a7713b1edbc 2581 #define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn, CAN1_Rx_Warning_IRQn }
AnnaBridge 171:3a7713b1edbc 2582 #define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn, CAN1_Tx_Warning_IRQn }
AnnaBridge 171:3a7713b1edbc 2583 #define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn, CAN1_Wake_Up_IRQn }
AnnaBridge 171:3a7713b1edbc 2584 #define CAN_Error_IRQS { CAN0_Error_IRQn, CAN1_Error_IRQn }
AnnaBridge 171:3a7713b1edbc 2585 #define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn, CAN1_Bus_Off_IRQn }
AnnaBridge 171:3a7713b1edbc 2586 #define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn, CAN1_ORed_Message_buffer_IRQn }
AnnaBridge 171:3a7713b1edbc 2587
AnnaBridge 171:3a7713b1edbc 2588 /*!
AnnaBridge 171:3a7713b1edbc 2589 * @}
AnnaBridge 171:3a7713b1edbc 2590 */ /* end of group CAN_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2591
AnnaBridge 171:3a7713b1edbc 2592
AnnaBridge 171:3a7713b1edbc 2593 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2594 -- CAU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2595 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2596
AnnaBridge 171:3a7713b1edbc 2597 /*!
AnnaBridge 171:3a7713b1edbc 2598 * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2599 * @{
AnnaBridge 171:3a7713b1edbc 2600 */
AnnaBridge 171:3a7713b1edbc 2601
AnnaBridge 171:3a7713b1edbc 2602 /** CAU - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2603 typedef struct {
AnnaBridge 171:3a7713b1edbc 2604 __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2605 uint8_t RESERVED_0[2048];
AnnaBridge 171:3a7713b1edbc 2606 __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
AnnaBridge 171:3a7713b1edbc 2607 __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
AnnaBridge 171:3a7713b1edbc 2608 __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2609 uint8_t RESERVED_1[20];
AnnaBridge 171:3a7713b1edbc 2610 __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
AnnaBridge 171:3a7713b1edbc 2611 __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
AnnaBridge 171:3a7713b1edbc 2612 __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2613 uint8_t RESERVED_2[20];
AnnaBridge 171:3a7713b1edbc 2614 __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
AnnaBridge 171:3a7713b1edbc 2615 __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
AnnaBridge 171:3a7713b1edbc 2616 __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2617 uint8_t RESERVED_3[20];
AnnaBridge 171:3a7713b1edbc 2618 __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
AnnaBridge 171:3a7713b1edbc 2619 __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
AnnaBridge 171:3a7713b1edbc 2620 __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2621 uint8_t RESERVED_4[84];
AnnaBridge 171:3a7713b1edbc 2622 __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
AnnaBridge 171:3a7713b1edbc 2623 __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
AnnaBridge 171:3a7713b1edbc 2624 __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2625 uint8_t RESERVED_5[20];
AnnaBridge 171:3a7713b1edbc 2626 __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
AnnaBridge 171:3a7713b1edbc 2627 __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
AnnaBridge 171:3a7713b1edbc 2628 __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2629 uint8_t RESERVED_6[276];
AnnaBridge 171:3a7713b1edbc 2630 __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
AnnaBridge 171:3a7713b1edbc 2631 __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
AnnaBridge 171:3a7713b1edbc 2632 __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2633 uint8_t RESERVED_7[20];
AnnaBridge 171:3a7713b1edbc 2634 __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
AnnaBridge 171:3a7713b1edbc 2635 __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
AnnaBridge 171:3a7713b1edbc 2636 __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2637 } CAU_Type;
AnnaBridge 171:3a7713b1edbc 2638
AnnaBridge 171:3a7713b1edbc 2639 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2640 -- CAU Register Masks
AnnaBridge 171:3a7713b1edbc 2641 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2642
AnnaBridge 171:3a7713b1edbc 2643 /*!
AnnaBridge 171:3a7713b1edbc 2644 * @addtogroup CAU_Register_Masks CAU Register Masks
AnnaBridge 171:3a7713b1edbc 2645 * @{
AnnaBridge 171:3a7713b1edbc 2646 */
AnnaBridge 171:3a7713b1edbc 2647
AnnaBridge 171:3a7713b1edbc 2648 /*! @name DIRECT - Direct access register 0..Direct access register 15 */
AnnaBridge 171:3a7713b1edbc 2649 #define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2650 #define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2651 #define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
AnnaBridge 171:3a7713b1edbc 2652 #define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2653 #define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2654 #define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
AnnaBridge 171:3a7713b1edbc 2655 #define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2656 #define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2657 #define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
AnnaBridge 171:3a7713b1edbc 2658 #define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2659 #define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2660 #define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
AnnaBridge 171:3a7713b1edbc 2661 #define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2662 #define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2663 #define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
AnnaBridge 171:3a7713b1edbc 2664 #define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2665 #define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2666 #define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
AnnaBridge 171:3a7713b1edbc 2667 #define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2668 #define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2669 #define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
AnnaBridge 171:3a7713b1edbc 2670 #define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2671 #define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2672 #define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
AnnaBridge 171:3a7713b1edbc 2673 #define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2674 #define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2675 #define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
AnnaBridge 171:3a7713b1edbc 2676 #define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2677 #define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2678 #define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
AnnaBridge 171:3a7713b1edbc 2679 #define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2680 #define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2681 #define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
AnnaBridge 171:3a7713b1edbc 2682 #define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2683 #define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2684 #define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
AnnaBridge 171:3a7713b1edbc 2685 #define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2686 #define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2687 #define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
AnnaBridge 171:3a7713b1edbc 2688 #define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2689 #define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2690 #define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
AnnaBridge 171:3a7713b1edbc 2691 #define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2692 #define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2693 #define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
AnnaBridge 171:3a7713b1edbc 2694 #define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2695 #define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2696 #define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
AnnaBridge 171:3a7713b1edbc 2697
AnnaBridge 171:3a7713b1edbc 2698 /* The count of CAU_DIRECT */
AnnaBridge 171:3a7713b1edbc 2699 #define CAU_DIRECT_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2700
AnnaBridge 171:3a7713b1edbc 2701 /*! @name LDR_CASR - Status register - Load Register command */
AnnaBridge 171:3a7713b1edbc 2702 #define CAU_LDR_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2703 #define CAU_LDR_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2704 #define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 2705 #define CAU_LDR_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2706 #define CAU_LDR_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2707 #define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 2708 #define CAU_LDR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 2709 #define CAU_LDR_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2710 #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 2711
AnnaBridge 171:3a7713b1edbc 2712 /*! @name LDR_CAA - Accumulator register - Load Register command */
AnnaBridge 171:3a7713b1edbc 2713 #define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2714 #define CAU_LDR_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2715 #define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 2716
AnnaBridge 171:3a7713b1edbc 2717 /*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */
AnnaBridge 171:3a7713b1edbc 2718 #define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2719 #define CAU_LDR_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2720 #define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 2721 #define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2722 #define CAU_LDR_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2723 #define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 2724 #define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2725 #define CAU_LDR_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2726 #define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 2727 #define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2728 #define CAU_LDR_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2729 #define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 2730 #define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2731 #define CAU_LDR_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2732 #define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 2733 #define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2734 #define CAU_LDR_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2735 #define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 2736 #define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2737 #define CAU_LDR_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2738 #define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 2739 #define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2740 #define CAU_LDR_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2741 #define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 2742 #define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2743 #define CAU_LDR_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2744 #define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 2745
AnnaBridge 171:3a7713b1edbc 2746 /* The count of CAU_LDR_CA */
AnnaBridge 171:3a7713b1edbc 2747 #define CAU_LDR_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 2748
AnnaBridge 171:3a7713b1edbc 2749 /*! @name STR_CASR - Status register - Store Register command */
AnnaBridge 171:3a7713b1edbc 2750 #define CAU_STR_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2751 #define CAU_STR_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2752 #define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 2753 #define CAU_STR_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2754 #define CAU_STR_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2755 #define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 2756 #define CAU_STR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 2757 #define CAU_STR_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2758 #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 2759
AnnaBridge 171:3a7713b1edbc 2760 /*! @name STR_CAA - Accumulator register - Store Register command */
AnnaBridge 171:3a7713b1edbc 2761 #define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2762 #define CAU_STR_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2763 #define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 2764
AnnaBridge 171:3a7713b1edbc 2765 /*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */
AnnaBridge 171:3a7713b1edbc 2766 #define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2767 #define CAU_STR_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2768 #define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 2769 #define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2770 #define CAU_STR_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2771 #define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 2772 #define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2773 #define CAU_STR_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2774 #define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 2775 #define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2776 #define CAU_STR_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2777 #define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 2778 #define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2779 #define CAU_STR_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2780 #define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 2781 #define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2782 #define CAU_STR_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2783 #define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 2784 #define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2785 #define CAU_STR_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2786 #define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 2787 #define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2788 #define CAU_STR_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2789 #define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 2790 #define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2791 #define CAU_STR_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2792 #define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 2793
AnnaBridge 171:3a7713b1edbc 2794 /* The count of CAU_STR_CA */
AnnaBridge 171:3a7713b1edbc 2795 #define CAU_STR_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 2796
AnnaBridge 171:3a7713b1edbc 2797 /*! @name ADR_CASR - Status register - Add Register command */
AnnaBridge 171:3a7713b1edbc 2798 #define CAU_ADR_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2799 #define CAU_ADR_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2800 #define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 2801 #define CAU_ADR_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2802 #define CAU_ADR_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2803 #define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 2804 #define CAU_ADR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 2805 #define CAU_ADR_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2806 #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 2807
AnnaBridge 171:3a7713b1edbc 2808 /*! @name ADR_CAA - Accumulator register - Add to register command */
AnnaBridge 171:3a7713b1edbc 2809 #define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2810 #define CAU_ADR_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2811 #define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 2812
AnnaBridge 171:3a7713b1edbc 2813 /*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */
AnnaBridge 171:3a7713b1edbc 2814 #define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2815 #define CAU_ADR_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2816 #define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 2817 #define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2818 #define CAU_ADR_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2819 #define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 2820 #define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2821 #define CAU_ADR_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2822 #define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 2823 #define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2824 #define CAU_ADR_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2825 #define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 2826 #define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2827 #define CAU_ADR_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2828 #define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 2829 #define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2830 #define CAU_ADR_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2831 #define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 2832 #define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2833 #define CAU_ADR_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2834 #define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 2835 #define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2836 #define CAU_ADR_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2837 #define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 2838 #define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2839 #define CAU_ADR_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2840 #define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 2841
AnnaBridge 171:3a7713b1edbc 2842 /* The count of CAU_ADR_CA */
AnnaBridge 171:3a7713b1edbc 2843 #define CAU_ADR_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 2844
AnnaBridge 171:3a7713b1edbc 2845 /*! @name RADR_CASR - Status register - Reverse and Add to Register command */
AnnaBridge 171:3a7713b1edbc 2846 #define CAU_RADR_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2847 #define CAU_RADR_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2848 #define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 2849 #define CAU_RADR_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2850 #define CAU_RADR_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2851 #define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 2852 #define CAU_RADR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 2853 #define CAU_RADR_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2854 #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 2855
AnnaBridge 171:3a7713b1edbc 2856 /*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */
AnnaBridge 171:3a7713b1edbc 2857 #define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2858 #define CAU_RADR_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2859 #define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 2860
AnnaBridge 171:3a7713b1edbc 2861 /*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */
AnnaBridge 171:3a7713b1edbc 2862 #define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2863 #define CAU_RADR_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2864 #define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 2865 #define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2866 #define CAU_RADR_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2867 #define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 2868 #define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2869 #define CAU_RADR_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2870 #define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 2871 #define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2872 #define CAU_RADR_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2873 #define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 2874 #define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2875 #define CAU_RADR_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2876 #define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 2877 #define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2878 #define CAU_RADR_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2879 #define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 2880 #define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2881 #define CAU_RADR_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2882 #define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 2883 #define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2884 #define CAU_RADR_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2885 #define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 2886 #define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2887 #define CAU_RADR_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2888 #define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 2889
AnnaBridge 171:3a7713b1edbc 2890 /* The count of CAU_RADR_CA */
AnnaBridge 171:3a7713b1edbc 2891 #define CAU_RADR_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 2892
AnnaBridge 171:3a7713b1edbc 2893 /*! @name XOR_CASR - Status register - Exclusive Or command */
AnnaBridge 171:3a7713b1edbc 2894 #define CAU_XOR_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2895 #define CAU_XOR_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2896 #define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 2897 #define CAU_XOR_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2898 #define CAU_XOR_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2899 #define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 2900 #define CAU_XOR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 2901 #define CAU_XOR_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2902 #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 2903
AnnaBridge 171:3a7713b1edbc 2904 /*! @name XOR_CAA - Accumulator register - Exclusive Or command */
AnnaBridge 171:3a7713b1edbc 2905 #define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2906 #define CAU_XOR_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2907 #define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 2908
AnnaBridge 171:3a7713b1edbc 2909 /*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */
AnnaBridge 171:3a7713b1edbc 2910 #define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2911 #define CAU_XOR_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2912 #define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 2913 #define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2914 #define CAU_XOR_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2915 #define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 2916 #define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2917 #define CAU_XOR_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2918 #define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 2919 #define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2920 #define CAU_XOR_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2921 #define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 2922 #define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2923 #define CAU_XOR_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2924 #define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 2925 #define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2926 #define CAU_XOR_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2927 #define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 2928 #define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2929 #define CAU_XOR_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2930 #define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 2931 #define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2932 #define CAU_XOR_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2933 #define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 2934 #define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2935 #define CAU_XOR_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2936 #define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 2937
AnnaBridge 171:3a7713b1edbc 2938 /* The count of CAU_XOR_CA */
AnnaBridge 171:3a7713b1edbc 2939 #define CAU_XOR_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 2940
AnnaBridge 171:3a7713b1edbc 2941 /*! @name ROTL_CASR - Status register - Rotate Left command */
AnnaBridge 171:3a7713b1edbc 2942 #define CAU_ROTL_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2943 #define CAU_ROTL_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2944 #define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 2945 #define CAU_ROTL_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2946 #define CAU_ROTL_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2947 #define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 2948 #define CAU_ROTL_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 2949 #define CAU_ROTL_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2950 #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 2951
AnnaBridge 171:3a7713b1edbc 2952 /*! @name ROTL_CAA - Accumulator register - Rotate Left command */
AnnaBridge 171:3a7713b1edbc 2953 #define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2954 #define CAU_ROTL_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2955 #define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 2956
AnnaBridge 171:3a7713b1edbc 2957 /*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */
AnnaBridge 171:3a7713b1edbc 2958 #define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2959 #define CAU_ROTL_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2960 #define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 2961 #define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2962 #define CAU_ROTL_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2963 #define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 2964 #define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2965 #define CAU_ROTL_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2966 #define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 2967 #define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2968 #define CAU_ROTL_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2969 #define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 2970 #define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2971 #define CAU_ROTL_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2972 #define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 2973 #define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2974 #define CAU_ROTL_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2975 #define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 2976 #define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2977 #define CAU_ROTL_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2978 #define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 2979 #define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2980 #define CAU_ROTL_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2981 #define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 2982 #define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2983 #define CAU_ROTL_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2984 #define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 2985
AnnaBridge 171:3a7713b1edbc 2986 /* The count of CAU_ROTL_CA */
AnnaBridge 171:3a7713b1edbc 2987 #define CAU_ROTL_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 2988
AnnaBridge 171:3a7713b1edbc 2989 /*! @name AESC_CASR - Status register - AES Column Operation command */
AnnaBridge 171:3a7713b1edbc 2990 #define CAU_AESC_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2991 #define CAU_AESC_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2992 #define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 2993 #define CAU_AESC_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2994 #define CAU_AESC_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2995 #define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 2996 #define CAU_AESC_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 2997 #define CAU_AESC_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2998 #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 2999
AnnaBridge 171:3a7713b1edbc 3000 /*! @name AESC_CAA - Accumulator register - AES Column Operation command */
AnnaBridge 171:3a7713b1edbc 3001 #define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3002 #define CAU_AESC_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3003 #define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 3004
AnnaBridge 171:3a7713b1edbc 3005 /*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */
AnnaBridge 171:3a7713b1edbc 3006 #define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3007 #define CAU_AESC_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3008 #define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 3009 #define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3010 #define CAU_AESC_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3011 #define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 3012 #define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3013 #define CAU_AESC_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3014 #define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 3015 #define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3016 #define CAU_AESC_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3017 #define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 3018 #define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3019 #define CAU_AESC_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3020 #define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 3021 #define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3022 #define CAU_AESC_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3023 #define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 3024 #define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3025 #define CAU_AESC_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3026 #define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 3027 #define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3028 #define CAU_AESC_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3029 #define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 3030 #define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3031 #define CAU_AESC_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3032 #define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 3033
AnnaBridge 171:3a7713b1edbc 3034 /* The count of CAU_AESC_CA */
AnnaBridge 171:3a7713b1edbc 3035 #define CAU_AESC_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 3036
AnnaBridge 171:3a7713b1edbc 3037 /*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */
AnnaBridge 171:3a7713b1edbc 3038 #define CAU_AESIC_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3039 #define CAU_AESIC_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3040 #define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 3041 #define CAU_AESIC_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3042 #define CAU_AESIC_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3043 #define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 3044 #define CAU_AESIC_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 3045 #define CAU_AESIC_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 3046 #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 3047
AnnaBridge 171:3a7713b1edbc 3048 /*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */
AnnaBridge 171:3a7713b1edbc 3049 #define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3050 #define CAU_AESIC_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3051 #define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 3052
AnnaBridge 171:3a7713b1edbc 3053 /*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */
AnnaBridge 171:3a7713b1edbc 3054 #define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3055 #define CAU_AESIC_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3056 #define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 3057 #define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3058 #define CAU_AESIC_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3059 #define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 3060 #define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3061 #define CAU_AESIC_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3062 #define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 3063 #define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3064 #define CAU_AESIC_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3065 #define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 3066 #define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3067 #define CAU_AESIC_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3068 #define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 3069 #define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3070 #define CAU_AESIC_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3071 #define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 3072 #define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3073 #define CAU_AESIC_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3074 #define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 3075 #define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3076 #define CAU_AESIC_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3077 #define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 3078 #define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3079 #define CAU_AESIC_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3080 #define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 3081
AnnaBridge 171:3a7713b1edbc 3082 /* The count of CAU_AESIC_CA */
AnnaBridge 171:3a7713b1edbc 3083 #define CAU_AESIC_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 3084
AnnaBridge 171:3a7713b1edbc 3085
AnnaBridge 171:3a7713b1edbc 3086 /*!
AnnaBridge 171:3a7713b1edbc 3087 * @}
AnnaBridge 171:3a7713b1edbc 3088 */ /* end of group CAU_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3089
AnnaBridge 171:3a7713b1edbc 3090
AnnaBridge 171:3a7713b1edbc 3091 /* CAU - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3092 /** Peripheral CAU base address */
AnnaBridge 171:3a7713b1edbc 3093 #define CAU_BASE (0xE0081000u)
AnnaBridge 171:3a7713b1edbc 3094 /** Peripheral CAU base pointer */
AnnaBridge 171:3a7713b1edbc 3095 #define CAU ((CAU_Type *)CAU_BASE)
AnnaBridge 171:3a7713b1edbc 3096 /** Array initializer of CAU peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3097 #define CAU_BASE_ADDRS { CAU_BASE }
AnnaBridge 171:3a7713b1edbc 3098 /** Array initializer of CAU peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3099 #define CAU_BASE_PTRS { CAU }
AnnaBridge 171:3a7713b1edbc 3100
AnnaBridge 171:3a7713b1edbc 3101 /*!
AnnaBridge 171:3a7713b1edbc 3102 * @}
AnnaBridge 171:3a7713b1edbc 3103 */ /* end of group CAU_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3104
AnnaBridge 171:3a7713b1edbc 3105
AnnaBridge 171:3a7713b1edbc 3106 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3107 -- CMP Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3108 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3109
AnnaBridge 171:3a7713b1edbc 3110 /*!
AnnaBridge 171:3a7713b1edbc 3111 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3112 * @{
AnnaBridge 171:3a7713b1edbc 3113 */
AnnaBridge 171:3a7713b1edbc 3114
AnnaBridge 171:3a7713b1edbc 3115 /** CMP - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3116 typedef struct {
AnnaBridge 171:3a7713b1edbc 3117 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3118 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 3119 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 3120 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 3121 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3122 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 3123 } CMP_Type;
AnnaBridge 171:3a7713b1edbc 3124
AnnaBridge 171:3a7713b1edbc 3125 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3126 -- CMP Register Masks
AnnaBridge 171:3a7713b1edbc 3127 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3128
AnnaBridge 171:3a7713b1edbc 3129 /*!
AnnaBridge 171:3a7713b1edbc 3130 * @addtogroup CMP_Register_Masks CMP Register Masks
AnnaBridge 171:3a7713b1edbc 3131 * @{
AnnaBridge 171:3a7713b1edbc 3132 */
AnnaBridge 171:3a7713b1edbc 3133
AnnaBridge 171:3a7713b1edbc 3134 /*! @name CR0 - CMP Control Register 0 */
AnnaBridge 171:3a7713b1edbc 3135 #define CMP_CR0_HYSTCTR_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 3136 #define CMP_CR0_HYSTCTR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3137 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
AnnaBridge 171:3a7713b1edbc 3138 #define CMP_CR0_FILTER_CNT_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 3139 #define CMP_CR0_FILTER_CNT_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3140 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
AnnaBridge 171:3a7713b1edbc 3141
AnnaBridge 171:3a7713b1edbc 3142 /*! @name CR1 - CMP Control Register 1 */
AnnaBridge 171:3a7713b1edbc 3143 #define CMP_CR1_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3144 #define CMP_CR1_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3145 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
AnnaBridge 171:3a7713b1edbc 3146 #define CMP_CR1_OPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3147 #define CMP_CR1_OPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3148 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
AnnaBridge 171:3a7713b1edbc 3149 #define CMP_CR1_COS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3150 #define CMP_CR1_COS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3151 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
AnnaBridge 171:3a7713b1edbc 3152 #define CMP_CR1_INV_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3153 #define CMP_CR1_INV_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3154 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
AnnaBridge 171:3a7713b1edbc 3155 #define CMP_CR1_PMODE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3156 #define CMP_CR1_PMODE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3157 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
AnnaBridge 171:3a7713b1edbc 3158 #define CMP_CR1_TRIGM_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3159 #define CMP_CR1_TRIGM_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3160 #define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
AnnaBridge 171:3a7713b1edbc 3161 #define CMP_CR1_WE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3162 #define CMP_CR1_WE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3163 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
AnnaBridge 171:3a7713b1edbc 3164 #define CMP_CR1_SE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3165 #define CMP_CR1_SE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3166 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
AnnaBridge 171:3a7713b1edbc 3167
AnnaBridge 171:3a7713b1edbc 3168 /*! @name FPR - CMP Filter Period Register */
AnnaBridge 171:3a7713b1edbc 3169 #define CMP_FPR_FILT_PER_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3170 #define CMP_FPR_FILT_PER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3171 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
AnnaBridge 171:3a7713b1edbc 3172
AnnaBridge 171:3a7713b1edbc 3173 /*! @name SCR - CMP Status and Control Register */
AnnaBridge 171:3a7713b1edbc 3174 #define CMP_SCR_COUT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3175 #define CMP_SCR_COUT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3176 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
AnnaBridge 171:3a7713b1edbc 3177 #define CMP_SCR_CFF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3178 #define CMP_SCR_CFF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3179 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
AnnaBridge 171:3a7713b1edbc 3180 #define CMP_SCR_CFR_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3181 #define CMP_SCR_CFR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3182 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
AnnaBridge 171:3a7713b1edbc 3183 #define CMP_SCR_IEF_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3184 #define CMP_SCR_IEF_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3185 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
AnnaBridge 171:3a7713b1edbc 3186 #define CMP_SCR_IER_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3187 #define CMP_SCR_IER_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3188 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
AnnaBridge 171:3a7713b1edbc 3189 #define CMP_SCR_DMAEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3190 #define CMP_SCR_DMAEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3191 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 3192
AnnaBridge 171:3a7713b1edbc 3193 /*! @name DACCR - DAC Control Register */
AnnaBridge 171:3a7713b1edbc 3194 #define CMP_DACCR_VOSEL_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 3195 #define CMP_DACCR_VOSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3196 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
AnnaBridge 171:3a7713b1edbc 3197 #define CMP_DACCR_VRSEL_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3198 #define CMP_DACCR_VRSEL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3199 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
AnnaBridge 171:3a7713b1edbc 3200 #define CMP_DACCR_DACEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3201 #define CMP_DACCR_DACEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3202 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
AnnaBridge 171:3a7713b1edbc 3203
AnnaBridge 171:3a7713b1edbc 3204 /*! @name MUXCR - MUX Control Register */
AnnaBridge 171:3a7713b1edbc 3205 #define CMP_MUXCR_MSEL_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 3206 #define CMP_MUXCR_MSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3207 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
AnnaBridge 171:3a7713b1edbc 3208 #define CMP_MUXCR_PSEL_MASK (0x38U)
AnnaBridge 171:3a7713b1edbc 3209 #define CMP_MUXCR_PSEL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3210 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
AnnaBridge 171:3a7713b1edbc 3211 #define CMP_MUXCR_PSTM_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3212 #define CMP_MUXCR_PSTM_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3213 #define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
AnnaBridge 171:3a7713b1edbc 3214
AnnaBridge 171:3a7713b1edbc 3215
AnnaBridge 171:3a7713b1edbc 3216 /*!
AnnaBridge 171:3a7713b1edbc 3217 * @}
AnnaBridge 171:3a7713b1edbc 3218 */ /* end of group CMP_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3219
AnnaBridge 171:3a7713b1edbc 3220
AnnaBridge 171:3a7713b1edbc 3221 /* CMP - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3222 /** Peripheral CMP0 base address */
AnnaBridge 171:3a7713b1edbc 3223 #define CMP0_BASE (0x40073000u)
AnnaBridge 171:3a7713b1edbc 3224 /** Peripheral CMP0 base pointer */
AnnaBridge 171:3a7713b1edbc 3225 #define CMP0 ((CMP_Type *)CMP0_BASE)
AnnaBridge 171:3a7713b1edbc 3226 /** Peripheral CMP1 base address */
AnnaBridge 171:3a7713b1edbc 3227 #define CMP1_BASE (0x40073008u)
AnnaBridge 171:3a7713b1edbc 3228 /** Peripheral CMP1 base pointer */
AnnaBridge 171:3a7713b1edbc 3229 #define CMP1 ((CMP_Type *)CMP1_BASE)
AnnaBridge 171:3a7713b1edbc 3230 /** Peripheral CMP2 base address */
AnnaBridge 171:3a7713b1edbc 3231 #define CMP2_BASE (0x40073010u)
AnnaBridge 171:3a7713b1edbc 3232 /** Peripheral CMP2 base pointer */
AnnaBridge 171:3a7713b1edbc 3233 #define CMP2 ((CMP_Type *)CMP2_BASE)
AnnaBridge 171:3a7713b1edbc 3234 /** Peripheral CMP3 base address */
AnnaBridge 171:3a7713b1edbc 3235 #define CMP3_BASE (0x40073018u)
AnnaBridge 171:3a7713b1edbc 3236 /** Peripheral CMP3 base pointer */
AnnaBridge 171:3a7713b1edbc 3237 #define CMP3 ((CMP_Type *)CMP3_BASE)
AnnaBridge 171:3a7713b1edbc 3238 /** Array initializer of CMP peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3239 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE, CMP3_BASE }
AnnaBridge 171:3a7713b1edbc 3240 /** Array initializer of CMP peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3241 #define CMP_BASE_PTRS { CMP0, CMP1, CMP2, CMP3 }
AnnaBridge 171:3a7713b1edbc 3242 /** Interrupt vectors for the CMP peripheral type */
AnnaBridge 171:3a7713b1edbc 3243 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn, CMP3_IRQn }
AnnaBridge 171:3a7713b1edbc 3244
AnnaBridge 171:3a7713b1edbc 3245 /*!
AnnaBridge 171:3a7713b1edbc 3246 * @}
AnnaBridge 171:3a7713b1edbc 3247 */ /* end of group CMP_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3248
AnnaBridge 171:3a7713b1edbc 3249
AnnaBridge 171:3a7713b1edbc 3250 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3251 -- CMT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3252 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3253
AnnaBridge 171:3a7713b1edbc 3254 /*!
AnnaBridge 171:3a7713b1edbc 3255 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3256 * @{
AnnaBridge 171:3a7713b1edbc 3257 */
AnnaBridge 171:3a7713b1edbc 3258
AnnaBridge 171:3a7713b1edbc 3259 /** CMT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3260 typedef struct {
AnnaBridge 171:3a7713b1edbc 3261 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3262 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 3263 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 3264 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 3265 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3266 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 3267 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 3268 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 3269 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3270 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 3271 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 3272 __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 3273 } CMT_Type;
AnnaBridge 171:3a7713b1edbc 3274
AnnaBridge 171:3a7713b1edbc 3275 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3276 -- CMT Register Masks
AnnaBridge 171:3a7713b1edbc 3277 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3278
AnnaBridge 171:3a7713b1edbc 3279 /*!
AnnaBridge 171:3a7713b1edbc 3280 * @addtogroup CMT_Register_Masks CMT Register Masks
AnnaBridge 171:3a7713b1edbc 3281 * @{
AnnaBridge 171:3a7713b1edbc 3282 */
AnnaBridge 171:3a7713b1edbc 3283
AnnaBridge 171:3a7713b1edbc 3284 /*! @name CGH1 - CMT Carrier Generator High Data Register 1 */
AnnaBridge 171:3a7713b1edbc 3285 #define CMT_CGH1_PH_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3286 #define CMT_CGH1_PH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3287 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
AnnaBridge 171:3a7713b1edbc 3288
AnnaBridge 171:3a7713b1edbc 3289 /*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */
AnnaBridge 171:3a7713b1edbc 3290 #define CMT_CGL1_PL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3291 #define CMT_CGL1_PL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3292 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
AnnaBridge 171:3a7713b1edbc 3293
AnnaBridge 171:3a7713b1edbc 3294 /*! @name CGH2 - CMT Carrier Generator High Data Register 2 */
AnnaBridge 171:3a7713b1edbc 3295 #define CMT_CGH2_SH_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3296 #define CMT_CGH2_SH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3297 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
AnnaBridge 171:3a7713b1edbc 3298
AnnaBridge 171:3a7713b1edbc 3299 /*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */
AnnaBridge 171:3a7713b1edbc 3300 #define CMT_CGL2_SL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3301 #define CMT_CGL2_SL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3302 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
AnnaBridge 171:3a7713b1edbc 3303
AnnaBridge 171:3a7713b1edbc 3304 /*! @name OC - CMT Output Control Register */
AnnaBridge 171:3a7713b1edbc 3305 #define CMT_OC_IROPEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3306 #define CMT_OC_IROPEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3307 #define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
AnnaBridge 171:3a7713b1edbc 3308 #define CMT_OC_CMTPOL_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3309 #define CMT_OC_CMTPOL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3310 #define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
AnnaBridge 171:3a7713b1edbc 3311 #define CMT_OC_IROL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3312 #define CMT_OC_IROL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3313 #define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
AnnaBridge 171:3a7713b1edbc 3314
AnnaBridge 171:3a7713b1edbc 3315 /*! @name MSC - CMT Modulator Status and Control Register */
AnnaBridge 171:3a7713b1edbc 3316 #define CMT_MSC_MCGEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3317 #define CMT_MSC_MCGEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3318 #define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
AnnaBridge 171:3a7713b1edbc 3319 #define CMT_MSC_EOCIE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3320 #define CMT_MSC_EOCIE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3321 #define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
AnnaBridge 171:3a7713b1edbc 3322 #define CMT_MSC_FSK_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3323 #define CMT_MSC_FSK_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3324 #define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
AnnaBridge 171:3a7713b1edbc 3325 #define CMT_MSC_BASE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3326 #define CMT_MSC_BASE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3327 #define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
AnnaBridge 171:3a7713b1edbc 3328 #define CMT_MSC_EXSPC_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3329 #define CMT_MSC_EXSPC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3330 #define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
AnnaBridge 171:3a7713b1edbc 3331 #define CMT_MSC_CMTDIV_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 3332 #define CMT_MSC_CMTDIV_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3333 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
AnnaBridge 171:3a7713b1edbc 3334 #define CMT_MSC_EOCF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3335 #define CMT_MSC_EOCF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3336 #define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
AnnaBridge 171:3a7713b1edbc 3337
AnnaBridge 171:3a7713b1edbc 3338 /*! @name CMD1 - CMT Modulator Data Register Mark High */
AnnaBridge 171:3a7713b1edbc 3339 #define CMT_CMD1_MB_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3340 #define CMT_CMD1_MB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3341 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
AnnaBridge 171:3a7713b1edbc 3342
AnnaBridge 171:3a7713b1edbc 3343 /*! @name CMD2 - CMT Modulator Data Register Mark Low */
AnnaBridge 171:3a7713b1edbc 3344 #define CMT_CMD2_MB_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3345 #define CMT_CMD2_MB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3346 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
AnnaBridge 171:3a7713b1edbc 3347
AnnaBridge 171:3a7713b1edbc 3348 /*! @name CMD3 - CMT Modulator Data Register Space High */
AnnaBridge 171:3a7713b1edbc 3349 #define CMT_CMD3_SB_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3350 #define CMT_CMD3_SB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3351 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
AnnaBridge 171:3a7713b1edbc 3352
AnnaBridge 171:3a7713b1edbc 3353 /*! @name CMD4 - CMT Modulator Data Register Space Low */
AnnaBridge 171:3a7713b1edbc 3354 #define CMT_CMD4_SB_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3355 #define CMT_CMD4_SB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3356 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
AnnaBridge 171:3a7713b1edbc 3357
AnnaBridge 171:3a7713b1edbc 3358 /*! @name PPS - CMT Primary Prescaler Register */
AnnaBridge 171:3a7713b1edbc 3359 #define CMT_PPS_PPSDIV_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 3360 #define CMT_PPS_PPSDIV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3361 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
AnnaBridge 171:3a7713b1edbc 3362
AnnaBridge 171:3a7713b1edbc 3363 /*! @name DMA - CMT Direct Memory Access Register */
AnnaBridge 171:3a7713b1edbc 3364 #define CMT_DMA_DMA_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3365 #define CMT_DMA_DMA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3366 #define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
AnnaBridge 171:3a7713b1edbc 3367
AnnaBridge 171:3a7713b1edbc 3368
AnnaBridge 171:3a7713b1edbc 3369 /*!
AnnaBridge 171:3a7713b1edbc 3370 * @}
AnnaBridge 171:3a7713b1edbc 3371 */ /* end of group CMT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3372
AnnaBridge 171:3a7713b1edbc 3373
AnnaBridge 171:3a7713b1edbc 3374 /* CMT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3375 /** Peripheral CMT base address */
AnnaBridge 171:3a7713b1edbc 3376 #define CMT_BASE (0x40062000u)
AnnaBridge 171:3a7713b1edbc 3377 /** Peripheral CMT base pointer */
AnnaBridge 171:3a7713b1edbc 3378 #define CMT ((CMT_Type *)CMT_BASE)
AnnaBridge 171:3a7713b1edbc 3379 /** Array initializer of CMT peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3380 #define CMT_BASE_ADDRS { CMT_BASE }
AnnaBridge 171:3a7713b1edbc 3381 /** Array initializer of CMT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3382 #define CMT_BASE_PTRS { CMT }
AnnaBridge 171:3a7713b1edbc 3383 /** Interrupt vectors for the CMT peripheral type */
AnnaBridge 171:3a7713b1edbc 3384 #define CMT_IRQS { CMT_IRQn }
AnnaBridge 171:3a7713b1edbc 3385
AnnaBridge 171:3a7713b1edbc 3386 /*!
AnnaBridge 171:3a7713b1edbc 3387 * @}
AnnaBridge 171:3a7713b1edbc 3388 */ /* end of group CMT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3389
AnnaBridge 171:3a7713b1edbc 3390
AnnaBridge 171:3a7713b1edbc 3391 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3392 -- CRC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3393 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3394
AnnaBridge 171:3a7713b1edbc 3395 /*!
AnnaBridge 171:3a7713b1edbc 3396 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3397 * @{
AnnaBridge 171:3a7713b1edbc 3398 */
AnnaBridge 171:3a7713b1edbc 3399
AnnaBridge 171:3a7713b1edbc 3400 /** CRC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3401 typedef struct {
AnnaBridge 171:3a7713b1edbc 3402 union { /* offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3403 struct { /* offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3404 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3405 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 3406 } ACCESS16BIT;
AnnaBridge 171:3a7713b1edbc 3407 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3408 struct { /* offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3409 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3410 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 3411 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 3412 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 3413 } ACCESS8BIT;
AnnaBridge 171:3a7713b1edbc 3414 };
AnnaBridge 171:3a7713b1edbc 3415 union { /* offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3416 struct { /* offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3417 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3418 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 3419 } GPOLY_ACCESS16BIT;
AnnaBridge 171:3a7713b1edbc 3420 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3421 struct { /* offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3422 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3423 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 3424 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 3425 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 3426 } GPOLY_ACCESS8BIT;
AnnaBridge 171:3a7713b1edbc 3427 };
AnnaBridge 171:3a7713b1edbc 3428 union { /* offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3429 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3430 struct { /* offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3431 uint8_t RESERVED_0[3];
AnnaBridge 171:3a7713b1edbc 3432 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
AnnaBridge 171:3a7713b1edbc 3433 } CTRL_ACCESS8BIT;
AnnaBridge 171:3a7713b1edbc 3434 };
AnnaBridge 171:3a7713b1edbc 3435 } CRC_Type;
AnnaBridge 171:3a7713b1edbc 3436
AnnaBridge 171:3a7713b1edbc 3437 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3438 -- CRC Register Masks
AnnaBridge 171:3a7713b1edbc 3439 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3440
AnnaBridge 171:3a7713b1edbc 3441 /*!
AnnaBridge 171:3a7713b1edbc 3442 * @addtogroup CRC_Register_Masks CRC Register Masks
AnnaBridge 171:3a7713b1edbc 3443 * @{
AnnaBridge 171:3a7713b1edbc 3444 */
AnnaBridge 171:3a7713b1edbc 3445
AnnaBridge 171:3a7713b1edbc 3446 /*! @name DATAL - CRC_DATAL register. */
AnnaBridge 171:3a7713b1edbc 3447 #define CRC_DATAL_DATAL_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 3448 #define CRC_DATAL_DATAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3449 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
AnnaBridge 171:3a7713b1edbc 3450
AnnaBridge 171:3a7713b1edbc 3451 /*! @name DATAH - CRC_DATAH register. */
AnnaBridge 171:3a7713b1edbc 3452 #define CRC_DATAH_DATAH_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 3453 #define CRC_DATAH_DATAH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3454 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
AnnaBridge 171:3a7713b1edbc 3455
AnnaBridge 171:3a7713b1edbc 3456 /*! @name DATA - CRC Data register */
AnnaBridge 171:3a7713b1edbc 3457 #define CRC_DATA_LL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3458 #define CRC_DATA_LL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3459 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
AnnaBridge 171:3a7713b1edbc 3460 #define CRC_DATA_LU_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 3461 #define CRC_DATA_LU_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 3462 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
AnnaBridge 171:3a7713b1edbc 3463 #define CRC_DATA_HL_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 3464 #define CRC_DATA_HL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3465 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
AnnaBridge 171:3a7713b1edbc 3466 #define CRC_DATA_HU_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 3467 #define CRC_DATA_HU_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 3468 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
AnnaBridge 171:3a7713b1edbc 3469
AnnaBridge 171:3a7713b1edbc 3470 /*! @name DATALL - CRC_DATALL register. */
AnnaBridge 171:3a7713b1edbc 3471 #define CRC_DATALL_DATALL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3472 #define CRC_DATALL_DATALL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3473 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
AnnaBridge 171:3a7713b1edbc 3474
AnnaBridge 171:3a7713b1edbc 3475 /*! @name DATALU - CRC_DATALU register. */
AnnaBridge 171:3a7713b1edbc 3476 #define CRC_DATALU_DATALU_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3477 #define CRC_DATALU_DATALU_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3478 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
AnnaBridge 171:3a7713b1edbc 3479
AnnaBridge 171:3a7713b1edbc 3480 /*! @name DATAHL - CRC_DATAHL register. */
AnnaBridge 171:3a7713b1edbc 3481 #define CRC_DATAHL_DATAHL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3482 #define CRC_DATAHL_DATAHL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3483 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
AnnaBridge 171:3a7713b1edbc 3484
AnnaBridge 171:3a7713b1edbc 3485 /*! @name DATAHU - CRC_DATAHU register. */
AnnaBridge 171:3a7713b1edbc 3486 #define CRC_DATAHU_DATAHU_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3487 #define CRC_DATAHU_DATAHU_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3488 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
AnnaBridge 171:3a7713b1edbc 3489
AnnaBridge 171:3a7713b1edbc 3490 /*! @name GPOLYL - CRC_GPOLYL register. */
AnnaBridge 171:3a7713b1edbc 3491 #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 3492 #define CRC_GPOLYL_GPOLYL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3493 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
AnnaBridge 171:3a7713b1edbc 3494
AnnaBridge 171:3a7713b1edbc 3495 /*! @name GPOLYH - CRC_GPOLYH register. */
AnnaBridge 171:3a7713b1edbc 3496 #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 3497 #define CRC_GPOLYH_GPOLYH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3498 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
AnnaBridge 171:3a7713b1edbc 3499
AnnaBridge 171:3a7713b1edbc 3500 /*! @name GPOLY - CRC Polynomial register */
AnnaBridge 171:3a7713b1edbc 3501 #define CRC_GPOLY_LOW_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 3502 #define CRC_GPOLY_LOW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3503 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
AnnaBridge 171:3a7713b1edbc 3504 #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 3505 #define CRC_GPOLY_HIGH_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3506 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
AnnaBridge 171:3a7713b1edbc 3507
AnnaBridge 171:3a7713b1edbc 3508 /*! @name GPOLYLL - CRC_GPOLYLL register. */
AnnaBridge 171:3a7713b1edbc 3509 #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3510 #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3511 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
AnnaBridge 171:3a7713b1edbc 3512
AnnaBridge 171:3a7713b1edbc 3513 /*! @name GPOLYLU - CRC_GPOLYLU register. */
AnnaBridge 171:3a7713b1edbc 3514 #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3515 #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3516 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
AnnaBridge 171:3a7713b1edbc 3517
AnnaBridge 171:3a7713b1edbc 3518 /*! @name GPOLYHL - CRC_GPOLYHL register. */
AnnaBridge 171:3a7713b1edbc 3519 #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3520 #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3521 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
AnnaBridge 171:3a7713b1edbc 3522
AnnaBridge 171:3a7713b1edbc 3523 /*! @name GPOLYHU - CRC_GPOLYHU register. */
AnnaBridge 171:3a7713b1edbc 3524 #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3525 #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3526 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
AnnaBridge 171:3a7713b1edbc 3527
AnnaBridge 171:3a7713b1edbc 3528 /*! @name CTRL - CRC Control register */
AnnaBridge 171:3a7713b1edbc 3529 #define CRC_CTRL_TCRC_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 3530 #define CRC_CTRL_TCRC_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 3531 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
AnnaBridge 171:3a7713b1edbc 3532 #define CRC_CTRL_WAS_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 3533 #define CRC_CTRL_WAS_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 3534 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
AnnaBridge 171:3a7713b1edbc 3535 #define CRC_CTRL_FXOR_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 3536 #define CRC_CTRL_FXOR_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 3537 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
AnnaBridge 171:3a7713b1edbc 3538 #define CRC_CTRL_TOTR_MASK (0x30000000U)
AnnaBridge 171:3a7713b1edbc 3539 #define CRC_CTRL_TOTR_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 3540 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
AnnaBridge 171:3a7713b1edbc 3541 #define CRC_CTRL_TOT_MASK (0xC0000000U)
AnnaBridge 171:3a7713b1edbc 3542 #define CRC_CTRL_TOT_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 3543 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
AnnaBridge 171:3a7713b1edbc 3544
AnnaBridge 171:3a7713b1edbc 3545 /*! @name CTRLHU - CRC_CTRLHU register. */
AnnaBridge 171:3a7713b1edbc 3546 #define CRC_CTRLHU_TCRC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3547 #define CRC_CTRLHU_TCRC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3548 #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
AnnaBridge 171:3a7713b1edbc 3549 #define CRC_CTRLHU_WAS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3550 #define CRC_CTRLHU_WAS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3551 #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
AnnaBridge 171:3a7713b1edbc 3552 #define CRC_CTRLHU_FXOR_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3553 #define CRC_CTRLHU_FXOR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3554 #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
AnnaBridge 171:3a7713b1edbc 3555 #define CRC_CTRLHU_TOTR_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 3556 #define CRC_CTRLHU_TOTR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3557 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
AnnaBridge 171:3a7713b1edbc 3558 #define CRC_CTRLHU_TOT_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 3559 #define CRC_CTRLHU_TOT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3560 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
AnnaBridge 171:3a7713b1edbc 3561
AnnaBridge 171:3a7713b1edbc 3562
AnnaBridge 171:3a7713b1edbc 3563 /*!
AnnaBridge 171:3a7713b1edbc 3564 * @}
AnnaBridge 171:3a7713b1edbc 3565 */ /* end of group CRC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3566
AnnaBridge 171:3a7713b1edbc 3567
AnnaBridge 171:3a7713b1edbc 3568 /* CRC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3569 /** Peripheral CRC base address */
AnnaBridge 171:3a7713b1edbc 3570 #define CRC_BASE (0x40032000u)
AnnaBridge 171:3a7713b1edbc 3571 /** Peripheral CRC base pointer */
AnnaBridge 171:3a7713b1edbc 3572 #define CRC0 ((CRC_Type *)CRC_BASE)
AnnaBridge 171:3a7713b1edbc 3573 /** Array initializer of CRC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3574 #define CRC_BASE_ADDRS { CRC_BASE }
AnnaBridge 171:3a7713b1edbc 3575 /** Array initializer of CRC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3576 #define CRC_BASE_PTRS { CRC0 }
AnnaBridge 171:3a7713b1edbc 3577
AnnaBridge 171:3a7713b1edbc 3578 /*!
AnnaBridge 171:3a7713b1edbc 3579 * @}
AnnaBridge 171:3a7713b1edbc 3580 */ /* end of group CRC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3581
AnnaBridge 171:3a7713b1edbc 3582
AnnaBridge 171:3a7713b1edbc 3583 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3584 -- DAC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3585 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3586
AnnaBridge 171:3a7713b1edbc 3587 /*!
AnnaBridge 171:3a7713b1edbc 3588 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3589 * @{
AnnaBridge 171:3a7713b1edbc 3590 */
AnnaBridge 171:3a7713b1edbc 3591
AnnaBridge 171:3a7713b1edbc 3592 /** DAC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3593 typedef struct {
AnnaBridge 171:3a7713b1edbc 3594 struct { /* offset: 0x0, array step: 0x2 */
AnnaBridge 171:3a7713b1edbc 3595 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
AnnaBridge 171:3a7713b1edbc 3596 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
AnnaBridge 171:3a7713b1edbc 3597 } DAT[16];
AnnaBridge 171:3a7713b1edbc 3598 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 3599 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
AnnaBridge 171:3a7713b1edbc 3600 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
AnnaBridge 171:3a7713b1edbc 3601 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
AnnaBridge 171:3a7713b1edbc 3602 } DAC_Type;
AnnaBridge 171:3a7713b1edbc 3603
AnnaBridge 171:3a7713b1edbc 3604 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3605 -- DAC Register Masks
AnnaBridge 171:3a7713b1edbc 3606 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3607
AnnaBridge 171:3a7713b1edbc 3608 /*!
AnnaBridge 171:3a7713b1edbc 3609 * @addtogroup DAC_Register_Masks DAC Register Masks
AnnaBridge 171:3a7713b1edbc 3610 * @{
AnnaBridge 171:3a7713b1edbc 3611 */
AnnaBridge 171:3a7713b1edbc 3612
AnnaBridge 171:3a7713b1edbc 3613 /*! @name DATL - DAC Data Low Register */
AnnaBridge 171:3a7713b1edbc 3614 #define DAC_DATL_DATA0_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3615 #define DAC_DATL_DATA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3616 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
AnnaBridge 171:3a7713b1edbc 3617
AnnaBridge 171:3a7713b1edbc 3618 /* The count of DAC_DATL */
AnnaBridge 171:3a7713b1edbc 3619 #define DAC_DATL_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 3620
AnnaBridge 171:3a7713b1edbc 3621 /*! @name DATH - DAC Data High Register */
AnnaBridge 171:3a7713b1edbc 3622 #define DAC_DATH_DATA1_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 3623 #define DAC_DATH_DATA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3624 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
AnnaBridge 171:3a7713b1edbc 3625
AnnaBridge 171:3a7713b1edbc 3626 /* The count of DAC_DATH */
AnnaBridge 171:3a7713b1edbc 3627 #define DAC_DATH_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 3628
AnnaBridge 171:3a7713b1edbc 3629 /*! @name SR - DAC Status Register */
AnnaBridge 171:3a7713b1edbc 3630 #define DAC_SR_DACBFRPBF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3631 #define DAC_SR_DACBFRPBF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3632 #define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
AnnaBridge 171:3a7713b1edbc 3633 #define DAC_SR_DACBFRPTF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3634 #define DAC_SR_DACBFRPTF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3635 #define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
AnnaBridge 171:3a7713b1edbc 3636 #define DAC_SR_DACBFWMF_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3637 #define DAC_SR_DACBFWMF_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3638 #define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
AnnaBridge 171:3a7713b1edbc 3639
AnnaBridge 171:3a7713b1edbc 3640 /*! @name C0 - DAC Control Register */
AnnaBridge 171:3a7713b1edbc 3641 #define DAC_C0_DACBBIEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3642 #define DAC_C0_DACBBIEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3643 #define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
AnnaBridge 171:3a7713b1edbc 3644 #define DAC_C0_DACBTIEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3645 #define DAC_C0_DACBTIEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3646 #define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
AnnaBridge 171:3a7713b1edbc 3647 #define DAC_C0_DACBWIEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3648 #define DAC_C0_DACBWIEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3649 #define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
AnnaBridge 171:3a7713b1edbc 3650 #define DAC_C0_LPEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3651 #define DAC_C0_LPEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3652 #define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
AnnaBridge 171:3a7713b1edbc 3653 #define DAC_C0_DACSWTRG_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3654 #define DAC_C0_DACSWTRG_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3655 #define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
AnnaBridge 171:3a7713b1edbc 3656 #define DAC_C0_DACTRGSEL_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3657 #define DAC_C0_DACTRGSEL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3658 #define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 3659 #define DAC_C0_DACRFS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3660 #define DAC_C0_DACRFS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3661 #define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
AnnaBridge 171:3a7713b1edbc 3662 #define DAC_C0_DACEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3663 #define DAC_C0_DACEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3664 #define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
AnnaBridge 171:3a7713b1edbc 3665
AnnaBridge 171:3a7713b1edbc 3666 /*! @name C1 - DAC Control Register 1 */
AnnaBridge 171:3a7713b1edbc 3667 #define DAC_C1_DACBFEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3668 #define DAC_C1_DACBFEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3669 #define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
AnnaBridge 171:3a7713b1edbc 3670 #define DAC_C1_DACBFMD_MASK (0x6U)
AnnaBridge 171:3a7713b1edbc 3671 #define DAC_C1_DACBFMD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3672 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
AnnaBridge 171:3a7713b1edbc 3673 #define DAC_C1_DACBFWM_MASK (0x18U)
AnnaBridge 171:3a7713b1edbc 3674 #define DAC_C1_DACBFWM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3675 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
AnnaBridge 171:3a7713b1edbc 3676 #define DAC_C1_DMAEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3677 #define DAC_C1_DMAEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3678 #define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 3679
AnnaBridge 171:3a7713b1edbc 3680 /*! @name C2 - DAC Control Register 2 */
AnnaBridge 171:3a7713b1edbc 3681 #define DAC_C2_DACBFUP_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 3682 #define DAC_C2_DACBFUP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3683 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
AnnaBridge 171:3a7713b1edbc 3684 #define DAC_C2_DACBFRP_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 3685 #define DAC_C2_DACBFRP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3686 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
AnnaBridge 171:3a7713b1edbc 3687
AnnaBridge 171:3a7713b1edbc 3688
AnnaBridge 171:3a7713b1edbc 3689 /*!
AnnaBridge 171:3a7713b1edbc 3690 * @}
AnnaBridge 171:3a7713b1edbc 3691 */ /* end of group DAC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3692
AnnaBridge 171:3a7713b1edbc 3693
AnnaBridge 171:3a7713b1edbc 3694 /* DAC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3695 /** Peripheral DAC0 base address */
AnnaBridge 171:3a7713b1edbc 3696 #define DAC0_BASE (0x400CC000u)
AnnaBridge 171:3a7713b1edbc 3697 /** Peripheral DAC0 base pointer */
AnnaBridge 171:3a7713b1edbc 3698 #define DAC0 ((DAC_Type *)DAC0_BASE)
AnnaBridge 171:3a7713b1edbc 3699 /** Peripheral DAC1 base address */
AnnaBridge 171:3a7713b1edbc 3700 #define DAC1_BASE (0x400CD000u)
AnnaBridge 171:3a7713b1edbc 3701 /** Peripheral DAC1 base pointer */
AnnaBridge 171:3a7713b1edbc 3702 #define DAC1 ((DAC_Type *)DAC1_BASE)
AnnaBridge 171:3a7713b1edbc 3703 /** Array initializer of DAC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3704 #define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
AnnaBridge 171:3a7713b1edbc 3705 /** Array initializer of DAC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3706 #define DAC_BASE_PTRS { DAC0, DAC1 }
AnnaBridge 171:3a7713b1edbc 3707 /** Interrupt vectors for the DAC peripheral type */
AnnaBridge 171:3a7713b1edbc 3708 #define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
AnnaBridge 171:3a7713b1edbc 3709
AnnaBridge 171:3a7713b1edbc 3710 /*!
AnnaBridge 171:3a7713b1edbc 3711 * @}
AnnaBridge 171:3a7713b1edbc 3712 */ /* end of group DAC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3713
AnnaBridge 171:3a7713b1edbc 3714
AnnaBridge 171:3a7713b1edbc 3715 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3716 -- DMA Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3717 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3718
AnnaBridge 171:3a7713b1edbc 3719 /*!
AnnaBridge 171:3a7713b1edbc 3720 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3721 * @{
AnnaBridge 171:3a7713b1edbc 3722 */
AnnaBridge 171:3a7713b1edbc 3723
AnnaBridge 171:3a7713b1edbc 3724 /** DMA - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3725 typedef struct {
AnnaBridge 171:3a7713b1edbc 3726 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3727 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3728 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 3729 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 3730 uint8_t RESERVED_1[4];
AnnaBridge 171:3a7713b1edbc 3731 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 3732 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 3733 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
AnnaBridge 171:3a7713b1edbc 3734 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
AnnaBridge 171:3a7713b1edbc 3735 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
AnnaBridge 171:3a7713b1edbc 3736 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 3737 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
AnnaBridge 171:3a7713b1edbc 3738 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
AnnaBridge 171:3a7713b1edbc 3739 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
AnnaBridge 171:3a7713b1edbc 3740 uint8_t RESERVED_2[4];
AnnaBridge 171:3a7713b1edbc 3741 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 3742 uint8_t RESERVED_3[4];
AnnaBridge 171:3a7713b1edbc 3743 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 3744 uint8_t RESERVED_4[4];
AnnaBridge 171:3a7713b1edbc 3745 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 3746 uint8_t RESERVED_5[12];
AnnaBridge 171:3a7713b1edbc 3747 __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 3748 uint8_t RESERVED_6[184];
AnnaBridge 171:3a7713b1edbc 3749 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
AnnaBridge 171:3a7713b1edbc 3750 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
AnnaBridge 171:3a7713b1edbc 3751 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
AnnaBridge 171:3a7713b1edbc 3752 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
AnnaBridge 171:3a7713b1edbc 3753 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
AnnaBridge 171:3a7713b1edbc 3754 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
AnnaBridge 171:3a7713b1edbc 3755 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
AnnaBridge 171:3a7713b1edbc 3756 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
AnnaBridge 171:3a7713b1edbc 3757 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
AnnaBridge 171:3a7713b1edbc 3758 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
AnnaBridge 171:3a7713b1edbc 3759 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
AnnaBridge 171:3a7713b1edbc 3760 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
AnnaBridge 171:3a7713b1edbc 3761 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
AnnaBridge 171:3a7713b1edbc 3762 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
AnnaBridge 171:3a7713b1edbc 3763 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
AnnaBridge 171:3a7713b1edbc 3764 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
AnnaBridge 171:3a7713b1edbc 3765 __IO uint8_t DCHPRI19; /**< Channel n Priority Register, offset: 0x110 */
AnnaBridge 171:3a7713b1edbc 3766 __IO uint8_t DCHPRI18; /**< Channel n Priority Register, offset: 0x111 */
AnnaBridge 171:3a7713b1edbc 3767 __IO uint8_t DCHPRI17; /**< Channel n Priority Register, offset: 0x112 */
AnnaBridge 171:3a7713b1edbc 3768 __IO uint8_t DCHPRI16; /**< Channel n Priority Register, offset: 0x113 */
AnnaBridge 171:3a7713b1edbc 3769 __IO uint8_t DCHPRI23; /**< Channel n Priority Register, offset: 0x114 */
AnnaBridge 171:3a7713b1edbc 3770 __IO uint8_t DCHPRI22; /**< Channel n Priority Register, offset: 0x115 */
AnnaBridge 171:3a7713b1edbc 3771 __IO uint8_t DCHPRI21; /**< Channel n Priority Register, offset: 0x116 */
AnnaBridge 171:3a7713b1edbc 3772 __IO uint8_t DCHPRI20; /**< Channel n Priority Register, offset: 0x117 */
AnnaBridge 171:3a7713b1edbc 3773 __IO uint8_t DCHPRI27; /**< Channel n Priority Register, offset: 0x118 */
AnnaBridge 171:3a7713b1edbc 3774 __IO uint8_t DCHPRI26; /**< Channel n Priority Register, offset: 0x119 */
AnnaBridge 171:3a7713b1edbc 3775 __IO uint8_t DCHPRI25; /**< Channel n Priority Register, offset: 0x11A */
AnnaBridge 171:3a7713b1edbc 3776 __IO uint8_t DCHPRI24; /**< Channel n Priority Register, offset: 0x11B */
AnnaBridge 171:3a7713b1edbc 3777 __IO uint8_t DCHPRI31; /**< Channel n Priority Register, offset: 0x11C */
AnnaBridge 171:3a7713b1edbc 3778 __IO uint8_t DCHPRI30; /**< Channel n Priority Register, offset: 0x11D */
AnnaBridge 171:3a7713b1edbc 3779 __IO uint8_t DCHPRI29; /**< Channel n Priority Register, offset: 0x11E */
AnnaBridge 171:3a7713b1edbc 3780 __IO uint8_t DCHPRI28; /**< Channel n Priority Register, offset: 0x11F */
AnnaBridge 171:3a7713b1edbc 3781 uint8_t RESERVED_7[3808];
AnnaBridge 171:3a7713b1edbc 3782 struct { /* offset: 0x1000, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3783 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3784 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3785 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3786 union { /* offset: 0x1008, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3787 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3788 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3789 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3790 };
AnnaBridge 171:3a7713b1edbc 3791 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3792 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3793 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3794 union { /* offset: 0x1016, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3795 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3796 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3797 };
AnnaBridge 171:3a7713b1edbc 3798 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3799 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3800 union { /* offset: 0x101E, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3801 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3802 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3803 };
AnnaBridge 171:3a7713b1edbc 3804 } TCD[32];
AnnaBridge 171:3a7713b1edbc 3805 } DMA_Type;
AnnaBridge 171:3a7713b1edbc 3806
AnnaBridge 171:3a7713b1edbc 3807 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3808 -- DMA Register Masks
AnnaBridge 171:3a7713b1edbc 3809 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3810
AnnaBridge 171:3a7713b1edbc 3811 /*!
AnnaBridge 171:3a7713b1edbc 3812 * @addtogroup DMA_Register_Masks DMA Register Masks
AnnaBridge 171:3a7713b1edbc 3813 * @{
AnnaBridge 171:3a7713b1edbc 3814 */
AnnaBridge 171:3a7713b1edbc 3815
AnnaBridge 171:3a7713b1edbc 3816 /*! @name CR - Control Register */
AnnaBridge 171:3a7713b1edbc 3817 #define DMA_CR_EDBG_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3818 #define DMA_CR_EDBG_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3819 #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
AnnaBridge 171:3a7713b1edbc 3820 #define DMA_CR_ERCA_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3821 #define DMA_CR_ERCA_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3822 #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
AnnaBridge 171:3a7713b1edbc 3823 #define DMA_CR_ERGA_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3824 #define DMA_CR_ERGA_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3825 #define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
AnnaBridge 171:3a7713b1edbc 3826 #define DMA_CR_HOE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3827 #define DMA_CR_HOE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3828 #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
AnnaBridge 171:3a7713b1edbc 3829 #define DMA_CR_HALT_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3830 #define DMA_CR_HALT_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3831 #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
AnnaBridge 171:3a7713b1edbc 3832 #define DMA_CR_CLM_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3833 #define DMA_CR_CLM_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3834 #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
AnnaBridge 171:3a7713b1edbc 3835 #define DMA_CR_EMLM_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3836 #define DMA_CR_EMLM_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3837 #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
AnnaBridge 171:3a7713b1edbc 3838 #define DMA_CR_GRP0PRI_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 3839 #define DMA_CR_GRP0PRI_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 3840 #define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
AnnaBridge 171:3a7713b1edbc 3841 #define DMA_CR_GRP1PRI_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 3842 #define DMA_CR_GRP1PRI_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 3843 #define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
AnnaBridge 171:3a7713b1edbc 3844 #define DMA_CR_ECX_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 3845 #define DMA_CR_ECX_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3846 #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
AnnaBridge 171:3a7713b1edbc 3847 #define DMA_CR_CX_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 3848 #define DMA_CR_CX_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 3849 #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
AnnaBridge 171:3a7713b1edbc 3850
AnnaBridge 171:3a7713b1edbc 3851 /*! @name ES - Error Status Register */
AnnaBridge 171:3a7713b1edbc 3852 #define DMA_ES_DBE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3853 #define DMA_ES_DBE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3854 #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
AnnaBridge 171:3a7713b1edbc 3855 #define DMA_ES_SBE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3856 #define DMA_ES_SBE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3857 #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
AnnaBridge 171:3a7713b1edbc 3858 #define DMA_ES_SGE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3859 #define DMA_ES_SGE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3860 #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
AnnaBridge 171:3a7713b1edbc 3861 #define DMA_ES_NCE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3862 #define DMA_ES_NCE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3863 #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
AnnaBridge 171:3a7713b1edbc 3864 #define DMA_ES_DOE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3865 #define DMA_ES_DOE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3866 #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
AnnaBridge 171:3a7713b1edbc 3867 #define DMA_ES_DAE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3868 #define DMA_ES_DAE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3869 #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
AnnaBridge 171:3a7713b1edbc 3870 #define DMA_ES_SOE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3871 #define DMA_ES_SOE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3872 #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
AnnaBridge 171:3a7713b1edbc 3873 #define DMA_ES_SAE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3874 #define DMA_ES_SAE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3875 #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
AnnaBridge 171:3a7713b1edbc 3876 #define DMA_ES_ERRCHN_MASK (0x1F00U)
AnnaBridge 171:3a7713b1edbc 3877 #define DMA_ES_ERRCHN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 3878 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
AnnaBridge 171:3a7713b1edbc 3879 #define DMA_ES_CPE_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 3880 #define DMA_ES_CPE_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 3881 #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
AnnaBridge 171:3a7713b1edbc 3882 #define DMA_ES_GPE_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 3883 #define DMA_ES_GPE_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 3884 #define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
AnnaBridge 171:3a7713b1edbc 3885 #define DMA_ES_ECX_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 3886 #define DMA_ES_ECX_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3887 #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
AnnaBridge 171:3a7713b1edbc 3888 #define DMA_ES_VLD_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 3889 #define DMA_ES_VLD_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 3890 #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
AnnaBridge 171:3a7713b1edbc 3891
AnnaBridge 171:3a7713b1edbc 3892 /*! @name ERQ - Enable Request Register */
AnnaBridge 171:3a7713b1edbc 3893 #define DMA_ERQ_ERQ0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3894 #define DMA_ERQ_ERQ0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3895 #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
AnnaBridge 171:3a7713b1edbc 3896 #define DMA_ERQ_ERQ1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3897 #define DMA_ERQ_ERQ1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3898 #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
AnnaBridge 171:3a7713b1edbc 3899 #define DMA_ERQ_ERQ2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3900 #define DMA_ERQ_ERQ2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3901 #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
AnnaBridge 171:3a7713b1edbc 3902 #define DMA_ERQ_ERQ3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3903 #define DMA_ERQ_ERQ3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3904 #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
AnnaBridge 171:3a7713b1edbc 3905 #define DMA_ERQ_ERQ4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3906 #define DMA_ERQ_ERQ4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3907 #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
AnnaBridge 171:3a7713b1edbc 3908 #define DMA_ERQ_ERQ5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3909 #define DMA_ERQ_ERQ5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3910 #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
AnnaBridge 171:3a7713b1edbc 3911 #define DMA_ERQ_ERQ6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3912 #define DMA_ERQ_ERQ6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3913 #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
AnnaBridge 171:3a7713b1edbc 3914 #define DMA_ERQ_ERQ7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3915 #define DMA_ERQ_ERQ7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3916 #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
AnnaBridge 171:3a7713b1edbc 3917 #define DMA_ERQ_ERQ8_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 3918 #define DMA_ERQ_ERQ8_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 3919 #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
AnnaBridge 171:3a7713b1edbc 3920 #define DMA_ERQ_ERQ9_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 3921 #define DMA_ERQ_ERQ9_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 3922 #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
AnnaBridge 171:3a7713b1edbc 3923 #define DMA_ERQ_ERQ10_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 3924 #define DMA_ERQ_ERQ10_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 3925 #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
AnnaBridge 171:3a7713b1edbc 3926 #define DMA_ERQ_ERQ11_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 3927 #define DMA_ERQ_ERQ11_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 3928 #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
AnnaBridge 171:3a7713b1edbc 3929 #define DMA_ERQ_ERQ12_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 3930 #define DMA_ERQ_ERQ12_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 3931 #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
AnnaBridge 171:3a7713b1edbc 3932 #define DMA_ERQ_ERQ13_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 3933 #define DMA_ERQ_ERQ13_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 3934 #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
AnnaBridge 171:3a7713b1edbc 3935 #define DMA_ERQ_ERQ14_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 3936 #define DMA_ERQ_ERQ14_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 3937 #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
AnnaBridge 171:3a7713b1edbc 3938 #define DMA_ERQ_ERQ15_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 3939 #define DMA_ERQ_ERQ15_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 3940 #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
AnnaBridge 171:3a7713b1edbc 3941 #define DMA_ERQ_ERQ16_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 3942 #define DMA_ERQ_ERQ16_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3943 #define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
AnnaBridge 171:3a7713b1edbc 3944 #define DMA_ERQ_ERQ17_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 3945 #define DMA_ERQ_ERQ17_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 3946 #define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
AnnaBridge 171:3a7713b1edbc 3947 #define DMA_ERQ_ERQ18_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 3948 #define DMA_ERQ_ERQ18_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 3949 #define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
AnnaBridge 171:3a7713b1edbc 3950 #define DMA_ERQ_ERQ19_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 3951 #define DMA_ERQ_ERQ19_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 3952 #define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
AnnaBridge 171:3a7713b1edbc 3953 #define DMA_ERQ_ERQ20_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 3954 #define DMA_ERQ_ERQ20_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 3955 #define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
AnnaBridge 171:3a7713b1edbc 3956 #define DMA_ERQ_ERQ21_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 3957 #define DMA_ERQ_ERQ21_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 3958 #define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
AnnaBridge 171:3a7713b1edbc 3959 #define DMA_ERQ_ERQ22_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 3960 #define DMA_ERQ_ERQ22_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 3961 #define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
AnnaBridge 171:3a7713b1edbc 3962 #define DMA_ERQ_ERQ23_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 3963 #define DMA_ERQ_ERQ23_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 3964 #define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
AnnaBridge 171:3a7713b1edbc 3965 #define DMA_ERQ_ERQ24_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 3966 #define DMA_ERQ_ERQ24_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 3967 #define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
AnnaBridge 171:3a7713b1edbc 3968 #define DMA_ERQ_ERQ25_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 3969 #define DMA_ERQ_ERQ25_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 3970 #define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
AnnaBridge 171:3a7713b1edbc 3971 #define DMA_ERQ_ERQ26_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 3972 #define DMA_ERQ_ERQ26_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 3973 #define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
AnnaBridge 171:3a7713b1edbc 3974 #define DMA_ERQ_ERQ27_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 3975 #define DMA_ERQ_ERQ27_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 3976 #define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
AnnaBridge 171:3a7713b1edbc 3977 #define DMA_ERQ_ERQ28_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 3978 #define DMA_ERQ_ERQ28_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 3979 #define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
AnnaBridge 171:3a7713b1edbc 3980 #define DMA_ERQ_ERQ29_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 3981 #define DMA_ERQ_ERQ29_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 3982 #define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
AnnaBridge 171:3a7713b1edbc 3983 #define DMA_ERQ_ERQ30_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 3984 #define DMA_ERQ_ERQ30_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 3985 #define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
AnnaBridge 171:3a7713b1edbc 3986 #define DMA_ERQ_ERQ31_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 3987 #define DMA_ERQ_ERQ31_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 3988 #define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
AnnaBridge 171:3a7713b1edbc 3989
AnnaBridge 171:3a7713b1edbc 3990 /*! @name EEI - Enable Error Interrupt Register */
AnnaBridge 171:3a7713b1edbc 3991 #define DMA_EEI_EEI0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3992 #define DMA_EEI_EEI0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3993 #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
AnnaBridge 171:3a7713b1edbc 3994 #define DMA_EEI_EEI1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3995 #define DMA_EEI_EEI1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3996 #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
AnnaBridge 171:3a7713b1edbc 3997 #define DMA_EEI_EEI2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3998 #define DMA_EEI_EEI2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3999 #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
AnnaBridge 171:3a7713b1edbc 4000 #define DMA_EEI_EEI3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4001 #define DMA_EEI_EEI3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4002 #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
AnnaBridge 171:3a7713b1edbc 4003 #define DMA_EEI_EEI4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4004 #define DMA_EEI_EEI4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4005 #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
AnnaBridge 171:3a7713b1edbc 4006 #define DMA_EEI_EEI5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4007 #define DMA_EEI_EEI5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4008 #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
AnnaBridge 171:3a7713b1edbc 4009 #define DMA_EEI_EEI6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4010 #define DMA_EEI_EEI6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4011 #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
AnnaBridge 171:3a7713b1edbc 4012 #define DMA_EEI_EEI7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4013 #define DMA_EEI_EEI7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4014 #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
AnnaBridge 171:3a7713b1edbc 4015 #define DMA_EEI_EEI8_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 4016 #define DMA_EEI_EEI8_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4017 #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
AnnaBridge 171:3a7713b1edbc 4018 #define DMA_EEI_EEI9_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 4019 #define DMA_EEI_EEI9_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 4020 #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
AnnaBridge 171:3a7713b1edbc 4021 #define DMA_EEI_EEI10_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 4022 #define DMA_EEI_EEI10_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 4023 #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
AnnaBridge 171:3a7713b1edbc 4024 #define DMA_EEI_EEI11_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 4025 #define DMA_EEI_EEI11_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 4026 #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
AnnaBridge 171:3a7713b1edbc 4027 #define DMA_EEI_EEI12_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 4028 #define DMA_EEI_EEI12_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 4029 #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
AnnaBridge 171:3a7713b1edbc 4030 #define DMA_EEI_EEI13_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 4031 #define DMA_EEI_EEI13_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 4032 #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
AnnaBridge 171:3a7713b1edbc 4033 #define DMA_EEI_EEI14_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 4034 #define DMA_EEI_EEI14_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 4035 #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
AnnaBridge 171:3a7713b1edbc 4036 #define DMA_EEI_EEI15_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 4037 #define DMA_EEI_EEI15_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 4038 #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
AnnaBridge 171:3a7713b1edbc 4039 #define DMA_EEI_EEI16_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 4040 #define DMA_EEI_EEI16_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4041 #define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
AnnaBridge 171:3a7713b1edbc 4042 #define DMA_EEI_EEI17_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 4043 #define DMA_EEI_EEI17_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 4044 #define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
AnnaBridge 171:3a7713b1edbc 4045 #define DMA_EEI_EEI18_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 4046 #define DMA_EEI_EEI18_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 4047 #define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
AnnaBridge 171:3a7713b1edbc 4048 #define DMA_EEI_EEI19_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 4049 #define DMA_EEI_EEI19_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 4050 #define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
AnnaBridge 171:3a7713b1edbc 4051 #define DMA_EEI_EEI20_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 4052 #define DMA_EEI_EEI20_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 4053 #define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
AnnaBridge 171:3a7713b1edbc 4054 #define DMA_EEI_EEI21_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 4055 #define DMA_EEI_EEI21_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 4056 #define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
AnnaBridge 171:3a7713b1edbc 4057 #define DMA_EEI_EEI22_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 4058 #define DMA_EEI_EEI22_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 4059 #define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
AnnaBridge 171:3a7713b1edbc 4060 #define DMA_EEI_EEI23_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 4061 #define DMA_EEI_EEI23_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 4062 #define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
AnnaBridge 171:3a7713b1edbc 4063 #define DMA_EEI_EEI24_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 4064 #define DMA_EEI_EEI24_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4065 #define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
AnnaBridge 171:3a7713b1edbc 4066 #define DMA_EEI_EEI25_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 4067 #define DMA_EEI_EEI25_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 4068 #define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
AnnaBridge 171:3a7713b1edbc 4069 #define DMA_EEI_EEI26_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 4070 #define DMA_EEI_EEI26_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 4071 #define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
AnnaBridge 171:3a7713b1edbc 4072 #define DMA_EEI_EEI27_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 4073 #define DMA_EEI_EEI27_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 4074 #define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
AnnaBridge 171:3a7713b1edbc 4075 #define DMA_EEI_EEI28_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 4076 #define DMA_EEI_EEI28_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 4077 #define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
AnnaBridge 171:3a7713b1edbc 4078 #define DMA_EEI_EEI29_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 4079 #define DMA_EEI_EEI29_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 4080 #define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
AnnaBridge 171:3a7713b1edbc 4081 #define DMA_EEI_EEI30_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 4082 #define DMA_EEI_EEI30_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 4083 #define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
AnnaBridge 171:3a7713b1edbc 4084 #define DMA_EEI_EEI31_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 4085 #define DMA_EEI_EEI31_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 4086 #define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
AnnaBridge 171:3a7713b1edbc 4087
AnnaBridge 171:3a7713b1edbc 4088 /*! @name CEEI - Clear Enable Error Interrupt Register */
AnnaBridge 171:3a7713b1edbc 4089 #define DMA_CEEI_CEEI_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 4090 #define DMA_CEEI_CEEI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4091 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
AnnaBridge 171:3a7713b1edbc 4092 #define DMA_CEEI_CAEE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4093 #define DMA_CEEI_CAEE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4094 #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
AnnaBridge 171:3a7713b1edbc 4095 #define DMA_CEEI_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4096 #define DMA_CEEI_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4097 #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 4098
AnnaBridge 171:3a7713b1edbc 4099 /*! @name SEEI - Set Enable Error Interrupt Register */
AnnaBridge 171:3a7713b1edbc 4100 #define DMA_SEEI_SEEI_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 4101 #define DMA_SEEI_SEEI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4102 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
AnnaBridge 171:3a7713b1edbc 4103 #define DMA_SEEI_SAEE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4104 #define DMA_SEEI_SAEE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4105 #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
AnnaBridge 171:3a7713b1edbc 4106 #define DMA_SEEI_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4107 #define DMA_SEEI_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4108 #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 4109
AnnaBridge 171:3a7713b1edbc 4110 /*! @name CERQ - Clear Enable Request Register */
AnnaBridge 171:3a7713b1edbc 4111 #define DMA_CERQ_CERQ_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 4112 #define DMA_CERQ_CERQ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4113 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
AnnaBridge 171:3a7713b1edbc 4114 #define DMA_CERQ_CAER_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4115 #define DMA_CERQ_CAER_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4116 #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
AnnaBridge 171:3a7713b1edbc 4117 #define DMA_CERQ_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4118 #define DMA_CERQ_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4119 #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 4120
AnnaBridge 171:3a7713b1edbc 4121 /*! @name SERQ - Set Enable Request Register */
AnnaBridge 171:3a7713b1edbc 4122 #define DMA_SERQ_SERQ_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 4123 #define DMA_SERQ_SERQ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4124 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
AnnaBridge 171:3a7713b1edbc 4125 #define DMA_SERQ_SAER_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4126 #define DMA_SERQ_SAER_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4127 #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
AnnaBridge 171:3a7713b1edbc 4128 #define DMA_SERQ_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4129 #define DMA_SERQ_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4130 #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 4131
AnnaBridge 171:3a7713b1edbc 4132 /*! @name CDNE - Clear DONE Status Bit Register */
AnnaBridge 171:3a7713b1edbc 4133 #define DMA_CDNE_CDNE_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 4134 #define DMA_CDNE_CDNE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4135 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
AnnaBridge 171:3a7713b1edbc 4136 #define DMA_CDNE_CADN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4137 #define DMA_CDNE_CADN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4138 #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
AnnaBridge 171:3a7713b1edbc 4139 #define DMA_CDNE_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4140 #define DMA_CDNE_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4141 #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 4142
AnnaBridge 171:3a7713b1edbc 4143 /*! @name SSRT - Set START Bit Register */
AnnaBridge 171:3a7713b1edbc 4144 #define DMA_SSRT_SSRT_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 4145 #define DMA_SSRT_SSRT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4146 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
AnnaBridge 171:3a7713b1edbc 4147 #define DMA_SSRT_SAST_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4148 #define DMA_SSRT_SAST_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4149 #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
AnnaBridge 171:3a7713b1edbc 4150 #define DMA_SSRT_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4151 #define DMA_SSRT_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4152 #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 4153
AnnaBridge 171:3a7713b1edbc 4154 /*! @name CERR - Clear Error Register */
AnnaBridge 171:3a7713b1edbc 4155 #define DMA_CERR_CERR_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 4156 #define DMA_CERR_CERR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4157 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
AnnaBridge 171:3a7713b1edbc 4158 #define DMA_CERR_CAEI_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4159 #define DMA_CERR_CAEI_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4160 #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
AnnaBridge 171:3a7713b1edbc 4161 #define DMA_CERR_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4162 #define DMA_CERR_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4163 #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 4164
AnnaBridge 171:3a7713b1edbc 4165 /*! @name CINT - Clear Interrupt Request Register */
AnnaBridge 171:3a7713b1edbc 4166 #define DMA_CINT_CINT_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 4167 #define DMA_CINT_CINT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4168 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
AnnaBridge 171:3a7713b1edbc 4169 #define DMA_CINT_CAIR_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4170 #define DMA_CINT_CAIR_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4171 #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
AnnaBridge 171:3a7713b1edbc 4172 #define DMA_CINT_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4173 #define DMA_CINT_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4174 #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 4175
AnnaBridge 171:3a7713b1edbc 4176 /*! @name INT - Interrupt Request Register */
AnnaBridge 171:3a7713b1edbc 4177 #define DMA_INT_INT0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4178 #define DMA_INT_INT0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4179 #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
AnnaBridge 171:3a7713b1edbc 4180 #define DMA_INT_INT1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4181 #define DMA_INT_INT1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4182 #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
AnnaBridge 171:3a7713b1edbc 4183 #define DMA_INT_INT2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4184 #define DMA_INT_INT2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4185 #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
AnnaBridge 171:3a7713b1edbc 4186 #define DMA_INT_INT3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4187 #define DMA_INT_INT3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4188 #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
AnnaBridge 171:3a7713b1edbc 4189 #define DMA_INT_INT4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4190 #define DMA_INT_INT4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4191 #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
AnnaBridge 171:3a7713b1edbc 4192 #define DMA_INT_INT5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4193 #define DMA_INT_INT5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4194 #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
AnnaBridge 171:3a7713b1edbc 4195 #define DMA_INT_INT6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4196 #define DMA_INT_INT6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4197 #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
AnnaBridge 171:3a7713b1edbc 4198 #define DMA_INT_INT7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4199 #define DMA_INT_INT7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4200 #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
AnnaBridge 171:3a7713b1edbc 4201 #define DMA_INT_INT8_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 4202 #define DMA_INT_INT8_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4203 #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
AnnaBridge 171:3a7713b1edbc 4204 #define DMA_INT_INT9_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 4205 #define DMA_INT_INT9_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 4206 #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
AnnaBridge 171:3a7713b1edbc 4207 #define DMA_INT_INT10_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 4208 #define DMA_INT_INT10_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 4209 #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
AnnaBridge 171:3a7713b1edbc 4210 #define DMA_INT_INT11_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 4211 #define DMA_INT_INT11_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 4212 #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
AnnaBridge 171:3a7713b1edbc 4213 #define DMA_INT_INT12_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 4214 #define DMA_INT_INT12_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 4215 #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
AnnaBridge 171:3a7713b1edbc 4216 #define DMA_INT_INT13_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 4217 #define DMA_INT_INT13_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 4218 #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
AnnaBridge 171:3a7713b1edbc 4219 #define DMA_INT_INT14_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 4220 #define DMA_INT_INT14_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 4221 #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
AnnaBridge 171:3a7713b1edbc 4222 #define DMA_INT_INT15_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 4223 #define DMA_INT_INT15_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 4224 #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
AnnaBridge 171:3a7713b1edbc 4225 #define DMA_INT_INT16_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 4226 #define DMA_INT_INT16_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4227 #define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
AnnaBridge 171:3a7713b1edbc 4228 #define DMA_INT_INT17_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 4229 #define DMA_INT_INT17_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 4230 #define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
AnnaBridge 171:3a7713b1edbc 4231 #define DMA_INT_INT18_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 4232 #define DMA_INT_INT18_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 4233 #define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
AnnaBridge 171:3a7713b1edbc 4234 #define DMA_INT_INT19_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 4235 #define DMA_INT_INT19_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 4236 #define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
AnnaBridge 171:3a7713b1edbc 4237 #define DMA_INT_INT20_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 4238 #define DMA_INT_INT20_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 4239 #define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
AnnaBridge 171:3a7713b1edbc 4240 #define DMA_INT_INT21_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 4241 #define DMA_INT_INT21_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 4242 #define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
AnnaBridge 171:3a7713b1edbc 4243 #define DMA_INT_INT22_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 4244 #define DMA_INT_INT22_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 4245 #define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
AnnaBridge 171:3a7713b1edbc 4246 #define DMA_INT_INT23_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 4247 #define DMA_INT_INT23_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 4248 #define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
AnnaBridge 171:3a7713b1edbc 4249 #define DMA_INT_INT24_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 4250 #define DMA_INT_INT24_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4251 #define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
AnnaBridge 171:3a7713b1edbc 4252 #define DMA_INT_INT25_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 4253 #define DMA_INT_INT25_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 4254 #define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
AnnaBridge 171:3a7713b1edbc 4255 #define DMA_INT_INT26_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 4256 #define DMA_INT_INT26_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 4257 #define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
AnnaBridge 171:3a7713b1edbc 4258 #define DMA_INT_INT27_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 4259 #define DMA_INT_INT27_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 4260 #define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
AnnaBridge 171:3a7713b1edbc 4261 #define DMA_INT_INT28_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 4262 #define DMA_INT_INT28_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 4263 #define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
AnnaBridge 171:3a7713b1edbc 4264 #define DMA_INT_INT29_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 4265 #define DMA_INT_INT29_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 4266 #define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
AnnaBridge 171:3a7713b1edbc 4267 #define DMA_INT_INT30_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 4268 #define DMA_INT_INT30_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 4269 #define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
AnnaBridge 171:3a7713b1edbc 4270 #define DMA_INT_INT31_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 4271 #define DMA_INT_INT31_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 4272 #define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
AnnaBridge 171:3a7713b1edbc 4273
AnnaBridge 171:3a7713b1edbc 4274 /*! @name ERR - Error Register */
AnnaBridge 171:3a7713b1edbc 4275 #define DMA_ERR_ERR0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4276 #define DMA_ERR_ERR0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4277 #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
AnnaBridge 171:3a7713b1edbc 4278 #define DMA_ERR_ERR1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4279 #define DMA_ERR_ERR1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4280 #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
AnnaBridge 171:3a7713b1edbc 4281 #define DMA_ERR_ERR2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4282 #define DMA_ERR_ERR2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4283 #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
AnnaBridge 171:3a7713b1edbc 4284 #define DMA_ERR_ERR3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4285 #define DMA_ERR_ERR3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4286 #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
AnnaBridge 171:3a7713b1edbc 4287 #define DMA_ERR_ERR4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4288 #define DMA_ERR_ERR4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4289 #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
AnnaBridge 171:3a7713b1edbc 4290 #define DMA_ERR_ERR5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4291 #define DMA_ERR_ERR5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4292 #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
AnnaBridge 171:3a7713b1edbc 4293 #define DMA_ERR_ERR6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4294 #define DMA_ERR_ERR6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4295 #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
AnnaBridge 171:3a7713b1edbc 4296 #define DMA_ERR_ERR7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4297 #define DMA_ERR_ERR7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4298 #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
AnnaBridge 171:3a7713b1edbc 4299 #define DMA_ERR_ERR8_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 4300 #define DMA_ERR_ERR8_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4301 #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
AnnaBridge 171:3a7713b1edbc 4302 #define DMA_ERR_ERR9_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 4303 #define DMA_ERR_ERR9_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 4304 #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
AnnaBridge 171:3a7713b1edbc 4305 #define DMA_ERR_ERR10_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 4306 #define DMA_ERR_ERR10_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 4307 #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
AnnaBridge 171:3a7713b1edbc 4308 #define DMA_ERR_ERR11_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 4309 #define DMA_ERR_ERR11_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 4310 #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
AnnaBridge 171:3a7713b1edbc 4311 #define DMA_ERR_ERR12_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 4312 #define DMA_ERR_ERR12_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 4313 #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
AnnaBridge 171:3a7713b1edbc 4314 #define DMA_ERR_ERR13_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 4315 #define DMA_ERR_ERR13_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 4316 #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
AnnaBridge 171:3a7713b1edbc 4317 #define DMA_ERR_ERR14_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 4318 #define DMA_ERR_ERR14_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 4319 #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
AnnaBridge 171:3a7713b1edbc 4320 #define DMA_ERR_ERR15_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 4321 #define DMA_ERR_ERR15_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 4322 #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
AnnaBridge 171:3a7713b1edbc 4323 #define DMA_ERR_ERR16_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 4324 #define DMA_ERR_ERR16_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4325 #define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
AnnaBridge 171:3a7713b1edbc 4326 #define DMA_ERR_ERR17_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 4327 #define DMA_ERR_ERR17_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 4328 #define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
AnnaBridge 171:3a7713b1edbc 4329 #define DMA_ERR_ERR18_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 4330 #define DMA_ERR_ERR18_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 4331 #define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
AnnaBridge 171:3a7713b1edbc 4332 #define DMA_ERR_ERR19_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 4333 #define DMA_ERR_ERR19_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 4334 #define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
AnnaBridge 171:3a7713b1edbc 4335 #define DMA_ERR_ERR20_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 4336 #define DMA_ERR_ERR20_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 4337 #define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
AnnaBridge 171:3a7713b1edbc 4338 #define DMA_ERR_ERR21_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 4339 #define DMA_ERR_ERR21_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 4340 #define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
AnnaBridge 171:3a7713b1edbc 4341 #define DMA_ERR_ERR22_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 4342 #define DMA_ERR_ERR22_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 4343 #define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
AnnaBridge 171:3a7713b1edbc 4344 #define DMA_ERR_ERR23_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 4345 #define DMA_ERR_ERR23_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 4346 #define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
AnnaBridge 171:3a7713b1edbc 4347 #define DMA_ERR_ERR24_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 4348 #define DMA_ERR_ERR24_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4349 #define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
AnnaBridge 171:3a7713b1edbc 4350 #define DMA_ERR_ERR25_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 4351 #define DMA_ERR_ERR25_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 4352 #define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
AnnaBridge 171:3a7713b1edbc 4353 #define DMA_ERR_ERR26_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 4354 #define DMA_ERR_ERR26_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 4355 #define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
AnnaBridge 171:3a7713b1edbc 4356 #define DMA_ERR_ERR27_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 4357 #define DMA_ERR_ERR27_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 4358 #define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
AnnaBridge 171:3a7713b1edbc 4359 #define DMA_ERR_ERR28_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 4360 #define DMA_ERR_ERR28_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 4361 #define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
AnnaBridge 171:3a7713b1edbc 4362 #define DMA_ERR_ERR29_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 4363 #define DMA_ERR_ERR29_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 4364 #define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
AnnaBridge 171:3a7713b1edbc 4365 #define DMA_ERR_ERR30_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 4366 #define DMA_ERR_ERR30_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 4367 #define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
AnnaBridge 171:3a7713b1edbc 4368 #define DMA_ERR_ERR31_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 4369 #define DMA_ERR_ERR31_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 4370 #define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
AnnaBridge 171:3a7713b1edbc 4371
AnnaBridge 171:3a7713b1edbc 4372 /*! @name HRS - Hardware Request Status Register */
AnnaBridge 171:3a7713b1edbc 4373 #define DMA_HRS_HRS0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4374 #define DMA_HRS_HRS0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4375 #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
AnnaBridge 171:3a7713b1edbc 4376 #define DMA_HRS_HRS1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4377 #define DMA_HRS_HRS1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4378 #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
AnnaBridge 171:3a7713b1edbc 4379 #define DMA_HRS_HRS2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4380 #define DMA_HRS_HRS2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4381 #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
AnnaBridge 171:3a7713b1edbc 4382 #define DMA_HRS_HRS3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4383 #define DMA_HRS_HRS3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4384 #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
AnnaBridge 171:3a7713b1edbc 4385 #define DMA_HRS_HRS4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4386 #define DMA_HRS_HRS4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4387 #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
AnnaBridge 171:3a7713b1edbc 4388 #define DMA_HRS_HRS5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4389 #define DMA_HRS_HRS5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4390 #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
AnnaBridge 171:3a7713b1edbc 4391 #define DMA_HRS_HRS6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4392 #define DMA_HRS_HRS6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4393 #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
AnnaBridge 171:3a7713b1edbc 4394 #define DMA_HRS_HRS7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4395 #define DMA_HRS_HRS7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4396 #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
AnnaBridge 171:3a7713b1edbc 4397 #define DMA_HRS_HRS8_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 4398 #define DMA_HRS_HRS8_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4399 #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
AnnaBridge 171:3a7713b1edbc 4400 #define DMA_HRS_HRS9_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 4401 #define DMA_HRS_HRS9_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 4402 #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
AnnaBridge 171:3a7713b1edbc 4403 #define DMA_HRS_HRS10_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 4404 #define DMA_HRS_HRS10_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 4405 #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
AnnaBridge 171:3a7713b1edbc 4406 #define DMA_HRS_HRS11_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 4407 #define DMA_HRS_HRS11_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 4408 #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
AnnaBridge 171:3a7713b1edbc 4409 #define DMA_HRS_HRS12_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 4410 #define DMA_HRS_HRS12_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 4411 #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
AnnaBridge 171:3a7713b1edbc 4412 #define DMA_HRS_HRS13_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 4413 #define DMA_HRS_HRS13_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 4414 #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
AnnaBridge 171:3a7713b1edbc 4415 #define DMA_HRS_HRS14_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 4416 #define DMA_HRS_HRS14_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 4417 #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
AnnaBridge 171:3a7713b1edbc 4418 #define DMA_HRS_HRS15_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 4419 #define DMA_HRS_HRS15_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 4420 #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
AnnaBridge 171:3a7713b1edbc 4421 #define DMA_HRS_HRS16_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 4422 #define DMA_HRS_HRS16_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4423 #define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
AnnaBridge 171:3a7713b1edbc 4424 #define DMA_HRS_HRS17_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 4425 #define DMA_HRS_HRS17_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 4426 #define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
AnnaBridge 171:3a7713b1edbc 4427 #define DMA_HRS_HRS18_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 4428 #define DMA_HRS_HRS18_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 4429 #define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
AnnaBridge 171:3a7713b1edbc 4430 #define DMA_HRS_HRS19_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 4431 #define DMA_HRS_HRS19_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 4432 #define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
AnnaBridge 171:3a7713b1edbc 4433 #define DMA_HRS_HRS20_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 4434 #define DMA_HRS_HRS20_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 4435 #define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
AnnaBridge 171:3a7713b1edbc 4436 #define DMA_HRS_HRS21_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 4437 #define DMA_HRS_HRS21_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 4438 #define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
AnnaBridge 171:3a7713b1edbc 4439 #define DMA_HRS_HRS22_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 4440 #define DMA_HRS_HRS22_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 4441 #define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
AnnaBridge 171:3a7713b1edbc 4442 #define DMA_HRS_HRS23_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 4443 #define DMA_HRS_HRS23_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 4444 #define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
AnnaBridge 171:3a7713b1edbc 4445 #define DMA_HRS_HRS24_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 4446 #define DMA_HRS_HRS24_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4447 #define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
AnnaBridge 171:3a7713b1edbc 4448 #define DMA_HRS_HRS25_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 4449 #define DMA_HRS_HRS25_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 4450 #define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
AnnaBridge 171:3a7713b1edbc 4451 #define DMA_HRS_HRS26_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 4452 #define DMA_HRS_HRS26_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 4453 #define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
AnnaBridge 171:3a7713b1edbc 4454 #define DMA_HRS_HRS27_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 4455 #define DMA_HRS_HRS27_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 4456 #define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
AnnaBridge 171:3a7713b1edbc 4457 #define DMA_HRS_HRS28_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 4458 #define DMA_HRS_HRS28_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 4459 #define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
AnnaBridge 171:3a7713b1edbc 4460 #define DMA_HRS_HRS29_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 4461 #define DMA_HRS_HRS29_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 4462 #define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
AnnaBridge 171:3a7713b1edbc 4463 #define DMA_HRS_HRS30_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 4464 #define DMA_HRS_HRS30_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 4465 #define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
AnnaBridge 171:3a7713b1edbc 4466 #define DMA_HRS_HRS31_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 4467 #define DMA_HRS_HRS31_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 4468 #define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
AnnaBridge 171:3a7713b1edbc 4469
AnnaBridge 171:3a7713b1edbc 4470 /*! @name EARS - Enable Asynchronous Request in Stop Register */
AnnaBridge 171:3a7713b1edbc 4471 #define DMA_EARS_EDREQ_0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4472 #define DMA_EARS_EDREQ_0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4473 #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
AnnaBridge 171:3a7713b1edbc 4474 #define DMA_EARS_EDREQ_1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4475 #define DMA_EARS_EDREQ_1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4476 #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
AnnaBridge 171:3a7713b1edbc 4477 #define DMA_EARS_EDREQ_2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4478 #define DMA_EARS_EDREQ_2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4479 #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
AnnaBridge 171:3a7713b1edbc 4480 #define DMA_EARS_EDREQ_3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4481 #define DMA_EARS_EDREQ_3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4482 #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
AnnaBridge 171:3a7713b1edbc 4483 #define DMA_EARS_EDREQ_4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4484 #define DMA_EARS_EDREQ_4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4485 #define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
AnnaBridge 171:3a7713b1edbc 4486 #define DMA_EARS_EDREQ_5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4487 #define DMA_EARS_EDREQ_5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4488 #define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
AnnaBridge 171:3a7713b1edbc 4489 #define DMA_EARS_EDREQ_6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4490 #define DMA_EARS_EDREQ_6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4491 #define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
AnnaBridge 171:3a7713b1edbc 4492 #define DMA_EARS_EDREQ_7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4493 #define DMA_EARS_EDREQ_7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4494 #define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
AnnaBridge 171:3a7713b1edbc 4495 #define DMA_EARS_EDREQ_8_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 4496 #define DMA_EARS_EDREQ_8_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4497 #define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
AnnaBridge 171:3a7713b1edbc 4498 #define DMA_EARS_EDREQ_9_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 4499 #define DMA_EARS_EDREQ_9_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 4500 #define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
AnnaBridge 171:3a7713b1edbc 4501 #define DMA_EARS_EDREQ_10_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 4502 #define DMA_EARS_EDREQ_10_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 4503 #define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
AnnaBridge 171:3a7713b1edbc 4504 #define DMA_EARS_EDREQ_11_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 4505 #define DMA_EARS_EDREQ_11_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 4506 #define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
AnnaBridge 171:3a7713b1edbc 4507 #define DMA_EARS_EDREQ_12_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 4508 #define DMA_EARS_EDREQ_12_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 4509 #define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
AnnaBridge 171:3a7713b1edbc 4510 #define DMA_EARS_EDREQ_13_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 4511 #define DMA_EARS_EDREQ_13_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 4512 #define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
AnnaBridge 171:3a7713b1edbc 4513 #define DMA_EARS_EDREQ_14_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 4514 #define DMA_EARS_EDREQ_14_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 4515 #define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
AnnaBridge 171:3a7713b1edbc 4516 #define DMA_EARS_EDREQ_15_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 4517 #define DMA_EARS_EDREQ_15_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 4518 #define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
AnnaBridge 171:3a7713b1edbc 4519 #define DMA_EARS_EDREQ_16_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 4520 #define DMA_EARS_EDREQ_16_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4521 #define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
AnnaBridge 171:3a7713b1edbc 4522 #define DMA_EARS_EDREQ_17_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 4523 #define DMA_EARS_EDREQ_17_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 4524 #define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
AnnaBridge 171:3a7713b1edbc 4525 #define DMA_EARS_EDREQ_18_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 4526 #define DMA_EARS_EDREQ_18_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 4527 #define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
AnnaBridge 171:3a7713b1edbc 4528 #define DMA_EARS_EDREQ_19_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 4529 #define DMA_EARS_EDREQ_19_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 4530 #define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
AnnaBridge 171:3a7713b1edbc 4531 #define DMA_EARS_EDREQ_20_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 4532 #define DMA_EARS_EDREQ_20_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 4533 #define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
AnnaBridge 171:3a7713b1edbc 4534 #define DMA_EARS_EDREQ_21_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 4535 #define DMA_EARS_EDREQ_21_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 4536 #define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
AnnaBridge 171:3a7713b1edbc 4537 #define DMA_EARS_EDREQ_22_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 4538 #define DMA_EARS_EDREQ_22_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 4539 #define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
AnnaBridge 171:3a7713b1edbc 4540 #define DMA_EARS_EDREQ_23_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 4541 #define DMA_EARS_EDREQ_23_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 4542 #define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
AnnaBridge 171:3a7713b1edbc 4543 #define DMA_EARS_EDREQ_24_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 4544 #define DMA_EARS_EDREQ_24_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4545 #define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
AnnaBridge 171:3a7713b1edbc 4546 #define DMA_EARS_EDREQ_25_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 4547 #define DMA_EARS_EDREQ_25_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 4548 #define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
AnnaBridge 171:3a7713b1edbc 4549 #define DMA_EARS_EDREQ_26_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 4550 #define DMA_EARS_EDREQ_26_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 4551 #define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
AnnaBridge 171:3a7713b1edbc 4552 #define DMA_EARS_EDREQ_27_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 4553 #define DMA_EARS_EDREQ_27_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 4554 #define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
AnnaBridge 171:3a7713b1edbc 4555 #define DMA_EARS_EDREQ_28_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 4556 #define DMA_EARS_EDREQ_28_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 4557 #define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
AnnaBridge 171:3a7713b1edbc 4558 #define DMA_EARS_EDREQ_29_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 4559 #define DMA_EARS_EDREQ_29_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 4560 #define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
AnnaBridge 171:3a7713b1edbc 4561 #define DMA_EARS_EDREQ_30_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 4562 #define DMA_EARS_EDREQ_30_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 4563 #define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
AnnaBridge 171:3a7713b1edbc 4564 #define DMA_EARS_EDREQ_31_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 4565 #define DMA_EARS_EDREQ_31_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 4566 #define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
AnnaBridge 171:3a7713b1edbc 4567
AnnaBridge 171:3a7713b1edbc 4568 /*! @name DCHPRI3 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4569 #define DMA_DCHPRI3_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4570 #define DMA_DCHPRI3_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4571 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4572 #define DMA_DCHPRI3_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4573 #define DMA_DCHPRI3_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4574 #define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4575 #define DMA_DCHPRI3_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4576 #define DMA_DCHPRI3_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4577 #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4578 #define DMA_DCHPRI3_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4579 #define DMA_DCHPRI3_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4580 #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4581
AnnaBridge 171:3a7713b1edbc 4582 /*! @name DCHPRI2 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4583 #define DMA_DCHPRI2_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4584 #define DMA_DCHPRI2_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4585 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4586 #define DMA_DCHPRI2_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4587 #define DMA_DCHPRI2_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4588 #define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4589 #define DMA_DCHPRI2_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4590 #define DMA_DCHPRI2_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4591 #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4592 #define DMA_DCHPRI2_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4593 #define DMA_DCHPRI2_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4594 #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4595
AnnaBridge 171:3a7713b1edbc 4596 /*! @name DCHPRI1 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4597 #define DMA_DCHPRI1_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4598 #define DMA_DCHPRI1_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4599 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4600 #define DMA_DCHPRI1_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4601 #define DMA_DCHPRI1_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4602 #define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4603 #define DMA_DCHPRI1_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4604 #define DMA_DCHPRI1_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4605 #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4606 #define DMA_DCHPRI1_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4607 #define DMA_DCHPRI1_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4608 #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4609
AnnaBridge 171:3a7713b1edbc 4610 /*! @name DCHPRI0 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4611 #define DMA_DCHPRI0_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4612 #define DMA_DCHPRI0_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4613 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4614 #define DMA_DCHPRI0_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4615 #define DMA_DCHPRI0_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4616 #define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4617 #define DMA_DCHPRI0_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4618 #define DMA_DCHPRI0_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4619 #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4620 #define DMA_DCHPRI0_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4621 #define DMA_DCHPRI0_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4622 #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4623
AnnaBridge 171:3a7713b1edbc 4624 /*! @name DCHPRI7 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4625 #define DMA_DCHPRI7_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4626 #define DMA_DCHPRI7_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4627 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4628 #define DMA_DCHPRI7_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4629 #define DMA_DCHPRI7_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4630 #define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4631 #define DMA_DCHPRI7_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4632 #define DMA_DCHPRI7_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4633 #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4634 #define DMA_DCHPRI7_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4635 #define DMA_DCHPRI7_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4636 #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4637
AnnaBridge 171:3a7713b1edbc 4638 /*! @name DCHPRI6 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4639 #define DMA_DCHPRI6_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4640 #define DMA_DCHPRI6_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4641 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4642 #define DMA_DCHPRI6_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4643 #define DMA_DCHPRI6_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4644 #define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4645 #define DMA_DCHPRI6_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4646 #define DMA_DCHPRI6_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4647 #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4648 #define DMA_DCHPRI6_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4649 #define DMA_DCHPRI6_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4650 #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4651
AnnaBridge 171:3a7713b1edbc 4652 /*! @name DCHPRI5 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4653 #define DMA_DCHPRI5_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4654 #define DMA_DCHPRI5_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4655 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4656 #define DMA_DCHPRI5_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4657 #define DMA_DCHPRI5_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4658 #define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4659 #define DMA_DCHPRI5_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4660 #define DMA_DCHPRI5_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4661 #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4662 #define DMA_DCHPRI5_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4663 #define DMA_DCHPRI5_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4664 #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4665
AnnaBridge 171:3a7713b1edbc 4666 /*! @name DCHPRI4 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4667 #define DMA_DCHPRI4_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4668 #define DMA_DCHPRI4_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4669 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4670 #define DMA_DCHPRI4_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4671 #define DMA_DCHPRI4_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4672 #define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4673 #define DMA_DCHPRI4_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4674 #define DMA_DCHPRI4_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4675 #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4676 #define DMA_DCHPRI4_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4677 #define DMA_DCHPRI4_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4678 #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4679
AnnaBridge 171:3a7713b1edbc 4680 /*! @name DCHPRI11 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4681 #define DMA_DCHPRI11_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4682 #define DMA_DCHPRI11_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4683 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4684 #define DMA_DCHPRI11_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4685 #define DMA_DCHPRI11_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4686 #define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4687 #define DMA_DCHPRI11_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4688 #define DMA_DCHPRI11_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4689 #define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4690 #define DMA_DCHPRI11_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4691 #define DMA_DCHPRI11_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4692 #define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4693
AnnaBridge 171:3a7713b1edbc 4694 /*! @name DCHPRI10 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4695 #define DMA_DCHPRI10_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4696 #define DMA_DCHPRI10_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4697 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4698 #define DMA_DCHPRI10_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4699 #define DMA_DCHPRI10_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4700 #define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4701 #define DMA_DCHPRI10_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4702 #define DMA_DCHPRI10_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4703 #define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4704 #define DMA_DCHPRI10_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4705 #define DMA_DCHPRI10_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4706 #define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4707
AnnaBridge 171:3a7713b1edbc 4708 /*! @name DCHPRI9 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4709 #define DMA_DCHPRI9_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4710 #define DMA_DCHPRI9_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4711 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4712 #define DMA_DCHPRI9_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4713 #define DMA_DCHPRI9_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4714 #define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4715 #define DMA_DCHPRI9_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4716 #define DMA_DCHPRI9_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4717 #define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4718 #define DMA_DCHPRI9_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4719 #define DMA_DCHPRI9_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4720 #define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4721
AnnaBridge 171:3a7713b1edbc 4722 /*! @name DCHPRI8 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4723 #define DMA_DCHPRI8_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4724 #define DMA_DCHPRI8_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4725 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4726 #define DMA_DCHPRI8_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4727 #define DMA_DCHPRI8_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4728 #define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4729 #define DMA_DCHPRI8_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4730 #define DMA_DCHPRI8_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4731 #define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4732 #define DMA_DCHPRI8_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4733 #define DMA_DCHPRI8_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4734 #define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4735
AnnaBridge 171:3a7713b1edbc 4736 /*! @name DCHPRI15 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4737 #define DMA_DCHPRI15_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4738 #define DMA_DCHPRI15_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4739 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4740 #define DMA_DCHPRI15_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4741 #define DMA_DCHPRI15_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4742 #define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4743 #define DMA_DCHPRI15_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4744 #define DMA_DCHPRI15_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4745 #define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4746 #define DMA_DCHPRI15_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4747 #define DMA_DCHPRI15_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4748 #define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4749
AnnaBridge 171:3a7713b1edbc 4750 /*! @name DCHPRI14 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4751 #define DMA_DCHPRI14_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4752 #define DMA_DCHPRI14_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4753 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4754 #define DMA_DCHPRI14_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4755 #define DMA_DCHPRI14_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4756 #define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4757 #define DMA_DCHPRI14_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4758 #define DMA_DCHPRI14_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4759 #define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4760 #define DMA_DCHPRI14_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4761 #define DMA_DCHPRI14_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4762 #define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4763
AnnaBridge 171:3a7713b1edbc 4764 /*! @name DCHPRI13 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4765 #define DMA_DCHPRI13_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4766 #define DMA_DCHPRI13_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4767 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4768 #define DMA_DCHPRI13_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4769 #define DMA_DCHPRI13_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4770 #define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4771 #define DMA_DCHPRI13_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4772 #define DMA_DCHPRI13_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4773 #define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4774 #define DMA_DCHPRI13_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4775 #define DMA_DCHPRI13_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4776 #define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4777
AnnaBridge 171:3a7713b1edbc 4778 /*! @name DCHPRI12 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4779 #define DMA_DCHPRI12_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4780 #define DMA_DCHPRI12_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4781 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4782 #define DMA_DCHPRI12_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4783 #define DMA_DCHPRI12_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4784 #define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4785 #define DMA_DCHPRI12_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4786 #define DMA_DCHPRI12_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4787 #define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4788 #define DMA_DCHPRI12_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4789 #define DMA_DCHPRI12_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4790 #define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4791
AnnaBridge 171:3a7713b1edbc 4792 /*! @name DCHPRI19 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4793 #define DMA_DCHPRI19_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4794 #define DMA_DCHPRI19_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4795 #define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4796 #define DMA_DCHPRI19_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4797 #define DMA_DCHPRI19_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4798 #define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4799 #define DMA_DCHPRI19_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4800 #define DMA_DCHPRI19_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4801 #define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4802 #define DMA_DCHPRI19_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4803 #define DMA_DCHPRI19_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4804 #define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4805
AnnaBridge 171:3a7713b1edbc 4806 /*! @name DCHPRI18 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4807 #define DMA_DCHPRI18_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4808 #define DMA_DCHPRI18_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4809 #define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4810 #define DMA_DCHPRI18_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4811 #define DMA_DCHPRI18_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4812 #define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4813 #define DMA_DCHPRI18_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4814 #define DMA_DCHPRI18_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4815 #define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4816 #define DMA_DCHPRI18_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4817 #define DMA_DCHPRI18_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4818 #define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4819
AnnaBridge 171:3a7713b1edbc 4820 /*! @name DCHPRI17 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4821 #define DMA_DCHPRI17_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4822 #define DMA_DCHPRI17_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4823 #define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4824 #define DMA_DCHPRI17_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4825 #define DMA_DCHPRI17_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4826 #define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4827 #define DMA_DCHPRI17_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4828 #define DMA_DCHPRI17_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4829 #define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4830 #define DMA_DCHPRI17_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4831 #define DMA_DCHPRI17_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4832 #define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4833
AnnaBridge 171:3a7713b1edbc 4834 /*! @name DCHPRI16 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4835 #define DMA_DCHPRI16_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4836 #define DMA_DCHPRI16_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4837 #define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4838 #define DMA_DCHPRI16_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4839 #define DMA_DCHPRI16_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4840 #define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4841 #define DMA_DCHPRI16_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4842 #define DMA_DCHPRI16_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4843 #define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4844 #define DMA_DCHPRI16_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4845 #define DMA_DCHPRI16_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4846 #define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4847
AnnaBridge 171:3a7713b1edbc 4848 /*! @name DCHPRI23 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4849 #define DMA_DCHPRI23_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4850 #define DMA_DCHPRI23_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4851 #define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4852 #define DMA_DCHPRI23_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4853 #define DMA_DCHPRI23_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4854 #define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4855 #define DMA_DCHPRI23_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4856 #define DMA_DCHPRI23_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4857 #define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4858 #define DMA_DCHPRI23_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4859 #define DMA_DCHPRI23_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4860 #define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4861
AnnaBridge 171:3a7713b1edbc 4862 /*! @name DCHPRI22 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4863 #define DMA_DCHPRI22_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4864 #define DMA_DCHPRI22_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4865 #define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4866 #define DMA_DCHPRI22_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4867 #define DMA_DCHPRI22_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4868 #define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4869 #define DMA_DCHPRI22_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4870 #define DMA_DCHPRI22_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4871 #define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4872 #define DMA_DCHPRI22_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4873 #define DMA_DCHPRI22_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4874 #define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4875
AnnaBridge 171:3a7713b1edbc 4876 /*! @name DCHPRI21 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4877 #define DMA_DCHPRI21_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4878 #define DMA_DCHPRI21_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4879 #define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4880 #define DMA_DCHPRI21_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4881 #define DMA_DCHPRI21_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4882 #define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4883 #define DMA_DCHPRI21_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4884 #define DMA_DCHPRI21_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4885 #define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4886 #define DMA_DCHPRI21_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4887 #define DMA_DCHPRI21_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4888 #define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4889
AnnaBridge 171:3a7713b1edbc 4890 /*! @name DCHPRI20 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4891 #define DMA_DCHPRI20_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4892 #define DMA_DCHPRI20_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4893 #define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4894 #define DMA_DCHPRI20_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4895 #define DMA_DCHPRI20_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4896 #define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4897 #define DMA_DCHPRI20_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4898 #define DMA_DCHPRI20_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4899 #define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4900 #define DMA_DCHPRI20_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4901 #define DMA_DCHPRI20_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4902 #define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4903
AnnaBridge 171:3a7713b1edbc 4904 /*! @name DCHPRI27 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4905 #define DMA_DCHPRI27_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4906 #define DMA_DCHPRI27_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4907 #define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4908 #define DMA_DCHPRI27_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4909 #define DMA_DCHPRI27_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4910 #define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4911 #define DMA_DCHPRI27_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4912 #define DMA_DCHPRI27_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4913 #define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4914 #define DMA_DCHPRI27_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4915 #define DMA_DCHPRI27_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4916 #define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4917
AnnaBridge 171:3a7713b1edbc 4918 /*! @name DCHPRI26 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4919 #define DMA_DCHPRI26_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4920 #define DMA_DCHPRI26_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4921 #define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4922 #define DMA_DCHPRI26_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4923 #define DMA_DCHPRI26_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4924 #define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4925 #define DMA_DCHPRI26_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4926 #define DMA_DCHPRI26_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4927 #define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4928 #define DMA_DCHPRI26_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4929 #define DMA_DCHPRI26_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4930 #define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4931
AnnaBridge 171:3a7713b1edbc 4932 /*! @name DCHPRI25 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4933 #define DMA_DCHPRI25_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4934 #define DMA_DCHPRI25_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4935 #define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4936 #define DMA_DCHPRI25_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4937 #define DMA_DCHPRI25_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4938 #define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4939 #define DMA_DCHPRI25_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4940 #define DMA_DCHPRI25_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4941 #define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4942 #define DMA_DCHPRI25_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4943 #define DMA_DCHPRI25_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4944 #define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4945
AnnaBridge 171:3a7713b1edbc 4946 /*! @name DCHPRI24 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4947 #define DMA_DCHPRI24_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4948 #define DMA_DCHPRI24_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4949 #define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4950 #define DMA_DCHPRI24_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4951 #define DMA_DCHPRI24_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4952 #define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4953 #define DMA_DCHPRI24_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4954 #define DMA_DCHPRI24_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4955 #define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4956 #define DMA_DCHPRI24_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4957 #define DMA_DCHPRI24_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4958 #define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4959
AnnaBridge 171:3a7713b1edbc 4960 /*! @name DCHPRI31 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4961 #define DMA_DCHPRI31_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4962 #define DMA_DCHPRI31_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4963 #define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4964 #define DMA_DCHPRI31_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4965 #define DMA_DCHPRI31_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4966 #define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4967 #define DMA_DCHPRI31_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4968 #define DMA_DCHPRI31_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4969 #define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4970 #define DMA_DCHPRI31_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4971 #define DMA_DCHPRI31_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4972 #define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4973
AnnaBridge 171:3a7713b1edbc 4974 /*! @name DCHPRI30 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4975 #define DMA_DCHPRI30_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4976 #define DMA_DCHPRI30_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4977 #define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4978 #define DMA_DCHPRI30_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4979 #define DMA_DCHPRI30_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4980 #define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4981 #define DMA_DCHPRI30_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4982 #define DMA_DCHPRI30_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4983 #define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4984 #define DMA_DCHPRI30_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4985 #define DMA_DCHPRI30_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4986 #define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4987
AnnaBridge 171:3a7713b1edbc 4988 /*! @name DCHPRI29 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4989 #define DMA_DCHPRI29_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4990 #define DMA_DCHPRI29_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4991 #define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4992 #define DMA_DCHPRI29_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4993 #define DMA_DCHPRI29_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4994 #define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4995 #define DMA_DCHPRI29_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4996 #define DMA_DCHPRI29_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4997 #define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4998 #define DMA_DCHPRI29_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4999 #define DMA_DCHPRI29_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5000 #define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 5001
AnnaBridge 171:3a7713b1edbc 5002 /*! @name DCHPRI28 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 5003 #define DMA_DCHPRI28_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 5004 #define DMA_DCHPRI28_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5005 #define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 5006 #define DMA_DCHPRI28_GRPPRI_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 5007 #define DMA_DCHPRI28_GRPPRI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5008 #define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
AnnaBridge 171:3a7713b1edbc 5009 #define DMA_DCHPRI28_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5010 #define DMA_DCHPRI28_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5011 #define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 5012 #define DMA_DCHPRI28_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5013 #define DMA_DCHPRI28_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5014 #define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 5015
AnnaBridge 171:3a7713b1edbc 5016 /*! @name SADDR - TCD Source Address */
AnnaBridge 171:3a7713b1edbc 5017 #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5018 #define DMA_SADDR_SADDR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5019 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
AnnaBridge 171:3a7713b1edbc 5020
AnnaBridge 171:3a7713b1edbc 5021 /* The count of DMA_SADDR */
AnnaBridge 171:3a7713b1edbc 5022 #define DMA_SADDR_COUNT (32U)
AnnaBridge 171:3a7713b1edbc 5023
AnnaBridge 171:3a7713b1edbc 5024 /*! @name SOFF - TCD Signed Source Address Offset */
AnnaBridge 171:3a7713b1edbc 5025 #define DMA_SOFF_SOFF_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5026 #define DMA_SOFF_SOFF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5027 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
AnnaBridge 171:3a7713b1edbc 5028
AnnaBridge 171:3a7713b1edbc 5029 /* The count of DMA_SOFF */
AnnaBridge 171:3a7713b1edbc 5030 #define DMA_SOFF_COUNT (32U)
AnnaBridge 171:3a7713b1edbc 5031
AnnaBridge 171:3a7713b1edbc 5032 /*! @name ATTR - TCD Transfer Attributes */
AnnaBridge 171:3a7713b1edbc 5033 #define DMA_ATTR_DSIZE_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 5034 #define DMA_ATTR_DSIZE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5035 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 5036 #define DMA_ATTR_DMOD_MASK (0xF8U)
AnnaBridge 171:3a7713b1edbc 5037 #define DMA_ATTR_DMOD_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5038 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
AnnaBridge 171:3a7713b1edbc 5039 #define DMA_ATTR_SSIZE_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 5040 #define DMA_ATTR_SSIZE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 5041 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 5042 #define DMA_ATTR_SMOD_MASK (0xF800U)
AnnaBridge 171:3a7713b1edbc 5043 #define DMA_ATTR_SMOD_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 5044 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
AnnaBridge 171:3a7713b1edbc 5045
AnnaBridge 171:3a7713b1edbc 5046 /* The count of DMA_ATTR */
AnnaBridge 171:3a7713b1edbc 5047 #define DMA_ATTR_COUNT (32U)
AnnaBridge 171:3a7713b1edbc 5048
AnnaBridge 171:3a7713b1edbc 5049 /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
AnnaBridge 171:3a7713b1edbc 5050 #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5051 #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5052 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
AnnaBridge 171:3a7713b1edbc 5053
AnnaBridge 171:3a7713b1edbc 5054 /* The count of DMA_NBYTES_MLNO */
AnnaBridge 171:3a7713b1edbc 5055 #define DMA_NBYTES_MLNO_COUNT (32U)
AnnaBridge 171:3a7713b1edbc 5056
AnnaBridge 171:3a7713b1edbc 5057 /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
AnnaBridge 171:3a7713b1edbc 5058 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5059 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5060 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
AnnaBridge 171:3a7713b1edbc 5061 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 5062 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 5063 #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
AnnaBridge 171:3a7713b1edbc 5064 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 5065 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 5066 #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
AnnaBridge 171:3a7713b1edbc 5067
AnnaBridge 171:3a7713b1edbc 5068 /* The count of DMA_NBYTES_MLOFFNO */
AnnaBridge 171:3a7713b1edbc 5069 #define DMA_NBYTES_MLOFFNO_COUNT (32U)
AnnaBridge 171:3a7713b1edbc 5070
AnnaBridge 171:3a7713b1edbc 5071 /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
AnnaBridge 171:3a7713b1edbc 5072 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 5073 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5074 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
AnnaBridge 171:3a7713b1edbc 5075 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
AnnaBridge 171:3a7713b1edbc 5076 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 5077 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
AnnaBridge 171:3a7713b1edbc 5078 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 5079 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 5080 #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
AnnaBridge 171:3a7713b1edbc 5081 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 5082 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 5083 #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
AnnaBridge 171:3a7713b1edbc 5084
AnnaBridge 171:3a7713b1edbc 5085 /* The count of DMA_NBYTES_MLOFFYES */
AnnaBridge 171:3a7713b1edbc 5086 #define DMA_NBYTES_MLOFFYES_COUNT (32U)
AnnaBridge 171:3a7713b1edbc 5087
AnnaBridge 171:3a7713b1edbc 5088 /*! @name SLAST - TCD Last Source Address Adjustment */
AnnaBridge 171:3a7713b1edbc 5089 #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5090 #define DMA_SLAST_SLAST_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5091 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
AnnaBridge 171:3a7713b1edbc 5092
AnnaBridge 171:3a7713b1edbc 5093 /* The count of DMA_SLAST */
AnnaBridge 171:3a7713b1edbc 5094 #define DMA_SLAST_COUNT (32U)
AnnaBridge 171:3a7713b1edbc 5095
AnnaBridge 171:3a7713b1edbc 5096 /*! @name DADDR - TCD Destination Address */
AnnaBridge 171:3a7713b1edbc 5097 #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5098 #define DMA_DADDR_DADDR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5099 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
AnnaBridge 171:3a7713b1edbc 5100
AnnaBridge 171:3a7713b1edbc 5101 /* The count of DMA_DADDR */
AnnaBridge 171:3a7713b1edbc 5102 #define DMA_DADDR_COUNT (32U)
AnnaBridge 171:3a7713b1edbc 5103
AnnaBridge 171:3a7713b1edbc 5104 /*! @name DOFF - TCD Signed Destination Address Offset */
AnnaBridge 171:3a7713b1edbc 5105 #define DMA_DOFF_DOFF_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5106 #define DMA_DOFF_DOFF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5107 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
AnnaBridge 171:3a7713b1edbc 5108
AnnaBridge 171:3a7713b1edbc 5109 /* The count of DMA_DOFF */
AnnaBridge 171:3a7713b1edbc 5110 #define DMA_DOFF_COUNT (32U)
AnnaBridge 171:3a7713b1edbc 5111
AnnaBridge 171:3a7713b1edbc 5112 /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
AnnaBridge 171:3a7713b1edbc 5113 #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
AnnaBridge 171:3a7713b1edbc 5114 #define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5115 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
AnnaBridge 171:3a7713b1edbc 5116 #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 5117 #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 5118 #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
AnnaBridge 171:3a7713b1edbc 5119
AnnaBridge 171:3a7713b1edbc 5120 /* The count of DMA_CITER_ELINKNO */
AnnaBridge 171:3a7713b1edbc 5121 #define DMA_CITER_ELINKNO_COUNT (32U)
AnnaBridge 171:3a7713b1edbc 5122
AnnaBridge 171:3a7713b1edbc 5123 /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
AnnaBridge 171:3a7713b1edbc 5124 #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 5125 #define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5126 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
AnnaBridge 171:3a7713b1edbc 5127 #define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
AnnaBridge 171:3a7713b1edbc 5128 #define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 5129 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
AnnaBridge 171:3a7713b1edbc 5130 #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 5131 #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 5132 #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
AnnaBridge 171:3a7713b1edbc 5133
AnnaBridge 171:3a7713b1edbc 5134 /* The count of DMA_CITER_ELINKYES */
AnnaBridge 171:3a7713b1edbc 5135 #define DMA_CITER_ELINKYES_COUNT (32U)
AnnaBridge 171:3a7713b1edbc 5136
AnnaBridge 171:3a7713b1edbc 5137 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
AnnaBridge 171:3a7713b1edbc 5138 #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5139 #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5140 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
AnnaBridge 171:3a7713b1edbc 5141
AnnaBridge 171:3a7713b1edbc 5142 /* The count of DMA_DLAST_SGA */
AnnaBridge 171:3a7713b1edbc 5143 #define DMA_DLAST_SGA_COUNT (32U)
AnnaBridge 171:3a7713b1edbc 5144
AnnaBridge 171:3a7713b1edbc 5145 /*! @name CSR - TCD Control and Status */
AnnaBridge 171:3a7713b1edbc 5146 #define DMA_CSR_START_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5147 #define DMA_CSR_START_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5148 #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
AnnaBridge 171:3a7713b1edbc 5149 #define DMA_CSR_INTMAJOR_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5150 #define DMA_CSR_INTMAJOR_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5151 #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
AnnaBridge 171:3a7713b1edbc 5152 #define DMA_CSR_INTHALF_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5153 #define DMA_CSR_INTHALF_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5154 #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
AnnaBridge 171:3a7713b1edbc 5155 #define DMA_CSR_DREQ_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5156 #define DMA_CSR_DREQ_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5157 #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
AnnaBridge 171:3a7713b1edbc 5158 #define DMA_CSR_ESG_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5159 #define DMA_CSR_ESG_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5160 #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
AnnaBridge 171:3a7713b1edbc 5161 #define DMA_CSR_MAJORELINK_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5162 #define DMA_CSR_MAJORELINK_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5163 #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
AnnaBridge 171:3a7713b1edbc 5164 #define DMA_CSR_ACTIVE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5165 #define DMA_CSR_ACTIVE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5166 #define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
AnnaBridge 171:3a7713b1edbc 5167 #define DMA_CSR_DONE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5168 #define DMA_CSR_DONE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5169 #define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
AnnaBridge 171:3a7713b1edbc 5170 #define DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
AnnaBridge 171:3a7713b1edbc 5171 #define DMA_CSR_MAJORLINKCH_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 5172 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
AnnaBridge 171:3a7713b1edbc 5173 #define DMA_CSR_BWC_MASK (0xC000U)
AnnaBridge 171:3a7713b1edbc 5174 #define DMA_CSR_BWC_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 5175 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
AnnaBridge 171:3a7713b1edbc 5176
AnnaBridge 171:3a7713b1edbc 5177 /* The count of DMA_CSR */
AnnaBridge 171:3a7713b1edbc 5178 #define DMA_CSR_COUNT (32U)
AnnaBridge 171:3a7713b1edbc 5179
AnnaBridge 171:3a7713b1edbc 5180 /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
AnnaBridge 171:3a7713b1edbc 5181 #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
AnnaBridge 171:3a7713b1edbc 5182 #define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5183 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
AnnaBridge 171:3a7713b1edbc 5184 #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 5185 #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 5186 #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
AnnaBridge 171:3a7713b1edbc 5187
AnnaBridge 171:3a7713b1edbc 5188 /* The count of DMA_BITER_ELINKNO */
AnnaBridge 171:3a7713b1edbc 5189 #define DMA_BITER_ELINKNO_COUNT (32U)
AnnaBridge 171:3a7713b1edbc 5190
AnnaBridge 171:3a7713b1edbc 5191 /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
AnnaBridge 171:3a7713b1edbc 5192 #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 5193 #define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5194 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
AnnaBridge 171:3a7713b1edbc 5195 #define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
AnnaBridge 171:3a7713b1edbc 5196 #define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 5197 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
AnnaBridge 171:3a7713b1edbc 5198 #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 5199 #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 5200 #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
AnnaBridge 171:3a7713b1edbc 5201
AnnaBridge 171:3a7713b1edbc 5202 /* The count of DMA_BITER_ELINKYES */
AnnaBridge 171:3a7713b1edbc 5203 #define DMA_BITER_ELINKYES_COUNT (32U)
AnnaBridge 171:3a7713b1edbc 5204
AnnaBridge 171:3a7713b1edbc 5205
AnnaBridge 171:3a7713b1edbc 5206 /*!
AnnaBridge 171:3a7713b1edbc 5207 * @}
AnnaBridge 171:3a7713b1edbc 5208 */ /* end of group DMA_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5209
AnnaBridge 171:3a7713b1edbc 5210
AnnaBridge 171:3a7713b1edbc 5211 /* DMA - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5212 /** Peripheral DMA base address */
AnnaBridge 171:3a7713b1edbc 5213 #define DMA_BASE (0x40008000u)
AnnaBridge 171:3a7713b1edbc 5214 /** Peripheral DMA base pointer */
AnnaBridge 171:3a7713b1edbc 5215 #define DMA0 ((DMA_Type *)DMA_BASE)
AnnaBridge 171:3a7713b1edbc 5216 /** Array initializer of DMA peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5217 #define DMA_BASE_ADDRS { DMA_BASE }
AnnaBridge 171:3a7713b1edbc 5218 /** Array initializer of DMA peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5219 #define DMA_BASE_PTRS { DMA0 }
AnnaBridge 171:3a7713b1edbc 5220 /** Interrupt vectors for the DMA peripheral type */
AnnaBridge 171:3a7713b1edbc 5221 #define DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
AnnaBridge 171:3a7713b1edbc 5222 #define DMA_ERROR_IRQS { DMA_Error_IRQn }
AnnaBridge 171:3a7713b1edbc 5223
AnnaBridge 171:3a7713b1edbc 5224 /*!
AnnaBridge 171:3a7713b1edbc 5225 * @}
AnnaBridge 171:3a7713b1edbc 5226 */ /* end of group DMA_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5227
AnnaBridge 171:3a7713b1edbc 5228
AnnaBridge 171:3a7713b1edbc 5229 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5230 -- DMAMUX Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5231 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5232
AnnaBridge 171:3a7713b1edbc 5233 /*!
AnnaBridge 171:3a7713b1edbc 5234 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5235 * @{
AnnaBridge 171:3a7713b1edbc 5236 */
AnnaBridge 171:3a7713b1edbc 5237
AnnaBridge 171:3a7713b1edbc 5238 /** DMAMUX - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5239 typedef struct {
AnnaBridge 171:3a7713b1edbc 5240 __IO uint8_t CHCFG[32]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
AnnaBridge 171:3a7713b1edbc 5241 } DMAMUX_Type;
AnnaBridge 171:3a7713b1edbc 5242
AnnaBridge 171:3a7713b1edbc 5243 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5244 -- DMAMUX Register Masks
AnnaBridge 171:3a7713b1edbc 5245 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5246
AnnaBridge 171:3a7713b1edbc 5247 /*!
AnnaBridge 171:3a7713b1edbc 5248 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
AnnaBridge 171:3a7713b1edbc 5249 * @{
AnnaBridge 171:3a7713b1edbc 5250 */
AnnaBridge 171:3a7713b1edbc 5251
AnnaBridge 171:3a7713b1edbc 5252 /*! @name CHCFG - Channel Configuration register */
AnnaBridge 171:3a7713b1edbc 5253 #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 5254 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5255 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
AnnaBridge 171:3a7713b1edbc 5256 #define DMAMUX_CHCFG_TRIG_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5257 #define DMAMUX_CHCFG_TRIG_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5258 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 5259 #define DMAMUX_CHCFG_ENBL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5260 #define DMAMUX_CHCFG_ENBL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5261 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
AnnaBridge 171:3a7713b1edbc 5262
AnnaBridge 171:3a7713b1edbc 5263 /* The count of DMAMUX_CHCFG */
AnnaBridge 171:3a7713b1edbc 5264 #define DMAMUX_CHCFG_COUNT (32U)
AnnaBridge 171:3a7713b1edbc 5265
AnnaBridge 171:3a7713b1edbc 5266
AnnaBridge 171:3a7713b1edbc 5267 /*!
AnnaBridge 171:3a7713b1edbc 5268 * @}
AnnaBridge 171:3a7713b1edbc 5269 */ /* end of group DMAMUX_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5270
AnnaBridge 171:3a7713b1edbc 5271
AnnaBridge 171:3a7713b1edbc 5272 /* DMAMUX - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5273 /** Peripheral DMAMUX base address */
AnnaBridge 171:3a7713b1edbc 5274 #define DMAMUX_BASE (0x40021000u)
AnnaBridge 171:3a7713b1edbc 5275 /** Peripheral DMAMUX base pointer */
AnnaBridge 171:3a7713b1edbc 5276 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
AnnaBridge 171:3a7713b1edbc 5277 /** Array initializer of DMAMUX peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5278 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
AnnaBridge 171:3a7713b1edbc 5279 /** Array initializer of DMAMUX peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5280 #define DMAMUX_BASE_PTRS { DMAMUX }
AnnaBridge 171:3a7713b1edbc 5281
AnnaBridge 171:3a7713b1edbc 5282 /*!
AnnaBridge 171:3a7713b1edbc 5283 * @}
AnnaBridge 171:3a7713b1edbc 5284 */ /* end of group DMAMUX_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5285
AnnaBridge 171:3a7713b1edbc 5286
AnnaBridge 171:3a7713b1edbc 5287 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5288 -- ENET Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5289 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5290
AnnaBridge 171:3a7713b1edbc 5291 /*!
AnnaBridge 171:3a7713b1edbc 5292 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5293 * @{
AnnaBridge 171:3a7713b1edbc 5294 */
AnnaBridge 171:3a7713b1edbc 5295
AnnaBridge 171:3a7713b1edbc 5296 /** ENET - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5297 typedef struct {
AnnaBridge 171:3a7713b1edbc 5298 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 5299 __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 5300 __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 5301 uint8_t RESERVED_1[4];
AnnaBridge 171:3a7713b1edbc 5302 __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 5303 __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 5304 uint8_t RESERVED_2[12];
AnnaBridge 171:3a7713b1edbc 5305 __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 5306 uint8_t RESERVED_3[24];
AnnaBridge 171:3a7713b1edbc 5307 __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 5308 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 5309 uint8_t RESERVED_4[28];
AnnaBridge 171:3a7713b1edbc 5310 __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 5311 uint8_t RESERVED_5[28];
AnnaBridge 171:3a7713b1edbc 5312 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 5313 uint8_t RESERVED_6[60];
AnnaBridge 171:3a7713b1edbc 5314 __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
AnnaBridge 171:3a7713b1edbc 5315 uint8_t RESERVED_7[28];
AnnaBridge 171:3a7713b1edbc 5316 __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
AnnaBridge 171:3a7713b1edbc 5317 __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
AnnaBridge 171:3a7713b1edbc 5318 __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
AnnaBridge 171:3a7713b1edbc 5319 uint8_t RESERVED_8[40];
AnnaBridge 171:3a7713b1edbc 5320 __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
AnnaBridge 171:3a7713b1edbc 5321 __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
AnnaBridge 171:3a7713b1edbc 5322 __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
AnnaBridge 171:3a7713b1edbc 5323 __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
AnnaBridge 171:3a7713b1edbc 5324 uint8_t RESERVED_9[28];
AnnaBridge 171:3a7713b1edbc 5325 __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
AnnaBridge 171:3a7713b1edbc 5326 uint8_t RESERVED_10[56];
AnnaBridge 171:3a7713b1edbc 5327 __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */
AnnaBridge 171:3a7713b1edbc 5328 __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
AnnaBridge 171:3a7713b1edbc 5329 __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */
AnnaBridge 171:3a7713b1edbc 5330 uint8_t RESERVED_11[4];
AnnaBridge 171:3a7713b1edbc 5331 __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
AnnaBridge 171:3a7713b1edbc 5332 __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
AnnaBridge 171:3a7713b1edbc 5333 __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
AnnaBridge 171:3a7713b1edbc 5334 __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
AnnaBridge 171:3a7713b1edbc 5335 __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
AnnaBridge 171:3a7713b1edbc 5336 __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
AnnaBridge 171:3a7713b1edbc 5337 __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
AnnaBridge 171:3a7713b1edbc 5338 __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
AnnaBridge 171:3a7713b1edbc 5339 __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
AnnaBridge 171:3a7713b1edbc 5340 uint8_t RESERVED_12[12];
AnnaBridge 171:3a7713b1edbc 5341 __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
AnnaBridge 171:3a7713b1edbc 5342 __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
AnnaBridge 171:3a7713b1edbc 5343 uint8_t RESERVED_13[56];
AnnaBridge 171:3a7713b1edbc 5344 __I uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */
AnnaBridge 171:3a7713b1edbc 5345 __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
AnnaBridge 171:3a7713b1edbc 5346 __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
AnnaBridge 171:3a7713b1edbc 5347 __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
AnnaBridge 171:3a7713b1edbc 5348 __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
AnnaBridge 171:3a7713b1edbc 5349 __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
AnnaBridge 171:3a7713b1edbc 5350 __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
AnnaBridge 171:3a7713b1edbc 5351 __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
AnnaBridge 171:3a7713b1edbc 5352 __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
AnnaBridge 171:3a7713b1edbc 5353 __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
AnnaBridge 171:3a7713b1edbc 5354 __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
AnnaBridge 171:3a7713b1edbc 5355 __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
AnnaBridge 171:3a7713b1edbc 5356 __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
AnnaBridge 171:3a7713b1edbc 5357 __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
AnnaBridge 171:3a7713b1edbc 5358 __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
AnnaBridge 171:3a7713b1edbc 5359 __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
AnnaBridge 171:3a7713b1edbc 5360 __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
AnnaBridge 171:3a7713b1edbc 5361 __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
AnnaBridge 171:3a7713b1edbc 5362 __I uint32_t IEEE_T_DROP; /**< IEEE_T_DROP Reserved Statistic Register, offset: 0x248 */
AnnaBridge 171:3a7713b1edbc 5363 __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
AnnaBridge 171:3a7713b1edbc 5364 __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
AnnaBridge 171:3a7713b1edbc 5365 __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
AnnaBridge 171:3a7713b1edbc 5366 __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
AnnaBridge 171:3a7713b1edbc 5367 __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
AnnaBridge 171:3a7713b1edbc 5368 __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
AnnaBridge 171:3a7713b1edbc 5369 __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
AnnaBridge 171:3a7713b1edbc 5370 __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
AnnaBridge 171:3a7713b1edbc 5371 __I uint32_t IEEE_T_SQE; /**< , offset: 0x26C */
AnnaBridge 171:3a7713b1edbc 5372 __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
AnnaBridge 171:3a7713b1edbc 5373 __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
AnnaBridge 171:3a7713b1edbc 5374 uint8_t RESERVED_14[12];
AnnaBridge 171:3a7713b1edbc 5375 __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
AnnaBridge 171:3a7713b1edbc 5376 __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
AnnaBridge 171:3a7713b1edbc 5377 __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
AnnaBridge 171:3a7713b1edbc 5378 __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
AnnaBridge 171:3a7713b1edbc 5379 __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
AnnaBridge 171:3a7713b1edbc 5380 __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
AnnaBridge 171:3a7713b1edbc 5381 __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
AnnaBridge 171:3a7713b1edbc 5382 __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
AnnaBridge 171:3a7713b1edbc 5383 __I uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */
AnnaBridge 171:3a7713b1edbc 5384 __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
AnnaBridge 171:3a7713b1edbc 5385 __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
AnnaBridge 171:3a7713b1edbc 5386 __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
AnnaBridge 171:3a7713b1edbc 5387 __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
AnnaBridge 171:3a7713b1edbc 5388 __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
AnnaBridge 171:3a7713b1edbc 5389 __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
AnnaBridge 171:3a7713b1edbc 5390 __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
AnnaBridge 171:3a7713b1edbc 5391 __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
AnnaBridge 171:3a7713b1edbc 5392 __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
AnnaBridge 171:3a7713b1edbc 5393 __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
AnnaBridge 171:3a7713b1edbc 5394 __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
AnnaBridge 171:3a7713b1edbc 5395 __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
AnnaBridge 171:3a7713b1edbc 5396 __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
AnnaBridge 171:3a7713b1edbc 5397 __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
AnnaBridge 171:3a7713b1edbc 5398 __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
AnnaBridge 171:3a7713b1edbc 5399 uint8_t RESERVED_15[284];
AnnaBridge 171:3a7713b1edbc 5400 __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
AnnaBridge 171:3a7713b1edbc 5401 __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
AnnaBridge 171:3a7713b1edbc 5402 __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
AnnaBridge 171:3a7713b1edbc 5403 __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
AnnaBridge 171:3a7713b1edbc 5404 __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
AnnaBridge 171:3a7713b1edbc 5405 __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
AnnaBridge 171:3a7713b1edbc 5406 __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
AnnaBridge 171:3a7713b1edbc 5407 uint8_t RESERVED_16[488];
AnnaBridge 171:3a7713b1edbc 5408 __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
AnnaBridge 171:3a7713b1edbc 5409 struct { /* offset: 0x608, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 5410 __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 5411 __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 5412 } CHANNEL[4];
AnnaBridge 171:3a7713b1edbc 5413 } ENET_Type;
AnnaBridge 171:3a7713b1edbc 5414
AnnaBridge 171:3a7713b1edbc 5415 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5416 -- ENET Register Masks
AnnaBridge 171:3a7713b1edbc 5417 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5418
AnnaBridge 171:3a7713b1edbc 5419 /*!
AnnaBridge 171:3a7713b1edbc 5420 * @addtogroup ENET_Register_Masks ENET Register Masks
AnnaBridge 171:3a7713b1edbc 5421 * @{
AnnaBridge 171:3a7713b1edbc 5422 */
AnnaBridge 171:3a7713b1edbc 5423
AnnaBridge 171:3a7713b1edbc 5424 /*! @name EIR - Interrupt Event Register */
AnnaBridge 171:3a7713b1edbc 5425 #define ENET_EIR_TS_TIMER_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 5426 #define ENET_EIR_TS_TIMER_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 5427 #define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
AnnaBridge 171:3a7713b1edbc 5428 #define ENET_EIR_TS_AVAIL_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 5429 #define ENET_EIR_TS_AVAIL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5430 #define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
AnnaBridge 171:3a7713b1edbc 5431 #define ENET_EIR_WAKEUP_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 5432 #define ENET_EIR_WAKEUP_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 5433 #define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
AnnaBridge 171:3a7713b1edbc 5434 #define ENET_EIR_PLR_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 5435 #define ENET_EIR_PLR_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 5436 #define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
AnnaBridge 171:3a7713b1edbc 5437 #define ENET_EIR_UN_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 5438 #define ENET_EIR_UN_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 5439 #define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
AnnaBridge 171:3a7713b1edbc 5440 #define ENET_EIR_RL_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 5441 #define ENET_EIR_RL_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 5442 #define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
AnnaBridge 171:3a7713b1edbc 5443 #define ENET_EIR_LC_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 5444 #define ENET_EIR_LC_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 5445 #define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
AnnaBridge 171:3a7713b1edbc 5446 #define ENET_EIR_EBERR_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 5447 #define ENET_EIR_EBERR_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 5448 #define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
AnnaBridge 171:3a7713b1edbc 5449 #define ENET_EIR_MII_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 5450 #define ENET_EIR_MII_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 5451 #define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
AnnaBridge 171:3a7713b1edbc 5452 #define ENET_EIR_RXB_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 5453 #define ENET_EIR_RXB_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 5454 #define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
AnnaBridge 171:3a7713b1edbc 5455 #define ENET_EIR_RXF_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 5456 #define ENET_EIR_RXF_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 5457 #define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
AnnaBridge 171:3a7713b1edbc 5458 #define ENET_EIR_TXB_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 5459 #define ENET_EIR_TXB_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 5460 #define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
AnnaBridge 171:3a7713b1edbc 5461 #define ENET_EIR_TXF_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 5462 #define ENET_EIR_TXF_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 5463 #define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
AnnaBridge 171:3a7713b1edbc 5464 #define ENET_EIR_GRA_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 5465 #define ENET_EIR_GRA_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 5466 #define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
AnnaBridge 171:3a7713b1edbc 5467 #define ENET_EIR_BABT_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 5468 #define ENET_EIR_BABT_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 5469 #define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
AnnaBridge 171:3a7713b1edbc 5470 #define ENET_EIR_BABR_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 5471 #define ENET_EIR_BABR_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 5472 #define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
AnnaBridge 171:3a7713b1edbc 5473
AnnaBridge 171:3a7713b1edbc 5474 /*! @name EIMR - Interrupt Mask Register */
AnnaBridge 171:3a7713b1edbc 5475 #define ENET_EIMR_TS_TIMER_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 5476 #define ENET_EIMR_TS_TIMER_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 5477 #define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
AnnaBridge 171:3a7713b1edbc 5478 #define ENET_EIMR_TS_AVAIL_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 5479 #define ENET_EIMR_TS_AVAIL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5480 #define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
AnnaBridge 171:3a7713b1edbc 5481 #define ENET_EIMR_WAKEUP_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 5482 #define ENET_EIMR_WAKEUP_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 5483 #define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
AnnaBridge 171:3a7713b1edbc 5484 #define ENET_EIMR_PLR_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 5485 #define ENET_EIMR_PLR_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 5486 #define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
AnnaBridge 171:3a7713b1edbc 5487 #define ENET_EIMR_UN_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 5488 #define ENET_EIMR_UN_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 5489 #define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
AnnaBridge 171:3a7713b1edbc 5490 #define ENET_EIMR_RL_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 5491 #define ENET_EIMR_RL_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 5492 #define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
AnnaBridge 171:3a7713b1edbc 5493 #define ENET_EIMR_LC_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 5494 #define ENET_EIMR_LC_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 5495 #define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
AnnaBridge 171:3a7713b1edbc 5496 #define ENET_EIMR_EBERR_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 5497 #define ENET_EIMR_EBERR_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 5498 #define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
AnnaBridge 171:3a7713b1edbc 5499 #define ENET_EIMR_MII_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 5500 #define ENET_EIMR_MII_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 5501 #define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
AnnaBridge 171:3a7713b1edbc 5502 #define ENET_EIMR_RXB_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 5503 #define ENET_EIMR_RXB_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 5504 #define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
AnnaBridge 171:3a7713b1edbc 5505 #define ENET_EIMR_RXF_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 5506 #define ENET_EIMR_RXF_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 5507 #define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
AnnaBridge 171:3a7713b1edbc 5508 #define ENET_EIMR_TXB_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 5509 #define ENET_EIMR_TXB_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 5510 #define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
AnnaBridge 171:3a7713b1edbc 5511 #define ENET_EIMR_TXF_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 5512 #define ENET_EIMR_TXF_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 5513 #define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
AnnaBridge 171:3a7713b1edbc 5514 #define ENET_EIMR_GRA_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 5515 #define ENET_EIMR_GRA_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 5516 #define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
AnnaBridge 171:3a7713b1edbc 5517 #define ENET_EIMR_BABT_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 5518 #define ENET_EIMR_BABT_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 5519 #define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
AnnaBridge 171:3a7713b1edbc 5520 #define ENET_EIMR_BABR_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 5521 #define ENET_EIMR_BABR_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 5522 #define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
AnnaBridge 171:3a7713b1edbc 5523
AnnaBridge 171:3a7713b1edbc 5524 /*! @name RDAR - Receive Descriptor Active Register */
AnnaBridge 171:3a7713b1edbc 5525 #define ENET_RDAR_RDAR_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 5526 #define ENET_RDAR_RDAR_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 5527 #define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
AnnaBridge 171:3a7713b1edbc 5528
AnnaBridge 171:3a7713b1edbc 5529 /*! @name TDAR - Transmit Descriptor Active Register */
AnnaBridge 171:3a7713b1edbc 5530 #define ENET_TDAR_TDAR_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 5531 #define ENET_TDAR_TDAR_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 5532 #define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
AnnaBridge 171:3a7713b1edbc 5533
AnnaBridge 171:3a7713b1edbc 5534 /*! @name ECR - Ethernet Control Register */
AnnaBridge 171:3a7713b1edbc 5535 #define ENET_ECR_RESET_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5536 #define ENET_ECR_RESET_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5537 #define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
AnnaBridge 171:3a7713b1edbc 5538 #define ENET_ECR_ETHEREN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5539 #define ENET_ECR_ETHEREN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5540 #define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
AnnaBridge 171:3a7713b1edbc 5541 #define ENET_ECR_MAGICEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5542 #define ENET_ECR_MAGICEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5543 #define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
AnnaBridge 171:3a7713b1edbc 5544 #define ENET_ECR_SLEEP_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5545 #define ENET_ECR_SLEEP_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5546 #define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
AnnaBridge 171:3a7713b1edbc 5547 #define ENET_ECR_EN1588_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5548 #define ENET_ECR_EN1588_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5549 #define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
AnnaBridge 171:3a7713b1edbc 5550 #define ENET_ECR_DBGEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5551 #define ENET_ECR_DBGEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5552 #define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
AnnaBridge 171:3a7713b1edbc 5553 #define ENET_ECR_STOPEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5554 #define ENET_ECR_STOPEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5555 #define ENET_ECR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK)
AnnaBridge 171:3a7713b1edbc 5556 #define ENET_ECR_DBSWP_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 5557 #define ENET_ECR_DBSWP_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 5558 #define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
AnnaBridge 171:3a7713b1edbc 5559
AnnaBridge 171:3a7713b1edbc 5560 /*! @name MMFR - MII Management Frame Register */
AnnaBridge 171:3a7713b1edbc 5561 #define ENET_MMFR_DATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5562 #define ENET_MMFR_DATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5563 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
AnnaBridge 171:3a7713b1edbc 5564 #define ENET_MMFR_TA_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 5565 #define ENET_MMFR_TA_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5566 #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
AnnaBridge 171:3a7713b1edbc 5567 #define ENET_MMFR_RA_MASK (0x7C0000U)
AnnaBridge 171:3a7713b1edbc 5568 #define ENET_MMFR_RA_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 5569 #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
AnnaBridge 171:3a7713b1edbc 5570 #define ENET_MMFR_PA_MASK (0xF800000U)
AnnaBridge 171:3a7713b1edbc 5571 #define ENET_MMFR_PA_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 5572 #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
AnnaBridge 171:3a7713b1edbc 5573 #define ENET_MMFR_OP_MASK (0x30000000U)
AnnaBridge 171:3a7713b1edbc 5574 #define ENET_MMFR_OP_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 5575 #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
AnnaBridge 171:3a7713b1edbc 5576 #define ENET_MMFR_ST_MASK (0xC0000000U)
AnnaBridge 171:3a7713b1edbc 5577 #define ENET_MMFR_ST_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 5578 #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
AnnaBridge 171:3a7713b1edbc 5579
AnnaBridge 171:3a7713b1edbc 5580 /*! @name MSCR - MII Speed Control Register */
AnnaBridge 171:3a7713b1edbc 5581 #define ENET_MSCR_MII_SPEED_MASK (0x7EU)
AnnaBridge 171:3a7713b1edbc 5582 #define ENET_MSCR_MII_SPEED_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5583 #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
AnnaBridge 171:3a7713b1edbc 5584 #define ENET_MSCR_DIS_PRE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5585 #define ENET_MSCR_DIS_PRE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5586 #define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
AnnaBridge 171:3a7713b1edbc 5587 #define ENET_MSCR_HOLDTIME_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 5588 #define ENET_MSCR_HOLDTIME_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 5589 #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
AnnaBridge 171:3a7713b1edbc 5590
AnnaBridge 171:3a7713b1edbc 5591 /*! @name MIBC - MIB Control Register */
AnnaBridge 171:3a7713b1edbc 5592 #define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 5593 #define ENET_MIBC_MIB_CLEAR_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 5594 #define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
AnnaBridge 171:3a7713b1edbc 5595 #define ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 5596 #define ENET_MIBC_MIB_IDLE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 5597 #define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
AnnaBridge 171:3a7713b1edbc 5598 #define ENET_MIBC_MIB_DIS_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 5599 #define ENET_MIBC_MIB_DIS_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 5600 #define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 5601
AnnaBridge 171:3a7713b1edbc 5602 /*! @name RCR - Receive Control Register */
AnnaBridge 171:3a7713b1edbc 5603 #define ENET_RCR_LOOP_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5604 #define ENET_RCR_LOOP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5605 #define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
AnnaBridge 171:3a7713b1edbc 5606 #define ENET_RCR_DRT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5607 #define ENET_RCR_DRT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5608 #define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
AnnaBridge 171:3a7713b1edbc 5609 #define ENET_RCR_MII_MODE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5610 #define ENET_RCR_MII_MODE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5611 #define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 5612 #define ENET_RCR_PROM_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5613 #define ENET_RCR_PROM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5614 #define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
AnnaBridge 171:3a7713b1edbc 5615 #define ENET_RCR_BC_REJ_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5616 #define ENET_RCR_BC_REJ_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5617 #define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
AnnaBridge 171:3a7713b1edbc 5618 #define ENET_RCR_FCE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5619 #define ENET_RCR_FCE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5620 #define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
AnnaBridge 171:3a7713b1edbc 5621 #define ENET_RCR_RMII_MODE_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 5622 #define ENET_RCR_RMII_MODE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 5623 #define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 5624 #define ENET_RCR_RMII_10T_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 5625 #define ENET_RCR_RMII_10T_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 5626 #define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
AnnaBridge 171:3a7713b1edbc 5627 #define ENET_RCR_PADEN_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 5628 #define ENET_RCR_PADEN_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 5629 #define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
AnnaBridge 171:3a7713b1edbc 5630 #define ENET_RCR_PAUFWD_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 5631 #define ENET_RCR_PAUFWD_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 5632 #define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
AnnaBridge 171:3a7713b1edbc 5633 #define ENET_RCR_CRCFWD_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 5634 #define ENET_RCR_CRCFWD_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 5635 #define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
AnnaBridge 171:3a7713b1edbc 5636 #define ENET_RCR_CFEN_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 5637 #define ENET_RCR_CFEN_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 5638 #define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
AnnaBridge 171:3a7713b1edbc 5639 #define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
AnnaBridge 171:3a7713b1edbc 5640 #define ENET_RCR_MAX_FL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5641 #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
AnnaBridge 171:3a7713b1edbc 5642 #define ENET_RCR_NLC_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 5643 #define ENET_RCR_NLC_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 5644 #define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
AnnaBridge 171:3a7713b1edbc 5645 #define ENET_RCR_GRS_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 5646 #define ENET_RCR_GRS_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 5647 #define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
AnnaBridge 171:3a7713b1edbc 5648
AnnaBridge 171:3a7713b1edbc 5649 /*! @name TCR - Transmit Control Register */
AnnaBridge 171:3a7713b1edbc 5650 #define ENET_TCR_GTS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5651 #define ENET_TCR_GTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5652 #define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
AnnaBridge 171:3a7713b1edbc 5653 #define ENET_TCR_FDEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5654 #define ENET_TCR_FDEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5655 #define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
AnnaBridge 171:3a7713b1edbc 5656 #define ENET_TCR_TFC_PAUSE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5657 #define ENET_TCR_TFC_PAUSE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5658 #define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
AnnaBridge 171:3a7713b1edbc 5659 #define ENET_TCR_RFC_PAUSE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5660 #define ENET_TCR_RFC_PAUSE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5661 #define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
AnnaBridge 171:3a7713b1edbc 5662 #define ENET_TCR_ADDSEL_MASK (0xE0U)
AnnaBridge 171:3a7713b1edbc 5663 #define ENET_TCR_ADDSEL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5664 #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
AnnaBridge 171:3a7713b1edbc 5665 #define ENET_TCR_ADDINS_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 5666 #define ENET_TCR_ADDINS_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 5667 #define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
AnnaBridge 171:3a7713b1edbc 5668 #define ENET_TCR_CRCFWD_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 5669 #define ENET_TCR_CRCFWD_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 5670 #define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
AnnaBridge 171:3a7713b1edbc 5671
AnnaBridge 171:3a7713b1edbc 5672 /*! @name PALR - Physical Address Lower Register */
AnnaBridge 171:3a7713b1edbc 5673 #define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5674 #define ENET_PALR_PADDR1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5675 #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
AnnaBridge 171:3a7713b1edbc 5676
AnnaBridge 171:3a7713b1edbc 5677 /*! @name PAUR - Physical Address Upper Register */
AnnaBridge 171:3a7713b1edbc 5678 #define ENET_PAUR_TYPE_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5679 #define ENET_PAUR_TYPE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5680 #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
AnnaBridge 171:3a7713b1edbc 5681 #define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 5682 #define ENET_PAUR_PADDR2_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5683 #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
AnnaBridge 171:3a7713b1edbc 5684
AnnaBridge 171:3a7713b1edbc 5685 /*! @name OPD - Opcode/Pause Duration Register */
AnnaBridge 171:3a7713b1edbc 5686 #define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5687 #define ENET_OPD_PAUSE_DUR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5688 #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
AnnaBridge 171:3a7713b1edbc 5689 #define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 5690 #define ENET_OPD_OPCODE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5691 #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
AnnaBridge 171:3a7713b1edbc 5692
AnnaBridge 171:3a7713b1edbc 5693 /*! @name IAUR - Descriptor Individual Upper Address Register */
AnnaBridge 171:3a7713b1edbc 5694 #define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5695 #define ENET_IAUR_IADDR1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5696 #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
AnnaBridge 171:3a7713b1edbc 5697
AnnaBridge 171:3a7713b1edbc 5698 /*! @name IALR - Descriptor Individual Lower Address Register */
AnnaBridge 171:3a7713b1edbc 5699 #define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5700 #define ENET_IALR_IADDR2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5701 #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
AnnaBridge 171:3a7713b1edbc 5702
AnnaBridge 171:3a7713b1edbc 5703 /*! @name GAUR - Descriptor Group Upper Address Register */
AnnaBridge 171:3a7713b1edbc 5704 #define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5705 #define ENET_GAUR_GADDR1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5706 #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
AnnaBridge 171:3a7713b1edbc 5707
AnnaBridge 171:3a7713b1edbc 5708 /*! @name GALR - Descriptor Group Lower Address Register */
AnnaBridge 171:3a7713b1edbc 5709 #define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5710 #define ENET_GALR_GADDR2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5711 #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
AnnaBridge 171:3a7713b1edbc 5712
AnnaBridge 171:3a7713b1edbc 5713 /*! @name TFWR - Transmit FIFO Watermark Register */
AnnaBridge 171:3a7713b1edbc 5714 #define ENET_TFWR_TFWR_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 5715 #define ENET_TFWR_TFWR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5716 #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
AnnaBridge 171:3a7713b1edbc 5717 #define ENET_TFWR_STRFWD_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 5718 #define ENET_TFWR_STRFWD_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 5719 #define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
AnnaBridge 171:3a7713b1edbc 5720
AnnaBridge 171:3a7713b1edbc 5721 /*! @name RDSR - Receive Descriptor Ring Start Register */
AnnaBridge 171:3a7713b1edbc 5722 #define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
AnnaBridge 171:3a7713b1edbc 5723 #define ENET_RDSR_R_DES_START_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5724 #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
AnnaBridge 171:3a7713b1edbc 5725
AnnaBridge 171:3a7713b1edbc 5726 /*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */
AnnaBridge 171:3a7713b1edbc 5727 #define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
AnnaBridge 171:3a7713b1edbc 5728 #define ENET_TDSR_X_DES_START_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5729 #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
AnnaBridge 171:3a7713b1edbc 5730
AnnaBridge 171:3a7713b1edbc 5731 /*! @name MRBR - Maximum Receive Buffer Size Register */
AnnaBridge 171:3a7713b1edbc 5732 #define ENET_MRBR_R_BUF_SIZE_MASK (0x7F0U)
AnnaBridge 171:3a7713b1edbc 5733 #define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5734 #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
AnnaBridge 171:3a7713b1edbc 5735
AnnaBridge 171:3a7713b1edbc 5736 /*! @name RSFL - Receive FIFO Section Full Threshold */
AnnaBridge 171:3a7713b1edbc 5737 #define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5738 #define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5739 #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
AnnaBridge 171:3a7713b1edbc 5740
AnnaBridge 171:3a7713b1edbc 5741 /*! @name RSEM - Receive FIFO Section Empty Threshold */
AnnaBridge 171:3a7713b1edbc 5742 #define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5743 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5744 #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
AnnaBridge 171:3a7713b1edbc 5745 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
AnnaBridge 171:3a7713b1edbc 5746 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5747 #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
AnnaBridge 171:3a7713b1edbc 5748
AnnaBridge 171:3a7713b1edbc 5749 /*! @name RAEM - Receive FIFO Almost Empty Threshold */
AnnaBridge 171:3a7713b1edbc 5750 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5751 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5752 #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
AnnaBridge 171:3a7713b1edbc 5753
AnnaBridge 171:3a7713b1edbc 5754 /*! @name RAFL - Receive FIFO Almost Full Threshold */
AnnaBridge 171:3a7713b1edbc 5755 #define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5756 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5757 #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
AnnaBridge 171:3a7713b1edbc 5758
AnnaBridge 171:3a7713b1edbc 5759 /*! @name TSEM - Transmit FIFO Section Empty Threshold */
AnnaBridge 171:3a7713b1edbc 5760 #define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5761 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5762 #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
AnnaBridge 171:3a7713b1edbc 5763
AnnaBridge 171:3a7713b1edbc 5764 /*! @name TAEM - Transmit FIFO Almost Empty Threshold */
AnnaBridge 171:3a7713b1edbc 5765 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5766 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5767 #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
AnnaBridge 171:3a7713b1edbc 5768
AnnaBridge 171:3a7713b1edbc 5769 /*! @name TAFL - Transmit FIFO Almost Full Threshold */
AnnaBridge 171:3a7713b1edbc 5770 #define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5771 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5772 #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
AnnaBridge 171:3a7713b1edbc 5773
AnnaBridge 171:3a7713b1edbc 5774 /*! @name TIPG - Transmit Inter-Packet Gap */
AnnaBridge 171:3a7713b1edbc 5775 #define ENET_TIPG_IPG_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 5776 #define ENET_TIPG_IPG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5777 #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
AnnaBridge 171:3a7713b1edbc 5778
AnnaBridge 171:3a7713b1edbc 5779 /*! @name FTRL - Frame Truncation Length */
AnnaBridge 171:3a7713b1edbc 5780 #define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
AnnaBridge 171:3a7713b1edbc 5781 #define ENET_FTRL_TRUNC_FL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5782 #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
AnnaBridge 171:3a7713b1edbc 5783
AnnaBridge 171:3a7713b1edbc 5784 /*! @name TACC - Transmit Accelerator Function Configuration */
AnnaBridge 171:3a7713b1edbc 5785 #define ENET_TACC_SHIFT16_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5786 #define ENET_TACC_SHIFT16_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5787 #define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
AnnaBridge 171:3a7713b1edbc 5788 #define ENET_TACC_IPCHK_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5789 #define ENET_TACC_IPCHK_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5790 #define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
AnnaBridge 171:3a7713b1edbc 5791 #define ENET_TACC_PROCHK_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5792 #define ENET_TACC_PROCHK_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5793 #define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
AnnaBridge 171:3a7713b1edbc 5794
AnnaBridge 171:3a7713b1edbc 5795 /*! @name RACC - Receive Accelerator Function Configuration */
AnnaBridge 171:3a7713b1edbc 5796 #define ENET_RACC_PADREM_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5797 #define ENET_RACC_PADREM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5798 #define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
AnnaBridge 171:3a7713b1edbc 5799 #define ENET_RACC_IPDIS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5800 #define ENET_RACC_IPDIS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5801 #define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
AnnaBridge 171:3a7713b1edbc 5802 #define ENET_RACC_PRODIS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5803 #define ENET_RACC_PRODIS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5804 #define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
AnnaBridge 171:3a7713b1edbc 5805 #define ENET_RACC_LINEDIS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5806 #define ENET_RACC_LINEDIS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5807 #define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
AnnaBridge 171:3a7713b1edbc 5808 #define ENET_RACC_SHIFT16_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5809 #define ENET_RACC_SHIFT16_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5810 #define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
AnnaBridge 171:3a7713b1edbc 5811
AnnaBridge 171:3a7713b1edbc 5812 /*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
AnnaBridge 171:3a7713b1edbc 5813 #define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5814 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5815 #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5816
AnnaBridge 171:3a7713b1edbc 5817 /*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5818 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5819 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5820 #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5821
AnnaBridge 171:3a7713b1edbc 5822 /*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5823 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5824 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5825 #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5826
AnnaBridge 171:3a7713b1edbc 5827 /*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
AnnaBridge 171:3a7713b1edbc 5828 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5829 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5830 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5831
AnnaBridge 171:3a7713b1edbc 5832 /*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
AnnaBridge 171:3a7713b1edbc 5833 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5834 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5835 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5836
AnnaBridge 171:3a7713b1edbc 5837 /*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
AnnaBridge 171:3a7713b1edbc 5838 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5839 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5840 #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5841
AnnaBridge 171:3a7713b1edbc 5842 /*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
AnnaBridge 171:3a7713b1edbc 5843 #define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5844 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5845 #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5846
AnnaBridge 171:3a7713b1edbc 5847 /*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
AnnaBridge 171:3a7713b1edbc 5848 #define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5849 #define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5850 #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5851
AnnaBridge 171:3a7713b1edbc 5852 /*! @name RMON_T_COL - Tx Collision Count Statistic Register */
AnnaBridge 171:3a7713b1edbc 5853 #define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5854 #define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5855 #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5856
AnnaBridge 171:3a7713b1edbc 5857 /*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5858 #define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5859 #define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5860 #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5861
AnnaBridge 171:3a7713b1edbc 5862 /*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5863 #define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5864 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5865 #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5866
AnnaBridge 171:3a7713b1edbc 5867 /*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5868 #define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5869 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5870 #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5871
AnnaBridge 171:3a7713b1edbc 5872 /*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5873 #define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5874 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5875 #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5876
AnnaBridge 171:3a7713b1edbc 5877 /*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5878 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5879 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5880 #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5881
AnnaBridge 171:3a7713b1edbc 5882 /*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5883 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5884 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5885 #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5886
AnnaBridge 171:3a7713b1edbc 5887 /*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
AnnaBridge 171:3a7713b1edbc 5888 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5889 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5890 #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5891
AnnaBridge 171:3a7713b1edbc 5892 /*! @name RMON_T_OCTETS - Tx Octets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5893 #define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5894 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5895 #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
AnnaBridge 171:3a7713b1edbc 5896
AnnaBridge 171:3a7713b1edbc 5897 /*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
AnnaBridge 171:3a7713b1edbc 5898 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5899 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5900 #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5901
AnnaBridge 171:3a7713b1edbc 5902 /*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
AnnaBridge 171:3a7713b1edbc 5903 #define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5904 #define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5905 #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5906
AnnaBridge 171:3a7713b1edbc 5907 /*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
AnnaBridge 171:3a7713b1edbc 5908 #define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5909 #define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5910 #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5911
AnnaBridge 171:3a7713b1edbc 5912 /*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
AnnaBridge 171:3a7713b1edbc 5913 #define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5914 #define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5915 #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5916
AnnaBridge 171:3a7713b1edbc 5917 /*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
AnnaBridge 171:3a7713b1edbc 5918 #define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5919 #define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5920 #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5921
AnnaBridge 171:3a7713b1edbc 5922 /*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
AnnaBridge 171:3a7713b1edbc 5923 #define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5924 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5925 #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5926
AnnaBridge 171:3a7713b1edbc 5927 /*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
AnnaBridge 171:3a7713b1edbc 5928 #define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5929 #define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5930 #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5931
AnnaBridge 171:3a7713b1edbc 5932 /*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
AnnaBridge 171:3a7713b1edbc 5933 #define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5934 #define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5935 #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5936
AnnaBridge 171:3a7713b1edbc 5937 /*! @name IEEE_T_SQE - */
AnnaBridge 171:3a7713b1edbc 5938 #define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5939 #define ENET_IEEE_T_SQE_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5940 #define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5941
AnnaBridge 171:3a7713b1edbc 5942 /*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
AnnaBridge 171:3a7713b1edbc 5943 #define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5944 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5945 #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5946
AnnaBridge 171:3a7713b1edbc 5947 /*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
AnnaBridge 171:3a7713b1edbc 5948 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5949 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5950 #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5951
AnnaBridge 171:3a7713b1edbc 5952 /*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
AnnaBridge 171:3a7713b1edbc 5953 #define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5954 #define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5955 #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5956
AnnaBridge 171:3a7713b1edbc 5957 /*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5958 #define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5959 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5960 #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5961
AnnaBridge 171:3a7713b1edbc 5962 /*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5963 #define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5964 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5965 #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5966
AnnaBridge 171:3a7713b1edbc 5967 /*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
AnnaBridge 171:3a7713b1edbc 5968 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5969 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5970 #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5971
AnnaBridge 171:3a7713b1edbc 5972 /*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
AnnaBridge 171:3a7713b1edbc 5973 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5974 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5975 #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5976
AnnaBridge 171:3a7713b1edbc 5977 /*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
AnnaBridge 171:3a7713b1edbc 5978 #define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5979 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5980 #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5981
AnnaBridge 171:3a7713b1edbc 5982 /*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
AnnaBridge 171:3a7713b1edbc 5983 #define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5984 #define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5985 #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5986
AnnaBridge 171:3a7713b1edbc 5987 /*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
AnnaBridge 171:3a7713b1edbc 5988 #define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5989 #define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5990 #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5991
AnnaBridge 171:3a7713b1edbc 5992 /*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5993 #define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5994 #define ENET_RMON_R_P64_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5995 #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5996
AnnaBridge 171:3a7713b1edbc 5997 /*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5998 #define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5999 #define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6000 #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 6001
AnnaBridge 171:3a7713b1edbc 6002 /*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 6003 #define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6004 #define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6005 #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 6006
AnnaBridge 171:3a7713b1edbc 6007 /*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 6008 #define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6009 #define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6010 #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 6011
AnnaBridge 171:3a7713b1edbc 6012 /*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 6013 #define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6014 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6015 #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 6016
AnnaBridge 171:3a7713b1edbc 6017 /*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 6018 #define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6019 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6020 #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 6021
AnnaBridge 171:3a7713b1edbc 6022 /*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
AnnaBridge 171:3a7713b1edbc 6023 #define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6024 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6025 #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 6026
AnnaBridge 171:3a7713b1edbc 6027 /*! @name RMON_R_OCTETS - Rx Octets Statistic Register */
AnnaBridge 171:3a7713b1edbc 6028 #define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6029 #define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6030 #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 6031
AnnaBridge 171:3a7713b1edbc 6032 /*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
AnnaBridge 171:3a7713b1edbc 6033 #define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6034 #define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6035 #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 6036
AnnaBridge 171:3a7713b1edbc 6037 /*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
AnnaBridge 171:3a7713b1edbc 6038 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6039 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6040 #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 6041
AnnaBridge 171:3a7713b1edbc 6042 /*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
AnnaBridge 171:3a7713b1edbc 6043 #define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6044 #define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6045 #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 6046
AnnaBridge 171:3a7713b1edbc 6047 /*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
AnnaBridge 171:3a7713b1edbc 6048 #define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6049 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6050 #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 6051
AnnaBridge 171:3a7713b1edbc 6052 /*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
AnnaBridge 171:3a7713b1edbc 6053 #define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6054 #define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6055 #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 6056
AnnaBridge 171:3a7713b1edbc 6057 /*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
AnnaBridge 171:3a7713b1edbc 6058 #define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6059 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6060 #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 6061
AnnaBridge 171:3a7713b1edbc 6062 /*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
AnnaBridge 171:3a7713b1edbc 6063 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6064 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6065 #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 6066
AnnaBridge 171:3a7713b1edbc 6067 /*! @name ATCR - Adjustable Timer Control Register */
AnnaBridge 171:3a7713b1edbc 6068 #define ENET_ATCR_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6069 #define ENET_ATCR_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6070 #define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
AnnaBridge 171:3a7713b1edbc 6071 #define ENET_ATCR_OFFEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6072 #define ENET_ATCR_OFFEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6073 #define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
AnnaBridge 171:3a7713b1edbc 6074 #define ENET_ATCR_OFFRST_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6075 #define ENET_ATCR_OFFRST_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6076 #define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
AnnaBridge 171:3a7713b1edbc 6077 #define ENET_ATCR_PEREN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6078 #define ENET_ATCR_PEREN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6079 #define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
AnnaBridge 171:3a7713b1edbc 6080 #define ENET_ATCR_PINPER_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6081 #define ENET_ATCR_PINPER_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6082 #define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
AnnaBridge 171:3a7713b1edbc 6083 #define ENET_ATCR_RESTART_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 6084 #define ENET_ATCR_RESTART_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 6085 #define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
AnnaBridge 171:3a7713b1edbc 6086 #define ENET_ATCR_CAPTURE_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 6087 #define ENET_ATCR_CAPTURE_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 6088 #define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
AnnaBridge 171:3a7713b1edbc 6089 #define ENET_ATCR_SLAVE_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 6090 #define ENET_ATCR_SLAVE_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 6091 #define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
AnnaBridge 171:3a7713b1edbc 6092
AnnaBridge 171:3a7713b1edbc 6093 /*! @name ATVR - Timer Value Register */
AnnaBridge 171:3a7713b1edbc 6094 #define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6095 #define ENET_ATVR_ATIME_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6096 #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
AnnaBridge 171:3a7713b1edbc 6097
AnnaBridge 171:3a7713b1edbc 6098 /*! @name ATOFF - Timer Offset Register */
AnnaBridge 171:3a7713b1edbc 6099 #define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6100 #define ENET_ATOFF_OFFSET_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6101 #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
AnnaBridge 171:3a7713b1edbc 6102
AnnaBridge 171:3a7713b1edbc 6103 /*! @name ATPER - Timer Period Register */
AnnaBridge 171:3a7713b1edbc 6104 #define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6105 #define ENET_ATPER_PERIOD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6106 #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
AnnaBridge 171:3a7713b1edbc 6107
AnnaBridge 171:3a7713b1edbc 6108 /*! @name ATCOR - Timer Correction Register */
AnnaBridge 171:3a7713b1edbc 6109 #define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6110 #define ENET_ATCOR_COR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6111 #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
AnnaBridge 171:3a7713b1edbc 6112
AnnaBridge 171:3a7713b1edbc 6113 /*! @name ATINC - Time-Stamping Clock Period Register */
AnnaBridge 171:3a7713b1edbc 6114 #define ENET_ATINC_INC_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 6115 #define ENET_ATINC_INC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6116 #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
AnnaBridge 171:3a7713b1edbc 6117 #define ENET_ATINC_INC_CORR_MASK (0x7F00U)
AnnaBridge 171:3a7713b1edbc 6118 #define ENET_ATINC_INC_CORR_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6119 #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
AnnaBridge 171:3a7713b1edbc 6120
AnnaBridge 171:3a7713b1edbc 6121 /*! @name ATSTMP - Timestamp of Last Transmitted Frame */
AnnaBridge 171:3a7713b1edbc 6122 #define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6123 #define ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6124 #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
AnnaBridge 171:3a7713b1edbc 6125
AnnaBridge 171:3a7713b1edbc 6126 /*! @name TGSR - Timer Global Status Register */
AnnaBridge 171:3a7713b1edbc 6127 #define ENET_TGSR_TF0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6128 #define ENET_TGSR_TF0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6129 #define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
AnnaBridge 171:3a7713b1edbc 6130 #define ENET_TGSR_TF1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6131 #define ENET_TGSR_TF1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6132 #define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
AnnaBridge 171:3a7713b1edbc 6133 #define ENET_TGSR_TF2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6134 #define ENET_TGSR_TF2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6135 #define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
AnnaBridge 171:3a7713b1edbc 6136 #define ENET_TGSR_TF3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6137 #define ENET_TGSR_TF3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6138 #define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
AnnaBridge 171:3a7713b1edbc 6139
AnnaBridge 171:3a7713b1edbc 6140 /*! @name TCSR - Timer Control Status Register */
AnnaBridge 171:3a7713b1edbc 6141 #define ENET_TCSR_TDRE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6142 #define ENET_TCSR_TDRE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6143 #define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
AnnaBridge 171:3a7713b1edbc 6144 #define ENET_TCSR_TMODE_MASK (0x3CU)
AnnaBridge 171:3a7713b1edbc 6145 #define ENET_TCSR_TMODE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6146 #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
AnnaBridge 171:3a7713b1edbc 6147 #define ENET_TCSR_TIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6148 #define ENET_TCSR_TIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6149 #define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
AnnaBridge 171:3a7713b1edbc 6150 #define ENET_TCSR_TF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6151 #define ENET_TCSR_TF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6152 #define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
AnnaBridge 171:3a7713b1edbc 6153
AnnaBridge 171:3a7713b1edbc 6154 /* The count of ENET_TCSR */
AnnaBridge 171:3a7713b1edbc 6155 #define ENET_TCSR_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 6156
AnnaBridge 171:3a7713b1edbc 6157 /*! @name TCCR - Timer Compare Capture Register */
AnnaBridge 171:3a7713b1edbc 6158 #define ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6159 #define ENET_TCCR_TCC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6160 #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
AnnaBridge 171:3a7713b1edbc 6161
AnnaBridge 171:3a7713b1edbc 6162 /* The count of ENET_TCCR */
AnnaBridge 171:3a7713b1edbc 6163 #define ENET_TCCR_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 6164
AnnaBridge 171:3a7713b1edbc 6165
AnnaBridge 171:3a7713b1edbc 6166 /*!
AnnaBridge 171:3a7713b1edbc 6167 * @}
AnnaBridge 171:3a7713b1edbc 6168 */ /* end of group ENET_Register_Masks */
AnnaBridge 171:3a7713b1edbc 6169
AnnaBridge 171:3a7713b1edbc 6170
AnnaBridge 171:3a7713b1edbc 6171 /* ENET - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 6172 /** Peripheral ENET base address */
AnnaBridge 171:3a7713b1edbc 6173 #define ENET_BASE (0x400C0000u)
AnnaBridge 171:3a7713b1edbc 6174 /** Peripheral ENET base pointer */
AnnaBridge 171:3a7713b1edbc 6175 #define ENET ((ENET_Type *)ENET_BASE)
AnnaBridge 171:3a7713b1edbc 6176 /** Array initializer of ENET peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 6177 #define ENET_BASE_ADDRS { ENET_BASE }
AnnaBridge 171:3a7713b1edbc 6178 /** Array initializer of ENET peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 6179 #define ENET_BASE_PTRS { ENET }
AnnaBridge 171:3a7713b1edbc 6180 /** Interrupt vectors for the ENET peripheral type */
AnnaBridge 171:3a7713b1edbc 6181 #define ENET_Transmit_IRQS { ENET_Transmit_IRQn }
AnnaBridge 171:3a7713b1edbc 6182 #define ENET_Receive_IRQS { ENET_Receive_IRQn }
AnnaBridge 171:3a7713b1edbc 6183 #define ENET_Error_IRQS { ENET_Error_IRQn }
AnnaBridge 171:3a7713b1edbc 6184 #define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }
AnnaBridge 171:3a7713b1edbc 6185 /* ENET Buffer Descriptor and Buffer Address Alignment. */
AnnaBridge 171:3a7713b1edbc 6186 #define ENET_BUFF_ALIGNMENT (16U)
AnnaBridge 171:3a7713b1edbc 6187
AnnaBridge 171:3a7713b1edbc 6188
AnnaBridge 171:3a7713b1edbc 6189 /*!
AnnaBridge 171:3a7713b1edbc 6190 * @}
AnnaBridge 171:3a7713b1edbc 6191 */ /* end of group ENET_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 6192
AnnaBridge 171:3a7713b1edbc 6193
AnnaBridge 171:3a7713b1edbc 6194 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6195 -- EWM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6196 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6197
AnnaBridge 171:3a7713b1edbc 6198 /*!
AnnaBridge 171:3a7713b1edbc 6199 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6200 * @{
AnnaBridge 171:3a7713b1edbc 6201 */
AnnaBridge 171:3a7713b1edbc 6202
AnnaBridge 171:3a7713b1edbc 6203 /** EWM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 6204 typedef struct {
AnnaBridge 171:3a7713b1edbc 6205 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 6206 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 6207 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 6208 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 6209 } EWM_Type;
AnnaBridge 171:3a7713b1edbc 6210
AnnaBridge 171:3a7713b1edbc 6211 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6212 -- EWM Register Masks
AnnaBridge 171:3a7713b1edbc 6213 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6214
AnnaBridge 171:3a7713b1edbc 6215 /*!
AnnaBridge 171:3a7713b1edbc 6216 * @addtogroup EWM_Register_Masks EWM Register Masks
AnnaBridge 171:3a7713b1edbc 6217 * @{
AnnaBridge 171:3a7713b1edbc 6218 */
AnnaBridge 171:3a7713b1edbc 6219
AnnaBridge 171:3a7713b1edbc 6220 /*! @name CTRL - Control Register */
AnnaBridge 171:3a7713b1edbc 6221 #define EWM_CTRL_EWMEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6222 #define EWM_CTRL_EWMEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6223 #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
AnnaBridge 171:3a7713b1edbc 6224 #define EWM_CTRL_ASSIN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6225 #define EWM_CTRL_ASSIN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6226 #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
AnnaBridge 171:3a7713b1edbc 6227 #define EWM_CTRL_INEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6228 #define EWM_CTRL_INEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6229 #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
AnnaBridge 171:3a7713b1edbc 6230 #define EWM_CTRL_INTEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6231 #define EWM_CTRL_INTEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6232 #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
AnnaBridge 171:3a7713b1edbc 6233
AnnaBridge 171:3a7713b1edbc 6234 /*! @name SERV - Service Register */
AnnaBridge 171:3a7713b1edbc 6235 #define EWM_SERV_SERVICE_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6236 #define EWM_SERV_SERVICE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6237 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
AnnaBridge 171:3a7713b1edbc 6238
AnnaBridge 171:3a7713b1edbc 6239 /*! @name CMPL - Compare Low Register */
AnnaBridge 171:3a7713b1edbc 6240 #define EWM_CMPL_COMPAREL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6241 #define EWM_CMPL_COMPAREL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6242 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
AnnaBridge 171:3a7713b1edbc 6243
AnnaBridge 171:3a7713b1edbc 6244 /*! @name CMPH - Compare High Register */
AnnaBridge 171:3a7713b1edbc 6245 #define EWM_CMPH_COMPAREH_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6246 #define EWM_CMPH_COMPAREH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6247 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
AnnaBridge 171:3a7713b1edbc 6248
AnnaBridge 171:3a7713b1edbc 6249
AnnaBridge 171:3a7713b1edbc 6250 /*!
AnnaBridge 171:3a7713b1edbc 6251 * @}
AnnaBridge 171:3a7713b1edbc 6252 */ /* end of group EWM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 6253
AnnaBridge 171:3a7713b1edbc 6254
AnnaBridge 171:3a7713b1edbc 6255 /* EWM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 6256 /** Peripheral EWM base address */
AnnaBridge 171:3a7713b1edbc 6257 #define EWM_BASE (0x40061000u)
AnnaBridge 171:3a7713b1edbc 6258 /** Peripheral EWM base pointer */
AnnaBridge 171:3a7713b1edbc 6259 #define EWM ((EWM_Type *)EWM_BASE)
AnnaBridge 171:3a7713b1edbc 6260 /** Array initializer of EWM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 6261 #define EWM_BASE_ADDRS { EWM_BASE }
AnnaBridge 171:3a7713b1edbc 6262 /** Array initializer of EWM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 6263 #define EWM_BASE_PTRS { EWM }
AnnaBridge 171:3a7713b1edbc 6264 /** Interrupt vectors for the EWM peripheral type */
AnnaBridge 171:3a7713b1edbc 6265 #define EWM_IRQS { WDOG_EWM_IRQn }
AnnaBridge 171:3a7713b1edbc 6266
AnnaBridge 171:3a7713b1edbc 6267 /*!
AnnaBridge 171:3a7713b1edbc 6268 * @}
AnnaBridge 171:3a7713b1edbc 6269 */ /* end of group EWM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 6270
AnnaBridge 171:3a7713b1edbc 6271
AnnaBridge 171:3a7713b1edbc 6272 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6273 -- FB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6274 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6275
AnnaBridge 171:3a7713b1edbc 6276 /*!
AnnaBridge 171:3a7713b1edbc 6277 * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6278 * @{
AnnaBridge 171:3a7713b1edbc 6279 */
AnnaBridge 171:3a7713b1edbc 6280
AnnaBridge 171:3a7713b1edbc 6281 /** FB - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 6282 typedef struct {
AnnaBridge 171:3a7713b1edbc 6283 struct { /* offset: 0x0, array step: 0xC */
AnnaBridge 171:3a7713b1edbc 6284 __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
AnnaBridge 171:3a7713b1edbc 6285 __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
AnnaBridge 171:3a7713b1edbc 6286 __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
AnnaBridge 171:3a7713b1edbc 6287 } CS[6];
AnnaBridge 171:3a7713b1edbc 6288 uint8_t RESERVED_0[24];
AnnaBridge 171:3a7713b1edbc 6289 __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 6290 } FB_Type;
AnnaBridge 171:3a7713b1edbc 6291
AnnaBridge 171:3a7713b1edbc 6292 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6293 -- FB Register Masks
AnnaBridge 171:3a7713b1edbc 6294 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6295
AnnaBridge 171:3a7713b1edbc 6296 /*!
AnnaBridge 171:3a7713b1edbc 6297 * @addtogroup FB_Register_Masks FB Register Masks
AnnaBridge 171:3a7713b1edbc 6298 * @{
AnnaBridge 171:3a7713b1edbc 6299 */
AnnaBridge 171:3a7713b1edbc 6300
AnnaBridge 171:3a7713b1edbc 6301 /*! @name CSAR - Chip Select Address Register */
AnnaBridge 171:3a7713b1edbc 6302 #define FB_CSAR_BA_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 6303 #define FB_CSAR_BA_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6304 #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
AnnaBridge 171:3a7713b1edbc 6305
AnnaBridge 171:3a7713b1edbc 6306 /* The count of FB_CSAR */
AnnaBridge 171:3a7713b1edbc 6307 #define FB_CSAR_COUNT (6U)
AnnaBridge 171:3a7713b1edbc 6308
AnnaBridge 171:3a7713b1edbc 6309 /*! @name CSMR - Chip Select Mask Register */
AnnaBridge 171:3a7713b1edbc 6310 #define FB_CSMR_V_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6311 #define FB_CSMR_V_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6312 #define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
AnnaBridge 171:3a7713b1edbc 6313 #define FB_CSMR_WP_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 6314 #define FB_CSMR_WP_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6315 #define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
AnnaBridge 171:3a7713b1edbc 6316 #define FB_CSMR_BAM_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 6317 #define FB_CSMR_BAM_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6318 #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
AnnaBridge 171:3a7713b1edbc 6319
AnnaBridge 171:3a7713b1edbc 6320 /* The count of FB_CSMR */
AnnaBridge 171:3a7713b1edbc 6321 #define FB_CSMR_COUNT (6U)
AnnaBridge 171:3a7713b1edbc 6322
AnnaBridge 171:3a7713b1edbc 6323 /*! @name CSCR - Chip Select Control Register */
AnnaBridge 171:3a7713b1edbc 6324 #define FB_CSCR_BSTW_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6325 #define FB_CSCR_BSTW_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6326 #define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
AnnaBridge 171:3a7713b1edbc 6327 #define FB_CSCR_BSTR_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6328 #define FB_CSCR_BSTR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6329 #define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
AnnaBridge 171:3a7713b1edbc 6330 #define FB_CSCR_BEM_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6331 #define FB_CSCR_BEM_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6332 #define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
AnnaBridge 171:3a7713b1edbc 6333 #define FB_CSCR_PS_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 6334 #define FB_CSCR_PS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6335 #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
AnnaBridge 171:3a7713b1edbc 6336 #define FB_CSCR_AA_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 6337 #define FB_CSCR_AA_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6338 #define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
AnnaBridge 171:3a7713b1edbc 6339 #define FB_CSCR_BLS_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 6340 #define FB_CSCR_BLS_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 6341 #define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
AnnaBridge 171:3a7713b1edbc 6342 #define FB_CSCR_WS_MASK (0xFC00U)
AnnaBridge 171:3a7713b1edbc 6343 #define FB_CSCR_WS_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 6344 #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
AnnaBridge 171:3a7713b1edbc 6345 #define FB_CSCR_WRAH_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 6346 #define FB_CSCR_WRAH_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6347 #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
AnnaBridge 171:3a7713b1edbc 6348 #define FB_CSCR_RDAH_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 6349 #define FB_CSCR_RDAH_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 6350 #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
AnnaBridge 171:3a7713b1edbc 6351 #define FB_CSCR_ASET_MASK (0x300000U)
AnnaBridge 171:3a7713b1edbc 6352 #define FB_CSCR_ASET_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 6353 #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
AnnaBridge 171:3a7713b1edbc 6354 #define FB_CSCR_EXTS_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 6355 #define FB_CSCR_EXTS_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 6356 #define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
AnnaBridge 171:3a7713b1edbc 6357 #define FB_CSCR_SWSEN_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 6358 #define FB_CSCR_SWSEN_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 6359 #define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
AnnaBridge 171:3a7713b1edbc 6360 #define FB_CSCR_SWS_MASK (0xFC000000U)
AnnaBridge 171:3a7713b1edbc 6361 #define FB_CSCR_SWS_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 6362 #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
AnnaBridge 171:3a7713b1edbc 6363
AnnaBridge 171:3a7713b1edbc 6364 /* The count of FB_CSCR */
AnnaBridge 171:3a7713b1edbc 6365 #define FB_CSCR_COUNT (6U)
AnnaBridge 171:3a7713b1edbc 6366
AnnaBridge 171:3a7713b1edbc 6367 /*! @name CSPMCR - Chip Select port Multiplexing Control Register */
AnnaBridge 171:3a7713b1edbc 6368 #define FB_CSPMCR_GROUP5_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 6369 #define FB_CSPMCR_GROUP5_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 6370 #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
AnnaBridge 171:3a7713b1edbc 6371 #define FB_CSPMCR_GROUP4_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 6372 #define FB_CSPMCR_GROUP4_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6373 #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
AnnaBridge 171:3a7713b1edbc 6374 #define FB_CSPMCR_GROUP3_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 6375 #define FB_CSPMCR_GROUP3_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 6376 #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
AnnaBridge 171:3a7713b1edbc 6377 #define FB_CSPMCR_GROUP2_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 6378 #define FB_CSPMCR_GROUP2_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6379 #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
AnnaBridge 171:3a7713b1edbc 6380 #define FB_CSPMCR_GROUP1_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 6381 #define FB_CSPMCR_GROUP1_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 6382 #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
AnnaBridge 171:3a7713b1edbc 6383
AnnaBridge 171:3a7713b1edbc 6384
AnnaBridge 171:3a7713b1edbc 6385 /*!
AnnaBridge 171:3a7713b1edbc 6386 * @}
AnnaBridge 171:3a7713b1edbc 6387 */ /* end of group FB_Register_Masks */
AnnaBridge 171:3a7713b1edbc 6388
AnnaBridge 171:3a7713b1edbc 6389
AnnaBridge 171:3a7713b1edbc 6390 /* FB - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 6391 /** Peripheral FB base address */
AnnaBridge 171:3a7713b1edbc 6392 #define FB_BASE (0x4000C000u)
AnnaBridge 171:3a7713b1edbc 6393 /** Peripheral FB base pointer */
AnnaBridge 171:3a7713b1edbc 6394 #define FB ((FB_Type *)FB_BASE)
AnnaBridge 171:3a7713b1edbc 6395 /** Array initializer of FB peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 6396 #define FB_BASE_ADDRS { FB_BASE }
AnnaBridge 171:3a7713b1edbc 6397 /** Array initializer of FB peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 6398 #define FB_BASE_PTRS { FB }
AnnaBridge 171:3a7713b1edbc 6399
AnnaBridge 171:3a7713b1edbc 6400 /*!
AnnaBridge 171:3a7713b1edbc 6401 * @}
AnnaBridge 171:3a7713b1edbc 6402 */ /* end of group FB_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 6403
AnnaBridge 171:3a7713b1edbc 6404
AnnaBridge 171:3a7713b1edbc 6405 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6406 -- FMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6407 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6408
AnnaBridge 171:3a7713b1edbc 6409 /*!
AnnaBridge 171:3a7713b1edbc 6410 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6411 * @{
AnnaBridge 171:3a7713b1edbc 6412 */
AnnaBridge 171:3a7713b1edbc 6413
AnnaBridge 171:3a7713b1edbc 6414 /** FMC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 6415 typedef struct {
AnnaBridge 171:3a7713b1edbc 6416 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 6417 __IO uint32_t PFB01CR; /**< Flash Bank 0-1 Control Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 6418 __IO uint32_t PFB23CR; /**< Flash Bank 2-3 Control Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 6419 uint8_t RESERVED_0[244];
AnnaBridge 171:3a7713b1edbc 6420 __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 6421 __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 6422 __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 6423 __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 6424 uint8_t RESERVED_1[192];
AnnaBridge 171:3a7713b1edbc 6425 struct { /* offset: 0x200, array step: index*0x40, index2*0x10 */
AnnaBridge 171:3a7713b1edbc 6426 __IO uint32_t DATA_UM; /**< Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 */
AnnaBridge 171:3a7713b1edbc 6427 __IO uint32_t DATA_MU; /**< Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 */
AnnaBridge 171:3a7713b1edbc 6428 __IO uint32_t DATA_ML; /**< Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 */
AnnaBridge 171:3a7713b1edbc 6429 __IO uint32_t DATA_LM; /**< Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 */
AnnaBridge 171:3a7713b1edbc 6430 } SET[4][4];
AnnaBridge 171:3a7713b1edbc 6431 } FMC_Type;
AnnaBridge 171:3a7713b1edbc 6432
AnnaBridge 171:3a7713b1edbc 6433 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6434 -- FMC Register Masks
AnnaBridge 171:3a7713b1edbc 6435 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6436
AnnaBridge 171:3a7713b1edbc 6437 /*!
AnnaBridge 171:3a7713b1edbc 6438 * @addtogroup FMC_Register_Masks FMC Register Masks
AnnaBridge 171:3a7713b1edbc 6439 * @{
AnnaBridge 171:3a7713b1edbc 6440 */
AnnaBridge 171:3a7713b1edbc 6441
AnnaBridge 171:3a7713b1edbc 6442 /*! @name PFAPR - Flash Access Protection Register */
AnnaBridge 171:3a7713b1edbc 6443 #define FMC_PFAPR_M0AP_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 6444 #define FMC_PFAPR_M0AP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6445 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
AnnaBridge 171:3a7713b1edbc 6446 #define FMC_PFAPR_M1AP_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 6447 #define FMC_PFAPR_M1AP_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6448 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
AnnaBridge 171:3a7713b1edbc 6449 #define FMC_PFAPR_M2AP_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 6450 #define FMC_PFAPR_M2AP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6451 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
AnnaBridge 171:3a7713b1edbc 6452 #define FMC_PFAPR_M3AP_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 6453 #define FMC_PFAPR_M3AP_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6454 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
AnnaBridge 171:3a7713b1edbc 6455 #define FMC_PFAPR_M4AP_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 6456 #define FMC_PFAPR_M4AP_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6457 #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
AnnaBridge 171:3a7713b1edbc 6458 #define FMC_PFAPR_M5AP_MASK (0xC00U)
AnnaBridge 171:3a7713b1edbc 6459 #define FMC_PFAPR_M5AP_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 6460 #define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
AnnaBridge 171:3a7713b1edbc 6461 #define FMC_PFAPR_M6AP_MASK (0x3000U)
AnnaBridge 171:3a7713b1edbc 6462 #define FMC_PFAPR_M6AP_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 6463 #define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
AnnaBridge 171:3a7713b1edbc 6464 #define FMC_PFAPR_M7AP_MASK (0xC000U)
AnnaBridge 171:3a7713b1edbc 6465 #define FMC_PFAPR_M7AP_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 6466 #define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
AnnaBridge 171:3a7713b1edbc 6467 #define FMC_PFAPR_M0PFD_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 6468 #define FMC_PFAPR_M0PFD_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6469 #define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
AnnaBridge 171:3a7713b1edbc 6470 #define FMC_PFAPR_M1PFD_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 6471 #define FMC_PFAPR_M1PFD_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 6472 #define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
AnnaBridge 171:3a7713b1edbc 6473 #define FMC_PFAPR_M2PFD_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 6474 #define FMC_PFAPR_M2PFD_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 6475 #define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
AnnaBridge 171:3a7713b1edbc 6476 #define FMC_PFAPR_M3PFD_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 6477 #define FMC_PFAPR_M3PFD_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 6478 #define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
AnnaBridge 171:3a7713b1edbc 6479 #define FMC_PFAPR_M4PFD_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 6480 #define FMC_PFAPR_M4PFD_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 6481 #define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
AnnaBridge 171:3a7713b1edbc 6482 #define FMC_PFAPR_M5PFD_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 6483 #define FMC_PFAPR_M5PFD_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 6484 #define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
AnnaBridge 171:3a7713b1edbc 6485 #define FMC_PFAPR_M6PFD_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 6486 #define FMC_PFAPR_M6PFD_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 6487 #define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
AnnaBridge 171:3a7713b1edbc 6488 #define FMC_PFAPR_M7PFD_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 6489 #define FMC_PFAPR_M7PFD_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 6490 #define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
AnnaBridge 171:3a7713b1edbc 6491
AnnaBridge 171:3a7713b1edbc 6492 /*! @name PFB01CR - Flash Bank 0-1 Control Register */
AnnaBridge 171:3a7713b1edbc 6493 #define FMC_PFB01CR_RFU_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6494 #define FMC_PFB01CR_RFU_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6495 #define FMC_PFB01CR_RFU(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_RFU_SHIFT)) & FMC_PFB01CR_RFU_MASK)
AnnaBridge 171:3a7713b1edbc 6496 #define FMC_PFB01CR_B0IPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6497 #define FMC_PFB01CR_B0IPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6498 #define FMC_PFB01CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0IPE_SHIFT)) & FMC_PFB01CR_B0IPE_MASK)
AnnaBridge 171:3a7713b1edbc 6499 #define FMC_PFB01CR_B0DPE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6500 #define FMC_PFB01CR_B0DPE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6501 #define FMC_PFB01CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DPE_SHIFT)) & FMC_PFB01CR_B0DPE_MASK)
AnnaBridge 171:3a7713b1edbc 6502 #define FMC_PFB01CR_B0ICE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6503 #define FMC_PFB01CR_B0ICE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6504 #define FMC_PFB01CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0ICE_SHIFT)) & FMC_PFB01CR_B0ICE_MASK)
AnnaBridge 171:3a7713b1edbc 6505 #define FMC_PFB01CR_B0DCE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6506 #define FMC_PFB01CR_B0DCE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6507 #define FMC_PFB01CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DCE_SHIFT)) & FMC_PFB01CR_B0DCE_MASK)
AnnaBridge 171:3a7713b1edbc 6508 #define FMC_PFB01CR_CRC_MASK (0xE0U)
AnnaBridge 171:3a7713b1edbc 6509 #define FMC_PFB01CR_CRC_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6510 #define FMC_PFB01CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CRC_SHIFT)) & FMC_PFB01CR_CRC_MASK)
AnnaBridge 171:3a7713b1edbc 6511 #define FMC_PFB01CR_B0MW_MASK (0x60000U)
AnnaBridge 171:3a7713b1edbc 6512 #define FMC_PFB01CR_B0MW_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 6513 #define FMC_PFB01CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0MW_SHIFT)) & FMC_PFB01CR_B0MW_MASK)
AnnaBridge 171:3a7713b1edbc 6514 #define FMC_PFB01CR_S_B_INV_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 6515 #define FMC_PFB01CR_S_B_INV_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 6516 #define FMC_PFB01CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_S_B_INV_SHIFT)) & FMC_PFB01CR_S_B_INV_MASK)
AnnaBridge 171:3a7713b1edbc 6517 #define FMC_PFB01CR_CINV_WAY_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 6518 #define FMC_PFB01CR_CINV_WAY_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 6519 #define FMC_PFB01CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CINV_WAY_SHIFT)) & FMC_PFB01CR_CINV_WAY_MASK)
AnnaBridge 171:3a7713b1edbc 6520 #define FMC_PFB01CR_CLCK_WAY_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 6521 #define FMC_PFB01CR_CLCK_WAY_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6522 #define FMC_PFB01CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CLCK_WAY_SHIFT)) & FMC_PFB01CR_CLCK_WAY_MASK)
AnnaBridge 171:3a7713b1edbc 6523 #define FMC_PFB01CR_B0RWSC_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 6524 #define FMC_PFB01CR_B0RWSC_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 6525 #define FMC_PFB01CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0RWSC_SHIFT)) & FMC_PFB01CR_B0RWSC_MASK)
AnnaBridge 171:3a7713b1edbc 6526
AnnaBridge 171:3a7713b1edbc 6527 /*! @name PFB23CR - Flash Bank 2-3 Control Register */
AnnaBridge 171:3a7713b1edbc 6528 #define FMC_PFB23CR_RFU_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6529 #define FMC_PFB23CR_RFU_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6530 #define FMC_PFB23CR_RFU(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_RFU_SHIFT)) & FMC_PFB23CR_RFU_MASK)
AnnaBridge 171:3a7713b1edbc 6531 #define FMC_PFB23CR_B1IPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6532 #define FMC_PFB23CR_B1IPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6533 #define FMC_PFB23CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1IPE_SHIFT)) & FMC_PFB23CR_B1IPE_MASK)
AnnaBridge 171:3a7713b1edbc 6534 #define FMC_PFB23CR_B1DPE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6535 #define FMC_PFB23CR_B1DPE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6536 #define FMC_PFB23CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DPE_SHIFT)) & FMC_PFB23CR_B1DPE_MASK)
AnnaBridge 171:3a7713b1edbc 6537 #define FMC_PFB23CR_B1ICE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6538 #define FMC_PFB23CR_B1ICE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6539 #define FMC_PFB23CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1ICE_SHIFT)) & FMC_PFB23CR_B1ICE_MASK)
AnnaBridge 171:3a7713b1edbc 6540 #define FMC_PFB23CR_B1DCE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6541 #define FMC_PFB23CR_B1DCE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6542 #define FMC_PFB23CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DCE_SHIFT)) & FMC_PFB23CR_B1DCE_MASK)
AnnaBridge 171:3a7713b1edbc 6543 #define FMC_PFB23CR_B1MW_MASK (0x60000U)
AnnaBridge 171:3a7713b1edbc 6544 #define FMC_PFB23CR_B1MW_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 6545 #define FMC_PFB23CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1MW_SHIFT)) & FMC_PFB23CR_B1MW_MASK)
AnnaBridge 171:3a7713b1edbc 6546 #define FMC_PFB23CR_B1RWSC_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 6547 #define FMC_PFB23CR_B1RWSC_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 6548 #define FMC_PFB23CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1RWSC_SHIFT)) & FMC_PFB23CR_B1RWSC_MASK)
AnnaBridge 171:3a7713b1edbc 6549
AnnaBridge 171:3a7713b1edbc 6550 /*! @name TAGVDW0S - Cache Tag Storage */
AnnaBridge 171:3a7713b1edbc 6551 #define FMC_TAGVDW0S_valid_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6552 #define FMC_TAGVDW0S_valid_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6553 #define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
AnnaBridge 171:3a7713b1edbc 6554 #define FMC_TAGVDW0S_tag_MASK (0x3FFFC0U)
AnnaBridge 171:3a7713b1edbc 6555 #define FMC_TAGVDW0S_tag_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6556 #define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)
AnnaBridge 171:3a7713b1edbc 6557
AnnaBridge 171:3a7713b1edbc 6558 /* The count of FMC_TAGVDW0S */
AnnaBridge 171:3a7713b1edbc 6559 #define FMC_TAGVDW0S_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 6560
AnnaBridge 171:3a7713b1edbc 6561 /*! @name TAGVDW1S - Cache Tag Storage */
AnnaBridge 171:3a7713b1edbc 6562 #define FMC_TAGVDW1S_valid_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6563 #define FMC_TAGVDW1S_valid_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6564 #define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
AnnaBridge 171:3a7713b1edbc 6565 #define FMC_TAGVDW1S_tag_MASK (0x3FFFC0U)
AnnaBridge 171:3a7713b1edbc 6566 #define FMC_TAGVDW1S_tag_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6567 #define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)
AnnaBridge 171:3a7713b1edbc 6568
AnnaBridge 171:3a7713b1edbc 6569 /* The count of FMC_TAGVDW1S */
AnnaBridge 171:3a7713b1edbc 6570 #define FMC_TAGVDW1S_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 6571
AnnaBridge 171:3a7713b1edbc 6572 /*! @name TAGVDW2S - Cache Tag Storage */
AnnaBridge 171:3a7713b1edbc 6573 #define FMC_TAGVDW2S_valid_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6574 #define FMC_TAGVDW2S_valid_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6575 #define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
AnnaBridge 171:3a7713b1edbc 6576 #define FMC_TAGVDW2S_tag_MASK (0x3FFFC0U)
AnnaBridge 171:3a7713b1edbc 6577 #define FMC_TAGVDW2S_tag_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6578 #define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)
AnnaBridge 171:3a7713b1edbc 6579
AnnaBridge 171:3a7713b1edbc 6580 /* The count of FMC_TAGVDW2S */
AnnaBridge 171:3a7713b1edbc 6581 #define FMC_TAGVDW2S_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 6582
AnnaBridge 171:3a7713b1edbc 6583 /*! @name TAGVDW3S - Cache Tag Storage */
AnnaBridge 171:3a7713b1edbc 6584 #define FMC_TAGVDW3S_valid_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6585 #define FMC_TAGVDW3S_valid_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6586 #define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
AnnaBridge 171:3a7713b1edbc 6587 #define FMC_TAGVDW3S_tag_MASK (0x3FFFC0U)
AnnaBridge 171:3a7713b1edbc 6588 #define FMC_TAGVDW3S_tag_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6589 #define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)
AnnaBridge 171:3a7713b1edbc 6590
AnnaBridge 171:3a7713b1edbc 6591 /* The count of FMC_TAGVDW3S */
AnnaBridge 171:3a7713b1edbc 6592 #define FMC_TAGVDW3S_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 6593
AnnaBridge 171:3a7713b1edbc 6594 /*! @name DATA_UM - Cache Data Storage (uppermost word) */
AnnaBridge 171:3a7713b1edbc 6595 #define FMC_DATA_UM_data_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6596 #define FMC_DATA_UM_data_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6597 #define FMC_DATA_UM_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_UM_data_SHIFT)) & FMC_DATA_UM_data_MASK)
AnnaBridge 171:3a7713b1edbc 6598
AnnaBridge 171:3a7713b1edbc 6599 /* The count of FMC_DATA_UM */
AnnaBridge 171:3a7713b1edbc 6600 #define FMC_DATA_UM_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 6601
AnnaBridge 171:3a7713b1edbc 6602 /* The count of FMC_DATA_UM */
AnnaBridge 171:3a7713b1edbc 6603 #define FMC_DATA_UM_COUNT2 (4U)
AnnaBridge 171:3a7713b1edbc 6604
AnnaBridge 171:3a7713b1edbc 6605 /*! @name DATA_MU - Cache Data Storage (mid-upper word) */
AnnaBridge 171:3a7713b1edbc 6606 #define FMC_DATA_MU_data_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6607 #define FMC_DATA_MU_data_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6608 #define FMC_DATA_MU_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_MU_data_SHIFT)) & FMC_DATA_MU_data_MASK)
AnnaBridge 171:3a7713b1edbc 6609
AnnaBridge 171:3a7713b1edbc 6610 /* The count of FMC_DATA_MU */
AnnaBridge 171:3a7713b1edbc 6611 #define FMC_DATA_MU_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 6612
AnnaBridge 171:3a7713b1edbc 6613 /* The count of FMC_DATA_MU */
AnnaBridge 171:3a7713b1edbc 6614 #define FMC_DATA_MU_COUNT2 (4U)
AnnaBridge 171:3a7713b1edbc 6615
AnnaBridge 171:3a7713b1edbc 6616 /*! @name DATA_ML - Cache Data Storage (mid-lower word) */
AnnaBridge 171:3a7713b1edbc 6617 #define FMC_DATA_ML_data_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6618 #define FMC_DATA_ML_data_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6619 #define FMC_DATA_ML_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_ML_data_SHIFT)) & FMC_DATA_ML_data_MASK)
AnnaBridge 171:3a7713b1edbc 6620
AnnaBridge 171:3a7713b1edbc 6621 /* The count of FMC_DATA_ML */
AnnaBridge 171:3a7713b1edbc 6622 #define FMC_DATA_ML_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 6623
AnnaBridge 171:3a7713b1edbc 6624 /* The count of FMC_DATA_ML */
AnnaBridge 171:3a7713b1edbc 6625 #define FMC_DATA_ML_COUNT2 (4U)
AnnaBridge 171:3a7713b1edbc 6626
AnnaBridge 171:3a7713b1edbc 6627 /*! @name DATA_LM - Cache Data Storage (lowermost word) */
AnnaBridge 171:3a7713b1edbc 6628 #define FMC_DATA_LM_data_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6629 #define FMC_DATA_LM_data_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6630 #define FMC_DATA_LM_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_LM_data_SHIFT)) & FMC_DATA_LM_data_MASK)
AnnaBridge 171:3a7713b1edbc 6631
AnnaBridge 171:3a7713b1edbc 6632 /* The count of FMC_DATA_LM */
AnnaBridge 171:3a7713b1edbc 6633 #define FMC_DATA_LM_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 6634
AnnaBridge 171:3a7713b1edbc 6635 /* The count of FMC_DATA_LM */
AnnaBridge 171:3a7713b1edbc 6636 #define FMC_DATA_LM_COUNT2 (4U)
AnnaBridge 171:3a7713b1edbc 6637
AnnaBridge 171:3a7713b1edbc 6638
AnnaBridge 171:3a7713b1edbc 6639 /*!
AnnaBridge 171:3a7713b1edbc 6640 * @}
AnnaBridge 171:3a7713b1edbc 6641 */ /* end of group FMC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 6642
AnnaBridge 171:3a7713b1edbc 6643
AnnaBridge 171:3a7713b1edbc 6644 /* FMC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 6645 /** Peripheral FMC base address */
AnnaBridge 171:3a7713b1edbc 6646 #define FMC_BASE (0x4001F000u)
AnnaBridge 171:3a7713b1edbc 6647 /** Peripheral FMC base pointer */
AnnaBridge 171:3a7713b1edbc 6648 #define FMC ((FMC_Type *)FMC_BASE)
AnnaBridge 171:3a7713b1edbc 6649 /** Array initializer of FMC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 6650 #define FMC_BASE_ADDRS { FMC_BASE }
AnnaBridge 171:3a7713b1edbc 6651 /** Array initializer of FMC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 6652 #define FMC_BASE_PTRS { FMC }
AnnaBridge 171:3a7713b1edbc 6653
AnnaBridge 171:3a7713b1edbc 6654 /*!
AnnaBridge 171:3a7713b1edbc 6655 * @}
AnnaBridge 171:3a7713b1edbc 6656 */ /* end of group FMC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 6657
AnnaBridge 171:3a7713b1edbc 6658
AnnaBridge 171:3a7713b1edbc 6659 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6660 -- FTFE Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6661 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6662
AnnaBridge 171:3a7713b1edbc 6663 /*!
AnnaBridge 171:3a7713b1edbc 6664 * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6665 * @{
AnnaBridge 171:3a7713b1edbc 6666 */
AnnaBridge 171:3a7713b1edbc 6667
AnnaBridge 171:3a7713b1edbc 6668 /** FTFE - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 6669 typedef struct {
AnnaBridge 171:3a7713b1edbc 6670 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 6671 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 6672 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 6673 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 6674 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 6675 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 6676 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 6677 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 6678 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 6679 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 6680 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 6681 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 6682 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 6683 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 6684 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
AnnaBridge 171:3a7713b1edbc 6685 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
AnnaBridge 171:3a7713b1edbc 6686 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 6687 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
AnnaBridge 171:3a7713b1edbc 6688 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
AnnaBridge 171:3a7713b1edbc 6689 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
AnnaBridge 171:3a7713b1edbc 6690 uint8_t RESERVED_0[2];
AnnaBridge 171:3a7713b1edbc 6691 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
AnnaBridge 171:3a7713b1edbc 6692 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
AnnaBridge 171:3a7713b1edbc 6693 __I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 6694 __I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */
AnnaBridge 171:3a7713b1edbc 6695 __I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */
AnnaBridge 171:3a7713b1edbc 6696 __I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */
AnnaBridge 171:3a7713b1edbc 6697 __I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 6698 __I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */
AnnaBridge 171:3a7713b1edbc 6699 __I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */
AnnaBridge 171:3a7713b1edbc 6700 __I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */
AnnaBridge 171:3a7713b1edbc 6701 __I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 6702 __I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */
AnnaBridge 171:3a7713b1edbc 6703 __I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */
AnnaBridge 171:3a7713b1edbc 6704 __I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */
AnnaBridge 171:3a7713b1edbc 6705 __I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 6706 __I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */
AnnaBridge 171:3a7713b1edbc 6707 __I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */
AnnaBridge 171:3a7713b1edbc 6708 __I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */
AnnaBridge 171:3a7713b1edbc 6709 __I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 6710 uint8_t RESERVED_1[2];
AnnaBridge 171:3a7713b1edbc 6711 __I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */
AnnaBridge 171:3a7713b1edbc 6712 } FTFE_Type;
AnnaBridge 171:3a7713b1edbc 6713
AnnaBridge 171:3a7713b1edbc 6714 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6715 -- FTFE Register Masks
AnnaBridge 171:3a7713b1edbc 6716 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6717
AnnaBridge 171:3a7713b1edbc 6718 /*!
AnnaBridge 171:3a7713b1edbc 6719 * @addtogroup FTFE_Register_Masks FTFE Register Masks
AnnaBridge 171:3a7713b1edbc 6720 * @{
AnnaBridge 171:3a7713b1edbc 6721 */
AnnaBridge 171:3a7713b1edbc 6722
AnnaBridge 171:3a7713b1edbc 6723 /*! @name FSTAT - Flash Status Register */
AnnaBridge 171:3a7713b1edbc 6724 #define FTFE_FSTAT_MGSTAT0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6725 #define FTFE_FSTAT_MGSTAT0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6726 #define FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK)
AnnaBridge 171:3a7713b1edbc 6727 #define FTFE_FSTAT_FPVIOL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6728 #define FTFE_FSTAT_FPVIOL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6729 #define FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)
AnnaBridge 171:3a7713b1edbc 6730 #define FTFE_FSTAT_ACCERR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6731 #define FTFE_FSTAT_ACCERR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6732 #define FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)
AnnaBridge 171:3a7713b1edbc 6733 #define FTFE_FSTAT_RDCOLERR_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6734 #define FTFE_FSTAT_RDCOLERR_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6735 #define FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)
AnnaBridge 171:3a7713b1edbc 6736 #define FTFE_FSTAT_CCIF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6737 #define FTFE_FSTAT_CCIF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6738 #define FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)
AnnaBridge 171:3a7713b1edbc 6739
AnnaBridge 171:3a7713b1edbc 6740 /*! @name FCNFG - Flash Configuration Register */
AnnaBridge 171:3a7713b1edbc 6741 #define FTFE_FCNFG_EEERDY_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6742 #define FTFE_FCNFG_EEERDY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6743 #define FTFE_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)
AnnaBridge 171:3a7713b1edbc 6744 #define FTFE_FCNFG_RAMRDY_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6745 #define FTFE_FCNFG_RAMRDY_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6746 #define FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)
AnnaBridge 171:3a7713b1edbc 6747 #define FTFE_FCNFG_PFLSH_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6748 #define FTFE_FCNFG_PFLSH_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6749 #define FTFE_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK)
AnnaBridge 171:3a7713b1edbc 6750 #define FTFE_FCNFG_SWAP_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6751 #define FTFE_FCNFG_SWAP_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6752 #define FTFE_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK)
AnnaBridge 171:3a7713b1edbc 6753 #define FTFE_FCNFG_ERSSUSP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6754 #define FTFE_FCNFG_ERSSUSP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6755 #define FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)
AnnaBridge 171:3a7713b1edbc 6756 #define FTFE_FCNFG_ERSAREQ_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6757 #define FTFE_FCNFG_ERSAREQ_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6758 #define FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)
AnnaBridge 171:3a7713b1edbc 6759 #define FTFE_FCNFG_RDCOLLIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6760 #define FTFE_FCNFG_RDCOLLIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6761 #define FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)
AnnaBridge 171:3a7713b1edbc 6762 #define FTFE_FCNFG_CCIE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6763 #define FTFE_FCNFG_CCIE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6764 #define FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)
AnnaBridge 171:3a7713b1edbc 6765
AnnaBridge 171:3a7713b1edbc 6766 /*! @name FSEC - Flash Security Register */
AnnaBridge 171:3a7713b1edbc 6767 #define FTFE_FSEC_SEC_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 6768 #define FTFE_FSEC_SEC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6769 #define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)
AnnaBridge 171:3a7713b1edbc 6770 #define FTFE_FSEC_FSLACC_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 6771 #define FTFE_FSEC_FSLACC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6772 #define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)
AnnaBridge 171:3a7713b1edbc 6773 #define FTFE_FSEC_MEEN_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 6774 #define FTFE_FSEC_MEEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6775 #define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)
AnnaBridge 171:3a7713b1edbc 6776 #define FTFE_FSEC_KEYEN_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 6777 #define FTFE_FSEC_KEYEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6778 #define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)
AnnaBridge 171:3a7713b1edbc 6779
AnnaBridge 171:3a7713b1edbc 6780 /*! @name FOPT - Flash Option Register */
AnnaBridge 171:3a7713b1edbc 6781 #define FTFE_FOPT_OPT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6782 #define FTFE_FOPT_OPT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6783 #define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK)
AnnaBridge 171:3a7713b1edbc 6784
AnnaBridge 171:3a7713b1edbc 6785 /*! @name FCCOB3 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6786 #define FTFE_FCCOB3_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6787 #define FTFE_FCCOB3_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6788 #define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6789
AnnaBridge 171:3a7713b1edbc 6790 /*! @name FCCOB2 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6791 #define FTFE_FCCOB2_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6792 #define FTFE_FCCOB2_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6793 #define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6794
AnnaBridge 171:3a7713b1edbc 6795 /*! @name FCCOB1 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6796 #define FTFE_FCCOB1_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6797 #define FTFE_FCCOB1_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6798 #define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6799
AnnaBridge 171:3a7713b1edbc 6800 /*! @name FCCOB0 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6801 #define FTFE_FCCOB0_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6802 #define FTFE_FCCOB0_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6803 #define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6804
AnnaBridge 171:3a7713b1edbc 6805 /*! @name FCCOB7 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6806 #define FTFE_FCCOB7_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6807 #define FTFE_FCCOB7_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6808 #define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6809
AnnaBridge 171:3a7713b1edbc 6810 /*! @name FCCOB6 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6811 #define FTFE_FCCOB6_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6812 #define FTFE_FCCOB6_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6813 #define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6814
AnnaBridge 171:3a7713b1edbc 6815 /*! @name FCCOB5 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6816 #define FTFE_FCCOB5_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6817 #define FTFE_FCCOB5_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6818 #define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6819
AnnaBridge 171:3a7713b1edbc 6820 /*! @name FCCOB4 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6821 #define FTFE_FCCOB4_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6822 #define FTFE_FCCOB4_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6823 #define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6824
AnnaBridge 171:3a7713b1edbc 6825 /*! @name FCCOBB - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6826 #define FTFE_FCCOBB_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6827 #define FTFE_FCCOBB_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6828 #define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6829
AnnaBridge 171:3a7713b1edbc 6830 /*! @name FCCOBA - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6831 #define FTFE_FCCOBA_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6832 #define FTFE_FCCOBA_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6833 #define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6834
AnnaBridge 171:3a7713b1edbc 6835 /*! @name FCCOB9 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6836 #define FTFE_FCCOB9_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6837 #define FTFE_FCCOB9_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6838 #define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6839
AnnaBridge 171:3a7713b1edbc 6840 /*! @name FCCOB8 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6841 #define FTFE_FCCOB8_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6842 #define FTFE_FCCOB8_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6843 #define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6844
AnnaBridge 171:3a7713b1edbc 6845 /*! @name FPROT3 - Program Flash Protection Registers */
AnnaBridge 171:3a7713b1edbc 6846 #define FTFE_FPROT3_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6847 #define FTFE_FPROT3_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6848 #define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 6849
AnnaBridge 171:3a7713b1edbc 6850 /*! @name FPROT2 - Program Flash Protection Registers */
AnnaBridge 171:3a7713b1edbc 6851 #define FTFE_FPROT2_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6852 #define FTFE_FPROT2_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6853 #define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 6854
AnnaBridge 171:3a7713b1edbc 6855 /*! @name FPROT1 - Program Flash Protection Registers */
AnnaBridge 171:3a7713b1edbc 6856 #define FTFE_FPROT1_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6857 #define FTFE_FPROT1_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6858 #define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 6859
AnnaBridge 171:3a7713b1edbc 6860 /*! @name FPROT0 - Program Flash Protection Registers */
AnnaBridge 171:3a7713b1edbc 6861 #define FTFE_FPROT0_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6862 #define FTFE_FPROT0_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6863 #define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 6864
AnnaBridge 171:3a7713b1edbc 6865 /*! @name FEPROT - EEPROM Protection Register */
AnnaBridge 171:3a7713b1edbc 6866 #define FTFE_FEPROT_EPROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6867 #define FTFE_FEPROT_EPROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6868 #define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK)
AnnaBridge 171:3a7713b1edbc 6869
AnnaBridge 171:3a7713b1edbc 6870 /*! @name FDPROT - Data Flash Protection Register */
AnnaBridge 171:3a7713b1edbc 6871 #define FTFE_FDPROT_DPROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6872 #define FTFE_FDPROT_DPROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6873 #define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK)
AnnaBridge 171:3a7713b1edbc 6874
AnnaBridge 171:3a7713b1edbc 6875 /*! @name XACCH3 - Execute-only Access Registers */
AnnaBridge 171:3a7713b1edbc 6876 #define FTFE_XACCH3_XA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6877 #define FTFE_XACCH3_XA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6878 #define FTFE_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH3_XA_SHIFT)) & FTFE_XACCH3_XA_MASK)
AnnaBridge 171:3a7713b1edbc 6879
AnnaBridge 171:3a7713b1edbc 6880 /*! @name XACCH2 - Execute-only Access Registers */
AnnaBridge 171:3a7713b1edbc 6881 #define FTFE_XACCH2_XA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6882 #define FTFE_XACCH2_XA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6883 #define FTFE_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH2_XA_SHIFT)) & FTFE_XACCH2_XA_MASK)
AnnaBridge 171:3a7713b1edbc 6884
AnnaBridge 171:3a7713b1edbc 6885 /*! @name XACCH1 - Execute-only Access Registers */
AnnaBridge 171:3a7713b1edbc 6886 #define FTFE_XACCH1_XA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6887 #define FTFE_XACCH1_XA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6888 #define FTFE_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH1_XA_SHIFT)) & FTFE_XACCH1_XA_MASK)
AnnaBridge 171:3a7713b1edbc 6889
AnnaBridge 171:3a7713b1edbc 6890 /*! @name XACCH0 - Execute-only Access Registers */
AnnaBridge 171:3a7713b1edbc 6891 #define FTFE_XACCH0_XA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6892 #define FTFE_XACCH0_XA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6893 #define FTFE_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH0_XA_SHIFT)) & FTFE_XACCH0_XA_MASK)
AnnaBridge 171:3a7713b1edbc 6894
AnnaBridge 171:3a7713b1edbc 6895 /*! @name XACCL3 - Execute-only Access Registers */
AnnaBridge 171:3a7713b1edbc 6896 #define FTFE_XACCL3_XA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6897 #define FTFE_XACCL3_XA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6898 #define FTFE_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL3_XA_SHIFT)) & FTFE_XACCL3_XA_MASK)
AnnaBridge 171:3a7713b1edbc 6899
AnnaBridge 171:3a7713b1edbc 6900 /*! @name XACCL2 - Execute-only Access Registers */
AnnaBridge 171:3a7713b1edbc 6901 #define FTFE_XACCL2_XA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6902 #define FTFE_XACCL2_XA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6903 #define FTFE_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL2_XA_SHIFT)) & FTFE_XACCL2_XA_MASK)
AnnaBridge 171:3a7713b1edbc 6904
AnnaBridge 171:3a7713b1edbc 6905 /*! @name XACCL1 - Execute-only Access Registers */
AnnaBridge 171:3a7713b1edbc 6906 #define FTFE_XACCL1_XA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6907 #define FTFE_XACCL1_XA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6908 #define FTFE_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL1_XA_SHIFT)) & FTFE_XACCL1_XA_MASK)
AnnaBridge 171:3a7713b1edbc 6909
AnnaBridge 171:3a7713b1edbc 6910 /*! @name XACCL0 - Execute-only Access Registers */
AnnaBridge 171:3a7713b1edbc 6911 #define FTFE_XACCL0_XA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6912 #define FTFE_XACCL0_XA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6913 #define FTFE_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL0_XA_SHIFT)) & FTFE_XACCL0_XA_MASK)
AnnaBridge 171:3a7713b1edbc 6914
AnnaBridge 171:3a7713b1edbc 6915 /*! @name SACCH3 - Supervisor-only Access Registers */
AnnaBridge 171:3a7713b1edbc 6916 #define FTFE_SACCH3_SA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6917 #define FTFE_SACCH3_SA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6918 #define FTFE_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH3_SA_SHIFT)) & FTFE_SACCH3_SA_MASK)
AnnaBridge 171:3a7713b1edbc 6919
AnnaBridge 171:3a7713b1edbc 6920 /*! @name SACCH2 - Supervisor-only Access Registers */
AnnaBridge 171:3a7713b1edbc 6921 #define FTFE_SACCH2_SA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6922 #define FTFE_SACCH2_SA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6923 #define FTFE_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH2_SA_SHIFT)) & FTFE_SACCH2_SA_MASK)
AnnaBridge 171:3a7713b1edbc 6924
AnnaBridge 171:3a7713b1edbc 6925 /*! @name SACCH1 - Supervisor-only Access Registers */
AnnaBridge 171:3a7713b1edbc 6926 #define FTFE_SACCH1_SA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6927 #define FTFE_SACCH1_SA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6928 #define FTFE_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH1_SA_SHIFT)) & FTFE_SACCH1_SA_MASK)
AnnaBridge 171:3a7713b1edbc 6929
AnnaBridge 171:3a7713b1edbc 6930 /*! @name SACCH0 - Supervisor-only Access Registers */
AnnaBridge 171:3a7713b1edbc 6931 #define FTFE_SACCH0_SA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6932 #define FTFE_SACCH0_SA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6933 #define FTFE_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH0_SA_SHIFT)) & FTFE_SACCH0_SA_MASK)
AnnaBridge 171:3a7713b1edbc 6934
AnnaBridge 171:3a7713b1edbc 6935 /*! @name SACCL3 - Supervisor-only Access Registers */
AnnaBridge 171:3a7713b1edbc 6936 #define FTFE_SACCL3_SA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6937 #define FTFE_SACCL3_SA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6938 #define FTFE_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL3_SA_SHIFT)) & FTFE_SACCL3_SA_MASK)
AnnaBridge 171:3a7713b1edbc 6939
AnnaBridge 171:3a7713b1edbc 6940 /*! @name SACCL2 - Supervisor-only Access Registers */
AnnaBridge 171:3a7713b1edbc 6941 #define FTFE_SACCL2_SA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6942 #define FTFE_SACCL2_SA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6943 #define FTFE_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL2_SA_SHIFT)) & FTFE_SACCL2_SA_MASK)
AnnaBridge 171:3a7713b1edbc 6944
AnnaBridge 171:3a7713b1edbc 6945 /*! @name SACCL1 - Supervisor-only Access Registers */
AnnaBridge 171:3a7713b1edbc 6946 #define FTFE_SACCL1_SA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6947 #define FTFE_SACCL1_SA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6948 #define FTFE_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL1_SA_SHIFT)) & FTFE_SACCL1_SA_MASK)
AnnaBridge 171:3a7713b1edbc 6949
AnnaBridge 171:3a7713b1edbc 6950 /*! @name SACCL0 - Supervisor-only Access Registers */
AnnaBridge 171:3a7713b1edbc 6951 #define FTFE_SACCL0_SA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6952 #define FTFE_SACCL0_SA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6953 #define FTFE_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL0_SA_SHIFT)) & FTFE_SACCL0_SA_MASK)
AnnaBridge 171:3a7713b1edbc 6954
AnnaBridge 171:3a7713b1edbc 6955 /*! @name FACSS - Flash Access Segment Size Register */
AnnaBridge 171:3a7713b1edbc 6956 #define FTFE_FACSS_SGSIZE_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6957 #define FTFE_FACSS_SGSIZE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6958 #define FTFE_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSS_SGSIZE_SHIFT)) & FTFE_FACSS_SGSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 6959
AnnaBridge 171:3a7713b1edbc 6960 /*! @name FACSN - Flash Access Segment Number Register */
AnnaBridge 171:3a7713b1edbc 6961 #define FTFE_FACSN_NUMSG_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6962 #define FTFE_FACSN_NUMSG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6963 #define FTFE_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSN_NUMSG_SHIFT)) & FTFE_FACSN_NUMSG_MASK)
AnnaBridge 171:3a7713b1edbc 6964
AnnaBridge 171:3a7713b1edbc 6965
AnnaBridge 171:3a7713b1edbc 6966 /*!
AnnaBridge 171:3a7713b1edbc 6967 * @}
AnnaBridge 171:3a7713b1edbc 6968 */ /* end of group FTFE_Register_Masks */
AnnaBridge 171:3a7713b1edbc 6969
AnnaBridge 171:3a7713b1edbc 6970
AnnaBridge 171:3a7713b1edbc 6971 /* FTFE - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 6972 /** Peripheral FTFE base address */
AnnaBridge 171:3a7713b1edbc 6973 #define FTFE_BASE (0x40020000u)
AnnaBridge 171:3a7713b1edbc 6974 /** Peripheral FTFE base pointer */
AnnaBridge 171:3a7713b1edbc 6975 #define FTFE ((FTFE_Type *)FTFE_BASE)
AnnaBridge 171:3a7713b1edbc 6976 /** Array initializer of FTFE peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 6977 #define FTFE_BASE_ADDRS { FTFE_BASE }
AnnaBridge 171:3a7713b1edbc 6978 /** Array initializer of FTFE peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 6979 #define FTFE_BASE_PTRS { FTFE }
AnnaBridge 171:3a7713b1edbc 6980 /** Interrupt vectors for the FTFE peripheral type */
AnnaBridge 171:3a7713b1edbc 6981 #define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn }
AnnaBridge 171:3a7713b1edbc 6982 #define FTFE_READ_COLLISION_IRQS { Read_Collision_IRQn }
AnnaBridge 171:3a7713b1edbc 6983
AnnaBridge 171:3a7713b1edbc 6984 /*!
AnnaBridge 171:3a7713b1edbc 6985 * @}
AnnaBridge 171:3a7713b1edbc 6986 */ /* end of group FTFE_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 6987
AnnaBridge 171:3a7713b1edbc 6988
AnnaBridge 171:3a7713b1edbc 6989 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6990 -- FTM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6991 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6992
AnnaBridge 171:3a7713b1edbc 6993 /*!
AnnaBridge 171:3a7713b1edbc 6994 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6995 * @{
AnnaBridge 171:3a7713b1edbc 6996 */
AnnaBridge 171:3a7713b1edbc 6997
AnnaBridge 171:3a7713b1edbc 6998 /** FTM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 6999 typedef struct {
AnnaBridge 171:3a7713b1edbc 7000 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 7001 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 7002 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 7003 struct { /* offset: 0xC, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 7004 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 7005 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 7006 } CONTROLS[8];
AnnaBridge 171:3a7713b1edbc 7007 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 7008 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 7009 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 7010 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 7011 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 7012 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 7013 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 7014 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 7015 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 7016 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
AnnaBridge 171:3a7713b1edbc 7017 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
AnnaBridge 171:3a7713b1edbc 7018 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
AnnaBridge 171:3a7713b1edbc 7019 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
AnnaBridge 171:3a7713b1edbc 7020 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 7021 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 7022 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 7023 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 7024 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 7025 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 7026 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
AnnaBridge 171:3a7713b1edbc 7027 } FTM_Type;
AnnaBridge 171:3a7713b1edbc 7028
AnnaBridge 171:3a7713b1edbc 7029 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7030 -- FTM Register Masks
AnnaBridge 171:3a7713b1edbc 7031 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7032
AnnaBridge 171:3a7713b1edbc 7033 /*!
AnnaBridge 171:3a7713b1edbc 7034 * @addtogroup FTM_Register_Masks FTM Register Masks
AnnaBridge 171:3a7713b1edbc 7035 * @{
AnnaBridge 171:3a7713b1edbc 7036 */
AnnaBridge 171:3a7713b1edbc 7037
AnnaBridge 171:3a7713b1edbc 7038 /*! @name SC - Status And Control */
AnnaBridge 171:3a7713b1edbc 7039 #define FTM_SC_PS_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 7040 #define FTM_SC_PS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7041 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
AnnaBridge 171:3a7713b1edbc 7042 #define FTM_SC_CLKS_MASK (0x18U)
AnnaBridge 171:3a7713b1edbc 7043 #define FTM_SC_CLKS_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7044 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
AnnaBridge 171:3a7713b1edbc 7045 #define FTM_SC_CPWMS_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7046 #define FTM_SC_CPWMS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7047 #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
AnnaBridge 171:3a7713b1edbc 7048 #define FTM_SC_TOIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7049 #define FTM_SC_TOIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7050 #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
AnnaBridge 171:3a7713b1edbc 7051 #define FTM_SC_TOF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7052 #define FTM_SC_TOF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7053 #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
AnnaBridge 171:3a7713b1edbc 7054
AnnaBridge 171:3a7713b1edbc 7055 /*! @name CNT - Counter */
AnnaBridge 171:3a7713b1edbc 7056 #define FTM_CNT_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7057 #define FTM_CNT_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7058 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 7059
AnnaBridge 171:3a7713b1edbc 7060 /*! @name MOD - Modulo */
AnnaBridge 171:3a7713b1edbc 7061 #define FTM_MOD_MOD_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7062 #define FTM_MOD_MOD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7063 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
AnnaBridge 171:3a7713b1edbc 7064
AnnaBridge 171:3a7713b1edbc 7065 /*! @name CnSC - Channel (n) Status And Control */
AnnaBridge 171:3a7713b1edbc 7066 #define FTM_CnSC_DMA_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7067 #define FTM_CnSC_DMA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7068 #define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
AnnaBridge 171:3a7713b1edbc 7069 #define FTM_CnSC_ELSA_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7070 #define FTM_CnSC_ELSA_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7071 #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
AnnaBridge 171:3a7713b1edbc 7072 #define FTM_CnSC_ELSB_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7073 #define FTM_CnSC_ELSB_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7074 #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
AnnaBridge 171:3a7713b1edbc 7075 #define FTM_CnSC_MSA_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7076 #define FTM_CnSC_MSA_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7077 #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
AnnaBridge 171:3a7713b1edbc 7078 #define FTM_CnSC_MSB_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7079 #define FTM_CnSC_MSB_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7080 #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
AnnaBridge 171:3a7713b1edbc 7081 #define FTM_CnSC_CHIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7082 #define FTM_CnSC_CHIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7083 #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
AnnaBridge 171:3a7713b1edbc 7084 #define FTM_CnSC_CHF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7085 #define FTM_CnSC_CHF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7086 #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
AnnaBridge 171:3a7713b1edbc 7087
AnnaBridge 171:3a7713b1edbc 7088 /* The count of FTM_CnSC */
AnnaBridge 171:3a7713b1edbc 7089 #define FTM_CnSC_COUNT (8U)
AnnaBridge 171:3a7713b1edbc 7090
AnnaBridge 171:3a7713b1edbc 7091 /*! @name CnV - Channel (n) Value */
AnnaBridge 171:3a7713b1edbc 7092 #define FTM_CnV_VAL_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7093 #define FTM_CnV_VAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7094 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
AnnaBridge 171:3a7713b1edbc 7095
AnnaBridge 171:3a7713b1edbc 7096 /* The count of FTM_CnV */
AnnaBridge 171:3a7713b1edbc 7097 #define FTM_CnV_COUNT (8U)
AnnaBridge 171:3a7713b1edbc 7098
AnnaBridge 171:3a7713b1edbc 7099 /*! @name CNTIN - Counter Initial Value */
AnnaBridge 171:3a7713b1edbc 7100 #define FTM_CNTIN_INIT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7101 #define FTM_CNTIN_INIT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7102 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
AnnaBridge 171:3a7713b1edbc 7103
AnnaBridge 171:3a7713b1edbc 7104 /*! @name STATUS - Capture And Compare Status */
AnnaBridge 171:3a7713b1edbc 7105 #define FTM_STATUS_CH0F_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7106 #define FTM_STATUS_CH0F_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7107 #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
AnnaBridge 171:3a7713b1edbc 7108 #define FTM_STATUS_CH1F_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7109 #define FTM_STATUS_CH1F_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7110 #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
AnnaBridge 171:3a7713b1edbc 7111 #define FTM_STATUS_CH2F_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7112 #define FTM_STATUS_CH2F_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7113 #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
AnnaBridge 171:3a7713b1edbc 7114 #define FTM_STATUS_CH3F_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7115 #define FTM_STATUS_CH3F_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7116 #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
AnnaBridge 171:3a7713b1edbc 7117 #define FTM_STATUS_CH4F_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7118 #define FTM_STATUS_CH4F_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7119 #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
AnnaBridge 171:3a7713b1edbc 7120 #define FTM_STATUS_CH5F_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7121 #define FTM_STATUS_CH5F_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7122 #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
AnnaBridge 171:3a7713b1edbc 7123 #define FTM_STATUS_CH6F_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7124 #define FTM_STATUS_CH6F_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7125 #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
AnnaBridge 171:3a7713b1edbc 7126 #define FTM_STATUS_CH7F_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7127 #define FTM_STATUS_CH7F_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7128 #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
AnnaBridge 171:3a7713b1edbc 7129
AnnaBridge 171:3a7713b1edbc 7130 /*! @name MODE - Features Mode Selection */
AnnaBridge 171:3a7713b1edbc 7131 #define FTM_MODE_FTMEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7132 #define FTM_MODE_FTMEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7133 #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
AnnaBridge 171:3a7713b1edbc 7134 #define FTM_MODE_INIT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7135 #define FTM_MODE_INIT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7136 #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
AnnaBridge 171:3a7713b1edbc 7137 #define FTM_MODE_WPDIS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7138 #define FTM_MODE_WPDIS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7139 #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
AnnaBridge 171:3a7713b1edbc 7140 #define FTM_MODE_PWMSYNC_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7141 #define FTM_MODE_PWMSYNC_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7142 #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
AnnaBridge 171:3a7713b1edbc 7143 #define FTM_MODE_CAPTEST_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7144 #define FTM_MODE_CAPTEST_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7145 #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
AnnaBridge 171:3a7713b1edbc 7146 #define FTM_MODE_FAULTM_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 7147 #define FTM_MODE_FAULTM_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7148 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
AnnaBridge 171:3a7713b1edbc 7149 #define FTM_MODE_FAULTIE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7150 #define FTM_MODE_FAULTIE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7151 #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
AnnaBridge 171:3a7713b1edbc 7152
AnnaBridge 171:3a7713b1edbc 7153 /*! @name SYNC - Synchronization */
AnnaBridge 171:3a7713b1edbc 7154 #define FTM_SYNC_CNTMIN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7155 #define FTM_SYNC_CNTMIN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7156 #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
AnnaBridge 171:3a7713b1edbc 7157 #define FTM_SYNC_CNTMAX_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7158 #define FTM_SYNC_CNTMAX_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7159 #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
AnnaBridge 171:3a7713b1edbc 7160 #define FTM_SYNC_REINIT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7161 #define FTM_SYNC_REINIT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7162 #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
AnnaBridge 171:3a7713b1edbc 7163 #define FTM_SYNC_SYNCHOM_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7164 #define FTM_SYNC_SYNCHOM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7165 #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
AnnaBridge 171:3a7713b1edbc 7166 #define FTM_SYNC_TRIG0_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7167 #define FTM_SYNC_TRIG0_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7168 #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
AnnaBridge 171:3a7713b1edbc 7169 #define FTM_SYNC_TRIG1_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7170 #define FTM_SYNC_TRIG1_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7171 #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
AnnaBridge 171:3a7713b1edbc 7172 #define FTM_SYNC_TRIG2_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7173 #define FTM_SYNC_TRIG2_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7174 #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
AnnaBridge 171:3a7713b1edbc 7175 #define FTM_SYNC_SWSYNC_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7176 #define FTM_SYNC_SWSYNC_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7177 #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
AnnaBridge 171:3a7713b1edbc 7178
AnnaBridge 171:3a7713b1edbc 7179 /*! @name OUTINIT - Initial State For Channels Output */
AnnaBridge 171:3a7713b1edbc 7180 #define FTM_OUTINIT_CH0OI_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7181 #define FTM_OUTINIT_CH0OI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7182 #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
AnnaBridge 171:3a7713b1edbc 7183 #define FTM_OUTINIT_CH1OI_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7184 #define FTM_OUTINIT_CH1OI_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7185 #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
AnnaBridge 171:3a7713b1edbc 7186 #define FTM_OUTINIT_CH2OI_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7187 #define FTM_OUTINIT_CH2OI_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7188 #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
AnnaBridge 171:3a7713b1edbc 7189 #define FTM_OUTINIT_CH3OI_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7190 #define FTM_OUTINIT_CH3OI_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7191 #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
AnnaBridge 171:3a7713b1edbc 7192 #define FTM_OUTINIT_CH4OI_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7193 #define FTM_OUTINIT_CH4OI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7194 #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
AnnaBridge 171:3a7713b1edbc 7195 #define FTM_OUTINIT_CH5OI_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7196 #define FTM_OUTINIT_CH5OI_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7197 #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
AnnaBridge 171:3a7713b1edbc 7198 #define FTM_OUTINIT_CH6OI_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7199 #define FTM_OUTINIT_CH6OI_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7200 #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
AnnaBridge 171:3a7713b1edbc 7201 #define FTM_OUTINIT_CH7OI_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7202 #define FTM_OUTINIT_CH7OI_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7203 #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
AnnaBridge 171:3a7713b1edbc 7204
AnnaBridge 171:3a7713b1edbc 7205 /*! @name OUTMASK - Output Mask */
AnnaBridge 171:3a7713b1edbc 7206 #define FTM_OUTMASK_CH0OM_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7207 #define FTM_OUTMASK_CH0OM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7208 #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
AnnaBridge 171:3a7713b1edbc 7209 #define FTM_OUTMASK_CH1OM_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7210 #define FTM_OUTMASK_CH1OM_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7211 #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
AnnaBridge 171:3a7713b1edbc 7212 #define FTM_OUTMASK_CH2OM_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7213 #define FTM_OUTMASK_CH2OM_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7214 #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
AnnaBridge 171:3a7713b1edbc 7215 #define FTM_OUTMASK_CH3OM_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7216 #define FTM_OUTMASK_CH3OM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7217 #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
AnnaBridge 171:3a7713b1edbc 7218 #define FTM_OUTMASK_CH4OM_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7219 #define FTM_OUTMASK_CH4OM_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7220 #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
AnnaBridge 171:3a7713b1edbc 7221 #define FTM_OUTMASK_CH5OM_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7222 #define FTM_OUTMASK_CH5OM_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7223 #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
AnnaBridge 171:3a7713b1edbc 7224 #define FTM_OUTMASK_CH6OM_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7225 #define FTM_OUTMASK_CH6OM_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7226 #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
AnnaBridge 171:3a7713b1edbc 7227 #define FTM_OUTMASK_CH7OM_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7228 #define FTM_OUTMASK_CH7OM_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7229 #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
AnnaBridge 171:3a7713b1edbc 7230
AnnaBridge 171:3a7713b1edbc 7231 /*! @name COMBINE - Function For Linked Channels */
AnnaBridge 171:3a7713b1edbc 7232 #define FTM_COMBINE_COMBINE0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7233 #define FTM_COMBINE_COMBINE0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7234 #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
AnnaBridge 171:3a7713b1edbc 7235 #define FTM_COMBINE_COMP0_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7236 #define FTM_COMBINE_COMP0_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7237 #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
AnnaBridge 171:3a7713b1edbc 7238 #define FTM_COMBINE_DECAPEN0_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7239 #define FTM_COMBINE_DECAPEN0_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7240 #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
AnnaBridge 171:3a7713b1edbc 7241 #define FTM_COMBINE_DECAP0_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7242 #define FTM_COMBINE_DECAP0_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7243 #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
AnnaBridge 171:3a7713b1edbc 7244 #define FTM_COMBINE_DTEN0_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7245 #define FTM_COMBINE_DTEN0_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7246 #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
AnnaBridge 171:3a7713b1edbc 7247 #define FTM_COMBINE_SYNCEN0_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7248 #define FTM_COMBINE_SYNCEN0_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7249 #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
AnnaBridge 171:3a7713b1edbc 7250 #define FTM_COMBINE_FAULTEN0_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7251 #define FTM_COMBINE_FAULTEN0_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7252 #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
AnnaBridge 171:3a7713b1edbc 7253 #define FTM_COMBINE_COMBINE1_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 7254 #define FTM_COMBINE_COMBINE1_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7255 #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
AnnaBridge 171:3a7713b1edbc 7256 #define FTM_COMBINE_COMP1_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 7257 #define FTM_COMBINE_COMP1_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 7258 #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
AnnaBridge 171:3a7713b1edbc 7259 #define FTM_COMBINE_DECAPEN1_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 7260 #define FTM_COMBINE_DECAPEN1_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 7261 #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
AnnaBridge 171:3a7713b1edbc 7262 #define FTM_COMBINE_DECAP1_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 7263 #define FTM_COMBINE_DECAP1_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 7264 #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
AnnaBridge 171:3a7713b1edbc 7265 #define FTM_COMBINE_DTEN1_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 7266 #define FTM_COMBINE_DTEN1_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 7267 #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
AnnaBridge 171:3a7713b1edbc 7268 #define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 7269 #define FTM_COMBINE_SYNCEN1_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 7270 #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
AnnaBridge 171:3a7713b1edbc 7271 #define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 7272 #define FTM_COMBINE_FAULTEN1_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 7273 #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
AnnaBridge 171:3a7713b1edbc 7274 #define FTM_COMBINE_COMBINE2_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 7275 #define FTM_COMBINE_COMBINE2_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7276 #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
AnnaBridge 171:3a7713b1edbc 7277 #define FTM_COMBINE_COMP2_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 7278 #define FTM_COMBINE_COMP2_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 7279 #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
AnnaBridge 171:3a7713b1edbc 7280 #define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 7281 #define FTM_COMBINE_DECAPEN2_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 7282 #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
AnnaBridge 171:3a7713b1edbc 7283 #define FTM_COMBINE_DECAP2_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 7284 #define FTM_COMBINE_DECAP2_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 7285 #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
AnnaBridge 171:3a7713b1edbc 7286 #define FTM_COMBINE_DTEN2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 7287 #define FTM_COMBINE_DTEN2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 7288 #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
AnnaBridge 171:3a7713b1edbc 7289 #define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 7290 #define FTM_COMBINE_SYNCEN2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 7291 #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
AnnaBridge 171:3a7713b1edbc 7292 #define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 7293 #define FTM_COMBINE_FAULTEN2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 7294 #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
AnnaBridge 171:3a7713b1edbc 7295 #define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 7296 #define FTM_COMBINE_COMBINE3_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 7297 #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
AnnaBridge 171:3a7713b1edbc 7298 #define FTM_COMBINE_COMP3_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 7299 #define FTM_COMBINE_COMP3_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 7300 #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
AnnaBridge 171:3a7713b1edbc 7301 #define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 7302 #define FTM_COMBINE_DECAPEN3_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 7303 #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
AnnaBridge 171:3a7713b1edbc 7304 #define FTM_COMBINE_DECAP3_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 7305 #define FTM_COMBINE_DECAP3_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 7306 #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
AnnaBridge 171:3a7713b1edbc 7307 #define FTM_COMBINE_DTEN3_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 7308 #define FTM_COMBINE_DTEN3_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 7309 #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
AnnaBridge 171:3a7713b1edbc 7310 #define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 7311 #define FTM_COMBINE_SYNCEN3_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 7312 #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
AnnaBridge 171:3a7713b1edbc 7313 #define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 7314 #define FTM_COMBINE_FAULTEN3_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 7315 #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
AnnaBridge 171:3a7713b1edbc 7316
AnnaBridge 171:3a7713b1edbc 7317 /*! @name DEADTIME - Deadtime Insertion Control */
AnnaBridge 171:3a7713b1edbc 7318 #define FTM_DEADTIME_DTVAL_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 7319 #define FTM_DEADTIME_DTVAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7320 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
AnnaBridge 171:3a7713b1edbc 7321 #define FTM_DEADTIME_DTPS_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 7322 #define FTM_DEADTIME_DTPS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7323 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
AnnaBridge 171:3a7713b1edbc 7324
AnnaBridge 171:3a7713b1edbc 7325 /*! @name EXTTRIG - FTM External Trigger */
AnnaBridge 171:3a7713b1edbc 7326 #define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7327 #define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7328 #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 7329 #define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7330 #define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7331 #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 7332 #define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7333 #define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7334 #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 7335 #define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7336 #define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7337 #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 7338 #define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7339 #define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7340 #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 7341 #define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7342 #define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7343 #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 7344 #define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7345 #define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7346 #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
AnnaBridge 171:3a7713b1edbc 7347 #define FTM_EXTTRIG_TRIGF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7348 #define FTM_EXTTRIG_TRIGF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7349 #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
AnnaBridge 171:3a7713b1edbc 7350
AnnaBridge 171:3a7713b1edbc 7351 /*! @name POL - Channels Polarity */
AnnaBridge 171:3a7713b1edbc 7352 #define FTM_POL_POL0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7353 #define FTM_POL_POL0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7354 #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
AnnaBridge 171:3a7713b1edbc 7355 #define FTM_POL_POL1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7356 #define FTM_POL_POL1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7357 #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
AnnaBridge 171:3a7713b1edbc 7358 #define FTM_POL_POL2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7359 #define FTM_POL_POL2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7360 #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
AnnaBridge 171:3a7713b1edbc 7361 #define FTM_POL_POL3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7362 #define FTM_POL_POL3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7363 #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
AnnaBridge 171:3a7713b1edbc 7364 #define FTM_POL_POL4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7365 #define FTM_POL_POL4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7366 #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
AnnaBridge 171:3a7713b1edbc 7367 #define FTM_POL_POL5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7368 #define FTM_POL_POL5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7369 #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
AnnaBridge 171:3a7713b1edbc 7370 #define FTM_POL_POL6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7371 #define FTM_POL_POL6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7372 #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
AnnaBridge 171:3a7713b1edbc 7373 #define FTM_POL_POL7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7374 #define FTM_POL_POL7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7375 #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
AnnaBridge 171:3a7713b1edbc 7376
AnnaBridge 171:3a7713b1edbc 7377 /*! @name FMS - Fault Mode Status */
AnnaBridge 171:3a7713b1edbc 7378 #define FTM_FMS_FAULTF0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7379 #define FTM_FMS_FAULTF0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7380 #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
AnnaBridge 171:3a7713b1edbc 7381 #define FTM_FMS_FAULTF1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7382 #define FTM_FMS_FAULTF1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7383 #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
AnnaBridge 171:3a7713b1edbc 7384 #define FTM_FMS_FAULTF2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7385 #define FTM_FMS_FAULTF2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7386 #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
AnnaBridge 171:3a7713b1edbc 7387 #define FTM_FMS_FAULTF3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7388 #define FTM_FMS_FAULTF3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7389 #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
AnnaBridge 171:3a7713b1edbc 7390 #define FTM_FMS_FAULTIN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7391 #define FTM_FMS_FAULTIN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7392 #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
AnnaBridge 171:3a7713b1edbc 7393 #define FTM_FMS_WPEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7394 #define FTM_FMS_WPEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7395 #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
AnnaBridge 171:3a7713b1edbc 7396 #define FTM_FMS_FAULTF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7397 #define FTM_FMS_FAULTF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7398 #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
AnnaBridge 171:3a7713b1edbc 7399
AnnaBridge 171:3a7713b1edbc 7400 /*! @name FILTER - Input Capture Filter Control */
AnnaBridge 171:3a7713b1edbc 7401 #define FTM_FILTER_CH0FVAL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 7402 #define FTM_FILTER_CH0FVAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7403 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
AnnaBridge 171:3a7713b1edbc 7404 #define FTM_FILTER_CH1FVAL_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 7405 #define FTM_FILTER_CH1FVAL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7406 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
AnnaBridge 171:3a7713b1edbc 7407 #define FTM_FILTER_CH2FVAL_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 7408 #define FTM_FILTER_CH2FVAL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7409 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
AnnaBridge 171:3a7713b1edbc 7410 #define FTM_FILTER_CH3FVAL_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 7411 #define FTM_FILTER_CH3FVAL_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 7412 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
AnnaBridge 171:3a7713b1edbc 7413
AnnaBridge 171:3a7713b1edbc 7414 /*! @name FLTCTRL - Fault Control */
AnnaBridge 171:3a7713b1edbc 7415 #define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7416 #define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7417 #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
AnnaBridge 171:3a7713b1edbc 7418 #define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7419 #define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7420 #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
AnnaBridge 171:3a7713b1edbc 7421 #define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7422 #define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7423 #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
AnnaBridge 171:3a7713b1edbc 7424 #define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7425 #define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7426 #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
AnnaBridge 171:3a7713b1edbc 7427 #define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7428 #define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7429 #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
AnnaBridge 171:3a7713b1edbc 7430 #define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7431 #define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7432 #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
AnnaBridge 171:3a7713b1edbc 7433 #define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7434 #define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7435 #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
AnnaBridge 171:3a7713b1edbc 7436 #define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7437 #define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7438 #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
AnnaBridge 171:3a7713b1edbc 7439 #define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 7440 #define FTM_FLTCTRL_FFVAL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7441 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
AnnaBridge 171:3a7713b1edbc 7442
AnnaBridge 171:3a7713b1edbc 7443 /*! @name QDCTRL - Quadrature Decoder Control And Status */
AnnaBridge 171:3a7713b1edbc 7444 #define FTM_QDCTRL_QUADEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7445 #define FTM_QDCTRL_QUADEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7446 #define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
AnnaBridge 171:3a7713b1edbc 7447 #define FTM_QDCTRL_TOFDIR_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7448 #define FTM_QDCTRL_TOFDIR_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7449 #define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
AnnaBridge 171:3a7713b1edbc 7450 #define FTM_QDCTRL_QUADIR_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7451 #define FTM_QDCTRL_QUADIR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7452 #define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
AnnaBridge 171:3a7713b1edbc 7453 #define FTM_QDCTRL_QUADMODE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7454 #define FTM_QDCTRL_QUADMODE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7455 #define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
AnnaBridge 171:3a7713b1edbc 7456 #define FTM_QDCTRL_PHBPOL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7457 #define FTM_QDCTRL_PHBPOL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7458 #define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
AnnaBridge 171:3a7713b1edbc 7459 #define FTM_QDCTRL_PHAPOL_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7460 #define FTM_QDCTRL_PHAPOL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7461 #define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
AnnaBridge 171:3a7713b1edbc 7462 #define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7463 #define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7464 #define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
AnnaBridge 171:3a7713b1edbc 7465 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7466 #define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7467 #define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
AnnaBridge 171:3a7713b1edbc 7468
AnnaBridge 171:3a7713b1edbc 7469 /*! @name CONF - Configuration */
AnnaBridge 171:3a7713b1edbc 7470 #define FTM_CONF_NUMTOF_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 7471 #define FTM_CONF_NUMTOF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7472 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
AnnaBridge 171:3a7713b1edbc 7473 #define FTM_CONF_BDMMODE_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 7474 #define FTM_CONF_BDMMODE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7475 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
AnnaBridge 171:3a7713b1edbc 7476 #define FTM_CONF_GTBEEN_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 7477 #define FTM_CONF_GTBEEN_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 7478 #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
AnnaBridge 171:3a7713b1edbc 7479 #define FTM_CONF_GTBEOUT_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 7480 #define FTM_CONF_GTBEOUT_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 7481 #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
AnnaBridge 171:3a7713b1edbc 7482
AnnaBridge 171:3a7713b1edbc 7483 /*! @name FLTPOL - FTM Fault Input Polarity */
AnnaBridge 171:3a7713b1edbc 7484 #define FTM_FLTPOL_FLT0POL_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7485 #define FTM_FLTPOL_FLT0POL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7486 #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
AnnaBridge 171:3a7713b1edbc 7487 #define FTM_FLTPOL_FLT1POL_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7488 #define FTM_FLTPOL_FLT1POL_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7489 #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
AnnaBridge 171:3a7713b1edbc 7490 #define FTM_FLTPOL_FLT2POL_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7491 #define FTM_FLTPOL_FLT2POL_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7492 #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
AnnaBridge 171:3a7713b1edbc 7493 #define FTM_FLTPOL_FLT3POL_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7494 #define FTM_FLTPOL_FLT3POL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7495 #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
AnnaBridge 171:3a7713b1edbc 7496
AnnaBridge 171:3a7713b1edbc 7497 /*! @name SYNCONF - Synchronization Configuration */
AnnaBridge 171:3a7713b1edbc 7498 #define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7499 #define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7500 #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
AnnaBridge 171:3a7713b1edbc 7501 #define FTM_SYNCONF_CNTINC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7502 #define FTM_SYNCONF_CNTINC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7503 #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
AnnaBridge 171:3a7713b1edbc 7504 #define FTM_SYNCONF_INVC_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7505 #define FTM_SYNCONF_INVC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7506 #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
AnnaBridge 171:3a7713b1edbc 7507 #define FTM_SYNCONF_SWOC_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7508 #define FTM_SYNCONF_SWOC_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7509 #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
AnnaBridge 171:3a7713b1edbc 7510 #define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7511 #define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7512 #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
AnnaBridge 171:3a7713b1edbc 7513 #define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 7514 #define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7515 #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
AnnaBridge 171:3a7713b1edbc 7516 #define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 7517 #define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 7518 #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
AnnaBridge 171:3a7713b1edbc 7519 #define FTM_SYNCONF_SWOM_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 7520 #define FTM_SYNCONF_SWOM_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 7521 #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
AnnaBridge 171:3a7713b1edbc 7522 #define FTM_SYNCONF_SWINVC_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 7523 #define FTM_SYNCONF_SWINVC_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 7524 #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
AnnaBridge 171:3a7713b1edbc 7525 #define FTM_SYNCONF_SWSOC_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 7526 #define FTM_SYNCONF_SWSOC_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 7527 #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
AnnaBridge 171:3a7713b1edbc 7528 #define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 7529 #define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7530 #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
AnnaBridge 171:3a7713b1edbc 7531 #define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 7532 #define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 7533 #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
AnnaBridge 171:3a7713b1edbc 7534 #define FTM_SYNCONF_HWOM_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 7535 #define FTM_SYNCONF_HWOM_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 7536 #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
AnnaBridge 171:3a7713b1edbc 7537 #define FTM_SYNCONF_HWINVC_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 7538 #define FTM_SYNCONF_HWINVC_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 7539 #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
AnnaBridge 171:3a7713b1edbc 7540 #define FTM_SYNCONF_HWSOC_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 7541 #define FTM_SYNCONF_HWSOC_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 7542 #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
AnnaBridge 171:3a7713b1edbc 7543
AnnaBridge 171:3a7713b1edbc 7544 /*! @name INVCTRL - FTM Inverting Control */
AnnaBridge 171:3a7713b1edbc 7545 #define FTM_INVCTRL_INV0EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7546 #define FTM_INVCTRL_INV0EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7547 #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
AnnaBridge 171:3a7713b1edbc 7548 #define FTM_INVCTRL_INV1EN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7549 #define FTM_INVCTRL_INV1EN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7550 #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
AnnaBridge 171:3a7713b1edbc 7551 #define FTM_INVCTRL_INV2EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7552 #define FTM_INVCTRL_INV2EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7553 #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
AnnaBridge 171:3a7713b1edbc 7554 #define FTM_INVCTRL_INV3EN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7555 #define FTM_INVCTRL_INV3EN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7556 #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
AnnaBridge 171:3a7713b1edbc 7557
AnnaBridge 171:3a7713b1edbc 7558 /*! @name SWOCTRL - FTM Software Output Control */
AnnaBridge 171:3a7713b1edbc 7559 #define FTM_SWOCTRL_CH0OC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7560 #define FTM_SWOCTRL_CH0OC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7561 #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
AnnaBridge 171:3a7713b1edbc 7562 #define FTM_SWOCTRL_CH1OC_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7563 #define FTM_SWOCTRL_CH1OC_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7564 #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
AnnaBridge 171:3a7713b1edbc 7565 #define FTM_SWOCTRL_CH2OC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7566 #define FTM_SWOCTRL_CH2OC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7567 #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
AnnaBridge 171:3a7713b1edbc 7568 #define FTM_SWOCTRL_CH3OC_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7569 #define FTM_SWOCTRL_CH3OC_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7570 #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
AnnaBridge 171:3a7713b1edbc 7571 #define FTM_SWOCTRL_CH4OC_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7572 #define FTM_SWOCTRL_CH4OC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7573 #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
AnnaBridge 171:3a7713b1edbc 7574 #define FTM_SWOCTRL_CH5OC_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7575 #define FTM_SWOCTRL_CH5OC_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7576 #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
AnnaBridge 171:3a7713b1edbc 7577 #define FTM_SWOCTRL_CH6OC_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7578 #define FTM_SWOCTRL_CH6OC_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7579 #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
AnnaBridge 171:3a7713b1edbc 7580 #define FTM_SWOCTRL_CH7OC_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7581 #define FTM_SWOCTRL_CH7OC_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7582 #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
AnnaBridge 171:3a7713b1edbc 7583 #define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 7584 #define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7585 #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
AnnaBridge 171:3a7713b1edbc 7586 #define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 7587 #define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 7588 #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
AnnaBridge 171:3a7713b1edbc 7589 #define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 7590 #define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 7591 #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
AnnaBridge 171:3a7713b1edbc 7592 #define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 7593 #define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 7594 #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
AnnaBridge 171:3a7713b1edbc 7595 #define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 7596 #define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 7597 #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
AnnaBridge 171:3a7713b1edbc 7598 #define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 7599 #define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 7600 #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
AnnaBridge 171:3a7713b1edbc 7601 #define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 7602 #define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 7603 #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
AnnaBridge 171:3a7713b1edbc 7604 #define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 7605 #define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 7606 #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
AnnaBridge 171:3a7713b1edbc 7607
AnnaBridge 171:3a7713b1edbc 7608 /*! @name PWMLOAD - FTM PWM Load */
AnnaBridge 171:3a7713b1edbc 7609 #define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7610 #define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7611 #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
AnnaBridge 171:3a7713b1edbc 7612 #define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7613 #define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7614 #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
AnnaBridge 171:3a7713b1edbc 7615 #define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7616 #define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7617 #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
AnnaBridge 171:3a7713b1edbc 7618 #define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7619 #define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7620 #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
AnnaBridge 171:3a7713b1edbc 7621 #define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7622 #define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7623 #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
AnnaBridge 171:3a7713b1edbc 7624 #define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7625 #define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7626 #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
AnnaBridge 171:3a7713b1edbc 7627 #define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7628 #define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7629 #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
AnnaBridge 171:3a7713b1edbc 7630 #define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7631 #define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7632 #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
AnnaBridge 171:3a7713b1edbc 7633 #define FTM_PWMLOAD_LDOK_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 7634 #define FTM_PWMLOAD_LDOK_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 7635 #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
AnnaBridge 171:3a7713b1edbc 7636
AnnaBridge 171:3a7713b1edbc 7637
AnnaBridge 171:3a7713b1edbc 7638 /*!
AnnaBridge 171:3a7713b1edbc 7639 * @}
AnnaBridge 171:3a7713b1edbc 7640 */ /* end of group FTM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 7641
AnnaBridge 171:3a7713b1edbc 7642
AnnaBridge 171:3a7713b1edbc 7643 /* FTM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 7644 /** Peripheral FTM0 base address */
AnnaBridge 171:3a7713b1edbc 7645 #define FTM0_BASE (0x40038000u)
AnnaBridge 171:3a7713b1edbc 7646 /** Peripheral FTM0 base pointer */
AnnaBridge 171:3a7713b1edbc 7647 #define FTM0 ((FTM_Type *)FTM0_BASE)
AnnaBridge 171:3a7713b1edbc 7648 /** Peripheral FTM1 base address */
AnnaBridge 171:3a7713b1edbc 7649 #define FTM1_BASE (0x40039000u)
AnnaBridge 171:3a7713b1edbc 7650 /** Peripheral FTM1 base pointer */
AnnaBridge 171:3a7713b1edbc 7651 #define FTM1 ((FTM_Type *)FTM1_BASE)
AnnaBridge 171:3a7713b1edbc 7652 /** Peripheral FTM2 base address */
AnnaBridge 171:3a7713b1edbc 7653 #define FTM2_BASE (0x4003A000u)
AnnaBridge 171:3a7713b1edbc 7654 /** Peripheral FTM2 base pointer */
AnnaBridge 171:3a7713b1edbc 7655 #define FTM2 ((FTM_Type *)FTM2_BASE)
AnnaBridge 171:3a7713b1edbc 7656 /** Peripheral FTM3 base address */
AnnaBridge 171:3a7713b1edbc 7657 #define FTM3_BASE (0x400B9000u)
AnnaBridge 171:3a7713b1edbc 7658 /** Peripheral FTM3 base pointer */
AnnaBridge 171:3a7713b1edbc 7659 #define FTM3 ((FTM_Type *)FTM3_BASE)
AnnaBridge 171:3a7713b1edbc 7660 /** Array initializer of FTM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 7661 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
AnnaBridge 171:3a7713b1edbc 7662 /** Array initializer of FTM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 7663 #define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
AnnaBridge 171:3a7713b1edbc 7664 /** Interrupt vectors for the FTM peripheral type */
AnnaBridge 171:3a7713b1edbc 7665 #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
AnnaBridge 171:3a7713b1edbc 7666
AnnaBridge 171:3a7713b1edbc 7667 /*!
AnnaBridge 171:3a7713b1edbc 7668 * @}
AnnaBridge 171:3a7713b1edbc 7669 */ /* end of group FTM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 7670
AnnaBridge 171:3a7713b1edbc 7671
AnnaBridge 171:3a7713b1edbc 7672 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7673 -- GPIO Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7674 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7675
AnnaBridge 171:3a7713b1edbc 7676 /*!
AnnaBridge 171:3a7713b1edbc 7677 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7678 * @{
AnnaBridge 171:3a7713b1edbc 7679 */
AnnaBridge 171:3a7713b1edbc 7680
AnnaBridge 171:3a7713b1edbc 7681 /** GPIO - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 7682 typedef struct {
AnnaBridge 171:3a7713b1edbc 7683 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 7684 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 7685 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 7686 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 7687 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 7688 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 7689 } GPIO_Type;
AnnaBridge 171:3a7713b1edbc 7690
AnnaBridge 171:3a7713b1edbc 7691 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7692 -- GPIO Register Masks
AnnaBridge 171:3a7713b1edbc 7693 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7694
AnnaBridge 171:3a7713b1edbc 7695 /*!
AnnaBridge 171:3a7713b1edbc 7696 * @addtogroup GPIO_Register_Masks GPIO Register Masks
AnnaBridge 171:3a7713b1edbc 7697 * @{
AnnaBridge 171:3a7713b1edbc 7698 */
AnnaBridge 171:3a7713b1edbc 7699
AnnaBridge 171:3a7713b1edbc 7700 /*! @name PDOR - Port Data Output Register */
AnnaBridge 171:3a7713b1edbc 7701 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 7702 #define GPIO_PDOR_PDO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7703 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
AnnaBridge 171:3a7713b1edbc 7704
AnnaBridge 171:3a7713b1edbc 7705 /*! @name PSOR - Port Set Output Register */
AnnaBridge 171:3a7713b1edbc 7706 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 7707 #define GPIO_PSOR_PTSO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7708 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
AnnaBridge 171:3a7713b1edbc 7709
AnnaBridge 171:3a7713b1edbc 7710 /*! @name PCOR - Port Clear Output Register */
AnnaBridge 171:3a7713b1edbc 7711 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 7712 #define GPIO_PCOR_PTCO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7713 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
AnnaBridge 171:3a7713b1edbc 7714
AnnaBridge 171:3a7713b1edbc 7715 /*! @name PTOR - Port Toggle Output Register */
AnnaBridge 171:3a7713b1edbc 7716 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 7717 #define GPIO_PTOR_PTTO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7718 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
AnnaBridge 171:3a7713b1edbc 7719
AnnaBridge 171:3a7713b1edbc 7720 /*! @name PDIR - Port Data Input Register */
AnnaBridge 171:3a7713b1edbc 7721 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 7722 #define GPIO_PDIR_PDI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7723 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
AnnaBridge 171:3a7713b1edbc 7724
AnnaBridge 171:3a7713b1edbc 7725 /*! @name PDDR - Port Data Direction Register */
AnnaBridge 171:3a7713b1edbc 7726 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 7727 #define GPIO_PDDR_PDD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7728 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
AnnaBridge 171:3a7713b1edbc 7729
AnnaBridge 171:3a7713b1edbc 7730
AnnaBridge 171:3a7713b1edbc 7731 /*!
AnnaBridge 171:3a7713b1edbc 7732 * @}
AnnaBridge 171:3a7713b1edbc 7733 */ /* end of group GPIO_Register_Masks */
AnnaBridge 171:3a7713b1edbc 7734
AnnaBridge 171:3a7713b1edbc 7735
AnnaBridge 171:3a7713b1edbc 7736 /* GPIO - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 7737 /** Peripheral GPIOA base address */
AnnaBridge 171:3a7713b1edbc 7738 #define GPIOA_BASE (0x400FF000u)
AnnaBridge 171:3a7713b1edbc 7739 /** Peripheral GPIOA base pointer */
AnnaBridge 171:3a7713b1edbc 7740 #define GPIOA ((GPIO_Type *)GPIOA_BASE)
AnnaBridge 171:3a7713b1edbc 7741 /** Peripheral GPIOB base address */
AnnaBridge 171:3a7713b1edbc 7742 #define GPIOB_BASE (0x400FF040u)
AnnaBridge 171:3a7713b1edbc 7743 /** Peripheral GPIOB base pointer */
AnnaBridge 171:3a7713b1edbc 7744 #define GPIOB ((GPIO_Type *)GPIOB_BASE)
AnnaBridge 171:3a7713b1edbc 7745 /** Peripheral GPIOC base address */
AnnaBridge 171:3a7713b1edbc 7746 #define GPIOC_BASE (0x400FF080u)
AnnaBridge 171:3a7713b1edbc 7747 /** Peripheral GPIOC base pointer */
AnnaBridge 171:3a7713b1edbc 7748 #define GPIOC ((GPIO_Type *)GPIOC_BASE)
AnnaBridge 171:3a7713b1edbc 7749 /** Peripheral GPIOD base address */
AnnaBridge 171:3a7713b1edbc 7750 #define GPIOD_BASE (0x400FF0C0u)
AnnaBridge 171:3a7713b1edbc 7751 /** Peripheral GPIOD base pointer */
AnnaBridge 171:3a7713b1edbc 7752 #define GPIOD ((GPIO_Type *)GPIOD_BASE)
AnnaBridge 171:3a7713b1edbc 7753 /** Peripheral GPIOE base address */
AnnaBridge 171:3a7713b1edbc 7754 #define GPIOE_BASE (0x400FF100u)
AnnaBridge 171:3a7713b1edbc 7755 /** Peripheral GPIOE base pointer */
AnnaBridge 171:3a7713b1edbc 7756 #define GPIOE ((GPIO_Type *)GPIOE_BASE)
AnnaBridge 171:3a7713b1edbc 7757 /** Array initializer of GPIO peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 7758 #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
AnnaBridge 171:3a7713b1edbc 7759 /** Array initializer of GPIO peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 7760 #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
AnnaBridge 171:3a7713b1edbc 7761
AnnaBridge 171:3a7713b1edbc 7762 /*!
AnnaBridge 171:3a7713b1edbc 7763 * @}
AnnaBridge 171:3a7713b1edbc 7764 */ /* end of group GPIO_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 7765
AnnaBridge 171:3a7713b1edbc 7766
AnnaBridge 171:3a7713b1edbc 7767 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7768 -- I2C Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7769 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7770
AnnaBridge 171:3a7713b1edbc 7771 /*!
AnnaBridge 171:3a7713b1edbc 7772 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7773 * @{
AnnaBridge 171:3a7713b1edbc 7774 */
AnnaBridge 171:3a7713b1edbc 7775
AnnaBridge 171:3a7713b1edbc 7776 /** I2C - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 7777 typedef struct {
AnnaBridge 171:3a7713b1edbc 7778 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 7779 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 7780 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 7781 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 7782 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 7783 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 7784 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 7785 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 7786 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 7787 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 7788 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 7789 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 7790 } I2C_Type;
AnnaBridge 171:3a7713b1edbc 7791
AnnaBridge 171:3a7713b1edbc 7792 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7793 -- I2C Register Masks
AnnaBridge 171:3a7713b1edbc 7794 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7795
AnnaBridge 171:3a7713b1edbc 7796 /*!
AnnaBridge 171:3a7713b1edbc 7797 * @addtogroup I2C_Register_Masks I2C Register Masks
AnnaBridge 171:3a7713b1edbc 7798 * @{
AnnaBridge 171:3a7713b1edbc 7799 */
AnnaBridge 171:3a7713b1edbc 7800
AnnaBridge 171:3a7713b1edbc 7801 /*! @name A1 - I2C Address Register 1 */
AnnaBridge 171:3a7713b1edbc 7802 #define I2C_A1_AD_MASK (0xFEU)
AnnaBridge 171:3a7713b1edbc 7803 #define I2C_A1_AD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7804 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
AnnaBridge 171:3a7713b1edbc 7805
AnnaBridge 171:3a7713b1edbc 7806 /*! @name F - I2C Frequency Divider register */
AnnaBridge 171:3a7713b1edbc 7807 #define I2C_F_ICR_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 7808 #define I2C_F_ICR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7809 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
AnnaBridge 171:3a7713b1edbc 7810 #define I2C_F_MULT_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 7811 #define I2C_F_MULT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7812 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
AnnaBridge 171:3a7713b1edbc 7813
AnnaBridge 171:3a7713b1edbc 7814 /*! @name C1 - I2C Control Register 1 */
AnnaBridge 171:3a7713b1edbc 7815 #define I2C_C1_DMAEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7816 #define I2C_C1_DMAEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7817 #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 7818 #define I2C_C1_WUEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7819 #define I2C_C1_WUEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7820 #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
AnnaBridge 171:3a7713b1edbc 7821 #define I2C_C1_RSTA_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7822 #define I2C_C1_RSTA_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7823 #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
AnnaBridge 171:3a7713b1edbc 7824 #define I2C_C1_TXAK_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7825 #define I2C_C1_TXAK_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7826 #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
AnnaBridge 171:3a7713b1edbc 7827 #define I2C_C1_TX_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7828 #define I2C_C1_TX_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7829 #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
AnnaBridge 171:3a7713b1edbc 7830 #define I2C_C1_MST_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7831 #define I2C_C1_MST_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7832 #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
AnnaBridge 171:3a7713b1edbc 7833 #define I2C_C1_IICIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7834 #define I2C_C1_IICIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7835 #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
AnnaBridge 171:3a7713b1edbc 7836 #define I2C_C1_IICEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7837 #define I2C_C1_IICEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7838 #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
AnnaBridge 171:3a7713b1edbc 7839
AnnaBridge 171:3a7713b1edbc 7840 /*! @name S - I2C Status register */
AnnaBridge 171:3a7713b1edbc 7841 #define I2C_S_RXAK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7842 #define I2C_S_RXAK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7843 #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
AnnaBridge 171:3a7713b1edbc 7844 #define I2C_S_IICIF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7845 #define I2C_S_IICIF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7846 #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
AnnaBridge 171:3a7713b1edbc 7847 #define I2C_S_SRW_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7848 #define I2C_S_SRW_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7849 #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
AnnaBridge 171:3a7713b1edbc 7850 #define I2C_S_RAM_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7851 #define I2C_S_RAM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7852 #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
AnnaBridge 171:3a7713b1edbc 7853 #define I2C_S_ARBL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7854 #define I2C_S_ARBL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7855 #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
AnnaBridge 171:3a7713b1edbc 7856 #define I2C_S_BUSY_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7857 #define I2C_S_BUSY_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7858 #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
AnnaBridge 171:3a7713b1edbc 7859 #define I2C_S_IAAS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7860 #define I2C_S_IAAS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7861 #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
AnnaBridge 171:3a7713b1edbc 7862 #define I2C_S_TCF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7863 #define I2C_S_TCF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7864 #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
AnnaBridge 171:3a7713b1edbc 7865
AnnaBridge 171:3a7713b1edbc 7866 /*! @name D - I2C Data I/O register */
AnnaBridge 171:3a7713b1edbc 7867 #define I2C_D_DATA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7868 #define I2C_D_DATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7869 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
AnnaBridge 171:3a7713b1edbc 7870
AnnaBridge 171:3a7713b1edbc 7871 /*! @name C2 - I2C Control Register 2 */
AnnaBridge 171:3a7713b1edbc 7872 #define I2C_C2_AD_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 7873 #define I2C_C2_AD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7874 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
AnnaBridge 171:3a7713b1edbc 7875 #define I2C_C2_RMEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7876 #define I2C_C2_RMEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7877 #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
AnnaBridge 171:3a7713b1edbc 7878 #define I2C_C2_SBRC_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7879 #define I2C_C2_SBRC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7880 #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
AnnaBridge 171:3a7713b1edbc 7881 #define I2C_C2_HDRS_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7882 #define I2C_C2_HDRS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7883 #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
AnnaBridge 171:3a7713b1edbc 7884 #define I2C_C2_ADEXT_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7885 #define I2C_C2_ADEXT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7886 #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
AnnaBridge 171:3a7713b1edbc 7887 #define I2C_C2_GCAEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7888 #define I2C_C2_GCAEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7889 #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
AnnaBridge 171:3a7713b1edbc 7890
AnnaBridge 171:3a7713b1edbc 7891 /*! @name FLT - I2C Programmable Input Glitch Filter Register */
AnnaBridge 171:3a7713b1edbc 7892 #define I2C_FLT_FLT_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 7893 #define I2C_FLT_FLT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7894 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
AnnaBridge 171:3a7713b1edbc 7895 #define I2C_FLT_STARTF_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7896 #define I2C_FLT_STARTF_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7897 #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
AnnaBridge 171:3a7713b1edbc 7898 #define I2C_FLT_SSIE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7899 #define I2C_FLT_SSIE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7900 #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
AnnaBridge 171:3a7713b1edbc 7901 #define I2C_FLT_STOPF_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7902 #define I2C_FLT_STOPF_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7903 #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
AnnaBridge 171:3a7713b1edbc 7904 #define I2C_FLT_SHEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7905 #define I2C_FLT_SHEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7906 #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
AnnaBridge 171:3a7713b1edbc 7907
AnnaBridge 171:3a7713b1edbc 7908 /*! @name RA - I2C Range Address register */
AnnaBridge 171:3a7713b1edbc 7909 #define I2C_RA_RAD_MASK (0xFEU)
AnnaBridge 171:3a7713b1edbc 7910 #define I2C_RA_RAD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7911 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
AnnaBridge 171:3a7713b1edbc 7912
AnnaBridge 171:3a7713b1edbc 7913 /*! @name SMB - I2C SMBus Control and Status register */
AnnaBridge 171:3a7713b1edbc 7914 #define I2C_SMB_SHTF2IE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7915 #define I2C_SMB_SHTF2IE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7916 #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
AnnaBridge 171:3a7713b1edbc 7917 #define I2C_SMB_SHTF2_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7918 #define I2C_SMB_SHTF2_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7919 #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
AnnaBridge 171:3a7713b1edbc 7920 #define I2C_SMB_SHTF1_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7921 #define I2C_SMB_SHTF1_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7922 #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
AnnaBridge 171:3a7713b1edbc 7923 #define I2C_SMB_SLTF_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7924 #define I2C_SMB_SLTF_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7925 #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
AnnaBridge 171:3a7713b1edbc 7926 #define I2C_SMB_TCKSEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7927 #define I2C_SMB_TCKSEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7928 #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 7929 #define I2C_SMB_SIICAEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7930 #define I2C_SMB_SIICAEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7931 #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
AnnaBridge 171:3a7713b1edbc 7932 #define I2C_SMB_ALERTEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7933 #define I2C_SMB_ALERTEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7934 #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
AnnaBridge 171:3a7713b1edbc 7935 #define I2C_SMB_FACK_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7936 #define I2C_SMB_FACK_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7937 #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
AnnaBridge 171:3a7713b1edbc 7938
AnnaBridge 171:3a7713b1edbc 7939 /*! @name A2 - I2C Address Register 2 */
AnnaBridge 171:3a7713b1edbc 7940 #define I2C_A2_SAD_MASK (0xFEU)
AnnaBridge 171:3a7713b1edbc 7941 #define I2C_A2_SAD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7942 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
AnnaBridge 171:3a7713b1edbc 7943
AnnaBridge 171:3a7713b1edbc 7944 /*! @name SLTH - I2C SCL Low Timeout Register High */
AnnaBridge 171:3a7713b1edbc 7945 #define I2C_SLTH_SSLT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7946 #define I2C_SLTH_SSLT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7947 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
AnnaBridge 171:3a7713b1edbc 7948
AnnaBridge 171:3a7713b1edbc 7949 /*! @name SLTL - I2C SCL Low Timeout Register Low */
AnnaBridge 171:3a7713b1edbc 7950 #define I2C_SLTL_SSLT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7951 #define I2C_SLTL_SSLT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7952 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
AnnaBridge 171:3a7713b1edbc 7953
AnnaBridge 171:3a7713b1edbc 7954
AnnaBridge 171:3a7713b1edbc 7955 /*!
AnnaBridge 171:3a7713b1edbc 7956 * @}
AnnaBridge 171:3a7713b1edbc 7957 */ /* end of group I2C_Register_Masks */
AnnaBridge 171:3a7713b1edbc 7958
AnnaBridge 171:3a7713b1edbc 7959
AnnaBridge 171:3a7713b1edbc 7960 /* I2C - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 7961 /** Peripheral I2C0 base address */
AnnaBridge 171:3a7713b1edbc 7962 #define I2C0_BASE (0x40066000u)
AnnaBridge 171:3a7713b1edbc 7963 /** Peripheral I2C0 base pointer */
AnnaBridge 171:3a7713b1edbc 7964 #define I2C0 ((I2C_Type *)I2C0_BASE)
AnnaBridge 171:3a7713b1edbc 7965 /** Peripheral I2C1 base address */
AnnaBridge 171:3a7713b1edbc 7966 #define I2C1_BASE (0x40067000u)
AnnaBridge 171:3a7713b1edbc 7967 /** Peripheral I2C1 base pointer */
AnnaBridge 171:3a7713b1edbc 7968 #define I2C1 ((I2C_Type *)I2C1_BASE)
AnnaBridge 171:3a7713b1edbc 7969 /** Peripheral I2C2 base address */
AnnaBridge 171:3a7713b1edbc 7970 #define I2C2_BASE (0x400E6000u)
AnnaBridge 171:3a7713b1edbc 7971 /** Peripheral I2C2 base pointer */
AnnaBridge 171:3a7713b1edbc 7972 #define I2C2 ((I2C_Type *)I2C2_BASE)
AnnaBridge 171:3a7713b1edbc 7973 /** Peripheral I2C3 base address */
AnnaBridge 171:3a7713b1edbc 7974 #define I2C3_BASE (0x400E7000u)
AnnaBridge 171:3a7713b1edbc 7975 /** Peripheral I2C3 base pointer */
AnnaBridge 171:3a7713b1edbc 7976 #define I2C3 ((I2C_Type *)I2C3_BASE)
AnnaBridge 171:3a7713b1edbc 7977 /** Array initializer of I2C peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 7978 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE }
AnnaBridge 171:3a7713b1edbc 7979 /** Array initializer of I2C peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 7980 #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3 }
AnnaBridge 171:3a7713b1edbc 7981 /** Interrupt vectors for the I2C peripheral type */
AnnaBridge 171:3a7713b1edbc 7982 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn }
AnnaBridge 171:3a7713b1edbc 7983
AnnaBridge 171:3a7713b1edbc 7984 /*!
AnnaBridge 171:3a7713b1edbc 7985 * @}
AnnaBridge 171:3a7713b1edbc 7986 */ /* end of group I2C_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 7987
AnnaBridge 171:3a7713b1edbc 7988
AnnaBridge 171:3a7713b1edbc 7989 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7990 -- I2S Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7991 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7992
AnnaBridge 171:3a7713b1edbc 7993 /*!
AnnaBridge 171:3a7713b1edbc 7994 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7995 * @{
AnnaBridge 171:3a7713b1edbc 7996 */
AnnaBridge 171:3a7713b1edbc 7997
AnnaBridge 171:3a7713b1edbc 7998 /** I2S - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 7999 typedef struct {
AnnaBridge 171:3a7713b1edbc 8000 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 8001 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 8002 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 8003 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 8004 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 8005 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 8006 uint8_t RESERVED_0[8];
AnnaBridge 171:3a7713b1edbc 8007 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 8008 uint8_t RESERVED_1[24];
AnnaBridge 171:3a7713b1edbc 8009 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 8010 uint8_t RESERVED_2[24];
AnnaBridge 171:3a7713b1edbc 8011 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 8012 uint8_t RESERVED_3[28];
AnnaBridge 171:3a7713b1edbc 8013 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 8014 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 8015 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 8016 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 8017 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 8018 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 8019 uint8_t RESERVED_4[8];
AnnaBridge 171:3a7713b1edbc 8020 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 8021 uint8_t RESERVED_5[24];
AnnaBridge 171:3a7713b1edbc 8022 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 8023 uint8_t RESERVED_6[24];
AnnaBridge 171:3a7713b1edbc 8024 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
AnnaBridge 171:3a7713b1edbc 8025 uint8_t RESERVED_7[28];
AnnaBridge 171:3a7713b1edbc 8026 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
AnnaBridge 171:3a7713b1edbc 8027 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
AnnaBridge 171:3a7713b1edbc 8028 } I2S_Type;
AnnaBridge 171:3a7713b1edbc 8029
AnnaBridge 171:3a7713b1edbc 8030 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8031 -- I2S Register Masks
AnnaBridge 171:3a7713b1edbc 8032 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8033
AnnaBridge 171:3a7713b1edbc 8034 /*!
AnnaBridge 171:3a7713b1edbc 8035 * @addtogroup I2S_Register_Masks I2S Register Masks
AnnaBridge 171:3a7713b1edbc 8036 * @{
AnnaBridge 171:3a7713b1edbc 8037 */
AnnaBridge 171:3a7713b1edbc 8038
AnnaBridge 171:3a7713b1edbc 8039 /*! @name TCSR - SAI Transmit Control Register */
AnnaBridge 171:3a7713b1edbc 8040 #define I2S_TCSR_FRDE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8041 #define I2S_TCSR_FRDE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8042 #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
AnnaBridge 171:3a7713b1edbc 8043 #define I2S_TCSR_FWDE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8044 #define I2S_TCSR_FWDE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8045 #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
AnnaBridge 171:3a7713b1edbc 8046 #define I2S_TCSR_FRIE_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 8047 #define I2S_TCSR_FRIE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8048 #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
AnnaBridge 171:3a7713b1edbc 8049 #define I2S_TCSR_FWIE_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 8050 #define I2S_TCSR_FWIE_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 8051 #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
AnnaBridge 171:3a7713b1edbc 8052 #define I2S_TCSR_FEIE_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 8053 #define I2S_TCSR_FEIE_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 8054 #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
AnnaBridge 171:3a7713b1edbc 8055 #define I2S_TCSR_SEIE_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 8056 #define I2S_TCSR_SEIE_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 8057 #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
AnnaBridge 171:3a7713b1edbc 8058 #define I2S_TCSR_WSIE_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 8059 #define I2S_TCSR_WSIE_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 8060 #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
AnnaBridge 171:3a7713b1edbc 8061 #define I2S_TCSR_FRF_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 8062 #define I2S_TCSR_FRF_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8063 #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
AnnaBridge 171:3a7713b1edbc 8064 #define I2S_TCSR_FWF_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 8065 #define I2S_TCSR_FWF_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 8066 #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
AnnaBridge 171:3a7713b1edbc 8067 #define I2S_TCSR_FEF_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 8068 #define I2S_TCSR_FEF_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 8069 #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
AnnaBridge 171:3a7713b1edbc 8070 #define I2S_TCSR_SEF_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 8071 #define I2S_TCSR_SEF_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 8072 #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
AnnaBridge 171:3a7713b1edbc 8073 #define I2S_TCSR_WSF_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 8074 #define I2S_TCSR_WSF_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 8075 #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
AnnaBridge 171:3a7713b1edbc 8076 #define I2S_TCSR_SR_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 8077 #define I2S_TCSR_SR_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8078 #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
AnnaBridge 171:3a7713b1edbc 8079 #define I2S_TCSR_FR_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 8080 #define I2S_TCSR_FR_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 8081 #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
AnnaBridge 171:3a7713b1edbc 8082 #define I2S_TCSR_BCE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 8083 #define I2S_TCSR_BCE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 8084 #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
AnnaBridge 171:3a7713b1edbc 8085 #define I2S_TCSR_DBGE_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 8086 #define I2S_TCSR_DBGE_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 8087 #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
AnnaBridge 171:3a7713b1edbc 8088 #define I2S_TCSR_STOPE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 8089 #define I2S_TCSR_STOPE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 8090 #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
AnnaBridge 171:3a7713b1edbc 8091 #define I2S_TCSR_TE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 8092 #define I2S_TCSR_TE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 8093 #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
AnnaBridge 171:3a7713b1edbc 8094
AnnaBridge 171:3a7713b1edbc 8095 /*! @name TCR1 - SAI Transmit Configuration 1 Register */
AnnaBridge 171:3a7713b1edbc 8096 #define I2S_TCR1_TFW_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 8097 #define I2S_TCR1_TFW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8098 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
AnnaBridge 171:3a7713b1edbc 8099
AnnaBridge 171:3a7713b1edbc 8100 /*! @name TCR2 - SAI Transmit Configuration 2 Register */
AnnaBridge 171:3a7713b1edbc 8101 #define I2S_TCR2_DIV_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8102 #define I2S_TCR2_DIV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8103 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
AnnaBridge 171:3a7713b1edbc 8104 #define I2S_TCR2_BCD_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 8105 #define I2S_TCR2_BCD_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8106 #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
AnnaBridge 171:3a7713b1edbc 8107 #define I2S_TCR2_BCP_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 8108 #define I2S_TCR2_BCP_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 8109 #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
AnnaBridge 171:3a7713b1edbc 8110 #define I2S_TCR2_MSEL_MASK (0xC000000U)
AnnaBridge 171:3a7713b1edbc 8111 #define I2S_TCR2_MSEL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 8112 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8113 #define I2S_TCR2_BCI_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 8114 #define I2S_TCR2_BCI_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 8115 #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
AnnaBridge 171:3a7713b1edbc 8116 #define I2S_TCR2_BCS_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 8117 #define I2S_TCR2_BCS_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 8118 #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
AnnaBridge 171:3a7713b1edbc 8119 #define I2S_TCR2_SYNC_MASK (0xC0000000U)
AnnaBridge 171:3a7713b1edbc 8120 #define I2S_TCR2_SYNC_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 8121 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
AnnaBridge 171:3a7713b1edbc 8122
AnnaBridge 171:3a7713b1edbc 8123 /*! @name TCR3 - SAI Transmit Configuration 3 Register */
AnnaBridge 171:3a7713b1edbc 8124 #define I2S_TCR3_WDFL_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 8125 #define I2S_TCR3_WDFL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8126 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
AnnaBridge 171:3a7713b1edbc 8127 #define I2S_TCR3_TCE_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 8128 #define I2S_TCR3_TCE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8129 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
AnnaBridge 171:3a7713b1edbc 8130 #define I2S_TCR3_CFR_MASK (0x3000000U)
AnnaBridge 171:3a7713b1edbc 8131 #define I2S_TCR3_CFR_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8132 #define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
AnnaBridge 171:3a7713b1edbc 8133
AnnaBridge 171:3a7713b1edbc 8134 /*! @name TCR4 - SAI Transmit Configuration 4 Register */
AnnaBridge 171:3a7713b1edbc 8135 #define I2S_TCR4_FSD_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8136 #define I2S_TCR4_FSD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8137 #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
AnnaBridge 171:3a7713b1edbc 8138 #define I2S_TCR4_FSP_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8139 #define I2S_TCR4_FSP_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8140 #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
AnnaBridge 171:3a7713b1edbc 8141 #define I2S_TCR4_ONDEM_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 8142 #define I2S_TCR4_ONDEM_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8143 #define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
AnnaBridge 171:3a7713b1edbc 8144 #define I2S_TCR4_FSE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8145 #define I2S_TCR4_FSE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8146 #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
AnnaBridge 171:3a7713b1edbc 8147 #define I2S_TCR4_MF_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8148 #define I2S_TCR4_MF_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8149 #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
AnnaBridge 171:3a7713b1edbc 8150 #define I2S_TCR4_SYWD_MASK (0x1F00U)
AnnaBridge 171:3a7713b1edbc 8151 #define I2S_TCR4_SYWD_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8152 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
AnnaBridge 171:3a7713b1edbc 8153 #define I2S_TCR4_FRSZ_MASK (0x1F0000U)
AnnaBridge 171:3a7713b1edbc 8154 #define I2S_TCR4_FRSZ_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8155 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
AnnaBridge 171:3a7713b1edbc 8156 #define I2S_TCR4_FPACK_MASK (0x3000000U)
AnnaBridge 171:3a7713b1edbc 8157 #define I2S_TCR4_FPACK_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8158 #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
AnnaBridge 171:3a7713b1edbc 8159 #define I2S_TCR4_FCOMB_MASK (0xC000000U)
AnnaBridge 171:3a7713b1edbc 8160 #define I2S_TCR4_FCOMB_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 8161 #define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
AnnaBridge 171:3a7713b1edbc 8162 #define I2S_TCR4_FCONT_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 8163 #define I2S_TCR4_FCONT_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 8164 #define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
AnnaBridge 171:3a7713b1edbc 8165
AnnaBridge 171:3a7713b1edbc 8166 /*! @name TCR5 - SAI Transmit Configuration 5 Register */
AnnaBridge 171:3a7713b1edbc 8167 #define I2S_TCR5_FBT_MASK (0x1F00U)
AnnaBridge 171:3a7713b1edbc 8168 #define I2S_TCR5_FBT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8169 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
AnnaBridge 171:3a7713b1edbc 8170 #define I2S_TCR5_W0W_MASK (0x1F0000U)
AnnaBridge 171:3a7713b1edbc 8171 #define I2S_TCR5_W0W_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8172 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
AnnaBridge 171:3a7713b1edbc 8173 #define I2S_TCR5_WNW_MASK (0x1F000000U)
AnnaBridge 171:3a7713b1edbc 8174 #define I2S_TCR5_WNW_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8175 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
AnnaBridge 171:3a7713b1edbc 8176
AnnaBridge 171:3a7713b1edbc 8177 /*! @name TDR - SAI Transmit Data Register */
AnnaBridge 171:3a7713b1edbc 8178 #define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 8179 #define I2S_TDR_TDR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8180 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
AnnaBridge 171:3a7713b1edbc 8181
AnnaBridge 171:3a7713b1edbc 8182 /* The count of I2S_TDR */
AnnaBridge 171:3a7713b1edbc 8183 #define I2S_TDR_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 8184
AnnaBridge 171:3a7713b1edbc 8185 /*! @name TFR - SAI Transmit FIFO Register */
AnnaBridge 171:3a7713b1edbc 8186 #define I2S_TFR_RFP_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 8187 #define I2S_TFR_RFP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8188 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
AnnaBridge 171:3a7713b1edbc 8189 #define I2S_TFR_WFP_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 8190 #define I2S_TFR_WFP_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8191 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
AnnaBridge 171:3a7713b1edbc 8192 #define I2S_TFR_WCP_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 8193 #define I2S_TFR_WCP_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 8194 #define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
AnnaBridge 171:3a7713b1edbc 8195
AnnaBridge 171:3a7713b1edbc 8196 /* The count of I2S_TFR */
AnnaBridge 171:3a7713b1edbc 8197 #define I2S_TFR_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 8198
AnnaBridge 171:3a7713b1edbc 8199 /*! @name TMR - SAI Transmit Mask Register */
AnnaBridge 171:3a7713b1edbc 8200 #define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 8201 #define I2S_TMR_TWM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8202 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
AnnaBridge 171:3a7713b1edbc 8203
AnnaBridge 171:3a7713b1edbc 8204 /*! @name RCSR - SAI Receive Control Register */
AnnaBridge 171:3a7713b1edbc 8205 #define I2S_RCSR_FRDE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8206 #define I2S_RCSR_FRDE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8207 #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
AnnaBridge 171:3a7713b1edbc 8208 #define I2S_RCSR_FWDE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8209 #define I2S_RCSR_FWDE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8210 #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
AnnaBridge 171:3a7713b1edbc 8211 #define I2S_RCSR_FRIE_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 8212 #define I2S_RCSR_FRIE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8213 #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
AnnaBridge 171:3a7713b1edbc 8214 #define I2S_RCSR_FWIE_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 8215 #define I2S_RCSR_FWIE_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 8216 #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
AnnaBridge 171:3a7713b1edbc 8217 #define I2S_RCSR_FEIE_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 8218 #define I2S_RCSR_FEIE_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 8219 #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
AnnaBridge 171:3a7713b1edbc 8220 #define I2S_RCSR_SEIE_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 8221 #define I2S_RCSR_SEIE_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 8222 #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
AnnaBridge 171:3a7713b1edbc 8223 #define I2S_RCSR_WSIE_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 8224 #define I2S_RCSR_WSIE_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 8225 #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
AnnaBridge 171:3a7713b1edbc 8226 #define I2S_RCSR_FRF_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 8227 #define I2S_RCSR_FRF_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8228 #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
AnnaBridge 171:3a7713b1edbc 8229 #define I2S_RCSR_FWF_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 8230 #define I2S_RCSR_FWF_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 8231 #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
AnnaBridge 171:3a7713b1edbc 8232 #define I2S_RCSR_FEF_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 8233 #define I2S_RCSR_FEF_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 8234 #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
AnnaBridge 171:3a7713b1edbc 8235 #define I2S_RCSR_SEF_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 8236 #define I2S_RCSR_SEF_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 8237 #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
AnnaBridge 171:3a7713b1edbc 8238 #define I2S_RCSR_WSF_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 8239 #define I2S_RCSR_WSF_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 8240 #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
AnnaBridge 171:3a7713b1edbc 8241 #define I2S_RCSR_SR_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 8242 #define I2S_RCSR_SR_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8243 #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
AnnaBridge 171:3a7713b1edbc 8244 #define I2S_RCSR_FR_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 8245 #define I2S_RCSR_FR_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 8246 #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
AnnaBridge 171:3a7713b1edbc 8247 #define I2S_RCSR_BCE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 8248 #define I2S_RCSR_BCE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 8249 #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
AnnaBridge 171:3a7713b1edbc 8250 #define I2S_RCSR_DBGE_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 8251 #define I2S_RCSR_DBGE_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 8252 #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
AnnaBridge 171:3a7713b1edbc 8253 #define I2S_RCSR_STOPE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 8254 #define I2S_RCSR_STOPE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 8255 #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
AnnaBridge 171:3a7713b1edbc 8256 #define I2S_RCSR_RE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 8257 #define I2S_RCSR_RE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 8258 #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
AnnaBridge 171:3a7713b1edbc 8259
AnnaBridge 171:3a7713b1edbc 8260 /*! @name RCR1 - SAI Receive Configuration 1 Register */
AnnaBridge 171:3a7713b1edbc 8261 #define I2S_RCR1_RFW_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 8262 #define I2S_RCR1_RFW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8263 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
AnnaBridge 171:3a7713b1edbc 8264
AnnaBridge 171:3a7713b1edbc 8265 /*! @name RCR2 - SAI Receive Configuration 2 Register */
AnnaBridge 171:3a7713b1edbc 8266 #define I2S_RCR2_DIV_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8267 #define I2S_RCR2_DIV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8268 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
AnnaBridge 171:3a7713b1edbc 8269 #define I2S_RCR2_BCD_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 8270 #define I2S_RCR2_BCD_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8271 #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
AnnaBridge 171:3a7713b1edbc 8272 #define I2S_RCR2_BCP_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 8273 #define I2S_RCR2_BCP_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 8274 #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
AnnaBridge 171:3a7713b1edbc 8275 #define I2S_RCR2_MSEL_MASK (0xC000000U)
AnnaBridge 171:3a7713b1edbc 8276 #define I2S_RCR2_MSEL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 8277 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8278 #define I2S_RCR2_BCI_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 8279 #define I2S_RCR2_BCI_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 8280 #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
AnnaBridge 171:3a7713b1edbc 8281 #define I2S_RCR2_BCS_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 8282 #define I2S_RCR2_BCS_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 8283 #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
AnnaBridge 171:3a7713b1edbc 8284 #define I2S_RCR2_SYNC_MASK (0xC0000000U)
AnnaBridge 171:3a7713b1edbc 8285 #define I2S_RCR2_SYNC_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 8286 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
AnnaBridge 171:3a7713b1edbc 8287
AnnaBridge 171:3a7713b1edbc 8288 /*! @name RCR3 - SAI Receive Configuration 3 Register */
AnnaBridge 171:3a7713b1edbc 8289 #define I2S_RCR3_WDFL_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 8290 #define I2S_RCR3_WDFL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8291 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
AnnaBridge 171:3a7713b1edbc 8292 #define I2S_RCR3_RCE_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 8293 #define I2S_RCR3_RCE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8294 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
AnnaBridge 171:3a7713b1edbc 8295 #define I2S_RCR3_CFR_MASK (0x3000000U)
AnnaBridge 171:3a7713b1edbc 8296 #define I2S_RCR3_CFR_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8297 #define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
AnnaBridge 171:3a7713b1edbc 8298
AnnaBridge 171:3a7713b1edbc 8299 /*! @name RCR4 - SAI Receive Configuration 4 Register */
AnnaBridge 171:3a7713b1edbc 8300 #define I2S_RCR4_FSD_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8301 #define I2S_RCR4_FSD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8302 #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
AnnaBridge 171:3a7713b1edbc 8303 #define I2S_RCR4_FSP_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8304 #define I2S_RCR4_FSP_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8305 #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
AnnaBridge 171:3a7713b1edbc 8306 #define I2S_RCR4_ONDEM_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 8307 #define I2S_RCR4_ONDEM_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8308 #define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
AnnaBridge 171:3a7713b1edbc 8309 #define I2S_RCR4_FSE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8310 #define I2S_RCR4_FSE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8311 #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
AnnaBridge 171:3a7713b1edbc 8312 #define I2S_RCR4_MF_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8313 #define I2S_RCR4_MF_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8314 #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
AnnaBridge 171:3a7713b1edbc 8315 #define I2S_RCR4_SYWD_MASK (0x1F00U)
AnnaBridge 171:3a7713b1edbc 8316 #define I2S_RCR4_SYWD_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8317 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
AnnaBridge 171:3a7713b1edbc 8318 #define I2S_RCR4_FRSZ_MASK (0x1F0000U)
AnnaBridge 171:3a7713b1edbc 8319 #define I2S_RCR4_FRSZ_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8320 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
AnnaBridge 171:3a7713b1edbc 8321 #define I2S_RCR4_FPACK_MASK (0x3000000U)
AnnaBridge 171:3a7713b1edbc 8322 #define I2S_RCR4_FPACK_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8323 #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
AnnaBridge 171:3a7713b1edbc 8324 #define I2S_RCR4_FCOMB_MASK (0xC000000U)
AnnaBridge 171:3a7713b1edbc 8325 #define I2S_RCR4_FCOMB_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 8326 #define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
AnnaBridge 171:3a7713b1edbc 8327 #define I2S_RCR4_FCONT_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 8328 #define I2S_RCR4_FCONT_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 8329 #define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
AnnaBridge 171:3a7713b1edbc 8330
AnnaBridge 171:3a7713b1edbc 8331 /*! @name RCR5 - SAI Receive Configuration 5 Register */
AnnaBridge 171:3a7713b1edbc 8332 #define I2S_RCR5_FBT_MASK (0x1F00U)
AnnaBridge 171:3a7713b1edbc 8333 #define I2S_RCR5_FBT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8334 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
AnnaBridge 171:3a7713b1edbc 8335 #define I2S_RCR5_W0W_MASK (0x1F0000U)
AnnaBridge 171:3a7713b1edbc 8336 #define I2S_RCR5_W0W_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8337 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
AnnaBridge 171:3a7713b1edbc 8338 #define I2S_RCR5_WNW_MASK (0x1F000000U)
AnnaBridge 171:3a7713b1edbc 8339 #define I2S_RCR5_WNW_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8340 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
AnnaBridge 171:3a7713b1edbc 8341
AnnaBridge 171:3a7713b1edbc 8342 /*! @name RDR - SAI Receive Data Register */
AnnaBridge 171:3a7713b1edbc 8343 #define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 8344 #define I2S_RDR_RDR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8345 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
AnnaBridge 171:3a7713b1edbc 8346
AnnaBridge 171:3a7713b1edbc 8347 /* The count of I2S_RDR */
AnnaBridge 171:3a7713b1edbc 8348 #define I2S_RDR_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 8349
AnnaBridge 171:3a7713b1edbc 8350 /*! @name RFR - SAI Receive FIFO Register */
AnnaBridge 171:3a7713b1edbc 8351 #define I2S_RFR_RFP_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 8352 #define I2S_RFR_RFP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8353 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
AnnaBridge 171:3a7713b1edbc 8354 #define I2S_RFR_RCP_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 8355 #define I2S_RFR_RCP_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 8356 #define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
AnnaBridge 171:3a7713b1edbc 8357 #define I2S_RFR_WFP_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 8358 #define I2S_RFR_WFP_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8359 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
AnnaBridge 171:3a7713b1edbc 8360
AnnaBridge 171:3a7713b1edbc 8361 /* The count of I2S_RFR */
AnnaBridge 171:3a7713b1edbc 8362 #define I2S_RFR_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 8363
AnnaBridge 171:3a7713b1edbc 8364 /*! @name RMR - SAI Receive Mask Register */
AnnaBridge 171:3a7713b1edbc 8365 #define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 8366 #define I2S_RMR_RWM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8367 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
AnnaBridge 171:3a7713b1edbc 8368
AnnaBridge 171:3a7713b1edbc 8369 /*! @name MCR - SAI MCLK Control Register */
AnnaBridge 171:3a7713b1edbc 8370 #define I2S_MCR_MICS_MASK (0x3000000U)
AnnaBridge 171:3a7713b1edbc 8371 #define I2S_MCR_MICS_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8372 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
AnnaBridge 171:3a7713b1edbc 8373 #define I2S_MCR_MOE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 8374 #define I2S_MCR_MOE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 8375 #define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
AnnaBridge 171:3a7713b1edbc 8376 #define I2S_MCR_DUF_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 8377 #define I2S_MCR_DUF_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 8378 #define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
AnnaBridge 171:3a7713b1edbc 8379
AnnaBridge 171:3a7713b1edbc 8380 /*! @name MDR - SAI MCLK Divide Register */
AnnaBridge 171:3a7713b1edbc 8381 #define I2S_MDR_DIVIDE_MASK (0xFFFU)
AnnaBridge 171:3a7713b1edbc 8382 #define I2S_MDR_DIVIDE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8383 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
AnnaBridge 171:3a7713b1edbc 8384 #define I2S_MDR_FRACT_MASK (0xFF000U)
AnnaBridge 171:3a7713b1edbc 8385 #define I2S_MDR_FRACT_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 8386 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
AnnaBridge 171:3a7713b1edbc 8387
AnnaBridge 171:3a7713b1edbc 8388
AnnaBridge 171:3a7713b1edbc 8389 /*!
AnnaBridge 171:3a7713b1edbc 8390 * @}
AnnaBridge 171:3a7713b1edbc 8391 */ /* end of group I2S_Register_Masks */
AnnaBridge 171:3a7713b1edbc 8392
AnnaBridge 171:3a7713b1edbc 8393
AnnaBridge 171:3a7713b1edbc 8394 /* I2S - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 8395 /** Peripheral I2S0 base address */
AnnaBridge 171:3a7713b1edbc 8396 #define I2S0_BASE (0x4002F000u)
AnnaBridge 171:3a7713b1edbc 8397 /** Peripheral I2S0 base pointer */
AnnaBridge 171:3a7713b1edbc 8398 #define I2S0 ((I2S_Type *)I2S0_BASE)
AnnaBridge 171:3a7713b1edbc 8399 /** Array initializer of I2S peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 8400 #define I2S_BASE_ADDRS { I2S0_BASE }
AnnaBridge 171:3a7713b1edbc 8401 /** Array initializer of I2S peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 8402 #define I2S_BASE_PTRS { I2S0 }
AnnaBridge 171:3a7713b1edbc 8403 /** Interrupt vectors for the I2S peripheral type */
AnnaBridge 171:3a7713b1edbc 8404 #define I2S_RX_IRQS { I2S0_Rx_IRQn }
AnnaBridge 171:3a7713b1edbc 8405 #define I2S_TX_IRQS { I2S0_Tx_IRQn }
AnnaBridge 171:3a7713b1edbc 8406
AnnaBridge 171:3a7713b1edbc 8407 /*!
AnnaBridge 171:3a7713b1edbc 8408 * @}
AnnaBridge 171:3a7713b1edbc 8409 */ /* end of group I2S_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 8410
AnnaBridge 171:3a7713b1edbc 8411
AnnaBridge 171:3a7713b1edbc 8412 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8413 -- LLWU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8414 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8415
AnnaBridge 171:3a7713b1edbc 8416 /*!
AnnaBridge 171:3a7713b1edbc 8417 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8418 * @{
AnnaBridge 171:3a7713b1edbc 8419 */
AnnaBridge 171:3a7713b1edbc 8420
AnnaBridge 171:3a7713b1edbc 8421 /** LLWU - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 8422 typedef struct {
AnnaBridge 171:3a7713b1edbc 8423 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 8424 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 8425 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 8426 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 8427 __IO uint8_t PE5; /**< LLWU Pin Enable 5 register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 8428 __IO uint8_t PE6; /**< LLWU Pin Enable 6 register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 8429 __IO uint8_t PE7; /**< LLWU Pin Enable 7 register, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 8430 __IO uint8_t PE8; /**< LLWU Pin Enable 8 register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 8431 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 8432 __IO uint8_t PF1; /**< LLWU Pin Flag 1 register, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 8433 __IO uint8_t PF2; /**< LLWU Pin Flag 2 register, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 8434 __IO uint8_t PF3; /**< LLWU Pin Flag 3 register, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 8435 __IO uint8_t PF4; /**< LLWU Pin Flag 4 register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 8436 __I uint8_t MF5; /**< LLWU Module Flag 5 register, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 8437 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0xE */
AnnaBridge 171:3a7713b1edbc 8438 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0xF */
AnnaBridge 171:3a7713b1edbc 8439 __IO uint8_t FILT3; /**< LLWU Pin Filter 3 register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 8440 __IO uint8_t FILT4; /**< LLWU Pin Filter 4 register, offset: 0x11 */
AnnaBridge 171:3a7713b1edbc 8441 } LLWU_Type;
AnnaBridge 171:3a7713b1edbc 8442
AnnaBridge 171:3a7713b1edbc 8443 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8444 -- LLWU Register Masks
AnnaBridge 171:3a7713b1edbc 8445 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8446
AnnaBridge 171:3a7713b1edbc 8447 /*!
AnnaBridge 171:3a7713b1edbc 8448 * @addtogroup LLWU_Register_Masks LLWU Register Masks
AnnaBridge 171:3a7713b1edbc 8449 * @{
AnnaBridge 171:3a7713b1edbc 8450 */
AnnaBridge 171:3a7713b1edbc 8451
AnnaBridge 171:3a7713b1edbc 8452 /*! @name PE1 - LLWU Pin Enable 1 register */
AnnaBridge 171:3a7713b1edbc 8453 #define LLWU_PE1_WUPE0_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 8454 #define LLWU_PE1_WUPE0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8455 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
AnnaBridge 171:3a7713b1edbc 8456 #define LLWU_PE1_WUPE1_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 8457 #define LLWU_PE1_WUPE1_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8458 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
AnnaBridge 171:3a7713b1edbc 8459 #define LLWU_PE1_WUPE2_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 8460 #define LLWU_PE1_WUPE2_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8461 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
AnnaBridge 171:3a7713b1edbc 8462 #define LLWU_PE1_WUPE3_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 8463 #define LLWU_PE1_WUPE3_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8464 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
AnnaBridge 171:3a7713b1edbc 8465
AnnaBridge 171:3a7713b1edbc 8466 /*! @name PE2 - LLWU Pin Enable 2 register */
AnnaBridge 171:3a7713b1edbc 8467 #define LLWU_PE2_WUPE4_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 8468 #define LLWU_PE2_WUPE4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8469 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
AnnaBridge 171:3a7713b1edbc 8470 #define LLWU_PE2_WUPE5_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 8471 #define LLWU_PE2_WUPE5_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8472 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
AnnaBridge 171:3a7713b1edbc 8473 #define LLWU_PE2_WUPE6_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 8474 #define LLWU_PE2_WUPE6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8475 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
AnnaBridge 171:3a7713b1edbc 8476 #define LLWU_PE2_WUPE7_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 8477 #define LLWU_PE2_WUPE7_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8478 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
AnnaBridge 171:3a7713b1edbc 8479
AnnaBridge 171:3a7713b1edbc 8480 /*! @name PE3 - LLWU Pin Enable 3 register */
AnnaBridge 171:3a7713b1edbc 8481 #define LLWU_PE3_WUPE8_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 8482 #define LLWU_PE3_WUPE8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8483 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
AnnaBridge 171:3a7713b1edbc 8484 #define LLWU_PE3_WUPE9_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 8485 #define LLWU_PE3_WUPE9_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8486 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
AnnaBridge 171:3a7713b1edbc 8487 #define LLWU_PE3_WUPE10_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 8488 #define LLWU_PE3_WUPE10_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8489 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
AnnaBridge 171:3a7713b1edbc 8490 #define LLWU_PE3_WUPE11_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 8491 #define LLWU_PE3_WUPE11_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8492 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
AnnaBridge 171:3a7713b1edbc 8493
AnnaBridge 171:3a7713b1edbc 8494 /*! @name PE4 - LLWU Pin Enable 4 register */
AnnaBridge 171:3a7713b1edbc 8495 #define LLWU_PE4_WUPE12_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 8496 #define LLWU_PE4_WUPE12_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8497 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
AnnaBridge 171:3a7713b1edbc 8498 #define LLWU_PE4_WUPE13_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 8499 #define LLWU_PE4_WUPE13_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8500 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
AnnaBridge 171:3a7713b1edbc 8501 #define LLWU_PE4_WUPE14_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 8502 #define LLWU_PE4_WUPE14_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8503 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
AnnaBridge 171:3a7713b1edbc 8504 #define LLWU_PE4_WUPE15_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 8505 #define LLWU_PE4_WUPE15_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8506 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
AnnaBridge 171:3a7713b1edbc 8507
AnnaBridge 171:3a7713b1edbc 8508 /*! @name PE5 - LLWU Pin Enable 5 register */
AnnaBridge 171:3a7713b1edbc 8509 #define LLWU_PE5_WUPE16_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 8510 #define LLWU_PE5_WUPE16_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8511 #define LLWU_PE5_WUPE16(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE16_SHIFT)) & LLWU_PE5_WUPE16_MASK)
AnnaBridge 171:3a7713b1edbc 8512 #define LLWU_PE5_WUPE17_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 8513 #define LLWU_PE5_WUPE17_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8514 #define LLWU_PE5_WUPE17(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE17_SHIFT)) & LLWU_PE5_WUPE17_MASK)
AnnaBridge 171:3a7713b1edbc 8515 #define LLWU_PE5_WUPE18_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 8516 #define LLWU_PE5_WUPE18_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8517 #define LLWU_PE5_WUPE18(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE18_SHIFT)) & LLWU_PE5_WUPE18_MASK)
AnnaBridge 171:3a7713b1edbc 8518 #define LLWU_PE5_WUPE19_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 8519 #define LLWU_PE5_WUPE19_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8520 #define LLWU_PE5_WUPE19(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE19_SHIFT)) & LLWU_PE5_WUPE19_MASK)
AnnaBridge 171:3a7713b1edbc 8521
AnnaBridge 171:3a7713b1edbc 8522 /*! @name PE6 - LLWU Pin Enable 6 register */
AnnaBridge 171:3a7713b1edbc 8523 #define LLWU_PE6_WUPE20_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 8524 #define LLWU_PE6_WUPE20_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8525 #define LLWU_PE6_WUPE20(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE20_SHIFT)) & LLWU_PE6_WUPE20_MASK)
AnnaBridge 171:3a7713b1edbc 8526 #define LLWU_PE6_WUPE21_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 8527 #define LLWU_PE6_WUPE21_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8528 #define LLWU_PE6_WUPE21(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE21_SHIFT)) & LLWU_PE6_WUPE21_MASK)
AnnaBridge 171:3a7713b1edbc 8529 #define LLWU_PE6_WUPE22_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 8530 #define LLWU_PE6_WUPE22_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8531 #define LLWU_PE6_WUPE22(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE22_SHIFT)) & LLWU_PE6_WUPE22_MASK)
AnnaBridge 171:3a7713b1edbc 8532 #define LLWU_PE6_WUPE23_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 8533 #define LLWU_PE6_WUPE23_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8534 #define LLWU_PE6_WUPE23(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE23_SHIFT)) & LLWU_PE6_WUPE23_MASK)
AnnaBridge 171:3a7713b1edbc 8535
AnnaBridge 171:3a7713b1edbc 8536 /*! @name PE7 - LLWU Pin Enable 7 register */
AnnaBridge 171:3a7713b1edbc 8537 #define LLWU_PE7_WUPE24_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 8538 #define LLWU_PE7_WUPE24_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8539 #define LLWU_PE7_WUPE24(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE24_SHIFT)) & LLWU_PE7_WUPE24_MASK)
AnnaBridge 171:3a7713b1edbc 8540 #define LLWU_PE7_WUPE25_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 8541 #define LLWU_PE7_WUPE25_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8542 #define LLWU_PE7_WUPE25(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE25_SHIFT)) & LLWU_PE7_WUPE25_MASK)
AnnaBridge 171:3a7713b1edbc 8543 #define LLWU_PE7_WUPE26_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 8544 #define LLWU_PE7_WUPE26_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8545 #define LLWU_PE7_WUPE26(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE26_SHIFT)) & LLWU_PE7_WUPE26_MASK)
AnnaBridge 171:3a7713b1edbc 8546 #define LLWU_PE7_WUPE27_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 8547 #define LLWU_PE7_WUPE27_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8548 #define LLWU_PE7_WUPE27(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE27_SHIFT)) & LLWU_PE7_WUPE27_MASK)
AnnaBridge 171:3a7713b1edbc 8549
AnnaBridge 171:3a7713b1edbc 8550 /*! @name PE8 - LLWU Pin Enable 8 register */
AnnaBridge 171:3a7713b1edbc 8551 #define LLWU_PE8_WUPE28_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 8552 #define LLWU_PE8_WUPE28_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8553 #define LLWU_PE8_WUPE28(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE28_SHIFT)) & LLWU_PE8_WUPE28_MASK)
AnnaBridge 171:3a7713b1edbc 8554 #define LLWU_PE8_WUPE29_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 8555 #define LLWU_PE8_WUPE29_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8556 #define LLWU_PE8_WUPE29(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE29_SHIFT)) & LLWU_PE8_WUPE29_MASK)
AnnaBridge 171:3a7713b1edbc 8557 #define LLWU_PE8_WUPE30_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 8558 #define LLWU_PE8_WUPE30_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8559 #define LLWU_PE8_WUPE30(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE30_SHIFT)) & LLWU_PE8_WUPE30_MASK)
AnnaBridge 171:3a7713b1edbc 8560 #define LLWU_PE8_WUPE31_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 8561 #define LLWU_PE8_WUPE31_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8562 #define LLWU_PE8_WUPE31(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE31_SHIFT)) & LLWU_PE8_WUPE31_MASK)
AnnaBridge 171:3a7713b1edbc 8563
AnnaBridge 171:3a7713b1edbc 8564 /*! @name ME - LLWU Module Enable register */
AnnaBridge 171:3a7713b1edbc 8565 #define LLWU_ME_WUME0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8566 #define LLWU_ME_WUME0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8567 #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
AnnaBridge 171:3a7713b1edbc 8568 #define LLWU_ME_WUME1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8569 #define LLWU_ME_WUME1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8570 #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
AnnaBridge 171:3a7713b1edbc 8571 #define LLWU_ME_WUME2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 8572 #define LLWU_ME_WUME2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8573 #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
AnnaBridge 171:3a7713b1edbc 8574 #define LLWU_ME_WUME3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8575 #define LLWU_ME_WUME3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8576 #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
AnnaBridge 171:3a7713b1edbc 8577 #define LLWU_ME_WUME4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8578 #define LLWU_ME_WUME4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8579 #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
AnnaBridge 171:3a7713b1edbc 8580 #define LLWU_ME_WUME5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8581 #define LLWU_ME_WUME5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8582 #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
AnnaBridge 171:3a7713b1edbc 8583 #define LLWU_ME_WUME6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8584 #define LLWU_ME_WUME6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8585 #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
AnnaBridge 171:3a7713b1edbc 8586 #define LLWU_ME_WUME7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8587 #define LLWU_ME_WUME7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8588 #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
AnnaBridge 171:3a7713b1edbc 8589
AnnaBridge 171:3a7713b1edbc 8590 /*! @name PF1 - LLWU Pin Flag 1 register */
AnnaBridge 171:3a7713b1edbc 8591 #define LLWU_PF1_WUF0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8592 #define LLWU_PF1_WUF0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8593 #define LLWU_PF1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF0_SHIFT)) & LLWU_PF1_WUF0_MASK)
AnnaBridge 171:3a7713b1edbc 8594 #define LLWU_PF1_WUF1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8595 #define LLWU_PF1_WUF1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8596 #define LLWU_PF1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF1_SHIFT)) & LLWU_PF1_WUF1_MASK)
AnnaBridge 171:3a7713b1edbc 8597 #define LLWU_PF1_WUF2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 8598 #define LLWU_PF1_WUF2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8599 #define LLWU_PF1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF2_SHIFT)) & LLWU_PF1_WUF2_MASK)
AnnaBridge 171:3a7713b1edbc 8600 #define LLWU_PF1_WUF3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8601 #define LLWU_PF1_WUF3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8602 #define LLWU_PF1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF3_SHIFT)) & LLWU_PF1_WUF3_MASK)
AnnaBridge 171:3a7713b1edbc 8603 #define LLWU_PF1_WUF4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8604 #define LLWU_PF1_WUF4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8605 #define LLWU_PF1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF4_SHIFT)) & LLWU_PF1_WUF4_MASK)
AnnaBridge 171:3a7713b1edbc 8606 #define LLWU_PF1_WUF5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8607 #define LLWU_PF1_WUF5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8608 #define LLWU_PF1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF5_SHIFT)) & LLWU_PF1_WUF5_MASK)
AnnaBridge 171:3a7713b1edbc 8609 #define LLWU_PF1_WUF6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8610 #define LLWU_PF1_WUF6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8611 #define LLWU_PF1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF6_SHIFT)) & LLWU_PF1_WUF6_MASK)
AnnaBridge 171:3a7713b1edbc 8612 #define LLWU_PF1_WUF7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8613 #define LLWU_PF1_WUF7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8614 #define LLWU_PF1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF7_SHIFT)) & LLWU_PF1_WUF7_MASK)
AnnaBridge 171:3a7713b1edbc 8615
AnnaBridge 171:3a7713b1edbc 8616 /*! @name PF2 - LLWU Pin Flag 2 register */
AnnaBridge 171:3a7713b1edbc 8617 #define LLWU_PF2_WUF8_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8618 #define LLWU_PF2_WUF8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8619 #define LLWU_PF2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF8_SHIFT)) & LLWU_PF2_WUF8_MASK)
AnnaBridge 171:3a7713b1edbc 8620 #define LLWU_PF2_WUF9_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8621 #define LLWU_PF2_WUF9_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8622 #define LLWU_PF2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF9_SHIFT)) & LLWU_PF2_WUF9_MASK)
AnnaBridge 171:3a7713b1edbc 8623 #define LLWU_PF2_WUF10_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 8624 #define LLWU_PF2_WUF10_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8625 #define LLWU_PF2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF10_SHIFT)) & LLWU_PF2_WUF10_MASK)
AnnaBridge 171:3a7713b1edbc 8626 #define LLWU_PF2_WUF11_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8627 #define LLWU_PF2_WUF11_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8628 #define LLWU_PF2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF11_SHIFT)) & LLWU_PF2_WUF11_MASK)
AnnaBridge 171:3a7713b1edbc 8629 #define LLWU_PF2_WUF12_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8630 #define LLWU_PF2_WUF12_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8631 #define LLWU_PF2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF12_SHIFT)) & LLWU_PF2_WUF12_MASK)
AnnaBridge 171:3a7713b1edbc 8632 #define LLWU_PF2_WUF13_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8633 #define LLWU_PF2_WUF13_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8634 #define LLWU_PF2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF13_SHIFT)) & LLWU_PF2_WUF13_MASK)
AnnaBridge 171:3a7713b1edbc 8635 #define LLWU_PF2_WUF14_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8636 #define LLWU_PF2_WUF14_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8637 #define LLWU_PF2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF14_SHIFT)) & LLWU_PF2_WUF14_MASK)
AnnaBridge 171:3a7713b1edbc 8638 #define LLWU_PF2_WUF15_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8639 #define LLWU_PF2_WUF15_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8640 #define LLWU_PF2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF15_SHIFT)) & LLWU_PF2_WUF15_MASK)
AnnaBridge 171:3a7713b1edbc 8641
AnnaBridge 171:3a7713b1edbc 8642 /*! @name PF3 - LLWU Pin Flag 3 register */
AnnaBridge 171:3a7713b1edbc 8643 #define LLWU_PF3_WUF16_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8644 #define LLWU_PF3_WUF16_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8645 #define LLWU_PF3_WUF16(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF16_SHIFT)) & LLWU_PF3_WUF16_MASK)
AnnaBridge 171:3a7713b1edbc 8646 #define LLWU_PF3_WUF17_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8647 #define LLWU_PF3_WUF17_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8648 #define LLWU_PF3_WUF17(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF17_SHIFT)) & LLWU_PF3_WUF17_MASK)
AnnaBridge 171:3a7713b1edbc 8649 #define LLWU_PF3_WUF18_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 8650 #define LLWU_PF3_WUF18_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8651 #define LLWU_PF3_WUF18(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF18_SHIFT)) & LLWU_PF3_WUF18_MASK)
AnnaBridge 171:3a7713b1edbc 8652 #define LLWU_PF3_WUF19_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8653 #define LLWU_PF3_WUF19_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8654 #define LLWU_PF3_WUF19(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF19_SHIFT)) & LLWU_PF3_WUF19_MASK)
AnnaBridge 171:3a7713b1edbc 8655 #define LLWU_PF3_WUF20_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8656 #define LLWU_PF3_WUF20_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8657 #define LLWU_PF3_WUF20(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF20_SHIFT)) & LLWU_PF3_WUF20_MASK)
AnnaBridge 171:3a7713b1edbc 8658 #define LLWU_PF3_WUF21_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8659 #define LLWU_PF3_WUF21_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8660 #define LLWU_PF3_WUF21(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF21_SHIFT)) & LLWU_PF3_WUF21_MASK)
AnnaBridge 171:3a7713b1edbc 8661 #define LLWU_PF3_WUF22_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8662 #define LLWU_PF3_WUF22_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8663 #define LLWU_PF3_WUF22(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF22_SHIFT)) & LLWU_PF3_WUF22_MASK)
AnnaBridge 171:3a7713b1edbc 8664 #define LLWU_PF3_WUF23_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8665 #define LLWU_PF3_WUF23_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8666 #define LLWU_PF3_WUF23(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF23_SHIFT)) & LLWU_PF3_WUF23_MASK)
AnnaBridge 171:3a7713b1edbc 8667
AnnaBridge 171:3a7713b1edbc 8668 /*! @name PF4 - LLWU Pin Flag 4 register */
AnnaBridge 171:3a7713b1edbc 8669 #define LLWU_PF4_WUF24_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8670 #define LLWU_PF4_WUF24_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8671 #define LLWU_PF4_WUF24(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF24_SHIFT)) & LLWU_PF4_WUF24_MASK)
AnnaBridge 171:3a7713b1edbc 8672 #define LLWU_PF4_WUF25_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8673 #define LLWU_PF4_WUF25_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8674 #define LLWU_PF4_WUF25(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF25_SHIFT)) & LLWU_PF4_WUF25_MASK)
AnnaBridge 171:3a7713b1edbc 8675 #define LLWU_PF4_WUF26_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 8676 #define LLWU_PF4_WUF26_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8677 #define LLWU_PF4_WUF26(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF26_SHIFT)) & LLWU_PF4_WUF26_MASK)
AnnaBridge 171:3a7713b1edbc 8678 #define LLWU_PF4_WUF27_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8679 #define LLWU_PF4_WUF27_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8680 #define LLWU_PF4_WUF27(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF27_SHIFT)) & LLWU_PF4_WUF27_MASK)
AnnaBridge 171:3a7713b1edbc 8681 #define LLWU_PF4_WUF28_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8682 #define LLWU_PF4_WUF28_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8683 #define LLWU_PF4_WUF28(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF28_SHIFT)) & LLWU_PF4_WUF28_MASK)
AnnaBridge 171:3a7713b1edbc 8684 #define LLWU_PF4_WUF29_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8685 #define LLWU_PF4_WUF29_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8686 #define LLWU_PF4_WUF29(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF29_SHIFT)) & LLWU_PF4_WUF29_MASK)
AnnaBridge 171:3a7713b1edbc 8687 #define LLWU_PF4_WUF30_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8688 #define LLWU_PF4_WUF30_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8689 #define LLWU_PF4_WUF30(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF30_SHIFT)) & LLWU_PF4_WUF30_MASK)
AnnaBridge 171:3a7713b1edbc 8690 #define LLWU_PF4_WUF31_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8691 #define LLWU_PF4_WUF31_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8692 #define LLWU_PF4_WUF31(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF31_SHIFT)) & LLWU_PF4_WUF31_MASK)
AnnaBridge 171:3a7713b1edbc 8693
AnnaBridge 171:3a7713b1edbc 8694 /*! @name MF5 - LLWU Module Flag 5 register */
AnnaBridge 171:3a7713b1edbc 8695 #define LLWU_MF5_MWUF0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8696 #define LLWU_MF5_MWUF0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8697 #define LLWU_MF5_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF0_SHIFT)) & LLWU_MF5_MWUF0_MASK)
AnnaBridge 171:3a7713b1edbc 8698 #define LLWU_MF5_MWUF1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8699 #define LLWU_MF5_MWUF1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8700 #define LLWU_MF5_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF1_SHIFT)) & LLWU_MF5_MWUF1_MASK)
AnnaBridge 171:3a7713b1edbc 8701 #define LLWU_MF5_MWUF2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 8702 #define LLWU_MF5_MWUF2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8703 #define LLWU_MF5_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF2_SHIFT)) & LLWU_MF5_MWUF2_MASK)
AnnaBridge 171:3a7713b1edbc 8704 #define LLWU_MF5_MWUF3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8705 #define LLWU_MF5_MWUF3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8706 #define LLWU_MF5_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF3_SHIFT)) & LLWU_MF5_MWUF3_MASK)
AnnaBridge 171:3a7713b1edbc 8707 #define LLWU_MF5_MWUF4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8708 #define LLWU_MF5_MWUF4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8709 #define LLWU_MF5_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF4_SHIFT)) & LLWU_MF5_MWUF4_MASK)
AnnaBridge 171:3a7713b1edbc 8710 #define LLWU_MF5_MWUF5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8711 #define LLWU_MF5_MWUF5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8712 #define LLWU_MF5_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF5_SHIFT)) & LLWU_MF5_MWUF5_MASK)
AnnaBridge 171:3a7713b1edbc 8713 #define LLWU_MF5_MWUF6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8714 #define LLWU_MF5_MWUF6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8715 #define LLWU_MF5_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF6_SHIFT)) & LLWU_MF5_MWUF6_MASK)
AnnaBridge 171:3a7713b1edbc 8716 #define LLWU_MF5_MWUF7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8717 #define LLWU_MF5_MWUF7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8718 #define LLWU_MF5_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF7_SHIFT)) & LLWU_MF5_MWUF7_MASK)
AnnaBridge 171:3a7713b1edbc 8719
AnnaBridge 171:3a7713b1edbc 8720 /*! @name FILT1 - LLWU Pin Filter 1 register */
AnnaBridge 171:3a7713b1edbc 8721 #define LLWU_FILT1_FILTSEL_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 8722 #define LLWU_FILT1_FILTSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8723 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8724 #define LLWU_FILT1_FILTE_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 8725 #define LLWU_FILT1_FILTE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8726 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
AnnaBridge 171:3a7713b1edbc 8727 #define LLWU_FILT1_FILTF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8728 #define LLWU_FILT1_FILTF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8729 #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
AnnaBridge 171:3a7713b1edbc 8730
AnnaBridge 171:3a7713b1edbc 8731 /*! @name FILT2 - LLWU Pin Filter 2 register */
AnnaBridge 171:3a7713b1edbc 8732 #define LLWU_FILT2_FILTSEL_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 8733 #define LLWU_FILT2_FILTSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8734 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8735 #define LLWU_FILT2_FILTE_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 8736 #define LLWU_FILT2_FILTE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8737 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
AnnaBridge 171:3a7713b1edbc 8738 #define LLWU_FILT2_FILTF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8739 #define LLWU_FILT2_FILTF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8740 #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
AnnaBridge 171:3a7713b1edbc 8741
AnnaBridge 171:3a7713b1edbc 8742 /*! @name FILT3 - LLWU Pin Filter 3 register */
AnnaBridge 171:3a7713b1edbc 8743 #define LLWU_FILT3_FILTSEL_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 8744 #define LLWU_FILT3_FILTSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8745 #define LLWU_FILT3_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTSEL_SHIFT)) & LLWU_FILT3_FILTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8746 #define LLWU_FILT3_FILTE_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 8747 #define LLWU_FILT3_FILTE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8748 #define LLWU_FILT3_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTE_SHIFT)) & LLWU_FILT3_FILTE_MASK)
AnnaBridge 171:3a7713b1edbc 8749 #define LLWU_FILT3_FILTF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8750 #define LLWU_FILT3_FILTF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8751 #define LLWU_FILT3_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTF_SHIFT)) & LLWU_FILT3_FILTF_MASK)
AnnaBridge 171:3a7713b1edbc 8752
AnnaBridge 171:3a7713b1edbc 8753 /*! @name FILT4 - LLWU Pin Filter 4 register */
AnnaBridge 171:3a7713b1edbc 8754 #define LLWU_FILT4_FILTSEL_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 8755 #define LLWU_FILT4_FILTSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8756 #define LLWU_FILT4_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTSEL_SHIFT)) & LLWU_FILT4_FILTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8757 #define LLWU_FILT4_FILTE_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 8758 #define LLWU_FILT4_FILTE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8759 #define LLWU_FILT4_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTE_SHIFT)) & LLWU_FILT4_FILTE_MASK)
AnnaBridge 171:3a7713b1edbc 8760 #define LLWU_FILT4_FILTF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8761 #define LLWU_FILT4_FILTF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8762 #define LLWU_FILT4_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTF_SHIFT)) & LLWU_FILT4_FILTF_MASK)
AnnaBridge 171:3a7713b1edbc 8763
AnnaBridge 171:3a7713b1edbc 8764
AnnaBridge 171:3a7713b1edbc 8765 /*!
AnnaBridge 171:3a7713b1edbc 8766 * @}
AnnaBridge 171:3a7713b1edbc 8767 */ /* end of group LLWU_Register_Masks */
AnnaBridge 171:3a7713b1edbc 8768
AnnaBridge 171:3a7713b1edbc 8769
AnnaBridge 171:3a7713b1edbc 8770 /* LLWU - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 8771 /** Peripheral LLWU base address */
AnnaBridge 171:3a7713b1edbc 8772 #define LLWU_BASE (0x4007C000u)
AnnaBridge 171:3a7713b1edbc 8773 /** Peripheral LLWU base pointer */
AnnaBridge 171:3a7713b1edbc 8774 #define LLWU ((LLWU_Type *)LLWU_BASE)
AnnaBridge 171:3a7713b1edbc 8775 /** Array initializer of LLWU peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 8776 #define LLWU_BASE_ADDRS { LLWU_BASE }
AnnaBridge 171:3a7713b1edbc 8777 /** Array initializer of LLWU peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 8778 #define LLWU_BASE_PTRS { LLWU }
AnnaBridge 171:3a7713b1edbc 8779 /** Interrupt vectors for the LLWU peripheral type */
AnnaBridge 171:3a7713b1edbc 8780 #define LLWU_IRQS { LLWU_IRQn }
AnnaBridge 171:3a7713b1edbc 8781
AnnaBridge 171:3a7713b1edbc 8782 /*!
AnnaBridge 171:3a7713b1edbc 8783 * @}
AnnaBridge 171:3a7713b1edbc 8784 */ /* end of group LLWU_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 8785
AnnaBridge 171:3a7713b1edbc 8786
AnnaBridge 171:3a7713b1edbc 8787 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8788 -- LMEM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8789 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8790
AnnaBridge 171:3a7713b1edbc 8791 /*!
AnnaBridge 171:3a7713b1edbc 8792 * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8793 * @{
AnnaBridge 171:3a7713b1edbc 8794 */
AnnaBridge 171:3a7713b1edbc 8795
AnnaBridge 171:3a7713b1edbc 8796 /** LMEM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 8797 typedef struct {
AnnaBridge 171:3a7713b1edbc 8798 __IO uint32_t PCCCR; /**< Cache control register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 8799 __IO uint32_t PCCLCR; /**< Cache line control register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 8800 __IO uint32_t PCCSAR; /**< Cache search address register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 8801 __IO uint32_t PCCCVR; /**< Cache read/write value register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 8802 uint8_t RESERVED_0[16];
AnnaBridge 171:3a7713b1edbc 8803 __IO uint32_t PCCRMR; /**< Cache regions mode register, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 8804 } LMEM_Type;
AnnaBridge 171:3a7713b1edbc 8805
AnnaBridge 171:3a7713b1edbc 8806 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8807 -- LMEM Register Masks
AnnaBridge 171:3a7713b1edbc 8808 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8809
AnnaBridge 171:3a7713b1edbc 8810 /*!
AnnaBridge 171:3a7713b1edbc 8811 * @addtogroup LMEM_Register_Masks LMEM Register Masks
AnnaBridge 171:3a7713b1edbc 8812 * @{
AnnaBridge 171:3a7713b1edbc 8813 */
AnnaBridge 171:3a7713b1edbc 8814
AnnaBridge 171:3a7713b1edbc 8815 /*! @name PCCCR - Cache control register */
AnnaBridge 171:3a7713b1edbc 8816 #define LMEM_PCCCR_ENCACHE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8817 #define LMEM_PCCCR_ENCACHE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8818 #define LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK)
AnnaBridge 171:3a7713b1edbc 8819 #define LMEM_PCCCR_ENWRBUF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8820 #define LMEM_PCCCR_ENWRBUF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8821 #define LMEM_PCCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK)
AnnaBridge 171:3a7713b1edbc 8822 #define LMEM_PCCCR_PCCR2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 8823 #define LMEM_PCCCR_PCCR2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8824 #define LMEM_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK)
AnnaBridge 171:3a7713b1edbc 8825 #define LMEM_PCCCR_PCCR3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8826 #define LMEM_PCCCR_PCCR3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8827 #define LMEM_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK)
AnnaBridge 171:3a7713b1edbc 8828 #define LMEM_PCCCR_INVW0_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 8829 #define LMEM_PCCCR_INVW0_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8830 #define LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK)
AnnaBridge 171:3a7713b1edbc 8831 #define LMEM_PCCCR_PUSHW0_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 8832 #define LMEM_PCCCR_PUSHW0_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 8833 #define LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK)
AnnaBridge 171:3a7713b1edbc 8834 #define LMEM_PCCCR_INVW1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 8835 #define LMEM_PCCCR_INVW1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 8836 #define LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK)
AnnaBridge 171:3a7713b1edbc 8837 #define LMEM_PCCCR_PUSHW1_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 8838 #define LMEM_PCCCR_PUSHW1_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 8839 #define LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK)
AnnaBridge 171:3a7713b1edbc 8840 #define LMEM_PCCCR_GO_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 8841 #define LMEM_PCCCR_GO_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 8842 #define LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK)
AnnaBridge 171:3a7713b1edbc 8843
AnnaBridge 171:3a7713b1edbc 8844 /*! @name PCCLCR - Cache line control register */
AnnaBridge 171:3a7713b1edbc 8845 #define LMEM_PCCLCR_LGO_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8846 #define LMEM_PCCLCR_LGO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8847 #define LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK)
AnnaBridge 171:3a7713b1edbc 8848 #define LMEM_PCCLCR_CACHEADDR_MASK (0xFFCU)
AnnaBridge 171:3a7713b1edbc 8849 #define LMEM_PCCLCR_CACHEADDR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8850 #define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK)
AnnaBridge 171:3a7713b1edbc 8851 #define LMEM_PCCLCR_WSEL_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 8852 #define LMEM_PCCLCR_WSEL_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 8853 #define LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8854 #define LMEM_PCCLCR_TDSEL_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 8855 #define LMEM_PCCLCR_TDSEL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8856 #define LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8857 #define LMEM_PCCLCR_LCIVB_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 8858 #define LMEM_PCCLCR_LCIVB_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 8859 #define LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK)
AnnaBridge 171:3a7713b1edbc 8860 #define LMEM_PCCLCR_LCIMB_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 8861 #define LMEM_PCCLCR_LCIMB_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 8862 #define LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK)
AnnaBridge 171:3a7713b1edbc 8863 #define LMEM_PCCLCR_LCWAY_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 8864 #define LMEM_PCCLCR_LCWAY_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 8865 #define LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK)
AnnaBridge 171:3a7713b1edbc 8866 #define LMEM_PCCLCR_LCMD_MASK (0x3000000U)
AnnaBridge 171:3a7713b1edbc 8867 #define LMEM_PCCLCR_LCMD_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8868 #define LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK)
AnnaBridge 171:3a7713b1edbc 8869 #define LMEM_PCCLCR_LADSEL_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 8870 #define LMEM_PCCLCR_LADSEL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 8871 #define LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8872 #define LMEM_PCCLCR_LACC_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 8873 #define LMEM_PCCLCR_LACC_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 8874 #define LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK)
AnnaBridge 171:3a7713b1edbc 8875
AnnaBridge 171:3a7713b1edbc 8876 /*! @name PCCSAR - Cache search address register */
AnnaBridge 171:3a7713b1edbc 8877 #define LMEM_PCCSAR_LGO_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8878 #define LMEM_PCCSAR_LGO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8879 #define LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK)
AnnaBridge 171:3a7713b1edbc 8880 #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU)
AnnaBridge 171:3a7713b1edbc 8881 #define LMEM_PCCSAR_PHYADDR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8882 #define LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
AnnaBridge 171:3a7713b1edbc 8883
AnnaBridge 171:3a7713b1edbc 8884 /*! @name PCCCVR - Cache read/write value register */
AnnaBridge 171:3a7713b1edbc 8885 #define LMEM_PCCCVR_DATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 8886 #define LMEM_PCCCVR_DATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8887 #define LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK)
AnnaBridge 171:3a7713b1edbc 8888
AnnaBridge 171:3a7713b1edbc 8889 /*! @name PCCRMR - Cache regions mode register */
AnnaBridge 171:3a7713b1edbc 8890 #define LMEM_PCCRMR_R15_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 8891 #define LMEM_PCCRMR_R15_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8892 #define LMEM_PCCRMR_R15(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R15_SHIFT)) & LMEM_PCCRMR_R15_MASK)
AnnaBridge 171:3a7713b1edbc 8893 #define LMEM_PCCRMR_R14_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 8894 #define LMEM_PCCRMR_R14_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8895 #define LMEM_PCCRMR_R14(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R14_SHIFT)) & LMEM_PCCRMR_R14_MASK)
AnnaBridge 171:3a7713b1edbc 8896 #define LMEM_PCCRMR_R13_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 8897 #define LMEM_PCCRMR_R13_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8898 #define LMEM_PCCRMR_R13(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R13_SHIFT)) & LMEM_PCCRMR_R13_MASK)
AnnaBridge 171:3a7713b1edbc 8899 #define LMEM_PCCRMR_R12_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 8900 #define LMEM_PCCRMR_R12_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8901 #define LMEM_PCCRMR_R12(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R12_SHIFT)) & LMEM_PCCRMR_R12_MASK)
AnnaBridge 171:3a7713b1edbc 8902 #define LMEM_PCCRMR_R11_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 8903 #define LMEM_PCCRMR_R11_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8904 #define LMEM_PCCRMR_R11(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R11_SHIFT)) & LMEM_PCCRMR_R11_MASK)
AnnaBridge 171:3a7713b1edbc 8905 #define LMEM_PCCRMR_R10_MASK (0xC00U)
AnnaBridge 171:3a7713b1edbc 8906 #define LMEM_PCCRMR_R10_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 8907 #define LMEM_PCCRMR_R10(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R10_SHIFT)) & LMEM_PCCRMR_R10_MASK)
AnnaBridge 171:3a7713b1edbc 8908 #define LMEM_PCCRMR_R9_MASK (0x3000U)
AnnaBridge 171:3a7713b1edbc 8909 #define LMEM_PCCRMR_R9_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 8910 #define LMEM_PCCRMR_R9(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R9_SHIFT)) & LMEM_PCCRMR_R9_MASK)
AnnaBridge 171:3a7713b1edbc 8911 #define LMEM_PCCRMR_R8_MASK (0xC000U)
AnnaBridge 171:3a7713b1edbc 8912 #define LMEM_PCCRMR_R8_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 8913 #define LMEM_PCCRMR_R8(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R8_SHIFT)) & LMEM_PCCRMR_R8_MASK)
AnnaBridge 171:3a7713b1edbc 8914 #define LMEM_PCCRMR_R7_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 8915 #define LMEM_PCCRMR_R7_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8916 #define LMEM_PCCRMR_R7(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R7_SHIFT)) & LMEM_PCCRMR_R7_MASK)
AnnaBridge 171:3a7713b1edbc 8917 #define LMEM_PCCRMR_R6_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 8918 #define LMEM_PCCRMR_R6_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 8919 #define LMEM_PCCRMR_R6(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R6_SHIFT)) & LMEM_PCCRMR_R6_MASK)
AnnaBridge 171:3a7713b1edbc 8920 #define LMEM_PCCRMR_R5_MASK (0x300000U)
AnnaBridge 171:3a7713b1edbc 8921 #define LMEM_PCCRMR_R5_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 8922 #define LMEM_PCCRMR_R5(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R5_SHIFT)) & LMEM_PCCRMR_R5_MASK)
AnnaBridge 171:3a7713b1edbc 8923 #define LMEM_PCCRMR_R4_MASK (0xC00000U)
AnnaBridge 171:3a7713b1edbc 8924 #define LMEM_PCCRMR_R4_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 8925 #define LMEM_PCCRMR_R4(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R4_SHIFT)) & LMEM_PCCRMR_R4_MASK)
AnnaBridge 171:3a7713b1edbc 8926 #define LMEM_PCCRMR_R3_MASK (0x3000000U)
AnnaBridge 171:3a7713b1edbc 8927 #define LMEM_PCCRMR_R3_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8928 #define LMEM_PCCRMR_R3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R3_SHIFT)) & LMEM_PCCRMR_R3_MASK)
AnnaBridge 171:3a7713b1edbc 8929 #define LMEM_PCCRMR_R2_MASK (0xC000000U)
AnnaBridge 171:3a7713b1edbc 8930 #define LMEM_PCCRMR_R2_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 8931 #define LMEM_PCCRMR_R2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R2_SHIFT)) & LMEM_PCCRMR_R2_MASK)
AnnaBridge 171:3a7713b1edbc 8932 #define LMEM_PCCRMR_R1_MASK (0x30000000U)
AnnaBridge 171:3a7713b1edbc 8933 #define LMEM_PCCRMR_R1_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 8934 #define LMEM_PCCRMR_R1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R1_SHIFT)) & LMEM_PCCRMR_R1_MASK)
AnnaBridge 171:3a7713b1edbc 8935 #define LMEM_PCCRMR_R0_MASK (0xC0000000U)
AnnaBridge 171:3a7713b1edbc 8936 #define LMEM_PCCRMR_R0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 8937 #define LMEM_PCCRMR_R0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R0_SHIFT)) & LMEM_PCCRMR_R0_MASK)
AnnaBridge 171:3a7713b1edbc 8938
AnnaBridge 171:3a7713b1edbc 8939
AnnaBridge 171:3a7713b1edbc 8940 /*!
AnnaBridge 171:3a7713b1edbc 8941 * @}
AnnaBridge 171:3a7713b1edbc 8942 */ /* end of group LMEM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 8943
AnnaBridge 171:3a7713b1edbc 8944
AnnaBridge 171:3a7713b1edbc 8945 /* LMEM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 8946 /** Peripheral LMEM base address */
AnnaBridge 171:3a7713b1edbc 8947 #define LMEM_BASE (0xE0082000u)
AnnaBridge 171:3a7713b1edbc 8948 /** Peripheral LMEM base pointer */
AnnaBridge 171:3a7713b1edbc 8949 #define LMEM ((LMEM_Type *)LMEM_BASE)
AnnaBridge 171:3a7713b1edbc 8950 /** Array initializer of LMEM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 8951 #define LMEM_BASE_ADDRS { LMEM_BASE }
AnnaBridge 171:3a7713b1edbc 8952 /** Array initializer of LMEM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 8953 #define LMEM_BASE_PTRS { LMEM }
AnnaBridge 171:3a7713b1edbc 8954
AnnaBridge 171:3a7713b1edbc 8955 /*!
AnnaBridge 171:3a7713b1edbc 8956 * @}
AnnaBridge 171:3a7713b1edbc 8957 */ /* end of group LMEM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 8958
AnnaBridge 171:3a7713b1edbc 8959
AnnaBridge 171:3a7713b1edbc 8960 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8961 -- LPTMR Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8962 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8963
AnnaBridge 171:3a7713b1edbc 8964 /*!
AnnaBridge 171:3a7713b1edbc 8965 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8966 * @{
AnnaBridge 171:3a7713b1edbc 8967 */
AnnaBridge 171:3a7713b1edbc 8968
AnnaBridge 171:3a7713b1edbc 8969 /** LPTMR - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 8970 typedef struct {
AnnaBridge 171:3a7713b1edbc 8971 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 8972 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 8973 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 8974 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 8975 } LPTMR_Type;
AnnaBridge 171:3a7713b1edbc 8976
AnnaBridge 171:3a7713b1edbc 8977 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8978 -- LPTMR Register Masks
AnnaBridge 171:3a7713b1edbc 8979 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8980
AnnaBridge 171:3a7713b1edbc 8981 /*!
AnnaBridge 171:3a7713b1edbc 8982 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
AnnaBridge 171:3a7713b1edbc 8983 * @{
AnnaBridge 171:3a7713b1edbc 8984 */
AnnaBridge 171:3a7713b1edbc 8985
AnnaBridge 171:3a7713b1edbc 8986 /*! @name CSR - Low Power Timer Control Status Register */
AnnaBridge 171:3a7713b1edbc 8987 #define LPTMR_CSR_TEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8988 #define LPTMR_CSR_TEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8989 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
AnnaBridge 171:3a7713b1edbc 8990 #define LPTMR_CSR_TMS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8991 #define LPTMR_CSR_TMS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8992 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
AnnaBridge 171:3a7713b1edbc 8993 #define LPTMR_CSR_TFC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 8994 #define LPTMR_CSR_TFC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8995 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
AnnaBridge 171:3a7713b1edbc 8996 #define LPTMR_CSR_TPP_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8997 #define LPTMR_CSR_TPP_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8998 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
AnnaBridge 171:3a7713b1edbc 8999 #define LPTMR_CSR_TPS_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 9000 #define LPTMR_CSR_TPS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9001 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
AnnaBridge 171:3a7713b1edbc 9002 #define LPTMR_CSR_TIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 9003 #define LPTMR_CSR_TIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 9004 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
AnnaBridge 171:3a7713b1edbc 9005 #define LPTMR_CSR_TCF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9006 #define LPTMR_CSR_TCF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9007 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
AnnaBridge 171:3a7713b1edbc 9008
AnnaBridge 171:3a7713b1edbc 9009 /*! @name PSR - Low Power Timer Prescale Register */
AnnaBridge 171:3a7713b1edbc 9010 #define LPTMR_PSR_PCS_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 9011 #define LPTMR_PSR_PCS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9012 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
AnnaBridge 171:3a7713b1edbc 9013 #define LPTMR_PSR_PBYP_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9014 #define LPTMR_PSR_PBYP_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9015 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
AnnaBridge 171:3a7713b1edbc 9016 #define LPTMR_PSR_PRESCALE_MASK (0x78U)
AnnaBridge 171:3a7713b1edbc 9017 #define LPTMR_PSR_PRESCALE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9018 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
AnnaBridge 171:3a7713b1edbc 9019
AnnaBridge 171:3a7713b1edbc 9020 /*! @name CMR - Low Power Timer Compare Register */
AnnaBridge 171:3a7713b1edbc 9021 #define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 9022 #define LPTMR_CMR_COMPARE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9023 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
AnnaBridge 171:3a7713b1edbc 9024
AnnaBridge 171:3a7713b1edbc 9025 /*! @name CNR - Low Power Timer Counter Register */
AnnaBridge 171:3a7713b1edbc 9026 #define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 9027 #define LPTMR_CNR_COUNTER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9028 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
AnnaBridge 171:3a7713b1edbc 9029
AnnaBridge 171:3a7713b1edbc 9030
AnnaBridge 171:3a7713b1edbc 9031 /*!
AnnaBridge 171:3a7713b1edbc 9032 * @}
AnnaBridge 171:3a7713b1edbc 9033 */ /* end of group LPTMR_Register_Masks */
AnnaBridge 171:3a7713b1edbc 9034
AnnaBridge 171:3a7713b1edbc 9035
AnnaBridge 171:3a7713b1edbc 9036 /* LPTMR - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 9037 /** Peripheral LPTMR0 base address */
AnnaBridge 171:3a7713b1edbc 9038 #define LPTMR0_BASE (0x40040000u)
AnnaBridge 171:3a7713b1edbc 9039 /** Peripheral LPTMR0 base pointer */
AnnaBridge 171:3a7713b1edbc 9040 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
AnnaBridge 171:3a7713b1edbc 9041 /** Array initializer of LPTMR peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 9042 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
AnnaBridge 171:3a7713b1edbc 9043 /** Array initializer of LPTMR peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 9044 #define LPTMR_BASE_PTRS { LPTMR0 }
AnnaBridge 171:3a7713b1edbc 9045 /** Interrupt vectors for the LPTMR peripheral type */
AnnaBridge 171:3a7713b1edbc 9046 #define LPTMR_IRQS { LPTMR0_IRQn }
AnnaBridge 171:3a7713b1edbc 9047
AnnaBridge 171:3a7713b1edbc 9048 /*!
AnnaBridge 171:3a7713b1edbc 9049 * @}
AnnaBridge 171:3a7713b1edbc 9050 */ /* end of group LPTMR_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 9051
AnnaBridge 171:3a7713b1edbc 9052
AnnaBridge 171:3a7713b1edbc 9053 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9054 -- LPUART Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9055 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9056
AnnaBridge 171:3a7713b1edbc 9057 /*!
AnnaBridge 171:3a7713b1edbc 9058 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9059 * @{
AnnaBridge 171:3a7713b1edbc 9060 */
AnnaBridge 171:3a7713b1edbc 9061
AnnaBridge 171:3a7713b1edbc 9062 /** LPUART - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 9063 typedef struct {
AnnaBridge 171:3a7713b1edbc 9064 __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 9065 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 9066 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 9067 __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 9068 __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 9069 __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 9070 } LPUART_Type;
AnnaBridge 171:3a7713b1edbc 9071
AnnaBridge 171:3a7713b1edbc 9072 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9073 -- LPUART Register Masks
AnnaBridge 171:3a7713b1edbc 9074 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9075
AnnaBridge 171:3a7713b1edbc 9076 /*!
AnnaBridge 171:3a7713b1edbc 9077 * @addtogroup LPUART_Register_Masks LPUART Register Masks
AnnaBridge 171:3a7713b1edbc 9078 * @{
AnnaBridge 171:3a7713b1edbc 9079 */
AnnaBridge 171:3a7713b1edbc 9080
AnnaBridge 171:3a7713b1edbc 9081 /*! @name BAUD - LPUART Baud Rate Register */
AnnaBridge 171:3a7713b1edbc 9082 #define LPUART_BAUD_SBR_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 9083 #define LPUART_BAUD_SBR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9084 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
AnnaBridge 171:3a7713b1edbc 9085 #define LPUART_BAUD_SBNS_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 9086 #define LPUART_BAUD_SBNS_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 9087 #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
AnnaBridge 171:3a7713b1edbc 9088 #define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 9089 #define LPUART_BAUD_RXEDGIE_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 9090 #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
AnnaBridge 171:3a7713b1edbc 9091 #define LPUART_BAUD_LBKDIE_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 9092 #define LPUART_BAUD_LBKDIE_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 9093 #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
AnnaBridge 171:3a7713b1edbc 9094 #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 9095 #define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9096 #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
AnnaBridge 171:3a7713b1edbc 9097 #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 9098 #define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 9099 #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
AnnaBridge 171:3a7713b1edbc 9100 #define LPUART_BAUD_MATCFG_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 9101 #define LPUART_BAUD_MATCFG_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 9102 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
AnnaBridge 171:3a7713b1edbc 9103 #define LPUART_BAUD_RDMAE_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 9104 #define LPUART_BAUD_RDMAE_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 9105 #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
AnnaBridge 171:3a7713b1edbc 9106 #define LPUART_BAUD_TDMAE_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 9107 #define LPUART_BAUD_TDMAE_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 9108 #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
AnnaBridge 171:3a7713b1edbc 9109 #define LPUART_BAUD_OSR_MASK (0x1F000000U)
AnnaBridge 171:3a7713b1edbc 9110 #define LPUART_BAUD_OSR_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9111 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
AnnaBridge 171:3a7713b1edbc 9112 #define LPUART_BAUD_M10_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 9113 #define LPUART_BAUD_M10_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 9114 #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
AnnaBridge 171:3a7713b1edbc 9115 #define LPUART_BAUD_MAEN2_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 9116 #define LPUART_BAUD_MAEN2_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 9117 #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
AnnaBridge 171:3a7713b1edbc 9118 #define LPUART_BAUD_MAEN1_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 9119 #define LPUART_BAUD_MAEN1_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 9120 #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
AnnaBridge 171:3a7713b1edbc 9121
AnnaBridge 171:3a7713b1edbc 9122 /*! @name STAT - LPUART Status Register */
AnnaBridge 171:3a7713b1edbc 9123 #define LPUART_STAT_MA2F_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 9124 #define LPUART_STAT_MA2F_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 9125 #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
AnnaBridge 171:3a7713b1edbc 9126 #define LPUART_STAT_MA1F_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 9127 #define LPUART_STAT_MA1F_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 9128 #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
AnnaBridge 171:3a7713b1edbc 9129 #define LPUART_STAT_PF_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 9130 #define LPUART_STAT_PF_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9131 #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
AnnaBridge 171:3a7713b1edbc 9132 #define LPUART_STAT_FE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 9133 #define LPUART_STAT_FE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 9134 #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
AnnaBridge 171:3a7713b1edbc 9135 #define LPUART_STAT_NF_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 9136 #define LPUART_STAT_NF_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 9137 #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
AnnaBridge 171:3a7713b1edbc 9138 #define LPUART_STAT_OR_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 9139 #define LPUART_STAT_OR_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 9140 #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
AnnaBridge 171:3a7713b1edbc 9141 #define LPUART_STAT_IDLE_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 9142 #define LPUART_STAT_IDLE_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 9143 #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
AnnaBridge 171:3a7713b1edbc 9144 #define LPUART_STAT_RDRF_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 9145 #define LPUART_STAT_RDRF_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 9146 #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
AnnaBridge 171:3a7713b1edbc 9147 #define LPUART_STAT_TC_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 9148 #define LPUART_STAT_TC_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 9149 #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
AnnaBridge 171:3a7713b1edbc 9150 #define LPUART_STAT_TDRE_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 9151 #define LPUART_STAT_TDRE_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 9152 #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
AnnaBridge 171:3a7713b1edbc 9153 #define LPUART_STAT_RAF_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 9154 #define LPUART_STAT_RAF_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9155 #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
AnnaBridge 171:3a7713b1edbc 9156 #define LPUART_STAT_LBKDE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 9157 #define LPUART_STAT_LBKDE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 9158 #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
AnnaBridge 171:3a7713b1edbc 9159 #define LPUART_STAT_BRK13_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 9160 #define LPUART_STAT_BRK13_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 9161 #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
AnnaBridge 171:3a7713b1edbc 9162 #define LPUART_STAT_RWUID_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 9163 #define LPUART_STAT_RWUID_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 9164 #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
AnnaBridge 171:3a7713b1edbc 9165 #define LPUART_STAT_RXINV_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 9166 #define LPUART_STAT_RXINV_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 9167 #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
AnnaBridge 171:3a7713b1edbc 9168 #define LPUART_STAT_MSBF_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 9169 #define LPUART_STAT_MSBF_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 9170 #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
AnnaBridge 171:3a7713b1edbc 9171 #define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 9172 #define LPUART_STAT_RXEDGIF_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 9173 #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
AnnaBridge 171:3a7713b1edbc 9174 #define LPUART_STAT_LBKDIF_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 9175 #define LPUART_STAT_LBKDIF_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 9176 #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
AnnaBridge 171:3a7713b1edbc 9177
AnnaBridge 171:3a7713b1edbc 9178 /*! @name CTRL - LPUART Control Register */
AnnaBridge 171:3a7713b1edbc 9179 #define LPUART_CTRL_PT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9180 #define LPUART_CTRL_PT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9181 #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
AnnaBridge 171:3a7713b1edbc 9182 #define LPUART_CTRL_PE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9183 #define LPUART_CTRL_PE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9184 #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
AnnaBridge 171:3a7713b1edbc 9185 #define LPUART_CTRL_ILT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9186 #define LPUART_CTRL_ILT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9187 #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
AnnaBridge 171:3a7713b1edbc 9188 #define LPUART_CTRL_WAKE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9189 #define LPUART_CTRL_WAKE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9190 #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
AnnaBridge 171:3a7713b1edbc 9191 #define LPUART_CTRL_M_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9192 #define LPUART_CTRL_M_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9193 #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
AnnaBridge 171:3a7713b1edbc 9194 #define LPUART_CTRL_RSRC_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 9195 #define LPUART_CTRL_RSRC_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9196 #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
AnnaBridge 171:3a7713b1edbc 9197 #define LPUART_CTRL_DOZEEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 9198 #define LPUART_CTRL_DOZEEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 9199 #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
AnnaBridge 171:3a7713b1edbc 9200 #define LPUART_CTRL_LOOPS_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9201 #define LPUART_CTRL_LOOPS_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9202 #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
AnnaBridge 171:3a7713b1edbc 9203 #define LPUART_CTRL_IDLECFG_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 9204 #define LPUART_CTRL_IDLECFG_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9205 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
AnnaBridge 171:3a7713b1edbc 9206 #define LPUART_CTRL_MA2IE_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 9207 #define LPUART_CTRL_MA2IE_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 9208 #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
AnnaBridge 171:3a7713b1edbc 9209 #define LPUART_CTRL_MA1IE_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 9210 #define LPUART_CTRL_MA1IE_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 9211 #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
AnnaBridge 171:3a7713b1edbc 9212 #define LPUART_CTRL_SBK_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 9213 #define LPUART_CTRL_SBK_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9214 #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
AnnaBridge 171:3a7713b1edbc 9215 #define LPUART_CTRL_RWU_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 9216 #define LPUART_CTRL_RWU_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 9217 #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
AnnaBridge 171:3a7713b1edbc 9218 #define LPUART_CTRL_RE_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 9219 #define LPUART_CTRL_RE_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 9220 #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
AnnaBridge 171:3a7713b1edbc 9221 #define LPUART_CTRL_TE_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 9222 #define LPUART_CTRL_TE_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 9223 #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
AnnaBridge 171:3a7713b1edbc 9224 #define LPUART_CTRL_ILIE_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 9225 #define LPUART_CTRL_ILIE_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 9226 #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
AnnaBridge 171:3a7713b1edbc 9227 #define LPUART_CTRL_RIE_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 9228 #define LPUART_CTRL_RIE_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 9229 #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
AnnaBridge 171:3a7713b1edbc 9230 #define LPUART_CTRL_TCIE_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 9231 #define LPUART_CTRL_TCIE_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 9232 #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
AnnaBridge 171:3a7713b1edbc 9233 #define LPUART_CTRL_TIE_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 9234 #define LPUART_CTRL_TIE_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 9235 #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
AnnaBridge 171:3a7713b1edbc 9236 #define LPUART_CTRL_PEIE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 9237 #define LPUART_CTRL_PEIE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9238 #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
AnnaBridge 171:3a7713b1edbc 9239 #define LPUART_CTRL_FEIE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 9240 #define LPUART_CTRL_FEIE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 9241 #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
AnnaBridge 171:3a7713b1edbc 9242 #define LPUART_CTRL_NEIE_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 9243 #define LPUART_CTRL_NEIE_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 9244 #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
AnnaBridge 171:3a7713b1edbc 9245 #define LPUART_CTRL_ORIE_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 9246 #define LPUART_CTRL_ORIE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 9247 #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
AnnaBridge 171:3a7713b1edbc 9248 #define LPUART_CTRL_TXINV_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 9249 #define LPUART_CTRL_TXINV_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 9250 #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
AnnaBridge 171:3a7713b1edbc 9251 #define LPUART_CTRL_TXDIR_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 9252 #define LPUART_CTRL_TXDIR_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 9253 #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
AnnaBridge 171:3a7713b1edbc 9254 #define LPUART_CTRL_R9T8_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 9255 #define LPUART_CTRL_R9T8_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 9256 #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
AnnaBridge 171:3a7713b1edbc 9257 #define LPUART_CTRL_R8T9_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 9258 #define LPUART_CTRL_R8T9_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 9259 #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
AnnaBridge 171:3a7713b1edbc 9260
AnnaBridge 171:3a7713b1edbc 9261 /*! @name DATA - LPUART Data Register */
AnnaBridge 171:3a7713b1edbc 9262 #define LPUART_DATA_R0T0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9263 #define LPUART_DATA_R0T0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9264 #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
AnnaBridge 171:3a7713b1edbc 9265 #define LPUART_DATA_R1T1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9266 #define LPUART_DATA_R1T1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9267 #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
AnnaBridge 171:3a7713b1edbc 9268 #define LPUART_DATA_R2T2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9269 #define LPUART_DATA_R2T2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9270 #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
AnnaBridge 171:3a7713b1edbc 9271 #define LPUART_DATA_R3T3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9272 #define LPUART_DATA_R3T3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9273 #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
AnnaBridge 171:3a7713b1edbc 9274 #define LPUART_DATA_R4T4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9275 #define LPUART_DATA_R4T4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9276 #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
AnnaBridge 171:3a7713b1edbc 9277 #define LPUART_DATA_R5T5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 9278 #define LPUART_DATA_R5T5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9279 #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
AnnaBridge 171:3a7713b1edbc 9280 #define LPUART_DATA_R6T6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 9281 #define LPUART_DATA_R6T6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 9282 #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
AnnaBridge 171:3a7713b1edbc 9283 #define LPUART_DATA_R7T7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9284 #define LPUART_DATA_R7T7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9285 #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
AnnaBridge 171:3a7713b1edbc 9286 #define LPUART_DATA_R8T8_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 9287 #define LPUART_DATA_R8T8_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9288 #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
AnnaBridge 171:3a7713b1edbc 9289 #define LPUART_DATA_R9T9_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 9290 #define LPUART_DATA_R9T9_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 9291 #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
AnnaBridge 171:3a7713b1edbc 9292 #define LPUART_DATA_IDLINE_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 9293 #define LPUART_DATA_IDLINE_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 9294 #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
AnnaBridge 171:3a7713b1edbc 9295 #define LPUART_DATA_RXEMPT_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 9296 #define LPUART_DATA_RXEMPT_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 9297 #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
AnnaBridge 171:3a7713b1edbc 9298 #define LPUART_DATA_FRETSC_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 9299 #define LPUART_DATA_FRETSC_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 9300 #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
AnnaBridge 171:3a7713b1edbc 9301 #define LPUART_DATA_PARITYE_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 9302 #define LPUART_DATA_PARITYE_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 9303 #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
AnnaBridge 171:3a7713b1edbc 9304 #define LPUART_DATA_NOISY_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 9305 #define LPUART_DATA_NOISY_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 9306 #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
AnnaBridge 171:3a7713b1edbc 9307
AnnaBridge 171:3a7713b1edbc 9308 /*! @name MATCH - LPUART Match Address Register */
AnnaBridge 171:3a7713b1edbc 9309 #define LPUART_MATCH_MA1_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 9310 #define LPUART_MATCH_MA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9311 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
AnnaBridge 171:3a7713b1edbc 9312 #define LPUART_MATCH_MA2_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 9313 #define LPUART_MATCH_MA2_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9314 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
AnnaBridge 171:3a7713b1edbc 9315
AnnaBridge 171:3a7713b1edbc 9316 /*! @name MODIR - LPUART Modem IrDA Register */
AnnaBridge 171:3a7713b1edbc 9317 #define LPUART_MODIR_TXCTSE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9318 #define LPUART_MODIR_TXCTSE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9319 #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
AnnaBridge 171:3a7713b1edbc 9320 #define LPUART_MODIR_TXRTSE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9321 #define LPUART_MODIR_TXRTSE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9322 #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
AnnaBridge 171:3a7713b1edbc 9323 #define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9324 #define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9325 #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
AnnaBridge 171:3a7713b1edbc 9326 #define LPUART_MODIR_RXRTSE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9327 #define LPUART_MODIR_RXRTSE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9328 #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
AnnaBridge 171:3a7713b1edbc 9329 #define LPUART_MODIR_TXCTSC_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9330 #define LPUART_MODIR_TXCTSC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9331 #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
AnnaBridge 171:3a7713b1edbc 9332 #define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 9333 #define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9334 #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
AnnaBridge 171:3a7713b1edbc 9335 #define LPUART_MODIR_TNP_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 9336 #define LPUART_MODIR_TNP_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9337 #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
AnnaBridge 171:3a7713b1edbc 9338 #define LPUART_MODIR_IREN_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 9339 #define LPUART_MODIR_IREN_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 9340 #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
AnnaBridge 171:3a7713b1edbc 9341
AnnaBridge 171:3a7713b1edbc 9342
AnnaBridge 171:3a7713b1edbc 9343 /*!
AnnaBridge 171:3a7713b1edbc 9344 * @}
AnnaBridge 171:3a7713b1edbc 9345 */ /* end of group LPUART_Register_Masks */
AnnaBridge 171:3a7713b1edbc 9346
AnnaBridge 171:3a7713b1edbc 9347
AnnaBridge 171:3a7713b1edbc 9348 /* LPUART - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 9349 /** Peripheral LPUART0 base address */
AnnaBridge 171:3a7713b1edbc 9350 #define LPUART0_BASE (0x400C4000u)
AnnaBridge 171:3a7713b1edbc 9351 /** Peripheral LPUART0 base pointer */
AnnaBridge 171:3a7713b1edbc 9352 #define LPUART0 ((LPUART_Type *)LPUART0_BASE)
AnnaBridge 171:3a7713b1edbc 9353 /** Array initializer of LPUART peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 9354 #define LPUART_BASE_ADDRS { LPUART0_BASE }
AnnaBridge 171:3a7713b1edbc 9355 /** Array initializer of LPUART peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 9356 #define LPUART_BASE_PTRS { LPUART0 }
AnnaBridge 171:3a7713b1edbc 9357 /** Interrupt vectors for the LPUART peripheral type */
AnnaBridge 171:3a7713b1edbc 9358 #define LPUART_RX_TX_IRQS { LPUART0_IRQn }
AnnaBridge 171:3a7713b1edbc 9359 #define LPUART_ERR_IRQS { LPUART0_IRQn }
AnnaBridge 171:3a7713b1edbc 9360
AnnaBridge 171:3a7713b1edbc 9361 /*!
AnnaBridge 171:3a7713b1edbc 9362 * @}
AnnaBridge 171:3a7713b1edbc 9363 */ /* end of group LPUART_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 9364
AnnaBridge 171:3a7713b1edbc 9365
AnnaBridge 171:3a7713b1edbc 9366 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9367 -- MCG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9368 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9369
AnnaBridge 171:3a7713b1edbc 9370 /*!
AnnaBridge 171:3a7713b1edbc 9371 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9372 * @{
AnnaBridge 171:3a7713b1edbc 9373 */
AnnaBridge 171:3a7713b1edbc 9374
AnnaBridge 171:3a7713b1edbc 9375 /** MCG - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 9376 typedef struct {
AnnaBridge 171:3a7713b1edbc 9377 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 9378 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 9379 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 9380 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 9381 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 9382 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 9383 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 9384 uint8_t RESERVED_0[1];
AnnaBridge 171:3a7713b1edbc 9385 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 9386 uint8_t RESERVED_1[1];
AnnaBridge 171:3a7713b1edbc 9387 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 9388 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 9389 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 9390 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 9391 __IO uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
AnnaBridge 171:3a7713b1edbc 9392 uint8_t RESERVED_2[1];
AnnaBridge 171:3a7713b1edbc 9393 __IO uint8_t C11; /**< MCG Control 11 Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 9394 uint8_t RESERVED_3[1];
AnnaBridge 171:3a7713b1edbc 9395 __I uint8_t S2; /**< MCG Status 2 Register, offset: 0x12 */
AnnaBridge 171:3a7713b1edbc 9396 } MCG_Type;
AnnaBridge 171:3a7713b1edbc 9397
AnnaBridge 171:3a7713b1edbc 9398 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9399 -- MCG Register Masks
AnnaBridge 171:3a7713b1edbc 9400 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9401
AnnaBridge 171:3a7713b1edbc 9402 /*!
AnnaBridge 171:3a7713b1edbc 9403 * @addtogroup MCG_Register_Masks MCG Register Masks
AnnaBridge 171:3a7713b1edbc 9404 * @{
AnnaBridge 171:3a7713b1edbc 9405 */
AnnaBridge 171:3a7713b1edbc 9406
AnnaBridge 171:3a7713b1edbc 9407 /*! @name C1 - MCG Control 1 Register */
AnnaBridge 171:3a7713b1edbc 9408 #define MCG_C1_IREFSTEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9409 #define MCG_C1_IREFSTEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9410 #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
AnnaBridge 171:3a7713b1edbc 9411 #define MCG_C1_IRCLKEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9412 #define MCG_C1_IRCLKEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9413 #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
AnnaBridge 171:3a7713b1edbc 9414 #define MCG_C1_IREFS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9415 #define MCG_C1_IREFS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9416 #define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
AnnaBridge 171:3a7713b1edbc 9417 #define MCG_C1_FRDIV_MASK (0x38U)
AnnaBridge 171:3a7713b1edbc 9418 #define MCG_C1_FRDIV_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9419 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
AnnaBridge 171:3a7713b1edbc 9420 #define MCG_C1_CLKS_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 9421 #define MCG_C1_CLKS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 9422 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
AnnaBridge 171:3a7713b1edbc 9423
AnnaBridge 171:3a7713b1edbc 9424 /*! @name C2 - MCG Control 2 Register */
AnnaBridge 171:3a7713b1edbc 9425 #define MCG_C2_IRCS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9426 #define MCG_C2_IRCS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9427 #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
AnnaBridge 171:3a7713b1edbc 9428 #define MCG_C2_LP_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9429 #define MCG_C2_LP_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9430 #define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
AnnaBridge 171:3a7713b1edbc 9431 #define MCG_C2_EREFS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9432 #define MCG_C2_EREFS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9433 #define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
AnnaBridge 171:3a7713b1edbc 9434 #define MCG_C2_HGO_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9435 #define MCG_C2_HGO_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9436 #define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
AnnaBridge 171:3a7713b1edbc 9437 #define MCG_C2_RANGE_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 9438 #define MCG_C2_RANGE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9439 #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
AnnaBridge 171:3a7713b1edbc 9440 #define MCG_C2_FCFTRIM_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 9441 #define MCG_C2_FCFTRIM_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 9442 #define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
AnnaBridge 171:3a7713b1edbc 9443 #define MCG_C2_LOCRE0_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9444 #define MCG_C2_LOCRE0_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9445 #define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
AnnaBridge 171:3a7713b1edbc 9446
AnnaBridge 171:3a7713b1edbc 9447 /*! @name C3 - MCG Control 3 Register */
AnnaBridge 171:3a7713b1edbc 9448 #define MCG_C3_SCTRIM_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9449 #define MCG_C3_SCTRIM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9450 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
AnnaBridge 171:3a7713b1edbc 9451
AnnaBridge 171:3a7713b1edbc 9452 /*! @name C4 - MCG Control 4 Register */
AnnaBridge 171:3a7713b1edbc 9453 #define MCG_C4_SCFTRIM_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9454 #define MCG_C4_SCFTRIM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9455 #define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
AnnaBridge 171:3a7713b1edbc 9456 #define MCG_C4_FCTRIM_MASK (0x1EU)
AnnaBridge 171:3a7713b1edbc 9457 #define MCG_C4_FCTRIM_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9458 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
AnnaBridge 171:3a7713b1edbc 9459 #define MCG_C4_DRST_DRS_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 9460 #define MCG_C4_DRST_DRS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9461 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
AnnaBridge 171:3a7713b1edbc 9462 #define MCG_C4_DMX32_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9463 #define MCG_C4_DMX32_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9464 #define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
AnnaBridge 171:3a7713b1edbc 9465
AnnaBridge 171:3a7713b1edbc 9466 /*! @name C5 - MCG Control 5 Register */
AnnaBridge 171:3a7713b1edbc 9467 #define MCG_C5_PRDIV_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 9468 #define MCG_C5_PRDIV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9469 #define MCG_C5_PRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV_SHIFT)) & MCG_C5_PRDIV_MASK)
AnnaBridge 171:3a7713b1edbc 9470 #define MCG_C5_PLLSTEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 9471 #define MCG_C5_PLLSTEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9472 #define MCG_C5_PLLSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN_SHIFT)) & MCG_C5_PLLSTEN_MASK)
AnnaBridge 171:3a7713b1edbc 9473 #define MCG_C5_PLLCLKEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 9474 #define MCG_C5_PLLCLKEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 9475 #define MCG_C5_PLLCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN_SHIFT)) & MCG_C5_PLLCLKEN_MASK)
AnnaBridge 171:3a7713b1edbc 9476
AnnaBridge 171:3a7713b1edbc 9477 /*! @name C6 - MCG Control 6 Register */
AnnaBridge 171:3a7713b1edbc 9478 #define MCG_C6_VDIV_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 9479 #define MCG_C6_VDIV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9480 #define MCG_C6_VDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV_SHIFT)) & MCG_C6_VDIV_MASK)
AnnaBridge 171:3a7713b1edbc 9481 #define MCG_C6_CME0_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 9482 #define MCG_C6_CME0_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9483 #define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
AnnaBridge 171:3a7713b1edbc 9484 #define MCG_C6_PLLS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 9485 #define MCG_C6_PLLS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 9486 #define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
AnnaBridge 171:3a7713b1edbc 9487 #define MCG_C6_LOLIE0_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9488 #define MCG_C6_LOLIE0_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9489 #define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
AnnaBridge 171:3a7713b1edbc 9490
AnnaBridge 171:3a7713b1edbc 9491 /*! @name S - MCG Status Register */
AnnaBridge 171:3a7713b1edbc 9492 #define MCG_S_IRCST_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9493 #define MCG_S_IRCST_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9494 #define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
AnnaBridge 171:3a7713b1edbc 9495 #define MCG_S_OSCINIT0_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9496 #define MCG_S_OSCINIT0_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9497 #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
AnnaBridge 171:3a7713b1edbc 9498 #define MCG_S_CLKST_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 9499 #define MCG_S_CLKST_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9500 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
AnnaBridge 171:3a7713b1edbc 9501 #define MCG_S_IREFST_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9502 #define MCG_S_IREFST_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9503 #define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
AnnaBridge 171:3a7713b1edbc 9504 #define MCG_S_PLLST_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 9505 #define MCG_S_PLLST_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9506 #define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
AnnaBridge 171:3a7713b1edbc 9507 #define MCG_S_LOCK0_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 9508 #define MCG_S_LOCK0_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 9509 #define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
AnnaBridge 171:3a7713b1edbc 9510 #define MCG_S_LOLS0_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9511 #define MCG_S_LOLS0_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9512 #define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
AnnaBridge 171:3a7713b1edbc 9513
AnnaBridge 171:3a7713b1edbc 9514 /*! @name SC - MCG Status and Control Register */
AnnaBridge 171:3a7713b1edbc 9515 #define MCG_SC_LOCS0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9516 #define MCG_SC_LOCS0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9517 #define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
AnnaBridge 171:3a7713b1edbc 9518 #define MCG_SC_FCRDIV_MASK (0xEU)
AnnaBridge 171:3a7713b1edbc 9519 #define MCG_SC_FCRDIV_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9520 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
AnnaBridge 171:3a7713b1edbc 9521 #define MCG_SC_FLTPRSRV_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9522 #define MCG_SC_FLTPRSRV_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9523 #define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
AnnaBridge 171:3a7713b1edbc 9524 #define MCG_SC_ATMF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 9525 #define MCG_SC_ATMF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9526 #define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
AnnaBridge 171:3a7713b1edbc 9527 #define MCG_SC_ATMS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 9528 #define MCG_SC_ATMS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 9529 #define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
AnnaBridge 171:3a7713b1edbc 9530 #define MCG_SC_ATME_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9531 #define MCG_SC_ATME_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9532 #define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
AnnaBridge 171:3a7713b1edbc 9533
AnnaBridge 171:3a7713b1edbc 9534 /*! @name ATCVH - MCG Auto Trim Compare Value High Register */
AnnaBridge 171:3a7713b1edbc 9535 #define MCG_ATCVH_ATCVH_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9536 #define MCG_ATCVH_ATCVH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9537 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
AnnaBridge 171:3a7713b1edbc 9538
AnnaBridge 171:3a7713b1edbc 9539 /*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
AnnaBridge 171:3a7713b1edbc 9540 #define MCG_ATCVL_ATCVL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9541 #define MCG_ATCVL_ATCVL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9542 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
AnnaBridge 171:3a7713b1edbc 9543
AnnaBridge 171:3a7713b1edbc 9544 /*! @name C7 - MCG Control 7 Register */
AnnaBridge 171:3a7713b1edbc 9545 #define MCG_C7_OSCSEL_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 9546 #define MCG_C7_OSCSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9547 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
AnnaBridge 171:3a7713b1edbc 9548
AnnaBridge 171:3a7713b1edbc 9549 /*! @name C8 - MCG Control 8 Register */
AnnaBridge 171:3a7713b1edbc 9550 #define MCG_C8_LOCS1_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9551 #define MCG_C8_LOCS1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9552 #define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
AnnaBridge 171:3a7713b1edbc 9553 #define MCG_C8_CME1_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 9554 #define MCG_C8_CME1_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9555 #define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
AnnaBridge 171:3a7713b1edbc 9556 #define MCG_C8_LOLRE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 9557 #define MCG_C8_LOLRE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 9558 #define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
AnnaBridge 171:3a7713b1edbc 9559 #define MCG_C8_LOCRE1_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9560 #define MCG_C8_LOCRE1_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9561 #define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
AnnaBridge 171:3a7713b1edbc 9562
AnnaBridge 171:3a7713b1edbc 9563 /*! @name C9 - MCG Control 9 Register */
AnnaBridge 171:3a7713b1edbc 9564 #define MCG_C9_EXT_PLL_LOCS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9565 #define MCG_C9_EXT_PLL_LOCS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9566 #define MCG_C9_EXT_PLL_LOCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C9_EXT_PLL_LOCS_SHIFT)) & MCG_C9_EXT_PLL_LOCS_MASK)
AnnaBridge 171:3a7713b1edbc 9567 #define MCG_C9_PLL_LOCRE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9568 #define MCG_C9_PLL_LOCRE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9569 #define MCG_C9_PLL_LOCRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_LOCRE_SHIFT)) & MCG_C9_PLL_LOCRE_MASK)
AnnaBridge 171:3a7713b1edbc 9570 #define MCG_C9_PLL_CME_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 9571 #define MCG_C9_PLL_CME_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9572 #define MCG_C9_PLL_CME(x) (((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_CME_SHIFT)) & MCG_C9_PLL_CME_MASK)
AnnaBridge 171:3a7713b1edbc 9573
AnnaBridge 171:3a7713b1edbc 9574 /*! @name C11 - MCG Control 11 Register */
AnnaBridge 171:3a7713b1edbc 9575 #define MCG_C11_PLLCS_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9576 #define MCG_C11_PLLCS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9577 #define MCG_C11_PLLCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C11_PLLCS_SHIFT)) & MCG_C11_PLLCS_MASK)
AnnaBridge 171:3a7713b1edbc 9578
AnnaBridge 171:3a7713b1edbc 9579 /*! @name S2 - MCG Status 2 Register */
AnnaBridge 171:3a7713b1edbc 9580 #define MCG_S2_PLLCST_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9581 #define MCG_S2_PLLCST_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9582 #define MCG_S2_PLLCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S2_PLLCST_SHIFT)) & MCG_S2_PLLCST_MASK)
AnnaBridge 171:3a7713b1edbc 9583
AnnaBridge 171:3a7713b1edbc 9584
AnnaBridge 171:3a7713b1edbc 9585 /*!
AnnaBridge 171:3a7713b1edbc 9586 * @}
AnnaBridge 171:3a7713b1edbc 9587 */ /* end of group MCG_Register_Masks */
AnnaBridge 171:3a7713b1edbc 9588
AnnaBridge 171:3a7713b1edbc 9589
AnnaBridge 171:3a7713b1edbc 9590 /* MCG - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 9591 /** Peripheral MCG base address */
AnnaBridge 171:3a7713b1edbc 9592 #define MCG_BASE (0x40064000u)
AnnaBridge 171:3a7713b1edbc 9593 /** Peripheral MCG base pointer */
AnnaBridge 171:3a7713b1edbc 9594 #define MCG ((MCG_Type *)MCG_BASE)
AnnaBridge 171:3a7713b1edbc 9595 /** Array initializer of MCG peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 9596 #define MCG_BASE_ADDRS { MCG_BASE }
AnnaBridge 171:3a7713b1edbc 9597 /** Array initializer of MCG peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 9598 #define MCG_BASE_PTRS { MCG }
AnnaBridge 171:3a7713b1edbc 9599 /* MCG C5[PLLCLKEN0] backward compatibility */
AnnaBridge 171:3a7713b1edbc 9600 #define MCG_C5_PLLCLKEN0_MASK (MCG_C5_PLLCLKEN_MASK)
AnnaBridge 171:3a7713b1edbc 9601 #define MCG_C5_PLLCLKEN0_SHIFT (MCG_C5_PLLCLKEN_SHIFT)
AnnaBridge 171:3a7713b1edbc 9602 #define MCG_C5_PLLCLKEN0_WIDTH (MCG_C5_PLLCLKEN_WIDTH)
AnnaBridge 171:3a7713b1edbc 9603 #define MCG_C5_PLLCLKEN0(x) (MCG_C5_PLLCLKEN(x))
AnnaBridge 171:3a7713b1edbc 9604
AnnaBridge 171:3a7713b1edbc 9605 /* MCG C5[PLLSTEN0] backward compatibility */
AnnaBridge 171:3a7713b1edbc 9606 #define MCG_C5_PLLSTEN0_MASK (MCG_C5_PLLSTEN_MASK)
AnnaBridge 171:3a7713b1edbc 9607 #define MCG_C5_PLLSTEN0_SHIFT (MCG_C5_PLLSTEN_SHIFT)
AnnaBridge 171:3a7713b1edbc 9608 #define MCG_C5_PLLSTEN0_WIDTH (MCG_C5_PLLSTEN_WIDTH)
AnnaBridge 171:3a7713b1edbc 9609 #define MCG_C5_PLLSTEN0(x) (MCG_C5_PLLSTEN(x))
AnnaBridge 171:3a7713b1edbc 9610
AnnaBridge 171:3a7713b1edbc 9611 /* MCG C5[PRDIV0] backward compatibility */
AnnaBridge 171:3a7713b1edbc 9612 #define MCG_C5_PRDIV0_MASK (MCG_C5_PRDIV_MASK)
AnnaBridge 171:3a7713b1edbc 9613 #define MCG_C5_PRDIV0_SHIFT (MCG_C5_PRDIV_SHIFT)
AnnaBridge 171:3a7713b1edbc 9614 #define MCG_C5_PRDIV0_WIDTH (MCG_C5_PRDIV_WIDTH)
AnnaBridge 171:3a7713b1edbc 9615 #define MCG_C5_PRDIV0(x) (MCG_C5_PRDIV(x))
AnnaBridge 171:3a7713b1edbc 9616
AnnaBridge 171:3a7713b1edbc 9617 /* MCG C6[VDIV0] backward compatibility */
AnnaBridge 171:3a7713b1edbc 9618 #define MCG_C6_VDIV0_MASK (MCG_C6_VDIV_MASK)
AnnaBridge 171:3a7713b1edbc 9619 #define MCG_C6_VDIV0_SHIFT (MCG_C6_VDIV_SHIFT)
AnnaBridge 171:3a7713b1edbc 9620 #define MCG_C6_VDIV0_WIDTH (MCG_C6_VDIV_WIDTH)
AnnaBridge 171:3a7713b1edbc 9621 #define MCG_C6_VDIV0(x) (MCG_C6_VDIV(x))
AnnaBridge 171:3a7713b1edbc 9622
AnnaBridge 171:3a7713b1edbc 9623
AnnaBridge 171:3a7713b1edbc 9624 /*!
AnnaBridge 171:3a7713b1edbc 9625 * @}
AnnaBridge 171:3a7713b1edbc 9626 */ /* end of group MCG_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 9627
AnnaBridge 171:3a7713b1edbc 9628
AnnaBridge 171:3a7713b1edbc 9629 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9630 -- MCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9631 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9632
AnnaBridge 171:3a7713b1edbc 9633 /*!
AnnaBridge 171:3a7713b1edbc 9634 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9635 * @{
AnnaBridge 171:3a7713b1edbc 9636 */
AnnaBridge 171:3a7713b1edbc 9637
AnnaBridge 171:3a7713b1edbc 9638 /** MCM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 9639 typedef struct {
AnnaBridge 171:3a7713b1edbc 9640 uint8_t RESERVED_0[8];
AnnaBridge 171:3a7713b1edbc 9641 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 9642 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 9643 __IO uint32_t CR; /**< Control Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 9644 __IO uint32_t ISCR; /**< Interrupt Status Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 9645 __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 9646 __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 9647 __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 9648 __I uint32_t FADR; /**< Fault address register, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 9649 __I uint32_t FATR; /**< Fault attributes register, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 9650 __I uint32_t FDR; /**< Fault data register, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 9651 uint8_t RESERVED_1[4];
AnnaBridge 171:3a7713b1edbc 9652 __IO uint32_t PID; /**< Process ID register, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 9653 uint8_t RESERVED_2[12];
AnnaBridge 171:3a7713b1edbc 9654 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 9655 } MCM_Type;
AnnaBridge 171:3a7713b1edbc 9656
AnnaBridge 171:3a7713b1edbc 9657 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9658 -- MCM Register Masks
AnnaBridge 171:3a7713b1edbc 9659 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9660
AnnaBridge 171:3a7713b1edbc 9661 /*!
AnnaBridge 171:3a7713b1edbc 9662 * @addtogroup MCM_Register_Masks MCM Register Masks
AnnaBridge 171:3a7713b1edbc 9663 * @{
AnnaBridge 171:3a7713b1edbc 9664 */
AnnaBridge 171:3a7713b1edbc 9665
AnnaBridge 171:3a7713b1edbc 9666 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
AnnaBridge 171:3a7713b1edbc 9667 #define MCM_PLASC_ASC_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9668 #define MCM_PLASC_ASC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9669 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
AnnaBridge 171:3a7713b1edbc 9670
AnnaBridge 171:3a7713b1edbc 9671 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
AnnaBridge 171:3a7713b1edbc 9672 #define MCM_PLAMC_AMC_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9673 #define MCM_PLAMC_AMC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9674 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
AnnaBridge 171:3a7713b1edbc 9675
AnnaBridge 171:3a7713b1edbc 9676 /*! @name CR - Control Register */
AnnaBridge 171:3a7713b1edbc 9677 #define MCM_CR_SRAMUAP_MASK (0x3000000U)
AnnaBridge 171:3a7713b1edbc 9678 #define MCM_CR_SRAMUAP_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9679 #define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
AnnaBridge 171:3a7713b1edbc 9680 #define MCM_CR_SRAMUWP_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 9681 #define MCM_CR_SRAMUWP_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 9682 #define MCM_CR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK)
AnnaBridge 171:3a7713b1edbc 9683 #define MCM_CR_SRAMLAP_MASK (0x30000000U)
AnnaBridge 171:3a7713b1edbc 9684 #define MCM_CR_SRAMLAP_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 9685 #define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
AnnaBridge 171:3a7713b1edbc 9686 #define MCM_CR_SRAMLWP_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 9687 #define MCM_CR_SRAMLWP_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 9688 #define MCM_CR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK)
AnnaBridge 171:3a7713b1edbc 9689
AnnaBridge 171:3a7713b1edbc 9690 /*! @name ISCR - Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 9691 #define MCM_ISCR_IRQ_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9692 #define MCM_ISCR_IRQ_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9693 #define MCM_ISCR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 9694 #define MCM_ISCR_NMI_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9695 #define MCM_ISCR_NMI_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9696 #define MCM_ISCR_NMI(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK)
AnnaBridge 171:3a7713b1edbc 9697 #define MCM_ISCR_DHREQ_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9698 #define MCM_ISCR_DHREQ_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9699 #define MCM_ISCR_DHREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK)
AnnaBridge 171:3a7713b1edbc 9700 #define MCM_ISCR_FIOC_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 9701 #define MCM_ISCR_FIOC_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9702 #define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
AnnaBridge 171:3a7713b1edbc 9703 #define MCM_ISCR_FDZC_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 9704 #define MCM_ISCR_FDZC_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 9705 #define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
AnnaBridge 171:3a7713b1edbc 9706 #define MCM_ISCR_FOFC_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 9707 #define MCM_ISCR_FOFC_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 9708 #define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
AnnaBridge 171:3a7713b1edbc 9709 #define MCM_ISCR_FUFC_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 9710 #define MCM_ISCR_FUFC_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 9711 #define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
AnnaBridge 171:3a7713b1edbc 9712 #define MCM_ISCR_FIXC_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 9713 #define MCM_ISCR_FIXC_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 9714 #define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
AnnaBridge 171:3a7713b1edbc 9715 #define MCM_ISCR_FIDC_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 9716 #define MCM_ISCR_FIDC_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 9717 #define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
AnnaBridge 171:3a7713b1edbc 9718 #define MCM_ISCR_FIOCE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 9719 #define MCM_ISCR_FIOCE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9720 #define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
AnnaBridge 171:3a7713b1edbc 9721 #define MCM_ISCR_FDZCE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 9722 #define MCM_ISCR_FDZCE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 9723 #define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
AnnaBridge 171:3a7713b1edbc 9724 #define MCM_ISCR_FOFCE_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 9725 #define MCM_ISCR_FOFCE_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 9726 #define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
AnnaBridge 171:3a7713b1edbc 9727 #define MCM_ISCR_FUFCE_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 9728 #define MCM_ISCR_FUFCE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 9729 #define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
AnnaBridge 171:3a7713b1edbc 9730 #define MCM_ISCR_FIXCE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 9731 #define MCM_ISCR_FIXCE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 9732 #define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
AnnaBridge 171:3a7713b1edbc 9733 #define MCM_ISCR_FIDCE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 9734 #define MCM_ISCR_FIDCE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 9735 #define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
AnnaBridge 171:3a7713b1edbc 9736
AnnaBridge 171:3a7713b1edbc 9737 /*! @name ETBCC - ETB Counter Control register */
AnnaBridge 171:3a7713b1edbc 9738 #define MCM_ETBCC_CNTEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9739 #define MCM_ETBCC_CNTEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9740 #define MCM_ETBCC_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)
AnnaBridge 171:3a7713b1edbc 9741 #define MCM_ETBCC_RSPT_MASK (0x6U)
AnnaBridge 171:3a7713b1edbc 9742 #define MCM_ETBCC_RSPT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9743 #define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)
AnnaBridge 171:3a7713b1edbc 9744 #define MCM_ETBCC_RLRQ_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9745 #define MCM_ETBCC_RLRQ_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9746 #define MCM_ETBCC_RLRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)
AnnaBridge 171:3a7713b1edbc 9747 #define MCM_ETBCC_ETDIS_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9748 #define MCM_ETBCC_ETDIS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9749 #define MCM_ETBCC_ETDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)
AnnaBridge 171:3a7713b1edbc 9750 #define MCM_ETBCC_ITDIS_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 9751 #define MCM_ETBCC_ITDIS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9752 #define MCM_ETBCC_ITDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)
AnnaBridge 171:3a7713b1edbc 9753
AnnaBridge 171:3a7713b1edbc 9754 /*! @name ETBRL - ETB Reload register */
AnnaBridge 171:3a7713b1edbc 9755 #define MCM_ETBRL_RELOAD_MASK (0x7FFU)
AnnaBridge 171:3a7713b1edbc 9756 #define MCM_ETBRL_RELOAD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9757 #define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK)
AnnaBridge 171:3a7713b1edbc 9758
AnnaBridge 171:3a7713b1edbc 9759 /*! @name ETBCNT - ETB Counter Value register */
AnnaBridge 171:3a7713b1edbc 9760 #define MCM_ETBCNT_COUNTER_MASK (0x7FFU)
AnnaBridge 171:3a7713b1edbc 9761 #define MCM_ETBCNT_COUNTER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9762 #define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK)
AnnaBridge 171:3a7713b1edbc 9763
AnnaBridge 171:3a7713b1edbc 9764 /*! @name FADR - Fault address register */
AnnaBridge 171:3a7713b1edbc 9765 #define MCM_FADR_ADDRESS_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 9766 #define MCM_FADR_ADDRESS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9767 #define MCM_FADR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK)
AnnaBridge 171:3a7713b1edbc 9768
AnnaBridge 171:3a7713b1edbc 9769 /*! @name FATR - Fault attributes register */
AnnaBridge 171:3a7713b1edbc 9770 #define MCM_FATR_BEDA_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9771 #define MCM_FATR_BEDA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9772 #define MCM_FATR_BEDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK)
AnnaBridge 171:3a7713b1edbc 9773 #define MCM_FATR_BEMD_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9774 #define MCM_FATR_BEMD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9775 #define MCM_FATR_BEMD(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK)
AnnaBridge 171:3a7713b1edbc 9776 #define MCM_FATR_BESZ_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 9777 #define MCM_FATR_BESZ_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9778 #define MCM_FATR_BESZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK)
AnnaBridge 171:3a7713b1edbc 9779 #define MCM_FATR_BEWT_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9780 #define MCM_FATR_BEWT_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9781 #define MCM_FATR_BEWT(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK)
AnnaBridge 171:3a7713b1edbc 9782 #define MCM_FATR_BEMN_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 9783 #define MCM_FATR_BEMN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9784 #define MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK)
AnnaBridge 171:3a7713b1edbc 9785 #define MCM_FATR_BEOVR_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 9786 #define MCM_FATR_BEOVR_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 9787 #define MCM_FATR_BEOVR(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK)
AnnaBridge 171:3a7713b1edbc 9788
AnnaBridge 171:3a7713b1edbc 9789 /*! @name FDR - Fault data register */
AnnaBridge 171:3a7713b1edbc 9790 #define MCM_FDR_DATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 9791 #define MCM_FDR_DATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9792 #define MCM_FDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK)
AnnaBridge 171:3a7713b1edbc 9793
AnnaBridge 171:3a7713b1edbc 9794 /*! @name PID - Process ID register */
AnnaBridge 171:3a7713b1edbc 9795 #define MCM_PID_PID_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9796 #define MCM_PID_PID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9797 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)
AnnaBridge 171:3a7713b1edbc 9798
AnnaBridge 171:3a7713b1edbc 9799 /*! @name CPO - Compute Operation Control Register */
AnnaBridge 171:3a7713b1edbc 9800 #define MCM_CPO_CPOREQ_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9801 #define MCM_CPO_CPOREQ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9802 #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
AnnaBridge 171:3a7713b1edbc 9803 #define MCM_CPO_CPOACK_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9804 #define MCM_CPO_CPOACK_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9805 #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
AnnaBridge 171:3a7713b1edbc 9806 #define MCM_CPO_CPOWOI_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9807 #define MCM_CPO_CPOWOI_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9808 #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
AnnaBridge 171:3a7713b1edbc 9809
AnnaBridge 171:3a7713b1edbc 9810
AnnaBridge 171:3a7713b1edbc 9811 /*!
AnnaBridge 171:3a7713b1edbc 9812 * @}
AnnaBridge 171:3a7713b1edbc 9813 */ /* end of group MCM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 9814
AnnaBridge 171:3a7713b1edbc 9815
AnnaBridge 171:3a7713b1edbc 9816 /* MCM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 9817 /** Peripheral MCM base address */
AnnaBridge 171:3a7713b1edbc 9818 #define MCM_BASE (0xE0080000u)
AnnaBridge 171:3a7713b1edbc 9819 /** Peripheral MCM base pointer */
AnnaBridge 171:3a7713b1edbc 9820 #define MCM ((MCM_Type *)MCM_BASE)
AnnaBridge 171:3a7713b1edbc 9821 /** Array initializer of MCM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 9822 #define MCM_BASE_ADDRS { MCM_BASE }
AnnaBridge 171:3a7713b1edbc 9823 /** Array initializer of MCM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 9824 #define MCM_BASE_PTRS { MCM }
AnnaBridge 171:3a7713b1edbc 9825 /** Interrupt vectors for the MCM peripheral type */
AnnaBridge 171:3a7713b1edbc 9826 #define MCM_IRQS { MCM_IRQn }
AnnaBridge 171:3a7713b1edbc 9827
AnnaBridge 171:3a7713b1edbc 9828 /*!
AnnaBridge 171:3a7713b1edbc 9829 * @}
AnnaBridge 171:3a7713b1edbc 9830 */ /* end of group MCM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 9831
AnnaBridge 171:3a7713b1edbc 9832
AnnaBridge 171:3a7713b1edbc 9833 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9834 -- NV Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9835 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9836
AnnaBridge 171:3a7713b1edbc 9837 /*!
AnnaBridge 171:3a7713b1edbc 9838 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9839 * @{
AnnaBridge 171:3a7713b1edbc 9840 */
AnnaBridge 171:3a7713b1edbc 9841
AnnaBridge 171:3a7713b1edbc 9842 /** NV - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 9843 typedef struct {
AnnaBridge 171:3a7713b1edbc 9844 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 9845 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 9846 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 9847 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 9848 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 9849 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 9850 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 9851 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 9852 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 9853 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 9854 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 9855 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 9856 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 9857 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 9858 __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
AnnaBridge 171:3a7713b1edbc 9859 __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
AnnaBridge 171:3a7713b1edbc 9860 } NV_Type;
AnnaBridge 171:3a7713b1edbc 9861
AnnaBridge 171:3a7713b1edbc 9862 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9863 -- NV Register Masks
AnnaBridge 171:3a7713b1edbc 9864 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9865
AnnaBridge 171:3a7713b1edbc 9866 /*!
AnnaBridge 171:3a7713b1edbc 9867 * @addtogroup NV_Register_Masks NV Register Masks
AnnaBridge 171:3a7713b1edbc 9868 * @{
AnnaBridge 171:3a7713b1edbc 9869 */
AnnaBridge 171:3a7713b1edbc 9870
AnnaBridge 171:3a7713b1edbc 9871 /*! @name BACKKEY3 - Backdoor Comparison Key 3. */
AnnaBridge 171:3a7713b1edbc 9872 #define NV_BACKKEY3_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9873 #define NV_BACKKEY3_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9874 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 9875
AnnaBridge 171:3a7713b1edbc 9876 /*! @name BACKKEY2 - Backdoor Comparison Key 2. */
AnnaBridge 171:3a7713b1edbc 9877 #define NV_BACKKEY2_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9878 #define NV_BACKKEY2_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9879 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 9880
AnnaBridge 171:3a7713b1edbc 9881 /*! @name BACKKEY1 - Backdoor Comparison Key 1. */
AnnaBridge 171:3a7713b1edbc 9882 #define NV_BACKKEY1_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9883 #define NV_BACKKEY1_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9884 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 9885
AnnaBridge 171:3a7713b1edbc 9886 /*! @name BACKKEY0 - Backdoor Comparison Key 0. */
AnnaBridge 171:3a7713b1edbc 9887 #define NV_BACKKEY0_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9888 #define NV_BACKKEY0_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9889 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 9890
AnnaBridge 171:3a7713b1edbc 9891 /*! @name BACKKEY7 - Backdoor Comparison Key 7. */
AnnaBridge 171:3a7713b1edbc 9892 #define NV_BACKKEY7_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9893 #define NV_BACKKEY7_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9894 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 9895
AnnaBridge 171:3a7713b1edbc 9896 /*! @name BACKKEY6 - Backdoor Comparison Key 6. */
AnnaBridge 171:3a7713b1edbc 9897 #define NV_BACKKEY6_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9898 #define NV_BACKKEY6_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9899 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 9900
AnnaBridge 171:3a7713b1edbc 9901 /*! @name BACKKEY5 - Backdoor Comparison Key 5. */
AnnaBridge 171:3a7713b1edbc 9902 #define NV_BACKKEY5_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9903 #define NV_BACKKEY5_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9904 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 9905
AnnaBridge 171:3a7713b1edbc 9906 /*! @name BACKKEY4 - Backdoor Comparison Key 4. */
AnnaBridge 171:3a7713b1edbc 9907 #define NV_BACKKEY4_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9908 #define NV_BACKKEY4_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9909 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 9910
AnnaBridge 171:3a7713b1edbc 9911 /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
AnnaBridge 171:3a7713b1edbc 9912 #define NV_FPROT3_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9913 #define NV_FPROT3_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9914 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 9915
AnnaBridge 171:3a7713b1edbc 9916 /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
AnnaBridge 171:3a7713b1edbc 9917 #define NV_FPROT2_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9918 #define NV_FPROT2_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9919 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 9920
AnnaBridge 171:3a7713b1edbc 9921 /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
AnnaBridge 171:3a7713b1edbc 9922 #define NV_FPROT1_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9923 #define NV_FPROT1_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9924 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 9925
AnnaBridge 171:3a7713b1edbc 9926 /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
AnnaBridge 171:3a7713b1edbc 9927 #define NV_FPROT0_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9928 #define NV_FPROT0_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9929 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 9930
AnnaBridge 171:3a7713b1edbc 9931 /*! @name FSEC - Non-volatile Flash Security Register */
AnnaBridge 171:3a7713b1edbc 9932 #define NV_FSEC_SEC_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 9933 #define NV_FSEC_SEC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9934 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
AnnaBridge 171:3a7713b1edbc 9935 #define NV_FSEC_FSLACC_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 9936 #define NV_FSEC_FSLACC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9937 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
AnnaBridge 171:3a7713b1edbc 9938 #define NV_FSEC_MEEN_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 9939 #define NV_FSEC_MEEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9940 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
AnnaBridge 171:3a7713b1edbc 9941 #define NV_FSEC_KEYEN_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 9942 #define NV_FSEC_KEYEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 9943 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
AnnaBridge 171:3a7713b1edbc 9944
AnnaBridge 171:3a7713b1edbc 9945 /*! @name FOPT - Non-volatile Flash Option Register */
AnnaBridge 171:3a7713b1edbc 9946 #define NV_FOPT_LPBOOT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9947 #define NV_FOPT_LPBOOT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9948 #define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
AnnaBridge 171:3a7713b1edbc 9949 #define NV_FOPT_EZPORT_DIS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9950 #define NV_FOPT_EZPORT_DIS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9951 #define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 9952 #define NV_FOPT_NMI_DIS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9953 #define NV_FOPT_NMI_DIS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9954 #define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 9955
AnnaBridge 171:3a7713b1edbc 9956 /*! @name FEPROT - Non-volatile EERAM Protection Register */
AnnaBridge 171:3a7713b1edbc 9957 #define NV_FEPROT_EPROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9958 #define NV_FEPROT_EPROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9959 #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK)
AnnaBridge 171:3a7713b1edbc 9960
AnnaBridge 171:3a7713b1edbc 9961 /*! @name FDPROT - Non-volatile D-Flash Protection Register */
AnnaBridge 171:3a7713b1edbc 9962 #define NV_FDPROT_DPROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9963 #define NV_FDPROT_DPROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9964 #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK)
AnnaBridge 171:3a7713b1edbc 9965
AnnaBridge 171:3a7713b1edbc 9966
AnnaBridge 171:3a7713b1edbc 9967 /*!
AnnaBridge 171:3a7713b1edbc 9968 * @}
AnnaBridge 171:3a7713b1edbc 9969 */ /* end of group NV_Register_Masks */
AnnaBridge 171:3a7713b1edbc 9970
AnnaBridge 171:3a7713b1edbc 9971
AnnaBridge 171:3a7713b1edbc 9972 /* NV - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 9973 /** Peripheral FTFE_FlashConfig base address */
AnnaBridge 171:3a7713b1edbc 9974 #define FTFE_FlashConfig_BASE (0x400u)
AnnaBridge 171:3a7713b1edbc 9975 /** Peripheral FTFE_FlashConfig base pointer */
AnnaBridge 171:3a7713b1edbc 9976 #define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE)
AnnaBridge 171:3a7713b1edbc 9977 /** Array initializer of NV peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 9978 #define NV_BASE_ADDRS { FTFE_FlashConfig_BASE }
AnnaBridge 171:3a7713b1edbc 9979 /** Array initializer of NV peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 9980 #define NV_BASE_PTRS { FTFE_FlashConfig }
AnnaBridge 171:3a7713b1edbc 9981
AnnaBridge 171:3a7713b1edbc 9982 /*!
AnnaBridge 171:3a7713b1edbc 9983 * @}
AnnaBridge 171:3a7713b1edbc 9984 */ /* end of group NV_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 9985
AnnaBridge 171:3a7713b1edbc 9986
AnnaBridge 171:3a7713b1edbc 9987 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9988 -- OSC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9989 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9990
AnnaBridge 171:3a7713b1edbc 9991 /*!
AnnaBridge 171:3a7713b1edbc 9992 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9993 * @{
AnnaBridge 171:3a7713b1edbc 9994 */
AnnaBridge 171:3a7713b1edbc 9995
AnnaBridge 171:3a7713b1edbc 9996 /** OSC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 9997 typedef struct {
AnnaBridge 171:3a7713b1edbc 9998 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 9999 uint8_t RESERVED_0[1];
AnnaBridge 171:3a7713b1edbc 10000 __IO uint8_t DIV; /**< OSC_DIV, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 10001 } OSC_Type;
AnnaBridge 171:3a7713b1edbc 10002
AnnaBridge 171:3a7713b1edbc 10003 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10004 -- OSC Register Masks
AnnaBridge 171:3a7713b1edbc 10005 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10006
AnnaBridge 171:3a7713b1edbc 10007 /*!
AnnaBridge 171:3a7713b1edbc 10008 * @addtogroup OSC_Register_Masks OSC Register Masks
AnnaBridge 171:3a7713b1edbc 10009 * @{
AnnaBridge 171:3a7713b1edbc 10010 */
AnnaBridge 171:3a7713b1edbc 10011
AnnaBridge 171:3a7713b1edbc 10012 /*! @name CR - OSC Control Register */
AnnaBridge 171:3a7713b1edbc 10013 #define OSC_CR_SC16P_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10014 #define OSC_CR_SC16P_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10015 #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
AnnaBridge 171:3a7713b1edbc 10016 #define OSC_CR_SC8P_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10017 #define OSC_CR_SC8P_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10018 #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
AnnaBridge 171:3a7713b1edbc 10019 #define OSC_CR_SC4P_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 10020 #define OSC_CR_SC4P_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10021 #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
AnnaBridge 171:3a7713b1edbc 10022 #define OSC_CR_SC2P_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 10023 #define OSC_CR_SC2P_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 10024 #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
AnnaBridge 171:3a7713b1edbc 10025 #define OSC_CR_EREFSTEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 10026 #define OSC_CR_EREFSTEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 10027 #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
AnnaBridge 171:3a7713b1edbc 10028 #define OSC_CR_ERCLKEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 10029 #define OSC_CR_ERCLKEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 10030 #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
AnnaBridge 171:3a7713b1edbc 10031
AnnaBridge 171:3a7713b1edbc 10032 /*! @name DIV - OSC_DIV */
AnnaBridge 171:3a7713b1edbc 10033 #define OSC_DIV_ERPS_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 10034 #define OSC_DIV_ERPS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 10035 #define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x)) << OSC_DIV_ERPS_SHIFT)) & OSC_DIV_ERPS_MASK)
AnnaBridge 171:3a7713b1edbc 10036
AnnaBridge 171:3a7713b1edbc 10037
AnnaBridge 171:3a7713b1edbc 10038 /*!
AnnaBridge 171:3a7713b1edbc 10039 * @}
AnnaBridge 171:3a7713b1edbc 10040 */ /* end of group OSC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 10041
AnnaBridge 171:3a7713b1edbc 10042
AnnaBridge 171:3a7713b1edbc 10043 /* OSC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 10044 /** Peripheral OSC base address */
AnnaBridge 171:3a7713b1edbc 10045 #define OSC_BASE (0x40065000u)
AnnaBridge 171:3a7713b1edbc 10046 /** Peripheral OSC base pointer */
AnnaBridge 171:3a7713b1edbc 10047 #define OSC ((OSC_Type *)OSC_BASE)
AnnaBridge 171:3a7713b1edbc 10048 /** Array initializer of OSC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 10049 #define OSC_BASE_ADDRS { OSC_BASE }
AnnaBridge 171:3a7713b1edbc 10050 /** Array initializer of OSC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 10051 #define OSC_BASE_PTRS { OSC }
AnnaBridge 171:3a7713b1edbc 10052
AnnaBridge 171:3a7713b1edbc 10053 /*!
AnnaBridge 171:3a7713b1edbc 10054 * @}
AnnaBridge 171:3a7713b1edbc 10055 */ /* end of group OSC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 10056
AnnaBridge 171:3a7713b1edbc 10057
AnnaBridge 171:3a7713b1edbc 10058 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10059 -- PDB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10060 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10061
AnnaBridge 171:3a7713b1edbc 10062 /*!
AnnaBridge 171:3a7713b1edbc 10063 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10064 * @{
AnnaBridge 171:3a7713b1edbc 10065 */
AnnaBridge 171:3a7713b1edbc 10066
AnnaBridge 171:3a7713b1edbc 10067 /** PDB - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 10068 typedef struct {
AnnaBridge 171:3a7713b1edbc 10069 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 10070 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 10071 __I uint32_t CNT; /**< Counter register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 10072 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 10073 struct { /* offset: 0x10, array step: 0x28 */
AnnaBridge 171:3a7713b1edbc 10074 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
AnnaBridge 171:3a7713b1edbc 10075 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
AnnaBridge 171:3a7713b1edbc 10076 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
AnnaBridge 171:3a7713b1edbc 10077 uint8_t RESERVED_0[24];
AnnaBridge 171:3a7713b1edbc 10078 } CH[2];
AnnaBridge 171:3a7713b1edbc 10079 uint8_t RESERVED_0[240];
AnnaBridge 171:3a7713b1edbc 10080 struct { /* offset: 0x150, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 10081 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 10082 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 10083 } DAC[2];
AnnaBridge 171:3a7713b1edbc 10084 uint8_t RESERVED_1[48];
AnnaBridge 171:3a7713b1edbc 10085 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
AnnaBridge 171:3a7713b1edbc 10086 __IO uint32_t PODLY[4]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 10087 } PDB_Type;
AnnaBridge 171:3a7713b1edbc 10088
AnnaBridge 171:3a7713b1edbc 10089 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10090 -- PDB Register Masks
AnnaBridge 171:3a7713b1edbc 10091 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10092
AnnaBridge 171:3a7713b1edbc 10093 /*!
AnnaBridge 171:3a7713b1edbc 10094 * @addtogroup PDB_Register_Masks PDB Register Masks
AnnaBridge 171:3a7713b1edbc 10095 * @{
AnnaBridge 171:3a7713b1edbc 10096 */
AnnaBridge 171:3a7713b1edbc 10097
AnnaBridge 171:3a7713b1edbc 10098 /*! @name SC - Status and Control register */
AnnaBridge 171:3a7713b1edbc 10099 #define PDB_SC_LDOK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10100 #define PDB_SC_LDOK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10101 #define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
AnnaBridge 171:3a7713b1edbc 10102 #define PDB_SC_CONT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10103 #define PDB_SC_CONT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10104 #define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
AnnaBridge 171:3a7713b1edbc 10105 #define PDB_SC_MULT_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 10106 #define PDB_SC_MULT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10107 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
AnnaBridge 171:3a7713b1edbc 10108 #define PDB_SC_PDBIE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 10109 #define PDB_SC_PDBIE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 10110 #define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
AnnaBridge 171:3a7713b1edbc 10111 #define PDB_SC_PDBIF_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 10112 #define PDB_SC_PDBIF_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 10113 #define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
AnnaBridge 171:3a7713b1edbc 10114 #define PDB_SC_PDBEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 10115 #define PDB_SC_PDBEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 10116 #define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
AnnaBridge 171:3a7713b1edbc 10117 #define PDB_SC_TRGSEL_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 10118 #define PDB_SC_TRGSEL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10119 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 10120 #define PDB_SC_PRESCALER_MASK (0x7000U)
AnnaBridge 171:3a7713b1edbc 10121 #define PDB_SC_PRESCALER_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10122 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
AnnaBridge 171:3a7713b1edbc 10123 #define PDB_SC_DMAEN_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 10124 #define PDB_SC_DMAEN_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 10125 #define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 10126 #define PDB_SC_SWTRIG_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 10127 #define PDB_SC_SWTRIG_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10128 #define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
AnnaBridge 171:3a7713b1edbc 10129 #define PDB_SC_PDBEIE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 10130 #define PDB_SC_PDBEIE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 10131 #define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
AnnaBridge 171:3a7713b1edbc 10132 #define PDB_SC_LDMOD_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 10133 #define PDB_SC_LDMOD_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 10134 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
AnnaBridge 171:3a7713b1edbc 10135
AnnaBridge 171:3a7713b1edbc 10136 /*! @name MOD - Modulus register */
AnnaBridge 171:3a7713b1edbc 10137 #define PDB_MOD_MOD_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 10138 #define PDB_MOD_MOD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10139 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
AnnaBridge 171:3a7713b1edbc 10140
AnnaBridge 171:3a7713b1edbc 10141 /*! @name CNT - Counter register */
AnnaBridge 171:3a7713b1edbc 10142 #define PDB_CNT_CNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 10143 #define PDB_CNT_CNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10144 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
AnnaBridge 171:3a7713b1edbc 10145
AnnaBridge 171:3a7713b1edbc 10146 /*! @name IDLY - Interrupt Delay register */
AnnaBridge 171:3a7713b1edbc 10147 #define PDB_IDLY_IDLY_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 10148 #define PDB_IDLY_IDLY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10149 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
AnnaBridge 171:3a7713b1edbc 10150
AnnaBridge 171:3a7713b1edbc 10151 /*! @name C1 - Channel n Control register 1 */
AnnaBridge 171:3a7713b1edbc 10152 #define PDB_C1_EN_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 10153 #define PDB_C1_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10154 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10155 #define PDB_C1_TOS_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 10156 #define PDB_C1_TOS_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10157 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
AnnaBridge 171:3a7713b1edbc 10158 #define PDB_C1_BB_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 10159 #define PDB_C1_BB_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10160 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
AnnaBridge 171:3a7713b1edbc 10161
AnnaBridge 171:3a7713b1edbc 10162 /* The count of PDB_C1 */
AnnaBridge 171:3a7713b1edbc 10163 #define PDB_C1_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 10164
AnnaBridge 171:3a7713b1edbc 10165 /*! @name S - Channel n Status register */
AnnaBridge 171:3a7713b1edbc 10166 #define PDB_S_ERR_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 10167 #define PDB_S_ERR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10168 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
AnnaBridge 171:3a7713b1edbc 10169 #define PDB_S_CF_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 10170 #define PDB_S_CF_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10171 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
AnnaBridge 171:3a7713b1edbc 10172
AnnaBridge 171:3a7713b1edbc 10173 /* The count of PDB_S */
AnnaBridge 171:3a7713b1edbc 10174 #define PDB_S_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 10175
AnnaBridge 171:3a7713b1edbc 10176 /*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */
AnnaBridge 171:3a7713b1edbc 10177 #define PDB_DLY_DLY_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 10178 #define PDB_DLY_DLY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10179 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
AnnaBridge 171:3a7713b1edbc 10180
AnnaBridge 171:3a7713b1edbc 10181 /* The count of PDB_DLY */
AnnaBridge 171:3a7713b1edbc 10182 #define PDB_DLY_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 10183
AnnaBridge 171:3a7713b1edbc 10184 /* The count of PDB_DLY */
AnnaBridge 171:3a7713b1edbc 10185 #define PDB_DLY_COUNT2 (2U)
AnnaBridge 171:3a7713b1edbc 10186
AnnaBridge 171:3a7713b1edbc 10187 /*! @name INTC - DAC Interval Trigger n Control register */
AnnaBridge 171:3a7713b1edbc 10188 #define PDB_INTC_TOE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10189 #define PDB_INTC_TOE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10190 #define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
AnnaBridge 171:3a7713b1edbc 10191 #define PDB_INTC_EXT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10192 #define PDB_INTC_EXT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10193 #define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
AnnaBridge 171:3a7713b1edbc 10194
AnnaBridge 171:3a7713b1edbc 10195 /* The count of PDB_INTC */
AnnaBridge 171:3a7713b1edbc 10196 #define PDB_INTC_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 10197
AnnaBridge 171:3a7713b1edbc 10198 /*! @name INT - DAC Interval n register */
AnnaBridge 171:3a7713b1edbc 10199 #define PDB_INT_INT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 10200 #define PDB_INT_INT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10201 #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
AnnaBridge 171:3a7713b1edbc 10202
AnnaBridge 171:3a7713b1edbc 10203 /* The count of PDB_INT */
AnnaBridge 171:3a7713b1edbc 10204 #define PDB_INT_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 10205
AnnaBridge 171:3a7713b1edbc 10206 /*! @name POEN - Pulse-Out n Enable register */
AnnaBridge 171:3a7713b1edbc 10207 #define PDB_POEN_POEN_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 10208 #define PDB_POEN_POEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10209 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
AnnaBridge 171:3a7713b1edbc 10210
AnnaBridge 171:3a7713b1edbc 10211 /*! @name PODLY - Pulse-Out n Delay register */
AnnaBridge 171:3a7713b1edbc 10212 #define PDB_PODLY_DLY2_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 10213 #define PDB_PODLY_DLY2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10214 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
AnnaBridge 171:3a7713b1edbc 10215 #define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 10216 #define PDB_PODLY_DLY1_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10217 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
AnnaBridge 171:3a7713b1edbc 10218
AnnaBridge 171:3a7713b1edbc 10219 /* The count of PDB_PODLY */
AnnaBridge 171:3a7713b1edbc 10220 #define PDB_PODLY_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 10221
AnnaBridge 171:3a7713b1edbc 10222
AnnaBridge 171:3a7713b1edbc 10223 /*!
AnnaBridge 171:3a7713b1edbc 10224 * @}
AnnaBridge 171:3a7713b1edbc 10225 */ /* end of group PDB_Register_Masks */
AnnaBridge 171:3a7713b1edbc 10226
AnnaBridge 171:3a7713b1edbc 10227
AnnaBridge 171:3a7713b1edbc 10228 /* PDB - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 10229 /** Peripheral PDB0 base address */
AnnaBridge 171:3a7713b1edbc 10230 #define PDB0_BASE (0x40036000u)
AnnaBridge 171:3a7713b1edbc 10231 /** Peripheral PDB0 base pointer */
AnnaBridge 171:3a7713b1edbc 10232 #define PDB0 ((PDB_Type *)PDB0_BASE)
AnnaBridge 171:3a7713b1edbc 10233 /** Array initializer of PDB peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 10234 #define PDB_BASE_ADDRS { PDB0_BASE }
AnnaBridge 171:3a7713b1edbc 10235 /** Array initializer of PDB peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 10236 #define PDB_BASE_PTRS { PDB0 }
AnnaBridge 171:3a7713b1edbc 10237 /** Interrupt vectors for the PDB peripheral type */
AnnaBridge 171:3a7713b1edbc 10238 #define PDB_IRQS { PDB0_IRQn }
AnnaBridge 171:3a7713b1edbc 10239
AnnaBridge 171:3a7713b1edbc 10240 /*!
AnnaBridge 171:3a7713b1edbc 10241 * @}
AnnaBridge 171:3a7713b1edbc 10242 */ /* end of group PDB_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 10243
AnnaBridge 171:3a7713b1edbc 10244
AnnaBridge 171:3a7713b1edbc 10245 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10246 -- PIT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10247 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10248
AnnaBridge 171:3a7713b1edbc 10249 /*!
AnnaBridge 171:3a7713b1edbc 10250 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10251 * @{
AnnaBridge 171:3a7713b1edbc 10252 */
AnnaBridge 171:3a7713b1edbc 10253
AnnaBridge 171:3a7713b1edbc 10254 /** PIT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 10255 typedef struct {
AnnaBridge 171:3a7713b1edbc 10256 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 10257 uint8_t RESERVED_0[220];
AnnaBridge 171:3a7713b1edbc 10258 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
AnnaBridge 171:3a7713b1edbc 10259 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
AnnaBridge 171:3a7713b1edbc 10260 uint8_t RESERVED_1[24];
AnnaBridge 171:3a7713b1edbc 10261 struct { /* offset: 0x100, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 10262 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 10263 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 10264 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 10265 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 10266 } CHANNEL[4];
AnnaBridge 171:3a7713b1edbc 10267 } PIT_Type;
AnnaBridge 171:3a7713b1edbc 10268
AnnaBridge 171:3a7713b1edbc 10269 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10270 -- PIT Register Masks
AnnaBridge 171:3a7713b1edbc 10271 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10272
AnnaBridge 171:3a7713b1edbc 10273 /*!
AnnaBridge 171:3a7713b1edbc 10274 * @addtogroup PIT_Register_Masks PIT Register Masks
AnnaBridge 171:3a7713b1edbc 10275 * @{
AnnaBridge 171:3a7713b1edbc 10276 */
AnnaBridge 171:3a7713b1edbc 10277
AnnaBridge 171:3a7713b1edbc 10278 /*! @name MCR - PIT Module Control Register */
AnnaBridge 171:3a7713b1edbc 10279 #define PIT_MCR_FRZ_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10280 #define PIT_MCR_FRZ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10281 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
AnnaBridge 171:3a7713b1edbc 10282 #define PIT_MCR_MDIS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10283 #define PIT_MCR_MDIS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10284 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
AnnaBridge 171:3a7713b1edbc 10285
AnnaBridge 171:3a7713b1edbc 10286 /*! @name LTMR64H - PIT Upper Lifetime Timer Register */
AnnaBridge 171:3a7713b1edbc 10287 #define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 10288 #define PIT_LTMR64H_LTH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10289 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
AnnaBridge 171:3a7713b1edbc 10290
AnnaBridge 171:3a7713b1edbc 10291 /*! @name LTMR64L - PIT Lower Lifetime Timer Register */
AnnaBridge 171:3a7713b1edbc 10292 #define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 10293 #define PIT_LTMR64L_LTL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10294 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
AnnaBridge 171:3a7713b1edbc 10295
AnnaBridge 171:3a7713b1edbc 10296 /*! @name LDVAL - Timer Load Value Register */
AnnaBridge 171:3a7713b1edbc 10297 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 10298 #define PIT_LDVAL_TSV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10299 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
AnnaBridge 171:3a7713b1edbc 10300
AnnaBridge 171:3a7713b1edbc 10301 /* The count of PIT_LDVAL */
AnnaBridge 171:3a7713b1edbc 10302 #define PIT_LDVAL_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 10303
AnnaBridge 171:3a7713b1edbc 10304 /*! @name CVAL - Current Timer Value Register */
AnnaBridge 171:3a7713b1edbc 10305 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 10306 #define PIT_CVAL_TVL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10307 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
AnnaBridge 171:3a7713b1edbc 10308
AnnaBridge 171:3a7713b1edbc 10309 /* The count of PIT_CVAL */
AnnaBridge 171:3a7713b1edbc 10310 #define PIT_CVAL_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 10311
AnnaBridge 171:3a7713b1edbc 10312 /*! @name TCTRL - Timer Control Register */
AnnaBridge 171:3a7713b1edbc 10313 #define PIT_TCTRL_TEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10314 #define PIT_TCTRL_TEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10315 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
AnnaBridge 171:3a7713b1edbc 10316 #define PIT_TCTRL_TIE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10317 #define PIT_TCTRL_TIE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10318 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
AnnaBridge 171:3a7713b1edbc 10319 #define PIT_TCTRL_CHN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 10320 #define PIT_TCTRL_CHN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10321 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
AnnaBridge 171:3a7713b1edbc 10322
AnnaBridge 171:3a7713b1edbc 10323 /* The count of PIT_TCTRL */
AnnaBridge 171:3a7713b1edbc 10324 #define PIT_TCTRL_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 10325
AnnaBridge 171:3a7713b1edbc 10326 /*! @name TFLG - Timer Flag Register */
AnnaBridge 171:3a7713b1edbc 10327 #define PIT_TFLG_TIF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10328 #define PIT_TFLG_TIF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10329 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
AnnaBridge 171:3a7713b1edbc 10330
AnnaBridge 171:3a7713b1edbc 10331 /* The count of PIT_TFLG */
AnnaBridge 171:3a7713b1edbc 10332 #define PIT_TFLG_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 10333
AnnaBridge 171:3a7713b1edbc 10334
AnnaBridge 171:3a7713b1edbc 10335 /*!
AnnaBridge 171:3a7713b1edbc 10336 * @}
AnnaBridge 171:3a7713b1edbc 10337 */ /* end of group PIT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 10338
AnnaBridge 171:3a7713b1edbc 10339
AnnaBridge 171:3a7713b1edbc 10340 /* PIT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 10341 /** Peripheral PIT base address */
AnnaBridge 171:3a7713b1edbc 10342 #define PIT_BASE (0x40037000u)
AnnaBridge 171:3a7713b1edbc 10343 /** Peripheral PIT base pointer */
AnnaBridge 171:3a7713b1edbc 10344 #define PIT ((PIT_Type *)PIT_BASE)
AnnaBridge 171:3a7713b1edbc 10345 /** Array initializer of PIT peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 10346 #define PIT_BASE_ADDRS { PIT_BASE }
AnnaBridge 171:3a7713b1edbc 10347 /** Array initializer of PIT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 10348 #define PIT_BASE_PTRS { PIT }
AnnaBridge 171:3a7713b1edbc 10349 /** Interrupt vectors for the PIT peripheral type */
AnnaBridge 171:3a7713b1edbc 10350 #define PIT_IRQS { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } }
AnnaBridge 171:3a7713b1edbc 10351
AnnaBridge 171:3a7713b1edbc 10352 /*!
AnnaBridge 171:3a7713b1edbc 10353 * @}
AnnaBridge 171:3a7713b1edbc 10354 */ /* end of group PIT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 10355
AnnaBridge 171:3a7713b1edbc 10356
AnnaBridge 171:3a7713b1edbc 10357 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10358 -- PMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10359 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10360
AnnaBridge 171:3a7713b1edbc 10361 /*!
AnnaBridge 171:3a7713b1edbc 10362 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10363 * @{
AnnaBridge 171:3a7713b1edbc 10364 */
AnnaBridge 171:3a7713b1edbc 10365
AnnaBridge 171:3a7713b1edbc 10366 /** PMC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 10367 typedef struct {
AnnaBridge 171:3a7713b1edbc 10368 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 10369 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 10370 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 10371 } PMC_Type;
AnnaBridge 171:3a7713b1edbc 10372
AnnaBridge 171:3a7713b1edbc 10373 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10374 -- PMC Register Masks
AnnaBridge 171:3a7713b1edbc 10375 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10376
AnnaBridge 171:3a7713b1edbc 10377 /*!
AnnaBridge 171:3a7713b1edbc 10378 * @addtogroup PMC_Register_Masks PMC Register Masks
AnnaBridge 171:3a7713b1edbc 10379 * @{
AnnaBridge 171:3a7713b1edbc 10380 */
AnnaBridge 171:3a7713b1edbc 10381
AnnaBridge 171:3a7713b1edbc 10382 /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
AnnaBridge 171:3a7713b1edbc 10383 #define PMC_LVDSC1_LVDV_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 10384 #define PMC_LVDSC1_LVDV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10385 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
AnnaBridge 171:3a7713b1edbc 10386 #define PMC_LVDSC1_LVDRE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 10387 #define PMC_LVDSC1_LVDRE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10388 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
AnnaBridge 171:3a7713b1edbc 10389 #define PMC_LVDSC1_LVDIE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 10390 #define PMC_LVDSC1_LVDIE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 10391 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
AnnaBridge 171:3a7713b1edbc 10392 #define PMC_LVDSC1_LVDACK_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 10393 #define PMC_LVDSC1_LVDACK_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 10394 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
AnnaBridge 171:3a7713b1edbc 10395 #define PMC_LVDSC1_LVDF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 10396 #define PMC_LVDSC1_LVDF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 10397 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
AnnaBridge 171:3a7713b1edbc 10398
AnnaBridge 171:3a7713b1edbc 10399 /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
AnnaBridge 171:3a7713b1edbc 10400 #define PMC_LVDSC2_LVWV_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 10401 #define PMC_LVDSC2_LVWV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10402 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
AnnaBridge 171:3a7713b1edbc 10403 #define PMC_LVDSC2_LVWIE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 10404 #define PMC_LVDSC2_LVWIE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 10405 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
AnnaBridge 171:3a7713b1edbc 10406 #define PMC_LVDSC2_LVWACK_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 10407 #define PMC_LVDSC2_LVWACK_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 10408 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
AnnaBridge 171:3a7713b1edbc 10409 #define PMC_LVDSC2_LVWF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 10410 #define PMC_LVDSC2_LVWF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 10411 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
AnnaBridge 171:3a7713b1edbc 10412
AnnaBridge 171:3a7713b1edbc 10413 /*! @name REGSC - Regulator Status And Control register */
AnnaBridge 171:3a7713b1edbc 10414 #define PMC_REGSC_BGBE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10415 #define PMC_REGSC_BGBE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10416 #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
AnnaBridge 171:3a7713b1edbc 10417 #define PMC_REGSC_REGONS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 10418 #define PMC_REGSC_REGONS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10419 #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
AnnaBridge 171:3a7713b1edbc 10420 #define PMC_REGSC_ACKISO_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 10421 #define PMC_REGSC_ACKISO_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 10422 #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
AnnaBridge 171:3a7713b1edbc 10423 #define PMC_REGSC_BGEN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 10424 #define PMC_REGSC_BGEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10425 #define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
AnnaBridge 171:3a7713b1edbc 10426
AnnaBridge 171:3a7713b1edbc 10427
AnnaBridge 171:3a7713b1edbc 10428 /*!
AnnaBridge 171:3a7713b1edbc 10429 * @}
AnnaBridge 171:3a7713b1edbc 10430 */ /* end of group PMC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 10431
AnnaBridge 171:3a7713b1edbc 10432
AnnaBridge 171:3a7713b1edbc 10433 /* PMC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 10434 /** Peripheral PMC base address */
AnnaBridge 171:3a7713b1edbc 10435 #define PMC_BASE (0x4007D000u)
AnnaBridge 171:3a7713b1edbc 10436 /** Peripheral PMC base pointer */
AnnaBridge 171:3a7713b1edbc 10437 #define PMC ((PMC_Type *)PMC_BASE)
AnnaBridge 171:3a7713b1edbc 10438 /** Array initializer of PMC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 10439 #define PMC_BASE_ADDRS { PMC_BASE }
AnnaBridge 171:3a7713b1edbc 10440 /** Array initializer of PMC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 10441 #define PMC_BASE_PTRS { PMC }
AnnaBridge 171:3a7713b1edbc 10442 /** Interrupt vectors for the PMC peripheral type */
AnnaBridge 171:3a7713b1edbc 10443 #define PMC_IRQS { LVD_LVW_IRQn }
AnnaBridge 171:3a7713b1edbc 10444
AnnaBridge 171:3a7713b1edbc 10445 /*!
AnnaBridge 171:3a7713b1edbc 10446 * @}
AnnaBridge 171:3a7713b1edbc 10447 */ /* end of group PMC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 10448
AnnaBridge 171:3a7713b1edbc 10449
AnnaBridge 171:3a7713b1edbc 10450 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10451 -- PORT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10452 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10453
AnnaBridge 171:3a7713b1edbc 10454 /*!
AnnaBridge 171:3a7713b1edbc 10455 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10456 * @{
AnnaBridge 171:3a7713b1edbc 10457 */
AnnaBridge 171:3a7713b1edbc 10458
AnnaBridge 171:3a7713b1edbc 10459 /** PORT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 10460 typedef struct {
AnnaBridge 171:3a7713b1edbc 10461 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 10462 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 10463 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 10464 uint8_t RESERVED_0[24];
AnnaBridge 171:3a7713b1edbc 10465 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
AnnaBridge 171:3a7713b1edbc 10466 uint8_t RESERVED_1[28];
AnnaBridge 171:3a7713b1edbc 10467 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
AnnaBridge 171:3a7713b1edbc 10468 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
AnnaBridge 171:3a7713b1edbc 10469 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
AnnaBridge 171:3a7713b1edbc 10470 } PORT_Type;
AnnaBridge 171:3a7713b1edbc 10471
AnnaBridge 171:3a7713b1edbc 10472 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10473 -- PORT Register Masks
AnnaBridge 171:3a7713b1edbc 10474 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10475
AnnaBridge 171:3a7713b1edbc 10476 /*!
AnnaBridge 171:3a7713b1edbc 10477 * @addtogroup PORT_Register_Masks PORT Register Masks
AnnaBridge 171:3a7713b1edbc 10478 * @{
AnnaBridge 171:3a7713b1edbc 10479 */
AnnaBridge 171:3a7713b1edbc 10480
AnnaBridge 171:3a7713b1edbc 10481 /*! @name PCR - Pin Control Register n */
AnnaBridge 171:3a7713b1edbc 10482 #define PORT_PCR_PS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10483 #define PORT_PCR_PS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10484 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
AnnaBridge 171:3a7713b1edbc 10485 #define PORT_PCR_PE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10486 #define PORT_PCR_PE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10487 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
AnnaBridge 171:3a7713b1edbc 10488 #define PORT_PCR_SRE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 10489 #define PORT_PCR_SRE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10490 #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
AnnaBridge 171:3a7713b1edbc 10491 #define PORT_PCR_PFE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 10492 #define PORT_PCR_PFE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10493 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
AnnaBridge 171:3a7713b1edbc 10494 #define PORT_PCR_ODE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 10495 #define PORT_PCR_ODE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 10496 #define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
AnnaBridge 171:3a7713b1edbc 10497 #define PORT_PCR_DSE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 10498 #define PORT_PCR_DSE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 10499 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
AnnaBridge 171:3a7713b1edbc 10500 #define PORT_PCR_MUX_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 10501 #define PORT_PCR_MUX_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10502 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
AnnaBridge 171:3a7713b1edbc 10503 #define PORT_PCR_LK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 10504 #define PORT_PCR_LK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 10505 #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
AnnaBridge 171:3a7713b1edbc 10506 #define PORT_PCR_IRQC_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 10507 #define PORT_PCR_IRQC_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10508 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
AnnaBridge 171:3a7713b1edbc 10509 #define PORT_PCR_ISF_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 10510 #define PORT_PCR_ISF_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10511 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
AnnaBridge 171:3a7713b1edbc 10512
AnnaBridge 171:3a7713b1edbc 10513 /* The count of PORT_PCR */
AnnaBridge 171:3a7713b1edbc 10514 #define PORT_PCR_COUNT (32U)
AnnaBridge 171:3a7713b1edbc 10515
AnnaBridge 171:3a7713b1edbc 10516 /*! @name GPCLR - Global Pin Control Low Register */
AnnaBridge 171:3a7713b1edbc 10517 #define PORT_GPCLR_GPWD_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 10518 #define PORT_GPCLR_GPWD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10519 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
AnnaBridge 171:3a7713b1edbc 10520 #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 10521 #define PORT_GPCLR_GPWE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10522 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
AnnaBridge 171:3a7713b1edbc 10523
AnnaBridge 171:3a7713b1edbc 10524 /*! @name GPCHR - Global Pin Control High Register */
AnnaBridge 171:3a7713b1edbc 10525 #define PORT_GPCHR_GPWD_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 10526 #define PORT_GPCHR_GPWD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10527 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
AnnaBridge 171:3a7713b1edbc 10528 #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 10529 #define PORT_GPCHR_GPWE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10530 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
AnnaBridge 171:3a7713b1edbc 10531
AnnaBridge 171:3a7713b1edbc 10532 /*! @name ISFR - Interrupt Status Flag Register */
AnnaBridge 171:3a7713b1edbc 10533 #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 10534 #define PORT_ISFR_ISF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10535 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
AnnaBridge 171:3a7713b1edbc 10536
AnnaBridge 171:3a7713b1edbc 10537 /*! @name DFER - Digital Filter Enable Register */
AnnaBridge 171:3a7713b1edbc 10538 #define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 10539 #define PORT_DFER_DFE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10540 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
AnnaBridge 171:3a7713b1edbc 10541
AnnaBridge 171:3a7713b1edbc 10542 /*! @name DFCR - Digital Filter Clock Register */
AnnaBridge 171:3a7713b1edbc 10543 #define PORT_DFCR_CS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10544 #define PORT_DFCR_CS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10545 #define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
AnnaBridge 171:3a7713b1edbc 10546
AnnaBridge 171:3a7713b1edbc 10547 /*! @name DFWR - Digital Filter Width Register */
AnnaBridge 171:3a7713b1edbc 10548 #define PORT_DFWR_FILT_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 10549 #define PORT_DFWR_FILT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10550 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
AnnaBridge 171:3a7713b1edbc 10551
AnnaBridge 171:3a7713b1edbc 10552
AnnaBridge 171:3a7713b1edbc 10553 /*!
AnnaBridge 171:3a7713b1edbc 10554 * @}
AnnaBridge 171:3a7713b1edbc 10555 */ /* end of group PORT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 10556
AnnaBridge 171:3a7713b1edbc 10557
AnnaBridge 171:3a7713b1edbc 10558 /* PORT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 10559 /** Peripheral PORTA base address */
AnnaBridge 171:3a7713b1edbc 10560 #define PORTA_BASE (0x40049000u)
AnnaBridge 171:3a7713b1edbc 10561 /** Peripheral PORTA base pointer */
AnnaBridge 171:3a7713b1edbc 10562 #define PORTA ((PORT_Type *)PORTA_BASE)
AnnaBridge 171:3a7713b1edbc 10563 /** Peripheral PORTB base address */
AnnaBridge 171:3a7713b1edbc 10564 #define PORTB_BASE (0x4004A000u)
AnnaBridge 171:3a7713b1edbc 10565 /** Peripheral PORTB base pointer */
AnnaBridge 171:3a7713b1edbc 10566 #define PORTB ((PORT_Type *)PORTB_BASE)
AnnaBridge 171:3a7713b1edbc 10567 /** Peripheral PORTC base address */
AnnaBridge 171:3a7713b1edbc 10568 #define PORTC_BASE (0x4004B000u)
AnnaBridge 171:3a7713b1edbc 10569 /** Peripheral PORTC base pointer */
AnnaBridge 171:3a7713b1edbc 10570 #define PORTC ((PORT_Type *)PORTC_BASE)
AnnaBridge 171:3a7713b1edbc 10571 /** Peripheral PORTD base address */
AnnaBridge 171:3a7713b1edbc 10572 #define PORTD_BASE (0x4004C000u)
AnnaBridge 171:3a7713b1edbc 10573 /** Peripheral PORTD base pointer */
AnnaBridge 171:3a7713b1edbc 10574 #define PORTD ((PORT_Type *)PORTD_BASE)
AnnaBridge 171:3a7713b1edbc 10575 /** Peripheral PORTE base address */
AnnaBridge 171:3a7713b1edbc 10576 #define PORTE_BASE (0x4004D000u)
AnnaBridge 171:3a7713b1edbc 10577 /** Peripheral PORTE base pointer */
AnnaBridge 171:3a7713b1edbc 10578 #define PORTE ((PORT_Type *)PORTE_BASE)
AnnaBridge 171:3a7713b1edbc 10579 /** Array initializer of PORT peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 10580 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
AnnaBridge 171:3a7713b1edbc 10581 /** Array initializer of PORT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 10582 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
AnnaBridge 171:3a7713b1edbc 10583 /** Interrupt vectors for the PORT peripheral type */
AnnaBridge 171:3a7713b1edbc 10584 #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
AnnaBridge 171:3a7713b1edbc 10585
AnnaBridge 171:3a7713b1edbc 10586 /*!
AnnaBridge 171:3a7713b1edbc 10587 * @}
AnnaBridge 171:3a7713b1edbc 10588 */ /* end of group PORT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 10589
AnnaBridge 171:3a7713b1edbc 10590
AnnaBridge 171:3a7713b1edbc 10591 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10592 -- RCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10593 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10594
AnnaBridge 171:3a7713b1edbc 10595 /*!
AnnaBridge 171:3a7713b1edbc 10596 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10597 * @{
AnnaBridge 171:3a7713b1edbc 10598 */
AnnaBridge 171:3a7713b1edbc 10599
AnnaBridge 171:3a7713b1edbc 10600 /** RCM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 10601 typedef struct {
AnnaBridge 171:3a7713b1edbc 10602 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 10603 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 10604 uint8_t RESERVED_0[2];
AnnaBridge 171:3a7713b1edbc 10605 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 10606 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 10607 uint8_t RESERVED_1[1];
AnnaBridge 171:3a7713b1edbc 10608 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 10609 __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 10610 __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 10611 } RCM_Type;
AnnaBridge 171:3a7713b1edbc 10612
AnnaBridge 171:3a7713b1edbc 10613 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10614 -- RCM Register Masks
AnnaBridge 171:3a7713b1edbc 10615 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10616
AnnaBridge 171:3a7713b1edbc 10617 /*!
AnnaBridge 171:3a7713b1edbc 10618 * @addtogroup RCM_Register_Masks RCM Register Masks
AnnaBridge 171:3a7713b1edbc 10619 * @{
AnnaBridge 171:3a7713b1edbc 10620 */
AnnaBridge 171:3a7713b1edbc 10621
AnnaBridge 171:3a7713b1edbc 10622 /*! @name SRS0 - System Reset Status Register 0 */
AnnaBridge 171:3a7713b1edbc 10623 #define RCM_SRS0_WAKEUP_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10624 #define RCM_SRS0_WAKEUP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10625 #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
AnnaBridge 171:3a7713b1edbc 10626 #define RCM_SRS0_LVD_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10627 #define RCM_SRS0_LVD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10628 #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
AnnaBridge 171:3a7713b1edbc 10629 #define RCM_SRS0_LOC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 10630 #define RCM_SRS0_LOC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10631 #define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
AnnaBridge 171:3a7713b1edbc 10632 #define RCM_SRS0_LOL_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 10633 #define RCM_SRS0_LOL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 10634 #define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
AnnaBridge 171:3a7713b1edbc 10635 #define RCM_SRS0_WDOG_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 10636 #define RCM_SRS0_WDOG_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 10637 #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
AnnaBridge 171:3a7713b1edbc 10638 #define RCM_SRS0_PIN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 10639 #define RCM_SRS0_PIN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 10640 #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
AnnaBridge 171:3a7713b1edbc 10641 #define RCM_SRS0_POR_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 10642 #define RCM_SRS0_POR_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 10643 #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
AnnaBridge 171:3a7713b1edbc 10644
AnnaBridge 171:3a7713b1edbc 10645 /*! @name SRS1 - System Reset Status Register 1 */
AnnaBridge 171:3a7713b1edbc 10646 #define RCM_SRS1_JTAG_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10647 #define RCM_SRS1_JTAG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10648 #define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
AnnaBridge 171:3a7713b1edbc 10649 #define RCM_SRS1_LOCKUP_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10650 #define RCM_SRS1_LOCKUP_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10651 #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
AnnaBridge 171:3a7713b1edbc 10652 #define RCM_SRS1_SW_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 10653 #define RCM_SRS1_SW_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10654 #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
AnnaBridge 171:3a7713b1edbc 10655 #define RCM_SRS1_MDM_AP_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 10656 #define RCM_SRS1_MDM_AP_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 10657 #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
AnnaBridge 171:3a7713b1edbc 10658 #define RCM_SRS1_EZPT_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 10659 #define RCM_SRS1_EZPT_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10660 #define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
AnnaBridge 171:3a7713b1edbc 10661 #define RCM_SRS1_SACKERR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 10662 #define RCM_SRS1_SACKERR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 10663 #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
AnnaBridge 171:3a7713b1edbc 10664
AnnaBridge 171:3a7713b1edbc 10665 /*! @name RPFC - Reset Pin Filter Control register */
AnnaBridge 171:3a7713b1edbc 10666 #define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 10667 #define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10668 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
AnnaBridge 171:3a7713b1edbc 10669 #define RCM_RPFC_RSTFLTSS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 10670 #define RCM_RPFC_RSTFLTSS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10671 #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
AnnaBridge 171:3a7713b1edbc 10672
AnnaBridge 171:3a7713b1edbc 10673 /*! @name RPFW - Reset Pin Filter Width register */
AnnaBridge 171:3a7713b1edbc 10674 #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 10675 #define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10676 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 10677
AnnaBridge 171:3a7713b1edbc 10678 /*! @name MR - Mode Register */
AnnaBridge 171:3a7713b1edbc 10679 #define RCM_MR_EZP_MS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10680 #define RCM_MR_EZP_MS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10681 #define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
AnnaBridge 171:3a7713b1edbc 10682
AnnaBridge 171:3a7713b1edbc 10683 /*! @name SSRS0 - Sticky System Reset Status Register 0 */
AnnaBridge 171:3a7713b1edbc 10684 #define RCM_SSRS0_SWAKEUP_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10685 #define RCM_SSRS0_SWAKEUP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10686 #define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK)
AnnaBridge 171:3a7713b1edbc 10687 #define RCM_SSRS0_SLVD_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10688 #define RCM_SSRS0_SLVD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10689 #define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK)
AnnaBridge 171:3a7713b1edbc 10690 #define RCM_SSRS0_SLOC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 10691 #define RCM_SSRS0_SLOC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10692 #define RCM_SSRS0_SLOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOC_SHIFT)) & RCM_SSRS0_SLOC_MASK)
AnnaBridge 171:3a7713b1edbc 10693 #define RCM_SSRS0_SLOL_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 10694 #define RCM_SSRS0_SLOL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 10695 #define RCM_SSRS0_SLOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOL_SHIFT)) & RCM_SSRS0_SLOL_MASK)
AnnaBridge 171:3a7713b1edbc 10696 #define RCM_SSRS0_SWDOG_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 10697 #define RCM_SSRS0_SWDOG_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 10698 #define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK)
AnnaBridge 171:3a7713b1edbc 10699 #define RCM_SSRS0_SPIN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 10700 #define RCM_SSRS0_SPIN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 10701 #define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK)
AnnaBridge 171:3a7713b1edbc 10702 #define RCM_SSRS0_SPOR_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 10703 #define RCM_SSRS0_SPOR_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 10704 #define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK)
AnnaBridge 171:3a7713b1edbc 10705
AnnaBridge 171:3a7713b1edbc 10706 /*! @name SSRS1 - Sticky System Reset Status Register 1 */
AnnaBridge 171:3a7713b1edbc 10707 #define RCM_SSRS1_SJTAG_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10708 #define RCM_SSRS1_SJTAG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10709 #define RCM_SSRS1_SJTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SJTAG_SHIFT)) & RCM_SSRS1_SJTAG_MASK)
AnnaBridge 171:3a7713b1edbc 10710 #define RCM_SSRS1_SLOCKUP_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10711 #define RCM_SSRS1_SLOCKUP_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10712 #define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK)
AnnaBridge 171:3a7713b1edbc 10713 #define RCM_SSRS1_SSW_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 10714 #define RCM_SSRS1_SSW_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10715 #define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK)
AnnaBridge 171:3a7713b1edbc 10716 #define RCM_SSRS1_SMDM_AP_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 10717 #define RCM_SSRS1_SMDM_AP_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 10718 #define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK)
AnnaBridge 171:3a7713b1edbc 10719 #define RCM_SSRS1_SEZPT_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 10720 #define RCM_SSRS1_SEZPT_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10721 #define RCM_SSRS1_SEZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SEZPT_SHIFT)) & RCM_SSRS1_SEZPT_MASK)
AnnaBridge 171:3a7713b1edbc 10722 #define RCM_SSRS1_SSACKERR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 10723 #define RCM_SSRS1_SSACKERR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 10724 #define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK)
AnnaBridge 171:3a7713b1edbc 10725
AnnaBridge 171:3a7713b1edbc 10726
AnnaBridge 171:3a7713b1edbc 10727 /*!
AnnaBridge 171:3a7713b1edbc 10728 * @}
AnnaBridge 171:3a7713b1edbc 10729 */ /* end of group RCM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 10730
AnnaBridge 171:3a7713b1edbc 10731
AnnaBridge 171:3a7713b1edbc 10732 /* RCM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 10733 /** Peripheral RCM base address */
AnnaBridge 171:3a7713b1edbc 10734 #define RCM_BASE (0x4007F000u)
AnnaBridge 171:3a7713b1edbc 10735 /** Peripheral RCM base pointer */
AnnaBridge 171:3a7713b1edbc 10736 #define RCM ((RCM_Type *)RCM_BASE)
AnnaBridge 171:3a7713b1edbc 10737 /** Array initializer of RCM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 10738 #define RCM_BASE_ADDRS { RCM_BASE }
AnnaBridge 171:3a7713b1edbc 10739 /** Array initializer of RCM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 10740 #define RCM_BASE_PTRS { RCM }
AnnaBridge 171:3a7713b1edbc 10741
AnnaBridge 171:3a7713b1edbc 10742 /*!
AnnaBridge 171:3a7713b1edbc 10743 * @}
AnnaBridge 171:3a7713b1edbc 10744 */ /* end of group RCM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 10745
AnnaBridge 171:3a7713b1edbc 10746
AnnaBridge 171:3a7713b1edbc 10747 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10748 -- RFSYS Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10749 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10750
AnnaBridge 171:3a7713b1edbc 10751 /*!
AnnaBridge 171:3a7713b1edbc 10752 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10753 * @{
AnnaBridge 171:3a7713b1edbc 10754 */
AnnaBridge 171:3a7713b1edbc 10755
AnnaBridge 171:3a7713b1edbc 10756 /** RFSYS - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 10757 typedef struct {
AnnaBridge 171:3a7713b1edbc 10758 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 10759 } RFSYS_Type;
AnnaBridge 171:3a7713b1edbc 10760
AnnaBridge 171:3a7713b1edbc 10761 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10762 -- RFSYS Register Masks
AnnaBridge 171:3a7713b1edbc 10763 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10764
AnnaBridge 171:3a7713b1edbc 10765 /*!
AnnaBridge 171:3a7713b1edbc 10766 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
AnnaBridge 171:3a7713b1edbc 10767 * @{
AnnaBridge 171:3a7713b1edbc 10768 */
AnnaBridge 171:3a7713b1edbc 10769
AnnaBridge 171:3a7713b1edbc 10770 /*! @name REG - Register file register */
AnnaBridge 171:3a7713b1edbc 10771 #define RFSYS_REG_LL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 10772 #define RFSYS_REG_LL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10773 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
AnnaBridge 171:3a7713b1edbc 10774 #define RFSYS_REG_LH_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 10775 #define RFSYS_REG_LH_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10776 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
AnnaBridge 171:3a7713b1edbc 10777 #define RFSYS_REG_HL_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 10778 #define RFSYS_REG_HL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10779 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
AnnaBridge 171:3a7713b1edbc 10780 #define RFSYS_REG_HH_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 10781 #define RFSYS_REG_HH_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10782 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
AnnaBridge 171:3a7713b1edbc 10783
AnnaBridge 171:3a7713b1edbc 10784 /* The count of RFSYS_REG */
AnnaBridge 171:3a7713b1edbc 10785 #define RFSYS_REG_COUNT (8U)
AnnaBridge 171:3a7713b1edbc 10786
AnnaBridge 171:3a7713b1edbc 10787
AnnaBridge 171:3a7713b1edbc 10788 /*!
AnnaBridge 171:3a7713b1edbc 10789 * @}
AnnaBridge 171:3a7713b1edbc 10790 */ /* end of group RFSYS_Register_Masks */
AnnaBridge 171:3a7713b1edbc 10791
AnnaBridge 171:3a7713b1edbc 10792
AnnaBridge 171:3a7713b1edbc 10793 /* RFSYS - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 10794 /** Peripheral RFSYS base address */
AnnaBridge 171:3a7713b1edbc 10795 #define RFSYS_BASE (0x40041000u)
AnnaBridge 171:3a7713b1edbc 10796 /** Peripheral RFSYS base pointer */
AnnaBridge 171:3a7713b1edbc 10797 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
AnnaBridge 171:3a7713b1edbc 10798 /** Array initializer of RFSYS peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 10799 #define RFSYS_BASE_ADDRS { RFSYS_BASE }
AnnaBridge 171:3a7713b1edbc 10800 /** Array initializer of RFSYS peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 10801 #define RFSYS_BASE_PTRS { RFSYS }
AnnaBridge 171:3a7713b1edbc 10802
AnnaBridge 171:3a7713b1edbc 10803 /*!
AnnaBridge 171:3a7713b1edbc 10804 * @}
AnnaBridge 171:3a7713b1edbc 10805 */ /* end of group RFSYS_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 10806
AnnaBridge 171:3a7713b1edbc 10807
AnnaBridge 171:3a7713b1edbc 10808 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10809 -- RFVBAT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10810 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10811
AnnaBridge 171:3a7713b1edbc 10812 /*!
AnnaBridge 171:3a7713b1edbc 10813 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10814 * @{
AnnaBridge 171:3a7713b1edbc 10815 */
AnnaBridge 171:3a7713b1edbc 10816
AnnaBridge 171:3a7713b1edbc 10817 /** RFVBAT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 10818 typedef struct {
AnnaBridge 171:3a7713b1edbc 10819 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 10820 } RFVBAT_Type;
AnnaBridge 171:3a7713b1edbc 10821
AnnaBridge 171:3a7713b1edbc 10822 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10823 -- RFVBAT Register Masks
AnnaBridge 171:3a7713b1edbc 10824 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10825
AnnaBridge 171:3a7713b1edbc 10826 /*!
AnnaBridge 171:3a7713b1edbc 10827 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
AnnaBridge 171:3a7713b1edbc 10828 * @{
AnnaBridge 171:3a7713b1edbc 10829 */
AnnaBridge 171:3a7713b1edbc 10830
AnnaBridge 171:3a7713b1edbc 10831 /*! @name REG - VBAT register file register */
AnnaBridge 171:3a7713b1edbc 10832 #define RFVBAT_REG_LL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 10833 #define RFVBAT_REG_LL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10834 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
AnnaBridge 171:3a7713b1edbc 10835 #define RFVBAT_REG_LH_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 10836 #define RFVBAT_REG_LH_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10837 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
AnnaBridge 171:3a7713b1edbc 10838 #define RFVBAT_REG_HL_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 10839 #define RFVBAT_REG_HL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10840 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
AnnaBridge 171:3a7713b1edbc 10841 #define RFVBAT_REG_HH_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 10842 #define RFVBAT_REG_HH_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10843 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
AnnaBridge 171:3a7713b1edbc 10844
AnnaBridge 171:3a7713b1edbc 10845 /* The count of RFVBAT_REG */
AnnaBridge 171:3a7713b1edbc 10846 #define RFVBAT_REG_COUNT (8U)
AnnaBridge 171:3a7713b1edbc 10847
AnnaBridge 171:3a7713b1edbc 10848
AnnaBridge 171:3a7713b1edbc 10849 /*!
AnnaBridge 171:3a7713b1edbc 10850 * @}
AnnaBridge 171:3a7713b1edbc 10851 */ /* end of group RFVBAT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 10852
AnnaBridge 171:3a7713b1edbc 10853
AnnaBridge 171:3a7713b1edbc 10854 /* RFVBAT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 10855 /** Peripheral RFVBAT base address */
AnnaBridge 171:3a7713b1edbc 10856 #define RFVBAT_BASE (0x4003E000u)
AnnaBridge 171:3a7713b1edbc 10857 /** Peripheral RFVBAT base pointer */
AnnaBridge 171:3a7713b1edbc 10858 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
AnnaBridge 171:3a7713b1edbc 10859 /** Array initializer of RFVBAT peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 10860 #define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
AnnaBridge 171:3a7713b1edbc 10861 /** Array initializer of RFVBAT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 10862 #define RFVBAT_BASE_PTRS { RFVBAT }
AnnaBridge 171:3a7713b1edbc 10863
AnnaBridge 171:3a7713b1edbc 10864 /*!
AnnaBridge 171:3a7713b1edbc 10865 * @}
AnnaBridge 171:3a7713b1edbc 10866 */ /* end of group RFVBAT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 10867
AnnaBridge 171:3a7713b1edbc 10868
AnnaBridge 171:3a7713b1edbc 10869 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10870 -- RNG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10871 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10872
AnnaBridge 171:3a7713b1edbc 10873 /*!
AnnaBridge 171:3a7713b1edbc 10874 * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10875 * @{
AnnaBridge 171:3a7713b1edbc 10876 */
AnnaBridge 171:3a7713b1edbc 10877
AnnaBridge 171:3a7713b1edbc 10878 /** RNG - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 10879 typedef struct {
AnnaBridge 171:3a7713b1edbc 10880 __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 10881 __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 10882 __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 10883 __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 10884 } RNG_Type;
AnnaBridge 171:3a7713b1edbc 10885
AnnaBridge 171:3a7713b1edbc 10886 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10887 -- RNG Register Masks
AnnaBridge 171:3a7713b1edbc 10888 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10889
AnnaBridge 171:3a7713b1edbc 10890 /*!
AnnaBridge 171:3a7713b1edbc 10891 * @addtogroup RNG_Register_Masks RNG Register Masks
AnnaBridge 171:3a7713b1edbc 10892 * @{
AnnaBridge 171:3a7713b1edbc 10893 */
AnnaBridge 171:3a7713b1edbc 10894
AnnaBridge 171:3a7713b1edbc 10895 /*! @name CR - RNGA Control Register */
AnnaBridge 171:3a7713b1edbc 10896 #define RNG_CR_GO_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10897 #define RNG_CR_GO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10898 #define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)
AnnaBridge 171:3a7713b1edbc 10899 #define RNG_CR_HA_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10900 #define RNG_CR_HA_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10901 #define RNG_CR_HA(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)
AnnaBridge 171:3a7713b1edbc 10902 #define RNG_CR_INTM_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 10903 #define RNG_CR_INTM_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10904 #define RNG_CR_INTM(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)
AnnaBridge 171:3a7713b1edbc 10905 #define RNG_CR_CLRI_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 10906 #define RNG_CR_CLRI_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 10907 #define RNG_CR_CLRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)
AnnaBridge 171:3a7713b1edbc 10908 #define RNG_CR_SLP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 10909 #define RNG_CR_SLP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10910 #define RNG_CR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)
AnnaBridge 171:3a7713b1edbc 10911
AnnaBridge 171:3a7713b1edbc 10912 /*! @name SR - RNGA Status Register */
AnnaBridge 171:3a7713b1edbc 10913 #define RNG_SR_SECV_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10914 #define RNG_SR_SECV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10915 #define RNG_SR_SECV(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)
AnnaBridge 171:3a7713b1edbc 10916 #define RNG_SR_LRS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10917 #define RNG_SR_LRS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10918 #define RNG_SR_LRS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)
AnnaBridge 171:3a7713b1edbc 10919 #define RNG_SR_ORU_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 10920 #define RNG_SR_ORU_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10921 #define RNG_SR_ORU(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)
AnnaBridge 171:3a7713b1edbc 10922 #define RNG_SR_ERRI_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 10923 #define RNG_SR_ERRI_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 10924 #define RNG_SR_ERRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)
AnnaBridge 171:3a7713b1edbc 10925 #define RNG_SR_SLP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 10926 #define RNG_SR_SLP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10927 #define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)
AnnaBridge 171:3a7713b1edbc 10928 #define RNG_SR_OREG_LVL_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 10929 #define RNG_SR_OREG_LVL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10930 #define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
AnnaBridge 171:3a7713b1edbc 10931 #define RNG_SR_OREG_SIZE_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 10932 #define RNG_SR_OREG_SIZE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10933 #define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)
AnnaBridge 171:3a7713b1edbc 10934
AnnaBridge 171:3a7713b1edbc 10935 /*! @name ER - RNGA Entropy Register */
AnnaBridge 171:3a7713b1edbc 10936 #define RNG_ER_EXT_ENT_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 10937 #define RNG_ER_EXT_ENT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10938 #define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK)
AnnaBridge 171:3a7713b1edbc 10939
AnnaBridge 171:3a7713b1edbc 10940 /*! @name OR - RNGA Output Register */
AnnaBridge 171:3a7713b1edbc 10941 #define RNG_OR_RANDOUT_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 10942 #define RNG_OR_RANDOUT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10943 #define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)
AnnaBridge 171:3a7713b1edbc 10944
AnnaBridge 171:3a7713b1edbc 10945
AnnaBridge 171:3a7713b1edbc 10946 /*!
AnnaBridge 171:3a7713b1edbc 10947 * @}
AnnaBridge 171:3a7713b1edbc 10948 */ /* end of group RNG_Register_Masks */
AnnaBridge 171:3a7713b1edbc 10949
AnnaBridge 171:3a7713b1edbc 10950
AnnaBridge 171:3a7713b1edbc 10951 /* RNG - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 10952 /** Peripheral RNG base address */
AnnaBridge 171:3a7713b1edbc 10953 #define RNG_BASE (0x400A0000u)
AnnaBridge 171:3a7713b1edbc 10954 /** Peripheral RNG base pointer */
AnnaBridge 171:3a7713b1edbc 10955 #define RNG ((RNG_Type *)RNG_BASE)
AnnaBridge 171:3a7713b1edbc 10956 /** Array initializer of RNG peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 10957 #define RNG_BASE_ADDRS { RNG_BASE }
AnnaBridge 171:3a7713b1edbc 10958 /** Array initializer of RNG peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 10959 #define RNG_BASE_PTRS { RNG }
AnnaBridge 171:3a7713b1edbc 10960 /** Interrupt vectors for the RNG peripheral type */
AnnaBridge 171:3a7713b1edbc 10961 #define RNG_IRQS { RNG_IRQn }
AnnaBridge 171:3a7713b1edbc 10962
AnnaBridge 171:3a7713b1edbc 10963 /*!
AnnaBridge 171:3a7713b1edbc 10964 * @}
AnnaBridge 171:3a7713b1edbc 10965 */ /* end of group RNG_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 10966
AnnaBridge 171:3a7713b1edbc 10967
AnnaBridge 171:3a7713b1edbc 10968 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10969 -- RTC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10970 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10971
AnnaBridge 171:3a7713b1edbc 10972 /*!
AnnaBridge 171:3a7713b1edbc 10973 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10974 * @{
AnnaBridge 171:3a7713b1edbc 10975 */
AnnaBridge 171:3a7713b1edbc 10976
AnnaBridge 171:3a7713b1edbc 10977 /** RTC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 10978 typedef struct {
AnnaBridge 171:3a7713b1edbc 10979 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 10980 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 10981 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 10982 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 10983 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 10984 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 10985 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 10986 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 10987 __I uint32_t TTSR; /**< RTC Tamper Time Seconds Register, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 10988 __IO uint32_t MER; /**< RTC Monotonic Enable Register, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 10989 __IO uint32_t MCLR; /**< RTC Monotonic Counter Low Register, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 10990 __IO uint32_t MCHR; /**< RTC Monotonic Counter High Register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 10991 uint8_t RESERVED_0[2000];
AnnaBridge 171:3a7713b1edbc 10992 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
AnnaBridge 171:3a7713b1edbc 10993 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
AnnaBridge 171:3a7713b1edbc 10994 } RTC_Type;
AnnaBridge 171:3a7713b1edbc 10995
AnnaBridge 171:3a7713b1edbc 10996 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10997 -- RTC Register Masks
AnnaBridge 171:3a7713b1edbc 10998 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10999
AnnaBridge 171:3a7713b1edbc 11000 /*!
AnnaBridge 171:3a7713b1edbc 11001 * @addtogroup RTC_Register_Masks RTC Register Masks
AnnaBridge 171:3a7713b1edbc 11002 * @{
AnnaBridge 171:3a7713b1edbc 11003 */
AnnaBridge 171:3a7713b1edbc 11004
AnnaBridge 171:3a7713b1edbc 11005 /*! @name TSR - RTC Time Seconds Register */
AnnaBridge 171:3a7713b1edbc 11006 #define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 11007 #define RTC_TSR_TSR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11008 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
AnnaBridge 171:3a7713b1edbc 11009
AnnaBridge 171:3a7713b1edbc 11010 /*! @name TPR - RTC Time Prescaler Register */
AnnaBridge 171:3a7713b1edbc 11011 #define RTC_TPR_TPR_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 11012 #define RTC_TPR_TPR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11013 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
AnnaBridge 171:3a7713b1edbc 11014
AnnaBridge 171:3a7713b1edbc 11015 /*! @name TAR - RTC Time Alarm Register */
AnnaBridge 171:3a7713b1edbc 11016 #define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 11017 #define RTC_TAR_TAR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11018 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
AnnaBridge 171:3a7713b1edbc 11019
AnnaBridge 171:3a7713b1edbc 11020 /*! @name TCR - RTC Time Compensation Register */
AnnaBridge 171:3a7713b1edbc 11021 #define RTC_TCR_TCR_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11022 #define RTC_TCR_TCR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11023 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
AnnaBridge 171:3a7713b1edbc 11024 #define RTC_TCR_CIR_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11025 #define RTC_TCR_CIR_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11026 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
AnnaBridge 171:3a7713b1edbc 11027 #define RTC_TCR_TCV_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11028 #define RTC_TCR_TCV_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11029 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
AnnaBridge 171:3a7713b1edbc 11030 #define RTC_TCR_CIC_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11031 #define RTC_TCR_CIC_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11032 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
AnnaBridge 171:3a7713b1edbc 11033
AnnaBridge 171:3a7713b1edbc 11034 /*! @name CR - RTC Control Register */
AnnaBridge 171:3a7713b1edbc 11035 #define RTC_CR_SWR_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11036 #define RTC_CR_SWR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11037 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
AnnaBridge 171:3a7713b1edbc 11038 #define RTC_CR_WPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11039 #define RTC_CR_WPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11040 #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
AnnaBridge 171:3a7713b1edbc 11041 #define RTC_CR_SUP_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11042 #define RTC_CR_SUP_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11043 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
AnnaBridge 171:3a7713b1edbc 11044 #define RTC_CR_UM_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11045 #define RTC_CR_UM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11046 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
AnnaBridge 171:3a7713b1edbc 11047 #define RTC_CR_WPS_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11048 #define RTC_CR_WPS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11049 #define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
AnnaBridge 171:3a7713b1edbc 11050 #define RTC_CR_OSCE_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 11051 #define RTC_CR_OSCE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11052 #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
AnnaBridge 171:3a7713b1edbc 11053 #define RTC_CR_CLKO_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 11054 #define RTC_CR_CLKO_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 11055 #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
AnnaBridge 171:3a7713b1edbc 11056 #define RTC_CR_SC16P_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 11057 #define RTC_CR_SC16P_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 11058 #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
AnnaBridge 171:3a7713b1edbc 11059 #define RTC_CR_SC8P_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 11060 #define RTC_CR_SC8P_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 11061 #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
AnnaBridge 171:3a7713b1edbc 11062 #define RTC_CR_SC4P_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 11063 #define RTC_CR_SC4P_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 11064 #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
AnnaBridge 171:3a7713b1edbc 11065 #define RTC_CR_SC2P_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 11066 #define RTC_CR_SC2P_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 11067 #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
AnnaBridge 171:3a7713b1edbc 11068
AnnaBridge 171:3a7713b1edbc 11069 /*! @name SR - RTC Status Register */
AnnaBridge 171:3a7713b1edbc 11070 #define RTC_SR_TIF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11071 #define RTC_SR_TIF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11072 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
AnnaBridge 171:3a7713b1edbc 11073 #define RTC_SR_TOF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11074 #define RTC_SR_TOF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11075 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
AnnaBridge 171:3a7713b1edbc 11076 #define RTC_SR_TAF_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11077 #define RTC_SR_TAF_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11078 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
AnnaBridge 171:3a7713b1edbc 11079 #define RTC_SR_MOF_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11080 #define RTC_SR_MOF_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11081 #define RTC_SR_MOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_MOF_SHIFT)) & RTC_SR_MOF_MASK)
AnnaBridge 171:3a7713b1edbc 11082 #define RTC_SR_TCE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11083 #define RTC_SR_TCE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11084 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
AnnaBridge 171:3a7713b1edbc 11085
AnnaBridge 171:3a7713b1edbc 11086 /*! @name LR - RTC Lock Register */
AnnaBridge 171:3a7713b1edbc 11087 #define RTC_LR_TCL_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11088 #define RTC_LR_TCL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11089 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
AnnaBridge 171:3a7713b1edbc 11090 #define RTC_LR_CRL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11091 #define RTC_LR_CRL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11092 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
AnnaBridge 171:3a7713b1edbc 11093 #define RTC_LR_SRL_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11094 #define RTC_LR_SRL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11095 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
AnnaBridge 171:3a7713b1edbc 11096 #define RTC_LR_LRL_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11097 #define RTC_LR_LRL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11098 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
AnnaBridge 171:3a7713b1edbc 11099 #define RTC_LR_TTSL_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 11100 #define RTC_LR_TTSL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11101 #define RTC_LR_TTSL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TTSL_SHIFT)) & RTC_LR_TTSL_MASK)
AnnaBridge 171:3a7713b1edbc 11102 #define RTC_LR_MEL_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 11103 #define RTC_LR_MEL_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 11104 #define RTC_LR_MEL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MEL_SHIFT)) & RTC_LR_MEL_MASK)
AnnaBridge 171:3a7713b1edbc 11105 #define RTC_LR_MCLL_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 11106 #define RTC_LR_MCLL_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 11107 #define RTC_LR_MCLL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCLL_SHIFT)) & RTC_LR_MCLL_MASK)
AnnaBridge 171:3a7713b1edbc 11108 #define RTC_LR_MCHL_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 11109 #define RTC_LR_MCHL_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 11110 #define RTC_LR_MCHL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCHL_SHIFT)) & RTC_LR_MCHL_MASK)
AnnaBridge 171:3a7713b1edbc 11111
AnnaBridge 171:3a7713b1edbc 11112 /*! @name IER - RTC Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 11113 #define RTC_IER_TIIE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11114 #define RTC_IER_TIIE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11115 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
AnnaBridge 171:3a7713b1edbc 11116 #define RTC_IER_TOIE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11117 #define RTC_IER_TOIE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11118 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
AnnaBridge 171:3a7713b1edbc 11119 #define RTC_IER_TAIE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11120 #define RTC_IER_TAIE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11121 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
AnnaBridge 171:3a7713b1edbc 11122 #define RTC_IER_MOIE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11123 #define RTC_IER_MOIE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11124 #define RTC_IER_MOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_MOIE_SHIFT)) & RTC_IER_MOIE_MASK)
AnnaBridge 171:3a7713b1edbc 11125 #define RTC_IER_TSIE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11126 #define RTC_IER_TSIE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11127 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
AnnaBridge 171:3a7713b1edbc 11128 #define RTC_IER_WPON_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11129 #define RTC_IER_WPON_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11130 #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
AnnaBridge 171:3a7713b1edbc 11131
AnnaBridge 171:3a7713b1edbc 11132 /*! @name TTSR - RTC Tamper Time Seconds Register */
AnnaBridge 171:3a7713b1edbc 11133 #define RTC_TTSR_TTS_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 11134 #define RTC_TTSR_TTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11135 #define RTC_TTSR_TTS(x) (((uint32_t)(((uint32_t)(x)) << RTC_TTSR_TTS_SHIFT)) & RTC_TTSR_TTS_MASK)
AnnaBridge 171:3a7713b1edbc 11136
AnnaBridge 171:3a7713b1edbc 11137 /*! @name MER - RTC Monotonic Enable Register */
AnnaBridge 171:3a7713b1edbc 11138 #define RTC_MER_MCE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11139 #define RTC_MER_MCE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11140 #define RTC_MER_MCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_MER_MCE_SHIFT)) & RTC_MER_MCE_MASK)
AnnaBridge 171:3a7713b1edbc 11141
AnnaBridge 171:3a7713b1edbc 11142 /*! @name MCLR - RTC Monotonic Counter Low Register */
AnnaBridge 171:3a7713b1edbc 11143 #define RTC_MCLR_MCL_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 11144 #define RTC_MCLR_MCL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11145 #define RTC_MCLR_MCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MCLR_MCL_SHIFT)) & RTC_MCLR_MCL_MASK)
AnnaBridge 171:3a7713b1edbc 11146
AnnaBridge 171:3a7713b1edbc 11147 /*! @name MCHR - RTC Monotonic Counter High Register */
AnnaBridge 171:3a7713b1edbc 11148 #define RTC_MCHR_MCH_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 11149 #define RTC_MCHR_MCH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11150 #define RTC_MCHR_MCH(x) (((uint32_t)(((uint32_t)(x)) << RTC_MCHR_MCH_SHIFT)) & RTC_MCHR_MCH_MASK)
AnnaBridge 171:3a7713b1edbc 11151
AnnaBridge 171:3a7713b1edbc 11152 /*! @name WAR - RTC Write Access Register */
AnnaBridge 171:3a7713b1edbc 11153 #define RTC_WAR_TSRW_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11154 #define RTC_WAR_TSRW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11155 #define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
AnnaBridge 171:3a7713b1edbc 11156 #define RTC_WAR_TPRW_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11157 #define RTC_WAR_TPRW_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11158 #define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
AnnaBridge 171:3a7713b1edbc 11159 #define RTC_WAR_TARW_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11160 #define RTC_WAR_TARW_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11161 #define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
AnnaBridge 171:3a7713b1edbc 11162 #define RTC_WAR_TCRW_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11163 #define RTC_WAR_TCRW_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11164 #define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
AnnaBridge 171:3a7713b1edbc 11165 #define RTC_WAR_CRW_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11166 #define RTC_WAR_CRW_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11167 #define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
AnnaBridge 171:3a7713b1edbc 11168 #define RTC_WAR_SRW_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11169 #define RTC_WAR_SRW_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11170 #define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
AnnaBridge 171:3a7713b1edbc 11171 #define RTC_WAR_LRW_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11172 #define RTC_WAR_LRW_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11173 #define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
AnnaBridge 171:3a7713b1edbc 11174 #define RTC_WAR_IERW_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11175 #define RTC_WAR_IERW_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11176 #define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
AnnaBridge 171:3a7713b1edbc 11177 #define RTC_WAR_TTSW_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 11178 #define RTC_WAR_TTSW_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11179 #define RTC_WAR_TTSW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TTSW_SHIFT)) & RTC_WAR_TTSW_MASK)
AnnaBridge 171:3a7713b1edbc 11180 #define RTC_WAR_MERW_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 11181 #define RTC_WAR_MERW_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 11182 #define RTC_WAR_MERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MERW_SHIFT)) & RTC_WAR_MERW_MASK)
AnnaBridge 171:3a7713b1edbc 11183 #define RTC_WAR_MCLW_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 11184 #define RTC_WAR_MCLW_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 11185 #define RTC_WAR_MCLW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCLW_SHIFT)) & RTC_WAR_MCLW_MASK)
AnnaBridge 171:3a7713b1edbc 11186 #define RTC_WAR_MCHW_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 11187 #define RTC_WAR_MCHW_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 11188 #define RTC_WAR_MCHW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCHW_SHIFT)) & RTC_WAR_MCHW_MASK)
AnnaBridge 171:3a7713b1edbc 11189
AnnaBridge 171:3a7713b1edbc 11190 /*! @name RAR - RTC Read Access Register */
AnnaBridge 171:3a7713b1edbc 11191 #define RTC_RAR_TSRR_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11192 #define RTC_RAR_TSRR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11193 #define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
AnnaBridge 171:3a7713b1edbc 11194 #define RTC_RAR_TPRR_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11195 #define RTC_RAR_TPRR_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11196 #define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
AnnaBridge 171:3a7713b1edbc 11197 #define RTC_RAR_TARR_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11198 #define RTC_RAR_TARR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11199 #define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
AnnaBridge 171:3a7713b1edbc 11200 #define RTC_RAR_TCRR_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11201 #define RTC_RAR_TCRR_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11202 #define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
AnnaBridge 171:3a7713b1edbc 11203 #define RTC_RAR_CRR_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11204 #define RTC_RAR_CRR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11205 #define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
AnnaBridge 171:3a7713b1edbc 11206 #define RTC_RAR_SRR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11207 #define RTC_RAR_SRR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11208 #define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
AnnaBridge 171:3a7713b1edbc 11209 #define RTC_RAR_LRR_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11210 #define RTC_RAR_LRR_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11211 #define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
AnnaBridge 171:3a7713b1edbc 11212 #define RTC_RAR_IERR_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11213 #define RTC_RAR_IERR_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11214 #define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
AnnaBridge 171:3a7713b1edbc 11215 #define RTC_RAR_TTSR_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 11216 #define RTC_RAR_TTSR_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11217 #define RTC_RAR_TTSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TTSR_SHIFT)) & RTC_RAR_TTSR_MASK)
AnnaBridge 171:3a7713b1edbc 11218 #define RTC_RAR_MERR_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 11219 #define RTC_RAR_MERR_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 11220 #define RTC_RAR_MERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MERR_SHIFT)) & RTC_RAR_MERR_MASK)
AnnaBridge 171:3a7713b1edbc 11221 #define RTC_RAR_MCLR_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 11222 #define RTC_RAR_MCLR_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 11223 #define RTC_RAR_MCLR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCLR_SHIFT)) & RTC_RAR_MCLR_MASK)
AnnaBridge 171:3a7713b1edbc 11224 #define RTC_RAR_MCHR_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 11225 #define RTC_RAR_MCHR_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 11226 #define RTC_RAR_MCHR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCHR_SHIFT)) & RTC_RAR_MCHR_MASK)
AnnaBridge 171:3a7713b1edbc 11227
AnnaBridge 171:3a7713b1edbc 11228
AnnaBridge 171:3a7713b1edbc 11229 /*!
AnnaBridge 171:3a7713b1edbc 11230 * @}
AnnaBridge 171:3a7713b1edbc 11231 */ /* end of group RTC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 11232
AnnaBridge 171:3a7713b1edbc 11233
AnnaBridge 171:3a7713b1edbc 11234 /* RTC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 11235 /** Peripheral RTC base address */
AnnaBridge 171:3a7713b1edbc 11236 #define RTC_BASE (0x4003D000u)
AnnaBridge 171:3a7713b1edbc 11237 /** Peripheral RTC base pointer */
AnnaBridge 171:3a7713b1edbc 11238 #define RTC ((RTC_Type *)RTC_BASE)
AnnaBridge 171:3a7713b1edbc 11239 /** Array initializer of RTC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 11240 #define RTC_BASE_ADDRS { RTC_BASE }
AnnaBridge 171:3a7713b1edbc 11241 /** Array initializer of RTC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 11242 #define RTC_BASE_PTRS { RTC }
AnnaBridge 171:3a7713b1edbc 11243 /** Interrupt vectors for the RTC peripheral type */
AnnaBridge 171:3a7713b1edbc 11244 #define RTC_IRQS { RTC_IRQn }
AnnaBridge 171:3a7713b1edbc 11245 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
AnnaBridge 171:3a7713b1edbc 11246
AnnaBridge 171:3a7713b1edbc 11247 /*!
AnnaBridge 171:3a7713b1edbc 11248 * @}
AnnaBridge 171:3a7713b1edbc 11249 */ /* end of group RTC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 11250
AnnaBridge 171:3a7713b1edbc 11251
AnnaBridge 171:3a7713b1edbc 11252 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11253 -- SDHC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 11254 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 11255
AnnaBridge 171:3a7713b1edbc 11256 /*!
AnnaBridge 171:3a7713b1edbc 11257 * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 11258 * @{
AnnaBridge 171:3a7713b1edbc 11259 */
AnnaBridge 171:3a7713b1edbc 11260
AnnaBridge 171:3a7713b1edbc 11261 /** SDHC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 11262 typedef struct {
AnnaBridge 171:3a7713b1edbc 11263 __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 11264 __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 11265 __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 11266 __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 11267 __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 11268 __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 11269 __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 11270 __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 11271 __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 11272 __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 11273 __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 11274 __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 11275 __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 11276 __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 11277 __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 11278 uint8_t RESERVED_0[8];
AnnaBridge 171:3a7713b1edbc 11279 __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 11280 __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 11281 __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 11282 uint8_t RESERVED_1[100];
AnnaBridge 171:3a7713b1edbc 11283 __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */
AnnaBridge 171:3a7713b1edbc 11284 __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */
AnnaBridge 171:3a7713b1edbc 11285 uint8_t RESERVED_2[52];
AnnaBridge 171:3a7713b1edbc 11286 __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
AnnaBridge 171:3a7713b1edbc 11287 } SDHC_Type;
AnnaBridge 171:3a7713b1edbc 11288
AnnaBridge 171:3a7713b1edbc 11289 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11290 -- SDHC Register Masks
AnnaBridge 171:3a7713b1edbc 11291 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 11292
AnnaBridge 171:3a7713b1edbc 11293 /*!
AnnaBridge 171:3a7713b1edbc 11294 * @addtogroup SDHC_Register_Masks SDHC Register Masks
AnnaBridge 171:3a7713b1edbc 11295 * @{
AnnaBridge 171:3a7713b1edbc 11296 */
AnnaBridge 171:3a7713b1edbc 11297
AnnaBridge 171:3a7713b1edbc 11298 /*! @name DSADDR - DMA System Address register */
AnnaBridge 171:3a7713b1edbc 11299 #define SDHC_DSADDR_DSADDR_MASK (0xFFFFFFFCU)
AnnaBridge 171:3a7713b1edbc 11300 #define SDHC_DSADDR_DSADDR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11301 #define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK)
AnnaBridge 171:3a7713b1edbc 11302
AnnaBridge 171:3a7713b1edbc 11303 /*! @name BLKATTR - Block Attributes register */
AnnaBridge 171:3a7713b1edbc 11304 #define SDHC_BLKATTR_BLKSIZE_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 11305 #define SDHC_BLKATTR_BLKSIZE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11306 #define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 11307 #define SDHC_BLKATTR_BLKCNT_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 11308 #define SDHC_BLKATTR_BLKCNT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11309 #define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
AnnaBridge 171:3a7713b1edbc 11310
AnnaBridge 171:3a7713b1edbc 11311 /*! @name CMDARG - Command Argument register */
AnnaBridge 171:3a7713b1edbc 11312 #define SDHC_CMDARG_CMDARG_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 11313 #define SDHC_CMDARG_CMDARG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11314 #define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK)
AnnaBridge 171:3a7713b1edbc 11315
AnnaBridge 171:3a7713b1edbc 11316 /*! @name XFERTYP - Transfer Type register */
AnnaBridge 171:3a7713b1edbc 11317 #define SDHC_XFERTYP_DMAEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11318 #define SDHC_XFERTYP_DMAEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11319 #define SDHC_XFERTYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 11320 #define SDHC_XFERTYP_BCEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11321 #define SDHC_XFERTYP_BCEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11322 #define SDHC_XFERTYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)
AnnaBridge 171:3a7713b1edbc 11323 #define SDHC_XFERTYP_AC12EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11324 #define SDHC_XFERTYP_AC12EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11325 #define SDHC_XFERTYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)
AnnaBridge 171:3a7713b1edbc 11326 #define SDHC_XFERTYP_DTDSEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11327 #define SDHC_XFERTYP_DTDSEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11328 #define SDHC_XFERTYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)
AnnaBridge 171:3a7713b1edbc 11329 #define SDHC_XFERTYP_MSBSEL_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11330 #define SDHC_XFERTYP_MSBSEL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11331 #define SDHC_XFERTYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)
AnnaBridge 171:3a7713b1edbc 11332 #define SDHC_XFERTYP_RSPTYP_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 11333 #define SDHC_XFERTYP_RSPTYP_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11334 #define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
AnnaBridge 171:3a7713b1edbc 11335 #define SDHC_XFERTYP_CCCEN_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 11336 #define SDHC_XFERTYP_CCCEN_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 11337 #define SDHC_XFERTYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)
AnnaBridge 171:3a7713b1edbc 11338 #define SDHC_XFERTYP_CICEN_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 11339 #define SDHC_XFERTYP_CICEN_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 11340 #define SDHC_XFERTYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)
AnnaBridge 171:3a7713b1edbc 11341 #define SDHC_XFERTYP_DPSEL_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 11342 #define SDHC_XFERTYP_DPSEL_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 11343 #define SDHC_XFERTYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)
AnnaBridge 171:3a7713b1edbc 11344 #define SDHC_XFERTYP_CMDTYP_MASK (0xC00000U)
AnnaBridge 171:3a7713b1edbc 11345 #define SDHC_XFERTYP_CMDTYP_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 11346 #define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
AnnaBridge 171:3a7713b1edbc 11347 #define SDHC_XFERTYP_CMDINX_MASK (0x3F000000U)
AnnaBridge 171:3a7713b1edbc 11348 #define SDHC_XFERTYP_CMDINX_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11349 #define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
AnnaBridge 171:3a7713b1edbc 11350
AnnaBridge 171:3a7713b1edbc 11351 /*! @name CMDRSP - Command Response 0..Command Response 3 */
AnnaBridge 171:3a7713b1edbc 11352 #define SDHC_CMDRSP_CMDRSP0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 11353 #define SDHC_CMDRSP_CMDRSP0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11354 #define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK)
AnnaBridge 171:3a7713b1edbc 11355 #define SDHC_CMDRSP_CMDRSP1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 11356 #define SDHC_CMDRSP_CMDRSP1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11357 #define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK)
AnnaBridge 171:3a7713b1edbc 11358 #define SDHC_CMDRSP_CMDRSP2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 11359 #define SDHC_CMDRSP_CMDRSP2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11360 #define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK)
AnnaBridge 171:3a7713b1edbc 11361 #define SDHC_CMDRSP_CMDRSP3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 11362 #define SDHC_CMDRSP_CMDRSP3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11363 #define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK)
AnnaBridge 171:3a7713b1edbc 11364
AnnaBridge 171:3a7713b1edbc 11365 /* The count of SDHC_CMDRSP */
AnnaBridge 171:3a7713b1edbc 11366 #define SDHC_CMDRSP_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 11367
AnnaBridge 171:3a7713b1edbc 11368 /*! @name DATPORT - Buffer Data Port register */
AnnaBridge 171:3a7713b1edbc 11369 #define SDHC_DATPORT_DATCONT_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 11370 #define SDHC_DATPORT_DATCONT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11371 #define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK)
AnnaBridge 171:3a7713b1edbc 11372
AnnaBridge 171:3a7713b1edbc 11373 /*! @name PRSSTAT - Present State register */
AnnaBridge 171:3a7713b1edbc 11374 #define SDHC_PRSSTAT_CIHB_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11375 #define SDHC_PRSSTAT_CIHB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11376 #define SDHC_PRSSTAT_CIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)
AnnaBridge 171:3a7713b1edbc 11377 #define SDHC_PRSSTAT_CDIHB_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11378 #define SDHC_PRSSTAT_CDIHB_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11379 #define SDHC_PRSSTAT_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)
AnnaBridge 171:3a7713b1edbc 11380 #define SDHC_PRSSTAT_DLA_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11381 #define SDHC_PRSSTAT_DLA_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11382 #define SDHC_PRSSTAT_DLA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)
AnnaBridge 171:3a7713b1edbc 11383 #define SDHC_PRSSTAT_SDSTB_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11384 #define SDHC_PRSSTAT_SDSTB_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11385 #define SDHC_PRSSTAT_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)
AnnaBridge 171:3a7713b1edbc 11386 #define SDHC_PRSSTAT_IPGOFF_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11387 #define SDHC_PRSSTAT_IPGOFF_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11388 #define SDHC_PRSSTAT_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)
AnnaBridge 171:3a7713b1edbc 11389 #define SDHC_PRSSTAT_HCKOFF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11390 #define SDHC_PRSSTAT_HCKOFF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11391 #define SDHC_PRSSTAT_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)
AnnaBridge 171:3a7713b1edbc 11392 #define SDHC_PRSSTAT_PEROFF_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11393 #define SDHC_PRSSTAT_PEROFF_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11394 #define SDHC_PRSSTAT_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)
AnnaBridge 171:3a7713b1edbc 11395 #define SDHC_PRSSTAT_SDOFF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11396 #define SDHC_PRSSTAT_SDOFF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11397 #define SDHC_PRSSTAT_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)
AnnaBridge 171:3a7713b1edbc 11398 #define SDHC_PRSSTAT_WTA_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 11399 #define SDHC_PRSSTAT_WTA_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11400 #define SDHC_PRSSTAT_WTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)
AnnaBridge 171:3a7713b1edbc 11401 #define SDHC_PRSSTAT_RTA_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 11402 #define SDHC_PRSSTAT_RTA_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 11403 #define SDHC_PRSSTAT_RTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)
AnnaBridge 171:3a7713b1edbc 11404 #define SDHC_PRSSTAT_BWEN_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 11405 #define SDHC_PRSSTAT_BWEN_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 11406 #define SDHC_PRSSTAT_BWEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)
AnnaBridge 171:3a7713b1edbc 11407 #define SDHC_PRSSTAT_BREN_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 11408 #define SDHC_PRSSTAT_BREN_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 11409 #define SDHC_PRSSTAT_BREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)
AnnaBridge 171:3a7713b1edbc 11410 #define SDHC_PRSSTAT_CINS_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 11411 #define SDHC_PRSSTAT_CINS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11412 #define SDHC_PRSSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)
AnnaBridge 171:3a7713b1edbc 11413 #define SDHC_PRSSTAT_CLSL_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 11414 #define SDHC_PRSSTAT_CLSL_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 11415 #define SDHC_PRSSTAT_CLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK)
AnnaBridge 171:3a7713b1edbc 11416 #define SDHC_PRSSTAT_DLSL_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11417 #define SDHC_PRSSTAT_DLSL_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11418 #define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
AnnaBridge 171:3a7713b1edbc 11419
AnnaBridge 171:3a7713b1edbc 11420 /*! @name PROCTL - Protocol Control register */
AnnaBridge 171:3a7713b1edbc 11421 #define SDHC_PROCTL_LCTL_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11422 #define SDHC_PROCTL_LCTL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11423 #define SDHC_PROCTL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)
AnnaBridge 171:3a7713b1edbc 11424 #define SDHC_PROCTL_DTW_MASK (0x6U)
AnnaBridge 171:3a7713b1edbc 11425 #define SDHC_PROCTL_DTW_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11426 #define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
AnnaBridge 171:3a7713b1edbc 11427 #define SDHC_PROCTL_D3CD_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11428 #define SDHC_PROCTL_D3CD_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11429 #define SDHC_PROCTL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)
AnnaBridge 171:3a7713b1edbc 11430 #define SDHC_PROCTL_EMODE_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 11431 #define SDHC_PROCTL_EMODE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11432 #define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
AnnaBridge 171:3a7713b1edbc 11433 #define SDHC_PROCTL_CDTL_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11434 #define SDHC_PROCTL_CDTL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11435 #define SDHC_PROCTL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)
AnnaBridge 171:3a7713b1edbc 11436 #define SDHC_PROCTL_CDSS_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11437 #define SDHC_PROCTL_CDSS_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11438 #define SDHC_PROCTL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)
AnnaBridge 171:3a7713b1edbc 11439 #define SDHC_PROCTL_DMAS_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 11440 #define SDHC_PROCTL_DMAS_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11441 #define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
AnnaBridge 171:3a7713b1edbc 11442 #define SDHC_PROCTL_SABGREQ_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 11443 #define SDHC_PROCTL_SABGREQ_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11444 #define SDHC_PROCTL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)
AnnaBridge 171:3a7713b1edbc 11445 #define SDHC_PROCTL_CREQ_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 11446 #define SDHC_PROCTL_CREQ_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 11447 #define SDHC_PROCTL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)
AnnaBridge 171:3a7713b1edbc 11448 #define SDHC_PROCTL_RWCTL_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 11449 #define SDHC_PROCTL_RWCTL_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 11450 #define SDHC_PROCTL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)
AnnaBridge 171:3a7713b1edbc 11451 #define SDHC_PROCTL_IABG_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 11452 #define SDHC_PROCTL_IABG_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 11453 #define SDHC_PROCTL_IABG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)
AnnaBridge 171:3a7713b1edbc 11454 #define SDHC_PROCTL_WECINT_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 11455 #define SDHC_PROCTL_WECINT_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11456 #define SDHC_PROCTL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)
AnnaBridge 171:3a7713b1edbc 11457 #define SDHC_PROCTL_WECINS_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 11458 #define SDHC_PROCTL_WECINS_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 11459 #define SDHC_PROCTL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)
AnnaBridge 171:3a7713b1edbc 11460 #define SDHC_PROCTL_WECRM_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 11461 #define SDHC_PROCTL_WECRM_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 11462 #define SDHC_PROCTL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)
AnnaBridge 171:3a7713b1edbc 11463
AnnaBridge 171:3a7713b1edbc 11464 /*! @name SYSCTL - System Control register */
AnnaBridge 171:3a7713b1edbc 11465 #define SDHC_SYSCTL_IPGEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11466 #define SDHC_SYSCTL_IPGEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11467 #define SDHC_SYSCTL_IPGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)
AnnaBridge 171:3a7713b1edbc 11468 #define SDHC_SYSCTL_HCKEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11469 #define SDHC_SYSCTL_HCKEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11470 #define SDHC_SYSCTL_HCKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)
AnnaBridge 171:3a7713b1edbc 11471 #define SDHC_SYSCTL_PEREN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11472 #define SDHC_SYSCTL_PEREN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11473 #define SDHC_SYSCTL_PEREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)
AnnaBridge 171:3a7713b1edbc 11474 #define SDHC_SYSCTL_SDCLKEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11475 #define SDHC_SYSCTL_SDCLKEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11476 #define SDHC_SYSCTL_SDCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK)
AnnaBridge 171:3a7713b1edbc 11477 #define SDHC_SYSCTL_DVS_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 11478 #define SDHC_SYSCTL_DVS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11479 #define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
AnnaBridge 171:3a7713b1edbc 11480 #define SDHC_SYSCTL_SDCLKFS_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11481 #define SDHC_SYSCTL_SDCLKFS_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11482 #define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
AnnaBridge 171:3a7713b1edbc 11483 #define SDHC_SYSCTL_DTOCV_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 11484 #define SDHC_SYSCTL_DTOCV_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11485 #define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
AnnaBridge 171:3a7713b1edbc 11486 #define SDHC_SYSCTL_RSTA_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 11487 #define SDHC_SYSCTL_RSTA_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11488 #define SDHC_SYSCTL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)
AnnaBridge 171:3a7713b1edbc 11489 #define SDHC_SYSCTL_RSTC_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 11490 #define SDHC_SYSCTL_RSTC_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 11491 #define SDHC_SYSCTL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)
AnnaBridge 171:3a7713b1edbc 11492 #define SDHC_SYSCTL_RSTD_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 11493 #define SDHC_SYSCTL_RSTD_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 11494 #define SDHC_SYSCTL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)
AnnaBridge 171:3a7713b1edbc 11495 #define SDHC_SYSCTL_INITA_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 11496 #define SDHC_SYSCTL_INITA_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 11497 #define SDHC_SYSCTL_INITA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK)
AnnaBridge 171:3a7713b1edbc 11498
AnnaBridge 171:3a7713b1edbc 11499 /*! @name IRQSTAT - Interrupt Status register */
AnnaBridge 171:3a7713b1edbc 11500 #define SDHC_IRQSTAT_CC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11501 #define SDHC_IRQSTAT_CC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11502 #define SDHC_IRQSTAT_CC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)
AnnaBridge 171:3a7713b1edbc 11503 #define SDHC_IRQSTAT_TC_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11504 #define SDHC_IRQSTAT_TC_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11505 #define SDHC_IRQSTAT_TC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)
AnnaBridge 171:3a7713b1edbc 11506 #define SDHC_IRQSTAT_BGE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11507 #define SDHC_IRQSTAT_BGE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11508 #define SDHC_IRQSTAT_BGE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)
AnnaBridge 171:3a7713b1edbc 11509 #define SDHC_IRQSTAT_DINT_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11510 #define SDHC_IRQSTAT_DINT_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11511 #define SDHC_IRQSTAT_DINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)
AnnaBridge 171:3a7713b1edbc 11512 #define SDHC_IRQSTAT_BWR_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11513 #define SDHC_IRQSTAT_BWR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11514 #define SDHC_IRQSTAT_BWR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)
AnnaBridge 171:3a7713b1edbc 11515 #define SDHC_IRQSTAT_BRR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11516 #define SDHC_IRQSTAT_BRR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11517 #define SDHC_IRQSTAT_BRR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)
AnnaBridge 171:3a7713b1edbc 11518 #define SDHC_IRQSTAT_CINS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11519 #define SDHC_IRQSTAT_CINS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11520 #define SDHC_IRQSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)
AnnaBridge 171:3a7713b1edbc 11521 #define SDHC_IRQSTAT_CRM_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11522 #define SDHC_IRQSTAT_CRM_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11523 #define SDHC_IRQSTAT_CRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)
AnnaBridge 171:3a7713b1edbc 11524 #define SDHC_IRQSTAT_CINT_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 11525 #define SDHC_IRQSTAT_CINT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11526 #define SDHC_IRQSTAT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)
AnnaBridge 171:3a7713b1edbc 11527 #define SDHC_IRQSTAT_CTOE_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 11528 #define SDHC_IRQSTAT_CTOE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11529 #define SDHC_IRQSTAT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)
AnnaBridge 171:3a7713b1edbc 11530 #define SDHC_IRQSTAT_CCE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 11531 #define SDHC_IRQSTAT_CCE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 11532 #define SDHC_IRQSTAT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)
AnnaBridge 171:3a7713b1edbc 11533 #define SDHC_IRQSTAT_CEBE_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 11534 #define SDHC_IRQSTAT_CEBE_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 11535 #define SDHC_IRQSTAT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)
AnnaBridge 171:3a7713b1edbc 11536 #define SDHC_IRQSTAT_CIE_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 11537 #define SDHC_IRQSTAT_CIE_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 11538 #define SDHC_IRQSTAT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)
AnnaBridge 171:3a7713b1edbc 11539 #define SDHC_IRQSTAT_DTOE_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 11540 #define SDHC_IRQSTAT_DTOE_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 11541 #define SDHC_IRQSTAT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)
AnnaBridge 171:3a7713b1edbc 11542 #define SDHC_IRQSTAT_DCE_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 11543 #define SDHC_IRQSTAT_DCE_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 11544 #define SDHC_IRQSTAT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)
AnnaBridge 171:3a7713b1edbc 11545 #define SDHC_IRQSTAT_DEBE_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 11546 #define SDHC_IRQSTAT_DEBE_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 11547 #define SDHC_IRQSTAT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)
AnnaBridge 171:3a7713b1edbc 11548 #define SDHC_IRQSTAT_AC12E_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 11549 #define SDHC_IRQSTAT_AC12E_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11550 #define SDHC_IRQSTAT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)
AnnaBridge 171:3a7713b1edbc 11551 #define SDHC_IRQSTAT_DMAE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 11552 #define SDHC_IRQSTAT_DMAE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 11553 #define SDHC_IRQSTAT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)
AnnaBridge 171:3a7713b1edbc 11554
AnnaBridge 171:3a7713b1edbc 11555 /*! @name IRQSTATEN - Interrupt Status Enable register */
AnnaBridge 171:3a7713b1edbc 11556 #define SDHC_IRQSTATEN_CCSEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11557 #define SDHC_IRQSTATEN_CCSEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11558 #define SDHC_IRQSTATEN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)
AnnaBridge 171:3a7713b1edbc 11559 #define SDHC_IRQSTATEN_TCSEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11560 #define SDHC_IRQSTATEN_TCSEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11561 #define SDHC_IRQSTATEN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)
AnnaBridge 171:3a7713b1edbc 11562 #define SDHC_IRQSTATEN_BGESEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11563 #define SDHC_IRQSTATEN_BGESEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11564 #define SDHC_IRQSTATEN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)
AnnaBridge 171:3a7713b1edbc 11565 #define SDHC_IRQSTATEN_DINTSEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11566 #define SDHC_IRQSTATEN_DINTSEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11567 #define SDHC_IRQSTATEN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)
AnnaBridge 171:3a7713b1edbc 11568 #define SDHC_IRQSTATEN_BWRSEN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11569 #define SDHC_IRQSTATEN_BWRSEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11570 #define SDHC_IRQSTATEN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)
AnnaBridge 171:3a7713b1edbc 11571 #define SDHC_IRQSTATEN_BRRSEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11572 #define SDHC_IRQSTATEN_BRRSEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11573 #define SDHC_IRQSTATEN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)
AnnaBridge 171:3a7713b1edbc 11574 #define SDHC_IRQSTATEN_CINSEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11575 #define SDHC_IRQSTATEN_CINSEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11576 #define SDHC_IRQSTATEN_CINSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)
AnnaBridge 171:3a7713b1edbc 11577 #define SDHC_IRQSTATEN_CRMSEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11578 #define SDHC_IRQSTATEN_CRMSEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11579 #define SDHC_IRQSTATEN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)
AnnaBridge 171:3a7713b1edbc 11580 #define SDHC_IRQSTATEN_CINTSEN_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 11581 #define SDHC_IRQSTATEN_CINTSEN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11582 #define SDHC_IRQSTATEN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)
AnnaBridge 171:3a7713b1edbc 11583 #define SDHC_IRQSTATEN_CTOESEN_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 11584 #define SDHC_IRQSTATEN_CTOESEN_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11585 #define SDHC_IRQSTATEN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)
AnnaBridge 171:3a7713b1edbc 11586 #define SDHC_IRQSTATEN_CCESEN_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 11587 #define SDHC_IRQSTATEN_CCESEN_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 11588 #define SDHC_IRQSTATEN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)
AnnaBridge 171:3a7713b1edbc 11589 #define SDHC_IRQSTATEN_CEBESEN_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 11590 #define SDHC_IRQSTATEN_CEBESEN_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 11591 #define SDHC_IRQSTATEN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)
AnnaBridge 171:3a7713b1edbc 11592 #define SDHC_IRQSTATEN_CIESEN_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 11593 #define SDHC_IRQSTATEN_CIESEN_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 11594 #define SDHC_IRQSTATEN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)
AnnaBridge 171:3a7713b1edbc 11595 #define SDHC_IRQSTATEN_DTOESEN_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 11596 #define SDHC_IRQSTATEN_DTOESEN_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 11597 #define SDHC_IRQSTATEN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)
AnnaBridge 171:3a7713b1edbc 11598 #define SDHC_IRQSTATEN_DCESEN_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 11599 #define SDHC_IRQSTATEN_DCESEN_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 11600 #define SDHC_IRQSTATEN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)
AnnaBridge 171:3a7713b1edbc 11601 #define SDHC_IRQSTATEN_DEBESEN_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 11602 #define SDHC_IRQSTATEN_DEBESEN_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 11603 #define SDHC_IRQSTATEN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)
AnnaBridge 171:3a7713b1edbc 11604 #define SDHC_IRQSTATEN_AC12ESEN_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 11605 #define SDHC_IRQSTATEN_AC12ESEN_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11606 #define SDHC_IRQSTATEN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)
AnnaBridge 171:3a7713b1edbc 11607 #define SDHC_IRQSTATEN_DMAESEN_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 11608 #define SDHC_IRQSTATEN_DMAESEN_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 11609 #define SDHC_IRQSTATEN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)
AnnaBridge 171:3a7713b1edbc 11610
AnnaBridge 171:3a7713b1edbc 11611 /*! @name IRQSIGEN - Interrupt Signal Enable register */
AnnaBridge 171:3a7713b1edbc 11612 #define SDHC_IRQSIGEN_CCIEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11613 #define SDHC_IRQSIGEN_CCIEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11614 #define SDHC_IRQSIGEN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)
AnnaBridge 171:3a7713b1edbc 11615 #define SDHC_IRQSIGEN_TCIEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11616 #define SDHC_IRQSIGEN_TCIEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11617 #define SDHC_IRQSIGEN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)
AnnaBridge 171:3a7713b1edbc 11618 #define SDHC_IRQSIGEN_BGEIEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11619 #define SDHC_IRQSIGEN_BGEIEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11620 #define SDHC_IRQSIGEN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)
AnnaBridge 171:3a7713b1edbc 11621 #define SDHC_IRQSIGEN_DINTIEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11622 #define SDHC_IRQSIGEN_DINTIEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11623 #define SDHC_IRQSIGEN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)
AnnaBridge 171:3a7713b1edbc 11624 #define SDHC_IRQSIGEN_BWRIEN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11625 #define SDHC_IRQSIGEN_BWRIEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11626 #define SDHC_IRQSIGEN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)
AnnaBridge 171:3a7713b1edbc 11627 #define SDHC_IRQSIGEN_BRRIEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11628 #define SDHC_IRQSIGEN_BRRIEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11629 #define SDHC_IRQSIGEN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)
AnnaBridge 171:3a7713b1edbc 11630 #define SDHC_IRQSIGEN_CINSIEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11631 #define SDHC_IRQSIGEN_CINSIEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11632 #define SDHC_IRQSIGEN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)
AnnaBridge 171:3a7713b1edbc 11633 #define SDHC_IRQSIGEN_CRMIEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11634 #define SDHC_IRQSIGEN_CRMIEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11635 #define SDHC_IRQSIGEN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)
AnnaBridge 171:3a7713b1edbc 11636 #define SDHC_IRQSIGEN_CINTIEN_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 11637 #define SDHC_IRQSIGEN_CINTIEN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11638 #define SDHC_IRQSIGEN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)
AnnaBridge 171:3a7713b1edbc 11639 #define SDHC_IRQSIGEN_CTOEIEN_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 11640 #define SDHC_IRQSIGEN_CTOEIEN_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11641 #define SDHC_IRQSIGEN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)
AnnaBridge 171:3a7713b1edbc 11642 #define SDHC_IRQSIGEN_CCEIEN_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 11643 #define SDHC_IRQSIGEN_CCEIEN_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 11644 #define SDHC_IRQSIGEN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)
AnnaBridge 171:3a7713b1edbc 11645 #define SDHC_IRQSIGEN_CEBEIEN_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 11646 #define SDHC_IRQSIGEN_CEBEIEN_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 11647 #define SDHC_IRQSIGEN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)
AnnaBridge 171:3a7713b1edbc 11648 #define SDHC_IRQSIGEN_CIEIEN_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 11649 #define SDHC_IRQSIGEN_CIEIEN_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 11650 #define SDHC_IRQSIGEN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)
AnnaBridge 171:3a7713b1edbc 11651 #define SDHC_IRQSIGEN_DTOEIEN_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 11652 #define SDHC_IRQSIGEN_DTOEIEN_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 11653 #define SDHC_IRQSIGEN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)
AnnaBridge 171:3a7713b1edbc 11654 #define SDHC_IRQSIGEN_DCEIEN_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 11655 #define SDHC_IRQSIGEN_DCEIEN_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 11656 #define SDHC_IRQSIGEN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)
AnnaBridge 171:3a7713b1edbc 11657 #define SDHC_IRQSIGEN_DEBEIEN_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 11658 #define SDHC_IRQSIGEN_DEBEIEN_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 11659 #define SDHC_IRQSIGEN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)
AnnaBridge 171:3a7713b1edbc 11660 #define SDHC_IRQSIGEN_AC12EIEN_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 11661 #define SDHC_IRQSIGEN_AC12EIEN_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11662 #define SDHC_IRQSIGEN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)
AnnaBridge 171:3a7713b1edbc 11663 #define SDHC_IRQSIGEN_DMAEIEN_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 11664 #define SDHC_IRQSIGEN_DMAEIEN_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 11665 #define SDHC_IRQSIGEN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)
AnnaBridge 171:3a7713b1edbc 11666
AnnaBridge 171:3a7713b1edbc 11667 /*! @name AC12ERR - Auto CMD12 Error Status Register */
AnnaBridge 171:3a7713b1edbc 11668 #define SDHC_AC12ERR_AC12NE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11669 #define SDHC_AC12ERR_AC12NE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11670 #define SDHC_AC12ERR_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)
AnnaBridge 171:3a7713b1edbc 11671 #define SDHC_AC12ERR_AC12TOE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11672 #define SDHC_AC12ERR_AC12TOE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11673 #define SDHC_AC12ERR_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)
AnnaBridge 171:3a7713b1edbc 11674 #define SDHC_AC12ERR_AC12EBE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11675 #define SDHC_AC12ERR_AC12EBE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11676 #define SDHC_AC12ERR_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)
AnnaBridge 171:3a7713b1edbc 11677 #define SDHC_AC12ERR_AC12CE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11678 #define SDHC_AC12ERR_AC12CE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11679 #define SDHC_AC12ERR_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)
AnnaBridge 171:3a7713b1edbc 11680 #define SDHC_AC12ERR_AC12IE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11681 #define SDHC_AC12ERR_AC12IE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11682 #define SDHC_AC12ERR_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)
AnnaBridge 171:3a7713b1edbc 11683 #define SDHC_AC12ERR_CNIBAC12E_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11684 #define SDHC_AC12ERR_CNIBAC12E_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11685 #define SDHC_AC12ERR_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)
AnnaBridge 171:3a7713b1edbc 11686
AnnaBridge 171:3a7713b1edbc 11687 /*! @name HTCAPBLT - Host Controller Capabilities */
AnnaBridge 171:3a7713b1edbc 11688 #define SDHC_HTCAPBLT_MBL_MASK (0x70000U)
AnnaBridge 171:3a7713b1edbc 11689 #define SDHC_HTCAPBLT_MBL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11690 #define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
AnnaBridge 171:3a7713b1edbc 11691 #define SDHC_HTCAPBLT_ADMAS_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 11692 #define SDHC_HTCAPBLT_ADMAS_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 11693 #define SDHC_HTCAPBLT_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)
AnnaBridge 171:3a7713b1edbc 11694 #define SDHC_HTCAPBLT_HSS_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 11695 #define SDHC_HTCAPBLT_HSS_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 11696 #define SDHC_HTCAPBLT_HSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)
AnnaBridge 171:3a7713b1edbc 11697 #define SDHC_HTCAPBLT_DMAS_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 11698 #define SDHC_HTCAPBLT_DMAS_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 11699 #define SDHC_HTCAPBLT_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)
AnnaBridge 171:3a7713b1edbc 11700 #define SDHC_HTCAPBLT_SRS_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 11701 #define SDHC_HTCAPBLT_SRS_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 11702 #define SDHC_HTCAPBLT_SRS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)
AnnaBridge 171:3a7713b1edbc 11703 #define SDHC_HTCAPBLT_VS33_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 11704 #define SDHC_HTCAPBLT_VS33_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11705 #define SDHC_HTCAPBLT_VS33(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)
AnnaBridge 171:3a7713b1edbc 11706
AnnaBridge 171:3a7713b1edbc 11707 /*! @name WML - Watermark Level Register */
AnnaBridge 171:3a7713b1edbc 11708 #define SDHC_WML_RDWML_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11709 #define SDHC_WML_RDWML_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11710 #define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
AnnaBridge 171:3a7713b1edbc 11711 #define SDHC_WML_WRWML_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11712 #define SDHC_WML_WRWML_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11713 #define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
AnnaBridge 171:3a7713b1edbc 11714
AnnaBridge 171:3a7713b1edbc 11715 /*! @name FEVT - Force Event register */
AnnaBridge 171:3a7713b1edbc 11716 #define SDHC_FEVT_AC12NE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11717 #define SDHC_FEVT_AC12NE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11718 #define SDHC_FEVT_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK)
AnnaBridge 171:3a7713b1edbc 11719 #define SDHC_FEVT_AC12TOE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11720 #define SDHC_FEVT_AC12TOE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11721 #define SDHC_FEVT_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK)
AnnaBridge 171:3a7713b1edbc 11722 #define SDHC_FEVT_AC12CE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11723 #define SDHC_FEVT_AC12CE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11724 #define SDHC_FEVT_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK)
AnnaBridge 171:3a7713b1edbc 11725 #define SDHC_FEVT_AC12EBE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11726 #define SDHC_FEVT_AC12EBE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11727 #define SDHC_FEVT_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK)
AnnaBridge 171:3a7713b1edbc 11728 #define SDHC_FEVT_AC12IE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11729 #define SDHC_FEVT_AC12IE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11730 #define SDHC_FEVT_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK)
AnnaBridge 171:3a7713b1edbc 11731 #define SDHC_FEVT_CNIBAC12E_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11732 #define SDHC_FEVT_CNIBAC12E_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11733 #define SDHC_FEVT_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK)
AnnaBridge 171:3a7713b1edbc 11734 #define SDHC_FEVT_CTOE_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 11735 #define SDHC_FEVT_CTOE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11736 #define SDHC_FEVT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK)
AnnaBridge 171:3a7713b1edbc 11737 #define SDHC_FEVT_CCE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 11738 #define SDHC_FEVT_CCE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 11739 #define SDHC_FEVT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK)
AnnaBridge 171:3a7713b1edbc 11740 #define SDHC_FEVT_CEBE_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 11741 #define SDHC_FEVT_CEBE_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 11742 #define SDHC_FEVT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK)
AnnaBridge 171:3a7713b1edbc 11743 #define SDHC_FEVT_CIE_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 11744 #define SDHC_FEVT_CIE_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 11745 #define SDHC_FEVT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK)
AnnaBridge 171:3a7713b1edbc 11746 #define SDHC_FEVT_DTOE_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 11747 #define SDHC_FEVT_DTOE_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 11748 #define SDHC_FEVT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK)
AnnaBridge 171:3a7713b1edbc 11749 #define SDHC_FEVT_DCE_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 11750 #define SDHC_FEVT_DCE_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 11751 #define SDHC_FEVT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK)
AnnaBridge 171:3a7713b1edbc 11752 #define SDHC_FEVT_DEBE_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 11753 #define SDHC_FEVT_DEBE_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 11754 #define SDHC_FEVT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK)
AnnaBridge 171:3a7713b1edbc 11755 #define SDHC_FEVT_AC12E_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 11756 #define SDHC_FEVT_AC12E_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11757 #define SDHC_FEVT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK)
AnnaBridge 171:3a7713b1edbc 11758 #define SDHC_FEVT_DMAE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 11759 #define SDHC_FEVT_DMAE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 11760 #define SDHC_FEVT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK)
AnnaBridge 171:3a7713b1edbc 11761 #define SDHC_FEVT_CINT_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 11762 #define SDHC_FEVT_CINT_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 11763 #define SDHC_FEVT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK)
AnnaBridge 171:3a7713b1edbc 11764
AnnaBridge 171:3a7713b1edbc 11765 /*! @name ADMAES - ADMA Error Status register */
AnnaBridge 171:3a7713b1edbc 11766 #define SDHC_ADMAES_ADMAES_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 11767 #define SDHC_ADMAES_ADMAES_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11768 #define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
AnnaBridge 171:3a7713b1edbc 11769 #define SDHC_ADMAES_ADMALME_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11770 #define SDHC_ADMAES_ADMALME_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11771 #define SDHC_ADMAES_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)
AnnaBridge 171:3a7713b1edbc 11772 #define SDHC_ADMAES_ADMADCE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11773 #define SDHC_ADMAES_ADMADCE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11774 #define SDHC_ADMAES_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)
AnnaBridge 171:3a7713b1edbc 11775
AnnaBridge 171:3a7713b1edbc 11776 /*! @name ADSADDR - ADMA System Addressregister */
AnnaBridge 171:3a7713b1edbc 11777 #define SDHC_ADSADDR_ADSADDR_MASK (0xFFFFFFFCU)
AnnaBridge 171:3a7713b1edbc 11778 #define SDHC_ADSADDR_ADSADDR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11779 #define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK)
AnnaBridge 171:3a7713b1edbc 11780
AnnaBridge 171:3a7713b1edbc 11781 /*! @name VENDOR - Vendor Specific register */
AnnaBridge 171:3a7713b1edbc 11782 #define SDHC_VENDOR_EXBLKNU_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11783 #define SDHC_VENDOR_EXBLKNU_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11784 #define SDHC_VENDOR_EXBLKNU(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)
AnnaBridge 171:3a7713b1edbc 11785 #define SDHC_VENDOR_INTSTVAL_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11786 #define SDHC_VENDOR_INTSTVAL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11787 #define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
AnnaBridge 171:3a7713b1edbc 11788
AnnaBridge 171:3a7713b1edbc 11789 /*! @name MMCBOOT - MMC Boot register */
AnnaBridge 171:3a7713b1edbc 11790 #define SDHC_MMCBOOT_DTOCVACK_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 11791 #define SDHC_MMCBOOT_DTOCVACK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11792 #define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
AnnaBridge 171:3a7713b1edbc 11793 #define SDHC_MMCBOOT_BOOTACK_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11794 #define SDHC_MMCBOOT_BOOTACK_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11795 #define SDHC_MMCBOOT_BOOTACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)
AnnaBridge 171:3a7713b1edbc 11796 #define SDHC_MMCBOOT_BOOTMODE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11797 #define SDHC_MMCBOOT_BOOTMODE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11798 #define SDHC_MMCBOOT_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)
AnnaBridge 171:3a7713b1edbc 11799 #define SDHC_MMCBOOT_BOOTEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11800 #define SDHC_MMCBOOT_BOOTEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11801 #define SDHC_MMCBOOT_BOOTEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)
AnnaBridge 171:3a7713b1edbc 11802 #define SDHC_MMCBOOT_AUTOSABGEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11803 #define SDHC_MMCBOOT_AUTOSABGEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11804 #define SDHC_MMCBOOT_AUTOSABGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK)
AnnaBridge 171:3a7713b1edbc 11805 #define SDHC_MMCBOOT_BOOTBLKCNT_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 11806 #define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11807 #define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
AnnaBridge 171:3a7713b1edbc 11808
AnnaBridge 171:3a7713b1edbc 11809 /*! @name HOSTVER - Host Controller Version */
AnnaBridge 171:3a7713b1edbc 11810 #define SDHC_HOSTVER_SVN_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11811 #define SDHC_HOSTVER_SVN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11812 #define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
AnnaBridge 171:3a7713b1edbc 11813 #define SDHC_HOSTVER_VVN_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11814 #define SDHC_HOSTVER_VVN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11815 #define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
AnnaBridge 171:3a7713b1edbc 11816
AnnaBridge 171:3a7713b1edbc 11817
AnnaBridge 171:3a7713b1edbc 11818 /*!
AnnaBridge 171:3a7713b1edbc 11819 * @}
AnnaBridge 171:3a7713b1edbc 11820 */ /* end of group SDHC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 11821
AnnaBridge 171:3a7713b1edbc 11822
AnnaBridge 171:3a7713b1edbc 11823 /* SDHC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 11824 /** Peripheral SDHC base address */
AnnaBridge 171:3a7713b1edbc 11825 #define SDHC_BASE (0x400B1000u)
AnnaBridge 171:3a7713b1edbc 11826 /** Peripheral SDHC base pointer */
AnnaBridge 171:3a7713b1edbc 11827 #define SDHC ((SDHC_Type *)SDHC_BASE)
AnnaBridge 171:3a7713b1edbc 11828 /** Array initializer of SDHC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 11829 #define SDHC_BASE_ADDRS { SDHC_BASE }
AnnaBridge 171:3a7713b1edbc 11830 /** Array initializer of SDHC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 11831 #define SDHC_BASE_PTRS { SDHC }
AnnaBridge 171:3a7713b1edbc 11832 /** Interrupt vectors for the SDHC peripheral type */
AnnaBridge 171:3a7713b1edbc 11833 #define SDHC_IRQS { SDHC_IRQn }
AnnaBridge 171:3a7713b1edbc 11834
AnnaBridge 171:3a7713b1edbc 11835 /*!
AnnaBridge 171:3a7713b1edbc 11836 * @}
AnnaBridge 171:3a7713b1edbc 11837 */ /* end of group SDHC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 11838
AnnaBridge 171:3a7713b1edbc 11839
AnnaBridge 171:3a7713b1edbc 11840 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11841 -- SDRAM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 11842 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 11843
AnnaBridge 171:3a7713b1edbc 11844 /*!
AnnaBridge 171:3a7713b1edbc 11845 * @addtogroup SDRAM_Peripheral_Access_Layer SDRAM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 11846 * @{
AnnaBridge 171:3a7713b1edbc 11847 */
AnnaBridge 171:3a7713b1edbc 11848
AnnaBridge 171:3a7713b1edbc 11849 /** SDRAM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 11850 typedef struct {
AnnaBridge 171:3a7713b1edbc 11851 uint8_t RESERVED_0[66];
AnnaBridge 171:3a7713b1edbc 11852 __IO uint16_t CTRL; /**< Control Register, offset: 0x42 */
AnnaBridge 171:3a7713b1edbc 11853 uint8_t RESERVED_1[4];
AnnaBridge 171:3a7713b1edbc 11854 struct { /* offset: 0x48, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 11855 __IO uint32_t AC; /**< Address and Control Register, array offset: 0x48, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 11856 __IO uint32_t CM; /**< Control Mask, array offset: 0x4C, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 11857 } BLOCK[2];
AnnaBridge 171:3a7713b1edbc 11858 } SDRAM_Type;
AnnaBridge 171:3a7713b1edbc 11859
AnnaBridge 171:3a7713b1edbc 11860 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11861 -- SDRAM Register Masks
AnnaBridge 171:3a7713b1edbc 11862 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 11863
AnnaBridge 171:3a7713b1edbc 11864 /*!
AnnaBridge 171:3a7713b1edbc 11865 * @addtogroup SDRAM_Register_Masks SDRAM Register Masks
AnnaBridge 171:3a7713b1edbc 11866 * @{
AnnaBridge 171:3a7713b1edbc 11867 */
AnnaBridge 171:3a7713b1edbc 11868
AnnaBridge 171:3a7713b1edbc 11869 /*! @name CTRL - Control Register */
AnnaBridge 171:3a7713b1edbc 11870 #define SDRAM_CTRL_RC_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 11871 #define SDRAM_CTRL_RC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11872 #define SDRAM_CTRL_RC(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RC_SHIFT)) & SDRAM_CTRL_RC_MASK)
AnnaBridge 171:3a7713b1edbc 11873 #define SDRAM_CTRL_RTIM_MASK (0x600U)
AnnaBridge 171:3a7713b1edbc 11874 #define SDRAM_CTRL_RTIM_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 11875 #define SDRAM_CTRL_RTIM(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RTIM_SHIFT)) & SDRAM_CTRL_RTIM_MASK)
AnnaBridge 171:3a7713b1edbc 11876 #define SDRAM_CTRL_IS_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 11877 #define SDRAM_CTRL_IS_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 11878 #define SDRAM_CTRL_IS(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_IS_SHIFT)) & SDRAM_CTRL_IS_MASK)
AnnaBridge 171:3a7713b1edbc 11879
AnnaBridge 171:3a7713b1edbc 11880 /*! @name AC - Address and Control Register */
AnnaBridge 171:3a7713b1edbc 11881 #define SDRAM_AC_IP_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11882 #define SDRAM_AC_IP_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11883 #define SDRAM_AC_IP(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IP_SHIFT)) & SDRAM_AC_IP_MASK)
AnnaBridge 171:3a7713b1edbc 11884 #define SDRAM_AC_PS_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 11885 #define SDRAM_AC_PS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11886 #define SDRAM_AC_PS(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_PS_SHIFT)) & SDRAM_AC_PS_MASK)
AnnaBridge 171:3a7713b1edbc 11887 #define SDRAM_AC_IMRS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11888 #define SDRAM_AC_IMRS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11889 #define SDRAM_AC_IMRS(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IMRS_SHIFT)) & SDRAM_AC_IMRS_MASK)
AnnaBridge 171:3a7713b1edbc 11890 #define SDRAM_AC_CBM_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 11891 #define SDRAM_AC_CBM_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11892 #define SDRAM_AC_CBM(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CBM_SHIFT)) & SDRAM_AC_CBM_MASK)
AnnaBridge 171:3a7713b1edbc 11893 #define SDRAM_AC_CASL_MASK (0x3000U)
AnnaBridge 171:3a7713b1edbc 11894 #define SDRAM_AC_CASL_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 11895 #define SDRAM_AC_CASL(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CASL_SHIFT)) & SDRAM_AC_CASL_MASK)
AnnaBridge 171:3a7713b1edbc 11896 #define SDRAM_AC_RE_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 11897 #define SDRAM_AC_RE_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 11898 #define SDRAM_AC_RE(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_RE_SHIFT)) & SDRAM_AC_RE_MASK)
AnnaBridge 171:3a7713b1edbc 11899 #define SDRAM_AC_BA_MASK (0xFFFC0000U)
AnnaBridge 171:3a7713b1edbc 11900 #define SDRAM_AC_BA_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 11901 #define SDRAM_AC_BA(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_BA_SHIFT)) & SDRAM_AC_BA_MASK)
AnnaBridge 171:3a7713b1edbc 11902
AnnaBridge 171:3a7713b1edbc 11903 /* The count of SDRAM_AC */
AnnaBridge 171:3a7713b1edbc 11904 #define SDRAM_AC_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 11905
AnnaBridge 171:3a7713b1edbc 11906 /*! @name CM - Control Mask */
AnnaBridge 171:3a7713b1edbc 11907 #define SDRAM_CM_V_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11908 #define SDRAM_CM_V_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11909 #define SDRAM_CM_V(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_V_SHIFT)) & SDRAM_CM_V_MASK)
AnnaBridge 171:3a7713b1edbc 11910 #define SDRAM_CM_WP_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 11911 #define SDRAM_CM_WP_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11912 #define SDRAM_CM_WP(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_WP_SHIFT)) & SDRAM_CM_WP_MASK)
AnnaBridge 171:3a7713b1edbc 11913 #define SDRAM_CM_BAM_MASK (0xFFFC0000U)
AnnaBridge 171:3a7713b1edbc 11914 #define SDRAM_CM_BAM_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 11915 #define SDRAM_CM_BAM(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_BAM_SHIFT)) & SDRAM_CM_BAM_MASK)
AnnaBridge 171:3a7713b1edbc 11916
AnnaBridge 171:3a7713b1edbc 11917 /* The count of SDRAM_CM */
AnnaBridge 171:3a7713b1edbc 11918 #define SDRAM_CM_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 11919
AnnaBridge 171:3a7713b1edbc 11920
AnnaBridge 171:3a7713b1edbc 11921 /*!
AnnaBridge 171:3a7713b1edbc 11922 * @}
AnnaBridge 171:3a7713b1edbc 11923 */ /* end of group SDRAM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 11924
AnnaBridge 171:3a7713b1edbc 11925
AnnaBridge 171:3a7713b1edbc 11926 /* SDRAM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 11927 /** Peripheral SDRAM base address */
AnnaBridge 171:3a7713b1edbc 11928 #define SDRAM_BASE (0x4000F000u)
AnnaBridge 171:3a7713b1edbc 11929 /** Peripheral SDRAM base pointer */
AnnaBridge 171:3a7713b1edbc 11930 #define SDRAM ((SDRAM_Type *)SDRAM_BASE)
AnnaBridge 171:3a7713b1edbc 11931 /** Array initializer of SDRAM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 11932 #define SDRAM_BASE_ADDRS { SDRAM_BASE }
AnnaBridge 171:3a7713b1edbc 11933 /** Array initializer of SDRAM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 11934 #define SDRAM_BASE_PTRS { SDRAM }
AnnaBridge 171:3a7713b1edbc 11935
AnnaBridge 171:3a7713b1edbc 11936 /*!
AnnaBridge 171:3a7713b1edbc 11937 * @}
AnnaBridge 171:3a7713b1edbc 11938 */ /* end of group SDRAM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 11939
AnnaBridge 171:3a7713b1edbc 11940
AnnaBridge 171:3a7713b1edbc 11941 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11942 -- SIM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 11943 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 11944
AnnaBridge 171:3a7713b1edbc 11945 /*!
AnnaBridge 171:3a7713b1edbc 11946 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 11947 * @{
AnnaBridge 171:3a7713b1edbc 11948 */
AnnaBridge 171:3a7713b1edbc 11949
AnnaBridge 171:3a7713b1edbc 11950 /** SIM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 11951 typedef struct {
AnnaBridge 171:3a7713b1edbc 11952 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 11953 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 11954 __IO uint32_t USBPHYCTL; /**< USB PHY Control Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 11955 uint8_t RESERVED_0[4088];
AnnaBridge 171:3a7713b1edbc 11956 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
AnnaBridge 171:3a7713b1edbc 11957 uint8_t RESERVED_1[4];
AnnaBridge 171:3a7713b1edbc 11958 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
AnnaBridge 171:3a7713b1edbc 11959 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
AnnaBridge 171:3a7713b1edbc 11960 uint8_t RESERVED_2[4];
AnnaBridge 171:3a7713b1edbc 11961 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
AnnaBridge 171:3a7713b1edbc 11962 __IO uint32_t SOPT8; /**< System Options Register 8, offset: 0x101C */
AnnaBridge 171:3a7713b1edbc 11963 __IO uint32_t SOPT9; /**< System Options Register 9, offset: 0x1020 */
AnnaBridge 171:3a7713b1edbc 11964 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
AnnaBridge 171:3a7713b1edbc 11965 __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
AnnaBridge 171:3a7713b1edbc 11966 __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
AnnaBridge 171:3a7713b1edbc 11967 __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
AnnaBridge 171:3a7713b1edbc 11968 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
AnnaBridge 171:3a7713b1edbc 11969 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
AnnaBridge 171:3a7713b1edbc 11970 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
AnnaBridge 171:3a7713b1edbc 11971 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
AnnaBridge 171:3a7713b1edbc 11972 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
AnnaBridge 171:3a7713b1edbc 11973 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
AnnaBridge 171:3a7713b1edbc 11974 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
AnnaBridge 171:3a7713b1edbc 11975 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
AnnaBridge 171:3a7713b1edbc 11976 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
AnnaBridge 171:3a7713b1edbc 11977 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
AnnaBridge 171:3a7713b1edbc 11978 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
AnnaBridge 171:3a7713b1edbc 11979 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
AnnaBridge 171:3a7713b1edbc 11980 __IO uint32_t CLKDIV3; /**< System Clock Divider Register 3, offset: 0x1064 */
AnnaBridge 171:3a7713b1edbc 11981 __IO uint32_t CLKDIV4; /**< System Clock Divider Register 4, offset: 0x1068 */
AnnaBridge 171:3a7713b1edbc 11982 } SIM_Type;
AnnaBridge 171:3a7713b1edbc 11983
AnnaBridge 171:3a7713b1edbc 11984 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11985 -- SIM Register Masks
AnnaBridge 171:3a7713b1edbc 11986 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 11987
AnnaBridge 171:3a7713b1edbc 11988 /*!
AnnaBridge 171:3a7713b1edbc 11989 * @addtogroup SIM_Register_Masks SIM Register Masks
AnnaBridge 171:3a7713b1edbc 11990 * @{
AnnaBridge 171:3a7713b1edbc 11991 */
AnnaBridge 171:3a7713b1edbc 11992
AnnaBridge 171:3a7713b1edbc 11993 /*! @name SOPT1 - System Options Register 1 */
AnnaBridge 171:3a7713b1edbc 11994 #define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 11995 #define SIM_SOPT1_RAMSIZE_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 11996 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 11997 #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 11998 #define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 11999 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
AnnaBridge 171:3a7713b1edbc 12000 #define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 12001 #define SIM_SOPT1_USBVSTBY_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 12002 #define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
AnnaBridge 171:3a7713b1edbc 12003 #define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 12004 #define SIM_SOPT1_USBSSTBY_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 12005 #define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
AnnaBridge 171:3a7713b1edbc 12006 #define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 12007 #define SIM_SOPT1_USBREGEN_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 12008 #define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
AnnaBridge 171:3a7713b1edbc 12009
AnnaBridge 171:3a7713b1edbc 12010 /*! @name SOPT1CFG - SOPT1 Configuration Register */
AnnaBridge 171:3a7713b1edbc 12011 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 12012 #define SIM_SOPT1CFG_URWE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12013 #define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
AnnaBridge 171:3a7713b1edbc 12014 #define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 12015 #define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 12016 #define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
AnnaBridge 171:3a7713b1edbc 12017 #define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 12018 #define SIM_SOPT1CFG_USSWE_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 12019 #define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
AnnaBridge 171:3a7713b1edbc 12020
AnnaBridge 171:3a7713b1edbc 12021 /*! @name USBPHYCTL - USB PHY Control Register */
AnnaBridge 171:3a7713b1edbc 12022 #define SIM_USBPHYCTL_USBVREGSEL_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 12023 #define SIM_USBPHYCTL_USBVREGSEL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12024 #define SIM_USBPHYCTL_USBVREGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGSEL_SHIFT)) & SIM_USBPHYCTL_USBVREGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 12025 #define SIM_USBPHYCTL_USBVREGPD_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 12026 #define SIM_USBPHYCTL_USBVREGPD_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 12027 #define SIM_USBPHYCTL_USBVREGPD(x) (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGPD_SHIFT)) & SIM_USBPHYCTL_USBVREGPD_MASK)
AnnaBridge 171:3a7713b1edbc 12028 #define SIM_USBPHYCTL_USB3VOUTTRG_MASK (0x700000U)
AnnaBridge 171:3a7713b1edbc 12029 #define SIM_USBPHYCTL_USB3VOUTTRG_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 12030 #define SIM_USBPHYCTL_USB3VOUTTRG(x) (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT)) & SIM_USBPHYCTL_USB3VOUTTRG_MASK)
AnnaBridge 171:3a7713b1edbc 12031 #define SIM_USBPHYCTL_USBDISILIM_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 12032 #define SIM_USBPHYCTL_USBDISILIM_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 12033 #define SIM_USBPHYCTL_USBDISILIM(x) (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBDISILIM_SHIFT)) & SIM_USBPHYCTL_USBDISILIM_MASK)
AnnaBridge 171:3a7713b1edbc 12034
AnnaBridge 171:3a7713b1edbc 12035 /*! @name SOPT2 - System Options Register 2 */
AnnaBridge 171:3a7713b1edbc 12036 #define SIM_SOPT2_USBSLSRC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12037 #define SIM_SOPT2_USBSLSRC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12038 #define SIM_SOPT2_USBSLSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSLSRC_SHIFT)) & SIM_SOPT2_USBSLSRC_MASK)
AnnaBridge 171:3a7713b1edbc 12039 #define SIM_SOPT2_USBREGEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12040 #define SIM_SOPT2_USBREGEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12041 #define SIM_SOPT2_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBREGEN_SHIFT)) & SIM_SOPT2_USBREGEN_MASK)
AnnaBridge 171:3a7713b1edbc 12042 #define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 12043 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12044 #define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 12045 #define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
AnnaBridge 171:3a7713b1edbc 12046 #define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 12047 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 12048 #define SIM_SOPT2_FBSL_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 12049 #define SIM_SOPT2_FBSL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12050 #define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
AnnaBridge 171:3a7713b1edbc 12051 #define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 12052 #define SIM_SOPT2_TRACECLKSEL_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 12053 #define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 12054 #define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 12055 #define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12056 #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
AnnaBridge 171:3a7713b1edbc 12057 #define SIM_SOPT2_USBSRC_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 12058 #define SIM_SOPT2_USBSRC_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 12059 #define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
AnnaBridge 171:3a7713b1edbc 12060 #define SIM_SOPT2_RMIISRC_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 12061 #define SIM_SOPT2_RMIISRC_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 12062 #define SIM_SOPT2_RMIISRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK)
AnnaBridge 171:3a7713b1edbc 12063 #define SIM_SOPT2_TIMESRC_MASK (0x300000U)
AnnaBridge 171:3a7713b1edbc 12064 #define SIM_SOPT2_TIMESRC_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 12065 #define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)
AnnaBridge 171:3a7713b1edbc 12066 #define SIM_SOPT2_TPMSRC_MASK (0x3000000U)
AnnaBridge 171:3a7713b1edbc 12067 #define SIM_SOPT2_TPMSRC_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12068 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
AnnaBridge 171:3a7713b1edbc 12069 #define SIM_SOPT2_LPUARTSRC_MASK (0xC000000U)
AnnaBridge 171:3a7713b1edbc 12070 #define SIM_SOPT2_LPUARTSRC_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 12071 #define SIM_SOPT2_LPUARTSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK)
AnnaBridge 171:3a7713b1edbc 12072 #define SIM_SOPT2_SDHCSRC_MASK (0x30000000U)
AnnaBridge 171:3a7713b1edbc 12073 #define SIM_SOPT2_SDHCSRC_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 12074 #define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
AnnaBridge 171:3a7713b1edbc 12075
AnnaBridge 171:3a7713b1edbc 12076 /*! @name SOPT4 - System Options Register 4 */
AnnaBridge 171:3a7713b1edbc 12077 #define SIM_SOPT4_FTM0FLT0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12078 #define SIM_SOPT4_FTM0FLT0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12079 #define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
AnnaBridge 171:3a7713b1edbc 12080 #define SIM_SOPT4_FTM0FLT1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12081 #define SIM_SOPT4_FTM0FLT1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12082 #define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
AnnaBridge 171:3a7713b1edbc 12083 #define SIM_SOPT4_FTM0FLT2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 12084 #define SIM_SOPT4_FTM0FLT2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12085 #define SIM_SOPT4_FTM0FLT2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)
AnnaBridge 171:3a7713b1edbc 12086 #define SIM_SOPT4_FTM0FLT3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 12087 #define SIM_SOPT4_FTM0FLT3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 12088 #define SIM_SOPT4_FTM0FLT3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT3_SHIFT)) & SIM_SOPT4_FTM0FLT3_MASK)
AnnaBridge 171:3a7713b1edbc 12089 #define SIM_SOPT4_FTM1FLT0_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 12090 #define SIM_SOPT4_FTM1FLT0_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12091 #define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
AnnaBridge 171:3a7713b1edbc 12092 #define SIM_SOPT4_FTM2FLT0_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 12093 #define SIM_SOPT4_FTM2FLT0_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12094 #define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
AnnaBridge 171:3a7713b1edbc 12095 #define SIM_SOPT4_FTM3FLT0_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 12096 #define SIM_SOPT4_FTM3FLT0_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 12097 #define SIM_SOPT4_FTM3FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)
AnnaBridge 171:3a7713b1edbc 12098 #define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 12099 #define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 12100 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12101 #define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U)
AnnaBridge 171:3a7713b1edbc 12102 #define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 12103 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12104 #define SIM_SOPT4_FTM2CH1SRC_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 12105 #define SIM_SOPT4_FTM2CH1SRC_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 12106 #define SIM_SOPT4_FTM2CH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12107 #define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 12108 #define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12109 #define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 12110 #define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 12111 #define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 12112 #define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 12113 #define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 12114 #define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 12115 #define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 12116 #define SIM_SOPT4_FTM3CLKSEL_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 12117 #define SIM_SOPT4_FTM3CLKSEL_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 12118 #define SIM_SOPT4_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 12119 #define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 12120 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 12121 #define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12122 #define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 12123 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 12124 #define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12125 #define SIM_SOPT4_FTM3TRG0SRC_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 12126 #define SIM_SOPT4_FTM3TRG0SRC_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 12127 #define SIM_SOPT4_FTM3TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12128 #define SIM_SOPT4_FTM3TRG1SRC_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 12129 #define SIM_SOPT4_FTM3TRG1SRC_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 12130 #define SIM_SOPT4_FTM3TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12131
AnnaBridge 171:3a7713b1edbc 12132 /*! @name SOPT5 - System Options Register 5 */
AnnaBridge 171:3a7713b1edbc 12133 #define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 12134 #define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12135 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 12136 #define SIM_SOPT5_UART0RXSRC_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 12137 #define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12138 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 12139 #define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 12140 #define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12141 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 12142 #define SIM_SOPT5_UART1RXSRC_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 12143 #define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 12144 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 12145 #define SIM_SOPT5_LPUART0TXSRC_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 12146 #define SIM_SOPT5_LPUART0TXSRC_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12147 #define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 12148 #define SIM_SOPT5_LPUART0RXSRC_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 12149 #define SIM_SOPT5_LPUART0RXSRC_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 12150 #define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 12151
AnnaBridge 171:3a7713b1edbc 12152 /*! @name SOPT7 - System Options Register 7 */
AnnaBridge 171:3a7713b1edbc 12153 #define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 12154 #define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12155 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 12156 #define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 12157 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12158 #define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 12159 #define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 12160 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12161 #define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
AnnaBridge 171:3a7713b1edbc 12162 #define SIM_SOPT7_ADC1TRGSEL_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 12163 #define SIM_SOPT7_ADC1TRGSEL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12164 #define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 12165 #define SIM_SOPT7_ADC1PRETRGSEL_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 12166 #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 12167 #define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 12168 #define SIM_SOPT7_ADC1ALTTRGEN_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 12169 #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 12170 #define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
AnnaBridge 171:3a7713b1edbc 12171
AnnaBridge 171:3a7713b1edbc 12172 /*! @name SOPT8 - System Options Register 8 */
AnnaBridge 171:3a7713b1edbc 12173 #define SIM_SOPT8_FTM0SYNCBIT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12174 #define SIM_SOPT8_FTM0SYNCBIT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12175 #define SIM_SOPT8_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)
AnnaBridge 171:3a7713b1edbc 12176 #define SIM_SOPT8_FTM1SYNCBIT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12177 #define SIM_SOPT8_FTM1SYNCBIT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12178 #define SIM_SOPT8_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)
AnnaBridge 171:3a7713b1edbc 12179 #define SIM_SOPT8_FTM2SYNCBIT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 12180 #define SIM_SOPT8_FTM2SYNCBIT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12181 #define SIM_SOPT8_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)
AnnaBridge 171:3a7713b1edbc 12182 #define SIM_SOPT8_FTM3SYNCBIT_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 12183 #define SIM_SOPT8_FTM3SYNCBIT_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 12184 #define SIM_SOPT8_FTM3SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3SYNCBIT_SHIFT)) & SIM_SOPT8_FTM3SYNCBIT_MASK)
AnnaBridge 171:3a7713b1edbc 12185 #define SIM_SOPT8_FTM0OCH0SRC_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 12186 #define SIM_SOPT8_FTM0OCH0SRC_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12187 #define SIM_SOPT8_FTM0OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12188 #define SIM_SOPT8_FTM0OCH1SRC_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 12189 #define SIM_SOPT8_FTM0OCH1SRC_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 12190 #define SIM_SOPT8_FTM0OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12191 #define SIM_SOPT8_FTM0OCH2SRC_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 12192 #define SIM_SOPT8_FTM0OCH2SRC_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 12193 #define SIM_SOPT8_FTM0OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12194 #define SIM_SOPT8_FTM0OCH3SRC_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 12195 #define SIM_SOPT8_FTM0OCH3SRC_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 12196 #define SIM_SOPT8_FTM0OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12197 #define SIM_SOPT8_FTM0OCH4SRC_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 12198 #define SIM_SOPT8_FTM0OCH4SRC_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 12199 #define SIM_SOPT8_FTM0OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12200 #define SIM_SOPT8_FTM0OCH5SRC_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 12201 #define SIM_SOPT8_FTM0OCH5SRC_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 12202 #define SIM_SOPT8_FTM0OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12203 #define SIM_SOPT8_FTM0OCH6SRC_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 12204 #define SIM_SOPT8_FTM0OCH6SRC_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 12205 #define SIM_SOPT8_FTM0OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12206 #define SIM_SOPT8_FTM0OCH7SRC_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 12207 #define SIM_SOPT8_FTM0OCH7SRC_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 12208 #define SIM_SOPT8_FTM0OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12209 #define SIM_SOPT8_FTM3OCH0SRC_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 12210 #define SIM_SOPT8_FTM3OCH0SRC_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12211 #define SIM_SOPT8_FTM3OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH0SRC_SHIFT)) & SIM_SOPT8_FTM3OCH0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12212 #define SIM_SOPT8_FTM3OCH1SRC_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 12213 #define SIM_SOPT8_FTM3OCH1SRC_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 12214 #define SIM_SOPT8_FTM3OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH1SRC_SHIFT)) & SIM_SOPT8_FTM3OCH1SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12215 #define SIM_SOPT8_FTM3OCH2SRC_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 12216 #define SIM_SOPT8_FTM3OCH2SRC_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 12217 #define SIM_SOPT8_FTM3OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH2SRC_SHIFT)) & SIM_SOPT8_FTM3OCH2SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12218 #define SIM_SOPT8_FTM3OCH3SRC_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 12219 #define SIM_SOPT8_FTM3OCH3SRC_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 12220 #define SIM_SOPT8_FTM3OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH3SRC_SHIFT)) & SIM_SOPT8_FTM3OCH3SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12221 #define SIM_SOPT8_FTM3OCH4SRC_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 12222 #define SIM_SOPT8_FTM3OCH4SRC_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 12223 #define SIM_SOPT8_FTM3OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH4SRC_SHIFT)) & SIM_SOPT8_FTM3OCH4SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12224 #define SIM_SOPT8_FTM3OCH5SRC_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 12225 #define SIM_SOPT8_FTM3OCH5SRC_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 12226 #define SIM_SOPT8_FTM3OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH5SRC_SHIFT)) & SIM_SOPT8_FTM3OCH5SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12227 #define SIM_SOPT8_FTM3OCH6SRC_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 12228 #define SIM_SOPT8_FTM3OCH6SRC_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 12229 #define SIM_SOPT8_FTM3OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH6SRC_SHIFT)) & SIM_SOPT8_FTM3OCH6SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12230 #define SIM_SOPT8_FTM3OCH7SRC_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 12231 #define SIM_SOPT8_FTM3OCH7SRC_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 12232 #define SIM_SOPT8_FTM3OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH7SRC_SHIFT)) & SIM_SOPT8_FTM3OCH7SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12233
AnnaBridge 171:3a7713b1edbc 12234 /*! @name SOPT9 - System Options Register 9 */
AnnaBridge 171:3a7713b1edbc 12235 #define SIM_SOPT9_TPM1CH0SRC_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 12236 #define SIM_SOPT9_TPM1CH0SRC_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 12237 #define SIM_SOPT9_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CH0SRC_SHIFT)) & SIM_SOPT9_TPM1CH0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12238 #define SIM_SOPT9_TPM2CH0SRC_MASK (0x300000U)
AnnaBridge 171:3a7713b1edbc 12239 #define SIM_SOPT9_TPM2CH0SRC_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 12240 #define SIM_SOPT9_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CH0SRC_SHIFT)) & SIM_SOPT9_TPM2CH0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 12241 #define SIM_SOPT9_TPM1CLKSEL_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 12242 #define SIM_SOPT9_TPM1CLKSEL_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 12243 #define SIM_SOPT9_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CLKSEL_SHIFT)) & SIM_SOPT9_TPM1CLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 12244 #define SIM_SOPT9_TPM2CLKSEL_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 12245 #define SIM_SOPT9_TPM2CLKSEL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 12246 #define SIM_SOPT9_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CLKSEL_SHIFT)) & SIM_SOPT9_TPM2CLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 12247
AnnaBridge 171:3a7713b1edbc 12248 /*! @name SDID - System Device Identification Register */
AnnaBridge 171:3a7713b1edbc 12249 #define SIM_SDID_PINID_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 12250 #define SIM_SDID_PINID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12251 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
AnnaBridge 171:3a7713b1edbc 12252 #define SIM_SDID_FAMID_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 12253 #define SIM_SDID_FAMID_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12254 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
AnnaBridge 171:3a7713b1edbc 12255 #define SIM_SDID_DIEID_MASK (0xF80U)
AnnaBridge 171:3a7713b1edbc 12256 #define SIM_SDID_DIEID_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12257 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
AnnaBridge 171:3a7713b1edbc 12258 #define SIM_SDID_REVID_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 12259 #define SIM_SDID_REVID_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 12260 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
AnnaBridge 171:3a7713b1edbc 12261 #define SIM_SDID_SERIESID_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 12262 #define SIM_SDID_SERIESID_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 12263 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
AnnaBridge 171:3a7713b1edbc 12264 #define SIM_SDID_SUBFAMID_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 12265 #define SIM_SDID_SUBFAMID_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12266 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
AnnaBridge 171:3a7713b1edbc 12267 #define SIM_SDID_FAMILYID_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 12268 #define SIM_SDID_FAMILYID_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 12269 #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
AnnaBridge 171:3a7713b1edbc 12270
AnnaBridge 171:3a7713b1edbc 12271 /*! @name SCGC1 - System Clock Gating Control Register 1 */
AnnaBridge 171:3a7713b1edbc 12272 #define SIM_SCGC1_I2C2_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 12273 #define SIM_SCGC1_I2C2_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 12274 #define SIM_SCGC1_I2C2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK)
AnnaBridge 171:3a7713b1edbc 12275 #define SIM_SCGC1_I2C3_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 12276 #define SIM_SCGC1_I2C3_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12277 #define SIM_SCGC1_I2C3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C3_SHIFT)) & SIM_SCGC1_I2C3_MASK)
AnnaBridge 171:3a7713b1edbc 12278 #define SIM_SCGC1_UART4_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 12279 #define SIM_SCGC1_UART4_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 12280 #define SIM_SCGC1_UART4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)
AnnaBridge 171:3a7713b1edbc 12281
AnnaBridge 171:3a7713b1edbc 12282 /*! @name SCGC2 - System Clock Gating Control Register 2 */
AnnaBridge 171:3a7713b1edbc 12283 #define SIM_SCGC2_ENET_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12284 #define SIM_SCGC2_ENET_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12285 #define SIM_SCGC2_ENET(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK)
AnnaBridge 171:3a7713b1edbc 12286 #define SIM_SCGC2_LPUART0_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 12287 #define SIM_SCGC2_LPUART0_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12288 #define SIM_SCGC2_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART0_SHIFT)) & SIM_SCGC2_LPUART0_MASK)
AnnaBridge 171:3a7713b1edbc 12289 #define SIM_SCGC2_TPM1_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 12290 #define SIM_SCGC2_TPM1_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 12291 #define SIM_SCGC2_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM1_SHIFT)) & SIM_SCGC2_TPM1_MASK)
AnnaBridge 171:3a7713b1edbc 12292 #define SIM_SCGC2_TPM2_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 12293 #define SIM_SCGC2_TPM2_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 12294 #define SIM_SCGC2_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM2_SHIFT)) & SIM_SCGC2_TPM2_MASK)
AnnaBridge 171:3a7713b1edbc 12295 #define SIM_SCGC2_DAC0_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 12296 #define SIM_SCGC2_DAC0_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 12297 #define SIM_SCGC2_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)
AnnaBridge 171:3a7713b1edbc 12298 #define SIM_SCGC2_DAC1_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 12299 #define SIM_SCGC2_DAC1_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 12300 #define SIM_SCGC2_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)
AnnaBridge 171:3a7713b1edbc 12301
AnnaBridge 171:3a7713b1edbc 12302 /*! @name SCGC3 - System Clock Gating Control Register 3 */
AnnaBridge 171:3a7713b1edbc 12303 #define SIM_SCGC3_RNGA_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12304 #define SIM_SCGC3_RNGA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12305 #define SIM_SCGC3_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK)
AnnaBridge 171:3a7713b1edbc 12306 #define SIM_SCGC3_USBHS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12307 #define SIM_SCGC3_USBHS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12308 #define SIM_SCGC3_USBHS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHS_SHIFT)) & SIM_SCGC3_USBHS_MASK)
AnnaBridge 171:3a7713b1edbc 12309 #define SIM_SCGC3_USBHSPHY_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 12310 #define SIM_SCGC3_USBHSPHY_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12311 #define SIM_SCGC3_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSPHY_SHIFT)) & SIM_SCGC3_USBHSPHY_MASK)
AnnaBridge 171:3a7713b1edbc 12312 #define SIM_SCGC3_USBHSDCD_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 12313 #define SIM_SCGC3_USBHSDCD_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 12314 #define SIM_SCGC3_USBHSDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSDCD_SHIFT)) & SIM_SCGC3_USBHSDCD_MASK)
AnnaBridge 171:3a7713b1edbc 12315 #define SIM_SCGC3_FLEXCAN1_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 12316 #define SIM_SCGC3_FLEXCAN1_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12317 #define SIM_SCGC3_FLEXCAN1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FLEXCAN1_SHIFT)) & SIM_SCGC3_FLEXCAN1_MASK)
AnnaBridge 171:3a7713b1edbc 12318 #define SIM_SCGC3_SPI2_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 12319 #define SIM_SCGC3_SPI2_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 12320 #define SIM_SCGC3_SPI2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
AnnaBridge 171:3a7713b1edbc 12321 #define SIM_SCGC3_SDHC_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 12322 #define SIM_SCGC3_SDHC_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 12323 #define SIM_SCGC3_SDHC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)
AnnaBridge 171:3a7713b1edbc 12324 #define SIM_SCGC3_FTM2_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 12325 #define SIM_SCGC3_FTM2_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12326 #define SIM_SCGC3_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)
AnnaBridge 171:3a7713b1edbc 12327 #define SIM_SCGC3_FTM3_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 12328 #define SIM_SCGC3_FTM3_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 12329 #define SIM_SCGC3_FTM3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK)
AnnaBridge 171:3a7713b1edbc 12330 #define SIM_SCGC3_ADC1_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 12331 #define SIM_SCGC3_ADC1_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 12332 #define SIM_SCGC3_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)
AnnaBridge 171:3a7713b1edbc 12333
AnnaBridge 171:3a7713b1edbc 12334 /*! @name SCGC4 - System Clock Gating Control Register 4 */
AnnaBridge 171:3a7713b1edbc 12335 #define SIM_SCGC4_EWM_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12336 #define SIM_SCGC4_EWM_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12337 #define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
AnnaBridge 171:3a7713b1edbc 12338 #define SIM_SCGC4_CMT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 12339 #define SIM_SCGC4_CMT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12340 #define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
AnnaBridge 171:3a7713b1edbc 12341 #define SIM_SCGC4_I2C0_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 12342 #define SIM_SCGC4_I2C0_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 12343 #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
AnnaBridge 171:3a7713b1edbc 12344 #define SIM_SCGC4_I2C1_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 12345 #define SIM_SCGC4_I2C1_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12346 #define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
AnnaBridge 171:3a7713b1edbc 12347 #define SIM_SCGC4_UART0_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 12348 #define SIM_SCGC4_UART0_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 12349 #define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
AnnaBridge 171:3a7713b1edbc 12350 #define SIM_SCGC4_UART1_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 12351 #define SIM_SCGC4_UART1_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 12352 #define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
AnnaBridge 171:3a7713b1edbc 12353 #define SIM_SCGC4_UART2_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 12354 #define SIM_SCGC4_UART2_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 12355 #define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
AnnaBridge 171:3a7713b1edbc 12356 #define SIM_SCGC4_UART3_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 12357 #define SIM_SCGC4_UART3_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 12358 #define SIM_SCGC4_UART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)
AnnaBridge 171:3a7713b1edbc 12359 #define SIM_SCGC4_USBOTG_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 12360 #define SIM_SCGC4_USBOTG_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 12361 #define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
AnnaBridge 171:3a7713b1edbc 12362 #define SIM_SCGC4_CMP_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 12363 #define SIM_SCGC4_CMP_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 12364 #define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
AnnaBridge 171:3a7713b1edbc 12365 #define SIM_SCGC4_VREF_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 12366 #define SIM_SCGC4_VREF_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 12367 #define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
AnnaBridge 171:3a7713b1edbc 12368
AnnaBridge 171:3a7713b1edbc 12369 /*! @name SCGC5 - System Clock Gating Control Register 5 */
AnnaBridge 171:3a7713b1edbc 12370 #define SIM_SCGC5_LPTMR_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12371 #define SIM_SCGC5_LPTMR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12372 #define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
AnnaBridge 171:3a7713b1edbc 12373 #define SIM_SCGC5_TSI_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 12374 #define SIM_SCGC5_TSI_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 12375 #define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
AnnaBridge 171:3a7713b1edbc 12376 #define SIM_SCGC5_PORTA_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 12377 #define SIM_SCGC5_PORTA_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 12378 #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
AnnaBridge 171:3a7713b1edbc 12379 #define SIM_SCGC5_PORTB_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 12380 #define SIM_SCGC5_PORTB_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 12381 #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
AnnaBridge 171:3a7713b1edbc 12382 #define SIM_SCGC5_PORTC_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 12383 #define SIM_SCGC5_PORTC_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 12384 #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
AnnaBridge 171:3a7713b1edbc 12385 #define SIM_SCGC5_PORTD_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 12386 #define SIM_SCGC5_PORTD_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 12387 #define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
AnnaBridge 171:3a7713b1edbc 12388 #define SIM_SCGC5_PORTE_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 12389 #define SIM_SCGC5_PORTE_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 12390 #define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
AnnaBridge 171:3a7713b1edbc 12391
AnnaBridge 171:3a7713b1edbc 12392 /*! @name SCGC6 - System Clock Gating Control Register 6 */
AnnaBridge 171:3a7713b1edbc 12393 #define SIM_SCGC6_FTF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12394 #define SIM_SCGC6_FTF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12395 #define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
AnnaBridge 171:3a7713b1edbc 12396 #define SIM_SCGC6_DMAMUX_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12397 #define SIM_SCGC6_DMAMUX_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12398 #define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
AnnaBridge 171:3a7713b1edbc 12399 #define SIM_SCGC6_FLEXCAN0_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 12400 #define SIM_SCGC6_FLEXCAN0_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12401 #define SIM_SCGC6_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)
AnnaBridge 171:3a7713b1edbc 12402 #define SIM_SCGC6_RNGA_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 12403 #define SIM_SCGC6_RNGA_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 12404 #define SIM_SCGC6_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK)
AnnaBridge 171:3a7713b1edbc 12405 #define SIM_SCGC6_SPI0_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 12406 #define SIM_SCGC6_SPI0_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 12407 #define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
AnnaBridge 171:3a7713b1edbc 12408 #define SIM_SCGC6_SPI1_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 12409 #define SIM_SCGC6_SPI1_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 12410 #define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
AnnaBridge 171:3a7713b1edbc 12411 #define SIM_SCGC6_I2S_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 12412 #define SIM_SCGC6_I2S_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 12413 #define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
AnnaBridge 171:3a7713b1edbc 12414 #define SIM_SCGC6_CRC_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 12415 #define SIM_SCGC6_CRC_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 12416 #define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
AnnaBridge 171:3a7713b1edbc 12417 #define SIM_SCGC6_USBDCD_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 12418 #define SIM_SCGC6_USBDCD_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 12419 #define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
AnnaBridge 171:3a7713b1edbc 12420 #define SIM_SCGC6_PDB_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 12421 #define SIM_SCGC6_PDB_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 12422 #define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
AnnaBridge 171:3a7713b1edbc 12423 #define SIM_SCGC6_PIT_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 12424 #define SIM_SCGC6_PIT_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 12425 #define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
AnnaBridge 171:3a7713b1edbc 12426 #define SIM_SCGC6_FTM0_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 12427 #define SIM_SCGC6_FTM0_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12428 #define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
AnnaBridge 171:3a7713b1edbc 12429 #define SIM_SCGC6_FTM1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 12430 #define SIM_SCGC6_FTM1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 12431 #define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
AnnaBridge 171:3a7713b1edbc 12432 #define SIM_SCGC6_FTM2_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 12433 #define SIM_SCGC6_FTM2_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 12434 #define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
AnnaBridge 171:3a7713b1edbc 12435 #define SIM_SCGC6_ADC0_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 12436 #define SIM_SCGC6_ADC0_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 12437 #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
AnnaBridge 171:3a7713b1edbc 12438 #define SIM_SCGC6_RTC_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 12439 #define SIM_SCGC6_RTC_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 12440 #define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
AnnaBridge 171:3a7713b1edbc 12441 #define SIM_SCGC6_DAC0_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 12442 #define SIM_SCGC6_DAC0_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 12443 #define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
AnnaBridge 171:3a7713b1edbc 12444
AnnaBridge 171:3a7713b1edbc 12445 /*! @name SCGC7 - System Clock Gating Control Register 7 */
AnnaBridge 171:3a7713b1edbc 12446 #define SIM_SCGC7_FLEXBUS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12447 #define SIM_SCGC7_FLEXBUS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12448 #define SIM_SCGC7_FLEXBUS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
AnnaBridge 171:3a7713b1edbc 12449 #define SIM_SCGC7_DMA_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12450 #define SIM_SCGC7_DMA_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12451 #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
AnnaBridge 171:3a7713b1edbc 12452 #define SIM_SCGC7_MPU_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 12453 #define SIM_SCGC7_MPU_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12454 #define SIM_SCGC7_MPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)
AnnaBridge 171:3a7713b1edbc 12455 #define SIM_SCGC7_SDRAMC_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 12456 #define SIM_SCGC7_SDRAMC_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 12457 #define SIM_SCGC7_SDRAMC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_SDRAMC_SHIFT)) & SIM_SCGC7_SDRAMC_MASK)
AnnaBridge 171:3a7713b1edbc 12458
AnnaBridge 171:3a7713b1edbc 12459 /*! @name CLKDIV1 - System Clock Divider Register 1 */
AnnaBridge 171:3a7713b1edbc 12460 #define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 12461 #define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12462 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
AnnaBridge 171:3a7713b1edbc 12463 #define SIM_CLKDIV1_OUTDIV3_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 12464 #define SIM_CLKDIV1_OUTDIV3_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 12465 #define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
AnnaBridge 171:3a7713b1edbc 12466 #define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 12467 #define SIM_CLKDIV1_OUTDIV2_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12468 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
AnnaBridge 171:3a7713b1edbc 12469 #define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 12470 #define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 12471 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
AnnaBridge 171:3a7713b1edbc 12472
AnnaBridge 171:3a7713b1edbc 12473 /*! @name CLKDIV2 - System Clock Divider Register 2 */
AnnaBridge 171:3a7713b1edbc 12474 #define SIM_CLKDIV2_USBFRAC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12475 #define SIM_CLKDIV2_USBFRAC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12476 #define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
AnnaBridge 171:3a7713b1edbc 12477 #define SIM_CLKDIV2_USBDIV_MASK (0xEU)
AnnaBridge 171:3a7713b1edbc 12478 #define SIM_CLKDIV2_USBDIV_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12479 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
AnnaBridge 171:3a7713b1edbc 12480
AnnaBridge 171:3a7713b1edbc 12481 /*! @name FCFG1 - Flash Configuration Register 1 */
AnnaBridge 171:3a7713b1edbc 12482 #define SIM_FCFG1_FLASHDIS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12483 #define SIM_FCFG1_FLASHDIS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12484 #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
AnnaBridge 171:3a7713b1edbc 12485 #define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12486 #define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12487 #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
AnnaBridge 171:3a7713b1edbc 12488 #define SIM_FCFG1_DEPART_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 12489 #define SIM_FCFG1_DEPART_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12490 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
AnnaBridge 171:3a7713b1edbc 12491 #define SIM_FCFG1_EESIZE_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 12492 #define SIM_FCFG1_EESIZE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12493 #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
AnnaBridge 171:3a7713b1edbc 12494 #define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 12495 #define SIM_FCFG1_PFSIZE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12496 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 12497 #define SIM_FCFG1_NVMSIZE_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 12498 #define SIM_FCFG1_NVMSIZE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 12499 #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 12500
AnnaBridge 171:3a7713b1edbc 12501 /*! @name FCFG2 - Flash Configuration Register 2 */
AnnaBridge 171:3a7713b1edbc 12502 #define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
AnnaBridge 171:3a7713b1edbc 12503 #define SIM_FCFG2_MAXADDR1_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12504 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
AnnaBridge 171:3a7713b1edbc 12505 #define SIM_FCFG2_PFLSH_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 12506 #define SIM_FCFG2_PFLSH_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 12507 #define SIM_FCFG2_PFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)
AnnaBridge 171:3a7713b1edbc 12508 #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
AnnaBridge 171:3a7713b1edbc 12509 #define SIM_FCFG2_MAXADDR0_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12510 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
AnnaBridge 171:3a7713b1edbc 12511 #define SIM_FCFG2_SWAPPFLSH_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 12512 #define SIM_FCFG2_SWAPPFLSH_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 12513 #define SIM_FCFG2_SWAPPFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAPPFLSH_SHIFT)) & SIM_FCFG2_SWAPPFLSH_MASK)
AnnaBridge 171:3a7713b1edbc 12514
AnnaBridge 171:3a7713b1edbc 12515 /*! @name UIDH - Unique Identification Register High */
AnnaBridge 171:3a7713b1edbc 12516 #define SIM_UIDH_UID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12517 #define SIM_UIDH_UID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12518 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
AnnaBridge 171:3a7713b1edbc 12519
AnnaBridge 171:3a7713b1edbc 12520 /*! @name UIDMH - Unique Identification Register Mid-High */
AnnaBridge 171:3a7713b1edbc 12521 #define SIM_UIDMH_UID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12522 #define SIM_UIDMH_UID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12523 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
AnnaBridge 171:3a7713b1edbc 12524
AnnaBridge 171:3a7713b1edbc 12525 /*! @name UIDML - Unique Identification Register Mid Low */
AnnaBridge 171:3a7713b1edbc 12526 #define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12527 #define SIM_UIDML_UID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12528 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
AnnaBridge 171:3a7713b1edbc 12529
AnnaBridge 171:3a7713b1edbc 12530 /*! @name UIDL - Unique Identification Register Low */
AnnaBridge 171:3a7713b1edbc 12531 #define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12532 #define SIM_UIDL_UID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12533 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
AnnaBridge 171:3a7713b1edbc 12534
AnnaBridge 171:3a7713b1edbc 12535 /*! @name CLKDIV3 - System Clock Divider Register 3 */
AnnaBridge 171:3a7713b1edbc 12536 #define SIM_CLKDIV3_PLLFLLFRAC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12537 #define SIM_CLKDIV3_PLLFLLFRAC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12538 #define SIM_CLKDIV3_PLLFLLFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLFRAC_SHIFT)) & SIM_CLKDIV3_PLLFLLFRAC_MASK)
AnnaBridge 171:3a7713b1edbc 12539 #define SIM_CLKDIV3_PLLFLLDIV_MASK (0xEU)
AnnaBridge 171:3a7713b1edbc 12540 #define SIM_CLKDIV3_PLLFLLDIV_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12541 #define SIM_CLKDIV3_PLLFLLDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLDIV_SHIFT)) & SIM_CLKDIV3_PLLFLLDIV_MASK)
AnnaBridge 171:3a7713b1edbc 12542
AnnaBridge 171:3a7713b1edbc 12543 /*! @name CLKDIV4 - System Clock Divider Register 4 */
AnnaBridge 171:3a7713b1edbc 12544 #define SIM_CLKDIV4_TRACEFRAC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12545 #define SIM_CLKDIV4_TRACEFRAC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12546 #define SIM_CLKDIV4_TRACEFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEFRAC_SHIFT)) & SIM_CLKDIV4_TRACEFRAC_MASK)
AnnaBridge 171:3a7713b1edbc 12547 #define SIM_CLKDIV4_TRACEDIV_MASK (0xEU)
AnnaBridge 171:3a7713b1edbc 12548 #define SIM_CLKDIV4_TRACEDIV_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12549 #define SIM_CLKDIV4_TRACEDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEDIV_SHIFT)) & SIM_CLKDIV4_TRACEDIV_MASK)
AnnaBridge 171:3a7713b1edbc 12550
AnnaBridge 171:3a7713b1edbc 12551
AnnaBridge 171:3a7713b1edbc 12552 /*!
AnnaBridge 171:3a7713b1edbc 12553 * @}
AnnaBridge 171:3a7713b1edbc 12554 */ /* end of group SIM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 12555
AnnaBridge 171:3a7713b1edbc 12556
AnnaBridge 171:3a7713b1edbc 12557 /* SIM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 12558 /** Peripheral SIM base address */
AnnaBridge 171:3a7713b1edbc 12559 #define SIM_BASE (0x40047000u)
AnnaBridge 171:3a7713b1edbc 12560 /** Peripheral SIM base pointer */
AnnaBridge 171:3a7713b1edbc 12561 #define SIM ((SIM_Type *)SIM_BASE)
AnnaBridge 171:3a7713b1edbc 12562 /** Array initializer of SIM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 12563 #define SIM_BASE_ADDRS { SIM_BASE }
AnnaBridge 171:3a7713b1edbc 12564 /** Array initializer of SIM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 12565 #define SIM_BASE_PTRS { SIM }
AnnaBridge 171:3a7713b1edbc 12566
AnnaBridge 171:3a7713b1edbc 12567 /*!
AnnaBridge 171:3a7713b1edbc 12568 * @}
AnnaBridge 171:3a7713b1edbc 12569 */ /* end of group SIM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 12570
AnnaBridge 171:3a7713b1edbc 12571
AnnaBridge 171:3a7713b1edbc 12572 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12573 -- SMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 12574 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 12575
AnnaBridge 171:3a7713b1edbc 12576 /*!
AnnaBridge 171:3a7713b1edbc 12577 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 12578 * @{
AnnaBridge 171:3a7713b1edbc 12579 */
AnnaBridge 171:3a7713b1edbc 12580
AnnaBridge 171:3a7713b1edbc 12581 /** SMC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 12582 typedef struct {
AnnaBridge 171:3a7713b1edbc 12583 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 12584 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 12585 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 12586 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 12587 } SMC_Type;
AnnaBridge 171:3a7713b1edbc 12588
AnnaBridge 171:3a7713b1edbc 12589 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12590 -- SMC Register Masks
AnnaBridge 171:3a7713b1edbc 12591 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 12592
AnnaBridge 171:3a7713b1edbc 12593 /*!
AnnaBridge 171:3a7713b1edbc 12594 * @addtogroup SMC_Register_Masks SMC Register Masks
AnnaBridge 171:3a7713b1edbc 12595 * @{
AnnaBridge 171:3a7713b1edbc 12596 */
AnnaBridge 171:3a7713b1edbc 12597
AnnaBridge 171:3a7713b1edbc 12598 /*! @name PMPROT - Power Mode Protection register */
AnnaBridge 171:3a7713b1edbc 12599 #define SMC_PMPROT_AVLLS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12600 #define SMC_PMPROT_AVLLS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12601 #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
AnnaBridge 171:3a7713b1edbc 12602 #define SMC_PMPROT_ALLS_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 12603 #define SMC_PMPROT_ALLS_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 12604 #define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
AnnaBridge 171:3a7713b1edbc 12605 #define SMC_PMPROT_AVLP_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 12606 #define SMC_PMPROT_AVLP_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 12607 #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
AnnaBridge 171:3a7713b1edbc 12608 #define SMC_PMPROT_AHSRUN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 12609 #define SMC_PMPROT_AHSRUN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12610 #define SMC_PMPROT_AHSRUN(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK)
AnnaBridge 171:3a7713b1edbc 12611
AnnaBridge 171:3a7713b1edbc 12612 /*! @name PMCTRL - Power Mode Control register */
AnnaBridge 171:3a7713b1edbc 12613 #define SMC_PMCTRL_STOPM_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 12614 #define SMC_PMCTRL_STOPM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12615 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
AnnaBridge 171:3a7713b1edbc 12616 #define SMC_PMCTRL_STOPA_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 12617 #define SMC_PMCTRL_STOPA_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 12618 #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
AnnaBridge 171:3a7713b1edbc 12619 #define SMC_PMCTRL_RUNM_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 12620 #define SMC_PMCTRL_RUNM_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 12621 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
AnnaBridge 171:3a7713b1edbc 12622
AnnaBridge 171:3a7713b1edbc 12623 /*! @name STOPCTRL - Stop Control Register */
AnnaBridge 171:3a7713b1edbc 12624 #define SMC_STOPCTRL_LLSM_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 12625 #define SMC_STOPCTRL_LLSM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12626 #define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK)
AnnaBridge 171:3a7713b1edbc 12627 #define SMC_STOPCTRL_RAM2PO_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 12628 #define SMC_STOPCTRL_RAM2PO_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12629 #define SMC_STOPCTRL_RAM2PO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_RAM2PO_SHIFT)) & SMC_STOPCTRL_RAM2PO_MASK)
AnnaBridge 171:3a7713b1edbc 12630 #define SMC_STOPCTRL_PORPO_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 12631 #define SMC_STOPCTRL_PORPO_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 12632 #define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
AnnaBridge 171:3a7713b1edbc 12633 #define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 12634 #define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 12635 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
AnnaBridge 171:3a7713b1edbc 12636
AnnaBridge 171:3a7713b1edbc 12637 /*! @name PMSTAT - Power Mode Status register */
AnnaBridge 171:3a7713b1edbc 12638 #define SMC_PMSTAT_PMSTAT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 12639 #define SMC_PMSTAT_PMSTAT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12640 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
AnnaBridge 171:3a7713b1edbc 12641
AnnaBridge 171:3a7713b1edbc 12642
AnnaBridge 171:3a7713b1edbc 12643 /*!
AnnaBridge 171:3a7713b1edbc 12644 * @}
AnnaBridge 171:3a7713b1edbc 12645 */ /* end of group SMC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 12646
AnnaBridge 171:3a7713b1edbc 12647
AnnaBridge 171:3a7713b1edbc 12648 /* SMC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 12649 /** Peripheral SMC base address */
AnnaBridge 171:3a7713b1edbc 12650 #define SMC_BASE (0x4007E000u)
AnnaBridge 171:3a7713b1edbc 12651 /** Peripheral SMC base pointer */
AnnaBridge 171:3a7713b1edbc 12652 #define SMC ((SMC_Type *)SMC_BASE)
AnnaBridge 171:3a7713b1edbc 12653 /** Array initializer of SMC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 12654 #define SMC_BASE_ADDRS { SMC_BASE }
AnnaBridge 171:3a7713b1edbc 12655 /** Array initializer of SMC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 12656 #define SMC_BASE_PTRS { SMC }
AnnaBridge 171:3a7713b1edbc 12657
AnnaBridge 171:3a7713b1edbc 12658 /*!
AnnaBridge 171:3a7713b1edbc 12659 * @}
AnnaBridge 171:3a7713b1edbc 12660 */ /* end of group SMC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 12661
AnnaBridge 171:3a7713b1edbc 12662
AnnaBridge 171:3a7713b1edbc 12663 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12664 -- SPI Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 12665 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 12666
AnnaBridge 171:3a7713b1edbc 12667 /*!
AnnaBridge 171:3a7713b1edbc 12668 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 12669 * @{
AnnaBridge 171:3a7713b1edbc 12670 */
AnnaBridge 171:3a7713b1edbc 12671
AnnaBridge 171:3a7713b1edbc 12672 /** SPI - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 12673 typedef struct {
AnnaBridge 171:3a7713b1edbc 12674 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 12675 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 12676 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 12677 union { /* offset: 0xC */
AnnaBridge 171:3a7713b1edbc 12678 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 12679 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 12680 };
AnnaBridge 171:3a7713b1edbc 12681 uint8_t RESERVED_1[24];
AnnaBridge 171:3a7713b1edbc 12682 __IO uint32_t SR; /**< Status Register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 12683 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 12684 union { /* offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 12685 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 12686 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 12687 };
AnnaBridge 171:3a7713b1edbc 12688 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 12689 __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 12690 __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 12691 __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 12692 __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 12693 uint8_t RESERVED_2[48];
AnnaBridge 171:3a7713b1edbc 12694 __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
AnnaBridge 171:3a7713b1edbc 12695 __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 12696 __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 12697 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 12698 } SPI_Type;
AnnaBridge 171:3a7713b1edbc 12699
AnnaBridge 171:3a7713b1edbc 12700 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12701 -- SPI Register Masks
AnnaBridge 171:3a7713b1edbc 12702 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 12703
AnnaBridge 171:3a7713b1edbc 12704 /*!
AnnaBridge 171:3a7713b1edbc 12705 * @addtogroup SPI_Register_Masks SPI Register Masks
AnnaBridge 171:3a7713b1edbc 12706 * @{
AnnaBridge 171:3a7713b1edbc 12707 */
AnnaBridge 171:3a7713b1edbc 12708
AnnaBridge 171:3a7713b1edbc 12709 /*! @name MCR - Module Configuration Register */
AnnaBridge 171:3a7713b1edbc 12710 #define SPI_MCR_HALT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12711 #define SPI_MCR_HALT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12712 #define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
AnnaBridge 171:3a7713b1edbc 12713 #define SPI_MCR_SMPL_PT_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 12714 #define SPI_MCR_SMPL_PT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12715 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
AnnaBridge 171:3a7713b1edbc 12716 #define SPI_MCR_CLR_RXF_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 12717 #define SPI_MCR_CLR_RXF_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 12718 #define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
AnnaBridge 171:3a7713b1edbc 12719 #define SPI_MCR_CLR_TXF_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 12720 #define SPI_MCR_CLR_TXF_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 12721 #define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
AnnaBridge 171:3a7713b1edbc 12722 #define SPI_MCR_DIS_RXF_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 12723 #define SPI_MCR_DIS_RXF_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 12724 #define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
AnnaBridge 171:3a7713b1edbc 12725 #define SPI_MCR_DIS_TXF_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 12726 #define SPI_MCR_DIS_TXF_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 12727 #define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
AnnaBridge 171:3a7713b1edbc 12728 #define SPI_MCR_MDIS_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 12729 #define SPI_MCR_MDIS_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 12730 #define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
AnnaBridge 171:3a7713b1edbc 12731 #define SPI_MCR_DOZE_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 12732 #define SPI_MCR_DOZE_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 12733 #define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
AnnaBridge 171:3a7713b1edbc 12734 #define SPI_MCR_PCSIS_MASK (0x3F0000U)
AnnaBridge 171:3a7713b1edbc 12735 #define SPI_MCR_PCSIS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12736 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
AnnaBridge 171:3a7713b1edbc 12737 #define SPI_MCR_ROOE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 12738 #define SPI_MCR_ROOE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12739 #define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
AnnaBridge 171:3a7713b1edbc 12740 #define SPI_MCR_PCSSE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 12741 #define SPI_MCR_PCSSE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 12742 #define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
AnnaBridge 171:3a7713b1edbc 12743 #define SPI_MCR_MTFE_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 12744 #define SPI_MCR_MTFE_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 12745 #define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
AnnaBridge 171:3a7713b1edbc 12746 #define SPI_MCR_FRZ_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 12747 #define SPI_MCR_FRZ_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 12748 #define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
AnnaBridge 171:3a7713b1edbc 12749 #define SPI_MCR_DCONF_MASK (0x30000000U)
AnnaBridge 171:3a7713b1edbc 12750 #define SPI_MCR_DCONF_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 12751 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
AnnaBridge 171:3a7713b1edbc 12752 #define SPI_MCR_CONT_SCKE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 12753 #define SPI_MCR_CONT_SCKE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 12754 #define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
AnnaBridge 171:3a7713b1edbc 12755 #define SPI_MCR_MSTR_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 12756 #define SPI_MCR_MSTR_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 12757 #define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
AnnaBridge 171:3a7713b1edbc 12758
AnnaBridge 171:3a7713b1edbc 12759 /*! @name TCR - Transfer Count Register */
AnnaBridge 171:3a7713b1edbc 12760 #define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 12761 #define SPI_TCR_SPI_TCNT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12762 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
AnnaBridge 171:3a7713b1edbc 12763
AnnaBridge 171:3a7713b1edbc 12764 /*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */
AnnaBridge 171:3a7713b1edbc 12765 #define SPI_CTAR_BR_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 12766 #define SPI_CTAR_BR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12767 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
AnnaBridge 171:3a7713b1edbc 12768 #define SPI_CTAR_DT_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 12769 #define SPI_CTAR_DT_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12770 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
AnnaBridge 171:3a7713b1edbc 12771 #define SPI_CTAR_ASC_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 12772 #define SPI_CTAR_ASC_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12773 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
AnnaBridge 171:3a7713b1edbc 12774 #define SPI_CTAR_CSSCK_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 12775 #define SPI_CTAR_CSSCK_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 12776 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
AnnaBridge 171:3a7713b1edbc 12777 #define SPI_CTAR_PBR_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 12778 #define SPI_CTAR_PBR_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12779 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
AnnaBridge 171:3a7713b1edbc 12780 #define SPI_CTAR_PDT_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 12781 #define SPI_CTAR_PDT_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 12782 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
AnnaBridge 171:3a7713b1edbc 12783 #define SPI_CTAR_PASC_MASK (0x300000U)
AnnaBridge 171:3a7713b1edbc 12784 #define SPI_CTAR_PASC_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 12785 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
AnnaBridge 171:3a7713b1edbc 12786 #define SPI_CTAR_PCSSCK_MASK (0xC00000U)
AnnaBridge 171:3a7713b1edbc 12787 #define SPI_CTAR_PCSSCK_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 12788 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
AnnaBridge 171:3a7713b1edbc 12789 #define SPI_CTAR_LSBFE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 12790 #define SPI_CTAR_LSBFE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12791 #define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
AnnaBridge 171:3a7713b1edbc 12792 #define SPI_CTAR_CPHA_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 12793 #define SPI_CTAR_CPHA_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 12794 #define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
AnnaBridge 171:3a7713b1edbc 12795 #define SPI_CTAR_CPOL_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 12796 #define SPI_CTAR_CPOL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 12797 #define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
AnnaBridge 171:3a7713b1edbc 12798 #define SPI_CTAR_FMSZ_MASK (0x78000000U)
AnnaBridge 171:3a7713b1edbc 12799 #define SPI_CTAR_FMSZ_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 12800 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
AnnaBridge 171:3a7713b1edbc 12801 #define SPI_CTAR_DBR_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 12802 #define SPI_CTAR_DBR_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 12803 #define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
AnnaBridge 171:3a7713b1edbc 12804
AnnaBridge 171:3a7713b1edbc 12805 /* The count of SPI_CTAR */
AnnaBridge 171:3a7713b1edbc 12806 #define SPI_CTAR_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 12807
AnnaBridge 171:3a7713b1edbc 12808 /*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
AnnaBridge 171:3a7713b1edbc 12809 #define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 12810 #define SPI_CTAR_SLAVE_CPHA_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 12811 #define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
AnnaBridge 171:3a7713b1edbc 12812 #define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 12813 #define SPI_CTAR_SLAVE_CPOL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 12814 #define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
AnnaBridge 171:3a7713b1edbc 12815 #define SPI_CTAR_SLAVE_FMSZ_MASK (0x78000000U)
AnnaBridge 171:3a7713b1edbc 12816 #define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 12817 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
AnnaBridge 171:3a7713b1edbc 12818
AnnaBridge 171:3a7713b1edbc 12819 /* The count of SPI_CTAR_SLAVE */
AnnaBridge 171:3a7713b1edbc 12820 #define SPI_CTAR_SLAVE_COUNT (1U)
AnnaBridge 171:3a7713b1edbc 12821
AnnaBridge 171:3a7713b1edbc 12822 /*! @name SR - Status Register */
AnnaBridge 171:3a7713b1edbc 12823 #define SPI_SR_POPNXTPTR_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 12824 #define SPI_SR_POPNXTPTR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12825 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
AnnaBridge 171:3a7713b1edbc 12826 #define SPI_SR_RXCTR_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 12827 #define SPI_SR_RXCTR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12828 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
AnnaBridge 171:3a7713b1edbc 12829 #define SPI_SR_TXNXTPTR_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 12830 #define SPI_SR_TXNXTPTR_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12831 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
AnnaBridge 171:3a7713b1edbc 12832 #define SPI_SR_TXCTR_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 12833 #define SPI_SR_TXCTR_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 12834 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
AnnaBridge 171:3a7713b1edbc 12835 #define SPI_SR_RFDF_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 12836 #define SPI_SR_RFDF_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 12837 #define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
AnnaBridge 171:3a7713b1edbc 12838 #define SPI_SR_RFOF_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 12839 #define SPI_SR_RFOF_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 12840 #define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
AnnaBridge 171:3a7713b1edbc 12841 #define SPI_SR_TFFF_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 12842 #define SPI_SR_TFFF_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 12843 #define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
AnnaBridge 171:3a7713b1edbc 12844 #define SPI_SR_TFUF_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 12845 #define SPI_SR_TFUF_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 12846 #define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
AnnaBridge 171:3a7713b1edbc 12847 #define SPI_SR_EOQF_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 12848 #define SPI_SR_EOQF_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 12849 #define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
AnnaBridge 171:3a7713b1edbc 12850 #define SPI_SR_TXRXS_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 12851 #define SPI_SR_TXRXS_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 12852 #define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
AnnaBridge 171:3a7713b1edbc 12853 #define SPI_SR_TCF_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 12854 #define SPI_SR_TCF_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 12855 #define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
AnnaBridge 171:3a7713b1edbc 12856
AnnaBridge 171:3a7713b1edbc 12857 /*! @name RSER - DMA/Interrupt Request Select and Enable Register */
AnnaBridge 171:3a7713b1edbc 12858 #define SPI_RSER_RFDF_DIRS_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 12859 #define SPI_RSER_RFDF_DIRS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12860 #define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
AnnaBridge 171:3a7713b1edbc 12861 #define SPI_RSER_RFDF_RE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 12862 #define SPI_RSER_RFDF_RE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 12863 #define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 12864 #define SPI_RSER_RFOF_RE_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 12865 #define SPI_RSER_RFOF_RE_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 12866 #define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 12867 #define SPI_RSER_TFFF_DIRS_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 12868 #define SPI_RSER_TFFF_DIRS_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12869 #define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
AnnaBridge 171:3a7713b1edbc 12870 #define SPI_RSER_TFFF_RE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 12871 #define SPI_RSER_TFFF_RE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 12872 #define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 12873 #define SPI_RSER_TFUF_RE_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 12874 #define SPI_RSER_TFUF_RE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 12875 #define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 12876 #define SPI_RSER_EOQF_RE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 12877 #define SPI_RSER_EOQF_RE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 12878 #define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 12879 #define SPI_RSER_TCF_RE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 12880 #define SPI_RSER_TCF_RE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 12881 #define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 12882
AnnaBridge 171:3a7713b1edbc 12883 /*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
AnnaBridge 171:3a7713b1edbc 12884 #define SPI_PUSHR_TXDATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 12885 #define SPI_PUSHR_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12886 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 12887 #define SPI_PUSHR_PCS_MASK (0x3F0000U)
AnnaBridge 171:3a7713b1edbc 12888 #define SPI_PUSHR_PCS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12889 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
AnnaBridge 171:3a7713b1edbc 12890 #define SPI_PUSHR_CTCNT_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 12891 #define SPI_PUSHR_CTCNT_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 12892 #define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
AnnaBridge 171:3a7713b1edbc 12893 #define SPI_PUSHR_EOQ_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 12894 #define SPI_PUSHR_EOQ_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 12895 #define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
AnnaBridge 171:3a7713b1edbc 12896 #define SPI_PUSHR_CTAS_MASK (0x70000000U)
AnnaBridge 171:3a7713b1edbc 12897 #define SPI_PUSHR_CTAS_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 12898 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
AnnaBridge 171:3a7713b1edbc 12899 #define SPI_PUSHR_CONT_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 12900 #define SPI_PUSHR_CONT_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 12901 #define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
AnnaBridge 171:3a7713b1edbc 12902
AnnaBridge 171:3a7713b1edbc 12903 /*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */
AnnaBridge 171:3a7713b1edbc 12904 #define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12905 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12906 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 12907
AnnaBridge 171:3a7713b1edbc 12908 /*! @name POPR - POP RX FIFO Register */
AnnaBridge 171:3a7713b1edbc 12909 #define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12910 #define SPI_POPR_RXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12911 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 12912
AnnaBridge 171:3a7713b1edbc 12913 /*! @name TXFR0 - Transmit FIFO Registers */
AnnaBridge 171:3a7713b1edbc 12914 #define SPI_TXFR0_TXDATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 12915 #define SPI_TXFR0_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12916 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 12917 #define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 12918 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12919 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 12920
AnnaBridge 171:3a7713b1edbc 12921 /*! @name TXFR1 - Transmit FIFO Registers */
AnnaBridge 171:3a7713b1edbc 12922 #define SPI_TXFR1_TXDATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 12923 #define SPI_TXFR1_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12924 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 12925 #define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 12926 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12927 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 12928
AnnaBridge 171:3a7713b1edbc 12929 /*! @name TXFR2 - Transmit FIFO Registers */
AnnaBridge 171:3a7713b1edbc 12930 #define SPI_TXFR2_TXDATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 12931 #define SPI_TXFR2_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12932 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 12933 #define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 12934 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12935 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 12936
AnnaBridge 171:3a7713b1edbc 12937 /*! @name TXFR3 - Transmit FIFO Registers */
AnnaBridge 171:3a7713b1edbc 12938 #define SPI_TXFR3_TXDATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 12939 #define SPI_TXFR3_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12940 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 12941 #define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 12942 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12943 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 12944
AnnaBridge 171:3a7713b1edbc 12945 /*! @name RXFR0 - Receive FIFO Registers */
AnnaBridge 171:3a7713b1edbc 12946 #define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12947 #define SPI_RXFR0_RXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12948 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 12949
AnnaBridge 171:3a7713b1edbc 12950 /*! @name RXFR1 - Receive FIFO Registers */
AnnaBridge 171:3a7713b1edbc 12951 #define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12952 #define SPI_RXFR1_RXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12953 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 12954
AnnaBridge 171:3a7713b1edbc 12955 /*! @name RXFR2 - Receive FIFO Registers */
AnnaBridge 171:3a7713b1edbc 12956 #define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12957 #define SPI_RXFR2_RXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12958 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 12959
AnnaBridge 171:3a7713b1edbc 12960 /*! @name RXFR3 - Receive FIFO Registers */
AnnaBridge 171:3a7713b1edbc 12961 #define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12962 #define SPI_RXFR3_RXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12963 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 12964
AnnaBridge 171:3a7713b1edbc 12965
AnnaBridge 171:3a7713b1edbc 12966 /*!
AnnaBridge 171:3a7713b1edbc 12967 * @}
AnnaBridge 171:3a7713b1edbc 12968 */ /* end of group SPI_Register_Masks */
AnnaBridge 171:3a7713b1edbc 12969
AnnaBridge 171:3a7713b1edbc 12970
AnnaBridge 171:3a7713b1edbc 12971 /* SPI - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 12972 /** Peripheral SPI0 base address */
AnnaBridge 171:3a7713b1edbc 12973 #define SPI0_BASE (0x4002C000u)
AnnaBridge 171:3a7713b1edbc 12974 /** Peripheral SPI0 base pointer */
AnnaBridge 171:3a7713b1edbc 12975 #define SPI0 ((SPI_Type *)SPI0_BASE)
AnnaBridge 171:3a7713b1edbc 12976 /** Peripheral SPI1 base address */
AnnaBridge 171:3a7713b1edbc 12977 #define SPI1_BASE (0x4002D000u)
AnnaBridge 171:3a7713b1edbc 12978 /** Peripheral SPI1 base pointer */
AnnaBridge 171:3a7713b1edbc 12979 #define SPI1 ((SPI_Type *)SPI1_BASE)
AnnaBridge 171:3a7713b1edbc 12980 /** Peripheral SPI2 base address */
AnnaBridge 171:3a7713b1edbc 12981 #define SPI2_BASE (0x400AC000u)
AnnaBridge 171:3a7713b1edbc 12982 /** Peripheral SPI2 base pointer */
AnnaBridge 171:3a7713b1edbc 12983 #define SPI2 ((SPI_Type *)SPI2_BASE)
AnnaBridge 171:3a7713b1edbc 12984 /** Array initializer of SPI peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 12985 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE }
AnnaBridge 171:3a7713b1edbc 12986 /** Array initializer of SPI peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 12987 #define SPI_BASE_PTRS { SPI0, SPI1, SPI2 }
AnnaBridge 171:3a7713b1edbc 12988 /** Interrupt vectors for the SPI peripheral type */
AnnaBridge 171:3a7713b1edbc 12989 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
AnnaBridge 171:3a7713b1edbc 12990
AnnaBridge 171:3a7713b1edbc 12991 /*!
AnnaBridge 171:3a7713b1edbc 12992 * @}
AnnaBridge 171:3a7713b1edbc 12993 */ /* end of group SPI_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 12994
AnnaBridge 171:3a7713b1edbc 12995
AnnaBridge 171:3a7713b1edbc 12996 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12997 -- SYSMPU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 12998 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 12999
AnnaBridge 171:3a7713b1edbc 13000 /*!
AnnaBridge 171:3a7713b1edbc 13001 * @addtogroup SYSMPU_Peripheral_Access_Layer SYSMPU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 13002 * @{
AnnaBridge 171:3a7713b1edbc 13003 */
AnnaBridge 171:3a7713b1edbc 13004
AnnaBridge 171:3a7713b1edbc 13005 /** SYSMPU - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 13006 typedef struct {
AnnaBridge 171:3a7713b1edbc 13007 __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 13008 uint8_t RESERVED_0[12];
AnnaBridge 171:3a7713b1edbc 13009 struct { /* offset: 0x10, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 13010 __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 13011 __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 13012 } SP[5];
AnnaBridge 171:3a7713b1edbc 13013 uint8_t RESERVED_1[968];
AnnaBridge 171:3a7713b1edbc 13014 __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
AnnaBridge 171:3a7713b1edbc 13015 uint8_t RESERVED_2[832];
AnnaBridge 171:3a7713b1edbc 13016 __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 13017 } SYSMPU_Type;
AnnaBridge 171:3a7713b1edbc 13018
AnnaBridge 171:3a7713b1edbc 13019 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13020 -- SYSMPU Register Masks
AnnaBridge 171:3a7713b1edbc 13021 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 13022
AnnaBridge 171:3a7713b1edbc 13023 /*!
AnnaBridge 171:3a7713b1edbc 13024 * @addtogroup SYSMPU_Register_Masks SYSMPU Register Masks
AnnaBridge 171:3a7713b1edbc 13025 * @{
AnnaBridge 171:3a7713b1edbc 13026 */
AnnaBridge 171:3a7713b1edbc 13027
AnnaBridge 171:3a7713b1edbc 13028 /*! @name CESR - Control/Error Status Register */
AnnaBridge 171:3a7713b1edbc 13029 #define SYSMPU_CESR_VLD_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 13030 #define SYSMPU_CESR_VLD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13031 #define SYSMPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)
AnnaBridge 171:3a7713b1edbc 13032 #define SYSMPU_CESR_NRGD_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 13033 #define SYSMPU_CESR_NRGD_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 13034 #define SYSMPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)
AnnaBridge 171:3a7713b1edbc 13035 #define SYSMPU_CESR_NSP_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 13036 #define SYSMPU_CESR_NSP_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 13037 #define SYSMPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK)
AnnaBridge 171:3a7713b1edbc 13038 #define SYSMPU_CESR_HRL_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 13039 #define SYSMPU_CESR_HRL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 13040 #define SYSMPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK)
AnnaBridge 171:3a7713b1edbc 13041 #define SYSMPU_CESR_SPERR_MASK (0xF8000000U)
AnnaBridge 171:3a7713b1edbc 13042 #define SYSMPU_CESR_SPERR_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 13043 #define SYSMPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)
AnnaBridge 171:3a7713b1edbc 13044
AnnaBridge 171:3a7713b1edbc 13045 /*! @name EAR - Error Address Register, slave port n */
AnnaBridge 171:3a7713b1edbc 13046 #define SYSMPU_EAR_EADDR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 13047 #define SYSMPU_EAR_EADDR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13048 #define SYSMPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK)
AnnaBridge 171:3a7713b1edbc 13049
AnnaBridge 171:3a7713b1edbc 13050 /* The count of SYSMPU_EAR */
AnnaBridge 171:3a7713b1edbc 13051 #define SYSMPU_EAR_COUNT (5U)
AnnaBridge 171:3a7713b1edbc 13052
AnnaBridge 171:3a7713b1edbc 13053 /*! @name EDR - Error Detail Register, slave port n */
AnnaBridge 171:3a7713b1edbc 13054 #define SYSMPU_EDR_ERW_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 13055 #define SYSMPU_EDR_ERW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13056 #define SYSMPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)
AnnaBridge 171:3a7713b1edbc 13057 #define SYSMPU_EDR_EATTR_MASK (0xEU)
AnnaBridge 171:3a7713b1edbc 13058 #define SYSMPU_EDR_EATTR_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 13059 #define SYSMPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)
AnnaBridge 171:3a7713b1edbc 13060 #define SYSMPU_EDR_EMN_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 13061 #define SYSMPU_EDR_EMN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 13062 #define SYSMPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK)
AnnaBridge 171:3a7713b1edbc 13063 #define SYSMPU_EDR_EPID_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 13064 #define SYSMPU_EDR_EPID_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 13065 #define SYSMPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK)
AnnaBridge 171:3a7713b1edbc 13066 #define SYSMPU_EDR_EACD_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 13067 #define SYSMPU_EDR_EACD_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 13068 #define SYSMPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK)
AnnaBridge 171:3a7713b1edbc 13069
AnnaBridge 171:3a7713b1edbc 13070 /* The count of SYSMPU_EDR */
AnnaBridge 171:3a7713b1edbc 13071 #define SYSMPU_EDR_COUNT (5U)
AnnaBridge 171:3a7713b1edbc 13072
AnnaBridge 171:3a7713b1edbc 13073 /*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */
AnnaBridge 171:3a7713b1edbc 13074 #define SYSMPU_WORD_VLD_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 13075 #define SYSMPU_WORD_VLD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13076 #define SYSMPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)
AnnaBridge 171:3a7713b1edbc 13077 #define SYSMPU_WORD_M0UM_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 13078 #define SYSMPU_WORD_M0UM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13079 #define SYSMPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK)
AnnaBridge 171:3a7713b1edbc 13080 #define SYSMPU_WORD_M0SM_MASK (0x18U)
AnnaBridge 171:3a7713b1edbc 13081 #define SYSMPU_WORD_M0SM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 13082 #define SYSMPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK)
AnnaBridge 171:3a7713b1edbc 13083 #define SYSMPU_WORD_M0PE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 13084 #define SYSMPU_WORD_M0PE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 13085 #define SYSMPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK)
AnnaBridge 171:3a7713b1edbc 13086 #define SYSMPU_WORD_ENDADDR_MASK (0xFFFFFFE0U)
AnnaBridge 171:3a7713b1edbc 13087 #define SYSMPU_WORD_ENDADDR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 13088 #define SYSMPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK)
AnnaBridge 171:3a7713b1edbc 13089 #define SYSMPU_WORD_SRTADDR_MASK (0xFFFFFFE0U)
AnnaBridge 171:3a7713b1edbc 13090 #define SYSMPU_WORD_SRTADDR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 13091 #define SYSMPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK)
AnnaBridge 171:3a7713b1edbc 13092 #define SYSMPU_WORD_M1UM_MASK (0x1C0U)
AnnaBridge 171:3a7713b1edbc 13093 #define SYSMPU_WORD_M1UM_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 13094 #define SYSMPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK)
AnnaBridge 171:3a7713b1edbc 13095 #define SYSMPU_WORD_M1SM_MASK (0x600U)
AnnaBridge 171:3a7713b1edbc 13096 #define SYSMPU_WORD_M1SM_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 13097 #define SYSMPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK)
AnnaBridge 171:3a7713b1edbc 13098 #define SYSMPU_WORD_M1PE_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 13099 #define SYSMPU_WORD_M1PE_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 13100 #define SYSMPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK)
AnnaBridge 171:3a7713b1edbc 13101 #define SYSMPU_WORD_M2UM_MASK (0x7000U)
AnnaBridge 171:3a7713b1edbc 13102 #define SYSMPU_WORD_M2UM_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 13103 #define SYSMPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK)
AnnaBridge 171:3a7713b1edbc 13104 #define SYSMPU_WORD_M2SM_MASK (0x18000U)
AnnaBridge 171:3a7713b1edbc 13105 #define SYSMPU_WORD_M2SM_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 13106 #define SYSMPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK)
AnnaBridge 171:3a7713b1edbc 13107 #define SYSMPU_WORD_PIDMASK_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 13108 #define SYSMPU_WORD_PIDMASK_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 13109 #define SYSMPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK)
AnnaBridge 171:3a7713b1edbc 13110 #define SYSMPU_WORD_M2PE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 13111 #define SYSMPU_WORD_M2PE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 13112 #define SYSMPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK)
AnnaBridge 171:3a7713b1edbc 13113 #define SYSMPU_WORD_M3UM_MASK (0x1C0000U)
AnnaBridge 171:3a7713b1edbc 13114 #define SYSMPU_WORD_M3UM_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 13115 #define SYSMPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)
AnnaBridge 171:3a7713b1edbc 13116 #define SYSMPU_WORD_M3SM_MASK (0x600000U)
AnnaBridge 171:3a7713b1edbc 13117 #define SYSMPU_WORD_M3SM_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 13118 #define SYSMPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)
AnnaBridge 171:3a7713b1edbc 13119 #define SYSMPU_WORD_M3PE_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 13120 #define SYSMPU_WORD_M3PE_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 13121 #define SYSMPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)
AnnaBridge 171:3a7713b1edbc 13122 #define SYSMPU_WORD_PID_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 13123 #define SYSMPU_WORD_PID_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 13124 #define SYSMPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK)
AnnaBridge 171:3a7713b1edbc 13125 #define SYSMPU_WORD_M4WE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 13126 #define SYSMPU_WORD_M4WE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 13127 #define SYSMPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)
AnnaBridge 171:3a7713b1edbc 13128 #define SYSMPU_WORD_M4RE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 13129 #define SYSMPU_WORD_M4RE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 13130 #define SYSMPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)
AnnaBridge 171:3a7713b1edbc 13131 #define SYSMPU_WORD_M5WE_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 13132 #define SYSMPU_WORD_M5WE_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 13133 #define SYSMPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)
AnnaBridge 171:3a7713b1edbc 13134 #define SYSMPU_WORD_M5RE_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 13135 #define SYSMPU_WORD_M5RE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 13136 #define SYSMPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)
AnnaBridge 171:3a7713b1edbc 13137 #define SYSMPU_WORD_M6WE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 13138 #define SYSMPU_WORD_M6WE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 13139 #define SYSMPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)
AnnaBridge 171:3a7713b1edbc 13140 #define SYSMPU_WORD_M6RE_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 13141 #define SYSMPU_WORD_M6RE_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 13142 #define SYSMPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)
AnnaBridge 171:3a7713b1edbc 13143 #define SYSMPU_WORD_M7WE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 13144 #define SYSMPU_WORD_M7WE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 13145 #define SYSMPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)
AnnaBridge 171:3a7713b1edbc 13146 #define SYSMPU_WORD_M7RE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 13147 #define SYSMPU_WORD_M7RE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 13148 #define SYSMPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)
AnnaBridge 171:3a7713b1edbc 13149
AnnaBridge 171:3a7713b1edbc 13150 /* The count of SYSMPU_WORD */
AnnaBridge 171:3a7713b1edbc 13151 #define SYSMPU_WORD_COUNT (12U)
AnnaBridge 171:3a7713b1edbc 13152
AnnaBridge 171:3a7713b1edbc 13153 /* The count of SYSMPU_WORD */
AnnaBridge 171:3a7713b1edbc 13154 #define SYSMPU_WORD_COUNT2 (4U)
AnnaBridge 171:3a7713b1edbc 13155
AnnaBridge 171:3a7713b1edbc 13156 /*! @name RGDAAC - Region Descriptor Alternate Access Control n */
AnnaBridge 171:3a7713b1edbc 13157 #define SYSMPU_RGDAAC_M0UM_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 13158 #define SYSMPU_RGDAAC_M0UM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13159 #define SYSMPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK)
AnnaBridge 171:3a7713b1edbc 13160 #define SYSMPU_RGDAAC_M0SM_MASK (0x18U)
AnnaBridge 171:3a7713b1edbc 13161 #define SYSMPU_RGDAAC_M0SM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 13162 #define SYSMPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK)
AnnaBridge 171:3a7713b1edbc 13163 #define SYSMPU_RGDAAC_M0PE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 13164 #define SYSMPU_RGDAAC_M0PE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 13165 #define SYSMPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK)
AnnaBridge 171:3a7713b1edbc 13166 #define SYSMPU_RGDAAC_M1UM_MASK (0x1C0U)
AnnaBridge 171:3a7713b1edbc 13167 #define SYSMPU_RGDAAC_M1UM_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 13168 #define SYSMPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK)
AnnaBridge 171:3a7713b1edbc 13169 #define SYSMPU_RGDAAC_M1SM_MASK (0x600U)
AnnaBridge 171:3a7713b1edbc 13170 #define SYSMPU_RGDAAC_M1SM_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 13171 #define SYSMPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK)
AnnaBridge 171:3a7713b1edbc 13172 #define SYSMPU_RGDAAC_M1PE_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 13173 #define SYSMPU_RGDAAC_M1PE_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 13174 #define SYSMPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK)
AnnaBridge 171:3a7713b1edbc 13175 #define SYSMPU_RGDAAC_M2UM_MASK (0x7000U)
AnnaBridge 171:3a7713b1edbc 13176 #define SYSMPU_RGDAAC_M2UM_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 13177 #define SYSMPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK)
AnnaBridge 171:3a7713b1edbc 13178 #define SYSMPU_RGDAAC_M2SM_MASK (0x18000U)
AnnaBridge 171:3a7713b1edbc 13179 #define SYSMPU_RGDAAC_M2SM_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 13180 #define SYSMPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK)
AnnaBridge 171:3a7713b1edbc 13181 #define SYSMPU_RGDAAC_M2PE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 13182 #define SYSMPU_RGDAAC_M2PE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 13183 #define SYSMPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK)
AnnaBridge 171:3a7713b1edbc 13184 #define SYSMPU_RGDAAC_M3UM_MASK (0x1C0000U)
AnnaBridge 171:3a7713b1edbc 13185 #define SYSMPU_RGDAAC_M3UM_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 13186 #define SYSMPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)
AnnaBridge 171:3a7713b1edbc 13187 #define SYSMPU_RGDAAC_M3SM_MASK (0x600000U)
AnnaBridge 171:3a7713b1edbc 13188 #define SYSMPU_RGDAAC_M3SM_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 13189 #define SYSMPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)
AnnaBridge 171:3a7713b1edbc 13190 #define SYSMPU_RGDAAC_M3PE_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 13191 #define SYSMPU_RGDAAC_M3PE_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 13192 #define SYSMPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)
AnnaBridge 171:3a7713b1edbc 13193 #define SYSMPU_RGDAAC_M4WE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 13194 #define SYSMPU_RGDAAC_M4WE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 13195 #define SYSMPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)
AnnaBridge 171:3a7713b1edbc 13196 #define SYSMPU_RGDAAC_M4RE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 13197 #define SYSMPU_RGDAAC_M4RE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 13198 #define SYSMPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)
AnnaBridge 171:3a7713b1edbc 13199 #define SYSMPU_RGDAAC_M5WE_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 13200 #define SYSMPU_RGDAAC_M5WE_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 13201 #define SYSMPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)
AnnaBridge 171:3a7713b1edbc 13202 #define SYSMPU_RGDAAC_M5RE_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 13203 #define SYSMPU_RGDAAC_M5RE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 13204 #define SYSMPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)
AnnaBridge 171:3a7713b1edbc 13205 #define SYSMPU_RGDAAC_M6WE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 13206 #define SYSMPU_RGDAAC_M6WE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 13207 #define SYSMPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)
AnnaBridge 171:3a7713b1edbc 13208 #define SYSMPU_RGDAAC_M6RE_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 13209 #define SYSMPU_RGDAAC_M6RE_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 13210 #define SYSMPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)
AnnaBridge 171:3a7713b1edbc 13211 #define SYSMPU_RGDAAC_M7WE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 13212 #define SYSMPU_RGDAAC_M7WE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 13213 #define SYSMPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)
AnnaBridge 171:3a7713b1edbc 13214 #define SYSMPU_RGDAAC_M7RE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 13215 #define SYSMPU_RGDAAC_M7RE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 13216 #define SYSMPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)
AnnaBridge 171:3a7713b1edbc 13217
AnnaBridge 171:3a7713b1edbc 13218 /* The count of SYSMPU_RGDAAC */
AnnaBridge 171:3a7713b1edbc 13219 #define SYSMPU_RGDAAC_COUNT (12U)
AnnaBridge 171:3a7713b1edbc 13220
AnnaBridge 171:3a7713b1edbc 13221
AnnaBridge 171:3a7713b1edbc 13222 /*!
AnnaBridge 171:3a7713b1edbc 13223 * @}
AnnaBridge 171:3a7713b1edbc 13224 */ /* end of group SYSMPU_Register_Masks */
AnnaBridge 171:3a7713b1edbc 13225
AnnaBridge 171:3a7713b1edbc 13226
AnnaBridge 171:3a7713b1edbc 13227 /* SYSMPU - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 13228 /** Peripheral SYSMPU base address */
AnnaBridge 171:3a7713b1edbc 13229 #define SYSMPU_BASE (0x4000D000u)
AnnaBridge 171:3a7713b1edbc 13230 /** Peripheral SYSMPU base pointer */
AnnaBridge 171:3a7713b1edbc 13231 #define SYSMPU ((SYSMPU_Type *)SYSMPU_BASE)
AnnaBridge 171:3a7713b1edbc 13232 /** Array initializer of SYSMPU peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 13233 #define SYSMPU_BASE_ADDRS { SYSMPU_BASE }
AnnaBridge 171:3a7713b1edbc 13234 /** Array initializer of SYSMPU peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 13235 #define SYSMPU_BASE_PTRS { SYSMPU }
AnnaBridge 171:3a7713b1edbc 13236
AnnaBridge 171:3a7713b1edbc 13237 /*!
AnnaBridge 171:3a7713b1edbc 13238 * @}
AnnaBridge 171:3a7713b1edbc 13239 */ /* end of group SYSMPU_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 13240
AnnaBridge 171:3a7713b1edbc 13241
AnnaBridge 171:3a7713b1edbc 13242 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13243 -- TPM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 13244 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 13245
AnnaBridge 171:3a7713b1edbc 13246 /*!
AnnaBridge 171:3a7713b1edbc 13247 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 13248 * @{
AnnaBridge 171:3a7713b1edbc 13249 */
AnnaBridge 171:3a7713b1edbc 13250
AnnaBridge 171:3a7713b1edbc 13251 /** TPM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 13252 typedef struct {
AnnaBridge 171:3a7713b1edbc 13253 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 13254 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 13255 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 13256 struct { /* offset: 0xC, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 13257 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 13258 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 13259 } CONTROLS[2];
AnnaBridge 171:3a7713b1edbc 13260 uint8_t RESERVED_0[52];
AnnaBridge 171:3a7713b1edbc 13261 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 13262 uint8_t RESERVED_1[16];
AnnaBridge 171:3a7713b1edbc 13263 __IO uint32_t COMBINE; /**< Combine Channel Register, offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 13264 uint8_t RESERVED_2[8];
AnnaBridge 171:3a7713b1edbc 13265 __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */
AnnaBridge 171:3a7713b1edbc 13266 uint8_t RESERVED_3[4];
AnnaBridge 171:3a7713b1edbc 13267 __IO uint32_t FILTER; /**< Filter Control, offset: 0x78 */
AnnaBridge 171:3a7713b1edbc 13268 uint8_t RESERVED_4[4];
AnnaBridge 171:3a7713b1edbc 13269 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 13270 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 13271 } TPM_Type;
AnnaBridge 171:3a7713b1edbc 13272
AnnaBridge 171:3a7713b1edbc 13273 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13274 -- TPM Register Masks
AnnaBridge 171:3a7713b1edbc 13275 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 13276
AnnaBridge 171:3a7713b1edbc 13277 /*!
AnnaBridge 171:3a7713b1edbc 13278 * @addtogroup TPM_Register_Masks TPM Register Masks
AnnaBridge 171:3a7713b1edbc 13279 * @{
AnnaBridge 171:3a7713b1edbc 13280 */
AnnaBridge 171:3a7713b1edbc 13281
AnnaBridge 171:3a7713b1edbc 13282 /*! @name SC - Status and Control */
AnnaBridge 171:3a7713b1edbc 13283 #define TPM_SC_PS_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 13284 #define TPM_SC_PS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13285 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
AnnaBridge 171:3a7713b1edbc 13286 #define TPM_SC_CMOD_MASK (0x18U)
AnnaBridge 171:3a7713b1edbc 13287 #define TPM_SC_CMOD_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 13288 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
AnnaBridge 171:3a7713b1edbc 13289 #define TPM_SC_CPWMS_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 13290 #define TPM_SC_CPWMS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 13291 #define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
AnnaBridge 171:3a7713b1edbc 13292 #define TPM_SC_TOIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 13293 #define TPM_SC_TOIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 13294 #define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
AnnaBridge 171:3a7713b1edbc 13295 #define TPM_SC_TOF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 13296 #define TPM_SC_TOF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 13297 #define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
AnnaBridge 171:3a7713b1edbc 13298 #define TPM_SC_DMA_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 13299 #define TPM_SC_DMA_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 13300 #define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
AnnaBridge 171:3a7713b1edbc 13301
AnnaBridge 171:3a7713b1edbc 13302 /*! @name CNT - Counter */
AnnaBridge 171:3a7713b1edbc 13303 #define TPM_CNT_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 13304 #define TPM_CNT_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13305 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 13306
AnnaBridge 171:3a7713b1edbc 13307 /*! @name MOD - Modulo */
AnnaBridge 171:3a7713b1edbc 13308 #define TPM_MOD_MOD_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 13309 #define TPM_MOD_MOD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13310 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
AnnaBridge 171:3a7713b1edbc 13311
AnnaBridge 171:3a7713b1edbc 13312 /*! @name CnSC - Channel (n) Status and Control */
AnnaBridge 171:3a7713b1edbc 13313 #define TPM_CnSC_DMA_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 13314 #define TPM_CnSC_DMA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13315 #define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
AnnaBridge 171:3a7713b1edbc 13316 #define TPM_CnSC_ELSA_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 13317 #define TPM_CnSC_ELSA_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 13318 #define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
AnnaBridge 171:3a7713b1edbc 13319 #define TPM_CnSC_ELSB_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 13320 #define TPM_CnSC_ELSB_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 13321 #define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
AnnaBridge 171:3a7713b1edbc 13322 #define TPM_CnSC_MSA_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 13323 #define TPM_CnSC_MSA_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 13324 #define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
AnnaBridge 171:3a7713b1edbc 13325 #define TPM_CnSC_MSB_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 13326 #define TPM_CnSC_MSB_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 13327 #define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
AnnaBridge 171:3a7713b1edbc 13328 #define TPM_CnSC_CHIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 13329 #define TPM_CnSC_CHIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 13330 #define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
AnnaBridge 171:3a7713b1edbc 13331 #define TPM_CnSC_CHF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 13332 #define TPM_CnSC_CHF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 13333 #define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
AnnaBridge 171:3a7713b1edbc 13334
AnnaBridge 171:3a7713b1edbc 13335 /* The count of TPM_CnSC */
AnnaBridge 171:3a7713b1edbc 13336 #define TPM_CnSC_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 13337
AnnaBridge 171:3a7713b1edbc 13338 /*! @name CnV - Channel (n) Value */
AnnaBridge 171:3a7713b1edbc 13339 #define TPM_CnV_VAL_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 13340 #define TPM_CnV_VAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13341 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
AnnaBridge 171:3a7713b1edbc 13342
AnnaBridge 171:3a7713b1edbc 13343 /* The count of TPM_CnV */
AnnaBridge 171:3a7713b1edbc 13344 #define TPM_CnV_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 13345
AnnaBridge 171:3a7713b1edbc 13346 /*! @name STATUS - Capture and Compare Status */
AnnaBridge 171:3a7713b1edbc 13347 #define TPM_STATUS_CH0F_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 13348 #define TPM_STATUS_CH0F_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13349 #define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
AnnaBridge 171:3a7713b1edbc 13350 #define TPM_STATUS_CH1F_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 13351 #define TPM_STATUS_CH1F_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 13352 #define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
AnnaBridge 171:3a7713b1edbc 13353 #define TPM_STATUS_TOF_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 13354 #define TPM_STATUS_TOF_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 13355 #define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
AnnaBridge 171:3a7713b1edbc 13356
AnnaBridge 171:3a7713b1edbc 13357 /*! @name COMBINE - Combine Channel Register */
AnnaBridge 171:3a7713b1edbc 13358 #define TPM_COMBINE_COMBINE0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 13359 #define TPM_COMBINE_COMBINE0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13360 #define TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)
AnnaBridge 171:3a7713b1edbc 13361 #define TPM_COMBINE_COMSWAP0_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 13362 #define TPM_COMBINE_COMSWAP0_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 13363 #define TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)
AnnaBridge 171:3a7713b1edbc 13364
AnnaBridge 171:3a7713b1edbc 13365 /*! @name POL - Channel Polarity */
AnnaBridge 171:3a7713b1edbc 13366 #define TPM_POL_POL0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 13367 #define TPM_POL_POL0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13368 #define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
AnnaBridge 171:3a7713b1edbc 13369 #define TPM_POL_POL1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 13370 #define TPM_POL_POL1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 13371 #define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
AnnaBridge 171:3a7713b1edbc 13372
AnnaBridge 171:3a7713b1edbc 13373 /*! @name FILTER - Filter Control */
AnnaBridge 171:3a7713b1edbc 13374 #define TPM_FILTER_CH0FVAL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 13375 #define TPM_FILTER_CH0FVAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13376 #define TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)
AnnaBridge 171:3a7713b1edbc 13377 #define TPM_FILTER_CH1FVAL_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 13378 #define TPM_FILTER_CH1FVAL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 13379 #define TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)
AnnaBridge 171:3a7713b1edbc 13380
AnnaBridge 171:3a7713b1edbc 13381 /*! @name QDCTRL - Quadrature Decoder Control and Status */
AnnaBridge 171:3a7713b1edbc 13382 #define TPM_QDCTRL_QUADEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 13383 #define TPM_QDCTRL_QUADEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13384 #define TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)
AnnaBridge 171:3a7713b1edbc 13385 #define TPM_QDCTRL_TOFDIR_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 13386 #define TPM_QDCTRL_TOFDIR_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 13387 #define TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)
AnnaBridge 171:3a7713b1edbc 13388 #define TPM_QDCTRL_QUADIR_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 13389 #define TPM_QDCTRL_QUADIR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 13390 #define TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)
AnnaBridge 171:3a7713b1edbc 13391 #define TPM_QDCTRL_QUADMODE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 13392 #define TPM_QDCTRL_QUADMODE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 13393 #define TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)
AnnaBridge 171:3a7713b1edbc 13394
AnnaBridge 171:3a7713b1edbc 13395 /*! @name CONF - Configuration */
AnnaBridge 171:3a7713b1edbc 13396 #define TPM_CONF_DOZEEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 13397 #define TPM_CONF_DOZEEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 13398 #define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
AnnaBridge 171:3a7713b1edbc 13399 #define TPM_CONF_DBGMODE_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 13400 #define TPM_CONF_DBGMODE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 13401 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
AnnaBridge 171:3a7713b1edbc 13402 #define TPM_CONF_GTBSYNC_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 13403 #define TPM_CONF_GTBSYNC_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 13404 #define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
AnnaBridge 171:3a7713b1edbc 13405 #define TPM_CONF_GTBEEN_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 13406 #define TPM_CONF_GTBEEN_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 13407 #define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
AnnaBridge 171:3a7713b1edbc 13408 #define TPM_CONF_CSOT_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 13409 #define TPM_CONF_CSOT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 13410 #define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
AnnaBridge 171:3a7713b1edbc 13411 #define TPM_CONF_CSOO_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 13412 #define TPM_CONF_CSOO_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 13413 #define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
AnnaBridge 171:3a7713b1edbc 13414 #define TPM_CONF_CROT_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 13415 #define TPM_CONF_CROT_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 13416 #define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
AnnaBridge 171:3a7713b1edbc 13417 #define TPM_CONF_CPOT_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 13418 #define TPM_CONF_CPOT_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 13419 #define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
AnnaBridge 171:3a7713b1edbc 13420 #define TPM_CONF_TRGPOL_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 13421 #define TPM_CONF_TRGPOL_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 13422 #define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
AnnaBridge 171:3a7713b1edbc 13423 #define TPM_CONF_TRGSRC_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 13424 #define TPM_CONF_TRGSRC_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 13425 #define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
AnnaBridge 171:3a7713b1edbc 13426 #define TPM_CONF_TRGSEL_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 13427 #define TPM_CONF_TRGSEL_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 13428 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 13429
AnnaBridge 171:3a7713b1edbc 13430
AnnaBridge 171:3a7713b1edbc 13431 /*!
AnnaBridge 171:3a7713b1edbc 13432 * @}
AnnaBridge 171:3a7713b1edbc 13433 */ /* end of group TPM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 13434
AnnaBridge 171:3a7713b1edbc 13435
AnnaBridge 171:3a7713b1edbc 13436 /* TPM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 13437 /** Peripheral TPM1 base address */
AnnaBridge 171:3a7713b1edbc 13438 #define TPM1_BASE (0x400C9000u)
AnnaBridge 171:3a7713b1edbc 13439 /** Peripheral TPM1 base pointer */
AnnaBridge 171:3a7713b1edbc 13440 #define TPM1 ((TPM_Type *)TPM1_BASE)
AnnaBridge 171:3a7713b1edbc 13441 /** Peripheral TPM2 base address */
AnnaBridge 171:3a7713b1edbc 13442 #define TPM2_BASE (0x400CA000u)
AnnaBridge 171:3a7713b1edbc 13443 /** Peripheral TPM2 base pointer */
AnnaBridge 171:3a7713b1edbc 13444 #define TPM2 ((TPM_Type *)TPM2_BASE)
AnnaBridge 171:3a7713b1edbc 13445 /** Array initializer of TPM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 13446 #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE }
AnnaBridge 171:3a7713b1edbc 13447 /** Array initializer of TPM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 13448 #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2 }
AnnaBridge 171:3a7713b1edbc 13449 /** Interrupt vectors for the TPM peripheral type */
AnnaBridge 171:3a7713b1edbc 13450 #define TPM_IRQS { NotAvail_IRQn, TPM1_IRQn, TPM2_IRQn }
AnnaBridge 171:3a7713b1edbc 13451
AnnaBridge 171:3a7713b1edbc 13452 /*!
AnnaBridge 171:3a7713b1edbc 13453 * @}
AnnaBridge 171:3a7713b1edbc 13454 */ /* end of group TPM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 13455
AnnaBridge 171:3a7713b1edbc 13456
AnnaBridge 171:3a7713b1edbc 13457 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13458 -- TSI Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 13459 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 13460
AnnaBridge 171:3a7713b1edbc 13461 /*!
AnnaBridge 171:3a7713b1edbc 13462 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 13463 * @{
AnnaBridge 171:3a7713b1edbc 13464 */
AnnaBridge 171:3a7713b1edbc 13465
AnnaBridge 171:3a7713b1edbc 13466 /** TSI - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 13467 typedef struct {
AnnaBridge 171:3a7713b1edbc 13468 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 13469 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 13470 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 13471 } TSI_Type;
AnnaBridge 171:3a7713b1edbc 13472
AnnaBridge 171:3a7713b1edbc 13473 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13474 -- TSI Register Masks
AnnaBridge 171:3a7713b1edbc 13475 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 13476
AnnaBridge 171:3a7713b1edbc 13477 /*!
AnnaBridge 171:3a7713b1edbc 13478 * @addtogroup TSI_Register_Masks TSI Register Masks
AnnaBridge 171:3a7713b1edbc 13479 * @{
AnnaBridge 171:3a7713b1edbc 13480 */
AnnaBridge 171:3a7713b1edbc 13481
AnnaBridge 171:3a7713b1edbc 13482 /*! @name GENCS - TSI General Control and Status Register */
AnnaBridge 171:3a7713b1edbc 13483 #define TSI_GENCS_EOSDMEO_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 13484 #define TSI_GENCS_EOSDMEO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13485 #define TSI_GENCS_EOSDMEO(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSDMEO_SHIFT)) & TSI_GENCS_EOSDMEO_MASK)
AnnaBridge 171:3a7713b1edbc 13486 #define TSI_GENCS_CURSW_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 13487 #define TSI_GENCS_CURSW_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 13488 #define TSI_GENCS_CURSW(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)
AnnaBridge 171:3a7713b1edbc 13489 #define TSI_GENCS_EOSF_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 13490 #define TSI_GENCS_EOSF_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 13491 #define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
AnnaBridge 171:3a7713b1edbc 13492 #define TSI_GENCS_SCNIP_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 13493 #define TSI_GENCS_SCNIP_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 13494 #define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
AnnaBridge 171:3a7713b1edbc 13495 #define TSI_GENCS_STM_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 13496 #define TSI_GENCS_STM_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 13497 #define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
AnnaBridge 171:3a7713b1edbc 13498 #define TSI_GENCS_STPE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 13499 #define TSI_GENCS_STPE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 13500 #define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
AnnaBridge 171:3a7713b1edbc 13501 #define TSI_GENCS_TSIIEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 13502 #define TSI_GENCS_TSIIEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 13503 #define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)
AnnaBridge 171:3a7713b1edbc 13504 #define TSI_GENCS_TSIEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 13505 #define TSI_GENCS_TSIEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 13506 #define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
AnnaBridge 171:3a7713b1edbc 13507 #define TSI_GENCS_NSCN_MASK (0x1F00U)
AnnaBridge 171:3a7713b1edbc 13508 #define TSI_GENCS_NSCN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 13509 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
AnnaBridge 171:3a7713b1edbc 13510 #define TSI_GENCS_PS_MASK (0xE000U)
AnnaBridge 171:3a7713b1edbc 13511 #define TSI_GENCS_PS_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 13512 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
AnnaBridge 171:3a7713b1edbc 13513 #define TSI_GENCS_EXTCHRG_MASK (0x70000U)
AnnaBridge 171:3a7713b1edbc 13514 #define TSI_GENCS_EXTCHRG_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 13515 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)
AnnaBridge 171:3a7713b1edbc 13516 #define TSI_GENCS_DVOLT_MASK (0x180000U)
AnnaBridge 171:3a7713b1edbc 13517 #define TSI_GENCS_DVOLT_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 13518 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
AnnaBridge 171:3a7713b1edbc 13519 #define TSI_GENCS_REFCHRG_MASK (0xE00000U)
AnnaBridge 171:3a7713b1edbc 13520 #define TSI_GENCS_REFCHRG_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 13521 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)
AnnaBridge 171:3a7713b1edbc 13522 #define TSI_GENCS_MODE_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 13523 #define TSI_GENCS_MODE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 13524 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 13525 #define TSI_GENCS_ESOR_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 13526 #define TSI_GENCS_ESOR_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 13527 #define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
AnnaBridge 171:3a7713b1edbc 13528 #define TSI_GENCS_OUTRGF_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 13529 #define TSI_GENCS_OUTRGF_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 13530 #define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
AnnaBridge 171:3a7713b1edbc 13531
AnnaBridge 171:3a7713b1edbc 13532 /*! @name DATA - TSI DATA Register */
AnnaBridge 171:3a7713b1edbc 13533 #define TSI_DATA_TSICNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 13534 #define TSI_DATA_TSICNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13535 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
AnnaBridge 171:3a7713b1edbc 13536 #define TSI_DATA_SWTS_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 13537 #define TSI_DATA_SWTS_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 13538 #define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)
AnnaBridge 171:3a7713b1edbc 13539 #define TSI_DATA_DMAEN_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 13540 #define TSI_DATA_DMAEN_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 13541 #define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 13542 #define TSI_DATA_TSICH_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 13543 #define TSI_DATA_TSICH_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 13544 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)
AnnaBridge 171:3a7713b1edbc 13545
AnnaBridge 171:3a7713b1edbc 13546 /*! @name TSHD - TSI Threshold Register */
AnnaBridge 171:3a7713b1edbc 13547 #define TSI_TSHD_THRESL_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 13548 #define TSI_TSHD_THRESL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13549 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
AnnaBridge 171:3a7713b1edbc 13550 #define TSI_TSHD_THRESH_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 13551 #define TSI_TSHD_THRESH_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 13552 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
AnnaBridge 171:3a7713b1edbc 13553
AnnaBridge 171:3a7713b1edbc 13554
AnnaBridge 171:3a7713b1edbc 13555 /*!
AnnaBridge 171:3a7713b1edbc 13556 * @}
AnnaBridge 171:3a7713b1edbc 13557 */ /* end of group TSI_Register_Masks */
AnnaBridge 171:3a7713b1edbc 13558
AnnaBridge 171:3a7713b1edbc 13559
AnnaBridge 171:3a7713b1edbc 13560 /* TSI - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 13561 /** Peripheral TSI0 base address */
AnnaBridge 171:3a7713b1edbc 13562 #define TSI0_BASE (0x40045000u)
AnnaBridge 171:3a7713b1edbc 13563 /** Peripheral TSI0 base pointer */
AnnaBridge 171:3a7713b1edbc 13564 #define TSI0 ((TSI_Type *)TSI0_BASE)
AnnaBridge 171:3a7713b1edbc 13565 /** Array initializer of TSI peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 13566 #define TSI_BASE_ADDRS { TSI0_BASE }
AnnaBridge 171:3a7713b1edbc 13567 /** Array initializer of TSI peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 13568 #define TSI_BASE_PTRS { TSI0 }
AnnaBridge 171:3a7713b1edbc 13569 /** Interrupt vectors for the TSI peripheral type */
AnnaBridge 171:3a7713b1edbc 13570 #define TSI_IRQS { TSI0_IRQn }
AnnaBridge 171:3a7713b1edbc 13571
AnnaBridge 171:3a7713b1edbc 13572 /*!
AnnaBridge 171:3a7713b1edbc 13573 * @}
AnnaBridge 171:3a7713b1edbc 13574 */ /* end of group TSI_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 13575
AnnaBridge 171:3a7713b1edbc 13576
AnnaBridge 171:3a7713b1edbc 13577 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13578 -- UART Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 13579 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 13580
AnnaBridge 171:3a7713b1edbc 13581 /*!
AnnaBridge 171:3a7713b1edbc 13582 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 13583 * @{
AnnaBridge 171:3a7713b1edbc 13584 */
AnnaBridge 171:3a7713b1edbc 13585
AnnaBridge 171:3a7713b1edbc 13586 /** UART - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 13587 typedef struct {
AnnaBridge 171:3a7713b1edbc 13588 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 13589 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 13590 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 13591 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 13592 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 13593 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 13594 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 13595 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 13596 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 13597 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 13598 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 13599 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 13600 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 13601 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 13602 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
AnnaBridge 171:3a7713b1edbc 13603 uint8_t RESERVED_0[1];
AnnaBridge 171:3a7713b1edbc 13604 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 13605 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
AnnaBridge 171:3a7713b1edbc 13606 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
AnnaBridge 171:3a7713b1edbc 13607 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
AnnaBridge 171:3a7713b1edbc 13608 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 13609 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
AnnaBridge 171:3a7713b1edbc 13610 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
AnnaBridge 171:3a7713b1edbc 13611 uint8_t RESERVED_1[1];
AnnaBridge 171:3a7713b1edbc 13612 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 13613 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
AnnaBridge 171:3a7713b1edbc 13614 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
AnnaBridge 171:3a7713b1edbc 13615 __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
AnnaBridge 171:3a7713b1edbc 13616 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 13617 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
AnnaBridge 171:3a7713b1edbc 13618 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
AnnaBridge 171:3a7713b1edbc 13619 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
AnnaBridge 171:3a7713b1edbc 13620 uint8_t RESERVED_2[26];
AnnaBridge 171:3a7713b1edbc 13621 __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
AnnaBridge 171:3a7713b1edbc 13622 __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
AnnaBridge 171:3a7713b1edbc 13623 union { /* offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 13624 struct { /* offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 13625 __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 13626 __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
AnnaBridge 171:3a7713b1edbc 13627 } TYPE0;
AnnaBridge 171:3a7713b1edbc 13628 struct { /* offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 13629 __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 13630 __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
AnnaBridge 171:3a7713b1edbc 13631 } TYPE1;
AnnaBridge 171:3a7713b1edbc 13632 };
AnnaBridge 171:3a7713b1edbc 13633 __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
AnnaBridge 171:3a7713b1edbc 13634 __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
AnnaBridge 171:3a7713b1edbc 13635 } UART_Type;
AnnaBridge 171:3a7713b1edbc 13636
AnnaBridge 171:3a7713b1edbc 13637 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 13638 -- UART Register Masks
AnnaBridge 171:3a7713b1edbc 13639 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 13640
AnnaBridge 171:3a7713b1edbc 13641 /*!
AnnaBridge 171:3a7713b1edbc 13642 * @addtogroup UART_Register_Masks UART Register Masks
AnnaBridge 171:3a7713b1edbc 13643 * @{
AnnaBridge 171:3a7713b1edbc 13644 */
AnnaBridge 171:3a7713b1edbc 13645
AnnaBridge 171:3a7713b1edbc 13646 /*! @name BDH - UART Baud Rate Registers: High */
AnnaBridge 171:3a7713b1edbc 13647 #define UART_BDH_SBR_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 13648 #define UART_BDH_SBR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13649 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
AnnaBridge 171:3a7713b1edbc 13650 #define UART_BDH_SBNS_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 13651 #define UART_BDH_SBNS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 13652 #define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK)
AnnaBridge 171:3a7713b1edbc 13653 #define UART_BDH_RXEDGIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 13654 #define UART_BDH_RXEDGIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 13655 #define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
AnnaBridge 171:3a7713b1edbc 13656 #define UART_BDH_LBKDIE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 13657 #define UART_BDH_LBKDIE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 13658 #define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
AnnaBridge 171:3a7713b1edbc 13659
AnnaBridge 171:3a7713b1edbc 13660 /*! @name BDL - UART Baud Rate Registers: Low */
AnnaBridge 171:3a7713b1edbc 13661 #define UART_BDL_SBR_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 13662 #define UART_BDL_SBR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13663 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
AnnaBridge 171:3a7713b1edbc 13664
AnnaBridge 171:3a7713b1edbc 13665 /*! @name C1 - UART Control Register 1 */
AnnaBridge 171:3a7713b1edbc 13666 #define UART_C1_PT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 13667 #define UART_C1_PT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13668 #define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
AnnaBridge 171:3a7713b1edbc 13669 #define UART_C1_PE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 13670 #define UART_C1_PE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 13671 #define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
AnnaBridge 171:3a7713b1edbc 13672 #define UART_C1_ILT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 13673 #define UART_C1_ILT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 13674 #define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
AnnaBridge 171:3a7713b1edbc 13675 #define UART_C1_WAKE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 13676 #define UART_C1_WAKE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 13677 #define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
AnnaBridge 171:3a7713b1edbc 13678 #define UART_C1_M_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 13679 #define UART_C1_M_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 13680 #define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
AnnaBridge 171:3a7713b1edbc 13681 #define UART_C1_RSRC_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 13682 #define UART_C1_RSRC_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 13683 #define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
AnnaBridge 171:3a7713b1edbc 13684 #define UART_C1_UARTSWAI_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 13685 #define UART_C1_UARTSWAI_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 13686 #define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
AnnaBridge 171:3a7713b1edbc 13687 #define UART_C1_LOOPS_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 13688 #define UART_C1_LOOPS_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 13689 #define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
AnnaBridge 171:3a7713b1edbc 13690
AnnaBridge 171:3a7713b1edbc 13691 /*! @name C2 - UART Control Register 2 */
AnnaBridge 171:3a7713b1edbc 13692 #define UART_C2_SBK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 13693 #define UART_C2_SBK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13694 #define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
AnnaBridge 171:3a7713b1edbc 13695 #define UART_C2_RWU_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 13696 #define UART_C2_RWU_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 13697 #define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
AnnaBridge 171:3a7713b1edbc 13698 #define UART_C2_RE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 13699 #define UART_C2_RE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 13700 #define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
AnnaBridge 171:3a7713b1edbc 13701 #define UART_C2_TE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 13702 #define UART_C2_TE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 13703 #define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
AnnaBridge 171:3a7713b1edbc 13704 #define UART_C2_ILIE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 13705 #define UART_C2_ILIE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 13706 #define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
AnnaBridge 171:3a7713b1edbc 13707 #define UART_C2_RIE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 13708 #define UART_C2_RIE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 13709 #define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
AnnaBridge 171:3a7713b1edbc 13710 #define UART_C2_TCIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 13711 #define UART_C2_TCIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 13712 #define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
AnnaBridge 171:3a7713b1edbc 13713 #define UART_C2_TIE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 13714 #define UART_C2_TIE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 13715 #define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
AnnaBridge 171:3a7713b1edbc 13716
AnnaBridge 171:3a7713b1edbc 13717 /*! @name S1 - UART Status Register 1 */
AnnaBridge 171:3a7713b1edbc 13718 #define UART_S1_PF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 13719 #define UART_S1_PF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13720 #define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
AnnaBridge 171:3a7713b1edbc 13721 #define UART_S1_FE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 13722 #define UART_S1_FE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 13723 #define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
AnnaBridge 171:3a7713b1edbc 13724 #define UART_S1_NF_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 13725 #define UART_S1_NF_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 13726 #define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
AnnaBridge 171:3a7713b1edbc 13727 #define UART_S1_OR_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 13728 #define UART_S1_OR_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 13729 #define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
AnnaBridge 171:3a7713b1edbc 13730 #define UART_S1_IDLE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 13731 #define UART_S1_IDLE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 13732 #define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
AnnaBridge 171:3a7713b1edbc 13733 #define UART_S1_RDRF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 13734 #define UART_S1_RDRF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 13735 #define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
AnnaBridge 171:3a7713b1edbc 13736 #define UART_S1_TC_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 13737 #define UART_S1_TC_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 13738 #define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
AnnaBridge 171:3a7713b1edbc 13739 #define UART_S1_TDRE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 13740 #define UART_S1_TDRE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 13741 #define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
AnnaBridge 171:3a7713b1edbc 13742
AnnaBridge 171:3a7713b1edbc 13743 /*! @name S2 - UART Status Register 2 */
AnnaBridge 171:3a7713b1edbc 13744 #define UART_S2_RAF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 13745 #define UART_S2_RAF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13746 #define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
AnnaBridge 171:3a7713b1edbc 13747 #define UART_S2_LBKDE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 13748 #define UART_S2_LBKDE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 13749 #define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
AnnaBridge 171:3a7713b1edbc 13750 #define UART_S2_BRK13_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 13751 #define UART_S2_BRK13_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 13752 #define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
AnnaBridge 171:3a7713b1edbc 13753 #define UART_S2_RWUID_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 13754 #define UART_S2_RWUID_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 13755 #define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
AnnaBridge 171:3a7713b1edbc 13756 #define UART_S2_RXINV_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 13757 #define UART_S2_RXINV_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 13758 #define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
AnnaBridge 171:3a7713b1edbc 13759 #define UART_S2_MSBF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 13760 #define UART_S2_MSBF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 13761 #define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
AnnaBridge 171:3a7713b1edbc 13762 #define UART_S2_RXEDGIF_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 13763 #define UART_S2_RXEDGIF_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 13764 #define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
AnnaBridge 171:3a7713b1edbc 13765 #define UART_S2_LBKDIF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 13766 #define UART_S2_LBKDIF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 13767 #define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
AnnaBridge 171:3a7713b1edbc 13768
AnnaBridge 171:3a7713b1edbc 13769 /*! @name C3 - UART Control Register 3 */
AnnaBridge 171:3a7713b1edbc 13770 #define UART_C3_PEIE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 13771 #define UART_C3_PEIE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13772 #define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
AnnaBridge 171:3a7713b1edbc 13773 #define UART_C3_FEIE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 13774 #define UART_C3_FEIE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 13775 #define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
AnnaBridge 171:3a7713b1edbc 13776 #define UART_C3_NEIE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 13777 #define UART_C3_NEIE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 13778 #define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
AnnaBridge 171:3a7713b1edbc 13779 #define UART_C3_ORIE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 13780 #define UART_C3_ORIE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 13781 #define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
AnnaBridge 171:3a7713b1edbc 13782 #define UART_C3_TXINV_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 13783 #define UART_C3_TXINV_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 13784 #define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
AnnaBridge 171:3a7713b1edbc 13785 #define UART_C3_TXDIR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 13786 #define UART_C3_TXDIR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 13787 #define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
AnnaBridge 171:3a7713b1edbc 13788 #define UART_C3_T8_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 13789 #define UART_C3_T8_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 13790 #define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
AnnaBridge 171:3a7713b1edbc 13791 #define UART_C3_R8_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 13792 #define UART_C3_R8_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 13793 #define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
AnnaBridge 171:3a7713b1edbc 13794
AnnaBridge 171:3a7713b1edbc 13795 /*! @name D - UART Data Register */
AnnaBridge 171:3a7713b1edbc 13796 #define UART_D_RT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 13797 #define UART_D_RT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13798 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
AnnaBridge 171:3a7713b1edbc 13799
AnnaBridge 171:3a7713b1edbc 13800 /*! @name MA1 - UART Match Address Registers 1 */
AnnaBridge 171:3a7713b1edbc 13801 #define UART_MA1_MA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 13802 #define UART_MA1_MA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13803 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
AnnaBridge 171:3a7713b1edbc 13804
AnnaBridge 171:3a7713b1edbc 13805 /*! @name MA2 - UART Match Address Registers 2 */
AnnaBridge 171:3a7713b1edbc 13806 #define UART_MA2_MA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 13807 #define UART_MA2_MA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13808 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
AnnaBridge 171:3a7713b1edbc 13809
AnnaBridge 171:3a7713b1edbc 13810 /*! @name C4 - UART Control Register 4 */
AnnaBridge 171:3a7713b1edbc 13811 #define UART_C4_BRFA_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 13812 #define UART_C4_BRFA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13813 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
AnnaBridge 171:3a7713b1edbc 13814 #define UART_C4_M10_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 13815 #define UART_C4_M10_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 13816 #define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
AnnaBridge 171:3a7713b1edbc 13817 #define UART_C4_MAEN2_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 13818 #define UART_C4_MAEN2_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 13819 #define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
AnnaBridge 171:3a7713b1edbc 13820 #define UART_C4_MAEN1_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 13821 #define UART_C4_MAEN1_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 13822 #define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
AnnaBridge 171:3a7713b1edbc 13823
AnnaBridge 171:3a7713b1edbc 13824 /*! @name C5 - UART Control Register 5 */
AnnaBridge 171:3a7713b1edbc 13825 #define UART_C5_RDMAS_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 13826 #define UART_C5_RDMAS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 13827 #define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
AnnaBridge 171:3a7713b1edbc 13828 #define UART_C5_TDMAS_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 13829 #define UART_C5_TDMAS_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 13830 #define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
AnnaBridge 171:3a7713b1edbc 13831
AnnaBridge 171:3a7713b1edbc 13832 /*! @name ED - UART Extended Data Register */
AnnaBridge 171:3a7713b1edbc 13833 #define UART_ED_PARITYE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 13834 #define UART_ED_PARITYE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 13835 #define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK)
AnnaBridge 171:3a7713b1edbc 13836 #define UART_ED_NOISY_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 13837 #define UART_ED_NOISY_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 13838 #define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK)
AnnaBridge 171:3a7713b1edbc 13839
AnnaBridge 171:3a7713b1edbc 13840 /*! @name MODEM - UART Modem Register */
AnnaBridge 171:3a7713b1edbc 13841 #define UART_MODEM_TXCTSE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 13842 #define UART_MODEM_TXCTSE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13843 #define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK)
AnnaBridge 171:3a7713b1edbc 13844 #define UART_MODEM_TXRTSE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 13845 #define UART_MODEM_TXRTSE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 13846 #define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK)
AnnaBridge 171:3a7713b1edbc 13847 #define UART_MODEM_TXRTSPOL_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 13848 #define UART_MODEM_TXRTSPOL_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 13849 #define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK)
AnnaBridge 171:3a7713b1edbc 13850 #define UART_MODEM_RXRTSE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 13851 #define UART_MODEM_RXRTSE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 13852 #define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK)
AnnaBridge 171:3a7713b1edbc 13853
AnnaBridge 171:3a7713b1edbc 13854 /*! @name IR - UART Infrared Register */
AnnaBridge 171:3a7713b1edbc 13855 #define UART_IR_TNP_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 13856 #define UART_IR_TNP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13857 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
AnnaBridge 171:3a7713b1edbc 13858 #define UART_IR_IREN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 13859 #define UART_IR_IREN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 13860 #define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK)
AnnaBridge 171:3a7713b1edbc 13861
AnnaBridge 171:3a7713b1edbc 13862 /*! @name PFIFO - UART FIFO Parameters */
AnnaBridge 171:3a7713b1edbc 13863 #define UART_PFIFO_RXFIFOSIZE_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 13864 #define UART_PFIFO_RXFIFOSIZE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13865 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 13866 #define UART_PFIFO_RXFE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 13867 #define UART_PFIFO_RXFE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 13868 #define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK)
AnnaBridge 171:3a7713b1edbc 13869 #define UART_PFIFO_TXFIFOSIZE_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 13870 #define UART_PFIFO_TXFIFOSIZE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 13871 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 13872 #define UART_PFIFO_TXFE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 13873 #define UART_PFIFO_TXFE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 13874 #define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK)
AnnaBridge 171:3a7713b1edbc 13875
AnnaBridge 171:3a7713b1edbc 13876 /*! @name CFIFO - UART FIFO Control Register */
AnnaBridge 171:3a7713b1edbc 13877 #define UART_CFIFO_RXUFE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 13878 #define UART_CFIFO_RXUFE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13879 #define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK)
AnnaBridge 171:3a7713b1edbc 13880 #define UART_CFIFO_TXOFE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 13881 #define UART_CFIFO_TXOFE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 13882 #define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK)
AnnaBridge 171:3a7713b1edbc 13883 #define UART_CFIFO_RXOFE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 13884 #define UART_CFIFO_RXOFE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 13885 #define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK)
AnnaBridge 171:3a7713b1edbc 13886 #define UART_CFIFO_RXFLUSH_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 13887 #define UART_CFIFO_RXFLUSH_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 13888 #define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK)
AnnaBridge 171:3a7713b1edbc 13889 #define UART_CFIFO_TXFLUSH_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 13890 #define UART_CFIFO_TXFLUSH_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 13891 #define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK)
AnnaBridge 171:3a7713b1edbc 13892
AnnaBridge 171:3a7713b1edbc 13893 /*! @name SFIFO - UART FIFO Status Register */
AnnaBridge 171:3a7713b1edbc 13894 #define UART_SFIFO_RXUF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 13895 #define UART_SFIFO_RXUF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13896 #define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK)
AnnaBridge 171:3a7713b1edbc 13897 #define UART_SFIFO_TXOF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 13898 #define UART_SFIFO_TXOF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 13899 #define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK)
AnnaBridge 171:3a7713b1edbc 13900 #define UART_SFIFO_RXOF_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 13901 #define UART_SFIFO_RXOF_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 13902 #define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK)
AnnaBridge 171:3a7713b1edbc 13903 #define UART_SFIFO_RXEMPT_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 13904 #define UART_SFIFO_RXEMPT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 13905 #define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK)
AnnaBridge 171:3a7713b1edbc 13906 #define UART_SFIFO_TXEMPT_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 13907 #define UART_SFIFO_TXEMPT_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 13908 #define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK)
AnnaBridge 171:3a7713b1edbc 13909
AnnaBridge 171:3a7713b1edbc 13910 /*! @name TWFIFO - UART FIFO Transmit Watermark */
AnnaBridge 171:3a7713b1edbc 13911 #define UART_TWFIFO_TXWATER_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 13912 #define UART_TWFIFO_TXWATER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13913 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
AnnaBridge 171:3a7713b1edbc 13914
AnnaBridge 171:3a7713b1edbc 13915 /*! @name TCFIFO - UART FIFO Transmit Count */
AnnaBridge 171:3a7713b1edbc 13916 #define UART_TCFIFO_TXCOUNT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 13917 #define UART_TCFIFO_TXCOUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13918 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
AnnaBridge 171:3a7713b1edbc 13919
AnnaBridge 171:3a7713b1edbc 13920 /*! @name RWFIFO - UART FIFO Receive Watermark */
AnnaBridge 171:3a7713b1edbc 13921 #define UART_RWFIFO_RXWATER_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 13922 #define UART_RWFIFO_RXWATER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13923 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
AnnaBridge 171:3a7713b1edbc 13924
AnnaBridge 171:3a7713b1edbc 13925 /*! @name RCFIFO - UART FIFO Receive Count */
AnnaBridge 171:3a7713b1edbc 13926 #define UART_RCFIFO_RXCOUNT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 13927 #define UART_RCFIFO_RXCOUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13928 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
AnnaBridge 171:3a7713b1edbc 13929
AnnaBridge 171:3a7713b1edbc 13930 /*! @name C7816 - UART 7816 Control Register */
AnnaBridge 171:3a7713b1edbc 13931 #define UART_C7816_ISO_7816E_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 13932 #define UART_C7816_ISO_7816E_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13933 #define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
AnnaBridge 171:3a7713b1edbc 13934 #define UART_C7816_TTYPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 13935 #define UART_C7816_TTYPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 13936 #define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
AnnaBridge 171:3a7713b1edbc 13937 #define UART_C7816_INIT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 13938 #define UART_C7816_INIT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 13939 #define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
AnnaBridge 171:3a7713b1edbc 13940 #define UART_C7816_ANACK_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 13941 #define UART_C7816_ANACK_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 13942 #define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
AnnaBridge 171:3a7713b1edbc 13943 #define UART_C7816_ONACK_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 13944 #define UART_C7816_ONACK_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 13945 #define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
AnnaBridge 171:3a7713b1edbc 13946
AnnaBridge 171:3a7713b1edbc 13947 /*! @name IE7816 - UART 7816 Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 13948 #define UART_IE7816_RXTE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 13949 #define UART_IE7816_RXTE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13950 #define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
AnnaBridge 171:3a7713b1edbc 13951 #define UART_IE7816_TXTE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 13952 #define UART_IE7816_TXTE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 13953 #define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
AnnaBridge 171:3a7713b1edbc 13954 #define UART_IE7816_GTVE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 13955 #define UART_IE7816_GTVE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 13956 #define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
AnnaBridge 171:3a7713b1edbc 13957 #define UART_IE7816_ADTE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 13958 #define UART_IE7816_ADTE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 13959 #define UART_IE7816_ADTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_ADTE_SHIFT)) & UART_IE7816_ADTE_MASK)
AnnaBridge 171:3a7713b1edbc 13960 #define UART_IE7816_INITDE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 13961 #define UART_IE7816_INITDE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 13962 #define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
AnnaBridge 171:3a7713b1edbc 13963 #define UART_IE7816_BWTE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 13964 #define UART_IE7816_BWTE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 13965 #define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
AnnaBridge 171:3a7713b1edbc 13966 #define UART_IE7816_CWTE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 13967 #define UART_IE7816_CWTE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 13968 #define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
AnnaBridge 171:3a7713b1edbc 13969 #define UART_IE7816_WTE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 13970 #define UART_IE7816_WTE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 13971 #define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
AnnaBridge 171:3a7713b1edbc 13972
AnnaBridge 171:3a7713b1edbc 13973 /*! @name IS7816 - UART 7816 Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 13974 #define UART_IS7816_RXT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 13975 #define UART_IS7816_RXT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 13976 #define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
AnnaBridge 171:3a7713b1edbc 13977 #define UART_IS7816_TXT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 13978 #define UART_IS7816_TXT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 13979 #define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
AnnaBridge 171:3a7713b1edbc 13980 #define UART_IS7816_GTV_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 13981 #define UART_IS7816_GTV_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 13982 #define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
AnnaBridge 171:3a7713b1edbc 13983 #define UART_IS7816_ADT_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 13984 #define UART_IS7816_ADT_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 13985 #define UART_IS7816_ADT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_ADT_SHIFT)) & UART_IS7816_ADT_MASK)
AnnaBridge 171:3a7713b1edbc 13986 #define UART_IS7816_INITD_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 13987 #define UART_IS7816_INITD_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 13988 #define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
AnnaBridge 171:3a7713b1edbc 13989 #define UART_IS7816_BWT_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 13990 #define UART_IS7816_BWT_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 13991 #define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
AnnaBridge 171:3a7713b1edbc 13992 #define UART_IS7816_CWT_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 13993 #define UART_IS7816_CWT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 13994 #define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
AnnaBridge 171:3a7713b1edbc 13995 #define UART_IS7816_WT_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 13996 #define UART_IS7816_WT_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 13997 #define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
AnnaBridge 171:3a7713b1edbc 13998
AnnaBridge 171:3a7713b1edbc 13999 /*! @name WP7816 - UART 7816 Wait Parameter Register */
AnnaBridge 171:3a7713b1edbc 14000 #define UART_WP7816_WTX_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 14001 #define UART_WP7816_WTX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14002 #define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816_WTX_SHIFT)) & UART_WP7816_WTX_MASK)
AnnaBridge 171:3a7713b1edbc 14003
AnnaBridge 171:3a7713b1edbc 14004 /*! @name WN7816 - UART 7816 Wait N Register */
AnnaBridge 171:3a7713b1edbc 14005 #define UART_WN7816_GTN_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 14006 #define UART_WN7816_GTN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14007 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
AnnaBridge 171:3a7713b1edbc 14008
AnnaBridge 171:3a7713b1edbc 14009 /*! @name WF7816 - UART 7816 Wait FD Register */
AnnaBridge 171:3a7713b1edbc 14010 #define UART_WF7816_GTFD_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 14011 #define UART_WF7816_GTFD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14012 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
AnnaBridge 171:3a7713b1edbc 14013
AnnaBridge 171:3a7713b1edbc 14014 /*! @name ET7816 - UART 7816 Error Threshold Register */
AnnaBridge 171:3a7713b1edbc 14015 #define UART_ET7816_RXTHRESHOLD_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 14016 #define UART_ET7816_RXTHRESHOLD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14017 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
AnnaBridge 171:3a7713b1edbc 14018 #define UART_ET7816_TXTHRESHOLD_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 14019 #define UART_ET7816_TXTHRESHOLD_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 14020 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
AnnaBridge 171:3a7713b1edbc 14021
AnnaBridge 171:3a7713b1edbc 14022 /*! @name TL7816 - UART 7816 Transmit Length Register */
AnnaBridge 171:3a7713b1edbc 14023 #define UART_TL7816_TLEN_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 14024 #define UART_TL7816_TLEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14025 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
AnnaBridge 171:3a7713b1edbc 14026
AnnaBridge 171:3a7713b1edbc 14027 /*! @name AP7816A_T0 - UART 7816 ATR Duration Timer Register A */
AnnaBridge 171:3a7713b1edbc 14028 #define UART_AP7816A_T0_ADTI_H_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 14029 #define UART_AP7816A_T0_ADTI_H_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14030 #define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816A_T0_ADTI_H_SHIFT)) & UART_AP7816A_T0_ADTI_H_MASK)
AnnaBridge 171:3a7713b1edbc 14031
AnnaBridge 171:3a7713b1edbc 14032 /*! @name AP7816B_T0 - UART 7816 ATR Duration Timer Register B */
AnnaBridge 171:3a7713b1edbc 14033 #define UART_AP7816B_T0_ADTI_L_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 14034 #define UART_AP7816B_T0_ADTI_L_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14035 #define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816B_T0_ADTI_L_SHIFT)) & UART_AP7816B_T0_ADTI_L_MASK)
AnnaBridge 171:3a7713b1edbc 14036
AnnaBridge 171:3a7713b1edbc 14037 /*! @name WP7816A_T0 - UART 7816 Wait Parameter Register A */
AnnaBridge 171:3a7713b1edbc 14038 #define UART_WP7816A_T0_WI_H_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 14039 #define UART_WP7816A_T0_WI_H_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14040 #define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T0_WI_H_SHIFT)) & UART_WP7816A_T0_WI_H_MASK)
AnnaBridge 171:3a7713b1edbc 14041
AnnaBridge 171:3a7713b1edbc 14042 /*! @name WP7816B_T0 - UART 7816 Wait Parameter Register B */
AnnaBridge 171:3a7713b1edbc 14043 #define UART_WP7816B_T0_WI_L_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 14044 #define UART_WP7816B_T0_WI_L_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14045 #define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T0_WI_L_SHIFT)) & UART_WP7816B_T0_WI_L_MASK)
AnnaBridge 171:3a7713b1edbc 14046
AnnaBridge 171:3a7713b1edbc 14047 /*! @name WP7816A_T1 - UART 7816 Wait Parameter Register A */
AnnaBridge 171:3a7713b1edbc 14048 #define UART_WP7816A_T1_BWI_H_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 14049 #define UART_WP7816A_T1_BWI_H_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14050 #define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T1_BWI_H_SHIFT)) & UART_WP7816A_T1_BWI_H_MASK)
AnnaBridge 171:3a7713b1edbc 14051
AnnaBridge 171:3a7713b1edbc 14052 /*! @name WP7816B_T1 - UART 7816 Wait Parameter Register B */
AnnaBridge 171:3a7713b1edbc 14053 #define UART_WP7816B_T1_BWI_L_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 14054 #define UART_WP7816B_T1_BWI_L_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14055 #define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T1_BWI_L_SHIFT)) & UART_WP7816B_T1_BWI_L_MASK)
AnnaBridge 171:3a7713b1edbc 14056
AnnaBridge 171:3a7713b1edbc 14057 /*! @name WGP7816_T1 - UART 7816 Wait and Guard Parameter Register */
AnnaBridge 171:3a7713b1edbc 14058 #define UART_WGP7816_T1_BGI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 14059 #define UART_WGP7816_T1_BGI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14060 #define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_BGI_SHIFT)) & UART_WGP7816_T1_BGI_MASK)
AnnaBridge 171:3a7713b1edbc 14061 #define UART_WGP7816_T1_CWI1_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 14062 #define UART_WGP7816_T1_CWI1_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 14063 #define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_CWI1_SHIFT)) & UART_WGP7816_T1_CWI1_MASK)
AnnaBridge 171:3a7713b1edbc 14064
AnnaBridge 171:3a7713b1edbc 14065 /*! @name WP7816C_T1 - UART 7816 Wait Parameter Register C */
AnnaBridge 171:3a7713b1edbc 14066 #define UART_WP7816C_T1_CWI2_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 14067 #define UART_WP7816C_T1_CWI2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14068 #define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816C_T1_CWI2_SHIFT)) & UART_WP7816C_T1_CWI2_MASK)
AnnaBridge 171:3a7713b1edbc 14069
AnnaBridge 171:3a7713b1edbc 14070
AnnaBridge 171:3a7713b1edbc 14071 /*!
AnnaBridge 171:3a7713b1edbc 14072 * @}
AnnaBridge 171:3a7713b1edbc 14073 */ /* end of group UART_Register_Masks */
AnnaBridge 171:3a7713b1edbc 14074
AnnaBridge 171:3a7713b1edbc 14075
AnnaBridge 171:3a7713b1edbc 14076 /* UART - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 14077 /** Peripheral UART0 base address */
AnnaBridge 171:3a7713b1edbc 14078 #define UART0_BASE (0x4006A000u)
AnnaBridge 171:3a7713b1edbc 14079 /** Peripheral UART0 base pointer */
AnnaBridge 171:3a7713b1edbc 14080 #define UART0 ((UART_Type *)UART0_BASE)
AnnaBridge 171:3a7713b1edbc 14081 /** Peripheral UART1 base address */
AnnaBridge 171:3a7713b1edbc 14082 #define UART1_BASE (0x4006B000u)
AnnaBridge 171:3a7713b1edbc 14083 /** Peripheral UART1 base pointer */
AnnaBridge 171:3a7713b1edbc 14084 #define UART1 ((UART_Type *)UART1_BASE)
AnnaBridge 171:3a7713b1edbc 14085 /** Peripheral UART2 base address */
AnnaBridge 171:3a7713b1edbc 14086 #define UART2_BASE (0x4006C000u)
AnnaBridge 171:3a7713b1edbc 14087 /** Peripheral UART2 base pointer */
AnnaBridge 171:3a7713b1edbc 14088 #define UART2 ((UART_Type *)UART2_BASE)
AnnaBridge 171:3a7713b1edbc 14089 /** Peripheral UART3 base address */
AnnaBridge 171:3a7713b1edbc 14090 #define UART3_BASE (0x4006D000u)
AnnaBridge 171:3a7713b1edbc 14091 /** Peripheral UART3 base pointer */
AnnaBridge 171:3a7713b1edbc 14092 #define UART3 ((UART_Type *)UART3_BASE)
AnnaBridge 171:3a7713b1edbc 14093 /** Peripheral UART4 base address */
AnnaBridge 171:3a7713b1edbc 14094 #define UART4_BASE (0x400EA000u)
AnnaBridge 171:3a7713b1edbc 14095 /** Peripheral UART4 base pointer */
AnnaBridge 171:3a7713b1edbc 14096 #define UART4 ((UART_Type *)UART4_BASE)
AnnaBridge 171:3a7713b1edbc 14097 /** Array initializer of UART peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 14098 #define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE }
AnnaBridge 171:3a7713b1edbc 14099 /** Array initializer of UART peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 14100 #define UART_BASE_PTRS { UART0, UART1, UART2, UART3, UART4 }
AnnaBridge 171:3a7713b1edbc 14101 /** Interrupt vectors for the UART peripheral type */
AnnaBridge 171:3a7713b1edbc 14102 #define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn }
AnnaBridge 171:3a7713b1edbc 14103 #define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn }
AnnaBridge 171:3a7713b1edbc 14104
AnnaBridge 171:3a7713b1edbc 14105 /*!
AnnaBridge 171:3a7713b1edbc 14106 * @}
AnnaBridge 171:3a7713b1edbc 14107 */ /* end of group UART_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 14108
AnnaBridge 171:3a7713b1edbc 14109
AnnaBridge 171:3a7713b1edbc 14110 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14111 -- USB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 14112 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 14113
AnnaBridge 171:3a7713b1edbc 14114 /*!
AnnaBridge 171:3a7713b1edbc 14115 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 14116 * @{
AnnaBridge 171:3a7713b1edbc 14117 */
AnnaBridge 171:3a7713b1edbc 14118
AnnaBridge 171:3a7713b1edbc 14119 /** USB - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 14120 typedef struct {
AnnaBridge 171:3a7713b1edbc 14121 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 14122 uint8_t RESERVED_0[3];
AnnaBridge 171:3a7713b1edbc 14123 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 14124 uint8_t RESERVED_1[3];
AnnaBridge 171:3a7713b1edbc 14125 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 14126 uint8_t RESERVED_2[3];
AnnaBridge 171:3a7713b1edbc 14127 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 14128 uint8_t RESERVED_3[3];
AnnaBridge 171:3a7713b1edbc 14129 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 14130 uint8_t RESERVED_4[3];
AnnaBridge 171:3a7713b1edbc 14131 __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 14132 uint8_t RESERVED_5[3];
AnnaBridge 171:3a7713b1edbc 14133 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 14134 uint8_t RESERVED_6[3];
AnnaBridge 171:3a7713b1edbc 14135 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 14136 uint8_t RESERVED_7[99];
AnnaBridge 171:3a7713b1edbc 14137 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 14138 uint8_t RESERVED_8[3];
AnnaBridge 171:3a7713b1edbc 14139 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 14140 uint8_t RESERVED_9[3];
AnnaBridge 171:3a7713b1edbc 14141 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 14142 uint8_t RESERVED_10[3];
AnnaBridge 171:3a7713b1edbc 14143 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 14144 uint8_t RESERVED_11[3];
AnnaBridge 171:3a7713b1edbc 14145 __I uint8_t STAT; /**< Status register, offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 14146 uint8_t RESERVED_12[3];
AnnaBridge 171:3a7713b1edbc 14147 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 14148 uint8_t RESERVED_13[3];
AnnaBridge 171:3a7713b1edbc 14149 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
AnnaBridge 171:3a7713b1edbc 14150 uint8_t RESERVED_14[3];
AnnaBridge 171:3a7713b1edbc 14151 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
AnnaBridge 171:3a7713b1edbc 14152 uint8_t RESERVED_15[3];
AnnaBridge 171:3a7713b1edbc 14153 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
AnnaBridge 171:3a7713b1edbc 14154 uint8_t RESERVED_16[3];
AnnaBridge 171:3a7713b1edbc 14155 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
AnnaBridge 171:3a7713b1edbc 14156 uint8_t RESERVED_17[3];
AnnaBridge 171:3a7713b1edbc 14157 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
AnnaBridge 171:3a7713b1edbc 14158 uint8_t RESERVED_18[3];
AnnaBridge 171:3a7713b1edbc 14159 __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
AnnaBridge 171:3a7713b1edbc 14160 uint8_t RESERVED_19[3];
AnnaBridge 171:3a7713b1edbc 14161 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
AnnaBridge 171:3a7713b1edbc 14162 uint8_t RESERVED_20[3];
AnnaBridge 171:3a7713b1edbc 14163 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
AnnaBridge 171:3a7713b1edbc 14164 uint8_t RESERVED_21[11];
AnnaBridge 171:3a7713b1edbc 14165 struct { /* offset: 0xC0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 14166 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 14167 uint8_t RESERVED_0[3];
AnnaBridge 171:3a7713b1edbc 14168 } ENDPOINT[16];
AnnaBridge 171:3a7713b1edbc 14169 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
AnnaBridge 171:3a7713b1edbc 14170 uint8_t RESERVED_22[3];
AnnaBridge 171:3a7713b1edbc 14171 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
AnnaBridge 171:3a7713b1edbc 14172 uint8_t RESERVED_23[3];
AnnaBridge 171:3a7713b1edbc 14173 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
AnnaBridge 171:3a7713b1edbc 14174 uint8_t RESERVED_24[3];
AnnaBridge 171:3a7713b1edbc 14175 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
AnnaBridge 171:3a7713b1edbc 14176 uint8_t RESERVED_25[7];
AnnaBridge 171:3a7713b1edbc 14177 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
AnnaBridge 171:3a7713b1edbc 14178 uint8_t RESERVED_26[43];
AnnaBridge 171:3a7713b1edbc 14179 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
AnnaBridge 171:3a7713b1edbc 14180 uint8_t RESERVED_27[3];
AnnaBridge 171:3a7713b1edbc 14181 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
AnnaBridge 171:3a7713b1edbc 14182 uint8_t RESERVED_28[15];
AnnaBridge 171:3a7713b1edbc 14183 __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */
AnnaBridge 171:3a7713b1edbc 14184 uint8_t RESERVED_29[7];
AnnaBridge 171:3a7713b1edbc 14185 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
AnnaBridge 171:3a7713b1edbc 14186 } USB_Type;
AnnaBridge 171:3a7713b1edbc 14187
AnnaBridge 171:3a7713b1edbc 14188 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14189 -- USB Register Masks
AnnaBridge 171:3a7713b1edbc 14190 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 14191
AnnaBridge 171:3a7713b1edbc 14192 /*!
AnnaBridge 171:3a7713b1edbc 14193 * @addtogroup USB_Register_Masks USB Register Masks
AnnaBridge 171:3a7713b1edbc 14194 * @{
AnnaBridge 171:3a7713b1edbc 14195 */
AnnaBridge 171:3a7713b1edbc 14196
AnnaBridge 171:3a7713b1edbc 14197 /*! @name PERID - Peripheral ID register */
AnnaBridge 171:3a7713b1edbc 14198 #define USB_PERID_ID_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 14199 #define USB_PERID_ID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14200 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
AnnaBridge 171:3a7713b1edbc 14201
AnnaBridge 171:3a7713b1edbc 14202 /*! @name IDCOMP - Peripheral ID Complement register */
AnnaBridge 171:3a7713b1edbc 14203 #define USB_IDCOMP_NID_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 14204 #define USB_IDCOMP_NID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14205 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
AnnaBridge 171:3a7713b1edbc 14206
AnnaBridge 171:3a7713b1edbc 14207 /*! @name REV - Peripheral Revision register */
AnnaBridge 171:3a7713b1edbc 14208 #define USB_REV_REV_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 14209 #define USB_REV_REV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14210 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
AnnaBridge 171:3a7713b1edbc 14211
AnnaBridge 171:3a7713b1edbc 14212 /*! @name ADDINFO - Peripheral Additional Info register */
AnnaBridge 171:3a7713b1edbc 14213 #define USB_ADDINFO_IEHOST_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 14214 #define USB_ADDINFO_IEHOST_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14215 #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
AnnaBridge 171:3a7713b1edbc 14216
AnnaBridge 171:3a7713b1edbc 14217 /*! @name OTGISTAT - OTG Interrupt Status register */
AnnaBridge 171:3a7713b1edbc 14218 #define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 14219 #define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14220 #define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
AnnaBridge 171:3a7713b1edbc 14221 #define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 14222 #define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 14223 #define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
AnnaBridge 171:3a7713b1edbc 14224 #define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 14225 #define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 14226 #define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
AnnaBridge 171:3a7713b1edbc 14227 #define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 14228 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 14229 #define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
AnnaBridge 171:3a7713b1edbc 14230 #define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 14231 #define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 14232 #define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
AnnaBridge 171:3a7713b1edbc 14233 #define USB_OTGISTAT_IDCHG_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 14234 #define USB_OTGISTAT_IDCHG_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 14235 #define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
AnnaBridge 171:3a7713b1edbc 14236
AnnaBridge 171:3a7713b1edbc 14237 /*! @name OTGICR - OTG Interrupt Control register */
AnnaBridge 171:3a7713b1edbc 14238 #define USB_OTGICR_AVBUSEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 14239 #define USB_OTGICR_AVBUSEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14240 #define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
AnnaBridge 171:3a7713b1edbc 14241 #define USB_OTGICR_BSESSEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 14242 #define USB_OTGICR_BSESSEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 14243 #define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
AnnaBridge 171:3a7713b1edbc 14244 #define USB_OTGICR_SESSVLDEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 14245 #define USB_OTGICR_SESSVLDEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 14246 #define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
AnnaBridge 171:3a7713b1edbc 14247 #define USB_OTGICR_LINESTATEEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 14248 #define USB_OTGICR_LINESTATEEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 14249 #define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
AnnaBridge 171:3a7713b1edbc 14250 #define USB_OTGICR_ONEMSECEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 14251 #define USB_OTGICR_ONEMSECEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 14252 #define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
AnnaBridge 171:3a7713b1edbc 14253 #define USB_OTGICR_IDEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 14254 #define USB_OTGICR_IDEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 14255 #define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
AnnaBridge 171:3a7713b1edbc 14256
AnnaBridge 171:3a7713b1edbc 14257 /*! @name OTGSTAT - OTG Status register */
AnnaBridge 171:3a7713b1edbc 14258 #define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 14259 #define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14260 #define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
AnnaBridge 171:3a7713b1edbc 14261 #define USB_OTGSTAT_BSESSEND_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 14262 #define USB_OTGSTAT_BSESSEND_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 14263 #define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
AnnaBridge 171:3a7713b1edbc 14264 #define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 14265 #define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 14266 #define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
AnnaBridge 171:3a7713b1edbc 14267 #define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 14268 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 14269 #define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
AnnaBridge 171:3a7713b1edbc 14270 #define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 14271 #define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 14272 #define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
AnnaBridge 171:3a7713b1edbc 14273 #define USB_OTGSTAT_ID_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 14274 #define USB_OTGSTAT_ID_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 14275 #define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
AnnaBridge 171:3a7713b1edbc 14276
AnnaBridge 171:3a7713b1edbc 14277 /*! @name OTGCTL - OTG Control register */
AnnaBridge 171:3a7713b1edbc 14278 #define USB_OTGCTL_OTGEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 14279 #define USB_OTGCTL_OTGEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 14280 #define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
AnnaBridge 171:3a7713b1edbc 14281 #define USB_OTGCTL_DMLOW_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 14282 #define USB_OTGCTL_DMLOW_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 14283 #define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
AnnaBridge 171:3a7713b1edbc 14284 #define USB_OTGCTL_DPLOW_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 14285 #define USB_OTGCTL_DPLOW_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 14286 #define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
AnnaBridge 171:3a7713b1edbc 14287 #define USB_OTGCTL_DPHIGH_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 14288 #define USB_OTGCTL_DPHIGH_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 14289 #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
AnnaBridge 171:3a7713b1edbc 14290
AnnaBridge 171:3a7713b1edbc 14291 /*! @name ISTAT - Interrupt Status register */
AnnaBridge 171:3a7713b1edbc 14292 #define USB_ISTAT_USBRST_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 14293 #define USB_ISTAT_USBRST_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14294 #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
AnnaBridge 171:3a7713b1edbc 14295 #define USB_ISTAT_ERROR_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 14296 #define USB_ISTAT_ERROR_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 14297 #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
AnnaBridge 171:3a7713b1edbc 14298 #define USB_ISTAT_SOFTOK_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 14299 #define USB_ISTAT_SOFTOK_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 14300 #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
AnnaBridge 171:3a7713b1edbc 14301 #define USB_ISTAT_TOKDNE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 14302 #define USB_ISTAT_TOKDNE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 14303 #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
AnnaBridge 171:3a7713b1edbc 14304 #define USB_ISTAT_SLEEP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 14305 #define USB_ISTAT_SLEEP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 14306 #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
AnnaBridge 171:3a7713b1edbc 14307 #define USB_ISTAT_RESUME_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 14308 #define USB_ISTAT_RESUME_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 14309 #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
AnnaBridge 171:3a7713b1edbc 14310 #define USB_ISTAT_ATTACH_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 14311 #define USB_ISTAT_ATTACH_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 14312 #define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
AnnaBridge 171:3a7713b1edbc 14313 #define USB_ISTAT_STALL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 14314 #define USB_ISTAT_STALL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 14315 #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
AnnaBridge 171:3a7713b1edbc 14316
AnnaBridge 171:3a7713b1edbc 14317 /*! @name INTEN - Interrupt Enable register */
AnnaBridge 171:3a7713b1edbc 14318 #define USB_INTEN_USBRSTEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 14319 #define USB_INTEN_USBRSTEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14320 #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
AnnaBridge 171:3a7713b1edbc 14321 #define USB_INTEN_ERROREN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 14322 #define USB_INTEN_ERROREN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 14323 #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
AnnaBridge 171:3a7713b1edbc 14324 #define USB_INTEN_SOFTOKEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 14325 #define USB_INTEN_SOFTOKEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 14326 #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
AnnaBridge 171:3a7713b1edbc 14327 #define USB_INTEN_TOKDNEEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 14328 #define USB_INTEN_TOKDNEEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 14329 #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
AnnaBridge 171:3a7713b1edbc 14330 #define USB_INTEN_SLEEPEN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 14331 #define USB_INTEN_SLEEPEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 14332 #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
AnnaBridge 171:3a7713b1edbc 14333 #define USB_INTEN_RESUMEEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 14334 #define USB_INTEN_RESUMEEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 14335 #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
AnnaBridge 171:3a7713b1edbc 14336 #define USB_INTEN_ATTACHEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 14337 #define USB_INTEN_ATTACHEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 14338 #define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
AnnaBridge 171:3a7713b1edbc 14339 #define USB_INTEN_STALLEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 14340 #define USB_INTEN_STALLEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 14341 #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
AnnaBridge 171:3a7713b1edbc 14342
AnnaBridge 171:3a7713b1edbc 14343 /*! @name ERRSTAT - Error Interrupt Status register */
AnnaBridge 171:3a7713b1edbc 14344 #define USB_ERRSTAT_PIDERR_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 14345 #define USB_ERRSTAT_PIDERR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14346 #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
AnnaBridge 171:3a7713b1edbc 14347 #define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 14348 #define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 14349 #define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
AnnaBridge 171:3a7713b1edbc 14350 #define USB_ERRSTAT_CRC16_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 14351 #define USB_ERRSTAT_CRC16_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 14352 #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
AnnaBridge 171:3a7713b1edbc 14353 #define USB_ERRSTAT_DFN8_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 14354 #define USB_ERRSTAT_DFN8_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 14355 #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
AnnaBridge 171:3a7713b1edbc 14356 #define USB_ERRSTAT_BTOERR_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 14357 #define USB_ERRSTAT_BTOERR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 14358 #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
AnnaBridge 171:3a7713b1edbc 14359 #define USB_ERRSTAT_DMAERR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 14360 #define USB_ERRSTAT_DMAERR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 14361 #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
AnnaBridge 171:3a7713b1edbc 14362 #define USB_ERRSTAT_BTSERR_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 14363 #define USB_ERRSTAT_BTSERR_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 14364 #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
AnnaBridge 171:3a7713b1edbc 14365
AnnaBridge 171:3a7713b1edbc 14366 /*! @name ERREN - Error Interrupt Enable register */
AnnaBridge 171:3a7713b1edbc 14367 #define USB_ERREN_PIDERREN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 14368 #define USB_ERREN_PIDERREN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14369 #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
AnnaBridge 171:3a7713b1edbc 14370 #define USB_ERREN_CRC5EOFEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 14371 #define USB_ERREN_CRC5EOFEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 14372 #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
AnnaBridge 171:3a7713b1edbc 14373 #define USB_ERREN_CRC16EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 14374 #define USB_ERREN_CRC16EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 14375 #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
AnnaBridge 171:3a7713b1edbc 14376 #define USB_ERREN_DFN8EN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 14377 #define USB_ERREN_DFN8EN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 14378 #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
AnnaBridge 171:3a7713b1edbc 14379 #define USB_ERREN_BTOERREN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 14380 #define USB_ERREN_BTOERREN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 14381 #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
AnnaBridge 171:3a7713b1edbc 14382 #define USB_ERREN_DMAERREN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 14383 #define USB_ERREN_DMAERREN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 14384 #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
AnnaBridge 171:3a7713b1edbc 14385 #define USB_ERREN_BTSERREN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 14386 #define USB_ERREN_BTSERREN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 14387 #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
AnnaBridge 171:3a7713b1edbc 14388
AnnaBridge 171:3a7713b1edbc 14389 /*! @name STAT - Status register */
AnnaBridge 171:3a7713b1edbc 14390 #define USB_STAT_ODD_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 14391 #define USB_STAT_ODD_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 14392 #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
AnnaBridge 171:3a7713b1edbc 14393 #define USB_STAT_TX_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 14394 #define USB_STAT_TX_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 14395 #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
AnnaBridge 171:3a7713b1edbc 14396 #define USB_STAT_ENDP_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 14397 #define USB_STAT_ENDP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 14398 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
AnnaBridge 171:3a7713b1edbc 14399
AnnaBridge 171:3a7713b1edbc 14400 /*! @name CTL - Control register */
AnnaBridge 171:3a7713b1edbc 14401 #define USB_CTL_USBENSOFEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 14402 #define USB_CTL_USBENSOFEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14403 #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
AnnaBridge 171:3a7713b1edbc 14404 #define USB_CTL_ODDRST_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 14405 #define USB_CTL_ODDRST_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 14406 #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
AnnaBridge 171:3a7713b1edbc 14407 #define USB_CTL_RESUME_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 14408 #define USB_CTL_RESUME_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 14409 #define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
AnnaBridge 171:3a7713b1edbc 14410 #define USB_CTL_HOSTMODEEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 14411 #define USB_CTL_HOSTMODEEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 14412 #define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
AnnaBridge 171:3a7713b1edbc 14413 #define USB_CTL_RESET_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 14414 #define USB_CTL_RESET_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 14415 #define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
AnnaBridge 171:3a7713b1edbc 14416 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 14417 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 14418 #define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
AnnaBridge 171:3a7713b1edbc 14419 #define USB_CTL_SE0_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 14420 #define USB_CTL_SE0_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 14421 #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
AnnaBridge 171:3a7713b1edbc 14422 #define USB_CTL_JSTATE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 14423 #define USB_CTL_JSTATE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 14424 #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
AnnaBridge 171:3a7713b1edbc 14425
AnnaBridge 171:3a7713b1edbc 14426 /*! @name ADDR - Address register */
AnnaBridge 171:3a7713b1edbc 14427 #define USB_ADDR_ADDR_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 14428 #define USB_ADDR_ADDR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14429 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
AnnaBridge 171:3a7713b1edbc 14430 #define USB_ADDR_LSEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 14431 #define USB_ADDR_LSEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 14432 #define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
AnnaBridge 171:3a7713b1edbc 14433
AnnaBridge 171:3a7713b1edbc 14434 /*! @name BDTPAGE1 - BDT Page register 1 */
AnnaBridge 171:3a7713b1edbc 14435 #define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
AnnaBridge 171:3a7713b1edbc 14436 #define USB_BDTPAGE1_BDTBA_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 14437 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
AnnaBridge 171:3a7713b1edbc 14438
AnnaBridge 171:3a7713b1edbc 14439 /*! @name FRMNUML - Frame Number register Low */
AnnaBridge 171:3a7713b1edbc 14440 #define USB_FRMNUML_FRM_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 14441 #define USB_FRMNUML_FRM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14442 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
AnnaBridge 171:3a7713b1edbc 14443
AnnaBridge 171:3a7713b1edbc 14444 /*! @name FRMNUMH - Frame Number register High */
AnnaBridge 171:3a7713b1edbc 14445 #define USB_FRMNUMH_FRM_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 14446 #define USB_FRMNUMH_FRM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14447 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
AnnaBridge 171:3a7713b1edbc 14448
AnnaBridge 171:3a7713b1edbc 14449 /*! @name TOKEN - Token register */
AnnaBridge 171:3a7713b1edbc 14450 #define USB_TOKEN_TOKENENDPT_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 14451 #define USB_TOKEN_TOKENENDPT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14452 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
AnnaBridge 171:3a7713b1edbc 14453 #define USB_TOKEN_TOKENPID_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 14454 #define USB_TOKEN_TOKENPID_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 14455 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
AnnaBridge 171:3a7713b1edbc 14456
AnnaBridge 171:3a7713b1edbc 14457 /*! @name SOFTHLD - SOF Threshold register */
AnnaBridge 171:3a7713b1edbc 14458 #define USB_SOFTHLD_CNT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 14459 #define USB_SOFTHLD_CNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14460 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
AnnaBridge 171:3a7713b1edbc 14461
AnnaBridge 171:3a7713b1edbc 14462 /*! @name BDTPAGE2 - BDT Page Register 2 */
AnnaBridge 171:3a7713b1edbc 14463 #define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 14464 #define USB_BDTPAGE2_BDTBA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14465 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
AnnaBridge 171:3a7713b1edbc 14466
AnnaBridge 171:3a7713b1edbc 14467 /*! @name BDTPAGE3 - BDT Page Register 3 */
AnnaBridge 171:3a7713b1edbc 14468 #define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 14469 #define USB_BDTPAGE3_BDTBA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14470 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
AnnaBridge 171:3a7713b1edbc 14471
AnnaBridge 171:3a7713b1edbc 14472 /*! @name ENDPT - Endpoint Control register */
AnnaBridge 171:3a7713b1edbc 14473 #define USB_ENDPT_EPHSHK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 14474 #define USB_ENDPT_EPHSHK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14475 #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
AnnaBridge 171:3a7713b1edbc 14476 #define USB_ENDPT_EPSTALL_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 14477 #define USB_ENDPT_EPSTALL_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 14478 #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
AnnaBridge 171:3a7713b1edbc 14479 #define USB_ENDPT_EPTXEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 14480 #define USB_ENDPT_EPTXEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 14481 #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
AnnaBridge 171:3a7713b1edbc 14482 #define USB_ENDPT_EPRXEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 14483 #define USB_ENDPT_EPRXEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 14484 #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
AnnaBridge 171:3a7713b1edbc 14485 #define USB_ENDPT_EPCTLDIS_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 14486 #define USB_ENDPT_EPCTLDIS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 14487 #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
AnnaBridge 171:3a7713b1edbc 14488 #define USB_ENDPT_RETRYDIS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 14489 #define USB_ENDPT_RETRYDIS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 14490 #define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
AnnaBridge 171:3a7713b1edbc 14491 #define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 14492 #define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 14493 #define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
AnnaBridge 171:3a7713b1edbc 14494
AnnaBridge 171:3a7713b1edbc 14495 /* The count of USB_ENDPT */
AnnaBridge 171:3a7713b1edbc 14496 #define USB_ENDPT_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 14497
AnnaBridge 171:3a7713b1edbc 14498 /*! @name USBCTRL - USB Control register */
AnnaBridge 171:3a7713b1edbc 14499 #define USB_USBCTRL_PDE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 14500 #define USB_USBCTRL_PDE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 14501 #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
AnnaBridge 171:3a7713b1edbc 14502 #define USB_USBCTRL_SUSP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 14503 #define USB_USBCTRL_SUSP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 14504 #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
AnnaBridge 171:3a7713b1edbc 14505
AnnaBridge 171:3a7713b1edbc 14506 /*! @name OBSERVE - USB OTG Observe register */
AnnaBridge 171:3a7713b1edbc 14507 #define USB_OBSERVE_DMPD_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 14508 #define USB_OBSERVE_DMPD_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 14509 #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
AnnaBridge 171:3a7713b1edbc 14510 #define USB_OBSERVE_DPPD_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 14511 #define USB_OBSERVE_DPPD_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 14512 #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
AnnaBridge 171:3a7713b1edbc 14513 #define USB_OBSERVE_DPPU_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 14514 #define USB_OBSERVE_DPPU_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 14515 #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
AnnaBridge 171:3a7713b1edbc 14516
AnnaBridge 171:3a7713b1edbc 14517 /*! @name CONTROL - USB OTG Control register */
AnnaBridge 171:3a7713b1edbc 14518 #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 14519 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 14520 #define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
AnnaBridge 171:3a7713b1edbc 14521
AnnaBridge 171:3a7713b1edbc 14522 /*! @name USBTRC0 - USB Transceiver Control register 0 */
AnnaBridge 171:3a7713b1edbc 14523 #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 14524 #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14525 #define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
AnnaBridge 171:3a7713b1edbc 14526 #define USB_USBTRC0_SYNC_DET_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 14527 #define USB_USBTRC0_SYNC_DET_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 14528 #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
AnnaBridge 171:3a7713b1edbc 14529 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 14530 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 14531 #define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
AnnaBridge 171:3a7713b1edbc 14532 #define USB_USBTRC0_USBRESMEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 14533 #define USB_USBTRC0_USBRESMEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 14534 #define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
AnnaBridge 171:3a7713b1edbc 14535 #define USB_USBTRC0_USBRESET_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 14536 #define USB_USBTRC0_USBRESET_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 14537 #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
AnnaBridge 171:3a7713b1edbc 14538
AnnaBridge 171:3a7713b1edbc 14539 /*! @name USBFRMADJUST - Frame Adjust Register */
AnnaBridge 171:3a7713b1edbc 14540 #define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 14541 #define USB_USBFRMADJUST_ADJ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14542 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
AnnaBridge 171:3a7713b1edbc 14543
AnnaBridge 171:3a7713b1edbc 14544 /*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
AnnaBridge 171:3a7713b1edbc 14545 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 14546 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 14547 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
AnnaBridge 171:3a7713b1edbc 14548 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 14549 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 14550 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
AnnaBridge 171:3a7713b1edbc 14551 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 14552 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 14553 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
AnnaBridge 171:3a7713b1edbc 14554
AnnaBridge 171:3a7713b1edbc 14555 /*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
AnnaBridge 171:3a7713b1edbc 14556 #define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 14557 #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14558 #define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
AnnaBridge 171:3a7713b1edbc 14559 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 14560 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 14561 #define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
AnnaBridge 171:3a7713b1edbc 14562
AnnaBridge 171:3a7713b1edbc 14563 /*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */
AnnaBridge 171:3a7713b1edbc 14564 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 14565 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 14566 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
AnnaBridge 171:3a7713b1edbc 14567
AnnaBridge 171:3a7713b1edbc 14568 /*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
AnnaBridge 171:3a7713b1edbc 14569 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 14570 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 14571 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
AnnaBridge 171:3a7713b1edbc 14572
AnnaBridge 171:3a7713b1edbc 14573
AnnaBridge 171:3a7713b1edbc 14574 /*!
AnnaBridge 171:3a7713b1edbc 14575 * @}
AnnaBridge 171:3a7713b1edbc 14576 */ /* end of group USB_Register_Masks */
AnnaBridge 171:3a7713b1edbc 14577
AnnaBridge 171:3a7713b1edbc 14578
AnnaBridge 171:3a7713b1edbc 14579 /* USB - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 14580 /** Peripheral USB0 base address */
AnnaBridge 171:3a7713b1edbc 14581 #define USB0_BASE (0x40072000u)
AnnaBridge 171:3a7713b1edbc 14582 /** Peripheral USB0 base pointer */
AnnaBridge 171:3a7713b1edbc 14583 #define USB0 ((USB_Type *)USB0_BASE)
AnnaBridge 171:3a7713b1edbc 14584 /** Array initializer of USB peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 14585 #define USB_BASE_ADDRS { USB0_BASE }
AnnaBridge 171:3a7713b1edbc 14586 /** Array initializer of USB peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 14587 #define USB_BASE_PTRS { USB0 }
AnnaBridge 171:3a7713b1edbc 14588 /** Interrupt vectors for the USB peripheral type */
AnnaBridge 171:3a7713b1edbc 14589 #define USB_IRQS { USB0_IRQn }
AnnaBridge 171:3a7713b1edbc 14590
AnnaBridge 171:3a7713b1edbc 14591 /*!
AnnaBridge 171:3a7713b1edbc 14592 * @}
AnnaBridge 171:3a7713b1edbc 14593 */ /* end of group USB_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 14594
AnnaBridge 171:3a7713b1edbc 14595
AnnaBridge 171:3a7713b1edbc 14596 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14597 -- USBDCD Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 14598 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 14599
AnnaBridge 171:3a7713b1edbc 14600 /*!
AnnaBridge 171:3a7713b1edbc 14601 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 14602 * @{
AnnaBridge 171:3a7713b1edbc 14603 */
AnnaBridge 171:3a7713b1edbc 14604
AnnaBridge 171:3a7713b1edbc 14605 /** USBDCD - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 14606 typedef struct {
AnnaBridge 171:3a7713b1edbc 14607 __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 14608 __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 14609 __I uint32_t STATUS; /**< Status register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 14610 __IO uint32_t SIGNAL_OVERRIDE; /**< Signal Override Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 14611 __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 14612 __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 14613 union { /* offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 14614 __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 14615 __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 14616 };
AnnaBridge 171:3a7713b1edbc 14617 } USBDCD_Type;
AnnaBridge 171:3a7713b1edbc 14618
AnnaBridge 171:3a7713b1edbc 14619 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14620 -- USBDCD Register Masks
AnnaBridge 171:3a7713b1edbc 14621 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 14622
AnnaBridge 171:3a7713b1edbc 14623 /*!
AnnaBridge 171:3a7713b1edbc 14624 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
AnnaBridge 171:3a7713b1edbc 14625 * @{
AnnaBridge 171:3a7713b1edbc 14626 */
AnnaBridge 171:3a7713b1edbc 14627
AnnaBridge 171:3a7713b1edbc 14628 /*! @name CONTROL - Control register */
AnnaBridge 171:3a7713b1edbc 14629 #define USBDCD_CONTROL_IACK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 14630 #define USBDCD_CONTROL_IACK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14631 #define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
AnnaBridge 171:3a7713b1edbc 14632 #define USBDCD_CONTROL_IF_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 14633 #define USBDCD_CONTROL_IF_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 14634 #define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
AnnaBridge 171:3a7713b1edbc 14635 #define USBDCD_CONTROL_IE_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 14636 #define USBDCD_CONTROL_IE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 14637 #define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
AnnaBridge 171:3a7713b1edbc 14638 #define USBDCD_CONTROL_BC12_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 14639 #define USBDCD_CONTROL_BC12_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 14640 #define USBDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK)
AnnaBridge 171:3a7713b1edbc 14641 #define USBDCD_CONTROL_START_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 14642 #define USBDCD_CONTROL_START_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 14643 #define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
AnnaBridge 171:3a7713b1edbc 14644 #define USBDCD_CONTROL_SR_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 14645 #define USBDCD_CONTROL_SR_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 14646 #define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
AnnaBridge 171:3a7713b1edbc 14647
AnnaBridge 171:3a7713b1edbc 14648 /*! @name CLOCK - Clock register */
AnnaBridge 171:3a7713b1edbc 14649 #define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 14650 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14651 #define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
AnnaBridge 171:3a7713b1edbc 14652 #define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
AnnaBridge 171:3a7713b1edbc 14653 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 14654 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
AnnaBridge 171:3a7713b1edbc 14655
AnnaBridge 171:3a7713b1edbc 14656 /*! @name STATUS - Status register */
AnnaBridge 171:3a7713b1edbc 14657 #define USBDCD_STATUS_SEQ_RES_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 14658 #define USBDCD_STATUS_SEQ_RES_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 14659 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
AnnaBridge 171:3a7713b1edbc 14660 #define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 14661 #define USBDCD_STATUS_SEQ_STAT_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 14662 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
AnnaBridge 171:3a7713b1edbc 14663 #define USBDCD_STATUS_ERR_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 14664 #define USBDCD_STATUS_ERR_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 14665 #define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
AnnaBridge 171:3a7713b1edbc 14666 #define USBDCD_STATUS_TO_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 14667 #define USBDCD_STATUS_TO_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 14668 #define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
AnnaBridge 171:3a7713b1edbc 14669 #define USBDCD_STATUS_ACTIVE_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 14670 #define USBDCD_STATUS_ACTIVE_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 14671 #define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
AnnaBridge 171:3a7713b1edbc 14672
AnnaBridge 171:3a7713b1edbc 14673 /*! @name SIGNAL_OVERRIDE - Signal Override Register */
AnnaBridge 171:3a7713b1edbc 14674 #define USBDCD_SIGNAL_OVERRIDE_PS_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 14675 #define USBDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14676 #define USBDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBDCD_SIGNAL_OVERRIDE_PS_MASK)
AnnaBridge 171:3a7713b1edbc 14677
AnnaBridge 171:3a7713b1edbc 14678 /*! @name TIMER0 - TIMER0 register */
AnnaBridge 171:3a7713b1edbc 14679 #define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU)
AnnaBridge 171:3a7713b1edbc 14680 #define USBDCD_TIMER0_TUNITCON_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14681 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
AnnaBridge 171:3a7713b1edbc 14682 #define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 14683 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 14684 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
AnnaBridge 171:3a7713b1edbc 14685
AnnaBridge 171:3a7713b1edbc 14686 /*! @name TIMER1 - TIMER1 register */
AnnaBridge 171:3a7713b1edbc 14687 #define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 14688 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14689 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
AnnaBridge 171:3a7713b1edbc 14690 #define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 14691 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 14692 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
AnnaBridge 171:3a7713b1edbc 14693
AnnaBridge 171:3a7713b1edbc 14694 /*! @name TIMER2_BC11 - TIMER2_BC11 register */
AnnaBridge 171:3a7713b1edbc 14695 #define USBDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 14696 #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14697 #define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK)
AnnaBridge 171:3a7713b1edbc 14698 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 14699 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 14700 #define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
AnnaBridge 171:3a7713b1edbc 14701
AnnaBridge 171:3a7713b1edbc 14702 /*! @name TIMER2_BC12 - TIMER2_BC12 register */
AnnaBridge 171:3a7713b1edbc 14703 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 14704 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14705 #define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
AnnaBridge 171:3a7713b1edbc 14706 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 14707 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 14708 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
AnnaBridge 171:3a7713b1edbc 14709
AnnaBridge 171:3a7713b1edbc 14710
AnnaBridge 171:3a7713b1edbc 14711 /*!
AnnaBridge 171:3a7713b1edbc 14712 * @}
AnnaBridge 171:3a7713b1edbc 14713 */ /* end of group USBDCD_Register_Masks */
AnnaBridge 171:3a7713b1edbc 14714
AnnaBridge 171:3a7713b1edbc 14715
AnnaBridge 171:3a7713b1edbc 14716 /* USBDCD - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 14717 /** Peripheral USBDCD base address */
AnnaBridge 171:3a7713b1edbc 14718 #define USBDCD_BASE (0x40035000u)
AnnaBridge 171:3a7713b1edbc 14719 /** Peripheral USBDCD base pointer */
AnnaBridge 171:3a7713b1edbc 14720 #define USBDCD ((USBDCD_Type *)USBDCD_BASE)
AnnaBridge 171:3a7713b1edbc 14721 /** Array initializer of USBDCD peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 14722 #define USBDCD_BASE_ADDRS { USBDCD_BASE }
AnnaBridge 171:3a7713b1edbc 14723 /** Array initializer of USBDCD peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 14724 #define USBDCD_BASE_PTRS { USBDCD }
AnnaBridge 171:3a7713b1edbc 14725 /** Interrupt vectors for the USBDCD peripheral type */
AnnaBridge 171:3a7713b1edbc 14726 #define USBDCD_IRQS { USBDCD_IRQn }
AnnaBridge 171:3a7713b1edbc 14727
AnnaBridge 171:3a7713b1edbc 14728 /*!
AnnaBridge 171:3a7713b1edbc 14729 * @}
AnnaBridge 171:3a7713b1edbc 14730 */ /* end of group USBDCD_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 14731
AnnaBridge 171:3a7713b1edbc 14732
AnnaBridge 171:3a7713b1edbc 14733 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14734 -- USBHS Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 14735 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 14736
AnnaBridge 171:3a7713b1edbc 14737 /*!
AnnaBridge 171:3a7713b1edbc 14738 * @addtogroup USBHS_Peripheral_Access_Layer USBHS Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 14739 * @{
AnnaBridge 171:3a7713b1edbc 14740 */
AnnaBridge 171:3a7713b1edbc 14741
AnnaBridge 171:3a7713b1edbc 14742 /** USBHS - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 14743 typedef struct {
AnnaBridge 171:3a7713b1edbc 14744 __I uint32_t ID; /**< Identification Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 14745 __I uint32_t HWGENERAL; /**< General Hardware Parameters Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 14746 __I uint32_t HWHOST; /**< Host Hardware Parameters Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 14747 __I uint32_t HWDEVICE; /**< Device Hardware Parameters Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 14748 __I uint32_t HWTXBUF; /**< Transmit Buffer Hardware Parameters Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 14749 __I uint32_t HWRXBUF; /**< Receive Buffer Hardware Parameters Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 14750 uint8_t RESERVED_0[104];
AnnaBridge 171:3a7713b1edbc 14751 __IO uint32_t GPTIMER0LD; /**< General Purpose Timer n Load Register, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 14752 __IO uint32_t GPTIMER0CTL; /**< General Purpose Timer n Control Register, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 14753 __IO uint32_t GPTIMER1LD; /**< General Purpose Timer n Load Register, offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 14754 __IO uint32_t GPTIMER1CTL; /**< General Purpose Timer n Control Register, offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 14755 __IO uint32_t USB_SBUSCFG; /**< System Bus Interface Configuration Register, offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 14756 uint8_t RESERVED_1[108];
AnnaBridge 171:3a7713b1edbc 14757 __I uint32_t HCIVERSION; /**< Host Controller Interface Version and Capability Registers Length Register, offset: 0x100 */
AnnaBridge 171:3a7713b1edbc 14758 __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters Register, offset: 0x104 */
AnnaBridge 171:3a7713b1edbc 14759 __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters Register, offset: 0x108 */
AnnaBridge 171:3a7713b1edbc 14760 uint8_t RESERVED_2[22];
AnnaBridge 171:3a7713b1edbc 14761 __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x122 */
AnnaBridge 171:3a7713b1edbc 14762 __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */
AnnaBridge 171:3a7713b1edbc 14763 uint8_t RESERVED_3[24];
AnnaBridge 171:3a7713b1edbc 14764 __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */
AnnaBridge 171:3a7713b1edbc 14765 __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */
AnnaBridge 171:3a7713b1edbc 14766 __IO uint32_t USBINTR; /**< USB Interrupt Enable Register, offset: 0x148 */
AnnaBridge 171:3a7713b1edbc 14767 __IO uint32_t FRINDEX; /**< Frame Index Register, offset: 0x14C */
AnnaBridge 171:3a7713b1edbc 14768 uint8_t RESERVED_4[4];
AnnaBridge 171:3a7713b1edbc 14769 union { /* offset: 0x154 */
AnnaBridge 171:3a7713b1edbc 14770 __IO uint32_t DEVICEADDR; /**< Device Address Register, offset: 0x154 */
AnnaBridge 171:3a7713b1edbc 14771 __IO uint32_t PERIODICLISTBASE; /**< Periodic Frame List Base Address Register, offset: 0x154 */
AnnaBridge 171:3a7713b1edbc 14772 };
AnnaBridge 171:3a7713b1edbc 14773 union { /* offset: 0x158 */
AnnaBridge 171:3a7713b1edbc 14774 __IO uint32_t ASYNCLISTADDR; /**< Current Asynchronous List Address Register, offset: 0x158 */
AnnaBridge 171:3a7713b1edbc 14775 __IO uint32_t EPLISTADDR; /**< Endpoint List Address Register, offset: 0x158 */
AnnaBridge 171:3a7713b1edbc 14776 };
AnnaBridge 171:3a7713b1edbc 14777 __I uint32_t TTCTRL; /**< Host TT Asynchronous Buffer Control, offset: 0x15C */
AnnaBridge 171:3a7713b1edbc 14778 __IO uint32_t BURSTSIZE; /**< Master Interface Data Burst Size Register, offset: 0x160 */
AnnaBridge 171:3a7713b1edbc 14779 __IO uint32_t TXFILLTUNING; /**< Transmit FIFO Tuning Control Register, offset: 0x164 */
AnnaBridge 171:3a7713b1edbc 14780 uint8_t RESERVED_5[16];
AnnaBridge 171:3a7713b1edbc 14781 __IO uint32_t ENDPTNAK; /**< Endpoint NAK Register, offset: 0x178 */
AnnaBridge 171:3a7713b1edbc 14782 __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable Register, offset: 0x17C */
AnnaBridge 171:3a7713b1edbc 14783 __I uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */
AnnaBridge 171:3a7713b1edbc 14784 __IO uint32_t PORTSC1; /**< Port Status and Control Registers, offset: 0x184 */
AnnaBridge 171:3a7713b1edbc 14785 uint8_t RESERVED_6[28];
AnnaBridge 171:3a7713b1edbc 14786 __IO uint32_t OTGSC; /**< On-the-Go Status and Control Register, offset: 0x1A4 */
AnnaBridge 171:3a7713b1edbc 14787 __IO uint32_t USBMODE; /**< USB Mode Register, offset: 0x1A8 */
AnnaBridge 171:3a7713b1edbc 14788 __IO uint32_t EPSETUPSR; /**< Endpoint Setup Status Register, offset: 0x1AC */
AnnaBridge 171:3a7713b1edbc 14789 __IO uint32_t EPPRIME; /**< Endpoint Initialization Register, offset: 0x1B0 */
AnnaBridge 171:3a7713b1edbc 14790 __IO uint32_t EPFLUSH; /**< Endpoint Flush Register, offset: 0x1B4 */
AnnaBridge 171:3a7713b1edbc 14791 __I uint32_t EPSR; /**< Endpoint Status Register, offset: 0x1B8 */
AnnaBridge 171:3a7713b1edbc 14792 __IO uint32_t EPCOMPLETE; /**< Endpoint Complete Register, offset: 0x1BC */
AnnaBridge 171:3a7713b1edbc 14793 __IO uint32_t EPCR0; /**< Endpoint Control Register 0, offset: 0x1C0 */
AnnaBridge 171:3a7713b1edbc 14794 __IO uint32_t EPCR[7]; /**< Endpoint Control Register n, array offset: 0x1C4, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 14795 uint8_t RESERVED_7[32];
AnnaBridge 171:3a7713b1edbc 14796 __IO uint32_t USBGENCTRL; /**< USB General Control Register, offset: 0x200 */
AnnaBridge 171:3a7713b1edbc 14797 } USBHS_Type;
AnnaBridge 171:3a7713b1edbc 14798
AnnaBridge 171:3a7713b1edbc 14799 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 14800 -- USBHS Register Masks
AnnaBridge 171:3a7713b1edbc 14801 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 14802
AnnaBridge 171:3a7713b1edbc 14803 /*!
AnnaBridge 171:3a7713b1edbc 14804 * @addtogroup USBHS_Register_Masks USBHS Register Masks
AnnaBridge 171:3a7713b1edbc 14805 * @{
AnnaBridge 171:3a7713b1edbc 14806 */
AnnaBridge 171:3a7713b1edbc 14807
AnnaBridge 171:3a7713b1edbc 14808 /*! @name ID - Identification Register */
AnnaBridge 171:3a7713b1edbc 14809 #define USBHS_ID_ID_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 14810 #define USBHS_ID_ID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14811 #define USBHS_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_ID_SHIFT)) & USBHS_ID_ID_MASK)
AnnaBridge 171:3a7713b1edbc 14812 #define USBHS_ID_NID_MASK (0x3F00U)
AnnaBridge 171:3a7713b1edbc 14813 #define USBHS_ID_NID_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 14814 #define USBHS_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_NID_SHIFT)) & USBHS_ID_NID_MASK)
AnnaBridge 171:3a7713b1edbc 14815 #define USBHS_ID_TAG_MASK (0x1F0000U)
AnnaBridge 171:3a7713b1edbc 14816 #define USBHS_ID_TAG_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 14817 #define USBHS_ID_TAG(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_TAG_SHIFT)) & USBHS_ID_TAG_MASK)
AnnaBridge 171:3a7713b1edbc 14818 #define USBHS_ID_REVISION_MASK (0x1E00000U)
AnnaBridge 171:3a7713b1edbc 14819 #define USBHS_ID_REVISION_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 14820 #define USBHS_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_REVISION_SHIFT)) & USBHS_ID_REVISION_MASK)
AnnaBridge 171:3a7713b1edbc 14821 #define USBHS_ID_VERSION_MASK (0x1E000000U)
AnnaBridge 171:3a7713b1edbc 14822 #define USBHS_ID_VERSION_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 14823 #define USBHS_ID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_VERSION_SHIFT)) & USBHS_ID_VERSION_MASK)
AnnaBridge 171:3a7713b1edbc 14824 #define USBHS_ID_VERSIONID_MASK (0xE0000000U)
AnnaBridge 171:3a7713b1edbc 14825 #define USBHS_ID_VERSIONID_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 14826 #define USBHS_ID_VERSIONID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_VERSIONID_SHIFT)) & USBHS_ID_VERSIONID_MASK)
AnnaBridge 171:3a7713b1edbc 14827
AnnaBridge 171:3a7713b1edbc 14828 /*! @name HWGENERAL - General Hardware Parameters Register */
AnnaBridge 171:3a7713b1edbc 14829 #define USBHS_HWGENERAL_PHYW_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 14830 #define USBHS_HWGENERAL_PHYW_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 14831 #define USBHS_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYW_SHIFT)) & USBHS_HWGENERAL_PHYW_MASK)
AnnaBridge 171:3a7713b1edbc 14832 #define USBHS_HWGENERAL_PHYM_MASK (0x1C0U)
AnnaBridge 171:3a7713b1edbc 14833 #define USBHS_HWGENERAL_PHYM_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 14834 #define USBHS_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYM_SHIFT)) & USBHS_HWGENERAL_PHYM_MASK)
AnnaBridge 171:3a7713b1edbc 14835 #define USBHS_HWGENERAL_SM_MASK (0x600U)
AnnaBridge 171:3a7713b1edbc 14836 #define USBHS_HWGENERAL_SM_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 14837 #define USBHS_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_SM_SHIFT)) & USBHS_HWGENERAL_SM_MASK)
AnnaBridge 171:3a7713b1edbc 14838
AnnaBridge 171:3a7713b1edbc 14839 /*! @name HWHOST - Host Hardware Parameters Register */
AnnaBridge 171:3a7713b1edbc 14840 #define USBHS_HWHOST_HC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 14841 #define USBHS_HWHOST_HC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14842 #define USBHS_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_HC_SHIFT)) & USBHS_HWHOST_HC_MASK)
AnnaBridge 171:3a7713b1edbc 14843 #define USBHS_HWHOST_NPORT_MASK (0xEU)
AnnaBridge 171:3a7713b1edbc 14844 #define USBHS_HWHOST_NPORT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 14845 #define USBHS_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_NPORT_SHIFT)) & USBHS_HWHOST_NPORT_MASK)
AnnaBridge 171:3a7713b1edbc 14846 #define USBHS_HWHOST_TTASY_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 14847 #define USBHS_HWHOST_TTASY_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 14848 #define USBHS_HWHOST_TTASY(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_TTASY_SHIFT)) & USBHS_HWHOST_TTASY_MASK)
AnnaBridge 171:3a7713b1edbc 14849 #define USBHS_HWHOST_TTPER_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 14850 #define USBHS_HWHOST_TTPER_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 14851 #define USBHS_HWHOST_TTPER(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_TTPER_SHIFT)) & USBHS_HWHOST_TTPER_MASK)
AnnaBridge 171:3a7713b1edbc 14852
AnnaBridge 171:3a7713b1edbc 14853 /*! @name HWDEVICE - Device Hardware Parameters Register */
AnnaBridge 171:3a7713b1edbc 14854 #define USBHS_HWDEVICE_DC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 14855 #define USBHS_HWDEVICE_DC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14856 #define USBHS_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DC_SHIFT)) & USBHS_HWDEVICE_DC_MASK)
AnnaBridge 171:3a7713b1edbc 14857 #define USBHS_HWDEVICE_DEVEP_MASK (0x3EU)
AnnaBridge 171:3a7713b1edbc 14858 #define USBHS_HWDEVICE_DEVEP_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 14859 #define USBHS_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DEVEP_SHIFT)) & USBHS_HWDEVICE_DEVEP_MASK)
AnnaBridge 171:3a7713b1edbc 14860
AnnaBridge 171:3a7713b1edbc 14861 /*! @name HWTXBUF - Transmit Buffer Hardware Parameters Register */
AnnaBridge 171:3a7713b1edbc 14862 #define USBHS_HWTXBUF_TXBURST_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 14863 #define USBHS_HWTXBUF_TXBURST_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14864 #define USBHS_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXBURST_SHIFT)) & USBHS_HWTXBUF_TXBURST_MASK)
AnnaBridge 171:3a7713b1edbc 14865 #define USBHS_HWTXBUF_TXADD_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 14866 #define USBHS_HWTXBUF_TXADD_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 14867 #define USBHS_HWTXBUF_TXADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXADD_SHIFT)) & USBHS_HWTXBUF_TXADD_MASK)
AnnaBridge 171:3a7713b1edbc 14868 #define USBHS_HWTXBUF_TXCHANADD_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 14869 #define USBHS_HWTXBUF_TXCHANADD_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 14870 #define USBHS_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXCHANADD_SHIFT)) & USBHS_HWTXBUF_TXCHANADD_MASK)
AnnaBridge 171:3a7713b1edbc 14871 #define USBHS_HWTXBUF_TXLC_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 14872 #define USBHS_HWTXBUF_TXLC_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 14873 #define USBHS_HWTXBUF_TXLC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXLC_SHIFT)) & USBHS_HWTXBUF_TXLC_MASK)
AnnaBridge 171:3a7713b1edbc 14874
AnnaBridge 171:3a7713b1edbc 14875 /*! @name HWRXBUF - Receive Buffer Hardware Parameters Register */
AnnaBridge 171:3a7713b1edbc 14876 #define USBHS_HWRXBUF_RXBURST_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 14877 #define USBHS_HWRXBUF_RXBURST_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14878 #define USBHS_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXBURST_SHIFT)) & USBHS_HWRXBUF_RXBURST_MASK)
AnnaBridge 171:3a7713b1edbc 14879 #define USBHS_HWRXBUF_RXADD_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 14880 #define USBHS_HWRXBUF_RXADD_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 14881 #define USBHS_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXADD_SHIFT)) & USBHS_HWRXBUF_RXADD_MASK)
AnnaBridge 171:3a7713b1edbc 14882
AnnaBridge 171:3a7713b1edbc 14883 /*! @name GPTIMER0LD - General Purpose Timer n Load Register */
AnnaBridge 171:3a7713b1edbc 14884 #define USBHS_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 14885 #define USBHS_GPTIMER0LD_GPTLD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14886 #define USBHS_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0LD_GPTLD_SHIFT)) & USBHS_GPTIMER0LD_GPTLD_MASK)
AnnaBridge 171:3a7713b1edbc 14887
AnnaBridge 171:3a7713b1edbc 14888 /*! @name GPTIMER0CTL - General Purpose Timer n Control Register */
AnnaBridge 171:3a7713b1edbc 14889 #define USBHS_GPTIMER0CTL_GPTCNT_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 14890 #define USBHS_GPTIMER0CTL_GPTCNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14891 #define USBHS_GPTIMER0CTL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_GPTCNT_SHIFT)) & USBHS_GPTIMER0CTL_GPTCNT_MASK)
AnnaBridge 171:3a7713b1edbc 14892 #define USBHS_GPTIMER0CTL_MODE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 14893 #define USBHS_GPTIMER0CTL_MODE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 14894 #define USBHS_GPTIMER0CTL_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_MODE_SHIFT)) & USBHS_GPTIMER0CTL_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 14895 #define USBHS_GPTIMER0CTL_RST_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 14896 #define USBHS_GPTIMER0CTL_RST_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 14897 #define USBHS_GPTIMER0CTL_RST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RST_SHIFT)) & USBHS_GPTIMER0CTL_RST_MASK)
AnnaBridge 171:3a7713b1edbc 14898 #define USBHS_GPTIMER0CTL_RUN_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 14899 #define USBHS_GPTIMER0CTL_RUN_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 14900 #define USBHS_GPTIMER0CTL_RUN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RUN_SHIFT)) & USBHS_GPTIMER0CTL_RUN_MASK)
AnnaBridge 171:3a7713b1edbc 14901
AnnaBridge 171:3a7713b1edbc 14902 /*! @name GPTIMER1LD - General Purpose Timer n Load Register */
AnnaBridge 171:3a7713b1edbc 14903 #define USBHS_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 14904 #define USBHS_GPTIMER1LD_GPTLD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14905 #define USBHS_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1LD_GPTLD_SHIFT)) & USBHS_GPTIMER1LD_GPTLD_MASK)
AnnaBridge 171:3a7713b1edbc 14906
AnnaBridge 171:3a7713b1edbc 14907 /*! @name GPTIMER1CTL - General Purpose Timer n Control Register */
AnnaBridge 171:3a7713b1edbc 14908 #define USBHS_GPTIMER1CTL_GPTCNT_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 14909 #define USBHS_GPTIMER1CTL_GPTCNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14910 #define USBHS_GPTIMER1CTL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_GPTCNT_SHIFT)) & USBHS_GPTIMER1CTL_GPTCNT_MASK)
AnnaBridge 171:3a7713b1edbc 14911 #define USBHS_GPTIMER1CTL_MODE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 14912 #define USBHS_GPTIMER1CTL_MODE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 14913 #define USBHS_GPTIMER1CTL_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_MODE_SHIFT)) & USBHS_GPTIMER1CTL_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 14914 #define USBHS_GPTIMER1CTL_RST_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 14915 #define USBHS_GPTIMER1CTL_RST_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 14916 #define USBHS_GPTIMER1CTL_RST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RST_SHIFT)) & USBHS_GPTIMER1CTL_RST_MASK)
AnnaBridge 171:3a7713b1edbc 14917 #define USBHS_GPTIMER1CTL_RUN_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 14918 #define USBHS_GPTIMER1CTL_RUN_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 14919 #define USBHS_GPTIMER1CTL_RUN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RUN_SHIFT)) & USBHS_GPTIMER1CTL_RUN_MASK)
AnnaBridge 171:3a7713b1edbc 14920
AnnaBridge 171:3a7713b1edbc 14921 /*! @name USB_SBUSCFG - System Bus Interface Configuration Register */
AnnaBridge 171:3a7713b1edbc 14922 #define USBHS_USB_SBUSCFG_BURSTMODE_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 14923 #define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14924 #define USBHS_USB_SBUSCFG_BURSTMODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USB_SBUSCFG_BURSTMODE_SHIFT)) & USBHS_USB_SBUSCFG_BURSTMODE_MASK)
AnnaBridge 171:3a7713b1edbc 14925
AnnaBridge 171:3a7713b1edbc 14926 /*! @name HCIVERSION - Host Controller Interface Version and Capability Registers Length Register */
AnnaBridge 171:3a7713b1edbc 14927 #define USBHS_HCIVERSION_CAPLENGTH_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 14928 #define USBHS_HCIVERSION_CAPLENGTH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14929 #define USBHS_HCIVERSION_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCIVERSION_CAPLENGTH_SHIFT)) & USBHS_HCIVERSION_CAPLENGTH_MASK)
AnnaBridge 171:3a7713b1edbc 14930 #define USBHS_HCIVERSION_HCIVERSION_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 14931 #define USBHS_HCIVERSION_HCIVERSION_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 14932 #define USBHS_HCIVERSION_HCIVERSION(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCIVERSION_HCIVERSION_SHIFT)) & USBHS_HCIVERSION_HCIVERSION_MASK)
AnnaBridge 171:3a7713b1edbc 14933
AnnaBridge 171:3a7713b1edbc 14934 /*! @name HCSPARAMS - Host Controller Structural Parameters Register */
AnnaBridge 171:3a7713b1edbc 14935 #define USBHS_HCSPARAMS_N_PORTS_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 14936 #define USBHS_HCSPARAMS_N_PORTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14937 #define USBHS_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PORTS_SHIFT)) & USBHS_HCSPARAMS_N_PORTS_MASK)
AnnaBridge 171:3a7713b1edbc 14938 #define USBHS_HCSPARAMS_PPC_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 14939 #define USBHS_HCSPARAMS_PPC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 14940 #define USBHS_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PPC_SHIFT)) & USBHS_HCSPARAMS_PPC_MASK)
AnnaBridge 171:3a7713b1edbc 14941 #define USBHS_HCSPARAMS_N_PCC_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 14942 #define USBHS_HCSPARAMS_N_PCC_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 14943 #define USBHS_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PCC_SHIFT)) & USBHS_HCSPARAMS_N_PCC_MASK)
AnnaBridge 171:3a7713b1edbc 14944 #define USBHS_HCSPARAMS_N_CC_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 14945 #define USBHS_HCSPARAMS_N_CC_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 14946 #define USBHS_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_CC_SHIFT)) & USBHS_HCSPARAMS_N_CC_MASK)
AnnaBridge 171:3a7713b1edbc 14947 #define USBHS_HCSPARAMS_PI_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 14948 #define USBHS_HCSPARAMS_PI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 14949 #define USBHS_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PI_SHIFT)) & USBHS_HCSPARAMS_PI_MASK)
AnnaBridge 171:3a7713b1edbc 14950 #define USBHS_HCSPARAMS_N_PTT_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 14951 #define USBHS_HCSPARAMS_N_PTT_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 14952 #define USBHS_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PTT_SHIFT)) & USBHS_HCSPARAMS_N_PTT_MASK)
AnnaBridge 171:3a7713b1edbc 14953 #define USBHS_HCSPARAMS_N_TT_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 14954 #define USBHS_HCSPARAMS_N_TT_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 14955 #define USBHS_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_TT_SHIFT)) & USBHS_HCSPARAMS_N_TT_MASK)
AnnaBridge 171:3a7713b1edbc 14956
AnnaBridge 171:3a7713b1edbc 14957 /*! @name HCCPARAMS - Host Controller Capability Parameters Register */
AnnaBridge 171:3a7713b1edbc 14958 #define USBHS_HCCPARAMS_ADC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 14959 #define USBHS_HCCPARAMS_ADC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14960 #define USBHS_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ADC_SHIFT)) & USBHS_HCCPARAMS_ADC_MASK)
AnnaBridge 171:3a7713b1edbc 14961 #define USBHS_HCCPARAMS_PFL_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 14962 #define USBHS_HCCPARAMS_PFL_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 14963 #define USBHS_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_PFL_SHIFT)) & USBHS_HCCPARAMS_PFL_MASK)
AnnaBridge 171:3a7713b1edbc 14964 #define USBHS_HCCPARAMS_ASP_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 14965 #define USBHS_HCCPARAMS_ASP_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 14966 #define USBHS_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ASP_SHIFT)) & USBHS_HCCPARAMS_ASP_MASK)
AnnaBridge 171:3a7713b1edbc 14967 #define USBHS_HCCPARAMS_IST_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 14968 #define USBHS_HCCPARAMS_IST_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 14969 #define USBHS_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_IST_SHIFT)) & USBHS_HCCPARAMS_IST_MASK)
AnnaBridge 171:3a7713b1edbc 14970 #define USBHS_HCCPARAMS_EECP_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 14971 #define USBHS_HCCPARAMS_EECP_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 14972 #define USBHS_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_EECP_SHIFT)) & USBHS_HCCPARAMS_EECP_MASK)
AnnaBridge 171:3a7713b1edbc 14973
AnnaBridge 171:3a7713b1edbc 14974 /*! @name DCIVERSION - Device Controller Interface Version */
AnnaBridge 171:3a7713b1edbc 14975 #define USBHS_DCIVERSION_DCIVERSION_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 14976 #define USBHS_DCIVERSION_DCIVERSION_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14977 #define USBHS_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USBHS_DCIVERSION_DCIVERSION_SHIFT)) & USBHS_DCIVERSION_DCIVERSION_MASK)
AnnaBridge 171:3a7713b1edbc 14978
AnnaBridge 171:3a7713b1edbc 14979 /*! @name DCCPARAMS - Device Controller Capability Parameters */
AnnaBridge 171:3a7713b1edbc 14980 #define USBHS_DCCPARAMS_DEN_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 14981 #define USBHS_DCCPARAMS_DEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14982 #define USBHS_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DEN_SHIFT)) & USBHS_DCCPARAMS_DEN_MASK)
AnnaBridge 171:3a7713b1edbc 14983 #define USBHS_DCCPARAMS_DC_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 14984 #define USBHS_DCCPARAMS_DC_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 14985 #define USBHS_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DC_SHIFT)) & USBHS_DCCPARAMS_DC_MASK)
AnnaBridge 171:3a7713b1edbc 14986 #define USBHS_DCCPARAMS_HC_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 14987 #define USBHS_DCCPARAMS_HC_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 14988 #define USBHS_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_HC_SHIFT)) & USBHS_DCCPARAMS_HC_MASK)
AnnaBridge 171:3a7713b1edbc 14989
AnnaBridge 171:3a7713b1edbc 14990 /*! @name USBCMD - USB Command Register */
AnnaBridge 171:3a7713b1edbc 14991 #define USBHS_USBCMD_RS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 14992 #define USBHS_USBCMD_RS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 14993 #define USBHS_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RS_SHIFT)) & USBHS_USBCMD_RS_MASK)
AnnaBridge 171:3a7713b1edbc 14994 #define USBHS_USBCMD_RST_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 14995 #define USBHS_USBCMD_RST_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 14996 #define USBHS_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RST_SHIFT)) & USBHS_USBCMD_RST_MASK)
AnnaBridge 171:3a7713b1edbc 14997 #define USBHS_USBCMD_FS_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 14998 #define USBHS_USBCMD_FS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 14999 #define USBHS_USBCMD_FS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_SHIFT)) & USBHS_USBCMD_FS_MASK)
AnnaBridge 171:3a7713b1edbc 15000 #define USBHS_USBCMD_PSE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 15001 #define USBHS_USBCMD_PSE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 15002 #define USBHS_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_PSE_SHIFT)) & USBHS_USBCMD_PSE_MASK)
AnnaBridge 171:3a7713b1edbc 15003 #define USBHS_USBCMD_ASE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 15004 #define USBHS_USBCMD_ASE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 15005 #define USBHS_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASE_SHIFT)) & USBHS_USBCMD_ASE_MASK)
AnnaBridge 171:3a7713b1edbc 15006 #define USBHS_USBCMD_IAA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 15007 #define USBHS_USBCMD_IAA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 15008 #define USBHS_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_IAA_SHIFT)) & USBHS_USBCMD_IAA_MASK)
AnnaBridge 171:3a7713b1edbc 15009 #define USBHS_USBCMD_ASP_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 15010 #define USBHS_USBCMD_ASP_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 15011 #define USBHS_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASP_SHIFT)) & USBHS_USBCMD_ASP_MASK)
AnnaBridge 171:3a7713b1edbc 15012 #define USBHS_USBCMD_ASPE_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 15013 #define USBHS_USBCMD_ASPE_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 15014 #define USBHS_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASPE_SHIFT)) & USBHS_USBCMD_ASPE_MASK)
AnnaBridge 171:3a7713b1edbc 15015 #define USBHS_USBCMD_SUTW_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 15016 #define USBHS_USBCMD_SUTW_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 15017 #define USBHS_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_SUTW_SHIFT)) & USBHS_USBCMD_SUTW_MASK)
AnnaBridge 171:3a7713b1edbc 15018 #define USBHS_USBCMD_ATDTW_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 15019 #define USBHS_USBCMD_ATDTW_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 15020 #define USBHS_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ATDTW_SHIFT)) & USBHS_USBCMD_ATDTW_MASK)
AnnaBridge 171:3a7713b1edbc 15021 #define USBHS_USBCMD_FS2_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 15022 #define USBHS_USBCMD_FS2_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 15023 #define USBHS_USBCMD_FS2(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS2_SHIFT)) & USBHS_USBCMD_FS2_MASK)
AnnaBridge 171:3a7713b1edbc 15024 #define USBHS_USBCMD_ITC_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 15025 #define USBHS_USBCMD_ITC_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15026 #define USBHS_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ITC_SHIFT)) & USBHS_USBCMD_ITC_MASK)
AnnaBridge 171:3a7713b1edbc 15027
AnnaBridge 171:3a7713b1edbc 15028 /*! @name USBSTS - USB Status Register */
AnnaBridge 171:3a7713b1edbc 15029 #define USBHS_USBSTS_UI_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 15030 #define USBHS_USBSTS_UI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15031 #define USBHS_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UI_SHIFT)) & USBHS_USBSTS_UI_MASK)
AnnaBridge 171:3a7713b1edbc 15032 #define USBHS_USBSTS_UEI_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 15033 #define USBHS_USBSTS_UEI_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 15034 #define USBHS_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UEI_SHIFT)) & USBHS_USBSTS_UEI_MASK)
AnnaBridge 171:3a7713b1edbc 15035 #define USBHS_USBSTS_PCI_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 15036 #define USBHS_USBSTS_PCI_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 15037 #define USBHS_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PCI_SHIFT)) & USBHS_USBSTS_PCI_MASK)
AnnaBridge 171:3a7713b1edbc 15038 #define USBHS_USBSTS_FRI_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 15039 #define USBHS_USBSTS_FRI_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 15040 #define USBHS_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_FRI_SHIFT)) & USBHS_USBSTS_FRI_MASK)
AnnaBridge 171:3a7713b1edbc 15041 #define USBHS_USBSTS_SEI_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 15042 #define USBHS_USBSTS_SEI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 15043 #define USBHS_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SEI_SHIFT)) & USBHS_USBSTS_SEI_MASK)
AnnaBridge 171:3a7713b1edbc 15044 #define USBHS_USBSTS_AAI_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 15045 #define USBHS_USBSTS_AAI_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 15046 #define USBHS_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AAI_SHIFT)) & USBHS_USBSTS_AAI_MASK)
AnnaBridge 171:3a7713b1edbc 15047 #define USBHS_USBSTS_URI_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 15048 #define USBHS_USBSTS_URI_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 15049 #define USBHS_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_URI_SHIFT)) & USBHS_USBSTS_URI_MASK)
AnnaBridge 171:3a7713b1edbc 15050 #define USBHS_USBSTS_SRI_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 15051 #define USBHS_USBSTS_SRI_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 15052 #define USBHS_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SRI_SHIFT)) & USBHS_USBSTS_SRI_MASK)
AnnaBridge 171:3a7713b1edbc 15053 #define USBHS_USBSTS_SLI_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 15054 #define USBHS_USBSTS_SLI_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 15055 #define USBHS_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SLI_SHIFT)) & USBHS_USBSTS_SLI_MASK)
AnnaBridge 171:3a7713b1edbc 15056 #define USBHS_USBSTS_HCH_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 15057 #define USBHS_USBSTS_HCH_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 15058 #define USBHS_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_HCH_SHIFT)) & USBHS_USBSTS_HCH_MASK)
AnnaBridge 171:3a7713b1edbc 15059 #define USBHS_USBSTS_RCL_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 15060 #define USBHS_USBSTS_RCL_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 15061 #define USBHS_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_RCL_SHIFT)) & USBHS_USBSTS_RCL_MASK)
AnnaBridge 171:3a7713b1edbc 15062 #define USBHS_USBSTS_PS_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 15063 #define USBHS_USBSTS_PS_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 15064 #define USBHS_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PS_SHIFT)) & USBHS_USBSTS_PS_MASK)
AnnaBridge 171:3a7713b1edbc 15065 #define USBHS_USBSTS_AS_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 15066 #define USBHS_USBSTS_AS_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 15067 #define USBHS_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AS_SHIFT)) & USBHS_USBSTS_AS_MASK)
AnnaBridge 171:3a7713b1edbc 15068 #define USBHS_USBSTS_NAKI_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 15069 #define USBHS_USBSTS_NAKI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15070 #define USBHS_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_NAKI_SHIFT)) & USBHS_USBSTS_NAKI_MASK)
AnnaBridge 171:3a7713b1edbc 15071 #define USBHS_USBSTS_UAI_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 15072 #define USBHS_USBSTS_UAI_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 15073 #define USBHS_USBSTS_UAI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UAI_SHIFT)) & USBHS_USBSTS_UAI_MASK)
AnnaBridge 171:3a7713b1edbc 15074 #define USBHS_USBSTS_UPI_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 15075 #define USBHS_USBSTS_UPI_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 15076 #define USBHS_USBSTS_UPI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UPI_SHIFT)) & USBHS_USBSTS_UPI_MASK)
AnnaBridge 171:3a7713b1edbc 15077 #define USBHS_USBSTS_TI0_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 15078 #define USBHS_USBSTS_TI0_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 15079 #define USBHS_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI0_SHIFT)) & USBHS_USBSTS_TI0_MASK)
AnnaBridge 171:3a7713b1edbc 15080 #define USBHS_USBSTS_TI1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 15081 #define USBHS_USBSTS_TI1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 15082 #define USBHS_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI1_SHIFT)) & USBHS_USBSTS_TI1_MASK)
AnnaBridge 171:3a7713b1edbc 15083
AnnaBridge 171:3a7713b1edbc 15084 /*! @name USBINTR - USB Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 15085 #define USBHS_USBINTR_UE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 15086 #define USBHS_USBINTR_UE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15087 #define USBHS_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UE_SHIFT)) & USBHS_USBINTR_UE_MASK)
AnnaBridge 171:3a7713b1edbc 15088 #define USBHS_USBINTR_UEE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 15089 #define USBHS_USBINTR_UEE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 15090 #define USBHS_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UEE_SHIFT)) & USBHS_USBINTR_UEE_MASK)
AnnaBridge 171:3a7713b1edbc 15091 #define USBHS_USBINTR_PCE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 15092 #define USBHS_USBINTR_PCE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 15093 #define USBHS_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_PCE_SHIFT)) & USBHS_USBINTR_PCE_MASK)
AnnaBridge 171:3a7713b1edbc 15094 #define USBHS_USBINTR_FRE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 15095 #define USBHS_USBINTR_FRE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 15096 #define USBHS_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_FRE_SHIFT)) & USBHS_USBINTR_FRE_MASK)
AnnaBridge 171:3a7713b1edbc 15097 #define USBHS_USBINTR_SEE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 15098 #define USBHS_USBINTR_SEE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 15099 #define USBHS_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SEE_SHIFT)) & USBHS_USBINTR_SEE_MASK)
AnnaBridge 171:3a7713b1edbc 15100 #define USBHS_USBINTR_AAE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 15101 #define USBHS_USBINTR_AAE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 15102 #define USBHS_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_AAE_SHIFT)) & USBHS_USBINTR_AAE_MASK)
AnnaBridge 171:3a7713b1edbc 15103 #define USBHS_USBINTR_URE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 15104 #define USBHS_USBINTR_URE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 15105 #define USBHS_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_URE_SHIFT)) & USBHS_USBINTR_URE_MASK)
AnnaBridge 171:3a7713b1edbc 15106 #define USBHS_USBINTR_SRE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 15107 #define USBHS_USBINTR_SRE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 15108 #define USBHS_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SRE_SHIFT)) & USBHS_USBINTR_SRE_MASK)
AnnaBridge 171:3a7713b1edbc 15109 #define USBHS_USBINTR_SLE_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 15110 #define USBHS_USBINTR_SLE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 15111 #define USBHS_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SLE_SHIFT)) & USBHS_USBINTR_SLE_MASK)
AnnaBridge 171:3a7713b1edbc 15112 #define USBHS_USBINTR_NAKE_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 15113 #define USBHS_USBINTR_NAKE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15114 #define USBHS_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_NAKE_SHIFT)) & USBHS_USBINTR_NAKE_MASK)
AnnaBridge 171:3a7713b1edbc 15115 #define USBHS_USBINTR_UAIE_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 15116 #define USBHS_USBINTR_UAIE_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 15117 #define USBHS_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UAIE_SHIFT)) & USBHS_USBINTR_UAIE_MASK)
AnnaBridge 171:3a7713b1edbc 15118 #define USBHS_USBINTR_UPIE_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 15119 #define USBHS_USBINTR_UPIE_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 15120 #define USBHS_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UPIE_SHIFT)) & USBHS_USBINTR_UPIE_MASK)
AnnaBridge 171:3a7713b1edbc 15121 #define USBHS_USBINTR_TIE0_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 15122 #define USBHS_USBINTR_TIE0_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 15123 #define USBHS_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE0_SHIFT)) & USBHS_USBINTR_TIE0_MASK)
AnnaBridge 171:3a7713b1edbc 15124 #define USBHS_USBINTR_TIE1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 15125 #define USBHS_USBINTR_TIE1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 15126 #define USBHS_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE1_SHIFT)) & USBHS_USBINTR_TIE1_MASK)
AnnaBridge 171:3a7713b1edbc 15127
AnnaBridge 171:3a7713b1edbc 15128 /*! @name FRINDEX - Frame Index Register */
AnnaBridge 171:3a7713b1edbc 15129 #define USBHS_FRINDEX_FRINDEX_MASK (0x3FFFU)
AnnaBridge 171:3a7713b1edbc 15130 #define USBHS_FRINDEX_FRINDEX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15131 #define USBHS_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_FRINDEX_SHIFT)) & USBHS_FRINDEX_FRINDEX_MASK)
AnnaBridge 171:3a7713b1edbc 15132 #define USBHS_FRINDEX_Reerved_MASK (0xFFFFC000U)
AnnaBridge 171:3a7713b1edbc 15133 #define USBHS_FRINDEX_Reerved_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 15134 #define USBHS_FRINDEX_Reerved(x) (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_Reerved_SHIFT)) & USBHS_FRINDEX_Reerved_MASK)
AnnaBridge 171:3a7713b1edbc 15135
AnnaBridge 171:3a7713b1edbc 15136 /*! @name DEVICEADDR - Device Address Register */
AnnaBridge 171:3a7713b1edbc 15137 #define USBHS_DEVICEADDR_USBADRA_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 15138 #define USBHS_DEVICEADDR_USBADRA_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 15139 #define USBHS_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADRA_SHIFT)) & USBHS_DEVICEADDR_USBADRA_MASK)
AnnaBridge 171:3a7713b1edbc 15140 #define USBHS_DEVICEADDR_USBADR_MASK (0xFE000000U)
AnnaBridge 171:3a7713b1edbc 15141 #define USBHS_DEVICEADDR_USBADR_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 15142 #define USBHS_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADR_SHIFT)) & USBHS_DEVICEADDR_USBADR_MASK)
AnnaBridge 171:3a7713b1edbc 15143
AnnaBridge 171:3a7713b1edbc 15144 /*! @name PERIODICLISTBASE - Periodic Frame List Base Address Register */
AnnaBridge 171:3a7713b1edbc 15145 #define USBHS_PERIODICLISTBASE_PERBASE_MASK (0xFFFFF000U)
AnnaBridge 171:3a7713b1edbc 15146 #define USBHS_PERIODICLISTBASE_PERBASE_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 15147 #define USBHS_PERIODICLISTBASE_PERBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PERIODICLISTBASE_PERBASE_SHIFT)) & USBHS_PERIODICLISTBASE_PERBASE_MASK)
AnnaBridge 171:3a7713b1edbc 15148
AnnaBridge 171:3a7713b1edbc 15149 /*! @name ASYNCLISTADDR - Current Asynchronous List Address Register */
AnnaBridge 171:3a7713b1edbc 15150 #define USBHS_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U)
AnnaBridge 171:3a7713b1edbc 15151 #define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 15152 #define USBHS_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ASYNCLISTADDR_ASYBASE_SHIFT)) & USBHS_ASYNCLISTADDR_ASYBASE_MASK)
AnnaBridge 171:3a7713b1edbc 15153
AnnaBridge 171:3a7713b1edbc 15154 /*! @name EPLISTADDR - Endpoint List Address Register */
AnnaBridge 171:3a7713b1edbc 15155 #define USBHS_EPLISTADDR_EPBASE_MASK (0xFFFFF800U)
AnnaBridge 171:3a7713b1edbc 15156 #define USBHS_EPLISTADDR_EPBASE_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 15157 #define USBHS_EPLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPLISTADDR_EPBASE_SHIFT)) & USBHS_EPLISTADDR_EPBASE_MASK)
AnnaBridge 171:3a7713b1edbc 15158
AnnaBridge 171:3a7713b1edbc 15159 /*! @name TTCTRL - Host TT Asynchronous Buffer Control */
AnnaBridge 171:3a7713b1edbc 15160 #define USBHS_TTCTRL_TTHA_MASK (0x7F000000U)
AnnaBridge 171:3a7713b1edbc 15161 #define USBHS_TTCTRL_TTHA_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 15162 #define USBHS_TTCTRL_TTHA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TTCTRL_TTHA_SHIFT)) & USBHS_TTCTRL_TTHA_MASK)
AnnaBridge 171:3a7713b1edbc 15163 #define USBHS_TTCTRL_Reerved_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 15164 #define USBHS_TTCTRL_Reerved_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 15165 #define USBHS_TTCTRL_Reerved(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TTCTRL_Reerved_SHIFT)) & USBHS_TTCTRL_Reerved_MASK)
AnnaBridge 171:3a7713b1edbc 15166
AnnaBridge 171:3a7713b1edbc 15167 /*! @name BURSTSIZE - Master Interface Data Burst Size Register */
AnnaBridge 171:3a7713b1edbc 15168 #define USBHS_BURSTSIZE_RXPBURST_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 15169 #define USBHS_BURSTSIZE_RXPBURST_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15170 #define USBHS_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_RXPBURST_SHIFT)) & USBHS_BURSTSIZE_RXPBURST_MASK)
AnnaBridge 171:3a7713b1edbc 15171 #define USBHS_BURSTSIZE_TXPBURST_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 15172 #define USBHS_BURSTSIZE_TXPBURST_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 15173 #define USBHS_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_TXPBURST_SHIFT)) & USBHS_BURSTSIZE_TXPBURST_MASK)
AnnaBridge 171:3a7713b1edbc 15174
AnnaBridge 171:3a7713b1edbc 15175 /*! @name TXFILLTUNING - Transmit FIFO Tuning Control Register */
AnnaBridge 171:3a7713b1edbc 15176 #define USBHS_TXFILLTUNING_TXSCHOH_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 15177 #define USBHS_TXFILLTUNING_TXSCHOH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15178 #define USBHS_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHOH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHOH_MASK)
AnnaBridge 171:3a7713b1edbc 15179 #define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U)
AnnaBridge 171:3a7713b1edbc 15180 #define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 15181 #define USBHS_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHHEALTH_MASK)
AnnaBridge 171:3a7713b1edbc 15182 #define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U)
AnnaBridge 171:3a7713b1edbc 15183 #define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15184 #define USBHS_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USBHS_TXFILLTUNING_TXFIFOTHRES_MASK)
AnnaBridge 171:3a7713b1edbc 15185
AnnaBridge 171:3a7713b1edbc 15186 /*! @name ENDPTNAK - Endpoint NAK Register */
AnnaBridge 171:3a7713b1edbc 15187 #define USBHS_ENDPTNAK_EPRN_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 15188 #define USBHS_ENDPTNAK_EPRN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15189 #define USBHS_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPRN_SHIFT)) & USBHS_ENDPTNAK_EPRN_MASK)
AnnaBridge 171:3a7713b1edbc 15190 #define USBHS_ENDPTNAK_EPTN_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 15191 #define USBHS_ENDPTNAK_EPTN_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15192 #define USBHS_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPTN_SHIFT)) & USBHS_ENDPTNAK_EPTN_MASK)
AnnaBridge 171:3a7713b1edbc 15193
AnnaBridge 171:3a7713b1edbc 15194 /*! @name ENDPTNAKEN - Endpoint NAK Enable Register */
AnnaBridge 171:3a7713b1edbc 15195 #define USBHS_ENDPTNAKEN_EPRNE_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 15196 #define USBHS_ENDPTNAKEN_EPRNE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15197 #define USBHS_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPRNE_SHIFT)) & USBHS_ENDPTNAKEN_EPRNE_MASK)
AnnaBridge 171:3a7713b1edbc 15198 #define USBHS_ENDPTNAKEN_EPTNE_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 15199 #define USBHS_ENDPTNAKEN_EPTNE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15200 #define USBHS_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPTNE_SHIFT)) & USBHS_ENDPTNAKEN_EPTNE_MASK)
AnnaBridge 171:3a7713b1edbc 15201
AnnaBridge 171:3a7713b1edbc 15202 /*! @name PORTSC1 - Port Status and Control Registers */
AnnaBridge 171:3a7713b1edbc 15203 #define USBHS_PORTSC1_CCS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 15204 #define USBHS_PORTSC1_CCS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15205 #define USBHS_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CCS_SHIFT)) & USBHS_PORTSC1_CCS_MASK)
AnnaBridge 171:3a7713b1edbc 15206 #define USBHS_PORTSC1_CSC_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 15207 #define USBHS_PORTSC1_CSC_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 15208 #define USBHS_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CSC_SHIFT)) & USBHS_PORTSC1_CSC_MASK)
AnnaBridge 171:3a7713b1edbc 15209 #define USBHS_PORTSC1_PE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 15210 #define USBHS_PORTSC1_PE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 15211 #define USBHS_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PE_SHIFT)) & USBHS_PORTSC1_PE_MASK)
AnnaBridge 171:3a7713b1edbc 15212 #define USBHS_PORTSC1_PEC_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 15213 #define USBHS_PORTSC1_PEC_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 15214 #define USBHS_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PEC_SHIFT)) & USBHS_PORTSC1_PEC_MASK)
AnnaBridge 171:3a7713b1edbc 15215 #define USBHS_PORTSC1_OCA_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 15216 #define USBHS_PORTSC1_OCA_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 15217 #define USBHS_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCA_SHIFT)) & USBHS_PORTSC1_OCA_MASK)
AnnaBridge 171:3a7713b1edbc 15218 #define USBHS_PORTSC1_OCC_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 15219 #define USBHS_PORTSC1_OCC_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 15220 #define USBHS_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCC_SHIFT)) & USBHS_PORTSC1_OCC_MASK)
AnnaBridge 171:3a7713b1edbc 15221 #define USBHS_PORTSC1_FPR_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 15222 #define USBHS_PORTSC1_FPR_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 15223 #define USBHS_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_FPR_SHIFT)) & USBHS_PORTSC1_FPR_MASK)
AnnaBridge 171:3a7713b1edbc 15224 #define USBHS_PORTSC1_SUSP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 15225 #define USBHS_PORTSC1_SUSP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 15226 #define USBHS_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_SUSP_SHIFT)) & USBHS_PORTSC1_SUSP_MASK)
AnnaBridge 171:3a7713b1edbc 15227 #define USBHS_PORTSC1_PR_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 15228 #define USBHS_PORTSC1_PR_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 15229 #define USBHS_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PR_SHIFT)) & USBHS_PORTSC1_PR_MASK)
AnnaBridge 171:3a7713b1edbc 15230 #define USBHS_PORTSC1_HSP_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 15231 #define USBHS_PORTSC1_HSP_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 15232 #define USBHS_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_HSP_SHIFT)) & USBHS_PORTSC1_HSP_MASK)
AnnaBridge 171:3a7713b1edbc 15233 #define USBHS_PORTSC1_LS_MASK (0xC00U)
AnnaBridge 171:3a7713b1edbc 15234 #define USBHS_PORTSC1_LS_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 15235 #define USBHS_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_LS_SHIFT)) & USBHS_PORTSC1_LS_MASK)
AnnaBridge 171:3a7713b1edbc 15236 #define USBHS_PORTSC1_PP_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 15237 #define USBHS_PORTSC1_PP_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 15238 #define USBHS_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PP_SHIFT)) & USBHS_PORTSC1_PP_MASK)
AnnaBridge 171:3a7713b1edbc 15239 #define USBHS_PORTSC1_PO_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 15240 #define USBHS_PORTSC1_PO_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 15241 #define USBHS_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PO_SHIFT)) & USBHS_PORTSC1_PO_MASK)
AnnaBridge 171:3a7713b1edbc 15242 #define USBHS_PORTSC1_PIC_MASK (0xC000U)
AnnaBridge 171:3a7713b1edbc 15243 #define USBHS_PORTSC1_PIC_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 15244 #define USBHS_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PIC_SHIFT)) & USBHS_PORTSC1_PIC_MASK)
AnnaBridge 171:3a7713b1edbc 15245 #define USBHS_PORTSC1_PTC_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 15246 #define USBHS_PORTSC1_PTC_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15247 #define USBHS_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTC_SHIFT)) & USBHS_PORTSC1_PTC_MASK)
AnnaBridge 171:3a7713b1edbc 15248 #define USBHS_PORTSC1_WKCN_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 15249 #define USBHS_PORTSC1_WKCN_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 15250 #define USBHS_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKCN_SHIFT)) & USBHS_PORTSC1_WKCN_MASK)
AnnaBridge 171:3a7713b1edbc 15251 #define USBHS_PORTSC1_WKDS_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 15252 #define USBHS_PORTSC1_WKDS_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 15253 #define USBHS_PORTSC1_WKDS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKDS_SHIFT)) & USBHS_PORTSC1_WKDS_MASK)
AnnaBridge 171:3a7713b1edbc 15254 #define USBHS_PORTSC1_WKOC_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 15255 #define USBHS_PORTSC1_WKOC_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 15256 #define USBHS_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKOC_SHIFT)) & USBHS_PORTSC1_WKOC_MASK)
AnnaBridge 171:3a7713b1edbc 15257 #define USBHS_PORTSC1_PHCD_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 15258 #define USBHS_PORTSC1_PHCD_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 15259 #define USBHS_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PHCD_SHIFT)) & USBHS_PORTSC1_PHCD_MASK)
AnnaBridge 171:3a7713b1edbc 15260 #define USBHS_PORTSC1_PFSC_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 15261 #define USBHS_PORTSC1_PFSC_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 15262 #define USBHS_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PFSC_SHIFT)) & USBHS_PORTSC1_PFSC_MASK)
AnnaBridge 171:3a7713b1edbc 15263 #define USBHS_PORTSC1_PTS2_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 15264 #define USBHS_PORTSC1_PTS2_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 15265 #define USBHS_PORTSC1_PTS2(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS2_SHIFT)) & USBHS_PORTSC1_PTS2_MASK)
AnnaBridge 171:3a7713b1edbc 15266 #define USBHS_PORTSC1_PSPD_MASK (0xC000000U)
AnnaBridge 171:3a7713b1edbc 15267 #define USBHS_PORTSC1_PSPD_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 15268 #define USBHS_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PSPD_SHIFT)) & USBHS_PORTSC1_PSPD_MASK)
AnnaBridge 171:3a7713b1edbc 15269 #define USBHS_PORTSC1_PTS_MASK (0xC0000000U)
AnnaBridge 171:3a7713b1edbc 15270 #define USBHS_PORTSC1_PTS_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 15271 #define USBHS_PORTSC1_PTS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_SHIFT)) & USBHS_PORTSC1_PTS_MASK)
AnnaBridge 171:3a7713b1edbc 15272
AnnaBridge 171:3a7713b1edbc 15273 /*! @name OTGSC - On-the-Go Status and Control Register */
AnnaBridge 171:3a7713b1edbc 15274 #define USBHS_OTGSC_VD_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 15275 #define USBHS_OTGSC_VD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15276 #define USBHS_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VD_SHIFT)) & USBHS_OTGSC_VD_MASK)
AnnaBridge 171:3a7713b1edbc 15277 #define USBHS_OTGSC_VC_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 15278 #define USBHS_OTGSC_VC_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 15279 #define USBHS_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VC_SHIFT)) & USBHS_OTGSC_VC_MASK)
AnnaBridge 171:3a7713b1edbc 15280 #define USBHS_OTGSC_HAAR_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 15281 #define USBHS_OTGSC_HAAR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 15282 #define USBHS_OTGSC_HAAR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HAAR_SHIFT)) & USBHS_OTGSC_HAAR_MASK)
AnnaBridge 171:3a7713b1edbc 15283 #define USBHS_OTGSC_OT_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 15284 #define USBHS_OTGSC_OT_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 15285 #define USBHS_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_OT_SHIFT)) & USBHS_OTGSC_OT_MASK)
AnnaBridge 171:3a7713b1edbc 15286 #define USBHS_OTGSC_DP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 15287 #define USBHS_OTGSC_DP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 15288 #define USBHS_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DP_SHIFT)) & USBHS_OTGSC_DP_MASK)
AnnaBridge 171:3a7713b1edbc 15289 #define USBHS_OTGSC_IDPU_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 15290 #define USBHS_OTGSC_IDPU_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 15291 #define USBHS_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDPU_SHIFT)) & USBHS_OTGSC_IDPU_MASK)
AnnaBridge 171:3a7713b1edbc 15292 #define USBHS_OTGSC_HABA_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 15293 #define USBHS_OTGSC_HABA_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 15294 #define USBHS_OTGSC_HABA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HABA_SHIFT)) & USBHS_OTGSC_HABA_MASK)
AnnaBridge 171:3a7713b1edbc 15295 #define USBHS_OTGSC_ID_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 15296 #define USBHS_OTGSC_ID_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 15297 #define USBHS_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ID_SHIFT)) & USBHS_OTGSC_ID_MASK)
AnnaBridge 171:3a7713b1edbc 15298 #define USBHS_OTGSC_AVV_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 15299 #define USBHS_OTGSC_AVV_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 15300 #define USBHS_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVV_SHIFT)) & USBHS_OTGSC_AVV_MASK)
AnnaBridge 171:3a7713b1edbc 15301 #define USBHS_OTGSC_ASV_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 15302 #define USBHS_OTGSC_ASV_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 15303 #define USBHS_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASV_SHIFT)) & USBHS_OTGSC_ASV_MASK)
AnnaBridge 171:3a7713b1edbc 15304 #define USBHS_OTGSC_BSV_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 15305 #define USBHS_OTGSC_BSV_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 15306 #define USBHS_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSV_SHIFT)) & USBHS_OTGSC_BSV_MASK)
AnnaBridge 171:3a7713b1edbc 15307 #define USBHS_OTGSC_BSE_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 15308 #define USBHS_OTGSC_BSE_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 15309 #define USBHS_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSE_SHIFT)) & USBHS_OTGSC_BSE_MASK)
AnnaBridge 171:3a7713b1edbc 15310 #define USBHS_OTGSC_MST_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 15311 #define USBHS_OTGSC_MST_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 15312 #define USBHS_OTGSC_MST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MST_SHIFT)) & USBHS_OTGSC_MST_MASK)
AnnaBridge 171:3a7713b1edbc 15313 #define USBHS_OTGSC_DPS_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 15314 #define USBHS_OTGSC_DPS_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 15315 #define USBHS_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPS_SHIFT)) & USBHS_OTGSC_DPS_MASK)
AnnaBridge 171:3a7713b1edbc 15316 #define USBHS_OTGSC_IDIS_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 15317 #define USBHS_OTGSC_IDIS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15318 #define USBHS_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIS_SHIFT)) & USBHS_OTGSC_IDIS_MASK)
AnnaBridge 171:3a7713b1edbc 15319 #define USBHS_OTGSC_AVVIS_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 15320 #define USBHS_OTGSC_AVVIS_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 15321 #define USBHS_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIS_SHIFT)) & USBHS_OTGSC_AVVIS_MASK)
AnnaBridge 171:3a7713b1edbc 15322 #define USBHS_OTGSC_ASVIS_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 15323 #define USBHS_OTGSC_ASVIS_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 15324 #define USBHS_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIS_SHIFT)) & USBHS_OTGSC_ASVIS_MASK)
AnnaBridge 171:3a7713b1edbc 15325 #define USBHS_OTGSC_BSVIS_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 15326 #define USBHS_OTGSC_BSVIS_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 15327 #define USBHS_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIS_SHIFT)) & USBHS_OTGSC_BSVIS_MASK)
AnnaBridge 171:3a7713b1edbc 15328 #define USBHS_OTGSC_BSEIS_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 15329 #define USBHS_OTGSC_BSEIS_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 15330 #define USBHS_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIS_SHIFT)) & USBHS_OTGSC_BSEIS_MASK)
AnnaBridge 171:3a7713b1edbc 15331 #define USBHS_OTGSC_MSS_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 15332 #define USBHS_OTGSC_MSS_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 15333 #define USBHS_OTGSC_MSS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MSS_SHIFT)) & USBHS_OTGSC_MSS_MASK)
AnnaBridge 171:3a7713b1edbc 15334 #define USBHS_OTGSC_DPIS_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 15335 #define USBHS_OTGSC_DPIS_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 15336 #define USBHS_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIS_SHIFT)) & USBHS_OTGSC_DPIS_MASK)
AnnaBridge 171:3a7713b1edbc 15337 #define USBHS_OTGSC_IDIE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 15338 #define USBHS_OTGSC_IDIE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 15339 #define USBHS_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIE_SHIFT)) & USBHS_OTGSC_IDIE_MASK)
AnnaBridge 171:3a7713b1edbc 15340 #define USBHS_OTGSC_AVVIE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 15341 #define USBHS_OTGSC_AVVIE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 15342 #define USBHS_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIE_SHIFT)) & USBHS_OTGSC_AVVIE_MASK)
AnnaBridge 171:3a7713b1edbc 15343 #define USBHS_OTGSC_ASVIE_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 15344 #define USBHS_OTGSC_ASVIE_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 15345 #define USBHS_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIE_SHIFT)) & USBHS_OTGSC_ASVIE_MASK)
AnnaBridge 171:3a7713b1edbc 15346 #define USBHS_OTGSC_BSVIE_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 15347 #define USBHS_OTGSC_BSVIE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 15348 #define USBHS_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIE_SHIFT)) & USBHS_OTGSC_BSVIE_MASK)
AnnaBridge 171:3a7713b1edbc 15349 #define USBHS_OTGSC_BSEIE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 15350 #define USBHS_OTGSC_BSEIE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 15351 #define USBHS_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIE_SHIFT)) & USBHS_OTGSC_BSEIE_MASK)
AnnaBridge 171:3a7713b1edbc 15352 #define USBHS_OTGSC_MSE_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 15353 #define USBHS_OTGSC_MSE_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 15354 #define USBHS_OTGSC_MSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MSE_SHIFT)) & USBHS_OTGSC_MSE_MASK)
AnnaBridge 171:3a7713b1edbc 15355 #define USBHS_OTGSC_DPIE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 15356 #define USBHS_OTGSC_DPIE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 15357 #define USBHS_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIE_SHIFT)) & USBHS_OTGSC_DPIE_MASK)
AnnaBridge 171:3a7713b1edbc 15358
AnnaBridge 171:3a7713b1edbc 15359 /*! @name USBMODE - USB Mode Register */
AnnaBridge 171:3a7713b1edbc 15360 #define USBHS_USBMODE_CM_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 15361 #define USBHS_USBMODE_CM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15362 #define USBHS_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_CM_SHIFT)) & USBHS_USBMODE_CM_MASK)
AnnaBridge 171:3a7713b1edbc 15363 #define USBHS_USBMODE_ES_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 15364 #define USBHS_USBMODE_ES_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 15365 #define USBHS_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_ES_SHIFT)) & USBHS_USBMODE_ES_MASK)
AnnaBridge 171:3a7713b1edbc 15366 #define USBHS_USBMODE_SLOM_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 15367 #define USBHS_USBMODE_SLOM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 15368 #define USBHS_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SLOM_SHIFT)) & USBHS_USBMODE_SLOM_MASK)
AnnaBridge 171:3a7713b1edbc 15369 #define USBHS_USBMODE_SDIS_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 15370 #define USBHS_USBMODE_SDIS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 15371 #define USBHS_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SDIS_SHIFT)) & USBHS_USBMODE_SDIS_MASK)
AnnaBridge 171:3a7713b1edbc 15372 #define USBHS_USBMODE_TXHSD_MASK (0x7000U)
AnnaBridge 171:3a7713b1edbc 15373 #define USBHS_USBMODE_TXHSD_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 15374 #define USBHS_USBMODE_TXHSD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_TXHSD_SHIFT)) & USBHS_USBMODE_TXHSD_MASK)
AnnaBridge 171:3a7713b1edbc 15375
AnnaBridge 171:3a7713b1edbc 15376 /*! @name EPSETUPSR - Endpoint Setup Status Register */
AnnaBridge 171:3a7713b1edbc 15377 #define USBHS_EPSETUPSR_EPSETUPSTAT_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 15378 #define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15379 #define USBHS_EPSETUPSR_EPSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT)) & USBHS_EPSETUPSR_EPSETUPSTAT_MASK)
AnnaBridge 171:3a7713b1edbc 15380
AnnaBridge 171:3a7713b1edbc 15381 /*! @name EPPRIME - Endpoint Initialization Register */
AnnaBridge 171:3a7713b1edbc 15382 #define USBHS_EPPRIME_PERB_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 15383 #define USBHS_EPPRIME_PERB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15384 #define USBHS_EPPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPPRIME_PERB_SHIFT)) & USBHS_EPPRIME_PERB_MASK)
AnnaBridge 171:3a7713b1edbc 15385 #define USBHS_EPPRIME_PETB_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 15386 #define USBHS_EPPRIME_PETB_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15387 #define USBHS_EPPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPPRIME_PETB_SHIFT)) & USBHS_EPPRIME_PETB_MASK)
AnnaBridge 171:3a7713b1edbc 15388
AnnaBridge 171:3a7713b1edbc 15389 /*! @name EPFLUSH - Endpoint Flush Register */
AnnaBridge 171:3a7713b1edbc 15390 #define USBHS_EPFLUSH_FERB_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 15391 #define USBHS_EPFLUSH_FERB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15392 #define USBHS_EPFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPFLUSH_FERB_SHIFT)) & USBHS_EPFLUSH_FERB_MASK)
AnnaBridge 171:3a7713b1edbc 15393 #define USBHS_EPFLUSH_FETB_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 15394 #define USBHS_EPFLUSH_FETB_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15395 #define USBHS_EPFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPFLUSH_FETB_SHIFT)) & USBHS_EPFLUSH_FETB_MASK)
AnnaBridge 171:3a7713b1edbc 15396
AnnaBridge 171:3a7713b1edbc 15397 /*! @name EPSR - Endpoint Status Register */
AnnaBridge 171:3a7713b1edbc 15398 #define USBHS_EPSR_ERBR_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 15399 #define USBHS_EPSR_ERBR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15400 #define USBHS_EPSR_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPSR_ERBR_SHIFT)) & USBHS_EPSR_ERBR_MASK)
AnnaBridge 171:3a7713b1edbc 15401 #define USBHS_EPSR_ETBR_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 15402 #define USBHS_EPSR_ETBR_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15403 #define USBHS_EPSR_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPSR_ETBR_SHIFT)) & USBHS_EPSR_ETBR_MASK)
AnnaBridge 171:3a7713b1edbc 15404
AnnaBridge 171:3a7713b1edbc 15405 /*! @name EPCOMPLETE - Endpoint Complete Register */
AnnaBridge 171:3a7713b1edbc 15406 #define USBHS_EPCOMPLETE_ERCE_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 15407 #define USBHS_EPCOMPLETE_ERCE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15408 #define USBHS_EPCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCOMPLETE_ERCE_SHIFT)) & USBHS_EPCOMPLETE_ERCE_MASK)
AnnaBridge 171:3a7713b1edbc 15409 #define USBHS_EPCOMPLETE_ETCE_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 15410 #define USBHS_EPCOMPLETE_ETCE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15411 #define USBHS_EPCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCOMPLETE_ETCE_SHIFT)) & USBHS_EPCOMPLETE_ETCE_MASK)
AnnaBridge 171:3a7713b1edbc 15412
AnnaBridge 171:3a7713b1edbc 15413 /*! @name EPCR0 - Endpoint Control Register 0 */
AnnaBridge 171:3a7713b1edbc 15414 #define USBHS_EPCR0_RXS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 15415 #define USBHS_EPCR0_RXS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15416 #define USBHS_EPCR0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXS_SHIFT)) & USBHS_EPCR0_RXS_MASK)
AnnaBridge 171:3a7713b1edbc 15417 #define USBHS_EPCR0_RXT_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 15418 #define USBHS_EPCR0_RXT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 15419 #define USBHS_EPCR0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXT_SHIFT)) & USBHS_EPCR0_RXT_MASK)
AnnaBridge 171:3a7713b1edbc 15420 #define USBHS_EPCR0_RXE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 15421 #define USBHS_EPCR0_RXE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 15422 #define USBHS_EPCR0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXE_SHIFT)) & USBHS_EPCR0_RXE_MASK)
AnnaBridge 171:3a7713b1edbc 15423 #define USBHS_EPCR0_TXS_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 15424 #define USBHS_EPCR0_TXS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15425 #define USBHS_EPCR0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXS_SHIFT)) & USBHS_EPCR0_TXS_MASK)
AnnaBridge 171:3a7713b1edbc 15426 #define USBHS_EPCR0_TXT_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 15427 #define USBHS_EPCR0_TXT_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 15428 #define USBHS_EPCR0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXT_SHIFT)) & USBHS_EPCR0_TXT_MASK)
AnnaBridge 171:3a7713b1edbc 15429 #define USBHS_EPCR0_TXE_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 15430 #define USBHS_EPCR0_TXE_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 15431 #define USBHS_EPCR0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXE_SHIFT)) & USBHS_EPCR0_TXE_MASK)
AnnaBridge 171:3a7713b1edbc 15432
AnnaBridge 171:3a7713b1edbc 15433 /*! @name EPCR - Endpoint Control Register n */
AnnaBridge 171:3a7713b1edbc 15434 #define USBHS_EPCR_RXS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 15435 #define USBHS_EPCR_RXS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15436 #define USBHS_EPCR_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXS_SHIFT)) & USBHS_EPCR_RXS_MASK)
AnnaBridge 171:3a7713b1edbc 15437 #define USBHS_EPCR_RXD_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 15438 #define USBHS_EPCR_RXD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 15439 #define USBHS_EPCR_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXD_SHIFT)) & USBHS_EPCR_RXD_MASK)
AnnaBridge 171:3a7713b1edbc 15440 #define USBHS_EPCR_RXT_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 15441 #define USBHS_EPCR_RXT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 15442 #define USBHS_EPCR_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXT_SHIFT)) & USBHS_EPCR_RXT_MASK)
AnnaBridge 171:3a7713b1edbc 15443 #define USBHS_EPCR_RXI_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 15444 #define USBHS_EPCR_RXI_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 15445 #define USBHS_EPCR_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXI_SHIFT)) & USBHS_EPCR_RXI_MASK)
AnnaBridge 171:3a7713b1edbc 15446 #define USBHS_EPCR_RXR_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 15447 #define USBHS_EPCR_RXR_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 15448 #define USBHS_EPCR_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXR_SHIFT)) & USBHS_EPCR_RXR_MASK)
AnnaBridge 171:3a7713b1edbc 15449 #define USBHS_EPCR_RXE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 15450 #define USBHS_EPCR_RXE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 15451 #define USBHS_EPCR_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXE_SHIFT)) & USBHS_EPCR_RXE_MASK)
AnnaBridge 171:3a7713b1edbc 15452 #define USBHS_EPCR_TXS_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 15453 #define USBHS_EPCR_TXS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15454 #define USBHS_EPCR_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXS_SHIFT)) & USBHS_EPCR_TXS_MASK)
AnnaBridge 171:3a7713b1edbc 15455 #define USBHS_EPCR_TXD_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 15456 #define USBHS_EPCR_TXD_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 15457 #define USBHS_EPCR_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXD_SHIFT)) & USBHS_EPCR_TXD_MASK)
AnnaBridge 171:3a7713b1edbc 15458 #define USBHS_EPCR_TXT_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 15459 #define USBHS_EPCR_TXT_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 15460 #define USBHS_EPCR_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXT_SHIFT)) & USBHS_EPCR_TXT_MASK)
AnnaBridge 171:3a7713b1edbc 15461 #define USBHS_EPCR_TXI_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 15462 #define USBHS_EPCR_TXI_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 15463 #define USBHS_EPCR_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXI_SHIFT)) & USBHS_EPCR_TXI_MASK)
AnnaBridge 171:3a7713b1edbc 15464 #define USBHS_EPCR_TXR_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 15465 #define USBHS_EPCR_TXR_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 15466 #define USBHS_EPCR_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXR_SHIFT)) & USBHS_EPCR_TXR_MASK)
AnnaBridge 171:3a7713b1edbc 15467 #define USBHS_EPCR_TXE_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 15468 #define USBHS_EPCR_TXE_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 15469 #define USBHS_EPCR_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXE_SHIFT)) & USBHS_EPCR_TXE_MASK)
AnnaBridge 171:3a7713b1edbc 15470
AnnaBridge 171:3a7713b1edbc 15471 /* The count of USBHS_EPCR */
AnnaBridge 171:3a7713b1edbc 15472 #define USBHS_EPCR_COUNT (7U)
AnnaBridge 171:3a7713b1edbc 15473
AnnaBridge 171:3a7713b1edbc 15474 /*! @name USBGENCTRL - USB General Control Register */
AnnaBridge 171:3a7713b1edbc 15475 #define USBHS_USBGENCTRL_WU_IE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 15476 #define USBHS_USBGENCTRL_WU_IE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15477 #define USBHS_USBGENCTRL_WU_IE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_IE_SHIFT)) & USBHS_USBGENCTRL_WU_IE_MASK)
AnnaBridge 171:3a7713b1edbc 15478 #define USBHS_USBGENCTRL_WU_INT_CLR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 15479 #define USBHS_USBGENCTRL_WU_INT_CLR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 15480 #define USBHS_USBGENCTRL_WU_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_INT_CLR_SHIFT)) & USBHS_USBGENCTRL_WU_INT_CLR_MASK)
AnnaBridge 171:3a7713b1edbc 15481
AnnaBridge 171:3a7713b1edbc 15482
AnnaBridge 171:3a7713b1edbc 15483 /*!
AnnaBridge 171:3a7713b1edbc 15484 * @}
AnnaBridge 171:3a7713b1edbc 15485 */ /* end of group USBHS_Register_Masks */
AnnaBridge 171:3a7713b1edbc 15486
AnnaBridge 171:3a7713b1edbc 15487
AnnaBridge 171:3a7713b1edbc 15488 /* USBHS - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 15489 /** Peripheral USBHS base address */
AnnaBridge 171:3a7713b1edbc 15490 #define USBHS_BASE (0x400A1000u)
AnnaBridge 171:3a7713b1edbc 15491 /** Peripheral USBHS base pointer */
AnnaBridge 171:3a7713b1edbc 15492 #define USBHS ((USBHS_Type *)USBHS_BASE)
AnnaBridge 171:3a7713b1edbc 15493 /** Array initializer of USBHS peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 15494 #define USBHS_BASE_ADDRS { USBHS_BASE }
AnnaBridge 171:3a7713b1edbc 15495 /** Array initializer of USBHS peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 15496 #define USBHS_BASE_PTRS { USBHS }
AnnaBridge 171:3a7713b1edbc 15497 /** Interrupt vectors for the USBHS peripheral type */
AnnaBridge 171:3a7713b1edbc 15498 #define USBHS_IRQS { USBHS_IRQn }
AnnaBridge 171:3a7713b1edbc 15499
AnnaBridge 171:3a7713b1edbc 15500 /*!
AnnaBridge 171:3a7713b1edbc 15501 * @}
AnnaBridge 171:3a7713b1edbc 15502 */ /* end of group USBHS_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 15503
AnnaBridge 171:3a7713b1edbc 15504
AnnaBridge 171:3a7713b1edbc 15505 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 15506 -- USBHSDCD Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 15507 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 15508
AnnaBridge 171:3a7713b1edbc 15509 /*!
AnnaBridge 171:3a7713b1edbc 15510 * @addtogroup USBHSDCD_Peripheral_Access_Layer USBHSDCD Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 15511 * @{
AnnaBridge 171:3a7713b1edbc 15512 */
AnnaBridge 171:3a7713b1edbc 15513
AnnaBridge 171:3a7713b1edbc 15514 /** USBHSDCD - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 15515 typedef struct {
AnnaBridge 171:3a7713b1edbc 15516 __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 15517 __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 15518 __I uint32_t STATUS; /**< Status register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 15519 __IO uint32_t SIGNAL_OVERRIDE; /**< Signal Override Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 15520 __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 15521 __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 15522 union { /* offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 15523 __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 15524 __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 15525 };
AnnaBridge 171:3a7713b1edbc 15526 } USBHSDCD_Type;
AnnaBridge 171:3a7713b1edbc 15527
AnnaBridge 171:3a7713b1edbc 15528 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 15529 -- USBHSDCD Register Masks
AnnaBridge 171:3a7713b1edbc 15530 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 15531
AnnaBridge 171:3a7713b1edbc 15532 /*!
AnnaBridge 171:3a7713b1edbc 15533 * @addtogroup USBHSDCD_Register_Masks USBHSDCD Register Masks
AnnaBridge 171:3a7713b1edbc 15534 * @{
AnnaBridge 171:3a7713b1edbc 15535 */
AnnaBridge 171:3a7713b1edbc 15536
AnnaBridge 171:3a7713b1edbc 15537 /*! @name CONTROL - Control register */
AnnaBridge 171:3a7713b1edbc 15538 #define USBHSDCD_CONTROL_IACK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 15539 #define USBHSDCD_CONTROL_IACK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15540 #define USBHSDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)
AnnaBridge 171:3a7713b1edbc 15541 #define USBHSDCD_CONTROL_IF_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 15542 #define USBHSDCD_CONTROL_IF_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 15543 #define USBHSDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)
AnnaBridge 171:3a7713b1edbc 15544 #define USBHSDCD_CONTROL_IE_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 15545 #define USBHSDCD_CONTROL_IE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15546 #define USBHSDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)
AnnaBridge 171:3a7713b1edbc 15547 #define USBHSDCD_CONTROL_BC12_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 15548 #define USBHSDCD_CONTROL_BC12_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 15549 #define USBHSDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)
AnnaBridge 171:3a7713b1edbc 15550 #define USBHSDCD_CONTROL_START_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 15551 #define USBHSDCD_CONTROL_START_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 15552 #define USBHSDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)
AnnaBridge 171:3a7713b1edbc 15553 #define USBHSDCD_CONTROL_SR_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 15554 #define USBHSDCD_CONTROL_SR_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 15555 #define USBHSDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)
AnnaBridge 171:3a7713b1edbc 15556
AnnaBridge 171:3a7713b1edbc 15557 /*! @name CLOCK - Clock register */
AnnaBridge 171:3a7713b1edbc 15558 #define USBHSDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 15559 #define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15560 #define USBHSDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)
AnnaBridge 171:3a7713b1edbc 15561 #define USBHSDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
AnnaBridge 171:3a7713b1edbc 15562 #define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 15563 #define USBHSDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)
AnnaBridge 171:3a7713b1edbc 15564
AnnaBridge 171:3a7713b1edbc 15565 /*! @name STATUS - Status register */
AnnaBridge 171:3a7713b1edbc 15566 #define USBHSDCD_STATUS_SEQ_RES_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 15567 #define USBHSDCD_STATUS_SEQ_RES_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15568 #define USBHSDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)
AnnaBridge 171:3a7713b1edbc 15569 #define USBHSDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 15570 #define USBHSDCD_STATUS_SEQ_STAT_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 15571 #define USBHSDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)
AnnaBridge 171:3a7713b1edbc 15572 #define USBHSDCD_STATUS_ERR_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 15573 #define USBHSDCD_STATUS_ERR_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 15574 #define USBHSDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)
AnnaBridge 171:3a7713b1edbc 15575 #define USBHSDCD_STATUS_TO_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 15576 #define USBHSDCD_STATUS_TO_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 15577 #define USBHSDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)
AnnaBridge 171:3a7713b1edbc 15578 #define USBHSDCD_STATUS_ACTIVE_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 15579 #define USBHSDCD_STATUS_ACTIVE_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 15580 #define USBHSDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)
AnnaBridge 171:3a7713b1edbc 15581
AnnaBridge 171:3a7713b1edbc 15582 /*! @name SIGNAL_OVERRIDE - Signal Override Register */
AnnaBridge 171:3a7713b1edbc 15583 #define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 15584 #define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15585 #define USBHSDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)
AnnaBridge 171:3a7713b1edbc 15586
AnnaBridge 171:3a7713b1edbc 15587 /*! @name TIMER0 - TIMER0 register */
AnnaBridge 171:3a7713b1edbc 15588 #define USBHSDCD_TIMER0_TUNITCON_MASK (0xFFFU)
AnnaBridge 171:3a7713b1edbc 15589 #define USBHSDCD_TIMER0_TUNITCON_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15590 #define USBHSDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)
AnnaBridge 171:3a7713b1edbc 15591 #define USBHSDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 15592 #define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15593 #define USBHSDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)
AnnaBridge 171:3a7713b1edbc 15594
AnnaBridge 171:3a7713b1edbc 15595 /*! @name TIMER1 - TIMER1 register */
AnnaBridge 171:3a7713b1edbc 15596 #define USBHSDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 15597 #define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15598 #define USBHSDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)
AnnaBridge 171:3a7713b1edbc 15599 #define USBHSDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 15600 #define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15601 #define USBHSDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)
AnnaBridge 171:3a7713b1edbc 15602
AnnaBridge 171:3a7713b1edbc 15603 /*! @name TIMER2_BC11 - TIMER2_BC11 register */
AnnaBridge 171:3a7713b1edbc 15604 #define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 15605 #define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15606 #define USBHSDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)
AnnaBridge 171:3a7713b1edbc 15607 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 15608 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15609 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
AnnaBridge 171:3a7713b1edbc 15610
AnnaBridge 171:3a7713b1edbc 15611 /*! @name TIMER2_BC12 - TIMER2_BC12 register */
AnnaBridge 171:3a7713b1edbc 15612 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 15613 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15614 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
AnnaBridge 171:3a7713b1edbc 15615 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 15616 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15617 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
AnnaBridge 171:3a7713b1edbc 15618
AnnaBridge 171:3a7713b1edbc 15619
AnnaBridge 171:3a7713b1edbc 15620 /*!
AnnaBridge 171:3a7713b1edbc 15621 * @}
AnnaBridge 171:3a7713b1edbc 15622 */ /* end of group USBHSDCD_Register_Masks */
AnnaBridge 171:3a7713b1edbc 15623
AnnaBridge 171:3a7713b1edbc 15624
AnnaBridge 171:3a7713b1edbc 15625 /* USBHSDCD - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 15626 /** Peripheral USBHSDCD base address */
AnnaBridge 171:3a7713b1edbc 15627 #define USBHSDCD_BASE (0x400A3000u)
AnnaBridge 171:3a7713b1edbc 15628 /** Peripheral USBHSDCD base pointer */
AnnaBridge 171:3a7713b1edbc 15629 #define USBHSDCD ((USBHSDCD_Type *)USBHSDCD_BASE)
AnnaBridge 171:3a7713b1edbc 15630 /** Array initializer of USBHSDCD peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 15631 #define USBHSDCD_BASE_ADDRS { USBHSDCD_BASE }
AnnaBridge 171:3a7713b1edbc 15632 /** Array initializer of USBHSDCD peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 15633 #define USBHSDCD_BASE_PTRS { USBHSDCD }
AnnaBridge 171:3a7713b1edbc 15634 /** Interrupt vectors for the USBHSDCD peripheral type */
AnnaBridge 171:3a7713b1edbc 15635 #define USBHSDCD_IRQS { USBHSDCD_IRQn }
AnnaBridge 171:3a7713b1edbc 15636
AnnaBridge 171:3a7713b1edbc 15637 /*!
AnnaBridge 171:3a7713b1edbc 15638 * @}
AnnaBridge 171:3a7713b1edbc 15639 */ /* end of group USBHSDCD_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 15640
AnnaBridge 171:3a7713b1edbc 15641
AnnaBridge 171:3a7713b1edbc 15642 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 15643 -- USBPHY Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 15644 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 15645
AnnaBridge 171:3a7713b1edbc 15646 /*!
AnnaBridge 171:3a7713b1edbc 15647 * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 15648 * @{
AnnaBridge 171:3a7713b1edbc 15649 */
AnnaBridge 171:3a7713b1edbc 15650
AnnaBridge 171:3a7713b1edbc 15651 /** USBPHY - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 15652 typedef struct {
AnnaBridge 171:3a7713b1edbc 15653 __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 15654 __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 15655 __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 15656 __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 15657 __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 15658 __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 15659 __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 15660 __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 15661 __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 15662 __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 15663 __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 15664 __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 15665 __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 15666 __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 15667 __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 15668 __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 15669 __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 15670 uint8_t RESERVED_0[12];
AnnaBridge 171:3a7713b1edbc 15671 __IO uint32_t DEBUGr; /**< USB PHY Debug Register, offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 15672 __IO uint32_t DEBUG_SET; /**< USB PHY Debug Register, offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 15673 __IO uint32_t DEBUG_CLR; /**< USB PHY Debug Register, offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 15674 __IO uint32_t DEBUG_TOG; /**< USB PHY Debug Register, offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 15675 __I uint32_t DEBUG0_STATUS; /**< UTMI Debug Status Register 0, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 15676 uint8_t RESERVED_1[12];
AnnaBridge 171:3a7713b1edbc 15677 __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */
AnnaBridge 171:3a7713b1edbc 15678 __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */
AnnaBridge 171:3a7713b1edbc 15679 __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */
AnnaBridge 171:3a7713b1edbc 15680 __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */
AnnaBridge 171:3a7713b1edbc 15681 __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 15682 uint8_t RESERVED_2[28];
AnnaBridge 171:3a7713b1edbc 15683 __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */
AnnaBridge 171:3a7713b1edbc 15684 __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */
AnnaBridge 171:3a7713b1edbc 15685 __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */
AnnaBridge 171:3a7713b1edbc 15686 __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */
AnnaBridge 171:3a7713b1edbc 15687 uint8_t RESERVED_3[16];
AnnaBridge 171:3a7713b1edbc 15688 __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */
AnnaBridge 171:3a7713b1edbc 15689 __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */
AnnaBridge 171:3a7713b1edbc 15690 __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */
AnnaBridge 171:3a7713b1edbc 15691 __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */
AnnaBridge 171:3a7713b1edbc 15692 __I uint32_t USB1_VBUS_DET_STAT; /**< USB PHY VBUS Detector Status Register, offset: 0xD0 */
AnnaBridge 171:3a7713b1edbc 15693 uint8_t RESERVED_4[28];
AnnaBridge 171:3a7713b1edbc 15694 __I uint32_t USB1_CHRG_DET_STAT; /**< USB PHY Charger Detect Status Register, offset: 0xF0 */
AnnaBridge 171:3a7713b1edbc 15695 uint8_t RESERVED_5[12];
AnnaBridge 171:3a7713b1edbc 15696 __IO uint32_t ANACTRL; /**< USB PHY Analog Control Register, offset: 0x100 */
AnnaBridge 171:3a7713b1edbc 15697 __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */
AnnaBridge 171:3a7713b1edbc 15698 __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */
AnnaBridge 171:3a7713b1edbc 15699 __IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */
AnnaBridge 171:3a7713b1edbc 15700 __IO uint32_t USB1_LOOPBACK; /**< USB PHY Loopback Control/Status Register, offset: 0x110 */
AnnaBridge 171:3a7713b1edbc 15701 __IO uint32_t USB1_LOOPBACK_SET; /**< USB PHY Loopback Control/Status Register, offset: 0x114 */
AnnaBridge 171:3a7713b1edbc 15702 __IO uint32_t USB1_LOOPBACK_CLR; /**< USB PHY Loopback Control/Status Register, offset: 0x118 */
AnnaBridge 171:3a7713b1edbc 15703 __IO uint32_t USB1_LOOPBACK_TOG; /**< USB PHY Loopback Control/Status Register, offset: 0x11C */
AnnaBridge 171:3a7713b1edbc 15704 __IO uint32_t USB1_LOOPBACK_HSFSCNT; /**< USB PHY Loopback Packet Number Select Register, offset: 0x120 */
AnnaBridge 171:3a7713b1edbc 15705 __IO uint32_t USB1_LOOPBACK_HSFSCNT_SET; /**< USB PHY Loopback Packet Number Select Register, offset: 0x124 */
AnnaBridge 171:3a7713b1edbc 15706 __IO uint32_t USB1_LOOPBACK_HSFSCNT_CLR; /**< USB PHY Loopback Packet Number Select Register, offset: 0x128 */
AnnaBridge 171:3a7713b1edbc 15707 __IO uint32_t USB1_LOOPBACK_HSFSCNT_TOG; /**< USB PHY Loopback Packet Number Select Register, offset: 0x12C */
AnnaBridge 171:3a7713b1edbc 15708 __IO uint32_t TRIM_OVERRIDE_EN; /**< USB PHY Trim Override Enable Register, offset: 0x130 */
AnnaBridge 171:3a7713b1edbc 15709 __IO uint32_t TRIM_OVERRIDE_EN_SET; /**< USB PHY Trim Override Enable Register, offset: 0x134 */
AnnaBridge 171:3a7713b1edbc 15710 __IO uint32_t TRIM_OVERRIDE_EN_CLR; /**< USB PHY Trim Override Enable Register, offset: 0x138 */
AnnaBridge 171:3a7713b1edbc 15711 __IO uint32_t TRIM_OVERRIDE_EN_TOG; /**< USB PHY Trim Override Enable Register, offset: 0x13C */
AnnaBridge 171:3a7713b1edbc 15712 } USBPHY_Type;
AnnaBridge 171:3a7713b1edbc 15713
AnnaBridge 171:3a7713b1edbc 15714 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 15715 -- USBPHY Register Masks
AnnaBridge 171:3a7713b1edbc 15716 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 15717
AnnaBridge 171:3a7713b1edbc 15718 /*!
AnnaBridge 171:3a7713b1edbc 15719 * @addtogroup USBPHY_Register_Masks USBPHY Register Masks
AnnaBridge 171:3a7713b1edbc 15720 * @{
AnnaBridge 171:3a7713b1edbc 15721 */
AnnaBridge 171:3a7713b1edbc 15722
AnnaBridge 171:3a7713b1edbc 15723 /*! @name PWD - USB PHY Power-Down Register */
AnnaBridge 171:3a7713b1edbc 15724 #define USBPHY_PWD_TXPWDFS_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 15725 #define USBPHY_PWD_TXPWDFS_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 15726 #define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
AnnaBridge 171:3a7713b1edbc 15727 #define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 15728 #define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 15729 #define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
AnnaBridge 171:3a7713b1edbc 15730 #define USBPHY_PWD_TXPWDV2I_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 15731 #define USBPHY_PWD_TXPWDV2I_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 15732 #define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
AnnaBridge 171:3a7713b1edbc 15733 #define USBPHY_PWD_RXPWDENV_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 15734 #define USBPHY_PWD_RXPWDENV_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 15735 #define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
AnnaBridge 171:3a7713b1edbc 15736 #define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 15737 #define USBPHY_PWD_RXPWD1PT1_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 15738 #define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
AnnaBridge 171:3a7713b1edbc 15739 #define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 15740 #define USBPHY_PWD_RXPWDDIFF_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 15741 #define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
AnnaBridge 171:3a7713b1edbc 15742 #define USBPHY_PWD_RXPWDRX_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 15743 #define USBPHY_PWD_RXPWDRX_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 15744 #define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
AnnaBridge 171:3a7713b1edbc 15745
AnnaBridge 171:3a7713b1edbc 15746 /*! @name PWD_SET - USB PHY Power-Down Register */
AnnaBridge 171:3a7713b1edbc 15747 #define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 15748 #define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 15749 #define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
AnnaBridge 171:3a7713b1edbc 15750 #define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 15751 #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 15752 #define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
AnnaBridge 171:3a7713b1edbc 15753 #define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 15754 #define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 15755 #define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
AnnaBridge 171:3a7713b1edbc 15756 #define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 15757 #define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 15758 #define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
AnnaBridge 171:3a7713b1edbc 15759 #define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 15760 #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 15761 #define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
AnnaBridge 171:3a7713b1edbc 15762 #define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 15763 #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 15764 #define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
AnnaBridge 171:3a7713b1edbc 15765 #define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 15766 #define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 15767 #define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
AnnaBridge 171:3a7713b1edbc 15768
AnnaBridge 171:3a7713b1edbc 15769 /*! @name PWD_CLR - USB PHY Power-Down Register */
AnnaBridge 171:3a7713b1edbc 15770 #define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 15771 #define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 15772 #define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
AnnaBridge 171:3a7713b1edbc 15773 #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 15774 #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 15775 #define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
AnnaBridge 171:3a7713b1edbc 15776 #define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 15777 #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 15778 #define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
AnnaBridge 171:3a7713b1edbc 15779 #define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 15780 #define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 15781 #define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
AnnaBridge 171:3a7713b1edbc 15782 #define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 15783 #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 15784 #define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
AnnaBridge 171:3a7713b1edbc 15785 #define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 15786 #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 15787 #define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
AnnaBridge 171:3a7713b1edbc 15788 #define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 15789 #define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 15790 #define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
AnnaBridge 171:3a7713b1edbc 15791
AnnaBridge 171:3a7713b1edbc 15792 /*! @name PWD_TOG - USB PHY Power-Down Register */
AnnaBridge 171:3a7713b1edbc 15793 #define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 15794 #define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 15795 #define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
AnnaBridge 171:3a7713b1edbc 15796 #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 15797 #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 15798 #define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
AnnaBridge 171:3a7713b1edbc 15799 #define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 15800 #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 15801 #define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
AnnaBridge 171:3a7713b1edbc 15802 #define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 15803 #define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 15804 #define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
AnnaBridge 171:3a7713b1edbc 15805 #define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 15806 #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 15807 #define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
AnnaBridge 171:3a7713b1edbc 15808 #define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 15809 #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 15810 #define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
AnnaBridge 171:3a7713b1edbc 15811 #define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 15812 #define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 15813 #define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
AnnaBridge 171:3a7713b1edbc 15814
AnnaBridge 171:3a7713b1edbc 15815 /*! @name TX - USB PHY Transmitter Control Register */
AnnaBridge 171:3a7713b1edbc 15816 #define USBPHY_TX_D_CAL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 15817 #define USBPHY_TX_D_CAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15818 #define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
AnnaBridge 171:3a7713b1edbc 15819 #define USBPHY_TX_TXCAL45DM_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 15820 #define USBPHY_TX_TXCAL45DM_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 15821 #define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK)
AnnaBridge 171:3a7713b1edbc 15822 #define USBPHY_TX_TXCAL45DP_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 15823 #define USBPHY_TX_TXCAL45DP_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15824 #define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
AnnaBridge 171:3a7713b1edbc 15825 #define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
AnnaBridge 171:3a7713b1edbc 15826 #define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 15827 #define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)
AnnaBridge 171:3a7713b1edbc 15828
AnnaBridge 171:3a7713b1edbc 15829 /*! @name TX_SET - USB PHY Transmitter Control Register */
AnnaBridge 171:3a7713b1edbc 15830 #define USBPHY_TX_SET_D_CAL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 15831 #define USBPHY_TX_SET_D_CAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15832 #define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
AnnaBridge 171:3a7713b1edbc 15833 #define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 15834 #define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 15835 #define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK)
AnnaBridge 171:3a7713b1edbc 15836 #define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 15837 #define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15838 #define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
AnnaBridge 171:3a7713b1edbc 15839 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
AnnaBridge 171:3a7713b1edbc 15840 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 15841 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)
AnnaBridge 171:3a7713b1edbc 15842
AnnaBridge 171:3a7713b1edbc 15843 /*! @name TX_CLR - USB PHY Transmitter Control Register */
AnnaBridge 171:3a7713b1edbc 15844 #define USBPHY_TX_CLR_D_CAL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 15845 #define USBPHY_TX_CLR_D_CAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15846 #define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
AnnaBridge 171:3a7713b1edbc 15847 #define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 15848 #define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 15849 #define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK)
AnnaBridge 171:3a7713b1edbc 15850 #define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 15851 #define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15852 #define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
AnnaBridge 171:3a7713b1edbc 15853 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
AnnaBridge 171:3a7713b1edbc 15854 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 15855 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)
AnnaBridge 171:3a7713b1edbc 15856
AnnaBridge 171:3a7713b1edbc 15857 /*! @name TX_TOG - USB PHY Transmitter Control Register */
AnnaBridge 171:3a7713b1edbc 15858 #define USBPHY_TX_TOG_D_CAL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 15859 #define USBPHY_TX_TOG_D_CAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15860 #define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
AnnaBridge 171:3a7713b1edbc 15861 #define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 15862 #define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 15863 #define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK)
AnnaBridge 171:3a7713b1edbc 15864 #define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 15865 #define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 15866 #define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
AnnaBridge 171:3a7713b1edbc 15867 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
AnnaBridge 171:3a7713b1edbc 15868 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 15869 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)
AnnaBridge 171:3a7713b1edbc 15870
AnnaBridge 171:3a7713b1edbc 15871 /*! @name RX - USB PHY Receiver Control Register */
AnnaBridge 171:3a7713b1edbc 15872 #define USBPHY_RX_ENVADJ_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 15873 #define USBPHY_RX_ENVADJ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15874 #define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
AnnaBridge 171:3a7713b1edbc 15875 #define USBPHY_RX_DISCONADJ_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 15876 #define USBPHY_RX_DISCONADJ_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 15877 #define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
AnnaBridge 171:3a7713b1edbc 15878 #define USBPHY_RX_RXDBYPASS_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 15879 #define USBPHY_RX_RXDBYPASS_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 15880 #define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
AnnaBridge 171:3a7713b1edbc 15881
AnnaBridge 171:3a7713b1edbc 15882 /*! @name RX_SET - USB PHY Receiver Control Register */
AnnaBridge 171:3a7713b1edbc 15883 #define USBPHY_RX_SET_ENVADJ_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 15884 #define USBPHY_RX_SET_ENVADJ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15885 #define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
AnnaBridge 171:3a7713b1edbc 15886 #define USBPHY_RX_SET_DISCONADJ_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 15887 #define USBPHY_RX_SET_DISCONADJ_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 15888 #define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
AnnaBridge 171:3a7713b1edbc 15889 #define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 15890 #define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 15891 #define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
AnnaBridge 171:3a7713b1edbc 15892
AnnaBridge 171:3a7713b1edbc 15893 /*! @name RX_CLR - USB PHY Receiver Control Register */
AnnaBridge 171:3a7713b1edbc 15894 #define USBPHY_RX_CLR_ENVADJ_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 15895 #define USBPHY_RX_CLR_ENVADJ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15896 #define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
AnnaBridge 171:3a7713b1edbc 15897 #define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 15898 #define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 15899 #define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
AnnaBridge 171:3a7713b1edbc 15900 #define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 15901 #define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 15902 #define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
AnnaBridge 171:3a7713b1edbc 15903
AnnaBridge 171:3a7713b1edbc 15904 /*! @name RX_TOG - USB PHY Receiver Control Register */
AnnaBridge 171:3a7713b1edbc 15905 #define USBPHY_RX_TOG_ENVADJ_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 15906 #define USBPHY_RX_TOG_ENVADJ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 15907 #define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
AnnaBridge 171:3a7713b1edbc 15908 #define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 15909 #define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 15910 #define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
AnnaBridge 171:3a7713b1edbc 15911 #define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 15912 #define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 15913 #define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
AnnaBridge 171:3a7713b1edbc 15914
AnnaBridge 171:3a7713b1edbc 15915 /*! @name CTRL - USB PHY General Control Register */
AnnaBridge 171:3a7713b1edbc 15916 #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 15917 #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 15918 #define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
AnnaBridge 171:3a7713b1edbc 15919 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 15920 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 15921 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 15922 #define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 15923 #define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 15924 #define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK)
AnnaBridge 171:3a7713b1edbc 15925 #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 15926 #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 15927 #define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 15928 #define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 15929 #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 15930 #define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
AnnaBridge 171:3a7713b1edbc 15931 #define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 15932 #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 15933 #define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
AnnaBridge 171:3a7713b1edbc 15934 #define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 15935 #define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 15936 #define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK)
AnnaBridge 171:3a7713b1edbc 15937 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 15938 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 15939 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
AnnaBridge 171:3a7713b1edbc 15940 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 15941 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 15942 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
AnnaBridge 171:3a7713b1edbc 15943 #define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 15944 #define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 15945 #define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
AnnaBridge 171:3a7713b1edbc 15946 #define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 15947 #define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 15948 #define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
AnnaBridge 171:3a7713b1edbc 15949 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 15950 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 15951 #define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
AnnaBridge 171:3a7713b1edbc 15952 #define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 15953 #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 15954 #define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
AnnaBridge 171:3a7713b1edbc 15955 #define USBPHY_CTRL_CLKGATE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 15956 #define USBPHY_CTRL_CLKGATE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 15957 #define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
AnnaBridge 171:3a7713b1edbc 15958 #define USBPHY_CTRL_SFTRST_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 15959 #define USBPHY_CTRL_SFTRST_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 15960 #define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
AnnaBridge 171:3a7713b1edbc 15961
AnnaBridge 171:3a7713b1edbc 15962 /*! @name CTRL_SET - USB PHY General Control Register */
AnnaBridge 171:3a7713b1edbc 15963 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 15964 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 15965 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
AnnaBridge 171:3a7713b1edbc 15966 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 15967 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 15968 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 15969 #define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 15970 #define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 15971 #define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK)
AnnaBridge 171:3a7713b1edbc 15972 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 15973 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 15974 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 15975 #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 15976 #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 15977 #define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
AnnaBridge 171:3a7713b1edbc 15978 #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 15979 #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 15980 #define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
AnnaBridge 171:3a7713b1edbc 15981 #define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 15982 #define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 15983 #define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK)
AnnaBridge 171:3a7713b1edbc 15984 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 15985 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 15986 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
AnnaBridge 171:3a7713b1edbc 15987 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 15988 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 15989 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
AnnaBridge 171:3a7713b1edbc 15990 #define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 15991 #define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 15992 #define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
AnnaBridge 171:3a7713b1edbc 15993 #define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 15994 #define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 15995 #define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
AnnaBridge 171:3a7713b1edbc 15996 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 15997 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 15998 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
AnnaBridge 171:3a7713b1edbc 15999 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 16000 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 16001 #define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
AnnaBridge 171:3a7713b1edbc 16002 #define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 16003 #define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 16004 #define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
AnnaBridge 171:3a7713b1edbc 16005 #define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 16006 #define USBPHY_CTRL_SET_SFTRST_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 16007 #define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
AnnaBridge 171:3a7713b1edbc 16008
AnnaBridge 171:3a7713b1edbc 16009 /*! @name CTRL_CLR - USB PHY General Control Register */
AnnaBridge 171:3a7713b1edbc 16010 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 16011 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 16012 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
AnnaBridge 171:3a7713b1edbc 16013 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 16014 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 16015 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 16016 #define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 16017 #define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16018 #define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK)
AnnaBridge 171:3a7713b1edbc 16019 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 16020 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 16021 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 16022 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 16023 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 16024 #define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
AnnaBridge 171:3a7713b1edbc 16025 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 16026 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 16027 #define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
AnnaBridge 171:3a7713b1edbc 16028 #define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 16029 #define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 16030 #define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK)
AnnaBridge 171:3a7713b1edbc 16031 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 16032 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 16033 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
AnnaBridge 171:3a7713b1edbc 16034 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 16035 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 16036 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
AnnaBridge 171:3a7713b1edbc 16037 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 16038 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 16039 #define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
AnnaBridge 171:3a7713b1edbc 16040 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 16041 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 16042 #define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
AnnaBridge 171:3a7713b1edbc 16043 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 16044 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 16045 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
AnnaBridge 171:3a7713b1edbc 16046 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 16047 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 16048 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
AnnaBridge 171:3a7713b1edbc 16049 #define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 16050 #define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 16051 #define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
AnnaBridge 171:3a7713b1edbc 16052 #define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 16053 #define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 16054 #define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
AnnaBridge 171:3a7713b1edbc 16055
AnnaBridge 171:3a7713b1edbc 16056 /*! @name CTRL_TOG - USB PHY General Control Register */
AnnaBridge 171:3a7713b1edbc 16057 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 16058 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 16059 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
AnnaBridge 171:3a7713b1edbc 16060 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 16061 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 16062 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 16063 #define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 16064 #define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16065 #define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK)
AnnaBridge 171:3a7713b1edbc 16066 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 16067 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 16068 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 16069 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 16070 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 16071 #define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
AnnaBridge 171:3a7713b1edbc 16072 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 16073 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 16074 #define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
AnnaBridge 171:3a7713b1edbc 16075 #define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 16076 #define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 16077 #define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK)
AnnaBridge 171:3a7713b1edbc 16078 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 16079 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 16080 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
AnnaBridge 171:3a7713b1edbc 16081 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 16082 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 16083 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
AnnaBridge 171:3a7713b1edbc 16084 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 16085 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 16086 #define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
AnnaBridge 171:3a7713b1edbc 16087 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 16088 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 16089 #define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
AnnaBridge 171:3a7713b1edbc 16090 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 16091 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 16092 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
AnnaBridge 171:3a7713b1edbc 16093 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 16094 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 16095 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
AnnaBridge 171:3a7713b1edbc 16096 #define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 16097 #define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 16098 #define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
AnnaBridge 171:3a7713b1edbc 16099 #define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 16100 #define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 16101 #define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
AnnaBridge 171:3a7713b1edbc 16102
AnnaBridge 171:3a7713b1edbc 16103 /*! @name STATUS - USB PHY Status Register */
AnnaBridge 171:3a7713b1edbc 16104 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 16105 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 16106 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
AnnaBridge 171:3a7713b1edbc 16107 #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 16108 #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 16109 #define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
AnnaBridge 171:3a7713b1edbc 16110 #define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 16111 #define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 16112 #define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
AnnaBridge 171:3a7713b1edbc 16113 #define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 16114 #define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 16115 #define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
AnnaBridge 171:3a7713b1edbc 16116
AnnaBridge 171:3a7713b1edbc 16117 /*! @name DEBUG - USB PHY Debug Register */
AnnaBridge 171:3a7713b1edbc 16118 #define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 16119 #define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16120 #define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)
AnnaBridge 171:3a7713b1edbc 16121 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 16122 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 16123 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)
AnnaBridge 171:3a7713b1edbc 16124 #define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 16125 #define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 16126 #define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)
AnnaBridge 171:3a7713b1edbc 16127 #define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 16128 #define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16129 #define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
AnnaBridge 171:3a7713b1edbc 16130 #define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 16131 #define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 16132 #define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)
AnnaBridge 171:3a7713b1edbc 16133 #define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 16134 #define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 16135 #define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)
AnnaBridge 171:3a7713b1edbc 16136 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
AnnaBridge 171:3a7713b1edbc 16137 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 16138 #define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
AnnaBridge 171:3a7713b1edbc 16139 #define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 16140 #define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 16141 #define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)
AnnaBridge 171:3a7713b1edbc 16142 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
AnnaBridge 171:3a7713b1edbc 16143 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 16144 #define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
AnnaBridge 171:3a7713b1edbc 16145 #define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 16146 #define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 16147 #define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)
AnnaBridge 171:3a7713b1edbc 16148 #define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 16149 #define USBPHY_DEBUG_CLKGATE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 16150 #define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
AnnaBridge 171:3a7713b1edbc 16151
AnnaBridge 171:3a7713b1edbc 16152 /*! @name DEBUG_SET - USB PHY Debug Register */
AnnaBridge 171:3a7713b1edbc 16153 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 16154 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16155 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)
AnnaBridge 171:3a7713b1edbc 16156 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 16157 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 16158 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)
AnnaBridge 171:3a7713b1edbc 16159 #define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 16160 #define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 16161 #define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
AnnaBridge 171:3a7713b1edbc 16162 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 16163 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16164 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
AnnaBridge 171:3a7713b1edbc 16165 #define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 16166 #define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 16167 #define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
AnnaBridge 171:3a7713b1edbc 16168 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 16169 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 16170 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)
AnnaBridge 171:3a7713b1edbc 16171 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)
AnnaBridge 171:3a7713b1edbc 16172 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 16173 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
AnnaBridge 171:3a7713b1edbc 16174 #define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 16175 #define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 16176 #define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)
AnnaBridge 171:3a7713b1edbc 16177 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
AnnaBridge 171:3a7713b1edbc 16178 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 16179 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
AnnaBridge 171:3a7713b1edbc 16180 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 16181 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 16182 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)
AnnaBridge 171:3a7713b1edbc 16183 #define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 16184 #define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 16185 #define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
AnnaBridge 171:3a7713b1edbc 16186
AnnaBridge 171:3a7713b1edbc 16187 /*! @name DEBUG_CLR - USB PHY Debug Register */
AnnaBridge 171:3a7713b1edbc 16188 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 16189 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16190 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)
AnnaBridge 171:3a7713b1edbc 16191 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 16192 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 16193 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)
AnnaBridge 171:3a7713b1edbc 16194 #define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 16195 #define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 16196 #define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
AnnaBridge 171:3a7713b1edbc 16197 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 16198 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16199 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
AnnaBridge 171:3a7713b1edbc 16200 #define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 16201 #define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 16202 #define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
AnnaBridge 171:3a7713b1edbc 16203 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 16204 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 16205 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)
AnnaBridge 171:3a7713b1edbc 16206 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)
AnnaBridge 171:3a7713b1edbc 16207 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 16208 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
AnnaBridge 171:3a7713b1edbc 16209 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 16210 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 16211 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)
AnnaBridge 171:3a7713b1edbc 16212 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
AnnaBridge 171:3a7713b1edbc 16213 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 16214 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
AnnaBridge 171:3a7713b1edbc 16215 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 16216 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 16217 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
AnnaBridge 171:3a7713b1edbc 16218 #define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 16219 #define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 16220 #define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
AnnaBridge 171:3a7713b1edbc 16221
AnnaBridge 171:3a7713b1edbc 16222 /*! @name DEBUG_TOG - USB PHY Debug Register */
AnnaBridge 171:3a7713b1edbc 16223 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 16224 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16225 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)
AnnaBridge 171:3a7713b1edbc 16226 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 16227 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 16228 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)
AnnaBridge 171:3a7713b1edbc 16229 #define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 16230 #define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 16231 #define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
AnnaBridge 171:3a7713b1edbc 16232 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 16233 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16234 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
AnnaBridge 171:3a7713b1edbc 16235 #define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 16236 #define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 16237 #define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
AnnaBridge 171:3a7713b1edbc 16238 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 16239 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 16240 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)
AnnaBridge 171:3a7713b1edbc 16241 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
AnnaBridge 171:3a7713b1edbc 16242 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 16243 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
AnnaBridge 171:3a7713b1edbc 16244 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 16245 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 16246 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)
AnnaBridge 171:3a7713b1edbc 16247 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
AnnaBridge 171:3a7713b1edbc 16248 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 16249 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
AnnaBridge 171:3a7713b1edbc 16250 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 16251 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 16252 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)
AnnaBridge 171:3a7713b1edbc 16253 #define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 16254 #define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 16255 #define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
AnnaBridge 171:3a7713b1edbc 16256
AnnaBridge 171:3a7713b1edbc 16257 /*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */
AnnaBridge 171:3a7713b1edbc 16258 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 16259 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16260 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 16261 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 16262 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 16263 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 16264 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U)
AnnaBridge 171:3a7713b1edbc 16265 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 16266 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 16267
AnnaBridge 171:3a7713b1edbc 16268 /*! @name DEBUG1 - UTMI Debug Status Register 1 */
AnnaBridge 171:3a7713b1edbc 16269 #define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U)
AnnaBridge 171:3a7713b1edbc 16270 #define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 16271 #define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
AnnaBridge 171:3a7713b1edbc 16272
AnnaBridge 171:3a7713b1edbc 16273 /*! @name DEBUG1_SET - UTMI Debug Status Register 1 */
AnnaBridge 171:3a7713b1edbc 16274 #define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U)
AnnaBridge 171:3a7713b1edbc 16275 #define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 16276 #define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
AnnaBridge 171:3a7713b1edbc 16277
AnnaBridge 171:3a7713b1edbc 16278 /*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */
AnnaBridge 171:3a7713b1edbc 16279 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U)
AnnaBridge 171:3a7713b1edbc 16280 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 16281 #define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
AnnaBridge 171:3a7713b1edbc 16282
AnnaBridge 171:3a7713b1edbc 16283 /*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */
AnnaBridge 171:3a7713b1edbc 16284 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U)
AnnaBridge 171:3a7713b1edbc 16285 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 16286 #define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
AnnaBridge 171:3a7713b1edbc 16287
AnnaBridge 171:3a7713b1edbc 16288 /*! @name VERSION - UTMI RTL Version */
AnnaBridge 171:3a7713b1edbc 16289 #define USBPHY_VERSION_STEP_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 16290 #define USBPHY_VERSION_STEP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16291 #define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
AnnaBridge 171:3a7713b1edbc 16292 #define USBPHY_VERSION_MINOR_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 16293 #define USBPHY_VERSION_MINOR_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 16294 #define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
AnnaBridge 171:3a7713b1edbc 16295 #define USBPHY_VERSION_MAJOR_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 16296 #define USBPHY_VERSION_MAJOR_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 16297 #define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
AnnaBridge 171:3a7713b1edbc 16298
AnnaBridge 171:3a7713b1edbc 16299 /*! @name PLL_SIC - USB PHY PLL Control/Status Register */
AnnaBridge 171:3a7713b1edbc 16300 #define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 16301 #define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16302 #define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16303 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 16304 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 16305 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK)
AnnaBridge 171:3a7713b1edbc 16306 #define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 16307 #define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 16308 #define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_MASK)
AnnaBridge 171:3a7713b1edbc 16309 #define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 16310 #define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 16311 #define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK)
AnnaBridge 171:3a7713b1edbc 16312 #define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 16313 #define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 16314 #define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK)
AnnaBridge 171:3a7713b1edbc 16315 #define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 16316 #define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 16317 #define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK)
AnnaBridge 171:3a7713b1edbc 16318 #define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 16319 #define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 16320 #define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK)
AnnaBridge 171:3a7713b1edbc 16321
AnnaBridge 171:3a7713b1edbc 16322 /*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */
AnnaBridge 171:3a7713b1edbc 16323 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 16324 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16325 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16326 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 16327 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 16328 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK)
AnnaBridge 171:3a7713b1edbc 16329 #define USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 16330 #define USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 16331 #define USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_MASK)
AnnaBridge 171:3a7713b1edbc 16332 #define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 16333 #define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 16334 #define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK)
AnnaBridge 171:3a7713b1edbc 16335 #define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 16336 #define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 16337 #define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK)
AnnaBridge 171:3a7713b1edbc 16338 #define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 16339 #define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 16340 #define USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK)
AnnaBridge 171:3a7713b1edbc 16341 #define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 16342 #define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 16343 #define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK)
AnnaBridge 171:3a7713b1edbc 16344
AnnaBridge 171:3a7713b1edbc 16345 /*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */
AnnaBridge 171:3a7713b1edbc 16346 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 16347 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16348 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16349 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 16350 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 16351 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK)
AnnaBridge 171:3a7713b1edbc 16352 #define USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 16353 #define USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 16354 #define USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_MASK)
AnnaBridge 171:3a7713b1edbc 16355 #define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 16356 #define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 16357 #define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK)
AnnaBridge 171:3a7713b1edbc 16358 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 16359 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 16360 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK)
AnnaBridge 171:3a7713b1edbc 16361 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 16362 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 16363 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK)
AnnaBridge 171:3a7713b1edbc 16364 #define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 16365 #define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 16366 #define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK)
AnnaBridge 171:3a7713b1edbc 16367
AnnaBridge 171:3a7713b1edbc 16368 /*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */
AnnaBridge 171:3a7713b1edbc 16369 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 16370 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16371 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16372 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 16373 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 16374 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK)
AnnaBridge 171:3a7713b1edbc 16375 #define USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 16376 #define USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 16377 #define USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_MASK)
AnnaBridge 171:3a7713b1edbc 16378 #define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 16379 #define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 16380 #define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK)
AnnaBridge 171:3a7713b1edbc 16381 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 16382 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 16383 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK)
AnnaBridge 171:3a7713b1edbc 16384 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 16385 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 16386 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK)
AnnaBridge 171:3a7713b1edbc 16387 #define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 16388 #define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 16389 #define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK)
AnnaBridge 171:3a7713b1edbc 16390
AnnaBridge 171:3a7713b1edbc 16391 /*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */
AnnaBridge 171:3a7713b1edbc 16392 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 16393 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16394 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK)
AnnaBridge 171:3a7713b1edbc 16395 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 16396 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 16397 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK)
AnnaBridge 171:3a7713b1edbc 16398 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 16399 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16400 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16401 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 16402 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 16403 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16404 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 16405 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 16406 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16407 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 16408 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 16409 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16410 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 16411 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 16412 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16413 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U)
AnnaBridge 171:3a7713b1edbc 16414 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 16415 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16416 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 16417 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 16418 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK)
AnnaBridge 171:3a7713b1edbc 16419 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 16420 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 16421 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK)
AnnaBridge 171:3a7713b1edbc 16422 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 16423 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 16424 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK)
AnnaBridge 171:3a7713b1edbc 16425 #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 16426 #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 16427 #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK)
AnnaBridge 171:3a7713b1edbc 16428
AnnaBridge 171:3a7713b1edbc 16429 /*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */
AnnaBridge 171:3a7713b1edbc 16430 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 16431 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16432 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
AnnaBridge 171:3a7713b1edbc 16433 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 16434 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 16435 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK)
AnnaBridge 171:3a7713b1edbc 16436 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 16437 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16438 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16439 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 16440 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 16441 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16442 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 16443 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 16444 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16445 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 16446 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 16447 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16448 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 16449 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 16450 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16451 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U)
AnnaBridge 171:3a7713b1edbc 16452 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 16453 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16454 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 16455 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 16456 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK)
AnnaBridge 171:3a7713b1edbc 16457 #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 16458 #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 16459 #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK)
AnnaBridge 171:3a7713b1edbc 16460 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 16461 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 16462 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
AnnaBridge 171:3a7713b1edbc 16463 #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 16464 #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 16465 #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK)
AnnaBridge 171:3a7713b1edbc 16466
AnnaBridge 171:3a7713b1edbc 16467 /*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */
AnnaBridge 171:3a7713b1edbc 16468 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 16469 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16470 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
AnnaBridge 171:3a7713b1edbc 16471 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 16472 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 16473 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK)
AnnaBridge 171:3a7713b1edbc 16474 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 16475 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16476 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16477 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 16478 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 16479 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16480 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 16481 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 16482 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16483 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 16484 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 16485 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16486 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 16487 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 16488 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16489 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U)
AnnaBridge 171:3a7713b1edbc 16490 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 16491 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16492 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 16493 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 16494 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK)
AnnaBridge 171:3a7713b1edbc 16495 #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 16496 #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 16497 #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK)
AnnaBridge 171:3a7713b1edbc 16498 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 16499 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 16500 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
AnnaBridge 171:3a7713b1edbc 16501 #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 16502 #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 16503 #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK)
AnnaBridge 171:3a7713b1edbc 16504
AnnaBridge 171:3a7713b1edbc 16505 /*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */
AnnaBridge 171:3a7713b1edbc 16506 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 16507 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16508 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
AnnaBridge 171:3a7713b1edbc 16509 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 16510 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 16511 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK)
AnnaBridge 171:3a7713b1edbc 16512 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 16513 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16514 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16515 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 16516 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 16517 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16518 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 16519 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 16520 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16521 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 16522 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 16523 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16524 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 16525 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 16526 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16527 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U)
AnnaBridge 171:3a7713b1edbc 16528 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 16529 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16530 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 16531 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 16532 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK)
AnnaBridge 171:3a7713b1edbc 16533 #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 16534 #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 16535 #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK)
AnnaBridge 171:3a7713b1edbc 16536 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 16537 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 16538 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
AnnaBridge 171:3a7713b1edbc 16539 #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 16540 #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 16541 #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK)
AnnaBridge 171:3a7713b1edbc 16542
AnnaBridge 171:3a7713b1edbc 16543 /*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */
AnnaBridge 171:3a7713b1edbc 16544 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 16545 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16546 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK)
AnnaBridge 171:3a7713b1edbc 16547 #define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 16548 #define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 16549 #define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK)
AnnaBridge 171:3a7713b1edbc 16550 #define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 16551 #define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 16552 #define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK)
AnnaBridge 171:3a7713b1edbc 16553 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 16554 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 16555 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK)
AnnaBridge 171:3a7713b1edbc 16556 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 16557 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16558 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)
AnnaBridge 171:3a7713b1edbc 16559
AnnaBridge 171:3a7713b1edbc 16560 /*! @name USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register */
AnnaBridge 171:3a7713b1edbc 16561 #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 16562 #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16563 #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK)
AnnaBridge 171:3a7713b1edbc 16564 #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 16565 #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 16566 #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK)
AnnaBridge 171:3a7713b1edbc 16567 #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 16568 #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 16569 #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK)
AnnaBridge 171:3a7713b1edbc 16570 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 16571 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 16572 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK)
AnnaBridge 171:3a7713b1edbc 16573 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 16574 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16575 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK)
AnnaBridge 171:3a7713b1edbc 16576
AnnaBridge 171:3a7713b1edbc 16577 /*! @name ANACTRL - USB PHY Analog Control Register */
AnnaBridge 171:3a7713b1edbc 16578 #define USBPHY_ANACTRL_TESTCLK_SEL_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 16579 #define USBPHY_ANACTRL_TESTCLK_SEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16580 #define USBPHY_ANACTRL_TESTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_TESTCLK_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16581 #define USBPHY_ANACTRL_PFD_CLKGATE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 16582 #define USBPHY_ANACTRL_PFD_CLKGATE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 16583 #define USBPHY_ANACTRL_PFD_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_PFD_CLKGATE_MASK)
AnnaBridge 171:3a7713b1edbc 16584 #define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 16585 #define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 16586 #define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16587 #define USBPHY_ANACTRL_PFD_FRAC_MASK (0x3F0U)
AnnaBridge 171:3a7713b1edbc 16588 #define USBPHY_ANACTRL_PFD_FRAC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16589 #define USBPHY_ANACTRL_PFD_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_PFD_FRAC_MASK)
AnnaBridge 171:3a7713b1edbc 16590 #define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 16591 #define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 16592 #define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK)
AnnaBridge 171:3a7713b1edbc 16593 #define USBPHY_ANACTRL_EMPH_PULSE_CTRL_MASK (0x1800U)
AnnaBridge 171:3a7713b1edbc 16594 #define USBPHY_ANACTRL_EMPH_PULSE_CTRL_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 16595 #define USBPHY_ANACTRL_EMPH_PULSE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_EMPH_PULSE_CTRL_MASK)
AnnaBridge 171:3a7713b1edbc 16596 #define USBPHY_ANACTRL_EMPH_EN_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 16597 #define USBPHY_ANACTRL_EMPH_EN_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 16598 #define USBPHY_ANACTRL_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_EMPH_EN_MASK)
AnnaBridge 171:3a7713b1edbc 16599 #define USBPHY_ANACTRL_EMPH_CUR_CTRL_MASK (0xC000U)
AnnaBridge 171:3a7713b1edbc 16600 #define USBPHY_ANACTRL_EMPH_CUR_CTRL_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 16601 #define USBPHY_ANACTRL_EMPH_CUR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_EMPH_CUR_CTRL_MASK)
AnnaBridge 171:3a7713b1edbc 16602 #define USBPHY_ANACTRL_PFD_STABLE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 16603 #define USBPHY_ANACTRL_PFD_STABLE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 16604 #define USBPHY_ANACTRL_PFD_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_PFD_STABLE_MASK)
AnnaBridge 171:3a7713b1edbc 16605
AnnaBridge 171:3a7713b1edbc 16606 /*! @name ANACTRL_SET - USB PHY Analog Control Register */
AnnaBridge 171:3a7713b1edbc 16607 #define USBPHY_ANACTRL_SET_TESTCLK_SEL_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 16608 #define USBPHY_ANACTRL_SET_TESTCLK_SEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16609 #define USBPHY_ANACTRL_SET_TESTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_TESTCLK_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16610 #define USBPHY_ANACTRL_SET_PFD_CLKGATE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 16611 #define USBPHY_ANACTRL_SET_PFD_CLKGATE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 16612 #define USBPHY_ANACTRL_SET_PFD_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLKGATE_MASK)
AnnaBridge 171:3a7713b1edbc 16613 #define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 16614 #define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 16615 #define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16616 #define USBPHY_ANACTRL_SET_PFD_FRAC_MASK (0x3F0U)
AnnaBridge 171:3a7713b1edbc 16617 #define USBPHY_ANACTRL_SET_PFD_FRAC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16618 #define USBPHY_ANACTRL_SET_PFD_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_SET_PFD_FRAC_MASK)
AnnaBridge 171:3a7713b1edbc 16619 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 16620 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 16621 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK)
AnnaBridge 171:3a7713b1edbc 16622 #define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_MASK (0x1800U)
AnnaBridge 171:3a7713b1edbc 16623 #define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 16624 #define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_MASK)
AnnaBridge 171:3a7713b1edbc 16625 #define USBPHY_ANACTRL_SET_EMPH_EN_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 16626 #define USBPHY_ANACTRL_SET_EMPH_EN_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 16627 #define USBPHY_ANACTRL_SET_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_EN_MASK)
AnnaBridge 171:3a7713b1edbc 16628 #define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_MASK (0xC000U)
AnnaBridge 171:3a7713b1edbc 16629 #define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 16630 #define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_MASK)
AnnaBridge 171:3a7713b1edbc 16631 #define USBPHY_ANACTRL_SET_PFD_STABLE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 16632 #define USBPHY_ANACTRL_SET_PFD_STABLE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 16633 #define USBPHY_ANACTRL_SET_PFD_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_SET_PFD_STABLE_MASK)
AnnaBridge 171:3a7713b1edbc 16634
AnnaBridge 171:3a7713b1edbc 16635 /*! @name ANACTRL_CLR - USB PHY Analog Control Register */
AnnaBridge 171:3a7713b1edbc 16636 #define USBPHY_ANACTRL_CLR_TESTCLK_SEL_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 16637 #define USBPHY_ANACTRL_CLR_TESTCLK_SEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16638 #define USBPHY_ANACTRL_CLR_TESTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_TESTCLK_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16639 #define USBPHY_ANACTRL_CLR_PFD_CLKGATE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 16640 #define USBPHY_ANACTRL_CLR_PFD_CLKGATE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 16641 #define USBPHY_ANACTRL_CLR_PFD_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLKGATE_MASK)
AnnaBridge 171:3a7713b1edbc 16642 #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 16643 #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 16644 #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16645 #define USBPHY_ANACTRL_CLR_PFD_FRAC_MASK (0x3F0U)
AnnaBridge 171:3a7713b1edbc 16646 #define USBPHY_ANACTRL_CLR_PFD_FRAC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16647 #define USBPHY_ANACTRL_CLR_PFD_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_FRAC_MASK)
AnnaBridge 171:3a7713b1edbc 16648 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 16649 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 16650 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK)
AnnaBridge 171:3a7713b1edbc 16651 #define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_MASK (0x1800U)
AnnaBridge 171:3a7713b1edbc 16652 #define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 16653 #define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_MASK)
AnnaBridge 171:3a7713b1edbc 16654 #define USBPHY_ANACTRL_CLR_EMPH_EN_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 16655 #define USBPHY_ANACTRL_CLR_EMPH_EN_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 16656 #define USBPHY_ANACTRL_CLR_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_EN_MASK)
AnnaBridge 171:3a7713b1edbc 16657 #define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_MASK (0xC000U)
AnnaBridge 171:3a7713b1edbc 16658 #define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 16659 #define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_MASK)
AnnaBridge 171:3a7713b1edbc 16660 #define USBPHY_ANACTRL_CLR_PFD_STABLE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 16661 #define USBPHY_ANACTRL_CLR_PFD_STABLE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 16662 #define USBPHY_ANACTRL_CLR_PFD_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_STABLE_MASK)
AnnaBridge 171:3a7713b1edbc 16663
AnnaBridge 171:3a7713b1edbc 16664 /*! @name ANACTRL_TOG - USB PHY Analog Control Register */
AnnaBridge 171:3a7713b1edbc 16665 #define USBPHY_ANACTRL_TOG_TESTCLK_SEL_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 16666 #define USBPHY_ANACTRL_TOG_TESTCLK_SEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16667 #define USBPHY_ANACTRL_TOG_TESTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_TESTCLK_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16668 #define USBPHY_ANACTRL_TOG_PFD_CLKGATE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 16669 #define USBPHY_ANACTRL_TOG_PFD_CLKGATE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 16670 #define USBPHY_ANACTRL_TOG_PFD_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLKGATE_MASK)
AnnaBridge 171:3a7713b1edbc 16671 #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 16672 #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 16673 #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16674 #define USBPHY_ANACTRL_TOG_PFD_FRAC_MASK (0x3F0U)
AnnaBridge 171:3a7713b1edbc 16675 #define USBPHY_ANACTRL_TOG_PFD_FRAC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16676 #define USBPHY_ANACTRL_TOG_PFD_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_FRAC_MASK)
AnnaBridge 171:3a7713b1edbc 16677 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 16678 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 16679 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK)
AnnaBridge 171:3a7713b1edbc 16680 #define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_MASK (0x1800U)
AnnaBridge 171:3a7713b1edbc 16681 #define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 16682 #define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_MASK)
AnnaBridge 171:3a7713b1edbc 16683 #define USBPHY_ANACTRL_TOG_EMPH_EN_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 16684 #define USBPHY_ANACTRL_TOG_EMPH_EN_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 16685 #define USBPHY_ANACTRL_TOG_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_EN_MASK)
AnnaBridge 171:3a7713b1edbc 16686 #define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_MASK (0xC000U)
AnnaBridge 171:3a7713b1edbc 16687 #define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 16688 #define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_MASK)
AnnaBridge 171:3a7713b1edbc 16689 #define USBPHY_ANACTRL_TOG_PFD_STABLE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 16690 #define USBPHY_ANACTRL_TOG_PFD_STABLE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 16691 #define USBPHY_ANACTRL_TOG_PFD_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_STABLE_MASK)
AnnaBridge 171:3a7713b1edbc 16692
AnnaBridge 171:3a7713b1edbc 16693 /*! @name USB1_LOOPBACK - USB PHY Loopback Control/Status Register */
AnnaBridge 171:3a7713b1edbc 16694 #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 16695 #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16696 #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK)
AnnaBridge 171:3a7713b1edbc 16697 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 16698 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 16699 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK)
AnnaBridge 171:3a7713b1edbc 16700 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 16701 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 16702 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK)
AnnaBridge 171:3a7713b1edbc 16703 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 16704 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 16705 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 16706 #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 16707 #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16708 #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 16709 #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 16710 #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 16711 #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK)
AnnaBridge 171:3a7713b1edbc 16712 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 16713 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 16714 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK)
AnnaBridge 171:3a7713b1edbc 16715 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 16716 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 16717 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK)
AnnaBridge 171:3a7713b1edbc 16718 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 16719 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 16720 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK)
AnnaBridge 171:3a7713b1edbc 16721 #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 16722 #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 16723 #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK)
AnnaBridge 171:3a7713b1edbc 16724 #define USBPHY_USB1_LOOPBACK_TSTPKT_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 16725 #define USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 16726 #define USBPHY_USB1_LOOPBACK_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTPKT_MASK)
AnnaBridge 171:3a7713b1edbc 16727
AnnaBridge 171:3a7713b1edbc 16728 /*! @name USB1_LOOPBACK_SET - USB PHY Loopback Control/Status Register */
AnnaBridge 171:3a7713b1edbc 16729 #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 16730 #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16731 #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK)
AnnaBridge 171:3a7713b1edbc 16732 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 16733 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 16734 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK)
AnnaBridge 171:3a7713b1edbc 16735 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 16736 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 16737 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK)
AnnaBridge 171:3a7713b1edbc 16738 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 16739 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 16740 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 16741 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 16742 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16743 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 16744 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 16745 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 16746 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK)
AnnaBridge 171:3a7713b1edbc 16747 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 16748 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 16749 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK)
AnnaBridge 171:3a7713b1edbc 16750 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 16751 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 16752 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK)
AnnaBridge 171:3a7713b1edbc 16753 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 16754 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 16755 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK)
AnnaBridge 171:3a7713b1edbc 16756 #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 16757 #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 16758 #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK)
AnnaBridge 171:3a7713b1edbc 16759 #define USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 16760 #define USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 16761 #define USBPHY_USB1_LOOPBACK_SET_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK)
AnnaBridge 171:3a7713b1edbc 16762
AnnaBridge 171:3a7713b1edbc 16763 /*! @name USB1_LOOPBACK_CLR - USB PHY Loopback Control/Status Register */
AnnaBridge 171:3a7713b1edbc 16764 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 16765 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16766 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
AnnaBridge 171:3a7713b1edbc 16767 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 16768 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 16769 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK)
AnnaBridge 171:3a7713b1edbc 16770 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 16771 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 16772 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK)
AnnaBridge 171:3a7713b1edbc 16773 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 16774 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 16775 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 16776 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 16777 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16778 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 16779 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 16780 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 16781 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK)
AnnaBridge 171:3a7713b1edbc 16782 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 16783 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 16784 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK)
AnnaBridge 171:3a7713b1edbc 16785 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 16786 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 16787 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK)
AnnaBridge 171:3a7713b1edbc 16788 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 16789 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 16790 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK)
AnnaBridge 171:3a7713b1edbc 16791 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 16792 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 16793 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK)
AnnaBridge 171:3a7713b1edbc 16794 #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 16795 #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 16796 #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK)
AnnaBridge 171:3a7713b1edbc 16797
AnnaBridge 171:3a7713b1edbc 16798 /*! @name USB1_LOOPBACK_TOG - USB PHY Loopback Control/Status Register */
AnnaBridge 171:3a7713b1edbc 16799 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 16800 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16801 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
AnnaBridge 171:3a7713b1edbc 16802 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 16803 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 16804 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK)
AnnaBridge 171:3a7713b1edbc 16805 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 16806 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 16807 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK)
AnnaBridge 171:3a7713b1edbc 16808 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 16809 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 16810 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 16811 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 16812 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16813 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 16814 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 16815 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 16816 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK)
AnnaBridge 171:3a7713b1edbc 16817 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 16818 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 16819 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK)
AnnaBridge 171:3a7713b1edbc 16820 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 16821 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 16822 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK)
AnnaBridge 171:3a7713b1edbc 16823 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 16824 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 16825 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK)
AnnaBridge 171:3a7713b1edbc 16826 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 16827 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 16828 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK)
AnnaBridge 171:3a7713b1edbc 16829 #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 16830 #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 16831 #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK)
AnnaBridge 171:3a7713b1edbc 16832
AnnaBridge 171:3a7713b1edbc 16833 /*! @name USB1_LOOPBACK_HSFSCNT - USB PHY Loopback Packet Number Select Register */
AnnaBridge 171:3a7713b1edbc 16834 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 16835 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16836 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK)
AnnaBridge 171:3a7713b1edbc 16837 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 16838 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 16839 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK)
AnnaBridge 171:3a7713b1edbc 16840
AnnaBridge 171:3a7713b1edbc 16841 /*! @name USB1_LOOPBACK_HSFSCNT_SET - USB PHY Loopback Packet Number Select Register */
AnnaBridge 171:3a7713b1edbc 16842 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 16843 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16844 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK)
AnnaBridge 171:3a7713b1edbc 16845 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 16846 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 16847 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK)
AnnaBridge 171:3a7713b1edbc 16848
AnnaBridge 171:3a7713b1edbc 16849 /*! @name USB1_LOOPBACK_HSFSCNT_CLR - USB PHY Loopback Packet Number Select Register */
AnnaBridge 171:3a7713b1edbc 16850 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 16851 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16852 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK)
AnnaBridge 171:3a7713b1edbc 16853 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 16854 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 16855 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK)
AnnaBridge 171:3a7713b1edbc 16856
AnnaBridge 171:3a7713b1edbc 16857 /*! @name USB1_LOOPBACK_HSFSCNT_TOG - USB PHY Loopback Packet Number Select Register */
AnnaBridge 171:3a7713b1edbc 16858 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 16859 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16860 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK)
AnnaBridge 171:3a7713b1edbc 16861 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 16862 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 16863 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK)
AnnaBridge 171:3a7713b1edbc 16864
AnnaBridge 171:3a7713b1edbc 16865 /*! @name TRIM_OVERRIDE_EN - USB PHY Trim Override Enable Register */
AnnaBridge 171:3a7713b1edbc 16866 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 16867 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16868 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16869 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 16870 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 16871 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16872 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 16873 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 16874 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16875 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 16876 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 16877 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16878 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 16879 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16880 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16881 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 16882 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 16883 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16884 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 16885 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 16886 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
AnnaBridge 171:3a7713b1edbc 16887 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 16888 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 16889 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK)
AnnaBridge 171:3a7713b1edbc 16890 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 16891 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 16892 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK)
AnnaBridge 171:3a7713b1edbc 16893 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 16894 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 16895 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_MASK)
AnnaBridge 171:3a7713b1edbc 16896
AnnaBridge 171:3a7713b1edbc 16897 /*! @name TRIM_OVERRIDE_EN_SET - USB PHY Trim Override Enable Register */
AnnaBridge 171:3a7713b1edbc 16898 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 16899 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16900 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16901 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 16902 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 16903 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16904 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 16905 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 16906 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16907 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 16908 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 16909 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16910 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 16911 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16912 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16913 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 16914 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 16915 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16916 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 16917 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 16918 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
AnnaBridge 171:3a7713b1edbc 16919 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 16920 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 16921 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK)
AnnaBridge 171:3a7713b1edbc 16922 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 16923 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 16924 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK)
AnnaBridge 171:3a7713b1edbc 16925 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 16926 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 16927 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_MASK)
AnnaBridge 171:3a7713b1edbc 16928
AnnaBridge 171:3a7713b1edbc 16929 /*! @name TRIM_OVERRIDE_EN_CLR - USB PHY Trim Override Enable Register */
AnnaBridge 171:3a7713b1edbc 16930 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 16931 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16932 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16933 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 16934 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 16935 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16936 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 16937 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 16938 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16939 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 16940 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 16941 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16942 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 16943 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16944 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16945 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 16946 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 16947 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16948 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 16949 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 16950 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
AnnaBridge 171:3a7713b1edbc 16951 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 16952 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 16953 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK)
AnnaBridge 171:3a7713b1edbc 16954 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 16955 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 16956 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK)
AnnaBridge 171:3a7713b1edbc 16957 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 16958 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 16959 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_MASK)
AnnaBridge 171:3a7713b1edbc 16960
AnnaBridge 171:3a7713b1edbc 16961 /*! @name TRIM_OVERRIDE_EN_TOG - USB PHY Trim Override Enable Register */
AnnaBridge 171:3a7713b1edbc 16962 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 16963 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 16964 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16965 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 16966 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 16967 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16968 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 16969 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 16970 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16971 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 16972 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 16973 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16974 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 16975 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 16976 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_MASK)
AnnaBridge 171:3a7713b1edbc 16977 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 16978 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 16979 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 16980 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 16981 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 16982 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
AnnaBridge 171:3a7713b1edbc 16983 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 16984 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 16985 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK)
AnnaBridge 171:3a7713b1edbc 16986 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 16987 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 16988 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK)
AnnaBridge 171:3a7713b1edbc 16989 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 16990 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 16991 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_MASK)
AnnaBridge 171:3a7713b1edbc 16992
AnnaBridge 171:3a7713b1edbc 16993
AnnaBridge 171:3a7713b1edbc 16994 /*!
AnnaBridge 171:3a7713b1edbc 16995 * @}
AnnaBridge 171:3a7713b1edbc 16996 */ /* end of group USBPHY_Register_Masks */
AnnaBridge 171:3a7713b1edbc 16997
AnnaBridge 171:3a7713b1edbc 16998
AnnaBridge 171:3a7713b1edbc 16999 /* USBPHY - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 17000 /** Peripheral USBPHY base address */
AnnaBridge 171:3a7713b1edbc 17001 #define USBPHY_BASE (0x400A2000u)
AnnaBridge 171:3a7713b1edbc 17002 /** Peripheral USBPHY base pointer */
AnnaBridge 171:3a7713b1edbc 17003 #define USBPHY ((USBPHY_Type *)USBPHY_BASE)
AnnaBridge 171:3a7713b1edbc 17004 /** Array initializer of USBPHY peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 17005 #define USBPHY_BASE_ADDRS { USBPHY_BASE }
AnnaBridge 171:3a7713b1edbc 17006 /** Array initializer of USBPHY peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 17007 #define USBPHY_BASE_PTRS { USBPHY }
AnnaBridge 171:3a7713b1edbc 17008
AnnaBridge 171:3a7713b1edbc 17009 /*!
AnnaBridge 171:3a7713b1edbc 17010 * @}
AnnaBridge 171:3a7713b1edbc 17011 */ /* end of group USBPHY_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 17012
AnnaBridge 171:3a7713b1edbc 17013
AnnaBridge 171:3a7713b1edbc 17014 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 17015 -- VREF Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 17016 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 17017
AnnaBridge 171:3a7713b1edbc 17018 /*!
AnnaBridge 171:3a7713b1edbc 17019 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 17020 * @{
AnnaBridge 171:3a7713b1edbc 17021 */
AnnaBridge 171:3a7713b1edbc 17022
AnnaBridge 171:3a7713b1edbc 17023 /** VREF - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 17024 typedef struct {
AnnaBridge 171:3a7713b1edbc 17025 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 17026 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 17027 } VREF_Type;
AnnaBridge 171:3a7713b1edbc 17028
AnnaBridge 171:3a7713b1edbc 17029 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 17030 -- VREF Register Masks
AnnaBridge 171:3a7713b1edbc 17031 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 17032
AnnaBridge 171:3a7713b1edbc 17033 /*!
AnnaBridge 171:3a7713b1edbc 17034 * @addtogroup VREF_Register_Masks VREF Register Masks
AnnaBridge 171:3a7713b1edbc 17035 * @{
AnnaBridge 171:3a7713b1edbc 17036 */
AnnaBridge 171:3a7713b1edbc 17037
AnnaBridge 171:3a7713b1edbc 17038 /*! @name TRM - VREF Trim Register */
AnnaBridge 171:3a7713b1edbc 17039 #define VREF_TRM_TRIM_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 17040 #define VREF_TRM_TRIM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 17041 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
AnnaBridge 171:3a7713b1edbc 17042 #define VREF_TRM_CHOPEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 17043 #define VREF_TRM_CHOPEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 17044 #define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
AnnaBridge 171:3a7713b1edbc 17045
AnnaBridge 171:3a7713b1edbc 17046 /*! @name SC - VREF Status and Control Register */
AnnaBridge 171:3a7713b1edbc 17047 #define VREF_SC_MODE_LV_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 17048 #define VREF_SC_MODE_LV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 17049 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
AnnaBridge 171:3a7713b1edbc 17050 #define VREF_SC_VREFST_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 17051 #define VREF_SC_VREFST_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 17052 #define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
AnnaBridge 171:3a7713b1edbc 17053 #define VREF_SC_ICOMPEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 17054 #define VREF_SC_ICOMPEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 17055 #define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
AnnaBridge 171:3a7713b1edbc 17056 #define VREF_SC_REGEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 17057 #define VREF_SC_REGEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 17058 #define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
AnnaBridge 171:3a7713b1edbc 17059 #define VREF_SC_VREFEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 17060 #define VREF_SC_VREFEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 17061 #define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
AnnaBridge 171:3a7713b1edbc 17062
AnnaBridge 171:3a7713b1edbc 17063
AnnaBridge 171:3a7713b1edbc 17064 /*!
AnnaBridge 171:3a7713b1edbc 17065 * @}
AnnaBridge 171:3a7713b1edbc 17066 */ /* end of group VREF_Register_Masks */
AnnaBridge 171:3a7713b1edbc 17067
AnnaBridge 171:3a7713b1edbc 17068
AnnaBridge 171:3a7713b1edbc 17069 /* VREF - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 17070 /** Peripheral VREF base address */
AnnaBridge 171:3a7713b1edbc 17071 #define VREF_BASE (0x40074000u)
AnnaBridge 171:3a7713b1edbc 17072 /** Peripheral VREF base pointer */
AnnaBridge 171:3a7713b1edbc 17073 #define VREF ((VREF_Type *)VREF_BASE)
AnnaBridge 171:3a7713b1edbc 17074 /** Array initializer of VREF peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 17075 #define VREF_BASE_ADDRS { VREF_BASE }
AnnaBridge 171:3a7713b1edbc 17076 /** Array initializer of VREF peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 17077 #define VREF_BASE_PTRS { VREF }
AnnaBridge 171:3a7713b1edbc 17078
AnnaBridge 171:3a7713b1edbc 17079 /*!
AnnaBridge 171:3a7713b1edbc 17080 * @}
AnnaBridge 171:3a7713b1edbc 17081 */ /* end of group VREF_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 17082
AnnaBridge 171:3a7713b1edbc 17083
AnnaBridge 171:3a7713b1edbc 17084 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 17085 -- WDOG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 17086 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 17087
AnnaBridge 171:3a7713b1edbc 17088 /*!
AnnaBridge 171:3a7713b1edbc 17089 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 17090 * @{
AnnaBridge 171:3a7713b1edbc 17091 */
AnnaBridge 171:3a7713b1edbc 17092
AnnaBridge 171:3a7713b1edbc 17093 /** WDOG - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 17094 typedef struct {
AnnaBridge 171:3a7713b1edbc 17095 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 17096 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 17097 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 17098 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 17099 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 17100 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 17101 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 17102 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
AnnaBridge 171:3a7713b1edbc 17103 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 17104 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
AnnaBridge 171:3a7713b1edbc 17105 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 17106 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
AnnaBridge 171:3a7713b1edbc 17107 } WDOG_Type;
AnnaBridge 171:3a7713b1edbc 17108
AnnaBridge 171:3a7713b1edbc 17109 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 17110 -- WDOG Register Masks
AnnaBridge 171:3a7713b1edbc 17111 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 17112
AnnaBridge 171:3a7713b1edbc 17113 /*!
AnnaBridge 171:3a7713b1edbc 17114 * @addtogroup WDOG_Register_Masks WDOG Register Masks
AnnaBridge 171:3a7713b1edbc 17115 * @{
AnnaBridge 171:3a7713b1edbc 17116 */
AnnaBridge 171:3a7713b1edbc 17117
AnnaBridge 171:3a7713b1edbc 17118 /*! @name STCTRLH - Watchdog Status and Control Register High */
AnnaBridge 171:3a7713b1edbc 17119 #define WDOG_STCTRLH_WDOGEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 17120 #define WDOG_STCTRLH_WDOGEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 17121 #define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
AnnaBridge 171:3a7713b1edbc 17122 #define WDOG_STCTRLH_CLKSRC_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 17123 #define WDOG_STCTRLH_CLKSRC_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 17124 #define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
AnnaBridge 171:3a7713b1edbc 17125 #define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 17126 #define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 17127 #define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
AnnaBridge 171:3a7713b1edbc 17128 #define WDOG_STCTRLH_WINEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 17129 #define WDOG_STCTRLH_WINEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 17130 #define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
AnnaBridge 171:3a7713b1edbc 17131 #define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 17132 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 17133 #define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
AnnaBridge 171:3a7713b1edbc 17134 #define WDOG_STCTRLH_DBGEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 17135 #define WDOG_STCTRLH_DBGEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 17136 #define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
AnnaBridge 171:3a7713b1edbc 17137 #define WDOG_STCTRLH_STOPEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 17138 #define WDOG_STCTRLH_STOPEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 17139 #define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
AnnaBridge 171:3a7713b1edbc 17140 #define WDOG_STCTRLH_WAITEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 17141 #define WDOG_STCTRLH_WAITEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 17142 #define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
AnnaBridge 171:3a7713b1edbc 17143 #define WDOG_STCTRLH_TESTWDOG_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 17144 #define WDOG_STCTRLH_TESTWDOG_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 17145 #define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
AnnaBridge 171:3a7713b1edbc 17146 #define WDOG_STCTRLH_TESTSEL_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 17147 #define WDOG_STCTRLH_TESTSEL_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 17148 #define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 17149 #define WDOG_STCTRLH_BYTESEL_MASK (0x3000U)
AnnaBridge 171:3a7713b1edbc 17150 #define WDOG_STCTRLH_BYTESEL_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 17151 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
AnnaBridge 171:3a7713b1edbc 17152 #define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 17153 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 17154 #define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
AnnaBridge 171:3a7713b1edbc 17155
AnnaBridge 171:3a7713b1edbc 17156 /*! @name STCTRLL - Watchdog Status and Control Register Low */
AnnaBridge 171:3a7713b1edbc 17157 #define WDOG_STCTRLL_INTFLG_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 17158 #define WDOG_STCTRLL_INTFLG_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 17159 #define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
AnnaBridge 171:3a7713b1edbc 17160
AnnaBridge 171:3a7713b1edbc 17161 /*! @name TOVALH - Watchdog Time-out Value Register High */
AnnaBridge 171:3a7713b1edbc 17162 #define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 17163 #define WDOG_TOVALH_TOVALHIGH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 17164 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
AnnaBridge 171:3a7713b1edbc 17165
AnnaBridge 171:3a7713b1edbc 17166 /*! @name TOVALL - Watchdog Time-out Value Register Low */
AnnaBridge 171:3a7713b1edbc 17167 #define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 17168 #define WDOG_TOVALL_TOVALLOW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 17169 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
AnnaBridge 171:3a7713b1edbc 17170
AnnaBridge 171:3a7713b1edbc 17171 /*! @name WINH - Watchdog Window Register High */
AnnaBridge 171:3a7713b1edbc 17172 #define WDOG_WINH_WINHIGH_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 17173 #define WDOG_WINH_WINHIGH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 17174 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
AnnaBridge 171:3a7713b1edbc 17175
AnnaBridge 171:3a7713b1edbc 17176 /*! @name WINL - Watchdog Window Register Low */
AnnaBridge 171:3a7713b1edbc 17177 #define WDOG_WINL_WINLOW_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 17178 #define WDOG_WINL_WINLOW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 17179 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
AnnaBridge 171:3a7713b1edbc 17180
AnnaBridge 171:3a7713b1edbc 17181 /*! @name REFRESH - Watchdog Refresh register */
AnnaBridge 171:3a7713b1edbc 17182 #define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 17183 #define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 17184 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
AnnaBridge 171:3a7713b1edbc 17185
AnnaBridge 171:3a7713b1edbc 17186 /*! @name UNLOCK - Watchdog Unlock register */
AnnaBridge 171:3a7713b1edbc 17187 #define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 17188 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 17189 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
AnnaBridge 171:3a7713b1edbc 17190
AnnaBridge 171:3a7713b1edbc 17191 /*! @name TMROUTH - Watchdog Timer Output Register High */
AnnaBridge 171:3a7713b1edbc 17192 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 17193 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 17194 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
AnnaBridge 171:3a7713b1edbc 17195
AnnaBridge 171:3a7713b1edbc 17196 /*! @name TMROUTL - Watchdog Timer Output Register Low */
AnnaBridge 171:3a7713b1edbc 17197 #define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 17198 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 17199 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
AnnaBridge 171:3a7713b1edbc 17200
AnnaBridge 171:3a7713b1edbc 17201 /*! @name RSTCNT - Watchdog Reset Count register */
AnnaBridge 171:3a7713b1edbc 17202 #define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 17203 #define WDOG_RSTCNT_RSTCNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 17204 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
AnnaBridge 171:3a7713b1edbc 17205
AnnaBridge 171:3a7713b1edbc 17206 /*! @name PRESC - Watchdog Prescaler register */
AnnaBridge 171:3a7713b1edbc 17207 #define WDOG_PRESC_PRESCVAL_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 17208 #define WDOG_PRESC_PRESCVAL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 17209 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
AnnaBridge 171:3a7713b1edbc 17210
AnnaBridge 171:3a7713b1edbc 17211
AnnaBridge 171:3a7713b1edbc 17212 /*!
AnnaBridge 171:3a7713b1edbc 17213 * @}
AnnaBridge 171:3a7713b1edbc 17214 */ /* end of group WDOG_Register_Masks */
AnnaBridge 171:3a7713b1edbc 17215
AnnaBridge 171:3a7713b1edbc 17216
AnnaBridge 171:3a7713b1edbc 17217 /* WDOG - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 17218 /** Peripheral WDOG base address */
AnnaBridge 171:3a7713b1edbc 17219 #define WDOG_BASE (0x40052000u)
AnnaBridge 171:3a7713b1edbc 17220 /** Peripheral WDOG base pointer */
AnnaBridge 171:3a7713b1edbc 17221 #define WDOG ((WDOG_Type *)WDOG_BASE)
AnnaBridge 171:3a7713b1edbc 17222 /** Array initializer of WDOG peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 17223 #define WDOG_BASE_ADDRS { WDOG_BASE }
AnnaBridge 171:3a7713b1edbc 17224 /** Array initializer of WDOG peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 17225 #define WDOG_BASE_PTRS { WDOG }
AnnaBridge 171:3a7713b1edbc 17226 /** Interrupt vectors for the WDOG peripheral type */
AnnaBridge 171:3a7713b1edbc 17227 #define WDOG_IRQS { WDOG_EWM_IRQn }
AnnaBridge 171:3a7713b1edbc 17228
AnnaBridge 171:3a7713b1edbc 17229 /*!
AnnaBridge 171:3a7713b1edbc 17230 * @}
AnnaBridge 171:3a7713b1edbc 17231 */ /* end of group WDOG_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 17232
AnnaBridge 171:3a7713b1edbc 17233
AnnaBridge 171:3a7713b1edbc 17234 /*
AnnaBridge 171:3a7713b1edbc 17235 ** End of section using anonymous unions
AnnaBridge 171:3a7713b1edbc 17236 */
AnnaBridge 171:3a7713b1edbc 17237
AnnaBridge 171:3a7713b1edbc 17238 #if defined(__ARMCC_VERSION)
AnnaBridge 171:3a7713b1edbc 17239 #pragma pop
AnnaBridge 171:3a7713b1edbc 17240 #elif defined(__CWCC__)
AnnaBridge 171:3a7713b1edbc 17241 #pragma pop
AnnaBridge 171:3a7713b1edbc 17242 #elif defined(__GNUC__)
AnnaBridge 171:3a7713b1edbc 17243 /* leave anonymous unions enabled */
AnnaBridge 171:3a7713b1edbc 17244 #elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge 171:3a7713b1edbc 17245 #pragma language=default
AnnaBridge 171:3a7713b1edbc 17246 #else
AnnaBridge 171:3a7713b1edbc 17247 #error Not supported compiler type
AnnaBridge 171:3a7713b1edbc 17248 #endif
AnnaBridge 171:3a7713b1edbc 17249
AnnaBridge 171:3a7713b1edbc 17250 /*!
AnnaBridge 171:3a7713b1edbc 17251 * @}
AnnaBridge 171:3a7713b1edbc 17252 */ /* end of group Peripheral_access_layer */
AnnaBridge 171:3a7713b1edbc 17253
AnnaBridge 171:3a7713b1edbc 17254
AnnaBridge 171:3a7713b1edbc 17255 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 17256 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
AnnaBridge 171:3a7713b1edbc 17257 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 17258
AnnaBridge 171:3a7713b1edbc 17259 /*!
AnnaBridge 171:3a7713b1edbc 17260 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
AnnaBridge 171:3a7713b1edbc 17261 * @{
AnnaBridge 171:3a7713b1edbc 17262 */
AnnaBridge 171:3a7713b1edbc 17263
AnnaBridge 171:3a7713b1edbc 17264 #if defined(__ARMCC_VERSION)
AnnaBridge 171:3a7713b1edbc 17265 #if (__ARMCC_VERSION >= 6010050)
AnnaBridge 171:3a7713b1edbc 17266 #pragma clang system_header
AnnaBridge 171:3a7713b1edbc 17267 #endif
AnnaBridge 171:3a7713b1edbc 17268 #elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge 171:3a7713b1edbc 17269 #pragma system_include
AnnaBridge 171:3a7713b1edbc 17270 #endif
AnnaBridge 171:3a7713b1edbc 17271
AnnaBridge 171:3a7713b1edbc 17272 /**
AnnaBridge 171:3a7713b1edbc 17273 * @brief Mask and left-shift a bit field value for use in a register bit range.
AnnaBridge 171:3a7713b1edbc 17274 * @param field Name of the register bit field.
AnnaBridge 171:3a7713b1edbc 17275 * @param value Value of the bit field.
AnnaBridge 171:3a7713b1edbc 17276 * @return Masked and shifted value.
AnnaBridge 171:3a7713b1edbc 17277 */
AnnaBridge 171:3a7713b1edbc 17278 #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
AnnaBridge 171:3a7713b1edbc 17279 /**
AnnaBridge 171:3a7713b1edbc 17280 * @brief Mask and right-shift a register value to extract a bit field value.
AnnaBridge 171:3a7713b1edbc 17281 * @param field Name of the register bit field.
AnnaBridge 171:3a7713b1edbc 17282 * @param value Value of the register.
AnnaBridge 171:3a7713b1edbc 17283 * @return Masked and shifted bit field value.
AnnaBridge 171:3a7713b1edbc 17284 */
AnnaBridge 171:3a7713b1edbc 17285 #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
AnnaBridge 171:3a7713b1edbc 17286
AnnaBridge 171:3a7713b1edbc 17287 /*!
AnnaBridge 171:3a7713b1edbc 17288 * @}
AnnaBridge 171:3a7713b1edbc 17289 */ /* end of group Bit_Field_Generic_Macros */
AnnaBridge 171:3a7713b1edbc 17290
AnnaBridge 171:3a7713b1edbc 17291
AnnaBridge 171:3a7713b1edbc 17292 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 17293 -- SDK Compatibility
AnnaBridge 171:3a7713b1edbc 17294 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 17295
AnnaBridge 171:3a7713b1edbc 17296 /*!
AnnaBridge 171:3a7713b1edbc 17297 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
AnnaBridge 171:3a7713b1edbc 17298 * @{
AnnaBridge 171:3a7713b1edbc 17299 */
AnnaBridge 171:3a7713b1edbc 17300
AnnaBridge 171:3a7713b1edbc 17301 #define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base)
AnnaBridge 171:3a7713b1edbc 17302 #define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base)
AnnaBridge 171:3a7713b1edbc 17303 #define FMC_PFB0CR_RFU_MASK FMC_PFB01CR_RFU_MASK
AnnaBridge 171:3a7713b1edbc 17304 #define FMC_PFB0CR_RFU_SHIFT FMC_PFB01CR_RFU_SHIFT
AnnaBridge 171:3a7713b1edbc 17305 #define FMC_PFB0CR_B0IPE_MASK FMC_PFB01CR_B0IPE_MASK
AnnaBridge 171:3a7713b1edbc 17306 #define FMC_PFB0CR_B0IPE_SHIFT FMC_PFB01CR_B0IPE_SHIFT
AnnaBridge 171:3a7713b1edbc 17307 #define FMC_PFB0CR_B0DPE_MASK FMC_PFB01CR_B0DPE_MASK
AnnaBridge 171:3a7713b1edbc 17308 #define FMC_PFB0CR_B0DPE_SHIFT FMC_PFB01CR_B0DPE_SHIFT
AnnaBridge 171:3a7713b1edbc 17309 #define FMC_PFB0CR_B0ICE_MASK FMC_PFB01CR_B0ICE_MASK
AnnaBridge 171:3a7713b1edbc 17310 #define FMC_PFB0CR_B0ICE_SHIFT FMC_PFB01CR_B0ICE_SHIFT
AnnaBridge 171:3a7713b1edbc 17311 #define FMC_PFB0CR_B0DCE_MASK FMC_PFB01CR_B0DCE_MASK
AnnaBridge 171:3a7713b1edbc 17312 #define FMC_PFB0CR_B0DCE_SHIFT FMC_PFB01CR_B0DCE_SHIFT
AnnaBridge 171:3a7713b1edbc 17313 #define FMC_PFB0CR_CRC_MASK FMC_PFB01CR_CRC_MASK
AnnaBridge 171:3a7713b1edbc 17314 #define FMC_PFB0CR_CRC_SHIFT FMC_PFB01CR_CRC_SHIFT
AnnaBridge 171:3a7713b1edbc 17315 #define FMC_PFB0CR_CRC(x) FMC_PFB01CR_CRC(x)
AnnaBridge 171:3a7713b1edbc 17316 #define FMC_PFB0CR_B0MW_MASK FMC_PFB01CR_B0MW_MASK
AnnaBridge 171:3a7713b1edbc 17317 #define FMC_PFB0CR_B0MW_SHIFT FMC_PFB01CR_B0MW_SHIFT
AnnaBridge 171:3a7713b1edbc 17318 #define FMC_PFB0CR_B0MW(x) FMC_PFB01CR_B0MW(x)
AnnaBridge 171:3a7713b1edbc 17319 #define FMC_PFB0CR_S_B_INV_MASK FMC_PFB01CR_S_B_INV_MASK
AnnaBridge 171:3a7713b1edbc 17320 #define FMC_PFB0CR_S_B_INV_SHIFT FMC_PFB01CR_S_B_INV_SHIFT
AnnaBridge 171:3a7713b1edbc 17321 #define FMC_PFB0CR_CINV_WAY_MASK FMC_PFB01CR_CINV_WAY_MASK
AnnaBridge 171:3a7713b1edbc 17322 #define FMC_PFB0CR_CINV_WAY_SHIFT FMC_PFB01CR_CINV_WAY_SHIFT
AnnaBridge 171:3a7713b1edbc 17323 #define FMC_PFB0CR_CINV_WAY(x) FMC_PFB01CR_CINV_WAY(x)
AnnaBridge 171:3a7713b1edbc 17324 #define FMC_PFB0CR_CLCK_WAY_MASK FMC_PFB01CR_CLCK_WAY_MASK
AnnaBridge 171:3a7713b1edbc 17325 #define FMC_PFB0CR_CLCK_WAY_SHIFT FMC_PFB01CR_CLCK_WAY_SHIFT
AnnaBridge 171:3a7713b1edbc 17326 #define FMC_PFB0CR_CLCK_WAY(x) FMC_PFB01CR_CLCK_WAY(x)
AnnaBridge 171:3a7713b1edbc 17327 #define FMC_PFB0CR_B0RWSC_MASK FMC_PFB01CR_B0RWSC_MASK
AnnaBridge 171:3a7713b1edbc 17328 #define FMC_PFB0CR_B0RWSC_SHIFT FMC_PFB01CR_B0RWSC_SHIFT
AnnaBridge 171:3a7713b1edbc 17329 #define FMC_PFB0CR_B0RWSC(x) FMC_PFB01CR_B0RWSC(x)
AnnaBridge 171:3a7713b1edbc 17330 #define FMC_PFB1CR_RFU_MASK FMC_PFB23CR_RFU_MASK
AnnaBridge 171:3a7713b1edbc 17331 #define FMC_PFB1CR_RFU_SHIFT FMC_PFB23CR_RFU_SHIFT
AnnaBridge 171:3a7713b1edbc 17332 #define FMC_PFB1CR_B1IPE_MASK FMC_PFB23CR_B1IPE_MASK
AnnaBridge 171:3a7713b1edbc 17333 #define FMC_PFB1CR_B1IPE_SHIFT FMC_PFB23CR_B1IPE_SHIFT
AnnaBridge 171:3a7713b1edbc 17334 #define FMC_PFB1CR_B1DPE_MASK FMC_PFB23CR_B1DPE_MASK
AnnaBridge 171:3a7713b1edbc 17335 #define FMC_PFB1CR_B1DPE_SHIFT FMC_PFB23CR_B1DPE_SHIFT
AnnaBridge 171:3a7713b1edbc 17336 #define FMC_PFB1CR_B1ICE_MASK FMC_PFB23CR_B1ICE_MASK
AnnaBridge 171:3a7713b1edbc 17337 #define FMC_PFB1CR_B1ICE_SHIFT FMC_PFB23CR_B1ICE_SHIFT
AnnaBridge 171:3a7713b1edbc 17338 #define FMC_PFB1CR_B1DCE_MASK FMC_PFB23CR_B1DCE_MASK
AnnaBridge 171:3a7713b1edbc 17339 #define FMC_PFB1CR_B1DCE_SHIFT FMC_PFB23CR_B1DCE_SHIFT
AnnaBridge 171:3a7713b1edbc 17340 #define FMC_PFB1CR_B1MW_MASK FMC_PFB23CR_B1MW_MASK
AnnaBridge 171:3a7713b1edbc 17341 #define FMC_PFB1CR_B1MW_SHIFT FMC_PFB23CR_B1MW_SHIFT
AnnaBridge 171:3a7713b1edbc 17342 #define FMC_PFB1CR_B1MW(x) FMC_PFB23CR_B1MW(x)
AnnaBridge 171:3a7713b1edbc 17343 #define FMC_PFB1CR_B1RWSC_MASK FMC_PFB23CR_B1RWSC_MASK
AnnaBridge 171:3a7713b1edbc 17344 #define FMC_PFB1CR_B1RWSC_SHIFT FMC_PFB23CR_B1RWSC_SHIFT
AnnaBridge 171:3a7713b1edbc 17345 #define FMC_PFB1CR_B1RWSC(x) FMC_PFB23CR_B1RWSC(x)
AnnaBridge 171:3a7713b1edbc 17346 #define LLWU_PE8_WUPE130_MASK LLWU_PE8_WUPE30_MASK
AnnaBridge 171:3a7713b1edbc 17347 #define LLWU_PE8_WUPE130_SHIFT LLWU_PE8_WUPE30_SHIFT
AnnaBridge 171:3a7713b1edbc 17348 #define LLWU_PE8_WUPE130(x) LLWU_PE8_WUPE30(x)
AnnaBridge 171:3a7713b1edbc 17349 #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
AnnaBridge 171:3a7713b1edbc 17350 #define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
AnnaBridge 171:3a7713b1edbc 17351 #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
AnnaBridge 171:3a7713b1edbc 17352 #define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
AnnaBridge 171:3a7713b1edbc 17353 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
AnnaBridge 171:3a7713b1edbc 17354 #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
AnnaBridge 171:3a7713b1edbc 17355 #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
AnnaBridge 171:3a7713b1edbc 17356 #define PMC_REGSC_BGBDS_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17357 #define PMC_REGSC_BGBDS_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17358 #define SDHC_VENDOR_EXTDMAEN_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17359 #define SDHC_VENDOR_EXTDMAEN_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17360 #define SDRAM_CTRL_COC_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17361 #define SDRAM_CTRL_COC_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17362 #define SDRAM_CTRL_NAM_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17363 #define SDRAM_CTRL_NAM_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17364 #define SMC_STOPCTRL_LPOPO_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17365 #define SMC_STOPCTRL_LPOPO_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17366 #define UART_C6_CP_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17367 #define UART_C6_CP_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17368 #define UART_C6_CE_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17369 #define UART_C6_CE_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17370 #define UART_C6_TX709_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17371 #define UART_C6_TX709_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17372 #define UART_C6_EN709_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17373 #define UART_C6_EN709_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17374 #define UART_PCTH_PCTH_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17375 #define UART_PCTH_PCTH_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17376 #define UART_PCTH_PCTH(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17377 #define UART_PCTL_PCTL_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17378 #define UART_PCTL_PCTL_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17379 #define UART_PCTL_PCTL(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17380 #define UART_IE0_CPTXIE_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17381 #define UART_IE0_CPTXIE_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17382 #define UART_IE0_CTXDIE_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17383 #define UART_IE0_CTXDIE_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17384 #define UART_IE0_RPLOFIE_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17385 #define UART_IE0_RPLOFIE_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17386 #define UART_SDTH_SDTH_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17387 #define UART_SDTH_SDTH_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17388 #define UART_SDTH_SDTH(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17389 #define UART_SDTL_SDTL_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17390 #define UART_SDTL_SDTL_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17391 #define UART_SDTL_SDTL(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17392 #define UART_PRE_PREAMBLE_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17393 #define UART_PRE_PREAMBLE_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17394 #define UART_PRE_PREAMBLE(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17395 #define UART_TPL_TPL_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17396 #define UART_TPL_TPL_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17397 #define UART_TPL_TPL(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17398 #define UART_IE_TXDIE_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17399 #define UART_IE_TXDIE_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17400 #define UART_IE_PSIE_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17401 #define UART_IE_PSIE_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17402 #define UART_IE_PCTEIE_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17403 #define UART_IE_PCTEIE_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17404 #define UART_IE_PTXIE_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17405 #define UART_IE_PTXIE_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17406 #define UART_IE_PRXIE_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17407 #define UART_IE_PRXIE_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17408 #define UART_IE_ISDIE_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17409 #define UART_IE_ISDIE_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17410 #define UART_IE_WBEIE_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17411 #define UART_IE_WBEIE_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17412 #define UART_IE_PEIE_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17413 #define UART_IE_PEIE_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17414 #define UART_WB_WBASE_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17415 #define UART_WB_WBASE_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17416 #define UART_WB_WBASE(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17417 #define UART_S3_TXFF_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17418 #define UART_S3_TXFF_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17419 #define UART_S3_PSF_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17420 #define UART_S3_PSF_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17421 #define UART_S3_PCTEF_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17422 #define UART_S3_PCTEF_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17423 #define UART_S3_PTXF_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17424 #define UART_S3_PTXF_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17425 #define UART_S3_PRXF_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17426 #define UART_S3_PRXF_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17427 #define UART_S3_ISD_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17428 #define UART_S3_ISD_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17429 #define UART_S3_WBEF_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17430 #define UART_S3_WBEF_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17431 #define UART_S3_PEF_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17432 #define UART_S3_PEF_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17433 #define UART_S4_FE_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17434 #define UART_S4_FE_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17435 #define UART_S4_TXDF_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17436 #define UART_S4_TXDF_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17437 #define UART_S4_CDET_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17438 #define UART_S4_CDET_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17439 #define UART_S4_CDET(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17440 #define UART_S4_RPLOF_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17441 #define UART_S4_RPLOF_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17442 #define UART_S4_LNF_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17443 #define UART_S4_LNF_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17444 #define UART_RPL_RPL_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17445 #define UART_RPL_RPL_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17446 #define UART_RPL_RPL(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17447 #define UART_RPREL_RPREL_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17448 #define UART_RPREL_RPREL_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17449 #define UART_RPREL_RPREL(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17450 #define UART_CPW_CPW_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17451 #define UART_CPW_CPW_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17452 #define UART_CPW_CPW(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17453 #define UART_RIDTH_RIDTH_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17454 #define UART_RIDTH_RIDTH_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17455 #define UART_RIDTH_RIDTH(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17456 #define UART_RIDTL_RIDTL_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17457 #define UART_RIDTL_RIDTL_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17458 #define UART_RIDTL_RIDTL(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17459 #define UART_TIDTH_TIDTH_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17460 #define UART_TIDTH_TIDTH_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17461 #define UART_TIDTH_TIDTH(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17462 #define UART_TIDTL_TIDTL_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17463 #define UART_TIDTL_TIDTL_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17464 #define UART_TIDTL_TIDTL(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17465 #define UART_RB1TH_RB1TH_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17466 #define UART_RB1TH_RB1TH_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17467 #define UART_RB1TH_RB1TH(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17468 #define UART_RB1TL_RB1TL_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17469 #define UART_RB1TL_RB1TL_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17470 #define UART_RB1TL_RB1TL(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17471 #define UART_TB1TH_TB1TH_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17472 #define UART_TB1TH_TB1TH_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17473 #define UART_TB1TH_TB1TH(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17474 #define UART_TB1TL_TB1TL_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17475 #define UART_TB1TL_TB1TL_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17476 #define UART_TB1TL_TB1TL(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17477 #define UART_PROG_REG_MIN_DMC1_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17478 #define UART_PROG_REG_MIN_DMC1_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17479 #define UART_PROG_REG_MIN_DMC1(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17480 #define UART_PROG_REG_LCV_LEN_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17481 #define UART_PROG_REG_LCV_LEN_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17482 #define UART_PROG_REG_LCV_LEN(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17483 #define UART_STATE_REG_SM_STATE_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17484 #define UART_STATE_REG_SM_STATE_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17485 #define UART_STATE_REG_SM_STATE(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17486 #define UART_STATE_REG_TX_STATE_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17487 #define UART_STATE_REG_TX_STATE_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17488 #define UART_STATE_REG_TX_STATE(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17489 #define USB_ADDINFO_IRQNUM_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17490 #define USB_ADDINFO_IRQNUM_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17491 #define USB_ADDINFO_IRQNUM(x) This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17492 #define USBHS_USBSTS_ULPII_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17493 #define USBHS_USBSTS_ULPII_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17494 #define USBHS_USBINTR_ULPIE_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17495 #define USBHS_USBINTR_ULPIE_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17496 #define USBPHY_CTRL_CLK_SWITCH_ENJ_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17497 #define USBPHY_CTRL_CLK_SWITCH_ENJ_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17498 #define USBPHY_CTRL_SET_CLK_SWITCH_ENJ_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17499 #define USBPHY_CTRL_SET_CLK_SWITCH_ENJ_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17500 #define USBPHY_CTRL_CLR_CLK_SWITCH_ENJ_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17501 #define USBPHY_CTRL_CLR_CLK_SWITCH_ENJ_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17502 #define USBPHY_CTRL_TOG_CLK_SWITCH_ENJ_MASK This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17503 #define USBPHY_CTRL_TOG_CLK_SWITCH_ENJ_SHIFT This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17504 #define MCM_ISR_REG(base) MCM_ISCR_REG(base)
AnnaBridge 171:3a7713b1edbc 17505 #define MCM_ISR_IRQ_MASK MCM_ISCR_IRQ_MASK
AnnaBridge 171:3a7713b1edbc 17506 #define MCM_ISR_IRQ_SHIFT MCM_ISCR_IRQ_SHIFT
AnnaBridge 171:3a7713b1edbc 17507 #define MCM_ISR_NMI_MASK MCM_ISCR_NMI_MASK
AnnaBridge 171:3a7713b1edbc 17508 #define MCM_ISR_NMI_SHIFT MCM_ISCR_NMI_SHIFT
AnnaBridge 171:3a7713b1edbc 17509 #define MCM_ISR_DHREQ_MASK MCM_ISCR_DHREQ_MASK
AnnaBridge 171:3a7713b1edbc 17510 #define MCM_ISR_DHREQ_SHIFT MCM_ISCR_DHREQ_SHIFT
AnnaBridge 171:3a7713b1edbc 17511 #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
AnnaBridge 171:3a7713b1edbc 17512 #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
AnnaBridge 171:3a7713b1edbc 17513 #define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
AnnaBridge 171:3a7713b1edbc 17514 #define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
AnnaBridge 171:3a7713b1edbc 17515 #define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
AnnaBridge 171:3a7713b1edbc 17516 #define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
AnnaBridge 171:3a7713b1edbc 17517 #define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
AnnaBridge 171:3a7713b1edbc 17518 #define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
AnnaBridge 171:3a7713b1edbc 17519 #define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
AnnaBridge 171:3a7713b1edbc 17520 #define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
AnnaBridge 171:3a7713b1edbc 17521 #define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
AnnaBridge 171:3a7713b1edbc 17522 #define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
AnnaBridge 171:3a7713b1edbc 17523 #define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
AnnaBridge 171:3a7713b1edbc 17524 #define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
AnnaBridge 171:3a7713b1edbc 17525 #define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
AnnaBridge 171:3a7713b1edbc 17526 #define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
AnnaBridge 171:3a7713b1edbc 17527 #define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
AnnaBridge 171:3a7713b1edbc 17528 #define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
AnnaBridge 171:3a7713b1edbc 17529 #define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
AnnaBridge 171:3a7713b1edbc 17530 #define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
AnnaBridge 171:3a7713b1edbc 17531 #define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
AnnaBridge 171:3a7713b1edbc 17532 #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
AnnaBridge 171:3a7713b1edbc 17533 #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
AnnaBridge 171:3a7713b1edbc 17534 #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
AnnaBridge 171:3a7713b1edbc 17535 #define DMAMUX0 DMAMUX
AnnaBridge 171:3a7713b1edbc 17536 #define DSPI0 SPI0
AnnaBridge 171:3a7713b1edbc 17537 #define DSPI1 SPI1
AnnaBridge 171:3a7713b1edbc 17538 #define DSPI2 SPI2
AnnaBridge 171:3a7713b1edbc 17539 #define FLEXCAN0 CAN0
AnnaBridge 171:3a7713b1edbc 17540 #define FLEXCAN1 CAN1
AnnaBridge 171:3a7713b1edbc 17541 #define PTA_BASE GPIOA_BASE
AnnaBridge 171:3a7713b1edbc 17542 #define PTA GPIOA
AnnaBridge 171:3a7713b1edbc 17543 #define PTB_BASE GPIOB_BASE
AnnaBridge 171:3a7713b1edbc 17544 #define PTB GPIOB
AnnaBridge 171:3a7713b1edbc 17545 #define PTC_BASE GPIOC_BASE
AnnaBridge 171:3a7713b1edbc 17546 #define PTC GPIOC
AnnaBridge 171:3a7713b1edbc 17547 #define PTD_BASE GPIOD_BASE
AnnaBridge 171:3a7713b1edbc 17548 #define PTD GPIOD
AnnaBridge 171:3a7713b1edbc 17549 #define PTE_BASE GPIOE_BASE
AnnaBridge 171:3a7713b1edbc 17550 #define PTE GPIOE
AnnaBridge 171:3a7713b1edbc 17551 #define Watchdog_IRQn WDOG_EWM_IRQn
AnnaBridge 171:3a7713b1edbc 17552 #define Watchdog_IRQHandler WDOG_EWM_IRQHandler
AnnaBridge 171:3a7713b1edbc 17553 #define LPTimer_IRQn LPTMR0_IRQn
AnnaBridge 171:3a7713b1edbc 17554 #define LPTimer_IRQHandler LPTMR0_IRQHandler
AnnaBridge 171:3a7713b1edbc 17555 #define UART0_LON_IRQn This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17556 #define UART0_LON_IRQHandler This_symbol_has_been_deprecated
AnnaBridge 171:3a7713b1edbc 17557 #define LLW_IRQn LLWU_IRQn
AnnaBridge 171:3a7713b1edbc 17558 #define LLW_IRQHandler LLWU_IRQHandler
AnnaBridge 171:3a7713b1edbc 17559
AnnaBridge 171:3a7713b1edbc 17560 /*!
AnnaBridge 171:3a7713b1edbc 17561 * @}
AnnaBridge 171:3a7713b1edbc 17562 */ /* end of group SDK_Compatibility_Symbols */
AnnaBridge 171:3a7713b1edbc 17563
AnnaBridge 171:3a7713b1edbc 17564
AnnaBridge 171:3a7713b1edbc 17565 #endif /* _MK66F18_H_ */
AnnaBridge 171:3a7713b1edbc 17566