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TARGET_FF_LPC546XX/TOOLCHAIN_GCC_ARM/fsl_reset.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 171:3a7713b1edbc | 1 | /* |
AnnaBridge | 171:3a7713b1edbc | 2 | * The Clear BSD License |
AnnaBridge | 171:3a7713b1edbc | 3 | * Copyright (c) 2016, Freescale Semiconductor, Inc. |
AnnaBridge | 171:3a7713b1edbc | 4 | * Copyright (c) 2016, NXP |
AnnaBridge | 171:3a7713b1edbc | 5 | * All rights reserved. |
AnnaBridge | 171:3a7713b1edbc | 6 | * |
AnnaBridge | 171:3a7713b1edbc | 7 | * |
AnnaBridge | 171:3a7713b1edbc | 8 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 9 | * are permitted (subject to the limitations in the disclaimer below) provided |
AnnaBridge | 171:3a7713b1edbc | 10 | * that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 11 | * |
AnnaBridge | 171:3a7713b1edbc | 12 | * o Redistributions of source code must retain the above copyright notice, this list |
AnnaBridge | 171:3a7713b1edbc | 13 | * of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 14 | * |
AnnaBridge | 171:3a7713b1edbc | 15 | * o Redistributions in binary form must reproduce the above copyright notice, this |
AnnaBridge | 171:3a7713b1edbc | 16 | * list of conditions and the following disclaimer in the documentation and/or |
AnnaBridge | 171:3a7713b1edbc | 17 | * other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 18 | * |
AnnaBridge | 171:3a7713b1edbc | 19 | * o Neither the name of copyright holder nor the names of its |
AnnaBridge | 171:3a7713b1edbc | 20 | * contributors may be used to endorse or promote products derived from this |
AnnaBridge | 171:3a7713b1edbc | 21 | * software without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 22 | * |
AnnaBridge | 171:3a7713b1edbc | 23 | * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. |
AnnaBridge | 171:3a7713b1edbc | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
AnnaBridge | 171:3a7713b1edbc | 25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
AnnaBridge | 171:3a7713b1edbc | 26 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
AnnaBridge | 171:3a7713b1edbc | 28 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
AnnaBridge | 171:3a7713b1edbc | 29 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
AnnaBridge | 171:3a7713b1edbc | 30 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
AnnaBridge | 171:3a7713b1edbc | 31 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
AnnaBridge | 171:3a7713b1edbc | 32 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
AnnaBridge | 171:3a7713b1edbc | 33 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 34 | */ |
AnnaBridge | 171:3a7713b1edbc | 35 | |
AnnaBridge | 171:3a7713b1edbc | 36 | #ifndef _FSL_RESET_H_ |
AnnaBridge | 171:3a7713b1edbc | 37 | #define _FSL_RESET_H_ |
AnnaBridge | 171:3a7713b1edbc | 38 | |
AnnaBridge | 171:3a7713b1edbc | 39 | #include <assert.h> |
AnnaBridge | 171:3a7713b1edbc | 40 | #include <stdbool.h> |
AnnaBridge | 171:3a7713b1edbc | 41 | #include <stdint.h> |
AnnaBridge | 171:3a7713b1edbc | 42 | #include <string.h> |
AnnaBridge | 171:3a7713b1edbc | 43 | #include "fsl_device_registers.h" |
AnnaBridge | 171:3a7713b1edbc | 44 | |
AnnaBridge | 171:3a7713b1edbc | 45 | /*! |
AnnaBridge | 171:3a7713b1edbc | 46 | * @addtogroup ksdk_common |
AnnaBridge | 171:3a7713b1edbc | 47 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 48 | */ |
AnnaBridge | 171:3a7713b1edbc | 49 | |
AnnaBridge | 171:3a7713b1edbc | 50 | /******************************************************************************* |
AnnaBridge | 171:3a7713b1edbc | 51 | * Definitions |
AnnaBridge | 171:3a7713b1edbc | 52 | ******************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 53 | |
AnnaBridge | 171:3a7713b1edbc | 54 | /*! @name Driver version */ |
AnnaBridge | 171:3a7713b1edbc | 55 | /*@{*/ |
AnnaBridge | 171:3a7713b1edbc | 56 | /*! @brief reset driver version 2.0.0. */ |
AnnaBridge | 171:3a7713b1edbc | 57 | #define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) |
AnnaBridge | 171:3a7713b1edbc | 58 | /*@}*/ |
AnnaBridge | 171:3a7713b1edbc | 59 | |
AnnaBridge | 171:3a7713b1edbc | 60 | /*! |
AnnaBridge | 171:3a7713b1edbc | 61 | * @brief Enumeration for peripheral reset control bits |
AnnaBridge | 171:3a7713b1edbc | 62 | * |
AnnaBridge | 171:3a7713b1edbc | 63 | * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers |
AnnaBridge | 171:3a7713b1edbc | 64 | */ |
AnnaBridge | 171:3a7713b1edbc | 65 | typedef enum _SYSCON_RSTn |
AnnaBridge | 171:3a7713b1edbc | 66 | { |
AnnaBridge | 171:3a7713b1edbc | 67 | kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ |
AnnaBridge | 171:3a7713b1edbc | 68 | kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ |
AnnaBridge | 171:3a7713b1edbc | 69 | kEEPROM_RST_SHIFT_RSTn = 0 | 9U, /**< EEPROM reset control */ |
AnnaBridge | 171:3a7713b1edbc | 70 | kSPIFI_RST_SHIFT_RSTn = 0 | 10U, /**< SPIFI reset control */ |
AnnaBridge | 171:3a7713b1edbc | 71 | kMUX_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux reset control */ |
AnnaBridge | 171:3a7713b1edbc | 72 | kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ |
AnnaBridge | 171:3a7713b1edbc | 73 | kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 74 | kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 75 | kGPIO2_RST_SHIFT_RSTn = 0 | 16U, /**< GPIO2 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 76 | kGPIO3_RST_SHIFT_RSTn = 0 | 17U, /**< GPIO3 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 77 | kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ |
AnnaBridge | 171:3a7713b1edbc | 78 | kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ |
AnnaBridge | 171:3a7713b1edbc | 79 | kDMA_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ |
AnnaBridge | 171:3a7713b1edbc | 80 | kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ |
AnnaBridge | 171:3a7713b1edbc | 81 | kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ |
AnnaBridge | 171:3a7713b1edbc | 82 | kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 83 | |
AnnaBridge | 171:3a7713b1edbc | 84 | kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ |
AnnaBridge | 171:3a7713b1edbc | 85 | kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ |
AnnaBridge | 171:3a7713b1edbc | 86 | kMCAN0_RST_SHIFT_RSTn = 65536 | 7U, /**< MCAN0 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 87 | kMCAN1_RST_SHIFT_RSTn = 65536 | 8U, /**< MCAN1 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 88 | kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ |
AnnaBridge | 171:3a7713b1edbc | 89 | kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 90 | kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 91 | kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 92 | kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 93 | kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 94 | kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 95 | kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 96 | kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 97 | kDMIC_RST_SHIFT_RSTn = 65536 | 19U, /**< Digital microphone interface reset control */ |
AnnaBridge | 171:3a7713b1edbc | 98 | kCT32B2_RST_SHIFT_RSTn = 65536 | 22U, /**< CT32B2 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 99 | kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0D reset control */ |
AnnaBridge | 171:3a7713b1edbc | 100 | kCT32B0_RST_SHIFT_RSTn = 65536 | 26U, /**< CT32B0 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 101 | kCT32B1_RST_SHIFT_RSTn = 65536 | 27U, /**< CT32B1 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 102 | |
AnnaBridge | 171:3a7713b1edbc | 103 | kLCD_RST_SHIFT_RSTn = 131072 | 2U, /**< LCD reset control */ |
AnnaBridge | 171:3a7713b1edbc | 104 | kSDIO_RST_SHIFT_RSTn = 131072 | 3U, /**< SDIO reset control */ |
AnnaBridge | 171:3a7713b1edbc | 105 | kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USB1H reset control */ |
AnnaBridge | 171:3a7713b1edbc | 106 | kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USB1D reset control */ |
AnnaBridge | 171:3a7713b1edbc | 107 | kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB1RAM reset control */ |
AnnaBridge | 171:3a7713b1edbc | 108 | kEMC_RST_SHIFT_RSTn = 131072 | 7U, /**< EMC reset control */ |
AnnaBridge | 171:3a7713b1edbc | 109 | kETH_RST_SHIFT_RSTn = 131072 | 8U, /**< ETH reset control */ |
AnnaBridge | 171:3a7713b1edbc | 110 | kGPIO4_RST_SHIFT_RSTn = 131072 | 9U, /**< GPIO4 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 111 | kGPIO5_RST_SHIFT_RSTn = 131072 | 10U, /**< GPIO5 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 112 | kAES_RST_SHIFT_RSTn = 131072 | 11U, /**< AES reset control */ |
AnnaBridge | 171:3a7713b1edbc | 113 | kOTP_RST_SHIFT_RSTn = 131072 | 12U, /**< OTP reset control */ |
AnnaBridge | 171:3a7713b1edbc | 114 | kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */ |
AnnaBridge | 171:3a7713b1edbc | 115 | kFC8_RST_SHIFT_RSTn = 131072 | 14U, /**< Flexcomm Interface 8 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 116 | kFC9_RST_SHIFT_RSTn = 131072 | 15U, /**< Flexcomm Interface 9 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 117 | kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */ |
AnnaBridge | 171:3a7713b1edbc | 118 | kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */ |
AnnaBridge | 171:3a7713b1edbc | 119 | kSHA_RST_SHIFT_RSTn = 131072 | 18U, /**< SHA reset control */ |
AnnaBridge | 171:3a7713b1edbc | 120 | kSC0_RST_SHIFT_RSTn = 131072 | 19U, /**< SC0 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 121 | kSC1_RST_SHIFT_RSTn = 131072 | 20U, /**< SC1 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 122 | |
AnnaBridge | 171:3a7713b1edbc | 123 | kCT32B3_RST_SHIFT_RSTn = 67108864 | 13U, /**< CT32B3 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 124 | kCT32B4_RST_SHIFT_RSTn = 67108864 | 14U, /**< CT32B4 reset control */ |
AnnaBridge | 171:3a7713b1edbc | 125 | } SYSCON_RSTn_t; |
AnnaBridge | 171:3a7713b1edbc | 126 | |
AnnaBridge | 171:3a7713b1edbc | 127 | /** Array initializers with peripheral reset bits **/ |
AnnaBridge | 171:3a7713b1edbc | 128 | #define ADC_RSTS \ |
AnnaBridge | 171:3a7713b1edbc | 129 | { \ |
AnnaBridge | 171:3a7713b1edbc | 130 | kADC0_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 131 | } /* Reset bits for ADC peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 132 | #define AES_RSTS \ |
AnnaBridge | 171:3a7713b1edbc | 133 | { \ |
AnnaBridge | 171:3a7713b1edbc | 134 | kAES_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 135 | } /* Reset bits for AES peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 136 | #define CRC_RSTS \ |
AnnaBridge | 171:3a7713b1edbc | 137 | { \ |
AnnaBridge | 171:3a7713b1edbc | 138 | kCRC_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 139 | } /* Reset bits for CRC peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 140 | #define CTIMER_RSTS \ |
AnnaBridge | 171:3a7713b1edbc | 141 | { \ |
AnnaBridge | 171:3a7713b1edbc | 142 | kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \ |
AnnaBridge | 171:3a7713b1edbc | 143 | kCT32B4_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 144 | } /* Reset bits for CTIMER peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 145 | #define DMA_RSTS \ |
AnnaBridge | 171:3a7713b1edbc | 146 | { \ |
AnnaBridge | 171:3a7713b1edbc | 147 | kDMA_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 148 | } /* Reset bits for DMA peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 149 | #define DMIC_RSTS \ |
AnnaBridge | 171:3a7713b1edbc | 150 | { \ |
AnnaBridge | 171:3a7713b1edbc | 151 | kDMIC_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 152 | } /* Reset bits for DMIC peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 153 | #define EMC_RSTS \ |
AnnaBridge | 171:3a7713b1edbc | 154 | { \ |
AnnaBridge | 171:3a7713b1edbc | 155 | kEMC_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 156 | } /* Reset bits for EMC peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 157 | #define ETH_RST \ |
AnnaBridge | 171:3a7713b1edbc | 158 | { \ |
AnnaBridge | 171:3a7713b1edbc | 159 | kETH_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 160 | } /* Reset bits for EMC peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 161 | #define FLEXCOMM_RSTS \ |
AnnaBridge | 171:3a7713b1edbc | 162 | { \ |
AnnaBridge | 171:3a7713b1edbc | 163 | kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ |
AnnaBridge | 171:3a7713b1edbc | 164 | kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kFC8_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 165 | } /* Reset bits for FLEXCOMM peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 166 | #define GINT_RSTS \ |
AnnaBridge | 171:3a7713b1edbc | 167 | { \ |
AnnaBridge | 171:3a7713b1edbc | 168 | kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 169 | } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ |
AnnaBridge | 171:3a7713b1edbc | 170 | #define GPIO_RSTS \ |
AnnaBridge | 171:3a7713b1edbc | 171 | { \ |
AnnaBridge | 171:3a7713b1edbc | 172 | kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \ |
AnnaBridge | 171:3a7713b1edbc | 173 | kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 174 | } /* Reset bits for GPIO peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 175 | #define INPUTMUX_RSTS \ |
AnnaBridge | 171:3a7713b1edbc | 176 | { \ |
AnnaBridge | 171:3a7713b1edbc | 177 | kMUX_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 178 | } /* Reset bits for INPUTMUX peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 179 | #define IOCON_RSTS \ |
AnnaBridge | 171:3a7713b1edbc | 180 | { \ |
AnnaBridge | 171:3a7713b1edbc | 181 | kIOCON_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 182 | } /* Reset bits for IOCON peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 183 | #define FLASH_RSTS \ |
AnnaBridge | 171:3a7713b1edbc | 184 | { \ |
AnnaBridge | 171:3a7713b1edbc | 185 | kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 186 | } /* Reset bits for Flash peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 187 | #define LCD_RSTS \ |
AnnaBridge | 171:3a7713b1edbc | 188 | { \ |
AnnaBridge | 171:3a7713b1edbc | 189 | kLCD_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 190 | } /* Reset bits for LCD peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 191 | #define MRT_RSTS \ |
AnnaBridge | 171:3a7713b1edbc | 192 | { \ |
AnnaBridge | 171:3a7713b1edbc | 193 | kMRT_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 194 | } /* Reset bits for MRT peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 195 | #define MCAN_RSTS \ |
AnnaBridge | 171:3a7713b1edbc | 196 | { \ |
AnnaBridge | 171:3a7713b1edbc | 197 | kMCAN0_RST_SHIFT_RSTn,kMCAN1_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 198 | } /* Reset bits for MCAN0&MACN1 peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 199 | #define OTP_RSTS \ |
AnnaBridge | 171:3a7713b1edbc | 200 | { \ |
AnnaBridge | 171:3a7713b1edbc | 201 | kOTP_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 202 | } /* Reset bits for OTP peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 203 | #define PINT_RSTS \ |
AnnaBridge | 171:3a7713b1edbc | 204 | { \ |
AnnaBridge | 171:3a7713b1edbc | 205 | kPINT_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 206 | } /* Reset bits for PINT peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 207 | #define RNG_RSTS \ |
AnnaBridge | 171:3a7713b1edbc | 208 | { \ |
AnnaBridge | 171:3a7713b1edbc | 209 | kRNG_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 210 | } /* Reset bits for RNG peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 211 | #define SDIO_RST \ |
AnnaBridge | 171:3a7713b1edbc | 212 | { \ |
AnnaBridge | 171:3a7713b1edbc | 213 | kSDIO_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 214 | } /* Reset bits for SDIO peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 215 | #define SCT_RSTS \ |
AnnaBridge | 171:3a7713b1edbc | 216 | { \ |
AnnaBridge | 171:3a7713b1edbc | 217 | kSCT0_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 218 | } /* Reset bits for SCT peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 219 | #define SHA_RST \ |
AnnaBridge | 171:3a7713b1edbc | 220 | { \ |
AnnaBridge | 171:3a7713b1edbc | 221 | kSHA_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 222 | } /* Reset bits for SHA peripheral */ |
AnnaBridge | 172:65be27845400 | 223 | #define SPIFI_RSTS \ |
AnnaBridge | 172:65be27845400 | 224 | { \ |
AnnaBridge | 172:65be27845400 | 225 | kSPIFI_RST_SHIFT_RSTn \ |
AnnaBridge | 172:65be27845400 | 226 | } /* Reset bits for SPIFI peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 227 | #define USB0D_RST \ |
AnnaBridge | 171:3a7713b1edbc | 228 | { \ |
AnnaBridge | 171:3a7713b1edbc | 229 | kUSB0D_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 230 | } /* Reset bits for USB0D peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 231 | #define USB0HMR_RST \ |
AnnaBridge | 171:3a7713b1edbc | 232 | { \ |
AnnaBridge | 171:3a7713b1edbc | 233 | kUSB0HMR_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 234 | } /* Reset bits for USB0HMR peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 235 | #define USB0HSL_RST \ |
AnnaBridge | 171:3a7713b1edbc | 236 | { \ |
AnnaBridge | 171:3a7713b1edbc | 237 | kUSB0HSL_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 238 | } /* Reset bits for USB0HSL peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 239 | #define USB1H_RST \ |
AnnaBridge | 171:3a7713b1edbc | 240 | { \ |
AnnaBridge | 171:3a7713b1edbc | 241 | kUSB1H_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 242 | } /* Reset bits for USB1H peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 243 | #define USB1D_RST \ |
AnnaBridge | 171:3a7713b1edbc | 244 | { \ |
AnnaBridge | 171:3a7713b1edbc | 245 | kUSB1D_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 246 | } /* Reset bits for USB1D peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 247 | #define USB1RAM_RST \ |
AnnaBridge | 171:3a7713b1edbc | 248 | { \ |
AnnaBridge | 171:3a7713b1edbc | 249 | kUSB1RAM_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 250 | } /* Reset bits for USB1RAM peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 251 | #define UTICK_RSTS \ |
AnnaBridge | 171:3a7713b1edbc | 252 | { \ |
AnnaBridge | 171:3a7713b1edbc | 253 | kUTICK_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 254 | } /* Reset bits for UTICK peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 255 | #define WWDT_RSTS \ |
AnnaBridge | 171:3a7713b1edbc | 256 | { \ |
AnnaBridge | 171:3a7713b1edbc | 257 | kWWDT_RST_SHIFT_RSTn \ |
AnnaBridge | 171:3a7713b1edbc | 258 | } /* Reset bits for WWDT peripheral */ |
AnnaBridge | 171:3a7713b1edbc | 259 | |
AnnaBridge | 171:3a7713b1edbc | 260 | typedef SYSCON_RSTn_t reset_ip_name_t; |
AnnaBridge | 171:3a7713b1edbc | 261 | |
AnnaBridge | 171:3a7713b1edbc | 262 | /******************************************************************************* |
AnnaBridge | 171:3a7713b1edbc | 263 | * API |
AnnaBridge | 171:3a7713b1edbc | 264 | ******************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 265 | #if defined(__cplusplus) |
AnnaBridge | 171:3a7713b1edbc | 266 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 267 | #endif |
AnnaBridge | 171:3a7713b1edbc | 268 | |
AnnaBridge | 171:3a7713b1edbc | 269 | /*! |
AnnaBridge | 171:3a7713b1edbc | 270 | * @brief Assert reset to peripheral. |
AnnaBridge | 171:3a7713b1edbc | 271 | * |
AnnaBridge | 171:3a7713b1edbc | 272 | * Asserts reset signal to specified peripheral module. |
AnnaBridge | 171:3a7713b1edbc | 273 | * |
AnnaBridge | 171:3a7713b1edbc | 274 | * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register |
AnnaBridge | 171:3a7713b1edbc | 275 | * and reset bit position in the reset register. |
AnnaBridge | 171:3a7713b1edbc | 276 | */ |
AnnaBridge | 171:3a7713b1edbc | 277 | void RESET_SetPeripheralReset(reset_ip_name_t peripheral); |
AnnaBridge | 171:3a7713b1edbc | 278 | |
AnnaBridge | 171:3a7713b1edbc | 279 | /*! |
AnnaBridge | 171:3a7713b1edbc | 280 | * @brief Clear reset to peripheral. |
AnnaBridge | 171:3a7713b1edbc | 281 | * |
AnnaBridge | 171:3a7713b1edbc | 282 | * Clears reset signal to specified peripheral module, allows it to operate. |
AnnaBridge | 171:3a7713b1edbc | 283 | * |
AnnaBridge | 171:3a7713b1edbc | 284 | * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register |
AnnaBridge | 171:3a7713b1edbc | 285 | * and reset bit position in the reset register. |
AnnaBridge | 171:3a7713b1edbc | 286 | */ |
AnnaBridge | 171:3a7713b1edbc | 287 | void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); |
AnnaBridge | 171:3a7713b1edbc | 288 | |
AnnaBridge | 171:3a7713b1edbc | 289 | /*! |
AnnaBridge | 171:3a7713b1edbc | 290 | * @brief Reset peripheral module. |
AnnaBridge | 171:3a7713b1edbc | 291 | * |
AnnaBridge | 171:3a7713b1edbc | 292 | * Reset peripheral module. |
AnnaBridge | 171:3a7713b1edbc | 293 | * |
AnnaBridge | 171:3a7713b1edbc | 294 | * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register |
AnnaBridge | 171:3a7713b1edbc | 295 | * and reset bit position in the reset register. |
AnnaBridge | 171:3a7713b1edbc | 296 | */ |
AnnaBridge | 171:3a7713b1edbc | 297 | void RESET_PeripheralReset(reset_ip_name_t peripheral); |
AnnaBridge | 171:3a7713b1edbc | 298 | |
AnnaBridge | 171:3a7713b1edbc | 299 | #if defined(__cplusplus) |
AnnaBridge | 171:3a7713b1edbc | 300 | } |
AnnaBridge | 171:3a7713b1edbc | 301 | #endif |
AnnaBridge | 171:3a7713b1edbc | 302 | |
AnnaBridge | 171:3a7713b1edbc | 303 | /*! @} */ |
AnnaBridge | 171:3a7713b1edbc | 304 | |
AnnaBridge | 171:3a7713b1edbc | 305 | #endif /* _FSL_RESET_H_ */ |