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TARGET_FF_LPC546XX/TOOLCHAIN_GCC_ARM/fsl_inputmux_connections.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 171:3a7713b1edbc | 1 | /* |
AnnaBridge | 171:3a7713b1edbc | 2 | * The Clear BSD License |
AnnaBridge | 171:3a7713b1edbc | 3 | * Copyright (c) 2016, Freescale Semiconductor, Inc. |
AnnaBridge | 171:3a7713b1edbc | 4 | * Copyright (c) 2017, NXP |
AnnaBridge | 171:3a7713b1edbc | 5 | * All rights reserved. |
AnnaBridge | 171:3a7713b1edbc | 6 | * |
AnnaBridge | 171:3a7713b1edbc | 7 | * |
AnnaBridge | 171:3a7713b1edbc | 8 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 9 | * are permitted (subject to the limitations in the disclaimer below) provided |
AnnaBridge | 171:3a7713b1edbc | 10 | * that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 11 | * |
AnnaBridge | 171:3a7713b1edbc | 12 | * o Redistributions of source code must retain the above copyright notice, this list |
AnnaBridge | 171:3a7713b1edbc | 13 | * of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 14 | * |
AnnaBridge | 171:3a7713b1edbc | 15 | * o Redistributions in binary form must reproduce the above copyright notice, this |
AnnaBridge | 171:3a7713b1edbc | 16 | * list of conditions and the following disclaimer in the documentation and/or |
AnnaBridge | 171:3a7713b1edbc | 17 | * other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 18 | * |
AnnaBridge | 171:3a7713b1edbc | 19 | * o Neither the name of copyright holder nor the names of its |
AnnaBridge | 171:3a7713b1edbc | 20 | * contributors may be used to endorse or promote products derived from this |
AnnaBridge | 171:3a7713b1edbc | 21 | * software without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 22 | * |
AnnaBridge | 171:3a7713b1edbc | 23 | * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. |
AnnaBridge | 171:3a7713b1edbc | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
AnnaBridge | 171:3a7713b1edbc | 25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
AnnaBridge | 171:3a7713b1edbc | 26 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
AnnaBridge | 171:3a7713b1edbc | 28 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
AnnaBridge | 171:3a7713b1edbc | 29 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
AnnaBridge | 171:3a7713b1edbc | 30 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
AnnaBridge | 171:3a7713b1edbc | 31 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
AnnaBridge | 171:3a7713b1edbc | 32 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
AnnaBridge | 171:3a7713b1edbc | 33 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 34 | */ |
AnnaBridge | 171:3a7713b1edbc | 35 | |
AnnaBridge | 171:3a7713b1edbc | 36 | #ifndef _FSL_INPUTMUX_CONNECTIONS_ |
AnnaBridge | 171:3a7713b1edbc | 37 | #define _FSL_INPUTMUX_CONNECTIONS_ |
AnnaBridge | 171:3a7713b1edbc | 38 | |
AnnaBridge | 171:3a7713b1edbc | 39 | /******************************************************************************* |
AnnaBridge | 171:3a7713b1edbc | 40 | * Definitions |
AnnaBridge | 171:3a7713b1edbc | 41 | ******************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 42 | |
AnnaBridge | 171:3a7713b1edbc | 43 | /*! |
AnnaBridge | 171:3a7713b1edbc | 44 | * @addtogroup inputmux_driver |
AnnaBridge | 171:3a7713b1edbc | 45 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 46 | */ |
AnnaBridge | 171:3a7713b1edbc | 47 | |
AnnaBridge | 171:3a7713b1edbc | 48 | /*! |
AnnaBridge | 171:3a7713b1edbc | 49 | * @name Input multiplexing connections |
AnnaBridge | 171:3a7713b1edbc | 50 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 51 | */ |
AnnaBridge | 171:3a7713b1edbc | 52 | |
AnnaBridge | 171:3a7713b1edbc | 53 | /*! @brief Periphinmux IDs */ |
AnnaBridge | 171:3a7713b1edbc | 54 | #define SCT0_PMUX_ID 0x00U |
AnnaBridge | 171:3a7713b1edbc | 55 | #define PINTSEL_PMUX_ID 0xC0U |
AnnaBridge | 171:3a7713b1edbc | 56 | #define DMA_TRIG0_PMUX_ID 0xE0U |
AnnaBridge | 171:3a7713b1edbc | 57 | #define DMA_OTRIG_PMUX_ID 0x160U |
AnnaBridge | 171:3a7713b1edbc | 58 | #define FREQMEAS_PMUX_ID 0x180U |
AnnaBridge | 171:3a7713b1edbc | 59 | #define PMUX_SHIFT 20U |
AnnaBridge | 171:3a7713b1edbc | 60 | |
AnnaBridge | 171:3a7713b1edbc | 61 | /*! @brief INPUTMUX connections type */ |
AnnaBridge | 171:3a7713b1edbc | 62 | typedef enum _inputmux_connection_t |
AnnaBridge | 171:3a7713b1edbc | 63 | { |
AnnaBridge | 171:3a7713b1edbc | 64 | /*!< SCT INMUX. */ |
AnnaBridge | 171:3a7713b1edbc | 65 | kINPUTMUX_SctGpi0ToSct0 = 0U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 66 | kINPUTMUX_SctGpi1ToSct0 = 1U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 67 | kINPUTMUX_SctGpi2ToSct0 = 2U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 68 | kINPUTMUX_SctGpi3ToSct0 = 3U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 69 | kINPUTMUX_SctGpi4ToSct0 = 4U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 70 | kINPUTMUX_SctGpi5ToSct0 = 5U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 71 | kINPUTMUX_SctGpi6ToSct0 = 6U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 72 | kINPUTMUX_SctGpi7ToSct0 = 7U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 73 | kINPUTMUX_T0Out0ToSct0 = 8U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 74 | kINPUTMUX_T1Out0ToSct0 = 9U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 75 | kINPUTMUX_T2Out0ToSct0 = 10U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 76 | kINPUTMUX_T3Out0ToSct0 = 11U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 77 | kINPUTMUX_T4Out0ToSct0 = 12U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 78 | kINPUTMUX_AdcThcmpIrqToSct0 = 13U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 79 | kINPUTMUX_GpioIntBmatchToSct0 = 14U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 80 | kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 81 | kINPUTMUX_Usb1FrameToggleToSct0 = 16U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 82 | kINPUTMUX_ArmTxevToSct0 = 17U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 83 | kINPUTMUX_DebugHaltedToSct0 = 18U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 84 | kINPUTMUX_SmartCard0TxActivreToSct0 = 19U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 85 | kINPUTMUX_SmartCard0RxActivreToSct0 = 20U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 86 | kINPUTMUX_SmartCard1TxActivreToSct0 = 21U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 87 | kINPUTMUX_SmartCard1RxActivreToSct0 = 22U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 88 | kINPUTMUX_I2s6SclkToSct0 = 23U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 89 | kINPUTMUX_I2sS7clkToSct0 = 24U + (SCT0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 90 | |
AnnaBridge | 171:3a7713b1edbc | 91 | /*!< Frequency measure. */ |
AnnaBridge | 171:3a7713b1edbc | 92 | kINPUTMUX_MainOscToFreqmeas = 0U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 93 | kINPUTMUX_Fro12MhzToFreqmeas = 1U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 94 | kINPUTMUX_Fro96MhzToFreqmeas = 2U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 95 | kINPUTMUX_WdtOscToFreqmeas = 3U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 96 | kINPUTMUX_32KhzOscToFreqmeas = 4U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 97 | kINPUTMUX_MainClkToFreqmeas = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 98 | kINPUTMUX_FreqmeGpioClk_a = 6U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 99 | kINPUTMUX_FreqmeGpioClk_b = 7U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 100 | |
AnnaBridge | 171:3a7713b1edbc | 101 | /*!< Pin Interrupt. */ |
AnnaBridge | 171:3a7713b1edbc | 102 | kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 103 | kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 104 | kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 105 | kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 106 | kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 107 | kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 108 | kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 109 | kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 110 | kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 111 | kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 112 | kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 113 | kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 114 | kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 115 | kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 116 | kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 117 | kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 118 | kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 119 | kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 120 | kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 121 | kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 122 | kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 123 | kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 124 | kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 125 | kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 126 | kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 127 | kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 128 | kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 129 | kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 130 | kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 131 | kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 132 | kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 133 | kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 134 | kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 135 | kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 136 | kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 137 | kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 138 | kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 139 | kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 140 | kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 141 | kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 142 | kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 143 | kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 144 | kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 145 | kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 146 | kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 147 | kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 148 | kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 149 | kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 150 | kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 151 | kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 152 | kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 153 | kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 154 | kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 155 | kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 156 | kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 157 | kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 158 | kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 159 | kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 160 | kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 161 | kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 162 | kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 163 | kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 164 | kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 165 | kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 166 | /*!< DMA ITRIG. */ |
AnnaBridge | 171:3a7713b1edbc | 167 | kINPUTMUX_Adc0SeqaIrqToDma = 0U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 168 | kINPUTMUX_Adc0SeqbIrqToDma = 1U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 169 | kINPUTMUX_Sct0DmaReq0ToDma = 2U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 170 | kINPUTMUX_Sct0DmaReq1ToDma = 3U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 171 | kINPUTMUX_PinInt0ToDma = 4U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 172 | kINPUTMUX_PinInt1ToDma = 5U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 173 | kINPUTMUX_PinInt2ToDma = 6U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 174 | kINPUTMUX_PinInt3ToDma = 7U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 175 | kINPUTMUX_Ctimer0M0ToDma = 8U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 176 | kINPUTMUX_Ctimer0M1ToDma = 9U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 177 | kINPUTMUX_Ctimer1M0ToDma = 10U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 178 | kINPUTMUX_Ctimer2M0ToDma = 11U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 179 | kINPUTMUX_Ctimer2M1ToDma = 12U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 180 | kINPUTMUX_Ctimer3M0ToDma = 13U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 181 | kINPUTMUX_Ctimer4M0ToDma = 14U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 182 | kINPUTMUX_Ctimer4M1ToDma = 15U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 183 | kINPUTMUX_Otrig0ToDma = 16U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 184 | kINPUTMUX_Otrig1ToDma = 17U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 185 | kINPUTMUX_Otrig2ToDma = 18U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 186 | kINPUTMUX_Otrig3ToDma = 19U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 187 | /*!< DMA OTRIG. */ |
AnnaBridge | 171:3a7713b1edbc | 188 | kINPUTMUX_DmaFlexcomm0RxTrigoutToTriginChannels = 0U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 189 | kINPUTMUX_DmaFlexcomm0TxTrigoutToTriginChannels = 1U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 190 | kINPUTMUX_DmaFlexcomm1RxTrigoutToTriginChannels = 2U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 191 | kINPUTMUX_DmaFlexcomm1TxTrigoutToTriginChannels = 3U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 192 | kINPUTMUX_DmaFlexcomm2RxTrigoutToTriginChannels = 4U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 193 | kINPUTMUX_DmaFlexcomm2TxTrigoutToTriginChannels = 5U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 194 | kINPUTMUX_DmaFlexcomm3RxTrigoutToTriginChannels = 6U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 195 | kINPUTMUX_DmaFlexcomm3TxTrigoutToTriginChannels = 7U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 196 | kINPUTMUX_DmaFlexcomm4RxTrigoutToTriginChannels = 8U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 197 | kINPUTMUX_DmaFlexcomm4TxTrigoutToTriginChannels = 9U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 198 | kINPUTMUX_DmaFlexcomm5RxTrigoutToTriginChannels = 10U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 199 | kINPUTMUX_DmaFlexcomm5TxTrigoutToTriginChannels = 11U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 200 | kINPUTMUX_DmaFlexcomm6RxTrigoutToTriginChannels = 12U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 201 | kINPUTMUX_DmaFlexcomm6TxTrigoutToTriginChannels = 13U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 202 | kINPUTMUX_DmaFlexcomm7RxTrigoutToTriginChannels = 14U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 203 | kINPUTMUX_DmaFlexcomm7TxTrigoutToTriginChannels = 15U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 204 | kINPUTMUX_DmaDmic0Ch0TrigoutToTriginChannels = 16U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 205 | kINPUTMUX_Dmamic0Ch1TrigoutToTriginChannels = 17U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 206 | kINPUTMUX_DmaSpifi0TrigoutToTriginChannels = 18U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 207 | kINPUTMUX_DmaChannel9_TrigoutToTriginChannels = 19U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 208 | kINPUTMUX_DmaFlexcomm8RxTrigoutToTriginChannels = 20U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 209 | kINPUTMUX_DmaFlexcomm8TxTrigoutToTriginChannels = 21U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 210 | kINPUTMUX_DmaFlexcomm9RxTrigoutToTriginChannels = 22U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 211 | kINPUTMUX_DmaFlexcomm9TxTrigoutToTriginChannels = 23U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 212 | kINPUTMUX_DmaSmartcard0RxTrigoutToTriginChannels = 24U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 213 | kINPUTMUX_DmaSmartcard0TxTrigoutToTriginChannels = 25U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 214 | kINPUTMUX_DmaSmartcard1RxTrigoutToTriginChannels = 26U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 215 | kINPUTMUX_DmaSmartcard1TxTrigoutToTriginChannels = 27U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), |
AnnaBridge | 171:3a7713b1edbc | 216 | } inputmux_connection_t; |
AnnaBridge | 171:3a7713b1edbc | 217 | |
AnnaBridge | 171:3a7713b1edbc | 218 | /*@}*/ |
AnnaBridge | 171:3a7713b1edbc | 219 | |
AnnaBridge | 171:3a7713b1edbc | 220 | #endif /* _FSL_INPUTMUX_CONNECTIONS_ */ |