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TARGET_DISCO_L053C8/TOOLCHAIN_IAR/stm32l0xx_ll_rcc.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 157:e7ca05fa8600 | 1 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2 | ****************************************************************************** |
AnnaBridge | 157:e7ca05fa8600 | 3 | * @file stm32l0xx_ll_rcc.h |
AnnaBridge | 157:e7ca05fa8600 | 4 | * @author MCD Application Team |
AnnaBridge | 157:e7ca05fa8600 | 5 | * @brief Header file of RCC LL module. |
AnnaBridge | 157:e7ca05fa8600 | 6 | ****************************************************************************** |
AnnaBridge | 157:e7ca05fa8600 | 7 | * @attention |
AnnaBridge | 157:e7ca05fa8600 | 8 | * |
AnnaBridge | 157:e7ca05fa8600 | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
AnnaBridge | 157:e7ca05fa8600 | 10 | * |
AnnaBridge | 157:e7ca05fa8600 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 157:e7ca05fa8600 | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 157:e7ca05fa8600 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 157:e7ca05fa8600 | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 157:e7ca05fa8600 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 157:e7ca05fa8600 | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 157:e7ca05fa8600 | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 157:e7ca05fa8600 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 157:e7ca05fa8600 | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 157:e7ca05fa8600 | 20 | * without specific prior written permission. |
AnnaBridge | 157:e7ca05fa8600 | 21 | * |
AnnaBridge | 157:e7ca05fa8600 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 157:e7ca05fa8600 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 157:e7ca05fa8600 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 157:e7ca05fa8600 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 157:e7ca05fa8600 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 157:e7ca05fa8600 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 157:e7ca05fa8600 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 157:e7ca05fa8600 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 157:e7ca05fa8600 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 157:e7ca05fa8600 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 157:e7ca05fa8600 | 32 | * |
AnnaBridge | 157:e7ca05fa8600 | 33 | ****************************************************************************** |
AnnaBridge | 157:e7ca05fa8600 | 34 | */ |
AnnaBridge | 157:e7ca05fa8600 | 35 | |
AnnaBridge | 157:e7ca05fa8600 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 37 | #ifndef __STM32L0xx_LL_RCC_H |
AnnaBridge | 157:e7ca05fa8600 | 38 | #define __STM32L0xx_LL_RCC_H |
AnnaBridge | 157:e7ca05fa8600 | 39 | |
AnnaBridge | 157:e7ca05fa8600 | 40 | #ifdef __cplusplus |
AnnaBridge | 157:e7ca05fa8600 | 41 | extern "C" { |
AnnaBridge | 157:e7ca05fa8600 | 42 | #endif |
AnnaBridge | 157:e7ca05fa8600 | 43 | |
AnnaBridge | 157:e7ca05fa8600 | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 45 | #include "stm32l0xx.h" |
AnnaBridge | 157:e7ca05fa8600 | 46 | |
AnnaBridge | 157:e7ca05fa8600 | 47 | /** @addtogroup STM32L0xx_LL_Driver |
AnnaBridge | 157:e7ca05fa8600 | 48 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 49 | */ |
AnnaBridge | 157:e7ca05fa8600 | 50 | |
AnnaBridge | 157:e7ca05fa8600 | 51 | #if defined(RCC) |
AnnaBridge | 157:e7ca05fa8600 | 52 | |
AnnaBridge | 157:e7ca05fa8600 | 53 | /** @defgroup RCC_LL RCC |
AnnaBridge | 157:e7ca05fa8600 | 54 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 55 | */ |
AnnaBridge | 157:e7ca05fa8600 | 56 | |
AnnaBridge | 157:e7ca05fa8600 | 57 | /* Private types -------------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 58 | /* Private variables ---------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 59 | /** @defgroup RCC_LL_Private_Variables RCC Private Variables |
AnnaBridge | 157:e7ca05fa8600 | 60 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 61 | */ |
AnnaBridge | 157:e7ca05fa8600 | 62 | |
AnnaBridge | 157:e7ca05fa8600 | 63 | /** |
AnnaBridge | 157:e7ca05fa8600 | 64 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 65 | */ |
AnnaBridge | 157:e7ca05fa8600 | 66 | |
AnnaBridge | 157:e7ca05fa8600 | 67 | /* Private constants ---------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 68 | /** @defgroup RCC_LL_Private_Constants RCC Private Constants |
AnnaBridge | 157:e7ca05fa8600 | 69 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 70 | */ |
AnnaBridge | 157:e7ca05fa8600 | 71 | /* Defines used for the bit position in the register and perform offsets*/ |
AnnaBridge | 157:e7ca05fa8600 | 72 | #define RCC_POSITION_HPRE (uint32_t)4U /*!< field position in register RCC_CFGR */ |
AnnaBridge | 157:e7ca05fa8600 | 73 | #define RCC_POSITION_PPRE1 (uint32_t)8U /*!< field position in register RCC_CFGR */ |
AnnaBridge | 157:e7ca05fa8600 | 74 | #define RCC_POSITION_PPRE2 (uint32_t)11U /*!< field position in register RCC_CFGR */ |
AnnaBridge | 157:e7ca05fa8600 | 75 | #define RCC_POSITION_PLLDIV (uint32_t)22U /*!< field position in register RCC_CFGR */ |
AnnaBridge | 157:e7ca05fa8600 | 76 | #define RCC_POSITION_PLLMUL (uint32_t)18U /*!< field position in register RCC_CFGR */ |
AnnaBridge | 157:e7ca05fa8600 | 77 | #define RCC_POSITION_HSICAL (uint32_t)0U /*!< field position in register RCC_ICSCR */ |
AnnaBridge | 157:e7ca05fa8600 | 78 | #define RCC_POSITION_HSITRIM (uint32_t)8U /*!< field position in register RCC_ICSCR */ |
AnnaBridge | 157:e7ca05fa8600 | 79 | #define RCC_POSITION_MSIRANGE (uint32_t)13U /*!< field position in register RCC_ICSCR */ |
AnnaBridge | 157:e7ca05fa8600 | 80 | #define RCC_POSITION_MSICAL (uint32_t)16U /*!< field position in register RCC_ICSCR */ |
AnnaBridge | 157:e7ca05fa8600 | 81 | #define RCC_POSITION_MSITRIM (uint32_t)24U /*!< field position in register RCC_ICSCR */ |
AnnaBridge | 157:e7ca05fa8600 | 82 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 157:e7ca05fa8600 | 83 | #define RCC_POSITION_HSI48CAL (uint32_t)8U /*!< field position in register RCC_CRRCR */ |
AnnaBridge | 157:e7ca05fa8600 | 84 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 157:e7ca05fa8600 | 85 | |
AnnaBridge | 157:e7ca05fa8600 | 86 | /** |
AnnaBridge | 157:e7ca05fa8600 | 87 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 88 | */ |
AnnaBridge | 157:e7ca05fa8600 | 89 | |
AnnaBridge | 157:e7ca05fa8600 | 90 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 91 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 157:e7ca05fa8600 | 92 | /** @defgroup RCC_LL_Private_Macros RCC Private Macros |
AnnaBridge | 157:e7ca05fa8600 | 93 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 94 | */ |
AnnaBridge | 157:e7ca05fa8600 | 95 | /** |
AnnaBridge | 157:e7ca05fa8600 | 96 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 97 | */ |
AnnaBridge | 157:e7ca05fa8600 | 98 | #endif /*USE_FULL_LL_DRIVER*/ |
AnnaBridge | 157:e7ca05fa8600 | 99 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 100 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 157:e7ca05fa8600 | 101 | /** @defgroup RCC_LL_Exported_Types RCC Exported Types |
AnnaBridge | 157:e7ca05fa8600 | 102 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 103 | */ |
AnnaBridge | 157:e7ca05fa8600 | 104 | |
AnnaBridge | 157:e7ca05fa8600 | 105 | /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure |
AnnaBridge | 157:e7ca05fa8600 | 106 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 107 | */ |
AnnaBridge | 157:e7ca05fa8600 | 108 | |
AnnaBridge | 157:e7ca05fa8600 | 109 | /** |
AnnaBridge | 157:e7ca05fa8600 | 110 | * @brief RCC Clocks Frequency Structure |
AnnaBridge | 157:e7ca05fa8600 | 111 | */ |
AnnaBridge | 157:e7ca05fa8600 | 112 | typedef struct |
AnnaBridge | 157:e7ca05fa8600 | 113 | { |
AnnaBridge | 157:e7ca05fa8600 | 114 | uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ |
AnnaBridge | 157:e7ca05fa8600 | 115 | uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ |
AnnaBridge | 157:e7ca05fa8600 | 116 | uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ |
AnnaBridge | 157:e7ca05fa8600 | 117 | uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ |
AnnaBridge | 157:e7ca05fa8600 | 118 | } LL_RCC_ClocksTypeDef; |
AnnaBridge | 157:e7ca05fa8600 | 119 | |
AnnaBridge | 157:e7ca05fa8600 | 120 | /** |
AnnaBridge | 157:e7ca05fa8600 | 121 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 122 | */ |
AnnaBridge | 157:e7ca05fa8600 | 123 | |
AnnaBridge | 157:e7ca05fa8600 | 124 | /** |
AnnaBridge | 157:e7ca05fa8600 | 125 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 126 | */ |
AnnaBridge | 157:e7ca05fa8600 | 127 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 157:e7ca05fa8600 | 128 | |
AnnaBridge | 157:e7ca05fa8600 | 129 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 130 | /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants |
AnnaBridge | 157:e7ca05fa8600 | 131 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 132 | */ |
AnnaBridge | 157:e7ca05fa8600 | 133 | |
AnnaBridge | 157:e7ca05fa8600 | 134 | /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation |
AnnaBridge | 157:e7ca05fa8600 | 135 | * @brief Defines used to adapt values of different oscillators |
AnnaBridge | 157:e7ca05fa8600 | 136 | * @note These values could be modified in the user environment according to |
AnnaBridge | 157:e7ca05fa8600 | 137 | * HW set-up. |
AnnaBridge | 157:e7ca05fa8600 | 138 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 139 | */ |
AnnaBridge | 157:e7ca05fa8600 | 140 | #if !defined (HSE_VALUE) |
AnnaBridge | 157:e7ca05fa8600 | 141 | #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the HSE oscillator in Hz */ |
AnnaBridge | 157:e7ca05fa8600 | 142 | #endif /* HSE_VALUE */ |
AnnaBridge | 157:e7ca05fa8600 | 143 | |
AnnaBridge | 157:e7ca05fa8600 | 144 | #if !defined (HSI_VALUE) |
AnnaBridge | 157:e7ca05fa8600 | 145 | #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the HSI oscillator in Hz */ |
AnnaBridge | 157:e7ca05fa8600 | 146 | #endif /* HSI_VALUE */ |
AnnaBridge | 157:e7ca05fa8600 | 147 | |
AnnaBridge | 157:e7ca05fa8600 | 148 | #if !defined (LSE_VALUE) |
AnnaBridge | 157:e7ca05fa8600 | 149 | #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the LSE oscillator in Hz */ |
AnnaBridge | 157:e7ca05fa8600 | 150 | #endif /* LSE_VALUE */ |
AnnaBridge | 157:e7ca05fa8600 | 151 | |
AnnaBridge | 157:e7ca05fa8600 | 152 | #if !defined (LSI_VALUE) |
AnnaBridge | 157:e7ca05fa8600 | 153 | #define LSI_VALUE ((uint32_t)37000U) /*!< Value of the LSI oscillator in Hz */ |
AnnaBridge | 157:e7ca05fa8600 | 154 | #endif /* LSI_VALUE */ |
AnnaBridge | 157:e7ca05fa8600 | 155 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 157:e7ca05fa8600 | 156 | |
AnnaBridge | 157:e7ca05fa8600 | 157 | #if !defined (HSI48_VALUE) |
AnnaBridge | 157:e7ca05fa8600 | 158 | #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the HSI48 oscillator in Hz */ |
AnnaBridge | 157:e7ca05fa8600 | 159 | #endif /* HSI48_VALUE */ |
AnnaBridge | 157:e7ca05fa8600 | 160 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 157:e7ca05fa8600 | 161 | /** |
AnnaBridge | 157:e7ca05fa8600 | 162 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 163 | */ |
AnnaBridge | 157:e7ca05fa8600 | 164 | |
AnnaBridge | 157:e7ca05fa8600 | 165 | /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines |
AnnaBridge | 157:e7ca05fa8600 | 166 | * @brief Flags defines which can be used with LL_RCC_WriteReg function |
AnnaBridge | 157:e7ca05fa8600 | 167 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 168 | */ |
AnnaBridge | 157:e7ca05fa8600 | 169 | #define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */ |
AnnaBridge | 157:e7ca05fa8600 | 170 | #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */ |
AnnaBridge | 157:e7ca05fa8600 | 171 | #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */ |
AnnaBridge | 157:e7ca05fa8600 | 172 | #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */ |
AnnaBridge | 157:e7ca05fa8600 | 173 | #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */ |
AnnaBridge | 157:e7ca05fa8600 | 174 | #define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */ |
AnnaBridge | 157:e7ca05fa8600 | 175 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 157:e7ca05fa8600 | 176 | #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ |
AnnaBridge | 157:e7ca05fa8600 | 177 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 157:e7ca05fa8600 | 178 | #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */ |
AnnaBridge | 157:e7ca05fa8600 | 179 | #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */ |
AnnaBridge | 157:e7ca05fa8600 | 180 | /** |
AnnaBridge | 157:e7ca05fa8600 | 181 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 182 | */ |
AnnaBridge | 157:e7ca05fa8600 | 183 | |
AnnaBridge | 157:e7ca05fa8600 | 184 | /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines |
AnnaBridge | 157:e7ca05fa8600 | 185 | * @brief Flags defines which can be used with LL_RCC_ReadReg function |
AnnaBridge | 157:e7ca05fa8600 | 186 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 187 | */ |
AnnaBridge | 157:e7ca05fa8600 | 188 | #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ |
AnnaBridge | 157:e7ca05fa8600 | 189 | #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ |
AnnaBridge | 157:e7ca05fa8600 | 190 | #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ |
AnnaBridge | 157:e7ca05fa8600 | 191 | #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ |
AnnaBridge | 157:e7ca05fa8600 | 192 | #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ |
AnnaBridge | 157:e7ca05fa8600 | 193 | #define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ |
AnnaBridge | 157:e7ca05fa8600 | 194 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 157:e7ca05fa8600 | 195 | #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ |
AnnaBridge | 157:e7ca05fa8600 | 196 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 157:e7ca05fa8600 | 197 | #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ |
AnnaBridge | 157:e7ca05fa8600 | 198 | #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ |
AnnaBridge | 157:e7ca05fa8600 | 199 | #define LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF /*!< Firewall reset flag */ |
AnnaBridge | 157:e7ca05fa8600 | 200 | #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ |
AnnaBridge | 157:e7ca05fa8600 | 201 | #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ |
AnnaBridge | 157:e7ca05fa8600 | 202 | #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ |
AnnaBridge | 157:e7ca05fa8600 | 203 | #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ |
AnnaBridge | 157:e7ca05fa8600 | 204 | #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ |
AnnaBridge | 157:e7ca05fa8600 | 205 | #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ |
AnnaBridge | 157:e7ca05fa8600 | 206 | #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ |
AnnaBridge | 157:e7ca05fa8600 | 207 | /** |
AnnaBridge | 157:e7ca05fa8600 | 208 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 209 | */ |
AnnaBridge | 157:e7ca05fa8600 | 210 | |
AnnaBridge | 157:e7ca05fa8600 | 211 | /** @defgroup RCC_LL_EC_IT IT Defines |
AnnaBridge | 157:e7ca05fa8600 | 212 | * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions |
AnnaBridge | 157:e7ca05fa8600 | 213 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 214 | */ |
AnnaBridge | 157:e7ca05fa8600 | 215 | #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */ |
AnnaBridge | 157:e7ca05fa8600 | 216 | #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */ |
AnnaBridge | 157:e7ca05fa8600 | 217 | #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */ |
AnnaBridge | 157:e7ca05fa8600 | 218 | #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */ |
AnnaBridge | 157:e7ca05fa8600 | 219 | #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */ |
AnnaBridge | 157:e7ca05fa8600 | 220 | #define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable */ |
AnnaBridge | 157:e7ca05fa8600 | 221 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 157:e7ca05fa8600 | 222 | #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */ |
AnnaBridge | 157:e7ca05fa8600 | 223 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 157:e7ca05fa8600 | 224 | #define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */ |
AnnaBridge | 157:e7ca05fa8600 | 225 | /** |
AnnaBridge | 157:e7ca05fa8600 | 226 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 227 | */ |
AnnaBridge | 157:e7ca05fa8600 | 228 | |
AnnaBridge | 157:e7ca05fa8600 | 229 | /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability |
AnnaBridge | 157:e7ca05fa8600 | 230 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 231 | */ |
AnnaBridge | 157:e7ca05fa8600 | 232 | #define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving capability */ |
AnnaBridge | 157:e7ca05fa8600 | 233 | #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0 /*!< Xtal mode medium low driving capability */ |
AnnaBridge | 157:e7ca05fa8600 | 234 | #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1 /*!< Xtal mode medium high driving capability */ |
AnnaBridge | 157:e7ca05fa8600 | 235 | #define LL_RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV /*!< Xtal mode higher driving capability */ |
AnnaBridge | 157:e7ca05fa8600 | 236 | /** |
AnnaBridge | 157:e7ca05fa8600 | 237 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 238 | */ |
AnnaBridge | 157:e7ca05fa8600 | 239 | |
AnnaBridge | 157:e7ca05fa8600 | 240 | /** @defgroup RCC_LL_EC_RTC_HSE_DIV RTC HSE Prescaler |
AnnaBridge | 157:e7ca05fa8600 | 241 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 242 | */ |
AnnaBridge | 157:e7ca05fa8600 | 243 | #define LL_RCC_RTC_HSE_DIV_2 (uint32_t)0x00000000U/*!< HSE is divided by 2 for RTC clock */ |
AnnaBridge | 157:e7ca05fa8600 | 244 | #define LL_RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /*!< HSE is divided by 4 for RTC clock */ |
AnnaBridge | 157:e7ca05fa8600 | 245 | #define LL_RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /*!< HSE is divided by 8 for RTC clock */ |
AnnaBridge | 157:e7ca05fa8600 | 246 | #define LL_RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /*!< HSE is divided by 16 for RTC clock */ |
AnnaBridge | 157:e7ca05fa8600 | 247 | /** |
AnnaBridge | 157:e7ca05fa8600 | 248 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 249 | */ |
AnnaBridge | 157:e7ca05fa8600 | 250 | |
AnnaBridge | 157:e7ca05fa8600 | 251 | /** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges |
AnnaBridge | 157:e7ca05fa8600 | 252 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 253 | */ |
AnnaBridge | 157:e7ca05fa8600 | 254 | #define LL_RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */ |
AnnaBridge | 157:e7ca05fa8600 | 255 | #define LL_RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz*/ |
AnnaBridge | 157:e7ca05fa8600 | 256 | #define LL_RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */ |
AnnaBridge | 157:e7ca05fa8600 | 257 | #define LL_RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */ |
AnnaBridge | 157:e7ca05fa8600 | 258 | #define LL_RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */ |
AnnaBridge | 157:e7ca05fa8600 | 259 | #define LL_RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */ |
AnnaBridge | 157:e7ca05fa8600 | 260 | #define LL_RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */ |
AnnaBridge | 157:e7ca05fa8600 | 261 | /** |
AnnaBridge | 157:e7ca05fa8600 | 262 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 263 | */ |
AnnaBridge | 157:e7ca05fa8600 | 264 | |
AnnaBridge | 157:e7ca05fa8600 | 265 | /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch |
AnnaBridge | 157:e7ca05fa8600 | 266 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 267 | */ |
AnnaBridge | 157:e7ca05fa8600 | 268 | #define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */ |
AnnaBridge | 157:e7ca05fa8600 | 269 | #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ |
AnnaBridge | 157:e7ca05fa8600 | 270 | #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ |
AnnaBridge | 157:e7ca05fa8600 | 271 | #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ |
AnnaBridge | 157:e7ca05fa8600 | 272 | /** |
AnnaBridge | 157:e7ca05fa8600 | 273 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 274 | */ |
AnnaBridge | 157:e7ca05fa8600 | 275 | |
AnnaBridge | 157:e7ca05fa8600 | 276 | /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status |
AnnaBridge | 157:e7ca05fa8600 | 277 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 278 | */ |
AnnaBridge | 157:e7ca05fa8600 | 279 | #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ |
AnnaBridge | 157:e7ca05fa8600 | 280 | #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ |
AnnaBridge | 157:e7ca05fa8600 | 281 | #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ |
AnnaBridge | 157:e7ca05fa8600 | 282 | #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ |
AnnaBridge | 157:e7ca05fa8600 | 283 | /** |
AnnaBridge | 157:e7ca05fa8600 | 284 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 285 | */ |
AnnaBridge | 157:e7ca05fa8600 | 286 | |
AnnaBridge | 157:e7ca05fa8600 | 287 | /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler |
AnnaBridge | 157:e7ca05fa8600 | 288 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 289 | */ |
AnnaBridge | 157:e7ca05fa8600 | 290 | #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ |
AnnaBridge | 157:e7ca05fa8600 | 291 | #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ |
AnnaBridge | 157:e7ca05fa8600 | 292 | #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ |
AnnaBridge | 157:e7ca05fa8600 | 293 | #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ |
AnnaBridge | 157:e7ca05fa8600 | 294 | #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ |
AnnaBridge | 157:e7ca05fa8600 | 295 | #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ |
AnnaBridge | 157:e7ca05fa8600 | 296 | #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ |
AnnaBridge | 157:e7ca05fa8600 | 297 | #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ |
AnnaBridge | 157:e7ca05fa8600 | 298 | #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ |
AnnaBridge | 157:e7ca05fa8600 | 299 | /** |
AnnaBridge | 157:e7ca05fa8600 | 300 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 301 | */ |
AnnaBridge | 157:e7ca05fa8600 | 302 | |
AnnaBridge | 157:e7ca05fa8600 | 303 | /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) |
AnnaBridge | 157:e7ca05fa8600 | 304 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 305 | */ |
AnnaBridge | 157:e7ca05fa8600 | 306 | #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ |
AnnaBridge | 157:e7ca05fa8600 | 307 | #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ |
AnnaBridge | 157:e7ca05fa8600 | 308 | #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ |
AnnaBridge | 157:e7ca05fa8600 | 309 | #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ |
AnnaBridge | 157:e7ca05fa8600 | 310 | #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ |
AnnaBridge | 157:e7ca05fa8600 | 311 | /** |
AnnaBridge | 157:e7ca05fa8600 | 312 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 313 | */ |
AnnaBridge | 157:e7ca05fa8600 | 314 | |
AnnaBridge | 157:e7ca05fa8600 | 315 | /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) |
AnnaBridge | 157:e7ca05fa8600 | 316 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 317 | */ |
AnnaBridge | 157:e7ca05fa8600 | 318 | #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ |
AnnaBridge | 157:e7ca05fa8600 | 319 | #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ |
AnnaBridge | 157:e7ca05fa8600 | 320 | #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ |
AnnaBridge | 157:e7ca05fa8600 | 321 | #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ |
AnnaBridge | 157:e7ca05fa8600 | 322 | #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ |
AnnaBridge | 157:e7ca05fa8600 | 323 | /** |
AnnaBridge | 157:e7ca05fa8600 | 324 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 325 | */ |
AnnaBridge | 157:e7ca05fa8600 | 326 | |
AnnaBridge | 157:e7ca05fa8600 | 327 | /** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection |
AnnaBridge | 157:e7ca05fa8600 | 328 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 329 | */ |
AnnaBridge | 157:e7ca05fa8600 | 330 | #define LL_RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000U) /*!< MSI selection after wake-up from STOP */ |
AnnaBridge | 157:e7ca05fa8600 | 331 | #define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ |
AnnaBridge | 157:e7ca05fa8600 | 332 | /** |
AnnaBridge | 157:e7ca05fa8600 | 333 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 334 | */ |
AnnaBridge | 157:e7ca05fa8600 | 335 | |
AnnaBridge | 157:e7ca05fa8600 | 336 | /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection |
AnnaBridge | 157:e7ca05fa8600 | 337 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 338 | */ |
AnnaBridge | 157:e7ca05fa8600 | 339 | #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */ |
AnnaBridge | 157:e7ca05fa8600 | 340 | #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */ |
AnnaBridge | 157:e7ca05fa8600 | 341 | #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */ |
AnnaBridge | 157:e7ca05fa8600 | 342 | #define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_MSI /*!< MSI selection as MCO source */ |
AnnaBridge | 157:e7ca05fa8600 | 343 | #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */ |
AnnaBridge | 157:e7ca05fa8600 | 344 | #define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */ |
AnnaBridge | 157:e7ca05fa8600 | 345 | #define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */ |
AnnaBridge | 157:e7ca05fa8600 | 346 | #if defined(RCC_CFGR_MCOSEL_HSI48) |
AnnaBridge | 157:e7ca05fa8600 | 347 | #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_HSI48 /*!< HSI48 selection as MCO source */ |
AnnaBridge | 157:e7ca05fa8600 | 348 | #endif /* RCC_CFGR_MCOSEL_HSI48 */ |
AnnaBridge | 157:e7ca05fa8600 | 349 | #define LL_RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCOSEL_PLL /*!< PLLCLK selection as MCO source */ |
AnnaBridge | 157:e7ca05fa8600 | 350 | /** |
AnnaBridge | 157:e7ca05fa8600 | 351 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 352 | */ |
AnnaBridge | 157:e7ca05fa8600 | 353 | |
AnnaBridge | 157:e7ca05fa8600 | 354 | /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler |
AnnaBridge | 157:e7ca05fa8600 | 355 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 356 | */ |
AnnaBridge | 157:e7ca05fa8600 | 357 | #define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO Clock divided by 1 */ |
AnnaBridge | 157:e7ca05fa8600 | 358 | #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */ |
AnnaBridge | 157:e7ca05fa8600 | 359 | #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */ |
AnnaBridge | 157:e7ca05fa8600 | 360 | #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */ |
AnnaBridge | 157:e7ca05fa8600 | 361 | #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */ |
AnnaBridge | 157:e7ca05fa8600 | 362 | /** |
AnnaBridge | 157:e7ca05fa8600 | 363 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 364 | */ |
AnnaBridge | 157:e7ca05fa8600 | 365 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 157:e7ca05fa8600 | 366 | /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency |
AnnaBridge | 157:e7ca05fa8600 | 367 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 368 | */ |
AnnaBridge | 157:e7ca05fa8600 | 369 | #define LL_RCC_PERIPH_FREQUENCY_NO (uint32_t)0x00000000U /*!< No clock enabled for the peripheral */ |
AnnaBridge | 157:e7ca05fa8600 | 370 | #define LL_RCC_PERIPH_FREQUENCY_NA (uint32_t)0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ |
AnnaBridge | 157:e7ca05fa8600 | 371 | /** |
AnnaBridge | 157:e7ca05fa8600 | 372 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 373 | */ |
AnnaBridge | 157:e7ca05fa8600 | 374 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 157:e7ca05fa8600 | 375 | |
AnnaBridge | 157:e7ca05fa8600 | 376 | /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection |
AnnaBridge | 157:e7ca05fa8600 | 377 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 378 | */ |
AnnaBridge | 157:e7ca05fa8600 | 379 | #if defined(RCC_CCIPR_USART1SEL) |
AnnaBridge | 157:e7ca05fa8600 | 380 | #define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | 0x00000000U) /*!< PCLK2 selected as USART1 clock */ |
AnnaBridge | 157:e7ca05fa8600 | 381 | #define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK selected as USART1 clock */ |
AnnaBridge | 157:e7ca05fa8600 | 382 | #define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI selected as USART1 clock */ |
AnnaBridge | 157:e7ca05fa8600 | 383 | #define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE selected as USART1 clock*/ |
AnnaBridge | 157:e7ca05fa8600 | 384 | #endif /* RCC_CCIPR_USART1SEL */ |
AnnaBridge | 157:e7ca05fa8600 | 385 | #define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | 0x00000000U) /*!< PCLK1 selected as USART2 clock */ |
AnnaBridge | 157:e7ca05fa8600 | 386 | #define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK selected as USART2 clock */ |
AnnaBridge | 157:e7ca05fa8600 | 387 | #define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI selected as USART2 clock */ |
AnnaBridge | 157:e7ca05fa8600 | 388 | #define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE selected as USART2 clock*/ |
AnnaBridge | 157:e7ca05fa8600 | 389 | /** |
AnnaBridge | 157:e7ca05fa8600 | 390 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 391 | */ |
AnnaBridge | 157:e7ca05fa8600 | 392 | |
AnnaBridge | 157:e7ca05fa8600 | 393 | |
AnnaBridge | 157:e7ca05fa8600 | 394 | |
AnnaBridge | 157:e7ca05fa8600 | 395 | /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection |
AnnaBridge | 157:e7ca05fa8600 | 396 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 397 | */ |
AnnaBridge | 157:e7ca05fa8600 | 398 | #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 (uint32_t)0x00000000U /*!< PCLK1 selected as LPUART1 clock */ |
AnnaBridge | 157:e7ca05fa8600 | 399 | #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYSCLK selected as LPUART1 clock */ |
AnnaBridge | 157:e7ca05fa8600 | 400 | #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI selected as LPUART1 clock */ |
AnnaBridge | 157:e7ca05fa8600 | 401 | #define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE selected as LPUART1 clock*/ |
AnnaBridge | 157:e7ca05fa8600 | 402 | /** |
AnnaBridge | 157:e7ca05fa8600 | 403 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 404 | */ |
AnnaBridge | 157:e7ca05fa8600 | 405 | |
AnnaBridge | 157:e7ca05fa8600 | 406 | /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection |
AnnaBridge | 157:e7ca05fa8600 | 407 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 408 | */ |
AnnaBridge | 157:e7ca05fa8600 | 409 | #define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) | (0x00000000U >> 4U)) /*!< PCLK1 selected as I2C1 clock */ |
AnnaBridge | 157:e7ca05fa8600 | 410 | #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) | (RCC_CCIPR_I2C1SEL_0 >> 4U)) /*!< SYSCLK selected as I2C1 clock */ |
AnnaBridge | 157:e7ca05fa8600 | 411 | #define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) | (RCC_CCIPR_I2C1SEL_1 >> 4U)) /*!< HSI selected as I2C1 clock */ |
AnnaBridge | 157:e7ca05fa8600 | 412 | #if defined(RCC_CCIPR_I2C3SEL) |
AnnaBridge | 157:e7ca05fa8600 | 413 | #define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) | (0x00000000U >> 4U)) /*!< PCLK1 selected as I2C3 clock */ |
AnnaBridge | 157:e7ca05fa8600 | 414 | #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) | (RCC_CCIPR_I2C3SEL_0 >> 4U)) /*!< SYSCLK selected as I2C3 clock */ |
AnnaBridge | 157:e7ca05fa8600 | 415 | #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) | (RCC_CCIPR_I2C3SEL_1 >> 4U)) /*!< HSI selected as I2C3 clock */ |
AnnaBridge | 157:e7ca05fa8600 | 416 | #endif /*RCC_CCIPR_I2C3SEL*/ |
AnnaBridge | 157:e7ca05fa8600 | 417 | /** |
AnnaBridge | 157:e7ca05fa8600 | 418 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 419 | */ |
AnnaBridge | 157:e7ca05fa8600 | 420 | |
AnnaBridge | 157:e7ca05fa8600 | 421 | /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection |
AnnaBridge | 157:e7ca05fa8600 | 422 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 423 | */ |
AnnaBridge | 157:e7ca05fa8600 | 424 | #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (uint32_t)(0x00000000U) /*!< PCLK1 selected as LPTIM1 clock */ |
AnnaBridge | 157:e7ca05fa8600 | 425 | #define LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)RCC_CCIPR_LPTIM1SEL_0 /*!< LSI selected as LPTIM1 clock */ |
AnnaBridge | 157:e7ca05fa8600 | 426 | #define LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)RCC_CCIPR_LPTIM1SEL_1 /*!< HSI selected as LPTIM1 clock */ |
AnnaBridge | 157:e7ca05fa8600 | 427 | #define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)RCC_CCIPR_LPTIM1SEL /*!< LSE selected as LPTIM1 clock*/ |
AnnaBridge | 157:e7ca05fa8600 | 428 | /** |
AnnaBridge | 157:e7ca05fa8600 | 429 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 430 | */ |
AnnaBridge | 157:e7ca05fa8600 | 431 | |
AnnaBridge | 157:e7ca05fa8600 | 432 | #if defined(RCC_CCIPR_HSI48SEL) |
AnnaBridge | 157:e7ca05fa8600 | 433 | |
AnnaBridge | 157:e7ca05fa8600 | 434 | #if defined(RNG) |
AnnaBridge | 157:e7ca05fa8600 | 435 | /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection |
AnnaBridge | 157:e7ca05fa8600 | 436 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 437 | */ |
AnnaBridge | 157:e7ca05fa8600 | 438 | #define LL_RCC_RNG_CLKSOURCE_PLL (uint32_t)(0x00000000U) /*!< PLL selected as RNG clock */ |
AnnaBridge | 157:e7ca05fa8600 | 439 | #define LL_RCC_RNG_CLKSOURCE_HSI48 (uint32_t)(RCC_CCIPR_HSI48SEL) /*!< HSI48 selected as RNG clock*/ |
AnnaBridge | 157:e7ca05fa8600 | 440 | /** |
AnnaBridge | 157:e7ca05fa8600 | 441 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 442 | */ |
AnnaBridge | 157:e7ca05fa8600 | 443 | #endif /* RNG */ |
AnnaBridge | 157:e7ca05fa8600 | 444 | #if defined(USB) |
AnnaBridge | 157:e7ca05fa8600 | 445 | /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection |
AnnaBridge | 157:e7ca05fa8600 | 446 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 447 | */ |
AnnaBridge | 157:e7ca05fa8600 | 448 | #define LL_RCC_USB_CLKSOURCE_PLL (uint32_t)(0x00000000U) /*!< PLL selected as USB clock */ |
AnnaBridge | 157:e7ca05fa8600 | 449 | #define LL_RCC_USB_CLKSOURCE_HSI48 (uint32_t)(RCC_CCIPR_HSI48SEL) /*!< HSI48 selected as USB clock*/ |
AnnaBridge | 157:e7ca05fa8600 | 450 | /** |
AnnaBridge | 157:e7ca05fa8600 | 451 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 452 | */ |
AnnaBridge | 157:e7ca05fa8600 | 453 | |
AnnaBridge | 157:e7ca05fa8600 | 454 | #endif /* USB */ |
AnnaBridge | 157:e7ca05fa8600 | 455 | #endif /* RCC_CCIPR_HSI48SEL */ |
AnnaBridge | 157:e7ca05fa8600 | 456 | |
AnnaBridge | 157:e7ca05fa8600 | 457 | |
AnnaBridge | 157:e7ca05fa8600 | 458 | /** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source |
AnnaBridge | 157:e7ca05fa8600 | 459 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 460 | */ |
AnnaBridge | 157:e7ca05fa8600 | 461 | #if defined(RCC_CCIPR_USART1SEL) |
AnnaBridge | 157:e7ca05fa8600 | 462 | #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 clock source selection bits */ |
AnnaBridge | 157:e7ca05fa8600 | 463 | #endif /* RCC_CCIPR_USART1SEL */ |
AnnaBridge | 157:e7ca05fa8600 | 464 | #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 clock source selection bits */ |
AnnaBridge | 157:e7ca05fa8600 | 465 | /** |
AnnaBridge | 157:e7ca05fa8600 | 466 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 467 | */ |
AnnaBridge | 157:e7ca05fa8600 | 468 | |
AnnaBridge | 157:e7ca05fa8600 | 469 | |
AnnaBridge | 157:e7ca05fa8600 | 470 | /** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source |
AnnaBridge | 157:e7ca05fa8600 | 471 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 472 | */ |
AnnaBridge | 157:e7ca05fa8600 | 473 | #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 clock source selection bits */ |
AnnaBridge | 157:e7ca05fa8600 | 474 | /** |
AnnaBridge | 157:e7ca05fa8600 | 475 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 476 | */ |
AnnaBridge | 157:e7ca05fa8600 | 477 | |
AnnaBridge | 157:e7ca05fa8600 | 478 | /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source |
AnnaBridge | 157:e7ca05fa8600 | 479 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 480 | */ |
AnnaBridge | 157:e7ca05fa8600 | 481 | #define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL /*!< I2C1 clock source selection bits */ |
AnnaBridge | 157:e7ca05fa8600 | 482 | #if defined(RCC_CCIPR_I2C3SEL) |
AnnaBridge | 157:e7ca05fa8600 | 483 | #define LL_RCC_I2C3_CLKSOURCE RCC_CCIPR_I2C3SEL /*!< I2C3 clock source selection bits */ |
AnnaBridge | 157:e7ca05fa8600 | 484 | #endif /*RCC_CCIPR_I2C3SEL*/ |
AnnaBridge | 157:e7ca05fa8600 | 485 | /** |
AnnaBridge | 157:e7ca05fa8600 | 486 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 487 | */ |
AnnaBridge | 157:e7ca05fa8600 | 488 | |
AnnaBridge | 157:e7ca05fa8600 | 489 | /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source |
AnnaBridge | 157:e7ca05fa8600 | 490 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 491 | */ |
AnnaBridge | 157:e7ca05fa8600 | 492 | #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 clock source selection bits */ |
AnnaBridge | 157:e7ca05fa8600 | 493 | /** |
AnnaBridge | 157:e7ca05fa8600 | 494 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 495 | */ |
AnnaBridge | 157:e7ca05fa8600 | 496 | |
AnnaBridge | 157:e7ca05fa8600 | 497 | #if defined(RCC_CCIPR_HSI48SEL) |
AnnaBridge | 157:e7ca05fa8600 | 498 | #if defined(RNG) |
AnnaBridge | 157:e7ca05fa8600 | 499 | /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source |
AnnaBridge | 157:e7ca05fa8600 | 500 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 501 | */ |
AnnaBridge | 157:e7ca05fa8600 | 502 | #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_HSI48SEL /*!< HSI48 RC clock source selection bit for RNG*/ |
AnnaBridge | 157:e7ca05fa8600 | 503 | /** |
AnnaBridge | 157:e7ca05fa8600 | 504 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 505 | */ |
AnnaBridge | 157:e7ca05fa8600 | 506 | #endif /* RNG */ |
AnnaBridge | 157:e7ca05fa8600 | 507 | |
AnnaBridge | 157:e7ca05fa8600 | 508 | #if defined(USB) |
AnnaBridge | 157:e7ca05fa8600 | 509 | /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source |
AnnaBridge | 157:e7ca05fa8600 | 510 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 511 | */ |
AnnaBridge | 157:e7ca05fa8600 | 512 | #define LL_RCC_USB_CLKSOURCE RCC_CCIPR_HSI48SEL /*!< HSI48 RC clock source selection bit for USB*/ |
AnnaBridge | 157:e7ca05fa8600 | 513 | /** |
AnnaBridge | 157:e7ca05fa8600 | 514 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 515 | */ |
AnnaBridge | 157:e7ca05fa8600 | 516 | |
AnnaBridge | 157:e7ca05fa8600 | 517 | #endif /* USB */ |
AnnaBridge | 157:e7ca05fa8600 | 518 | #endif /* RCC_CCIPR_HSI48SEL */ |
AnnaBridge | 157:e7ca05fa8600 | 519 | |
AnnaBridge | 157:e7ca05fa8600 | 520 | /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection |
AnnaBridge | 157:e7ca05fa8600 | 521 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 522 | */ |
AnnaBridge | 157:e7ca05fa8600 | 523 | #define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)0x00000000U /*!< No clock used as RTC clock */ |
AnnaBridge | 157:e7ca05fa8600 | 524 | #define LL_RCC_RTC_CLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ |
AnnaBridge | 157:e7ca05fa8600 | 525 | #define LL_RCC_RTC_CLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ |
AnnaBridge | 157:e7ca05fa8600 | 526 | #define LL_RCC_RTC_CLKSOURCE_HSE RCC_CSR_RTCSEL_HSE /*!< HSE oscillator clock divided by a programmable prescaler |
AnnaBridge | 157:e7ca05fa8600 | 527 | (selection through @ref LL_RCC_SetRTC_HSEPrescaler function ) */ |
AnnaBridge | 157:e7ca05fa8600 | 528 | /** |
AnnaBridge | 157:e7ca05fa8600 | 529 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 530 | */ |
AnnaBridge | 157:e7ca05fa8600 | 531 | |
AnnaBridge | 157:e7ca05fa8600 | 532 | /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor |
AnnaBridge | 157:e7ca05fa8600 | 533 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 534 | */ |
AnnaBridge | 157:e7ca05fa8600 | 535 | #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock * 3 */ |
AnnaBridge | 157:e7ca05fa8600 | 536 | #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock * 4 */ |
AnnaBridge | 157:e7ca05fa8600 | 537 | #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock * 6 */ |
AnnaBridge | 157:e7ca05fa8600 | 538 | #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock * 8 */ |
AnnaBridge | 157:e7ca05fa8600 | 539 | #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock * 12 */ |
AnnaBridge | 157:e7ca05fa8600 | 540 | #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock * 16 */ |
AnnaBridge | 157:e7ca05fa8600 | 541 | #define LL_RCC_PLL_MUL_24 RCC_CFGR_PLLMUL24 /*!< PLL input clock * 24 */ |
AnnaBridge | 157:e7ca05fa8600 | 542 | #define LL_RCC_PLL_MUL_32 RCC_CFGR_PLLMUL32 /*!< PLL input clock * 32 */ |
AnnaBridge | 157:e7ca05fa8600 | 543 | #define LL_RCC_PLL_MUL_48 RCC_CFGR_PLLMUL48 /*!< PLL input clock * 48 */ |
AnnaBridge | 157:e7ca05fa8600 | 544 | /** |
AnnaBridge | 157:e7ca05fa8600 | 545 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 546 | */ |
AnnaBridge | 157:e7ca05fa8600 | 547 | |
AnnaBridge | 157:e7ca05fa8600 | 548 | /** @defgroup RCC_LL_EC_PLL_DIV PLL division factor |
AnnaBridge | 157:e7ca05fa8600 | 549 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 550 | */ |
AnnaBridge | 157:e7ca05fa8600 | 551 | #define LL_RCC_PLL_DIV_2 RCC_CFGR_PLLDIV2 /*!< PLL clock output = PLLVCO / 2 */ |
AnnaBridge | 157:e7ca05fa8600 | 552 | #define LL_RCC_PLL_DIV_3 RCC_CFGR_PLLDIV3 /*!< PLL clock output = PLLVCO / 3 */ |
AnnaBridge | 157:e7ca05fa8600 | 553 | #define LL_RCC_PLL_DIV_4 RCC_CFGR_PLLDIV4 /*!< PLL clock output = PLLVCO / 4 */ |
AnnaBridge | 157:e7ca05fa8600 | 554 | /** |
AnnaBridge | 157:e7ca05fa8600 | 555 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 556 | */ |
AnnaBridge | 157:e7ca05fa8600 | 557 | |
AnnaBridge | 157:e7ca05fa8600 | 558 | /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE |
AnnaBridge | 157:e7ca05fa8600 | 559 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 560 | */ |
AnnaBridge | 157:e7ca05fa8600 | 561 | #define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ |
AnnaBridge | 157:e7ca05fa8600 | 562 | #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ |
AnnaBridge | 157:e7ca05fa8600 | 563 | /** |
AnnaBridge | 157:e7ca05fa8600 | 564 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 565 | */ |
AnnaBridge | 157:e7ca05fa8600 | 566 | |
AnnaBridge | 157:e7ca05fa8600 | 567 | /** |
AnnaBridge | 157:e7ca05fa8600 | 568 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 569 | */ |
AnnaBridge | 157:e7ca05fa8600 | 570 | |
AnnaBridge | 157:e7ca05fa8600 | 571 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 572 | /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros |
AnnaBridge | 157:e7ca05fa8600 | 573 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 574 | */ |
AnnaBridge | 157:e7ca05fa8600 | 575 | |
AnnaBridge | 157:e7ca05fa8600 | 576 | /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros |
AnnaBridge | 157:e7ca05fa8600 | 577 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 578 | */ |
AnnaBridge | 157:e7ca05fa8600 | 579 | |
AnnaBridge | 157:e7ca05fa8600 | 580 | /** |
AnnaBridge | 157:e7ca05fa8600 | 581 | * @brief Write a value in RCC register |
AnnaBridge | 157:e7ca05fa8600 | 582 | * @param __REG__ Register to be written |
AnnaBridge | 157:e7ca05fa8600 | 583 | * @param __VALUE__ Value to be written in the register |
AnnaBridge | 157:e7ca05fa8600 | 584 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 585 | */ |
AnnaBridge | 157:e7ca05fa8600 | 586 | #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) |
AnnaBridge | 157:e7ca05fa8600 | 587 | |
AnnaBridge | 157:e7ca05fa8600 | 588 | /** |
AnnaBridge | 157:e7ca05fa8600 | 589 | * @brief Read a value in RCC register |
AnnaBridge | 157:e7ca05fa8600 | 590 | * @param __REG__ Register to be read |
AnnaBridge | 157:e7ca05fa8600 | 591 | * @retval Register value |
AnnaBridge | 157:e7ca05fa8600 | 592 | */ |
AnnaBridge | 157:e7ca05fa8600 | 593 | #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) |
AnnaBridge | 157:e7ca05fa8600 | 594 | /** |
AnnaBridge | 157:e7ca05fa8600 | 595 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 596 | */ |
AnnaBridge | 157:e7ca05fa8600 | 597 | |
AnnaBridge | 157:e7ca05fa8600 | 598 | /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies |
AnnaBridge | 157:e7ca05fa8600 | 599 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 600 | */ |
AnnaBridge | 157:e7ca05fa8600 | 601 | |
AnnaBridge | 157:e7ca05fa8600 | 602 | /** |
AnnaBridge | 157:e7ca05fa8600 | 603 | * @brief Helper macro to calculate the PLLCLK frequency |
AnnaBridge | 157:e7ca05fa8600 | 604 | * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, |
AnnaBridge | 157:e7ca05fa8600 | 605 | * @ref LL_RCC_PLL_GetMultiplicator (), |
AnnaBridge | 157:e7ca05fa8600 | 606 | * @ref LL_RCC_PLL_GetDivider ()); |
AnnaBridge | 157:e7ca05fa8600 | 607 | * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) |
AnnaBridge | 157:e7ca05fa8600 | 608 | * @param __PLLMUL__ This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 609 | * @arg @ref LL_RCC_PLL_MUL_3 |
AnnaBridge | 157:e7ca05fa8600 | 610 | * @arg @ref LL_RCC_PLL_MUL_4 |
AnnaBridge | 157:e7ca05fa8600 | 611 | * @arg @ref LL_RCC_PLL_MUL_6 |
AnnaBridge | 157:e7ca05fa8600 | 612 | * @arg @ref LL_RCC_PLL_MUL_8 |
AnnaBridge | 157:e7ca05fa8600 | 613 | * @arg @ref LL_RCC_PLL_MUL_12 |
AnnaBridge | 157:e7ca05fa8600 | 614 | * @arg @ref LL_RCC_PLL_MUL_16 |
AnnaBridge | 157:e7ca05fa8600 | 615 | * @arg @ref LL_RCC_PLL_MUL_24 |
AnnaBridge | 157:e7ca05fa8600 | 616 | * @arg @ref LL_RCC_PLL_MUL_32 |
AnnaBridge | 157:e7ca05fa8600 | 617 | * @arg @ref LL_RCC_PLL_MUL_48 |
AnnaBridge | 157:e7ca05fa8600 | 618 | * @param __PLLDIV__ This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 619 | * @arg @ref LL_RCC_PLL_DIV_2 |
AnnaBridge | 157:e7ca05fa8600 | 620 | * @arg @ref LL_RCC_PLL_DIV_3 |
AnnaBridge | 157:e7ca05fa8600 | 621 | * @arg @ref LL_RCC_PLL_DIV_4 |
AnnaBridge | 157:e7ca05fa8600 | 622 | * @retval PLL clock frequency (in Hz) |
AnnaBridge | 157:e7ca05fa8600 | 623 | */ |
AnnaBridge | 157:e7ca05fa8600 | 624 | #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLDIV__) ((__INPUTFREQ__) * (PLLMulTable[(__PLLMUL__) >> RCC_POSITION_PLLMUL]) / (((__PLLDIV__) >> RCC_POSITION_PLLDIV)+1U)) |
AnnaBridge | 157:e7ca05fa8600 | 625 | |
AnnaBridge | 157:e7ca05fa8600 | 626 | /** |
AnnaBridge | 157:e7ca05fa8600 | 627 | * @brief Helper macro to calculate the HCLK frequency |
AnnaBridge | 157:e7ca05fa8600 | 628 | * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler |
AnnaBridge | 157:e7ca05fa8600 | 629 | * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) |
AnnaBridge | 157:e7ca05fa8600 | 630 | * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK) |
AnnaBridge | 157:e7ca05fa8600 | 631 | * @param __AHBPRESCALER__: This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 632 | * @arg @ref LL_RCC_SYSCLK_DIV_1 |
AnnaBridge | 157:e7ca05fa8600 | 633 | * @arg @ref LL_RCC_SYSCLK_DIV_2 |
AnnaBridge | 157:e7ca05fa8600 | 634 | * @arg @ref LL_RCC_SYSCLK_DIV_4 |
AnnaBridge | 157:e7ca05fa8600 | 635 | * @arg @ref LL_RCC_SYSCLK_DIV_8 |
AnnaBridge | 157:e7ca05fa8600 | 636 | * @arg @ref LL_RCC_SYSCLK_DIV_16 |
AnnaBridge | 157:e7ca05fa8600 | 637 | * @arg @ref LL_RCC_SYSCLK_DIV_64 |
AnnaBridge | 157:e7ca05fa8600 | 638 | * @arg @ref LL_RCC_SYSCLK_DIV_128 |
AnnaBridge | 157:e7ca05fa8600 | 639 | * @arg @ref LL_RCC_SYSCLK_DIV_256 |
AnnaBridge | 157:e7ca05fa8600 | 640 | * @arg @ref LL_RCC_SYSCLK_DIV_512 |
AnnaBridge | 157:e7ca05fa8600 | 641 | * @retval HCLK clock frequency (in Hz) |
AnnaBridge | 157:e7ca05fa8600 | 642 | */ |
AnnaBridge | 157:e7ca05fa8600 | 643 | #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE]) |
AnnaBridge | 157:e7ca05fa8600 | 644 | |
AnnaBridge | 157:e7ca05fa8600 | 645 | /** |
AnnaBridge | 157:e7ca05fa8600 | 646 | * @brief Helper macro to calculate the PCLK1 frequency (ABP1) |
AnnaBridge | 157:e7ca05fa8600 | 647 | * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler |
AnnaBridge | 157:e7ca05fa8600 | 648 | * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) |
AnnaBridge | 157:e7ca05fa8600 | 649 | * @param __HCLKFREQ__ HCLK frequency |
AnnaBridge | 157:e7ca05fa8600 | 650 | * @param __APB1PRESCALER__: This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 651 | * @arg @ref LL_RCC_APB1_DIV_1 |
AnnaBridge | 157:e7ca05fa8600 | 652 | * @arg @ref LL_RCC_APB1_DIV_2 |
AnnaBridge | 157:e7ca05fa8600 | 653 | * @arg @ref LL_RCC_APB1_DIV_4 |
AnnaBridge | 157:e7ca05fa8600 | 654 | * @arg @ref LL_RCC_APB1_DIV_8 |
AnnaBridge | 157:e7ca05fa8600 | 655 | * @arg @ref LL_RCC_APB1_DIV_16 |
AnnaBridge | 157:e7ca05fa8600 | 656 | * @retval PCLK1 clock frequency (in Hz) |
AnnaBridge | 157:e7ca05fa8600 | 657 | */ |
AnnaBridge | 157:e7ca05fa8600 | 658 | #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_POSITION_PPRE1]) |
AnnaBridge | 157:e7ca05fa8600 | 659 | |
AnnaBridge | 157:e7ca05fa8600 | 660 | /** |
AnnaBridge | 157:e7ca05fa8600 | 661 | * @brief Helper macro to calculate the PCLK2 frequency (ABP2) |
AnnaBridge | 157:e7ca05fa8600 | 662 | * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler |
AnnaBridge | 157:e7ca05fa8600 | 663 | * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler()) |
AnnaBridge | 157:e7ca05fa8600 | 664 | * @param __HCLKFREQ__ HCLK frequency |
AnnaBridge | 157:e7ca05fa8600 | 665 | * @param __APB2PRESCALER__: This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 666 | * @arg @ref LL_RCC_APB2_DIV_1 |
AnnaBridge | 157:e7ca05fa8600 | 667 | * @arg @ref LL_RCC_APB2_DIV_2 |
AnnaBridge | 157:e7ca05fa8600 | 668 | * @arg @ref LL_RCC_APB2_DIV_4 |
AnnaBridge | 157:e7ca05fa8600 | 669 | * @arg @ref LL_RCC_APB2_DIV_8 |
AnnaBridge | 157:e7ca05fa8600 | 670 | * @arg @ref LL_RCC_APB2_DIV_16 |
AnnaBridge | 157:e7ca05fa8600 | 671 | * @retval PCLK2 clock frequency (in Hz) |
AnnaBridge | 157:e7ca05fa8600 | 672 | */ |
AnnaBridge | 157:e7ca05fa8600 | 673 | #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_POSITION_PPRE2]) |
AnnaBridge | 157:e7ca05fa8600 | 674 | |
AnnaBridge | 157:e7ca05fa8600 | 675 | /** |
AnnaBridge | 157:e7ca05fa8600 | 676 | * @brief Helper macro to calculate the MSI frequency (in Hz) |
AnnaBridge | 157:e7ca05fa8600 | 677 | * @note: __MSIRANGE__can be retrieved by @ref LL_RCC_MSI_GetRange |
AnnaBridge | 157:e7ca05fa8600 | 678 | * ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()) |
AnnaBridge | 157:e7ca05fa8600 | 679 | * @param __MSIRANGE__: This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 680 | * @arg @ref LL_RCC_MSIRANGE_0 |
AnnaBridge | 157:e7ca05fa8600 | 681 | * @arg @ref LL_RCC_MSIRANGE_1 |
AnnaBridge | 157:e7ca05fa8600 | 682 | * @arg @ref LL_RCC_MSIRANGE_2 |
AnnaBridge | 157:e7ca05fa8600 | 683 | * @arg @ref LL_RCC_MSIRANGE_3 |
AnnaBridge | 157:e7ca05fa8600 | 684 | * @arg @ref LL_RCC_MSIRANGE_4 |
AnnaBridge | 157:e7ca05fa8600 | 685 | * @arg @ref LL_RCC_MSIRANGE_5 |
AnnaBridge | 157:e7ca05fa8600 | 686 | * @arg @ref LL_RCC_MSIRANGE_6 |
AnnaBridge | 157:e7ca05fa8600 | 687 | * @retval MSI clock frequency (in Hz) |
AnnaBridge | 157:e7ca05fa8600 | 688 | */ |
AnnaBridge | 157:e7ca05fa8600 | 689 | #define __LL_RCC_CALC_MSI_FREQ(__MSIRANGE__) ((32768U * ( 1U << (((__MSIRANGE__) >> RCC_POSITION_MSIRANGE) + 1U)))) |
AnnaBridge | 157:e7ca05fa8600 | 690 | |
AnnaBridge | 157:e7ca05fa8600 | 691 | /** |
AnnaBridge | 157:e7ca05fa8600 | 692 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 693 | */ |
AnnaBridge | 157:e7ca05fa8600 | 694 | |
AnnaBridge | 157:e7ca05fa8600 | 695 | /** |
AnnaBridge | 157:e7ca05fa8600 | 696 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 697 | */ |
AnnaBridge | 157:e7ca05fa8600 | 698 | |
AnnaBridge | 157:e7ca05fa8600 | 699 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 700 | /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions |
AnnaBridge | 157:e7ca05fa8600 | 701 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 702 | */ |
AnnaBridge | 157:e7ca05fa8600 | 703 | |
AnnaBridge | 157:e7ca05fa8600 | 704 | /** @defgroup RCC_LL_EF_HSE HSE |
AnnaBridge | 157:e7ca05fa8600 | 705 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 706 | */ |
AnnaBridge | 157:e7ca05fa8600 | 707 | |
AnnaBridge | 157:e7ca05fa8600 | 708 | #if defined(RCC_HSECSS_SUPPORT) |
AnnaBridge | 157:e7ca05fa8600 | 709 | /** |
AnnaBridge | 157:e7ca05fa8600 | 710 | * @brief Enable the Clock Security System. |
AnnaBridge | 157:e7ca05fa8600 | 711 | * @rmtoll CR CSSHSEON LL_RCC_HSE_EnableCSS |
AnnaBridge | 157:e7ca05fa8600 | 712 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 713 | */ |
AnnaBridge | 157:e7ca05fa8600 | 714 | __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) |
AnnaBridge | 157:e7ca05fa8600 | 715 | { |
AnnaBridge | 157:e7ca05fa8600 | 716 | SET_BIT(RCC->CR, RCC_CR_CSSON); |
AnnaBridge | 157:e7ca05fa8600 | 717 | } |
AnnaBridge | 157:e7ca05fa8600 | 718 | #endif /* RCC_HSECSS_SUPPORT */ |
AnnaBridge | 157:e7ca05fa8600 | 719 | |
AnnaBridge | 157:e7ca05fa8600 | 720 | /** |
AnnaBridge | 157:e7ca05fa8600 | 721 | * @brief Enable HSE external oscillator (HSE Bypass) |
AnnaBridge | 157:e7ca05fa8600 | 722 | * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass |
AnnaBridge | 157:e7ca05fa8600 | 723 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 724 | */ |
AnnaBridge | 157:e7ca05fa8600 | 725 | __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) |
AnnaBridge | 157:e7ca05fa8600 | 726 | { |
AnnaBridge | 157:e7ca05fa8600 | 727 | SET_BIT(RCC->CR, RCC_CR_HSEBYP); |
AnnaBridge | 157:e7ca05fa8600 | 728 | } |
AnnaBridge | 157:e7ca05fa8600 | 729 | |
AnnaBridge | 157:e7ca05fa8600 | 730 | /** |
AnnaBridge | 157:e7ca05fa8600 | 731 | * @brief Disable HSE external oscillator (HSE Bypass) |
AnnaBridge | 157:e7ca05fa8600 | 732 | * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass |
AnnaBridge | 157:e7ca05fa8600 | 733 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 734 | */ |
AnnaBridge | 157:e7ca05fa8600 | 735 | __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) |
AnnaBridge | 157:e7ca05fa8600 | 736 | { |
AnnaBridge | 157:e7ca05fa8600 | 737 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); |
AnnaBridge | 157:e7ca05fa8600 | 738 | } |
AnnaBridge | 157:e7ca05fa8600 | 739 | |
AnnaBridge | 157:e7ca05fa8600 | 740 | /** |
AnnaBridge | 157:e7ca05fa8600 | 741 | * @brief Enable HSE crystal oscillator (HSE ON) |
AnnaBridge | 157:e7ca05fa8600 | 742 | * @rmtoll CR HSEON LL_RCC_HSE_Enable |
AnnaBridge | 157:e7ca05fa8600 | 743 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 744 | */ |
AnnaBridge | 157:e7ca05fa8600 | 745 | __STATIC_INLINE void LL_RCC_HSE_Enable(void) |
AnnaBridge | 157:e7ca05fa8600 | 746 | { |
AnnaBridge | 157:e7ca05fa8600 | 747 | SET_BIT(RCC->CR, RCC_CR_HSEON); |
AnnaBridge | 157:e7ca05fa8600 | 748 | } |
AnnaBridge | 157:e7ca05fa8600 | 749 | |
AnnaBridge | 157:e7ca05fa8600 | 750 | /** |
AnnaBridge | 157:e7ca05fa8600 | 751 | * @brief Disable HSE crystal oscillator (HSE ON) |
AnnaBridge | 157:e7ca05fa8600 | 752 | * @rmtoll CR HSEON LL_RCC_HSE_Disable |
AnnaBridge | 157:e7ca05fa8600 | 753 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 754 | */ |
AnnaBridge | 157:e7ca05fa8600 | 755 | __STATIC_INLINE void LL_RCC_HSE_Disable(void) |
AnnaBridge | 157:e7ca05fa8600 | 756 | { |
AnnaBridge | 157:e7ca05fa8600 | 757 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON); |
AnnaBridge | 157:e7ca05fa8600 | 758 | } |
AnnaBridge | 157:e7ca05fa8600 | 759 | |
AnnaBridge | 157:e7ca05fa8600 | 760 | /** |
AnnaBridge | 157:e7ca05fa8600 | 761 | * @brief Check if HSE oscillator Ready |
AnnaBridge | 157:e7ca05fa8600 | 762 | * @rmtoll CR HSERDY LL_RCC_HSE_IsReady |
AnnaBridge | 157:e7ca05fa8600 | 763 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 764 | */ |
AnnaBridge | 157:e7ca05fa8600 | 765 | __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) |
AnnaBridge | 157:e7ca05fa8600 | 766 | { |
AnnaBridge | 157:e7ca05fa8600 | 767 | return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); |
AnnaBridge | 157:e7ca05fa8600 | 768 | } |
AnnaBridge | 157:e7ca05fa8600 | 769 | |
AnnaBridge | 157:e7ca05fa8600 | 770 | /** |
AnnaBridge | 157:e7ca05fa8600 | 771 | * @brief Configure the RTC prescaler (divider) |
AnnaBridge | 157:e7ca05fa8600 | 772 | * @rmtoll CR RTCPRE LL_RCC_SetRTC_HSEPrescaler |
AnnaBridge | 157:e7ca05fa8600 | 773 | * @param Div This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 774 | * @arg @ref LL_RCC_RTC_HSE_DIV_2 |
AnnaBridge | 157:e7ca05fa8600 | 775 | * @arg @ref LL_RCC_RTC_HSE_DIV_4 |
AnnaBridge | 157:e7ca05fa8600 | 776 | * @arg @ref LL_RCC_RTC_HSE_DIV_8 |
AnnaBridge | 157:e7ca05fa8600 | 777 | * @arg @ref LL_RCC_RTC_HSE_DIV_16 |
AnnaBridge | 157:e7ca05fa8600 | 778 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 779 | */ |
AnnaBridge | 157:e7ca05fa8600 | 780 | __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Div) |
AnnaBridge | 157:e7ca05fa8600 | 781 | { |
AnnaBridge | 157:e7ca05fa8600 | 782 | MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, Div); |
AnnaBridge | 157:e7ca05fa8600 | 783 | } |
AnnaBridge | 157:e7ca05fa8600 | 784 | |
AnnaBridge | 157:e7ca05fa8600 | 785 | /** |
AnnaBridge | 157:e7ca05fa8600 | 786 | * @brief Get the RTC divider (prescaler) |
AnnaBridge | 157:e7ca05fa8600 | 787 | * @rmtoll CR RTCPRE LL_RCC_GetRTC_HSEPrescaler |
AnnaBridge | 157:e7ca05fa8600 | 788 | * @retval Returned value can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 789 | * @arg @ref LL_RCC_RTC_HSE_DIV_2 |
AnnaBridge | 157:e7ca05fa8600 | 790 | * @arg @ref LL_RCC_RTC_HSE_DIV_4 |
AnnaBridge | 157:e7ca05fa8600 | 791 | * @arg @ref LL_RCC_RTC_HSE_DIV_8 |
AnnaBridge | 157:e7ca05fa8600 | 792 | * @arg @ref LL_RCC_RTC_HSE_DIV_16 |
AnnaBridge | 157:e7ca05fa8600 | 793 | */ |
AnnaBridge | 157:e7ca05fa8600 | 794 | __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) |
AnnaBridge | 157:e7ca05fa8600 | 795 | { |
AnnaBridge | 157:e7ca05fa8600 | 796 | return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)); |
AnnaBridge | 157:e7ca05fa8600 | 797 | } |
AnnaBridge | 157:e7ca05fa8600 | 798 | |
AnnaBridge | 157:e7ca05fa8600 | 799 | /** |
AnnaBridge | 157:e7ca05fa8600 | 800 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 801 | */ |
AnnaBridge | 157:e7ca05fa8600 | 802 | |
AnnaBridge | 157:e7ca05fa8600 | 803 | /** @defgroup RCC_LL_EF_HSI HSI |
AnnaBridge | 157:e7ca05fa8600 | 804 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 805 | */ |
AnnaBridge | 157:e7ca05fa8600 | 806 | |
AnnaBridge | 157:e7ca05fa8600 | 807 | /** |
AnnaBridge | 157:e7ca05fa8600 | 808 | * @brief Enable HSI oscillator |
AnnaBridge | 157:e7ca05fa8600 | 809 | * @rmtoll CR HSION LL_RCC_HSI_Enable |
AnnaBridge | 157:e7ca05fa8600 | 810 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 811 | */ |
AnnaBridge | 157:e7ca05fa8600 | 812 | __STATIC_INLINE void LL_RCC_HSI_Enable(void) |
AnnaBridge | 157:e7ca05fa8600 | 813 | { |
AnnaBridge | 157:e7ca05fa8600 | 814 | SET_BIT(RCC->CR, RCC_CR_HSION); |
AnnaBridge | 157:e7ca05fa8600 | 815 | } |
AnnaBridge | 157:e7ca05fa8600 | 816 | |
AnnaBridge | 157:e7ca05fa8600 | 817 | /** |
AnnaBridge | 157:e7ca05fa8600 | 818 | * @brief Disable HSI oscillator |
AnnaBridge | 157:e7ca05fa8600 | 819 | * @rmtoll CR HSION LL_RCC_HSI_Disable |
AnnaBridge | 157:e7ca05fa8600 | 820 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 821 | */ |
AnnaBridge | 157:e7ca05fa8600 | 822 | __STATIC_INLINE void LL_RCC_HSI_Disable(void) |
AnnaBridge | 157:e7ca05fa8600 | 823 | { |
AnnaBridge | 157:e7ca05fa8600 | 824 | CLEAR_BIT(RCC->CR, RCC_CR_HSION); |
AnnaBridge | 157:e7ca05fa8600 | 825 | } |
AnnaBridge | 157:e7ca05fa8600 | 826 | |
AnnaBridge | 157:e7ca05fa8600 | 827 | /** |
AnnaBridge | 157:e7ca05fa8600 | 828 | * @brief Check if HSI clock is ready |
AnnaBridge | 157:e7ca05fa8600 | 829 | * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady |
AnnaBridge | 157:e7ca05fa8600 | 830 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 831 | */ |
AnnaBridge | 157:e7ca05fa8600 | 832 | __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) |
AnnaBridge | 157:e7ca05fa8600 | 833 | { |
AnnaBridge | 157:e7ca05fa8600 | 834 | return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); |
AnnaBridge | 157:e7ca05fa8600 | 835 | } |
AnnaBridge | 157:e7ca05fa8600 | 836 | |
AnnaBridge | 157:e7ca05fa8600 | 837 | /** |
AnnaBridge | 157:e7ca05fa8600 | 838 | * @brief Enable HSI even in stop mode |
AnnaBridge | 157:e7ca05fa8600 | 839 | * @note HSI oscillator is forced ON even in Stop mode |
AnnaBridge | 157:e7ca05fa8600 | 840 | * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode |
AnnaBridge | 157:e7ca05fa8600 | 841 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 842 | */ |
AnnaBridge | 157:e7ca05fa8600 | 843 | __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void) |
AnnaBridge | 157:e7ca05fa8600 | 844 | { |
AnnaBridge | 157:e7ca05fa8600 | 845 | SET_BIT(RCC->CR, RCC_CR_HSIKERON); |
AnnaBridge | 157:e7ca05fa8600 | 846 | } |
AnnaBridge | 157:e7ca05fa8600 | 847 | |
AnnaBridge | 157:e7ca05fa8600 | 848 | /** |
AnnaBridge | 157:e7ca05fa8600 | 849 | * @brief Disable HSI in stop mode |
AnnaBridge | 157:e7ca05fa8600 | 850 | * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode |
AnnaBridge | 157:e7ca05fa8600 | 851 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 852 | */ |
AnnaBridge | 157:e7ca05fa8600 | 853 | __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) |
AnnaBridge | 157:e7ca05fa8600 | 854 | { |
AnnaBridge | 157:e7ca05fa8600 | 855 | CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); |
AnnaBridge | 157:e7ca05fa8600 | 856 | } |
AnnaBridge | 157:e7ca05fa8600 | 857 | |
AnnaBridge | 157:e7ca05fa8600 | 858 | /** |
AnnaBridge | 157:e7ca05fa8600 | 859 | * @brief Enable HSI Divider (it divides by 4) |
AnnaBridge | 157:e7ca05fa8600 | 860 | * @rmtoll CR HSIDIVEN LL_RCC_HSI_EnableDivider |
AnnaBridge | 157:e7ca05fa8600 | 861 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 862 | */ |
AnnaBridge | 157:e7ca05fa8600 | 863 | __STATIC_INLINE void LL_RCC_HSI_EnableDivider(void) |
AnnaBridge | 157:e7ca05fa8600 | 864 | { |
AnnaBridge | 157:e7ca05fa8600 | 865 | SET_BIT(RCC->CR, RCC_CR_HSIDIVEN); |
AnnaBridge | 157:e7ca05fa8600 | 866 | } |
AnnaBridge | 157:e7ca05fa8600 | 867 | |
AnnaBridge | 157:e7ca05fa8600 | 868 | /** |
AnnaBridge | 157:e7ca05fa8600 | 869 | * @brief Disable HSI Divider (it divides by 4) |
AnnaBridge | 157:e7ca05fa8600 | 870 | * @rmtoll CR HSIDIVEN LL_RCC_HSI_DisableDivider |
AnnaBridge | 157:e7ca05fa8600 | 871 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 872 | */ |
AnnaBridge | 157:e7ca05fa8600 | 873 | __STATIC_INLINE void LL_RCC_HSI_DisableDivider(void) |
AnnaBridge | 157:e7ca05fa8600 | 874 | { |
AnnaBridge | 157:e7ca05fa8600 | 875 | CLEAR_BIT(RCC->CR, RCC_CR_HSIDIVEN); |
AnnaBridge | 157:e7ca05fa8600 | 876 | } |
AnnaBridge | 157:e7ca05fa8600 | 877 | |
AnnaBridge | 157:e7ca05fa8600 | 878 | |
AnnaBridge | 157:e7ca05fa8600 | 879 | |
AnnaBridge | 157:e7ca05fa8600 | 880 | #if defined(RCC_CR_HSIOUTEN) |
AnnaBridge | 157:e7ca05fa8600 | 881 | /** |
AnnaBridge | 157:e7ca05fa8600 | 882 | * @brief Enable HSI Output |
AnnaBridge | 157:e7ca05fa8600 | 883 | * @rmtoll CR HSIOUTEN LL_RCC_HSI_EnableOutput |
AnnaBridge | 157:e7ca05fa8600 | 884 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 885 | */ |
AnnaBridge | 157:e7ca05fa8600 | 886 | __STATIC_INLINE void LL_RCC_HSI_EnableOutput(void) |
AnnaBridge | 157:e7ca05fa8600 | 887 | { |
AnnaBridge | 157:e7ca05fa8600 | 888 | SET_BIT(RCC->CR, RCC_CR_HSIOUTEN); |
AnnaBridge | 157:e7ca05fa8600 | 889 | } |
AnnaBridge | 157:e7ca05fa8600 | 890 | |
AnnaBridge | 157:e7ca05fa8600 | 891 | /** |
AnnaBridge | 157:e7ca05fa8600 | 892 | * @brief Disable HSI Output |
AnnaBridge | 157:e7ca05fa8600 | 893 | * @rmtoll CR HSIOUTEN LL_RCC_HSI_DisableOutput |
AnnaBridge | 157:e7ca05fa8600 | 894 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 895 | */ |
AnnaBridge | 157:e7ca05fa8600 | 896 | __STATIC_INLINE void LL_RCC_HSI_DisableOutput(void) |
AnnaBridge | 157:e7ca05fa8600 | 897 | { |
AnnaBridge | 157:e7ca05fa8600 | 898 | CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN); |
AnnaBridge | 157:e7ca05fa8600 | 899 | } |
AnnaBridge | 157:e7ca05fa8600 | 900 | #endif /* RCC_CR_HSIOUTEN */ |
AnnaBridge | 157:e7ca05fa8600 | 901 | |
AnnaBridge | 157:e7ca05fa8600 | 902 | /** |
AnnaBridge | 157:e7ca05fa8600 | 903 | * @brief Get HSI Calibration value |
AnnaBridge | 157:e7ca05fa8600 | 904 | * @note When HSITRIM is written, HSICAL is updated with the sum of |
AnnaBridge | 157:e7ca05fa8600 | 905 | * HSITRIM and the factory trim value |
AnnaBridge | 157:e7ca05fa8600 | 906 | * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration |
AnnaBridge | 157:e7ca05fa8600 | 907 | * @retval Between Min_Data = 0x00 and Max_Data = 0xFF |
AnnaBridge | 157:e7ca05fa8600 | 908 | */ |
AnnaBridge | 157:e7ca05fa8600 | 909 | __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) |
AnnaBridge | 157:e7ca05fa8600 | 910 | { |
AnnaBridge | 157:e7ca05fa8600 | 911 | return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_POSITION_HSICAL); |
AnnaBridge | 157:e7ca05fa8600 | 912 | } |
AnnaBridge | 157:e7ca05fa8600 | 913 | |
AnnaBridge | 157:e7ca05fa8600 | 914 | /** |
AnnaBridge | 157:e7ca05fa8600 | 915 | * @brief Set HSI Calibration trimming |
AnnaBridge | 157:e7ca05fa8600 | 916 | * @note user-programmable trimming value that is added to the HSICAL |
AnnaBridge | 157:e7ca05fa8600 | 917 | * @note Default value is 16, which, when added to the HSICAL value, |
AnnaBridge | 157:e7ca05fa8600 | 918 | * should trim the HSI to 16 MHz +/- 1 % |
AnnaBridge | 157:e7ca05fa8600 | 919 | * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming |
AnnaBridge | 157:e7ca05fa8600 | 920 | * @param Value between Min_Data = 0x00 and Max_Data = 0x1F |
AnnaBridge | 157:e7ca05fa8600 | 921 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 922 | */ |
AnnaBridge | 157:e7ca05fa8600 | 923 | __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) |
AnnaBridge | 157:e7ca05fa8600 | 924 | { |
AnnaBridge | 157:e7ca05fa8600 | 925 | MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_POSITION_HSITRIM); |
AnnaBridge | 157:e7ca05fa8600 | 926 | } |
AnnaBridge | 157:e7ca05fa8600 | 927 | |
AnnaBridge | 157:e7ca05fa8600 | 928 | /** |
AnnaBridge | 157:e7ca05fa8600 | 929 | * @brief Get HSI Calibration trimming |
AnnaBridge | 157:e7ca05fa8600 | 930 | * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming |
AnnaBridge | 157:e7ca05fa8600 | 931 | * @retval Between Min_Data = 0x00 and Max_Data = 0x1F |
AnnaBridge | 157:e7ca05fa8600 | 932 | */ |
AnnaBridge | 157:e7ca05fa8600 | 933 | __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) |
AnnaBridge | 157:e7ca05fa8600 | 934 | { |
AnnaBridge | 157:e7ca05fa8600 | 935 | return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_POSITION_HSITRIM); |
AnnaBridge | 157:e7ca05fa8600 | 936 | } |
AnnaBridge | 157:e7ca05fa8600 | 937 | |
AnnaBridge | 157:e7ca05fa8600 | 938 | /** |
AnnaBridge | 157:e7ca05fa8600 | 939 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 940 | */ |
AnnaBridge | 157:e7ca05fa8600 | 941 | |
AnnaBridge | 157:e7ca05fa8600 | 942 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 157:e7ca05fa8600 | 943 | /** @defgroup RCC_LL_EF_HSI48 HSI48 |
AnnaBridge | 157:e7ca05fa8600 | 944 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 945 | */ |
AnnaBridge | 157:e7ca05fa8600 | 946 | |
AnnaBridge | 157:e7ca05fa8600 | 947 | /** |
AnnaBridge | 157:e7ca05fa8600 | 948 | * @brief Enable HSI48 |
AnnaBridge | 157:e7ca05fa8600 | 949 | * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable |
AnnaBridge | 157:e7ca05fa8600 | 950 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 951 | */ |
AnnaBridge | 157:e7ca05fa8600 | 952 | __STATIC_INLINE void LL_RCC_HSI48_Enable(void) |
AnnaBridge | 157:e7ca05fa8600 | 953 | { |
AnnaBridge | 157:e7ca05fa8600 | 954 | SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); |
AnnaBridge | 157:e7ca05fa8600 | 955 | } |
AnnaBridge | 157:e7ca05fa8600 | 956 | |
AnnaBridge | 157:e7ca05fa8600 | 957 | /** |
AnnaBridge | 157:e7ca05fa8600 | 958 | * @brief Disable HSI48 |
AnnaBridge | 157:e7ca05fa8600 | 959 | * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable |
AnnaBridge | 157:e7ca05fa8600 | 960 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 961 | */ |
AnnaBridge | 157:e7ca05fa8600 | 962 | __STATIC_INLINE void LL_RCC_HSI48_Disable(void) |
AnnaBridge | 157:e7ca05fa8600 | 963 | { |
AnnaBridge | 157:e7ca05fa8600 | 964 | CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); |
AnnaBridge | 157:e7ca05fa8600 | 965 | } |
AnnaBridge | 157:e7ca05fa8600 | 966 | |
AnnaBridge | 157:e7ca05fa8600 | 967 | /** |
AnnaBridge | 157:e7ca05fa8600 | 968 | * @brief Check if HSI48 oscillator Ready |
AnnaBridge | 157:e7ca05fa8600 | 969 | * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady |
AnnaBridge | 157:e7ca05fa8600 | 970 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 971 | */ |
AnnaBridge | 157:e7ca05fa8600 | 972 | __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) |
AnnaBridge | 157:e7ca05fa8600 | 973 | { |
AnnaBridge | 157:e7ca05fa8600 | 974 | return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)); |
AnnaBridge | 157:e7ca05fa8600 | 975 | } |
AnnaBridge | 157:e7ca05fa8600 | 976 | |
AnnaBridge | 157:e7ca05fa8600 | 977 | /** |
AnnaBridge | 157:e7ca05fa8600 | 978 | * @brief Get HSI48 Calibration value |
AnnaBridge | 157:e7ca05fa8600 | 979 | * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration |
AnnaBridge | 157:e7ca05fa8600 | 980 | * @retval Between Min_Data = 0x00 and Max_Data = 0xFF |
AnnaBridge | 157:e7ca05fa8600 | 981 | */ |
AnnaBridge | 157:e7ca05fa8600 | 982 | __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) |
AnnaBridge | 157:e7ca05fa8600 | 983 | { |
AnnaBridge | 157:e7ca05fa8600 | 984 | return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_POSITION_HSI48CAL); |
AnnaBridge | 157:e7ca05fa8600 | 985 | } |
AnnaBridge | 157:e7ca05fa8600 | 986 | |
AnnaBridge | 157:e7ca05fa8600 | 987 | #if defined(RCC_CRRCR_HSI48DIV6OUTEN) |
AnnaBridge | 157:e7ca05fa8600 | 988 | /** |
AnnaBridge | 157:e7ca05fa8600 | 989 | * @brief Enable HSI48 Divider (it divides by 6) |
AnnaBridge | 157:e7ca05fa8600 | 990 | * @rmtoll CRRCR HSI48DIV6OUTEN LL_RCC_HSI48_EnableDivider |
AnnaBridge | 157:e7ca05fa8600 | 991 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 992 | */ |
AnnaBridge | 157:e7ca05fa8600 | 993 | __STATIC_INLINE void LL_RCC_HSI48_EnableDivider(void) |
AnnaBridge | 157:e7ca05fa8600 | 994 | { |
AnnaBridge | 157:e7ca05fa8600 | 995 | SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN); |
AnnaBridge | 157:e7ca05fa8600 | 996 | } |
AnnaBridge | 157:e7ca05fa8600 | 997 | |
AnnaBridge | 157:e7ca05fa8600 | 998 | /** |
AnnaBridge | 157:e7ca05fa8600 | 999 | * @brief Disable HSI48 Divider (it divides by 6) |
AnnaBridge | 157:e7ca05fa8600 | 1000 | * @rmtoll CRRCR HSI48DIV6OUTEN LL_RCC_HSI48_DisableDivider |
AnnaBridge | 157:e7ca05fa8600 | 1001 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1002 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1003 | __STATIC_INLINE void LL_RCC_HSI48_DisableDivider(void) |
AnnaBridge | 157:e7ca05fa8600 | 1004 | { |
AnnaBridge | 157:e7ca05fa8600 | 1005 | CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN); |
AnnaBridge | 157:e7ca05fa8600 | 1006 | } |
AnnaBridge | 157:e7ca05fa8600 | 1007 | |
AnnaBridge | 157:e7ca05fa8600 | 1008 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1009 | * @brief Check if HSI48 Divider is enabled (it divides by 6) |
AnnaBridge | 157:e7ca05fa8600 | 1010 | * @rmtoll CRRCR HSI48DIV6OUTEN LL_RCC_HSI48_IsDivided |
AnnaBridge | 157:e7ca05fa8600 | 1011 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 1012 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1013 | __STATIC_INLINE uint32_t LL_RCC_HSI48_IsDivided(void) |
AnnaBridge | 157:e7ca05fa8600 | 1014 | { |
AnnaBridge | 157:e7ca05fa8600 | 1015 | return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN) == (RCC_CRRCR_HSI48DIV6OUTEN)); |
AnnaBridge | 157:e7ca05fa8600 | 1016 | } |
AnnaBridge | 157:e7ca05fa8600 | 1017 | |
AnnaBridge | 157:e7ca05fa8600 | 1018 | #endif /*RCC_CRRCR_HSI48DIV6OUTEN*/ |
AnnaBridge | 157:e7ca05fa8600 | 1019 | |
AnnaBridge | 157:e7ca05fa8600 | 1020 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1021 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1022 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1023 | |
AnnaBridge | 157:e7ca05fa8600 | 1024 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 157:e7ca05fa8600 | 1025 | |
AnnaBridge | 157:e7ca05fa8600 | 1026 | /** @defgroup RCC_LL_EF_LSE LSE |
AnnaBridge | 157:e7ca05fa8600 | 1027 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 1028 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1029 | |
AnnaBridge | 157:e7ca05fa8600 | 1030 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1031 | * @brief Enable Low Speed External (LSE) crystal. |
AnnaBridge | 157:e7ca05fa8600 | 1032 | * @rmtoll CSR LSEON LL_RCC_LSE_Enable |
AnnaBridge | 157:e7ca05fa8600 | 1033 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1034 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1035 | __STATIC_INLINE void LL_RCC_LSE_Enable(void) |
AnnaBridge | 157:e7ca05fa8600 | 1036 | { |
AnnaBridge | 157:e7ca05fa8600 | 1037 | SET_BIT(RCC->CSR, RCC_CSR_LSEON); |
AnnaBridge | 157:e7ca05fa8600 | 1038 | } |
AnnaBridge | 157:e7ca05fa8600 | 1039 | |
AnnaBridge | 157:e7ca05fa8600 | 1040 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1041 | * @brief Disable Low Speed External (LSE) crystal. |
AnnaBridge | 157:e7ca05fa8600 | 1042 | * @rmtoll CSR LSEON LL_RCC_LSE_Disable |
AnnaBridge | 157:e7ca05fa8600 | 1043 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1044 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1045 | __STATIC_INLINE void LL_RCC_LSE_Disable(void) |
AnnaBridge | 157:e7ca05fa8600 | 1046 | { |
AnnaBridge | 157:e7ca05fa8600 | 1047 | CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); |
AnnaBridge | 157:e7ca05fa8600 | 1048 | } |
AnnaBridge | 157:e7ca05fa8600 | 1049 | |
AnnaBridge | 157:e7ca05fa8600 | 1050 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1051 | * @brief Enable external clock source (LSE bypass). |
AnnaBridge | 157:e7ca05fa8600 | 1052 | * @rmtoll CSR LSEBYP LL_RCC_LSE_EnableBypass |
AnnaBridge | 157:e7ca05fa8600 | 1053 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1054 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1055 | __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) |
AnnaBridge | 157:e7ca05fa8600 | 1056 | { |
AnnaBridge | 157:e7ca05fa8600 | 1057 | SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); |
AnnaBridge | 157:e7ca05fa8600 | 1058 | } |
AnnaBridge | 157:e7ca05fa8600 | 1059 | |
AnnaBridge | 157:e7ca05fa8600 | 1060 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1061 | * @brief Disable external clock source (LSE bypass). |
AnnaBridge | 157:e7ca05fa8600 | 1062 | * @rmtoll CSR LSEBYP LL_RCC_LSE_DisableBypass |
AnnaBridge | 157:e7ca05fa8600 | 1063 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1064 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1065 | __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) |
AnnaBridge | 157:e7ca05fa8600 | 1066 | { |
AnnaBridge | 157:e7ca05fa8600 | 1067 | CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); |
AnnaBridge | 157:e7ca05fa8600 | 1068 | } |
AnnaBridge | 157:e7ca05fa8600 | 1069 | |
AnnaBridge | 157:e7ca05fa8600 | 1070 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1071 | * @brief Set LSE oscillator drive capability |
AnnaBridge | 157:e7ca05fa8600 | 1072 | * @note The oscillator is in Xtal mode when it is not in bypass mode. |
AnnaBridge | 157:e7ca05fa8600 | 1073 | * @rmtoll CSR LSEDRV LL_RCC_LSE_SetDriveCapability |
AnnaBridge | 157:e7ca05fa8600 | 1074 | * @param LSEDrive This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1075 | * @arg @ref LL_RCC_LSEDRIVE_LOW |
AnnaBridge | 157:e7ca05fa8600 | 1076 | * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW |
AnnaBridge | 157:e7ca05fa8600 | 1077 | * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH |
AnnaBridge | 157:e7ca05fa8600 | 1078 | * @arg @ref LL_RCC_LSEDRIVE_HIGH |
AnnaBridge | 157:e7ca05fa8600 | 1079 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1080 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1081 | __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) |
AnnaBridge | 157:e7ca05fa8600 | 1082 | { |
AnnaBridge | 157:e7ca05fa8600 | 1083 | MODIFY_REG(RCC->CSR, RCC_CSR_LSEDRV, LSEDrive); |
AnnaBridge | 157:e7ca05fa8600 | 1084 | } |
AnnaBridge | 157:e7ca05fa8600 | 1085 | |
AnnaBridge | 157:e7ca05fa8600 | 1086 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1087 | * @brief Get LSE oscillator drive capability |
AnnaBridge | 157:e7ca05fa8600 | 1088 | * @rmtoll CSR LSEDRV LL_RCC_LSE_GetDriveCapability |
AnnaBridge | 157:e7ca05fa8600 | 1089 | * @retval Returned value can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1090 | * @arg @ref LL_RCC_LSEDRIVE_LOW |
AnnaBridge | 157:e7ca05fa8600 | 1091 | * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW |
AnnaBridge | 157:e7ca05fa8600 | 1092 | * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH |
AnnaBridge | 157:e7ca05fa8600 | 1093 | * @arg @ref LL_RCC_LSEDRIVE_HIGH |
AnnaBridge | 157:e7ca05fa8600 | 1094 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1095 | __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) |
AnnaBridge | 157:e7ca05fa8600 | 1096 | { |
AnnaBridge | 157:e7ca05fa8600 | 1097 | return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_LSEDRV)); |
AnnaBridge | 157:e7ca05fa8600 | 1098 | } |
AnnaBridge | 157:e7ca05fa8600 | 1099 | |
AnnaBridge | 157:e7ca05fa8600 | 1100 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1101 | * @brief Enable Clock security system on LSE. |
AnnaBridge | 157:e7ca05fa8600 | 1102 | * @rmtoll CSR LSECSSON LL_RCC_LSE_EnableCSS |
AnnaBridge | 157:e7ca05fa8600 | 1103 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1104 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1105 | __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) |
AnnaBridge | 157:e7ca05fa8600 | 1106 | { |
AnnaBridge | 157:e7ca05fa8600 | 1107 | SET_BIT(RCC->CSR, RCC_CSR_LSECSSON); |
AnnaBridge | 157:e7ca05fa8600 | 1108 | } |
AnnaBridge | 157:e7ca05fa8600 | 1109 | |
AnnaBridge | 157:e7ca05fa8600 | 1110 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1111 | * @brief Disable Clock security system on LSE. |
AnnaBridge | 157:e7ca05fa8600 | 1112 | * @note Clock security system can be disabled only after a LSE |
AnnaBridge | 157:e7ca05fa8600 | 1113 | * failure detection. In that case it MUST be disabled by software. |
AnnaBridge | 157:e7ca05fa8600 | 1114 | * @rmtoll CSR LSECSSON LL_RCC_LSE_DisableCSS |
AnnaBridge | 157:e7ca05fa8600 | 1115 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1116 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1117 | __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) |
AnnaBridge | 157:e7ca05fa8600 | 1118 | { |
AnnaBridge | 157:e7ca05fa8600 | 1119 | CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON); |
AnnaBridge | 157:e7ca05fa8600 | 1120 | } |
AnnaBridge | 157:e7ca05fa8600 | 1121 | |
AnnaBridge | 157:e7ca05fa8600 | 1122 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1123 | * @brief Check if LSE oscillator Ready |
AnnaBridge | 157:e7ca05fa8600 | 1124 | * @rmtoll CSR LSERDY LL_RCC_LSE_IsReady |
AnnaBridge | 157:e7ca05fa8600 | 1125 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 1126 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1127 | __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) |
AnnaBridge | 157:e7ca05fa8600 | 1128 | { |
AnnaBridge | 157:e7ca05fa8600 | 1129 | return (READ_BIT(RCC->CSR, RCC_CSR_LSERDY) == (RCC_CSR_LSERDY)); |
AnnaBridge | 157:e7ca05fa8600 | 1130 | } |
AnnaBridge | 157:e7ca05fa8600 | 1131 | |
AnnaBridge | 157:e7ca05fa8600 | 1132 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1133 | * @brief Check if CSS on LSE failure Detection |
AnnaBridge | 157:e7ca05fa8600 | 1134 | * @rmtoll CSR LSECSSD LL_RCC_LSE_IsCSSDetected |
AnnaBridge | 157:e7ca05fa8600 | 1135 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 1136 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1137 | __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) |
AnnaBridge | 157:e7ca05fa8600 | 1138 | { |
AnnaBridge | 157:e7ca05fa8600 | 1139 | return (READ_BIT(RCC->CSR, RCC_CSR_LSECSSD) == (RCC_CSR_LSECSSD)); |
AnnaBridge | 157:e7ca05fa8600 | 1140 | } |
AnnaBridge | 157:e7ca05fa8600 | 1141 | |
AnnaBridge | 157:e7ca05fa8600 | 1142 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1143 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1144 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1145 | |
AnnaBridge | 157:e7ca05fa8600 | 1146 | /** @defgroup RCC_LL_EF_LSI LSI |
AnnaBridge | 157:e7ca05fa8600 | 1147 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 1148 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1149 | |
AnnaBridge | 157:e7ca05fa8600 | 1150 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1151 | * @brief Enable LSI Oscillator |
AnnaBridge | 157:e7ca05fa8600 | 1152 | * @rmtoll CSR LSION LL_RCC_LSI_Enable |
AnnaBridge | 157:e7ca05fa8600 | 1153 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1154 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1155 | __STATIC_INLINE void LL_RCC_LSI_Enable(void) |
AnnaBridge | 157:e7ca05fa8600 | 1156 | { |
AnnaBridge | 157:e7ca05fa8600 | 1157 | SET_BIT(RCC->CSR, RCC_CSR_LSION); |
AnnaBridge | 157:e7ca05fa8600 | 1158 | } |
AnnaBridge | 157:e7ca05fa8600 | 1159 | |
AnnaBridge | 157:e7ca05fa8600 | 1160 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1161 | * @brief Disable LSI Oscillator |
AnnaBridge | 157:e7ca05fa8600 | 1162 | * @rmtoll CSR LSION LL_RCC_LSI_Disable |
AnnaBridge | 157:e7ca05fa8600 | 1163 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1164 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1165 | __STATIC_INLINE void LL_RCC_LSI_Disable(void) |
AnnaBridge | 157:e7ca05fa8600 | 1166 | { |
AnnaBridge | 157:e7ca05fa8600 | 1167 | CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); |
AnnaBridge | 157:e7ca05fa8600 | 1168 | } |
AnnaBridge | 157:e7ca05fa8600 | 1169 | |
AnnaBridge | 157:e7ca05fa8600 | 1170 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1171 | * @brief Check if LSI is Ready |
AnnaBridge | 157:e7ca05fa8600 | 1172 | * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady |
AnnaBridge | 157:e7ca05fa8600 | 1173 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 1174 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1175 | __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) |
AnnaBridge | 157:e7ca05fa8600 | 1176 | { |
AnnaBridge | 157:e7ca05fa8600 | 1177 | return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); |
AnnaBridge | 157:e7ca05fa8600 | 1178 | } |
AnnaBridge | 157:e7ca05fa8600 | 1179 | |
AnnaBridge | 157:e7ca05fa8600 | 1180 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1181 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1182 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1183 | |
AnnaBridge | 157:e7ca05fa8600 | 1184 | /** @defgroup RCC_LL_EF_MSI MSI |
AnnaBridge | 157:e7ca05fa8600 | 1185 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 1186 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1187 | |
AnnaBridge | 157:e7ca05fa8600 | 1188 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1189 | * @brief Enable MSI oscillator |
AnnaBridge | 157:e7ca05fa8600 | 1190 | * @rmtoll CR MSION LL_RCC_MSI_Enable |
AnnaBridge | 157:e7ca05fa8600 | 1191 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1192 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1193 | __STATIC_INLINE void LL_RCC_MSI_Enable(void) |
AnnaBridge | 157:e7ca05fa8600 | 1194 | { |
AnnaBridge | 157:e7ca05fa8600 | 1195 | SET_BIT(RCC->CR, RCC_CR_MSION); |
AnnaBridge | 157:e7ca05fa8600 | 1196 | } |
AnnaBridge | 157:e7ca05fa8600 | 1197 | |
AnnaBridge | 157:e7ca05fa8600 | 1198 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1199 | * @brief Disable MSI oscillator |
AnnaBridge | 157:e7ca05fa8600 | 1200 | * @rmtoll CR MSION LL_RCC_MSI_Disable |
AnnaBridge | 157:e7ca05fa8600 | 1201 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1202 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1203 | __STATIC_INLINE void LL_RCC_MSI_Disable(void) |
AnnaBridge | 157:e7ca05fa8600 | 1204 | { |
AnnaBridge | 157:e7ca05fa8600 | 1205 | CLEAR_BIT(RCC->CR, RCC_CR_MSION); |
AnnaBridge | 157:e7ca05fa8600 | 1206 | } |
AnnaBridge | 157:e7ca05fa8600 | 1207 | |
AnnaBridge | 157:e7ca05fa8600 | 1208 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1209 | * @brief Check if MSI oscillator Ready |
AnnaBridge | 157:e7ca05fa8600 | 1210 | * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady |
AnnaBridge | 157:e7ca05fa8600 | 1211 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 1212 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1213 | __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void) |
AnnaBridge | 157:e7ca05fa8600 | 1214 | { |
AnnaBridge | 157:e7ca05fa8600 | 1215 | return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)); |
AnnaBridge | 157:e7ca05fa8600 | 1216 | } |
AnnaBridge | 157:e7ca05fa8600 | 1217 | |
AnnaBridge | 157:e7ca05fa8600 | 1218 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1219 | * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode. |
AnnaBridge | 157:e7ca05fa8600 | 1220 | * @rmtoll ICSCR MSIRANGE LL_RCC_MSI_SetRange |
AnnaBridge | 157:e7ca05fa8600 | 1221 | * @param Range This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1222 | * @arg @ref LL_RCC_MSIRANGE_0 |
AnnaBridge | 157:e7ca05fa8600 | 1223 | * @arg @ref LL_RCC_MSIRANGE_1 |
AnnaBridge | 157:e7ca05fa8600 | 1224 | * @arg @ref LL_RCC_MSIRANGE_2 |
AnnaBridge | 157:e7ca05fa8600 | 1225 | * @arg @ref LL_RCC_MSIRANGE_3 |
AnnaBridge | 157:e7ca05fa8600 | 1226 | * @arg @ref LL_RCC_MSIRANGE_4 |
AnnaBridge | 157:e7ca05fa8600 | 1227 | * @arg @ref LL_RCC_MSIRANGE_5 |
AnnaBridge | 157:e7ca05fa8600 | 1228 | * @arg @ref LL_RCC_MSIRANGE_6 |
AnnaBridge | 157:e7ca05fa8600 | 1229 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1230 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1231 | __STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range) |
AnnaBridge | 157:e7ca05fa8600 | 1232 | { |
AnnaBridge | 157:e7ca05fa8600 | 1233 | MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, Range); |
AnnaBridge | 157:e7ca05fa8600 | 1234 | } |
AnnaBridge | 157:e7ca05fa8600 | 1235 | |
AnnaBridge | 157:e7ca05fa8600 | 1236 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1237 | * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode. |
AnnaBridge | 157:e7ca05fa8600 | 1238 | * @rmtoll ICSCR MSIRANGE LL_RCC_MSI_GetRange |
AnnaBridge | 157:e7ca05fa8600 | 1239 | * @retval Returned value can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1240 | * @arg @ref LL_RCC_MSIRANGE_0 |
AnnaBridge | 157:e7ca05fa8600 | 1241 | * @arg @ref LL_RCC_MSIRANGE_1 |
AnnaBridge | 157:e7ca05fa8600 | 1242 | * @arg @ref LL_RCC_MSIRANGE_2 |
AnnaBridge | 157:e7ca05fa8600 | 1243 | * @arg @ref LL_RCC_MSIRANGE_3 |
AnnaBridge | 157:e7ca05fa8600 | 1244 | * @arg @ref LL_RCC_MSIRANGE_4 |
AnnaBridge | 157:e7ca05fa8600 | 1245 | * @arg @ref LL_RCC_MSIRANGE_5 |
AnnaBridge | 157:e7ca05fa8600 | 1246 | * @arg @ref LL_RCC_MSIRANGE_6 |
AnnaBridge | 157:e7ca05fa8600 | 1247 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1248 | __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void) |
AnnaBridge | 157:e7ca05fa8600 | 1249 | { |
AnnaBridge | 157:e7ca05fa8600 | 1250 | return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE)); |
AnnaBridge | 157:e7ca05fa8600 | 1251 | } |
AnnaBridge | 157:e7ca05fa8600 | 1252 | |
AnnaBridge | 157:e7ca05fa8600 | 1253 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1254 | * @brief Get MSI Calibration value |
AnnaBridge | 157:e7ca05fa8600 | 1255 | * @note When MSITRIM is written, MSICAL is updated with the sum of |
AnnaBridge | 157:e7ca05fa8600 | 1256 | * MSITRIM and the factory trim value |
AnnaBridge | 157:e7ca05fa8600 | 1257 | * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration |
AnnaBridge | 157:e7ca05fa8600 | 1258 | * @retval Between Min_Data = 0x00 and Max_Data = 0xFF |
AnnaBridge | 157:e7ca05fa8600 | 1259 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1260 | __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void) |
AnnaBridge | 157:e7ca05fa8600 | 1261 | { |
AnnaBridge | 157:e7ca05fa8600 | 1262 | return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_POSITION_MSICAL); |
AnnaBridge | 157:e7ca05fa8600 | 1263 | } |
AnnaBridge | 157:e7ca05fa8600 | 1264 | |
AnnaBridge | 157:e7ca05fa8600 | 1265 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1266 | * @brief Set MSI Calibration trimming |
AnnaBridge | 157:e7ca05fa8600 | 1267 | * @note user-programmable trimming value that is added to the MSICAL |
AnnaBridge | 157:e7ca05fa8600 | 1268 | * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming |
AnnaBridge | 157:e7ca05fa8600 | 1269 | * @param Value between Min_Data = 0x00 and Max_Data = 0xFF |
AnnaBridge | 157:e7ca05fa8600 | 1270 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1271 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1272 | __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value) |
AnnaBridge | 157:e7ca05fa8600 | 1273 | { |
AnnaBridge | 157:e7ca05fa8600 | 1274 | MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_POSITION_MSITRIM); |
AnnaBridge | 157:e7ca05fa8600 | 1275 | } |
AnnaBridge | 157:e7ca05fa8600 | 1276 | |
AnnaBridge | 157:e7ca05fa8600 | 1277 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1278 | * @brief Get MSI Calibration trimming |
AnnaBridge | 157:e7ca05fa8600 | 1279 | * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming |
AnnaBridge | 157:e7ca05fa8600 | 1280 | * @retval Between Min_Data = 0x00 and Max_Data = 0xFF |
AnnaBridge | 157:e7ca05fa8600 | 1281 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1282 | __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void) |
AnnaBridge | 157:e7ca05fa8600 | 1283 | { |
AnnaBridge | 157:e7ca05fa8600 | 1284 | return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_POSITION_MSITRIM); |
AnnaBridge | 157:e7ca05fa8600 | 1285 | } |
AnnaBridge | 157:e7ca05fa8600 | 1286 | |
AnnaBridge | 157:e7ca05fa8600 | 1287 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1288 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1289 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1290 | |
AnnaBridge | 157:e7ca05fa8600 | 1291 | /** @defgroup RCC_LL_EF_System System |
AnnaBridge | 157:e7ca05fa8600 | 1292 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 1293 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1294 | |
AnnaBridge | 157:e7ca05fa8600 | 1295 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1296 | * @brief Configure the system clock source |
AnnaBridge | 157:e7ca05fa8600 | 1297 | * @rmtoll CFGR SW LL_RCC_SetSysClkSource |
AnnaBridge | 157:e7ca05fa8600 | 1298 | * @param Source This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1299 | * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI |
AnnaBridge | 157:e7ca05fa8600 | 1300 | * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI |
AnnaBridge | 157:e7ca05fa8600 | 1301 | * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE |
AnnaBridge | 157:e7ca05fa8600 | 1302 | * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL |
AnnaBridge | 157:e7ca05fa8600 | 1303 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1304 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1305 | __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) |
AnnaBridge | 157:e7ca05fa8600 | 1306 | { |
AnnaBridge | 157:e7ca05fa8600 | 1307 | MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); |
AnnaBridge | 157:e7ca05fa8600 | 1308 | } |
AnnaBridge | 157:e7ca05fa8600 | 1309 | |
AnnaBridge | 157:e7ca05fa8600 | 1310 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1311 | * @brief Get the system clock source |
AnnaBridge | 157:e7ca05fa8600 | 1312 | * @rmtoll CFGR SWS LL_RCC_GetSysClkSource |
AnnaBridge | 157:e7ca05fa8600 | 1313 | * @retval Returned value can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1314 | * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI |
AnnaBridge | 157:e7ca05fa8600 | 1315 | * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI |
AnnaBridge | 157:e7ca05fa8600 | 1316 | * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE |
AnnaBridge | 157:e7ca05fa8600 | 1317 | * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL |
AnnaBridge | 157:e7ca05fa8600 | 1318 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1319 | __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) |
AnnaBridge | 157:e7ca05fa8600 | 1320 | { |
AnnaBridge | 157:e7ca05fa8600 | 1321 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); |
AnnaBridge | 157:e7ca05fa8600 | 1322 | } |
AnnaBridge | 157:e7ca05fa8600 | 1323 | |
AnnaBridge | 157:e7ca05fa8600 | 1324 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1325 | * @brief Set AHB prescaler |
AnnaBridge | 157:e7ca05fa8600 | 1326 | * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler |
AnnaBridge | 157:e7ca05fa8600 | 1327 | * @param Prescaler This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1328 | * @arg @ref LL_RCC_SYSCLK_DIV_1 |
AnnaBridge | 157:e7ca05fa8600 | 1329 | * @arg @ref LL_RCC_SYSCLK_DIV_2 |
AnnaBridge | 157:e7ca05fa8600 | 1330 | * @arg @ref LL_RCC_SYSCLK_DIV_4 |
AnnaBridge | 157:e7ca05fa8600 | 1331 | * @arg @ref LL_RCC_SYSCLK_DIV_8 |
AnnaBridge | 157:e7ca05fa8600 | 1332 | * @arg @ref LL_RCC_SYSCLK_DIV_16 |
AnnaBridge | 157:e7ca05fa8600 | 1333 | * @arg @ref LL_RCC_SYSCLK_DIV_64 |
AnnaBridge | 157:e7ca05fa8600 | 1334 | * @arg @ref LL_RCC_SYSCLK_DIV_128 |
AnnaBridge | 157:e7ca05fa8600 | 1335 | * @arg @ref LL_RCC_SYSCLK_DIV_256 |
AnnaBridge | 157:e7ca05fa8600 | 1336 | * @arg @ref LL_RCC_SYSCLK_DIV_512 |
AnnaBridge | 157:e7ca05fa8600 | 1337 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1338 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1339 | __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) |
AnnaBridge | 157:e7ca05fa8600 | 1340 | { |
AnnaBridge | 157:e7ca05fa8600 | 1341 | MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); |
AnnaBridge | 157:e7ca05fa8600 | 1342 | } |
AnnaBridge | 157:e7ca05fa8600 | 1343 | |
AnnaBridge | 157:e7ca05fa8600 | 1344 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1345 | * @brief Set APB1 prescaler |
AnnaBridge | 157:e7ca05fa8600 | 1346 | * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler |
AnnaBridge | 157:e7ca05fa8600 | 1347 | * @param Prescaler This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1348 | * @arg @ref LL_RCC_APB1_DIV_1 |
AnnaBridge | 157:e7ca05fa8600 | 1349 | * @arg @ref LL_RCC_APB1_DIV_2 |
AnnaBridge | 157:e7ca05fa8600 | 1350 | * @arg @ref LL_RCC_APB1_DIV_4 |
AnnaBridge | 157:e7ca05fa8600 | 1351 | * @arg @ref LL_RCC_APB1_DIV_8 |
AnnaBridge | 157:e7ca05fa8600 | 1352 | * @arg @ref LL_RCC_APB1_DIV_16 |
AnnaBridge | 157:e7ca05fa8600 | 1353 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1354 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1355 | __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) |
AnnaBridge | 157:e7ca05fa8600 | 1356 | { |
AnnaBridge | 157:e7ca05fa8600 | 1357 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); |
AnnaBridge | 157:e7ca05fa8600 | 1358 | } |
AnnaBridge | 157:e7ca05fa8600 | 1359 | |
AnnaBridge | 157:e7ca05fa8600 | 1360 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1361 | * @brief Set APB2 prescaler |
AnnaBridge | 157:e7ca05fa8600 | 1362 | * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler |
AnnaBridge | 157:e7ca05fa8600 | 1363 | * @param Prescaler This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1364 | * @arg @ref LL_RCC_APB2_DIV_1 |
AnnaBridge | 157:e7ca05fa8600 | 1365 | * @arg @ref LL_RCC_APB2_DIV_2 |
AnnaBridge | 157:e7ca05fa8600 | 1366 | * @arg @ref LL_RCC_APB2_DIV_4 |
AnnaBridge | 157:e7ca05fa8600 | 1367 | * @arg @ref LL_RCC_APB2_DIV_8 |
AnnaBridge | 157:e7ca05fa8600 | 1368 | * @arg @ref LL_RCC_APB2_DIV_16 |
AnnaBridge | 157:e7ca05fa8600 | 1369 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1370 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1371 | __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) |
AnnaBridge | 157:e7ca05fa8600 | 1372 | { |
AnnaBridge | 157:e7ca05fa8600 | 1373 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); |
AnnaBridge | 157:e7ca05fa8600 | 1374 | } |
AnnaBridge | 157:e7ca05fa8600 | 1375 | |
AnnaBridge | 157:e7ca05fa8600 | 1376 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1377 | * @brief Get AHB prescaler |
AnnaBridge | 157:e7ca05fa8600 | 1378 | * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler |
AnnaBridge | 157:e7ca05fa8600 | 1379 | * @retval Returned value can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1380 | * @arg @ref LL_RCC_SYSCLK_DIV_1 |
AnnaBridge | 157:e7ca05fa8600 | 1381 | * @arg @ref LL_RCC_SYSCLK_DIV_2 |
AnnaBridge | 157:e7ca05fa8600 | 1382 | * @arg @ref LL_RCC_SYSCLK_DIV_4 |
AnnaBridge | 157:e7ca05fa8600 | 1383 | * @arg @ref LL_RCC_SYSCLK_DIV_8 |
AnnaBridge | 157:e7ca05fa8600 | 1384 | * @arg @ref LL_RCC_SYSCLK_DIV_16 |
AnnaBridge | 157:e7ca05fa8600 | 1385 | * @arg @ref LL_RCC_SYSCLK_DIV_64 |
AnnaBridge | 157:e7ca05fa8600 | 1386 | * @arg @ref LL_RCC_SYSCLK_DIV_128 |
AnnaBridge | 157:e7ca05fa8600 | 1387 | * @arg @ref LL_RCC_SYSCLK_DIV_256 |
AnnaBridge | 157:e7ca05fa8600 | 1388 | * @arg @ref LL_RCC_SYSCLK_DIV_512 |
AnnaBridge | 157:e7ca05fa8600 | 1389 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1390 | __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) |
AnnaBridge | 157:e7ca05fa8600 | 1391 | { |
AnnaBridge | 157:e7ca05fa8600 | 1392 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); |
AnnaBridge | 157:e7ca05fa8600 | 1393 | } |
AnnaBridge | 157:e7ca05fa8600 | 1394 | |
AnnaBridge | 157:e7ca05fa8600 | 1395 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1396 | * @brief Get APB1 prescaler |
AnnaBridge | 157:e7ca05fa8600 | 1397 | * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler |
AnnaBridge | 157:e7ca05fa8600 | 1398 | * @retval Returned value can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1399 | * @arg @ref LL_RCC_APB1_DIV_1 |
AnnaBridge | 157:e7ca05fa8600 | 1400 | * @arg @ref LL_RCC_APB1_DIV_2 |
AnnaBridge | 157:e7ca05fa8600 | 1401 | * @arg @ref LL_RCC_APB1_DIV_4 |
AnnaBridge | 157:e7ca05fa8600 | 1402 | * @arg @ref LL_RCC_APB1_DIV_8 |
AnnaBridge | 157:e7ca05fa8600 | 1403 | * @arg @ref LL_RCC_APB1_DIV_16 |
AnnaBridge | 157:e7ca05fa8600 | 1404 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1405 | __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) |
AnnaBridge | 157:e7ca05fa8600 | 1406 | { |
AnnaBridge | 157:e7ca05fa8600 | 1407 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); |
AnnaBridge | 157:e7ca05fa8600 | 1408 | } |
AnnaBridge | 157:e7ca05fa8600 | 1409 | |
AnnaBridge | 157:e7ca05fa8600 | 1410 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1411 | * @brief Get APB2 prescaler |
AnnaBridge | 157:e7ca05fa8600 | 1412 | * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler |
AnnaBridge | 157:e7ca05fa8600 | 1413 | * @retval Returned value can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1414 | * @arg @ref LL_RCC_APB2_DIV_1 |
AnnaBridge | 157:e7ca05fa8600 | 1415 | * @arg @ref LL_RCC_APB2_DIV_2 |
AnnaBridge | 157:e7ca05fa8600 | 1416 | * @arg @ref LL_RCC_APB2_DIV_4 |
AnnaBridge | 157:e7ca05fa8600 | 1417 | * @arg @ref LL_RCC_APB2_DIV_8 |
AnnaBridge | 157:e7ca05fa8600 | 1418 | * @arg @ref LL_RCC_APB2_DIV_16 |
AnnaBridge | 157:e7ca05fa8600 | 1419 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1420 | __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) |
AnnaBridge | 157:e7ca05fa8600 | 1421 | { |
AnnaBridge | 157:e7ca05fa8600 | 1422 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); |
AnnaBridge | 157:e7ca05fa8600 | 1423 | } |
AnnaBridge | 157:e7ca05fa8600 | 1424 | |
AnnaBridge | 157:e7ca05fa8600 | 1425 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1426 | * @brief Set Clock After Wake-Up From Stop mode |
AnnaBridge | 157:e7ca05fa8600 | 1427 | * @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop |
AnnaBridge | 157:e7ca05fa8600 | 1428 | * @param Clock This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1429 | * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI |
AnnaBridge | 157:e7ca05fa8600 | 1430 | * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI |
AnnaBridge | 157:e7ca05fa8600 | 1431 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1432 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1433 | __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock) |
AnnaBridge | 157:e7ca05fa8600 | 1434 | { |
AnnaBridge | 157:e7ca05fa8600 | 1435 | MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock); |
AnnaBridge | 157:e7ca05fa8600 | 1436 | } |
AnnaBridge | 157:e7ca05fa8600 | 1437 | |
AnnaBridge | 157:e7ca05fa8600 | 1438 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1439 | * @brief Get Clock After Wake-Up From Stop mode |
AnnaBridge | 157:e7ca05fa8600 | 1440 | * @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop |
AnnaBridge | 157:e7ca05fa8600 | 1441 | * @retval Returned value can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1442 | * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI |
AnnaBridge | 157:e7ca05fa8600 | 1443 | * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI |
AnnaBridge | 157:e7ca05fa8600 | 1444 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1445 | __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void) |
AnnaBridge | 157:e7ca05fa8600 | 1446 | { |
AnnaBridge | 157:e7ca05fa8600 | 1447 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK)); |
AnnaBridge | 157:e7ca05fa8600 | 1448 | } |
AnnaBridge | 157:e7ca05fa8600 | 1449 | |
AnnaBridge | 157:e7ca05fa8600 | 1450 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1451 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1452 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1453 | |
AnnaBridge | 157:e7ca05fa8600 | 1454 | /** @defgroup RCC_LL_EF_MCO MCO |
AnnaBridge | 157:e7ca05fa8600 | 1455 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 1456 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1457 | |
AnnaBridge | 157:e7ca05fa8600 | 1458 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1459 | * @brief Configure MCOx |
AnnaBridge | 157:e7ca05fa8600 | 1460 | * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n |
AnnaBridge | 157:e7ca05fa8600 | 1461 | * CFGR MCOPRE LL_RCC_ConfigMCO |
AnnaBridge | 157:e7ca05fa8600 | 1462 | * @param MCOxSource This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1463 | * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK |
AnnaBridge | 157:e7ca05fa8600 | 1464 | * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK |
AnnaBridge | 157:e7ca05fa8600 | 1465 | * @arg @ref LL_RCC_MCO1SOURCE_HSI |
AnnaBridge | 157:e7ca05fa8600 | 1466 | * @arg @ref LL_RCC_MCO1SOURCE_MSI |
AnnaBridge | 157:e7ca05fa8600 | 1467 | * @arg @ref LL_RCC_MCO1SOURCE_HSE |
AnnaBridge | 157:e7ca05fa8600 | 1468 | * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK |
AnnaBridge | 157:e7ca05fa8600 | 1469 | * @arg @ref LL_RCC_MCO1SOURCE_LSI |
AnnaBridge | 157:e7ca05fa8600 | 1470 | * @arg @ref LL_RCC_MCO1SOURCE_LSE |
AnnaBridge | 157:e7ca05fa8600 | 1471 | * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*) |
AnnaBridge | 157:e7ca05fa8600 | 1472 | * |
AnnaBridge | 157:e7ca05fa8600 | 1473 | * (*) value not defined in all devices. |
AnnaBridge | 157:e7ca05fa8600 | 1474 | * @param MCOxPrescaler This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1475 | * @arg @ref LL_RCC_MCO1_DIV_1 |
AnnaBridge | 157:e7ca05fa8600 | 1476 | * @arg @ref LL_RCC_MCO1_DIV_2 |
AnnaBridge | 157:e7ca05fa8600 | 1477 | * @arg @ref LL_RCC_MCO1_DIV_4 |
AnnaBridge | 157:e7ca05fa8600 | 1478 | * @arg @ref LL_RCC_MCO1_DIV_8 |
AnnaBridge | 157:e7ca05fa8600 | 1479 | * @arg @ref LL_RCC_MCO1_DIV_16 |
AnnaBridge | 157:e7ca05fa8600 | 1480 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1481 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1482 | __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) |
AnnaBridge | 157:e7ca05fa8600 | 1483 | { |
AnnaBridge | 157:e7ca05fa8600 | 1484 | MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); |
AnnaBridge | 157:e7ca05fa8600 | 1485 | } |
AnnaBridge | 157:e7ca05fa8600 | 1486 | |
AnnaBridge | 157:e7ca05fa8600 | 1487 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1488 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1489 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1490 | |
AnnaBridge | 157:e7ca05fa8600 | 1491 | /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source |
AnnaBridge | 157:e7ca05fa8600 | 1492 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 1493 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1494 | |
AnnaBridge | 157:e7ca05fa8600 | 1495 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1496 | * @brief Configure USARTx clock source |
AnnaBridge | 157:e7ca05fa8600 | 1497 | * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource |
AnnaBridge | 157:e7ca05fa8600 | 1498 | * @param USARTxSource This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1499 | * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*) |
AnnaBridge | 157:e7ca05fa8600 | 1500 | * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK (*) |
AnnaBridge | 157:e7ca05fa8600 | 1501 | * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI (*) |
AnnaBridge | 157:e7ca05fa8600 | 1502 | * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE (*) |
AnnaBridge | 157:e7ca05fa8600 | 1503 | * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 |
AnnaBridge | 157:e7ca05fa8600 | 1504 | * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK |
AnnaBridge | 157:e7ca05fa8600 | 1505 | * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI |
AnnaBridge | 157:e7ca05fa8600 | 1506 | * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE |
AnnaBridge | 157:e7ca05fa8600 | 1507 | * |
AnnaBridge | 157:e7ca05fa8600 | 1508 | * (*) value not defined in all devices. |
AnnaBridge | 157:e7ca05fa8600 | 1509 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1510 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1511 | __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) |
AnnaBridge | 157:e7ca05fa8600 | 1512 | { |
AnnaBridge | 157:e7ca05fa8600 | 1513 | MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU)); |
AnnaBridge | 157:e7ca05fa8600 | 1514 | } |
AnnaBridge | 157:e7ca05fa8600 | 1515 | |
AnnaBridge | 157:e7ca05fa8600 | 1516 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1517 | * @brief Configure LPUART1x clock source |
AnnaBridge | 157:e7ca05fa8600 | 1518 | * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource |
AnnaBridge | 157:e7ca05fa8600 | 1519 | * @param LPUARTxSource This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1520 | * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1 |
AnnaBridge | 157:e7ca05fa8600 | 1521 | * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK |
AnnaBridge | 157:e7ca05fa8600 | 1522 | * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI |
AnnaBridge | 157:e7ca05fa8600 | 1523 | * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE |
AnnaBridge | 157:e7ca05fa8600 | 1524 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1525 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1526 | __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) |
AnnaBridge | 157:e7ca05fa8600 | 1527 | { |
AnnaBridge | 157:e7ca05fa8600 | 1528 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource); |
AnnaBridge | 157:e7ca05fa8600 | 1529 | } |
AnnaBridge | 157:e7ca05fa8600 | 1530 | |
AnnaBridge | 157:e7ca05fa8600 | 1531 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1532 | * @brief Configure I2Cx clock source |
AnnaBridge | 157:e7ca05fa8600 | 1533 | * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource |
AnnaBridge | 157:e7ca05fa8600 | 1534 | * @param I2CxSource This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1535 | * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 |
AnnaBridge | 157:e7ca05fa8600 | 1536 | * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK |
AnnaBridge | 157:e7ca05fa8600 | 1537 | * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI |
AnnaBridge | 157:e7ca05fa8600 | 1538 | * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 (*) |
AnnaBridge | 157:e7ca05fa8600 | 1539 | * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*) |
AnnaBridge | 157:e7ca05fa8600 | 1540 | * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*) |
AnnaBridge | 157:e7ca05fa8600 | 1541 | * |
AnnaBridge | 157:e7ca05fa8600 | 1542 | * (*) value not defined in all devices. |
AnnaBridge | 157:e7ca05fa8600 | 1543 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1544 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1545 | __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) |
AnnaBridge | 157:e7ca05fa8600 | 1546 | { |
AnnaBridge | 157:e7ca05fa8600 | 1547 | MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4U) & 0x000FF000U), ((I2CxSource << 4U) & 0x000FF000U)); |
AnnaBridge | 157:e7ca05fa8600 | 1548 | } |
AnnaBridge | 157:e7ca05fa8600 | 1549 | |
AnnaBridge | 157:e7ca05fa8600 | 1550 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1551 | * @brief Configure LPTIMx clock source |
AnnaBridge | 157:e7ca05fa8600 | 1552 | * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource |
AnnaBridge | 157:e7ca05fa8600 | 1553 | * @param LPTIMxSource This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1554 | * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 |
AnnaBridge | 157:e7ca05fa8600 | 1555 | * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI |
AnnaBridge | 157:e7ca05fa8600 | 1556 | * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI |
AnnaBridge | 157:e7ca05fa8600 | 1557 | * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE |
AnnaBridge | 157:e7ca05fa8600 | 1558 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1559 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1560 | __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) |
AnnaBridge | 157:e7ca05fa8600 | 1561 | { |
AnnaBridge | 157:e7ca05fa8600 | 1562 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, LPTIMxSource); |
AnnaBridge | 157:e7ca05fa8600 | 1563 | } |
AnnaBridge | 157:e7ca05fa8600 | 1564 | |
AnnaBridge | 157:e7ca05fa8600 | 1565 | #if defined(RCC_CCIPR_HSI48SEL) |
AnnaBridge | 157:e7ca05fa8600 | 1566 | #if defined(RNG) |
AnnaBridge | 157:e7ca05fa8600 | 1567 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1568 | * @brief Configure RNG clock source |
AnnaBridge | 157:e7ca05fa8600 | 1569 | * @rmtoll CCIPR HSI48SEL LL_RCC_SetRNGClockSource |
AnnaBridge | 157:e7ca05fa8600 | 1570 | * @param RNGxSource This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1571 | * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL |
AnnaBridge | 157:e7ca05fa8600 | 1572 | * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 |
AnnaBridge | 157:e7ca05fa8600 | 1573 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1574 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1575 | __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) |
AnnaBridge | 157:e7ca05fa8600 | 1576 | { |
AnnaBridge | 157:e7ca05fa8600 | 1577 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, RNGxSource); |
AnnaBridge | 157:e7ca05fa8600 | 1578 | } |
AnnaBridge | 157:e7ca05fa8600 | 1579 | #endif /* RNG */ |
AnnaBridge | 157:e7ca05fa8600 | 1580 | |
AnnaBridge | 157:e7ca05fa8600 | 1581 | #if defined(USB) |
AnnaBridge | 157:e7ca05fa8600 | 1582 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1583 | * @brief Configure USB clock source |
AnnaBridge | 157:e7ca05fa8600 | 1584 | * @rmtoll CCIPR HSI48SEL LL_RCC_SetUSBClockSource |
AnnaBridge | 157:e7ca05fa8600 | 1585 | * @param USBxSource This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1586 | * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL |
AnnaBridge | 157:e7ca05fa8600 | 1587 | * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 |
AnnaBridge | 157:e7ca05fa8600 | 1588 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1589 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1590 | __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) |
AnnaBridge | 157:e7ca05fa8600 | 1591 | { |
AnnaBridge | 157:e7ca05fa8600 | 1592 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, USBxSource); |
AnnaBridge | 157:e7ca05fa8600 | 1593 | } |
AnnaBridge | 157:e7ca05fa8600 | 1594 | #endif /* USB */ |
AnnaBridge | 157:e7ca05fa8600 | 1595 | |
AnnaBridge | 157:e7ca05fa8600 | 1596 | #endif /* RCC_CCIPR_HSI48SEL */ |
AnnaBridge | 157:e7ca05fa8600 | 1597 | |
AnnaBridge | 157:e7ca05fa8600 | 1598 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1599 | * @brief Get USARTx clock source |
AnnaBridge | 157:e7ca05fa8600 | 1600 | * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource |
AnnaBridge | 157:e7ca05fa8600 | 1601 | * @param USARTx This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1602 | * @arg @ref LL_RCC_USART1_CLKSOURCE (*) |
AnnaBridge | 157:e7ca05fa8600 | 1603 | * @arg @ref LL_RCC_USART2_CLKSOURCE |
AnnaBridge | 157:e7ca05fa8600 | 1604 | * @retval Returned value can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1605 | * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*) |
AnnaBridge | 157:e7ca05fa8600 | 1606 | * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK (*) |
AnnaBridge | 157:e7ca05fa8600 | 1607 | * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI (*) |
AnnaBridge | 157:e7ca05fa8600 | 1608 | * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE (*) |
AnnaBridge | 157:e7ca05fa8600 | 1609 | * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 |
AnnaBridge | 157:e7ca05fa8600 | 1610 | * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK |
AnnaBridge | 157:e7ca05fa8600 | 1611 | * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI |
AnnaBridge | 157:e7ca05fa8600 | 1612 | * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE |
AnnaBridge | 157:e7ca05fa8600 | 1613 | * |
AnnaBridge | 157:e7ca05fa8600 | 1614 | * (*) value not defined in all devices. |
AnnaBridge | 157:e7ca05fa8600 | 1615 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1616 | __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) |
AnnaBridge | 157:e7ca05fa8600 | 1617 | { |
AnnaBridge | 157:e7ca05fa8600 | 1618 | return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U)); |
AnnaBridge | 157:e7ca05fa8600 | 1619 | } |
AnnaBridge | 157:e7ca05fa8600 | 1620 | |
AnnaBridge | 157:e7ca05fa8600 | 1621 | |
AnnaBridge | 157:e7ca05fa8600 | 1622 | |
AnnaBridge | 157:e7ca05fa8600 | 1623 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1624 | * @brief Get LPUARTx clock source |
AnnaBridge | 157:e7ca05fa8600 | 1625 | * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource |
AnnaBridge | 157:e7ca05fa8600 | 1626 | * @param LPUARTx This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1627 | * @arg @ref LL_RCC_LPUART1_CLKSOURCE |
AnnaBridge | 157:e7ca05fa8600 | 1628 | * @retval Returned value can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1629 | * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1 |
AnnaBridge | 157:e7ca05fa8600 | 1630 | * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK |
AnnaBridge | 157:e7ca05fa8600 | 1631 | * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI |
AnnaBridge | 157:e7ca05fa8600 | 1632 | * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE |
AnnaBridge | 157:e7ca05fa8600 | 1633 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1634 | __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) |
AnnaBridge | 157:e7ca05fa8600 | 1635 | { |
AnnaBridge | 157:e7ca05fa8600 | 1636 | return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx)); |
AnnaBridge | 157:e7ca05fa8600 | 1637 | } |
AnnaBridge | 157:e7ca05fa8600 | 1638 | |
AnnaBridge | 157:e7ca05fa8600 | 1639 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1640 | * @brief Get I2Cx clock source |
AnnaBridge | 157:e7ca05fa8600 | 1641 | * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource |
AnnaBridge | 157:e7ca05fa8600 | 1642 | * @param I2Cx This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1643 | * @arg @ref LL_RCC_I2C1_CLKSOURCE |
AnnaBridge | 157:e7ca05fa8600 | 1644 | * @arg @ref LL_RCC_I2C3_CLKSOURCE |
AnnaBridge | 157:e7ca05fa8600 | 1645 | * @retval Returned value can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1646 | * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 |
AnnaBridge | 157:e7ca05fa8600 | 1647 | * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK |
AnnaBridge | 157:e7ca05fa8600 | 1648 | * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI |
AnnaBridge | 157:e7ca05fa8600 | 1649 | * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 (*) |
AnnaBridge | 157:e7ca05fa8600 | 1650 | * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*) |
AnnaBridge | 157:e7ca05fa8600 | 1651 | * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*) |
AnnaBridge | 157:e7ca05fa8600 | 1652 | * |
AnnaBridge | 157:e7ca05fa8600 | 1653 | * (*) value not defined in all devices. |
AnnaBridge | 157:e7ca05fa8600 | 1654 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1655 | __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) |
AnnaBridge | 157:e7ca05fa8600 | 1656 | { |
AnnaBridge | 157:e7ca05fa8600 | 1657 | return (uint32_t)((READ_BIT(RCC->CCIPR, I2Cx) >> 4U) | (I2Cx << 4U)); |
AnnaBridge | 157:e7ca05fa8600 | 1658 | } |
AnnaBridge | 157:e7ca05fa8600 | 1659 | |
AnnaBridge | 157:e7ca05fa8600 | 1660 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1661 | * @brief Get LPTIMx clock source |
AnnaBridge | 157:e7ca05fa8600 | 1662 | * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource |
AnnaBridge | 157:e7ca05fa8600 | 1663 | * @param LPTIMx This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1664 | * @arg @ref LL_RCC_LPTIM1_CLKSOURCE |
AnnaBridge | 157:e7ca05fa8600 | 1665 | * @retval Returned value can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1666 | * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 |
AnnaBridge | 157:e7ca05fa8600 | 1667 | * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI |
AnnaBridge | 157:e7ca05fa8600 | 1668 | * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI |
AnnaBridge | 157:e7ca05fa8600 | 1669 | * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE |
AnnaBridge | 157:e7ca05fa8600 | 1670 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1671 | __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) |
AnnaBridge | 157:e7ca05fa8600 | 1672 | { |
AnnaBridge | 157:e7ca05fa8600 | 1673 | return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx)); |
AnnaBridge | 157:e7ca05fa8600 | 1674 | } |
AnnaBridge | 157:e7ca05fa8600 | 1675 | |
AnnaBridge | 157:e7ca05fa8600 | 1676 | #if defined(RCC_CCIPR_HSI48SEL) |
AnnaBridge | 157:e7ca05fa8600 | 1677 | #if defined(RNG) |
AnnaBridge | 157:e7ca05fa8600 | 1678 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1679 | * @brief Get RNGx clock source |
AnnaBridge | 157:e7ca05fa8600 | 1680 | * @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource |
AnnaBridge | 157:e7ca05fa8600 | 1681 | * @param RNGx This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1682 | * @arg @ref LL_RCC_RNG_CLKSOURCE |
AnnaBridge | 157:e7ca05fa8600 | 1683 | * @retval Returned value can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1684 | * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL |
AnnaBridge | 157:e7ca05fa8600 | 1685 | * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 |
AnnaBridge | 157:e7ca05fa8600 | 1686 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1687 | __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) |
AnnaBridge | 157:e7ca05fa8600 | 1688 | { |
AnnaBridge | 157:e7ca05fa8600 | 1689 | return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx)); |
AnnaBridge | 157:e7ca05fa8600 | 1690 | } |
AnnaBridge | 157:e7ca05fa8600 | 1691 | #endif /* RNG */ |
AnnaBridge | 157:e7ca05fa8600 | 1692 | |
AnnaBridge | 157:e7ca05fa8600 | 1693 | #if defined(USB) |
AnnaBridge | 157:e7ca05fa8600 | 1694 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1695 | * @brief Get USBx clock source |
AnnaBridge | 157:e7ca05fa8600 | 1696 | * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource |
AnnaBridge | 157:e7ca05fa8600 | 1697 | * @param USBx This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1698 | * @arg @ref LL_RCC_USB_CLKSOURCE |
AnnaBridge | 157:e7ca05fa8600 | 1699 | * @retval Returned value can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1700 | * @arg @ref LL_RCC_USB_CLKSOURCE_PLL |
AnnaBridge | 157:e7ca05fa8600 | 1701 | * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 |
AnnaBridge | 157:e7ca05fa8600 | 1702 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1703 | __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) |
AnnaBridge | 157:e7ca05fa8600 | 1704 | { |
AnnaBridge | 157:e7ca05fa8600 | 1705 | return (uint32_t)(READ_BIT(RCC->CCIPR, USBx)); |
AnnaBridge | 157:e7ca05fa8600 | 1706 | } |
AnnaBridge | 157:e7ca05fa8600 | 1707 | #endif /* USB */ |
AnnaBridge | 157:e7ca05fa8600 | 1708 | |
AnnaBridge | 157:e7ca05fa8600 | 1709 | #endif /* RCC_CCIPR_HSI48SEL */ |
AnnaBridge | 157:e7ca05fa8600 | 1710 | |
AnnaBridge | 157:e7ca05fa8600 | 1711 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1712 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1713 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1714 | |
AnnaBridge | 157:e7ca05fa8600 | 1715 | /** @defgroup RCC_LL_EF_RTC RTC |
AnnaBridge | 157:e7ca05fa8600 | 1716 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 1717 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1718 | |
AnnaBridge | 157:e7ca05fa8600 | 1719 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1720 | * @brief Set RTC Clock Source |
AnnaBridge | 157:e7ca05fa8600 | 1721 | * @note Once the RTC clock source has been selected, it cannot be changed any more unless |
AnnaBridge | 157:e7ca05fa8600 | 1722 | * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is |
AnnaBridge | 157:e7ca05fa8600 | 1723 | * set). The RTCRST bit can be used to reset them. |
AnnaBridge | 157:e7ca05fa8600 | 1724 | * @rmtoll CSR RTCSEL LL_RCC_SetRTCClockSource |
AnnaBridge | 157:e7ca05fa8600 | 1725 | * @param Source This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1726 | * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE |
AnnaBridge | 157:e7ca05fa8600 | 1727 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE |
AnnaBridge | 157:e7ca05fa8600 | 1728 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI |
AnnaBridge | 157:e7ca05fa8600 | 1729 | * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE |
AnnaBridge | 157:e7ca05fa8600 | 1730 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1731 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1732 | __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) |
AnnaBridge | 157:e7ca05fa8600 | 1733 | { |
AnnaBridge | 157:e7ca05fa8600 | 1734 | MODIFY_REG(RCC->CSR, RCC_CSR_RTCSEL, Source); |
AnnaBridge | 157:e7ca05fa8600 | 1735 | } |
AnnaBridge | 157:e7ca05fa8600 | 1736 | |
AnnaBridge | 157:e7ca05fa8600 | 1737 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1738 | * @brief Get RTC Clock Source |
AnnaBridge | 157:e7ca05fa8600 | 1739 | * @rmtoll CSR RTCSEL LL_RCC_GetRTCClockSource |
AnnaBridge | 157:e7ca05fa8600 | 1740 | * @retval Returned value can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1741 | * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE |
AnnaBridge | 157:e7ca05fa8600 | 1742 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE |
AnnaBridge | 157:e7ca05fa8600 | 1743 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI |
AnnaBridge | 157:e7ca05fa8600 | 1744 | * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE |
AnnaBridge | 157:e7ca05fa8600 | 1745 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1746 | __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) |
AnnaBridge | 157:e7ca05fa8600 | 1747 | { |
AnnaBridge | 157:e7ca05fa8600 | 1748 | return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)); |
AnnaBridge | 157:e7ca05fa8600 | 1749 | } |
AnnaBridge | 157:e7ca05fa8600 | 1750 | |
AnnaBridge | 157:e7ca05fa8600 | 1751 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1752 | * @brief Enable RTC |
AnnaBridge | 157:e7ca05fa8600 | 1753 | * @rmtoll CSR RTCEN LL_RCC_EnableRTC |
AnnaBridge | 157:e7ca05fa8600 | 1754 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1755 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1756 | __STATIC_INLINE void LL_RCC_EnableRTC(void) |
AnnaBridge | 157:e7ca05fa8600 | 1757 | { |
AnnaBridge | 157:e7ca05fa8600 | 1758 | SET_BIT(RCC->CSR, RCC_CSR_RTCEN); |
AnnaBridge | 157:e7ca05fa8600 | 1759 | } |
AnnaBridge | 157:e7ca05fa8600 | 1760 | |
AnnaBridge | 157:e7ca05fa8600 | 1761 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1762 | * @brief Disable RTC |
AnnaBridge | 157:e7ca05fa8600 | 1763 | * @rmtoll CSR RTCEN LL_RCC_DisableRTC |
AnnaBridge | 157:e7ca05fa8600 | 1764 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1765 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1766 | __STATIC_INLINE void LL_RCC_DisableRTC(void) |
AnnaBridge | 157:e7ca05fa8600 | 1767 | { |
AnnaBridge | 157:e7ca05fa8600 | 1768 | CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN); |
AnnaBridge | 157:e7ca05fa8600 | 1769 | } |
AnnaBridge | 157:e7ca05fa8600 | 1770 | |
AnnaBridge | 157:e7ca05fa8600 | 1771 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1772 | * @brief Check if RTC has been enabled or not |
AnnaBridge | 157:e7ca05fa8600 | 1773 | * @rmtoll CSR RTCEN LL_RCC_IsEnabledRTC |
AnnaBridge | 157:e7ca05fa8600 | 1774 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 1775 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1776 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) |
AnnaBridge | 157:e7ca05fa8600 | 1777 | { |
AnnaBridge | 157:e7ca05fa8600 | 1778 | return (READ_BIT(RCC->CSR, RCC_CSR_RTCEN) == (RCC_CSR_RTCEN)); |
AnnaBridge | 157:e7ca05fa8600 | 1779 | } |
AnnaBridge | 157:e7ca05fa8600 | 1780 | |
AnnaBridge | 157:e7ca05fa8600 | 1781 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1782 | * @brief Force the Backup domain reset |
AnnaBridge | 157:e7ca05fa8600 | 1783 | * @rmtoll CSR RTCRST LL_RCC_ForceBackupDomainReset |
AnnaBridge | 157:e7ca05fa8600 | 1784 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1785 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1786 | __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) |
AnnaBridge | 157:e7ca05fa8600 | 1787 | { |
AnnaBridge | 157:e7ca05fa8600 | 1788 | SET_BIT(RCC->CSR, RCC_CSR_RTCRST); |
AnnaBridge | 157:e7ca05fa8600 | 1789 | } |
AnnaBridge | 157:e7ca05fa8600 | 1790 | |
AnnaBridge | 157:e7ca05fa8600 | 1791 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1792 | * @brief Release the Backup domain reset |
AnnaBridge | 157:e7ca05fa8600 | 1793 | * @rmtoll CSR RTCRST LL_RCC_ReleaseBackupDomainReset |
AnnaBridge | 157:e7ca05fa8600 | 1794 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1795 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1796 | __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) |
AnnaBridge | 157:e7ca05fa8600 | 1797 | { |
AnnaBridge | 157:e7ca05fa8600 | 1798 | CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST); |
AnnaBridge | 157:e7ca05fa8600 | 1799 | } |
AnnaBridge | 157:e7ca05fa8600 | 1800 | |
AnnaBridge | 157:e7ca05fa8600 | 1801 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1802 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1803 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1804 | |
AnnaBridge | 157:e7ca05fa8600 | 1805 | /** @defgroup RCC_LL_EF_PLL PLL |
AnnaBridge | 157:e7ca05fa8600 | 1806 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 1807 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1808 | |
AnnaBridge | 157:e7ca05fa8600 | 1809 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1810 | * @brief Enable PLL |
AnnaBridge | 157:e7ca05fa8600 | 1811 | * @rmtoll CR PLLON LL_RCC_PLL_Enable |
AnnaBridge | 157:e7ca05fa8600 | 1812 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1813 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1814 | __STATIC_INLINE void LL_RCC_PLL_Enable(void) |
AnnaBridge | 157:e7ca05fa8600 | 1815 | { |
AnnaBridge | 157:e7ca05fa8600 | 1816 | SET_BIT(RCC->CR, RCC_CR_PLLON); |
AnnaBridge | 157:e7ca05fa8600 | 1817 | } |
AnnaBridge | 157:e7ca05fa8600 | 1818 | |
AnnaBridge | 157:e7ca05fa8600 | 1819 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1820 | * @brief Disable PLL |
AnnaBridge | 157:e7ca05fa8600 | 1821 | * @note Cannot be disabled if the PLL clock is used as the system clock |
AnnaBridge | 157:e7ca05fa8600 | 1822 | * @rmtoll CR PLLON LL_RCC_PLL_Disable |
AnnaBridge | 157:e7ca05fa8600 | 1823 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1824 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1825 | __STATIC_INLINE void LL_RCC_PLL_Disable(void) |
AnnaBridge | 157:e7ca05fa8600 | 1826 | { |
AnnaBridge | 157:e7ca05fa8600 | 1827 | CLEAR_BIT(RCC->CR, RCC_CR_PLLON); |
AnnaBridge | 157:e7ca05fa8600 | 1828 | } |
AnnaBridge | 157:e7ca05fa8600 | 1829 | |
AnnaBridge | 157:e7ca05fa8600 | 1830 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1831 | * @brief Check if PLL Ready |
AnnaBridge | 157:e7ca05fa8600 | 1832 | * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady |
AnnaBridge | 157:e7ca05fa8600 | 1833 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 1834 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1835 | __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) |
AnnaBridge | 157:e7ca05fa8600 | 1836 | { |
AnnaBridge | 157:e7ca05fa8600 | 1837 | return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); |
AnnaBridge | 157:e7ca05fa8600 | 1838 | } |
AnnaBridge | 157:e7ca05fa8600 | 1839 | |
AnnaBridge | 157:e7ca05fa8600 | 1840 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1841 | * @brief Configure PLL used for SYSCLK Domain |
AnnaBridge | 157:e7ca05fa8600 | 1842 | * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n |
AnnaBridge | 157:e7ca05fa8600 | 1843 | * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n |
AnnaBridge | 157:e7ca05fa8600 | 1844 | * CFGR PLLDIV LL_RCC_PLL_ConfigDomain_SYS |
AnnaBridge | 157:e7ca05fa8600 | 1845 | * @param Source This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1846 | * @arg @ref LL_RCC_PLLSOURCE_HSI |
AnnaBridge | 157:e7ca05fa8600 | 1847 | * @arg @ref LL_RCC_PLLSOURCE_HSE |
AnnaBridge | 157:e7ca05fa8600 | 1848 | * @param PLLMul This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1849 | * @arg @ref LL_RCC_PLL_MUL_3 |
AnnaBridge | 157:e7ca05fa8600 | 1850 | * @arg @ref LL_RCC_PLL_MUL_4 |
AnnaBridge | 157:e7ca05fa8600 | 1851 | * @arg @ref LL_RCC_PLL_MUL_6 |
AnnaBridge | 157:e7ca05fa8600 | 1852 | * @arg @ref LL_RCC_PLL_MUL_8 |
AnnaBridge | 157:e7ca05fa8600 | 1853 | * @arg @ref LL_RCC_PLL_MUL_12 |
AnnaBridge | 157:e7ca05fa8600 | 1854 | * @arg @ref LL_RCC_PLL_MUL_16 |
AnnaBridge | 157:e7ca05fa8600 | 1855 | * @arg @ref LL_RCC_PLL_MUL_24 |
AnnaBridge | 157:e7ca05fa8600 | 1856 | * @arg @ref LL_RCC_PLL_MUL_32 |
AnnaBridge | 157:e7ca05fa8600 | 1857 | * @arg @ref LL_RCC_PLL_MUL_48 |
AnnaBridge | 157:e7ca05fa8600 | 1858 | * @param PLLDiv This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1859 | * @arg @ref LL_RCC_PLL_DIV_2 |
AnnaBridge | 157:e7ca05fa8600 | 1860 | * @arg @ref LL_RCC_PLL_DIV_3 |
AnnaBridge | 157:e7ca05fa8600 | 1861 | * @arg @ref LL_RCC_PLL_DIV_4 |
AnnaBridge | 157:e7ca05fa8600 | 1862 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1863 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1864 | __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) |
AnnaBridge | 157:e7ca05fa8600 | 1865 | { |
AnnaBridge | 157:e7ca05fa8600 | 1866 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV, Source | PLLMul | PLLDiv); |
AnnaBridge | 157:e7ca05fa8600 | 1867 | } |
AnnaBridge | 157:e7ca05fa8600 | 1868 | |
AnnaBridge | 157:e7ca05fa8600 | 1869 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1870 | * @brief Get the oscillator used as PLL clock source. |
AnnaBridge | 157:e7ca05fa8600 | 1871 | * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource |
AnnaBridge | 157:e7ca05fa8600 | 1872 | * @retval Returned value can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1873 | * @arg @ref LL_RCC_PLLSOURCE_HSI |
AnnaBridge | 157:e7ca05fa8600 | 1874 | * @arg @ref LL_RCC_PLLSOURCE_HSE |
AnnaBridge | 157:e7ca05fa8600 | 1875 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1876 | __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) |
AnnaBridge | 157:e7ca05fa8600 | 1877 | { |
AnnaBridge | 157:e7ca05fa8600 | 1878 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); |
AnnaBridge | 157:e7ca05fa8600 | 1879 | } |
AnnaBridge | 157:e7ca05fa8600 | 1880 | |
AnnaBridge | 157:e7ca05fa8600 | 1881 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1882 | * @brief Get PLL multiplication Factor |
AnnaBridge | 157:e7ca05fa8600 | 1883 | * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator |
AnnaBridge | 157:e7ca05fa8600 | 1884 | * @retval Returned value can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1885 | * @arg @ref LL_RCC_PLL_MUL_3 |
AnnaBridge | 157:e7ca05fa8600 | 1886 | * @arg @ref LL_RCC_PLL_MUL_4 |
AnnaBridge | 157:e7ca05fa8600 | 1887 | * @arg @ref LL_RCC_PLL_MUL_6 |
AnnaBridge | 157:e7ca05fa8600 | 1888 | * @arg @ref LL_RCC_PLL_MUL_8 |
AnnaBridge | 157:e7ca05fa8600 | 1889 | * @arg @ref LL_RCC_PLL_MUL_12 |
AnnaBridge | 157:e7ca05fa8600 | 1890 | * @arg @ref LL_RCC_PLL_MUL_16 |
AnnaBridge | 157:e7ca05fa8600 | 1891 | * @arg @ref LL_RCC_PLL_MUL_24 |
AnnaBridge | 157:e7ca05fa8600 | 1892 | * @arg @ref LL_RCC_PLL_MUL_32 |
AnnaBridge | 157:e7ca05fa8600 | 1893 | * @arg @ref LL_RCC_PLL_MUL_48 |
AnnaBridge | 157:e7ca05fa8600 | 1894 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1895 | __STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) |
AnnaBridge | 157:e7ca05fa8600 | 1896 | { |
AnnaBridge | 157:e7ca05fa8600 | 1897 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL)); |
AnnaBridge | 157:e7ca05fa8600 | 1898 | } |
AnnaBridge | 157:e7ca05fa8600 | 1899 | |
AnnaBridge | 157:e7ca05fa8600 | 1900 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1901 | * @brief Get Division factor for the main PLL and other PLL |
AnnaBridge | 157:e7ca05fa8600 | 1902 | * @rmtoll CFGR PLLDIV LL_RCC_PLL_GetDivider |
AnnaBridge | 157:e7ca05fa8600 | 1903 | * @retval Returned value can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1904 | * @arg @ref LL_RCC_PLL_DIV_2 |
AnnaBridge | 157:e7ca05fa8600 | 1905 | * @arg @ref LL_RCC_PLL_DIV_3 |
AnnaBridge | 157:e7ca05fa8600 | 1906 | * @arg @ref LL_RCC_PLL_DIV_4 |
AnnaBridge | 157:e7ca05fa8600 | 1907 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1908 | __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) |
AnnaBridge | 157:e7ca05fa8600 | 1909 | { |
AnnaBridge | 157:e7ca05fa8600 | 1910 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV)); |
AnnaBridge | 157:e7ca05fa8600 | 1911 | } |
AnnaBridge | 157:e7ca05fa8600 | 1912 | |
AnnaBridge | 157:e7ca05fa8600 | 1913 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1914 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1915 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1916 | |
AnnaBridge | 157:e7ca05fa8600 | 1917 | /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management |
AnnaBridge | 157:e7ca05fa8600 | 1918 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 1919 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1920 | |
AnnaBridge | 157:e7ca05fa8600 | 1921 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1922 | * @brief Clear LSI ready interrupt flag |
AnnaBridge | 157:e7ca05fa8600 | 1923 | * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY |
AnnaBridge | 157:e7ca05fa8600 | 1924 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1925 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1926 | __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 1927 | { |
AnnaBridge | 157:e7ca05fa8600 | 1928 | SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC); |
AnnaBridge | 157:e7ca05fa8600 | 1929 | } |
AnnaBridge | 157:e7ca05fa8600 | 1930 | |
AnnaBridge | 157:e7ca05fa8600 | 1931 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1932 | * @brief Clear LSE ready interrupt flag |
AnnaBridge | 157:e7ca05fa8600 | 1933 | * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY |
AnnaBridge | 157:e7ca05fa8600 | 1934 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1935 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1936 | __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 1937 | { |
AnnaBridge | 157:e7ca05fa8600 | 1938 | SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); |
AnnaBridge | 157:e7ca05fa8600 | 1939 | } |
AnnaBridge | 157:e7ca05fa8600 | 1940 | |
AnnaBridge | 157:e7ca05fa8600 | 1941 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1942 | * @brief Clear MSI ready interrupt flag |
AnnaBridge | 157:e7ca05fa8600 | 1943 | * @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY |
AnnaBridge | 157:e7ca05fa8600 | 1944 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1945 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1946 | __STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 1947 | { |
AnnaBridge | 157:e7ca05fa8600 | 1948 | SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC); |
AnnaBridge | 157:e7ca05fa8600 | 1949 | } |
AnnaBridge | 157:e7ca05fa8600 | 1950 | |
AnnaBridge | 157:e7ca05fa8600 | 1951 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1952 | * @brief Clear HSI ready interrupt flag |
AnnaBridge | 157:e7ca05fa8600 | 1953 | * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY |
AnnaBridge | 157:e7ca05fa8600 | 1954 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1955 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1956 | __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 1957 | { |
AnnaBridge | 157:e7ca05fa8600 | 1958 | SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC); |
AnnaBridge | 157:e7ca05fa8600 | 1959 | } |
AnnaBridge | 157:e7ca05fa8600 | 1960 | |
AnnaBridge | 157:e7ca05fa8600 | 1961 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1962 | * @brief Clear HSE ready interrupt flag |
AnnaBridge | 157:e7ca05fa8600 | 1963 | * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY |
AnnaBridge | 157:e7ca05fa8600 | 1964 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1965 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1966 | __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 1967 | { |
AnnaBridge | 157:e7ca05fa8600 | 1968 | SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); |
AnnaBridge | 157:e7ca05fa8600 | 1969 | } |
AnnaBridge | 157:e7ca05fa8600 | 1970 | |
AnnaBridge | 157:e7ca05fa8600 | 1971 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1972 | * @brief Clear PLL ready interrupt flag |
AnnaBridge | 157:e7ca05fa8600 | 1973 | * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY |
AnnaBridge | 157:e7ca05fa8600 | 1974 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1975 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1976 | __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 1977 | { |
AnnaBridge | 157:e7ca05fa8600 | 1978 | SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC); |
AnnaBridge | 157:e7ca05fa8600 | 1979 | } |
AnnaBridge | 157:e7ca05fa8600 | 1980 | |
AnnaBridge | 157:e7ca05fa8600 | 1981 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 157:e7ca05fa8600 | 1982 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1983 | * @brief Clear HSI48 ready interrupt flag |
AnnaBridge | 157:e7ca05fa8600 | 1984 | * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY |
AnnaBridge | 157:e7ca05fa8600 | 1985 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1986 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1987 | __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 1988 | { |
AnnaBridge | 157:e7ca05fa8600 | 1989 | SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC); |
AnnaBridge | 157:e7ca05fa8600 | 1990 | } |
AnnaBridge | 157:e7ca05fa8600 | 1991 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 157:e7ca05fa8600 | 1992 | |
AnnaBridge | 157:e7ca05fa8600 | 1993 | #if defined(RCC_HSECSS_SUPPORT) |
AnnaBridge | 157:e7ca05fa8600 | 1994 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1995 | * @brief Clear Clock security system interrupt flag |
AnnaBridge | 157:e7ca05fa8600 | 1996 | * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS |
AnnaBridge | 157:e7ca05fa8600 | 1997 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1998 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1999 | __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) |
AnnaBridge | 157:e7ca05fa8600 | 2000 | { |
AnnaBridge | 157:e7ca05fa8600 | 2001 | SET_BIT(RCC->CICR, RCC_CICR_CSSC); |
AnnaBridge | 157:e7ca05fa8600 | 2002 | } |
AnnaBridge | 157:e7ca05fa8600 | 2003 | #endif /* RCC_HSECSS_SUPPORT */ |
AnnaBridge | 157:e7ca05fa8600 | 2004 | |
AnnaBridge | 157:e7ca05fa8600 | 2005 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2006 | * @brief Clear LSE Clock security system interrupt flag |
AnnaBridge | 157:e7ca05fa8600 | 2007 | * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS |
AnnaBridge | 157:e7ca05fa8600 | 2008 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 2009 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2010 | __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) |
AnnaBridge | 157:e7ca05fa8600 | 2011 | { |
AnnaBridge | 157:e7ca05fa8600 | 2012 | SET_BIT(RCC->CICR, RCC_CICR_LSECSSC); |
AnnaBridge | 157:e7ca05fa8600 | 2013 | } |
AnnaBridge | 157:e7ca05fa8600 | 2014 | |
AnnaBridge | 157:e7ca05fa8600 | 2015 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2016 | * @brief Check if LSI ready interrupt occurred or not |
AnnaBridge | 157:e7ca05fa8600 | 2017 | * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY |
AnnaBridge | 157:e7ca05fa8600 | 2018 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2019 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2020 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2021 | { |
AnnaBridge | 157:e7ca05fa8600 | 2022 | return (READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)); |
AnnaBridge | 157:e7ca05fa8600 | 2023 | } |
AnnaBridge | 157:e7ca05fa8600 | 2024 | |
AnnaBridge | 157:e7ca05fa8600 | 2025 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2026 | * @brief Check if LSE ready interrupt occurred or not |
AnnaBridge | 157:e7ca05fa8600 | 2027 | * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY |
AnnaBridge | 157:e7ca05fa8600 | 2028 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2029 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2030 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2031 | { |
AnnaBridge | 157:e7ca05fa8600 | 2032 | return (READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)); |
AnnaBridge | 157:e7ca05fa8600 | 2033 | } |
AnnaBridge | 157:e7ca05fa8600 | 2034 | |
AnnaBridge | 157:e7ca05fa8600 | 2035 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2036 | * @brief Check if MSI ready interrupt occurred or not |
AnnaBridge | 157:e7ca05fa8600 | 2037 | * @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY |
AnnaBridge | 157:e7ca05fa8600 | 2038 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2039 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2040 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2041 | { |
AnnaBridge | 157:e7ca05fa8600 | 2042 | return (READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF)); |
AnnaBridge | 157:e7ca05fa8600 | 2043 | } |
AnnaBridge | 157:e7ca05fa8600 | 2044 | |
AnnaBridge | 157:e7ca05fa8600 | 2045 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2046 | * @brief Check if HSI ready interrupt occurred or not |
AnnaBridge | 157:e7ca05fa8600 | 2047 | * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY |
AnnaBridge | 157:e7ca05fa8600 | 2048 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2049 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2050 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2051 | { |
AnnaBridge | 157:e7ca05fa8600 | 2052 | return (READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)); |
AnnaBridge | 157:e7ca05fa8600 | 2053 | } |
AnnaBridge | 157:e7ca05fa8600 | 2054 | |
AnnaBridge | 157:e7ca05fa8600 | 2055 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2056 | * @brief Check if HSE ready interrupt occurred or not |
AnnaBridge | 157:e7ca05fa8600 | 2057 | * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY |
AnnaBridge | 157:e7ca05fa8600 | 2058 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2059 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2060 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2061 | { |
AnnaBridge | 157:e7ca05fa8600 | 2062 | return (READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)); |
AnnaBridge | 157:e7ca05fa8600 | 2063 | } |
AnnaBridge | 157:e7ca05fa8600 | 2064 | |
AnnaBridge | 157:e7ca05fa8600 | 2065 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2066 | * @brief Check if PLL ready interrupt occurred or not |
AnnaBridge | 157:e7ca05fa8600 | 2067 | * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY |
AnnaBridge | 157:e7ca05fa8600 | 2068 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2069 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2070 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2071 | { |
AnnaBridge | 157:e7ca05fa8600 | 2072 | return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)); |
AnnaBridge | 157:e7ca05fa8600 | 2073 | } |
AnnaBridge | 157:e7ca05fa8600 | 2074 | |
AnnaBridge | 157:e7ca05fa8600 | 2075 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 157:e7ca05fa8600 | 2076 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2077 | * @brief Check if HSI48 ready interrupt occurred or not |
AnnaBridge | 157:e7ca05fa8600 | 2078 | * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY |
AnnaBridge | 157:e7ca05fa8600 | 2079 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2080 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2081 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2082 | { |
AnnaBridge | 157:e7ca05fa8600 | 2083 | return (READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)); |
AnnaBridge | 157:e7ca05fa8600 | 2084 | } |
AnnaBridge | 157:e7ca05fa8600 | 2085 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 157:e7ca05fa8600 | 2086 | |
AnnaBridge | 157:e7ca05fa8600 | 2087 | #if defined(RCC_HSECSS_SUPPORT) |
AnnaBridge | 157:e7ca05fa8600 | 2088 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2089 | * @brief Check if Clock security system interrupt occurred or not |
AnnaBridge | 157:e7ca05fa8600 | 2090 | * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS |
AnnaBridge | 157:e7ca05fa8600 | 2091 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2092 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2093 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) |
AnnaBridge | 157:e7ca05fa8600 | 2094 | { |
AnnaBridge | 157:e7ca05fa8600 | 2095 | return (READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)); |
AnnaBridge | 157:e7ca05fa8600 | 2096 | } |
AnnaBridge | 157:e7ca05fa8600 | 2097 | #endif /* RCC_HSECSS_SUPPORT */ |
AnnaBridge | 157:e7ca05fa8600 | 2098 | |
AnnaBridge | 157:e7ca05fa8600 | 2099 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2100 | * @brief Check if LSE Clock security system interrupt occurred or not |
AnnaBridge | 157:e7ca05fa8600 | 2101 | * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS |
AnnaBridge | 157:e7ca05fa8600 | 2102 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2103 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2104 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) |
AnnaBridge | 157:e7ca05fa8600 | 2105 | { |
AnnaBridge | 157:e7ca05fa8600 | 2106 | return (READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)); |
AnnaBridge | 157:e7ca05fa8600 | 2107 | } |
AnnaBridge | 157:e7ca05fa8600 | 2108 | |
AnnaBridge | 157:e7ca05fa8600 | 2109 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2110 | * @brief Check if HSI Divider is enabled (it divides by 4) |
AnnaBridge | 157:e7ca05fa8600 | 2111 | * @rmtoll CR HSIDIVF LL_RCC_IsActiveFlag_HSIDIV |
AnnaBridge | 157:e7ca05fa8600 | 2112 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2113 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2114 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIDIV(void) |
AnnaBridge | 157:e7ca05fa8600 | 2115 | { |
AnnaBridge | 157:e7ca05fa8600 | 2116 | return (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF)); |
AnnaBridge | 157:e7ca05fa8600 | 2117 | } |
AnnaBridge | 157:e7ca05fa8600 | 2118 | |
AnnaBridge | 157:e7ca05fa8600 | 2119 | #if defined(RCC_CSR_FWRSTF) |
AnnaBridge | 157:e7ca05fa8600 | 2120 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2121 | * @brief Check if RCC flag FW reset is set or not. |
AnnaBridge | 157:e7ca05fa8600 | 2122 | * @rmtoll CSR FWRSTF LL_RCC_IsActiveFlag_FWRST |
AnnaBridge | 157:e7ca05fa8600 | 2123 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2124 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2125 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void) |
AnnaBridge | 157:e7ca05fa8600 | 2126 | { |
AnnaBridge | 157:e7ca05fa8600 | 2127 | return (READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == (RCC_CSR_FWRSTF)); |
AnnaBridge | 157:e7ca05fa8600 | 2128 | } |
AnnaBridge | 157:e7ca05fa8600 | 2129 | #endif /* RCC_CSR_FWRSTF */ |
AnnaBridge | 157:e7ca05fa8600 | 2130 | |
AnnaBridge | 157:e7ca05fa8600 | 2131 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2132 | * @brief Check if RCC flag Independent Watchdog reset is set or not. |
AnnaBridge | 157:e7ca05fa8600 | 2133 | * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST |
AnnaBridge | 157:e7ca05fa8600 | 2134 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2135 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2136 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) |
AnnaBridge | 157:e7ca05fa8600 | 2137 | { |
AnnaBridge | 157:e7ca05fa8600 | 2138 | return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); |
AnnaBridge | 157:e7ca05fa8600 | 2139 | } |
AnnaBridge | 157:e7ca05fa8600 | 2140 | |
AnnaBridge | 157:e7ca05fa8600 | 2141 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2142 | * @brief Check if RCC flag Low Power reset is set or not. |
AnnaBridge | 157:e7ca05fa8600 | 2143 | * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST |
AnnaBridge | 157:e7ca05fa8600 | 2144 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2145 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2146 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) |
AnnaBridge | 157:e7ca05fa8600 | 2147 | { |
AnnaBridge | 157:e7ca05fa8600 | 2148 | return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); |
AnnaBridge | 157:e7ca05fa8600 | 2149 | } |
AnnaBridge | 157:e7ca05fa8600 | 2150 | |
AnnaBridge | 157:e7ca05fa8600 | 2151 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2152 | * @brief Check if RCC flag is set or not. |
AnnaBridge | 157:e7ca05fa8600 | 2153 | * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST |
AnnaBridge | 157:e7ca05fa8600 | 2154 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2155 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2156 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) |
AnnaBridge | 157:e7ca05fa8600 | 2157 | { |
AnnaBridge | 157:e7ca05fa8600 | 2158 | return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)); |
AnnaBridge | 157:e7ca05fa8600 | 2159 | } |
AnnaBridge | 157:e7ca05fa8600 | 2160 | |
AnnaBridge | 157:e7ca05fa8600 | 2161 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2162 | * @brief Check if RCC flag Pin reset is set or not. |
AnnaBridge | 157:e7ca05fa8600 | 2163 | * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST |
AnnaBridge | 157:e7ca05fa8600 | 2164 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2165 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2166 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) |
AnnaBridge | 157:e7ca05fa8600 | 2167 | { |
AnnaBridge | 157:e7ca05fa8600 | 2168 | return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); |
AnnaBridge | 157:e7ca05fa8600 | 2169 | } |
AnnaBridge | 157:e7ca05fa8600 | 2170 | |
AnnaBridge | 157:e7ca05fa8600 | 2171 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2172 | * @brief Check if RCC flag POR/PDR reset is set or not. |
AnnaBridge | 157:e7ca05fa8600 | 2173 | * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST |
AnnaBridge | 157:e7ca05fa8600 | 2174 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2175 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2176 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) |
AnnaBridge | 157:e7ca05fa8600 | 2177 | { |
AnnaBridge | 157:e7ca05fa8600 | 2178 | return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); |
AnnaBridge | 157:e7ca05fa8600 | 2179 | } |
AnnaBridge | 157:e7ca05fa8600 | 2180 | |
AnnaBridge | 157:e7ca05fa8600 | 2181 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2182 | * @brief Check if RCC flag Software reset is set or not. |
AnnaBridge | 157:e7ca05fa8600 | 2183 | * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST |
AnnaBridge | 157:e7ca05fa8600 | 2184 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2185 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2186 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) |
AnnaBridge | 157:e7ca05fa8600 | 2187 | { |
AnnaBridge | 157:e7ca05fa8600 | 2188 | return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); |
AnnaBridge | 157:e7ca05fa8600 | 2189 | } |
AnnaBridge | 157:e7ca05fa8600 | 2190 | |
AnnaBridge | 157:e7ca05fa8600 | 2191 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2192 | * @brief Check if RCC flag Window Watchdog reset is set or not. |
AnnaBridge | 157:e7ca05fa8600 | 2193 | * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST |
AnnaBridge | 157:e7ca05fa8600 | 2194 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2195 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2196 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) |
AnnaBridge | 157:e7ca05fa8600 | 2197 | { |
AnnaBridge | 157:e7ca05fa8600 | 2198 | return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); |
AnnaBridge | 157:e7ca05fa8600 | 2199 | } |
AnnaBridge | 157:e7ca05fa8600 | 2200 | |
AnnaBridge | 157:e7ca05fa8600 | 2201 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2202 | * @brief Set RMVF bit to clear the reset flags. |
AnnaBridge | 157:e7ca05fa8600 | 2203 | * @rmtoll CSR RMVF LL_RCC_ClearResetFlags |
AnnaBridge | 157:e7ca05fa8600 | 2204 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 2205 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2206 | __STATIC_INLINE void LL_RCC_ClearResetFlags(void) |
AnnaBridge | 157:e7ca05fa8600 | 2207 | { |
AnnaBridge | 157:e7ca05fa8600 | 2208 | SET_BIT(RCC->CSR, RCC_CSR_RMVF); |
AnnaBridge | 157:e7ca05fa8600 | 2209 | } |
AnnaBridge | 157:e7ca05fa8600 | 2210 | |
AnnaBridge | 157:e7ca05fa8600 | 2211 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2212 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 2213 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2214 | |
AnnaBridge | 157:e7ca05fa8600 | 2215 | /** @defgroup RCC_LL_EF_IT_Management IT Management |
AnnaBridge | 157:e7ca05fa8600 | 2216 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 2217 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2218 | |
AnnaBridge | 157:e7ca05fa8600 | 2219 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2220 | * @brief Enable LSI ready interrupt |
AnnaBridge | 157:e7ca05fa8600 | 2221 | * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY |
AnnaBridge | 157:e7ca05fa8600 | 2222 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 2223 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2224 | __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2225 | { |
AnnaBridge | 157:e7ca05fa8600 | 2226 | SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); |
AnnaBridge | 157:e7ca05fa8600 | 2227 | } |
AnnaBridge | 157:e7ca05fa8600 | 2228 | |
AnnaBridge | 157:e7ca05fa8600 | 2229 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2230 | * @brief Enable LSE ready interrupt |
AnnaBridge | 157:e7ca05fa8600 | 2231 | * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY |
AnnaBridge | 157:e7ca05fa8600 | 2232 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 2233 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2234 | __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2235 | { |
AnnaBridge | 157:e7ca05fa8600 | 2236 | SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); |
AnnaBridge | 157:e7ca05fa8600 | 2237 | } |
AnnaBridge | 157:e7ca05fa8600 | 2238 | |
AnnaBridge | 157:e7ca05fa8600 | 2239 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2240 | * @brief Enable MSI ready interrupt |
AnnaBridge | 157:e7ca05fa8600 | 2241 | * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY |
AnnaBridge | 157:e7ca05fa8600 | 2242 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 2243 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2244 | __STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2245 | { |
AnnaBridge | 157:e7ca05fa8600 | 2246 | SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE); |
AnnaBridge | 157:e7ca05fa8600 | 2247 | } |
AnnaBridge | 157:e7ca05fa8600 | 2248 | |
AnnaBridge | 157:e7ca05fa8600 | 2249 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2250 | * @brief Enable HSI ready interrupt |
AnnaBridge | 157:e7ca05fa8600 | 2251 | * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY |
AnnaBridge | 157:e7ca05fa8600 | 2252 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 2253 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2254 | __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2255 | { |
AnnaBridge | 157:e7ca05fa8600 | 2256 | SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); |
AnnaBridge | 157:e7ca05fa8600 | 2257 | } |
AnnaBridge | 157:e7ca05fa8600 | 2258 | |
AnnaBridge | 157:e7ca05fa8600 | 2259 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2260 | * @brief Enable HSE ready interrupt |
AnnaBridge | 157:e7ca05fa8600 | 2261 | * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY |
AnnaBridge | 157:e7ca05fa8600 | 2262 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 2263 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2264 | __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2265 | { |
AnnaBridge | 157:e7ca05fa8600 | 2266 | SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); |
AnnaBridge | 157:e7ca05fa8600 | 2267 | } |
AnnaBridge | 157:e7ca05fa8600 | 2268 | |
AnnaBridge | 157:e7ca05fa8600 | 2269 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2270 | * @brief Enable PLL ready interrupt |
AnnaBridge | 157:e7ca05fa8600 | 2271 | * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY |
AnnaBridge | 157:e7ca05fa8600 | 2272 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 2273 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2274 | __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2275 | { |
AnnaBridge | 157:e7ca05fa8600 | 2276 | SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); |
AnnaBridge | 157:e7ca05fa8600 | 2277 | } |
AnnaBridge | 157:e7ca05fa8600 | 2278 | |
AnnaBridge | 157:e7ca05fa8600 | 2279 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 157:e7ca05fa8600 | 2280 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2281 | * @brief Enable HSI48 ready interrupt |
AnnaBridge | 157:e7ca05fa8600 | 2282 | * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY |
AnnaBridge | 157:e7ca05fa8600 | 2283 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 2284 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2285 | __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2286 | { |
AnnaBridge | 157:e7ca05fa8600 | 2287 | SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); |
AnnaBridge | 157:e7ca05fa8600 | 2288 | } |
AnnaBridge | 157:e7ca05fa8600 | 2289 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 157:e7ca05fa8600 | 2290 | |
AnnaBridge | 157:e7ca05fa8600 | 2291 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2292 | * @brief Enable LSE clock security system interrupt |
AnnaBridge | 157:e7ca05fa8600 | 2293 | * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS |
AnnaBridge | 157:e7ca05fa8600 | 2294 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 2295 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2296 | __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void) |
AnnaBridge | 157:e7ca05fa8600 | 2297 | { |
AnnaBridge | 157:e7ca05fa8600 | 2298 | SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE); |
AnnaBridge | 157:e7ca05fa8600 | 2299 | } |
AnnaBridge | 157:e7ca05fa8600 | 2300 | |
AnnaBridge | 157:e7ca05fa8600 | 2301 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2302 | * @brief Disable LSI ready interrupt |
AnnaBridge | 157:e7ca05fa8600 | 2303 | * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY |
AnnaBridge | 157:e7ca05fa8600 | 2304 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 2305 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2306 | __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2307 | { |
AnnaBridge | 157:e7ca05fa8600 | 2308 | CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); |
AnnaBridge | 157:e7ca05fa8600 | 2309 | } |
AnnaBridge | 157:e7ca05fa8600 | 2310 | |
AnnaBridge | 157:e7ca05fa8600 | 2311 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2312 | * @brief Disable LSE ready interrupt |
AnnaBridge | 157:e7ca05fa8600 | 2313 | * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY |
AnnaBridge | 157:e7ca05fa8600 | 2314 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 2315 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2316 | __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2317 | { |
AnnaBridge | 157:e7ca05fa8600 | 2318 | CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); |
AnnaBridge | 157:e7ca05fa8600 | 2319 | } |
AnnaBridge | 157:e7ca05fa8600 | 2320 | |
AnnaBridge | 157:e7ca05fa8600 | 2321 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2322 | * @brief Disable MSI ready interrupt |
AnnaBridge | 157:e7ca05fa8600 | 2323 | * @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY |
AnnaBridge | 157:e7ca05fa8600 | 2324 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 2325 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2326 | __STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2327 | { |
AnnaBridge | 157:e7ca05fa8600 | 2328 | CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE); |
AnnaBridge | 157:e7ca05fa8600 | 2329 | } |
AnnaBridge | 157:e7ca05fa8600 | 2330 | |
AnnaBridge | 157:e7ca05fa8600 | 2331 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2332 | * @brief Disable HSI ready interrupt |
AnnaBridge | 157:e7ca05fa8600 | 2333 | * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY |
AnnaBridge | 157:e7ca05fa8600 | 2334 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 2335 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2336 | __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2337 | { |
AnnaBridge | 157:e7ca05fa8600 | 2338 | CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); |
AnnaBridge | 157:e7ca05fa8600 | 2339 | } |
AnnaBridge | 157:e7ca05fa8600 | 2340 | |
AnnaBridge | 157:e7ca05fa8600 | 2341 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2342 | * @brief Disable HSE ready interrupt |
AnnaBridge | 157:e7ca05fa8600 | 2343 | * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY |
AnnaBridge | 157:e7ca05fa8600 | 2344 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 2345 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2346 | __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2347 | { |
AnnaBridge | 157:e7ca05fa8600 | 2348 | CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); |
AnnaBridge | 157:e7ca05fa8600 | 2349 | } |
AnnaBridge | 157:e7ca05fa8600 | 2350 | |
AnnaBridge | 157:e7ca05fa8600 | 2351 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2352 | * @brief Disable PLL ready interrupt |
AnnaBridge | 157:e7ca05fa8600 | 2353 | * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY |
AnnaBridge | 157:e7ca05fa8600 | 2354 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 2355 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2356 | __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2357 | { |
AnnaBridge | 157:e7ca05fa8600 | 2358 | CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); |
AnnaBridge | 157:e7ca05fa8600 | 2359 | } |
AnnaBridge | 157:e7ca05fa8600 | 2360 | |
AnnaBridge | 157:e7ca05fa8600 | 2361 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 157:e7ca05fa8600 | 2362 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2363 | * @brief Disable HSI48 ready interrupt |
AnnaBridge | 157:e7ca05fa8600 | 2364 | * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY |
AnnaBridge | 157:e7ca05fa8600 | 2365 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 2366 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2367 | __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2368 | { |
AnnaBridge | 157:e7ca05fa8600 | 2369 | CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); |
AnnaBridge | 157:e7ca05fa8600 | 2370 | } |
AnnaBridge | 157:e7ca05fa8600 | 2371 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 157:e7ca05fa8600 | 2372 | |
AnnaBridge | 157:e7ca05fa8600 | 2373 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2374 | * @brief Disable LSE clock security system interrupt |
AnnaBridge | 157:e7ca05fa8600 | 2375 | * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS |
AnnaBridge | 157:e7ca05fa8600 | 2376 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 2377 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2378 | __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void) |
AnnaBridge | 157:e7ca05fa8600 | 2379 | { |
AnnaBridge | 157:e7ca05fa8600 | 2380 | CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE); |
AnnaBridge | 157:e7ca05fa8600 | 2381 | } |
AnnaBridge | 157:e7ca05fa8600 | 2382 | |
AnnaBridge | 157:e7ca05fa8600 | 2383 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2384 | * @brief Checks if LSI ready interrupt source is enabled or disabled. |
AnnaBridge | 157:e7ca05fa8600 | 2385 | * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY |
AnnaBridge | 157:e7ca05fa8600 | 2386 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2387 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2388 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2389 | { |
AnnaBridge | 157:e7ca05fa8600 | 2390 | return (READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)); |
AnnaBridge | 157:e7ca05fa8600 | 2391 | } |
AnnaBridge | 157:e7ca05fa8600 | 2392 | |
AnnaBridge | 157:e7ca05fa8600 | 2393 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2394 | * @brief Checks if LSE ready interrupt source is enabled or disabled. |
AnnaBridge | 157:e7ca05fa8600 | 2395 | * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY |
AnnaBridge | 157:e7ca05fa8600 | 2396 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2397 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2398 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2399 | { |
AnnaBridge | 157:e7ca05fa8600 | 2400 | return (READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)); |
AnnaBridge | 157:e7ca05fa8600 | 2401 | } |
AnnaBridge | 157:e7ca05fa8600 | 2402 | |
AnnaBridge | 157:e7ca05fa8600 | 2403 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2404 | * @brief Checks if MSI ready interrupt source is enabled or disabled. |
AnnaBridge | 157:e7ca05fa8600 | 2405 | * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY |
AnnaBridge | 157:e7ca05fa8600 | 2406 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2407 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2408 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2409 | { |
AnnaBridge | 157:e7ca05fa8600 | 2410 | return (READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE)); |
AnnaBridge | 157:e7ca05fa8600 | 2411 | } |
AnnaBridge | 157:e7ca05fa8600 | 2412 | |
AnnaBridge | 157:e7ca05fa8600 | 2413 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2414 | * @brief Checks if HSI ready interrupt source is enabled or disabled. |
AnnaBridge | 157:e7ca05fa8600 | 2415 | * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY |
AnnaBridge | 157:e7ca05fa8600 | 2416 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2417 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2418 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2419 | { |
AnnaBridge | 157:e7ca05fa8600 | 2420 | return (READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)); |
AnnaBridge | 157:e7ca05fa8600 | 2421 | } |
AnnaBridge | 157:e7ca05fa8600 | 2422 | |
AnnaBridge | 157:e7ca05fa8600 | 2423 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2424 | * @brief Checks if HSE ready interrupt source is enabled or disabled. |
AnnaBridge | 157:e7ca05fa8600 | 2425 | * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY |
AnnaBridge | 157:e7ca05fa8600 | 2426 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2427 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2428 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2429 | { |
AnnaBridge | 157:e7ca05fa8600 | 2430 | return (READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)); |
AnnaBridge | 157:e7ca05fa8600 | 2431 | } |
AnnaBridge | 157:e7ca05fa8600 | 2432 | |
AnnaBridge | 157:e7ca05fa8600 | 2433 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2434 | * @brief Checks if PLL ready interrupt source is enabled or disabled. |
AnnaBridge | 157:e7ca05fa8600 | 2435 | * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY |
AnnaBridge | 157:e7ca05fa8600 | 2436 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2437 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2438 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2439 | { |
AnnaBridge | 157:e7ca05fa8600 | 2440 | return (READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)); |
AnnaBridge | 157:e7ca05fa8600 | 2441 | } |
AnnaBridge | 157:e7ca05fa8600 | 2442 | |
AnnaBridge | 157:e7ca05fa8600 | 2443 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 157:e7ca05fa8600 | 2444 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2445 | * @brief Checks if HSI48 ready interrupt source is enabled or disabled. |
AnnaBridge | 157:e7ca05fa8600 | 2446 | * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY |
AnnaBridge | 157:e7ca05fa8600 | 2447 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2448 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2449 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) |
AnnaBridge | 157:e7ca05fa8600 | 2450 | { |
AnnaBridge | 157:e7ca05fa8600 | 2451 | return (READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)); |
AnnaBridge | 157:e7ca05fa8600 | 2452 | } |
AnnaBridge | 157:e7ca05fa8600 | 2453 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 157:e7ca05fa8600 | 2454 | |
AnnaBridge | 157:e7ca05fa8600 | 2455 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2456 | * @brief Checks if LSECSS interrupt source is enabled or disabled. |
AnnaBridge | 157:e7ca05fa8600 | 2457 | * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS |
AnnaBridge | 157:e7ca05fa8600 | 2458 | * @retval State of bit (1 or 0). |
AnnaBridge | 157:e7ca05fa8600 | 2459 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2460 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void) |
AnnaBridge | 157:e7ca05fa8600 | 2461 | { |
AnnaBridge | 157:e7ca05fa8600 | 2462 | return (READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE)); |
AnnaBridge | 157:e7ca05fa8600 | 2463 | } |
AnnaBridge | 157:e7ca05fa8600 | 2464 | |
AnnaBridge | 157:e7ca05fa8600 | 2465 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2466 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 2467 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2468 | |
AnnaBridge | 157:e7ca05fa8600 | 2469 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 157:e7ca05fa8600 | 2470 | /** @defgroup RCC_LL_EF_Init De-initialization function |
AnnaBridge | 157:e7ca05fa8600 | 2471 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 2472 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2473 | ErrorStatus LL_RCC_DeInit(void); |
AnnaBridge | 157:e7ca05fa8600 | 2474 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2475 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 2476 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2477 | |
AnnaBridge | 157:e7ca05fa8600 | 2478 | /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions |
AnnaBridge | 157:e7ca05fa8600 | 2479 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 2480 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2481 | void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); |
AnnaBridge | 157:e7ca05fa8600 | 2482 | uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); |
AnnaBridge | 157:e7ca05fa8600 | 2483 | uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); |
AnnaBridge | 157:e7ca05fa8600 | 2484 | uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); |
AnnaBridge | 157:e7ca05fa8600 | 2485 | uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); |
AnnaBridge | 157:e7ca05fa8600 | 2486 | #if defined(USB_OTG_FS) || defined(USB) |
AnnaBridge | 157:e7ca05fa8600 | 2487 | uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); |
AnnaBridge | 157:e7ca05fa8600 | 2488 | #endif /* USB_OTG_FS || USB */ |
AnnaBridge | 157:e7ca05fa8600 | 2489 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2490 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 2491 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2492 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 157:e7ca05fa8600 | 2493 | |
AnnaBridge | 157:e7ca05fa8600 | 2494 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2495 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 2496 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2497 | |
AnnaBridge | 157:e7ca05fa8600 | 2498 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2499 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 2500 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2501 | |
AnnaBridge | 157:e7ca05fa8600 | 2502 | #endif /* RCC */ |
AnnaBridge | 157:e7ca05fa8600 | 2503 | |
AnnaBridge | 157:e7ca05fa8600 | 2504 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2505 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 2506 | */ |
AnnaBridge | 157:e7ca05fa8600 | 2507 | |
AnnaBridge | 157:e7ca05fa8600 | 2508 | #ifdef __cplusplus |
AnnaBridge | 157:e7ca05fa8600 | 2509 | } |
AnnaBridge | 157:e7ca05fa8600 | 2510 | #endif |
AnnaBridge | 157:e7ca05fa8600 | 2511 | |
AnnaBridge | 157:e7ca05fa8600 | 2512 | #endif /* __STM32L0xx_LL_RCC_H */ |
AnnaBridge | 157:e7ca05fa8600 | 2513 | |
AnnaBridge | 157:e7ca05fa8600 | 2514 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |